1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void BND_Fixup (int, int);
111 static void NOTRACK_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void PCMPESTR_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define EbndS { OP_E, bnd_swap_mode }
250 #define Ev { OP_E, v_mode }
251 #define Eva { OP_E, va_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mv_bnd { OP_M, v_bndmk_mode }
275 #define Mx { OP_M, x_mode }
276 #define Mxmm { OP_M, xmm_mode }
277 #define Gb { OP_G, b_mode }
278 #define Gbnd { OP_G, bnd_mode }
279 #define Gv { OP_G, v_mode }
280 #define Gd { OP_G, d_mode }
281 #define Gdq { OP_G, dq_mode }
282 #define Gm { OP_G, m_mode }
283 #define Gva { OP_G, va_mode }
284 #define Gw { OP_G, w_mode }
285 #define Rd { OP_R, d_mode }
286 #define Rdq { OP_R, dq_mode }
287 #define Rm { OP_R, m_mode }
288 #define Ib { OP_I, b_mode }
289 #define sIb { OP_sI, b_mode } /* sign extened byte */
290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
291 #define Iv { OP_I, v_mode }
292 #define sIv { OP_sI, v_mode }
293 #define Iv64 { OP_I64, v_mode }
294 #define Id { OP_I, d_mode }
295 #define Iw { OP_I, w_mode }
296 #define I1 { OP_I, const_1_mode }
297 #define Jb { OP_J, b_mode }
298 #define Jv { OP_J, v_mode }
299 #define Jdqw { OP_J, dqw_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
403 #define EXxmmdw { OP_EX, xmmdw_mode }
404 #define EXxmmqd { OP_EX, xmmqd_mode }
405 #define EXymmq { OP_EX, ymmq_mode }
406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define CMP { CMP_Fixup, 0 }
416 #define XMM0 { XMM_Fixup, 0 }
417 #define FXSAVE { FXSAVE_Fixup, 0 }
418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
421 #define Vex { OP_VEX, vex_mode }
422 #define VexScalar { OP_VEX, vex_scalar_mode }
423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
424 #define Vex128 { OP_VEX, vex128_mode }
425 #define Vex256 { OP_VEX, vex256_mode }
426 #define VexGdq { OP_VEX, dq_mode }
427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
434 #define XMVexW { OP_XMM_VexW, 0 }
435 #define XMVexI4 { OP_REG_VexI4, x_mode }
436 #define PCLMUL { PCLMUL_Fixup, 0 }
437 #define VCMP { VCMP_Fixup, 0 }
438 #define VPCMP { VPCMP_Fixup, 0 }
439 #define VPCOM { VPCOM_Fixup, 0 }
441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
476 #define NOTRACK { NOTRACK_Fixup, 0 }
478 #define cond_jump_flag { NULL, cond_jump_mode }
479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
481 /* bits in sizeflag */
482 #define SUFFIX_ALWAYS 4
490 /* byte operand with operand swapped */
492 /* byte operand, sign extend like 'T' suffix */
494 /* operand size depends on prefixes */
496 /* operand size depends on prefixes with operand swapped */
498 /* operand size depends on address prefix */
502 /* double word operand */
504 /* double word operand with operand swapped */
506 /* quad word operand */
508 /* quad word operand with operand swapped */
510 /* ten-byte operand */
512 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
513 broadcast enabled. */
515 /* Similar to x_mode, but with different EVEX mem shifts. */
517 /* Similar to x_mode, but with disabled broadcast. */
519 /* Similar to x_mode, but with operands swapped and disabled broadcast
522 /* 16-byte XMM operand */
524 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
525 memory operand (depending on vector length). Broadcast isn't
528 /* Same as xmmq_mode, but broadcast is allowed. */
529 evex_half_bcst_xmmq_mode
,
530 /* XMM register or byte memory operand */
532 /* XMM register or word memory operand */
534 /* XMM register or double word memory operand */
536 /* XMM register or quad word memory operand */
538 /* XMM register or double/quad word memory operand, depending on
541 /* 16-byte XMM, word, double word or quad word operand. */
543 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
545 /* 32-byte YMM operand */
547 /* quad word, ymmword or zmmword memory operand. */
549 /* 32-byte YMM or 16-byte word operand */
551 /* d_mode in 32bit, q_mode in 64bit mode. */
553 /* pair of v_mode operands */
558 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode, displacements like
563 v_mode without considering Intel64 ISA. */
567 /* bounds operand with operand swapped */
569 /* 4- or 6-byte pointer operand */
572 /* v_mode for indirect branch opcodes. */
574 /* v_mode for stack-related opcodes. */
576 /* non-quad operand size depends on prefixes */
578 /* 16-byte operand */
580 /* registers like dq_mode, memory like b_mode. */
582 /* registers like d_mode, memory like b_mode. */
584 /* registers like d_mode, memory like w_mode. */
586 /* registers like dq_mode, memory like d_mode. */
588 /* normal vex mode */
590 /* 128bit vex mode */
592 /* 256bit vex mode */
594 /* operand size depends on the VEX.W bit. */
597 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
598 vex_vsib_d_w_dq_mode
,
599 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
601 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
602 vex_vsib_q_w_dq_mode
,
603 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
606 /* scalar, ignore vector length. */
608 /* like b_mode, ignore vector length. */
610 /* like w_mode, ignore vector length. */
612 /* like d_mode, ignore vector length. */
614 /* like d_swap_mode, ignore vector length. */
616 /* like q_mode, ignore vector length. */
618 /* like q_swap_mode, ignore vector length. */
620 /* like vex_mode, ignore vector length. */
622 /* like vex_w_dq_mode, ignore vector length. */
623 vex_scalar_w_dq_mode
,
625 /* Static rounding. */
627 /* Static rounding, 64-bit mode only. */
628 evex_rounding_64_mode
,
629 /* Supress all exceptions. */
632 /* Mask register operand. */
634 /* Mask register operand. */
702 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
704 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
705 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
706 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
707 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
708 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
709 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
710 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
711 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
712 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
713 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
714 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
715 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
716 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
717 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
718 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
719 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
847 MOD_VEX_0F12_PREFIX_0
,
849 MOD_VEX_0F16_PREFIX_0
,
852 MOD_VEX_W_0_0F41_P_0_LEN_1
,
853 MOD_VEX_W_1_0F41_P_0_LEN_1
,
854 MOD_VEX_W_0_0F41_P_2_LEN_1
,
855 MOD_VEX_W_1_0F41_P_2_LEN_1
,
856 MOD_VEX_W_0_0F42_P_0_LEN_1
,
857 MOD_VEX_W_1_0F42_P_0_LEN_1
,
858 MOD_VEX_W_0_0F42_P_2_LEN_1
,
859 MOD_VEX_W_1_0F42_P_2_LEN_1
,
860 MOD_VEX_W_0_0F44_P_0_LEN_1
,
861 MOD_VEX_W_1_0F44_P_0_LEN_1
,
862 MOD_VEX_W_0_0F44_P_2_LEN_1
,
863 MOD_VEX_W_1_0F44_P_2_LEN_1
,
864 MOD_VEX_W_0_0F45_P_0_LEN_1
,
865 MOD_VEX_W_1_0F45_P_0_LEN_1
,
866 MOD_VEX_W_0_0F45_P_2_LEN_1
,
867 MOD_VEX_W_1_0F45_P_2_LEN_1
,
868 MOD_VEX_W_0_0F46_P_0_LEN_1
,
869 MOD_VEX_W_1_0F46_P_0_LEN_1
,
870 MOD_VEX_W_0_0F46_P_2_LEN_1
,
871 MOD_VEX_W_1_0F46_P_2_LEN_1
,
872 MOD_VEX_W_0_0F47_P_0_LEN_1
,
873 MOD_VEX_W_1_0F47_P_0_LEN_1
,
874 MOD_VEX_W_0_0F47_P_2_LEN_1
,
875 MOD_VEX_W_1_0F47_P_2_LEN_1
,
876 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
877 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
878 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
879 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
880 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
881 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
882 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
894 MOD_VEX_W_0_0F91_P_0_LEN_0
,
895 MOD_VEX_W_1_0F91_P_0_LEN_0
,
896 MOD_VEX_W_0_0F91_P_2_LEN_0
,
897 MOD_VEX_W_1_0F91_P_2_LEN_0
,
898 MOD_VEX_W_0_0F92_P_0_LEN_0
,
899 MOD_VEX_W_0_0F92_P_2_LEN_0
,
900 MOD_VEX_0F92_P_3_LEN_0
,
901 MOD_VEX_W_0_0F93_P_0_LEN_0
,
902 MOD_VEX_W_0_0F93_P_2_LEN_0
,
903 MOD_VEX_0F93_P_3_LEN_0
,
904 MOD_VEX_W_0_0F98_P_0_LEN_0
,
905 MOD_VEX_W_1_0F98_P_0_LEN_0
,
906 MOD_VEX_W_0_0F98_P_2_LEN_0
,
907 MOD_VEX_W_1_0F98_P_2_LEN_0
,
908 MOD_VEX_W_0_0F99_P_0_LEN_0
,
909 MOD_VEX_W_1_0F99_P_0_LEN_0
,
910 MOD_VEX_W_0_0F99_P_2_LEN_0
,
911 MOD_VEX_W_1_0F99_P_2_LEN_0
,
914 MOD_VEX_0FD7_PREFIX_2
,
915 MOD_VEX_0FE7_PREFIX_2
,
916 MOD_VEX_0FF0_PREFIX_3
,
917 MOD_VEX_0F381A_PREFIX_2
,
918 MOD_VEX_0F382A_PREFIX_2
,
919 MOD_VEX_0F382C_PREFIX_2
,
920 MOD_VEX_0F382D_PREFIX_2
,
921 MOD_VEX_0F382E_PREFIX_2
,
922 MOD_VEX_0F382F_PREFIX_2
,
923 MOD_VEX_0F385A_PREFIX_2
,
924 MOD_VEX_0F388C_PREFIX_2
,
925 MOD_VEX_0F388E_PREFIX_2
,
926 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
928 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
930 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
932 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
935 MOD_EVEX_0F12_PREFIX_0
,
936 MOD_EVEX_0F16_PREFIX_0
,
937 MOD_EVEX_0F38C6_REG_1
,
938 MOD_EVEX_0F38C6_REG_2
,
939 MOD_EVEX_0F38C6_REG_5
,
940 MOD_EVEX_0F38C6_REG_6
,
941 MOD_EVEX_0F38C7_REG_1
,
942 MOD_EVEX_0F38C7_REG_2
,
943 MOD_EVEX_0F38C7_REG_5
,
944 MOD_EVEX_0F38C7_REG_6
957 RM_0F1E_P_1_MOD_3_REG_7
,
958 RM_0FAE_REG_6_MOD_3_P_0
,
965 PREFIX_0F01_REG_5_MOD_0
,
966 PREFIX_0F01_REG_5_MOD_3_RM_0
,
967 PREFIX_0F01_REG_5_MOD_3_RM_2
,
968 PREFIX_0F01_REG_7_MOD_3_RM_2
,
969 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1011 PREFIX_0FAE_REG_0_MOD_3
,
1012 PREFIX_0FAE_REG_1_MOD_3
,
1013 PREFIX_0FAE_REG_2_MOD_3
,
1014 PREFIX_0FAE_REG_3_MOD_3
,
1015 PREFIX_0FAE_REG_4_MOD_0
,
1016 PREFIX_0FAE_REG_4_MOD_3
,
1017 PREFIX_0FAE_REG_5_MOD_0
,
1018 PREFIX_0FAE_REG_5_MOD_3
,
1019 PREFIX_0FAE_REG_6_MOD_0
,
1020 PREFIX_0FAE_REG_6_MOD_3
,
1021 PREFIX_0FAE_REG_7_MOD_0
,
1027 PREFIX_0FC7_REG_6_MOD_0
,
1028 PREFIX_0FC7_REG_6_MOD_3
,
1029 PREFIX_0FC7_REG_7_MOD_3
,
1159 PREFIX_VEX_0F71_REG_2
,
1160 PREFIX_VEX_0F71_REG_4
,
1161 PREFIX_VEX_0F71_REG_6
,
1162 PREFIX_VEX_0F72_REG_2
,
1163 PREFIX_VEX_0F72_REG_4
,
1164 PREFIX_VEX_0F72_REG_6
,
1165 PREFIX_VEX_0F73_REG_2
,
1166 PREFIX_VEX_0F73_REG_3
,
1167 PREFIX_VEX_0F73_REG_6
,
1168 PREFIX_VEX_0F73_REG_7
,
1341 PREFIX_VEX_0F38F3_REG_1
,
1342 PREFIX_VEX_0F38F3_REG_2
,
1343 PREFIX_VEX_0F38F3_REG_3
,
1462 PREFIX_EVEX_0F71_REG_2
,
1463 PREFIX_EVEX_0F71_REG_4
,
1464 PREFIX_EVEX_0F71_REG_6
,
1465 PREFIX_EVEX_0F72_REG_0
,
1466 PREFIX_EVEX_0F72_REG_1
,
1467 PREFIX_EVEX_0F72_REG_2
,
1468 PREFIX_EVEX_0F72_REG_4
,
1469 PREFIX_EVEX_0F72_REG_6
,
1470 PREFIX_EVEX_0F73_REG_2
,
1471 PREFIX_EVEX_0F73_REG_3
,
1472 PREFIX_EVEX_0F73_REG_6
,
1473 PREFIX_EVEX_0F73_REG_7
,
1670 PREFIX_EVEX_0F38C6_REG_1
,
1671 PREFIX_EVEX_0F38C6_REG_2
,
1672 PREFIX_EVEX_0F38C6_REG_5
,
1673 PREFIX_EVEX_0F38C6_REG_6
,
1674 PREFIX_EVEX_0F38C7_REG_1
,
1675 PREFIX_EVEX_0F38C7_REG_2
,
1676 PREFIX_EVEX_0F38C7_REG_5
,
1677 PREFIX_EVEX_0F38C7_REG_6
,
1779 THREE_BYTE_0F38
= 0,
1806 VEX_LEN_0F12_P_0_M_0
= 0,
1807 VEX_LEN_0F12_P_0_M_1
,
1810 VEX_LEN_0F16_P_0_M_0
,
1811 VEX_LEN_0F16_P_0_M_1
,
1848 VEX_LEN_0FAE_R_2_M_0
,
1849 VEX_LEN_0FAE_R_3_M_0
,
1856 VEX_LEN_0F381A_P_2_M_0
,
1859 VEX_LEN_0F385A_P_2_M_0
,
1862 VEX_LEN_0F38F3_R_1_P_0
,
1863 VEX_LEN_0F38F3_R_2_P_0
,
1864 VEX_LEN_0F38F3_R_3_P_0
,
1907 VEX_LEN_0FXOP_08_CC
,
1908 VEX_LEN_0FXOP_08_CD
,
1909 VEX_LEN_0FXOP_08_CE
,
1910 VEX_LEN_0FXOP_08_CF
,
1911 VEX_LEN_0FXOP_08_EC
,
1912 VEX_LEN_0FXOP_08_ED
,
1913 VEX_LEN_0FXOP_08_EE
,
1914 VEX_LEN_0FXOP_08_EF
,
1915 VEX_LEN_0FXOP_09_80
,
1921 EVEX_LEN_0F6E_P_2
= 0,
1925 EVEX_LEN_0F3819_P_2_W_0
,
1926 EVEX_LEN_0F3819_P_2_W_1
,
1927 EVEX_LEN_0F381A_P_2_W_0
,
1928 EVEX_LEN_0F381A_P_2_W_1
,
1929 EVEX_LEN_0F381B_P_2_W_0
,
1930 EVEX_LEN_0F381B_P_2_W_1
,
1931 EVEX_LEN_0F385A_P_2_W_0
,
1932 EVEX_LEN_0F385A_P_2_W_1
,
1933 EVEX_LEN_0F385B_P_2_W_0
,
1934 EVEX_LEN_0F385B_P_2_W_1
,
1935 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1936 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1937 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1938 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1939 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1940 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1941 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1943 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1945 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1947 EVEX_LEN_0F3A18_P_2_W_0
,
1948 EVEX_LEN_0F3A18_P_2_W_1
,
1949 EVEX_LEN_0F3A19_P_2_W_0
,
1950 EVEX_LEN_0F3A19_P_2_W_1
,
1951 EVEX_LEN_0F3A1A_P_2_W_0
,
1952 EVEX_LEN_0F3A1A_P_2_W_1
,
1953 EVEX_LEN_0F3A1B_P_2_W_0
,
1954 EVEX_LEN_0F3A1B_P_2_W_1
,
1955 EVEX_LEN_0F3A23_P_2_W_0
,
1956 EVEX_LEN_0F3A23_P_2_W_1
,
1957 EVEX_LEN_0F3A38_P_2_W_0
,
1958 EVEX_LEN_0F3A38_P_2_W_1
,
1959 EVEX_LEN_0F3A39_P_2_W_0
,
1960 EVEX_LEN_0F3A39_P_2_W_1
,
1961 EVEX_LEN_0F3A3A_P_2_W_0
,
1962 EVEX_LEN_0F3A3A_P_2_W_1
,
1963 EVEX_LEN_0F3A3B_P_2_W_0
,
1964 EVEX_LEN_0F3A3B_P_2_W_1
,
1965 EVEX_LEN_0F3A43_P_2_W_0
,
1966 EVEX_LEN_0F3A43_P_2_W_1
1971 VEX_W_0F41_P_0_LEN_1
= 0,
1972 VEX_W_0F41_P_2_LEN_1
,
1973 VEX_W_0F42_P_0_LEN_1
,
1974 VEX_W_0F42_P_2_LEN_1
,
1975 VEX_W_0F44_P_0_LEN_0
,
1976 VEX_W_0F44_P_2_LEN_0
,
1977 VEX_W_0F45_P_0_LEN_1
,
1978 VEX_W_0F45_P_2_LEN_1
,
1979 VEX_W_0F46_P_0_LEN_1
,
1980 VEX_W_0F46_P_2_LEN_1
,
1981 VEX_W_0F47_P_0_LEN_1
,
1982 VEX_W_0F47_P_2_LEN_1
,
1983 VEX_W_0F4A_P_0_LEN_1
,
1984 VEX_W_0F4A_P_2_LEN_1
,
1985 VEX_W_0F4B_P_0_LEN_1
,
1986 VEX_W_0F4B_P_2_LEN_1
,
1987 VEX_W_0F90_P_0_LEN_0
,
1988 VEX_W_0F90_P_2_LEN_0
,
1989 VEX_W_0F91_P_0_LEN_0
,
1990 VEX_W_0F91_P_2_LEN_0
,
1991 VEX_W_0F92_P_0_LEN_0
,
1992 VEX_W_0F92_P_2_LEN_0
,
1993 VEX_W_0F93_P_0_LEN_0
,
1994 VEX_W_0F93_P_2_LEN_0
,
1995 VEX_W_0F98_P_0_LEN_0
,
1996 VEX_W_0F98_P_2_LEN_0
,
1997 VEX_W_0F99_P_0_LEN_0
,
1998 VEX_W_0F99_P_2_LEN_0
,
2006 VEX_W_0F381A_P_2_M_0
,
2007 VEX_W_0F382C_P_2_M_0
,
2008 VEX_W_0F382D_P_2_M_0
,
2009 VEX_W_0F382E_P_2_M_0
,
2010 VEX_W_0F382F_P_2_M_0
,
2015 VEX_W_0F385A_P_2_M_0
,
2027 VEX_W_0F3A30_P_2_LEN_0
,
2028 VEX_W_0F3A31_P_2_LEN_0
,
2029 VEX_W_0F3A32_P_2_LEN_0
,
2030 VEX_W_0F3A33_P_2_LEN_0
,
2050 EVEX_W_0F12_P_0_M_0
,
2051 EVEX_W_0F12_P_0_M_1
,
2061 EVEX_W_0F16_P_0_M_0
,
2062 EVEX_W_0F16_P_0_M_1
,
2131 EVEX_W_0F72_R_2_P_2
,
2132 EVEX_W_0F72_R_6_P_2
,
2133 EVEX_W_0F73_R_2_P_2
,
2134 EVEX_W_0F73_R_6_P_2
,
2244 EVEX_W_0F38C7_R_1_P_2
,
2245 EVEX_W_0F38C7_R_2_P_2
,
2246 EVEX_W_0F38C7_R_5_P_2
,
2247 EVEX_W_0F38C7_R_6_P_2
,
2286 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2295 unsigned int prefix_requirement
;
2298 /* Upper case letters in the instruction names here are macros.
2299 'A' => print 'b' if no register operands or suffix_always is true
2300 'B' => print 'b' if suffix_always is true
2301 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2303 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2304 suffix_always is true
2305 'E' => print 'e' if 32-bit form of jcxz
2306 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2307 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2308 'H' => print ",pt" or ",pn" branch hint
2309 'I' => honor following macro letter even in Intel mode (implemented only
2310 for some of the macro letters)
2312 'K' => print 'd' or 'q' if rex prefix is present.
2313 'L' => print 'l' if suffix_always is true
2314 'M' => print 'r' if intel_mnemonic is false.
2315 'N' => print 'n' if instruction has no wait "prefix"
2316 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2317 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2318 or suffix_always is true. print 'q' if rex prefix is present.
2319 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2321 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2322 'S' => print 'w', 'l' or 'q' if suffix_always is true
2323 'T' => print 'q' in 64bit mode if instruction has no operand size
2324 prefix and behave as 'P' otherwise
2325 'U' => print 'q' in 64bit mode if instruction has no operand size
2326 prefix and behave as 'Q' otherwise
2327 'V' => print 'q' in 64bit mode if instruction has no operand size
2328 prefix and behave as 'S' otherwise
2329 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2330 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2332 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2333 '!' => change condition from true to false or from false to true.
2334 '%' => add 1 upper case letter to the macro.
2335 '^' => print 'w' or 'l' depending on operand size prefix or
2336 suffix_always is true (lcall/ljmp).
2337 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2338 on operand size prefix.
2339 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2340 has no operand size prefix for AMD64 ISA, behave as 'P'
2343 2 upper case letter macros:
2344 "XY" => print 'x' or 'y' if suffix_always is true or no register
2345 operands and no broadcast.
2346 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2347 register operands and no broadcast.
2348 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2349 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2350 or suffix_always is true
2351 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2352 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2353 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2354 "LW" => print 'd', 'q' depending on the VEX.W bit
2355 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2356 an operand size prefix, or suffix_always is true. print
2357 'q' if rex prefix is present.
2359 Many of the above letters print nothing in Intel mode. See "putop"
2362 Braces '{' and '}', and vertical bars '|', indicate alternative
2363 mnemonic strings for AT&T and Intel. */
2365 static const struct dis386 dis386
[] = {
2367 { "addB", { Ebh1
, Gb
}, 0 },
2368 { "addS", { Evh1
, Gv
}, 0 },
2369 { "addB", { Gb
, EbS
}, 0 },
2370 { "addS", { Gv
, EvS
}, 0 },
2371 { "addB", { AL
, Ib
}, 0 },
2372 { "addS", { eAX
, Iv
}, 0 },
2373 { X86_64_TABLE (X86_64_06
) },
2374 { X86_64_TABLE (X86_64_07
) },
2376 { "orB", { Ebh1
, Gb
}, 0 },
2377 { "orS", { Evh1
, Gv
}, 0 },
2378 { "orB", { Gb
, EbS
}, 0 },
2379 { "orS", { Gv
, EvS
}, 0 },
2380 { "orB", { AL
, Ib
}, 0 },
2381 { "orS", { eAX
, Iv
}, 0 },
2382 { X86_64_TABLE (X86_64_0D
) },
2383 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2385 { "adcB", { Ebh1
, Gb
}, 0 },
2386 { "adcS", { Evh1
, Gv
}, 0 },
2387 { "adcB", { Gb
, EbS
}, 0 },
2388 { "adcS", { Gv
, EvS
}, 0 },
2389 { "adcB", { AL
, Ib
}, 0 },
2390 { "adcS", { eAX
, Iv
}, 0 },
2391 { X86_64_TABLE (X86_64_16
) },
2392 { X86_64_TABLE (X86_64_17
) },
2394 { "sbbB", { Ebh1
, Gb
}, 0 },
2395 { "sbbS", { Evh1
, Gv
}, 0 },
2396 { "sbbB", { Gb
, EbS
}, 0 },
2397 { "sbbS", { Gv
, EvS
}, 0 },
2398 { "sbbB", { AL
, Ib
}, 0 },
2399 { "sbbS", { eAX
, Iv
}, 0 },
2400 { X86_64_TABLE (X86_64_1E
) },
2401 { X86_64_TABLE (X86_64_1F
) },
2403 { "andB", { Ebh1
, Gb
}, 0 },
2404 { "andS", { Evh1
, Gv
}, 0 },
2405 { "andB", { Gb
, EbS
}, 0 },
2406 { "andS", { Gv
, EvS
}, 0 },
2407 { "andB", { AL
, Ib
}, 0 },
2408 { "andS", { eAX
, Iv
}, 0 },
2409 { Bad_Opcode
}, /* SEG ES prefix */
2410 { X86_64_TABLE (X86_64_27
) },
2412 { "subB", { Ebh1
, Gb
}, 0 },
2413 { "subS", { Evh1
, Gv
}, 0 },
2414 { "subB", { Gb
, EbS
}, 0 },
2415 { "subS", { Gv
, EvS
}, 0 },
2416 { "subB", { AL
, Ib
}, 0 },
2417 { "subS", { eAX
, Iv
}, 0 },
2418 { Bad_Opcode
}, /* SEG CS prefix */
2419 { X86_64_TABLE (X86_64_2F
) },
2421 { "xorB", { Ebh1
, Gb
}, 0 },
2422 { "xorS", { Evh1
, Gv
}, 0 },
2423 { "xorB", { Gb
, EbS
}, 0 },
2424 { "xorS", { Gv
, EvS
}, 0 },
2425 { "xorB", { AL
, Ib
}, 0 },
2426 { "xorS", { eAX
, Iv
}, 0 },
2427 { Bad_Opcode
}, /* SEG SS prefix */
2428 { X86_64_TABLE (X86_64_37
) },
2430 { "cmpB", { Eb
, Gb
}, 0 },
2431 { "cmpS", { Ev
, Gv
}, 0 },
2432 { "cmpB", { Gb
, EbS
}, 0 },
2433 { "cmpS", { Gv
, EvS
}, 0 },
2434 { "cmpB", { AL
, Ib
}, 0 },
2435 { "cmpS", { eAX
, Iv
}, 0 },
2436 { Bad_Opcode
}, /* SEG DS prefix */
2437 { X86_64_TABLE (X86_64_3F
) },
2439 { "inc{S|}", { RMeAX
}, 0 },
2440 { "inc{S|}", { RMeCX
}, 0 },
2441 { "inc{S|}", { RMeDX
}, 0 },
2442 { "inc{S|}", { RMeBX
}, 0 },
2443 { "inc{S|}", { RMeSP
}, 0 },
2444 { "inc{S|}", { RMeBP
}, 0 },
2445 { "inc{S|}", { RMeSI
}, 0 },
2446 { "inc{S|}", { RMeDI
}, 0 },
2448 { "dec{S|}", { RMeAX
}, 0 },
2449 { "dec{S|}", { RMeCX
}, 0 },
2450 { "dec{S|}", { RMeDX
}, 0 },
2451 { "dec{S|}", { RMeBX
}, 0 },
2452 { "dec{S|}", { RMeSP
}, 0 },
2453 { "dec{S|}", { RMeBP
}, 0 },
2454 { "dec{S|}", { RMeSI
}, 0 },
2455 { "dec{S|}", { RMeDI
}, 0 },
2457 { "pushV", { RMrAX
}, 0 },
2458 { "pushV", { RMrCX
}, 0 },
2459 { "pushV", { RMrDX
}, 0 },
2460 { "pushV", { RMrBX
}, 0 },
2461 { "pushV", { RMrSP
}, 0 },
2462 { "pushV", { RMrBP
}, 0 },
2463 { "pushV", { RMrSI
}, 0 },
2464 { "pushV", { RMrDI
}, 0 },
2466 { "popV", { RMrAX
}, 0 },
2467 { "popV", { RMrCX
}, 0 },
2468 { "popV", { RMrDX
}, 0 },
2469 { "popV", { RMrBX
}, 0 },
2470 { "popV", { RMrSP
}, 0 },
2471 { "popV", { RMrBP
}, 0 },
2472 { "popV", { RMrSI
}, 0 },
2473 { "popV", { RMrDI
}, 0 },
2475 { X86_64_TABLE (X86_64_60
) },
2476 { X86_64_TABLE (X86_64_61
) },
2477 { X86_64_TABLE (X86_64_62
) },
2478 { X86_64_TABLE (X86_64_63
) },
2479 { Bad_Opcode
}, /* seg fs */
2480 { Bad_Opcode
}, /* seg gs */
2481 { Bad_Opcode
}, /* op size prefix */
2482 { Bad_Opcode
}, /* adr size prefix */
2484 { "pushT", { sIv
}, 0 },
2485 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2486 { "pushT", { sIbT
}, 0 },
2487 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2488 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2489 { X86_64_TABLE (X86_64_6D
) },
2490 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2491 { X86_64_TABLE (X86_64_6F
) },
2493 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { REG_TABLE (REG_80
) },
2512 { REG_TABLE (REG_81
) },
2513 { X86_64_TABLE (X86_64_82
) },
2514 { REG_TABLE (REG_83
) },
2515 { "testB", { Eb
, Gb
}, 0 },
2516 { "testS", { Ev
, Gv
}, 0 },
2517 { "xchgB", { Ebh2
, Gb
}, 0 },
2518 { "xchgS", { Evh2
, Gv
}, 0 },
2520 { "movB", { Ebh3
, Gb
}, 0 },
2521 { "movS", { Evh3
, Gv
}, 0 },
2522 { "movB", { Gb
, EbS
}, 0 },
2523 { "movS", { Gv
, EvS
}, 0 },
2524 { "movD", { Sv
, Sw
}, 0 },
2525 { MOD_TABLE (MOD_8D
) },
2526 { "movD", { Sw
, Sv
}, 0 },
2527 { REG_TABLE (REG_8F
) },
2529 { PREFIX_TABLE (PREFIX_90
) },
2530 { "xchgS", { RMeCX
, eAX
}, 0 },
2531 { "xchgS", { RMeDX
, eAX
}, 0 },
2532 { "xchgS", { RMeBX
, eAX
}, 0 },
2533 { "xchgS", { RMeSP
, eAX
}, 0 },
2534 { "xchgS", { RMeBP
, eAX
}, 0 },
2535 { "xchgS", { RMeSI
, eAX
}, 0 },
2536 { "xchgS", { RMeDI
, eAX
}, 0 },
2538 { "cW{t|}R", { XX
}, 0 },
2539 { "cR{t|}O", { XX
}, 0 },
2540 { X86_64_TABLE (X86_64_9A
) },
2541 { Bad_Opcode
}, /* fwait */
2542 { "pushfT", { XX
}, 0 },
2543 { "popfT", { XX
}, 0 },
2544 { "sahf", { XX
}, 0 },
2545 { "lahf", { XX
}, 0 },
2547 { "mov%LB", { AL
, Ob
}, 0 },
2548 { "mov%LS", { eAX
, Ov
}, 0 },
2549 { "mov%LB", { Ob
, AL
}, 0 },
2550 { "mov%LS", { Ov
, eAX
}, 0 },
2551 { "movs{b|}", { Ybr
, Xb
}, 0 },
2552 { "movs{R|}", { Yvr
, Xv
}, 0 },
2553 { "cmps{b|}", { Xb
, Yb
}, 0 },
2554 { "cmps{R|}", { Xv
, Yv
}, 0 },
2556 { "testB", { AL
, Ib
}, 0 },
2557 { "testS", { eAX
, Iv
}, 0 },
2558 { "stosB", { Ybr
, AL
}, 0 },
2559 { "stosS", { Yvr
, eAX
}, 0 },
2560 { "lodsB", { ALr
, Xb
}, 0 },
2561 { "lodsS", { eAXr
, Xv
}, 0 },
2562 { "scasB", { AL
, Yb
}, 0 },
2563 { "scasS", { eAX
, Yv
}, 0 },
2565 { "movB", { RMAL
, Ib
}, 0 },
2566 { "movB", { RMCL
, Ib
}, 0 },
2567 { "movB", { RMDL
, Ib
}, 0 },
2568 { "movB", { RMBL
, Ib
}, 0 },
2569 { "movB", { RMAH
, Ib
}, 0 },
2570 { "movB", { RMCH
, Ib
}, 0 },
2571 { "movB", { RMDH
, Ib
}, 0 },
2572 { "movB", { RMBH
, Ib
}, 0 },
2574 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2577 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2578 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2579 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2580 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2581 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2583 { REG_TABLE (REG_C0
) },
2584 { REG_TABLE (REG_C1
) },
2585 { "retT", { Iw
, BND
}, 0 },
2586 { "retT", { BND
}, 0 },
2587 { X86_64_TABLE (X86_64_C4
) },
2588 { X86_64_TABLE (X86_64_C5
) },
2589 { REG_TABLE (REG_C6
) },
2590 { REG_TABLE (REG_C7
) },
2592 { "enterT", { Iw
, Ib
}, 0 },
2593 { "leaveT", { XX
}, 0 },
2594 { "Jret{|f}P", { Iw
}, 0 },
2595 { "Jret{|f}P", { XX
}, 0 },
2596 { "int3", { XX
}, 0 },
2597 { "int", { Ib
}, 0 },
2598 { X86_64_TABLE (X86_64_CE
) },
2599 { "iret%LP", { XX
}, 0 },
2601 { REG_TABLE (REG_D0
) },
2602 { REG_TABLE (REG_D1
) },
2603 { REG_TABLE (REG_D2
) },
2604 { REG_TABLE (REG_D3
) },
2605 { X86_64_TABLE (X86_64_D4
) },
2606 { X86_64_TABLE (X86_64_D5
) },
2608 { "xlat", { DSBX
}, 0 },
2619 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2622 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2623 { "inB", { AL
, Ib
}, 0 },
2624 { "inG", { zAX
, Ib
}, 0 },
2625 { "outB", { Ib
, AL
}, 0 },
2626 { "outG", { Ib
, zAX
}, 0 },
2628 { X86_64_TABLE (X86_64_E8
) },
2629 { X86_64_TABLE (X86_64_E9
) },
2630 { X86_64_TABLE (X86_64_EA
) },
2631 { "jmp", { Jb
, BND
}, 0 },
2632 { "inB", { AL
, indirDX
}, 0 },
2633 { "inG", { zAX
, indirDX
}, 0 },
2634 { "outB", { indirDX
, AL
}, 0 },
2635 { "outG", { indirDX
, zAX
}, 0 },
2637 { Bad_Opcode
}, /* lock prefix */
2638 { "icebp", { XX
}, 0 },
2639 { Bad_Opcode
}, /* repne */
2640 { Bad_Opcode
}, /* repz */
2641 { "hlt", { XX
}, 0 },
2642 { "cmc", { XX
}, 0 },
2643 { REG_TABLE (REG_F6
) },
2644 { REG_TABLE (REG_F7
) },
2646 { "clc", { XX
}, 0 },
2647 { "stc", { XX
}, 0 },
2648 { "cli", { XX
}, 0 },
2649 { "sti", { XX
}, 0 },
2650 { "cld", { XX
}, 0 },
2651 { "std", { XX
}, 0 },
2652 { REG_TABLE (REG_FE
) },
2653 { REG_TABLE (REG_FF
) },
2656 static const struct dis386 dis386_twobyte
[] = {
2658 { REG_TABLE (REG_0F00
) },
2659 { REG_TABLE (REG_0F01
) },
2660 { "larS", { Gv
, Ew
}, 0 },
2661 { "lslS", { Gv
, Ew
}, 0 },
2663 { "syscall", { XX
}, 0 },
2664 { "clts", { XX
}, 0 },
2665 { "sysret%LP", { XX
}, 0 },
2667 { "invd", { XX
}, 0 },
2668 { PREFIX_TABLE (PREFIX_0F09
) },
2670 { "ud2", { XX
}, 0 },
2672 { REG_TABLE (REG_0F0D
) },
2673 { "femms", { XX
}, 0 },
2674 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2676 { PREFIX_TABLE (PREFIX_0F10
) },
2677 { PREFIX_TABLE (PREFIX_0F11
) },
2678 { PREFIX_TABLE (PREFIX_0F12
) },
2679 { MOD_TABLE (MOD_0F13
) },
2680 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2681 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2682 { PREFIX_TABLE (PREFIX_0F16
) },
2683 { MOD_TABLE (MOD_0F17
) },
2685 { REG_TABLE (REG_0F18
) },
2686 { "nopQ", { Ev
}, 0 },
2687 { PREFIX_TABLE (PREFIX_0F1A
) },
2688 { PREFIX_TABLE (PREFIX_0F1B
) },
2689 { PREFIX_TABLE (PREFIX_0F1C
) },
2690 { "nopQ", { Ev
}, 0 },
2691 { PREFIX_TABLE (PREFIX_0F1E
) },
2692 { "nopQ", { Ev
}, 0 },
2694 { "movZ", { Rm
, Cm
}, 0 },
2695 { "movZ", { Rm
, Dm
}, 0 },
2696 { "movZ", { Cm
, Rm
}, 0 },
2697 { "movZ", { Dm
, Rm
}, 0 },
2698 { MOD_TABLE (MOD_0F24
) },
2700 { MOD_TABLE (MOD_0F26
) },
2703 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2704 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2705 { PREFIX_TABLE (PREFIX_0F2A
) },
2706 { PREFIX_TABLE (PREFIX_0F2B
) },
2707 { PREFIX_TABLE (PREFIX_0F2C
) },
2708 { PREFIX_TABLE (PREFIX_0F2D
) },
2709 { PREFIX_TABLE (PREFIX_0F2E
) },
2710 { PREFIX_TABLE (PREFIX_0F2F
) },
2712 { "wrmsr", { XX
}, 0 },
2713 { "rdtsc", { XX
}, 0 },
2714 { "rdmsr", { XX
}, 0 },
2715 { "rdpmc", { XX
}, 0 },
2716 { "sysenter", { XX
}, 0 },
2717 { "sysexit", { XX
}, 0 },
2719 { "getsec", { XX
}, 0 },
2721 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2723 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2730 { "cmovoS", { Gv
, Ev
}, 0 },
2731 { "cmovnoS", { Gv
, Ev
}, 0 },
2732 { "cmovbS", { Gv
, Ev
}, 0 },
2733 { "cmovaeS", { Gv
, Ev
}, 0 },
2734 { "cmoveS", { Gv
, Ev
}, 0 },
2735 { "cmovneS", { Gv
, Ev
}, 0 },
2736 { "cmovbeS", { Gv
, Ev
}, 0 },
2737 { "cmovaS", { Gv
, Ev
}, 0 },
2739 { "cmovsS", { Gv
, Ev
}, 0 },
2740 { "cmovnsS", { Gv
, Ev
}, 0 },
2741 { "cmovpS", { Gv
, Ev
}, 0 },
2742 { "cmovnpS", { Gv
, Ev
}, 0 },
2743 { "cmovlS", { Gv
, Ev
}, 0 },
2744 { "cmovgeS", { Gv
, Ev
}, 0 },
2745 { "cmovleS", { Gv
, Ev
}, 0 },
2746 { "cmovgS", { Gv
, Ev
}, 0 },
2748 { MOD_TABLE (MOD_0F51
) },
2749 { PREFIX_TABLE (PREFIX_0F51
) },
2750 { PREFIX_TABLE (PREFIX_0F52
) },
2751 { PREFIX_TABLE (PREFIX_0F53
) },
2752 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2753 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2755 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2757 { PREFIX_TABLE (PREFIX_0F58
) },
2758 { PREFIX_TABLE (PREFIX_0F59
) },
2759 { PREFIX_TABLE (PREFIX_0F5A
) },
2760 { PREFIX_TABLE (PREFIX_0F5B
) },
2761 { PREFIX_TABLE (PREFIX_0F5C
) },
2762 { PREFIX_TABLE (PREFIX_0F5D
) },
2763 { PREFIX_TABLE (PREFIX_0F5E
) },
2764 { PREFIX_TABLE (PREFIX_0F5F
) },
2766 { PREFIX_TABLE (PREFIX_0F60
) },
2767 { PREFIX_TABLE (PREFIX_0F61
) },
2768 { PREFIX_TABLE (PREFIX_0F62
) },
2769 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2779 { PREFIX_TABLE (PREFIX_0F6C
) },
2780 { PREFIX_TABLE (PREFIX_0F6D
) },
2781 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2782 { PREFIX_TABLE (PREFIX_0F6F
) },
2784 { PREFIX_TABLE (PREFIX_0F70
) },
2785 { REG_TABLE (REG_0F71
) },
2786 { REG_TABLE (REG_0F72
) },
2787 { REG_TABLE (REG_0F73
) },
2788 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2790 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2791 { "emms", { XX
}, PREFIX_OPCODE
},
2793 { PREFIX_TABLE (PREFIX_0F78
) },
2794 { PREFIX_TABLE (PREFIX_0F79
) },
2797 { PREFIX_TABLE (PREFIX_0F7C
) },
2798 { PREFIX_TABLE (PREFIX_0F7D
) },
2799 { PREFIX_TABLE (PREFIX_0F7E
) },
2800 { PREFIX_TABLE (PREFIX_0F7F
) },
2802 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "seto", { Eb
}, 0 },
2821 { "setno", { Eb
}, 0 },
2822 { "setb", { Eb
}, 0 },
2823 { "setae", { Eb
}, 0 },
2824 { "sete", { Eb
}, 0 },
2825 { "setne", { Eb
}, 0 },
2826 { "setbe", { Eb
}, 0 },
2827 { "seta", { Eb
}, 0 },
2829 { "sets", { Eb
}, 0 },
2830 { "setns", { Eb
}, 0 },
2831 { "setp", { Eb
}, 0 },
2832 { "setnp", { Eb
}, 0 },
2833 { "setl", { Eb
}, 0 },
2834 { "setge", { Eb
}, 0 },
2835 { "setle", { Eb
}, 0 },
2836 { "setg", { Eb
}, 0 },
2838 { "pushT", { fs
}, 0 },
2839 { "popT", { fs
}, 0 },
2840 { "cpuid", { XX
}, 0 },
2841 { "btS", { Ev
, Gv
}, 0 },
2842 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2843 { "shldS", { Ev
, Gv
, CL
}, 0 },
2844 { REG_TABLE (REG_0FA6
) },
2845 { REG_TABLE (REG_0FA7
) },
2847 { "pushT", { gs
}, 0 },
2848 { "popT", { gs
}, 0 },
2849 { "rsm", { XX
}, 0 },
2850 { "btsS", { Evh1
, Gv
}, 0 },
2851 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2852 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2853 { REG_TABLE (REG_0FAE
) },
2854 { "imulS", { Gv
, Ev
}, 0 },
2856 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2857 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2858 { MOD_TABLE (MOD_0FB2
) },
2859 { "btrS", { Evh1
, Gv
}, 0 },
2860 { MOD_TABLE (MOD_0FB4
) },
2861 { MOD_TABLE (MOD_0FB5
) },
2862 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2863 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2865 { PREFIX_TABLE (PREFIX_0FB8
) },
2866 { "ud1S", { Gv
, Ev
}, 0 },
2867 { REG_TABLE (REG_0FBA
) },
2868 { "btcS", { Evh1
, Gv
}, 0 },
2869 { PREFIX_TABLE (PREFIX_0FBC
) },
2870 { PREFIX_TABLE (PREFIX_0FBD
) },
2871 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2872 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2874 { "xaddB", { Ebh1
, Gb
}, 0 },
2875 { "xaddS", { Evh1
, Gv
}, 0 },
2876 { PREFIX_TABLE (PREFIX_0FC2
) },
2877 { MOD_TABLE (MOD_0FC3
) },
2878 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2879 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2880 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2881 { REG_TABLE (REG_0FC7
) },
2883 { "bswap", { RMeAX
}, 0 },
2884 { "bswap", { RMeCX
}, 0 },
2885 { "bswap", { RMeDX
}, 0 },
2886 { "bswap", { RMeBX
}, 0 },
2887 { "bswap", { RMeSP
}, 0 },
2888 { "bswap", { RMeBP
}, 0 },
2889 { "bswap", { RMeSI
}, 0 },
2890 { "bswap", { RMeDI
}, 0 },
2892 { PREFIX_TABLE (PREFIX_0FD0
) },
2893 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2896 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2897 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2898 { PREFIX_TABLE (PREFIX_0FD6
) },
2899 { MOD_TABLE (MOD_0FD7
) },
2901 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { PREFIX_TABLE (PREFIX_0FE6
) },
2917 { PREFIX_TABLE (PREFIX_0FE7
) },
2919 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2928 { PREFIX_TABLE (PREFIX_0FF0
) },
2929 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2933 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2935 { PREFIX_TABLE (PREFIX_0FF7
) },
2937 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "ud0S", { Gv
, Ev
}, 0 },
2947 static const unsigned char onebyte_has_modrm
[256] = {
2948 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2949 /* ------------------------------- */
2950 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2951 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2952 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2953 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2954 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2955 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2956 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2957 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2958 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2959 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2960 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2961 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2962 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2963 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2964 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2965 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2966 /* ------------------------------- */
2967 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2970 static const unsigned char twobyte_has_modrm
[256] = {
2971 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2972 /* ------------------------------- */
2973 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2974 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2975 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2976 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2977 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2978 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2979 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2980 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2981 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2982 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2983 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2984 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2985 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2986 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2987 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2988 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2989 /* ------------------------------- */
2990 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2993 static char obuf
[100];
2995 static char *mnemonicendp
;
2996 static char scratchbuf
[100];
2997 static unsigned char *start_codep
;
2998 static unsigned char *insn_codep
;
2999 static unsigned char *codep
;
3000 static unsigned char *end_codep
;
3001 static int last_lock_prefix
;
3002 static int last_repz_prefix
;
3003 static int last_repnz_prefix
;
3004 static int last_data_prefix
;
3005 static int last_addr_prefix
;
3006 static int last_rex_prefix
;
3007 static int last_seg_prefix
;
3008 static int fwait_prefix
;
3009 /* The active segment register prefix. */
3010 static int active_seg_prefix
;
3011 #define MAX_CODE_LENGTH 15
3012 /* We can up to 14 prefixes since the maximum instruction length is
3014 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3015 static disassemble_info
*the_info
;
3023 static unsigned char need_modrm
;
3033 int register_specifier
;
3040 int mask_register_specifier
;
3046 static unsigned char need_vex
;
3047 static unsigned char need_vex_reg
;
3048 static unsigned char vex_w_done
;
3056 /* If we are accessing mod/rm/reg without need_modrm set, then the
3057 values are stale. Hitting this abort likely indicates that you
3058 need to update onebyte_has_modrm or twobyte_has_modrm. */
3059 #define MODRM_CHECK if (!need_modrm) abort ()
3061 static const char **names64
;
3062 static const char **names32
;
3063 static const char **names16
;
3064 static const char **names8
;
3065 static const char **names8rex
;
3066 static const char **names_seg
;
3067 static const char *index64
;
3068 static const char *index32
;
3069 static const char **index16
;
3070 static const char **names_bnd
;
3072 static const char *intel_names64
[] = {
3073 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3074 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3076 static const char *intel_names32
[] = {
3077 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3078 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3080 static const char *intel_names16
[] = {
3081 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3082 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3084 static const char *intel_names8
[] = {
3085 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3087 static const char *intel_names8rex
[] = {
3088 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3089 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3091 static const char *intel_names_seg
[] = {
3092 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3094 static const char *intel_index64
= "riz";
3095 static const char *intel_index32
= "eiz";
3096 static const char *intel_index16
[] = {
3097 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3100 static const char *att_names64
[] = {
3101 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3102 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3104 static const char *att_names32
[] = {
3105 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3106 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3108 static const char *att_names16
[] = {
3109 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3110 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3112 static const char *att_names8
[] = {
3113 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3115 static const char *att_names8rex
[] = {
3116 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3117 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3119 static const char *att_names_seg
[] = {
3120 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3122 static const char *att_index64
= "%riz";
3123 static const char *att_index32
= "%eiz";
3124 static const char *att_index16
[] = {
3125 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3128 static const char **names_mm
;
3129 static const char *intel_names_mm
[] = {
3130 "mm0", "mm1", "mm2", "mm3",
3131 "mm4", "mm5", "mm6", "mm7"
3133 static const char *att_names_mm
[] = {
3134 "%mm0", "%mm1", "%mm2", "%mm3",
3135 "%mm4", "%mm5", "%mm6", "%mm7"
3138 static const char *intel_names_bnd
[] = {
3139 "bnd0", "bnd1", "bnd2", "bnd3"
3142 static const char *att_names_bnd
[] = {
3143 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3146 static const char **names_xmm
;
3147 static const char *intel_names_xmm
[] = {
3148 "xmm0", "xmm1", "xmm2", "xmm3",
3149 "xmm4", "xmm5", "xmm6", "xmm7",
3150 "xmm8", "xmm9", "xmm10", "xmm11",
3151 "xmm12", "xmm13", "xmm14", "xmm15",
3152 "xmm16", "xmm17", "xmm18", "xmm19",
3153 "xmm20", "xmm21", "xmm22", "xmm23",
3154 "xmm24", "xmm25", "xmm26", "xmm27",
3155 "xmm28", "xmm29", "xmm30", "xmm31"
3157 static const char *att_names_xmm
[] = {
3158 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3159 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3160 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3161 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3162 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3163 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3164 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3165 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3168 static const char **names_ymm
;
3169 static const char *intel_names_ymm
[] = {
3170 "ymm0", "ymm1", "ymm2", "ymm3",
3171 "ymm4", "ymm5", "ymm6", "ymm7",
3172 "ymm8", "ymm9", "ymm10", "ymm11",
3173 "ymm12", "ymm13", "ymm14", "ymm15",
3174 "ymm16", "ymm17", "ymm18", "ymm19",
3175 "ymm20", "ymm21", "ymm22", "ymm23",
3176 "ymm24", "ymm25", "ymm26", "ymm27",
3177 "ymm28", "ymm29", "ymm30", "ymm31"
3179 static const char *att_names_ymm
[] = {
3180 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3181 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3182 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3183 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3184 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3185 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3186 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3187 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3190 static const char **names_zmm
;
3191 static const char *intel_names_zmm
[] = {
3192 "zmm0", "zmm1", "zmm2", "zmm3",
3193 "zmm4", "zmm5", "zmm6", "zmm7",
3194 "zmm8", "zmm9", "zmm10", "zmm11",
3195 "zmm12", "zmm13", "zmm14", "zmm15",
3196 "zmm16", "zmm17", "zmm18", "zmm19",
3197 "zmm20", "zmm21", "zmm22", "zmm23",
3198 "zmm24", "zmm25", "zmm26", "zmm27",
3199 "zmm28", "zmm29", "zmm30", "zmm31"
3201 static const char *att_names_zmm
[] = {
3202 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3203 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3204 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3205 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3206 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3207 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3208 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3209 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3212 static const char **names_mask
;
3213 static const char *intel_names_mask
[] = {
3214 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3216 static const char *att_names_mask
[] = {
3217 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3220 static const char *names_rounding
[] =
3228 static const struct dis386 reg_table
[][8] = {
3231 { "addA", { Ebh1
, Ib
}, 0 },
3232 { "orA", { Ebh1
, Ib
}, 0 },
3233 { "adcA", { Ebh1
, Ib
}, 0 },
3234 { "sbbA", { Ebh1
, Ib
}, 0 },
3235 { "andA", { Ebh1
, Ib
}, 0 },
3236 { "subA", { Ebh1
, Ib
}, 0 },
3237 { "xorA", { Ebh1
, Ib
}, 0 },
3238 { "cmpA", { Eb
, Ib
}, 0 },
3242 { "addQ", { Evh1
, Iv
}, 0 },
3243 { "orQ", { Evh1
, Iv
}, 0 },
3244 { "adcQ", { Evh1
, Iv
}, 0 },
3245 { "sbbQ", { Evh1
, Iv
}, 0 },
3246 { "andQ", { Evh1
, Iv
}, 0 },
3247 { "subQ", { Evh1
, Iv
}, 0 },
3248 { "xorQ", { Evh1
, Iv
}, 0 },
3249 { "cmpQ", { Ev
, Iv
}, 0 },
3253 { "addQ", { Evh1
, sIb
}, 0 },
3254 { "orQ", { Evh1
, sIb
}, 0 },
3255 { "adcQ", { Evh1
, sIb
}, 0 },
3256 { "sbbQ", { Evh1
, sIb
}, 0 },
3257 { "andQ", { Evh1
, sIb
}, 0 },
3258 { "subQ", { Evh1
, sIb
}, 0 },
3259 { "xorQ", { Evh1
, sIb
}, 0 },
3260 { "cmpQ", { Ev
, sIb
}, 0 },
3264 { "popU", { stackEv
}, 0 },
3265 { XOP_8F_TABLE (XOP_09
) },
3269 { XOP_8F_TABLE (XOP_09
) },
3273 { "rolA", { Eb
, Ib
}, 0 },
3274 { "rorA", { Eb
, Ib
}, 0 },
3275 { "rclA", { Eb
, Ib
}, 0 },
3276 { "rcrA", { Eb
, Ib
}, 0 },
3277 { "shlA", { Eb
, Ib
}, 0 },
3278 { "shrA", { Eb
, Ib
}, 0 },
3279 { "shlA", { Eb
, Ib
}, 0 },
3280 { "sarA", { Eb
, Ib
}, 0 },
3284 { "rolQ", { Ev
, Ib
}, 0 },
3285 { "rorQ", { Ev
, Ib
}, 0 },
3286 { "rclQ", { Ev
, Ib
}, 0 },
3287 { "rcrQ", { Ev
, Ib
}, 0 },
3288 { "shlQ", { Ev
, Ib
}, 0 },
3289 { "shrQ", { Ev
, Ib
}, 0 },
3290 { "shlQ", { Ev
, Ib
}, 0 },
3291 { "sarQ", { Ev
, Ib
}, 0 },
3295 { "movA", { Ebh3
, Ib
}, 0 },
3302 { MOD_TABLE (MOD_C6_REG_7
) },
3306 { "movQ", { Evh3
, Iv
}, 0 },
3313 { MOD_TABLE (MOD_C7_REG_7
) },
3317 { "rolA", { Eb
, I1
}, 0 },
3318 { "rorA", { Eb
, I1
}, 0 },
3319 { "rclA", { Eb
, I1
}, 0 },
3320 { "rcrA", { Eb
, I1
}, 0 },
3321 { "shlA", { Eb
, I1
}, 0 },
3322 { "shrA", { Eb
, I1
}, 0 },
3323 { "shlA", { Eb
, I1
}, 0 },
3324 { "sarA", { Eb
, I1
}, 0 },
3328 { "rolQ", { Ev
, I1
}, 0 },
3329 { "rorQ", { Ev
, I1
}, 0 },
3330 { "rclQ", { Ev
, I1
}, 0 },
3331 { "rcrQ", { Ev
, I1
}, 0 },
3332 { "shlQ", { Ev
, I1
}, 0 },
3333 { "shrQ", { Ev
, I1
}, 0 },
3334 { "shlQ", { Ev
, I1
}, 0 },
3335 { "sarQ", { Ev
, I1
}, 0 },
3339 { "rolA", { Eb
, CL
}, 0 },
3340 { "rorA", { Eb
, CL
}, 0 },
3341 { "rclA", { Eb
, CL
}, 0 },
3342 { "rcrA", { Eb
, CL
}, 0 },
3343 { "shlA", { Eb
, CL
}, 0 },
3344 { "shrA", { Eb
, CL
}, 0 },
3345 { "shlA", { Eb
, CL
}, 0 },
3346 { "sarA", { Eb
, CL
}, 0 },
3350 { "rolQ", { Ev
, CL
}, 0 },
3351 { "rorQ", { Ev
, CL
}, 0 },
3352 { "rclQ", { Ev
, CL
}, 0 },
3353 { "rcrQ", { Ev
, CL
}, 0 },
3354 { "shlQ", { Ev
, CL
}, 0 },
3355 { "shrQ", { Ev
, CL
}, 0 },
3356 { "shlQ", { Ev
, CL
}, 0 },
3357 { "sarQ", { Ev
, CL
}, 0 },
3361 { "testA", { Eb
, Ib
}, 0 },
3362 { "testA", { Eb
, Ib
}, 0 },
3363 { "notA", { Ebh1
}, 0 },
3364 { "negA", { Ebh1
}, 0 },
3365 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3366 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3367 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3368 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3372 { "testQ", { Ev
, Iv
}, 0 },
3373 { "testQ", { Ev
, Iv
}, 0 },
3374 { "notQ", { Evh1
}, 0 },
3375 { "negQ", { Evh1
}, 0 },
3376 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3377 { "imulQ", { Ev
}, 0 },
3378 { "divQ", { Ev
}, 0 },
3379 { "idivQ", { Ev
}, 0 },
3383 { "incA", { Ebh1
}, 0 },
3384 { "decA", { Ebh1
}, 0 },
3388 { "incQ", { Evh1
}, 0 },
3389 { "decQ", { Evh1
}, 0 },
3390 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3391 { MOD_TABLE (MOD_FF_REG_3
) },
3392 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3393 { MOD_TABLE (MOD_FF_REG_5
) },
3394 { "pushU", { stackEv
}, 0 },
3399 { "sldtD", { Sv
}, 0 },
3400 { "strD", { Sv
}, 0 },
3401 { "lldt", { Ew
}, 0 },
3402 { "ltr", { Ew
}, 0 },
3403 { "verr", { Ew
}, 0 },
3404 { "verw", { Ew
}, 0 },
3410 { MOD_TABLE (MOD_0F01_REG_0
) },
3411 { MOD_TABLE (MOD_0F01_REG_1
) },
3412 { MOD_TABLE (MOD_0F01_REG_2
) },
3413 { MOD_TABLE (MOD_0F01_REG_3
) },
3414 { "smswD", { Sv
}, 0 },
3415 { MOD_TABLE (MOD_0F01_REG_5
) },
3416 { "lmsw", { Ew
}, 0 },
3417 { MOD_TABLE (MOD_0F01_REG_7
) },
3421 { "prefetch", { Mb
}, 0 },
3422 { "prefetchw", { Mb
}, 0 },
3423 { "prefetchwt1", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetch", { Mb
}, 0 },
3432 { MOD_TABLE (MOD_0F18_REG_0
) },
3433 { MOD_TABLE (MOD_0F18_REG_1
) },
3434 { MOD_TABLE (MOD_0F18_REG_2
) },
3435 { MOD_TABLE (MOD_0F18_REG_3
) },
3436 { MOD_TABLE (MOD_0F18_REG_4
) },
3437 { MOD_TABLE (MOD_0F18_REG_5
) },
3438 { MOD_TABLE (MOD_0F18_REG_6
) },
3439 { MOD_TABLE (MOD_0F18_REG_7
) },
3441 /* REG_0F1C_P_0_MOD_0 */
3443 { "cldemote", { Mb
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3452 /* REG_0F1E_P_1_MOD_3 */
3454 { "nopQ", { Ev
}, 0 },
3455 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { "nopQ", { Ev
}, 0 },
3460 { "nopQ", { Ev
}, 0 },
3461 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3467 { MOD_TABLE (MOD_0F71_REG_2
) },
3469 { MOD_TABLE (MOD_0F71_REG_4
) },
3471 { MOD_TABLE (MOD_0F71_REG_6
) },
3477 { MOD_TABLE (MOD_0F72_REG_2
) },
3479 { MOD_TABLE (MOD_0F72_REG_4
) },
3481 { MOD_TABLE (MOD_0F72_REG_6
) },
3487 { MOD_TABLE (MOD_0F73_REG_2
) },
3488 { MOD_TABLE (MOD_0F73_REG_3
) },
3491 { MOD_TABLE (MOD_0F73_REG_6
) },
3492 { MOD_TABLE (MOD_0F73_REG_7
) },
3496 { "montmul", { { OP_0f07
, 0 } }, 0 },
3497 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3498 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3502 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3506 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3507 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3511 { MOD_TABLE (MOD_0FAE_REG_0
) },
3512 { MOD_TABLE (MOD_0FAE_REG_1
) },
3513 { MOD_TABLE (MOD_0FAE_REG_2
) },
3514 { MOD_TABLE (MOD_0FAE_REG_3
) },
3515 { MOD_TABLE (MOD_0FAE_REG_4
) },
3516 { MOD_TABLE (MOD_0FAE_REG_5
) },
3517 { MOD_TABLE (MOD_0FAE_REG_6
) },
3518 { MOD_TABLE (MOD_0FAE_REG_7
) },
3526 { "btQ", { Ev
, Ib
}, 0 },
3527 { "btsQ", { Evh1
, Ib
}, 0 },
3528 { "btrQ", { Evh1
, Ib
}, 0 },
3529 { "btcQ", { Evh1
, Ib
}, 0 },
3534 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3536 { MOD_TABLE (MOD_0FC7_REG_3
) },
3537 { MOD_TABLE (MOD_0FC7_REG_4
) },
3538 { MOD_TABLE (MOD_0FC7_REG_5
) },
3539 { MOD_TABLE (MOD_0FC7_REG_6
) },
3540 { MOD_TABLE (MOD_0FC7_REG_7
) },
3546 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3548 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3550 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3556 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3558 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3560 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3566 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3567 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3570 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3571 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3577 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3578 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3580 /* REG_VEX_0F38F3 */
3583 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3584 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3585 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3589 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3590 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3594 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3595 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3597 /* REG_XOP_TBM_01 */
3600 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 /* REG_XOP_TBM_02 */
3611 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3616 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3619 #include "i386-dis-evex-reg.h"
3622 static const struct dis386 prefix_table
[][4] = {
3625 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3626 { "pause", { XX
}, 0 },
3627 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3628 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3631 /* PREFIX_0F01_REG_5_MOD_0 */
3634 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3637 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3640 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3643 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3646 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3649 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3651 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3652 { "mcommit", { Skip_MODRM
}, 0 },
3655 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3657 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3662 { "wbinvd", { XX
}, 0 },
3663 { "wbnoinvd", { XX
}, 0 },
3668 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3669 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3670 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3671 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3676 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3677 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3678 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3679 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3684 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3685 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3686 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3687 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3692 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3693 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3694 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3699 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3700 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3701 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3702 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3707 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3708 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3709 { "bndmov", { EbndS
, Gbnd
}, 0 },
3710 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3715 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3716 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3717 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3718 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3723 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3724 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3725 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3726 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3731 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3732 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3733 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3734 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3742 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3747 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3748 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3749 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3750 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3755 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3756 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3757 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3758 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3763 { "ucomiss",{ XM
, EXd
}, 0 },
3765 { "ucomisd",{ XM
, EXq
}, 0 },
3770 { "comiss", { XM
, EXd
}, 0 },
3772 { "comisd", { XM
, EXq
}, 0 },
3777 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3779 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3780 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3785 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3786 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3791 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3797 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3798 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3799 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3800 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3805 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3806 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3807 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3813 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3814 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3815 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3816 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3821 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3822 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3828 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3829 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3830 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3836 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3837 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3838 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3844 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3845 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3846 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3847 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3852 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3853 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3854 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3855 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3860 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3862 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3867 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3869 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3874 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3876 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3883 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3890 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3895 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3896 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3897 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3902 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3903 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3904 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3905 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3908 /* PREFIX_0F73_REG_3 */
3912 { "psrldq", { XS
, Ib
}, 0 },
3915 /* PREFIX_0F73_REG_7 */
3919 { "pslldq", { XS
, Ib
}, 0 },
3924 {"vmread", { Em
, Gm
}, 0 },
3926 {"extrq", { XS
, Ib
, Ib
}, 0 },
3927 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3932 {"vmwrite", { Gm
, Em
}, 0 },
3934 {"extrq", { XM
, XS
}, 0 },
3935 {"insertq", { XM
, XS
}, 0 },
3942 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3943 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3950 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3951 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3956 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3957 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3958 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3963 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3964 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3965 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3968 /* PREFIX_0FAE_REG_0_MOD_3 */
3971 { "rdfsbase", { Ev
}, 0 },
3974 /* PREFIX_0FAE_REG_1_MOD_3 */
3977 { "rdgsbase", { Ev
}, 0 },
3980 /* PREFIX_0FAE_REG_2_MOD_3 */
3983 { "wrfsbase", { Ev
}, 0 },
3986 /* PREFIX_0FAE_REG_3_MOD_3 */
3989 { "wrgsbase", { Ev
}, 0 },
3992 /* PREFIX_0FAE_REG_4_MOD_0 */
3994 { "xsave", { FXSAVE
}, 0 },
3995 { "ptwrite%LQ", { Edq
}, 0 },
3998 /* PREFIX_0FAE_REG_4_MOD_3 */
4001 { "ptwrite%LQ", { Edq
}, 0 },
4004 /* PREFIX_0FAE_REG_5_MOD_0 */
4006 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4009 /* PREFIX_0FAE_REG_5_MOD_3 */
4011 { "lfence", { Skip_MODRM
}, 0 },
4012 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4015 /* PREFIX_0FAE_REG_6_MOD_0 */
4017 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4018 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4019 { "clwb", { Mb
}, PREFIX_OPCODE
},
4022 /* PREFIX_0FAE_REG_6_MOD_3 */
4024 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4025 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4026 { "tpause", { Edq
}, PREFIX_OPCODE
},
4027 { "umwait", { Edq
}, PREFIX_OPCODE
},
4030 /* PREFIX_0FAE_REG_7_MOD_0 */
4032 { "clflush", { Mb
}, 0 },
4034 { "clflushopt", { Mb
}, 0 },
4040 { "popcntS", { Gv
, Ev
}, 0 },
4045 { "bsfS", { Gv
, Ev
}, 0 },
4046 { "tzcntS", { Gv
, Ev
}, 0 },
4047 { "bsfS", { Gv
, Ev
}, 0 },
4052 { "bsrS", { Gv
, Ev
}, 0 },
4053 { "lzcntS", { Gv
, Ev
}, 0 },
4054 { "bsrS", { Gv
, Ev
}, 0 },
4059 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4060 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4061 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4062 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4065 /* PREFIX_0FC3_MOD_0 */
4067 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4070 /* PREFIX_0FC7_REG_6_MOD_0 */
4072 { "vmptrld",{ Mq
}, 0 },
4073 { "vmxon", { Mq
}, 0 },
4074 { "vmclear",{ Mq
}, 0 },
4077 /* PREFIX_0FC7_REG_6_MOD_3 */
4079 { "rdrand", { Ev
}, 0 },
4081 { "rdrand", { Ev
}, 0 }
4084 /* PREFIX_0FC7_REG_7_MOD_3 */
4086 { "rdseed", { Ev
}, 0 },
4087 { "rdpid", { Em
}, 0 },
4088 { "rdseed", { Ev
}, 0 },
4095 { "addsubpd", { XM
, EXx
}, 0 },
4096 { "addsubps", { XM
, EXx
}, 0 },
4102 { "movq2dq",{ XM
, MS
}, 0 },
4103 { "movq", { EXqS
, XM
}, 0 },
4104 { "movdq2q",{ MX
, XS
}, 0 },
4110 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4111 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4112 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4117 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4119 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4127 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4132 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4134 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4141 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4148 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4155 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4162 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4169 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4176 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4183 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4190 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4197 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4204 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4211 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4218 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4225 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4232 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4239 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4246 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4253 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4260 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4267 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4274 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4281 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4288 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4295 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4302 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4309 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4316 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4323 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4330 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4337 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4344 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4351 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4358 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4365 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4372 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4377 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4382 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4387 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4392 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4397 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4402 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4409 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4416 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4423 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4430 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4437 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4444 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4449 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4451 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4452 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4457 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4459 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4460 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4467 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4472 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4473 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4474 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4482 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4483 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4488 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4495 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4502 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4509 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4516 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4523 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4530 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4537 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4544 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4551 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4558 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4565 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4572 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4579 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4586 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4593 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4600 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4607 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4614 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4621 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4628 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4635 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4642 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4647 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4654 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4661 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4668 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4671 /* PREFIX_VEX_0F10 */
4673 { "vmovups", { XM
, EXx
}, 0 },
4674 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4675 { "vmovupd", { XM
, EXx
}, 0 },
4676 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4679 /* PREFIX_VEX_0F11 */
4681 { "vmovups", { EXxS
, XM
}, 0 },
4682 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4683 { "vmovupd", { EXxS
, XM
}, 0 },
4684 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4687 /* PREFIX_VEX_0F12 */
4689 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4690 { "vmovsldup", { XM
, EXx
}, 0 },
4691 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4692 { "vmovddup", { XM
, EXymmq
}, 0 },
4695 /* PREFIX_VEX_0F16 */
4697 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4698 { "vmovshdup", { XM
, EXx
}, 0 },
4699 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4702 /* PREFIX_VEX_0F2A */
4705 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4707 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4710 /* PREFIX_VEX_0F2C */
4713 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4715 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4718 /* PREFIX_VEX_0F2D */
4721 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4723 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4726 /* PREFIX_VEX_0F2E */
4728 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4730 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4733 /* PREFIX_VEX_0F2F */
4735 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4737 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4740 /* PREFIX_VEX_0F41 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4747 /* PREFIX_VEX_0F42 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4754 /* PREFIX_VEX_0F44 */
4756 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4761 /* PREFIX_VEX_0F45 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4768 /* PREFIX_VEX_0F46 */
4770 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4775 /* PREFIX_VEX_0F47 */
4777 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4782 /* PREFIX_VEX_0F4A */
4784 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4789 /* PREFIX_VEX_0F4B */
4791 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4796 /* PREFIX_VEX_0F51 */
4798 { "vsqrtps", { XM
, EXx
}, 0 },
4799 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4800 { "vsqrtpd", { XM
, EXx
}, 0 },
4801 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4804 /* PREFIX_VEX_0F52 */
4806 { "vrsqrtps", { XM
, EXx
}, 0 },
4807 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4810 /* PREFIX_VEX_0F53 */
4812 { "vrcpps", { XM
, EXx
}, 0 },
4813 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4816 /* PREFIX_VEX_0F58 */
4818 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4819 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4820 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4821 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4824 /* PREFIX_VEX_0F59 */
4826 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4827 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4828 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4829 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4832 /* PREFIX_VEX_0F5A */
4834 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4835 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4836 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4837 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4840 /* PREFIX_VEX_0F5B */
4842 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4843 { "vcvttps2dq", { XM
, EXx
}, 0 },
4844 { "vcvtps2dq", { XM
, EXx
}, 0 },
4847 /* PREFIX_VEX_0F5C */
4849 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4850 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4851 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4852 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4855 /* PREFIX_VEX_0F5D */
4857 { "vminps", { XM
, Vex
, EXx
}, 0 },
4858 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4859 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4860 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4863 /* PREFIX_VEX_0F5E */
4865 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4866 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4867 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4868 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4871 /* PREFIX_VEX_0F5F */
4873 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4874 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4875 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4876 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4879 /* PREFIX_VEX_0F60 */
4883 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4886 /* PREFIX_VEX_0F61 */
4890 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4893 /* PREFIX_VEX_0F62 */
4897 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4900 /* PREFIX_VEX_0F63 */
4904 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4907 /* PREFIX_VEX_0F64 */
4911 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4914 /* PREFIX_VEX_0F65 */
4918 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4921 /* PREFIX_VEX_0F66 */
4925 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4928 /* PREFIX_VEX_0F67 */
4932 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4935 /* PREFIX_VEX_0F68 */
4939 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4942 /* PREFIX_VEX_0F69 */
4946 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4949 /* PREFIX_VEX_0F6A */
4953 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4956 /* PREFIX_VEX_0F6B */
4960 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4963 /* PREFIX_VEX_0F6C */
4967 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4970 /* PREFIX_VEX_0F6D */
4974 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4977 /* PREFIX_VEX_0F6E */
4981 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4984 /* PREFIX_VEX_0F6F */
4987 { "vmovdqu", { XM
, EXx
}, 0 },
4988 { "vmovdqa", { XM
, EXx
}, 0 },
4991 /* PREFIX_VEX_0F70 */
4994 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4995 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4996 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4999 /* PREFIX_VEX_0F71_REG_2 */
5003 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5006 /* PREFIX_VEX_0F71_REG_4 */
5010 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5013 /* PREFIX_VEX_0F71_REG_6 */
5017 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5020 /* PREFIX_VEX_0F72_REG_2 */
5024 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5027 /* PREFIX_VEX_0F72_REG_4 */
5031 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5034 /* PREFIX_VEX_0F72_REG_6 */
5038 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5041 /* PREFIX_VEX_0F73_REG_2 */
5045 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5048 /* PREFIX_VEX_0F73_REG_3 */
5052 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5055 /* PREFIX_VEX_0F73_REG_6 */
5059 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5062 /* PREFIX_VEX_0F73_REG_7 */
5066 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5069 /* PREFIX_VEX_0F74 */
5073 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5076 /* PREFIX_VEX_0F75 */
5080 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5083 /* PREFIX_VEX_0F76 */
5087 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5090 /* PREFIX_VEX_0F77 */
5092 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5095 /* PREFIX_VEX_0F7C */
5099 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5100 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5103 /* PREFIX_VEX_0F7D */
5107 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5108 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5111 /* PREFIX_VEX_0F7E */
5114 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5115 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5118 /* PREFIX_VEX_0F7F */
5121 { "vmovdqu", { EXxS
, XM
}, 0 },
5122 { "vmovdqa", { EXxS
, XM
}, 0 },
5125 /* PREFIX_VEX_0F90 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5132 /* PREFIX_VEX_0F91 */
5134 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5139 /* PREFIX_VEX_0F92 */
5141 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5144 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5147 /* PREFIX_VEX_0F93 */
5149 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5152 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5155 /* PREFIX_VEX_0F98 */
5157 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5159 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5162 /* PREFIX_VEX_0F99 */
5164 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5166 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5169 /* PREFIX_VEX_0FC2 */
5171 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5172 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5173 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5174 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5177 /* PREFIX_VEX_0FC4 */
5181 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5184 /* PREFIX_VEX_0FC5 */
5188 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5191 /* PREFIX_VEX_0FD0 */
5195 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5196 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5199 /* PREFIX_VEX_0FD1 */
5203 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5206 /* PREFIX_VEX_0FD2 */
5210 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5213 /* PREFIX_VEX_0FD3 */
5217 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5220 /* PREFIX_VEX_0FD4 */
5224 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5227 /* PREFIX_VEX_0FD5 */
5231 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5234 /* PREFIX_VEX_0FD6 */
5238 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5241 /* PREFIX_VEX_0FD7 */
5245 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5248 /* PREFIX_VEX_0FD8 */
5252 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5255 /* PREFIX_VEX_0FD9 */
5259 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5262 /* PREFIX_VEX_0FDA */
5266 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5269 /* PREFIX_VEX_0FDB */
5273 { "vpand", { XM
, Vex
, EXx
}, 0 },
5276 /* PREFIX_VEX_0FDC */
5280 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5283 /* PREFIX_VEX_0FDD */
5287 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5290 /* PREFIX_VEX_0FDE */
5294 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5297 /* PREFIX_VEX_0FDF */
5301 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5304 /* PREFIX_VEX_0FE0 */
5308 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5311 /* PREFIX_VEX_0FE1 */
5315 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5318 /* PREFIX_VEX_0FE2 */
5322 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5325 /* PREFIX_VEX_0FE3 */
5329 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5332 /* PREFIX_VEX_0FE4 */
5336 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5339 /* PREFIX_VEX_0FE5 */
5343 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5346 /* PREFIX_VEX_0FE6 */
5349 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5350 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5351 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FE7 */
5358 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5361 /* PREFIX_VEX_0FE8 */
5365 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5368 /* PREFIX_VEX_0FE9 */
5372 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5375 /* PREFIX_VEX_0FEA */
5379 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5382 /* PREFIX_VEX_0FEB */
5386 { "vpor", { XM
, Vex
, EXx
}, 0 },
5389 /* PREFIX_VEX_0FEC */
5393 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5396 /* PREFIX_VEX_0FED */
5400 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5403 /* PREFIX_VEX_0FEE */
5407 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5410 /* PREFIX_VEX_0FEF */
5414 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5417 /* PREFIX_VEX_0FF0 */
5422 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5425 /* PREFIX_VEX_0FF1 */
5429 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5432 /* PREFIX_VEX_0FF2 */
5436 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5439 /* PREFIX_VEX_0FF3 */
5443 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5446 /* PREFIX_VEX_0FF4 */
5450 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5453 /* PREFIX_VEX_0FF5 */
5457 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5460 /* PREFIX_VEX_0FF6 */
5464 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5467 /* PREFIX_VEX_0FF7 */
5471 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5474 /* PREFIX_VEX_0FF8 */
5478 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5481 /* PREFIX_VEX_0FF9 */
5485 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5488 /* PREFIX_VEX_0FFA */
5492 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5495 /* PREFIX_VEX_0FFB */
5499 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5502 /* PREFIX_VEX_0FFC */
5506 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5509 /* PREFIX_VEX_0FFD */
5513 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5516 /* PREFIX_VEX_0FFE */
5520 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5523 /* PREFIX_VEX_0F3800 */
5527 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5530 /* PREFIX_VEX_0F3801 */
5534 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5537 /* PREFIX_VEX_0F3802 */
5541 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5544 /* PREFIX_VEX_0F3803 */
5548 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5551 /* PREFIX_VEX_0F3804 */
5555 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5558 /* PREFIX_VEX_0F3805 */
5562 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5565 /* PREFIX_VEX_0F3806 */
5569 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5572 /* PREFIX_VEX_0F3807 */
5576 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5579 /* PREFIX_VEX_0F3808 */
5583 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5586 /* PREFIX_VEX_0F3809 */
5590 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5593 /* PREFIX_VEX_0F380A */
5597 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5600 /* PREFIX_VEX_0F380B */
5604 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5607 /* PREFIX_VEX_0F380C */
5611 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5614 /* PREFIX_VEX_0F380D */
5618 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5621 /* PREFIX_VEX_0F380E */
5625 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5628 /* PREFIX_VEX_0F380F */
5632 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5635 /* PREFIX_VEX_0F3813 */
5639 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5642 /* PREFIX_VEX_0F3816 */
5646 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5649 /* PREFIX_VEX_0F3817 */
5653 { "vptest", { XM
, EXx
}, 0 },
5656 /* PREFIX_VEX_0F3818 */
5660 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5663 /* PREFIX_VEX_0F3819 */
5667 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5670 /* PREFIX_VEX_0F381A */
5674 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5677 /* PREFIX_VEX_0F381C */
5681 { "vpabsb", { XM
, EXx
}, 0 },
5684 /* PREFIX_VEX_0F381D */
5688 { "vpabsw", { XM
, EXx
}, 0 },
5691 /* PREFIX_VEX_0F381E */
5695 { "vpabsd", { XM
, EXx
}, 0 },
5698 /* PREFIX_VEX_0F3820 */
5702 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5705 /* PREFIX_VEX_0F3821 */
5709 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5712 /* PREFIX_VEX_0F3822 */
5716 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5719 /* PREFIX_VEX_0F3823 */
5723 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5726 /* PREFIX_VEX_0F3824 */
5730 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5733 /* PREFIX_VEX_0F3825 */
5737 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5740 /* PREFIX_VEX_0F3828 */
5744 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5747 /* PREFIX_VEX_0F3829 */
5751 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5754 /* PREFIX_VEX_0F382A */
5758 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5761 /* PREFIX_VEX_0F382B */
5765 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5768 /* PREFIX_VEX_0F382C */
5772 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5775 /* PREFIX_VEX_0F382D */
5779 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5782 /* PREFIX_VEX_0F382E */
5786 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5789 /* PREFIX_VEX_0F382F */
5793 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5796 /* PREFIX_VEX_0F3830 */
5800 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5803 /* PREFIX_VEX_0F3831 */
5807 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5810 /* PREFIX_VEX_0F3832 */
5814 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5817 /* PREFIX_VEX_0F3833 */
5821 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5824 /* PREFIX_VEX_0F3834 */
5828 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5831 /* PREFIX_VEX_0F3835 */
5835 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5838 /* PREFIX_VEX_0F3836 */
5842 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5845 /* PREFIX_VEX_0F3837 */
5849 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5852 /* PREFIX_VEX_0F3838 */
5856 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5859 /* PREFIX_VEX_0F3839 */
5863 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5866 /* PREFIX_VEX_0F383A */
5870 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5873 /* PREFIX_VEX_0F383B */
5877 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5880 /* PREFIX_VEX_0F383C */
5884 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5887 /* PREFIX_VEX_0F383D */
5891 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5894 /* PREFIX_VEX_0F383E */
5898 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5901 /* PREFIX_VEX_0F383F */
5905 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5908 /* PREFIX_VEX_0F3840 */
5912 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5915 /* PREFIX_VEX_0F3841 */
5919 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5922 /* PREFIX_VEX_0F3845 */
5926 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5929 /* PREFIX_VEX_0F3846 */
5933 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5936 /* PREFIX_VEX_0F3847 */
5940 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5943 /* PREFIX_VEX_0F3858 */
5947 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5950 /* PREFIX_VEX_0F3859 */
5954 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5957 /* PREFIX_VEX_0F385A */
5961 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5964 /* PREFIX_VEX_0F3878 */
5968 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5971 /* PREFIX_VEX_0F3879 */
5975 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5978 /* PREFIX_VEX_0F388C */
5982 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5985 /* PREFIX_VEX_0F388E */
5989 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5992 /* PREFIX_VEX_0F3890 */
5996 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5999 /* PREFIX_VEX_0F3891 */
6003 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6006 /* PREFIX_VEX_0F3892 */
6010 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6013 /* PREFIX_VEX_0F3893 */
6017 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6020 /* PREFIX_VEX_0F3896 */
6024 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6027 /* PREFIX_VEX_0F3897 */
6031 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6034 /* PREFIX_VEX_0F3898 */
6038 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6041 /* PREFIX_VEX_0F3899 */
6045 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6048 /* PREFIX_VEX_0F389A */
6052 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6055 /* PREFIX_VEX_0F389B */
6059 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6062 /* PREFIX_VEX_0F389C */
6066 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6069 /* PREFIX_VEX_0F389D */
6073 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6076 /* PREFIX_VEX_0F389E */
6080 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6083 /* PREFIX_VEX_0F389F */
6087 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6090 /* PREFIX_VEX_0F38A6 */
6094 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6098 /* PREFIX_VEX_0F38A7 */
6102 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6105 /* PREFIX_VEX_0F38A8 */
6109 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6112 /* PREFIX_VEX_0F38A9 */
6116 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6119 /* PREFIX_VEX_0F38AA */
6123 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6126 /* PREFIX_VEX_0F38AB */
6130 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6133 /* PREFIX_VEX_0F38AC */
6137 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6140 /* PREFIX_VEX_0F38AD */
6144 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6147 /* PREFIX_VEX_0F38AE */
6151 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6154 /* PREFIX_VEX_0F38AF */
6158 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6161 /* PREFIX_VEX_0F38B6 */
6165 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6168 /* PREFIX_VEX_0F38B7 */
6172 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6175 /* PREFIX_VEX_0F38B8 */
6179 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6182 /* PREFIX_VEX_0F38B9 */
6186 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6189 /* PREFIX_VEX_0F38BA */
6193 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6196 /* PREFIX_VEX_0F38BB */
6200 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6203 /* PREFIX_VEX_0F38BC */
6207 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6210 /* PREFIX_VEX_0F38BD */
6214 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6217 /* PREFIX_VEX_0F38BE */
6221 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6224 /* PREFIX_VEX_0F38BF */
6228 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6231 /* PREFIX_VEX_0F38CF */
6235 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6238 /* PREFIX_VEX_0F38DB */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6245 /* PREFIX_VEX_0F38DC */
6249 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6252 /* PREFIX_VEX_0F38DD */
6256 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6259 /* PREFIX_VEX_0F38DE */
6263 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6266 /* PREFIX_VEX_0F38DF */
6270 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6273 /* PREFIX_VEX_0F38F2 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6278 /* PREFIX_VEX_0F38F3_REG_1 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6283 /* PREFIX_VEX_0F38F3_REG_2 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6288 /* PREFIX_VEX_0F38F3_REG_3 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6293 /* PREFIX_VEX_0F38F5 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6301 /* PREFIX_VEX_0F38F6 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6309 /* PREFIX_VEX_0F38F7 */
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6317 /* PREFIX_VEX_0F3A00 */
6321 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6324 /* PREFIX_VEX_0F3A01 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6331 /* PREFIX_VEX_0F3A02 */
6335 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6338 /* PREFIX_VEX_0F3A04 */
6342 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6345 /* PREFIX_VEX_0F3A05 */
6349 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6352 /* PREFIX_VEX_0F3A06 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6359 /* PREFIX_VEX_0F3A08 */
6363 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6366 /* PREFIX_VEX_0F3A09 */
6370 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6373 /* PREFIX_VEX_0F3A0A */
6377 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6380 /* PREFIX_VEX_0F3A0B */
6384 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6387 /* PREFIX_VEX_0F3A0C */
6391 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6394 /* PREFIX_VEX_0F3A0D */
6398 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6401 /* PREFIX_VEX_0F3A0E */
6405 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6408 /* PREFIX_VEX_0F3A0F */
6412 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6415 /* PREFIX_VEX_0F3A14 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6422 /* PREFIX_VEX_0F3A15 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6429 /* PREFIX_VEX_0F3A16 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6436 /* PREFIX_VEX_0F3A17 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6443 /* PREFIX_VEX_0F3A18 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6450 /* PREFIX_VEX_0F3A19 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6457 /* PREFIX_VEX_0F3A1D */
6461 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6464 /* PREFIX_VEX_0F3A20 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6471 /* PREFIX_VEX_0F3A21 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6478 /* PREFIX_VEX_0F3A22 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6485 /* PREFIX_VEX_0F3A30 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6492 /* PREFIX_VEX_0F3A31 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6499 /* PREFIX_VEX_0F3A32 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6506 /* PREFIX_VEX_0F3A33 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6513 /* PREFIX_VEX_0F3A38 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6520 /* PREFIX_VEX_0F3A39 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6527 /* PREFIX_VEX_0F3A40 */
6531 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6534 /* PREFIX_VEX_0F3A41 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6541 /* PREFIX_VEX_0F3A42 */
6545 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6548 /* PREFIX_VEX_0F3A44 */
6552 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6555 /* PREFIX_VEX_0F3A46 */
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6562 /* PREFIX_VEX_0F3A48 */
6566 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6569 /* PREFIX_VEX_0F3A49 */
6573 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6576 /* PREFIX_VEX_0F3A4A */
6580 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6583 /* PREFIX_VEX_0F3A4B */
6587 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6590 /* PREFIX_VEX_0F3A4C */
6594 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6597 /* PREFIX_VEX_0F3A5C */
6601 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6604 /* PREFIX_VEX_0F3A5D */
6608 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6611 /* PREFIX_VEX_0F3A5E */
6615 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6618 /* PREFIX_VEX_0F3A5F */
6622 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6625 /* PREFIX_VEX_0F3A60 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6633 /* PREFIX_VEX_0F3A61 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6640 /* PREFIX_VEX_0F3A62 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6647 /* PREFIX_VEX_0F3A63 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6654 /* PREFIX_VEX_0F3A68 */
6658 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6661 /* PREFIX_VEX_0F3A69 */
6665 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6668 /* PREFIX_VEX_0F3A6A */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6675 /* PREFIX_VEX_0F3A6B */
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6682 /* PREFIX_VEX_0F3A6C */
6686 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6689 /* PREFIX_VEX_0F3A6D */
6693 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6696 /* PREFIX_VEX_0F3A6E */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6703 /* PREFIX_VEX_0F3A6F */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6710 /* PREFIX_VEX_0F3A78 */
6714 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6717 /* PREFIX_VEX_0F3A79 */
6721 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6724 /* PREFIX_VEX_0F3A7A */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6731 /* PREFIX_VEX_0F3A7B */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6738 /* PREFIX_VEX_0F3A7C */
6742 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6746 /* PREFIX_VEX_0F3A7D */
6750 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6753 /* PREFIX_VEX_0F3A7E */
6757 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6760 /* PREFIX_VEX_0F3A7F */
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6767 /* PREFIX_VEX_0F3ACE */
6771 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6774 /* PREFIX_VEX_0F3ACF */
6778 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6781 /* PREFIX_VEX_0F3ADF */
6785 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6788 /* PREFIX_VEX_0F3AF0 */
6793 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6796 #include "i386-dis-evex-prefix.h"
6799 static const struct dis386 x86_64_table
[][2] = {
6802 { "pushP", { es
}, 0 },
6807 { "popP", { es
}, 0 },
6812 { "pushP", { cs
}, 0 },
6817 { "pushP", { ss
}, 0 },
6822 { "popP", { ss
}, 0 },
6827 { "pushP", { ds
}, 0 },
6832 { "popP", { ds
}, 0 },
6837 { "daa", { XX
}, 0 },
6842 { "das", { XX
}, 0 },
6847 { "aaa", { XX
}, 0 },
6852 { "aas", { XX
}, 0 },
6857 { "pushaP", { XX
}, 0 },
6862 { "popaP", { XX
}, 0 },
6867 { MOD_TABLE (MOD_62_32BIT
) },
6868 { EVEX_TABLE (EVEX_0F
) },
6873 { "arpl", { Ew
, Gw
}, 0 },
6874 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6879 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6880 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6885 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6886 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6891 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6892 { REG_TABLE (REG_80
) },
6897 { "Jcall{T|}", { Ap
}, 0 },
6902 { MOD_TABLE (MOD_C4_32BIT
) },
6903 { VEX_C4_TABLE (VEX_0F
) },
6908 { MOD_TABLE (MOD_C5_32BIT
) },
6909 { VEX_C5_TABLE (VEX_0F
) },
6914 { "into", { XX
}, 0 },
6919 { "aam", { Ib
}, 0 },
6924 { "aad", { Ib
}, 0 },
6929 { "callP", { Jv
, BND
}, 0 },
6930 { "call@", { Jv
, BND
}, 0 }
6935 { "jmpP", { Jv
, BND
}, 0 },
6936 { "jmp@", { Jv
, BND
}, 0 }
6941 { "Jjmp{T|}", { Ap
}, 0 },
6944 /* X86_64_0F01_REG_0 */
6946 { "sgdt{Q|IQ}", { M
}, 0 },
6947 { "sgdt", { M
}, 0 },
6950 /* X86_64_0F01_REG_1 */
6952 { "sidt{Q|IQ}", { M
}, 0 },
6953 { "sidt", { M
}, 0 },
6956 /* X86_64_0F01_REG_2 */
6958 { "lgdt{Q|Q}", { M
}, 0 },
6959 { "lgdt", { M
}, 0 },
6962 /* X86_64_0F01_REG_3 */
6964 { "lidt{Q|Q}", { M
}, 0 },
6965 { "lidt", { M
}, 0 },
6969 static const struct dis386 three_byte_table
[][256] = {
6971 /* THREE_BYTE_0F38 */
6974 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6984 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6986 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6992 { PREFIX_TABLE (PREFIX_0F3810
) },
6996 { PREFIX_TABLE (PREFIX_0F3814
) },
6997 { PREFIX_TABLE (PREFIX_0F3815
) },
6999 { PREFIX_TABLE (PREFIX_0F3817
) },
7005 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7006 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7007 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7010 { PREFIX_TABLE (PREFIX_0F3820
) },
7011 { PREFIX_TABLE (PREFIX_0F3821
) },
7012 { PREFIX_TABLE (PREFIX_0F3822
) },
7013 { PREFIX_TABLE (PREFIX_0F3823
) },
7014 { PREFIX_TABLE (PREFIX_0F3824
) },
7015 { PREFIX_TABLE (PREFIX_0F3825
) },
7019 { PREFIX_TABLE (PREFIX_0F3828
) },
7020 { PREFIX_TABLE (PREFIX_0F3829
) },
7021 { PREFIX_TABLE (PREFIX_0F382A
) },
7022 { PREFIX_TABLE (PREFIX_0F382B
) },
7028 { PREFIX_TABLE (PREFIX_0F3830
) },
7029 { PREFIX_TABLE (PREFIX_0F3831
) },
7030 { PREFIX_TABLE (PREFIX_0F3832
) },
7031 { PREFIX_TABLE (PREFIX_0F3833
) },
7032 { PREFIX_TABLE (PREFIX_0F3834
) },
7033 { PREFIX_TABLE (PREFIX_0F3835
) },
7035 { PREFIX_TABLE (PREFIX_0F3837
) },
7037 { PREFIX_TABLE (PREFIX_0F3838
) },
7038 { PREFIX_TABLE (PREFIX_0F3839
) },
7039 { PREFIX_TABLE (PREFIX_0F383A
) },
7040 { PREFIX_TABLE (PREFIX_0F383B
) },
7041 { PREFIX_TABLE (PREFIX_0F383C
) },
7042 { PREFIX_TABLE (PREFIX_0F383D
) },
7043 { PREFIX_TABLE (PREFIX_0F383E
) },
7044 { PREFIX_TABLE (PREFIX_0F383F
) },
7046 { PREFIX_TABLE (PREFIX_0F3840
) },
7047 { PREFIX_TABLE (PREFIX_0F3841
) },
7118 { PREFIX_TABLE (PREFIX_0F3880
) },
7119 { PREFIX_TABLE (PREFIX_0F3881
) },
7120 { PREFIX_TABLE (PREFIX_0F3882
) },
7199 { PREFIX_TABLE (PREFIX_0F38C8
) },
7200 { PREFIX_TABLE (PREFIX_0F38C9
) },
7201 { PREFIX_TABLE (PREFIX_0F38CA
) },
7202 { PREFIX_TABLE (PREFIX_0F38CB
) },
7203 { PREFIX_TABLE (PREFIX_0F38CC
) },
7204 { PREFIX_TABLE (PREFIX_0F38CD
) },
7206 { PREFIX_TABLE (PREFIX_0F38CF
) },
7220 { PREFIX_TABLE (PREFIX_0F38DB
) },
7221 { PREFIX_TABLE (PREFIX_0F38DC
) },
7222 { PREFIX_TABLE (PREFIX_0F38DD
) },
7223 { PREFIX_TABLE (PREFIX_0F38DE
) },
7224 { PREFIX_TABLE (PREFIX_0F38DF
) },
7244 { PREFIX_TABLE (PREFIX_0F38F0
) },
7245 { PREFIX_TABLE (PREFIX_0F38F1
) },
7249 { PREFIX_TABLE (PREFIX_0F38F5
) },
7250 { PREFIX_TABLE (PREFIX_0F38F6
) },
7253 { PREFIX_TABLE (PREFIX_0F38F8
) },
7254 { PREFIX_TABLE (PREFIX_0F38F9
) },
7262 /* THREE_BYTE_0F3A */
7274 { PREFIX_TABLE (PREFIX_0F3A08
) },
7275 { PREFIX_TABLE (PREFIX_0F3A09
) },
7276 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7277 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7278 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7279 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7281 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7287 { PREFIX_TABLE (PREFIX_0F3A14
) },
7288 { PREFIX_TABLE (PREFIX_0F3A15
) },
7289 { PREFIX_TABLE (PREFIX_0F3A16
) },
7290 { PREFIX_TABLE (PREFIX_0F3A17
) },
7301 { PREFIX_TABLE (PREFIX_0F3A20
) },
7302 { PREFIX_TABLE (PREFIX_0F3A21
) },
7303 { PREFIX_TABLE (PREFIX_0F3A22
) },
7337 { PREFIX_TABLE (PREFIX_0F3A40
) },
7338 { PREFIX_TABLE (PREFIX_0F3A41
) },
7339 { PREFIX_TABLE (PREFIX_0F3A42
) },
7341 { PREFIX_TABLE (PREFIX_0F3A44
) },
7373 { PREFIX_TABLE (PREFIX_0F3A60
) },
7374 { PREFIX_TABLE (PREFIX_0F3A61
) },
7375 { PREFIX_TABLE (PREFIX_0F3A62
) },
7376 { PREFIX_TABLE (PREFIX_0F3A63
) },
7494 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7496 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7497 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7515 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7555 static const struct dis386 xop_table
[][256] = {
7708 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7709 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7710 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7718 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7719 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7726 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7727 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7728 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7736 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7737 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7741 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7742 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7745 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7763 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7775 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7776 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7777 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7778 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7851 { REG_TABLE (REG_XOP_TBM_01
) },
7852 { REG_TABLE (REG_XOP_TBM_02
) },
7870 { REG_TABLE (REG_XOP_LWPCB
) },
7994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7996 { "vfrczss", { XM
, EXd
}, 0 },
7997 { "vfrczsd", { XM
, EXq
}, 0 },
8012 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8013 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8014 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8015 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8022 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8023 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8024 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8067 { "vphaddbw", { XM
, EXxmm
}, 0 },
8068 { "vphaddbd", { XM
, EXxmm
}, 0 },
8069 { "vphaddbq", { XM
, EXxmm
}, 0 },
8072 { "vphaddwd", { XM
, EXxmm
}, 0 },
8073 { "vphaddwq", { XM
, EXxmm
}, 0 },
8078 { "vphadddq", { XM
, EXxmm
}, 0 },
8085 { "vphaddubw", { XM
, EXxmm
}, 0 },
8086 { "vphaddubd", { XM
, EXxmm
}, 0 },
8087 { "vphaddubq", { XM
, EXxmm
}, 0 },
8090 { "vphadduwd", { XM
, EXxmm
}, 0 },
8091 { "vphadduwq", { XM
, EXxmm
}, 0 },
8096 { "vphaddudq", { XM
, EXxmm
}, 0 },
8103 { "vphsubbw", { XM
, EXxmm
}, 0 },
8104 { "vphsubwd", { XM
, EXxmm
}, 0 },
8105 { "vphsubdq", { XM
, EXxmm
}, 0 },
8159 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8161 { REG_TABLE (REG_XOP_LWP
) },
8431 static const struct dis386 vex_table
[][256] = {
8453 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8456 { MOD_TABLE (MOD_VEX_0F13
) },
8457 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8458 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8459 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8460 { MOD_TABLE (MOD_VEX_0F17
) },
8480 { "vmovapX", { XM
, EXx
}, 0 },
8481 { "vmovapX", { EXxS
, XM
}, 0 },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8483 { MOD_TABLE (MOD_VEX_0F2B
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8525 { MOD_TABLE (MOD_VEX_0F50
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8529 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8530 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8531 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8532 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8534 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8562 { REG_TABLE (REG_VEX_0F71
) },
8563 { REG_TABLE (REG_VEX_0F72
) },
8564 { REG_TABLE (REG_VEX_0F73
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8630 { REG_TABLE (REG_VEX_0FAE
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8657 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8999 { REG_TABLE (REG_VEX_0F38F3
) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9248 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9249 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9307 #include "i386-dis-evex.h"
9309 static const struct dis386 vex_len_table
[][2] = {
9310 /* VEX_LEN_0F12_P_0_M_0 */
9312 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9315 /* VEX_LEN_0F12_P_0_M_1 */
9317 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9320 /* VEX_LEN_0F12_P_2 */
9322 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9325 /* VEX_LEN_0F13_M_0 */
9327 { "vmovlpX", { EXq
, XM
}, 0 },
9330 /* VEX_LEN_0F16_P_0_M_0 */
9332 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9335 /* VEX_LEN_0F16_P_0_M_1 */
9337 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9340 /* VEX_LEN_0F16_P_2 */
9342 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9345 /* VEX_LEN_0F17_M_0 */
9347 { "vmovhpX", { EXq
, XM
}, 0 },
9350 /* VEX_LEN_0F41_P_0 */
9353 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9355 /* VEX_LEN_0F41_P_2 */
9358 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9360 /* VEX_LEN_0F42_P_0 */
9363 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9365 /* VEX_LEN_0F42_P_2 */
9368 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9370 /* VEX_LEN_0F44_P_0 */
9372 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9374 /* VEX_LEN_0F44_P_2 */
9376 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9378 /* VEX_LEN_0F45_P_0 */
9381 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9383 /* VEX_LEN_0F45_P_2 */
9386 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9388 /* VEX_LEN_0F46_P_0 */
9391 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9393 /* VEX_LEN_0F46_P_2 */
9396 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9398 /* VEX_LEN_0F47_P_0 */
9401 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9403 /* VEX_LEN_0F47_P_2 */
9406 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9408 /* VEX_LEN_0F4A_P_0 */
9411 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9413 /* VEX_LEN_0F4A_P_2 */
9416 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9418 /* VEX_LEN_0F4B_P_0 */
9421 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9423 /* VEX_LEN_0F4B_P_2 */
9426 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9429 /* VEX_LEN_0F6E_P_2 */
9431 { "vmovK", { XMScalar
, Edq
}, 0 },
9434 /* VEX_LEN_0F77_P_1 */
9436 { "vzeroupper", { XX
}, 0 },
9437 { "vzeroall", { XX
}, 0 },
9440 /* VEX_LEN_0F7E_P_1 */
9442 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9445 /* VEX_LEN_0F7E_P_2 */
9447 { "vmovK", { Edq
, XMScalar
}, 0 },
9450 /* VEX_LEN_0F90_P_0 */
9452 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9455 /* VEX_LEN_0F90_P_2 */
9457 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9460 /* VEX_LEN_0F91_P_0 */
9462 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9465 /* VEX_LEN_0F91_P_2 */
9467 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9470 /* VEX_LEN_0F92_P_0 */
9472 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9475 /* VEX_LEN_0F92_P_2 */
9477 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9480 /* VEX_LEN_0F92_P_3 */
9482 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9485 /* VEX_LEN_0F93_P_0 */
9487 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9490 /* VEX_LEN_0F93_P_2 */
9492 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9495 /* VEX_LEN_0F93_P_3 */
9497 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9500 /* VEX_LEN_0F98_P_0 */
9502 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9505 /* VEX_LEN_0F98_P_2 */
9507 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9510 /* VEX_LEN_0F99_P_0 */
9512 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9515 /* VEX_LEN_0F99_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9520 /* VEX_LEN_0FAE_R_2_M_0 */
9522 { "vldmxcsr", { Md
}, 0 },
9525 /* VEX_LEN_0FAE_R_3_M_0 */
9527 { "vstmxcsr", { Md
}, 0 },
9530 /* VEX_LEN_0FC4_P_2 */
9532 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9535 /* VEX_LEN_0FC5_P_2 */
9537 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9540 /* VEX_LEN_0FD6_P_2 */
9542 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9545 /* VEX_LEN_0FF7_P_2 */
9547 { "vmaskmovdqu", { XM
, XS
}, 0 },
9550 /* VEX_LEN_0F3816_P_2 */
9553 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9556 /* VEX_LEN_0F3819_P_2 */
9559 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9562 /* VEX_LEN_0F381A_P_2_M_0 */
9565 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9568 /* VEX_LEN_0F3836_P_2 */
9571 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9574 /* VEX_LEN_0F3841_P_2 */
9576 { "vphminposuw", { XM
, EXx
}, 0 },
9579 /* VEX_LEN_0F385A_P_2_M_0 */
9582 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9585 /* VEX_LEN_0F38DB_P_2 */
9587 { "vaesimc", { XM
, EXx
}, 0 },
9590 /* VEX_LEN_0F38F2_P_0 */
9592 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9595 /* VEX_LEN_0F38F3_R_1_P_0 */
9597 { "blsrS", { VexGdq
, Edq
}, 0 },
9600 /* VEX_LEN_0F38F3_R_2_P_0 */
9602 { "blsmskS", { VexGdq
, Edq
}, 0 },
9605 /* VEX_LEN_0F38F3_R_3_P_0 */
9607 { "blsiS", { VexGdq
, Edq
}, 0 },
9610 /* VEX_LEN_0F38F5_P_0 */
9612 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9615 /* VEX_LEN_0F38F5_P_1 */
9617 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9620 /* VEX_LEN_0F38F5_P_3 */
9622 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9625 /* VEX_LEN_0F38F6_P_3 */
9627 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9630 /* VEX_LEN_0F38F7_P_0 */
9632 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9635 /* VEX_LEN_0F38F7_P_1 */
9637 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9640 /* VEX_LEN_0F38F7_P_2 */
9642 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9645 /* VEX_LEN_0F38F7_P_3 */
9647 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9650 /* VEX_LEN_0F3A00_P_2 */
9653 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9656 /* VEX_LEN_0F3A01_P_2 */
9659 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9662 /* VEX_LEN_0F3A06_P_2 */
9665 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9668 /* VEX_LEN_0F3A14_P_2 */
9670 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9673 /* VEX_LEN_0F3A15_P_2 */
9675 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9678 /* VEX_LEN_0F3A16_P_2 */
9680 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9683 /* VEX_LEN_0F3A17_P_2 */
9685 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9688 /* VEX_LEN_0F3A18_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9694 /* VEX_LEN_0F3A19_P_2 */
9697 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9700 /* VEX_LEN_0F3A20_P_2 */
9702 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9705 /* VEX_LEN_0F3A21_P_2 */
9707 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9710 /* VEX_LEN_0F3A22_P_2 */
9712 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9715 /* VEX_LEN_0F3A30_P_2 */
9717 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9720 /* VEX_LEN_0F3A31_P_2 */
9722 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9725 /* VEX_LEN_0F3A32_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9730 /* VEX_LEN_0F3A33_P_2 */
9732 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9735 /* VEX_LEN_0F3A38_P_2 */
9738 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9741 /* VEX_LEN_0F3A39_P_2 */
9744 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9747 /* VEX_LEN_0F3A41_P_2 */
9749 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9752 /* VEX_LEN_0F3A46_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9758 /* VEX_LEN_0F3A60_P_2 */
9760 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9763 /* VEX_LEN_0F3A61_P_2 */
9765 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9768 /* VEX_LEN_0F3A62_P_2 */
9770 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9773 /* VEX_LEN_0F3A63_P_2 */
9775 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9778 /* VEX_LEN_0F3A6A_P_2 */
9780 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9783 /* VEX_LEN_0F3A6B_P_2 */
9785 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9788 /* VEX_LEN_0F3A6E_P_2 */
9790 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9793 /* VEX_LEN_0F3A6F_P_2 */
9795 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9798 /* VEX_LEN_0F3A7A_P_2 */
9800 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9803 /* VEX_LEN_0F3A7B_P_2 */
9805 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9808 /* VEX_LEN_0F3A7E_P_2 */
9810 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9813 /* VEX_LEN_0F3A7F_P_2 */
9815 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9818 /* VEX_LEN_0F3ADF_P_2 */
9820 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9823 /* VEX_LEN_0F3AF0_P_3 */
9825 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9828 /* VEX_LEN_0FXOP_08_CC */
9830 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9833 /* VEX_LEN_0FXOP_08_CD */
9835 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9838 /* VEX_LEN_0FXOP_08_CE */
9840 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9843 /* VEX_LEN_0FXOP_08_CF */
9845 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9848 /* VEX_LEN_0FXOP_08_EC */
9850 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9853 /* VEX_LEN_0FXOP_08_ED */
9855 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9858 /* VEX_LEN_0FXOP_08_EE */
9860 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9863 /* VEX_LEN_0FXOP_08_EF */
9865 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9868 /* VEX_LEN_0FXOP_09_80 */
9870 { "vfrczps", { XM
, EXxmm
}, 0 },
9871 { "vfrczps", { XM
, EXymmq
}, 0 },
9874 /* VEX_LEN_0FXOP_09_81 */
9876 { "vfrczpd", { XM
, EXxmm
}, 0 },
9877 { "vfrczpd", { XM
, EXymmq
}, 0 },
9881 #include "i386-dis-evex-len.h"
9883 static const struct dis386 vex_w_table
[][2] = {
9885 /* VEX_W_0F41_P_0_LEN_1 */
9886 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9887 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9890 /* VEX_W_0F41_P_2_LEN_1 */
9891 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9892 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9895 /* VEX_W_0F42_P_0_LEN_1 */
9896 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9897 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9900 /* VEX_W_0F42_P_2_LEN_1 */
9901 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9902 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9905 /* VEX_W_0F44_P_0_LEN_0 */
9906 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9907 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9910 /* VEX_W_0F44_P_2_LEN_0 */
9911 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9912 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9915 /* VEX_W_0F45_P_0_LEN_1 */
9916 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9917 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9920 /* VEX_W_0F45_P_2_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9925 /* VEX_W_0F46_P_0_LEN_1 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9930 /* VEX_W_0F46_P_2_LEN_1 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9935 /* VEX_W_0F47_P_0_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9940 /* VEX_W_0F47_P_2_LEN_1 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9945 /* VEX_W_0F4A_P_0_LEN_1 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9950 /* VEX_W_0F4A_P_2_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9955 /* VEX_W_0F4B_P_0_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9957 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9960 /* VEX_W_0F4B_P_2_LEN_1 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9964 /* VEX_W_0F90_P_0_LEN_0 */
9965 { "kmovw", { MaskG
, MaskE
}, 0 },
9966 { "kmovq", { MaskG
, MaskE
}, 0 },
9969 /* VEX_W_0F90_P_2_LEN_0 */
9970 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9971 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9974 /* VEX_W_0F91_P_0_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9976 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9979 /* VEX_W_0F91_P_2_LEN_0 */
9980 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9981 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9984 /* VEX_W_0F92_P_0_LEN_0 */
9985 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9988 /* VEX_W_0F92_P_2_LEN_0 */
9989 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9992 /* VEX_W_0F93_P_0_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9996 /* VEX_W_0F93_P_2_LEN_0 */
9997 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10000 /* VEX_W_0F98_P_0_LEN_0 */
10001 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10002 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10005 /* VEX_W_0F98_P_2_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10007 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10010 /* VEX_W_0F99_P_0_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10015 /* VEX_W_0F99_P_2_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10017 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10020 /* VEX_W_0F380C_P_2 */
10021 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10024 /* VEX_W_0F380D_P_2 */
10025 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10028 /* VEX_W_0F380E_P_2 */
10029 { "vtestps", { XM
, EXx
}, 0 },
10032 /* VEX_W_0F380F_P_2 */
10033 { "vtestpd", { XM
, EXx
}, 0 },
10036 /* VEX_W_0F3816_P_2 */
10037 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10040 /* VEX_W_0F3818_P_2 */
10041 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10044 /* VEX_W_0F3819_P_2 */
10045 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10048 /* VEX_W_0F381A_P_2_M_0 */
10049 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10052 /* VEX_W_0F382C_P_2_M_0 */
10053 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10056 /* VEX_W_0F382D_P_2_M_0 */
10057 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10060 /* VEX_W_0F382E_P_2_M_0 */
10061 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10064 /* VEX_W_0F382F_P_2_M_0 */
10065 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10068 /* VEX_W_0F3836_P_2 */
10069 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10072 /* VEX_W_0F3846_P_2 */
10073 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10076 /* VEX_W_0F3858_P_2 */
10077 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10080 /* VEX_W_0F3859_P_2 */
10081 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10084 /* VEX_W_0F385A_P_2_M_0 */
10085 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10088 /* VEX_W_0F3878_P_2 */
10089 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10092 /* VEX_W_0F3879_P_2 */
10093 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10096 /* VEX_W_0F38CF_P_2 */
10097 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10100 /* VEX_W_0F3A00_P_2 */
10102 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10105 /* VEX_W_0F3A01_P_2 */
10107 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10110 /* VEX_W_0F3A02_P_2 */
10111 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10114 /* VEX_W_0F3A04_P_2 */
10115 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10118 /* VEX_W_0F3A05_P_2 */
10119 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10122 /* VEX_W_0F3A06_P_2 */
10123 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10126 /* VEX_W_0F3A18_P_2 */
10127 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10130 /* VEX_W_0F3A19_P_2 */
10131 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10134 /* VEX_W_0F3A30_P_2_LEN_0 */
10135 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10136 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10139 /* VEX_W_0F3A31_P_2_LEN_0 */
10140 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10141 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10144 /* VEX_W_0F3A32_P_2_LEN_0 */
10145 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10146 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10149 /* VEX_W_0F3A33_P_2_LEN_0 */
10150 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10151 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10154 /* VEX_W_0F3A38_P_2 */
10155 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10158 /* VEX_W_0F3A39_P_2 */
10159 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10162 /* VEX_W_0F3A46_P_2 */
10163 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10166 /* VEX_W_0F3A48_P_2 */
10167 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10168 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10171 /* VEX_W_0F3A49_P_2 */
10172 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10173 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10176 /* VEX_W_0F3A4A_P_2 */
10177 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10180 /* VEX_W_0F3A4B_P_2 */
10181 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10184 /* VEX_W_0F3A4C_P_2 */
10185 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10188 /* VEX_W_0F3ACE_P_2 */
10190 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10193 /* VEX_W_0F3ACF_P_2 */
10195 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10198 #include "i386-dis-evex-w.h"
10201 static const struct dis386 mod_table
[][2] = {
10204 { "leaS", { Gv
, M
}, 0 },
10209 { RM_TABLE (RM_C6_REG_7
) },
10214 { RM_TABLE (RM_C7_REG_7
) },
10218 { "Jcall^", { indirEp
}, 0 },
10222 { "Jjmp^", { indirEp
}, 0 },
10225 /* MOD_0F01_REG_0 */
10226 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10227 { RM_TABLE (RM_0F01_REG_0
) },
10230 /* MOD_0F01_REG_1 */
10231 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10232 { RM_TABLE (RM_0F01_REG_1
) },
10235 /* MOD_0F01_REG_2 */
10236 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10237 { RM_TABLE (RM_0F01_REG_2
) },
10240 /* MOD_0F01_REG_3 */
10241 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10242 { RM_TABLE (RM_0F01_REG_3
) },
10245 /* MOD_0F01_REG_5 */
10246 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10247 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10250 /* MOD_0F01_REG_7 */
10251 { "invlpg", { Mb
}, 0 },
10252 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10255 /* MOD_0F12_PREFIX_0 */
10256 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10257 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10261 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10264 /* MOD_0F16_PREFIX_0 */
10265 { "movhps", { XM
, EXq
}, 0 },
10266 { "movlhps", { XM
, EXq
}, 0 },
10270 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10273 /* MOD_0F18_REG_0 */
10274 { "prefetchnta", { Mb
}, 0 },
10277 /* MOD_0F18_REG_1 */
10278 { "prefetcht0", { Mb
}, 0 },
10281 /* MOD_0F18_REG_2 */
10282 { "prefetcht1", { Mb
}, 0 },
10285 /* MOD_0F18_REG_3 */
10286 { "prefetcht2", { Mb
}, 0 },
10289 /* MOD_0F18_REG_4 */
10290 { "nop/reserved", { Mb
}, 0 },
10293 /* MOD_0F18_REG_5 */
10294 { "nop/reserved", { Mb
}, 0 },
10297 /* MOD_0F18_REG_6 */
10298 { "nop/reserved", { Mb
}, 0 },
10301 /* MOD_0F18_REG_7 */
10302 { "nop/reserved", { Mb
}, 0 },
10305 /* MOD_0F1A_PREFIX_0 */
10306 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10307 { "nopQ", { Ev
}, 0 },
10310 /* MOD_0F1B_PREFIX_0 */
10311 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10312 { "nopQ", { Ev
}, 0 },
10315 /* MOD_0F1B_PREFIX_1 */
10316 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10317 { "nopQ", { Ev
}, 0 },
10320 /* MOD_0F1C_PREFIX_0 */
10321 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10322 { "nopQ", { Ev
}, 0 },
10325 /* MOD_0F1E_PREFIX_1 */
10326 { "nopQ", { Ev
}, 0 },
10327 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10332 { "movL", { Rd
, Td
}, 0 },
10337 { "movL", { Td
, Rd
}, 0 },
10340 /* MOD_0F2B_PREFIX_0 */
10341 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10344 /* MOD_0F2B_PREFIX_1 */
10345 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10348 /* MOD_0F2B_PREFIX_2 */
10349 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10352 /* MOD_0F2B_PREFIX_3 */
10353 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10358 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10361 /* MOD_0F71_REG_2 */
10363 { "psrlw", { MS
, Ib
}, 0 },
10366 /* MOD_0F71_REG_4 */
10368 { "psraw", { MS
, Ib
}, 0 },
10371 /* MOD_0F71_REG_6 */
10373 { "psllw", { MS
, Ib
}, 0 },
10376 /* MOD_0F72_REG_2 */
10378 { "psrld", { MS
, Ib
}, 0 },
10381 /* MOD_0F72_REG_4 */
10383 { "psrad", { MS
, Ib
}, 0 },
10386 /* MOD_0F72_REG_6 */
10388 { "pslld", { MS
, Ib
}, 0 },
10391 /* MOD_0F73_REG_2 */
10393 { "psrlq", { MS
, Ib
}, 0 },
10396 /* MOD_0F73_REG_3 */
10398 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10401 /* MOD_0F73_REG_6 */
10403 { "psllq", { MS
, Ib
}, 0 },
10406 /* MOD_0F73_REG_7 */
10408 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10411 /* MOD_0FAE_REG_0 */
10412 { "fxsave", { FXSAVE
}, 0 },
10413 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10416 /* MOD_0FAE_REG_1 */
10417 { "fxrstor", { FXSAVE
}, 0 },
10418 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10421 /* MOD_0FAE_REG_2 */
10422 { "ldmxcsr", { Md
}, 0 },
10423 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10426 /* MOD_0FAE_REG_3 */
10427 { "stmxcsr", { Md
}, 0 },
10428 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10431 /* MOD_0FAE_REG_4 */
10432 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10433 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10436 /* MOD_0FAE_REG_5 */
10437 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10438 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10441 /* MOD_0FAE_REG_6 */
10442 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10443 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10446 /* MOD_0FAE_REG_7 */
10447 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10448 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10452 { "lssS", { Gv
, Mp
}, 0 },
10456 { "lfsS", { Gv
, Mp
}, 0 },
10460 { "lgsS", { Gv
, Mp
}, 0 },
10464 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10467 /* MOD_0FC7_REG_3 */
10468 { "xrstors", { FXSAVE
}, 0 },
10471 /* MOD_0FC7_REG_4 */
10472 { "xsavec", { FXSAVE
}, 0 },
10475 /* MOD_0FC7_REG_5 */
10476 { "xsaves", { FXSAVE
}, 0 },
10479 /* MOD_0FC7_REG_6 */
10480 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10481 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10484 /* MOD_0FC7_REG_7 */
10485 { "vmptrst", { Mq
}, 0 },
10486 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10491 { "pmovmskb", { Gdq
, MS
}, 0 },
10494 /* MOD_0FE7_PREFIX_2 */
10495 { "movntdq", { Mx
, XM
}, 0 },
10498 /* MOD_0FF0_PREFIX_3 */
10499 { "lddqu", { XM
, M
}, 0 },
10502 /* MOD_0F382A_PREFIX_2 */
10503 { "movntdqa", { XM
, Mx
}, 0 },
10506 /* MOD_0F38F5_PREFIX_2 */
10507 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10510 /* MOD_0F38F6_PREFIX_0 */
10511 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10514 /* MOD_0F38F8_PREFIX_1 */
10515 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10518 /* MOD_0F38F8_PREFIX_2 */
10519 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10522 /* MOD_0F38F8_PREFIX_3 */
10523 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10526 /* MOD_0F38F9_PREFIX_0 */
10527 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10531 { "bound{S|}", { Gv
, Ma
}, 0 },
10532 { EVEX_TABLE (EVEX_0F
) },
10536 { "lesS", { Gv
, Mp
}, 0 },
10537 { VEX_C4_TABLE (VEX_0F
) },
10541 { "ldsS", { Gv
, Mp
}, 0 },
10542 { VEX_C5_TABLE (VEX_0F
) },
10545 /* MOD_VEX_0F12_PREFIX_0 */
10546 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10547 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10551 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10554 /* MOD_VEX_0F16_PREFIX_0 */
10555 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10556 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10560 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10564 { "vmovntpX", { Mx
, XM
}, 0 },
10567 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10569 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10572 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10574 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10577 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10579 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10582 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10584 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10587 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10589 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10592 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10594 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10597 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10599 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10602 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10604 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10607 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10609 { "knotw", { MaskG
, MaskR
}, 0 },
10612 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10614 { "knotq", { MaskG
, MaskR
}, 0 },
10617 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10619 { "knotb", { MaskG
, MaskR
}, 0 },
10622 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10624 { "knotd", { MaskG
, MaskR
}, 0 },
10627 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10629 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10632 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10634 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10637 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10639 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10642 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10644 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10647 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10649 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10652 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10654 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10659 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10664 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10669 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10674 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10679 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10684 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10689 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10694 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10697 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10699 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10702 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10704 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10707 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10709 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10712 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10714 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10717 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10719 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10724 { "vmovmskpX", { Gdq
, XS
}, 0 },
10727 /* MOD_VEX_0F71_REG_2 */
10729 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10732 /* MOD_VEX_0F71_REG_4 */
10734 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10737 /* MOD_VEX_0F71_REG_6 */
10739 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10742 /* MOD_VEX_0F72_REG_2 */
10744 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10747 /* MOD_VEX_0F72_REG_4 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10752 /* MOD_VEX_0F72_REG_6 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10757 /* MOD_VEX_0F73_REG_2 */
10759 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10762 /* MOD_VEX_0F73_REG_3 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10767 /* MOD_VEX_0F73_REG_6 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10772 /* MOD_VEX_0F73_REG_7 */
10774 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10777 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778 { "kmovw", { Ew
, MaskG
}, 0 },
10782 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10783 { "kmovq", { Eq
, MaskG
}, 0 },
10787 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788 { "kmovb", { Eb
, MaskG
}, 0 },
10792 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10793 { "kmovd", { Ed
, MaskG
}, 0 },
10797 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10799 { "kmovw", { MaskG
, Rdq
}, 0 },
10802 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10804 { "kmovb", { MaskG
, Rdq
}, 0 },
10807 /* MOD_VEX_0F92_P_3_LEN_0 */
10809 { "kmovK", { MaskG
, Rdq
}, 0 },
10812 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10814 { "kmovw", { Gdq
, MaskR
}, 0 },
10817 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10819 { "kmovb", { Gdq
, MaskR
}, 0 },
10822 /* MOD_VEX_0F93_P_3_LEN_0 */
10824 { "kmovK", { Gdq
, MaskR
}, 0 },
10827 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10829 { "kortestw", { MaskG
, MaskR
}, 0 },
10832 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10834 { "kortestq", { MaskG
, MaskR
}, 0 },
10837 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10839 { "kortestb", { MaskG
, MaskR
}, 0 },
10842 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10844 { "kortestd", { MaskG
, MaskR
}, 0 },
10847 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10849 { "ktestw", { MaskG
, MaskR
}, 0 },
10852 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10854 { "ktestq", { MaskG
, MaskR
}, 0 },
10857 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10859 { "ktestb", { MaskG
, MaskR
}, 0 },
10862 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10864 { "ktestd", { MaskG
, MaskR
}, 0 },
10867 /* MOD_VEX_0FAE_REG_2 */
10868 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10871 /* MOD_VEX_0FAE_REG_3 */
10872 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10875 /* MOD_VEX_0FD7_PREFIX_2 */
10877 { "vpmovmskb", { Gdq
, XS
}, 0 },
10880 /* MOD_VEX_0FE7_PREFIX_2 */
10881 { "vmovntdq", { Mx
, XM
}, 0 },
10884 /* MOD_VEX_0FF0_PREFIX_3 */
10885 { "vlddqu", { XM
, M
}, 0 },
10888 /* MOD_VEX_0F381A_PREFIX_2 */
10889 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10892 /* MOD_VEX_0F382A_PREFIX_2 */
10893 { "vmovntdqa", { XM
, Mx
}, 0 },
10896 /* MOD_VEX_0F382C_PREFIX_2 */
10897 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10900 /* MOD_VEX_0F382D_PREFIX_2 */
10901 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10904 /* MOD_VEX_0F382E_PREFIX_2 */
10905 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10908 /* MOD_VEX_0F382F_PREFIX_2 */
10909 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10912 /* MOD_VEX_0F385A_PREFIX_2 */
10913 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10916 /* MOD_VEX_0F388C_PREFIX_2 */
10917 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10920 /* MOD_VEX_0F388E_PREFIX_2 */
10921 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10924 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10926 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10929 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10931 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10934 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10936 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10939 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10941 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10944 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10946 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10949 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10951 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10954 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10956 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10959 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10961 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10964 #include "i386-dis-evex-mod.h"
10967 static const struct dis386 rm_table
[][8] = {
10970 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10974 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10977 /* RM_0F01_REG_0 */
10978 { "enclv", { Skip_MODRM
}, 0 },
10979 { "vmcall", { Skip_MODRM
}, 0 },
10980 { "vmlaunch", { Skip_MODRM
}, 0 },
10981 { "vmresume", { Skip_MODRM
}, 0 },
10982 { "vmxoff", { Skip_MODRM
}, 0 },
10983 { "pconfig", { Skip_MODRM
}, 0 },
10986 /* RM_0F01_REG_1 */
10987 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10988 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10989 { "clac", { Skip_MODRM
}, 0 },
10990 { "stac", { Skip_MODRM
}, 0 },
10994 { "encls", { Skip_MODRM
}, 0 },
10997 /* RM_0F01_REG_2 */
10998 { "xgetbv", { Skip_MODRM
}, 0 },
10999 { "xsetbv", { Skip_MODRM
}, 0 },
11002 { "vmfunc", { Skip_MODRM
}, 0 },
11003 { "xend", { Skip_MODRM
}, 0 },
11004 { "xtest", { Skip_MODRM
}, 0 },
11005 { "enclu", { Skip_MODRM
}, 0 },
11008 /* RM_0F01_REG_3 */
11009 { "vmrun", { Skip_MODRM
}, 0 },
11010 { "vmmcall", { Skip_MODRM
}, 0 },
11011 { "vmload", { Skip_MODRM
}, 0 },
11012 { "vmsave", { Skip_MODRM
}, 0 },
11013 { "stgi", { Skip_MODRM
}, 0 },
11014 { "clgi", { Skip_MODRM
}, 0 },
11015 { "skinit", { Skip_MODRM
}, 0 },
11016 { "invlpga", { Skip_MODRM
}, 0 },
11019 /* RM_0F01_REG_5_MOD_3 */
11020 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11022 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11026 { "rdpkru", { Skip_MODRM
}, 0 },
11027 { "wrpkru", { Skip_MODRM
}, 0 },
11030 /* RM_0F01_REG_7_MOD_3 */
11031 { "swapgs", { Skip_MODRM
}, 0 },
11032 { "rdtscp", { Skip_MODRM
}, 0 },
11033 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11034 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11035 { "clzero", { Skip_MODRM
}, 0 },
11036 { "rdpru", { Skip_MODRM
}, 0 },
11039 /* RM_0F1E_P_1_MOD_3_REG_7 */
11040 { "nopQ", { Ev
}, 0 },
11041 { "nopQ", { Ev
}, 0 },
11042 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11043 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11044 { "nopQ", { Ev
}, 0 },
11045 { "nopQ", { Ev
}, 0 },
11046 { "nopQ", { Ev
}, 0 },
11047 { "nopQ", { Ev
}, 0 },
11050 /* RM_0FAE_REG_6_MOD_3 */
11051 { "mfence", { Skip_MODRM
}, 0 },
11054 /* RM_0FAE_REG_7_MOD_3 */
11055 { "sfence", { Skip_MODRM
}, 0 },
11060 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11062 /* We use the high bit to indicate different name for the same
11064 #define REP_PREFIX (0xf3 | 0x100)
11065 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11066 #define XRELEASE_PREFIX (0xf3 | 0x400)
11067 #define BND_PREFIX (0xf2 | 0x400)
11068 #define NOTRACK_PREFIX (0x3e | 0x100)
11073 int newrex
, i
, length
;
11079 last_lock_prefix
= -1;
11080 last_repz_prefix
= -1;
11081 last_repnz_prefix
= -1;
11082 last_data_prefix
= -1;
11083 last_addr_prefix
= -1;
11084 last_rex_prefix
= -1;
11085 last_seg_prefix
= -1;
11087 active_seg_prefix
= 0;
11088 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11089 all_prefixes
[i
] = 0;
11092 /* The maximum instruction length is 15bytes. */
11093 while (length
< MAX_CODE_LENGTH
- 1)
11095 FETCH_DATA (the_info
, codep
+ 1);
11099 /* REX prefixes family. */
11116 if (address_mode
== mode_64bit
)
11120 last_rex_prefix
= i
;
11123 prefixes
|= PREFIX_REPZ
;
11124 last_repz_prefix
= i
;
11127 prefixes
|= PREFIX_REPNZ
;
11128 last_repnz_prefix
= i
;
11131 prefixes
|= PREFIX_LOCK
;
11132 last_lock_prefix
= i
;
11135 prefixes
|= PREFIX_CS
;
11136 last_seg_prefix
= i
;
11137 active_seg_prefix
= PREFIX_CS
;
11140 prefixes
|= PREFIX_SS
;
11141 last_seg_prefix
= i
;
11142 active_seg_prefix
= PREFIX_SS
;
11145 prefixes
|= PREFIX_DS
;
11146 last_seg_prefix
= i
;
11147 active_seg_prefix
= PREFIX_DS
;
11150 prefixes
|= PREFIX_ES
;
11151 last_seg_prefix
= i
;
11152 active_seg_prefix
= PREFIX_ES
;
11155 prefixes
|= PREFIX_FS
;
11156 last_seg_prefix
= i
;
11157 active_seg_prefix
= PREFIX_FS
;
11160 prefixes
|= PREFIX_GS
;
11161 last_seg_prefix
= i
;
11162 active_seg_prefix
= PREFIX_GS
;
11165 prefixes
|= PREFIX_DATA
;
11166 last_data_prefix
= i
;
11169 prefixes
|= PREFIX_ADDR
;
11170 last_addr_prefix
= i
;
11173 /* fwait is really an instruction. If there are prefixes
11174 before the fwait, they belong to the fwait, *not* to the
11175 following instruction. */
11177 if (prefixes
|| rex
)
11179 prefixes
|= PREFIX_FWAIT
;
11181 /* This ensures that the previous REX prefixes are noticed
11182 as unused prefixes, as in the return case below. */
11186 prefixes
= PREFIX_FWAIT
;
11191 /* Rex is ignored when followed by another prefix. */
11197 if (*codep
!= FWAIT_OPCODE
)
11198 all_prefixes
[i
++] = *codep
;
11206 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11209 static const char *
11210 prefix_name (int pref
, int sizeflag
)
11212 static const char *rexes
[16] =
11215 "rex.B", /* 0x41 */
11216 "rex.X", /* 0x42 */
11217 "rex.XB", /* 0x43 */
11218 "rex.R", /* 0x44 */
11219 "rex.RB", /* 0x45 */
11220 "rex.RX", /* 0x46 */
11221 "rex.RXB", /* 0x47 */
11222 "rex.W", /* 0x48 */
11223 "rex.WB", /* 0x49 */
11224 "rex.WX", /* 0x4a */
11225 "rex.WXB", /* 0x4b */
11226 "rex.WR", /* 0x4c */
11227 "rex.WRB", /* 0x4d */
11228 "rex.WRX", /* 0x4e */
11229 "rex.WRXB", /* 0x4f */
11234 /* REX prefixes family. */
11251 return rexes
[pref
- 0x40];
11271 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11273 if (address_mode
== mode_64bit
)
11274 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11276 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11281 case XACQUIRE_PREFIX
:
11283 case XRELEASE_PREFIX
:
11287 case NOTRACK_PREFIX
:
11294 static char op_out
[MAX_OPERANDS
][100];
11295 static int op_ad
, op_index
[MAX_OPERANDS
];
11296 static int two_source_ops
;
11297 static bfd_vma op_address
[MAX_OPERANDS
];
11298 static bfd_vma op_riprel
[MAX_OPERANDS
];
11299 static bfd_vma start_pc
;
11302 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11303 * (see topic "Redundant prefixes" in the "Differences from 8086"
11304 * section of the "Virtual 8086 Mode" chapter.)
11305 * 'pc' should be the address of this instruction, it will
11306 * be used to print the target address if this is a relative jump or call
11307 * The function returns the length of this instruction in bytes.
11310 static char intel_syntax
;
11311 static char intel_mnemonic
= !SYSV386_COMPAT
;
11312 static char open_char
;
11313 static char close_char
;
11314 static char separator_char
;
11315 static char scale_char
;
11323 static enum x86_64_isa isa64
;
11325 /* Here for backwards compatibility. When gdb stops using
11326 print_insn_i386_att and print_insn_i386_intel these functions can
11327 disappear, and print_insn_i386 be merged into print_insn. */
11329 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11333 return print_insn (pc
, info
);
11337 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11341 return print_insn (pc
, info
);
11345 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11349 return print_insn (pc
, info
);
11353 print_i386_disassembler_options (FILE *stream
)
11355 fprintf (stream
, _("\n\
11356 The following i386/x86-64 specific disassembler options are supported for use\n\
11357 with the -M switch (multiple options should be separated by commas):\n"));
11359 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11360 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11361 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11362 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11363 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11364 fprintf (stream
, _(" att-mnemonic\n"
11365 " Display instruction in AT&T mnemonic\n"));
11366 fprintf (stream
, _(" intel-mnemonic\n"
11367 " Display instruction in Intel mnemonic\n"));
11368 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11369 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11370 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11371 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11372 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11373 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11374 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11375 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11379 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11381 /* Get a pointer to struct dis386 with a valid name. */
11383 static const struct dis386
*
11384 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11386 int vindex
, vex_table_index
;
11388 if (dp
->name
!= NULL
)
11391 switch (dp
->op
[0].bytemode
)
11393 case USE_REG_TABLE
:
11394 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11397 case USE_MOD_TABLE
:
11398 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11399 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11403 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11406 case USE_PREFIX_TABLE
:
11409 /* The prefix in VEX is implicit. */
11410 switch (vex
.prefix
)
11415 case REPE_PREFIX_OPCODE
:
11418 case DATA_PREFIX_OPCODE
:
11421 case REPNE_PREFIX_OPCODE
:
11431 int last_prefix
= -1;
11434 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11435 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11437 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11439 if (last_repz_prefix
> last_repnz_prefix
)
11442 prefix
= PREFIX_REPZ
;
11443 last_prefix
= last_repz_prefix
;
11448 prefix
= PREFIX_REPNZ
;
11449 last_prefix
= last_repnz_prefix
;
11452 /* Check if prefix should be ignored. */
11453 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11454 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11459 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11462 prefix
= PREFIX_DATA
;
11463 last_prefix
= last_data_prefix
;
11468 used_prefixes
|= prefix
;
11469 all_prefixes
[last_prefix
] = 0;
11472 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11475 case USE_X86_64_TABLE
:
11476 vindex
= address_mode
== mode_64bit
? 1 : 0;
11477 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11480 case USE_3BYTE_TABLE
:
11481 FETCH_DATA (info
, codep
+ 2);
11483 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11485 modrm
.mod
= (*codep
>> 6) & 3;
11486 modrm
.reg
= (*codep
>> 3) & 7;
11487 modrm
.rm
= *codep
& 7;
11490 case USE_VEX_LEN_TABLE
:
11494 switch (vex
.length
)
11507 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11510 case USE_EVEX_LEN_TABLE
:
11514 switch (vex
.length
)
11530 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11533 case USE_XOP_8F_TABLE
:
11534 FETCH_DATA (info
, codep
+ 3);
11535 /* All bits in the REX prefix are ignored. */
11537 rex
= ~(*codep
>> 5) & 0x7;
11539 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11540 switch ((*codep
& 0x1f))
11546 vex_table_index
= XOP_08
;
11549 vex_table_index
= XOP_09
;
11552 vex_table_index
= XOP_0A
;
11556 vex
.w
= *codep
& 0x80;
11557 if (vex
.w
&& address_mode
== mode_64bit
)
11560 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11561 if (address_mode
!= mode_64bit
)
11563 /* In 16/32-bit mode REX_B is silently ignored. */
11567 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11568 switch ((*codep
& 0x3))
11573 vex
.prefix
= DATA_PREFIX_OPCODE
;
11576 vex
.prefix
= REPE_PREFIX_OPCODE
;
11579 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11586 dp
= &xop_table
[vex_table_index
][vindex
];
11589 FETCH_DATA (info
, codep
+ 1);
11590 modrm
.mod
= (*codep
>> 6) & 3;
11591 modrm
.reg
= (*codep
>> 3) & 7;
11592 modrm
.rm
= *codep
& 7;
11595 case USE_VEX_C4_TABLE
:
11597 FETCH_DATA (info
, codep
+ 3);
11598 /* All bits in the REX prefix are ignored. */
11600 rex
= ~(*codep
>> 5) & 0x7;
11601 switch ((*codep
& 0x1f))
11607 vex_table_index
= VEX_0F
;
11610 vex_table_index
= VEX_0F38
;
11613 vex_table_index
= VEX_0F3A
;
11617 vex
.w
= *codep
& 0x80;
11618 if (address_mode
== mode_64bit
)
11625 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11626 is ignored, other REX bits are 0 and the highest bit in
11627 VEX.vvvv is also ignored (but we mustn't clear it here). */
11630 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11631 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11632 switch ((*codep
& 0x3))
11637 vex
.prefix
= DATA_PREFIX_OPCODE
;
11640 vex
.prefix
= REPE_PREFIX_OPCODE
;
11643 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11650 dp
= &vex_table
[vex_table_index
][vindex
];
11652 /* There is no MODRM byte for VEX0F 77. */
11653 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11655 FETCH_DATA (info
, codep
+ 1);
11656 modrm
.mod
= (*codep
>> 6) & 3;
11657 modrm
.reg
= (*codep
>> 3) & 7;
11658 modrm
.rm
= *codep
& 7;
11662 case USE_VEX_C5_TABLE
:
11664 FETCH_DATA (info
, codep
+ 2);
11665 /* All bits in the REX prefix are ignored. */
11667 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11669 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11671 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11672 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11673 switch ((*codep
& 0x3))
11678 vex
.prefix
= DATA_PREFIX_OPCODE
;
11681 vex
.prefix
= REPE_PREFIX_OPCODE
;
11684 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11691 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11693 /* There is no MODRM byte for VEX 77. */
11694 if (vindex
!= 0x77)
11696 FETCH_DATA (info
, codep
+ 1);
11697 modrm
.mod
= (*codep
>> 6) & 3;
11698 modrm
.reg
= (*codep
>> 3) & 7;
11699 modrm
.rm
= *codep
& 7;
11703 case USE_VEX_W_TABLE
:
11707 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11710 case USE_EVEX_TABLE
:
11711 two_source_ops
= 0;
11714 FETCH_DATA (info
, codep
+ 4);
11715 /* All bits in the REX prefix are ignored. */
11717 /* The first byte after 0x62. */
11718 rex
= ~(*codep
>> 5) & 0x7;
11719 vex
.r
= *codep
& 0x10;
11720 switch ((*codep
& 0xf))
11723 return &bad_opcode
;
11725 vex_table_index
= EVEX_0F
;
11728 vex_table_index
= EVEX_0F38
;
11731 vex_table_index
= EVEX_0F3A
;
11735 /* The second byte after 0x62. */
11737 vex
.w
= *codep
& 0x80;
11738 if (vex
.w
&& address_mode
== mode_64bit
)
11741 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11744 if (!(*codep
& 0x4))
11745 return &bad_opcode
;
11747 switch ((*codep
& 0x3))
11752 vex
.prefix
= DATA_PREFIX_OPCODE
;
11755 vex
.prefix
= REPE_PREFIX_OPCODE
;
11758 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11762 /* The third byte after 0x62. */
11765 /* Remember the static rounding bits. */
11766 vex
.ll
= (*codep
>> 5) & 3;
11767 vex
.b
= (*codep
& 0x10) != 0;
11769 vex
.v
= *codep
& 0x8;
11770 vex
.mask_register_specifier
= *codep
& 0x7;
11771 vex
.zeroing
= *codep
& 0x80;
11773 if (address_mode
!= mode_64bit
)
11775 /* In 16/32-bit mode silently ignore following bits. */
11785 dp
= &evex_table
[vex_table_index
][vindex
];
11787 FETCH_DATA (info
, codep
+ 1);
11788 modrm
.mod
= (*codep
>> 6) & 3;
11789 modrm
.reg
= (*codep
>> 3) & 7;
11790 modrm
.rm
= *codep
& 7;
11792 /* Set vector length. */
11793 if (modrm
.mod
== 3 && vex
.b
)
11809 return &bad_opcode
;
11822 if (dp
->name
!= NULL
)
11825 return get_valid_dis386 (dp
, info
);
11829 get_sib (disassemble_info
*info
, int sizeflag
)
11831 /* If modrm.mod == 3, operand must be register. */
11833 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11837 FETCH_DATA (info
, codep
+ 2);
11838 sib
.index
= (codep
[1] >> 3) & 7;
11839 sib
.scale
= (codep
[1] >> 6) & 3;
11840 sib
.base
= codep
[1] & 7;
11845 print_insn (bfd_vma pc
, disassemble_info
*info
)
11847 const struct dis386
*dp
;
11849 char *op_txt
[MAX_OPERANDS
];
11851 int sizeflag
, orig_sizeflag
;
11853 struct dis_private priv
;
11856 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11857 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11858 address_mode
= mode_32bit
;
11859 else if (info
->mach
== bfd_mach_i386_i8086
)
11861 address_mode
= mode_16bit
;
11862 priv
.orig_sizeflag
= 0;
11865 address_mode
= mode_64bit
;
11867 if (intel_syntax
== (char) -1)
11868 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11870 for (p
= info
->disassembler_options
; p
!= NULL
; )
11872 if (CONST_STRNEQ (p
, "amd64"))
11874 else if (CONST_STRNEQ (p
, "intel64"))
11876 else if (CONST_STRNEQ (p
, "x86-64"))
11878 address_mode
= mode_64bit
;
11879 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11881 else if (CONST_STRNEQ (p
, "i386"))
11883 address_mode
= mode_32bit
;
11884 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11886 else if (CONST_STRNEQ (p
, "i8086"))
11888 address_mode
= mode_16bit
;
11889 priv
.orig_sizeflag
= 0;
11891 else if (CONST_STRNEQ (p
, "intel"))
11894 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11895 intel_mnemonic
= 1;
11897 else if (CONST_STRNEQ (p
, "att"))
11900 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11901 intel_mnemonic
= 0;
11903 else if (CONST_STRNEQ (p
, "addr"))
11905 if (address_mode
== mode_64bit
)
11907 if (p
[4] == '3' && p
[5] == '2')
11908 priv
.orig_sizeflag
&= ~AFLAG
;
11909 else if (p
[4] == '6' && p
[5] == '4')
11910 priv
.orig_sizeflag
|= AFLAG
;
11914 if (p
[4] == '1' && p
[5] == '6')
11915 priv
.orig_sizeflag
&= ~AFLAG
;
11916 else if (p
[4] == '3' && p
[5] == '2')
11917 priv
.orig_sizeflag
|= AFLAG
;
11920 else if (CONST_STRNEQ (p
, "data"))
11922 if (p
[4] == '1' && p
[5] == '6')
11923 priv
.orig_sizeflag
&= ~DFLAG
;
11924 else if (p
[4] == '3' && p
[5] == '2')
11925 priv
.orig_sizeflag
|= DFLAG
;
11927 else if (CONST_STRNEQ (p
, "suffix"))
11928 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11930 p
= strchr (p
, ',');
11935 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11937 (*info
->fprintf_func
) (info
->stream
,
11938 _("64-bit address is disabled"));
11944 names64
= intel_names64
;
11945 names32
= intel_names32
;
11946 names16
= intel_names16
;
11947 names8
= intel_names8
;
11948 names8rex
= intel_names8rex
;
11949 names_seg
= intel_names_seg
;
11950 names_mm
= intel_names_mm
;
11951 names_bnd
= intel_names_bnd
;
11952 names_xmm
= intel_names_xmm
;
11953 names_ymm
= intel_names_ymm
;
11954 names_zmm
= intel_names_zmm
;
11955 index64
= intel_index64
;
11956 index32
= intel_index32
;
11957 names_mask
= intel_names_mask
;
11958 index16
= intel_index16
;
11961 separator_char
= '+';
11966 names64
= att_names64
;
11967 names32
= att_names32
;
11968 names16
= att_names16
;
11969 names8
= att_names8
;
11970 names8rex
= att_names8rex
;
11971 names_seg
= att_names_seg
;
11972 names_mm
= att_names_mm
;
11973 names_bnd
= att_names_bnd
;
11974 names_xmm
= att_names_xmm
;
11975 names_ymm
= att_names_ymm
;
11976 names_zmm
= att_names_zmm
;
11977 index64
= att_index64
;
11978 index32
= att_index32
;
11979 names_mask
= att_names_mask
;
11980 index16
= att_index16
;
11983 separator_char
= ',';
11987 /* The output looks better if we put 7 bytes on a line, since that
11988 puts most long word instructions on a single line. Use 8 bytes
11990 if ((info
->mach
& bfd_mach_l1om
) != 0)
11991 info
->bytes_per_line
= 8;
11993 info
->bytes_per_line
= 7;
11995 info
->private_data
= &priv
;
11996 priv
.max_fetched
= priv
.the_buffer
;
11997 priv
.insn_start
= pc
;
12000 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12008 start_codep
= priv
.the_buffer
;
12009 codep
= priv
.the_buffer
;
12011 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12015 /* Getting here means we tried for data but didn't get it. That
12016 means we have an incomplete instruction of some sort. Just
12017 print the first byte as a prefix or a .byte pseudo-op. */
12018 if (codep
> priv
.the_buffer
)
12020 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12022 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12025 /* Just print the first byte as a .byte instruction. */
12026 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12027 (unsigned int) priv
.the_buffer
[0]);
12037 sizeflag
= priv
.orig_sizeflag
;
12039 if (!ckprefix () || rex_used
)
12041 /* Too many prefixes or unused REX prefixes. */
12043 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12045 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12047 prefix_name (all_prefixes
[i
], sizeflag
));
12051 insn_codep
= codep
;
12053 FETCH_DATA (info
, codep
+ 1);
12054 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12056 if (((prefixes
& PREFIX_FWAIT
)
12057 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12059 /* Handle prefixes before fwait. */
12060 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12062 (*info
->fprintf_func
) (info
->stream
, "%s ",
12063 prefix_name (all_prefixes
[i
], sizeflag
));
12064 (*info
->fprintf_func
) (info
->stream
, "fwait");
12068 if (*codep
== 0x0f)
12070 unsigned char threebyte
;
12073 FETCH_DATA (info
, codep
+ 1);
12074 threebyte
= *codep
;
12075 dp
= &dis386_twobyte
[threebyte
];
12076 need_modrm
= twobyte_has_modrm
[*codep
];
12081 dp
= &dis386
[*codep
];
12082 need_modrm
= onebyte_has_modrm
[*codep
];
12086 /* Save sizeflag for printing the extra prefixes later before updating
12087 it for mnemonic and operand processing. The prefix names depend
12088 only on the address mode. */
12089 orig_sizeflag
= sizeflag
;
12090 if (prefixes
& PREFIX_ADDR
)
12092 if ((prefixes
& PREFIX_DATA
))
12098 FETCH_DATA (info
, codep
+ 1);
12099 modrm
.mod
= (*codep
>> 6) & 3;
12100 modrm
.reg
= (*codep
>> 3) & 7;
12101 modrm
.rm
= *codep
& 7;
12107 memset (&vex
, 0, sizeof (vex
));
12109 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12111 get_sib (info
, sizeflag
);
12112 dofloat (sizeflag
);
12116 dp
= get_valid_dis386 (dp
, info
);
12117 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12119 get_sib (info
, sizeflag
);
12120 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12123 op_ad
= MAX_OPERANDS
- 1 - i
;
12125 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12126 /* For EVEX instruction after the last operand masking
12127 should be printed. */
12128 if (i
== 0 && vex
.evex
)
12130 /* Don't print {%k0}. */
12131 if (vex
.mask_register_specifier
)
12134 oappend (names_mask
[vex
.mask_register_specifier
]);
12144 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12145 are all 0s in inverted form. */
12146 if (need_vex
&& vex
.register_specifier
!= 0)
12148 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12149 return end_codep
- priv
.the_buffer
;
12152 /* Check if the REX prefix is used. */
12153 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12154 all_prefixes
[last_rex_prefix
] = 0;
12156 /* Check if the SEG prefix is used. */
12157 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12158 | PREFIX_FS
| PREFIX_GS
)) != 0
12159 && (used_prefixes
& active_seg_prefix
) != 0)
12160 all_prefixes
[last_seg_prefix
] = 0;
12162 /* Check if the ADDR prefix is used. */
12163 if ((prefixes
& PREFIX_ADDR
) != 0
12164 && (used_prefixes
& PREFIX_ADDR
) != 0)
12165 all_prefixes
[last_addr_prefix
] = 0;
12167 /* Check if the DATA prefix is used. */
12168 if ((prefixes
& PREFIX_DATA
) != 0
12169 && (used_prefixes
& PREFIX_DATA
) != 0)
12170 all_prefixes
[last_data_prefix
] = 0;
12172 /* Print the extra prefixes. */
12174 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12175 if (all_prefixes
[i
])
12178 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12181 prefix_length
+= strlen (name
) + 1;
12182 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12185 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12186 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12187 used by putop and MMX/SSE operand and may be overriden by the
12188 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12190 if (dp
->prefix_requirement
== PREFIX_OPCODE
12191 && dp
!= &bad_opcode
12193 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12195 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12197 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12199 && (used_prefixes
& PREFIX_DATA
) == 0))))
12201 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12202 return end_codep
- priv
.the_buffer
;
12205 /* Check maximum code length. */
12206 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12208 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12209 return MAX_CODE_LENGTH
;
12212 obufp
= mnemonicendp
;
12213 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12216 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12218 /* The enter and bound instructions are printed with operands in the same
12219 order as the intel book; everything else is printed in reverse order. */
12220 if (intel_syntax
|| two_source_ops
)
12224 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12225 op_txt
[i
] = op_out
[i
];
12227 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12228 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12230 op_txt
[2] = op_out
[3];
12231 op_txt
[3] = op_out
[2];
12234 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12236 op_ad
= op_index
[i
];
12237 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12238 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12239 riprel
= op_riprel
[i
];
12240 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12241 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12246 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12247 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12251 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12255 (*info
->fprintf_func
) (info
->stream
, ",");
12256 if (op_index
[i
] != -1 && !op_riprel
[i
])
12257 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12259 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12263 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12264 if (op_index
[i
] != -1 && op_riprel
[i
])
12266 (*info
->fprintf_func
) (info
->stream
, " # ");
12267 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12268 + op_address
[op_index
[i
]]), info
);
12271 return codep
- priv
.the_buffer
;
12274 static const char *float_mem
[] = {
12349 static const unsigned char float_mem_mode
[] = {
12424 #define ST { OP_ST, 0 }
12425 #define STi { OP_STi, 0 }
12427 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12428 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12429 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12430 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12431 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12432 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12433 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12434 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12435 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12437 static const struct dis386 float_reg
[][8] = {
12440 { "fadd", { ST
, STi
}, 0 },
12441 { "fmul", { ST
, STi
}, 0 },
12442 { "fcom", { STi
}, 0 },
12443 { "fcomp", { STi
}, 0 },
12444 { "fsub", { ST
, STi
}, 0 },
12445 { "fsubr", { ST
, STi
}, 0 },
12446 { "fdiv", { ST
, STi
}, 0 },
12447 { "fdivr", { ST
, STi
}, 0 },
12451 { "fld", { STi
}, 0 },
12452 { "fxch", { STi
}, 0 },
12462 { "fcmovb", { ST
, STi
}, 0 },
12463 { "fcmove", { ST
, STi
}, 0 },
12464 { "fcmovbe",{ ST
, STi
}, 0 },
12465 { "fcmovu", { ST
, STi
}, 0 },
12473 { "fcmovnb",{ ST
, STi
}, 0 },
12474 { "fcmovne",{ ST
, STi
}, 0 },
12475 { "fcmovnbe",{ ST
, STi
}, 0 },
12476 { "fcmovnu",{ ST
, STi
}, 0 },
12478 { "fucomi", { ST
, STi
}, 0 },
12479 { "fcomi", { ST
, STi
}, 0 },
12484 { "fadd", { STi
, ST
}, 0 },
12485 { "fmul", { STi
, ST
}, 0 },
12488 { "fsub{!M|r}", { STi
, ST
}, 0 },
12489 { "fsub{M|}", { STi
, ST
}, 0 },
12490 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12491 { "fdiv{M|}", { STi
, ST
}, 0 },
12495 { "ffree", { STi
}, 0 },
12497 { "fst", { STi
}, 0 },
12498 { "fstp", { STi
}, 0 },
12499 { "fucom", { STi
}, 0 },
12500 { "fucomp", { STi
}, 0 },
12506 { "faddp", { STi
, ST
}, 0 },
12507 { "fmulp", { STi
, ST
}, 0 },
12510 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12511 { "fsub{M|}p", { STi
, ST
}, 0 },
12512 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12513 { "fdiv{M|}p", { STi
, ST
}, 0 },
12517 { "ffreep", { STi
}, 0 },
12522 { "fucomip", { ST
, STi
}, 0 },
12523 { "fcomip", { ST
, STi
}, 0 },
12528 static char *fgrps
[][8] = {
12531 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12536 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12541 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12546 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12551 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12556 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12561 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12566 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12567 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12572 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12577 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12582 swap_operand (void)
12584 mnemonicendp
[0] = '.';
12585 mnemonicendp
[1] = 's';
12590 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12591 int sizeflag ATTRIBUTE_UNUSED
)
12593 /* Skip mod/rm byte. */
12599 dofloat (int sizeflag
)
12601 const struct dis386
*dp
;
12602 unsigned char floatop
;
12604 floatop
= codep
[-1];
12606 if (modrm
.mod
!= 3)
12608 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12610 putop (float_mem
[fp_indx
], sizeflag
);
12613 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12616 /* Skip mod/rm byte. */
12620 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12621 if (dp
->name
== NULL
)
12623 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12625 /* Instruction fnstsw is only one with strange arg. */
12626 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12627 strcpy (op_out
[0], names16
[0]);
12631 putop (dp
->name
, sizeflag
);
12636 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12641 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12645 /* Like oappend (below), but S is a string starting with '%'.
12646 In Intel syntax, the '%' is elided. */
12648 oappend_maybe_intel (const char *s
)
12650 oappend (s
+ intel_syntax
);
12654 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12656 oappend_maybe_intel ("%st");
12660 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12662 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12663 oappend_maybe_intel (scratchbuf
);
12666 /* Capital letters in template are macros. */
12668 putop (const char *in_template
, int sizeflag
)
12673 unsigned int l
= 0, len
= 1;
12676 #define SAVE_LAST(c) \
12677 if (l < len && l < sizeof (last)) \
12682 for (p
= in_template
; *p
; p
++)
12698 while (*++p
!= '|')
12699 if (*p
== '}' || *p
== '\0')
12702 /* Fall through. */
12707 while (*++p
!= '}')
12718 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12722 if (l
== 0 && len
== 1)
12727 if (sizeflag
& SUFFIX_ALWAYS
)
12740 if (address_mode
== mode_64bit
12741 && !(prefixes
& PREFIX_ADDR
))
12752 if (intel_syntax
&& !alt
)
12754 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12756 if (sizeflag
& DFLAG
)
12757 *obufp
++ = intel_syntax
? 'd' : 'l';
12759 *obufp
++ = intel_syntax
? 'w' : 's';
12760 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12764 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12767 if (modrm
.mod
== 3)
12773 if (sizeflag
& DFLAG
)
12774 *obufp
++ = intel_syntax
? 'd' : 'l';
12777 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12783 case 'E': /* For jcxz/jecxz */
12784 if (address_mode
== mode_64bit
)
12786 if (sizeflag
& AFLAG
)
12792 if (sizeflag
& AFLAG
)
12794 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12799 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12801 if (sizeflag
& AFLAG
)
12802 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12804 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12805 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12809 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12811 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12815 if (!(rex
& REX_W
))
12816 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12821 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12822 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12824 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12827 if (prefixes
& PREFIX_DS
)
12846 if (l
!= 0 || len
!= 1)
12848 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12853 if (!need_vex
|| !vex
.evex
)
12856 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12858 switch (vex
.length
)
12876 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12881 /* Fall through. */
12884 if (l
!= 0 || len
!= 1)
12892 if (sizeflag
& SUFFIX_ALWAYS
)
12896 if (intel_mnemonic
!= cond
)
12900 if ((prefixes
& PREFIX_FWAIT
) == 0)
12903 used_prefixes
|= PREFIX_FWAIT
;
12909 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12913 if (!(rex
& REX_W
))
12914 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12918 && address_mode
== mode_64bit
12919 && isa64
== intel64
)
12924 /* Fall through. */
12927 && address_mode
== mode_64bit
12928 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12933 /* Fall through. */
12936 if (l
== 0 && len
== 1)
12941 if ((rex
& REX_W
) == 0
12942 && (prefixes
& PREFIX_DATA
))
12944 if ((sizeflag
& DFLAG
) == 0)
12946 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12950 if ((prefixes
& PREFIX_DATA
)
12952 || (sizeflag
& SUFFIX_ALWAYS
))
12959 if (sizeflag
& DFLAG
)
12963 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12969 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12975 if ((prefixes
& PREFIX_DATA
)
12977 || (sizeflag
& SUFFIX_ALWAYS
))
12984 if (sizeflag
& DFLAG
)
12985 *obufp
++ = intel_syntax
? 'd' : 'l';
12988 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12996 if (address_mode
== mode_64bit
12997 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12999 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13003 /* Fall through. */
13006 if (l
== 0 && len
== 1)
13009 if (intel_syntax
&& !alt
)
13012 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13018 if (sizeflag
& DFLAG
)
13019 *obufp
++ = intel_syntax
? 'd' : 'l';
13022 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13028 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13034 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13049 else if (sizeflag
& DFLAG
)
13058 if (intel_syntax
&& !p
[1]
13059 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13061 if (!(rex
& REX_W
))
13062 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13065 if (l
== 0 && len
== 1)
13069 if (address_mode
== mode_64bit
13070 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13072 if (sizeflag
& SUFFIX_ALWAYS
)
13094 /* Fall through. */
13097 if (l
== 0 && len
== 1)
13102 if (sizeflag
& SUFFIX_ALWAYS
)
13108 if (sizeflag
& DFLAG
)
13112 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13126 if (address_mode
== mode_64bit
13127 && !(prefixes
& PREFIX_ADDR
))
13138 if (l
!= 0 || len
!= 1)
13143 if (need_vex
&& vex
.prefix
)
13145 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13152 if (prefixes
& PREFIX_DATA
)
13156 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13160 if (l
== 0 && len
== 1)
13164 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13172 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13174 switch (vex
.length
)
13190 if (l
== 0 && len
== 1)
13192 /* operand size flag for cwtl, cbtw */
13201 else if (sizeflag
& DFLAG
)
13205 if (!(rex
& REX_W
))
13206 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13213 && last
[0] != 'L'))
13220 if (last
[0] == 'X')
13221 *obufp
++ = vex
.w
? 'd': 's';
13223 *obufp
++ = vex
.w
? 'q': 'd';
13229 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13231 if (sizeflag
& DFLAG
)
13235 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13241 if (address_mode
== mode_64bit
13242 && (isa64
== intel64
13243 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13245 else if ((prefixes
& PREFIX_DATA
))
13247 if (!(sizeflag
& DFLAG
))
13249 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13256 mnemonicendp
= obufp
;
13261 oappend (const char *s
)
13263 obufp
= stpcpy (obufp
, s
);
13269 /* Only print the active segment register. */
13270 if (!active_seg_prefix
)
13273 used_prefixes
|= active_seg_prefix
;
13274 switch (active_seg_prefix
)
13277 oappend_maybe_intel ("%cs:");
13280 oappend_maybe_intel ("%ds:");
13283 oappend_maybe_intel ("%ss:");
13286 oappend_maybe_intel ("%es:");
13289 oappend_maybe_intel ("%fs:");
13292 oappend_maybe_intel ("%gs:");
13300 OP_indirE (int bytemode
, int sizeflag
)
13304 OP_E (bytemode
, sizeflag
);
13308 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13310 if (address_mode
== mode_64bit
)
13318 sprintf_vma (tmp
, disp
);
13319 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13320 strcpy (buf
+ 2, tmp
+ i
);
13324 bfd_signed_vma v
= disp
;
13331 /* Check for possible overflow on 0x8000000000000000. */
13334 strcpy (buf
, "9223372036854775808");
13348 tmp
[28 - i
] = (v
% 10) + '0';
13352 strcpy (buf
, tmp
+ 29 - i
);
13358 sprintf (buf
, "0x%x", (unsigned int) disp
);
13360 sprintf (buf
, "%d", (int) disp
);
13364 /* Put DISP in BUF as signed hex number. */
13367 print_displacement (char *buf
, bfd_vma disp
)
13369 bfd_signed_vma val
= disp
;
13378 /* Check for possible overflow. */
13381 switch (address_mode
)
13384 strcpy (buf
+ j
, "0x8000000000000000");
13387 strcpy (buf
+ j
, "0x80000000");
13390 strcpy (buf
+ j
, "0x8000");
13400 sprintf_vma (tmp
, (bfd_vma
) val
);
13401 for (i
= 0; tmp
[i
] == '0'; i
++)
13403 if (tmp
[i
] == '\0')
13405 strcpy (buf
+ j
, tmp
+ i
);
13409 intel_operand_size (int bytemode
, int sizeflag
)
13413 && (bytemode
== x_mode
13414 || bytemode
== evex_half_bcst_xmmq_mode
))
13417 oappend ("QWORD PTR ");
13419 oappend ("DWORD PTR ");
13428 oappend ("BYTE PTR ");
13433 oappend ("WORD PTR ");
13436 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13438 oappend ("QWORD PTR ");
13441 /* Fall through. */
13443 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13445 oappend ("QWORD PTR ");
13448 /* Fall through. */
13454 oappend ("QWORD PTR ");
13457 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13458 oappend ("DWORD PTR ");
13460 oappend ("WORD PTR ");
13461 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13465 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13467 oappend ("WORD PTR ");
13468 if (!(rex
& REX_W
))
13469 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13472 if (sizeflag
& DFLAG
)
13473 oappend ("QWORD PTR ");
13475 oappend ("DWORD PTR ");
13476 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13479 case d_scalar_mode
:
13480 case d_scalar_swap_mode
:
13483 oappend ("DWORD PTR ");
13486 case q_scalar_mode
:
13487 case q_scalar_swap_mode
:
13489 oappend ("QWORD PTR ");
13492 if (address_mode
== mode_64bit
)
13493 oappend ("QWORD PTR ");
13495 oappend ("DWORD PTR ");
13498 if (sizeflag
& DFLAG
)
13499 oappend ("FWORD PTR ");
13501 oappend ("DWORD PTR ");
13502 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13505 oappend ("TBYTE PTR ");
13509 case evex_x_gscat_mode
:
13510 case evex_x_nobcst_mode
:
13511 case b_scalar_mode
:
13512 case w_scalar_mode
:
13515 switch (vex
.length
)
13518 oappend ("XMMWORD PTR ");
13521 oappend ("YMMWORD PTR ");
13524 oappend ("ZMMWORD PTR ");
13531 oappend ("XMMWORD PTR ");
13534 oappend ("XMMWORD PTR ");
13537 oappend ("YMMWORD PTR ");
13540 case evex_half_bcst_xmmq_mode
:
13544 switch (vex
.length
)
13547 oappend ("QWORD PTR ");
13550 oappend ("XMMWORD PTR ");
13553 oappend ("YMMWORD PTR ");
13563 switch (vex
.length
)
13568 oappend ("BYTE PTR ");
13578 switch (vex
.length
)
13583 oappend ("WORD PTR ");
13593 switch (vex
.length
)
13598 oappend ("DWORD PTR ");
13608 switch (vex
.length
)
13613 oappend ("QWORD PTR ");
13623 switch (vex
.length
)
13626 oappend ("WORD PTR ");
13629 oappend ("DWORD PTR ");
13632 oappend ("QWORD PTR ");
13642 switch (vex
.length
)
13645 oappend ("DWORD PTR ");
13648 oappend ("QWORD PTR ");
13651 oappend ("XMMWORD PTR ");
13661 switch (vex
.length
)
13664 oappend ("QWORD PTR ");
13667 oappend ("YMMWORD PTR ");
13670 oappend ("ZMMWORD PTR ");
13680 switch (vex
.length
)
13684 oappend ("XMMWORD PTR ");
13691 oappend ("OWORD PTR ");
13694 case vex_w_dq_mode
:
13695 case vex_scalar_w_dq_mode
:
13700 oappend ("QWORD PTR ");
13702 oappend ("DWORD PTR ");
13704 case vex_vsib_d_w_dq_mode
:
13705 case vex_vsib_q_w_dq_mode
:
13712 oappend ("QWORD PTR ");
13714 oappend ("DWORD PTR ");
13718 switch (vex
.length
)
13721 oappend ("XMMWORD PTR ");
13724 oappend ("YMMWORD PTR ");
13727 oappend ("ZMMWORD PTR ");
13734 case vex_vsib_q_w_d_mode
:
13735 case vex_vsib_d_w_d_mode
:
13736 if (!need_vex
|| !vex
.evex
)
13739 switch (vex
.length
)
13742 oappend ("QWORD PTR ");
13745 oappend ("XMMWORD PTR ");
13748 oappend ("YMMWORD PTR ");
13756 if (!need_vex
|| vex
.length
!= 128)
13759 oappend ("DWORD PTR ");
13761 oappend ("BYTE PTR ");
13767 oappend ("QWORD PTR ");
13769 oappend ("WORD PTR ");
13779 OP_E_register (int bytemode
, int sizeflag
)
13781 int reg
= modrm
.rm
;
13782 const char **names
;
13788 if ((sizeflag
& SUFFIX_ALWAYS
)
13789 && (bytemode
== b_swap_mode
13790 || bytemode
== bnd_swap_mode
13791 || bytemode
== v_swap_mode
))
13817 names
= address_mode
== mode_64bit
? names64
: names32
;
13820 case bnd_swap_mode
:
13829 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13834 /* Fall through. */
13836 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13842 /* Fall through. */
13854 if ((sizeflag
& DFLAG
)
13855 || (bytemode
!= v_mode
13856 && bytemode
!= v_swap_mode
))
13860 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13864 names
= (address_mode
== mode_64bit
13865 ? names64
: names32
);
13866 if (!(prefixes
& PREFIX_ADDR
))
13867 names
= (address_mode
== mode_16bit
13868 ? names16
: names
);
13871 /* Remove "addr16/addr32". */
13872 all_prefixes
[last_addr_prefix
] = 0;
13873 names
= (address_mode
!= mode_32bit
13874 ? names32
: names16
);
13875 used_prefixes
|= PREFIX_ADDR
;
13885 names
= names_mask
;
13890 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13893 oappend (names
[reg
]);
13897 OP_E_memory (int bytemode
, int sizeflag
)
13900 int add
= (rex
& REX_B
) ? 8 : 0;
13906 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13908 && bytemode
!= x_mode
13909 && bytemode
!= xmmq_mode
13910 && bytemode
!= evex_half_bcst_xmmq_mode
)
13926 if (address_mode
!= mode_64bit
)
13932 case vex_vsib_d_w_dq_mode
:
13933 case vex_vsib_d_w_d_mode
:
13934 case vex_vsib_q_w_dq_mode
:
13935 case vex_vsib_q_w_d_mode
:
13936 case evex_x_gscat_mode
:
13938 shift
= vex
.w
? 3 : 2;
13941 case evex_half_bcst_xmmq_mode
:
13945 shift
= vex
.w
? 3 : 2;
13948 /* Fall through. */
13952 case evex_x_nobcst_mode
:
13954 switch (vex
.length
)
13977 case q_scalar_mode
:
13979 case q_scalar_swap_mode
:
13985 case d_scalar_mode
:
13987 case d_scalar_swap_mode
:
13990 case w_scalar_mode
:
13994 case b_scalar_mode
:
14001 /* Make necessary corrections to shift for modes that need it.
14002 For these modes we currently have shift 4, 5 or 6 depending on
14003 vex.length (it corresponds to xmmword, ymmword or zmmword
14004 operand). We might want to make it 3, 4 or 5 (e.g. for
14005 xmmq_mode). In case of broadcast enabled the corrections
14006 aren't needed, as element size is always 32 or 64 bits. */
14008 && (bytemode
== xmmq_mode
14009 || bytemode
== evex_half_bcst_xmmq_mode
))
14011 else if (bytemode
== xmmqd_mode
)
14013 else if (bytemode
== xmmdw_mode
)
14015 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14023 intel_operand_size (bytemode
, sizeflag
);
14026 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14028 /* 32/64 bit address mode */
14038 int addr32flag
= !((sizeflag
& AFLAG
)
14039 || bytemode
== v_bnd_mode
14040 || bytemode
== v_bndmk_mode
14041 || bytemode
== bnd_mode
14042 || bytemode
== bnd_swap_mode
);
14043 const char **indexes64
= names64
;
14044 const char **indexes32
= names32
;
14054 vindex
= sib
.index
;
14060 case vex_vsib_d_w_dq_mode
:
14061 case vex_vsib_d_w_d_mode
:
14062 case vex_vsib_q_w_dq_mode
:
14063 case vex_vsib_q_w_d_mode
:
14073 switch (vex
.length
)
14076 indexes64
= indexes32
= names_xmm
;
14080 || bytemode
== vex_vsib_q_w_dq_mode
14081 || bytemode
== vex_vsib_q_w_d_mode
)
14082 indexes64
= indexes32
= names_ymm
;
14084 indexes64
= indexes32
= names_xmm
;
14088 || bytemode
== vex_vsib_q_w_dq_mode
14089 || bytemode
== vex_vsib_q_w_d_mode
)
14090 indexes64
= indexes32
= names_zmm
;
14092 indexes64
= indexes32
= names_ymm
;
14099 haveindex
= vindex
!= 4;
14106 rbase
= base
+ add
;
14114 if (address_mode
== mode_64bit
&& !havesib
)
14117 if (riprel
&& bytemode
== v_bndmk_mode
)
14125 FETCH_DATA (the_info
, codep
+ 1);
14127 if ((disp
& 0x80) != 0)
14129 if (vex
.evex
&& shift
> 0)
14142 && address_mode
!= mode_16bit
)
14144 if (address_mode
== mode_64bit
)
14146 /* Display eiz instead of addr32. */
14147 needindex
= addr32flag
;
14152 /* In 32-bit mode, we need index register to tell [offset]
14153 from [eiz*1 + offset]. */
14158 havedisp
= (havebase
14160 || (havesib
&& (haveindex
|| scale
!= 0)));
14163 if (modrm
.mod
!= 0 || base
== 5)
14165 if (havedisp
|| riprel
)
14166 print_displacement (scratchbuf
, disp
);
14168 print_operand_value (scratchbuf
, 1, disp
);
14169 oappend (scratchbuf
);
14173 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14177 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14178 && (bytemode
!= v_bnd_mode
)
14179 && (bytemode
!= v_bndmk_mode
)
14180 && (bytemode
!= bnd_mode
)
14181 && (bytemode
!= bnd_swap_mode
))
14182 used_prefixes
|= PREFIX_ADDR
;
14184 if (havedisp
|| (intel_syntax
&& riprel
))
14186 *obufp
++ = open_char
;
14187 if (intel_syntax
&& riprel
)
14190 oappend (!addr32flag
? "rip" : "eip");
14194 oappend (address_mode
== mode_64bit
&& !addr32flag
14195 ? names64
[rbase
] : names32
[rbase
]);
14198 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14199 print index to tell base + index from base. */
14203 || (havebase
&& base
!= ESP_REG_NUM
))
14205 if (!intel_syntax
|| havebase
)
14207 *obufp
++ = separator_char
;
14211 oappend (address_mode
== mode_64bit
&& !addr32flag
14212 ? indexes64
[vindex
] : indexes32
[vindex
]);
14214 oappend (address_mode
== mode_64bit
&& !addr32flag
14215 ? index64
: index32
);
14217 *obufp
++ = scale_char
;
14219 sprintf (scratchbuf
, "%d", 1 << scale
);
14220 oappend (scratchbuf
);
14224 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14226 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14231 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14235 disp
= - (bfd_signed_vma
) disp
;
14239 print_displacement (scratchbuf
, disp
);
14241 print_operand_value (scratchbuf
, 1, disp
);
14242 oappend (scratchbuf
);
14245 *obufp
++ = close_char
;
14248 else if (intel_syntax
)
14250 if (modrm
.mod
!= 0 || base
== 5)
14252 if (!active_seg_prefix
)
14254 oappend (names_seg
[ds_reg
- es_reg
]);
14257 print_operand_value (scratchbuf
, 1, disp
);
14258 oappend (scratchbuf
);
14264 /* 16 bit address mode */
14265 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14272 if ((disp
& 0x8000) != 0)
14277 FETCH_DATA (the_info
, codep
+ 1);
14279 if ((disp
& 0x80) != 0)
14281 if (vex
.evex
&& shift
> 0)
14286 if ((disp
& 0x8000) != 0)
14292 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14294 print_displacement (scratchbuf
, disp
);
14295 oappend (scratchbuf
);
14298 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14300 *obufp
++ = open_char
;
14302 oappend (index16
[modrm
.rm
]);
14304 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14306 if ((bfd_signed_vma
) disp
>= 0)
14311 else if (modrm
.mod
!= 1)
14315 disp
= - (bfd_signed_vma
) disp
;
14318 print_displacement (scratchbuf
, disp
);
14319 oappend (scratchbuf
);
14322 *obufp
++ = close_char
;
14325 else if (intel_syntax
)
14327 if (!active_seg_prefix
)
14329 oappend (names_seg
[ds_reg
- es_reg
]);
14332 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14333 oappend (scratchbuf
);
14336 if (vex
.evex
&& vex
.b
14337 && (bytemode
== x_mode
14338 || bytemode
== xmmq_mode
14339 || bytemode
== evex_half_bcst_xmmq_mode
))
14342 || bytemode
== xmmq_mode
14343 || bytemode
== evex_half_bcst_xmmq_mode
)
14345 switch (vex
.length
)
14348 oappend ("{1to2}");
14351 oappend ("{1to4}");
14354 oappend ("{1to8}");
14362 switch (vex
.length
)
14365 oappend ("{1to4}");
14368 oappend ("{1to8}");
14371 oappend ("{1to16}");
14381 OP_E (int bytemode
, int sizeflag
)
14383 /* Skip mod/rm byte. */
14387 if (modrm
.mod
== 3)
14388 OP_E_register (bytemode
, sizeflag
);
14390 OP_E_memory (bytemode
, sizeflag
);
14394 OP_G (int bytemode
, int sizeflag
)
14397 const char **names
;
14406 oappend (names8rex
[modrm
.reg
+ add
]);
14408 oappend (names8
[modrm
.reg
+ add
]);
14411 oappend (names16
[modrm
.reg
+ add
]);
14416 oappend (names32
[modrm
.reg
+ add
]);
14419 oappend (names64
[modrm
.reg
+ add
]);
14422 if (modrm
.reg
> 0x3)
14427 oappend (names_bnd
[modrm
.reg
]);
14436 oappend (names64
[modrm
.reg
+ add
]);
14439 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14440 oappend (names32
[modrm
.reg
+ add
]);
14442 oappend (names16
[modrm
.reg
+ add
]);
14443 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14447 names
= (address_mode
== mode_64bit
14448 ? names64
: names32
);
14449 if (!(prefixes
& PREFIX_ADDR
))
14451 if (address_mode
== mode_16bit
)
14456 /* Remove "addr16/addr32". */
14457 all_prefixes
[last_addr_prefix
] = 0;
14458 names
= (address_mode
!= mode_32bit
14459 ? names32
: names16
);
14460 used_prefixes
|= PREFIX_ADDR
;
14462 oappend (names
[modrm
.reg
+ add
]);
14465 if (address_mode
== mode_64bit
)
14466 oappend (names64
[modrm
.reg
+ add
]);
14468 oappend (names32
[modrm
.reg
+ add
]);
14472 if ((modrm
.reg
+ add
) > 0x7)
14477 oappend (names_mask
[modrm
.reg
+ add
]);
14480 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14493 FETCH_DATA (the_info
, codep
+ 8);
14494 a
= *codep
++ & 0xff;
14495 a
|= (*codep
++ & 0xff) << 8;
14496 a
|= (*codep
++ & 0xff) << 16;
14497 a
|= (*codep
++ & 0xffu
) << 24;
14498 b
= *codep
++ & 0xff;
14499 b
|= (*codep
++ & 0xff) << 8;
14500 b
|= (*codep
++ & 0xff) << 16;
14501 b
|= (*codep
++ & 0xffu
) << 24;
14502 x
= a
+ ((bfd_vma
) b
<< 32);
14510 static bfd_signed_vma
14513 bfd_signed_vma x
= 0;
14515 FETCH_DATA (the_info
, codep
+ 4);
14516 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14517 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14518 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14519 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14523 static bfd_signed_vma
14526 bfd_signed_vma x
= 0;
14528 FETCH_DATA (the_info
, codep
+ 4);
14529 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14530 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14531 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14532 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14534 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14544 FETCH_DATA (the_info
, codep
+ 2);
14545 x
= *codep
++ & 0xff;
14546 x
|= (*codep
++ & 0xff) << 8;
14551 set_op (bfd_vma op
, int riprel
)
14553 op_index
[op_ad
] = op_ad
;
14554 if (address_mode
== mode_64bit
)
14556 op_address
[op_ad
] = op
;
14557 op_riprel
[op_ad
] = riprel
;
14561 /* Mask to get a 32-bit address. */
14562 op_address
[op_ad
] = op
& 0xffffffff;
14563 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14568 OP_REG (int code
, int sizeflag
)
14575 case es_reg
: case ss_reg
: case cs_reg
:
14576 case ds_reg
: case fs_reg
: case gs_reg
:
14577 oappend (names_seg
[code
- es_reg
]);
14589 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14590 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14591 s
= names16
[code
- ax_reg
+ add
];
14593 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14594 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14597 s
= names8rex
[code
- al_reg
+ add
];
14599 s
= names8
[code
- al_reg
];
14601 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14602 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14603 if (address_mode
== mode_64bit
14604 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14606 s
= names64
[code
- rAX_reg
+ add
];
14609 code
+= eAX_reg
- rAX_reg
;
14610 /* Fall through. */
14611 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14612 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14615 s
= names64
[code
- eAX_reg
+ add
];
14618 if (sizeflag
& DFLAG
)
14619 s
= names32
[code
- eAX_reg
+ add
];
14621 s
= names16
[code
- eAX_reg
+ add
];
14622 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14626 s
= INTERNAL_DISASSEMBLER_ERROR
;
14633 OP_IMREG (int code
, int sizeflag
)
14645 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14646 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14647 s
= names16
[code
- ax_reg
];
14649 case es_reg
: case ss_reg
: case cs_reg
:
14650 case ds_reg
: case fs_reg
: case gs_reg
:
14651 s
= names_seg
[code
- es_reg
];
14653 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14654 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14657 s
= names8rex
[code
- al_reg
];
14659 s
= names8
[code
- al_reg
];
14661 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14662 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14665 s
= names64
[code
- eAX_reg
];
14668 if (sizeflag
& DFLAG
)
14669 s
= names32
[code
- eAX_reg
];
14671 s
= names16
[code
- eAX_reg
];
14672 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14675 case z_mode_ax_reg
:
14676 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14680 if (!(rex
& REX_W
))
14681 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14684 s
= INTERNAL_DISASSEMBLER_ERROR
;
14691 OP_I (int bytemode
, int sizeflag
)
14694 bfd_signed_vma mask
= -1;
14699 FETCH_DATA (the_info
, codep
+ 1);
14709 if (sizeflag
& DFLAG
)
14719 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14735 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14740 scratchbuf
[0] = '$';
14741 print_operand_value (scratchbuf
+ 1, 1, op
);
14742 oappend_maybe_intel (scratchbuf
);
14743 scratchbuf
[0] = '\0';
14747 OP_I64 (int bytemode
, int sizeflag
)
14749 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14751 OP_I (bytemode
, sizeflag
);
14757 scratchbuf
[0] = '$';
14758 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14759 oappend_maybe_intel (scratchbuf
);
14760 scratchbuf
[0] = '\0';
14764 OP_sI (int bytemode
, int sizeflag
)
14772 FETCH_DATA (the_info
, codep
+ 1);
14774 if ((op
& 0x80) != 0)
14776 if (bytemode
== b_T_mode
)
14778 if (address_mode
!= mode_64bit
14779 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14781 /* The operand-size prefix is overridden by a REX prefix. */
14782 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14790 if (!(rex
& REX_W
))
14792 if (sizeflag
& DFLAG
)
14800 /* The operand-size prefix is overridden by a REX prefix. */
14801 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14807 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14811 scratchbuf
[0] = '$';
14812 print_operand_value (scratchbuf
+ 1, 1, op
);
14813 oappend_maybe_intel (scratchbuf
);
14817 OP_J (int bytemode
, int sizeflag
)
14821 bfd_vma segment
= 0;
14826 FETCH_DATA (the_info
, codep
+ 1);
14828 if ((disp
& 0x80) != 0)
14832 if (isa64
== amd64
)
14835 if ((sizeflag
& DFLAG
)
14836 || (address_mode
== mode_64bit
14837 && ((isa64
!= amd64
&& bytemode
!= dqw_mode
)
14838 || (rex
& REX_W
))))
14843 if ((disp
& 0x8000) != 0)
14845 /* In 16bit mode, address is wrapped around at 64k within
14846 the same segment. Otherwise, a data16 prefix on a jump
14847 instruction means that the pc is masked to 16 bits after
14848 the displacement is added! */
14850 if ((prefixes
& PREFIX_DATA
) == 0)
14851 segment
= ((start_pc
+ (codep
- start_codep
))
14852 & ~((bfd_vma
) 0xffff));
14854 if (address_mode
!= mode_64bit
14855 || (isa64
== amd64
&& !(rex
& REX_W
)))
14856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14859 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14862 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14864 print_operand_value (scratchbuf
, 1, disp
);
14865 oappend (scratchbuf
);
14869 OP_SEG (int bytemode
, int sizeflag
)
14871 if (bytemode
== w_mode
)
14872 oappend (names_seg
[modrm
.reg
]);
14874 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14878 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14882 if (sizeflag
& DFLAG
)
14892 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14894 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14896 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14897 oappend (scratchbuf
);
14901 OP_OFF (int bytemode
, int sizeflag
)
14905 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14906 intel_operand_size (bytemode
, sizeflag
);
14909 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14916 if (!active_seg_prefix
)
14918 oappend (names_seg
[ds_reg
- es_reg
]);
14922 print_operand_value (scratchbuf
, 1, off
);
14923 oappend (scratchbuf
);
14927 OP_OFF64 (int bytemode
, int sizeflag
)
14931 if (address_mode
!= mode_64bit
14932 || (prefixes
& PREFIX_ADDR
))
14934 OP_OFF (bytemode
, sizeflag
);
14938 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14939 intel_operand_size (bytemode
, sizeflag
);
14946 if (!active_seg_prefix
)
14948 oappend (names_seg
[ds_reg
- es_reg
]);
14952 print_operand_value (scratchbuf
, 1, off
);
14953 oappend (scratchbuf
);
14957 ptr_reg (int code
, int sizeflag
)
14961 *obufp
++ = open_char
;
14962 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14963 if (address_mode
== mode_64bit
)
14965 if (!(sizeflag
& AFLAG
))
14966 s
= names32
[code
- eAX_reg
];
14968 s
= names64
[code
- eAX_reg
];
14970 else if (sizeflag
& AFLAG
)
14971 s
= names32
[code
- eAX_reg
];
14973 s
= names16
[code
- eAX_reg
];
14975 *obufp
++ = close_char
;
14980 OP_ESreg (int code
, int sizeflag
)
14986 case 0x6d: /* insw/insl */
14987 intel_operand_size (z_mode
, sizeflag
);
14989 case 0xa5: /* movsw/movsl/movsq */
14990 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14991 case 0xab: /* stosw/stosl */
14992 case 0xaf: /* scasw/scasl */
14993 intel_operand_size (v_mode
, sizeflag
);
14996 intel_operand_size (b_mode
, sizeflag
);
14999 oappend_maybe_intel ("%es:");
15000 ptr_reg (code
, sizeflag
);
15004 OP_DSreg (int code
, int sizeflag
)
15010 case 0x6f: /* outsw/outsl */
15011 intel_operand_size (z_mode
, sizeflag
);
15013 case 0xa5: /* movsw/movsl/movsq */
15014 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15015 case 0xad: /* lodsw/lodsl/lodsq */
15016 intel_operand_size (v_mode
, sizeflag
);
15019 intel_operand_size (b_mode
, sizeflag
);
15022 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15023 default segment register DS is printed. */
15024 if (!active_seg_prefix
)
15025 active_seg_prefix
= PREFIX_DS
;
15027 ptr_reg (code
, sizeflag
);
15031 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15039 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15041 all_prefixes
[last_lock_prefix
] = 0;
15042 used_prefixes
|= PREFIX_LOCK
;
15047 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15048 oappend_maybe_intel (scratchbuf
);
15052 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15061 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15063 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15064 oappend (scratchbuf
);
15068 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15070 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15071 oappend_maybe_intel (scratchbuf
);
15075 OP_R (int bytemode
, int sizeflag
)
15077 /* Skip mod/rm byte. */
15080 OP_E_register (bytemode
, sizeflag
);
15084 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15086 int reg
= modrm
.reg
;
15087 const char **names
;
15089 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15090 if (prefixes
& PREFIX_DATA
)
15099 oappend (names
[reg
]);
15103 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15105 int reg
= modrm
.reg
;
15106 const char **names
;
15118 && bytemode
!= xmm_mode
15119 && bytemode
!= xmmq_mode
15120 && bytemode
!= evex_half_bcst_xmmq_mode
15121 && bytemode
!= ymm_mode
15122 && bytemode
!= scalar_mode
)
15124 switch (vex
.length
)
15131 || (bytemode
!= vex_vsib_q_w_dq_mode
15132 && bytemode
!= vex_vsib_q_w_d_mode
))
15144 else if (bytemode
== xmmq_mode
15145 || bytemode
== evex_half_bcst_xmmq_mode
)
15147 switch (vex
.length
)
15160 else if (bytemode
== ymm_mode
)
15164 oappend (names
[reg
]);
15168 OP_EM (int bytemode
, int sizeflag
)
15171 const char **names
;
15173 if (modrm
.mod
!= 3)
15176 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15178 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15179 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15181 OP_E (bytemode
, sizeflag
);
15185 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15188 /* Skip mod/rm byte. */
15191 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15193 if (prefixes
& PREFIX_DATA
)
15202 oappend (names
[reg
]);
15205 /* cvt* are the only instructions in sse2 which have
15206 both SSE and MMX operands and also have 0x66 prefix
15207 in their opcode. 0x66 was originally used to differentiate
15208 between SSE and MMX instruction(operands). So we have to handle the
15209 cvt* separately using OP_EMC and OP_MXC */
15211 OP_EMC (int bytemode
, int sizeflag
)
15213 if (modrm
.mod
!= 3)
15215 if (intel_syntax
&& bytemode
== v_mode
)
15217 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15218 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15220 OP_E (bytemode
, sizeflag
);
15224 /* Skip mod/rm byte. */
15227 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15228 oappend (names_mm
[modrm
.rm
]);
15232 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15234 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15235 oappend (names_mm
[modrm
.reg
]);
15239 OP_EX (int bytemode
, int sizeflag
)
15242 const char **names
;
15244 /* Skip mod/rm byte. */
15248 if (modrm
.mod
!= 3)
15250 OP_E_memory (bytemode
, sizeflag
);
15265 if ((sizeflag
& SUFFIX_ALWAYS
)
15266 && (bytemode
== x_swap_mode
15267 || bytemode
== d_swap_mode
15268 || bytemode
== d_scalar_swap_mode
15269 || bytemode
== q_swap_mode
15270 || bytemode
== q_scalar_swap_mode
))
15274 && bytemode
!= xmm_mode
15275 && bytemode
!= xmmdw_mode
15276 && bytemode
!= xmmqd_mode
15277 && bytemode
!= xmm_mb_mode
15278 && bytemode
!= xmm_mw_mode
15279 && bytemode
!= xmm_md_mode
15280 && bytemode
!= xmm_mq_mode
15281 && bytemode
!= xmm_mdq_mode
15282 && bytemode
!= xmmq_mode
15283 && bytemode
!= evex_half_bcst_xmmq_mode
15284 && bytemode
!= ymm_mode
15285 && bytemode
!= d_scalar_mode
15286 && bytemode
!= d_scalar_swap_mode
15287 && bytemode
!= q_scalar_mode
15288 && bytemode
!= q_scalar_swap_mode
15289 && bytemode
!= vex_scalar_w_dq_mode
)
15291 switch (vex
.length
)
15306 else if (bytemode
== xmmq_mode
15307 || bytemode
== evex_half_bcst_xmmq_mode
)
15309 switch (vex
.length
)
15322 else if (bytemode
== ymm_mode
)
15326 oappend (names
[reg
]);
15330 OP_MS (int bytemode
, int sizeflag
)
15332 if (modrm
.mod
== 3)
15333 OP_EM (bytemode
, sizeflag
);
15339 OP_XS (int bytemode
, int sizeflag
)
15341 if (modrm
.mod
== 3)
15342 OP_EX (bytemode
, sizeflag
);
15348 OP_M (int bytemode
, int sizeflag
)
15350 if (modrm
.mod
== 3)
15351 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15354 OP_E (bytemode
, sizeflag
);
15358 OP_0f07 (int bytemode
, int sizeflag
)
15360 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15363 OP_E (bytemode
, sizeflag
);
15366 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15367 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15370 NOP_Fixup1 (int bytemode
, int sizeflag
)
15372 if ((prefixes
& PREFIX_DATA
) != 0
15375 && address_mode
== mode_64bit
))
15376 OP_REG (bytemode
, sizeflag
);
15378 strcpy (obuf
, "nop");
15382 NOP_Fixup2 (int bytemode
, int sizeflag
)
15384 if ((prefixes
& PREFIX_DATA
) != 0
15387 && address_mode
== mode_64bit
))
15388 OP_IMREG (bytemode
, sizeflag
);
15391 static const char *const Suffix3DNow
[] = {
15392 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15393 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15394 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15395 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15396 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15397 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15398 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15399 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15400 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15401 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15402 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15403 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15404 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15405 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15406 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15407 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15408 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15409 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15410 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15411 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15412 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15413 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15414 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15415 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15416 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15417 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15418 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15419 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15420 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15421 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15422 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15423 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15424 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15425 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15426 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15427 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15428 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15429 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15430 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15431 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15432 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15433 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15434 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15435 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15436 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15437 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15438 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15439 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15440 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15441 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15442 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15443 /* CC */ NULL
, NULL
, NULL
, NULL
,
15444 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15445 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15446 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15447 /* DC */ NULL
, NULL
, NULL
, NULL
,
15448 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15449 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15450 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15451 /* EC */ NULL
, NULL
, NULL
, NULL
,
15452 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15453 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15454 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15455 /* FC */ NULL
, NULL
, NULL
, NULL
,
15459 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15461 const char *mnemonic
;
15463 FETCH_DATA (the_info
, codep
+ 1);
15464 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15465 place where an 8-bit immediate would normally go. ie. the last
15466 byte of the instruction. */
15467 obufp
= mnemonicendp
;
15468 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15470 oappend (mnemonic
);
15473 /* Since a variable sized modrm/sib chunk is between the start
15474 of the opcode (0x0f0f) and the opcode suffix, we need to do
15475 all the modrm processing first, and don't know until now that
15476 we have a bad opcode. This necessitates some cleaning up. */
15477 op_out
[0][0] = '\0';
15478 op_out
[1][0] = '\0';
15481 mnemonicendp
= obufp
;
15484 static struct op simd_cmp_op
[] =
15486 { STRING_COMMA_LEN ("eq") },
15487 { STRING_COMMA_LEN ("lt") },
15488 { STRING_COMMA_LEN ("le") },
15489 { STRING_COMMA_LEN ("unord") },
15490 { STRING_COMMA_LEN ("neq") },
15491 { STRING_COMMA_LEN ("nlt") },
15492 { STRING_COMMA_LEN ("nle") },
15493 { STRING_COMMA_LEN ("ord") }
15497 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15499 unsigned int cmp_type
;
15501 FETCH_DATA (the_info
, codep
+ 1);
15502 cmp_type
= *codep
++ & 0xff;
15503 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15506 char *p
= mnemonicendp
- 2;
15510 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15511 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15515 /* We have a reserved extension byte. Output it directly. */
15516 scratchbuf
[0] = '$';
15517 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15518 oappend_maybe_intel (scratchbuf
);
15519 scratchbuf
[0] = '\0';
15524 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15526 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15529 strcpy (op_out
[0], names32
[0]);
15530 strcpy (op_out
[1], names32
[1]);
15531 if (bytemode
== eBX_reg
)
15532 strcpy (op_out
[2], names32
[3]);
15533 two_source_ops
= 1;
15535 /* Skip mod/rm byte. */
15541 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15542 int sizeflag ATTRIBUTE_UNUSED
)
15544 /* monitor %{e,r,}ax,%ecx,%edx" */
15547 const char **names
= (address_mode
== mode_64bit
15548 ? names64
: names32
);
15550 if (prefixes
& PREFIX_ADDR
)
15552 /* Remove "addr16/addr32". */
15553 all_prefixes
[last_addr_prefix
] = 0;
15554 names
= (address_mode
!= mode_32bit
15555 ? names32
: names16
);
15556 used_prefixes
|= PREFIX_ADDR
;
15558 else if (address_mode
== mode_16bit
)
15560 strcpy (op_out
[0], names
[0]);
15561 strcpy (op_out
[1], names32
[1]);
15562 strcpy (op_out
[2], names32
[2]);
15563 two_source_ops
= 1;
15565 /* Skip mod/rm byte. */
15573 /* Throw away prefixes and 1st. opcode byte. */
15574 codep
= insn_codep
+ 1;
15579 REP_Fixup (int bytemode
, int sizeflag
)
15581 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15583 if (prefixes
& PREFIX_REPZ
)
15584 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15591 OP_IMREG (bytemode
, sizeflag
);
15594 OP_ESreg (bytemode
, sizeflag
);
15597 OP_DSreg (bytemode
, sizeflag
);
15605 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15609 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15611 if (prefixes
& PREFIX_REPNZ
)
15612 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15615 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15619 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15620 int sizeflag ATTRIBUTE_UNUSED
)
15622 if (active_seg_prefix
== PREFIX_DS
15623 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15625 /* NOTRACK prefix is only valid on indirect branch instructions.
15626 NB: DATA prefix is unsupported for Intel64. */
15627 active_seg_prefix
= 0;
15628 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15632 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15633 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15637 HLE_Fixup1 (int bytemode
, int sizeflag
)
15640 && (prefixes
& PREFIX_LOCK
) != 0)
15642 if (prefixes
& PREFIX_REPZ
)
15643 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15644 if (prefixes
& PREFIX_REPNZ
)
15645 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15648 OP_E (bytemode
, sizeflag
);
15651 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15652 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15656 HLE_Fixup2 (int bytemode
, int sizeflag
)
15658 if (modrm
.mod
!= 3)
15660 if (prefixes
& PREFIX_REPZ
)
15661 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15662 if (prefixes
& PREFIX_REPNZ
)
15663 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15666 OP_E (bytemode
, sizeflag
);
15669 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15670 "xrelease" for memory operand. No check for LOCK prefix. */
15673 HLE_Fixup3 (int bytemode
, int sizeflag
)
15676 && last_repz_prefix
> last_repnz_prefix
15677 && (prefixes
& PREFIX_REPZ
) != 0)
15678 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15680 OP_E (bytemode
, sizeflag
);
15684 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15689 /* Change cmpxchg8b to cmpxchg16b. */
15690 char *p
= mnemonicendp
- 2;
15691 mnemonicendp
= stpcpy (p
, "16b");
15694 else if ((prefixes
& PREFIX_LOCK
) != 0)
15696 if (prefixes
& PREFIX_REPZ
)
15697 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15698 if (prefixes
& PREFIX_REPNZ
)
15699 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15702 OP_M (bytemode
, sizeflag
);
15706 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15708 const char **names
;
15712 switch (vex
.length
)
15726 oappend (names
[reg
]);
15730 CRC32_Fixup (int bytemode
, int sizeflag
)
15732 /* Add proper suffix to "crc32". */
15733 char *p
= mnemonicendp
;
15752 if (sizeflag
& DFLAG
)
15756 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15760 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15767 if (modrm
.mod
== 3)
15771 /* Skip mod/rm byte. */
15776 add
= (rex
& REX_B
) ? 8 : 0;
15777 if (bytemode
== b_mode
)
15781 oappend (names8rex
[modrm
.rm
+ add
]);
15783 oappend (names8
[modrm
.rm
+ add
]);
15789 oappend (names64
[modrm
.rm
+ add
]);
15790 else if ((prefixes
& PREFIX_DATA
))
15791 oappend (names16
[modrm
.rm
+ add
]);
15793 oappend (names32
[modrm
.rm
+ add
]);
15797 OP_E (bytemode
, sizeflag
);
15801 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15803 /* Add proper suffix to "fxsave" and "fxrstor". */
15807 char *p
= mnemonicendp
;
15813 OP_M (bytemode
, sizeflag
);
15817 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15819 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15822 char *p
= mnemonicendp
;
15827 else if (sizeflag
& SUFFIX_ALWAYS
)
15834 OP_EX (bytemode
, sizeflag
);
15837 /* Display the destination register operand for instructions with
15841 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15844 const char **names
;
15852 reg
= vex
.register_specifier
;
15853 vex
.register_specifier
= 0;
15854 if (address_mode
!= mode_64bit
)
15856 else if (vex
.evex
&& !vex
.v
)
15859 if (bytemode
== vex_scalar_mode
)
15861 oappend (names_xmm
[reg
]);
15865 switch (vex
.length
)
15872 case vex_vsib_q_w_dq_mode
:
15873 case vex_vsib_q_w_d_mode
:
15889 names
= names_mask
;
15903 case vex_vsib_q_w_dq_mode
:
15904 case vex_vsib_q_w_d_mode
:
15905 names
= vex
.w
? names_ymm
: names_xmm
;
15914 names
= names_mask
;
15917 /* See PR binutils/20893 for a reproducer. */
15929 oappend (names
[reg
]);
15932 /* Get the VEX immediate byte without moving codep. */
15934 static unsigned char
15935 get_vex_imm8 (int sizeflag
, int opnum
)
15937 int bytes_before_imm
= 0;
15939 if (modrm
.mod
!= 3)
15941 /* There are SIB/displacement bytes. */
15942 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15944 /* 32/64 bit address mode */
15945 int base
= modrm
.rm
;
15947 /* Check SIB byte. */
15950 FETCH_DATA (the_info
, codep
+ 1);
15952 /* When decoding the third source, don't increase
15953 bytes_before_imm as this has already been incremented
15954 by one in OP_E_memory while decoding the second
15957 bytes_before_imm
++;
15960 /* Don't increase bytes_before_imm when decoding the third source,
15961 it has already been incremented by OP_E_memory while decoding
15962 the second source operand. */
15968 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15969 SIB == 5, there is a 4 byte displacement. */
15971 /* No displacement. */
15973 /* Fall through. */
15975 /* 4 byte displacement. */
15976 bytes_before_imm
+= 4;
15979 /* 1 byte displacement. */
15980 bytes_before_imm
++;
15987 /* 16 bit address mode */
15988 /* Don't increase bytes_before_imm when decoding the third source,
15989 it has already been incremented by OP_E_memory while decoding
15990 the second source operand. */
15996 /* When modrm.rm == 6, there is a 2 byte displacement. */
15998 /* No displacement. */
16000 /* Fall through. */
16002 /* 2 byte displacement. */
16003 bytes_before_imm
+= 2;
16006 /* 1 byte displacement: when decoding the third source,
16007 don't increase bytes_before_imm as this has already
16008 been incremented by one in OP_E_memory while decoding
16009 the second source operand. */
16011 bytes_before_imm
++;
16019 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16020 return codep
[bytes_before_imm
];
16024 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16026 const char **names
;
16028 if (reg
== -1 && modrm
.mod
!= 3)
16030 OP_E_memory (bytemode
, sizeflag
);
16042 if (address_mode
!= mode_64bit
)
16046 switch (vex
.length
)
16057 oappend (names
[reg
]);
16061 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16064 static unsigned char vex_imm8
;
16066 if (vex_w_done
== 0)
16070 /* Skip mod/rm byte. */
16074 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16077 reg
= vex_imm8
>> 4;
16079 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16081 else if (vex_w_done
== 1)
16086 reg
= vex_imm8
>> 4;
16088 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16092 /* Output the imm8 directly. */
16093 scratchbuf
[0] = '$';
16094 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16095 oappend_maybe_intel (scratchbuf
);
16096 scratchbuf
[0] = '\0';
16102 OP_Vex_2src (int bytemode
, int sizeflag
)
16104 if (modrm
.mod
== 3)
16106 int reg
= modrm
.rm
;
16110 oappend (names_xmm
[reg
]);
16115 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16117 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16118 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16120 OP_E (bytemode
, sizeflag
);
16125 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16127 if (modrm
.mod
== 3)
16129 /* Skip mod/rm byte. */
16136 unsigned int reg
= vex
.register_specifier
;
16137 vex
.register_specifier
= 0;
16139 if (address_mode
!= mode_64bit
)
16141 oappend (names_xmm
[reg
]);
16144 OP_Vex_2src (bytemode
, sizeflag
);
16148 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16151 OP_Vex_2src (bytemode
, sizeflag
);
16154 unsigned int reg
= vex
.register_specifier
;
16155 vex
.register_specifier
= 0;
16157 if (address_mode
!= mode_64bit
)
16159 oappend (names_xmm
[reg
]);
16164 OP_EX_VexW (int bytemode
, int sizeflag
)
16170 /* Skip mod/rm byte. */
16175 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16180 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16183 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16191 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16194 const char **names
;
16196 FETCH_DATA (the_info
, codep
+ 1);
16199 if (bytemode
!= x_mode
)
16203 if (address_mode
!= mode_64bit
)
16206 switch (vex
.length
)
16217 oappend (names
[reg
]);
16221 OP_XMM_VexW (int bytemode
, int sizeflag
)
16223 /* Turn off the REX.W bit since it is used for swapping operands
16226 OP_XMM (bytemode
, sizeflag
);
16230 OP_EX_Vex (int bytemode
, int sizeflag
)
16232 if (modrm
.mod
!= 3)
16234 OP_EX (bytemode
, sizeflag
);
16238 OP_XMM_Vex (int bytemode
, int sizeflag
)
16240 if (modrm
.mod
!= 3)
16242 OP_XMM (bytemode
, sizeflag
);
16245 static struct op vex_cmp_op
[] =
16247 { STRING_COMMA_LEN ("eq") },
16248 { STRING_COMMA_LEN ("lt") },
16249 { STRING_COMMA_LEN ("le") },
16250 { STRING_COMMA_LEN ("unord") },
16251 { STRING_COMMA_LEN ("neq") },
16252 { STRING_COMMA_LEN ("nlt") },
16253 { STRING_COMMA_LEN ("nle") },
16254 { STRING_COMMA_LEN ("ord") },
16255 { STRING_COMMA_LEN ("eq_uq") },
16256 { STRING_COMMA_LEN ("nge") },
16257 { STRING_COMMA_LEN ("ngt") },
16258 { STRING_COMMA_LEN ("false") },
16259 { STRING_COMMA_LEN ("neq_oq") },
16260 { STRING_COMMA_LEN ("ge") },
16261 { STRING_COMMA_LEN ("gt") },
16262 { STRING_COMMA_LEN ("true") },
16263 { STRING_COMMA_LEN ("eq_os") },
16264 { STRING_COMMA_LEN ("lt_oq") },
16265 { STRING_COMMA_LEN ("le_oq") },
16266 { STRING_COMMA_LEN ("unord_s") },
16267 { STRING_COMMA_LEN ("neq_us") },
16268 { STRING_COMMA_LEN ("nlt_uq") },
16269 { STRING_COMMA_LEN ("nle_uq") },
16270 { STRING_COMMA_LEN ("ord_s") },
16271 { STRING_COMMA_LEN ("eq_us") },
16272 { STRING_COMMA_LEN ("nge_uq") },
16273 { STRING_COMMA_LEN ("ngt_uq") },
16274 { STRING_COMMA_LEN ("false_os") },
16275 { STRING_COMMA_LEN ("neq_os") },
16276 { STRING_COMMA_LEN ("ge_oq") },
16277 { STRING_COMMA_LEN ("gt_oq") },
16278 { STRING_COMMA_LEN ("true_us") },
16282 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16284 unsigned int cmp_type
;
16286 FETCH_DATA (the_info
, codep
+ 1);
16287 cmp_type
= *codep
++ & 0xff;
16288 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16291 char *p
= mnemonicendp
- 2;
16295 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16296 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16300 /* We have a reserved extension byte. Output it directly. */
16301 scratchbuf
[0] = '$';
16302 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16303 oappend_maybe_intel (scratchbuf
);
16304 scratchbuf
[0] = '\0';
16309 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16310 int sizeflag ATTRIBUTE_UNUSED
)
16312 unsigned int cmp_type
;
16317 FETCH_DATA (the_info
, codep
+ 1);
16318 cmp_type
= *codep
++ & 0xff;
16319 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16320 If it's the case, print suffix, otherwise - print the immediate. */
16321 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16326 char *p
= mnemonicendp
- 2;
16328 /* vpcmp* can have both one- and two-lettered suffix. */
16342 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16343 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16347 /* We have a reserved extension byte. Output it directly. */
16348 scratchbuf
[0] = '$';
16349 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16350 oappend_maybe_intel (scratchbuf
);
16351 scratchbuf
[0] = '\0';
16355 static const struct op xop_cmp_op
[] =
16357 { STRING_COMMA_LEN ("lt") },
16358 { STRING_COMMA_LEN ("le") },
16359 { STRING_COMMA_LEN ("gt") },
16360 { STRING_COMMA_LEN ("ge") },
16361 { STRING_COMMA_LEN ("eq") },
16362 { STRING_COMMA_LEN ("neq") },
16363 { STRING_COMMA_LEN ("false") },
16364 { STRING_COMMA_LEN ("true") }
16368 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16369 int sizeflag ATTRIBUTE_UNUSED
)
16371 unsigned int cmp_type
;
16373 FETCH_DATA (the_info
, codep
+ 1);
16374 cmp_type
= *codep
++ & 0xff;
16375 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16378 char *p
= mnemonicendp
- 2;
16380 /* vpcom* can have both one- and two-lettered suffix. */
16394 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16395 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16399 /* We have a reserved extension byte. Output it directly. */
16400 scratchbuf
[0] = '$';
16401 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16402 oappend_maybe_intel (scratchbuf
);
16403 scratchbuf
[0] = '\0';
16407 static const struct op pclmul_op
[] =
16409 { STRING_COMMA_LEN ("lql") },
16410 { STRING_COMMA_LEN ("hql") },
16411 { STRING_COMMA_LEN ("lqh") },
16412 { STRING_COMMA_LEN ("hqh") }
16416 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16417 int sizeflag ATTRIBUTE_UNUSED
)
16419 unsigned int pclmul_type
;
16421 FETCH_DATA (the_info
, codep
+ 1);
16422 pclmul_type
= *codep
++ & 0xff;
16423 switch (pclmul_type
)
16434 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16437 char *p
= mnemonicendp
- 3;
16442 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16443 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16447 /* We have a reserved extension byte. Output it directly. */
16448 scratchbuf
[0] = '$';
16449 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16450 oappend_maybe_intel (scratchbuf
);
16451 scratchbuf
[0] = '\0';
16456 MOVBE_Fixup (int bytemode
, int sizeflag
)
16458 /* Add proper suffix to "movbe". */
16459 char *p
= mnemonicendp
;
16468 if (sizeflag
& SUFFIX_ALWAYS
)
16474 if (sizeflag
& DFLAG
)
16478 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16483 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16490 OP_M (bytemode
, sizeflag
);
16494 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16497 const char **names
;
16499 /* Skip mod/rm byte. */
16513 oappend (names
[reg
]);
16517 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16519 const char **names
;
16520 unsigned int reg
= vex
.register_specifier
;
16521 vex
.register_specifier
= 0;
16528 if (address_mode
!= mode_64bit
)
16530 oappend (names
[reg
]);
16534 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16537 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16541 if ((rex
& REX_R
) != 0 || !vex
.r
)
16547 oappend (names_mask
[modrm
.reg
]);
16551 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16554 || (bytemode
!= evex_rounding_mode
16555 && bytemode
!= evex_rounding_64_mode
16556 && bytemode
!= evex_sae_mode
))
16558 if (modrm
.mod
== 3 && vex
.b
)
16561 case evex_rounding_64_mode
:
16562 if (address_mode
!= mode_64bit
)
16567 /* Fall through. */
16568 case evex_rounding_mode
:
16569 oappend (names_rounding
[vex
.ll
]);
16571 case evex_sae_mode
: