opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define SEP { SEP_Fixup, 0 }
 418 #define CMP { CMP_Fixup, 0 }
 419 #define XMM0 { XMM_Fixup, 0 }
 420 #define FXSAVE { FXSAVE_Fixup, 0 }
 421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 423
 424 #define Vex { OP_VEX, vex_mode }
 425 #define VexScalar { OP_VEX, vex_scalar_mode }
 426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 427 #define Vex128 { OP_VEX, vex128_mode }
 428 #define Vex256 { OP_VEX, vex256_mode }
 429 #define VexGdq { OP_VEX, dq_mode }
 430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 432 #define EXVexW { OP_EX_VexW, x_mode }
 433 #define EXdVexW { OP_EX_VexW, d_mode }
 434 #define EXqVexW { OP_EX_VexW, q_mode }
 435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 437 #define XMVexW { OP_XMM_VexW, 0 }
 438 #define XMVexI4 { OP_REG_VexI4, x_mode }
 439 #define PCLMUL { PCLMUL_Fixup, 0 }
 440 #define VCMP { VCMP_Fixup, 0 }
 441 #define VPCMP { VPCMP_Fixup, 0 }
 442 #define VPCOM { VPCOM_Fixup, 0 }
 443
 444 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 445 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 447
 448 #define XMask { OP_Mask, mask_mode }
 449 #define MaskG { OP_G, mask_mode }
 450 #define MaskE { OP_E, mask_mode }
 451 #define MaskBDE { OP_E, mask_bd_mode }
 452 #define MaskR { OP_R, mask_mode }
 453 #define MaskVex { OP_VEX, mask_mode }
 454
 455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 459
 460 /* Used handle "rep" prefix for string instructions.  */
 461 #define Xbr { REP_Fixup, eSI_reg }
 462 #define Xvr { REP_Fixup, eSI_reg }
 463 #define Ybr { REP_Fixup, eDI_reg }
 464 #define Yvr { REP_Fixup, eDI_reg }
 465 #define Yzr { REP_Fixup, eDI_reg }
 466 #define indirDXr { REP_Fixup, indir_dx_reg }
 467 #define ALr { REP_Fixup, al_reg }
 468 #define eAXr { REP_Fixup, eAX_reg }
 469
 470 /* Used handle HLE prefix for lockable instructions.  */
 471 #define Ebh1 { HLE_Fixup1, b_mode }
 472 #define Evh1 { HLE_Fixup1, v_mode }
 473 #define Ebh2 { HLE_Fixup2, b_mode }
 474 #define Evh2 { HLE_Fixup2, v_mode }
 475 #define Ebh3 { HLE_Fixup3, b_mode }
 476 #define Evh3 { HLE_Fixup3, v_mode }
 477
 478 #define BND { BND_Fixup, 0 }
 479 #define NOTRACK { NOTRACK_Fixup, 0 }
 480
 481 #define cond_jump_flag { NULL, cond_jump_mode }
 482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 483
 484 /* bits in sizeflag */
 485 #define SUFFIX_ALWAYS 4
 486 #define AFLAG 2
 487 #define DFLAG 1
 488
 489 enum
 490 {
 491   /* byte operand */
 492   b_mode = 1,
 493   /* byte operand with operand swapped */
 494   b_swap_mode,
 495   /* byte operand, sign extend like 'T' suffix */
 496   b_T_mode,
 497   /* operand size depends on prefixes */
 498   v_mode,
 499   /* operand size depends on prefixes with operand swapped */
 500   v_swap_mode,
 501   /* operand size depends on address prefix */
 502   va_mode,
 503   /* word operand */
 504   w_mode,
 505   /* double word operand  */
 506   d_mode,
 507   /* double word operand with operand swapped */
 508   d_swap_mode,
 509   /* quad word operand */
 510   q_mode,
 511   /* quad word operand with operand swapped */
 512   q_swap_mode,
 513   /* ten-byte operand */
 514   t_mode,
 515   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 516      broadcast enabled.  */
 517   x_mode,
 518   /* Similar to x_mode, but with different EVEX mem shifts.  */
 519   evex_x_gscat_mode,
 520   /* Similar to x_mode, but with disabled broadcast.  */
 521   evex_x_nobcst_mode,
 522   /* Similar to x_mode, but with operands swapped and disabled broadcast
 523      in EVEX.  */
 524   x_swap_mode,
 525   /* 16-byte XMM operand */
 526   xmm_mode,
 527   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 528      memory operand (depending on vector length).  Broadcast isn't
 529      allowed.  */
 530   xmmq_mode,
 531   /* Same as xmmq_mode, but broadcast is allowed.  */
 532   evex_half_bcst_xmmq_mode,
 533   /* XMM register or byte memory operand */
 534   xmm_mb_mode,
 535   /* XMM register or word memory operand */
 536   xmm_mw_mode,
 537   /* XMM register or double word memory operand */
 538   xmm_md_mode,
 539   /* XMM register or quad word memory operand */
 540   xmm_mq_mode,
 541   /* XMM register or double/quad word memory operand, depending on
 542      VEX.W.  */
 543   xmm_mdq_mode,
 544   /* 16-byte XMM, word, double word or quad word operand.  */
 545   xmmdw_mode,
 546   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 547   xmmqd_mode,
 548   /* 32-byte YMM operand */
 549   ymm_mode,
 550   /* quad word, ymmword or zmmword memory operand.  */
 551   ymmq_mode,
 552   /* 32-byte YMM or 16-byte word operand */
 553   ymmxmm_mode,
 554   /* d_mode in 32bit, q_mode in 64bit mode.  */
 555   m_mode,
 556   /* pair of v_mode operands */
 557   a_mode,
 558   cond_jump_mode,
 559   loop_jcxz_mode,
 560   movsxd_mode,
 561   v_bnd_mode,
 562   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 563   v_bndmk_mode,
 564   /* operand size depends on REX prefixes.  */
 565   dq_mode,
 566   /* registers like dq_mode, memory like w_mode, displacements like
 567      v_mode without considering Intel64 ISA.  */
 568   dqw_mode,
 569   /* bounds operand */
 570   bnd_mode,
 571   /* bounds operand with operand swapped */
 572   bnd_swap_mode,
 573   /* 4- or 6-byte pointer operand */
 574   f_mode,
 575   const_1_mode,
 576   /* v_mode for indirect branch opcodes.  */
 577   indir_v_mode,
 578   /* v_mode for stack-related opcodes.  */
 579   stack_v_mode,
 580   /* non-quad operand size depends on prefixes */
 581   z_mode,
 582   /* 16-byte operand */
 583   o_mode,
 584   /* registers like dq_mode, memory like b_mode.  */
 585   dqb_mode,
 586   /* registers like d_mode, memory like b_mode.  */
 587   db_mode,
 588   /* registers like d_mode, memory like w_mode.  */
 589   dw_mode,
 590   /* registers like dq_mode, memory like d_mode.  */
 591   dqd_mode,
 592   /* normal vex mode */
 593   vex_mode,
 594   /* 128bit vex mode */
 595   vex128_mode,
 596   /* 256bit vex mode */
 597   vex256_mode,
 598   /* operand size depends on the VEX.W bit.  */
 599   vex_w_dq_mode,
 600
 601   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 602   vex_vsib_d_w_dq_mode,
 603   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 604   vex_vsib_d_w_d_mode,
 605   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 606   vex_vsib_q_w_dq_mode,
 607   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 608   vex_vsib_q_w_d_mode,
 609
 610   /* scalar, ignore vector length.  */
 611   scalar_mode,
 612   /* like b_mode, ignore vector length.  */
 613   b_scalar_mode,
 614   /* like w_mode, ignore vector length.  */
 615   w_scalar_mode,
 616   /* like d_mode, ignore vector length.  */
 617   d_scalar_mode,
 618   /* like d_swap_mode, ignore vector length.  */
 619   d_scalar_swap_mode,
 620   /* like q_mode, ignore vector length.  */
 621   q_scalar_mode,
 622   /* like q_swap_mode, ignore vector length.  */
 623   q_scalar_swap_mode,
 624   /* like vex_mode, ignore vector length.  */
 625   vex_scalar_mode,
 626   /* like vex_w_dq_mode, ignore vector length.  */
 627   vex_scalar_w_dq_mode,
 628
 629   /* Static rounding.  */
 630   evex_rounding_mode,
 631   /* Static rounding, 64-bit mode only.  */
 632   evex_rounding_64_mode,
 633   /* Supress all exceptions.  */
 634   evex_sae_mode,
 635
 636   /* Mask register operand.  */
 637   mask_mode,
 638   /* Mask register operand.  */
 639   mask_bd_mode,
 640
 641   es_reg,
 642   cs_reg,
 643   ss_reg,
 644   ds_reg,
 645   fs_reg,
 646   gs_reg,
 647
 648   eAX_reg,
 649   eCX_reg,
 650   eDX_reg,
 651   eBX_reg,
 652   eSP_reg,
 653   eBP_reg,
 654   eSI_reg,
 655   eDI_reg,
 656
 657   al_reg,
 658   cl_reg,
 659   dl_reg,
 660   bl_reg,
 661   ah_reg,
 662   ch_reg,
 663   dh_reg,
 664   bh_reg,
 665
 666   ax_reg,
 667   cx_reg,
 668   dx_reg,
 669   bx_reg,
 670   sp_reg,
 671   bp_reg,
 672   si_reg,
 673   di_reg,
 674
 675   rAX_reg,
 676   rCX_reg,
 677   rDX_reg,
 678   rBX_reg,
 679   rSP_reg,
 680   rBP_reg,
 681   rSI_reg,
 682   rDI_reg,
 683
 684   z_mode_ax_reg,
 685   indir_dx_reg
 686 };
 687
 688 enum
 689 {
 690   FLOATCODE = 1,
 691   USE_REG_TABLE,
 692   USE_MOD_TABLE,
 693   USE_RM_TABLE,
 694   USE_PREFIX_TABLE,
 695   USE_X86_64_TABLE,
 696   USE_3BYTE_TABLE,
 697   USE_XOP_8F_TABLE,
 698   USE_VEX_C4_TABLE,
 699   USE_VEX_C5_TABLE,
 700   USE_VEX_LEN_TABLE,
 701   USE_VEX_W_TABLE,
 702   USE_EVEX_TABLE,
 703   USE_EVEX_LEN_TABLE
 704 };
 705
 706 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 707
 708 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 709 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 710 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 711 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 712 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 713 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 714 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 715 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 716 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 717 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 718 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 719 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 720 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 721 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 722 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 723 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 724
 725 enum
 726 {
 727   REG_80 = 0,
 728   REG_81,
 729   REG_83,
 730   REG_8F,
 731   REG_C0,
 732   REG_C1,
 733   REG_C6,
 734   REG_C7,
 735   REG_D0,
 736   REG_D1,
 737   REG_D2,
 738   REG_D3,
 739   REG_F6,
 740   REG_F7,
 741   REG_FE,
 742   REG_FF,
 743   REG_0F00,
 744   REG_0F01,
 745   REG_0F0D,
 746   REG_0F18,
 747   REG_0F1C_P_0_MOD_0,
 748   REG_0F1E_P_1_MOD_3,
 749   REG_0F71,
 750   REG_0F72,
 751   REG_0F73,
 752   REG_0FA6,
 753   REG_0FA7,
 754   REG_0FAE,
 755   REG_0FBA,
 756   REG_0FC7,
 757   REG_VEX_0F71,
 758   REG_VEX_0F72,
 759   REG_VEX_0F73,
 760   REG_VEX_0FAE,
 761   REG_VEX_0F38F3,
 762   REG_XOP_LWPCB,
 763   REG_XOP_LWP,
 764   REG_XOP_TBM_01,
 765   REG_XOP_TBM_02,
 766
 767   REG_EVEX_0F71,
 768   REG_EVEX_0F72,
 769   REG_EVEX_0F73,
 770   REG_EVEX_0F38C6,
 771   REG_EVEX_0F38C7
 772 };
 773
 774 enum
 775 {
 776   MOD_8D = 0,
 777   MOD_C6_REG_7,
 778   MOD_C7_REG_7,
 779   MOD_FF_REG_3,
 780   MOD_FF_REG_5,
 781   MOD_0F01_REG_0,
 782   MOD_0F01_REG_1,
 783   MOD_0F01_REG_2,
 784   MOD_0F01_REG_3,
 785   MOD_0F01_REG_5,
 786   MOD_0F01_REG_7,
 787   MOD_0F12_PREFIX_0,
 788   MOD_0F13,
 789   MOD_0F16_PREFIX_0,
 790   MOD_0F17,
 791   MOD_0F18_REG_0,
 792   MOD_0F18_REG_1,
 793   MOD_0F18_REG_2,
 794   MOD_0F18_REG_3,
 795   MOD_0F18_REG_4,
 796   MOD_0F18_REG_5,
 797   MOD_0F18_REG_6,
 798   MOD_0F18_REG_7,
 799   MOD_0F1A_PREFIX_0,
 800   MOD_0F1B_PREFIX_0,
 801   MOD_0F1B_PREFIX_1,
 802   MOD_0F1C_PREFIX_0,
 803   MOD_0F1E_PREFIX_1,
 804   MOD_0F24,
 805   MOD_0F26,
 806   MOD_0F2B_PREFIX_0,
 807   MOD_0F2B_PREFIX_1,
 808   MOD_0F2B_PREFIX_2,
 809   MOD_0F2B_PREFIX_3,
 810   MOD_0F51,
 811   MOD_0F71_REG_2,
 812   MOD_0F71_REG_4,
 813   MOD_0F71_REG_6,
 814   MOD_0F72_REG_2,
 815   MOD_0F72_REG_4,
 816   MOD_0F72_REG_6,
 817   MOD_0F73_REG_2,
 818   MOD_0F73_REG_3,
 819   MOD_0F73_REG_6,
 820   MOD_0F73_REG_7,
 821   MOD_0FAE_REG_0,
 822   MOD_0FAE_REG_1,
 823   MOD_0FAE_REG_2,
 824   MOD_0FAE_REG_3,
 825   MOD_0FAE_REG_4,
 826   MOD_0FAE_REG_5,
 827   MOD_0FAE_REG_6,
 828   MOD_0FAE_REG_7,
 829   MOD_0FB2,
 830   MOD_0FB4,
 831   MOD_0FB5,
 832   MOD_0FC3,
 833   MOD_0FC7_REG_3,
 834   MOD_0FC7_REG_4,
 835   MOD_0FC7_REG_5,
 836   MOD_0FC7_REG_6,
 837   MOD_0FC7_REG_7,
 838   MOD_0FD7,
 839   MOD_0FE7_PREFIX_2,
 840   MOD_0FF0_PREFIX_3,
 841   MOD_0F382A_PREFIX_2,
 842   MOD_0F38F5_PREFIX_2,
 843   MOD_0F38F6_PREFIX_0,
 844   MOD_0F38F8_PREFIX_1,
 845   MOD_0F38F8_PREFIX_2,
 846   MOD_0F38F8_PREFIX_3,
 847   MOD_0F38F9_PREFIX_0,
 848   MOD_62_32BIT,
 849   MOD_C4_32BIT,
 850   MOD_C5_32BIT,
 851   MOD_VEX_0F12_PREFIX_0,
 852   MOD_VEX_0F13,
 853   MOD_VEX_0F16_PREFIX_0,
 854   MOD_VEX_0F17,
 855   MOD_VEX_0F2B,
 856   MOD_VEX_W_0_0F41_P_0_LEN_1,
 857   MOD_VEX_W_1_0F41_P_0_LEN_1,
 858   MOD_VEX_W_0_0F41_P_2_LEN_1,
 859   MOD_VEX_W_1_0F41_P_2_LEN_1,
 860   MOD_VEX_W_0_0F42_P_0_LEN_1,
 861   MOD_VEX_W_1_0F42_P_0_LEN_1,
 862   MOD_VEX_W_0_0F42_P_2_LEN_1,
 863   MOD_VEX_W_1_0F42_P_2_LEN_1,
 864   MOD_VEX_W_0_0F44_P_0_LEN_1,
 865   MOD_VEX_W_1_0F44_P_0_LEN_1,
 866   MOD_VEX_W_0_0F44_P_2_LEN_1,
 867   MOD_VEX_W_1_0F44_P_2_LEN_1,
 868   MOD_VEX_W_0_0F45_P_0_LEN_1,
 869   MOD_VEX_W_1_0F45_P_0_LEN_1,
 870   MOD_VEX_W_0_0F45_P_2_LEN_1,
 871   MOD_VEX_W_1_0F45_P_2_LEN_1,
 872   MOD_VEX_W_0_0F46_P_0_LEN_1,
 873   MOD_VEX_W_1_0F46_P_0_LEN_1,
 874   MOD_VEX_W_0_0F46_P_2_LEN_1,
 875   MOD_VEX_W_1_0F46_P_2_LEN_1,
 876   MOD_VEX_W_0_0F47_P_0_LEN_1,
 877   MOD_VEX_W_1_0F47_P_0_LEN_1,
 878   MOD_VEX_W_0_0F47_P_2_LEN_1,
 879   MOD_VEX_W_1_0F47_P_2_LEN_1,
 880   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 881   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 882   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 883   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 884   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 885   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 886   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 887   MOD_VEX_0F50,
 888   MOD_VEX_0F71_REG_2,
 889   MOD_VEX_0F71_REG_4,
 890   MOD_VEX_0F71_REG_6,
 891   MOD_VEX_0F72_REG_2,
 892   MOD_VEX_0F72_REG_4,
 893   MOD_VEX_0F72_REG_6,
 894   MOD_VEX_0F73_REG_2,
 895   MOD_VEX_0F73_REG_3,
 896   MOD_VEX_0F73_REG_6,
 897   MOD_VEX_0F73_REG_7,
 898   MOD_VEX_W_0_0F91_P_0_LEN_0,
 899   MOD_VEX_W_1_0F91_P_0_LEN_0,
 900   MOD_VEX_W_0_0F91_P_2_LEN_0,
 901   MOD_VEX_W_1_0F91_P_2_LEN_0,
 902   MOD_VEX_W_0_0F92_P_0_LEN_0,
 903   MOD_VEX_W_0_0F92_P_2_LEN_0,
 904   MOD_VEX_0F92_P_3_LEN_0,
 905   MOD_VEX_W_0_0F93_P_0_LEN_0,
 906   MOD_VEX_W_0_0F93_P_2_LEN_0,
 907   MOD_VEX_0F93_P_3_LEN_0,
 908   MOD_VEX_W_0_0F98_P_0_LEN_0,
 909   MOD_VEX_W_1_0F98_P_0_LEN_0,
 910   MOD_VEX_W_0_0F98_P_2_LEN_0,
 911   MOD_VEX_W_1_0F98_P_2_LEN_0,
 912   MOD_VEX_W_0_0F99_P_0_LEN_0,
 913   MOD_VEX_W_1_0F99_P_0_LEN_0,
 914   MOD_VEX_W_0_0F99_P_2_LEN_0,
 915   MOD_VEX_W_1_0F99_P_2_LEN_0,
 916   MOD_VEX_0FAE_REG_2,
 917   MOD_VEX_0FAE_REG_3,
 918   MOD_VEX_0FD7_PREFIX_2,
 919   MOD_VEX_0FE7_PREFIX_2,
 920   MOD_VEX_0FF0_PREFIX_3,
 921   MOD_VEX_0F381A_PREFIX_2,
 922   MOD_VEX_0F382A_PREFIX_2,
 923   MOD_VEX_0F382C_PREFIX_2,
 924   MOD_VEX_0F382D_PREFIX_2,
 925   MOD_VEX_0F382E_PREFIX_2,
 926   MOD_VEX_0F382F_PREFIX_2,
 927   MOD_VEX_0F385A_PREFIX_2,
 928   MOD_VEX_0F388C_PREFIX_2,
 929   MOD_VEX_0F388E_PREFIX_2,
 930   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 932   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 936   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 937   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 938
 939   MOD_EVEX_0F12_PREFIX_0,
 940   MOD_EVEX_0F16_PREFIX_0,
 941   MOD_EVEX_0F38C6_REG_1,
 942   MOD_EVEX_0F38C6_REG_2,
 943   MOD_EVEX_0F38C6_REG_5,
 944   MOD_EVEX_0F38C6_REG_6,
 945   MOD_EVEX_0F38C7_REG_1,
 946   MOD_EVEX_0F38C7_REG_2,
 947   MOD_EVEX_0F38C7_REG_5,
 948   MOD_EVEX_0F38C7_REG_6
 949 };
 950
 951 enum
 952 {
 953   RM_C6_REG_7 = 0,
 954   RM_C7_REG_7,
 955   RM_0F01_REG_0,
 956   RM_0F01_REG_1,
 957   RM_0F01_REG_2,
 958   RM_0F01_REG_3,
 959   RM_0F01_REG_5_MOD_3,
 960   RM_0F01_REG_7_MOD_3,
 961   RM_0F1E_P_1_MOD_3_REG_7,
 962   RM_0FAE_REG_6_MOD_3_P_0,
 963   RM_0FAE_REG_7_MOD_3,
 964 };
 965
 966 enum
 967 {
 968   PREFIX_90 = 0,
 969   PREFIX_0F01_REG_5_MOD_0,
 970   PREFIX_0F01_REG_5_MOD_3_RM_0,
 971   PREFIX_0F01_REG_5_MOD_3_RM_2,
 972   PREFIX_0F01_REG_7_MOD_3_RM_2,
 973   PREFIX_0F01_REG_7_MOD_3_RM_3,
 974   PREFIX_0F09,
 975   PREFIX_0F10,
 976   PREFIX_0F11,
 977   PREFIX_0F12,
 978   PREFIX_0F16,
 979   PREFIX_0F1A,
 980   PREFIX_0F1B,
 981   PREFIX_0F1C,
 982   PREFIX_0F1E,
 983   PREFIX_0F2A,
 984   PREFIX_0F2B,
 985   PREFIX_0F2C,
 986   PREFIX_0F2D,
 987   PREFIX_0F2E,
 988   PREFIX_0F2F,
 989   PREFIX_0F51,
 990   PREFIX_0F52,
 991   PREFIX_0F53,
 992   PREFIX_0F58,
 993   PREFIX_0F59,
 994   PREFIX_0F5A,
 995   PREFIX_0F5B,
 996   PREFIX_0F5C,
 997   PREFIX_0F5D,
 998   PREFIX_0F5E,
 999   PREFIX_0F5F,
1000   PREFIX_0F60,
1001   PREFIX_0F61,
1002   PREFIX_0F62,
1003   PREFIX_0F6C,
1004   PREFIX_0F6D,
1005   PREFIX_0F6F,
1006   PREFIX_0F70,
1007   PREFIX_0F73_REG_3,
1008   PREFIX_0F73_REG_7,
1009   PREFIX_0F78,
1010   PREFIX_0F79,
1011   PREFIX_0F7C,
1012   PREFIX_0F7D,
1013   PREFIX_0F7E,
1014   PREFIX_0F7F,
1015   PREFIX_0FAE_REG_0_MOD_3,
1016   PREFIX_0FAE_REG_1_MOD_3,
1017   PREFIX_0FAE_REG_2_MOD_3,
1018   PREFIX_0FAE_REG_3_MOD_3,
1019   PREFIX_0FAE_REG_4_MOD_0,
1020   PREFIX_0FAE_REG_4_MOD_3,
1021   PREFIX_0FAE_REG_5_MOD_0,
1022   PREFIX_0FAE_REG_5_MOD_3,
1023   PREFIX_0FAE_REG_6_MOD_0,
1024   PREFIX_0FAE_REG_6_MOD_3,
1025   PREFIX_0FAE_REG_7_MOD_0,
1026   PREFIX_0FB8,
1027   PREFIX_0FBC,
1028   PREFIX_0FBD,
1029   PREFIX_0FC2,
1030   PREFIX_0FC3_MOD_0,
1031   PREFIX_0FC7_REG_6_MOD_0,
1032   PREFIX_0FC7_REG_6_MOD_3,
1033   PREFIX_0FC7_REG_7_MOD_3,
1034   PREFIX_0FD0,
1035   PREFIX_0FD6,
1036   PREFIX_0FE6,
1037   PREFIX_0FE7,
1038   PREFIX_0FF0,
1039   PREFIX_0FF7,
1040   PREFIX_0F3810,
1041   PREFIX_0F3814,
1042   PREFIX_0F3815,
1043   PREFIX_0F3817,
1044   PREFIX_0F3820,
1045   PREFIX_0F3821,
1046   PREFIX_0F3822,
1047   PREFIX_0F3823,
1048   PREFIX_0F3824,
1049   PREFIX_0F3825,
1050   PREFIX_0F3828,
1051   PREFIX_0F3829,
1052   PREFIX_0F382A,
1053   PREFIX_0F382B,
1054   PREFIX_0F3830,
1055   PREFIX_0F3831,
1056   PREFIX_0F3832,
1057   PREFIX_0F3833,
1058   PREFIX_0F3834,
1059   PREFIX_0F3835,
1060   PREFIX_0F3837,
1061   PREFIX_0F3838,
1062   PREFIX_0F3839,
1063   PREFIX_0F383A,
1064   PREFIX_0F383B,
1065   PREFIX_0F383C,
1066   PREFIX_0F383D,
1067   PREFIX_0F383E,
1068   PREFIX_0F383F,
1069   PREFIX_0F3840,
1070   PREFIX_0F3841,
1071   PREFIX_0F3880,
1072   PREFIX_0F3881,
1073   PREFIX_0F3882,
1074   PREFIX_0F38C8,
1075   PREFIX_0F38C9,
1076   PREFIX_0F38CA,
1077   PREFIX_0F38CB,
1078   PREFIX_0F38CC,
1079   PREFIX_0F38CD,
1080   PREFIX_0F38CF,
1081   PREFIX_0F38DB,
1082   PREFIX_0F38DC,
1083   PREFIX_0F38DD,
1084   PREFIX_0F38DE,
1085   PREFIX_0F38DF,
1086   PREFIX_0F38F0,
1087   PREFIX_0F38F1,
1088   PREFIX_0F38F5,
1089   PREFIX_0F38F6,
1090   PREFIX_0F38F8,
1091   PREFIX_0F38F9,
1092   PREFIX_0F3A08,
1093   PREFIX_0F3A09,
1094   PREFIX_0F3A0A,
1095   PREFIX_0F3A0B,
1096   PREFIX_0F3A0C,
1097   PREFIX_0F3A0D,
1098   PREFIX_0F3A0E,
1099   PREFIX_0F3A14,
1100   PREFIX_0F3A15,
1101   PREFIX_0F3A16,
1102   PREFIX_0F3A17,
1103   PREFIX_0F3A20,
1104   PREFIX_0F3A21,
1105   PREFIX_0F3A22,
1106   PREFIX_0F3A40,
1107   PREFIX_0F3A41,
1108   PREFIX_0F3A42,
1109   PREFIX_0F3A44,
1110   PREFIX_0F3A60,
1111   PREFIX_0F3A61,
1112   PREFIX_0F3A62,
1113   PREFIX_0F3A63,
1114   PREFIX_0F3ACC,
1115   PREFIX_0F3ACE,
1116   PREFIX_0F3ACF,
1117   PREFIX_0F3ADF,
1118   PREFIX_VEX_0F10,
1119   PREFIX_VEX_0F11,
1120   PREFIX_VEX_0F12,
1121   PREFIX_VEX_0F16,
1122   PREFIX_VEX_0F2A,
1123   PREFIX_VEX_0F2C,
1124   PREFIX_VEX_0F2D,
1125   PREFIX_VEX_0F2E,
1126   PREFIX_VEX_0F2F,
1127   PREFIX_VEX_0F41,
1128   PREFIX_VEX_0F42,
1129   PREFIX_VEX_0F44,
1130   PREFIX_VEX_0F45,
1131   PREFIX_VEX_0F46,
1132   PREFIX_VEX_0F47,
1133   PREFIX_VEX_0F4A,
1134   PREFIX_VEX_0F4B,
1135   PREFIX_VEX_0F51,
1136   PREFIX_VEX_0F52,
1137   PREFIX_VEX_0F53,
1138   PREFIX_VEX_0F58,
1139   PREFIX_VEX_0F59,
1140   PREFIX_VEX_0F5A,
1141   PREFIX_VEX_0F5B,
1142   PREFIX_VEX_0F5C,
1143   PREFIX_VEX_0F5D,
1144   PREFIX_VEX_0F5E,
1145   PREFIX_VEX_0F5F,
1146   PREFIX_VEX_0F60,
1147   PREFIX_VEX_0F61,
1148   PREFIX_VEX_0F62,
1149   PREFIX_VEX_0F63,
1150   PREFIX_VEX_0F64,
1151   PREFIX_VEX_0F65,
1152   PREFIX_VEX_0F66,
1153   PREFIX_VEX_0F67,
1154   PREFIX_VEX_0F68,
1155   PREFIX_VEX_0F69,
1156   PREFIX_VEX_0F6A,
1157   PREFIX_VEX_0F6B,
1158   PREFIX_VEX_0F6C,
1159   PREFIX_VEX_0F6D,
1160   PREFIX_VEX_0F6E,
1161   PREFIX_VEX_0F6F,
1162   PREFIX_VEX_0F70,
1163   PREFIX_VEX_0F71_REG_2,
1164   PREFIX_VEX_0F71_REG_4,
1165   PREFIX_VEX_0F71_REG_6,
1166   PREFIX_VEX_0F72_REG_2,
1167   PREFIX_VEX_0F72_REG_4,
1168   PREFIX_VEX_0F72_REG_6,
1169   PREFIX_VEX_0F73_REG_2,
1170   PREFIX_VEX_0F73_REG_3,
1171   PREFIX_VEX_0F73_REG_6,
1172   PREFIX_VEX_0F73_REG_7,
1173   PREFIX_VEX_0F74,
1174   PREFIX_VEX_0F75,
1175   PREFIX_VEX_0F76,
1176   PREFIX_VEX_0F77,
1177   PREFIX_VEX_0F7C,
1178   PREFIX_VEX_0F7D,
1179   PREFIX_VEX_0F7E,
1180   PREFIX_VEX_0F7F,
1181   PREFIX_VEX_0F90,
1182   PREFIX_VEX_0F91,
1183   PREFIX_VEX_0F92,
1184   PREFIX_VEX_0F93,
1185   PREFIX_VEX_0F98,
1186   PREFIX_VEX_0F99,
1187   PREFIX_VEX_0FC2,
1188   PREFIX_VEX_0FC4,
1189   PREFIX_VEX_0FC5,
1190   PREFIX_VEX_0FD0,
1191   PREFIX_VEX_0FD1,
1192   PREFIX_VEX_0FD2,
1193   PREFIX_VEX_0FD3,
1194   PREFIX_VEX_0FD4,
1195   PREFIX_VEX_0FD5,
1196   PREFIX_VEX_0FD6,
1197   PREFIX_VEX_0FD7,
1198   PREFIX_VEX_0FD8,
1199   PREFIX_VEX_0FD9,
1200   PREFIX_VEX_0FDA,
1201   PREFIX_VEX_0FDB,
1202   PREFIX_VEX_0FDC,
1203   PREFIX_VEX_0FDD,
1204   PREFIX_VEX_0FDE,
1205   PREFIX_VEX_0FDF,
1206   PREFIX_VEX_0FE0,
1207   PREFIX_VEX_0FE1,
1208   PREFIX_VEX_0FE2,
1209   PREFIX_VEX_0FE3,
1210   PREFIX_VEX_0FE4,
1211   PREFIX_VEX_0FE5,
1212   PREFIX_VEX_0FE6,
1213   PREFIX_VEX_0FE7,
1214   PREFIX_VEX_0FE8,
1215   PREFIX_VEX_0FE9,
1216   PREFIX_VEX_0FEA,
1217   PREFIX_VEX_0FEB,
1218   PREFIX_VEX_0FEC,
1219   PREFIX_VEX_0FED,
1220   PREFIX_VEX_0FEE,
1221   PREFIX_VEX_0FEF,
1222   PREFIX_VEX_0FF0,
1223   PREFIX_VEX_0FF1,
1224   PREFIX_VEX_0FF2,
1225   PREFIX_VEX_0FF3,
1226   PREFIX_VEX_0FF4,
1227   PREFIX_VEX_0FF5,
1228   PREFIX_VEX_0FF6,
1229   PREFIX_VEX_0FF7,
1230   PREFIX_VEX_0FF8,
1231   PREFIX_VEX_0FF9,
1232   PREFIX_VEX_0FFA,
1233   PREFIX_VEX_0FFB,
1234   PREFIX_VEX_0FFC,
1235   PREFIX_VEX_0FFD,
1236   PREFIX_VEX_0FFE,
1237   PREFIX_VEX_0F3800,
1238   PREFIX_VEX_0F3801,
1239   PREFIX_VEX_0F3802,
1240   PREFIX_VEX_0F3803,
1241   PREFIX_VEX_0F3804,
1242   PREFIX_VEX_0F3805,
1243   PREFIX_VEX_0F3806,
1244   PREFIX_VEX_0F3807,
1245   PREFIX_VEX_0F3808,
1246   PREFIX_VEX_0F3809,
1247   PREFIX_VEX_0F380A,
1248   PREFIX_VEX_0F380B,
1249   PREFIX_VEX_0F380C,
1250   PREFIX_VEX_0F380D,
1251   PREFIX_VEX_0F380E,
1252   PREFIX_VEX_0F380F,
1253   PREFIX_VEX_0F3813,
1254   PREFIX_VEX_0F3816,
1255   PREFIX_VEX_0F3817,
1256   PREFIX_VEX_0F3818,
1257   PREFIX_VEX_0F3819,
1258   PREFIX_VEX_0F381A,
1259   PREFIX_VEX_0F381C,
1260   PREFIX_VEX_0F381D,
1261   PREFIX_VEX_0F381E,
1262   PREFIX_VEX_0F3820,
1263   PREFIX_VEX_0F3821,
1264   PREFIX_VEX_0F3822,
1265   PREFIX_VEX_0F3823,
1266   PREFIX_VEX_0F3824,
1267   PREFIX_VEX_0F3825,
1268   PREFIX_VEX_0F3828,
1269   PREFIX_VEX_0F3829,
1270   PREFIX_VEX_0F382A,
1271   PREFIX_VEX_0F382B,
1272   PREFIX_VEX_0F382C,
1273   PREFIX_VEX_0F382D,
1274   PREFIX_VEX_0F382E,
1275   PREFIX_VEX_0F382F,
1276   PREFIX_VEX_0F3830,
1277   PREFIX_VEX_0F3831,
1278   PREFIX_VEX_0F3832,
1279   PREFIX_VEX_0F3833,
1280   PREFIX_VEX_0F3834,
1281   PREFIX_VEX_0F3835,
1282   PREFIX_VEX_0F3836,
1283   PREFIX_VEX_0F3837,
1284   PREFIX_VEX_0F3838,
1285   PREFIX_VEX_0F3839,
1286   PREFIX_VEX_0F383A,
1287   PREFIX_VEX_0F383B,
1288   PREFIX_VEX_0F383C,
1289   PREFIX_VEX_0F383D,
1290   PREFIX_VEX_0F383E,
1291   PREFIX_VEX_0F383F,
1292   PREFIX_VEX_0F3840,
1293   PREFIX_VEX_0F3841,
1294   PREFIX_VEX_0F3845,
1295   PREFIX_VEX_0F3846,
1296   PREFIX_VEX_0F3847,
1297   PREFIX_VEX_0F3858,
1298   PREFIX_VEX_0F3859,
1299   PREFIX_VEX_0F385A,
1300   PREFIX_VEX_0F3878,
1301   PREFIX_VEX_0F3879,
1302   PREFIX_VEX_0F388C,
1303   PREFIX_VEX_0F388E,
1304   PREFIX_VEX_0F3890,
1305   PREFIX_VEX_0F3891,
1306   PREFIX_VEX_0F3892,
1307   PREFIX_VEX_0F3893,
1308   PREFIX_VEX_0F3896,
1309   PREFIX_VEX_0F3897,
1310   PREFIX_VEX_0F3898,
1311   PREFIX_VEX_0F3899,
1312   PREFIX_VEX_0F389A,
1313   PREFIX_VEX_0F389B,
1314   PREFIX_VEX_0F389C,
1315   PREFIX_VEX_0F389D,
1316   PREFIX_VEX_0F389E,
1317   PREFIX_VEX_0F389F,
1318   PREFIX_VEX_0F38A6,
1319   PREFIX_VEX_0F38A7,
1320   PREFIX_VEX_0F38A8,
1321   PREFIX_VEX_0F38A9,
1322   PREFIX_VEX_0F38AA,
1323   PREFIX_VEX_0F38AB,
1324   PREFIX_VEX_0F38AC,
1325   PREFIX_VEX_0F38AD,
1326   PREFIX_VEX_0F38AE,
1327   PREFIX_VEX_0F38AF,
1328   PREFIX_VEX_0F38B6,
1329   PREFIX_VEX_0F38B7,
1330   PREFIX_VEX_0F38B8,
1331   PREFIX_VEX_0F38B9,
1332   PREFIX_VEX_0F38BA,
1333   PREFIX_VEX_0F38BB,
1334   PREFIX_VEX_0F38BC,
1335   PREFIX_VEX_0F38BD,
1336   PREFIX_VEX_0F38BE,
1337   PREFIX_VEX_0F38BF,
1338   PREFIX_VEX_0F38CF,
1339   PREFIX_VEX_0F38DB,
1340   PREFIX_VEX_0F38DC,
1341   PREFIX_VEX_0F38DD,
1342   PREFIX_VEX_0F38DE,
1343   PREFIX_VEX_0F38DF,
1344   PREFIX_VEX_0F38F2,
1345   PREFIX_VEX_0F38F3_REG_1,
1346   PREFIX_VEX_0F38F3_REG_2,
1347   PREFIX_VEX_0F38F3_REG_3,
1348   PREFIX_VEX_0F38F5,
1349   PREFIX_VEX_0F38F6,
1350   PREFIX_VEX_0F38F7,
1351   PREFIX_VEX_0F3A00,
1352   PREFIX_VEX_0F3A01,
1353   PREFIX_VEX_0F3A02,
1354   PREFIX_VEX_0F3A04,
1355   PREFIX_VEX_0F3A05,
1356   PREFIX_VEX_0F3A06,
1357   PREFIX_VEX_0F3A08,
1358   PREFIX_VEX_0F3A09,
1359   PREFIX_VEX_0F3A0A,
1360   PREFIX_VEX_0F3A0B,
1361   PREFIX_VEX_0F3A0C,
1362   PREFIX_VEX_0F3A0D,
1363   PREFIX_VEX_0F3A0E,
1364   PREFIX_VEX_0F3A0F,
1365   PREFIX_VEX_0F3A14,
1366   PREFIX_VEX_0F3A15,
1367   PREFIX_VEX_0F3A16,
1368   PREFIX_VEX_0F3A17,
1369   PREFIX_VEX_0F3A18,
1370   PREFIX_VEX_0F3A19,
1371   PREFIX_VEX_0F3A1D,
1372   PREFIX_VEX_0F3A20,
1373   PREFIX_VEX_0F3A21,
1374   PREFIX_VEX_0F3A22,
1375   PREFIX_VEX_0F3A30,
1376   PREFIX_VEX_0F3A31,
1377   PREFIX_VEX_0F3A32,
1378   PREFIX_VEX_0F3A33,
1379   PREFIX_VEX_0F3A38,
1380   PREFIX_VEX_0F3A39,
1381   PREFIX_VEX_0F3A40,
1382   PREFIX_VEX_0F3A41,
1383   PREFIX_VEX_0F3A42,
1384   PREFIX_VEX_0F3A44,
1385   PREFIX_VEX_0F3A46,
1386   PREFIX_VEX_0F3A48,
1387   PREFIX_VEX_0F3A49,
1388   PREFIX_VEX_0F3A4A,
1389   PREFIX_VEX_0F3A4B,
1390   PREFIX_VEX_0F3A4C,
1391   PREFIX_VEX_0F3A5C,
1392   PREFIX_VEX_0F3A5D,
1393   PREFIX_VEX_0F3A5E,
1394   PREFIX_VEX_0F3A5F,
1395   PREFIX_VEX_0F3A60,
1396   PREFIX_VEX_0F3A61,
1397   PREFIX_VEX_0F3A62,
1398   PREFIX_VEX_0F3A63,
1399   PREFIX_VEX_0F3A68,
1400   PREFIX_VEX_0F3A69,
1401   PREFIX_VEX_0F3A6A,
1402   PREFIX_VEX_0F3A6B,
1403   PREFIX_VEX_0F3A6C,
1404   PREFIX_VEX_0F3A6D,
1405   PREFIX_VEX_0F3A6E,
1406   PREFIX_VEX_0F3A6F,
1407   PREFIX_VEX_0F3A78,
1408   PREFIX_VEX_0F3A79,
1409   PREFIX_VEX_0F3A7A,
1410   PREFIX_VEX_0F3A7B,
1411   PREFIX_VEX_0F3A7C,
1412   PREFIX_VEX_0F3A7D,
1413   PREFIX_VEX_0F3A7E,
1414   PREFIX_VEX_0F3A7F,
1415   PREFIX_VEX_0F3ACE,
1416   PREFIX_VEX_0F3ACF,
1417   PREFIX_VEX_0F3ADF,
1418   PREFIX_VEX_0F3AF0,
1419
1420   PREFIX_EVEX_0F10,
1421   PREFIX_EVEX_0F11,
1422   PREFIX_EVEX_0F12,
1423   PREFIX_EVEX_0F13,
1424   PREFIX_EVEX_0F14,
1425   PREFIX_EVEX_0F15,
1426   PREFIX_EVEX_0F16,
1427   PREFIX_EVEX_0F17,
1428   PREFIX_EVEX_0F28,
1429   PREFIX_EVEX_0F29,
1430   PREFIX_EVEX_0F2A,
1431   PREFIX_EVEX_0F2B,
1432   PREFIX_EVEX_0F2C,
1433   PREFIX_EVEX_0F2D,
1434   PREFIX_EVEX_0F2E,
1435   PREFIX_EVEX_0F2F,
1436   PREFIX_EVEX_0F51,
1437   PREFIX_EVEX_0F54,
1438   PREFIX_EVEX_0F55,
1439   PREFIX_EVEX_0F56,
1440   PREFIX_EVEX_0F57,
1441   PREFIX_EVEX_0F58,
1442   PREFIX_EVEX_0F59,
1443   PREFIX_EVEX_0F5A,
1444   PREFIX_EVEX_0F5B,
1445   PREFIX_EVEX_0F5C,
1446   PREFIX_EVEX_0F5D,
1447   PREFIX_EVEX_0F5E,
1448   PREFIX_EVEX_0F5F,
1449   PREFIX_EVEX_0F60,
1450   PREFIX_EVEX_0F61,
1451   PREFIX_EVEX_0F62,
1452   PREFIX_EVEX_0F63,
1453   PREFIX_EVEX_0F64,
1454   PREFIX_EVEX_0F65,
1455   PREFIX_EVEX_0F66,
1456   PREFIX_EVEX_0F67,
1457   PREFIX_EVEX_0F68,
1458   PREFIX_EVEX_0F69,
1459   PREFIX_EVEX_0F6A,
1460   PREFIX_EVEX_0F6B,
1461   PREFIX_EVEX_0F6C,
1462   PREFIX_EVEX_0F6D,
1463   PREFIX_EVEX_0F6E,
1464   PREFIX_EVEX_0F6F,
1465   PREFIX_EVEX_0F70,
1466   PREFIX_EVEX_0F71_REG_2,
1467   PREFIX_EVEX_0F71_REG_4,
1468   PREFIX_EVEX_0F71_REG_6,
1469   PREFIX_EVEX_0F72_REG_0,
1470   PREFIX_EVEX_0F72_REG_1,
1471   PREFIX_EVEX_0F72_REG_2,
1472   PREFIX_EVEX_0F72_REG_4,
1473   PREFIX_EVEX_0F72_REG_6,
1474   PREFIX_EVEX_0F73_REG_2,
1475   PREFIX_EVEX_0F73_REG_3,
1476   PREFIX_EVEX_0F73_REG_6,
1477   PREFIX_EVEX_0F73_REG_7,
1478   PREFIX_EVEX_0F74,
1479   PREFIX_EVEX_0F75,
1480   PREFIX_EVEX_0F76,
1481   PREFIX_EVEX_0F78,
1482   PREFIX_EVEX_0F79,
1483   PREFIX_EVEX_0F7A,
1484   PREFIX_EVEX_0F7B,
1485   PREFIX_EVEX_0F7E,
1486   PREFIX_EVEX_0F7F,
1487   PREFIX_EVEX_0FC2,
1488   PREFIX_EVEX_0FC4,
1489   PREFIX_EVEX_0FC5,
1490   PREFIX_EVEX_0FC6,
1491   PREFIX_EVEX_0FD1,
1492   PREFIX_EVEX_0FD2,
1493   PREFIX_EVEX_0FD3,
1494   PREFIX_EVEX_0FD4,
1495   PREFIX_EVEX_0FD5,
1496   PREFIX_EVEX_0FD6,
1497   PREFIX_EVEX_0FD8,
1498   PREFIX_EVEX_0FD9,
1499   PREFIX_EVEX_0FDA,
1500   PREFIX_EVEX_0FDB,
1501   PREFIX_EVEX_0FDC,
1502   PREFIX_EVEX_0FDD,
1503   PREFIX_EVEX_0FDE,
1504   PREFIX_EVEX_0FDF,
1505   PREFIX_EVEX_0FE0,
1506   PREFIX_EVEX_0FE1,
1507   PREFIX_EVEX_0FE2,
1508   PREFIX_EVEX_0FE3,
1509   PREFIX_EVEX_0FE4,
1510   PREFIX_EVEX_0FE5,
1511   PREFIX_EVEX_0FE6,
1512   PREFIX_EVEX_0FE7,
1513   PREFIX_EVEX_0FE8,
1514   PREFIX_EVEX_0FE9,
1515   PREFIX_EVEX_0FEA,
1516   PREFIX_EVEX_0FEB,
1517   PREFIX_EVEX_0FEC,
1518   PREFIX_EVEX_0FED,
1519   PREFIX_EVEX_0FEE,
1520   PREFIX_EVEX_0FEF,
1521   PREFIX_EVEX_0FF1,
1522   PREFIX_EVEX_0FF2,
1523   PREFIX_EVEX_0FF3,
1524   PREFIX_EVEX_0FF4,
1525   PREFIX_EVEX_0FF5,
1526   PREFIX_EVEX_0FF6,
1527   PREFIX_EVEX_0FF8,
1528   PREFIX_EVEX_0FF9,
1529   PREFIX_EVEX_0FFA,
1530   PREFIX_EVEX_0FFB,
1531   PREFIX_EVEX_0FFC,
1532   PREFIX_EVEX_0FFD,
1533   PREFIX_EVEX_0FFE,
1534   PREFIX_EVEX_0F3800,
1535   PREFIX_EVEX_0F3804,
1536   PREFIX_EVEX_0F380B,
1537   PREFIX_EVEX_0F380C,
1538   PREFIX_EVEX_0F380D,
1539   PREFIX_EVEX_0F3810,
1540   PREFIX_EVEX_0F3811,
1541   PREFIX_EVEX_0F3812,
1542   PREFIX_EVEX_0F3813,
1543   PREFIX_EVEX_0F3814,
1544   PREFIX_EVEX_0F3815,
1545   PREFIX_EVEX_0F3816,
1546   PREFIX_EVEX_0F3818,
1547   PREFIX_EVEX_0F3819,
1548   PREFIX_EVEX_0F381A,
1549   PREFIX_EVEX_0F381B,
1550   PREFIX_EVEX_0F381C,
1551   PREFIX_EVEX_0F381D,
1552   PREFIX_EVEX_0F381E,
1553   PREFIX_EVEX_0F381F,
1554   PREFIX_EVEX_0F3820,
1555   PREFIX_EVEX_0F3821,
1556   PREFIX_EVEX_0F3822,
1557   PREFIX_EVEX_0F3823,
1558   PREFIX_EVEX_0F3824,
1559   PREFIX_EVEX_0F3825,
1560   PREFIX_EVEX_0F3826,
1561   PREFIX_EVEX_0F3827,
1562   PREFIX_EVEX_0F3828,
1563   PREFIX_EVEX_0F3829,
1564   PREFIX_EVEX_0F382A,
1565   PREFIX_EVEX_0F382B,
1566   PREFIX_EVEX_0F382C,
1567   PREFIX_EVEX_0F382D,
1568   PREFIX_EVEX_0F3830,
1569   PREFIX_EVEX_0F3831,
1570   PREFIX_EVEX_0F3832,
1571   PREFIX_EVEX_0F3833,
1572   PREFIX_EVEX_0F3834,
1573   PREFIX_EVEX_0F3835,
1574   PREFIX_EVEX_0F3836,
1575   PREFIX_EVEX_0F3837,
1576   PREFIX_EVEX_0F3838,
1577   PREFIX_EVEX_0F3839,
1578   PREFIX_EVEX_0F383A,
1579   PREFIX_EVEX_0F383B,
1580   PREFIX_EVEX_0F383C,
1581   PREFIX_EVEX_0F383D,
1582   PREFIX_EVEX_0F383E,
1583   PREFIX_EVEX_0F383F,
1584   PREFIX_EVEX_0F3840,
1585   PREFIX_EVEX_0F3842,
1586   PREFIX_EVEX_0F3843,
1587   PREFIX_EVEX_0F3844,
1588   PREFIX_EVEX_0F3845,
1589   PREFIX_EVEX_0F3846,
1590   PREFIX_EVEX_0F3847,
1591   PREFIX_EVEX_0F384C,
1592   PREFIX_EVEX_0F384D,
1593   PREFIX_EVEX_0F384E,
1594   PREFIX_EVEX_0F384F,
1595   PREFIX_EVEX_0F3850,
1596   PREFIX_EVEX_0F3851,
1597   PREFIX_EVEX_0F3852,
1598   PREFIX_EVEX_0F3853,
1599   PREFIX_EVEX_0F3854,
1600   PREFIX_EVEX_0F3855,
1601   PREFIX_EVEX_0F3858,
1602   PREFIX_EVEX_0F3859,
1603   PREFIX_EVEX_0F385A,
1604   PREFIX_EVEX_0F385B,
1605   PREFIX_EVEX_0F3862,
1606   PREFIX_EVEX_0F3863,
1607   PREFIX_EVEX_0F3864,
1608   PREFIX_EVEX_0F3865,
1609   PREFIX_EVEX_0F3866,
1610   PREFIX_EVEX_0F3868,
1611   PREFIX_EVEX_0F3870,
1612   PREFIX_EVEX_0F3871,
1613   PREFIX_EVEX_0F3872,
1614   PREFIX_EVEX_0F3873,
1615   PREFIX_EVEX_0F3875,
1616   PREFIX_EVEX_0F3876,
1617   PREFIX_EVEX_0F3877,
1618   PREFIX_EVEX_0F3878,
1619   PREFIX_EVEX_0F3879,
1620   PREFIX_EVEX_0F387A,
1621   PREFIX_EVEX_0F387B,
1622   PREFIX_EVEX_0F387C,
1623   PREFIX_EVEX_0F387D,
1624   PREFIX_EVEX_0F387E,
1625   PREFIX_EVEX_0F387F,
1626   PREFIX_EVEX_0F3883,
1627   PREFIX_EVEX_0F3888,
1628   PREFIX_EVEX_0F3889,
1629   PREFIX_EVEX_0F388A,
1630   PREFIX_EVEX_0F388B,
1631   PREFIX_EVEX_0F388D,
1632   PREFIX_EVEX_0F388F,
1633   PREFIX_EVEX_0F3890,
1634   PREFIX_EVEX_0F3891,
1635   PREFIX_EVEX_0F3892,
1636   PREFIX_EVEX_0F3893,
1637   PREFIX_EVEX_0F3896,
1638   PREFIX_EVEX_0F3897,
1639   PREFIX_EVEX_0F3898,
1640   PREFIX_EVEX_0F3899,
1641   PREFIX_EVEX_0F389A,
1642   PREFIX_EVEX_0F389B,
1643   PREFIX_EVEX_0F389C,
1644   PREFIX_EVEX_0F389D,
1645   PREFIX_EVEX_0F389E,
1646   PREFIX_EVEX_0F389F,
1647   PREFIX_EVEX_0F38A0,
1648   PREFIX_EVEX_0F38A1,
1649   PREFIX_EVEX_0F38A2,
1650   PREFIX_EVEX_0F38A3,
1651   PREFIX_EVEX_0F38A6,
1652   PREFIX_EVEX_0F38A7,
1653   PREFIX_EVEX_0F38A8,
1654   PREFIX_EVEX_0F38A9,
1655   PREFIX_EVEX_0F38AA,
1656   PREFIX_EVEX_0F38AB,
1657   PREFIX_EVEX_0F38AC,
1658   PREFIX_EVEX_0F38AD,
1659   PREFIX_EVEX_0F38AE,
1660   PREFIX_EVEX_0F38AF,
1661   PREFIX_EVEX_0F38B4,
1662   PREFIX_EVEX_0F38B5,
1663   PREFIX_EVEX_0F38B6,
1664   PREFIX_EVEX_0F38B7,
1665   PREFIX_EVEX_0F38B8,
1666   PREFIX_EVEX_0F38B9,
1667   PREFIX_EVEX_0F38BA,
1668   PREFIX_EVEX_0F38BB,
1669   PREFIX_EVEX_0F38BC,
1670   PREFIX_EVEX_0F38BD,
1671   PREFIX_EVEX_0F38BE,
1672   PREFIX_EVEX_0F38BF,
1673   PREFIX_EVEX_0F38C4,
1674   PREFIX_EVEX_0F38C6_REG_1,
1675   PREFIX_EVEX_0F38C6_REG_2,
1676   PREFIX_EVEX_0F38C6_REG_5,
1677   PREFIX_EVEX_0F38C6_REG_6,
1678   PREFIX_EVEX_0F38C7_REG_1,
1679   PREFIX_EVEX_0F38C7_REG_2,
1680   PREFIX_EVEX_0F38C7_REG_5,
1681   PREFIX_EVEX_0F38C7_REG_6,
1682   PREFIX_EVEX_0F38C8,
1683   PREFIX_EVEX_0F38CA,
1684   PREFIX_EVEX_0F38CB,
1685   PREFIX_EVEX_0F38CC,
1686   PREFIX_EVEX_0F38CD,
1687   PREFIX_EVEX_0F38CF,
1688   PREFIX_EVEX_0F38DC,
1689   PREFIX_EVEX_0F38DD,
1690   PREFIX_EVEX_0F38DE,
1691   PREFIX_EVEX_0F38DF,
1692
1693   PREFIX_EVEX_0F3A00,
1694   PREFIX_EVEX_0F3A01,
1695   PREFIX_EVEX_0F3A03,
1696   PREFIX_EVEX_0F3A04,
1697   PREFIX_EVEX_0F3A05,
1698   PREFIX_EVEX_0F3A08,
1699   PREFIX_EVEX_0F3A09,
1700   PREFIX_EVEX_0F3A0A,
1701   PREFIX_EVEX_0F3A0B,
1702   PREFIX_EVEX_0F3A0F,
1703   PREFIX_EVEX_0F3A14,
1704   PREFIX_EVEX_0F3A15,
1705   PREFIX_EVEX_0F3A16,
1706   PREFIX_EVEX_0F3A17,
1707   PREFIX_EVEX_0F3A18,
1708   PREFIX_EVEX_0F3A19,
1709   PREFIX_EVEX_0F3A1A,
1710   PREFIX_EVEX_0F3A1B,
1711   PREFIX_EVEX_0F3A1D,
1712   PREFIX_EVEX_0F3A1E,
1713   PREFIX_EVEX_0F3A1F,
1714   PREFIX_EVEX_0F3A20,
1715   PREFIX_EVEX_0F3A21,
1716   PREFIX_EVEX_0F3A22,
1717   PREFIX_EVEX_0F3A23,
1718   PREFIX_EVEX_0F3A25,
1719   PREFIX_EVEX_0F3A26,
1720   PREFIX_EVEX_0F3A27,
1721   PREFIX_EVEX_0F3A38,
1722   PREFIX_EVEX_0F3A39,
1723   PREFIX_EVEX_0F3A3A,
1724   PREFIX_EVEX_0F3A3B,
1725   PREFIX_EVEX_0F3A3E,
1726   PREFIX_EVEX_0F3A3F,
1727   PREFIX_EVEX_0F3A42,
1728   PREFIX_EVEX_0F3A43,
1729   PREFIX_EVEX_0F3A44,
1730   PREFIX_EVEX_0F3A50,
1731   PREFIX_EVEX_0F3A51,
1732   PREFIX_EVEX_0F3A54,
1733   PREFIX_EVEX_0F3A55,
1734   PREFIX_EVEX_0F3A56,
1735   PREFIX_EVEX_0F3A57,
1736   PREFIX_EVEX_0F3A66,
1737   PREFIX_EVEX_0F3A67,
1738   PREFIX_EVEX_0F3A70,
1739   PREFIX_EVEX_0F3A71,
1740   PREFIX_EVEX_0F3A72,
1741   PREFIX_EVEX_0F3A73,
1742   PREFIX_EVEX_0F3ACE,
1743   PREFIX_EVEX_0F3ACF
1744 };
1745
1746 enum
1747 {
1748   X86_64_06 = 0,
1749   X86_64_07,
1750   X86_64_0D,
1751   X86_64_16,
1752   X86_64_17,
1753   X86_64_1E,
1754   X86_64_1F,
1755   X86_64_27,
1756   X86_64_2F,
1757   X86_64_37,
1758   X86_64_3F,
1759   X86_64_60,
1760   X86_64_61,
1761   X86_64_62,
1762   X86_64_63,
1763   X86_64_6D,
1764   X86_64_6F,
1765   X86_64_82,
1766   X86_64_9A,
1767   X86_64_C2,
1768   X86_64_C3,
1769   X86_64_C4,
1770   X86_64_C5,
1771   X86_64_CE,
1772   X86_64_D4,
1773   X86_64_D5,
1774   X86_64_E8,
1775   X86_64_E9,
1776   X86_64_EA,
1777   X86_64_0F01_REG_0,
1778   X86_64_0F01_REG_1,
1779   X86_64_0F01_REG_2,
1780   X86_64_0F01_REG_3
1781 };
1782
1783 enum
1784 {
1785   THREE_BYTE_0F38 = 0,
1786   THREE_BYTE_0F3A
1787 };
1788
1789 enum
1790 {
1791   XOP_08 = 0,
1792   XOP_09,
1793   XOP_0A
1794 };
1795
1796 enum
1797 {
1798   VEX_0F = 0,
1799   VEX_0F38,
1800   VEX_0F3A
1801 };
1802
1803 enum
1804 {
1805   EVEX_0F = 0,
1806   EVEX_0F38,
1807   EVEX_0F3A
1808 };
1809
1810 enum
1811 {
1812   VEX_LEN_0F12_P_0_M_0 = 0,
1813   VEX_LEN_0F12_P_0_M_1,
1814   VEX_LEN_0F12_P_2,
1815   VEX_LEN_0F13_M_0,
1816   VEX_LEN_0F16_P_0_M_0,
1817   VEX_LEN_0F16_P_0_M_1,
1818   VEX_LEN_0F16_P_2,
1819   VEX_LEN_0F17_M_0,
1820   VEX_LEN_0F41_P_0,
1821   VEX_LEN_0F41_P_2,
1822   VEX_LEN_0F42_P_0,
1823   VEX_LEN_0F42_P_2,
1824   VEX_LEN_0F44_P_0,
1825   VEX_LEN_0F44_P_2,
1826   VEX_LEN_0F45_P_0,
1827   VEX_LEN_0F45_P_2,
1828   VEX_LEN_0F46_P_0,
1829   VEX_LEN_0F46_P_2,
1830   VEX_LEN_0F47_P_0,
1831   VEX_LEN_0F47_P_2,
1832   VEX_LEN_0F4A_P_0,
1833   VEX_LEN_0F4A_P_2,
1834   VEX_LEN_0F4B_P_0,
1835   VEX_LEN_0F4B_P_2,
1836   VEX_LEN_0F6E_P_2,
1837   VEX_LEN_0F77_P_0,
1838   VEX_LEN_0F7E_P_1,
1839   VEX_LEN_0F7E_P_2,
1840   VEX_LEN_0F90_P_0,
1841   VEX_LEN_0F90_P_2,
1842   VEX_LEN_0F91_P_0,
1843   VEX_LEN_0F91_P_2,
1844   VEX_LEN_0F92_P_0,
1845   VEX_LEN_0F92_P_2,
1846   VEX_LEN_0F92_P_3,
1847   VEX_LEN_0F93_P_0,
1848   VEX_LEN_0F93_P_2,
1849   VEX_LEN_0F93_P_3,
1850   VEX_LEN_0F98_P_0,
1851   VEX_LEN_0F98_P_2,
1852   VEX_LEN_0F99_P_0,
1853   VEX_LEN_0F99_P_2,
1854   VEX_LEN_0FAE_R_2_M_0,
1855   VEX_LEN_0FAE_R_3_M_0,
1856   VEX_LEN_0FC4_P_2,
1857   VEX_LEN_0FC5_P_2,
1858   VEX_LEN_0FD6_P_2,
1859   VEX_LEN_0FF7_P_2,
1860   VEX_LEN_0F3816_P_2,
1861   VEX_LEN_0F3819_P_2,
1862   VEX_LEN_0F381A_P_2_M_0,
1863   VEX_LEN_0F3836_P_2,
1864   VEX_LEN_0F3841_P_2,
1865   VEX_LEN_0F385A_P_2_M_0,
1866   VEX_LEN_0F38DB_P_2,
1867   VEX_LEN_0F38F2_P_0,
1868   VEX_LEN_0F38F3_R_1_P_0,
1869   VEX_LEN_0F38F3_R_2_P_0,
1870   VEX_LEN_0F38F3_R_3_P_0,
1871   VEX_LEN_0F38F5_P_0,
1872   VEX_LEN_0F38F5_P_1,
1873   VEX_LEN_0F38F5_P_3,
1874   VEX_LEN_0F38F6_P_3,
1875   VEX_LEN_0F38F7_P_0,
1876   VEX_LEN_0F38F7_P_1,
1877   VEX_LEN_0F38F7_P_2,
1878   VEX_LEN_0F38F7_P_3,
1879   VEX_LEN_0F3A00_P_2,
1880   VEX_LEN_0F3A01_P_2,
1881   VEX_LEN_0F3A06_P_2,
1882   VEX_LEN_0F3A14_P_2,
1883   VEX_LEN_0F3A15_P_2,
1884   VEX_LEN_0F3A16_P_2,
1885   VEX_LEN_0F3A17_P_2,
1886   VEX_LEN_0F3A18_P_2,
1887   VEX_LEN_0F3A19_P_2,
1888   VEX_LEN_0F3A20_P_2,
1889   VEX_LEN_0F3A21_P_2,
1890   VEX_LEN_0F3A22_P_2,
1891   VEX_LEN_0F3A30_P_2,
1892   VEX_LEN_0F3A31_P_2,
1893   VEX_LEN_0F3A32_P_2,
1894   VEX_LEN_0F3A33_P_2,
1895   VEX_LEN_0F3A38_P_2,
1896   VEX_LEN_0F3A39_P_2,
1897   VEX_LEN_0F3A41_P_2,
1898   VEX_LEN_0F3A46_P_2,
1899   VEX_LEN_0F3A60_P_2,
1900   VEX_LEN_0F3A61_P_2,
1901   VEX_LEN_0F3A62_P_2,
1902   VEX_LEN_0F3A63_P_2,
1903   VEX_LEN_0F3A6A_P_2,
1904   VEX_LEN_0F3A6B_P_2,
1905   VEX_LEN_0F3A6E_P_2,
1906   VEX_LEN_0F3A6F_P_2,
1907   VEX_LEN_0F3A7A_P_2,
1908   VEX_LEN_0F3A7B_P_2,
1909   VEX_LEN_0F3A7E_P_2,
1910   VEX_LEN_0F3A7F_P_2,
1911   VEX_LEN_0F3ADF_P_2,
1912   VEX_LEN_0F3AF0_P_3,
1913   VEX_LEN_0FXOP_08_CC,
1914   VEX_LEN_0FXOP_08_CD,
1915   VEX_LEN_0FXOP_08_CE,
1916   VEX_LEN_0FXOP_08_CF,
1917   VEX_LEN_0FXOP_08_EC,
1918   VEX_LEN_0FXOP_08_ED,
1919   VEX_LEN_0FXOP_08_EE,
1920   VEX_LEN_0FXOP_08_EF,
1921   VEX_LEN_0FXOP_09_80,
1922   VEX_LEN_0FXOP_09_81
1923 };
1924
1925 enum
1926 {
1927   EVEX_LEN_0F6E_P_2 = 0,
1928   EVEX_LEN_0F7E_P_1,
1929   EVEX_LEN_0F7E_P_2,
1930   EVEX_LEN_0FD6_P_2,
1931   EVEX_LEN_0F3819_P_2_W_0,
1932   EVEX_LEN_0F3819_P_2_W_1,
1933   EVEX_LEN_0F381A_P_2_W_0,
1934   EVEX_LEN_0F381A_P_2_W_1,
1935   EVEX_LEN_0F381B_P_2_W_0,
1936   EVEX_LEN_0F381B_P_2_W_1,
1937   EVEX_LEN_0F385A_P_2_W_0,
1938   EVEX_LEN_0F385A_P_2_W_1,
1939   EVEX_LEN_0F385B_P_2_W_0,
1940   EVEX_LEN_0F385B_P_2_W_1,
1941   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1942   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1943   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1944   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1945   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1946   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1947   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1948   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1949   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1950   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1951   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1952   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1953   EVEX_LEN_0F3A18_P_2_W_0,
1954   EVEX_LEN_0F3A18_P_2_W_1,
1955   EVEX_LEN_0F3A19_P_2_W_0,
1956   EVEX_LEN_0F3A19_P_2_W_1,
1957   EVEX_LEN_0F3A1A_P_2_W_0,
1958   EVEX_LEN_0F3A1A_P_2_W_1,
1959   EVEX_LEN_0F3A1B_P_2_W_0,
1960   EVEX_LEN_0F3A1B_P_2_W_1,
1961   EVEX_LEN_0F3A23_P_2_W_0,
1962   EVEX_LEN_0F3A23_P_2_W_1,
1963   EVEX_LEN_0F3A38_P_2_W_0,
1964   EVEX_LEN_0F3A38_P_2_W_1,
1965   EVEX_LEN_0F3A39_P_2_W_0,
1966   EVEX_LEN_0F3A39_P_2_W_1,
1967   EVEX_LEN_0F3A3A_P_2_W_0,
1968   EVEX_LEN_0F3A3A_P_2_W_1,
1969   EVEX_LEN_0F3A3B_P_2_W_0,
1970   EVEX_LEN_0F3A3B_P_2_W_1,
1971   EVEX_LEN_0F3A43_P_2_W_0,
1972   EVEX_LEN_0F3A43_P_2_W_1
1973 };
1974
1975 enum
1976 {
1977   VEX_W_0F41_P_0_LEN_1 = 0,
1978   VEX_W_0F41_P_2_LEN_1,
1979   VEX_W_0F42_P_0_LEN_1,
1980   VEX_W_0F42_P_2_LEN_1,
1981   VEX_W_0F44_P_0_LEN_0,
1982   VEX_W_0F44_P_2_LEN_0,
1983   VEX_W_0F45_P_0_LEN_1,
1984   VEX_W_0F45_P_2_LEN_1,
1985   VEX_W_0F46_P_0_LEN_1,
1986   VEX_W_0F46_P_2_LEN_1,
1987   VEX_W_0F47_P_0_LEN_1,
1988   VEX_W_0F47_P_2_LEN_1,
1989   VEX_W_0F4A_P_0_LEN_1,
1990   VEX_W_0F4A_P_2_LEN_1,
1991   VEX_W_0F4B_P_0_LEN_1,
1992   VEX_W_0F4B_P_2_LEN_1,
1993   VEX_W_0F90_P_0_LEN_0,
1994   VEX_W_0F90_P_2_LEN_0,
1995   VEX_W_0F91_P_0_LEN_0,
1996   VEX_W_0F91_P_2_LEN_0,
1997   VEX_W_0F92_P_0_LEN_0,
1998   VEX_W_0F92_P_2_LEN_0,
1999   VEX_W_0F93_P_0_LEN_0,
2000   VEX_W_0F93_P_2_LEN_0,
2001   VEX_W_0F98_P_0_LEN_0,
2002   VEX_W_0F98_P_2_LEN_0,
2003   VEX_W_0F99_P_0_LEN_0,
2004   VEX_W_0F99_P_2_LEN_0,
2005   VEX_W_0F380C_P_2,
2006   VEX_W_0F380D_P_2,
2007   VEX_W_0F380E_P_2,
2008   VEX_W_0F380F_P_2,
2009   VEX_W_0F3816_P_2,
2010   VEX_W_0F3818_P_2,
2011   VEX_W_0F3819_P_2,
2012   VEX_W_0F381A_P_2_M_0,
2013   VEX_W_0F382C_P_2_M_0,
2014   VEX_W_0F382D_P_2_M_0,
2015   VEX_W_0F382E_P_2_M_0,
2016   VEX_W_0F382F_P_2_M_0,
2017   VEX_W_0F3836_P_2,
2018   VEX_W_0F3846_P_2,
2019   VEX_W_0F3858_P_2,
2020   VEX_W_0F3859_P_2,
2021   VEX_W_0F385A_P_2_M_0,
2022   VEX_W_0F3878_P_2,
2023   VEX_W_0F3879_P_2,
2024   VEX_W_0F38CF_P_2,
2025   VEX_W_0F3A00_P_2,
2026   VEX_W_0F3A01_P_2,
2027   VEX_W_0F3A02_P_2,
2028   VEX_W_0F3A04_P_2,
2029   VEX_W_0F3A05_P_2,
2030   VEX_W_0F3A06_P_2,
2031   VEX_W_0F3A18_P_2,
2032   VEX_W_0F3A19_P_2,
2033   VEX_W_0F3A30_P_2_LEN_0,
2034   VEX_W_0F3A31_P_2_LEN_0,
2035   VEX_W_0F3A32_P_2_LEN_0,
2036   VEX_W_0F3A33_P_2_LEN_0,
2037   VEX_W_0F3A38_P_2,
2038   VEX_W_0F3A39_P_2,
2039   VEX_W_0F3A46_P_2,
2040   VEX_W_0F3A48_P_2,
2041   VEX_W_0F3A49_P_2,
2042   VEX_W_0F3A4A_P_2,
2043   VEX_W_0F3A4B_P_2,
2044   VEX_W_0F3A4C_P_2,
2045   VEX_W_0F3ACE_P_2,
2046   VEX_W_0F3ACF_P_2,
2047
2048   EVEX_W_0F10_P_0,
2049   EVEX_W_0F10_P_1,
2050   EVEX_W_0F10_P_2,
2051   EVEX_W_0F10_P_3,
2052   EVEX_W_0F11_P_0,
2053   EVEX_W_0F11_P_1,
2054   EVEX_W_0F11_P_2,
2055   EVEX_W_0F11_P_3,
2056   EVEX_W_0F12_P_0_M_0,
2057   EVEX_W_0F12_P_0_M_1,
2058   EVEX_W_0F12_P_1,
2059   EVEX_W_0F12_P_2,
2060   EVEX_W_0F12_P_3,
2061   EVEX_W_0F13_P_0,
2062   EVEX_W_0F13_P_2,
2063   EVEX_W_0F14_P_0,
2064   EVEX_W_0F14_P_2,
2065   EVEX_W_0F15_P_0,
2066   EVEX_W_0F15_P_2,
2067   EVEX_W_0F16_P_0_M_0,
2068   EVEX_W_0F16_P_0_M_1,
2069   EVEX_W_0F16_P_1,
2070   EVEX_W_0F16_P_2,
2071   EVEX_W_0F17_P_0,
2072   EVEX_W_0F17_P_2,
2073   EVEX_W_0F28_P_0,
2074   EVEX_W_0F28_P_2,
2075   EVEX_W_0F29_P_0,
2076   EVEX_W_0F29_P_2,
2077   EVEX_W_0F2A_P_3,
2078   EVEX_W_0F2B_P_0,
2079   EVEX_W_0F2B_P_2,
2080   EVEX_W_0F2E_P_0,
2081   EVEX_W_0F2E_P_2,
2082   EVEX_W_0F2F_P_0,
2083   EVEX_W_0F2F_P_2,
2084   EVEX_W_0F51_P_0,
2085   EVEX_W_0F51_P_1,
2086   EVEX_W_0F51_P_2,
2087   EVEX_W_0F51_P_3,
2088   EVEX_W_0F54_P_0,
2089   EVEX_W_0F54_P_2,
2090   EVEX_W_0F55_P_0,
2091   EVEX_W_0F55_P_2,
2092   EVEX_W_0F56_P_0,
2093   EVEX_W_0F56_P_2,
2094   EVEX_W_0F57_P_0,
2095   EVEX_W_0F57_P_2,
2096   EVEX_W_0F58_P_0,
2097   EVEX_W_0F58_P_1,
2098   EVEX_W_0F58_P_2,
2099   EVEX_W_0F58_P_3,
2100   EVEX_W_0F59_P_0,
2101   EVEX_W_0F59_P_1,
2102   EVEX_W_0F59_P_2,
2103   EVEX_W_0F59_P_3,
2104   EVEX_W_0F5A_P_0,
2105   EVEX_W_0F5A_P_1,
2106   EVEX_W_0F5A_P_2,
2107   EVEX_W_0F5A_P_3,
2108   EVEX_W_0F5B_P_0,
2109   EVEX_W_0F5B_P_1,
2110   EVEX_W_0F5B_P_2,
2111   EVEX_W_0F5C_P_0,
2112   EVEX_W_0F5C_P_1,
2113   EVEX_W_0F5C_P_2,
2114   EVEX_W_0F5C_P_3,
2115   EVEX_W_0F5D_P_0,
2116   EVEX_W_0F5D_P_1,
2117   EVEX_W_0F5D_P_2,
2118   EVEX_W_0F5D_P_3,
2119   EVEX_W_0F5E_P_0,
2120   EVEX_W_0F5E_P_1,
2121   EVEX_W_0F5E_P_2,
2122   EVEX_W_0F5E_P_3,
2123   EVEX_W_0F5F_P_0,
2124   EVEX_W_0F5F_P_1,
2125   EVEX_W_0F5F_P_2,
2126   EVEX_W_0F5F_P_3,
2127   EVEX_W_0F62_P_2,
2128   EVEX_W_0F66_P_2,
2129   EVEX_W_0F6A_P_2,
2130   EVEX_W_0F6B_P_2,
2131   EVEX_W_0F6C_P_2,
2132   EVEX_W_0F6D_P_2,
2133   EVEX_W_0F6F_P_1,
2134   EVEX_W_0F6F_P_2,
2135   EVEX_W_0F6F_P_3,
2136   EVEX_W_0F70_P_2,
2137   EVEX_W_0F72_R_2_P_2,
2138   EVEX_W_0F72_R_6_P_2,
2139   EVEX_W_0F73_R_2_P_2,
2140   EVEX_W_0F73_R_6_P_2,
2141   EVEX_W_0F76_P_2,
2142   EVEX_W_0F78_P_0,
2143   EVEX_W_0F78_P_2,
2144   EVEX_W_0F79_P_0,
2145   EVEX_W_0F79_P_2,
2146   EVEX_W_0F7A_P_1,
2147   EVEX_W_0F7A_P_2,
2148   EVEX_W_0F7A_P_3,
2149   EVEX_W_0F7B_P_2,
2150   EVEX_W_0F7B_P_3,
2151   EVEX_W_0F7E_P_1,
2152   EVEX_W_0F7F_P_1,
2153   EVEX_W_0F7F_P_2,
2154   EVEX_W_0F7F_P_3,
2155   EVEX_W_0FC2_P_0,
2156   EVEX_W_0FC2_P_1,
2157   EVEX_W_0FC2_P_2,
2158   EVEX_W_0FC2_P_3,
2159   EVEX_W_0FC6_P_0,
2160   EVEX_W_0FC6_P_2,
2161   EVEX_W_0FD2_P_2,
2162   EVEX_W_0FD3_P_2,
2163   EVEX_W_0FD4_P_2,
2164   EVEX_W_0FD6_P_2,
2165   EVEX_W_0FE6_P_1,
2166   EVEX_W_0FE6_P_2,
2167   EVEX_W_0FE6_P_3,
2168   EVEX_W_0FE7_P_2,
2169   EVEX_W_0FF2_P_2,
2170   EVEX_W_0FF3_P_2,
2171   EVEX_W_0FF4_P_2,
2172   EVEX_W_0FFA_P_2,
2173   EVEX_W_0FFB_P_2,
2174   EVEX_W_0FFE_P_2,
2175   EVEX_W_0F380C_P_2,
2176   EVEX_W_0F380D_P_2,
2177   EVEX_W_0F3810_P_1,
2178   EVEX_W_0F3810_P_2,
2179   EVEX_W_0F3811_P_1,
2180   EVEX_W_0F3811_P_2,
2181   EVEX_W_0F3812_P_1,
2182   EVEX_W_0F3812_P_2,
2183   EVEX_W_0F3813_P_1,
2184   EVEX_W_0F3813_P_2,
2185   EVEX_W_0F3814_P_1,
2186   EVEX_W_0F3815_P_1,
2187   EVEX_W_0F3818_P_2,
2188   EVEX_W_0F3819_P_2,
2189   EVEX_W_0F381A_P_2,
2190   EVEX_W_0F381B_P_2,
2191   EVEX_W_0F381E_P_2,
2192   EVEX_W_0F381F_P_2,
2193   EVEX_W_0F3820_P_1,
2194   EVEX_W_0F3821_P_1,
2195   EVEX_W_0F3822_P_1,
2196   EVEX_W_0F3823_P_1,
2197   EVEX_W_0F3824_P_1,
2198   EVEX_W_0F3825_P_1,
2199   EVEX_W_0F3825_P_2,
2200   EVEX_W_0F3826_P_1,
2201   EVEX_W_0F3826_P_2,
2202   EVEX_W_0F3828_P_1,
2203   EVEX_W_0F3828_P_2,
2204   EVEX_W_0F3829_P_1,
2205   EVEX_W_0F3829_P_2,
2206   EVEX_W_0F382A_P_1,
2207   EVEX_W_0F382A_P_2,
2208   EVEX_W_0F382B_P_2,
2209   EVEX_W_0F3830_P_1,
2210   EVEX_W_0F3831_P_1,
2211   EVEX_W_0F3832_P_1,
2212   EVEX_W_0F3833_P_1,
2213   EVEX_W_0F3834_P_1,
2214   EVEX_W_0F3835_P_1,
2215   EVEX_W_0F3835_P_2,
2216   EVEX_W_0F3837_P_2,
2217   EVEX_W_0F3838_P_1,
2218   EVEX_W_0F3839_P_1,
2219   EVEX_W_0F383A_P_1,
2220   EVEX_W_0F3840_P_2,
2221   EVEX_W_0F3852_P_1,
2222   EVEX_W_0F3854_P_2,
2223   EVEX_W_0F3855_P_2,
2224   EVEX_W_0F3858_P_2,
2225   EVEX_W_0F3859_P_2,
2226   EVEX_W_0F385A_P_2,
2227   EVEX_W_0F385B_P_2,
2228   EVEX_W_0F3862_P_2,
2229   EVEX_W_0F3863_P_2,
2230   EVEX_W_0F3866_P_2,
2231   EVEX_W_0F3868_P_3,
2232   EVEX_W_0F3870_P_2,
2233   EVEX_W_0F3871_P_2,
2234   EVEX_W_0F3872_P_1,
2235   EVEX_W_0F3872_P_2,
2236   EVEX_W_0F3872_P_3,
2237   EVEX_W_0F3873_P_2,
2238   EVEX_W_0F3875_P_2,
2239   EVEX_W_0F3878_P_2,
2240   EVEX_W_0F3879_P_2,
2241   EVEX_W_0F387A_P_2,
2242   EVEX_W_0F387B_P_2,
2243   EVEX_W_0F387D_P_2,
2244   EVEX_W_0F3883_P_2,
2245   EVEX_W_0F388D_P_2,
2246   EVEX_W_0F3891_P_2,
2247   EVEX_W_0F3893_P_2,
2248   EVEX_W_0F38A1_P_2,
2249   EVEX_W_0F38A3_P_2,
2250   EVEX_W_0F38C7_R_1_P_2,
2251   EVEX_W_0F38C7_R_2_P_2,
2252   EVEX_W_0F38C7_R_5_P_2,
2253   EVEX_W_0F38C7_R_6_P_2,
2254
2255   EVEX_W_0F3A00_P_2,
2256   EVEX_W_0F3A01_P_2,
2257   EVEX_W_0F3A04_P_2,
2258   EVEX_W_0F3A05_P_2,
2259   EVEX_W_0F3A08_P_2,
2260   EVEX_W_0F3A09_P_2,
2261   EVEX_W_0F3A0A_P_2,
2262   EVEX_W_0F3A0B_P_2,
2263   EVEX_W_0F3A18_P_2,
2264   EVEX_W_0F3A19_P_2,
2265   EVEX_W_0F3A1A_P_2,
2266   EVEX_W_0F3A1B_P_2,
2267   EVEX_W_0F3A1D_P_2,
2268   EVEX_W_0F3A21_P_2,
2269   EVEX_W_0F3A23_P_2,
2270   EVEX_W_0F3A38_P_2,
2271   EVEX_W_0F3A39_P_2,
2272   EVEX_W_0F3A3A_P_2,
2273   EVEX_W_0F3A3B_P_2,
2274   EVEX_W_0F3A3E_P_2,
2275   EVEX_W_0F3A3F_P_2,
2276   EVEX_W_0F3A42_P_2,
2277   EVEX_W_0F3A43_P_2,
2278   EVEX_W_0F3A50_P_2,
2279   EVEX_W_0F3A51_P_2,
2280   EVEX_W_0F3A56_P_2,
2281   EVEX_W_0F3A57_P_2,
2282   EVEX_W_0F3A66_P_2,
2283   EVEX_W_0F3A67_P_2,
2284   EVEX_W_0F3A70_P_2,
2285   EVEX_W_0F3A71_P_2,
2286   EVEX_W_0F3A72_P_2,
2287   EVEX_W_0F3A73_P_2,
2288   EVEX_W_0F3ACE_P_2,
2289   EVEX_W_0F3ACF_P_2
2290 };
2291
2292 typedef void (*op_rtn) (int bytemode, int sizeflag);
2293
2294 struct dis386 {
2295   const char *name;
2296   struct
2297     {
2298       op_rtn rtn;
2299       int bytemode;
2300     } op[MAX_OPERANDS];
2301   unsigned int prefix_requirement;
2302 };
2303
2304 /* Upper case letters in the instruction names here are macros.
2305    'A' => print 'b' if no register operands or suffix_always is true
2306    'B' => print 'b' if suffix_always is true
2307    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2308           size prefix
2309    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2310           suffix_always is true
2311    'E' => print 'e' if 32-bit form of jcxz
2312    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2313    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2314    'H' => print ",pt" or ",pn" branch hint
2315    'I' => honor following macro letter even in Intel mode (implemented only
2316           for some of the macro letters)
2317    'J' => print 'l'
2318    'K' => print 'd' or 'q' if rex prefix is present.
2319    'L' => print 'l' if suffix_always is true
2320    'M' => print 'r' if intel_mnemonic is false.
2321    'N' => print 'n' if instruction has no wait "prefix"
2322    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2323    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2324           or suffix_always is true.  print 'q' if rex prefix is present.
2325    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2326           is true
2327    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2328    'S' => print 'w', 'l' or 'q' if suffix_always is true
2329    'T' => print 'q' in 64bit mode if instruction has no operand size
2330           prefix and behave as 'P' otherwise
2331    'U' => print 'q' in 64bit mode if instruction has no operand size
2332           prefix and behave as 'Q' otherwise
2333    'V' => print 'q' in 64bit mode if instruction has no operand size
2334           prefix and behave as 'S' otherwise
2335    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2336    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2337    'Y' unused.
2338    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2339    '!' => change condition from true to false or from false to true.
2340    '%' => add 1 upper case letter to the macro.
2341    '^' => print 'w' or 'l' depending on operand size prefix or
2342           suffix_always is true (lcall/ljmp).
2343    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2344           on operand size prefix.
2345    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2346           has no operand size prefix for AMD64 ISA, behave as 'P'
2347           otherwise
2348
2349    2 upper case letter macros:
2350    "XY" => print 'x' or 'y' if suffix_always is true or no register
2351            operands and no broadcast.
2352    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2353            register operands and no broadcast.
2354    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2355    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2356            or suffix_always is true
2357    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2358    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2359    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2360    "LW" => print 'd', 'q' depending on the VEX.W bit
2361    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2362            an operand size prefix, or suffix_always is true.  print
2363            'q' if rex prefix is present.
2364
2365    Many of the above letters print nothing in Intel mode.  See "putop"
2366    for the details.
2367
2368    Braces '{' and '}', and vertical bars '|', indicate alternative
2369    mnemonic strings for AT&T and Intel.  */
2370
2371 static const struct dis386 dis386[] = {
2372   /* 00 */
2373   { "addB",             { Ebh1, Gb }, 0 },
2374   { "addS",             { Evh1, Gv }, 0 },
2375   { "addB",             { Gb, EbS }, 0 },
2376   { "addS",             { Gv, EvS }, 0 },
2377   { "addB",             { AL, Ib }, 0 },
2378   { "addS",             { eAX, Iv }, 0 },
2379   { X86_64_TABLE (X86_64_06) },
2380   { X86_64_TABLE (X86_64_07) },
2381   /* 08 */
2382   { "orB",              { Ebh1, Gb }, 0 },
2383   { "orS",              { Evh1, Gv }, 0 },
2384   { "orB",              { Gb, EbS }, 0 },
2385   { "orS",              { Gv, EvS }, 0 },
2386   { "orB",              { AL, Ib }, 0 },
2387   { "orS",              { eAX, Iv }, 0 },
2388   { X86_64_TABLE (X86_64_0D) },
2389   { Bad_Opcode },       /* 0x0f extended opcode escape */
2390   /* 10 */
2391   { "adcB",             { Ebh1, Gb }, 0 },
2392   { "adcS",             { Evh1, Gv }, 0 },
2393   { "adcB",             { Gb, EbS }, 0 },
2394   { "adcS",             { Gv, EvS }, 0 },
2395   { "adcB",             { AL, Ib }, 0 },
2396   { "adcS",             { eAX, Iv }, 0 },
2397   { X86_64_TABLE (X86_64_16) },
2398   { X86_64_TABLE (X86_64_17) },
2399   /* 18 */
2400   { "sbbB",             { Ebh1, Gb }, 0 },
2401   { "sbbS",             { Evh1, Gv }, 0 },
2402   { "sbbB",             { Gb, EbS }, 0 },
2403   { "sbbS",             { Gv, EvS }, 0 },
2404   { "sbbB",             { AL, Ib }, 0 },
2405   { "sbbS",             { eAX, Iv }, 0 },
2406   { X86_64_TABLE (X86_64_1E) },
2407   { X86_64_TABLE (X86_64_1F) },
2408   /* 20 */
2409   { "andB",             { Ebh1, Gb }, 0 },
2410   { "andS",             { Evh1, Gv }, 0 },
2411   { "andB",             { Gb, EbS }, 0 },
2412   { "andS",             { Gv, EvS }, 0 },
2413   { "andB",             { AL, Ib }, 0 },
2414   { "andS",             { eAX, Iv }, 0 },
2415   { Bad_Opcode },       /* SEG ES prefix */
2416   { X86_64_TABLE (X86_64_27) },
2417   /* 28 */
2418   { "subB",             { Ebh1, Gb }, 0 },
2419   { "subS",             { Evh1, Gv }, 0 },
2420   { "subB",             { Gb, EbS }, 0 },
2421   { "subS",             { Gv, EvS }, 0 },
2422   { "subB",             { AL, Ib }, 0 },
2423   { "subS",             { eAX, Iv }, 0 },
2424   { Bad_Opcode },       /* SEG CS prefix */
2425   { X86_64_TABLE (X86_64_2F) },
2426   /* 30 */
2427   { "xorB",             { Ebh1, Gb }, 0 },
2428   { "xorS",             { Evh1, Gv }, 0 },
2429   { "xorB",             { Gb, EbS }, 0 },
2430   { "xorS",             { Gv, EvS }, 0 },
2431   { "xorB",             { AL, Ib }, 0 },
2432   { "xorS",             { eAX, Iv }, 0 },
2433   { Bad_Opcode },       /* SEG SS prefix */
2434   { X86_64_TABLE (X86_64_37) },
2435   /* 38 */
2436   { "cmpB",             { Eb, Gb }, 0 },
2437   { "cmpS",             { Ev, Gv }, 0 },
2438   { "cmpB",             { Gb, EbS }, 0 },
2439   { "cmpS",             { Gv, EvS }, 0 },
2440   { "cmpB",             { AL, Ib }, 0 },
2441   { "cmpS",             { eAX, Iv }, 0 },
2442   { Bad_Opcode },       /* SEG DS prefix */
2443   { X86_64_TABLE (X86_64_3F) },
2444   /* 40 */
2445   { "inc{S|}",          { RMeAX }, 0 },
2446   { "inc{S|}",          { RMeCX }, 0 },
2447   { "inc{S|}",          { RMeDX }, 0 },
2448   { "inc{S|}",          { RMeBX }, 0 },
2449   { "inc{S|}",          { RMeSP }, 0 },
2450   { "inc{S|}",          { RMeBP }, 0 },
2451   { "inc{S|}",          { RMeSI }, 0 },
2452   { "inc{S|}",          { RMeDI }, 0 },
2453   /* 48 */
2454   { "dec{S|}",          { RMeAX }, 0 },
2455   { "dec{S|}",          { RMeCX }, 0 },
2456   { "dec{S|}",          { RMeDX }, 0 },
2457   { "dec{S|}",          { RMeBX }, 0 },
2458   { "dec{S|}",          { RMeSP }, 0 },
2459   { "dec{S|}",          { RMeBP }, 0 },
2460   { "dec{S|}",          { RMeSI }, 0 },
2461   { "dec{S|}",          { RMeDI }, 0 },
2462   /* 50 */
2463   { "pushV",            { RMrAX }, 0 },
2464   { "pushV",            { RMrCX }, 0 },
2465   { "pushV",            { RMrDX }, 0 },
2466   { "pushV",            { RMrBX }, 0 },
2467   { "pushV",            { RMrSP }, 0 },
2468   { "pushV",            { RMrBP }, 0 },
2469   { "pushV",            { RMrSI }, 0 },
2470   { "pushV",            { RMrDI }, 0 },
2471   /* 58 */
2472   { "popV",             { RMrAX }, 0 },
2473   { "popV",             { RMrCX }, 0 },
2474   { "popV",             { RMrDX }, 0 },
2475   { "popV",             { RMrBX }, 0 },
2476   { "popV",             { RMrSP }, 0 },
2477   { "popV",             { RMrBP }, 0 },
2478   { "popV",             { RMrSI }, 0 },
2479   { "popV",             { RMrDI }, 0 },
2480   /* 60 */
2481   { X86_64_TABLE (X86_64_60) },
2482   { X86_64_TABLE (X86_64_61) },
2483   { X86_64_TABLE (X86_64_62) },
2484   { X86_64_TABLE (X86_64_63) },
2485   { Bad_Opcode },       /* seg fs */
2486   { Bad_Opcode },       /* seg gs */
2487   { Bad_Opcode },       /* op size prefix */
2488   { Bad_Opcode },       /* adr size prefix */
2489   /* 68 */
2490   { "pushT",            { sIv }, 0 },
2491   { "imulS",            { Gv, Ev, Iv }, 0 },
2492   { "pushT",            { sIbT }, 0 },
2493   { "imulS",            { Gv, Ev, sIb }, 0 },
2494   { "ins{b|}",          { Ybr, indirDX }, 0 },
2495   { X86_64_TABLE (X86_64_6D) },
2496   { "outs{b|}",         { indirDXr, Xb }, 0 },
2497   { X86_64_TABLE (X86_64_6F) },
2498   /* 70 */
2499   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2500   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2501   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2507   /* 78 */
2508   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2509   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2510   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2511   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2512   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2513   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2514   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2515   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2516   /* 80 */
2517   { REG_TABLE (REG_80) },
2518   { REG_TABLE (REG_81) },
2519   { X86_64_TABLE (X86_64_82) },
2520   { REG_TABLE (REG_83) },
2521   { "testB",            { Eb, Gb }, 0 },
2522   { "testS",            { Ev, Gv }, 0 },
2523   { "xchgB",            { Ebh2, Gb }, 0 },
2524   { "xchgS",            { Evh2, Gv }, 0 },
2525   /* 88 */
2526   { "movB",             { Ebh3, Gb }, 0 },
2527   { "movS",             { Evh3, Gv }, 0 },
2528   { "movB",             { Gb, EbS }, 0 },
2529   { "movS",             { Gv, EvS }, 0 },
2530   { "movD",             { Sv, Sw }, 0 },
2531   { MOD_TABLE (MOD_8D) },
2532   { "movD",             { Sw, Sv }, 0 },
2533   { REG_TABLE (REG_8F) },
2534   /* 90 */
2535   { PREFIX_TABLE (PREFIX_90) },
2536   { "xchgS",            { RMeCX, eAX }, 0 },
2537   { "xchgS",            { RMeDX, eAX }, 0 },
2538   { "xchgS",            { RMeBX, eAX }, 0 },
2539   { "xchgS",            { RMeSP, eAX }, 0 },
2540   { "xchgS",            { RMeBP, eAX }, 0 },
2541   { "xchgS",            { RMeSI, eAX }, 0 },
2542   { "xchgS",            { RMeDI, eAX }, 0 },
2543   /* 98 */
2544   { "cW{t|}R",          { XX }, 0 },
2545   { "cR{t|}O",          { XX }, 0 },
2546   { X86_64_TABLE (X86_64_9A) },
2547   { Bad_Opcode },       /* fwait */
2548   { "pushfT",           { XX }, 0 },
2549   { "popfT",            { XX }, 0 },
2550   { "sahf",             { XX }, 0 },
2551   { "lahf",             { XX }, 0 },
2552   /* a0 */
2553   { "mov%LB",           { AL, Ob }, 0 },
2554   { "mov%LS",           { eAX, Ov }, 0 },
2555   { "mov%LB",           { Ob, AL }, 0 },
2556   { "mov%LS",           { Ov, eAX }, 0 },
2557   { "movs{b|}",         { Ybr, Xb }, 0 },
2558   { "movs{R|}",         { Yvr, Xv }, 0 },
2559   { "cmps{b|}",         { Xb, Yb }, 0 },
2560   { "cmps{R|}",         { Xv, Yv }, 0 },
2561   /* a8 */
2562   { "testB",            { AL, Ib }, 0 },
2563   { "testS",            { eAX, Iv }, 0 },
2564   { "stosB",            { Ybr, AL }, 0 },
2565   { "stosS",            { Yvr, eAX }, 0 },
2566   { "lodsB",            { ALr, Xb }, 0 },
2567   { "lodsS",            { eAXr, Xv }, 0 },
2568   { "scasB",            { AL, Yb }, 0 },
2569   { "scasS",            { eAX, Yv }, 0 },
2570   /* b0 */
2571   { "movB",             { RMAL, Ib }, 0 },
2572   { "movB",             { RMCL, Ib }, 0 },
2573   { "movB",             { RMDL, Ib }, 0 },
2574   { "movB",             { RMBL, Ib }, 0 },
2575   { "movB",             { RMAH, Ib }, 0 },
2576   { "movB",             { RMCH, Ib }, 0 },
2577   { "movB",             { RMDH, Ib }, 0 },
2578   { "movB",             { RMBH, Ib }, 0 },
2579   /* b8 */
2580   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2581   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2582   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2583   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2584   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2585   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2586   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2587   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2588   /* c0 */
2589   { REG_TABLE (REG_C0) },
2590   { REG_TABLE (REG_C1) },
2591   { X86_64_TABLE (X86_64_C2) },
2592   { X86_64_TABLE (X86_64_C3) },
2593   { X86_64_TABLE (X86_64_C4) },
2594   { X86_64_TABLE (X86_64_C5) },
2595   { REG_TABLE (REG_C6) },
2596   { REG_TABLE (REG_C7) },
2597   /* c8 */
2598   { "enterT",           { Iw, Ib }, 0 },
2599   { "leaveT",           { XX }, 0 },
2600   { "Jret{|f}P",        { Iw }, 0 },
2601   { "Jret{|f}P",        { XX }, 0 },
2602   { "int3",             { XX }, 0 },
2603   { "int",              { Ib }, 0 },
2604   { X86_64_TABLE (X86_64_CE) },
2605   { "iret%LP",          { XX }, 0 },
2606   /* d0 */
2607   { REG_TABLE (REG_D0) },
2608   { REG_TABLE (REG_D1) },
2609   { REG_TABLE (REG_D2) },
2610   { REG_TABLE (REG_D3) },
2611   { X86_64_TABLE (X86_64_D4) },
2612   { X86_64_TABLE (X86_64_D5) },
2613   { Bad_Opcode },
2614   { "xlat",             { DSBX }, 0 },
2615   /* d8 */
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   { FLOAT },
2621   { FLOAT },
2622   { FLOAT },
2623   { FLOAT },
2624   /* e0 */
2625   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2626   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2627   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2628   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2629   { "inB",              { AL, Ib }, 0 },
2630   { "inG",              { zAX, Ib }, 0 },
2631   { "outB",             { Ib, AL }, 0 },
2632   { "outG",             { Ib, zAX }, 0 },
2633   /* e8 */
2634   { X86_64_TABLE (X86_64_E8) },
2635   { X86_64_TABLE (X86_64_E9) },
2636   { X86_64_TABLE (X86_64_EA) },
2637   { "jmp",              { Jb, BND }, 0 },
2638   { "inB",              { AL, indirDX }, 0 },
2639   { "inG",              { zAX, indirDX }, 0 },
2640   { "outB",             { indirDX, AL }, 0 },
2641   { "outG",             { indirDX, zAX }, 0 },
2642   /* f0 */
2643   { Bad_Opcode },       /* lock prefix */
2644   { "icebp",            { XX }, 0 },
2645   { Bad_Opcode },       /* repne */
2646   { Bad_Opcode },       /* repz */
2647   { "hlt",              { XX }, 0 },
2648   { "cmc",              { XX }, 0 },
2649   { REG_TABLE (REG_F6) },
2650   { REG_TABLE (REG_F7) },
2651   /* f8 */
2652   { "clc",              { XX }, 0 },
2653   { "stc",              { XX }, 0 },
2654   { "cli",              { XX }, 0 },
2655   { "sti",              { XX }, 0 },
2656   { "cld",              { XX }, 0 },
2657   { "std",              { XX }, 0 },
2658   { REG_TABLE (REG_FE) },
2659   { REG_TABLE (REG_FF) },
2660 };
2661
2662 static const struct dis386 dis386_twobyte[] = {
2663   /* 00 */
2664   { REG_TABLE (REG_0F00 ) },
2665   { REG_TABLE (REG_0F01 ) },
2666   { "larS",             { Gv, Ew }, 0 },
2667   { "lslS",             { Gv, Ew }, 0 },
2668   { Bad_Opcode },
2669   { "syscall",          { XX }, 0 },
2670   { "clts",             { XX }, 0 },
2671   { "sysret%LP",                { XX }, 0 },
2672   /* 08 */
2673   { "invd",             { XX }, 0 },
2674   { PREFIX_TABLE (PREFIX_0F09) },
2675   { Bad_Opcode },
2676   { "ud2",              { XX }, 0 },
2677   { Bad_Opcode },
2678   { REG_TABLE (REG_0F0D) },
2679   { "femms",            { XX }, 0 },
2680   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2681   /* 10 */
2682   { PREFIX_TABLE (PREFIX_0F10) },
2683   { PREFIX_TABLE (PREFIX_0F11) },
2684   { PREFIX_TABLE (PREFIX_0F12) },
2685   { MOD_TABLE (MOD_0F13) },
2686   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2687   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2688   { PREFIX_TABLE (PREFIX_0F16) },
2689   { MOD_TABLE (MOD_0F17) },
2690   /* 18 */
2691   { REG_TABLE (REG_0F18) },
2692   { "nopQ",             { Ev }, 0 },
2693   { PREFIX_TABLE (PREFIX_0F1A) },
2694   { PREFIX_TABLE (PREFIX_0F1B) },
2695   { PREFIX_TABLE (PREFIX_0F1C) },
2696   { "nopQ",             { Ev }, 0 },
2697   { PREFIX_TABLE (PREFIX_0F1E) },
2698   { "nopQ",             { Ev }, 0 },
2699   /* 20 */
2700   { "movZ",             { Rm, Cm }, 0 },
2701   { "movZ",             { Rm, Dm }, 0 },
2702   { "movZ",             { Cm, Rm }, 0 },
2703   { "movZ",             { Dm, Rm }, 0 },
2704   { MOD_TABLE (MOD_0F24) },
2705   { Bad_Opcode },
2706   { MOD_TABLE (MOD_0F26) },
2707   { Bad_Opcode },
2708   /* 28 */
2709   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2710   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2711   { PREFIX_TABLE (PREFIX_0F2A) },
2712   { PREFIX_TABLE (PREFIX_0F2B) },
2713   { PREFIX_TABLE (PREFIX_0F2C) },
2714   { PREFIX_TABLE (PREFIX_0F2D) },
2715   { PREFIX_TABLE (PREFIX_0F2E) },
2716   { PREFIX_TABLE (PREFIX_0F2F) },
2717   /* 30 */
2718   { "wrmsr",            { XX }, 0 },
2719   { "rdtsc",            { XX }, 0 },
2720   { "rdmsr",            { XX }, 0 },
2721   { "rdpmc",            { XX }, 0 },
2722   { "sysenter",         { SEP }, 0 },
2723   { "sysexit",          { SEP }, 0 },
2724   { Bad_Opcode },
2725   { "getsec",           { XX }, 0 },
2726   /* 38 */
2727   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2728   { Bad_Opcode },
2729   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2730   { Bad_Opcode },
2731   { Bad_Opcode },
2732   { Bad_Opcode },
2733   { Bad_Opcode },
2734   { Bad_Opcode },
2735   /* 40 */
2736   { "cmovoS",           { Gv, Ev }, 0 },
2737   { "cmovnoS",          { Gv, Ev }, 0 },
2738   { "cmovbS",           { Gv, Ev }, 0 },
2739   { "cmovaeS",          { Gv, Ev }, 0 },
2740   { "cmoveS",           { Gv, Ev }, 0 },
2741   { "cmovneS",          { Gv, Ev }, 0 },
2742   { "cmovbeS",          { Gv, Ev }, 0 },
2743   { "cmovaS",           { Gv, Ev }, 0 },
2744   /* 48 */
2745   { "cmovsS",           { Gv, Ev }, 0 },
2746   { "cmovnsS",          { Gv, Ev }, 0 },
2747   { "cmovpS",           { Gv, Ev }, 0 },
2748   { "cmovnpS",          { Gv, Ev }, 0 },
2749   { "cmovlS",           { Gv, Ev }, 0 },
2750   { "cmovgeS",          { Gv, Ev }, 0 },
2751   { "cmovleS",          { Gv, Ev }, 0 },
2752   { "cmovgS",           { Gv, Ev }, 0 },
2753   /* 50 */
2754   { MOD_TABLE (MOD_0F51) },
2755   { PREFIX_TABLE (PREFIX_0F51) },
2756   { PREFIX_TABLE (PREFIX_0F52) },
2757   { PREFIX_TABLE (PREFIX_0F53) },
2758   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2759   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2760   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2761   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2762   /* 58 */
2763   { PREFIX_TABLE (PREFIX_0F58) },
2764   { PREFIX_TABLE (PREFIX_0F59) },
2765   { PREFIX_TABLE (PREFIX_0F5A) },
2766   { PREFIX_TABLE (PREFIX_0F5B) },
2767   { PREFIX_TABLE (PREFIX_0F5C) },
2768   { PREFIX_TABLE (PREFIX_0F5D) },
2769   { PREFIX_TABLE (PREFIX_0F5E) },
2770   { PREFIX_TABLE (PREFIX_0F5F) },
2771   /* 60 */
2772   { PREFIX_TABLE (PREFIX_0F60) },
2773   { PREFIX_TABLE (PREFIX_0F61) },
2774   { PREFIX_TABLE (PREFIX_0F62) },
2775   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2776   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2777   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2778   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2779   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2780   /* 68 */
2781   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2782   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2783   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2784   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2785   { PREFIX_TABLE (PREFIX_0F6C) },
2786   { PREFIX_TABLE (PREFIX_0F6D) },
2787   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2788   { PREFIX_TABLE (PREFIX_0F6F) },
2789   /* 70 */
2790   { PREFIX_TABLE (PREFIX_0F70) },
2791   { REG_TABLE (REG_0F71) },
2792   { REG_TABLE (REG_0F72) },
2793   { REG_TABLE (REG_0F73) },
2794   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2795   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2796   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2797   { "emms",             { XX }, PREFIX_OPCODE },
2798   /* 78 */
2799   { PREFIX_TABLE (PREFIX_0F78) },
2800   { PREFIX_TABLE (PREFIX_0F79) },
2801   { Bad_Opcode },
2802   { Bad_Opcode },
2803   { PREFIX_TABLE (PREFIX_0F7C) },
2804   { PREFIX_TABLE (PREFIX_0F7D) },
2805   { PREFIX_TABLE (PREFIX_0F7E) },
2806   { PREFIX_TABLE (PREFIX_0F7F) },
2807   /* 80 */
2808   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2809   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2810   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2816   /* 88 */
2817   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2818   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2819   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2820   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2821   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2822   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2823   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2824   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2825   /* 90 */
2826   { "seto",             { Eb }, 0 },
2827   { "setno",            { Eb }, 0 },
2828   { "setb",             { Eb }, 0 },
2829   { "setae",            { Eb }, 0 },
2830   { "sete",             { Eb }, 0 },
2831   { "setne",            { Eb }, 0 },
2832   { "setbe",            { Eb }, 0 },
2833   { "seta",             { Eb }, 0 },
2834   /* 98 */
2835   { "sets",             { Eb }, 0 },
2836   { "setns",            { Eb }, 0 },
2837   { "setp",             { Eb }, 0 },
2838   { "setnp",            { Eb }, 0 },
2839   { "setl",             { Eb }, 0 },
2840   { "setge",            { Eb }, 0 },
2841   { "setle",            { Eb }, 0 },
2842   { "setg",             { Eb }, 0 },
2843   /* a0 */
2844   { "pushT",            { fs }, 0 },
2845   { "popT",             { fs }, 0 },
2846   { "cpuid",            { XX }, 0 },
2847   { "btS",              { Ev, Gv }, 0 },
2848   { "shldS",            { Ev, Gv, Ib }, 0 },
2849   { "shldS",            { Ev, Gv, CL }, 0 },
2850   { REG_TABLE (REG_0FA6) },
2851   { REG_TABLE (REG_0FA7) },
2852   /* a8 */
2853   { "pushT",            { gs }, 0 },
2854   { "popT",             { gs }, 0 },
2855   { "rsm",              { XX }, 0 },
2856   { "btsS",             { Evh1, Gv }, 0 },
2857   { "shrdS",            { Ev, Gv, Ib }, 0 },
2858   { "shrdS",            { Ev, Gv, CL }, 0 },
2859   { REG_TABLE (REG_0FAE) },
2860   { "imulS",            { Gv, Ev }, 0 },
2861   /* b0 */
2862   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2863   { "cmpxchgS",         { Evh1, Gv }, 0 },
2864   { MOD_TABLE (MOD_0FB2) },
2865   { "btrS",             { Evh1, Gv }, 0 },
2866   { MOD_TABLE (MOD_0FB4) },
2867   { MOD_TABLE (MOD_0FB5) },
2868   { "movz{bR|x}",       { Gv, Eb }, 0 },
2869   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2870   /* b8 */
2871   { PREFIX_TABLE (PREFIX_0FB8) },
2872   { "ud1S",             { Gv, Ev }, 0 },
2873   { REG_TABLE (REG_0FBA) },
2874   { "btcS",             { Evh1, Gv }, 0 },
2875   { PREFIX_TABLE (PREFIX_0FBC) },
2876   { PREFIX_TABLE (PREFIX_0FBD) },
2877   { "movs{bR|x}",       { Gv, Eb }, 0 },
2878   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2879   /* c0 */
2880   { "xaddB",            { Ebh1, Gb }, 0 },
2881   { "xaddS",            { Evh1, Gv }, 0 },
2882   { PREFIX_TABLE (PREFIX_0FC2) },
2883   { MOD_TABLE (MOD_0FC3) },
2884   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2885   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2886   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2887   { REG_TABLE (REG_0FC7) },
2888   /* c8 */
2889   { "bswap",            { RMeAX }, 0 },
2890   { "bswap",            { RMeCX }, 0 },
2891   { "bswap",            { RMeDX }, 0 },
2892   { "bswap",            { RMeBX }, 0 },
2893   { "bswap",            { RMeSP }, 0 },
2894   { "bswap",            { RMeBP }, 0 },
2895   { "bswap",            { RMeSI }, 0 },
2896   { "bswap",            { RMeDI }, 0 },
2897   /* d0 */
2898   { PREFIX_TABLE (PREFIX_0FD0) },
2899   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2900   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2901   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2902   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2903   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2904   { PREFIX_TABLE (PREFIX_0FD6) },
2905   { MOD_TABLE (MOD_0FD7) },
2906   /* d8 */
2907   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2908   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2909   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2910   { "pand",             { MX, EM }, PREFIX_OPCODE },
2911   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2912   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2913   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2914   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2915   /* e0 */
2916   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2917   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2918   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2919   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2920   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2921   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2922   { PREFIX_TABLE (PREFIX_0FE6) },
2923   { PREFIX_TABLE (PREFIX_0FE7) },
2924   /* e8 */
2925   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2926   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2927   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2928   { "por",              { MX, EM }, PREFIX_OPCODE },
2929   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2930   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2931   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2932   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2933   /* f0 */
2934   { PREFIX_TABLE (PREFIX_0FF0) },
2935   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2936   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2937   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2938   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2939   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2940   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2941   { PREFIX_TABLE (PREFIX_0FF7) },
2942   /* f8 */
2943   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2944   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2945   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2946   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2947   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2948   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2949   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2950   { "ud0S",             { Gv, Ev }, 0 },
2951 };
2952
2953 static const unsigned char onebyte_has_modrm[256] = {
2954   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2955   /*       -------------------------------        */
2956   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2957   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2958   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2959   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2960   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2961   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2962   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2963   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2964   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2965   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2966   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2967   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2968   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2969   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2970   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2971   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2972   /*       -------------------------------        */
2973   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2974 };
2975
2976 static const unsigned char twobyte_has_modrm[256] = {
2977   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2978   /*       -------------------------------        */
2979   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2980   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2981   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2982   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2983   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2984   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2985   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2986   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2987   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2988   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2989   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2990   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2991   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2992   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2993   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2994   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2995   /*       -------------------------------        */
2996   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2997 };
2998
2999 static char obuf[100];
3000 static char *obufp;
3001 static char *mnemonicendp;
3002 static char scratchbuf[100];
3003 static unsigned char *start_codep;
3004 static unsigned char *insn_codep;
3005 static unsigned char *codep;
3006 static unsigned char *end_codep;
3007 static int last_lock_prefix;
3008 static int last_repz_prefix;
3009 static int last_repnz_prefix;
3010 static int last_data_prefix;
3011 static int last_addr_prefix;
3012 static int last_rex_prefix;
3013 static int last_seg_prefix;
3014 static int fwait_prefix;
3015 /* The active segment register prefix.  */
3016 static int active_seg_prefix;
3017 #define MAX_CODE_LENGTH 15
3018 /* We can up to 14 prefixes since the maximum instruction length is
3019    15bytes.  */
3020 static int all_prefixes[MAX_CODE_LENGTH - 1];
3021 static disassemble_info *the_info;
3022 static struct
3023   {
3024     int mod;
3025     int reg;
3026     int rm;
3027   }
3028 modrm;
3029 static unsigned char need_modrm;
3030 static struct
3031   {
3032     int scale;
3033     int index;
3034     int base;
3035   }
3036 sib;
3037 static struct
3038   {
3039     int register_specifier;
3040     int length;
3041     int prefix;
3042     int w;
3043     int evex;
3044     int r;
3045     int v;
3046     int mask_register_specifier;
3047     int zeroing;
3048     int ll;
3049     int b;
3050   }
3051 vex;
3052 static unsigned char need_vex;
3053 static unsigned char need_vex_reg;
3054 static unsigned char vex_w_done;
3055
3056 struct op
3057   {
3058     const char *name;
3059     unsigned int len;
3060   };
3061
3062 /* If we are accessing mod/rm/reg without need_modrm set, then the
3063    values are stale.  Hitting this abort likely indicates that you
3064    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3065 #define MODRM_CHECK  if (!need_modrm) abort ()
3066
3067 static const char **names64;
3068 static const char **names32;
3069 static const char **names16;
3070 static const char **names8;
3071 static const char **names8rex;
3072 static const char **names_seg;
3073 static const char *index64;
3074 static const char *index32;
3075 static const char **index16;
3076 static const char **names_bnd;
3077
3078 static const char *intel_names64[] = {
3079   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3080   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3081 };
3082 static const char *intel_names32[] = {
3083   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3084   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3085 };
3086 static const char *intel_names16[] = {
3087   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3088   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3089 };
3090 static const char *intel_names8[] = {
3091   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3092 };
3093 static const char *intel_names8rex[] = {
3094   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3095   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3096 };
3097 static const char *intel_names_seg[] = {
3098   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3099 };
3100 static const char *intel_index64 = "riz";
3101 static const char *intel_index32 = "eiz";
3102 static const char *intel_index16[] = {
3103   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3104 };
3105
3106 static const char *att_names64[] = {
3107   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3108   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3109 };
3110 static const char *att_names32[] = {
3111   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3112   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3113 };
3114 static const char *att_names16[] = {
3115   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3116   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3117 };
3118 static const char *att_names8[] = {
3119   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3120 };
3121 static const char *att_names8rex[] = {
3122   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3123   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3124 };
3125 static const char *att_names_seg[] = {
3126   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3127 };
3128 static const char *att_index64 = "%riz";
3129 static const char *att_index32 = "%eiz";
3130 static const char *att_index16[] = {
3131   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3132 };
3133
3134 static const char **names_mm;
3135 static const char *intel_names_mm[] = {
3136   "mm0", "mm1", "mm2", "mm3",
3137   "mm4", "mm5", "mm6", "mm7"
3138 };
3139 static const char *att_names_mm[] = {
3140   "%mm0", "%mm1", "%mm2", "%mm3",
3141   "%mm4", "%mm5", "%mm6", "%mm7"
3142 };
3143
3144 static const char *intel_names_bnd[] = {
3145   "bnd0", "bnd1", "bnd2", "bnd3"
3146 };
3147
3148 static const char *att_names_bnd[] = {
3149   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3150 };
3151
3152 static const char **names_xmm;
3153 static const char *intel_names_xmm[] = {
3154   "xmm0", "xmm1", "xmm2", "xmm3",
3155   "xmm4", "xmm5", "xmm6", "xmm7",
3156   "xmm8", "xmm9", "xmm10", "xmm11",
3157   "xmm12", "xmm13", "xmm14", "xmm15",
3158   "xmm16", "xmm17", "xmm18", "xmm19",
3159   "xmm20", "xmm21", "xmm22", "xmm23",
3160   "xmm24", "xmm25", "xmm26", "xmm27",
3161   "xmm28", "xmm29", "xmm30", "xmm31"
3162 };
3163 static const char *att_names_xmm[] = {
3164   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3165   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3166   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3167   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3168   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3169   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3170   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3171   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3172 };
3173
3174 static const char **names_ymm;
3175 static const char *intel_names_ymm[] = {
3176   "ymm0", "ymm1", "ymm2", "ymm3",
3177   "ymm4", "ymm5", "ymm6", "ymm7",
3178   "ymm8", "ymm9", "ymm10", "ymm11",
3179   "ymm12", "ymm13", "ymm14", "ymm15",
3180   "ymm16", "ymm17", "ymm18", "ymm19",
3181   "ymm20", "ymm21", "ymm22", "ymm23",
3182   "ymm24", "ymm25", "ymm26", "ymm27",
3183   "ymm28", "ymm29", "ymm30", "ymm31"
3184 };
3185 static const char *att_names_ymm[] = {
3186   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3187   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3188   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3189   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3190   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3191   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3192   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3193   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3194 };
3195
3196 static const char **names_zmm;
3197 static const char *intel_names_zmm[] = {
3198   "zmm0", "zmm1", "zmm2", "zmm3",
3199   "zmm4", "zmm5", "zmm6", "zmm7",
3200   "zmm8", "zmm9", "zmm10", "zmm11",
3201   "zmm12", "zmm13", "zmm14", "zmm15",
3202   "zmm16", "zmm17", "zmm18", "zmm19",
3203   "zmm20", "zmm21", "zmm22", "zmm23",
3204   "zmm24", "zmm25", "zmm26", "zmm27",
3205   "zmm28", "zmm29", "zmm30", "zmm31"
3206 };
3207 static const char *att_names_zmm[] = {
3208   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3209   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3210   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3211   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3212   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3213   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3214   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3215   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3216 };
3217
3218 static const char **names_mask;
3219 static const char *intel_names_mask[] = {
3220   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3221 };
3222 static const char *att_names_mask[] = {
3223   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3224 };
3225
3226 static const char *names_rounding[] =
3227 {
3228   "{rn-sae}",
3229   "{rd-sae}",
3230   "{ru-sae}",
3231   "{rz-sae}"
3232 };
3233
3234 static const struct dis386 reg_table[][8] = {
3235   /* REG_80 */
3236   {
3237     { "addA",   { Ebh1, Ib }, 0 },
3238     { "orA",    { Ebh1, Ib }, 0 },
3239     { "adcA",   { Ebh1, Ib }, 0 },
3240     { "sbbA",   { Ebh1, Ib }, 0 },
3241     { "andA",   { Ebh1, Ib }, 0 },
3242     { "subA",   { Ebh1, Ib }, 0 },
3243     { "xorA",   { Ebh1, Ib }, 0 },
3244     { "cmpA",   { Eb, Ib }, 0 },
3245   },
3246   /* REG_81 */
3247   {
3248     { "addQ",   { Evh1, Iv }, 0 },
3249     { "orQ",    { Evh1, Iv }, 0 },
3250     { "adcQ",   { Evh1, Iv }, 0 },
3251     { "sbbQ",   { Evh1, Iv }, 0 },
3252     { "andQ",   { Evh1, Iv }, 0 },
3253     { "subQ",   { Evh1, Iv }, 0 },
3254     { "xorQ",   { Evh1, Iv }, 0 },
3255     { "cmpQ",   { Ev, Iv }, 0 },
3256   },
3257   /* REG_83 */
3258   {
3259     { "addQ",   { Evh1, sIb }, 0 },
3260     { "orQ",    { Evh1, sIb }, 0 },
3261     { "adcQ",   { Evh1, sIb }, 0 },
3262     { "sbbQ",   { Evh1, sIb }, 0 },
3263     { "andQ",   { Evh1, sIb }, 0 },
3264     { "subQ",   { Evh1, sIb }, 0 },
3265     { "xorQ",   { Evh1, sIb }, 0 },
3266     { "cmpQ",   { Ev, sIb }, 0 },
3267   },
3268   /* REG_8F */
3269   {
3270     { "popU",   { stackEv }, 0 },
3271     { XOP_8F_TABLE (XOP_09) },
3272     { Bad_Opcode },
3273     { Bad_Opcode },
3274     { Bad_Opcode },
3275     { XOP_8F_TABLE (XOP_09) },
3276   },
3277   /* REG_C0 */
3278   {
3279     { "rolA",   { Eb, Ib }, 0 },
3280     { "rorA",   { Eb, Ib }, 0 },
3281     { "rclA",   { Eb, Ib }, 0 },
3282     { "rcrA",   { Eb, Ib }, 0 },
3283     { "shlA",   { Eb, Ib }, 0 },
3284     { "shrA",   { Eb, Ib }, 0 },
3285     { "shlA",   { Eb, Ib }, 0 },
3286     { "sarA",   { Eb, Ib }, 0 },
3287   },
3288   /* REG_C1 */
3289   {
3290     { "rolQ",   { Ev, Ib }, 0 },
3291     { "rorQ",   { Ev, Ib }, 0 },
3292     { "rclQ",   { Ev, Ib }, 0 },
3293     { "rcrQ",   { Ev, Ib }, 0 },
3294     { "shlQ",   { Ev, Ib }, 0 },
3295     { "shrQ",   { Ev, Ib }, 0 },
3296     { "shlQ",   { Ev, Ib }, 0 },
3297     { "sarQ",   { Ev, Ib }, 0 },
3298   },
3299   /* REG_C6 */
3300   {
3301     { "movA",   { Ebh3, Ib }, 0 },
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { MOD_TABLE (MOD_C6_REG_7) },
3309   },
3310   /* REG_C7 */
3311   {
3312     { "movQ",   { Evh3, Iv }, 0 },
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { Bad_Opcode },
3317     { Bad_Opcode },
3318     { Bad_Opcode },
3319     { MOD_TABLE (MOD_C7_REG_7) },
3320   },
3321   /* REG_D0 */
3322   {
3323     { "rolA",   { Eb, I1 }, 0 },
3324     { "rorA",   { Eb, I1 }, 0 },
3325     { "rclA",   { Eb, I1 }, 0 },
3326     { "rcrA",   { Eb, I1 }, 0 },
3327     { "shlA",   { Eb, I1 }, 0 },
3328     { "shrA",   { Eb, I1 }, 0 },
3329     { "shlA",   { Eb, I1 }, 0 },
3330     { "sarA",   { Eb, I1 }, 0 },
3331   },
3332   /* REG_D1 */
3333   {
3334     { "rolQ",   { Ev, I1 }, 0 },
3335     { "rorQ",   { Ev, I1 }, 0 },
3336     { "rclQ",   { Ev, I1 }, 0 },
3337     { "rcrQ",   { Ev, I1 }, 0 },
3338     { "shlQ",   { Ev, I1 }, 0 },
3339     { "shrQ",   { Ev, I1 }, 0 },
3340     { "shlQ",   { Ev, I1 }, 0 },
3341     { "sarQ",   { Ev, I1 }, 0 },
3342   },
3343   /* REG_D2 */
3344   {
3345     { "rolA",   { Eb, CL }, 0 },
3346     { "rorA",   { Eb, CL }, 0 },
3347     { "rclA",   { Eb, CL }, 0 },
3348     { "rcrA",   { Eb, CL }, 0 },
3349     { "shlA",   { Eb, CL }, 0 },
3350     { "shrA",   { Eb, CL }, 0 },
3351     { "shlA",   { Eb, CL }, 0 },
3352     { "sarA",   { Eb, CL }, 0 },
3353   },
3354   /* REG_D3 */
3355   {
3356     { "rolQ",   { Ev, CL }, 0 },
3357     { "rorQ",   { Ev, CL }, 0 },
3358     { "rclQ",   { Ev, CL }, 0 },
3359     { "rcrQ",   { Ev, CL }, 0 },
3360     { "shlQ",   { Ev, CL }, 0 },
3361     { "shrQ",   { Ev, CL }, 0 },
3362     { "shlQ",   { Ev, CL }, 0 },
3363     { "sarQ",   { Ev, CL }, 0 },
3364   },
3365   /* REG_F6 */
3366   {
3367     { "testA",  { Eb, Ib }, 0 },
3368     { "testA",  { Eb, Ib }, 0 },
3369     { "notA",   { Ebh1 }, 0 },
3370     { "negA",   { Ebh1 }, 0 },
3371     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3372     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3373     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3374     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3375   },
3376   /* REG_F7 */
3377   {
3378     { "testQ",  { Ev, Iv }, 0 },
3379     { "testQ",  { Ev, Iv }, 0 },
3380     { "notQ",   { Evh1 }, 0 },
3381     { "negQ",   { Evh1 }, 0 },
3382     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3383     { "imulQ",  { Ev }, 0 },
3384     { "divQ",   { Ev }, 0 },
3385     { "idivQ",  { Ev }, 0 },
3386   },
3387   /* REG_FE */
3388   {
3389     { "incA",   { Ebh1 }, 0 },
3390     { "decA",   { Ebh1 }, 0 },
3391   },
3392   /* REG_FF */
3393   {
3394     { "incQ",   { Evh1 }, 0 },
3395     { "decQ",   { Evh1 }, 0 },
3396     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3397     { MOD_TABLE (MOD_FF_REG_3) },
3398     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3399     { MOD_TABLE (MOD_FF_REG_5) },
3400     { "pushU",  { stackEv }, 0 },
3401     { Bad_Opcode },
3402   },
3403   /* REG_0F00 */
3404   {
3405     { "sldtD",  { Sv }, 0 },
3406     { "strD",   { Sv }, 0 },
3407     { "lldt",   { Ew }, 0 },
3408     { "ltr",    { Ew }, 0 },
3409     { "verr",   { Ew }, 0 },
3410     { "verw",   { Ew }, 0 },
3411     { Bad_Opcode },
3412     { Bad_Opcode },
3413   },
3414   /* REG_0F01 */
3415   {
3416     { MOD_TABLE (MOD_0F01_REG_0) },
3417     { MOD_TABLE (MOD_0F01_REG_1) },
3418     { MOD_TABLE (MOD_0F01_REG_2) },
3419     { MOD_TABLE (MOD_0F01_REG_3) },
3420     { "smswD",  { Sv }, 0 },
3421     { MOD_TABLE (MOD_0F01_REG_5) },
3422     { "lmsw",   { Ew }, 0 },
3423     { MOD_TABLE (MOD_0F01_REG_7) },
3424   },
3425   /* REG_0F0D */
3426   {
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetchw",      { Mb }, 0 },
3429     { "prefetchwt1",    { Mb }, 0 },
3430     { "prefetch",       { Mb }, 0 },
3431     { "prefetch",       { Mb }, 0 },
3432     { "prefetch",       { Mb }, 0 },
3433     { "prefetch",       { Mb }, 0 },
3434     { "prefetch",       { Mb }, 0 },
3435   },
3436   /* REG_0F18 */
3437   {
3438     { MOD_TABLE (MOD_0F18_REG_0) },
3439     { MOD_TABLE (MOD_0F18_REG_1) },
3440     { MOD_TABLE (MOD_0F18_REG_2) },
3441     { MOD_TABLE (MOD_0F18_REG_3) },
3442     { MOD_TABLE (MOD_0F18_REG_4) },
3443     { MOD_TABLE (MOD_0F18_REG_5) },
3444     { MOD_TABLE (MOD_0F18_REG_6) },
3445     { MOD_TABLE (MOD_0F18_REG_7) },
3446   },
3447   /* REG_0F1C_P_0_MOD_0 */
3448   {
3449     { "cldemote",       { Mb }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452     { "nopQ",           { Ev }, 0 },
3453     { "nopQ",           { Ev }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457   },
3458   /* REG_0F1E_P_1_MOD_3 */
3459   {
3460     { "nopQ",           { Ev }, 0 },
3461     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3462     { "nopQ",           { Ev }, 0 },
3463     { "nopQ",           { Ev }, 0 },
3464     { "nopQ",           { Ev }, 0 },
3465     { "nopQ",           { Ev }, 0 },
3466     { "nopQ",           { Ev }, 0 },
3467     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3468   },
3469   /* REG_0F71 */
3470   {
3471     { Bad_Opcode },
3472     { Bad_Opcode },
3473     { MOD_TABLE (MOD_0F71_REG_2) },
3474     { Bad_Opcode },
3475     { MOD_TABLE (MOD_0F71_REG_4) },
3476     { Bad_Opcode },
3477     { MOD_TABLE (MOD_0F71_REG_6) },
3478   },
3479   /* REG_0F72 */
3480   {
3481     { Bad_Opcode },
3482     { Bad_Opcode },
3483     { MOD_TABLE (MOD_0F72_REG_2) },
3484     { Bad_Opcode },
3485     { MOD_TABLE (MOD_0F72_REG_4) },
3486     { Bad_Opcode },
3487     { MOD_TABLE (MOD_0F72_REG_6) },
3488   },
3489   /* REG_0F73 */
3490   {
3491     { Bad_Opcode },
3492     { Bad_Opcode },
3493     { MOD_TABLE (MOD_0F73_REG_2) },
3494     { MOD_TABLE (MOD_0F73_REG_3) },
3495     { Bad_Opcode },
3496     { Bad_Opcode },
3497     { MOD_TABLE (MOD_0F73_REG_6) },
3498     { MOD_TABLE (MOD_0F73_REG_7) },
3499   },
3500   /* REG_0FA6 */
3501   {
3502     { "montmul",        { { OP_0f07, 0 } }, 0 },
3503     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3504     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3505   },
3506   /* REG_0FA7 */
3507   {
3508     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3509     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3510     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3511     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3512     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3513     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3514   },
3515   /* REG_0FAE */
3516   {
3517     { MOD_TABLE (MOD_0FAE_REG_0) },
3518     { MOD_TABLE (MOD_0FAE_REG_1) },
3519     { MOD_TABLE (MOD_0FAE_REG_2) },
3520     { MOD_TABLE (MOD_0FAE_REG_3) },
3521     { MOD_TABLE (MOD_0FAE_REG_4) },
3522     { MOD_TABLE (MOD_0FAE_REG_5) },
3523     { MOD_TABLE (MOD_0FAE_REG_6) },
3524     { MOD_TABLE (MOD_0FAE_REG_7) },
3525   },
3526   /* REG_0FBA */
3527   {
3528     { Bad_Opcode },
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { "btQ",    { Ev, Ib }, 0 },
3533     { "btsQ",   { Evh1, Ib }, 0 },
3534     { "btrQ",   { Evh1, Ib }, 0 },
3535     { "btcQ",   { Evh1, Ib }, 0 },
3536   },
3537   /* REG_0FC7 */
3538   {
3539     { Bad_Opcode },
3540     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3541     { Bad_Opcode },
3542     { MOD_TABLE (MOD_0FC7_REG_3) },
3543     { MOD_TABLE (MOD_0FC7_REG_4) },
3544     { MOD_TABLE (MOD_0FC7_REG_5) },
3545     { MOD_TABLE (MOD_0FC7_REG_6) },
3546     { MOD_TABLE (MOD_0FC7_REG_7) },
3547   },
3548   /* REG_VEX_0F71 */
3549   {
3550     { Bad_Opcode },
3551     { Bad_Opcode },
3552     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3553     { Bad_Opcode },
3554     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3555     { Bad_Opcode },
3556     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3557   },
3558   /* REG_VEX_0F72 */
3559   {
3560     { Bad_Opcode },
3561     { Bad_Opcode },
3562     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3563     { Bad_Opcode },
3564     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3567   },
3568   /* REG_VEX_0F73 */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3573     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3574     { Bad_Opcode },
3575     { Bad_Opcode },
3576     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3577     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3578   },
3579   /* REG_VEX_0FAE */
3580   {
3581     { Bad_Opcode },
3582     { Bad_Opcode },
3583     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3584     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3585   },
3586   /* REG_VEX_0F38F3 */
3587   {
3588     { Bad_Opcode },
3589     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3590     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3591     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3592   },
3593   /* REG_XOP_LWPCB */
3594   {
3595     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3596     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3597   },
3598   /* REG_XOP_LWP */
3599   {
3600     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3601     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3602   },
3603   /* REG_XOP_TBM_01 */
3604   {
3605     { Bad_Opcode },
3606     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3607     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3608     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3609     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3610     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3611     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3612     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3613   },
3614   /* REG_XOP_TBM_02 */
3615   {
3616     { Bad_Opcode },
3617     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3618     { Bad_Opcode },
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3623   },
3624
3625 #include "i386-dis-evex-reg.h"
3626 };
3627
3628 static const struct dis386 prefix_table[][4] = {
3629   /* PREFIX_90 */
3630   {
3631     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3632     { "pause", { XX }, 0 },
3633     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3634     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3635   },
3636
3637   /* PREFIX_0F01_REG_5_MOD_0 */
3638   {
3639     { Bad_Opcode },
3640     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3641   },
3642
3643   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3644   {
3645     { Bad_Opcode },
3646     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3647   },
3648
3649   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3650   {
3651     { Bad_Opcode },
3652     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3653   },
3654
3655   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3656   {
3657     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3658     { "mcommit",        { Skip_MODRM }, 0 },
3659   },
3660
3661   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3662   {
3663     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3664   },
3665
3666   /* PREFIX_0F09 */
3667   {
3668     { "wbinvd",   { XX }, 0 },
3669     { "wbnoinvd", { XX }, 0 },
3670   },
3671
3672   /* PREFIX_0F10 */
3673   {
3674     { "movups", { XM, EXx }, PREFIX_OPCODE },
3675     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3676     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3677     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3678   },
3679
3680   /* PREFIX_0F11 */
3681   {
3682     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3683     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3684     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3685     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F12 */
3689   {
3690     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3691     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3692     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3693     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F16 */
3697   {
3698     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3699     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3700     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3701   },
3702
3703   /* PREFIX_0F1A */
3704   {
3705     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3706     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3707     { "bndmov", { Gbnd, Ebnd }, 0 },
3708     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3709   },
3710
3711   /* PREFIX_0F1B */
3712   {
3713     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3714     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3715     { "bndmov", { EbndS, Gbnd }, 0 },
3716     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3717   },
3718
3719   /* PREFIX_0F1C */
3720   {
3721     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3722     { "nopQ",   { Ev }, PREFIX_OPCODE },
3723     { "nopQ",   { Ev }, PREFIX_OPCODE },
3724     { "nopQ",   { Ev }, PREFIX_OPCODE },
3725   },
3726
3727   /* PREFIX_0F1E */
3728   {
3729     { "nopQ",   { Ev }, PREFIX_OPCODE },
3730     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3731     { "nopQ",   { Ev }, PREFIX_OPCODE },
3732     { "nopQ",   { Ev }, PREFIX_OPCODE },
3733   },
3734
3735   /* PREFIX_0F2A */
3736   {
3737     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3738     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3739     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3740     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3741   },
3742
3743   /* PREFIX_0F2B */
3744   {
3745     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3746     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3747     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3748     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3749   },
3750
3751   /* PREFIX_0F2C */
3752   {
3753     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3755     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F2D */
3760   {
3761     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3762     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3763     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3764     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3765   },
3766
3767   /* PREFIX_0F2E */
3768   {
3769     { "ucomiss",{ XM, EXd }, 0 },
3770     { Bad_Opcode },
3771     { "ucomisd",{ XM, EXq }, 0 },
3772   },
3773
3774   /* PREFIX_0F2F */
3775   {
3776     { "comiss", { XM, EXd }, 0 },
3777     { Bad_Opcode },
3778     { "comisd", { XM, EXq }, 0 },
3779   },
3780
3781   /* PREFIX_0F51 */
3782   {
3783     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3784     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3785     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3786     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F52 */
3790   {
3791     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3792     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F53 */
3796   {
3797     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3798     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F58 */
3802   {
3803     { "addps", { XM, EXx }, PREFIX_OPCODE },
3804     { "addss", { XM, EXd }, PREFIX_OPCODE },
3805     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3806     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F59 */
3810   {
3811     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3812     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3813     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3814     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F5A */
3818   {
3819     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3820     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3821     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3822     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3823   },
3824
3825   /* PREFIX_0F5B */
3826   {
3827     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3828     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3829     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F5C */
3833   {
3834     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3835     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3836     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3837     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F5D */
3841   {
3842     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3843     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3844     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3845     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F5E */
3849   {
3850     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3851     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3852     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3853     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F5F */
3857   {
3858     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3859     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3860     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3861     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3862   },
3863
3864   /* PREFIX_0F60 */
3865   {
3866     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3867     { Bad_Opcode },
3868     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3869   },
3870
3871   /* PREFIX_0F61 */
3872   {
3873     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3874     { Bad_Opcode },
3875     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3876   },
3877
3878   /* PREFIX_0F62 */
3879   {
3880     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3881     { Bad_Opcode },
3882     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3883   },
3884
3885   /* PREFIX_0F6C */
3886   {
3887     { Bad_Opcode },
3888     { Bad_Opcode },
3889     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3890   },
3891
3892   /* PREFIX_0F6D */
3893   {
3894     { Bad_Opcode },
3895     { Bad_Opcode },
3896     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0F6F */
3900   {
3901     { "movq",   { MX, EM }, PREFIX_OPCODE },
3902     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3903     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F70 */
3907   {
3908     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3909     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3910     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3911     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3912   },
3913
3914   /* PREFIX_0F73_REG_3 */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "psrldq", { XS, Ib }, 0 },
3919   },
3920
3921   /* PREFIX_0F73_REG_7 */
3922   {
3923     { Bad_Opcode },
3924     { Bad_Opcode },
3925     { "pslldq", { XS, Ib }, 0 },
3926   },
3927
3928   /* PREFIX_0F78 */
3929   {
3930     {"vmread",  { Em, Gm }, 0 },
3931     { Bad_Opcode },
3932     {"extrq",   { XS, Ib, Ib }, 0 },
3933     {"insertq", { XM, XS, Ib, Ib }, 0 },
3934   },
3935
3936   /* PREFIX_0F79 */
3937   {
3938     {"vmwrite", { Gm, Em }, 0 },
3939     { Bad_Opcode },
3940     {"extrq",   { XM, XS }, 0 },
3941     {"insertq", { XM, XS }, 0 },
3942   },
3943
3944   /* PREFIX_0F7C */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F7D */
3953   {
3954     { Bad_Opcode },
3955     { Bad_Opcode },
3956     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3957     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3958   },
3959
3960   /* PREFIX_0F7E */
3961   {
3962     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3963     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3964     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3965   },
3966
3967   /* PREFIX_0F7F */
3968   {
3969     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3970     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3971     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0FAE_REG_0_MOD_3 */
3975   {
3976     { Bad_Opcode },
3977     { "rdfsbase", { Ev }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_1_MOD_3 */
3981   {
3982     { Bad_Opcode },
3983     { "rdgsbase", { Ev }, 0 },
3984   },
3985
3986   /* PREFIX_0FAE_REG_2_MOD_3 */
3987   {
3988     { Bad_Opcode },
3989     { "wrfsbase", { Ev }, 0 },
3990   },
3991
3992   /* PREFIX_0FAE_REG_3_MOD_3 */
3993   {
3994     { Bad_Opcode },
3995     { "wrgsbase", { Ev }, 0 },
3996   },
3997
3998   /* PREFIX_0FAE_REG_4_MOD_0 */
3999   {
4000     { "xsave",  { FXSAVE }, 0 },
4001     { "ptwrite%LQ", { Edq }, 0 },
4002   },
4003
4004   /* PREFIX_0FAE_REG_4_MOD_3 */
4005   {
4006     { Bad_Opcode },
4007     { "ptwrite%LQ", { Edq }, 0 },
4008   },
4009
4010   /* PREFIX_0FAE_REG_5_MOD_0 */
4011   {
4012     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4013   },
4014
4015   /* PREFIX_0FAE_REG_5_MOD_3 */
4016   {
4017     { "lfence",         { Skip_MODRM }, 0 },
4018     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4019   },
4020
4021   /* PREFIX_0FAE_REG_6_MOD_0 */
4022   {
4023     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4024     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4025     { "clwb",   { Mb }, PREFIX_OPCODE },
4026   },
4027
4028   /* PREFIX_0FAE_REG_6_MOD_3 */
4029   {
4030     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4031     { "umonitor",       { Eva }, PREFIX_OPCODE },
4032     { "tpause", { Edq }, PREFIX_OPCODE },
4033     { "umwait", { Edq }, PREFIX_OPCODE },
4034   },
4035
4036   /* PREFIX_0FAE_REG_7_MOD_0 */
4037   {
4038     { "clflush",        { Mb }, 0 },
4039     { Bad_Opcode },
4040     { "clflushopt",     { Mb }, 0 },
4041   },
4042
4043   /* PREFIX_0FB8 */
4044   {
4045     { Bad_Opcode },
4046     { "popcntS", { Gv, Ev }, 0 },
4047   },
4048
4049   /* PREFIX_0FBC */
4050   {
4051     { "bsfS",   { Gv, Ev }, 0 },
4052     { "tzcntS", { Gv, Ev }, 0 },
4053     { "bsfS",   { Gv, Ev }, 0 },
4054   },
4055
4056   /* PREFIX_0FBD */
4057   {
4058     { "bsrS",   { Gv, Ev }, 0 },
4059     { "lzcntS", { Gv, Ev }, 0 },
4060     { "bsrS",   { Gv, Ev }, 0 },
4061   },
4062
4063   /* PREFIX_0FC2 */
4064   {
4065     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4066     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4067     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4068     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0FC3_MOD_0 */
4072   {
4073     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0FC7_REG_6_MOD_0 */
4077   {
4078     { "vmptrld",{ Mq }, 0 },
4079     { "vmxon",  { Mq }, 0 },
4080     { "vmclear",{ Mq }, 0 },
4081   },
4082
4083   /* PREFIX_0FC7_REG_6_MOD_3 */
4084   {
4085     { "rdrand", { Ev }, 0 },
4086     { Bad_Opcode },
4087     { "rdrand", { Ev }, 0 }
4088   },
4089
4090   /* PREFIX_0FC7_REG_7_MOD_3 */
4091   {
4092     { "rdseed", { Ev }, 0 },
4093     { "rdpid",  { Em }, 0 },
4094     { "rdseed", { Ev }, 0 },
4095   },
4096
4097   /* PREFIX_0FD0 */
4098   {
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { "addsubpd", { XM, EXx }, 0 },
4102     { "addsubps", { XM, EXx }, 0 },
4103   },
4104
4105   /* PREFIX_0FD6 */
4106   {
4107     { Bad_Opcode },
4108     { "movq2dq",{ XM, MS }, 0 },
4109     { "movq",   { EXqS, XM }, 0 },
4110     { "movdq2q",{ MX, XS }, 0 },
4111   },
4112
4113   /* PREFIX_0FE6 */
4114   {
4115     { Bad_Opcode },
4116     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4117     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4118     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0FE7 */
4122   {
4123     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4124     { Bad_Opcode },
4125     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4126   },
4127
4128   /* PREFIX_0FF0 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { Bad_Opcode },
4133     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4134   },
4135
4136   /* PREFIX_0FF7 */
4137   {
4138     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4139     { Bad_Opcode },
4140     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4141   },
4142
4143   /* PREFIX_0F3810 */
4144   {
4145     { Bad_Opcode },
4146     { Bad_Opcode },
4147     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4148   },
4149
4150   /* PREFIX_0F3814 */
4151   {
4152     { Bad_Opcode },
4153     { Bad_Opcode },
4154     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4155   },
4156
4157   /* PREFIX_0F3815 */
4158   {
4159     { Bad_Opcode },
4160     { Bad_Opcode },
4161     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4162   },
4163
4164   /* PREFIX_0F3817 */
4165   {
4166     { Bad_Opcode },
4167     { Bad_Opcode },
4168     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4169   },
4170
4171   /* PREFIX_0F3820 */
4172   {
4173     { Bad_Opcode },
4174     { Bad_Opcode },
4175     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4176   },
4177
4178   /* PREFIX_0F3821 */
4179   {
4180     { Bad_Opcode },
4181     { Bad_Opcode },
4182     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4183   },
4184
4185   /* PREFIX_0F3822 */
4186   {
4187     { Bad_Opcode },
4188     { Bad_Opcode },
4189     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_0F3823 */
4193   {
4194     { Bad_Opcode },
4195     { Bad_Opcode },
4196     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4197   },
4198
4199   /* PREFIX_0F3824 */
4200   {
4201     { Bad_Opcode },
4202     { Bad_Opcode },
4203     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4204   },
4205
4206   /* PREFIX_0F3825 */
4207   {
4208     { Bad_Opcode },
4209     { Bad_Opcode },
4210     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4211   },
4212
4213   /* PREFIX_0F3828 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4218   },
4219
4220   /* PREFIX_0F3829 */
4221   {
4222     { Bad_Opcode },
4223     { Bad_Opcode },
4224     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4225   },
4226
4227   /* PREFIX_0F382A */
4228   {
4229     { Bad_Opcode },
4230     { Bad_Opcode },
4231     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4232   },
4233
4234   /* PREFIX_0F382B */
4235   {
4236     { Bad_Opcode },
4237     { Bad_Opcode },
4238     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4239   },
4240
4241   /* PREFIX_0F3830 */
4242   {
4243     { Bad_Opcode },
4244     { Bad_Opcode },
4245     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4246   },
4247
4248   /* PREFIX_0F3831 */
4249   {
4250     { Bad_Opcode },
4251     { Bad_Opcode },
4252     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4253   },
4254
4255   /* PREFIX_0F3832 */
4256   {
4257     { Bad_Opcode },
4258     { Bad_Opcode },
4259     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4260   },
4261
4262   /* PREFIX_0F3833 */
4263   {
4264     { Bad_Opcode },
4265     { Bad_Opcode },
4266     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4267   },
4268
4269   /* PREFIX_0F3834 */
4270   {
4271     { Bad_Opcode },
4272     { Bad_Opcode },
4273     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4274   },
4275
4276   /* PREFIX_0F3835 */
4277   {
4278     { Bad_Opcode },
4279     { Bad_Opcode },
4280     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_0F3837 */
4284   {
4285     { Bad_Opcode },
4286     { Bad_Opcode },
4287     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4288   },
4289
4290   /* PREFIX_0F3838 */
4291   {
4292     { Bad_Opcode },
4293     { Bad_Opcode },
4294     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4295   },
4296
4297   /* PREFIX_0F3839 */
4298   {
4299     { Bad_Opcode },
4300     { Bad_Opcode },
4301     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4302   },
4303
4304   /* PREFIX_0F383A */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4309   },
4310
4311   /* PREFIX_0F383B */
4312   {
4313     { Bad_Opcode },
4314     { Bad_Opcode },
4315     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4316   },
4317
4318   /* PREFIX_0F383C */
4319   {
4320     { Bad_Opcode },
4321     { Bad_Opcode },
4322     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4323   },
4324
4325   /* PREFIX_0F383D */
4326   {
4327     { Bad_Opcode },
4328     { Bad_Opcode },
4329     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4330   },
4331
4332   /* PREFIX_0F383E */
4333   {
4334     { Bad_Opcode },
4335     { Bad_Opcode },
4336     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4337   },
4338
4339   /* PREFIX_0F383F */
4340   {
4341     { Bad_Opcode },
4342     { Bad_Opcode },
4343     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4344   },
4345
4346   /* PREFIX_0F3840 */
4347   {
4348     { Bad_Opcode },
4349     { Bad_Opcode },
4350     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4351   },
4352
4353   /* PREFIX_0F3841 */
4354   {
4355     { Bad_Opcode },
4356     { Bad_Opcode },
4357     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4358   },
4359
4360   /* PREFIX_0F3880 */
4361   {
4362     { Bad_Opcode },
4363     { Bad_Opcode },
4364     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4365   },
4366
4367   /* PREFIX_0F3881 */
4368   {
4369     { Bad_Opcode },
4370     { Bad_Opcode },
4371     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F3882 */
4375   {
4376     { Bad_Opcode },
4377     { Bad_Opcode },
4378     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38C8 */
4382   {
4383     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F38C9 */
4387   {
4388     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F38CA */
4392   {
4393     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4394   },
4395
4396   /* PREFIX_0F38CB */
4397   {
4398     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F38CC */
4402   {
4403     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F38CD */
4407   {
4408     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4409   },
4410
4411   /* PREFIX_0F38CF */
4412   {
4413     { Bad_Opcode },
4414     { Bad_Opcode },
4415     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4416   },
4417
4418   /* PREFIX_0F38DB */
4419   {
4420     { Bad_Opcode },
4421     { Bad_Opcode },
4422     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4423   },
4424
4425   /* PREFIX_0F38DC */
4426   {
4427     { Bad_Opcode },
4428     { Bad_Opcode },
4429     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4430   },
4431
4432   /* PREFIX_0F38DD */
4433   {
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38DE */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F38DF */
4447   {
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4451   },
4452
4453   /* PREFIX_0F38F0 */
4454   {
4455     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4456     { Bad_Opcode },
4457     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4458     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F38F1 */
4462   {
4463     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4464     { Bad_Opcode },
4465     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4466     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F38F5 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4474   },
4475
4476   /* PREFIX_0F38F6 */
4477   {
4478     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4479     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4480     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4481     { Bad_Opcode },
4482   },
4483
4484   /* PREFIX_0F38F8 */
4485   {
4486     { Bad_Opcode },
4487     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4488     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4489     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4490   },
4491
4492   /* PREFIX_0F38F9 */
4493   {
4494     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4495   },
4496
4497   /* PREFIX_0F3A08 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3A09 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F3A0A */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F3A0B */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F3A0C */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A0D */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A0E */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A14 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A15 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A16 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A17 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A20 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A21 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A22 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A40 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A41 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A42 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A44 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3A60 */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4628   },
4629
4630   /* PREFIX_0F3A61 */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4635   },
4636
4637   /* PREFIX_0F3A62 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3A63 */
4645   {
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4649   },
4650
4651   /* PREFIX_0F3ACC */
4652   {
4653     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3ACE */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3ACF */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3ADF */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_VEX_0F10 */
4678   {
4679     { "vmovups",        { XM, EXx }, 0 },
4680     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4681     { "vmovupd",        { XM, EXx }, 0 },
4682     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4683   },
4684
4685   /* PREFIX_VEX_0F11 */
4686   {
4687     { "vmovups",        { EXxS, XM }, 0 },
4688     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4689     { "vmovupd",        { EXxS, XM }, 0 },
4690     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4691   },
4692
4693   /* PREFIX_VEX_0F12 */
4694   {
4695     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4696     { "vmovsldup",      { XM, EXx }, 0 },
4697     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4698     { "vmovddup",       { XM, EXymmq }, 0 },
4699   },
4700
4701   /* PREFIX_VEX_0F16 */
4702   {
4703     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4704     { "vmovshdup",      { XM, EXx }, 0 },
4705     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F2A */
4709   {
4710     { Bad_Opcode },
4711     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4712     { Bad_Opcode },
4713     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4714   },
4715
4716   /* PREFIX_VEX_0F2C */
4717   {
4718     { Bad_Opcode },
4719     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4720     { Bad_Opcode },
4721     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4722   },
4723
4724   /* PREFIX_VEX_0F2D */
4725   {
4726     { Bad_Opcode },
4727     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4728     { Bad_Opcode },
4729     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4730   },
4731
4732   /* PREFIX_VEX_0F2E */
4733   {
4734     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4735     { Bad_Opcode },
4736     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4737   },
4738
4739   /* PREFIX_VEX_0F2F */
4740   {
4741     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4742     { Bad_Opcode },
4743     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4744   },
4745
4746   /* PREFIX_VEX_0F41 */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F42 */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F44 */
4761   {
4762     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4763     { Bad_Opcode },
4764     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F45 */
4768   {
4769     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4770     { Bad_Opcode },
4771     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F46 */
4775   {
4776     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4777     { Bad_Opcode },
4778     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4779   },
4780
4781   /* PREFIX_VEX_0F47 */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F4A */
4789   {
4790     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4791     { Bad_Opcode },
4792     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4793   },
4794
4795   /* PREFIX_VEX_0F4B */
4796   {
4797     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4798     { Bad_Opcode },
4799     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4800   },
4801
4802   /* PREFIX_VEX_0F51 */
4803   {
4804     { "vsqrtps",        { XM, EXx }, 0 },
4805     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4806     { "vsqrtpd",        { XM, EXx }, 0 },
4807     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F52 */
4811   {
4812     { "vrsqrtps",       { XM, EXx }, 0 },
4813     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F53 */
4817   {
4818     { "vrcpps",         { XM, EXx }, 0 },
4819     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4820   },
4821
4822   /* PREFIX_VEX_0F58 */
4823   {
4824     { "vaddps",         { XM, Vex, EXx }, 0 },
4825     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4826     { "vaddpd",         { XM, Vex, EXx }, 0 },
4827     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4828   },
4829
4830   /* PREFIX_VEX_0F59 */
4831   {
4832     { "vmulps",         { XM, Vex, EXx }, 0 },
4833     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4834     { "vmulpd",         { XM, Vex, EXx }, 0 },
4835     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4836   },
4837
4838   /* PREFIX_VEX_0F5A */
4839   {
4840     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4841     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4842     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4843     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4844   },
4845
4846   /* PREFIX_VEX_0F5B */
4847   {
4848     { "vcvtdq2ps",      { XM, EXx }, 0 },
4849     { "vcvttps2dq",     { XM, EXx }, 0 },
4850     { "vcvtps2dq",      { XM, EXx }, 0 },
4851   },
4852
4853   /* PREFIX_VEX_0F5C */
4854   {
4855     { "vsubps",         { XM, Vex, EXx }, 0 },
4856     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4857     { "vsubpd",         { XM, Vex, EXx }, 0 },
4858     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4859   },
4860
4861   /* PREFIX_VEX_0F5D */
4862   {
4863     { "vminps",         { XM, Vex, EXx }, 0 },
4864     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4865     { "vminpd",         { XM, Vex, EXx }, 0 },
4866     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F5E */
4870   {
4871     { "vdivps",         { XM, Vex, EXx }, 0 },
4872     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4873     { "vdivpd",         { XM, Vex, EXx }, 0 },
4874     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4875   },
4876
4877   /* PREFIX_VEX_0F5F */
4878   {
4879     { "vmaxps",         { XM, Vex, EXx }, 0 },
4880     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4881     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4882     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4883   },
4884
4885   /* PREFIX_VEX_0F60 */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4890   },
4891
4892   /* PREFIX_VEX_0F61 */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4897   },
4898
4899   /* PREFIX_VEX_0F62 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4904   },
4905
4906   /* PREFIX_VEX_0F63 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4911   },
4912
4913   /* PREFIX_VEX_0F64 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4918   },
4919
4920   /* PREFIX_VEX_0F65 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4925   },
4926
4927   /* PREFIX_VEX_0F66 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4932   },
4933
4934   /* PREFIX_VEX_0F67 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4939   },
4940
4941   /* PREFIX_VEX_0F68 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4946   },
4947
4948   /* PREFIX_VEX_0F69 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4953   },
4954
4955   /* PREFIX_VEX_0F6A */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4960   },
4961
4962   /* PREFIX_VEX_0F6B */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4967   },
4968
4969   /* PREFIX_VEX_0F6C */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4974   },
4975
4976   /* PREFIX_VEX_0F6D */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4981   },
4982
4983   /* PREFIX_VEX_0F6E */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F6F */
4991   {
4992     { Bad_Opcode },
4993     { "vmovdqu",        { XM, EXx }, 0 },
4994     { "vmovdqa",        { XM, EXx }, 0 },
4995   },
4996
4997   /* PREFIX_VEX_0F70 */
4998   {
4999     { Bad_Opcode },
5000     { "vpshufhw",       { XM, EXx, Ib }, 0 },
5001     { "vpshufd",        { XM, EXx, Ib }, 0 },
5002     { "vpshuflw",       { XM, EXx, Ib }, 0 },
5003   },
5004
5005   /* PREFIX_VEX_0F71_REG_2 */
5006   {
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5010   },
5011
5012   /* PREFIX_VEX_0F71_REG_4 */
5013   {
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { "vpsraw",         { Vex, XS, Ib }, 0 },
5017   },
5018
5019   /* PREFIX_VEX_0F71_REG_6 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { "vpsllw",         { Vex, XS, Ib }, 0 },
5024   },
5025
5026   /* PREFIX_VEX_0F72_REG_2 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { "vpsrld",         { Vex, XS, Ib }, 0 },
5031   },
5032
5033   /* PREFIX_VEX_0F72_REG_4 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { "vpsrad",         { Vex, XS, Ib }, 0 },
5038   },
5039
5040   /* PREFIX_VEX_0F72_REG_6 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { "vpslld",         { Vex, XS, Ib }, 0 },
5045   },
5046
5047   /* PREFIX_VEX_0F73_REG_2 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5052   },
5053
5054   /* PREFIX_VEX_0F73_REG_3 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5059   },
5060
5061   /* PREFIX_VEX_0F73_REG_6 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { "vpsllq",         { Vex, XS, Ib }, 0 },
5066   },
5067
5068   /* PREFIX_VEX_0F73_REG_7 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { "vpslldq",        { Vex, XS, Ib }, 0 },
5073   },
5074
5075   /* PREFIX_VEX_0F74 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5080   },
5081
5082   /* PREFIX_VEX_0F75 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F76 */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5094   },
5095
5096   /* PREFIX_VEX_0F77 */
5097   {
5098     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5099   },
5100
5101   /* PREFIX_VEX_0F7C */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5106     { "vhaddps",        { XM, Vex, EXx }, 0 },
5107   },
5108
5109   /* PREFIX_VEX_0F7D */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5114     { "vhsubps",        { XM, Vex, EXx }, 0 },
5115   },
5116
5117   /* PREFIX_VEX_0F7E */
5118   {
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5121     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0F7F */
5125   {
5126     { Bad_Opcode },
5127     { "vmovdqu",        { EXxS, XM }, 0 },
5128     { "vmovdqa",        { EXxS, XM }, 0 },
5129   },
5130
5131   /* PREFIX_VEX_0F90 */
5132   {
5133     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F91 */
5139   {
5140     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0F92 */
5146   {
5147     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5150     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5151   },
5152
5153   /* PREFIX_VEX_0F93 */
5154   {
5155     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5156     { Bad_Opcode },
5157     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5158     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5159   },
5160
5161   /* PREFIX_VEX_0F98 */
5162   {
5163     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5164     { Bad_Opcode },
5165     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F99 */
5169   {
5170     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5171     { Bad_Opcode },
5172     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0FC2 */
5176   {
5177     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5178     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5179     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5180     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5181   },
5182
5183   /* PREFIX_VEX_0FC4 */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5188   },
5189
5190   /* PREFIX_VEX_0FC5 */
5191   {
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5195   },
5196
5197   /* PREFIX_VEX_0FD0 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5202     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5203   },
5204
5205   /* PREFIX_VEX_0FD1 */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5210   },
5211
5212   /* PREFIX_VEX_0FD2 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5217   },
5218
5219   /* PREFIX_VEX_0FD3 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5224   },
5225
5226   /* PREFIX_VEX_0FD4 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { "vpaddq",         { XM, Vex, EXx }, 0 },
5231   },
5232
5233   /* PREFIX_VEX_0FD5 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { "vpmullw",        { XM, Vex, EXx }, 0 },
5238   },
5239
5240   /* PREFIX_VEX_0FD6 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FD7 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5252   },
5253
5254   /* PREFIX_VEX_0FD8 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5259   },
5260
5261   /* PREFIX_VEX_0FD9 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5266   },
5267
5268   /* PREFIX_VEX_0FDA */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { "vpminub",        { XM, Vex, EXx }, 0 },
5273   },
5274
5275   /* PREFIX_VEX_0FDB */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { "vpand",          { XM, Vex, EXx }, 0 },
5280   },
5281
5282   /* PREFIX_VEX_0FDC */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5287   },
5288
5289   /* PREFIX_VEX_0FDD */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5294   },
5295
5296   /* PREFIX_VEX_0FDE */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5301   },
5302
5303   /* PREFIX_VEX_0FDF */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { "vpandn",         { XM, Vex, EXx }, 0 },
5308   },
5309
5310   /* PREFIX_VEX_0FE0 */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { "vpavgb",         { XM, Vex, EXx }, 0 },
5315   },
5316
5317   /* PREFIX_VEX_0FE1 */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5322   },
5323
5324   /* PREFIX_VEX_0FE2 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5329   },
5330
5331   /* PREFIX_VEX_0FE3 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { "vpavgw",         { XM, Vex, EXx }, 0 },
5336   },
5337
5338   /* PREFIX_VEX_0FE4 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5343   },
5344
5345   /* PREFIX_VEX_0FE5 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5350   },
5351
5352   /* PREFIX_VEX_0FE6 */
5353   {
5354     { Bad_Opcode },
5355     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5356     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5357     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5358   },
5359
5360   /* PREFIX_VEX_0FE7 */
5361   {
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5365   },
5366
5367   /* PREFIX_VEX_0FE8 */
5368   {
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5372   },
5373
5374   /* PREFIX_VEX_0FE9 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5379   },
5380
5381   /* PREFIX_VEX_0FEA */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { "vpminsw",        { XM, Vex, EXx }, 0 },
5386   },
5387
5388   /* PREFIX_VEX_0FEB */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { "vpor",           { XM, Vex, EXx }, 0 },
5393   },
5394
5395   /* PREFIX_VEX_0FEC */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5400   },
5401
5402   /* PREFIX_VEX_0FED */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5407   },
5408
5409   /* PREFIX_VEX_0FEE */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5414   },
5415
5416   /* PREFIX_VEX_0FEF */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { "vpxor",          { XM, Vex, EXx }, 0 },
5421   },
5422
5423   /* PREFIX_VEX_0FF0 */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5429   },
5430
5431   /* PREFIX_VEX_0FF1 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5436   },
5437
5438   /* PREFIX_VEX_0FF2 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5443   },
5444
5445   /* PREFIX_VEX_0FF3 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5450   },
5451
5452   /* PREFIX_VEX_0FF4 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5457   },
5458
5459   /* PREFIX_VEX_0FF5 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5464   },
5465
5466   /* PREFIX_VEX_0FF6 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5471   },
5472
5473   /* PREFIX_VEX_0FF7 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FF8 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { "vpsubb",         { XM, Vex, EXx }, 0 },
5485   },
5486
5487   /* PREFIX_VEX_0FF9 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { "vpsubw",         { XM, Vex, EXx }, 0 },
5492   },
5493
5494   /* PREFIX_VEX_0FFA */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { "vpsubd",         { XM, Vex, EXx }, 0 },
5499   },
5500
5501   /* PREFIX_VEX_0FFB */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { "vpsubq",         { XM, Vex, EXx }, 0 },
5506   },
5507
5508   /* PREFIX_VEX_0FFC */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { "vpaddb",         { XM, Vex, EXx }, 0 },
5513   },
5514
5515   /* PREFIX_VEX_0FFD */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { "vpaddw",         { XM, Vex, EXx }, 0 },
5520   },
5521
5522   /* PREFIX_VEX_0FFE */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { "vpaddd",         { XM, Vex, EXx }, 0 },
5527   },
5528
5529   /* PREFIX_VEX_0F3800 */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { "vpshufb",        { XM, Vex, EXx }, 0 },
5534   },
5535
5536   /* PREFIX_VEX_0F3801 */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { "vphaddw",        { XM, Vex, EXx }, 0 },
5541   },
5542
5543   /* PREFIX_VEX_0F3802 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vphaddd",        { XM, Vex, EXx }, 0 },
5548   },
5549
5550   /* PREFIX_VEX_0F3803 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5555   },
5556
5557   /* PREFIX_VEX_0F3804 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5562   },
5563
5564   /* PREFIX_VEX_0F3805 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { "vphsubw",        { XM, Vex, EXx }, 0 },
5569   },
5570
5571   /* PREFIX_VEX_0F3806 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { "vphsubd",        { XM, Vex, EXx }, 0 },
5576   },
5577
5578   /* PREFIX_VEX_0F3807 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5583   },
5584
5585   /* PREFIX_VEX_0F3808 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { "vpsignb",        { XM, Vex, EXx }, 0 },
5590   },
5591
5592   /* PREFIX_VEX_0F3809 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { "vpsignw",        { XM, Vex, EXx }, 0 },
5597   },
5598
5599   /* PREFIX_VEX_0F380A */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { "vpsignd",        { XM, Vex, EXx }, 0 },
5604   },
5605
5606   /* PREFIX_VEX_0F380B */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5611   },
5612
5613   /* PREFIX_VEX_0F380C */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F380D */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F380E */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F380F */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3813 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5646   },
5647
5648   /* PREFIX_VEX_0F3816 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F3817 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vptest",         { XM, EXx }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3818 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F3819 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F381A */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5681   },
5682
5683   /* PREFIX_VEX_0F381C */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { "vpabsb",         { XM, EXx }, 0 },
5688   },
5689
5690   /* PREFIX_VEX_0F381D */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { "vpabsw",         { XM, EXx }, 0 },
5695   },
5696
5697   /* PREFIX_VEX_0F381E */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { "vpabsd",         { XM, EXx }, 0 },
5702   },
5703
5704   /* PREFIX_VEX_0F3820 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5709   },
5710
5711   /* PREFIX_VEX_0F3821 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5716   },
5717
5718   /* PREFIX_VEX_0F3822 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5723   },
5724
5725   /* PREFIX_VEX_0F3823 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5730   },
5731
5732   /* PREFIX_VEX_0F3824 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5737   },
5738
5739   /* PREFIX_VEX_0F3825 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5744   },
5745
5746   /* PREFIX_VEX_0F3828 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5751   },
5752
5753   /* PREFIX_VEX_0F3829 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5758   },
5759
5760   /* PREFIX_VEX_0F382A */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F382B */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5772   },
5773
5774   /* PREFIX_VEX_0F382C */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F382D */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F382E */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F382F */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F3830 */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5807   },
5808
5809   /* PREFIX_VEX_0F3831 */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5814   },
5815
5816   /* PREFIX_VEX_0F3832 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5821   },
5822
5823   /* PREFIX_VEX_0F3833 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5828   },
5829
5830   /* PREFIX_VEX_0F3834 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5835   },
5836
5837   /* PREFIX_VEX_0F3835 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5842   },
5843
5844   /* PREFIX_VEX_0F3836 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5849   },
5850
5851   /* PREFIX_VEX_0F3837 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5856   },
5857
5858   /* PREFIX_VEX_0F3838 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { "vpminsb",        { XM, Vex, EXx }, 0 },
5863   },
5864
5865   /* PREFIX_VEX_0F3839 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { "vpminsd",        { XM, Vex, EXx }, 0 },
5870   },
5871
5872   /* PREFIX_VEX_0F383A */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { "vpminuw",        { XM, Vex, EXx }, 0 },
5877   },
5878
5879   /* PREFIX_VEX_0F383B */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { "vpminud",        { XM, Vex, EXx }, 0 },
5884   },
5885
5886   /* PREFIX_VEX_0F383C */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5891   },
5892
5893   /* PREFIX_VEX_0F383D */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5898   },
5899
5900   /* PREFIX_VEX_0F383E */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5905   },
5906
5907   /* PREFIX_VEX_0F383F */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5912   },
5913
5914   /* PREFIX_VEX_0F3840 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vpmulld",        { XM, Vex, EXx }, 0 },
5919   },
5920
5921   /* PREFIX_VEX_0F3841 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3845 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5933   },
5934
5935   /* PREFIX_VEX_0F3846 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F3847 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5947   },
5948
5949   /* PREFIX_VEX_0F3858 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3859 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5961   },
5962
5963   /* PREFIX_VEX_0F385A */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3878 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F3879 */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F388C */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F388E */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5996   },
5997
5998   /* PREFIX_VEX_0F3890 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6003   },
6004
6005   /* PREFIX_VEX_0F3891 */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6010   },
6011
6012   /* PREFIX_VEX_0F3892 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3893 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3896 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F3897 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F3898 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F3899 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F389A */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F389B */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389C */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F389D */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F389E */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F389F */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F38A6 */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6101     { Bad_Opcode },
6102   },
6103
6104   /* PREFIX_VEX_0F38A7 */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6109   },
6110
6111   /* PREFIX_VEX_0F38A8 */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6116   },
6117
6118   /* PREFIX_VEX_0F38A9 */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38AA */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38AB */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AC */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38AD */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38AE */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38AF */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38B6 */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38B7 */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38B8 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38B9 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38BA */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38BB */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BC */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38BD */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38BE */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38BF */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38CF */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6242   },
6243
6244   /* PREFIX_VEX_0F38DB */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6249   },
6250
6251   /* PREFIX_VEX_0F38DC */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { "vaesenc",        { XM, Vex, EXx }, 0 },
6256   },
6257
6258   /* PREFIX_VEX_0F38DD */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6263   },
6264
6265   /* PREFIX_VEX_0F38DE */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { "vaesdec",        { XM, Vex, EXx }, 0 },
6270   },
6271
6272   /* PREFIX_VEX_0F38DF */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6277   },
6278
6279   /* PREFIX_VEX_0F38F2 */
6280   {
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6282   },
6283
6284   /* PREFIX_VEX_0F38F3_REG_1 */
6285   {
6286     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6287   },
6288
6289   /* PREFIX_VEX_0F38F3_REG_2 */
6290   {
6291     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6292   },
6293
6294   /* PREFIX_VEX_0F38F3_REG_3 */
6295   {
6296     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6297   },
6298
6299   /* PREFIX_VEX_0F38F5 */
6300   {
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6302     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6303     { Bad_Opcode },
6304     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6305   },
6306
6307   /* PREFIX_VEX_0F38F6 */
6308   {
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6313   },
6314
6315   /* PREFIX_VEX_0F38F7 */
6316   {
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6318     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6319     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6320     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A00 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A01 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A02 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A04 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A05 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A06 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A08 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { "vroundps",       { XM, EXx, Ib }, 0 },
6370   },
6371
6372   /* PREFIX_VEX_0F3A09 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vroundpd",       { XM, EXx, Ib }, 0 },
6377   },
6378
6379   /* PREFIX_VEX_0F3A0A */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0B */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0C */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6398   },
6399
6400   /* PREFIX_VEX_0F3A0D */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6405   },
6406
6407   /* PREFIX_VEX_0F3A0E */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6412   },
6413
6414   /* PREFIX_VEX_0F3A0F */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6419   },
6420
6421   /* PREFIX_VEX_0F3A14 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A15 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A16 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A17 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A18 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A19 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A1D */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6468   },
6469
6470   /* PREFIX_VEX_0F3A20 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A21 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A22 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A30 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A31 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A32 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A33 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A38 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A39 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A40 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6538   },
6539
6540   /* PREFIX_VEX_0F3A41 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A42 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6552   },
6553
6554   /* PREFIX_VEX_0F3A44 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6559   },
6560
6561   /* PREFIX_VEX_0F3A46 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A48 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A49 */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A4A */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A4B */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A4C */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A5C */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6608   },
6609
6610   /* PREFIX_VEX_0F3A5D */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A5E */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A5F */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6629   },
6630
6631   /* PREFIX_VEX_0F3A60 */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6636     { Bad_Opcode },
6637   },
6638
6639   /* PREFIX_VEX_0F3A61 */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6644   },
6645
6646   /* PREFIX_VEX_0F3A62 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A63 */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6658   },
6659
6660   /* PREFIX_VEX_0F3A68 */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6665   },
6666
6667   /* PREFIX_VEX_0F3A69 */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A6A */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6B */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6C */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6693   },
6694
6695   /* PREFIX_VEX_0F3A6D */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6700   },
6701
6702   /* PREFIX_VEX_0F3A6E */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6707   },
6708
6709   /* PREFIX_VEX_0F3A6F */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6714   },
6715
6716   /* PREFIX_VEX_0F3A78 */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6721   },
6722
6723   /* PREFIX_VEX_0F3A79 */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6728   },
6729
6730   /* PREFIX_VEX_0F3A7A */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6735   },
6736
6737   /* PREFIX_VEX_0F3A7B */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6742   },
6743
6744   /* PREFIX_VEX_0F3A7C */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6749     { Bad_Opcode },
6750   },
6751
6752   /* PREFIX_VEX_0F3A7D */
6753   {
6754     { Bad_Opcode },
6755     { Bad_Opcode },
6756     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6757   },
6758
6759   /* PREFIX_VEX_0F3A7E */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6764   },
6765
6766   /* PREFIX_VEX_0F3A7F */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3ACE */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3ACF */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3ADF */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6792   },
6793
6794   /* PREFIX_VEX_0F3AF0 */
6795   {
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6800   },
6801
6802 #include "i386-dis-evex-prefix.h"
6803 };
6804
6805 static const struct dis386 x86_64_table[][2] = {
6806   /* X86_64_06 */
6807   {
6808     { "pushP", { es }, 0 },
6809   },
6810
6811   /* X86_64_07 */
6812   {
6813     { "popP", { es }, 0 },
6814   },
6815
6816   /* X86_64_0D */
6817   {
6818     { "pushP", { cs }, 0 },
6819   },
6820
6821   /* X86_64_16 */
6822   {
6823     { "pushP", { ss }, 0 },
6824   },
6825
6826   /* X86_64_17 */
6827   {
6828     { "popP", { ss }, 0 },
6829   },
6830
6831   /* X86_64_1E */
6832   {
6833     { "pushP", { ds }, 0 },
6834   },
6835
6836   /* X86_64_1F */
6837   {
6838     { "popP", { ds }, 0 },
6839   },
6840
6841   /* X86_64_27 */
6842   {
6843     { "daa", { XX }, 0 },
6844   },
6845
6846   /* X86_64_2F */
6847   {
6848     { "das", { XX }, 0 },
6849   },
6850
6851   /* X86_64_37 */
6852   {
6853     { "aaa", { XX }, 0 },
6854   },
6855
6856   /* X86_64_3F */
6857   {
6858     { "aas", { XX }, 0 },
6859   },
6860
6861   /* X86_64_60 */
6862   {
6863     { "pushaP", { XX }, 0 },
6864   },
6865
6866   /* X86_64_61 */
6867   {
6868     { "popaP", { XX }, 0 },
6869   },
6870
6871   /* X86_64_62 */
6872   {
6873     { MOD_TABLE (MOD_62_32BIT) },
6874     { EVEX_TABLE (EVEX_0F) },
6875   },
6876
6877   /* X86_64_63 */
6878   {
6879     { "arpl", { Ew, Gw }, 0 },
6880     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6881   },
6882
6883   /* X86_64_6D */
6884   {
6885     { "ins{R|}", { Yzr, indirDX }, 0 },
6886     { "ins{G|}", { Yzr, indirDX }, 0 },
6887   },
6888
6889   /* X86_64_6F */
6890   {
6891     { "outs{R|}", { indirDXr, Xz }, 0 },
6892     { "outs{G|}", { indirDXr, Xz }, 0 },
6893   },
6894
6895   /* X86_64_82 */
6896   {
6897     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6898     { REG_TABLE (REG_80) },
6899   },
6900
6901   /* X86_64_9A */
6902   {
6903     { "Jcall{T|}", { Ap }, 0 },
6904   },
6905
6906   /* X86_64_C2 */
6907   {
6908     { "retP",           { Iw, BND }, 0 },
6909     { "ret@",           { Iw, BND }, 0 },
6910   },
6911
6912   /* X86_64_C3 */
6913   {
6914     { "retP",           { BND }, 0 },
6915     { "ret@",           { BND }, 0 },
6916   },
6917
6918   /* X86_64_C4 */
6919   {
6920     { MOD_TABLE (MOD_C4_32BIT) },
6921     { VEX_C4_TABLE (VEX_0F) },
6922   },
6923
6924   /* X86_64_C5 */
6925   {
6926     { MOD_TABLE (MOD_C5_32BIT) },
6927     { VEX_C5_TABLE (VEX_0F) },
6928   },
6929
6930   /* X86_64_CE */
6931   {
6932     { "into", { XX }, 0 },
6933   },
6934
6935   /* X86_64_D4 */
6936   {
6937     { "aam", { Ib }, 0 },
6938   },
6939
6940   /* X86_64_D5 */
6941   {
6942     { "aad", { Ib }, 0 },
6943   },
6944
6945   /* X86_64_E8 */
6946   {
6947     { "callP",          { Jv, BND }, 0 },
6948     { "call@",          { Jv, BND }, 0 }
6949   },
6950
6951   /* X86_64_E9 */
6952   {
6953     { "jmpP",           { Jv, BND }, 0 },
6954     { "jmp@",           { Jv, BND }, 0 }
6955   },
6956
6957   /* X86_64_EA */
6958   {
6959     { "Jjmp{T|}", { Ap }, 0 },
6960   },
6961
6962   /* X86_64_0F01_REG_0 */
6963   {
6964     { "sgdt{Q|IQ}", { M }, 0 },
6965     { "sgdt", { M }, 0 },
6966   },
6967
6968   /* X86_64_0F01_REG_1 */
6969   {
6970     { "sidt{Q|IQ}", { M }, 0 },
6971     { "sidt", { M }, 0 },
6972   },
6973
6974   /* X86_64_0F01_REG_2 */
6975   {
6976     { "lgdt{Q|Q}", { M }, 0 },
6977     { "lgdt", { M }, 0 },
6978   },
6979
6980   /* X86_64_0F01_REG_3 */
6981   {
6982     { "lidt{Q|Q}", { M }, 0 },
6983     { "lidt", { M }, 0 },
6984   },
6985 };
6986
6987 static const struct dis386 three_byte_table[][256] = {
6988
6989   /* THREE_BYTE_0F38 */
6990   {
6991     /* 00 */
6992     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6993     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6994     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6995     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6996     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6997     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6998     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6999     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7000     /* 08 */
7001     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7002     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7003     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7004     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     /* 10 */
7010     { PREFIX_TABLE (PREFIX_0F3810) },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { PREFIX_TABLE (PREFIX_0F3814) },
7015     { PREFIX_TABLE (PREFIX_0F3815) },
7016     { Bad_Opcode },
7017     { PREFIX_TABLE (PREFIX_0F3817) },
7018     /* 18 */
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7024     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7025     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7026     { Bad_Opcode },
7027     /* 20 */
7028     { PREFIX_TABLE (PREFIX_0F3820) },
7029     { PREFIX_TABLE (PREFIX_0F3821) },
7030     { PREFIX_TABLE (PREFIX_0F3822) },
7031     { PREFIX_TABLE (PREFIX_0F3823) },
7032     { PREFIX_TABLE (PREFIX_0F3824) },
7033     { PREFIX_TABLE (PREFIX_0F3825) },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     /* 28 */
7037     { PREFIX_TABLE (PREFIX_0F3828) },
7038     { PREFIX_TABLE (PREFIX_0F3829) },
7039     { PREFIX_TABLE (PREFIX_0F382A) },
7040     { PREFIX_TABLE (PREFIX_0F382B) },
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     /* 30 */
7046     { PREFIX_TABLE (PREFIX_0F3830) },
7047     { PREFIX_TABLE (PREFIX_0F3831) },
7048     { PREFIX_TABLE (PREFIX_0F3832) },
7049     { PREFIX_TABLE (PREFIX_0F3833) },
7050     { PREFIX_TABLE (PREFIX_0F3834) },
7051     { PREFIX_TABLE (PREFIX_0F3835) },
7052     { Bad_Opcode },
7053     { PREFIX_TABLE (PREFIX_0F3837) },
7054     /* 38 */
7055     { PREFIX_TABLE (PREFIX_0F3838) },
7056     { PREFIX_TABLE (PREFIX_0F3839) },
7057     { PREFIX_TABLE (PREFIX_0F383A) },
7058     { PREFIX_TABLE (PREFIX_0F383B) },
7059     { PREFIX_TABLE (PREFIX_0F383C) },
7060     { PREFIX_TABLE (PREFIX_0F383D) },
7061     { PREFIX_TABLE (PREFIX_0F383E) },
7062     { PREFIX_TABLE (PREFIX_0F383F) },
7063     /* 40 */
7064     { PREFIX_TABLE (PREFIX_0F3840) },
7065     { PREFIX_TABLE (PREFIX_0F3841) },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     /* 48 */
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     /* 50 */
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     /* 58 */
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     /* 60 */
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     /* 68 */
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     /* 70 */
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     /* 78 */
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     /* 80 */
7136     { PREFIX_TABLE (PREFIX_0F3880) },
7137     { PREFIX_TABLE (PREFIX_0F3881) },
7138     { PREFIX_TABLE (PREFIX_0F3882) },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 88 */
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     /* 90 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     /* 98 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* a0 */
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* a8 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* b0 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* b8 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* c0 */
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* c8 */
7217     { PREFIX_TABLE (PREFIX_0F38C8) },
7218     { PREFIX_TABLE (PREFIX_0F38C9) },
7219     { PREFIX_TABLE (PREFIX_0F38CA) },
7220     { PREFIX_TABLE (PREFIX_0F38CB) },
7221     { PREFIX_TABLE (PREFIX_0F38CC) },
7222     { PREFIX_TABLE (PREFIX_0F38CD) },
7223     { Bad_Opcode },
7224     { PREFIX_TABLE (PREFIX_0F38CF) },
7225     /* d0 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* d8 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { PREFIX_TABLE (PREFIX_0F38DB) },
7239     { PREFIX_TABLE (PREFIX_0F38DC) },
7240     { PREFIX_TABLE (PREFIX_0F38DD) },
7241     { PREFIX_TABLE (PREFIX_0F38DE) },
7242     { PREFIX_TABLE (PREFIX_0F38DF) },
7243     /* e0 */
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* e8 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* f0 */
7262     { PREFIX_TABLE (PREFIX_0F38F0) },
7263     { PREFIX_TABLE (PREFIX_0F38F1) },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { PREFIX_TABLE (PREFIX_0F38F5) },
7268     { PREFIX_TABLE (PREFIX_0F38F6) },
7269     { Bad_Opcode },
7270     /* f8 */
7271     { PREFIX_TABLE (PREFIX_0F38F8) },
7272     { PREFIX_TABLE (PREFIX_0F38F9) },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279   },
7280   /* THREE_BYTE_0F3A */
7281   {
7282     /* 00 */
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     /* 08 */
7292     { PREFIX_TABLE (PREFIX_0F3A08) },
7293     { PREFIX_TABLE (PREFIX_0F3A09) },
7294     { PREFIX_TABLE (PREFIX_0F3A0A) },
7295     { PREFIX_TABLE (PREFIX_0F3A0B) },
7296     { PREFIX_TABLE (PREFIX_0F3A0C) },
7297     { PREFIX_TABLE (PREFIX_0F3A0D) },
7298     { PREFIX_TABLE (PREFIX_0F3A0E) },
7299     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7300     /* 10 */
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { PREFIX_TABLE (PREFIX_0F3A14) },
7306     { PREFIX_TABLE (PREFIX_0F3A15) },
7307     { PREFIX_TABLE (PREFIX_0F3A16) },
7308     { PREFIX_TABLE (PREFIX_0F3A17) },
7309     /* 18 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     /* 20 */
7319     { PREFIX_TABLE (PREFIX_0F3A20) },
7320     { PREFIX_TABLE (PREFIX_0F3A21) },
7321     { PREFIX_TABLE (PREFIX_0F3A22) },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 28 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 30 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 38 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* 40 */
7355     { PREFIX_TABLE (PREFIX_0F3A40) },
7356     { PREFIX_TABLE (PREFIX_0F3A41) },
7357     { PREFIX_TABLE (PREFIX_0F3A42) },
7358     { Bad_Opcode },
7359     { PREFIX_TABLE (PREFIX_0F3A44) },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* 48 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     /* 50 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* 58 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* 60 */
7391     { PREFIX_TABLE (PREFIX_0F3A60) },
7392     { PREFIX_TABLE (PREFIX_0F3A61) },
7393     { PREFIX_TABLE (PREFIX_0F3A62) },
7394     { PREFIX_TABLE (PREFIX_0F3A63) },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     /* 68 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* 70 */
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     /* 78 */
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     /* 80 */
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     /* 88 */
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     /* 90 */
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     /* 98 */
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     /* a0 */
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     /* a8 */
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     /* b0 */
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     /* b8 */
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     /* c0 */
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     /* c8 */
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { PREFIX_TABLE (PREFIX_0F3ACC) },
7513     { Bad_Opcode },
7514     { PREFIX_TABLE (PREFIX_0F3ACE) },
7515     { PREFIX_TABLE (PREFIX_0F3ACF) },
7516     /* d0 */
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     /* d8 */
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { PREFIX_TABLE (PREFIX_0F3ADF) },
7534     /* e0 */
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     /* e8 */
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     /* f0 */
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     /* f8 */
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570   },
7571 };
7572
7573 static const struct dis386 xop_table[][256] = {
7574   /* XOP_08 */
7575   {
7576     /* 00 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     /* 08 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* 10 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* 18 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* 20 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     /* 28 */
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     /* 30 */
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     /* 38 */
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     /* 40 */
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     /* 48 */
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     /* 50 */
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     /* 58 */
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     /* 60 */
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     /* 68 */
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     /* 70 */
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     /* 78 */
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     /* 80 */
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     /* 88 */
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738     /* 90 */
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7745     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7746     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7747     /* 98 */
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7755     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7756     /* a0 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7760     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7764     { Bad_Opcode },
7765     /* a8 */
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     /* b0 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7782     { Bad_Opcode },
7783     /* b8 */
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* c0 */
7793     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7794     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7795     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7796     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* c8 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7807     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7808     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7809     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7810     /* d0 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* d8 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* e0 */
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* e8 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7843     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7844     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7845     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7846     /* f0 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* f8 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864   },
7865   /* XOP_09 */
7866   {
7867     /* 00 */
7868     { Bad_Opcode },
7869     { REG_TABLE (REG_XOP_TBM_01) },
7870     { REG_TABLE (REG_XOP_TBM_02) },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     /* 08 */
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     /* 10 */
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { REG_TABLE (REG_XOP_LWPCB) },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     /* 18 */
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     /* 20 */
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     /* 28 */
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     /* 30 */
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     /* 38 */
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     /* 40 */
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     /* 48 */
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     /* 50 */
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     /* 58 */
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     /* 60 */
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     /* 68 */
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     /* 70 */
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     /* 78 */
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     /* 80 */
8012     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8013     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8014     { "vfrczss",        { XM, EXd }, 0 },
8015     { "vfrczsd",        { XM, EXq }, 0 },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     /* 88 */
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     /* 90 */
8030     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8031     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8032     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8033     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8034     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8035     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8036     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8037     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8038     /* 98 */
8039     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8040     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8041     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8042     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     /* a0 */
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     /* a8 */
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     /* b0 */
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     /* b8 */
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     /* c0 */
8084     { Bad_Opcode },
8085     { "vphaddbw",       { XM, EXxmm }, 0 },
8086     { "vphaddbd",       { XM, EXxmm }, 0 },
8087     { "vphaddbq",       { XM, EXxmm }, 0 },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { "vphaddwd",       { XM, EXxmm }, 0 },
8091     { "vphaddwq",       { XM, EXxmm }, 0 },
8092     /* c8 */
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { "vphadddq",       { XM, EXxmm }, 0 },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     /* d0 */
8102     { Bad_Opcode },
8103     { "vphaddubw",      { XM, EXxmm }, 0 },
8104     { "vphaddubd",      { XM, EXxmm }, 0 },
8105     { "vphaddubq",      { XM, EXxmm }, 0 },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { "vphadduwd",      { XM, EXxmm }, 0 },
8109     { "vphadduwq",      { XM, EXxmm }, 0 },
8110     /* d8 */
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { "vphaddudq",      { XM, EXxmm }, 0 },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     /* e0 */
8120     { Bad_Opcode },
8121     { "vphsubbw",       { XM, EXxmm }, 0 },
8122     { "vphsubwd",       { XM, EXxmm }, 0 },
8123     { "vphsubdq",       { XM, EXxmm }, 0 },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     /* e8 */
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     /* f0 */
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     /* f8 */
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155   },
8156   /* XOP_0A */
8157   {
8158     /* 00 */
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     /* 08 */
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     /* 10 */
8177     { "bextrS", { Gdq, Edq, Id }, 0 },
8178     { Bad_Opcode },
8179     { REG_TABLE (REG_XOP_LWP) },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     /* 18 */
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     /* 20 */
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     /* 28 */
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     /* 30 */
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     /* 38 */
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     /* 40 */
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     /* 48 */
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     /* 50 */
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     /* 58 */
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     /* 60 */
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     /* 68 */
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     /* 70 */
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     /* 78 */
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     /* 80 */
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     /* 88 */
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     /* 90 */
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     /* 98 */
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     /* a0 */
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     /* a8 */
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     /* b0 */
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     /* b8 */
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     /* c0 */
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     /* c8 */
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     /* d0 */
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     /* d8 */
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     /* e0 */
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     /* e8 */
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     /* f0 */
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     /* f8 */
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446   },
8447 };
8448
8449 static const struct dis386 vex_table[][256] = {
8450   /* VEX_0F */
8451   {
8452     /* 00 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* 08 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* 10 */
8471     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8474     { MOD_TABLE (MOD_VEX_0F13) },
8475     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8476     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8477     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8478     { MOD_TABLE (MOD_VEX_0F17) },
8479     /* 18 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* 20 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     /* 28 */
8498     { "vmovapX",        { XM, EXx }, 0 },
8499     { "vmovapX",        { EXxS, XM }, 0 },
8500     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8501     { MOD_TABLE (MOD_VEX_0F2B) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8503     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8504     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8506     /* 30 */
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     /* 38 */
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     /* 40 */
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8528     { Bad_Opcode },
8529     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8533     /* 48 */
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     /* 50 */
8543     { MOD_TABLE (MOD_VEX_0F50) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8547     { "vandpX",         { XM, Vex, EXx }, 0 },
8548     { "vandnpX",        { XM, Vex, EXx }, 0 },
8549     { "vorpX",          { XM, Vex, EXx }, 0 },
8550     { "vxorpX",         { XM, Vex, EXx }, 0 },
8551     /* 58 */
8552     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8560     /* 60 */
8561     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8569     /* 68 */
8570     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8575     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8578     /* 70 */
8579     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8580     { REG_TABLE (REG_VEX_0F71) },
8581     { REG_TABLE (REG_VEX_0F72) },
8582     { REG_TABLE (REG_VEX_0F73) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8587     /* 78 */
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8594     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8596     /* 80 */
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     /* 88 */
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     /* 90 */
8615     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     /* 98 */
8624     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     /* a0 */
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     /* a8 */
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { REG_TABLE (REG_VEX_0FAE) },
8649     { Bad_Opcode },
8650     /* b0 */
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     /* b8 */
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     /* c0 */
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8672     { Bad_Opcode },
8673     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8675     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8676     { Bad_Opcode },
8677     /* c8 */
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     /* d0 */
8687     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8695     /* d8 */
8696     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8704     /* e0 */
8705     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8713     /* e8 */
8714     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8722     /* f0 */
8723     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8729     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8731     /* f8 */
8732     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8738     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8739     { Bad_Opcode },
8740   },
8741   /* VEX_0F38 */
8742   {
8743     /* 00 */
8744     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8752     /* 08 */
8753     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8761     /* 10 */
8762     { Bad_Opcode },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8770     /* 18 */
8771     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8774     { Bad_Opcode },
8775     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8778     { Bad_Opcode },
8779     /* 20 */
8780     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     /* 28 */
8789     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8797     /* 30 */
8798     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8803     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8806     /* 38 */
8807     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8815     /* 40 */
8816     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8822     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8824     /* 48 */
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     /* 50 */
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     /* 58 */
8843     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     /* 60 */
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     /* 68 */
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     /* 70 */
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     /* 78 */
8879     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     /* 80 */
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     /* 88 */
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8902     { Bad_Opcode },
8903     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8904     { Bad_Opcode },
8905     /* 90 */
8906     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8914     /* 98 */
8915     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8923     /* a0 */
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8932     /* a8 */
8933     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8941     /* b0 */
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8950     /* b8 */
8951     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8959     /* c0 */
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     /* c8 */
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8977     /* d0 */
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     /* d8 */
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8994     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8995     /* e0 */
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     /* e8 */
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     /* f0 */
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9017     { REG_TABLE (REG_VEX_0F38F3) },
9018     { Bad_Opcode },
9019     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9021     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9022     /* f8 */
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031   },
9032   /* VEX_0F3A */
9033   {
9034     /* 00 */
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9038     { Bad_Opcode },
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9042     { Bad_Opcode },
9043     /* 08 */
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9049     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9051     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9052     /* 10 */
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9061     /* 18 */
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     /* 20 */
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     /* 28 */
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     /* 30 */
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     /* 38 */
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     /* 40 */
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9110     { Bad_Opcode },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9112     { Bad_Opcode },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9114     { Bad_Opcode },
9115     /* 48 */
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     /* 50 */
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     /* 58 */
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9142     /* 60 */
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9146     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     /* 68 */
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9160     /* 70 */
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     /* 78 */
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9175     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9176     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9178     /* 80 */
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     /* 88 */
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     /* 90 */
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     /* 98 */
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     /* a0 */
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     /* a8 */
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     /* b0 */
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     /* b8 */
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     /* c0 */
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     /* c8 */
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9267     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9268     /* d0 */
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     /* d8 */
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9286     /* e0 */
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     /* e8 */
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     /* f0 */
9305     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     /* f8 */
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322   },
9323 };
9324
9325 #include "i386-dis-evex.h"
9326
9327 static const struct dis386 vex_len_table[][2] = {
9328   /* VEX_LEN_0F12_P_0_M_0 */
9329   {
9330     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9331   },
9332
9333   /* VEX_LEN_0F12_P_0_M_1 */
9334   {
9335     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9336   },
9337
9338   /* VEX_LEN_0F12_P_2 */
9339   {
9340     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9341   },
9342
9343   /* VEX_LEN_0F13_M_0 */
9344   {
9345     { "vmovlpX",        { EXq, XM }, 0 },
9346   },
9347
9348   /* VEX_LEN_0F16_P_0_M_0 */
9349   {
9350     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9351   },
9352
9353   /* VEX_LEN_0F16_P_0_M_1 */
9354   {
9355     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9356   },
9357
9358   /* VEX_LEN_0F16_P_2 */
9359   {
9360     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9361   },
9362
9363   /* VEX_LEN_0F17_M_0 */
9364   {
9365     { "vmovhpX",        { EXq, XM }, 0 },
9366   },
9367
9368   /* VEX_LEN_0F41_P_0 */
9369   {
9370     { Bad_Opcode },
9371     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9372   },
9373   /* VEX_LEN_0F41_P_2 */
9374   {
9375     { Bad_Opcode },
9376     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9377   },
9378   /* VEX_LEN_0F42_P_0 */
9379   {
9380     { Bad_Opcode },
9381     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9382   },
9383   /* VEX_LEN_0F42_P_2 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9387   },
9388   /* VEX_LEN_0F44_P_0 */
9389   {
9390     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9391   },
9392   /* VEX_LEN_0F44_P_2 */
9393   {
9394     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9395   },
9396   /* VEX_LEN_0F45_P_0 */
9397   {
9398     { Bad_Opcode },
9399     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9400   },
9401   /* VEX_LEN_0F45_P_2 */
9402   {
9403     { Bad_Opcode },
9404     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9405   },
9406   /* VEX_LEN_0F46_P_0 */
9407   {
9408     { Bad_Opcode },
9409     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9410   },
9411   /* VEX_LEN_0F46_P_2 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9415   },
9416   /* VEX_LEN_0F47_P_0 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9420   },
9421   /* VEX_LEN_0F47_P_2 */
9422   {
9423     { Bad_Opcode },
9424     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9425   },
9426   /* VEX_LEN_0F4A_P_0 */
9427   {
9428     { Bad_Opcode },
9429     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9430   },
9431   /* VEX_LEN_0F4A_P_2 */
9432   {
9433     { Bad_Opcode },
9434     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9435   },
9436   /* VEX_LEN_0F4B_P_0 */
9437   {
9438     { Bad_Opcode },
9439     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9440   },
9441   /* VEX_LEN_0F4B_P_2 */
9442   {
9443     { Bad_Opcode },
9444     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9445   },
9446
9447   /* VEX_LEN_0F6E_P_2 */
9448   {
9449     { "vmovK",          { XMScalar, Edq }, 0 },
9450   },
9451
9452   /* VEX_LEN_0F77_P_1 */
9453   {
9454     { "vzeroupper",     { XX }, 0 },
9455     { "vzeroall",       { XX }, 0 },
9456   },
9457
9458   /* VEX_LEN_0F7E_P_1 */
9459   {
9460     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9461   },
9462
9463   /* VEX_LEN_0F7E_P_2 */
9464   {
9465     { "vmovK",          { Edq, XMScalar }, 0 },
9466   },
9467
9468   /* VEX_LEN_0F90_P_0 */
9469   {
9470     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9471   },
9472
9473   /* VEX_LEN_0F90_P_2 */
9474   {
9475     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9476   },
9477
9478   /* VEX_LEN_0F91_P_0 */
9479   {
9480     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9481   },
9482
9483   /* VEX_LEN_0F91_P_2 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F92_P_0 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F92_P_2 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F92_P_3 */
9499   {
9500     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F93_P_0 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0F93_P_2 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9511   },
9512
9513   /* VEX_LEN_0F93_P_3 */
9514   {
9515     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0F98_P_0 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9521   },
9522
9523   /* VEX_LEN_0F98_P_2 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9526   },
9527
9528   /* VEX_LEN_0F99_P_0 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9531   },
9532
9533   /* VEX_LEN_0F99_P_2 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9536   },
9537
9538   /* VEX_LEN_0FAE_R_2_M_0 */
9539   {
9540     { "vldmxcsr",       { Md }, 0 },
9541   },
9542
9543   /* VEX_LEN_0FAE_R_3_M_0 */
9544   {
9545     { "vstmxcsr",       { Md }, 0 },
9546   },
9547
9548   /* VEX_LEN_0FC4_P_2 */
9549   {
9550     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9551   },
9552
9553   /* VEX_LEN_0FC5_P_2 */
9554   {
9555     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9556   },
9557
9558   /* VEX_LEN_0FD6_P_2 */
9559   {
9560     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9561   },
9562
9563   /* VEX_LEN_0FF7_P_2 */
9564   {
9565     { "vmaskmovdqu",    { XM, XS }, 0 },
9566   },
9567
9568   /* VEX_LEN_0F3816_P_2 */
9569   {
9570     { Bad_Opcode },
9571     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9572   },
9573
9574   /* VEX_LEN_0F3819_P_2 */
9575   {
9576     { Bad_Opcode },
9577     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9578   },
9579
9580   /* VEX_LEN_0F381A_P_2_M_0 */
9581   {
9582     { Bad_Opcode },
9583     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9584   },
9585
9586   /* VEX_LEN_0F3836_P_2 */
9587   {
9588     { Bad_Opcode },
9589     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9590   },
9591
9592   /* VEX_LEN_0F3841_P_2 */
9593   {
9594     { "vphminposuw",    { XM, EXx }, 0 },
9595   },
9596
9597   /* VEX_LEN_0F385A_P_2_M_0 */
9598   {
9599     { Bad_Opcode },
9600     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9601   },
9602
9603   /* VEX_LEN_0F38DB_P_2 */
9604   {
9605     { "vaesimc",        { XM, EXx }, 0 },
9606   },
9607
9608   /* VEX_LEN_0F38F2_P_0 */
9609   {
9610     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F38F3_R_1_P_0 */
9614   {
9615     { "blsrS",          { VexGdq, Edq }, 0 },
9616   },
9617
9618   /* VEX_LEN_0F38F3_R_2_P_0 */
9619   {
9620     { "blsmskS",        { VexGdq, Edq }, 0 },
9621   },
9622
9623   /* VEX_LEN_0F38F3_R_3_P_0 */
9624   {
9625     { "blsiS",          { VexGdq, Edq }, 0 },
9626   },
9627
9628   /* VEX_LEN_0F38F5_P_0 */
9629   {
9630     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9631   },
9632
9633   /* VEX_LEN_0F38F5_P_1 */
9634   {
9635     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9636   },
9637
9638   /* VEX_LEN_0F38F5_P_3 */
9639   {
9640     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9641   },
9642
9643   /* VEX_LEN_0F38F6_P_3 */
9644   {
9645     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9646   },
9647
9648   /* VEX_LEN_0F38F7_P_0 */
9649   {
9650     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9651   },
9652
9653   /* VEX_LEN_0F38F7_P_1 */
9654   {
9655     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9656   },
9657
9658   /* VEX_LEN_0F38F7_P_2 */
9659   {
9660     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9661   },
9662
9663   /* VEX_LEN_0F38F7_P_3 */
9664   {
9665     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9666   },
9667
9668   /* VEX_LEN_0F3A00_P_2 */
9669   {
9670     { Bad_Opcode },
9671     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9672   },
9673
9674   /* VEX_LEN_0F3A01_P_2 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9678   },
9679
9680   /* VEX_LEN_0F3A06_P_2 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9684   },
9685
9686   /* VEX_LEN_0F3A14_P_2 */
9687   {
9688     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9689   },
9690
9691   /* VEX_LEN_0F3A15_P_2 */
9692   {
9693     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F3A16_P_2  */
9697   {
9698     { "vpextrK",        { Edq, XM, Ib }, 0 },
9699   },
9700
9701   /* VEX_LEN_0F3A17_P_2 */
9702   {
9703     { "vextractps",     { Edqd, XM, Ib }, 0 },
9704   },
9705
9706   /* VEX_LEN_0F3A18_P_2 */
9707   {
9708     { Bad_Opcode },
9709     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9710   },
9711
9712   /* VEX_LEN_0F3A19_P_2 */
9713   {
9714     { Bad_Opcode },
9715     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9716   },
9717
9718   /* VEX_LEN_0F3A20_P_2 */
9719   {
9720     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9721   },
9722
9723   /* VEX_LEN_0F3A21_P_2 */
9724   {
9725     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9726   },
9727
9728   /* VEX_LEN_0F3A22_P_2 */
9729   {
9730     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9731   },
9732
9733   /* VEX_LEN_0F3A30_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9736   },
9737
9738   /* VEX_LEN_0F3A31_P_2 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9741   },
9742
9743   /* VEX_LEN_0F3A32_P_2 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9746   },
9747
9748   /* VEX_LEN_0F3A33_P_2 */
9749   {
9750     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9751   },
9752
9753   /* VEX_LEN_0F3A38_P_2 */
9754   {
9755     { Bad_Opcode },
9756     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9757   },
9758
9759   /* VEX_LEN_0F3A39_P_2 */
9760   {
9761     { Bad_Opcode },
9762     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9763   },
9764
9765   /* VEX_LEN_0F3A41_P_2 */
9766   {
9767     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9768   },
9769
9770   /* VEX_LEN_0F3A46_P_2 */
9771   {
9772     { Bad_Opcode },
9773     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9774   },
9775
9776   /* VEX_LEN_0F3A60_P_2 */
9777   {
9778     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9779   },
9780
9781   /* VEX_LEN_0F3A61_P_2 */
9782   {
9783     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9784   },
9785
9786   /* VEX_LEN_0F3A62_P_2 */
9787   {
9788     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9789   },
9790
9791   /* VEX_LEN_0F3A63_P_2 */
9792   {
9793     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9794   },
9795
9796   /* VEX_LEN_0F3A6A_P_2 */
9797   {
9798     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9799   },
9800
9801   /* VEX_LEN_0F3A6B_P_2 */
9802   {
9803     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9804   },
9805
9806   /* VEX_LEN_0F3A6E_P_2 */
9807   {
9808     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9809   },
9810
9811   /* VEX_LEN_0F3A6F_P_2 */
9812   {
9813     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9814   },
9815
9816   /* VEX_LEN_0F3A7A_P_2 */
9817   {
9818     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9819   },
9820
9821   /* VEX_LEN_0F3A7B_P_2 */
9822   {
9823     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9824   },
9825
9826   /* VEX_LEN_0F3A7E_P_2 */
9827   {
9828     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9829   },
9830
9831   /* VEX_LEN_0F3A7F_P_2 */
9832   {
9833     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9834   },
9835
9836   /* VEX_LEN_0F3ADF_P_2 */
9837   {
9838     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9839   },
9840
9841   /* VEX_LEN_0F3AF0_P_3 */
9842   {
9843     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9844   },
9845
9846   /* VEX_LEN_0FXOP_08_CC */
9847   {
9848      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9849   },
9850
9851   /* VEX_LEN_0FXOP_08_CD */
9852   {
9853      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9854   },
9855
9856   /* VEX_LEN_0FXOP_08_CE */
9857   {
9858      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9859   },
9860
9861   /* VEX_LEN_0FXOP_08_CF */
9862   {
9863      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9864   },
9865
9866   /* VEX_LEN_0FXOP_08_EC */
9867   {
9868      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9869   },
9870
9871   /* VEX_LEN_0FXOP_08_ED */
9872   {
9873      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9874   },
9875
9876   /* VEX_LEN_0FXOP_08_EE */
9877   {
9878      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9879   },
9880
9881   /* VEX_LEN_0FXOP_08_EF */
9882   {
9883      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9884   },
9885
9886   /* VEX_LEN_0FXOP_09_80 */
9887   {
9888     { "vfrczps",        { XM, EXxmm }, 0 },
9889     { "vfrczps",        { XM, EXymmq }, 0 },
9890   },
9891
9892   /* VEX_LEN_0FXOP_09_81 */
9893   {
9894     { "vfrczpd",        { XM, EXxmm }, 0 },
9895     { "vfrczpd",        { XM, EXymmq }, 0 },
9896   },
9897 };
9898
9899 #include "i386-dis-evex-len.h"
9900
9901 static const struct dis386 vex_w_table[][2] = {
9902   {
9903     /* VEX_W_0F41_P_0_LEN_1 */
9904     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9905     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9906   },
9907   {
9908     /* VEX_W_0F41_P_2_LEN_1 */
9909     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9910     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9911   },
9912   {
9913     /* VEX_W_0F42_P_0_LEN_1 */
9914     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9915     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9916   },
9917   {
9918     /* VEX_W_0F42_P_2_LEN_1 */
9919     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9920     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9921   },
9922   {
9923     /* VEX_W_0F44_P_0_LEN_0 */
9924     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9925     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9926   },
9927   {
9928     /* VEX_W_0F44_P_2_LEN_0 */
9929     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9930     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9931   },
9932   {
9933     /* VEX_W_0F45_P_0_LEN_1 */
9934     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9935     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9936   },
9937   {
9938     /* VEX_W_0F45_P_2_LEN_1 */
9939     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9940     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9941   },
9942   {
9943     /* VEX_W_0F46_P_0_LEN_1 */
9944     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9945     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9946   },
9947   {
9948     /* VEX_W_0F46_P_2_LEN_1 */
9949     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9950     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9951   },
9952   {
9953     /* VEX_W_0F47_P_0_LEN_1 */
9954     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9955     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9956   },
9957   {
9958     /* VEX_W_0F47_P_2_LEN_1 */
9959     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9960     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9961   },
9962   {
9963     /* VEX_W_0F4A_P_0_LEN_1 */
9964     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9965     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9966   },
9967   {
9968     /* VEX_W_0F4A_P_2_LEN_1 */
9969     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9970     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9971   },
9972   {
9973     /* VEX_W_0F4B_P_0_LEN_1 */
9974     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9975     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9976   },
9977   {
9978     /* VEX_W_0F4B_P_2_LEN_1 */
9979     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9980   },
9981   {
9982     /* VEX_W_0F90_P_0_LEN_0 */
9983     { "kmovw",          { MaskG, MaskE }, 0 },
9984     { "kmovq",          { MaskG, MaskE }, 0 },
9985   },
9986   {
9987     /* VEX_W_0F90_P_2_LEN_0 */
9988     { "kmovb",          { MaskG, MaskBDE }, 0 },
9989     { "kmovd",          { MaskG, MaskBDE }, 0 },
9990   },
9991   {
9992     /* VEX_W_0F91_P_0_LEN_0 */
9993     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9994     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9995   },
9996   {
9997     /* VEX_W_0F91_P_2_LEN_0 */
9998     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9999     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10000   },
10001   {
10002     /* VEX_W_0F92_P_0_LEN_0 */
10003     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10004   },
10005   {
10006     /* VEX_W_0F92_P_2_LEN_0 */
10007     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10008   },
10009   {
10010     /* VEX_W_0F93_P_0_LEN_0 */
10011     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10012   },
10013   {
10014     /* VEX_W_0F93_P_2_LEN_0 */
10015     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10016   },
10017   {
10018     /* VEX_W_0F98_P_0_LEN_0 */
10019     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10020     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10021   },
10022   {
10023     /* VEX_W_0F98_P_2_LEN_0 */
10024     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10025     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10026   },
10027   {
10028     /* VEX_W_0F99_P_0_LEN_0 */
10029     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10030     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10031   },
10032   {
10033     /* VEX_W_0F99_P_2_LEN_0 */
10034     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10035     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10036   },
10037   {
10038     /* VEX_W_0F380C_P_2  */
10039     { "vpermilps",      { XM, Vex, EXx }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F380D_P_2  */
10043     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F380E_P_2  */
10047     { "vtestps",        { XM, EXx }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F380F_P_2  */
10051     { "vtestpd",        { XM, EXx }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F3816_P_2  */
10055     { "vpermps",        { XM, Vex, EXx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3818_P_2 */
10059     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F3819_P_2 */
10063     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F381A_P_2_M_0 */
10067     { "vbroadcastf128", { XM, Mxmm }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F382C_P_2_M_0 */
10071     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F382D_P_2_M_0 */
10075     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F382E_P_2_M_0 */
10079     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F382F_P_2_M_0 */
10083     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F3836_P_2  */
10087     { "vpermd",         { XM, Vex, EXx }, 0 },
10088   },
10089   {
10090     /* VEX_W_0F3846_P_2 */
10091     { "vpsravd",        { XM, Vex, EXx }, 0 },
10092   },
10093   {
10094     /* VEX_W_0F3858_P_2 */
10095     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10096   },
10097   {
10098     /* VEX_W_0F3859_P_2 */
10099     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10100   },
10101   {
10102     /* VEX_W_0F385A_P_2_M_0 */
10103     { "vbroadcasti128", { XM, Mxmm }, 0 },
10104   },
10105   {
10106     /* VEX_W_0F3878_P_2 */
10107     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10108   },
10109   {
10110     /* VEX_W_0F3879_P_2 */
10111     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10112   },
10113   {
10114     /* VEX_W_0F38CF_P_2 */
10115     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10116   },
10117   {
10118     /* VEX_W_0F3A00_P_2 */
10119     { Bad_Opcode },
10120     { "vpermq",         { XM, EXx, Ib }, 0 },
10121   },
10122   {
10123     /* VEX_W_0F3A01_P_2 */
10124     { Bad_Opcode },
10125     { "vpermpd",        { XM, EXx, Ib }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F3A02_P_2 */
10129     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F3A04_P_2 */
10133     { "vpermilps",      { XM, EXx, Ib }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F3A05_P_2 */
10137     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10138   },
10139   {
10140     /* VEX_W_0F3A06_P_2 */
10141     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10142   },
10143   {
10144     /* VEX_W_0F3A18_P_2 */
10145     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10146   },
10147   {
10148     /* VEX_W_0F3A19_P_2 */
10149     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10150   },
10151   {
10152     /* VEX_W_0F3A30_P_2_LEN_0 */
10153     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10154     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10155   },
10156   {
10157     /* VEX_W_0F3A31_P_2_LEN_0 */
10158     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10159     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10160   },
10161   {
10162     /* VEX_W_0F3A32_P_2_LEN_0 */
10163     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10164     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10165   },
10166   {
10167     /* VEX_W_0F3A33_P_2_LEN_0 */
10168     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10169     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10170   },
10171   {
10172     /* VEX_W_0F3A38_P_2 */
10173     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F3A39_P_2 */
10177     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10178   },
10179   {
10180     /* VEX_W_0F3A46_P_2 */
10181     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10182   },
10183   {
10184     /* VEX_W_0F3A48_P_2 */
10185     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10186     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10187   },
10188   {
10189     /* VEX_W_0F3A49_P_2 */
10190     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10191     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10192   },
10193   {
10194     /* VEX_W_0F3A4A_P_2 */
10195     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10196   },
10197   {
10198     /* VEX_W_0F3A4B_P_2 */
10199     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10200   },
10201   {
10202     /* VEX_W_0F3A4C_P_2 */
10203     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10204   },
10205   {
10206     /* VEX_W_0F3ACE_P_2 */
10207     { Bad_Opcode },
10208     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10209   },
10210   {
10211     /* VEX_W_0F3ACF_P_2 */
10212     { Bad_Opcode },
10213     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10214   },
10215
10216 #include "i386-dis-evex-w.h"
10217 };
10218
10219 static const struct dis386 mod_table[][2] = {
10220   {
10221     /* MOD_8D */
10222     { "leaS",           { Gv, M }, 0 },
10223   },
10224   {
10225     /* MOD_C6_REG_7 */
10226     { Bad_Opcode },
10227     { RM_TABLE (RM_C6_REG_7) },
10228   },
10229   {
10230     /* MOD_C7_REG_7 */
10231     { Bad_Opcode },
10232     { RM_TABLE (RM_C7_REG_7) },
10233   },
10234   {
10235     /* MOD_FF_REG_3 */
10236     { "Jcall^", { indirEp }, 0 },
10237   },
10238   {
10239     /* MOD_FF_REG_5 */
10240     { "Jjmp^", { indirEp }, 0 },
10241   },
10242   {
10243     /* MOD_0F01_REG_0 */
10244     { X86_64_TABLE (X86_64_0F01_REG_0) },
10245     { RM_TABLE (RM_0F01_REG_0) },
10246   },
10247   {
10248     /* MOD_0F01_REG_1 */
10249     { X86_64_TABLE (X86_64_0F01_REG_1) },
10250     { RM_TABLE (RM_0F01_REG_1) },
10251   },
10252   {
10253     /* MOD_0F01_REG_2 */
10254     { X86_64_TABLE (X86_64_0F01_REG_2) },
10255     { RM_TABLE (RM_0F01_REG_2) },
10256   },
10257   {
10258     /* MOD_0F01_REG_3 */
10259     { X86_64_TABLE (X86_64_0F01_REG_3) },
10260     { RM_TABLE (RM_0F01_REG_3) },
10261   },
10262   {
10263     /* MOD_0F01_REG_5 */
10264     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10265     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10266   },
10267   {
10268     /* MOD_0F01_REG_7 */
10269     { "invlpg",         { Mb }, 0 },
10270     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10271   },
10272   {
10273     /* MOD_0F12_PREFIX_0 */
10274     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10275     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10276   },
10277   {
10278     /* MOD_0F13 */
10279     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10280   },
10281   {
10282     /* MOD_0F16_PREFIX_0 */
10283     { "movhps",         { XM, EXq }, 0 },
10284     { "movlhps",        { XM, EXq }, 0 },
10285   },
10286   {
10287     /* MOD_0F17 */
10288     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10289   },
10290   {
10291     /* MOD_0F18_REG_0 */
10292     { "prefetchnta",    { Mb }, 0 },
10293   },
10294   {
10295     /* MOD_0F18_REG_1 */
10296     { "prefetcht0",     { Mb }, 0 },
10297   },
10298   {
10299     /* MOD_0F18_REG_2 */
10300     { "prefetcht1",     { Mb }, 0 },
10301   },
10302   {
10303     /* MOD_0F18_REG_3 */
10304     { "prefetcht2",     { Mb }, 0 },
10305   },
10306   {
10307     /* MOD_0F18_REG_4 */
10308     { "nop/reserved",   { Mb }, 0 },
10309   },
10310   {
10311     /* MOD_0F18_REG_5 */
10312     { "nop/reserved",   { Mb }, 0 },
10313   },
10314   {
10315     /* MOD_0F18_REG_6 */
10316     { "nop/reserved",   { Mb }, 0 },
10317   },
10318   {
10319     /* MOD_0F18_REG_7 */
10320     { "nop/reserved",   { Mb }, 0 },
10321   },
10322   {
10323     /* MOD_0F1A_PREFIX_0 */
10324     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10325     { "nopQ",           { Ev }, 0 },
10326   },
10327   {
10328     /* MOD_0F1B_PREFIX_0 */
10329     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10330     { "nopQ",           { Ev }, 0 },
10331   },
10332   {
10333     /* MOD_0F1B_PREFIX_1 */
10334     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10335     { "nopQ",           { Ev }, 0 },
10336   },
10337   {
10338     /* MOD_0F1C_PREFIX_0 */
10339     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10340     { "nopQ",           { Ev }, 0 },
10341   },
10342   {
10343     /* MOD_0F1E_PREFIX_1 */
10344     { "nopQ",           { Ev }, 0 },
10345     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10346   },
10347   {
10348     /* MOD_0F24 */
10349     { Bad_Opcode },
10350     { "movL",           { Rd, Td }, 0 },
10351   },
10352   {
10353     /* MOD_0F26 */
10354     { Bad_Opcode },
10355     { "movL",           { Td, Rd }, 0 },
10356   },
10357   {
10358     /* MOD_0F2B_PREFIX_0 */
10359     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10360   },
10361   {
10362     /* MOD_0F2B_PREFIX_1 */
10363     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10364   },
10365   {
10366     /* MOD_0F2B_PREFIX_2 */
10367     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10368   },
10369   {
10370     /* MOD_0F2B_PREFIX_3 */
10371     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10372   },
10373   {
10374     /* MOD_0F51 */
10375     { Bad_Opcode },
10376     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10377   },
10378   {
10379     /* MOD_0F71_REG_2 */
10380     { Bad_Opcode },
10381     { "psrlw",          { MS, Ib }, 0 },
10382   },
10383   {
10384     /* MOD_0F71_REG_4 */
10385     { Bad_Opcode },
10386     { "psraw",          { MS, Ib }, 0 },
10387   },
10388   {
10389     /* MOD_0F71_REG_6 */
10390     { Bad_Opcode },
10391     { "psllw",          { MS, Ib }, 0 },
10392   },
10393   {
10394     /* MOD_0F72_REG_2 */
10395     { Bad_Opcode },
10396     { "psrld",          { MS, Ib }, 0 },
10397   },
10398   {
10399     /* MOD_0F72_REG_4 */
10400     { Bad_Opcode },
10401     { "psrad",          { MS, Ib }, 0 },
10402   },
10403   {
10404     /* MOD_0F72_REG_6 */
10405     { Bad_Opcode },
10406     { "pslld",          { MS, Ib }, 0 },
10407   },
10408   {
10409     /* MOD_0F73_REG_2 */
10410     { Bad_Opcode },
10411     { "psrlq",          { MS, Ib }, 0 },
10412   },
10413   {
10414     /* MOD_0F73_REG_3 */
10415     { Bad_Opcode },
10416     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10417   },
10418   {
10419     /* MOD_0F73_REG_6 */
10420     { Bad_Opcode },
10421     { "psllq",          { MS, Ib }, 0 },
10422   },
10423   {
10424     /* MOD_0F73_REG_7 */
10425     { Bad_Opcode },
10426     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10427   },
10428   {
10429     /* MOD_0FAE_REG_0 */
10430     { "fxsave",         { FXSAVE }, 0 },
10431     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10432   },
10433   {
10434     /* MOD_0FAE_REG_1 */
10435     { "fxrstor",        { FXSAVE }, 0 },
10436     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10437   },
10438   {
10439     /* MOD_0FAE_REG_2 */
10440     { "ldmxcsr",        { Md }, 0 },
10441     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10442   },
10443   {
10444     /* MOD_0FAE_REG_3 */
10445     { "stmxcsr",        { Md }, 0 },
10446     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10447   },
10448   {
10449     /* MOD_0FAE_REG_4 */
10450     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10451     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10452   },
10453   {
10454     /* MOD_0FAE_REG_5 */
10455     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10456     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10457   },
10458   {
10459     /* MOD_0FAE_REG_6 */
10460     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10461     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10462   },
10463   {
10464     /* MOD_0FAE_REG_7 */
10465     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10466     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10467   },
10468   {
10469     /* MOD_0FB2 */
10470     { "lssS",           { Gv, Mp }, 0 },
10471   },
10472   {
10473     /* MOD_0FB4 */
10474     { "lfsS",           { Gv, Mp }, 0 },
10475   },
10476   {
10477     /* MOD_0FB5 */
10478     { "lgsS",           { Gv, Mp }, 0 },
10479   },
10480   {
10481     /* MOD_0FC3 */
10482     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10483   },
10484   {
10485     /* MOD_0FC7_REG_3 */
10486     { "xrstors",        { FXSAVE }, 0 },
10487   },
10488   {
10489     /* MOD_0FC7_REG_4 */
10490     { "xsavec",         { FXSAVE }, 0 },
10491   },
10492   {
10493     /* MOD_0FC7_REG_5 */
10494     { "xsaves",         { FXSAVE }, 0 },
10495   },
10496   {
10497     /* MOD_0FC7_REG_6 */
10498     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10499     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10500   },
10501   {
10502     /* MOD_0FC7_REG_7 */
10503     { "vmptrst",        { Mq }, 0 },
10504     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10505   },
10506   {
10507     /* MOD_0FD7 */
10508     { Bad_Opcode },
10509     { "pmovmskb",       { Gdq, MS }, 0 },
10510   },
10511   {
10512     /* MOD_0FE7_PREFIX_2 */
10513     { "movntdq",        { Mx, XM }, 0 },
10514   },
10515   {
10516     /* MOD_0FF0_PREFIX_3 */
10517     { "lddqu",          { XM, M }, 0 },
10518   },
10519   {
10520     /* MOD_0F382A_PREFIX_2 */
10521     { "movntdqa",       { XM, Mx }, 0 },
10522   },
10523   {
10524     /* MOD_0F38F5_PREFIX_2 */
10525     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10526   },
10527   {
10528     /* MOD_0F38F6_PREFIX_0 */
10529     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10530   },
10531   {
10532     /* MOD_0F38F8_PREFIX_1 */
10533     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10534   },
10535   {
10536     /* MOD_0F38F8_PREFIX_2 */
10537     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10538   },
10539   {
10540     /* MOD_0F38F8_PREFIX_3 */
10541     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10542   },
10543   {
10544     /* MOD_0F38F9_PREFIX_0 */
10545     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10546   },
10547   {
10548     /* MOD_62_32BIT */
10549     { "bound{S|}",      { Gv, Ma }, 0 },
10550     { EVEX_TABLE (EVEX_0F) },
10551   },
10552   {
10553     /* MOD_C4_32BIT */
10554     { "lesS",           { Gv, Mp }, 0 },
10555     { VEX_C4_TABLE (VEX_0F) },
10556   },
10557   {
10558     /* MOD_C5_32BIT */
10559     { "ldsS",           { Gv, Mp }, 0 },
10560     { VEX_C5_TABLE (VEX_0F) },
10561   },
10562   {
10563     /* MOD_VEX_0F12_PREFIX_0 */
10564     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10565     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10566   },
10567   {
10568     /* MOD_VEX_0F13 */
10569     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10570   },
10571   {
10572     /* MOD_VEX_0F16_PREFIX_0 */
10573     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10574     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10575   },
10576   {
10577     /* MOD_VEX_0F17 */
10578     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10579   },
10580   {
10581     /* MOD_VEX_0F2B */
10582     { "vmovntpX",       { Mx, XM }, 0 },
10583   },
10584   {
10585     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10586     { Bad_Opcode },
10587     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10588   },
10589   {
10590     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10591     { Bad_Opcode },
10592     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10593   },
10594   {
10595     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10596     { Bad_Opcode },
10597     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10598   },
10599   {
10600     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10601     { Bad_Opcode },
10602     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10603   },
10604   {
10605     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10606     { Bad_Opcode },
10607     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10608   },
10609   {
10610     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10611     { Bad_Opcode },
10612     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10613   },
10614   {
10615     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10616     { Bad_Opcode },
10617     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10618   },
10619   {
10620     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10621     { Bad_Opcode },
10622     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10623   },
10624   {
10625     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10626     { Bad_Opcode },
10627     { "knotw",          { MaskG, MaskR }, 0 },
10628   },
10629   {
10630     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10631     { Bad_Opcode },
10632     { "knotq",          { MaskG, MaskR }, 0 },
10633   },
10634   {
10635     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10636     { Bad_Opcode },
10637     { "knotb",          { MaskG, MaskR }, 0 },
10638   },
10639   {
10640     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10641     { Bad_Opcode },
10642     { "knotd",          { MaskG, MaskR }, 0 },
10643   },
10644   {
10645     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10646     { Bad_Opcode },
10647     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10648   },
10649   {
10650     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10651     { Bad_Opcode },
10652     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10653   },
10654   {
10655     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10656     { Bad_Opcode },
10657     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10658   },
10659   {
10660     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10661     { Bad_Opcode },
10662     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10663   },
10664  {
10665     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10666     { Bad_Opcode },
10667     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10668   },
10669   {
10670     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10671     { Bad_Opcode },
10672     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10673   },
10674   {
10675     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10676     { Bad_Opcode },
10677     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10678   },
10679   {
10680     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10681     { Bad_Opcode },
10682     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10683   },
10684   {
10685     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10686     { Bad_Opcode },
10687     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10688   },
10689   {
10690     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10691     { Bad_Opcode },
10692     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10693   },
10694   {
10695     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10696     { Bad_Opcode },
10697     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10698   },
10699   {
10700     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10701     { Bad_Opcode },
10702     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10703   },
10704   {
10705     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10706     { Bad_Opcode },
10707     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10708   },
10709   {
10710     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10711     { Bad_Opcode },
10712     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10713   },
10714   {
10715     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10716     { Bad_Opcode },
10717     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10718   },
10719   {
10720     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10721     { Bad_Opcode },
10722     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10723   },
10724   {
10725     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10726     { Bad_Opcode },
10727     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10728   },
10729   {
10730     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10731     { Bad_Opcode },
10732     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10733   },
10734   {
10735     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10736     { Bad_Opcode },
10737     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10738   },
10739   {
10740     /* MOD_VEX_0F50 */
10741     { Bad_Opcode },
10742     { "vmovmskpX",      { Gdq, XS }, 0 },
10743   },
10744   {
10745     /* MOD_VEX_0F71_REG_2 */
10746     { Bad_Opcode },
10747     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10748   },
10749   {
10750     /* MOD_VEX_0F71_REG_4 */
10751     { Bad_Opcode },
10752     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10753   },
10754   {
10755     /* MOD_VEX_0F71_REG_6 */
10756     { Bad_Opcode },
10757     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10758   },
10759   {
10760     /* MOD_VEX_0F72_REG_2 */
10761     { Bad_Opcode },
10762     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10763   },
10764   {
10765     /* MOD_VEX_0F72_REG_4 */
10766     { Bad_Opcode },
10767     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10768   },
10769   {
10770     /* MOD_VEX_0F72_REG_6 */
10771     { Bad_Opcode },
10772     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10773   },
10774   {
10775     /* MOD_VEX_0F73_REG_2 */
10776     { Bad_Opcode },
10777     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10778   },
10779   {
10780     /* MOD_VEX_0F73_REG_3 */
10781     { Bad_Opcode },
10782     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10783   },
10784   {
10785     /* MOD_VEX_0F73_REG_6 */
10786     { Bad_Opcode },
10787     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10788   },
10789   {
10790     /* MOD_VEX_0F73_REG_7 */
10791     { Bad_Opcode },
10792     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10793   },
10794   {
10795     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10796     { "kmovw",          { Ew, MaskG }, 0 },
10797     { Bad_Opcode },
10798   },
10799   {
10800     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10801     { "kmovq",          { Eq, MaskG }, 0 },
10802     { Bad_Opcode },
10803   },
10804   {
10805     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10806     { "kmovb",          { Eb, MaskG }, 0 },
10807     { Bad_Opcode },
10808   },
10809   {
10810     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10811     { "kmovd",          { Ed, MaskG }, 0 },
10812     { Bad_Opcode },
10813   },
10814   {
10815     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10816     { Bad_Opcode },
10817     { "kmovw",          { MaskG, Rdq }, 0 },
10818   },
10819   {
10820     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10821     { Bad_Opcode },
10822     { "kmovb",          { MaskG, Rdq }, 0 },
10823   },
10824   {
10825     /* MOD_VEX_0F92_P_3_LEN_0 */
10826     { Bad_Opcode },
10827     { "kmovK",          { MaskG, Rdq }, 0 },
10828   },
10829   {
10830     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10831     { Bad_Opcode },
10832     { "kmovw",          { Gdq, MaskR }, 0 },
10833   },
10834   {
10835     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10836     { Bad_Opcode },
10837     { "kmovb",          { Gdq, MaskR }, 0 },
10838   },
10839   {
10840     /* MOD_VEX_0F93_P_3_LEN_0 */
10841     { Bad_Opcode },
10842     { "kmovK",          { Gdq, MaskR }, 0 },
10843   },
10844   {
10845     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10846     { Bad_Opcode },
10847     { "kortestw", { MaskG, MaskR }, 0 },
10848   },
10849   {
10850     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10851     { Bad_Opcode },
10852     { "kortestq", { MaskG, MaskR }, 0 },
10853   },
10854   {
10855     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10856     { Bad_Opcode },
10857     { "kortestb", { MaskG, MaskR }, 0 },
10858   },
10859   {
10860     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10861     { Bad_Opcode },
10862     { "kortestd", { MaskG, MaskR }, 0 },
10863   },
10864   {
10865     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10866     { Bad_Opcode },
10867     { "ktestw", { MaskG, MaskR }, 0 },
10868   },
10869   {
10870     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10871     { Bad_Opcode },
10872     { "ktestq", { MaskG, MaskR }, 0 },
10873   },
10874   {
10875     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10876     { Bad_Opcode },
10877     { "ktestb", { MaskG, MaskR }, 0 },
10878   },
10879   {
10880     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10881     { Bad_Opcode },
10882     { "ktestd", { MaskG, MaskR }, 0 },
10883   },
10884   {
10885     /* MOD_VEX_0FAE_REG_2 */
10886     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10887   },
10888   {
10889     /* MOD_VEX_0FAE_REG_3 */
10890     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10891   },
10892   {
10893     /* MOD_VEX_0FD7_PREFIX_2 */
10894     { Bad_Opcode },
10895     { "vpmovmskb",      { Gdq, XS }, 0 },
10896   },
10897   {
10898     /* MOD_VEX_0FE7_PREFIX_2 */
10899     { "vmovntdq",       { Mx, XM }, 0 },
10900   },
10901   {
10902     /* MOD_VEX_0FF0_PREFIX_3 */
10903     { "vlddqu",         { XM, M }, 0 },
10904   },
10905   {
10906     /* MOD_VEX_0F381A_PREFIX_2 */
10907     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10908   },
10909   {
10910     /* MOD_VEX_0F382A_PREFIX_2 */
10911     { "vmovntdqa",      { XM, Mx }, 0 },
10912   },
10913   {
10914     /* MOD_VEX_0F382C_PREFIX_2 */
10915     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10916   },
10917   {
10918     /* MOD_VEX_0F382D_PREFIX_2 */
10919     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10920   },
10921   {
10922     /* MOD_VEX_0F382E_PREFIX_2 */
10923     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10924   },
10925   {
10926     /* MOD_VEX_0F382F_PREFIX_2 */
10927     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10928   },
10929   {
10930     /* MOD_VEX_0F385A_PREFIX_2 */
10931     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10932   },
10933   {
10934     /* MOD_VEX_0F388C_PREFIX_2 */
10935     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10936   },
10937   {
10938     /* MOD_VEX_0F388E_PREFIX_2 */
10939     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10940   },
10941   {
10942     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10943     { Bad_Opcode },
10944     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10945   },
10946   {
10947     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10948     { Bad_Opcode },
10949     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10950   },
10951   {
10952     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10953     { Bad_Opcode },
10954     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10955   },
10956   {
10957     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10958     { Bad_Opcode },
10959     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10960   },
10961   {
10962     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10963     { Bad_Opcode },
10964     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10965   },
10966   {
10967     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10968     { Bad_Opcode },
10969     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10970   },
10971   {
10972     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10973     { Bad_Opcode },
10974     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10975   },
10976   {
10977     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10978     { Bad_Opcode },
10979     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10980   },
10981
10982 #include "i386-dis-evex-mod.h"
10983 };
10984
10985 static const struct dis386 rm_table[][8] = {
10986   {
10987     /* RM_C6_REG_7 */
10988     { "xabort",         { Skip_MODRM, Ib }, 0 },
10989   },
10990   {
10991     /* RM_C7_REG_7 */
10992     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10993   },
10994   {
10995     /* RM_0F01_REG_0 */
10996     { "enclv",          { Skip_MODRM }, 0 },
10997     { "vmcall",         { Skip_MODRM }, 0 },
10998     { "vmlaunch",       { Skip_MODRM }, 0 },
10999     { "vmresume",       { Skip_MODRM }, 0 },
11000     { "vmxoff",         { Skip_MODRM }, 0 },
11001     { "pconfig",        { Skip_MODRM }, 0 },
11002   },
11003   {
11004     /* RM_0F01_REG_1 */
11005     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11006     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11007     { "clac",           { Skip_MODRM }, 0 },
11008     { "stac",           { Skip_MODRM }, 0 },
11009     { Bad_Opcode },
11010     { Bad_Opcode },
11011     { Bad_Opcode },
11012     { "encls",          { Skip_MODRM }, 0 },
11013   },
11014   {
11015     /* RM_0F01_REG_2 */
11016     { "xgetbv",         { Skip_MODRM }, 0 },
11017     { "xsetbv",         { Skip_MODRM }, 0 },
11018     { Bad_Opcode },
11019     { Bad_Opcode },
11020     { "vmfunc",         { Skip_MODRM }, 0 },
11021     { "xend",           { Skip_MODRM }, 0 },
11022     { "xtest",          { Skip_MODRM }, 0 },
11023     { "enclu",          { Skip_MODRM }, 0 },
11024   },
11025   {
11026     /* RM_0F01_REG_3 */
11027     { "vmrun",          { Skip_MODRM }, 0 },
11028     { "vmmcall",        { Skip_MODRM }, 0 },
11029     { "vmload",         { Skip_MODRM }, 0 },
11030     { "vmsave",         { Skip_MODRM }, 0 },
11031     { "stgi",           { Skip_MODRM }, 0 },
11032     { "clgi",           { Skip_MODRM }, 0 },
11033     { "skinit",         { Skip_MODRM }, 0 },
11034     { "invlpga",        { Skip_MODRM }, 0 },
11035   },
11036   {
11037     /* RM_0F01_REG_5_MOD_3 */
11038     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11039     { Bad_Opcode },
11040     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11041     { Bad_Opcode },
11042     { Bad_Opcode },
11043     { Bad_Opcode },
11044     { "rdpkru",         { Skip_MODRM }, 0 },
11045     { "wrpkru",         { Skip_MODRM }, 0 },
11046   },
11047   {
11048     /* RM_0F01_REG_7_MOD_3 */
11049     { "swapgs",         { Skip_MODRM }, 0  },
11050     { "rdtscp",         { Skip_MODRM }, 0  },
11051     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11052     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11053     { "clzero",         { Skip_MODRM }, 0  },
11054     { "rdpru",          { Skip_MODRM }, 0  },
11055   },
11056   {
11057     /* RM_0F1E_P_1_MOD_3_REG_7 */
11058     { "nopQ",           { Ev }, 0 },
11059     { "nopQ",           { Ev }, 0 },
11060     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11061     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11062     { "nopQ",           { Ev }, 0 },
11063     { "nopQ",           { Ev }, 0 },
11064     { "nopQ",           { Ev }, 0 },
11065     { "nopQ",           { Ev }, 0 },
11066   },
11067   {
11068     /* RM_0FAE_REG_6_MOD_3 */
11069     { "mfence",         { Skip_MODRM }, 0 },
11070   },
11071   {
11072     /* RM_0FAE_REG_7_MOD_3 */
11073     { "sfence",         { Skip_MODRM }, 0 },
11074
11075   },
11076 };
11077
11078 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11079
11080 /* We use the high bit to indicate different name for the same
11081    prefix.  */
11082 #define REP_PREFIX      (0xf3 | 0x100)
11083 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11084 #define XRELEASE_PREFIX (0xf3 | 0x400)
11085 #define BND_PREFIX      (0xf2 | 0x400)
11086 #define NOTRACK_PREFIX  (0x3e | 0x100)
11087
11088 /* Remember if the current op is a jump instruction.  */
11089 static bfd_boolean op_is_jump = FALSE;
11090
11091 static int
11092 ckprefix (void)
11093 {
11094   int newrex, i, length;
11095   rex = 0;
11096   rex_ignored = 0;
11097   prefixes = 0;
11098   used_prefixes = 0;
11099   rex_used = 0;
11100   last_lock_prefix = -1;
11101   last_repz_prefix = -1;
11102   last_repnz_prefix = -1;
11103   last_data_prefix = -1;
11104   last_addr_prefix = -1;
11105   last_rex_prefix = -1;
11106   last_seg_prefix = -1;
11107   fwait_prefix = -1;
11108   active_seg_prefix = 0;
11109   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11110     all_prefixes[i] = 0;
11111   i = 0;
11112   length = 0;
11113   /* The maximum instruction length is 15bytes.  */
11114   while (length < MAX_CODE_LENGTH - 1)
11115     {
11116       FETCH_DATA (the_info, codep + 1);
11117       newrex = 0;
11118       switch (*codep)
11119         {
11120         /* REX prefixes family.  */
11121         case 0x40:
11122         case 0x41:
11123         case 0x42:
11124         case 0x43:
11125         case 0x44:
11126         case 0x45:
11127         case 0x46:
11128         case 0x47:
11129         case 0x48:
11130         case 0x49:
11131         case 0x4a:
11132         case 0x4b:
11133         case 0x4c:
11134         case 0x4d:
11135         case 0x4e:
11136         case 0x4f:
11137           if (address_mode == mode_64bit)
11138             newrex = *codep;
11139           else
11140             return 1;
11141           last_rex_prefix = i;
11142           break;
11143         case 0xf3:
11144           prefixes |= PREFIX_REPZ;
11145           last_repz_prefix = i;
11146           break;
11147         case 0xf2:
11148           prefixes |= PREFIX_REPNZ;
11149           last_repnz_prefix = i;
11150           break;
11151         case 0xf0:
11152           prefixes |= PREFIX_LOCK;
11153           last_lock_prefix = i;
11154           break;
11155         case 0x2e:
11156           prefixes |= PREFIX_CS;
11157           last_seg_prefix = i;
11158           active_seg_prefix = PREFIX_CS;
11159           break;
11160         case 0x36:
11161           prefixes |= PREFIX_SS;
11162           last_seg_prefix = i;
11163           active_seg_prefix = PREFIX_SS;
11164           break;
11165         case 0x3e:
11166           prefixes |= PREFIX_DS;
11167           last_seg_prefix = i;
11168           active_seg_prefix = PREFIX_DS;
11169           break;
11170         case 0x26:
11171           prefixes |= PREFIX_ES;
11172           last_seg_prefix = i;
11173           active_seg_prefix = PREFIX_ES;
11174           break;
11175         case 0x64:
11176           prefixes |= PREFIX_FS;
11177           last_seg_prefix = i;
11178           active_seg_prefix = PREFIX_FS;
11179           break;
11180         case 0x65:
11181           prefixes |= PREFIX_GS;
11182           last_seg_prefix = i;
11183           active_seg_prefix = PREFIX_GS;
11184           break;
11185         case 0x66:
11186           prefixes |= PREFIX_DATA;
11187           last_data_prefix = i;
11188           break;
11189         case 0x67:
11190           prefixes |= PREFIX_ADDR;
11191           last_addr_prefix = i;
11192           break;
11193         case FWAIT_OPCODE:
11194           /* fwait is really an instruction.  If there are prefixes
11195              before the fwait, they belong to the fwait, *not* to the
11196              following instruction.  */
11197           fwait_prefix = i;
11198           if (prefixes || rex)
11199             {
11200               prefixes |= PREFIX_FWAIT;
11201               codep++;
11202               /* This ensures that the previous REX prefixes are noticed
11203                  as unused prefixes, as in the return case below.  */
11204               rex_used = rex;
11205               return 1;
11206             }
11207           prefixes = PREFIX_FWAIT;
11208           break;
11209         default:
11210           return 1;
11211         }
11212       /* Rex is ignored when followed by another prefix.  */
11213       if (rex)
11214         {
11215           rex_used = rex;
11216           return 1;
11217         }
11218       if (*codep != FWAIT_OPCODE)
11219         all_prefixes[i++] = *codep;
11220       rex = newrex;
11221       codep++;
11222       length++;
11223     }
11224   return 0;
11225 }
11226
11227 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11228    prefix byte.  */
11229
11230 static const char *
11231 prefix_name (int pref, int sizeflag)
11232 {
11233   static const char *rexes [16] =
11234     {
11235       "rex",            /* 0x40 */
11236       "rex.B",          /* 0x41 */
11237       "rex.X",          /* 0x42 */
11238       "rex.XB",         /* 0x43 */
11239       "rex.R",          /* 0x44 */
11240       "rex.RB",         /* 0x45 */
11241       "rex.RX",         /* 0x46 */
11242       "rex.RXB",        /* 0x47 */
11243       "rex.W",          /* 0x48 */
11244       "rex.WB",         /* 0x49 */
11245       "rex.WX",         /* 0x4a */
11246       "rex.WXB",        /* 0x4b */
11247       "rex.WR",         /* 0x4c */
11248       "rex.WRB",        /* 0x4d */
11249       "rex.WRX",        /* 0x4e */
11250       "rex.WRXB",       /* 0x4f */
11251     };
11252
11253   switch (pref)
11254     {
11255     /* REX prefixes family.  */
11256     case 0x40:
11257     case 0x41:
11258     case 0x42:
11259     case 0x43:
11260     case 0x44:
11261     case 0x45:
11262     case 0x46:
11263     case 0x47:
11264     case 0x48:
11265     case 0x49:
11266     case 0x4a:
11267     case 0x4b:
11268     case 0x4c:
11269     case 0x4d:
11270     case 0x4e:
11271     case 0x4f:
11272       return rexes [pref - 0x40];
11273     case 0xf3:
11274       return "repz";
11275     case 0xf2:
11276       return "repnz";
11277     case 0xf0:
11278       return "lock";
11279     case 0x2e:
11280       return "cs";
11281     case 0x36:
11282       return "ss";
11283     case 0x3e:
11284       return "ds";
11285     case 0x26:
11286       return "es";
11287     case 0x64:
11288       return "fs";
11289     case 0x65:
11290       return "gs";
11291     case 0x66:
11292       return (sizeflag & DFLAG) ? "data16" : "data32";
11293     case 0x67:
11294       if (address_mode == mode_64bit)
11295         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11296       else
11297         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11298     case FWAIT_OPCODE:
11299       return "fwait";
11300     case REP_PREFIX:
11301       return "rep";
11302     case XACQUIRE_PREFIX:
11303       return "xacquire";
11304     case XRELEASE_PREFIX:
11305       return "xrelease";
11306     case BND_PREFIX:
11307       return "bnd";
11308     case NOTRACK_PREFIX:
11309       return "notrack";
11310     default:
11311       return NULL;
11312     }
11313 }
11314
11315 static char op_out[MAX_OPERANDS][100];
11316 static int op_ad, op_index[MAX_OPERANDS];
11317 static int two_source_ops;
11318 static bfd_vma op_address[MAX_OPERANDS];
11319 static bfd_vma op_riprel[MAX_OPERANDS];
11320 static bfd_vma start_pc;
11321
11322 /*
11323  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11324  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11325  *   section of the "Virtual 8086 Mode" chapter.)
11326  * 'pc' should be the address of this instruction, it will
11327  *   be used to print the target address if this is a relative jump or call
11328  * The function returns the length of this instruction in bytes.
11329  */
11330
11331 static char intel_syntax;
11332 static char intel_mnemonic = !SYSV386_COMPAT;
11333 static char open_char;
11334 static char close_char;
11335 static char separator_char;
11336 static char scale_char;
11337
11338 enum x86_64_isa
11339 {
11340   amd64 = 1,
11341   intel64
11342 };
11343
11344 static enum x86_64_isa isa64;
11345
11346 /* Here for backwards compatibility.  When gdb stops using
11347    print_insn_i386_att and print_insn_i386_intel these functions can
11348    disappear, and print_insn_i386 be merged into print_insn.  */
11349 int
11350 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11351 {
11352   intel_syntax = 0;
11353
11354   return print_insn (pc, info);
11355 }
11356
11357 int
11358 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11359 {
11360   intel_syntax = 1;
11361
11362   return print_insn (pc, info);
11363 }
11364
11365 int
11366 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11367 {
11368   intel_syntax = -1;
11369
11370   return print_insn (pc, info);
11371 }
11372
11373 void
11374 print_i386_disassembler_options (FILE *stream)
11375 {
11376   fprintf (stream, _("\n\
11377 The following i386/x86-64 specific disassembler options are supported for use\n\
11378 with the -M switch (multiple options should be separated by commas):\n"));
11379
11380   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11381   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11382   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11383   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11384   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11385   fprintf (stream, _("  att-mnemonic\n"
11386                      "              Display instruction in AT&T mnemonic\n"));
11387   fprintf (stream, _("  intel-mnemonic\n"
11388                      "              Display instruction in Intel mnemonic\n"));
11389   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11390   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11391   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11392   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11393   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11394   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11395   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11396   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11397 }
11398
11399 /* Bad opcode.  */
11400 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11401
11402 /* Get a pointer to struct dis386 with a valid name.  */
11403
11404 static const struct dis386 *
11405 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11406 {
11407   int vindex, vex_table_index;
11408
11409   if (dp->name != NULL)
11410     return dp;
11411
11412   switch (dp->op[0].bytemode)
11413     {
11414     case USE_REG_TABLE:
11415       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11416       break;
11417
11418     case USE_MOD_TABLE:
11419       vindex = modrm.mod == 0x3 ? 1 : 0;
11420       dp = &mod_table[dp->op[1].bytemode][vindex];
11421       break;
11422
11423     case USE_RM_TABLE:
11424       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11425       break;
11426
11427     case USE_PREFIX_TABLE:
11428       if (need_vex)
11429         {
11430           /* The prefix in VEX is implicit.  */
11431           switch (vex.prefix)
11432             {
11433             case 0:
11434               vindex = 0;
11435               break;
11436             case REPE_PREFIX_OPCODE:
11437               vindex = 1;
11438               break;
11439             case DATA_PREFIX_OPCODE:
11440               vindex = 2;
11441               break;
11442             case REPNE_PREFIX_OPCODE:
11443               vindex = 3;
11444               break;
11445             default:
11446               abort ();
11447               break;
11448             }
11449         }
11450       else
11451         {
11452           int last_prefix = -1;
11453           int prefix = 0;
11454           vindex = 0;
11455           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11456              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11457              last one wins.  */
11458           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11459             {
11460               if (last_repz_prefix > last_repnz_prefix)
11461                 {
11462                   vindex = 1;
11463                   prefix = PREFIX_REPZ;
11464                   last_prefix = last_repz_prefix;
11465                 }
11466               else
11467                 {
11468                   vindex = 3;
11469                   prefix = PREFIX_REPNZ;
11470                   last_prefix = last_repnz_prefix;
11471                 }
11472
11473               /* Check if prefix should be ignored.  */
11474               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11475                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11476                    & prefix) != 0)
11477                 vindex = 0;
11478             }
11479
11480           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11481             {
11482               vindex = 2;
11483               prefix = PREFIX_DATA;
11484               last_prefix = last_data_prefix;
11485             }
11486
11487           if (vindex != 0)
11488             {
11489               used_prefixes |= prefix;
11490               all_prefixes[last_prefix] = 0;
11491             }
11492         }
11493       dp = &prefix_table[dp->op[1].bytemode][vindex];
11494       break;
11495
11496     case USE_X86_64_TABLE:
11497       vindex = address_mode == mode_64bit ? 1 : 0;
11498       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11499       break;
11500
11501     case USE_3BYTE_TABLE:
11502       FETCH_DATA (info, codep + 2);
11503       vindex = *codep++;
11504       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11505       end_codep = codep;
11506       modrm.mod = (*codep >> 6) & 3;
11507       modrm.reg = (*codep >> 3) & 7;
11508       modrm.rm = *codep & 7;
11509       break;
11510
11511     case USE_VEX_LEN_TABLE:
11512       if (!need_vex)
11513         abort ();
11514
11515       switch (vex.length)
11516         {
11517         case 128:
11518           vindex = 0;
11519           break;
11520         case 256:
11521           vindex = 1;
11522           break;
11523         default:
11524           abort ();
11525           break;
11526         }
11527
11528       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11529       break;
11530
11531     case USE_EVEX_LEN_TABLE:
11532       if (!vex.evex)
11533         abort ();
11534
11535       switch (vex.length)
11536         {
11537         case 128:
11538           vindex = 0;
11539           break;
11540         case 256:
11541           vindex = 1;
11542           break;
11543         case 512:
11544           vindex = 2;
11545           break;
11546         default:
11547           abort ();
11548           break;
11549         }
11550
11551       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11552       break;
11553
11554     case USE_XOP_8F_TABLE:
11555       FETCH_DATA (info, codep + 3);
11556       /* All bits in the REX prefix are ignored.  */
11557       rex_ignored = rex;
11558       rex = ~(*codep >> 5) & 0x7;
11559
11560       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11561       switch ((*codep & 0x1f))
11562         {
11563         default:
11564           dp = &bad_opcode;
11565           return dp;
11566         case 0x8:
11567           vex_table_index = XOP_08;
11568           break;
11569         case 0x9:
11570           vex_table_index = XOP_09;
11571           break;
11572         case 0xa:
11573           vex_table_index = XOP_0A;
11574           break;
11575         }
11576       codep++;
11577       vex.w = *codep & 0x80;
11578       if (vex.w && address_mode == mode_64bit)
11579         rex |= REX_W;
11580
11581       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11582       if (address_mode != mode_64bit)
11583         {
11584           /* In 16/32-bit mode REX_B is silently ignored.  */
11585           rex &= ~REX_B;
11586         }
11587
11588       vex.length = (*codep & 0x4) ? 256 : 128;
11589       switch ((*codep & 0x3))
11590         {
11591         case 0:
11592           break;
11593         case 1:
11594           vex.prefix = DATA_PREFIX_OPCODE;
11595           break;
11596         case 2:
11597           vex.prefix = REPE_PREFIX_OPCODE;
11598           break;
11599         case 3:
11600           vex.prefix = REPNE_PREFIX_OPCODE;
11601           break;
11602         }
11603       need_vex = 1;
11604       need_vex_reg = 1;
11605       codep++;
11606       vindex = *codep++;
11607       dp = &xop_table[vex_table_index][vindex];
11608
11609       end_codep = codep;
11610       FETCH_DATA (info, codep + 1);
11611       modrm.mod = (*codep >> 6) & 3;
11612       modrm.reg = (*codep >> 3) & 7;
11613       modrm.rm = *codep & 7;
11614       break;
11615
11616     case USE_VEX_C4_TABLE:
11617       /* VEX prefix.  */
11618       FETCH_DATA (info, codep + 3);
11619       /* All bits in the REX prefix are ignored.  */
11620       rex_ignored = rex;
11621       rex = ~(*codep >> 5) & 0x7;
11622       switch ((*codep & 0x1f))
11623         {
11624         default:
11625           dp = &bad_opcode;
11626           return dp;
11627         case 0x1:
11628           vex_table_index = VEX_0F;
11629           break;
11630         case 0x2:
11631           vex_table_index = VEX_0F38;
11632           break;
11633         case 0x3:
11634           vex_table_index = VEX_0F3A;
11635           break;
11636         }
11637       codep++;
11638       vex.w = *codep & 0x80;
11639       if (address_mode == mode_64bit)
11640         {
11641           if (vex.w)
11642             rex |= REX_W;
11643         }
11644       else
11645         {
11646           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11647              is ignored, other REX bits are 0 and the highest bit in
11648              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11649           rex = 0;
11650         }
11651       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11652       vex.length = (*codep & 0x4) ? 256 : 128;
11653       switch ((*codep & 0x3))
11654         {
11655         case 0:
11656           break;
11657         case 1:
11658           vex.prefix = DATA_PREFIX_OPCODE;
11659           break;
11660         case 2:
11661           vex.prefix = REPE_PREFIX_OPCODE;
11662           break;
11663         case 3:
11664           vex.prefix = REPNE_PREFIX_OPCODE;
11665           break;
11666         }
11667       need_vex = 1;
11668       need_vex_reg = 1;
11669       codep++;
11670       vindex = *codep++;
11671       dp = &vex_table[vex_table_index][vindex];
11672       end_codep = codep;
11673       /* There is no MODRM byte for VEX0F 77.  */
11674       if (vex_table_index != VEX_0F || vindex != 0x77)
11675         {
11676           FETCH_DATA (info, codep + 1);
11677           modrm.mod = (*codep >> 6) & 3;
11678           modrm.reg = (*codep >> 3) & 7;
11679           modrm.rm = *codep & 7;
11680         }
11681       break;
11682
11683     case USE_VEX_C5_TABLE:
11684       /* VEX prefix.  */
11685       FETCH_DATA (info, codep + 2);
11686       /* All bits in the REX prefix are ignored.  */
11687       rex_ignored = rex;
11688       rex = (*codep & 0x80) ? 0 : REX_R;
11689
11690       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11691          VEX.vvvv is 1.  */
11692       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11693       vex.length = (*codep & 0x4) ? 256 : 128;
11694       switch ((*codep & 0x3))
11695         {
11696         case 0:
11697           break;
11698         case 1:
11699           vex.prefix = DATA_PREFIX_OPCODE;
11700           break;
11701         case 2:
11702           vex.prefix = REPE_PREFIX_OPCODE;
11703           break;
11704         case 3:
11705           vex.prefix = REPNE_PREFIX_OPCODE;
11706           break;
11707         }
11708       need_vex = 1;
11709       need_vex_reg = 1;
11710       codep++;
11711       vindex = *codep++;
11712       dp = &vex_table[dp->op[1].bytemode][vindex];
11713       end_codep = codep;
11714       /* There is no MODRM byte for VEX 77.  */
11715       if (vindex != 0x77)
11716         {
11717           FETCH_DATA (info, codep + 1);
11718           modrm.mod = (*codep >> 6) & 3;
11719           modrm.reg = (*codep >> 3) & 7;
11720           modrm.rm = *codep & 7;
11721         }
11722       break;
11723
11724     case USE_VEX_W_TABLE:
11725       if (!need_vex)
11726         abort ();
11727
11728       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11729       break;
11730
11731     case USE_EVEX_TABLE:
11732       two_source_ops = 0;
11733       /* EVEX prefix.  */
11734       vex.evex = 1;
11735       FETCH_DATA (info, codep + 4);
11736       /* All bits in the REX prefix are ignored.  */
11737       rex_ignored = rex;
11738       /* The first byte after 0x62.  */
11739       rex = ~(*codep >> 5) & 0x7;
11740       vex.r = *codep & 0x10;
11741       switch ((*codep & 0xf))
11742         {
11743         default:
11744           return &bad_opcode;
11745         case 0x1:
11746           vex_table_index = EVEX_0F;
11747           break;
11748         case 0x2:
11749           vex_table_index = EVEX_0F38;
11750           break;
11751         case 0x3:
11752           vex_table_index = EVEX_0F3A;
11753           break;
11754         }
11755
11756       /* The second byte after 0x62.  */
11757       codep++;
11758       vex.w = *codep & 0x80;
11759       if (vex.w && address_mode == mode_64bit)
11760         rex |= REX_W;
11761
11762       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11763
11764       /* The U bit.  */
11765       if (!(*codep & 0x4))
11766         return &bad_opcode;
11767
11768       switch ((*codep & 0x3))
11769         {
11770         case 0:
11771           break;
11772         case 1:
11773           vex.prefix = DATA_PREFIX_OPCODE;
11774           break;
11775         case 2:
11776           vex.prefix = REPE_PREFIX_OPCODE;
11777           break;
11778         case 3:
11779           vex.prefix = REPNE_PREFIX_OPCODE;
11780           break;
11781         }
11782
11783       /* The third byte after 0x62.  */
11784       codep++;
11785
11786       /* Remember the static rounding bits.  */
11787       vex.ll = (*codep >> 5) & 3;
11788       vex.b = (*codep & 0x10) != 0;
11789
11790       vex.v = *codep & 0x8;
11791       vex.mask_register_specifier = *codep & 0x7;
11792       vex.zeroing = *codep & 0x80;
11793
11794       if (address_mode != mode_64bit)
11795         {
11796           /* In 16/32-bit mode silently ignore following bits.  */
11797           rex &= ~REX_B;
11798           vex.r = 1;
11799           vex.v = 1;
11800         }
11801
11802       need_vex = 1;
11803       need_vex_reg = 1;
11804       codep++;
11805       vindex = *codep++;
11806       dp = &evex_table[vex_table_index][vindex];
11807       end_codep = codep;
11808       FETCH_DATA (info, codep + 1);
11809       modrm.mod = (*codep >> 6) & 3;
11810       modrm.reg = (*codep >> 3) & 7;
11811       modrm.rm = *codep & 7;
11812
11813       /* Set vector length.  */
11814       if (modrm.mod == 3 && vex.b)
11815         vex.length = 512;
11816       else
11817         {
11818           switch (vex.ll)
11819             {
11820             case 0x0:
11821               vex.length = 128;
11822               break;
11823             case 0x1:
11824               vex.length = 256;
11825               break;
11826             case 0x2:
11827               vex.length = 512;
11828               break;
11829             default:
11830               return &bad_opcode;
11831             }
11832         }
11833       break;
11834
11835     case 0:
11836       dp = &bad_opcode;
11837       break;
11838
11839     default:
11840       abort ();
11841     }
11842
11843   if (dp->name != NULL)
11844     return dp;
11845   else
11846     return get_valid_dis386 (dp, info);
11847 }
11848
11849 static void
11850 get_sib (disassemble_info *info, int sizeflag)
11851 {
11852   /* If modrm.mod == 3, operand must be register.  */
11853   if (need_modrm
11854       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11855       && modrm.mod != 3
11856       && modrm.rm == 4)
11857     {
11858       FETCH_DATA (info, codep + 2);
11859       sib.index = (codep [1] >> 3) & 7;
11860       sib.scale = (codep [1] >> 6) & 3;
11861       sib.base = codep [1] & 7;
11862     }
11863 }
11864
11865 static int
11866 print_insn (bfd_vma pc, disassemble_info *info)
11867 {
11868   const struct dis386 *dp;
11869   int i;
11870   char *op_txt[MAX_OPERANDS];
11871   int needcomma;
11872   int sizeflag, orig_sizeflag;
11873   const char *p;
11874   struct dis_private priv;
11875   int prefix_length;
11876
11877   priv.orig_sizeflag = AFLAG | DFLAG;
11878   if ((info->mach & bfd_mach_i386_i386) != 0)
11879     address_mode = mode_32bit;
11880   else if (info->mach == bfd_mach_i386_i8086)
11881     {
11882       address_mode = mode_16bit;
11883       priv.orig_sizeflag = 0;
11884     }
11885   else
11886     address_mode = mode_64bit;
11887
11888   if (intel_syntax == (char) -1)
11889     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11890
11891   for (p = info->disassembler_options; p != NULL; )
11892     {
11893       if (CONST_STRNEQ (p, "amd64"))
11894         isa64 = amd64;
11895       else if (CONST_STRNEQ (p, "intel64"))
11896         isa64 = intel64;
11897       else if (CONST_STRNEQ (p, "x86-64"))
11898         {
11899           address_mode = mode_64bit;
11900           priv.orig_sizeflag = AFLAG | DFLAG;
11901         }
11902       else if (CONST_STRNEQ (p, "i386"))
11903         {
11904           address_mode = mode_32bit;
11905           priv.orig_sizeflag = AFLAG | DFLAG;
11906         }
11907       else if (CONST_STRNEQ (p, "i8086"))
11908         {
11909           address_mode = mode_16bit;
11910           priv.orig_sizeflag = 0;
11911         }
11912       else if (CONST_STRNEQ (p, "intel"))
11913         {
11914           intel_syntax = 1;
11915           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11916             intel_mnemonic = 1;
11917         }
11918       else if (CONST_STRNEQ (p, "att"))
11919         {
11920           intel_syntax = 0;
11921           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11922             intel_mnemonic = 0;
11923         }
11924       else if (CONST_STRNEQ (p, "addr"))
11925         {
11926           if (address_mode == mode_64bit)
11927             {
11928               if (p[4] == '3' && p[5] == '2')
11929                 priv.orig_sizeflag &= ~AFLAG;
11930               else if (p[4] == '6' && p[5] == '4')
11931                 priv.orig_sizeflag |= AFLAG;
11932             }
11933           else
11934             {
11935               if (p[4] == '1' && p[5] == '6')
11936                 priv.orig_sizeflag &= ~AFLAG;
11937               else if (p[4] == '3' && p[5] == '2')
11938                 priv.orig_sizeflag |= AFLAG;
11939             }
11940         }
11941       else if (CONST_STRNEQ (p, "data"))
11942         {
11943           if (p[4] == '1' && p[5] == '6')
11944             priv.orig_sizeflag &= ~DFLAG;
11945           else if (p[4] == '3' && p[5] == '2')
11946             priv.orig_sizeflag |= DFLAG;
11947         }
11948       else if (CONST_STRNEQ (p, "suffix"))
11949         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11950
11951       p = strchr (p, ',');
11952       if (p != NULL)
11953         p++;
11954     }
11955
11956   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11957     {
11958       (*info->fprintf_func) (info->stream,
11959                              _("64-bit address is disabled"));
11960       return -1;
11961     }
11962
11963   if (intel_syntax)
11964     {
11965       names64 = intel_names64;
11966       names32 = intel_names32;
11967       names16 = intel_names16;
11968       names8 = intel_names8;
11969       names8rex = intel_names8rex;
11970       names_seg = intel_names_seg;
11971       names_mm = intel_names_mm;
11972       names_bnd = intel_names_bnd;
11973       names_xmm = intel_names_xmm;
11974       names_ymm = intel_names_ymm;
11975       names_zmm = intel_names_zmm;
11976       index64 = intel_index64;
11977       index32 = intel_index32;
11978       names_mask = intel_names_mask;
11979       index16 = intel_index16;
11980       open_char = '[';
11981       close_char = ']';
11982       separator_char = '+';
11983       scale_char = '*';
11984     }
11985   else
11986     {
11987       names64 = att_names64;
11988       names32 = att_names32;
11989       names16 = att_names16;
11990       names8 = att_names8;
11991       names8rex = att_names8rex;
11992       names_seg = att_names_seg;
11993       names_mm = att_names_mm;
11994       names_bnd = att_names_bnd;
11995       names_xmm = att_names_xmm;
11996       names_ymm = att_names_ymm;
11997       names_zmm = att_names_zmm;
11998       index64 = att_index64;
11999       index32 = att_index32;
12000       names_mask = att_names_mask;
12001       index16 = att_index16;
12002       open_char = '(';
12003       close_char =  ')';
12004       separator_char = ',';
12005       scale_char = ',';
12006     }
12007
12008   /* The output looks better if we put 7 bytes on a line, since that
12009      puts most long word instructions on a single line.  Use 8 bytes
12010      for Intel L1OM.  */
12011   if ((info->mach & bfd_mach_l1om) != 0)
12012     info->bytes_per_line = 8;
12013   else
12014     info->bytes_per_line = 7;
12015
12016   info->private_data = &priv;
12017   priv.max_fetched = priv.the_buffer;
12018   priv.insn_start = pc;
12019
12020   obuf[0] = 0;
12021   for (i = 0; i < MAX_OPERANDS; ++i)
12022     {
12023       op_out[i][0] = 0;
12024       op_index[i] = -1;
12025     }
12026
12027   the_info = info;
12028   start_pc = pc;
12029   start_codep = priv.the_buffer;
12030   codep = priv.the_buffer;
12031
12032   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12033     {
12034       const char *name;
12035
12036       /* Getting here means we tried for data but didn't get it.  That
12037          means we have an incomplete instruction of some sort.  Just
12038          print the first byte as a prefix or a .byte pseudo-op.  */
12039       if (codep > priv.the_buffer)
12040         {
12041           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12042           if (name != NULL)
12043             (*info->fprintf_func) (info->stream, "%s", name);
12044           else
12045             {
12046               /* Just print the first byte as a .byte instruction.  */
12047               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12048                                      (unsigned int) priv.the_buffer[0]);
12049             }
12050
12051           return 1;
12052         }
12053
12054       return -1;
12055     }
12056
12057   obufp = obuf;
12058   sizeflag = priv.orig_sizeflag;
12059
12060   if (!ckprefix () || rex_used)
12061     {
12062       /* Too many prefixes or unused REX prefixes.  */
12063       for (i = 0;
12064            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12065            i++)
12066         (*info->fprintf_func) (info->stream, "%s%s",
12067                                i == 0 ? "" : " ",
12068                                prefix_name (all_prefixes[i], sizeflag));
12069       return i;
12070     }
12071
12072   insn_codep = codep;
12073
12074   FETCH_DATA (info, codep + 1);
12075   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12076
12077   if (((prefixes & PREFIX_FWAIT)
12078        && ((*codep < 0xd8) || (*codep > 0xdf))))
12079     {
12080       /* Handle prefixes before fwait.  */
12081       for (i = 0; i < fwait_prefix && all_prefixes[i];
12082            i++)
12083         (*info->fprintf_func) (info->stream, "%s ",
12084                                prefix_name (all_prefixes[i], sizeflag));
12085       (*info->fprintf_func) (info->stream, "fwait");
12086       return i + 1;
12087     }
12088
12089   if (*codep == 0x0f)
12090     {
12091       unsigned char threebyte;
12092
12093       codep++;
12094       FETCH_DATA (info, codep + 1);
12095       threebyte = *codep;
12096       dp = &dis386_twobyte[threebyte];
12097       need_modrm = twobyte_has_modrm[*codep];
12098       codep++;
12099     }
12100   else
12101     {
12102       dp = &dis386[*codep];
12103       need_modrm = onebyte_has_modrm[*codep];
12104       codep++;
12105     }
12106
12107   /* Save sizeflag for printing the extra prefixes later before updating
12108      it for mnemonic and operand processing.  The prefix names depend
12109      only on the address mode.  */
12110   orig_sizeflag = sizeflag;
12111   if (prefixes & PREFIX_ADDR)
12112     sizeflag ^= AFLAG;
12113   if ((prefixes & PREFIX_DATA))
12114     sizeflag ^= DFLAG;
12115
12116   end_codep = codep;
12117   if (need_modrm)
12118     {
12119       FETCH_DATA (info, codep + 1);
12120       modrm.mod = (*codep >> 6) & 3;
12121       modrm.reg = (*codep >> 3) & 7;
12122       modrm.rm = *codep & 7;
12123     }
12124
12125   need_vex = 0;
12126   need_vex_reg = 0;
12127   vex_w_done = 0;
12128   memset (&vex, 0, sizeof (vex));
12129
12130   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12131     {
12132       get_sib (info, sizeflag);
12133       dofloat (sizeflag);
12134     }
12135   else
12136     {
12137       dp = get_valid_dis386 (dp, info);
12138       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12139         {
12140           get_sib (info, sizeflag);
12141           for (i = 0; i < MAX_OPERANDS; ++i)
12142             {
12143               obufp = op_out[i];
12144               op_ad = MAX_OPERANDS - 1 - i;
12145               if (dp->op[i].rtn)
12146                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12147               /* For EVEX instruction after the last operand masking
12148                  should be printed.  */
12149               if (i == 0 && vex.evex)
12150                 {
12151                   /* Don't print {%k0}.  */
12152                   if (vex.mask_register_specifier)
12153                     {
12154                       oappend ("{");
12155                       oappend (names_mask[vex.mask_register_specifier]);
12156                       oappend ("}");
12157                     }
12158                   if (vex.zeroing)
12159                     oappend ("{z}");
12160                 }
12161             }
12162         }
12163     }
12164
12165   /* Clear instruction information.  */
12166   if (the_info)
12167     {
12168       the_info->insn_info_valid = 0;
12169       the_info->branch_delay_insns = 0;
12170       the_info->data_size = 0;
12171       the_info->insn_type = dis_noninsn;
12172       the_info->target = 0;
12173       the_info->target2 = 0;
12174     }
12175
12176   /* Reset jump operation indicator.  */
12177   op_is_jump = FALSE;
12178
12179   {
12180     int jump_detection = 0;
12181
12182     /* Extract flags.  */
12183     for (i = 0; i < MAX_OPERANDS; ++i)
12184       {
12185         if ((dp->op[i].rtn == OP_J)
12186             || (dp->op[i].rtn == OP_indirE))
12187           jump_detection |= 1;
12188         else if ((dp->op[i].rtn == BND_Fixup)
12189                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12190           jump_detection |= 2;
12191         else if ((dp->op[i].bytemode == cond_jump_mode)
12192                  || (dp->op[i].bytemode == loop_jcxz_mode))
12193           jump_detection |= 4;
12194       }
12195
12196     /* Determine if this is a jump or branch.  */
12197     if ((jump_detection & 0x3) == 0x3)
12198       {
12199         op_is_jump = TRUE;
12200         if (jump_detection & 0x4)
12201           the_info->insn_type = dis_condbranch;
12202         else
12203           the_info->insn_type =
12204             (dp->name && !strncmp(dp->name, "call", 4))
12205             ? dis_jsr : dis_branch;
12206       }
12207   }
12208
12209   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12210      are all 0s in inverted form.  */
12211   if (need_vex && vex.register_specifier != 0)
12212     {
12213       (*info->fprintf_func) (info->stream, "(bad)");
12214       return end_codep - priv.the_buffer;
12215     }
12216
12217   /* Check if the REX prefix is used.  */
12218   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12219     all_prefixes[last_rex_prefix] = 0;
12220
12221   /* Check if the SEG prefix is used.  */
12222   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12223                    | PREFIX_FS | PREFIX_GS)) != 0
12224       && (used_prefixes & active_seg_prefix) != 0)
12225     all_prefixes[last_seg_prefix] = 0;
12226
12227   /* Check if the ADDR prefix is used.  */
12228   if ((prefixes & PREFIX_ADDR) != 0
12229       && (used_prefixes & PREFIX_ADDR) != 0)
12230     all_prefixes[last_addr_prefix] = 0;
12231
12232   /* Check if the DATA prefix is used.  */
12233   if ((prefixes & PREFIX_DATA) != 0
12234       && (used_prefixes & PREFIX_DATA) != 0)
12235     all_prefixes[last_data_prefix] = 0;
12236
12237   /* Print the extra prefixes.  */
12238   prefix_length = 0;
12239   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12240     if (all_prefixes[i])
12241       {
12242         const char *name;
12243         name = prefix_name (all_prefixes[i], orig_sizeflag);
12244         if (name == NULL)
12245           abort ();
12246         prefix_length += strlen (name) + 1;
12247         (*info->fprintf_func) (info->stream, "%s ", name);
12248       }
12249
12250   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12251      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12252      used by putop and MMX/SSE operand and may be overriden by the
12253      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12254      separately.  */
12255   if (dp->prefix_requirement == PREFIX_OPCODE
12256       && dp != &bad_opcode
12257       && (((prefixes
12258             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12259            && (used_prefixes
12260                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12261           || ((((prefixes
12262                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12263                 == PREFIX_DATA)
12264                && (used_prefixes & PREFIX_DATA) == 0))))
12265     {
12266       (*info->fprintf_func) (info->stream, "(bad)");
12267       return end_codep - priv.the_buffer;
12268     }
12269
12270   /* Check maximum code length.  */
12271   if ((codep - start_codep) > MAX_CODE_LENGTH)
12272     {
12273       (*info->fprintf_func) (info->stream, "(bad)");
12274       return MAX_CODE_LENGTH;
12275     }
12276
12277   obufp = mnemonicendp;
12278   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12279     oappend (" ");
12280   oappend (" ");
12281   (*info->fprintf_func) (info->stream, "%s", obuf);
12282
12283   /* The enter and bound instructions are printed with operands in the same
12284      order as the intel book; everything else is printed in reverse order.  */
12285   if (intel_syntax || two_source_ops)
12286     {
12287       bfd_vma riprel;
12288
12289       for (i = 0; i < MAX_OPERANDS; ++i)
12290         op_txt[i] = op_out[i];
12291
12292       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12293           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12294         {
12295           op_txt[2] = op_out[3];
12296           op_txt[3] = op_out[2];
12297         }
12298
12299       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12300         {
12301           op_ad = op_index[i];
12302           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12303           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12304           riprel = op_riprel[i];
12305           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12306           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12307         }
12308     }
12309   else
12310     {
12311       for (i = 0; i < MAX_OPERANDS; ++i)
12312         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12313     }
12314
12315   needcomma = 0;
12316   for (i = 0; i < MAX_OPERANDS; ++i)
12317     if (*op_txt[i])
12318       {
12319         if (needcomma)
12320           (*info->fprintf_func) (info->stream, ",");
12321         if (op_index[i] != -1 && !op_riprel[i])
12322           {
12323             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12324
12325             if (the_info && op_is_jump)
12326               {
12327                 the_info->insn_info_valid = 1;
12328                 the_info->branch_delay_insns = 0;
12329                 the_info->data_size = 0;
12330                 the_info->target = target;
12331                 the_info->target2 = 0;
12332               }
12333             (*info->print_address_func) (target, info);
12334           }
12335         else
12336           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12337         needcomma = 1;
12338       }
12339
12340   for (i = 0; i < MAX_OPERANDS; i++)
12341     if (op_index[i] != -1 && op_riprel[i])
12342       {
12343         (*info->fprintf_func) (info->stream, "        # ");
12344         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12345                                                 + op_address[op_index[i]]), info);
12346         break;
12347       }
12348   return codep - priv.the_buffer;
12349 }
12350
12351 static const char *float_mem[] = {
12352   /* d8 */
12353   "fadd{s|}",
12354   "fmul{s|}",
12355   "fcom{s|}",
12356   "fcomp{s|}",
12357   "fsub{s|}",
12358   "fsubr{s|}",
12359   "fdiv{s|}",
12360   "fdivr{s|}",
12361   /* d9 */
12362   "fld{s|}",
12363   "(bad)",
12364   "fst{s|}",
12365   "fstp{s|}",
12366   "fldenvIC",
12367   "fldcw",
12368   "fNstenvIC",
12369   "fNstcw",
12370   /* da */
12371   "fiadd{l|}",
12372   "fimul{l|}",
12373   "ficom{l|}",
12374   "ficomp{l|}",
12375   "fisub{l|}",
12376   "fisubr{l|}",
12377   "fidiv{l|}",
12378   "fidivr{l|}",
12379   /* db */
12380   "fild{l|}",
12381   "fisttp{l|}",
12382   "fist{l|}",
12383   "fistp{l|}",
12384   "(bad)",
12385   "fld{t||t|}",
12386   "(bad)",
12387   "fstp{t||t|}",
12388   /* dc */
12389   "fadd{l|}",
12390   "fmul{l|}",
12391   "fcom{l|}",
12392   "fcomp{l|}",
12393   "fsub{l|}",
12394   "fsubr{l|}",
12395   "fdiv{l|}",
12396   "fdivr{l|}",
12397   /* dd */
12398   "fld{l|}",
12399   "fisttp{ll|}",
12400   "fst{l||}",
12401   "fstp{l|}",
12402   "frstorIC",
12403   "(bad)",
12404   "fNsaveIC",
12405   "fNstsw",
12406   /* de */
12407   "fiadd{s|}",
12408   "fimul{s|}",
12409   "ficom{s|}",
12410   "ficomp{s|}",
12411   "fisub{s|}",
12412   "fisubr{s|}",
12413   "fidiv{s|}",
12414   "fidivr{s|}",
12415   /* df */
12416   "fild{s|}",
12417   "fisttp{s|}",
12418   "fist{s|}",
12419   "fistp{s|}",
12420   "fbld",
12421   "fild{ll|}",
12422   "fbstp",
12423   "fistp{ll|}",
12424 };
12425
12426 static const unsigned char float_mem_mode[] = {
12427   /* d8 */
12428   d_mode,
12429   d_mode,
12430   d_mode,
12431   d_mode,
12432   d_mode,
12433   d_mode,
12434   d_mode,
12435   d_mode,
12436   /* d9 */
12437   d_mode,
12438   0,
12439   d_mode,
12440   d_mode,
12441   0,
12442   w_mode,
12443   0,
12444   w_mode,
12445   /* da */
12446   d_mode,
12447   d_mode,
12448   d_mode,
12449   d_mode,
12450   d_mode,
12451   d_mode,
12452   d_mode,
12453   d_mode,
12454   /* db */
12455   d_mode,
12456   d_mode,
12457   d_mode,
12458   d_mode,
12459   0,
12460   t_mode,
12461   0,
12462   t_mode,
12463   /* dc */
12464   q_mode,
12465   q_mode,
12466   q_mode,
12467   q_mode,
12468   q_mode,
12469   q_mode,
12470   q_mode,
12471   q_mode,
12472   /* dd */
12473   q_mode,
12474   q_mode,
12475   q_mode,
12476   q_mode,
12477   0,
12478   0,
12479   0,
12480   w_mode,
12481   /* de */
12482   w_mode,
12483   w_mode,
12484   w_mode,
12485   w_mode,
12486   w_mode,
12487   w_mode,
12488   w_mode,
12489   w_mode,
12490   /* df */
12491   w_mode,
12492   w_mode,
12493   w_mode,
12494   w_mode,
12495   t_mode,
12496   q_mode,
12497   t_mode,
12498   q_mode
12499 };
12500
12501 #define ST { OP_ST, 0 }
12502 #define STi { OP_STi, 0 }
12503
12504 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12505 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12506 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12507 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12508 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12509 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12510 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12511 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12512 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12513
12514 static const struct dis386 float_reg[][8] = {
12515   /* d8 */
12516   {
12517     { "fadd",   { ST, STi }, 0 },
12518     { "fmul",   { ST, STi }, 0 },
12519     { "fcom",   { STi }, 0 },
12520     { "fcomp",  { STi }, 0 },
12521     { "fsub",   { ST, STi }, 0 },
12522     { "fsubr",  { ST, STi }, 0 },
12523     { "fdiv",   { ST, STi }, 0 },
12524     { "fdivr",  { ST, STi }, 0 },
12525   },
12526   /* d9 */
12527   {
12528     { "fld",    { STi }, 0 },
12529     { "fxch",   { STi }, 0 },
12530     { FGRPd9_2 },
12531     { Bad_Opcode },
12532     { FGRPd9_4 },
12533     { FGRPd9_5 },
12534     { FGRPd9_6 },
12535     { FGRPd9_7 },
12536   },
12537   /* da */
12538   {
12539     { "fcmovb", { ST, STi }, 0 },
12540     { "fcmove", { ST, STi }, 0 },
12541     { "fcmovbe",{ ST, STi }, 0 },
12542     { "fcmovu", { ST, STi }, 0 },
12543     { Bad_Opcode },
12544     { FGRPda_5 },
12545     { Bad_Opcode },
12546     { Bad_Opcode },
12547   },
12548   /* db */
12549   {
12550     { "fcmovnb",{ ST, STi }, 0 },
12551     { "fcmovne",{ ST, STi }, 0 },
12552     { "fcmovnbe",{ ST, STi }, 0 },
12553     { "fcmovnu",{ ST, STi }, 0 },
12554     { FGRPdb_4 },
12555     { "fucomi", { ST, STi }, 0 },
12556     { "fcomi",  { ST, STi }, 0 },
12557     { Bad_Opcode },
12558   },
12559   /* dc */
12560   {
12561     { "fadd",   { STi, ST }, 0 },
12562     { "fmul",   { STi, ST }, 0 },
12563     { Bad_Opcode },
12564     { Bad_Opcode },
12565     { "fsub{!M|r}",     { STi, ST }, 0 },
12566     { "fsub{M|}",       { STi, ST }, 0 },
12567     { "fdiv{!M|r}",     { STi, ST }, 0 },
12568     { "fdiv{M|}",       { STi, ST }, 0 },
12569   },
12570   /* dd */
12571   {
12572     { "ffree",  { STi }, 0 },
12573     { Bad_Opcode },
12574     { "fst",    { STi }, 0 },
12575     { "fstp",   { STi }, 0 },
12576     { "fucom",  { STi }, 0 },
12577     { "fucomp", { STi }, 0 },
12578     { Bad_Opcode },
12579     { Bad_Opcode },
12580   },
12581   /* de */
12582   {
12583     { "faddp",  { STi, ST }, 0 },
12584     { "fmulp",  { STi, ST }, 0 },
12585     { Bad_Opcode },
12586     { FGRPde_3 },
12587     { "fsub{!M|r}p",    { STi, ST }, 0 },
12588     { "fsub{M|}p",      { STi, ST }, 0 },
12589     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12590     { "fdiv{M|}p",      { STi, ST }, 0 },
12591   },
12592   /* df */
12593   {
12594     { "ffreep", { STi }, 0 },
12595     { Bad_Opcode },
12596     { Bad_Opcode },
12597     { Bad_Opcode },
12598     { FGRPdf_4 },
12599     { "fucomip", { ST, STi }, 0 },
12600     { "fcomip", { ST, STi }, 0 },
12601     { Bad_Opcode },
12602   },
12603 };
12604
12605 static char *fgrps[][8] = {
12606   /* Bad opcode 0 */
12607   {
12608     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12609   },
12610
12611   /* d9_2  1 */
12612   {
12613     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12614   },
12615
12616   /* d9_4  2 */
12617   {
12618     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12619   },
12620
12621   /* d9_5  3 */
12622   {
12623     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12624   },
12625
12626   /* d9_6  4 */
12627   {
12628     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12629   },
12630
12631   /* d9_7  5 */
12632   {
12633     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12634   },
12635
12636   /* da_5  6 */
12637   {
12638     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12639   },
12640
12641   /* db_4  7 */
12642   {
12643     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12644     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12645   },
12646
12647   /* de_3  8 */
12648   {
12649     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12650   },
12651
12652   /* df_4  9 */
12653   {
12654     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12655   },
12656 };
12657
12658 static void
12659 swap_operand (void)
12660 {
12661   mnemonicendp[0] = '.';
12662   mnemonicendp[1] = 's';
12663   mnemonicendp += 2;
12664 }
12665
12666 static void
12667 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12668                int sizeflag ATTRIBUTE_UNUSED)
12669 {
12670   /* Skip mod/rm byte.  */
12671   MODRM_CHECK;
12672   codep++;
12673 }
12674
12675 static void
12676 dofloat (int sizeflag)
12677 {
12678   const struct dis386 *dp;
12679   unsigned char floatop;
12680
12681   floatop = codep[-1];
12682
12683   if (modrm.mod != 3)
12684     {
12685       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12686
12687       putop (float_mem[fp_indx], sizeflag);
12688       obufp = op_out[0];
12689       op_ad = 2;
12690       OP_E (float_mem_mode[fp_indx], sizeflag);
12691       return;
12692     }
12693   /* Skip mod/rm byte.  */
12694   MODRM_CHECK;
12695   codep++;
12696
12697   dp = &float_reg[floatop - 0xd8][modrm.reg];
12698   if (dp->name == NULL)
12699     {
12700       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12701
12702       /* Instruction fnstsw is only one with strange arg.  */
12703       if (floatop == 0xdf && codep[-1] == 0xe0)
12704         strcpy (op_out[0], names16[0]);
12705     }
12706   else
12707     {
12708       putop (dp->name, sizeflag);
12709
12710       obufp = op_out[0];
12711       op_ad = 2;
12712       if (dp->op[0].rtn)
12713         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12714
12715       obufp = op_out[1];
12716       op_ad = 1;
12717       if (dp->op[1].rtn)
12718         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12719     }
12720 }
12721
12722 /* Like oappend (below), but S is a string starting with '%'.
12723    In Intel syntax, the '%' is elided.  */
12724 static void
12725 oappend_maybe_intel (const char *s)
12726 {
12727   oappend (s + intel_syntax);
12728 }
12729
12730 static void
12731 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12732 {
12733   oappend_maybe_intel ("%st");
12734 }
12735
12736 static void
12737 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12738 {
12739   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12740   oappend_maybe_intel (scratchbuf);
12741 }
12742
12743 /* Capital letters in template are macros.  */
12744 static int
12745 putop (const char *in_template, int sizeflag)
12746 {
12747   const char *p;
12748   int alt = 0;
12749   int cond = 1;
12750   unsigned int l = 0, len = 1;
12751   char last[4];
12752
12753 #define SAVE_LAST(c)                    \
12754   if (l < len && l < sizeof (last))     \
12755     last[l++] = c;                      \
12756   else                                  \
12757     abort ();
12758
12759   for (p = in_template; *p; p++)
12760     {
12761       switch (*p)
12762         {
12763         default:
12764           *obufp++ = *p;
12765           break;
12766         case '%':
12767           len++;
12768           break;
12769         case '!':
12770           cond = 0;
12771           break;
12772         case '{':
12773           if (intel_syntax)
12774             {
12775               while (*++p != '|')
12776                 if (*p == '}' || *p == '\0')
12777                   abort ();
12778             }
12779           /* Fall through.  */
12780         case 'I':
12781           alt = 1;
12782           continue;
12783         case '|':
12784           while (*++p != '}')
12785             {
12786               if (*p == '\0')
12787                 abort ();
12788             }
12789           break;
12790         case '}':
12791           break;
12792         case 'A':
12793           if (intel_syntax)
12794             break;
12795           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12796             *obufp++ = 'b';
12797           break;
12798         case 'B':
12799           if (l == 0 && len == 1)
12800             {
12801 case_B:
12802               if (intel_syntax)
12803                 break;
12804               if (sizeflag & SUFFIX_ALWAYS)
12805                 *obufp++ = 'b';
12806             }
12807           else
12808             {
12809               if (l != 1
12810                   || len != 2
12811                   || last[0] != 'L')
12812                 {
12813                   SAVE_LAST (*p);
12814                   break;
12815                 }
12816
12817               if (address_mode == mode_64bit
12818                   && !(prefixes & PREFIX_ADDR))
12819                 {
12820                   *obufp++ = 'a';
12821                   *obufp++ = 'b';
12822                   *obufp++ = 's';
12823                 }
12824
12825               goto case_B;
12826             }
12827           break;
12828         case 'C':
12829           if (intel_syntax && !alt)
12830             break;
12831           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12832             {
12833               if (sizeflag & DFLAG)
12834                 *obufp++ = intel_syntax ? 'd' : 'l';
12835               else
12836                 *obufp++ = intel_syntax ? 'w' : 's';
12837               used_prefixes |= (prefixes & PREFIX_DATA);
12838             }
12839           break;
12840         case 'D':
12841           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12842             break;
12843           USED_REX (REX_W);
12844           if (modrm.mod == 3)
12845             {
12846               if (rex & REX_W)
12847                 *obufp++ = 'q';
12848               else
12849                 {
12850                   if (sizeflag & DFLAG)
12851                     *obufp++ = intel_syntax ? 'd' : 'l';
12852                   else
12853                     *obufp++ = 'w';
12854                   used_prefixes |= (prefixes & PREFIX_DATA);
12855                 }
12856             }
12857           else
12858             *obufp++ = 'w';
12859           break;
12860         case 'E':               /* For jcxz/jecxz */
12861           if (address_mode == mode_64bit)
12862             {
12863               if (sizeflag & AFLAG)
12864                 *obufp++ = 'r';
12865               else
12866                 *obufp++ = 'e';
12867             }
12868           else
12869             if (sizeflag & AFLAG)
12870               *obufp++ = 'e';
12871           used_prefixes |= (prefixes & PREFIX_ADDR);
12872           break;
12873         case 'F':
12874           if (intel_syntax)
12875             break;
12876           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12877             {
12878               if (sizeflag & AFLAG)
12879                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12880               else
12881                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12882               used_prefixes |= (prefixes & PREFIX_ADDR);
12883             }
12884           break;
12885         case 'G':
12886           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12887             break;
12888           if ((rex & REX_W) || (sizeflag & DFLAG))
12889             *obufp++ = 'l';
12890           else
12891             *obufp++ = 'w';
12892           if (!(rex & REX_W))
12893             used_prefixes |= (prefixes & PREFIX_DATA);
12894           break;
12895         case 'H':
12896           if (intel_syntax)
12897             break;
12898           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12899               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12900             {
12901               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12902               *obufp++ = ',';
12903               *obufp++ = 'p';
12904               if (prefixes & PREFIX_DS)
12905                 *obufp++ = 't';
12906               else
12907                 *obufp++ = 'n';
12908             }
12909           break;
12910         case 'J':
12911           if (intel_syntax)
12912             break;
12913           *obufp++ = 'l';
12914           break;
12915         case 'K':
12916           USED_REX (REX_W);
12917           if (rex & REX_W)
12918             *obufp++ = 'q';
12919           else
12920             *obufp++ = 'd';
12921           break;
12922         case 'Z':
12923           if (l != 0 || len != 1)
12924             {
12925               if (l != 1 || len != 2 || last[0] != 'X')
12926                 {
12927                   SAVE_LAST (*p);
12928                   break;
12929                 }
12930               if (!need_vex || !vex.evex)
12931                 abort ();
12932               if (intel_syntax
12933                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12934                 break;
12935               switch (vex.length)
12936                 {
12937                 case 128:
12938                   *obufp++ = 'x';
12939                   break;
12940                 case 256:
12941                   *obufp++ = 'y';
12942                   break;
12943                 case 512:
12944                   *obufp++ = 'z';
12945                   break;
12946                 default:
12947                   abort ();
12948                 }
12949               break;
12950             }
12951           if (intel_syntax)
12952             break;
12953           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12954             {
12955               *obufp++ = 'q';
12956               break;
12957             }
12958           /* Fall through.  */
12959           goto case_L;
12960         case 'L':
12961           if (l != 0 || len != 1)
12962             {
12963               SAVE_LAST (*p);
12964               break;
12965             }
12966 case_L:
12967           if (intel_syntax)
12968             break;
12969           if (sizeflag & SUFFIX_ALWAYS)
12970             *obufp++ = 'l';
12971           break;
12972         case 'M':
12973           if (intel_mnemonic != cond)
12974             *obufp++ = 'r';
12975           break;
12976         case 'N':
12977           if ((prefixes & PREFIX_FWAIT) == 0)
12978             *obufp++ = 'n';
12979           else
12980             used_prefixes |= PREFIX_FWAIT;
12981           break;
12982         case 'O':
12983           USED_REX (REX_W);
12984           if (rex & REX_W)
12985             *obufp++ = 'o';
12986           else if (intel_syntax && (sizeflag & DFLAG))
12987             *obufp++ = 'q';
12988           else
12989             *obufp++ = 'd';
12990           if (!(rex & REX_W))
12991             used_prefixes |= (prefixes & PREFIX_DATA);
12992           break;
12993         case '&':
12994           if (!intel_syntax
12995               && address_mode == mode_64bit
12996               && isa64 == intel64)
12997             {
12998               *obufp++ = 'q';
12999               break;
13000             }
13001           /* Fall through.  */
13002         case 'T':
13003           if (!intel_syntax
13004               && address_mode == mode_64bit
13005               && ((sizeflag & DFLAG) || (rex & REX_W)))
13006             {
13007               *obufp++ = 'q';
13008               break;
13009             }
13010           /* Fall through.  */
13011           goto case_P;
13012         case 'P':
13013           if (l == 0 && len == 1)
13014             {
13015 case_P:
13016               if (intel_syntax)
13017                 {
13018                   if ((rex & REX_W) == 0
13019                       && (prefixes & PREFIX_DATA))
13020                     {
13021                       if ((sizeflag & DFLAG) == 0)
13022                         *obufp++ = 'w';
13023                       used_prefixes |= (prefixes & PREFIX_DATA);
13024                     }
13025                   break;
13026                 }
13027               if ((prefixes & PREFIX_DATA)
13028                   || (rex & REX_W)
13029                   || (sizeflag & SUFFIX_ALWAYS))
13030                 {
13031                   USED_REX (REX_W);
13032                   if (rex & REX_W)
13033                     *obufp++ = 'q';
13034                   else
13035                     {
13036                       if (sizeflag & DFLAG)
13037                         *obufp++ = 'l';
13038                       else
13039                         *obufp++ = 'w';
13040                       used_prefixes |= (prefixes & PREFIX_DATA);
13041                     }
13042                 }
13043             }
13044           else
13045             {
13046               if (l != 1 || len != 2 || last[0] != 'L')
13047                 {
13048                   SAVE_LAST (*p);
13049                   break;
13050                 }
13051
13052               if ((prefixes & PREFIX_DATA)
13053                   || (rex & REX_W)
13054                   || (sizeflag & SUFFIX_ALWAYS))
13055                 {
13056                   USED_REX (REX_W);
13057                   if (rex & REX_W)
13058                     *obufp++ = 'q';
13059                   else
13060                     {
13061                       if (sizeflag & DFLAG)
13062                         *obufp++ = intel_syntax ? 'd' : 'l';
13063                       else
13064                         *obufp++ = 'w';
13065                       used_prefixes |= (prefixes & PREFIX_DATA);
13066                     }
13067                 }
13068             }
13069           break;
13070         case 'U':
13071           if (intel_syntax)
13072             break;
13073           if (address_mode == mode_64bit
13074               && ((sizeflag & DFLAG) || (rex & REX_W)))
13075             {
13076               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13077                 *obufp++ = 'q';
13078               break;
13079             }
13080           /* Fall through.  */
13081           goto case_Q;
13082         case 'Q':
13083           if (l == 0 && len == 1)
13084             {
13085 case_Q:
13086               if (intel_syntax && !alt)
13087                 break;
13088               USED_REX (REX_W);
13089               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13090                 {
13091                   if (rex & REX_W)
13092                     *obufp++ = 'q';
13093                   else
13094                     {
13095                       if (sizeflag & DFLAG)
13096                         *obufp++ = intel_syntax ? 'd' : 'l';
13097                       else
13098                         *obufp++ = 'w';
13099                       used_prefixes |= (prefixes & PREFIX_DATA);
13100                     }
13101                 }
13102             }
13103           else
13104             {
13105               if (l != 1 || len != 2 || last[0] != 'L')
13106                 {
13107                   SAVE_LAST (*p);
13108                   break;
13109                 }
13110               if (intel_syntax
13111                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13112                 break;
13113               if ((rex & REX_W))
13114                 {
13115                   USED_REX (REX_W);
13116                   *obufp++ = 'q';
13117                 }
13118               else
13119                 *obufp++ = 'l';
13120             }
13121           break;
13122         case 'R':
13123           USED_REX (REX_W);
13124           if (rex & REX_W)
13125             *obufp++ = 'q';
13126           else if (sizeflag & DFLAG)
13127             {
13128               if (intel_syntax)
13129                   *obufp++ = 'd';
13130               else
13131                   *obufp++ = 'l';
13132             }
13133           else
13134             *obufp++ = 'w';
13135           if (intel_syntax && !p[1]
13136               && ((rex & REX_W) || (sizeflag & DFLAG)))
13137             *obufp++ = 'e';
13138           if (!(rex & REX_W))
13139             used_prefixes |= (prefixes & PREFIX_DATA);
13140           break;
13141         case 'V':
13142           if (l == 0 && len == 1)
13143             {
13144               if (intel_syntax)
13145                 break;
13146               if (address_mode == mode_64bit
13147                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13148                 {
13149                   if (sizeflag & SUFFIX_ALWAYS)
13150                     *obufp++ = 'q';
13151                   break;
13152                 }
13153             }
13154           else
13155             {
13156               if (l != 1
13157                   || len != 2
13158                   || last[0] != 'L')
13159                 {
13160                   SAVE_LAST (*p);
13161                   break;
13162                 }
13163
13164               if (rex & REX_W)
13165                 {
13166                   *obufp++ = 'a';
13167                   *obufp++ = 'b';
13168                   *obufp++ = 's';
13169                 }
13170             }
13171           /* Fall through.  */
13172           goto case_S;
13173         case 'S':
13174           if (l == 0 && len == 1)
13175             {
13176 case_S:
13177               if (intel_syntax)
13178                 break;
13179               if (sizeflag & SUFFIX_ALWAYS)
13180                 {
13181                   if (rex & REX_W)
13182                     *obufp++ = 'q';
13183                   else
13184                     {
13185                       if (sizeflag & DFLAG)
13186                         *obufp++ = 'l';
13187                       else
13188                         *obufp++ = 'w';
13189                       used_prefixes |= (prefixes & PREFIX_DATA);
13190                     }
13191                 }
13192             }
13193           else
13194             {
13195               if (l != 1
13196                   || len != 2
13197                   || last[0] != 'L')
13198                 {
13199                   SAVE_LAST (*p);
13200                   break;
13201                 }
13202
13203               if (address_mode == mode_64bit
13204                   && !(prefixes & PREFIX_ADDR))
13205                 {
13206                   *obufp++ = 'a';
13207                   *obufp++ = 'b';
13208                   *obufp++ = 's';
13209                 }
13210
13211               goto case_S;
13212             }
13213           break;
13214         case 'X':
13215           if (l != 0 || len != 1)
13216             {
13217               SAVE_LAST (*p);
13218               break;
13219             }
13220           if (need_vex && vex.prefix)
13221             {
13222               if (vex.prefix == DATA_PREFIX_OPCODE)
13223                 *obufp++ = 'd';
13224               else
13225                 *obufp++ = 's';
13226             }
13227           else
13228             {
13229               if (prefixes & PREFIX_DATA)
13230                 *obufp++ = 'd';
13231               else
13232                 *obufp++ = 's';
13233               used_prefixes |= (prefixes & PREFIX_DATA);
13234             }
13235           break;
13236         case 'Y':
13237           if (l == 0 && len == 1)
13238             abort ();
13239           else
13240             {
13241               if (l != 1 || len != 2 || last[0] != 'X')
13242                 {
13243                   SAVE_LAST (*p);
13244                   break;
13245                 }
13246               if (!need_vex)
13247                 abort ();
13248               if (intel_syntax
13249                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13250                 break;
13251               switch (vex.length)
13252                 {
13253                 case 128:
13254                   *obufp++ = 'x';
13255                   break;
13256                 case 256:
13257                   *obufp++ = 'y';
13258                   break;
13259                 case 512:
13260                   if (!vex.evex)
13261                 default:
13262                     abort ();
13263                 }
13264             }
13265           break;
13266         case 'W':
13267           if (l == 0 && len == 1)
13268             {
13269               /* operand size flag for cwtl, cbtw */
13270               USED_REX (REX_W);
13271               if (rex & REX_W)
13272                 {
13273                   if (intel_syntax)
13274                     *obufp++ = 'd';
13275                   else
13276                     *obufp++ = 'l';
13277                 }
13278               else if (sizeflag & DFLAG)
13279                 *obufp++ = 'w';
13280               else
13281                 *obufp++ = 'b';
13282               if (!(rex & REX_W))
13283                 used_prefixes |= (prefixes & PREFIX_DATA);
13284             }
13285           else
13286             {
13287               if (l != 1
13288                   || len != 2
13289                   || (last[0] != 'X'
13290                       && last[0] != 'L'))
13291                 {
13292                   SAVE_LAST (*p);
13293                   break;
13294                 }
13295               if (!need_vex)
13296                 abort ();
13297               if (last[0] == 'X')
13298                 *obufp++ = vex.w ? 'd': 's';
13299               else
13300                 *obufp++ = vex.w ? 'q': 'd';
13301             }
13302           break;
13303         case '^':
13304           if (intel_syntax)
13305             break;
13306           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13307             {
13308               if (sizeflag & DFLAG)
13309                 *obufp++ = 'l';
13310               else
13311                 *obufp++ = 'w';
13312               used_prefixes |= (prefixes & PREFIX_DATA);
13313             }
13314           break;
13315         case '@':
13316           if (intel_syntax)
13317             break;
13318           if (address_mode == mode_64bit
13319               && (isa64 == intel64
13320                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13321               *obufp++ = 'q';
13322           else if ((prefixes & PREFIX_DATA))
13323             {
13324               if (!(sizeflag & DFLAG))
13325                 *obufp++ = 'w';
13326               used_prefixes |= (prefixes & PREFIX_DATA);
13327             }
13328           break;
13329         }
13330       alt = 0;
13331     }
13332   *obufp = 0;
13333   mnemonicendp = obufp;
13334   return 0;
13335 }
13336
13337 static void
13338 oappend (const char *s)
13339 {
13340   obufp = stpcpy (obufp, s);
13341 }
13342
13343 static void
13344 append_seg (void)
13345 {
13346   /* Only print the active segment register.  */
13347   if (!active_seg_prefix)
13348     return;
13349
13350   used_prefixes |= active_seg_prefix;
13351   switch (active_seg_prefix)
13352     {
13353     case PREFIX_CS:
13354       oappend_maybe_intel ("%cs:");
13355       break;
13356     case PREFIX_DS:
13357       oappend_maybe_intel ("%ds:");
13358       break;
13359     case PREFIX_SS:
13360       oappend_maybe_intel ("%ss:");
13361       break;
13362     case PREFIX_ES:
13363       oappend_maybe_intel ("%es:");
13364       break;
13365     case PREFIX_FS:
13366       oappend_maybe_intel ("%fs:");
13367       break;
13368     case PREFIX_GS:
13369       oappend_maybe_intel ("%gs:");
13370       break;
13371     default:
13372       break;
13373     }
13374 }
13375
13376 static void
13377 OP_indirE (int bytemode, int sizeflag)
13378 {
13379   if (!intel_syntax)
13380     oappend ("*");
13381   OP_E (bytemode, sizeflag);
13382 }
13383
13384 static void
13385 print_operand_value (char *buf, int hex, bfd_vma disp)
13386 {
13387   if (address_mode == mode_64bit)
13388     {
13389       if (hex)
13390         {
13391           char tmp[30];
13392           int i;
13393           buf[0] = '0';
13394           buf[1] = 'x';
13395           sprintf_vma (tmp, disp);
13396           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13397           strcpy (buf + 2, tmp + i);
13398         }
13399       else
13400         {
13401           bfd_signed_vma v = disp;
13402           char tmp[30];
13403           int i;
13404           if (v < 0)
13405             {
13406               *(buf++) = '-';
13407               v = -disp;
13408               /* Check for possible overflow on 0x8000000000000000.  */
13409               if (v < 0)
13410                 {
13411                   strcpy (buf, "9223372036854775808");
13412                   return;
13413                 }
13414             }
13415           if (!v)
13416             {
13417               strcpy (buf, "0");
13418               return;
13419             }
13420
13421           i = 0;
13422           tmp[29] = 0;
13423           while (v)
13424             {
13425               tmp[28 - i] = (v % 10) + '0';
13426               v /= 10;
13427               i++;
13428             }
13429           strcpy (buf, tmp + 29 - i);
13430         }
13431     }
13432   else
13433     {
13434       if (hex)
13435         sprintf (buf, "0x%x", (unsigned int) disp);
13436       else
13437         sprintf (buf, "%d", (int) disp);
13438     }
13439 }
13440
13441 /* Put DISP in BUF as signed hex number.  */
13442
13443 static void
13444 print_displacement (char *buf, bfd_vma disp)
13445 {
13446   bfd_signed_vma val = disp;
13447   char tmp[30];
13448   int i, j = 0;
13449
13450   if (val < 0)
13451     {
13452       buf[j++] = '-';
13453       val = -disp;
13454
13455       /* Check for possible overflow.  */
13456       if (val < 0)
13457         {
13458           switch (address_mode)
13459             {
13460             case mode_64bit:
13461               strcpy (buf + j, "0x8000000000000000");
13462               break;
13463             case mode_32bit:
13464               strcpy (buf + j, "0x80000000");
13465               break;
13466             case mode_16bit:
13467               strcpy (buf + j, "0x8000");
13468               break;
13469             }
13470           return;
13471         }
13472     }
13473
13474   buf[j++] = '0';
13475   buf[j++] = 'x';
13476
13477   sprintf_vma (tmp, (bfd_vma) val);
13478   for (i = 0; tmp[i] == '0'; i++)
13479     continue;
13480   if (tmp[i] == '\0')
13481     i--;
13482   strcpy (buf + j, tmp + i);
13483 }
13484
13485 static void
13486 intel_operand_size (int bytemode, int sizeflag)
13487 {
13488   if (vex.evex
13489       && vex.b
13490       && (bytemode == x_mode
13491           || bytemode == evex_half_bcst_xmmq_mode))
13492     {
13493       if (vex.w)
13494         oappend ("QWORD PTR ");
13495       else
13496         oappend ("DWORD PTR ");
13497       return;
13498     }
13499   switch (bytemode)
13500     {
13501     case b_mode:
13502     case b_swap_mode:
13503     case dqb_mode:
13504     case db_mode:
13505       oappend ("BYTE PTR ");
13506       break;
13507     case w_mode:
13508     case dw_mode:
13509     case dqw_mode:
13510       oappend ("WORD PTR ");
13511       break;
13512     case indir_v_mode:
13513       if (address_mode == mode_64bit && isa64 == intel64)
13514         {
13515           oappend ("QWORD PTR ");
13516           break;
13517         }
13518       /* Fall through.  */
13519     case stack_v_mode:
13520       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13521         {
13522           oappend ("QWORD PTR ");
13523           break;
13524         }
13525       /* Fall through.  */
13526     case v_mode:
13527     case v_swap_mode:
13528     case dq_mode:
13529       USED_REX (REX_W);
13530       if (rex & REX_W)
13531         oappend ("QWORD PTR ");
13532       else
13533         {
13534           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13535             oappend ("DWORD PTR ");
13536           else
13537             oappend ("WORD PTR ");
13538           used_prefixes |= (prefixes & PREFIX_DATA);
13539         }
13540       break;
13541     case z_mode:
13542       if ((rex & REX_W) || (sizeflag & DFLAG))
13543         *obufp++ = 'D';
13544       oappend ("WORD PTR ");
13545       if (!(rex & REX_W))
13546         used_prefixes |= (prefixes & PREFIX_DATA);
13547       break;
13548     case a_mode:
13549       if (sizeflag & DFLAG)
13550         oappend ("QWORD PTR ");
13551       else
13552         oappend ("DWORD PTR ");
13553       used_prefixes |= (prefixes & PREFIX_DATA);
13554       break;
13555     case movsxd_mode:
13556       if (!(sizeflag & DFLAG) && isa64 == intel64)
13557         oappend ("WORD PTR ");
13558       else
13559         oappend ("DWORD PTR ");
13560       used_prefixes |= (prefixes & PREFIX_DATA);
13561       break;
13562     case d_mode:
13563     case d_scalar_mode:
13564     case d_scalar_swap_mode:
13565     case d_swap_mode:
13566     case dqd_mode:
13567       oappend ("DWORD PTR ");
13568       break;
13569     case q_mode:
13570     case q_scalar_mode:
13571     case q_scalar_swap_mode:
13572     case q_swap_mode:
13573       oappend ("QWORD PTR ");
13574       break;
13575     case m_mode:
13576       if (address_mode == mode_64bit)
13577         oappend ("QWORD PTR ");
13578       else
13579         oappend ("DWORD PTR ");
13580       break;
13581     case f_mode:
13582       if (sizeflag & DFLAG)
13583         oappend ("FWORD PTR ");
13584       else
13585         oappend ("DWORD PTR ");
13586       used_prefixes |= (prefixes & PREFIX_DATA);
13587       break;
13588     case t_mode:
13589       oappend ("TBYTE PTR ");
13590       break;
13591     case x_mode:
13592     case x_swap_mode:
13593     case evex_x_gscat_mode:
13594     case evex_x_nobcst_mode:
13595     case b_scalar_mode:
13596     case w_scalar_mode:
13597       if (need_vex)
13598         {
13599           switch (vex.length)
13600             {
13601             case 128:
13602               oappend ("XMMWORD PTR ");
13603               break;
13604             case 256:
13605               oappend ("YMMWORD PTR ");
13606               break;
13607             case 512:
13608               oappend ("ZMMWORD PTR ");
13609               break;
13610             default:
13611               abort ();
13612             }
13613         }
13614       else
13615         oappend ("XMMWORD PTR ");
13616       break;
13617     case xmm_mode:
13618       oappend ("XMMWORD PTR ");
13619       break;
13620     case ymm_mode:
13621       oappend ("YMMWORD PTR ");
13622       break;
13623     case xmmq_mode:
13624     case evex_half_bcst_xmmq_mode:
13625       if (!need_vex)
13626         abort ();
13627
13628       switch (vex.length)
13629         {
13630         case 128:
13631           oappend ("QWORD PTR ");
13632           break;
13633         case 256:
13634           oappend ("XMMWORD PTR ");
13635           break;
13636         case 512:
13637           oappend ("YMMWORD PTR ");
13638           break;
13639         default:
13640           abort ();
13641         }
13642       break;
13643     case xmm_mb_mode:
13644       if (!need_vex)
13645         abort ();
13646
13647       switch (vex.length)
13648         {
13649         case 128:
13650         case 256:
13651         case 512:
13652           oappend ("BYTE PTR ");
13653           break;
13654         default:
13655           abort ();
13656         }
13657       break;
13658     case xmm_mw_mode:
13659       if (!need_vex)
13660         abort ();
13661
13662       switch (vex.length)
13663         {
13664         case 128:
13665         case 256:
13666         case 512:
13667           oappend ("WORD PTR ");
13668           break;
13669         default:
13670           abort ();
13671         }
13672       break;
13673     case xmm_md_mode:
13674       if (!need_vex)
13675         abort ();
13676
13677       switch (vex.length)
13678         {
13679         case 128:
13680         case 256:
13681         case 512:
13682           oappend ("DWORD PTR ");
13683           break;
13684         default:
13685           abort ();
13686         }
13687       break;
13688     case xmm_mq_mode:
13689       if (!need_vex)
13690         abort ();
13691
13692       switch (vex.length)
13693         {
13694         case 128:
13695         case 256:
13696         case 512:
13697           oappend ("QWORD PTR ");
13698           break;
13699         default:
13700           abort ();
13701         }
13702       break;
13703     case xmmdw_mode:
13704       if (!need_vex)
13705         abort ();
13706
13707       switch (vex.length)
13708         {
13709         case 128:
13710           oappend ("WORD PTR ");
13711           break;
13712         case 256:
13713           oappend ("DWORD PTR ");
13714           break;
13715         case 512:
13716           oappend ("QWORD PTR ");
13717           break;
13718         default:
13719           abort ();
13720         }
13721       break;
13722     case xmmqd_mode:
13723       if (!need_vex)
13724         abort ();
13725
13726       switch (vex.length)
13727         {
13728         case 128:
13729           oappend ("DWORD PTR ");
13730           break;
13731         case 256:
13732           oappend ("QWORD PTR ");
13733           break;
13734         case 512:
13735           oappend ("XMMWORD PTR ");
13736           break;
13737         default:
13738           abort ();
13739         }
13740       break;
13741     case ymmq_mode:
13742       if (!need_vex)
13743         abort ();
13744
13745       switch (vex.length)
13746         {
13747         case 128:
13748           oappend ("QWORD PTR ");
13749           break;
13750         case 256:
13751           oappend ("YMMWORD PTR ");
13752           break;
13753         case 512:
13754           oappend ("ZMMWORD PTR ");
13755           break;
13756         default:
13757           abort ();
13758         }
13759       break;
13760     case ymmxmm_mode:
13761       if (!need_vex)
13762         abort ();
13763
13764       switch (vex.length)
13765         {
13766         case 128:
13767         case 256:
13768           oappend ("XMMWORD PTR ");
13769           break;
13770         default:
13771           abort ();
13772         }
13773       break;
13774     case o_mode:
13775       oappend ("OWORD PTR ");
13776       break;
13777     case xmm_mdq_mode:
13778     case vex_w_dq_mode:
13779     case vex_scalar_w_dq_mode:
13780       if (!need_vex)
13781         abort ();
13782
13783       if (vex.w)
13784         oappend ("QWORD PTR ");
13785       else
13786         oappend ("DWORD PTR ");
13787       break;
13788     case vex_vsib_d_w_dq_mode:
13789     case vex_vsib_q_w_dq_mode:
13790       if (!need_vex)
13791         abort ();
13792
13793       if (!vex.evex)
13794         {
13795           if (vex.w)
13796             oappend ("QWORD PTR ");
13797           else
13798             oappend ("DWORD PTR ");
13799         }
13800       else
13801         {
13802           switch (vex.length)
13803             {
13804             case 128:
13805               oappend ("XMMWORD PTR ");
13806               break;
13807             case 256:
13808               oappend ("YMMWORD PTR ");
13809               break;
13810             case 512:
13811               oappend ("ZMMWORD PTR ");
13812               break;
13813             default:
13814               abort ();
13815             }
13816         }
13817       break;
13818     case vex_vsib_q_w_d_mode:
13819     case vex_vsib_d_w_d_mode:
13820       if (!need_vex || !vex.evex)
13821         abort ();
13822
13823       switch (vex.length)
13824         {
13825         case 128:
13826           oappend ("QWORD PTR ");
13827           break;
13828         case 256:
13829           oappend ("XMMWORD PTR ");
13830           break;
13831         case 512:
13832           oappend ("YMMWORD PTR ");
13833           break;
13834         default:
13835           abort ();
13836         }
13837
13838       break;
13839     case mask_bd_mode:
13840       if (!need_vex || vex.length != 128)
13841         abort ();
13842       if (vex.w)
13843         oappend ("DWORD PTR ");
13844       else
13845         oappend ("BYTE PTR ");
13846       break;
13847     case mask_mode:
13848       if (!need_vex)
13849         abort ();
13850       if (vex.w)
13851         oappend ("QWORD PTR ");
13852       else
13853         oappend ("WORD PTR ");
13854       break;
13855     case v_bnd_mode:
13856     case v_bndmk_mode:
13857     default:
13858       break;
13859     }
13860 }
13861
13862 static void
13863 OP_E_register (int bytemode, int sizeflag)
13864 {
13865   int reg = modrm.rm;
13866   const char **names;
13867
13868   USED_REX (REX_B);
13869   if ((rex & REX_B))
13870     reg += 8;
13871
13872   if ((sizeflag & SUFFIX_ALWAYS)
13873       && (bytemode == b_swap_mode
13874           || bytemode == bnd_swap_mode
13875           || bytemode == v_swap_mode))
13876     swap_operand ();
13877
13878   switch (bytemode)
13879     {
13880     case b_mode:
13881     case b_swap_mode:
13882       USED_REX (0);
13883       if (rex)
13884         names = names8rex;
13885       else
13886         names = names8;
13887       break;
13888     case w_mode:
13889       names = names16;
13890       break;
13891     case d_mode:
13892     case dw_mode:
13893     case db_mode:
13894       names = names32;
13895       break;
13896     case q_mode:
13897       names = names64;
13898       break;
13899     case m_mode:
13900     case v_bnd_mode:
13901       names = address_mode == mode_64bit ? names64 : names32;
13902       break;
13903     case bnd_mode:
13904     case bnd_swap_mode:
13905       if (reg > 0x3)
13906         {
13907           oappend ("(bad)");
13908           return;
13909         }
13910       names = names_bnd;
13911       break;
13912     case indir_v_mode:
13913       if (address_mode == mode_64bit && isa64 == intel64)
13914         {
13915           names = names64;
13916           break;
13917         }
13918       /* Fall through.  */
13919     case stack_v_mode:
13920       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13921         {
13922           names = names64;
13923           break;
13924         }
13925       bytemode = v_mode;
13926       /* Fall through.  */
13927     case v_mode:
13928     case v_swap_mode:
13929     case dq_mode:
13930     case dqb_mode:
13931     case dqd_mode:
13932     case dqw_mode:
13933       USED_REX (REX_W);
13934       if (rex & REX_W)
13935         names = names64;
13936       else
13937         {
13938           if ((sizeflag & DFLAG)
13939               || (bytemode != v_mode
13940                   && bytemode != v_swap_mode))
13941             names = names32;
13942           else
13943             names = names16;
13944           used_prefixes |= (prefixes & PREFIX_DATA);
13945         }
13946       break;
13947     case movsxd_mode:
13948       if (!(sizeflag & DFLAG) && isa64 == intel64)
13949         names = names16;
13950       else
13951         names = names32;
13952       used_prefixes |= (prefixes & PREFIX_DATA);
13953       break;
13954     case va_mode:
13955       names = (address_mode == mode_64bit
13956                ? names64 : names32);
13957       if (!(prefixes & PREFIX_ADDR))
13958         names = (address_mode == mode_16bit
13959                      ? names16 : names);
13960       else
13961         {
13962           /* Remove "addr16/addr32".  */
13963           all_prefixes[last_addr_prefix] = 0;
13964           names = (address_mode != mode_32bit
13965                        ? names32 : names16);
13966           used_prefixes |= PREFIX_ADDR;
13967         }
13968       break;
13969     case mask_bd_mode:
13970     case mask_mode:
13971       if (reg > 0x7)
13972         {
13973           oappend ("(bad)");
13974           return;
13975         }
13976       names = names_mask;
13977       break;
13978     case 0:
13979       return;
13980     default:
13981       oappend (INTERNAL_DISASSEMBLER_ERROR);
13982       return;
13983     }
13984   oappend (names[reg]);
13985 }
13986
13987 static void
13988 OP_E_memory (int bytemode, int sizeflag)
13989 {
13990   bfd_vma disp = 0;
13991   int add = (rex & REX_B) ? 8 : 0;
13992   int riprel = 0;
13993   int shift;
13994
13995   if (vex.evex)
13996     {
13997       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13998       if (vex.b
13999           && bytemode != x_mode
14000           && bytemode != xmmq_mode
14001           && bytemode != evex_half_bcst_xmmq_mode)
14002         {
14003           BadOp ();
14004           return;
14005         }
14006       switch (bytemode)
14007         {
14008         case dqw_mode:
14009         case dw_mode:
14010           shift = 1;
14011           break;
14012         case dqb_mode:
14013         case db_mode:
14014           shift = 0;
14015           break;
14016         case dq_mode:
14017           if (address_mode != mode_64bit)
14018             {
14019               shift = 2;
14020               break;
14021             }
14022             /* fall through */
14023         case vex_vsib_d_w_dq_mode:
14024         case vex_vsib_d_w_d_mode:
14025         case vex_vsib_q_w_dq_mode:
14026         case vex_vsib_q_w_d_mode:
14027         case evex_x_gscat_mode:
14028         case xmm_mdq_mode:
14029           shift = vex.w ? 3 : 2;
14030           break;
14031         case x_mode:
14032         case evex_half_bcst_xmmq_mode:
14033         case xmmq_mode:
14034           if (vex.b)
14035             {
14036               shift = vex.w ? 3 : 2;
14037               break;
14038             }
14039           /* Fall through.  */
14040         case xmmqd_mode:
14041         case xmmdw_mode:
14042         case ymmq_mode:
14043         case evex_x_nobcst_mode:
14044         case x_swap_mode:
14045           switch (vex.length)
14046             {
14047             case 128:
14048               shift = 4;
14049               break;
14050             case 256:
14051               shift = 5;
14052               break;
14053             case 512:
14054               shift = 6;
14055               break;
14056             default:
14057               abort ();
14058             }
14059           break;
14060         case ymm_mode:
14061           shift = 5;
14062           break;
14063         case xmm_mode:
14064           shift = 4;
14065           break;
14066         case xmm_mq_mode:
14067         case q_mode:
14068         case q_scalar_mode:
14069         case q_swap_mode:
14070         case q_scalar_swap_mode:
14071           shift = 3;
14072           break;
14073         case dqd_mode:
14074         case xmm_md_mode:
14075         case d_mode:
14076         case d_scalar_mode:
14077         case d_swap_mode:
14078         case d_scalar_swap_mode:
14079           shift = 2;
14080           break;
14081         case w_scalar_mode:
14082         case xmm_mw_mode:
14083           shift = 1;
14084           break;
14085         case b_scalar_mode:
14086         case xmm_mb_mode:
14087           shift = 0;
14088           break;
14089         default:
14090           abort ();
14091         }
14092       /* Make necessary corrections to shift for modes that need it.
14093          For these modes we currently have shift 4, 5 or 6 depending on
14094          vex.length (it corresponds to xmmword, ymmword or zmmword
14095          operand).  We might want to make it 3, 4 or 5 (e.g. for
14096          xmmq_mode).  In case of broadcast enabled the corrections
14097          aren't needed, as element size is always 32 or 64 bits.  */
14098       if (!vex.b
14099           && (bytemode == xmmq_mode
14100               || bytemode == evex_half_bcst_xmmq_mode))
14101         shift -= 1;
14102       else if (bytemode == xmmqd_mode)
14103         shift -= 2;
14104       else if (bytemode == xmmdw_mode)
14105         shift -= 3;
14106       else if (bytemode == ymmq_mode && vex.length == 128)
14107         shift -= 1;
14108     }
14109   else
14110     shift = 0;
14111
14112   USED_REX (REX_B);
14113   if (intel_syntax)
14114     intel_operand_size (bytemode, sizeflag);
14115   append_seg ();
14116
14117   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14118     {
14119       /* 32/64 bit address mode */
14120       int havedisp;
14121       int havesib;
14122       int havebase;
14123       int haveindex;
14124       int needindex;
14125       int needaddr32;
14126       int base, rbase;
14127       int vindex = 0;
14128       int scale = 0;
14129       int addr32flag = !((sizeflag & AFLAG)
14130                          || bytemode == v_bnd_mode
14131                          || bytemode == v_bndmk_mode
14132                          || bytemode == bnd_mode
14133                          || bytemode == bnd_swap_mode);
14134       const char **indexes64 = names64;
14135       const char **indexes32 = names32;
14136
14137       havesib = 0;
14138       havebase = 1;
14139       haveindex = 0;
14140       base = modrm.rm;
14141
14142       if (base == 4)
14143         {
14144           havesib = 1;
14145           vindex = sib.index;
14146           USED_REX (REX_X);
14147           if (rex & REX_X)
14148             vindex += 8;
14149           switch (bytemode)
14150             {
14151             case vex_vsib_d_w_dq_mode:
14152             case vex_vsib_d_w_d_mode:
14153             case vex_vsib_q_w_dq_mode:
14154             case vex_vsib_q_w_d_mode:
14155               if (!need_vex)
14156                 abort ();
14157               if (vex.evex)
14158                 {
14159                   if (!vex.v)
14160                     vindex += 16;
14161                 }
14162
14163               haveindex = 1;
14164               switch (vex.length)
14165                 {
14166                 case 128:
14167                   indexes64 = indexes32 = names_xmm;
14168                   break;
14169                 case 256:
14170                   if (!vex.w
14171                       || bytemode == vex_vsib_q_w_dq_mode
14172                       || bytemode == vex_vsib_q_w_d_mode)
14173                     indexes64 = indexes32 = names_ymm;
14174                   else
14175                     indexes64 = indexes32 = names_xmm;
14176                   break;
14177                 case 512:
14178                   if (!vex.w
14179                       || bytemode == vex_vsib_q_w_dq_mode
14180                       || bytemode == vex_vsib_q_w_d_mode)
14181                     indexes64 = indexes32 = names_zmm;
14182                   else
14183                     indexes64 = indexes32 = names_ymm;
14184                   break;
14185                 default:
14186                   abort ();
14187                 }
14188               break;
14189             default:
14190               haveindex = vindex != 4;
14191               break;
14192             }
14193           scale = sib.scale;
14194           base = sib.base;
14195           codep++;
14196         }
14197       rbase = base + add;
14198
14199       switch (modrm.mod)
14200         {
14201         case 0:
14202           if (base == 5)
14203             {
14204               havebase = 0;
14205               if (address_mode == mode_64bit && !havesib)
14206                 riprel = 1;
14207               disp = get32s ();
14208               if (riprel && bytemode == v_bndmk_mode)
14209                 {
14210                   oappend ("(bad)");
14211                   return;
14212                 }
14213             }
14214           break;
14215         case 1:
14216           FETCH_DATA (the_info, codep + 1);
14217           disp = *codep++;
14218           if ((disp & 0x80) != 0)
14219             disp -= 0x100;
14220           if (vex.evex && shift > 0)
14221             disp <<= shift;
14222           break;
14223         case 2:
14224           disp = get32s ();
14225           break;
14226         }
14227
14228       needindex = 0;
14229       needaddr32 = 0;
14230       if (havesib
14231           && !havebase
14232           && !haveindex
14233           && address_mode != mode_16bit)
14234         {
14235           if (address_mode == mode_64bit)
14236             {
14237               /* Display eiz instead of addr32.  */
14238               needindex = addr32flag;
14239               needaddr32 = 1;
14240             }
14241           else
14242             {
14243               /* In 32-bit mode, we need index register to tell [offset]
14244                  from [eiz*1 + offset].  */
14245               needindex = 1;
14246             }
14247         }
14248
14249       havedisp = (havebase
14250                   || needindex
14251                   || (havesib && (haveindex || scale != 0)));
14252
14253       if (!intel_syntax)
14254         if (modrm.mod != 0 || base == 5)
14255           {
14256             if (havedisp || riprel)
14257               print_displacement (scratchbuf, disp);
14258             else
14259               print_operand_value (scratchbuf, 1, disp);
14260             oappend (scratchbuf);
14261             if (riprel)
14262               {
14263                 set_op (disp, 1);
14264                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14265               }
14266           }
14267
14268       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14269           && (bytemode != v_bnd_mode)
14270           && (bytemode != v_bndmk_mode)
14271           && (bytemode != bnd_mode)
14272           && (bytemode != bnd_swap_mode))
14273         used_prefixes |= PREFIX_ADDR;
14274
14275       if (havedisp || (intel_syntax && riprel))
14276         {
14277           *obufp++ = open_char;
14278           if (intel_syntax && riprel)
14279             {
14280               set_op (disp, 1);
14281               oappend (!addr32flag ? "rip" : "eip");
14282             }
14283           *obufp = '\0';
14284           if (havebase)
14285             oappend (address_mode == mode_64bit && !addr32flag
14286                      ? names64[rbase] : names32[rbase]);
14287           if (havesib)
14288             {
14289               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14290                  print index to tell base + index from base.  */
14291               if (scale != 0
14292                   || needindex
14293                   || haveindex
14294                   || (havebase && base != ESP_REG_NUM))
14295                 {
14296                   if (!intel_syntax || havebase)
14297                     {
14298                       *obufp++ = separator_char;
14299                       *obufp = '\0';
14300                     }
14301                   if (haveindex)
14302                     oappend (address_mode == mode_64bit && !addr32flag
14303                              ? indexes64[vindex] : indexes32[vindex]);
14304                   else
14305                     oappend (address_mode == mode_64bit && !addr32flag
14306                              ? index64 : index32);
14307
14308                   *obufp++ = scale_char;
14309                   *obufp = '\0';
14310                   sprintf (scratchbuf, "%d", 1 << scale);
14311                   oappend (scratchbuf);
14312                 }
14313             }
14314           if (intel_syntax
14315               && (disp || modrm.mod != 0 || base == 5))
14316             {
14317               if (!havedisp || (bfd_signed_vma) disp >= 0)
14318                 {
14319                   *obufp++ = '+';
14320                   *obufp = '\0';
14321                 }
14322               else if (modrm.mod != 1 && disp != -disp)
14323                 {
14324                   *obufp++ = '-';
14325                   *obufp = '\0';
14326                   disp = - (bfd_signed_vma) disp;
14327                 }
14328
14329               if (havedisp)
14330                 print_displacement (scratchbuf, disp);
14331               else
14332                 print_operand_value (scratchbuf, 1, disp);
14333               oappend (scratchbuf);
14334             }
14335
14336           *obufp++ = close_char;
14337           *obufp = '\0';
14338         }
14339       else if (intel_syntax)
14340         {
14341           if (modrm.mod != 0 || base == 5)
14342             {
14343               if (!active_seg_prefix)
14344                 {
14345                   oappend (names_seg[ds_reg - es_reg]);
14346                   oappend (":");
14347                 }
14348               print_operand_value (scratchbuf, 1, disp);
14349               oappend (scratchbuf);
14350             }
14351         }
14352     }
14353   else
14354     {
14355       /* 16 bit address mode */
14356       used_prefixes |= prefixes & PREFIX_ADDR;
14357       switch (modrm.mod)
14358         {
14359         case 0:
14360           if (modrm.rm == 6)
14361             {
14362               disp = get16 ();
14363               if ((disp & 0x8000) != 0)
14364                 disp -= 0x10000;
14365             }
14366           break;
14367         case 1:
14368           FETCH_DATA (the_info, codep + 1);
14369           disp = *codep++;
14370           if ((disp & 0x80) != 0)
14371             disp -= 0x100;
14372           if (vex.evex && shift > 0)
14373             disp <<= shift;
14374           break;
14375         case 2:
14376           disp = get16 ();
14377           if ((disp & 0x8000) != 0)
14378             disp -= 0x10000;
14379           break;
14380         }
14381
14382       if (!intel_syntax)
14383         if (modrm.mod != 0 || modrm.rm == 6)
14384           {
14385             print_displacement (scratchbuf, disp);
14386             oappend (scratchbuf);
14387           }
14388
14389       if (modrm.mod != 0 || modrm.rm != 6)
14390         {
14391           *obufp++ = open_char;
14392           *obufp = '\0';
14393           oappend (index16[modrm.rm]);
14394           if (intel_syntax
14395               && (disp || modrm.mod != 0 || modrm.rm == 6))
14396             {
14397               if ((bfd_signed_vma) disp >= 0)
14398                 {
14399                   *obufp++ = '+';
14400                   *obufp = '\0';
14401                 }
14402               else if (modrm.mod != 1)
14403                 {
14404                   *obufp++ = '-';
14405                   *obufp = '\0';
14406                   disp = - (bfd_signed_vma) disp;
14407                 }
14408
14409               print_displacement (scratchbuf, disp);
14410               oappend (scratchbuf);
14411             }
14412
14413           *obufp++ = close_char;
14414           *obufp = '\0';
14415         }
14416       else if (intel_syntax)
14417         {
14418           if (!active_seg_prefix)
14419             {
14420               oappend (names_seg[ds_reg - es_reg]);
14421               oappend (":");
14422             }
14423           print_operand_value (scratchbuf, 1, disp & 0xffff);
14424           oappend (scratchbuf);
14425         }
14426     }
14427   if (vex.evex && vex.b
14428       && (bytemode == x_mode
14429           || bytemode == xmmq_mode
14430           || bytemode == evex_half_bcst_xmmq_mode))
14431     {
14432       if (vex.w
14433           || bytemode == xmmq_mode
14434           || bytemode == evex_half_bcst_xmmq_mode)
14435         {
14436           switch (vex.length)
14437             {
14438             case 128:
14439               oappend ("{1to2}");
14440               break;
14441             case 256:
14442               oappend ("{1to4}");
14443               break;
14444             case 512:
14445               oappend ("{1to8}");
14446               break;
14447             default:
14448               abort ();
14449             }
14450         }
14451       else
14452         {
14453           switch (vex.length)
14454             {
14455             case 128:
14456               oappend ("{1to4}");
14457               break;
14458             case 256:
14459               oappend ("{1to8}");
14460               break;
14461             case 512:
14462               oappend ("{1to16}");
14463               break;
14464             default:
14465               abort ();
14466             }
14467         }
14468     }
14469 }
14470
14471 static void
14472 OP_E (int bytemode, int sizeflag)
14473 {
14474   /* Skip mod/rm byte.  */
14475   MODRM_CHECK;
14476   codep++;
14477
14478   if (modrm.mod == 3)
14479     OP_E_register (bytemode, sizeflag);
14480   else
14481     OP_E_memory (bytemode, sizeflag);
14482 }
14483
14484 static void
14485 OP_G (int bytemode, int sizeflag)
14486 {
14487   int add = 0;
14488   const char **names;
14489   USED_REX (REX_R);
14490   if (rex & REX_R)
14491     add += 8;
14492   switch (bytemode)
14493     {
14494     case b_mode:
14495       USED_REX (0);
14496       if (rex)
14497         oappend (names8rex[modrm.reg + add]);
14498       else
14499         oappend (names8[modrm.reg + add]);
14500       break;
14501     case w_mode:
14502       oappend (names16[modrm.reg + add]);
14503       break;
14504     case d_mode:
14505     case db_mode:
14506     case dw_mode:
14507       oappend (names32[modrm.reg + add]);
14508       break;
14509     case q_mode:
14510       oappend (names64[modrm.reg + add]);
14511       break;
14512     case bnd_mode:
14513       if (modrm.reg > 0x3)
14514         {
14515           oappend ("(bad)");
14516           return;
14517         }
14518       oappend (names_bnd[modrm.reg]);
14519       break;
14520     case v_mode:
14521     case dq_mode:
14522     case dqb_mode:
14523     case dqd_mode:
14524     case dqw_mode:
14525     case movsxd_mode:
14526       USED_REX (REX_W);
14527       if (rex & REX_W)
14528         oappend (names64[modrm.reg + add]);
14529       else
14530         {
14531           if ((sizeflag & DFLAG)
14532               || (bytemode != v_mode && bytemode != movsxd_mode))
14533             oappend (names32[modrm.reg + add]);
14534           else
14535             oappend (names16[modrm.reg + add]);
14536           used_prefixes |= (prefixes & PREFIX_DATA);
14537         }
14538       break;
14539     case va_mode:
14540       names = (address_mode == mode_64bit
14541                ? names64 : names32);
14542       if (!(prefixes & PREFIX_ADDR))
14543         {
14544           if (address_mode == mode_16bit)
14545             names = names16;
14546         }
14547       else
14548         {
14549           /* Remove "addr16/addr32".  */
14550           all_prefixes[last_addr_prefix] = 0;
14551           names = (address_mode != mode_32bit
14552                        ? names32 : names16);
14553           used_prefixes |= PREFIX_ADDR;
14554         }
14555       oappend (names[modrm.reg + add]);
14556       break;
14557     case m_mode:
14558       if (address_mode == mode_64bit)
14559         oappend (names64[modrm.reg + add]);
14560       else
14561         oappend (names32[modrm.reg + add]);
14562       break;
14563     case mask_bd_mode:
14564     case mask_mode:
14565       if ((modrm.reg + add) > 0x7)
14566         {
14567           oappend ("(bad)");
14568           return;
14569         }
14570       oappend (names_mask[modrm.reg + add]);
14571       break;
14572     default:
14573       oappend (INTERNAL_DISASSEMBLER_ERROR);
14574       break;
14575     }
14576 }
14577
14578 static bfd_vma
14579 get64 (void)
14580 {
14581   bfd_vma x;
14582 #ifdef BFD64
14583   unsigned int a;
14584   unsigned int b;
14585
14586   FETCH_DATA (the_info, codep + 8);
14587   a = *codep++ & 0xff;
14588   a |= (*codep++ & 0xff) << 8;
14589   a |= (*codep++ & 0xff) << 16;
14590   a |= (*codep++ & 0xffu) << 24;
14591   b = *codep++ & 0xff;
14592   b |= (*codep++ & 0xff) << 8;
14593   b |= (*codep++ & 0xff) << 16;
14594   b |= (*codep++ & 0xffu) << 24;
14595   x = a + ((bfd_vma) b << 32);
14596 #else
14597   abort ();
14598   x = 0;
14599 #endif
14600   return x;
14601 }
14602
14603 static bfd_signed_vma
14604 get32 (void)
14605 {
14606   bfd_signed_vma x = 0;
14607
14608   FETCH_DATA (the_info, codep + 4);
14609   x = *codep++ & (bfd_signed_vma) 0xff;
14610   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14611   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14612   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14613   return x;
14614 }
14615
14616 static bfd_signed_vma
14617 get32s (void)
14618 {
14619   bfd_signed_vma x = 0;
14620
14621   FETCH_DATA (the_info, codep + 4);
14622   x = *codep++ & (bfd_signed_vma) 0xff;
14623   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14624   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14625   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14626
14627   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14628
14629   return x;
14630 }
14631
14632 static int
14633 get16 (void)
14634 {
14635   int x = 0;
14636
14637   FETCH_DATA (the_info, codep + 2);
14638   x = *codep++ & 0xff;
14639   x |= (*codep++ & 0xff) << 8;
14640   return x;
14641 }
14642
14643 static void
14644 set_op (bfd_vma op, int riprel)
14645 {
14646   op_index[op_ad] = op_ad;
14647   if (address_mode == mode_64bit)
14648     {
14649       op_address[op_ad] = op;
14650       op_riprel[op_ad] = riprel;
14651     }
14652   else
14653     {
14654       /* Mask to get a 32-bit address.  */
14655       op_address[op_ad] = op & 0xffffffff;
14656       op_riprel[op_ad] = riprel & 0xffffffff;
14657     }
14658 }
14659
14660 static void
14661 OP_REG (int code, int sizeflag)
14662 {
14663   const char *s;
14664   int add;
14665
14666   switch (code)
14667     {
14668     case es_reg: case ss_reg: case cs_reg:
14669     case ds_reg: case fs_reg: case gs_reg:
14670       oappend (names_seg[code - es_reg]);
14671       return;
14672     }
14673
14674   USED_REX (REX_B);
14675   if (rex & REX_B)
14676     add = 8;
14677   else
14678     add = 0;
14679
14680   switch (code)
14681     {
14682     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14683     case sp_reg: case bp_reg: case si_reg: case di_reg:
14684       s = names16[code - ax_reg + add];
14685       break;
14686     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14687     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14688       USED_REX (0);
14689       if (rex)
14690         s = names8rex[code - al_reg + add];
14691       else
14692         s = names8[code - al_reg];
14693       break;
14694     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14695     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14696       if (address_mode == mode_64bit
14697           && ((sizeflag & DFLAG) || (rex & REX_W)))
14698         {
14699           s = names64[code - rAX_reg + add];
14700           break;
14701         }
14702       code += eAX_reg - rAX_reg;
14703       /* Fall through.  */
14704     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14705     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14706       USED_REX (REX_W);
14707       if (rex & REX_W)
14708         s = names64[code - eAX_reg + add];
14709       else
14710         {
14711           if (sizeflag & DFLAG)
14712             s = names32[code - eAX_reg + add];
14713           else
14714             s = names16[code - eAX_reg + add];
14715           used_prefixes |= (prefixes & PREFIX_DATA);
14716         }
14717       break;
14718     default:
14719       s = INTERNAL_DISASSEMBLER_ERROR;
14720       break;
14721     }
14722   oappend (s);
14723 }
14724
14725 static void
14726 OP_IMREG (int code, int sizeflag)
14727 {
14728   const char *s;
14729
14730   switch (code)
14731     {
14732     case indir_dx_reg:
14733       if (intel_syntax)
14734         s = "dx";
14735       else
14736         s = "(%dx)";
14737       break;
14738     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14739     case sp_reg: case bp_reg: case si_reg: case di_reg:
14740       s = names16[code - ax_reg];
14741       break;
14742     case es_reg: case ss_reg: case cs_reg:
14743     case ds_reg: case fs_reg: case gs_reg:
14744       s = names_seg[code - es_reg];
14745       break;
14746     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14747     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14748       USED_REX (0);
14749       if (rex)
14750         s = names8rex[code - al_reg];
14751       else
14752         s = names8[code - al_reg];
14753       break;
14754     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14755     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14756       USED_REX (REX_W);
14757       if (rex & REX_W)
14758         s = names64[code - eAX_reg];
14759       else
14760         {
14761           if (sizeflag & DFLAG)
14762             s = names32[code - eAX_reg];
14763           else
14764             s = names16[code - eAX_reg];
14765           used_prefixes |= (prefixes & PREFIX_DATA);
14766         }
14767       break;
14768     case z_mode_ax_reg:
14769       if ((rex & REX_W) || (sizeflag & DFLAG))
14770         s = *names32;
14771       else
14772         s = *names16;
14773       if (!(rex & REX_W))
14774         used_prefixes |= (prefixes & PREFIX_DATA);
14775       break;
14776     default:
14777       s = INTERNAL_DISASSEMBLER_ERROR;
14778       break;
14779     }
14780   oappend (s);
14781 }
14782
14783 static void
14784 OP_I (int bytemode, int sizeflag)
14785 {
14786   bfd_signed_vma op;
14787   bfd_signed_vma mask = -1;
14788
14789   switch (bytemode)
14790     {
14791     case b_mode:
14792       FETCH_DATA (the_info, codep + 1);
14793       op = *codep++;
14794       mask = 0xff;
14795       break;
14796     case v_mode:
14797       USED_REX (REX_W);
14798       if (rex & REX_W)
14799         op = get32s ();
14800       else
14801         {
14802           if (sizeflag & DFLAG)
14803             {
14804               op = get32 ();
14805               mask = 0xffffffff;
14806             }
14807           else
14808             {
14809               op = get16 ();
14810               mask = 0xfffff;
14811             }
14812           used_prefixes |= (prefixes & PREFIX_DATA);
14813         }
14814       break;
14815     case d_mode:
14816       mask = 0xffffffff;
14817       op = get32 ();
14818       break;
14819     case w_mode:
14820       mask = 0xfffff;
14821       op = get16 ();
14822       break;
14823     case const_1_mode:
14824       if (intel_syntax)
14825         oappend ("1");
14826       return;
14827     default:
14828       oappend (INTERNAL_DISASSEMBLER_ERROR);
14829       return;
14830     }
14831
14832   op &= mask;
14833   scratchbuf[0] = '$';
14834   print_operand_value (scratchbuf + 1, 1, op);
14835   oappend_maybe_intel (scratchbuf);
14836   scratchbuf[0] = '\0';
14837 }
14838
14839 static void
14840 OP_I64 (int bytemode, int sizeflag)
14841 {
14842   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14843     {
14844       OP_I (bytemode, sizeflag);
14845       return;
14846     }
14847
14848   USED_REX (REX_W);
14849
14850   scratchbuf[0] = '$';
14851   print_operand_value (scratchbuf + 1, 1, get64 ());
14852   oappend_maybe_intel (scratchbuf);
14853   scratchbuf[0] = '\0';
14854 }
14855
14856 static void
14857 OP_sI (int bytemode, int sizeflag)
14858 {
14859   bfd_signed_vma op;
14860
14861   switch (bytemode)
14862     {
14863     case b_mode:
14864     case b_T_mode:
14865       FETCH_DATA (the_info, codep + 1);
14866       op = *codep++;
14867       if ((op & 0x80) != 0)
14868         op -= 0x100;
14869       if (bytemode == b_T_mode)
14870         {
14871           if (address_mode != mode_64bit
14872               || !((sizeflag & DFLAG) || (rex & REX_W)))
14873             {
14874               /* The operand-size prefix is overridden by a REX prefix.  */
14875               if ((sizeflag & DFLAG) || (rex & REX_W))
14876                 op &= 0xffffffff;
14877               else
14878                 op &= 0xffff;
14879           }
14880         }
14881       else
14882         {
14883           if (!(rex & REX_W))
14884             {
14885               if (sizeflag & DFLAG)
14886                 op &= 0xffffffff;
14887               else
14888                 op &= 0xffff;
14889             }
14890         }
14891       break;
14892     case v_mode:
14893       /* The operand-size prefix is overridden by a REX prefix.  */
14894       if ((sizeflag & DFLAG) || (rex & REX_W))
14895         op = get32s ();
14896       else
14897         op = get16 ();
14898       break;
14899     default:
14900       oappend (INTERNAL_DISASSEMBLER_ERROR);
14901       return;
14902     }
14903
14904   scratchbuf[0] = '$';
14905   print_operand_value (scratchbuf + 1, 1, op);
14906   oappend_maybe_intel (scratchbuf);
14907 }
14908
14909 static void
14910 OP_J (int bytemode, int sizeflag)
14911 {
14912   bfd_vma disp;
14913   bfd_vma mask = -1;
14914   bfd_vma segment = 0;
14915
14916   switch (bytemode)
14917     {
14918     case b_mode:
14919       FETCH_DATA (the_info, codep + 1);
14920       disp = *codep++;
14921       if ((disp & 0x80) != 0)
14922         disp -= 0x100;
14923       break;
14924     case v_mode:
14925       if (isa64 != intel64)
14926     case dqw_mode:
14927         USED_REX (REX_W);
14928       if ((sizeflag & DFLAG)
14929           || (address_mode == mode_64bit
14930               && ((isa64 == intel64 && bytemode != dqw_mode)
14931                   || (rex & REX_W))))
14932         disp = get32s ();
14933       else
14934         {
14935           disp = get16 ();
14936           if ((disp & 0x8000) != 0)
14937             disp -= 0x10000;
14938           /* In 16bit mode, address is wrapped around at 64k within
14939              the same segment.  Otherwise, a data16 prefix on a jump
14940              instruction means that the pc is masked to 16 bits after
14941              the displacement is added!  */
14942           mask = 0xffff;
14943           if ((prefixes & PREFIX_DATA) == 0)
14944             segment = ((start_pc + (codep - start_codep))
14945                        & ~((bfd_vma) 0xffff));
14946         }
14947       if (address_mode != mode_64bit
14948           || (isa64 != intel64 && !(rex & REX_W)))
14949         used_prefixes |= (prefixes & PREFIX_DATA);
14950       break;
14951     default:
14952       oappend (INTERNAL_DISASSEMBLER_ERROR);
14953       return;
14954     }
14955   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14956   set_op (disp, 0);
14957   print_operand_value (scratchbuf, 1, disp);
14958   oappend (scratchbuf);
14959 }
14960
14961 static void
14962 OP_SEG (int bytemode, int sizeflag)
14963 {
14964   if (bytemode == w_mode)
14965     oappend (names_seg[modrm.reg]);
14966   else
14967     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14968 }
14969
14970 static void
14971 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14972 {
14973   int seg, offset;
14974
14975   if (sizeflag & DFLAG)
14976     {
14977       offset = get32 ();
14978       seg = get16 ();
14979     }
14980   else
14981     {
14982       offset = get16 ();
14983       seg = get16 ();
14984     }
14985   used_prefixes |= (prefixes & PREFIX_DATA);
14986   if (intel_syntax)
14987     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14988   else
14989     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14990   oappend (scratchbuf);
14991 }
14992
14993 static void
14994 OP_OFF (int bytemode, int sizeflag)
14995 {
14996   bfd_vma off;
14997
14998   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14999     intel_operand_size (bytemode, sizeflag);
15000   append_seg ();
15001
15002   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15003     off = get32 ();
15004   else
15005     off = get16 ();
15006
15007   if (intel_syntax)
15008     {
15009       if (!active_seg_prefix)
15010         {
15011           oappend (names_seg[ds_reg - es_reg]);
15012           oappend (":");
15013         }
15014     }
15015   print_operand_value (scratchbuf, 1, off);
15016   oappend (scratchbuf);
15017 }
15018
15019 static void
15020 OP_OFF64 (int bytemode, int sizeflag)
15021 {
15022   bfd_vma off;
15023
15024   if (address_mode != mode_64bit
15025       || (prefixes & PREFIX_ADDR))
15026     {
15027       OP_OFF (bytemode, sizeflag);
15028       return;
15029     }
15030
15031   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15032     intel_operand_size (bytemode, sizeflag);
15033   append_seg ();
15034
15035   off = get64 ();
15036
15037   if (intel_syntax)
15038     {
15039       if (!active_seg_prefix)
15040         {
15041           oappend (names_seg[ds_reg - es_reg]);
15042           oappend (":");
15043         }
15044     }
15045   print_operand_value (scratchbuf, 1, off);
15046   oappend (scratchbuf);
15047 }
15048
15049 static void
15050 ptr_reg (int code, int sizeflag)
15051 {
15052   const char *s;
15053
15054   *obufp++ = open_char;
15055   used_prefixes |= (prefixes & PREFIX_ADDR);
15056   if (address_mode == mode_64bit)
15057     {
15058       if (!(sizeflag & AFLAG))
15059         s = names32[code - eAX_reg];
15060       else
15061         s = names64[code - eAX_reg];
15062     }
15063   else if (sizeflag & AFLAG)
15064     s = names32[code - eAX_reg];
15065   else
15066     s = names16[code - eAX_reg];
15067   oappend (s);
15068   *obufp++ = close_char;
15069   *obufp = 0;
15070 }
15071
15072 static void
15073 OP_ESreg (int code, int sizeflag)
15074 {
15075   if (intel_syntax)
15076     {
15077       switch (codep[-1])
15078         {
15079         case 0x6d:      /* insw/insl */
15080           intel_operand_size (z_mode, sizeflag);
15081           break;
15082         case 0xa5:      /* movsw/movsl/movsq */
15083         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15084         case 0xab:      /* stosw/stosl */
15085         case 0xaf:      /* scasw/scasl */
15086           intel_operand_size (v_mode, sizeflag);
15087           break;
15088         default:
15089           intel_operand_size (b_mode, sizeflag);
15090         }
15091     }
15092   oappend_maybe_intel ("%es:");
15093   ptr_reg (code, sizeflag);
15094 }
15095
15096 static void
15097 OP_DSreg (int code, int sizeflag)
15098 {
15099   if (intel_syntax)
15100     {
15101       switch (codep[-1])
15102         {
15103         case 0x6f:      /* outsw/outsl */
15104           intel_operand_size (z_mode, sizeflag);
15105           break;
15106         case 0xa5:      /* movsw/movsl/movsq */
15107         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15108         case 0xad:      /* lodsw/lodsl/lodsq */
15109           intel_operand_size (v_mode, sizeflag);
15110           break;
15111         default:
15112           intel_operand_size (b_mode, sizeflag);
15113         }
15114     }
15115   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15116      default segment register DS is printed.  */
15117   if (!active_seg_prefix)
15118     active_seg_prefix = PREFIX_DS;
15119   append_seg ();
15120   ptr_reg (code, sizeflag);
15121 }
15122
15123 static void
15124 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15125 {
15126   int add;
15127   if (rex & REX_R)
15128     {
15129       USED_REX (REX_R);
15130       add = 8;
15131     }
15132   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15133     {
15134       all_prefixes[last_lock_prefix] = 0;
15135       used_prefixes |= PREFIX_LOCK;
15136       add = 8;
15137     }
15138   else
15139     add = 0;
15140   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15141   oappend_maybe_intel (scratchbuf);
15142 }
15143
15144 static void
15145 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15146 {
15147   int add;
15148   USED_REX (REX_R);
15149   if (rex & REX_R)
15150     add = 8;
15151   else
15152     add = 0;
15153   if (intel_syntax)
15154     sprintf (scratchbuf, "db%d", modrm.reg + add);
15155   else
15156     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15157   oappend (scratchbuf);
15158 }
15159
15160 static void
15161 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15162 {
15163   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15164   oappend_maybe_intel (scratchbuf);
15165 }
15166
15167 static void
15168 OP_R (int bytemode, int sizeflag)
15169 {
15170   /* Skip mod/rm byte.  */
15171   MODRM_CHECK;
15172   codep++;
15173   OP_E_register (bytemode, sizeflag);
15174 }
15175
15176 static void
15177 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15178 {
15179   int reg = modrm.reg;
15180   const char **names;
15181
15182   used_prefixes |= (prefixes & PREFIX_DATA);
15183   if (prefixes & PREFIX_DATA)
15184     {
15185       names = names_xmm;
15186       USED_REX (REX_R);
15187       if (rex & REX_R)
15188         reg += 8;
15189     }
15190   else
15191     names = names_mm;
15192   oappend (names[reg]);
15193 }
15194
15195 static void
15196 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15197 {
15198   int reg = modrm.reg;
15199   const char **names;
15200
15201   USED_REX (REX_R);
15202   if (rex & REX_R)
15203     reg += 8;
15204   if (vex.evex)
15205     {
15206       if (!vex.r)
15207         reg += 16;
15208     }
15209
15210   if (need_vex
15211       && bytemode != xmm_mode
15212       && bytemode != xmmq_mode
15213       && bytemode != evex_half_bcst_xmmq_mode
15214       && bytemode != ymm_mode
15215       && bytemode != scalar_mode)
15216     {
15217       switch (vex.length)
15218         {
15219         case 128:
15220           names = names_xmm;
15221           break;
15222         case 256:
15223           if (vex.w
15224               || (bytemode != vex_vsib_q_w_dq_mode
15225                   && bytemode != vex_vsib_q_w_d_mode))
15226             names = names_ymm;
15227           else
15228             names = names_xmm;
15229           break;
15230         case 512:
15231           names = names_zmm;
15232           break;
15233         default:
15234           abort ();
15235         }
15236     }
15237   else if (bytemode == xmmq_mode
15238            || bytemode == evex_half_bcst_xmmq_mode)
15239     {
15240       switch (vex.length)
15241         {
15242         case 128:
15243         case 256:
15244           names = names_xmm;
15245           break;
15246         case 512:
15247           names = names_ymm;
15248           break;
15249         default:
15250           abort ();
15251         }
15252     }
15253   else if (bytemode == ymm_mode)
15254     names = names_ymm;
15255   else
15256     names = names_xmm;
15257   oappend (names[reg]);
15258 }
15259
15260 static void
15261 OP_EM (int bytemode, int sizeflag)
15262 {
15263   int reg;
15264   const char **names;
15265
15266   if (modrm.mod != 3)
15267     {
15268       if (intel_syntax
15269           && (bytemode == v_mode || bytemode == v_swap_mode))
15270         {
15271           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15272           used_prefixes |= (prefixes & PREFIX_DATA);
15273         }
15274       OP_E (bytemode, sizeflag);
15275       return;
15276     }
15277
15278   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15279     swap_operand ();
15280
15281   /* Skip mod/rm byte.  */
15282   MODRM_CHECK;
15283   codep++;
15284   used_prefixes |= (prefixes & PREFIX_DATA);
15285   reg = modrm.rm;
15286   if (prefixes & PREFIX_DATA)
15287     {
15288       names = names_xmm;
15289       USED_REX (REX_B);
15290       if (rex & REX_B)
15291         reg += 8;
15292     }
15293   else
15294     names = names_mm;
15295   oappend (names[reg]);
15296 }
15297
15298 /* cvt* are the only instructions in sse2 which have
15299    both SSE and MMX operands and also have 0x66 prefix
15300    in their opcode. 0x66 was originally used to differentiate
15301    between SSE and MMX instruction(operands). So we have to handle the
15302    cvt* separately using OP_EMC and OP_MXC */
15303 static void
15304 OP_EMC (int bytemode, int sizeflag)
15305 {
15306   if (modrm.mod != 3)
15307     {
15308       if (intel_syntax && bytemode == v_mode)
15309         {
15310           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15311           used_prefixes |= (prefixes & PREFIX_DATA);
15312         }
15313       OP_E (bytemode, sizeflag);
15314       return;
15315     }
15316
15317   /* Skip mod/rm byte.  */
15318   MODRM_CHECK;
15319   codep++;
15320   used_prefixes |= (prefixes & PREFIX_DATA);
15321   oappend (names_mm[modrm.rm]);
15322 }
15323
15324 static void
15325 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15326 {
15327   used_prefixes |= (prefixes & PREFIX_DATA);
15328   oappend (names_mm[modrm.reg]);
15329 }
15330
15331 static void
15332 OP_EX (int bytemode, int sizeflag)
15333 {
15334   int reg;
15335   const char **names;
15336
15337   /* Skip mod/rm byte.  */
15338   MODRM_CHECK;
15339   codep++;
15340
15341   if (modrm.mod != 3)
15342     {
15343       OP_E_memory (bytemode, sizeflag);
15344       return;
15345     }
15346
15347   reg = modrm.rm;
15348   USED_REX (REX_B);
15349   if (rex & REX_B)
15350     reg += 8;
15351   if (vex.evex)
15352     {
15353       USED_REX (REX_X);
15354       if ((rex & REX_X))
15355         reg += 16;
15356     }
15357
15358   if ((sizeflag & SUFFIX_ALWAYS)
15359       && (bytemode == x_swap_mode
15360           || bytemode == d_swap_mode
15361           || bytemode == d_scalar_swap_mode
15362           || bytemode == q_swap_mode
15363           || bytemode == q_scalar_swap_mode))
15364     swap_operand ();
15365
15366   if (need_vex
15367       && bytemode != xmm_mode
15368       && bytemode != xmmdw_mode
15369       && bytemode != xmmqd_mode
15370       && bytemode != xmm_mb_mode
15371       && bytemode != xmm_mw_mode
15372       && bytemode != xmm_md_mode
15373       && bytemode != xmm_mq_mode
15374       && bytemode != xmm_mdq_mode
15375       && bytemode != xmmq_mode
15376       && bytemode != evex_half_bcst_xmmq_mode
15377       && bytemode != ymm_mode
15378       && bytemode != d_scalar_mode
15379       && bytemode != d_scalar_swap_mode
15380       && bytemode != q_scalar_mode
15381       && bytemode != q_scalar_swap_mode
15382       && bytemode != vex_scalar_w_dq_mode)
15383     {
15384       switch (vex.length)
15385         {
15386         case 128:
15387           names = names_xmm;
15388           break;
15389         case 256:
15390           names = names_ymm;
15391           break;
15392         case 512:
15393           names = names_zmm;
15394           break;
15395         default:
15396           abort ();
15397         }
15398     }
15399   else if (bytemode == xmmq_mode
15400            || bytemode == evex_half_bcst_xmmq_mode)
15401     {
15402       switch (vex.length)
15403         {
15404         case 128:
15405         case 256:
15406           names = names_xmm;
15407           break;
15408         case 512:
15409           names = names_ymm;
15410           break;
15411         default:
15412           abort ();
15413         }
15414     }
15415   else if (bytemode == ymm_mode)
15416     names = names_ymm;
15417   else
15418     names = names_xmm;
15419   oappend (names[reg]);
15420 }
15421
15422 static void
15423 OP_MS (int bytemode, int sizeflag)
15424 {
15425   if (modrm.mod == 3)
15426     OP_EM (bytemode, sizeflag);
15427   else
15428     BadOp ();
15429 }
15430
15431 static void
15432 OP_XS (int bytemode, int sizeflag)
15433 {
15434   if (modrm.mod == 3)
15435     OP_EX (bytemode, sizeflag);
15436   else
15437     BadOp ();
15438 }
15439
15440 static void
15441 OP_M (int bytemode, int sizeflag)
15442 {
15443   if (modrm.mod == 3)
15444     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15445     BadOp ();
15446   else
15447     OP_E (bytemode, sizeflag);
15448 }
15449
15450 static void
15451 OP_0f07 (int bytemode, int sizeflag)
15452 {
15453   if (modrm.mod != 3 || modrm.rm != 0)
15454     BadOp ();
15455   else
15456     OP_E (bytemode, sizeflag);
15457 }
15458
15459 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15460    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15461
15462 static void
15463 NOP_Fixup1 (int bytemode, int sizeflag)
15464 {
15465   if ((prefixes & PREFIX_DATA) != 0
15466       || (rex != 0
15467           && rex != 0x48
15468           && address_mode == mode_64bit))
15469     OP_REG (bytemode, sizeflag);
15470   else
15471     strcpy (obuf, "nop");
15472 }
15473
15474 static void
15475 NOP_Fixup2 (int bytemode, int sizeflag)
15476 {
15477   if ((prefixes & PREFIX_DATA) != 0
15478       || (rex != 0
15479           && rex != 0x48
15480           && address_mode == mode_64bit))
15481     OP_IMREG (bytemode, sizeflag);
15482 }
15483
15484 static const char *const Suffix3DNow[] = {
15485 /* 00 */        NULL,           NULL,           NULL,           NULL,
15486 /* 04 */        NULL,           NULL,           NULL,           NULL,
15487 /* 08 */        NULL,           NULL,           NULL,           NULL,
15488 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15489 /* 10 */        NULL,           NULL,           NULL,           NULL,
15490 /* 14 */        NULL,           NULL,           NULL,           NULL,
15491 /* 18 */        NULL,           NULL,           NULL,           NULL,
15492 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15493 /* 20 */        NULL,           NULL,           NULL,           NULL,
15494 /* 24 */        NULL,           NULL,           NULL,           NULL,
15495 /* 28 */        NULL,           NULL,           NULL,           NULL,
15496 /* 2C */        NULL,           NULL,           NULL,           NULL,
15497 /* 30 */        NULL,           NULL,           NULL,           NULL,
15498 /* 34 */        NULL,           NULL,           NULL,           NULL,
15499 /* 38 */        NULL,           NULL,           NULL,           NULL,
15500 /* 3C */        NULL,           NULL,           NULL,           NULL,
15501 /* 40 */        NULL,           NULL,           NULL,           NULL,
15502 /* 44 */        NULL,           NULL,           NULL,           NULL,
15503 /* 48 */        NULL,           NULL,           NULL,           NULL,
15504 /* 4C */        NULL,           NULL,           NULL,           NULL,
15505 /* 50 */        NULL,           NULL,           NULL,           NULL,
15506 /* 54 */        NULL,           NULL,           NULL,           NULL,
15507 /* 58 */        NULL,           NULL,           NULL,           NULL,
15508 /* 5C */        NULL,           NULL,           NULL,           NULL,
15509 /* 60 */        NULL,           NULL,           NULL,           NULL,
15510 /* 64 */        NULL,           NULL,           NULL,           NULL,
15511 /* 68 */        NULL,           NULL,           NULL,           NULL,
15512 /* 6C */        NULL,           NULL,           NULL,           NULL,
15513 /* 70 */        NULL,           NULL,           NULL,           NULL,
15514 /* 74 */        NULL,           NULL,           NULL,           NULL,
15515 /* 78 */        NULL,           NULL,           NULL,           NULL,
15516 /* 7C */        NULL,           NULL,           NULL,           NULL,
15517 /* 80 */        NULL,           NULL,           NULL,           NULL,
15518 /* 84 */        NULL,           NULL,           NULL,           NULL,
15519 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15520 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15521 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15522 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15523 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15524 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15525 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15526 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15527 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15528 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15529 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15530 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15531 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15532 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15533 /* C0 */        NULL,           NULL,           NULL,           NULL,
15534 /* C4 */        NULL,           NULL,           NULL,           NULL,
15535 /* C8 */        NULL,           NULL,           NULL,           NULL,
15536 /* CC */        NULL,           NULL,           NULL,           NULL,
15537 /* D0 */        NULL,           NULL,           NULL,           NULL,
15538 /* D4 */        NULL,           NULL,           NULL,           NULL,
15539 /* D8 */        NULL,           NULL,           NULL,           NULL,
15540 /* DC */        NULL,           NULL,           NULL,           NULL,
15541 /* E0 */        NULL,           NULL,           NULL,           NULL,
15542 /* E4 */        NULL,           NULL,           NULL,           NULL,
15543 /* E8 */        NULL,           NULL,           NULL,           NULL,
15544 /* EC */        NULL,           NULL,           NULL,           NULL,
15545 /* F0 */        NULL,           NULL,           NULL,           NULL,
15546 /* F4 */        NULL,           NULL,           NULL,           NULL,
15547 /* F8 */        NULL,           NULL,           NULL,           NULL,
15548 /* FC */        NULL,           NULL,           NULL,           NULL,
15549 };
15550
15551 static void
15552 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15553 {
15554   const char *mnemonic;
15555
15556   FETCH_DATA (the_info, codep + 1);
15557   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15558      place where an 8-bit immediate would normally go.  ie. the last
15559      byte of the instruction.  */
15560   obufp = mnemonicendp;
15561   mnemonic = Suffix3DNow[*codep++ & 0xff];
15562   if (mnemonic)
15563     oappend (mnemonic);
15564   else
15565     {
15566       /* Since a variable sized modrm/sib chunk is between the start
15567          of the opcode (0x0f0f) and the opcode suffix, we need to do
15568          all the modrm processing first, and don't know until now that
15569          we have a bad opcode.  This necessitates some cleaning up.  */
15570       op_out[0][0] = '\0';
15571       op_out[1][0] = '\0';
15572       BadOp ();
15573     }
15574   mnemonicendp = obufp;
15575 }
15576
15577 static struct op simd_cmp_op[] =
15578 {
15579   { STRING_COMMA_LEN ("eq") },
15580   { STRING_COMMA_LEN ("lt") },
15581   { STRING_COMMA_LEN ("le") },
15582   { STRING_COMMA_LEN ("unord") },
15583   { STRING_COMMA_LEN ("neq") },
15584   { STRING_COMMA_LEN ("nlt") },
15585   { STRING_COMMA_LEN ("nle") },
15586   { STRING_COMMA_LEN ("ord") }
15587 };
15588
15589 static void
15590 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15591 {
15592   unsigned int cmp_type;
15593
15594   FETCH_DATA (the_info, codep + 1);
15595   cmp_type = *codep++ & 0xff;
15596   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15597     {
15598       char suffix [3];
15599       char *p = mnemonicendp - 2;
15600       suffix[0] = p[0];
15601       suffix[1] = p[1];
15602       suffix[2] = '\0';
15603       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15604       mnemonicendp += simd_cmp_op[cmp_type].len;
15605     }
15606   else
15607     {
15608       /* We have a reserved extension byte.  Output it directly.  */
15609       scratchbuf[0] = '$';
15610       print_operand_value (scratchbuf + 1, 1, cmp_type);
15611       oappend_maybe_intel (scratchbuf);
15612       scratchbuf[0] = '\0';
15613     }
15614 }
15615
15616 static void
15617 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15618 {
15619   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15620   if (!intel_syntax)
15621     {
15622       strcpy (op_out[0], names32[0]);
15623       strcpy (op_out[1], names32[1]);
15624       if (bytemode == eBX_reg)
15625         strcpy (op_out[2], names32[3]);
15626       two_source_ops = 1;
15627     }
15628   /* Skip mod/rm byte.  */
15629   MODRM_CHECK;
15630   codep++;
15631 }
15632
15633 static void
15634 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15635             int sizeflag ATTRIBUTE_UNUSED)
15636 {
15637   /* monitor %{e,r,}ax,%ecx,%edx"  */
15638   if (!intel_syntax)
15639     {
15640       const char **names = (address_mode == mode_64bit
15641                             ? names64 : names32);
15642
15643       if (prefixes & PREFIX_ADDR)
15644         {
15645           /* Remove "addr16/addr32".  */
15646           all_prefixes[last_addr_prefix] = 0;
15647           names = (address_mode != mode_32bit
15648                    ? names32 : names16);
15649           used_prefixes |= PREFIX_ADDR;
15650         }
15651       else if (address_mode == mode_16bit)
15652         names = names16;
15653       strcpy (op_out[0], names[0]);
15654       strcpy (op_out[1], names32[1]);
15655       strcpy (op_out[2], names32[2]);
15656       two_source_ops = 1;
15657     }
15658   /* Skip mod/rm byte.  */
15659   MODRM_CHECK;
15660   codep++;
15661 }
15662
15663 static void
15664 BadOp (void)
15665 {
15666   /* Throw away prefixes and 1st. opcode byte.  */
15667   codep = insn_codep + 1;
15668   oappend ("(bad)");
15669 }
15670
15671 static void
15672 REP_Fixup (int bytemode, int sizeflag)
15673 {
15674   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15675      lods and stos.  */
15676   if (prefixes & PREFIX_REPZ)
15677     all_prefixes[last_repz_prefix] = REP_PREFIX;
15678
15679   switch (bytemode)
15680     {
15681     case al_reg:
15682     case eAX_reg:
15683     case indir_dx_reg:
15684       OP_IMREG (bytemode, sizeflag);
15685       break;
15686     case eDI_reg:
15687       OP_ESreg (bytemode, sizeflag);
15688       break;
15689     case eSI_reg:
15690       OP_DSreg (bytemode, sizeflag);
15691       break;
15692     default:
15693       abort ();
15694       break;
15695     }
15696 }
15697
15698 static void
15699 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15700 {
15701   if ( isa64 != amd64 )
15702     return;
15703
15704   obufp = obuf;
15705   BadOp ();
15706   mnemonicendp = obufp;
15707   ++codep;
15708 }
15709
15710 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15711    "bnd".  */
15712
15713 static void
15714 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15715 {
15716   if (prefixes & PREFIX_REPNZ)
15717     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15718 }
15719
15720 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15721    "notrack".  */
15722
15723 static void
15724 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15725                int sizeflag ATTRIBUTE_UNUSED)
15726 {
15727   if (active_seg_prefix == PREFIX_DS
15728       && (address_mode != mode_64bit || last_data_prefix < 0))
15729     {
15730       /* NOTRACK prefix is only valid on indirect branch instructions.
15731          NB: DATA prefix is unsupported for Intel64.  */
15732       active_seg_prefix = 0;
15733       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15734     }
15735 }
15736
15737 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15738    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15739  */
15740
15741 static void
15742 HLE_Fixup1 (int bytemode, int sizeflag)
15743 {
15744   if (modrm.mod != 3
15745       && (prefixes & PREFIX_LOCK) != 0)
15746     {
15747       if (prefixes & PREFIX_REPZ)
15748         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15749       if (prefixes & PREFIX_REPNZ)
15750         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15751     }
15752
15753   OP_E (bytemode, sizeflag);
15754 }
15755
15756 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15757    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15758  */
15759
15760 static void
15761 HLE_Fixup2 (int bytemode, int sizeflag)
15762 {
15763   if (modrm.mod != 3)
15764     {
15765       if (prefixes & PREFIX_REPZ)
15766         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15767       if (prefixes & PREFIX_REPNZ)
15768         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15769     }
15770
15771   OP_E (bytemode, sizeflag);
15772 }
15773
15774 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15775    "xrelease" for memory operand.  No check for LOCK prefix.   */
15776
15777 static void
15778 HLE_Fixup3 (int bytemode, int sizeflag)
15779 {
15780   if (modrm.mod != 3
15781       && last_repz_prefix > last_repnz_prefix
15782       && (prefixes & PREFIX_REPZ) != 0)
15783     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15784
15785   OP_E (bytemode, sizeflag);
15786 }
15787
15788 static void
15789 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15790 {
15791   USED_REX (REX_W);
15792   if (rex & REX_W)
15793     {
15794       /* Change cmpxchg8b to cmpxchg16b.  */
15795       char *p = mnemonicendp - 2;
15796       mnemonicendp = stpcpy (p, "16b");
15797       bytemode = o_mode;
15798     }
15799   else if ((prefixes & PREFIX_LOCK) != 0)
15800     {
15801       if (prefixes & PREFIX_REPZ)
15802         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15803       if (prefixes & PREFIX_REPNZ)
15804         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15805     }
15806
15807   OP_M (bytemode, sizeflag);
15808 }
15809
15810 static void
15811 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15812 {
15813   const char **names;
15814
15815   if (need_vex)
15816     {
15817       switch (vex.length)
15818         {
15819         case 128:
15820           names = names_xmm;
15821           break;
15822         case 256:
15823           names = names_ymm;
15824           break;
15825         default:
15826           abort ();
15827         }
15828     }
15829   else
15830     names = names_xmm;
15831   oappend (names[reg]);
15832 }
15833
15834 static void
15835 CRC32_Fixup (int bytemode, int sizeflag)
15836 {
15837   /* Add proper suffix to "crc32".  */
15838   char *p = mnemonicendp;
15839
15840   switch (bytemode)
15841     {
15842     case b_mode:
15843       if (intel_syntax)
15844         goto skip;
15845
15846       *p++ = 'b';
15847       break;
15848     case v_mode:
15849       if (intel_syntax)
15850         goto skip;
15851
15852       USED_REX (REX_W);
15853       if (rex & REX_W)
15854         *p++ = 'q';
15855       else
15856         {
15857           if (sizeflag & DFLAG)
15858             *p++ = 'l';
15859           else
15860             *p++ = 'w';
15861           used_prefixes |= (prefixes & PREFIX_DATA);
15862         }
15863       break;
15864     default:
15865       oappend (INTERNAL_DISASSEMBLER_ERROR);
15866       break;
15867     }
15868   mnemonicendp = p;
15869   *p = '\0';
15870
15871 skip:
15872   if (modrm.mod == 3)
15873     {
15874       int add;
15875
15876       /* Skip mod/rm byte.  */
15877       MODRM_CHECK;
15878       codep++;
15879
15880       USED_REX (REX_B);
15881       add = (rex & REX_B) ? 8 : 0;
15882       if (bytemode == b_mode)
15883         {
15884           USED_REX (0);
15885           if (rex)
15886             oappend (names8rex[modrm.rm + add]);
15887           else
15888             oappend (names8[modrm.rm + add]);
15889         }
15890       else
15891         {
15892           USED_REX (REX_W);
15893           if (rex & REX_W)
15894             oappend (names64[modrm.rm + add]);
15895           else if ((prefixes & PREFIX_DATA))
15896             oappend (names16[modrm.rm + add]);
15897           else
15898             oappend (names32[modrm.rm + add]);
15899         }
15900     }
15901   else
15902     OP_E (bytemode, sizeflag);
15903 }
15904
15905 static void
15906 FXSAVE_Fixup (int bytemode, int sizeflag)
15907 {
15908   /* Add proper suffix to "fxsave" and "fxrstor".  */
15909   USED_REX (REX_W);
15910   if (rex & REX_W)
15911     {
15912       char *p = mnemonicendp;
15913       *p++ = '6';
15914       *p++ = '4';
15915       *p = '\0';
15916       mnemonicendp = p;
15917     }
15918   OP_M (bytemode, sizeflag);
15919 }
15920
15921 static void
15922 PCMPESTR_Fixup (int bytemode, int sizeflag)
15923 {
15924   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15925   if (!intel_syntax)
15926     {
15927       char *p = mnemonicendp;
15928
15929       USED_REX (REX_W);
15930       if (rex & REX_W)
15931         *p++ = 'q';
15932       else if (sizeflag & SUFFIX_ALWAYS)
15933         *p++ = 'l';
15934
15935       *p = '\0';
15936       mnemonicendp = p;
15937     }
15938
15939   OP_EX (bytemode, sizeflag);
15940 }
15941
15942 /* Display the destination register operand for instructions with
15943    VEX. */
15944
15945 static void
15946 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15947 {
15948   int reg;
15949   const char **names;
15950
15951   if (!need_vex)
15952     abort ();
15953
15954   if (!need_vex_reg)
15955     return;
15956
15957   reg = vex.register_specifier;
15958   vex.register_specifier = 0;
15959   if (address_mode != mode_64bit)
15960     reg &= 7;
15961   else if (vex.evex && !vex.v)
15962     reg += 16;
15963
15964   if (bytemode == vex_scalar_mode)
15965     {
15966       oappend (names_xmm[reg]);
15967       return;
15968     }
15969
15970   switch (vex.length)
15971     {
15972     case 128:
15973       switch (bytemode)
15974         {
15975         case vex_mode:
15976         case vex128_mode:
15977         case vex_vsib_q_w_dq_mode:
15978         case vex_vsib_q_w_d_mode:
15979           names = names_xmm;
15980           break;
15981         case dq_mode:
15982           if (rex & REX_W)
15983             names = names64;
15984           else
15985             names = names32;
15986           break;
15987         case mask_bd_mode:
15988         case mask_mode:
15989           if (reg > 0x7)
15990             {
15991               oappend ("(bad)");
15992               return;
15993             }
15994           names = names_mask;
15995           break;
15996         default:
15997           abort ();
15998           return;
15999         }
16000       break;
16001     case 256:
16002       switch (bytemode)
16003         {
16004         case vex_mode:
16005         case vex256_mode:
16006           names = names_ymm;
16007           break;
16008         case vex_vsib_q_w_dq_mode:
16009         case vex_vsib_q_w_d_mode:
16010           names = vex.w ? names_ymm : names_xmm;
16011           break;
16012         case mask_bd_mode:
16013         case mask_mode:
16014           if (reg > 0x7)
16015             {
16016               oappend ("(bad)");
16017               return;
16018             }
16019           names = names_mask;
16020           break;
16021         default:
16022           /* See PR binutils/20893 for a reproducer.  */
16023           oappend ("(bad)");
16024           return;
16025         }
16026       break;
16027     case 512:
16028       names = names_zmm;
16029       break;
16030     default:
16031       abort ();
16032       break;
16033     }
16034   oappend (names[reg]);
16035 }
16036
16037 /* Get the VEX immediate byte without moving codep.  */
16038
16039 static unsigned char
16040 get_vex_imm8 (int sizeflag, int opnum)
16041 {
16042   int bytes_before_imm = 0;
16043
16044   if (modrm.mod != 3)
16045     {
16046       /* There are SIB/displacement bytes.  */
16047       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16048         {
16049           /* 32/64 bit address mode */
16050           int base = modrm.rm;
16051
16052           /* Check SIB byte.  */
16053           if (base == 4)
16054             {
16055               FETCH_DATA (the_info, codep + 1);
16056               base = *codep & 7;
16057               /* When decoding the third source, don't increase
16058                  bytes_before_imm as this has already been incremented
16059                  by one in OP_E_memory while decoding the second
16060                  source operand.  */
16061               if (opnum == 0)
16062                 bytes_before_imm++;
16063             }
16064
16065           /* Don't increase bytes_before_imm when decoding the third source,
16066              it has already been incremented by OP_E_memory while decoding
16067              the second source operand.  */
16068           if (opnum == 0)
16069             {
16070               switch (modrm.mod)
16071                 {
16072                   case 0:
16073                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16074                        SIB == 5, there is a 4 byte displacement.  */
16075                     if (base != 5)
16076                       /* No displacement. */
16077                       break;
16078                     /* Fall through.  */
16079                   case 2:
16080                     /* 4 byte displacement.  */
16081                     bytes_before_imm += 4;
16082                     break;
16083                   case 1:
16084                     /* 1 byte displacement.  */
16085                     bytes_before_imm++;
16086                     break;
16087                 }
16088             }
16089         }
16090       else
16091         {
16092           /* 16 bit address mode */
16093           /* Don't increase bytes_before_imm when decoding the third source,
16094              it has already been incremented by OP_E_memory while decoding
16095              the second source operand.  */
16096           if (opnum == 0)
16097             {
16098               switch (modrm.mod)
16099                 {
16100                 case 0:
16101                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16102                   if (modrm.rm != 6)
16103                     /* No displacement. */
16104                     break;
16105                   /* Fall through.  */
16106                 case 2:
16107                   /* 2 byte displacement.  */
16108                   bytes_before_imm += 2;
16109                   break;
16110                 case 1:
16111                   /* 1 byte displacement: when decoding the third source,
16112                      don't increase bytes_before_imm as this has already
16113                      been incremented by one in OP_E_memory while decoding
16114                      the second source operand.  */
16115                   if (opnum == 0)
16116                     bytes_before_imm++;
16117
16118                   break;
16119                 }
16120             }
16121         }
16122     }
16123
16124   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16125   return codep [bytes_before_imm];
16126 }
16127
16128 static void
16129 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16130 {
16131   const char **names;
16132
16133   if (reg == -1 && modrm.mod != 3)
16134     {
16135       OP_E_memory (bytemode, sizeflag);
16136       return;
16137     }
16138   else
16139     {
16140       if (reg == -1)
16141         {
16142           reg = modrm.rm;
16143           USED_REX (REX_B);
16144           if (rex & REX_B)
16145             reg += 8;
16146         }
16147       if (address_mode != mode_64bit)
16148         reg &= 7;
16149     }
16150
16151   switch (vex.length)
16152     {
16153     case 128:
16154       names = names_xmm;
16155       break;
16156     case 256:
16157       names = names_ymm;
16158       break;
16159     default:
16160       abort ();
16161     }
16162   oappend (names[reg]);
16163 }
16164
16165 static void
16166 OP_EX_VexImmW (int bytemode, int sizeflag)
16167 {
16168   int reg = -1;
16169   static unsigned char vex_imm8;
16170
16171   if (vex_w_done == 0)
16172     {
16173       vex_w_done = 1;
16174
16175       /* Skip mod/rm byte.  */
16176       MODRM_CHECK;
16177       codep++;
16178
16179       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16180
16181       if (vex.w)
16182           reg = vex_imm8 >> 4;
16183
16184       OP_EX_VexReg (bytemode, sizeflag, reg);
16185     }
16186   else if (vex_w_done == 1)
16187     {
16188       vex_w_done = 2;
16189
16190       if (!vex.w)
16191           reg = vex_imm8 >> 4;
16192
16193       OP_EX_VexReg (bytemode, sizeflag, reg);
16194     }
16195   else
16196     {
16197       /* Output the imm8 directly.  */
16198       scratchbuf[0] = '$';
16199       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16200       oappend_maybe_intel (scratchbuf);
16201       scratchbuf[0] = '\0';
16202       codep++;
16203     }
16204 }
16205
16206 static void
16207 OP_Vex_2src (int bytemode, int sizeflag)
16208 {
16209   if (modrm.mod == 3)
16210     {
16211       int reg = modrm.rm;
16212       USED_REX (REX_B);
16213       if (rex & REX_B)
16214         reg += 8;
16215       oappend (names_xmm[reg]);
16216     }
16217   else
16218     {
16219       if (intel_syntax
16220           && (bytemode == v_mode || bytemode == v_swap_mode))
16221         {
16222           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16223           used_prefixes |= (prefixes & PREFIX_DATA);
16224         }
16225       OP_E (bytemode, sizeflag);
16226     }
16227 }
16228
16229 static void
16230 OP_Vex_2src_1 (int bytemode, int sizeflag)
16231 {
16232   if (modrm.mod == 3)
16233     {
16234       /* Skip mod/rm byte.   */
16235       MODRM_CHECK;
16236       codep++;
16237     }
16238
16239   if (vex.w)
16240     {
16241       unsigned int reg = vex.register_specifier;
16242       vex.register_specifier = 0;
16243
16244       if (address_mode != mode_64bit)
16245         reg &= 7;
16246       oappend (names_xmm[reg]);
16247     }
16248   else
16249     OP_Vex_2src (bytemode, sizeflag);
16250 }
16251
16252 static void
16253 OP_Vex_2src_2 (int bytemode, int sizeflag)
16254 {
16255   if (vex.w)
16256     OP_Vex_2src (bytemode, sizeflag);
16257   else
16258     {
16259       unsigned int reg = vex.register_specifier;
16260       vex.register_specifier = 0;
16261
16262       if (address_mode != mode_64bit)
16263         reg &= 7;
16264       oappend (names_xmm[reg]);
16265     }
16266 }
16267
16268 static void
16269 OP_EX_VexW (int bytemode, int sizeflag)
16270 {
16271   int reg = -1;
16272
16273   if (!vex_w_done)
16274     {
16275       /* Skip mod/rm byte.  */
16276       MODRM_CHECK;
16277       codep++;
16278
16279       if (vex.w)
16280         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16281     }
16282   else
16283     {
16284       if (!vex.w)
16285         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16286     }
16287
16288   OP_EX_VexReg (bytemode, sizeflag, reg);
16289
16290   if (vex_w_done)
16291     codep++;
16292   vex_w_done = 1;
16293 }
16294
16295 static void
16296 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16297 {
16298   int reg;
16299   const char **names;
16300
16301   FETCH_DATA (the_info, codep + 1);
16302   reg = *codep++;
16303
16304   if (bytemode != x_mode)
16305     abort ();
16306
16307   reg >>= 4;
16308   if (address_mode != mode_64bit)
16309     reg &= 7;
16310
16311   switch (vex.length)
16312     {
16313     case 128:
16314       names = names_xmm;
16315       break;
16316     case 256:
16317       names = names_ymm;
16318       break;
16319     default:
16320       abort ();
16321     }
16322   oappend (names[reg]);
16323 }
16324
16325 static void
16326 OP_XMM_VexW (int bytemode, int sizeflag)
16327 {
16328   /* Turn off the REX.W bit since it is used for swapping operands
16329      now.  */
16330   rex &= ~REX_W;
16331   OP_XMM (bytemode, sizeflag);
16332 }
16333
16334 static void
16335 OP_EX_Vex (int bytemode, int sizeflag)
16336 {
16337   if (modrm.mod != 3)
16338     need_vex_reg = 0;
16339   OP_EX (bytemode, sizeflag);
16340 }
16341
16342 static void
16343 OP_XMM_Vex (int bytemode, int sizeflag)
16344 {
16345   if (modrm.mod != 3)
16346     need_vex_reg = 0;
16347   OP_XMM (bytemode, sizeflag);
16348 }
16349
16350 static struct op vex_cmp_op[] =
16351 {
16352   { STRING_COMMA_LEN ("eq") },
16353   { STRING_COMMA_LEN ("lt") },
16354   { STRING_COMMA_LEN ("le") },
16355   { STRING_COMMA_LEN ("unord") },
16356   { STRING_COMMA_LEN ("neq") },
16357   { STRING_COMMA_LEN ("nlt") },
16358   { STRING_COMMA_LEN ("nle") },
16359   { STRING_COMMA_LEN ("ord") },
16360   { STRING_COMMA_LEN ("eq_uq") },
16361   { STRING_COMMA_LEN ("nge") },
16362   { STRING_COMMA_LEN ("ngt") },
16363   { STRING_COMMA_LEN ("false") },
16364   { STRING_COMMA_LEN ("neq_oq") },
16365   { STRING_COMMA_LEN ("ge") },
16366   { STRING_COMMA_LEN ("gt") },
16367   { STRING_COMMA_LEN ("true") },
16368   { STRING_COMMA_LEN ("eq_os") },
16369   { STRING_COMMA_LEN ("lt_oq") },
16370   { STRING_COMMA_LEN ("le_oq") },
16371   { STRING_COMMA_LEN ("unord_s") },
16372   { STRING_COMMA_LEN ("neq_us") },
16373   { STRING_COMMA_LEN ("nlt_uq") },
16374   { STRING_COMMA_LEN ("nle_uq") },
16375   { STRING_COMMA_LEN ("ord_s") },
16376   { STRING_COMMA_LEN ("eq_us") },
16377   { STRING_COMMA_LEN ("nge_uq") },
16378   { STRING_COMMA_LEN ("ngt_uq") },
16379   { STRING_COMMA_LEN ("false_os") },
16380   { STRING_COMMA_LEN ("neq_os") },
16381   { STRING_COMMA_LEN ("ge_oq") },
16382   { STRING_COMMA_LEN ("gt_oq") },
16383   { STRING_COMMA_LEN ("true_us") },
16384 };
16385
16386 static void
16387 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16388 {
16389   unsigned int cmp_type;
16390
16391   FETCH_DATA (the_info, codep + 1);
16392   cmp_type = *codep++ & 0xff;
16393   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16394     {
16395       char suffix [3];
16396       char *p = mnemonicendp - 2;
16397       suffix[0] = p[0];
16398       suffix[1] = p[1];
16399       suffix[2] = '\0';
16400       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16401       mnemonicendp += vex_cmp_op[cmp_type].len;
16402     }
16403   else
16404     {
16405       /* We have a reserved extension byte.  Output it directly.  */
16406       scratchbuf[0] = '$';
16407       print_operand_value (scratchbuf + 1, 1, cmp_type);
16408       oappend_maybe_intel (scratchbuf);
16409       scratchbuf[0] = '\0';
16410     }
16411 }
16412
16413 static void
16414 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16415              int sizeflag ATTRIBUTE_UNUSED)
16416 {
16417   unsigned int cmp_type;
16418
16419   if (!vex.evex)
16420     abort ();
16421
16422   FETCH_DATA (the_info, codep + 1);
16423   cmp_type = *codep++ & 0xff;
16424   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16425      If it's the case, print suffix, otherwise - print the immediate.  */
16426   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16427       && cmp_type != 3
16428       && cmp_type != 7)
16429     {
16430       char suffix [3];
16431       char *p = mnemonicendp - 2;
16432
16433       /* vpcmp* can have both one- and two-lettered suffix.  */
16434       if (p[0] == 'p')
16435         {
16436           p++;
16437           suffix[0] = p[0];
16438           suffix[1] = '\0';
16439         }
16440       else
16441         {
16442           suffix[0] = p[0];
16443           suffix[1] = p[1];
16444           suffix[2] = '\0';
16445         }
16446
16447       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16448       mnemonicendp += simd_cmp_op[cmp_type].len;
16449     }
16450   else
16451     {
16452       /* We have a reserved extension byte.  Output it directly.  */
16453       scratchbuf[0] = '$';
16454       print_operand_value (scratchbuf + 1, 1, cmp_type);
16455       oappend_maybe_intel (scratchbuf);
16456       scratchbuf[0] = '\0';
16457     }
16458 }
16459
16460 static const struct op xop_cmp_op[] =
16461 {
16462   { STRING_COMMA_LEN ("lt") },
16463   { STRING_COMMA_LEN ("le") },
16464   { STRING_COMMA_LEN ("gt") },
16465   { STRING_COMMA_LEN ("ge") },
16466   { STRING_COMMA_LEN ("eq") },
16467   { STRING_COMMA_LEN ("neq") },
16468   { STRING_COMMA_LEN ("false") },
16469   { STRING_COMMA_LEN ("true") }
16470 };
16471
16472 static void
16473 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16474              int sizeflag ATTRIBUTE_UNUSED)
16475 {
16476   unsigned int cmp_type;
16477
16478   FETCH_DATA (the_info, codep + 1);
16479   cmp_type = *codep++ & 0xff;
16480   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16481     {
16482       char suffix[3];
16483       char *p = mnemonicendp - 2;
16484
16485       /* vpcom* can have both one- and two-lettered suffix.  */
16486       if (p[0] == 'm')
16487         {
16488           p++;
16489           suffix[0] = p[0];
16490           suffix[1] = '\0';
16491         }
16492       else
16493         {
16494           suffix[0] = p[0];
16495           suffix[1] = p[1];
16496           suffix[2] = '\0';
16497         }
16498
16499       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16500       mnemonicendp += xop_cmp_op[cmp_type].len;
16501     }
16502   else
16503     {
16504       /* We have a reserved extension byte.  Output it directly.  */
16505       scratchbuf[0] = '$';
16506       print_operand_value (scratchbuf + 1, 1, cmp_type);
16507       oappend_maybe_intel (scratchbuf);
16508       scratchbuf[0] = '\0';
16509     }
16510 }
16511
16512 static const struct op pclmul_op[] =
16513 {
16514   { STRING_COMMA_LEN ("lql") },
16515   { STRING_COMMA_LEN ("hql") },
16516   { STRING_COMMA_LEN ("lqh") },
16517   { STRING_COMMA_LEN ("hqh") }
16518 };
16519
16520 static void
16521 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16522               int sizeflag ATTRIBUTE_UNUSED)
16523 {
16524   unsigned int pclmul_type;
16525
16526   FETCH_DATA (the_info, codep + 1);
16527   pclmul_type = *codep++ & 0xff;
16528   switch (pclmul_type)
16529     {
16530     case 0x10:
16531       pclmul_type = 2;
16532       break;
16533     case 0x11:
16534       pclmul_type = 3;
16535       break;
16536     default:
16537       break;
16538     }
16539   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16540     {
16541       char suffix [4];
16542       char *p = mnemonicendp - 3;
16543       suffix[0] = p[0];
16544       suffix[1] = p[1];
16545       suffix[2] = p[2];
16546       suffix[3] = '\0';
16547       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16548       mnemonicendp += pclmul_op[pclmul_type].len;
16549     }
16550   else
16551     {
16552       /* We have a reserved extension byte.  Output it directly.  */
16553       scratchbuf[0] = '$';
16554       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16555       oappend_maybe_intel (scratchbuf);
16556       scratchbuf[0] = '\0';
16557     }
16558 }
16559
16560 static void
16561 MOVBE_Fixup (int bytemode, int sizeflag)
16562 {
16563   /* Add proper suffix to "movbe".  */
16564   char *p = mnemonicendp;
16565
16566   switch (bytemode)
16567     {
16568     case v_mode:
16569       if (intel_syntax)
16570         goto skip;
16571
16572       USED_REX (REX_W);
16573       if (sizeflag & SUFFIX_ALWAYS)
16574         {
16575           if (rex & REX_W)
16576             *p++ = 'q';
16577           else
16578             {
16579               if (sizeflag & DFLAG)
16580                 *p++ = 'l';
16581               else
16582                 *p++ = 'w';
16583               used_prefixes |= (prefixes & PREFIX_DATA);
16584             }
16585         }
16586       break;
16587     default:
16588       oappend (INTERNAL_DISASSEMBLER_ERROR);
16589       break;
16590     }
16591   mnemonicendp = p;
16592   *p = '\0';
16593
16594 skip:
16595   OP_M (bytemode, sizeflag);
16596 }
16597
16598 static void
16599 MOVSXD_Fixup (int bytemode, int sizeflag)
16600 {
16601   /* Add proper suffix to "movsxd".  */
16602   char *p = mnemonicendp;
16603
16604   switch (bytemode)
16605     {
16606     case movsxd_mode:
16607       if (intel_syntax)
16608         {
16609           *p++ = 'x';
16610           *p++ = 'd';
16611           goto skip;
16612         }
16613
16614       USED_REX (REX_W);
16615       if (rex & REX_W)
16616         {
16617           *p++ = 'l';
16618           *p++ = 'q';
16619         }
16620       else
16621         {
16622           *p++ = 'x';
16623           *p++ = 'd';
16624         }
16625       break;
16626     default:
16627       oappend (INTERNAL_DISASSEMBLER_ERROR);
16628       break;
16629     }
16630
16631 skip:
16632   mnemonicendp = p;
16633   *p = '\0';
16634   OP_E (bytemode, sizeflag);
16635 }
16636
16637 static void
16638 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16639 {
16640   int reg;
16641   const char **names;
16642
16643   /* Skip mod/rm byte.  */
16644   MODRM_CHECK;
16645   codep++;
16646
16647   if (rex & REX_W)
16648     names = names64;
16649   else
16650     names = names32;
16651
16652   reg = modrm.rm;
16653   USED_REX (REX_B);
16654   if (rex & REX_B)
16655     reg += 8;
16656
16657   oappend (names[reg]);
16658 }
16659
16660 static void
16661 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16662 {
16663   const char **names;
16664   unsigned int reg = vex.register_specifier;
16665   vex.register_specifier = 0;
16666
16667   if (rex & REX_W)
16668     names = names64;
16669   else
16670     names = names32;
16671
16672   if (address_mode != mode_64bit)
16673     reg &= 7;
16674   oappend (names[reg]);
16675 }
16676
16677 static void
16678 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16679 {
16680   if (!vex.evex
16681       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16682     abort ();
16683
16684   USED_REX (REX_R);
16685   if ((rex & REX_R) != 0 || !vex.r)
16686     {
16687       BadOp ();
16688       return;
16689     }
16690
16691   oappend (names_mask [modrm.reg]);
16692 }
16693
16694 static void
16695 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16696 {
16697   if (!vex.evex
16698       || (bytemode != evex_rounding_mode
16699           && bytemode != evex_rounding_64_mode
16700           && bytemode != evex_sae_mode))
16701     abort ();
16702   if (modrm.mod == 3 && vex.b)
16703     switch (bytemode)
16704       {
16705       case evex_rounding_64_mode:
16706         if (address_mode != mode_64bit)
16707           {
16708             oappend ("(bad)");
16709             break;
16710           }
16711         /* Fall through.  */
16712       case evex_rounding_mode:
16713         oappend (names_rounding[vex.ll]);
16714         break;
16715       case evex_sae_mode:
16716         oappend ("{sae}");
16717         break;
16718       default:
16719         break;
16720       }
16721 }