1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXq { OP_EX, q_mode }
389 #define EXqScalar { OP_EX, q_scalar_mode }
390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
391 #define EXqS { OP_EX, q_swap_mode }
392 #define EXx { OP_EX, x_mode }
393 #define EXxS { OP_EX, x_swap_mode }
394 #define EXxmm { OP_EX, xmm_mode }
395 #define EXymm { OP_EX, ymm_mode }
396 #define EXxmmq { OP_EX, xmmq_mode }
397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
400 #define EXxmm_md { OP_EX, xmm_md_mode }
401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
403 #define EXxmmdw { OP_EX, xmmdw_mode }
404 #define EXxmmqd { OP_EX, xmmqd_mode }
405 #define EXymmq { OP_EX, ymmq_mode }
406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
410 #define MS { OP_MS, v_mode }
411 #define XS { OP_XS, v_mode }
412 #define EMCq { OP_EMC, q_mode }
413 #define MXC { OP_MXC, 0 }
414 #define OPSUF { OP_3DNowSuffix, 0 }
415 #define CMP { CMP_Fixup, 0 }
416 #define XMM0 { XMM_Fixup, 0 }
417 #define FXSAVE { FXSAVE_Fixup, 0 }
418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
421 #define Vex { OP_VEX, vex_mode }
422 #define VexScalar { OP_VEX, vex_scalar_mode }
423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
424 #define Vex128 { OP_VEX, vex128_mode }
425 #define Vex256 { OP_VEX, vex256_mode }
426 #define VexGdq { OP_VEX, dq_mode }
427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
429 #define EXVexW { OP_EX_VexW, x_mode }
430 #define EXdVexW { OP_EX_VexW, d_mode }
431 #define EXqVexW { OP_EX_VexW, q_mode }
432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
434 #define XMVexW { OP_XMM_VexW, 0 }
435 #define XMVexI4 { OP_REG_VexI4, x_mode }
436 #define PCLMUL { PCLMUL_Fixup, 0 }
437 #define VCMP { VCMP_Fixup, 0 }
438 #define VPCMP { VPCMP_Fixup, 0 }
439 #define VPCOM { VPCOM_Fixup, 0 }
441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
445 #define XMask { OP_Mask, mask_mode }
446 #define MaskG { OP_G, mask_mode }
447 #define MaskE { OP_E, mask_mode }
448 #define MaskBDE { OP_E, mask_bd_mode }
449 #define MaskR { OP_R, mask_mode }
450 #define MaskVex { OP_VEX, mask_mode }
452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
457 /* Used handle "rep" prefix for string instructions. */
458 #define Xbr { REP_Fixup, eSI_reg }
459 #define Xvr { REP_Fixup, eSI_reg }
460 #define Ybr { REP_Fixup, eDI_reg }
461 #define Yvr { REP_Fixup, eDI_reg }
462 #define Yzr { REP_Fixup, eDI_reg }
463 #define indirDXr { REP_Fixup, indir_dx_reg }
464 #define ALr { REP_Fixup, al_reg }
465 #define eAXr { REP_Fixup, eAX_reg }
467 /* Used handle HLE prefix for lockable instructions. */
468 #define Ebh1 { HLE_Fixup1, b_mode }
469 #define Evh1 { HLE_Fixup1, v_mode }
470 #define Ebh2 { HLE_Fixup2, b_mode }
471 #define Evh2 { HLE_Fixup2, v_mode }
472 #define Ebh3 { HLE_Fixup3, b_mode }
473 #define Evh3 { HLE_Fixup3, v_mode }
475 #define BND { BND_Fixup, 0 }
476 #define NOTRACK { NOTRACK_Fixup, 0 }
478 #define cond_jump_flag { NULL, cond_jump_mode }
479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
481 /* bits in sizeflag */
482 #define SUFFIX_ALWAYS 4
490 /* byte operand with operand swapped */
492 /* byte operand, sign extend like 'T' suffix */
494 /* operand size depends on prefixes */
496 /* operand size depends on prefixes with operand swapped */
498 /* operand size depends on address prefix */
502 /* double word operand */
504 /* double word operand with operand swapped */
506 /* quad word operand */
508 /* quad word operand with operand swapped */
510 /* ten-byte operand */
512 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
513 broadcast enabled. */
515 /* Similar to x_mode, but with different EVEX mem shifts. */
517 /* Similar to x_mode, but with disabled broadcast. */
519 /* Similar to x_mode, but with operands swapped and disabled broadcast
522 /* 16-byte XMM operand */
524 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
525 memory operand (depending on vector length). Broadcast isn't
528 /* Same as xmmq_mode, but broadcast is allowed. */
529 evex_half_bcst_xmmq_mode
,
530 /* XMM register or byte memory operand */
532 /* XMM register or word memory operand */
534 /* XMM register or double word memory operand */
536 /* XMM register or quad word memory operand */
538 /* XMM register or double/quad word memory operand, depending on
541 /* 16-byte XMM, word, double word or quad word operand. */
543 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
545 /* 32-byte YMM operand */
547 /* quad word, ymmword or zmmword memory operand. */
549 /* 32-byte YMM or 16-byte word operand */
551 /* d_mode in 32bit, q_mode in 64bit mode. */
553 /* pair of v_mode operands */
558 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
593 /* operand size depends on the VEX.W bit. */
596 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
597 vex_vsib_d_w_dq_mode
,
598 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
600 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
601 vex_vsib_q_w_dq_mode
,
602 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
605 /* scalar, ignore vector length. */
607 /* like b_mode, ignore vector length. */
609 /* like w_mode, ignore vector length. */
611 /* like d_mode, ignore vector length. */
613 /* like d_swap_mode, ignore vector length. */
615 /* like q_mode, ignore vector length. */
617 /* like q_swap_mode, ignore vector length. */
619 /* like vex_mode, ignore vector length. */
621 /* like vex_w_dq_mode, ignore vector length. */
622 vex_scalar_w_dq_mode
,
624 /* Static rounding. */
626 /* Static rounding, 64-bit mode only. */
627 evex_rounding_64_mode
,
628 /* Supress all exceptions. */
631 /* Mask register operand. */
633 /* Mask register operand. */
701 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
703 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
704 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
705 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
706 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
707 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
708 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
709 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
710 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
711 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
712 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
713 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
714 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
715 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
716 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
717 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
718 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
846 MOD_VEX_0F12_PREFIX_0
,
848 MOD_VEX_0F16_PREFIX_0
,
851 MOD_VEX_W_0_0F41_P_0_LEN_1
,
852 MOD_VEX_W_1_0F41_P_0_LEN_1
,
853 MOD_VEX_W_0_0F41_P_2_LEN_1
,
854 MOD_VEX_W_1_0F41_P_2_LEN_1
,
855 MOD_VEX_W_0_0F42_P_0_LEN_1
,
856 MOD_VEX_W_1_0F42_P_0_LEN_1
,
857 MOD_VEX_W_0_0F42_P_2_LEN_1
,
858 MOD_VEX_W_1_0F42_P_2_LEN_1
,
859 MOD_VEX_W_0_0F44_P_0_LEN_1
,
860 MOD_VEX_W_1_0F44_P_0_LEN_1
,
861 MOD_VEX_W_0_0F44_P_2_LEN_1
,
862 MOD_VEX_W_1_0F44_P_2_LEN_1
,
863 MOD_VEX_W_0_0F45_P_0_LEN_1
,
864 MOD_VEX_W_1_0F45_P_0_LEN_1
,
865 MOD_VEX_W_0_0F45_P_2_LEN_1
,
866 MOD_VEX_W_1_0F45_P_2_LEN_1
,
867 MOD_VEX_W_0_0F46_P_0_LEN_1
,
868 MOD_VEX_W_1_0F46_P_0_LEN_1
,
869 MOD_VEX_W_0_0F46_P_2_LEN_1
,
870 MOD_VEX_W_1_0F46_P_2_LEN_1
,
871 MOD_VEX_W_0_0F47_P_0_LEN_1
,
872 MOD_VEX_W_1_0F47_P_0_LEN_1
,
873 MOD_VEX_W_0_0F47_P_2_LEN_1
,
874 MOD_VEX_W_1_0F47_P_2_LEN_1
,
875 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
876 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
877 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
878 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
879 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
880 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
881 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
893 MOD_VEX_W_0_0F91_P_0_LEN_0
,
894 MOD_VEX_W_1_0F91_P_0_LEN_0
,
895 MOD_VEX_W_0_0F91_P_2_LEN_0
,
896 MOD_VEX_W_1_0F91_P_2_LEN_0
,
897 MOD_VEX_W_0_0F92_P_0_LEN_0
,
898 MOD_VEX_W_0_0F92_P_2_LEN_0
,
899 MOD_VEX_0F92_P_3_LEN_0
,
900 MOD_VEX_W_0_0F93_P_0_LEN_0
,
901 MOD_VEX_W_0_0F93_P_2_LEN_0
,
902 MOD_VEX_0F93_P_3_LEN_0
,
903 MOD_VEX_W_0_0F98_P_0_LEN_0
,
904 MOD_VEX_W_1_0F98_P_0_LEN_0
,
905 MOD_VEX_W_0_0F98_P_2_LEN_0
,
906 MOD_VEX_W_1_0F98_P_2_LEN_0
,
907 MOD_VEX_W_0_0F99_P_0_LEN_0
,
908 MOD_VEX_W_1_0F99_P_0_LEN_0
,
909 MOD_VEX_W_0_0F99_P_2_LEN_0
,
910 MOD_VEX_W_1_0F99_P_2_LEN_0
,
913 MOD_VEX_0FD7_PREFIX_2
,
914 MOD_VEX_0FE7_PREFIX_2
,
915 MOD_VEX_0FF0_PREFIX_3
,
916 MOD_VEX_0F381A_PREFIX_2
,
917 MOD_VEX_0F382A_PREFIX_2
,
918 MOD_VEX_0F382C_PREFIX_2
,
919 MOD_VEX_0F382D_PREFIX_2
,
920 MOD_VEX_0F382E_PREFIX_2
,
921 MOD_VEX_0F382F_PREFIX_2
,
922 MOD_VEX_0F385A_PREFIX_2
,
923 MOD_VEX_0F388C_PREFIX_2
,
924 MOD_VEX_0F388E_PREFIX_2
,
925 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
926 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
928 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
930 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
932 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
934 MOD_EVEX_0F12_PREFIX_0
,
935 MOD_EVEX_0F16_PREFIX_0
,
936 MOD_EVEX_0F38C6_REG_1
,
937 MOD_EVEX_0F38C6_REG_2
,
938 MOD_EVEX_0F38C6_REG_5
,
939 MOD_EVEX_0F38C6_REG_6
,
940 MOD_EVEX_0F38C7_REG_1
,
941 MOD_EVEX_0F38C7_REG_2
,
942 MOD_EVEX_0F38C7_REG_5
,
943 MOD_EVEX_0F38C7_REG_6
964 PREFIX_MOD_0_0F01_REG_5
,
965 PREFIX_MOD_3_0F01_REG_5_RM_0
,
966 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1012 PREFIX_MOD_0_0FAE_REG_4
,
1013 PREFIX_MOD_3_0FAE_REG_4
,
1014 PREFIX_MOD_0_0FAE_REG_5
,
1015 PREFIX_MOD_3_0FAE_REG_5
,
1016 PREFIX_MOD_0_0FAE_REG_6
,
1017 PREFIX_MOD_1_0FAE_REG_6
,
1024 PREFIX_MOD_0_0FC7_REG_6
,
1025 PREFIX_MOD_3_0FC7_REG_6
,
1026 PREFIX_MOD_3_0FC7_REG_7
,
1156 PREFIX_VEX_0F71_REG_2
,
1157 PREFIX_VEX_0F71_REG_4
,
1158 PREFIX_VEX_0F71_REG_6
,
1159 PREFIX_VEX_0F72_REG_2
,
1160 PREFIX_VEX_0F72_REG_4
,
1161 PREFIX_VEX_0F72_REG_6
,
1162 PREFIX_VEX_0F73_REG_2
,
1163 PREFIX_VEX_0F73_REG_3
,
1164 PREFIX_VEX_0F73_REG_6
,
1165 PREFIX_VEX_0F73_REG_7
,
1338 PREFIX_VEX_0F38F3_REG_1
,
1339 PREFIX_VEX_0F38F3_REG_2
,
1340 PREFIX_VEX_0F38F3_REG_3
,
1459 PREFIX_EVEX_0F71_REG_2
,
1460 PREFIX_EVEX_0F71_REG_4
,
1461 PREFIX_EVEX_0F71_REG_6
,
1462 PREFIX_EVEX_0F72_REG_0
,
1463 PREFIX_EVEX_0F72_REG_1
,
1464 PREFIX_EVEX_0F72_REG_2
,
1465 PREFIX_EVEX_0F72_REG_4
,
1466 PREFIX_EVEX_0F72_REG_6
,
1467 PREFIX_EVEX_0F73_REG_2
,
1468 PREFIX_EVEX_0F73_REG_3
,
1469 PREFIX_EVEX_0F73_REG_6
,
1470 PREFIX_EVEX_0F73_REG_7
,
1667 PREFIX_EVEX_0F38C6_REG_1
,
1668 PREFIX_EVEX_0F38C6_REG_2
,
1669 PREFIX_EVEX_0F38C6_REG_5
,
1670 PREFIX_EVEX_0F38C6_REG_6
,
1671 PREFIX_EVEX_0F38C7_REG_1
,
1672 PREFIX_EVEX_0F38C7_REG_2
,
1673 PREFIX_EVEX_0F38C7_REG_5
,
1674 PREFIX_EVEX_0F38C7_REG_6
,
1776 THREE_BYTE_0F38
= 0,
1803 VEX_LEN_0F12_P_0_M_0
= 0,
1804 VEX_LEN_0F12_P_0_M_1
,
1807 VEX_LEN_0F16_P_0_M_0
,
1808 VEX_LEN_0F16_P_0_M_1
,
1845 VEX_LEN_0FAE_R_2_M_0
,
1846 VEX_LEN_0FAE_R_3_M_0
,
1853 VEX_LEN_0F381A_P_2_M_0
,
1856 VEX_LEN_0F385A_P_2_M_0
,
1859 VEX_LEN_0F38F3_R_1_P_0
,
1860 VEX_LEN_0F38F3_R_2_P_0
,
1861 VEX_LEN_0F38F3_R_3_P_0
,
1904 VEX_LEN_0FXOP_08_CC
,
1905 VEX_LEN_0FXOP_08_CD
,
1906 VEX_LEN_0FXOP_08_CE
,
1907 VEX_LEN_0FXOP_08_CF
,
1908 VEX_LEN_0FXOP_08_EC
,
1909 VEX_LEN_0FXOP_08_ED
,
1910 VEX_LEN_0FXOP_08_EE
,
1911 VEX_LEN_0FXOP_08_EF
,
1912 VEX_LEN_0FXOP_09_80
,
1918 EVEX_LEN_0F6E_P_2
= 0,
1922 EVEX_LEN_0F3819_P_2_W_0
,
1923 EVEX_LEN_0F3819_P_2_W_1
,
1924 EVEX_LEN_0F381A_P_2_W_0
,
1925 EVEX_LEN_0F381A_P_2_W_1
,
1926 EVEX_LEN_0F381B_P_2_W_0
,
1927 EVEX_LEN_0F381B_P_2_W_1
,
1928 EVEX_LEN_0F385A_P_2_W_0
,
1929 EVEX_LEN_0F385A_P_2_W_1
,
1930 EVEX_LEN_0F385B_P_2_W_0
,
1931 EVEX_LEN_0F385B_P_2_W_1
,
1932 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1933 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1934 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1935 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1936 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1937 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1938 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1939 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1940 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1941 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1942 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1943 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1944 EVEX_LEN_0F3A18_P_2_W_0
,
1945 EVEX_LEN_0F3A18_P_2_W_1
,
1946 EVEX_LEN_0F3A19_P_2_W_0
,
1947 EVEX_LEN_0F3A19_P_2_W_1
,
1948 EVEX_LEN_0F3A1A_P_2_W_0
,
1949 EVEX_LEN_0F3A1A_P_2_W_1
,
1950 EVEX_LEN_0F3A1B_P_2_W_0
,
1951 EVEX_LEN_0F3A1B_P_2_W_1
,
1952 EVEX_LEN_0F3A23_P_2_W_0
,
1953 EVEX_LEN_0F3A23_P_2_W_1
,
1954 EVEX_LEN_0F3A38_P_2_W_0
,
1955 EVEX_LEN_0F3A38_P_2_W_1
,
1956 EVEX_LEN_0F3A39_P_2_W_0
,
1957 EVEX_LEN_0F3A39_P_2_W_1
,
1958 EVEX_LEN_0F3A3A_P_2_W_0
,
1959 EVEX_LEN_0F3A3A_P_2_W_1
,
1960 EVEX_LEN_0F3A3B_P_2_W_0
,
1961 EVEX_LEN_0F3A3B_P_2_W_1
,
1962 EVEX_LEN_0F3A43_P_2_W_0
,
1963 EVEX_LEN_0F3A43_P_2_W_1
1968 VEX_W_0F41_P_0_LEN_1
= 0,
1969 VEX_W_0F41_P_2_LEN_1
,
1970 VEX_W_0F42_P_0_LEN_1
,
1971 VEX_W_0F42_P_2_LEN_1
,
1972 VEX_W_0F44_P_0_LEN_0
,
1973 VEX_W_0F44_P_2_LEN_0
,
1974 VEX_W_0F45_P_0_LEN_1
,
1975 VEX_W_0F45_P_2_LEN_1
,
1976 VEX_W_0F46_P_0_LEN_1
,
1977 VEX_W_0F46_P_2_LEN_1
,
1978 VEX_W_0F47_P_0_LEN_1
,
1979 VEX_W_0F47_P_2_LEN_1
,
1980 VEX_W_0F4A_P_0_LEN_1
,
1981 VEX_W_0F4A_P_2_LEN_1
,
1982 VEX_W_0F4B_P_0_LEN_1
,
1983 VEX_W_0F4B_P_2_LEN_1
,
1984 VEX_W_0F90_P_0_LEN_0
,
1985 VEX_W_0F90_P_2_LEN_0
,
1986 VEX_W_0F91_P_0_LEN_0
,
1987 VEX_W_0F91_P_2_LEN_0
,
1988 VEX_W_0F92_P_0_LEN_0
,
1989 VEX_W_0F92_P_2_LEN_0
,
1990 VEX_W_0F93_P_0_LEN_0
,
1991 VEX_W_0F93_P_2_LEN_0
,
1992 VEX_W_0F98_P_0_LEN_0
,
1993 VEX_W_0F98_P_2_LEN_0
,
1994 VEX_W_0F99_P_0_LEN_0
,
1995 VEX_W_0F99_P_2_LEN_0
,
2003 VEX_W_0F381A_P_2_M_0
,
2004 VEX_W_0F382C_P_2_M_0
,
2005 VEX_W_0F382D_P_2_M_0
,
2006 VEX_W_0F382E_P_2_M_0
,
2007 VEX_W_0F382F_P_2_M_0
,
2012 VEX_W_0F385A_P_2_M_0
,
2024 VEX_W_0F3A30_P_2_LEN_0
,
2025 VEX_W_0F3A31_P_2_LEN_0
,
2026 VEX_W_0F3A32_P_2_LEN_0
,
2027 VEX_W_0F3A33_P_2_LEN_0
,
2047 EVEX_W_0F12_P_0_M_0
,
2048 EVEX_W_0F12_P_0_M_1
,
2058 EVEX_W_0F16_P_0_M_0
,
2059 EVEX_W_0F16_P_0_M_1
,
2128 EVEX_W_0F72_R_2_P_2
,
2129 EVEX_W_0F72_R_6_P_2
,
2130 EVEX_W_0F73_R_2_P_2
,
2131 EVEX_W_0F73_R_6_P_2
,
2241 EVEX_W_0F38C7_R_1_P_2
,
2242 EVEX_W_0F38C7_R_2_P_2
,
2243 EVEX_W_0F38C7_R_5_P_2
,
2244 EVEX_W_0F38C7_R_6_P_2
,
2283 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2292 unsigned int prefix_requirement
;
2295 /* Upper case letters in the instruction names here are macros.
2296 'A' => print 'b' if no register operands or suffix_always is true
2297 'B' => print 'b' if suffix_always is true
2298 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2300 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2301 suffix_always is true
2302 'E' => print 'e' if 32-bit form of jcxz
2303 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2304 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2305 'H' => print ",pt" or ",pn" branch hint
2306 'I' => honor following macro letter even in Intel mode (implemented only
2307 for some of the macro letters)
2309 'K' => print 'd' or 'q' if rex prefix is present.
2310 'L' => print 'l' if suffix_always is true
2311 'M' => print 'r' if intel_mnemonic is false.
2312 'N' => print 'n' if instruction has no wait "prefix"
2313 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2314 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2315 or suffix_always is true. print 'q' if rex prefix is present.
2316 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2318 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2319 'S' => print 'w', 'l' or 'q' if suffix_always is true
2320 'T' => print 'q' in 64bit mode if instruction has no operand size
2321 prefix and behave as 'P' otherwise
2322 'U' => print 'q' in 64bit mode if instruction has no operand size
2323 prefix and behave as 'Q' otherwise
2324 'V' => print 'q' in 64bit mode if instruction has no operand size
2325 prefix and behave as 'S' otherwise
2326 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2327 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2329 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2330 '!' => change condition from true to false or from false to true.
2331 '%' => add 1 upper case letter to the macro.
2332 '^' => print 'w' or 'l' depending on operand size prefix or
2333 suffix_always is true (lcall/ljmp).
2334 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2335 on operand size prefix.
2336 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2337 has no operand size prefix for AMD64 ISA, behave as 'P'
2340 2 upper case letter macros:
2341 "XY" => print 'x' or 'y' if suffix_always is true or no register
2342 operands and no broadcast.
2343 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2344 register operands and no broadcast.
2345 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2346 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2347 or suffix_always is true
2348 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2349 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2350 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2351 "LW" => print 'd', 'q' depending on the VEX.W bit
2352 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2353 an operand size prefix, or suffix_always is true. print
2354 'q' if rex prefix is present.
2356 Many of the above letters print nothing in Intel mode. See "putop"
2359 Braces '{' and '}', and vertical bars '|', indicate alternative
2360 mnemonic strings for AT&T and Intel. */
2362 static const struct dis386 dis386
[] = {
2364 { "addB", { Ebh1
, Gb
}, 0 },
2365 { "addS", { Evh1
, Gv
}, 0 },
2366 { "addB", { Gb
, EbS
}, 0 },
2367 { "addS", { Gv
, EvS
}, 0 },
2368 { "addB", { AL
, Ib
}, 0 },
2369 { "addS", { eAX
, Iv
}, 0 },
2370 { X86_64_TABLE (X86_64_06
) },
2371 { X86_64_TABLE (X86_64_07
) },
2373 { "orB", { Ebh1
, Gb
}, 0 },
2374 { "orS", { Evh1
, Gv
}, 0 },
2375 { "orB", { Gb
, EbS
}, 0 },
2376 { "orS", { Gv
, EvS
}, 0 },
2377 { "orB", { AL
, Ib
}, 0 },
2378 { "orS", { eAX
, Iv
}, 0 },
2379 { X86_64_TABLE (X86_64_0D
) },
2380 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2382 { "adcB", { Ebh1
, Gb
}, 0 },
2383 { "adcS", { Evh1
, Gv
}, 0 },
2384 { "adcB", { Gb
, EbS
}, 0 },
2385 { "adcS", { Gv
, EvS
}, 0 },
2386 { "adcB", { AL
, Ib
}, 0 },
2387 { "adcS", { eAX
, Iv
}, 0 },
2388 { X86_64_TABLE (X86_64_16
) },
2389 { X86_64_TABLE (X86_64_17
) },
2391 { "sbbB", { Ebh1
, Gb
}, 0 },
2392 { "sbbS", { Evh1
, Gv
}, 0 },
2393 { "sbbB", { Gb
, EbS
}, 0 },
2394 { "sbbS", { Gv
, EvS
}, 0 },
2395 { "sbbB", { AL
, Ib
}, 0 },
2396 { "sbbS", { eAX
, Iv
}, 0 },
2397 { X86_64_TABLE (X86_64_1E
) },
2398 { X86_64_TABLE (X86_64_1F
) },
2400 { "andB", { Ebh1
, Gb
}, 0 },
2401 { "andS", { Evh1
, Gv
}, 0 },
2402 { "andB", { Gb
, EbS
}, 0 },
2403 { "andS", { Gv
, EvS
}, 0 },
2404 { "andB", { AL
, Ib
}, 0 },
2405 { "andS", { eAX
, Iv
}, 0 },
2406 { Bad_Opcode
}, /* SEG ES prefix */
2407 { X86_64_TABLE (X86_64_27
) },
2409 { "subB", { Ebh1
, Gb
}, 0 },
2410 { "subS", { Evh1
, Gv
}, 0 },
2411 { "subB", { Gb
, EbS
}, 0 },
2412 { "subS", { Gv
, EvS
}, 0 },
2413 { "subB", { AL
, Ib
}, 0 },
2414 { "subS", { eAX
, Iv
}, 0 },
2415 { Bad_Opcode
}, /* SEG CS prefix */
2416 { X86_64_TABLE (X86_64_2F
) },
2418 { "xorB", { Ebh1
, Gb
}, 0 },
2419 { "xorS", { Evh1
, Gv
}, 0 },
2420 { "xorB", { Gb
, EbS
}, 0 },
2421 { "xorS", { Gv
, EvS
}, 0 },
2422 { "xorB", { AL
, Ib
}, 0 },
2423 { "xorS", { eAX
, Iv
}, 0 },
2424 { Bad_Opcode
}, /* SEG SS prefix */
2425 { X86_64_TABLE (X86_64_37
) },
2427 { "cmpB", { Eb
, Gb
}, 0 },
2428 { "cmpS", { Ev
, Gv
}, 0 },
2429 { "cmpB", { Gb
, EbS
}, 0 },
2430 { "cmpS", { Gv
, EvS
}, 0 },
2431 { "cmpB", { AL
, Ib
}, 0 },
2432 { "cmpS", { eAX
, Iv
}, 0 },
2433 { Bad_Opcode
}, /* SEG DS prefix */
2434 { X86_64_TABLE (X86_64_3F
) },
2436 { "inc{S|}", { RMeAX
}, 0 },
2437 { "inc{S|}", { RMeCX
}, 0 },
2438 { "inc{S|}", { RMeDX
}, 0 },
2439 { "inc{S|}", { RMeBX
}, 0 },
2440 { "inc{S|}", { RMeSP
}, 0 },
2441 { "inc{S|}", { RMeBP
}, 0 },
2442 { "inc{S|}", { RMeSI
}, 0 },
2443 { "inc{S|}", { RMeDI
}, 0 },
2445 { "dec{S|}", { RMeAX
}, 0 },
2446 { "dec{S|}", { RMeCX
}, 0 },
2447 { "dec{S|}", { RMeDX
}, 0 },
2448 { "dec{S|}", { RMeBX
}, 0 },
2449 { "dec{S|}", { RMeSP
}, 0 },
2450 { "dec{S|}", { RMeBP
}, 0 },
2451 { "dec{S|}", { RMeSI
}, 0 },
2452 { "dec{S|}", { RMeDI
}, 0 },
2454 { "pushV", { RMrAX
}, 0 },
2455 { "pushV", { RMrCX
}, 0 },
2456 { "pushV", { RMrDX
}, 0 },
2457 { "pushV", { RMrBX
}, 0 },
2458 { "pushV", { RMrSP
}, 0 },
2459 { "pushV", { RMrBP
}, 0 },
2460 { "pushV", { RMrSI
}, 0 },
2461 { "pushV", { RMrDI
}, 0 },
2463 { "popV", { RMrAX
}, 0 },
2464 { "popV", { RMrCX
}, 0 },
2465 { "popV", { RMrDX
}, 0 },
2466 { "popV", { RMrBX
}, 0 },
2467 { "popV", { RMrSP
}, 0 },
2468 { "popV", { RMrBP
}, 0 },
2469 { "popV", { RMrSI
}, 0 },
2470 { "popV", { RMrDI
}, 0 },
2472 { X86_64_TABLE (X86_64_60
) },
2473 { X86_64_TABLE (X86_64_61
) },
2474 { X86_64_TABLE (X86_64_62
) },
2475 { X86_64_TABLE (X86_64_63
) },
2476 { Bad_Opcode
}, /* seg fs */
2477 { Bad_Opcode
}, /* seg gs */
2478 { Bad_Opcode
}, /* op size prefix */
2479 { Bad_Opcode
}, /* adr size prefix */
2481 { "pushT", { sIv
}, 0 },
2482 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2483 { "pushT", { sIbT
}, 0 },
2484 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2485 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2486 { X86_64_TABLE (X86_64_6D
) },
2487 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2488 { X86_64_TABLE (X86_64_6F
) },
2490 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2491 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2492 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2493 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { REG_TABLE (REG_80
) },
2509 { REG_TABLE (REG_81
) },
2510 { X86_64_TABLE (X86_64_82
) },
2511 { REG_TABLE (REG_83
) },
2512 { "testB", { Eb
, Gb
}, 0 },
2513 { "testS", { Ev
, Gv
}, 0 },
2514 { "xchgB", { Ebh2
, Gb
}, 0 },
2515 { "xchgS", { Evh2
, Gv
}, 0 },
2517 { "movB", { Ebh3
, Gb
}, 0 },
2518 { "movS", { Evh3
, Gv
}, 0 },
2519 { "movB", { Gb
, EbS
}, 0 },
2520 { "movS", { Gv
, EvS
}, 0 },
2521 { "movD", { Sv
, Sw
}, 0 },
2522 { MOD_TABLE (MOD_8D
) },
2523 { "movD", { Sw
, Sv
}, 0 },
2524 { REG_TABLE (REG_8F
) },
2526 { PREFIX_TABLE (PREFIX_90
) },
2527 { "xchgS", { RMeCX
, eAX
}, 0 },
2528 { "xchgS", { RMeDX
, eAX
}, 0 },
2529 { "xchgS", { RMeBX
, eAX
}, 0 },
2530 { "xchgS", { RMeSP
, eAX
}, 0 },
2531 { "xchgS", { RMeBP
, eAX
}, 0 },
2532 { "xchgS", { RMeSI
, eAX
}, 0 },
2533 { "xchgS", { RMeDI
, eAX
}, 0 },
2535 { "cW{t|}R", { XX
}, 0 },
2536 { "cR{t|}O", { XX
}, 0 },
2537 { X86_64_TABLE (X86_64_9A
) },
2538 { Bad_Opcode
}, /* fwait */
2539 { "pushfT", { XX
}, 0 },
2540 { "popfT", { XX
}, 0 },
2541 { "sahf", { XX
}, 0 },
2542 { "lahf", { XX
}, 0 },
2544 { "mov%LB", { AL
, Ob
}, 0 },
2545 { "mov%LS", { eAX
, Ov
}, 0 },
2546 { "mov%LB", { Ob
, AL
}, 0 },
2547 { "mov%LS", { Ov
, eAX
}, 0 },
2548 { "movs{b|}", { Ybr
, Xb
}, 0 },
2549 { "movs{R|}", { Yvr
, Xv
}, 0 },
2550 { "cmps{b|}", { Xb
, Yb
}, 0 },
2551 { "cmps{R|}", { Xv
, Yv
}, 0 },
2553 { "testB", { AL
, Ib
}, 0 },
2554 { "testS", { eAX
, Iv
}, 0 },
2555 { "stosB", { Ybr
, AL
}, 0 },
2556 { "stosS", { Yvr
, eAX
}, 0 },
2557 { "lodsB", { ALr
, Xb
}, 0 },
2558 { "lodsS", { eAXr
, Xv
}, 0 },
2559 { "scasB", { AL
, Yb
}, 0 },
2560 { "scasS", { eAX
, Yv
}, 0 },
2562 { "movB", { RMAL
, Ib
}, 0 },
2563 { "movB", { RMCL
, Ib
}, 0 },
2564 { "movB", { RMDL
, Ib
}, 0 },
2565 { "movB", { RMBL
, Ib
}, 0 },
2566 { "movB", { RMAH
, Ib
}, 0 },
2567 { "movB", { RMCH
, Ib
}, 0 },
2568 { "movB", { RMDH
, Ib
}, 0 },
2569 { "movB", { RMBH
, Ib
}, 0 },
2571 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2572 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2573 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2574 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2576 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2577 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2578 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2580 { REG_TABLE (REG_C0
) },
2581 { REG_TABLE (REG_C1
) },
2582 { "retT", { Iw
, BND
}, 0 },
2583 { "retT", { BND
}, 0 },
2584 { X86_64_TABLE (X86_64_C4
) },
2585 { X86_64_TABLE (X86_64_C5
) },
2586 { REG_TABLE (REG_C6
) },
2587 { REG_TABLE (REG_C7
) },
2589 { "enterT", { Iw
, Ib
}, 0 },
2590 { "leaveT", { XX
}, 0 },
2591 { "Jret{|f}P", { Iw
}, 0 },
2592 { "Jret{|f}P", { XX
}, 0 },
2593 { "int3", { XX
}, 0 },
2594 { "int", { Ib
}, 0 },
2595 { X86_64_TABLE (X86_64_CE
) },
2596 { "iret%LP", { XX
}, 0 },
2598 { REG_TABLE (REG_D0
) },
2599 { REG_TABLE (REG_D1
) },
2600 { REG_TABLE (REG_D2
) },
2601 { REG_TABLE (REG_D3
) },
2602 { X86_64_TABLE (X86_64_D4
) },
2603 { X86_64_TABLE (X86_64_D5
) },
2605 { "xlat", { DSBX
}, 0 },
2616 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2617 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2618 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2619 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "inB", { AL
, Ib
}, 0 },
2621 { "inG", { zAX
, Ib
}, 0 },
2622 { "outB", { Ib
, AL
}, 0 },
2623 { "outG", { Ib
, zAX
}, 0 },
2625 { X86_64_TABLE (X86_64_E8
) },
2626 { X86_64_TABLE (X86_64_E9
) },
2627 { X86_64_TABLE (X86_64_EA
) },
2628 { "jmp", { Jb
, BND
}, 0 },
2629 { "inB", { AL
, indirDX
}, 0 },
2630 { "inG", { zAX
, indirDX
}, 0 },
2631 { "outB", { indirDX
, AL
}, 0 },
2632 { "outG", { indirDX
, zAX
}, 0 },
2634 { Bad_Opcode
}, /* lock prefix */
2635 { "icebp", { XX
}, 0 },
2636 { Bad_Opcode
}, /* repne */
2637 { Bad_Opcode
}, /* repz */
2638 { "hlt", { XX
}, 0 },
2639 { "cmc", { XX
}, 0 },
2640 { REG_TABLE (REG_F6
) },
2641 { REG_TABLE (REG_F7
) },
2643 { "clc", { XX
}, 0 },
2644 { "stc", { XX
}, 0 },
2645 { "cli", { XX
}, 0 },
2646 { "sti", { XX
}, 0 },
2647 { "cld", { XX
}, 0 },
2648 { "std", { XX
}, 0 },
2649 { REG_TABLE (REG_FE
) },
2650 { REG_TABLE (REG_FF
) },
2653 static const struct dis386 dis386_twobyte
[] = {
2655 { REG_TABLE (REG_0F00
) },
2656 { REG_TABLE (REG_0F01
) },
2657 { "larS", { Gv
, Ew
}, 0 },
2658 { "lslS", { Gv
, Ew
}, 0 },
2660 { "syscall", { XX
}, 0 },
2661 { "clts", { XX
}, 0 },
2662 { "sysret%LP", { XX
}, 0 },
2664 { "invd", { XX
}, 0 },
2665 { PREFIX_TABLE (PREFIX_0F09
) },
2667 { "ud2", { XX
}, 0 },
2669 { REG_TABLE (REG_0F0D
) },
2670 { "femms", { XX
}, 0 },
2671 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2673 { PREFIX_TABLE (PREFIX_0F10
) },
2674 { PREFIX_TABLE (PREFIX_0F11
) },
2675 { PREFIX_TABLE (PREFIX_0F12
) },
2676 { MOD_TABLE (MOD_0F13
) },
2677 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2678 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2679 { PREFIX_TABLE (PREFIX_0F16
) },
2680 { MOD_TABLE (MOD_0F17
) },
2682 { REG_TABLE (REG_0F18
) },
2683 { "nopQ", { Ev
}, 0 },
2684 { PREFIX_TABLE (PREFIX_0F1A
) },
2685 { PREFIX_TABLE (PREFIX_0F1B
) },
2686 { PREFIX_TABLE (PREFIX_0F1C
) },
2687 { "nopQ", { Ev
}, 0 },
2688 { PREFIX_TABLE (PREFIX_0F1E
) },
2689 { "nopQ", { Ev
}, 0 },
2691 { "movZ", { Rm
, Cm
}, 0 },
2692 { "movZ", { Rm
, Dm
}, 0 },
2693 { "movZ", { Cm
, Rm
}, 0 },
2694 { "movZ", { Dm
, Rm
}, 0 },
2695 { MOD_TABLE (MOD_0F24
) },
2697 { MOD_TABLE (MOD_0F26
) },
2700 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2701 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2702 { PREFIX_TABLE (PREFIX_0F2A
) },
2703 { PREFIX_TABLE (PREFIX_0F2B
) },
2704 { PREFIX_TABLE (PREFIX_0F2C
) },
2705 { PREFIX_TABLE (PREFIX_0F2D
) },
2706 { PREFIX_TABLE (PREFIX_0F2E
) },
2707 { PREFIX_TABLE (PREFIX_0F2F
) },
2709 { "wrmsr", { XX
}, 0 },
2710 { "rdtsc", { XX
}, 0 },
2711 { "rdmsr", { XX
}, 0 },
2712 { "rdpmc", { XX
}, 0 },
2713 { "sysenter", { XX
}, 0 },
2714 { "sysexit", { XX
}, 0 },
2716 { "getsec", { XX
}, 0 },
2718 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2720 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2727 { "cmovoS", { Gv
, Ev
}, 0 },
2728 { "cmovnoS", { Gv
, Ev
}, 0 },
2729 { "cmovbS", { Gv
, Ev
}, 0 },
2730 { "cmovaeS", { Gv
, Ev
}, 0 },
2731 { "cmoveS", { Gv
, Ev
}, 0 },
2732 { "cmovneS", { Gv
, Ev
}, 0 },
2733 { "cmovbeS", { Gv
, Ev
}, 0 },
2734 { "cmovaS", { Gv
, Ev
}, 0 },
2736 { "cmovsS", { Gv
, Ev
}, 0 },
2737 { "cmovnsS", { Gv
, Ev
}, 0 },
2738 { "cmovpS", { Gv
, Ev
}, 0 },
2739 { "cmovnpS", { Gv
, Ev
}, 0 },
2740 { "cmovlS", { Gv
, Ev
}, 0 },
2741 { "cmovgeS", { Gv
, Ev
}, 0 },
2742 { "cmovleS", { Gv
, Ev
}, 0 },
2743 { "cmovgS", { Gv
, Ev
}, 0 },
2745 { MOD_TABLE (MOD_0F51
) },
2746 { PREFIX_TABLE (PREFIX_0F51
) },
2747 { PREFIX_TABLE (PREFIX_0F52
) },
2748 { PREFIX_TABLE (PREFIX_0F53
) },
2749 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2750 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2751 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2752 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2754 { PREFIX_TABLE (PREFIX_0F58
) },
2755 { PREFIX_TABLE (PREFIX_0F59
) },
2756 { PREFIX_TABLE (PREFIX_0F5A
) },
2757 { PREFIX_TABLE (PREFIX_0F5B
) },
2758 { PREFIX_TABLE (PREFIX_0F5C
) },
2759 { PREFIX_TABLE (PREFIX_0F5D
) },
2760 { PREFIX_TABLE (PREFIX_0F5E
) },
2761 { PREFIX_TABLE (PREFIX_0F5F
) },
2763 { PREFIX_TABLE (PREFIX_0F60
) },
2764 { PREFIX_TABLE (PREFIX_0F61
) },
2765 { PREFIX_TABLE (PREFIX_0F62
) },
2766 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2767 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2768 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2772 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2776 { PREFIX_TABLE (PREFIX_0F6C
) },
2777 { PREFIX_TABLE (PREFIX_0F6D
) },
2778 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2779 { PREFIX_TABLE (PREFIX_0F6F
) },
2781 { PREFIX_TABLE (PREFIX_0F70
) },
2782 { REG_TABLE (REG_0F71
) },
2783 { REG_TABLE (REG_0F72
) },
2784 { REG_TABLE (REG_0F73
) },
2785 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2786 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2787 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2788 { "emms", { XX
}, PREFIX_OPCODE
},
2790 { PREFIX_TABLE (PREFIX_0F78
) },
2791 { PREFIX_TABLE (PREFIX_0F79
) },
2794 { PREFIX_TABLE (PREFIX_0F7C
) },
2795 { PREFIX_TABLE (PREFIX_0F7D
) },
2796 { PREFIX_TABLE (PREFIX_0F7E
) },
2797 { PREFIX_TABLE (PREFIX_0F7F
) },
2799 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2800 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2801 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2802 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "seto", { Eb
}, 0 },
2818 { "setno", { Eb
}, 0 },
2819 { "setb", { Eb
}, 0 },
2820 { "setae", { Eb
}, 0 },
2821 { "sete", { Eb
}, 0 },
2822 { "setne", { Eb
}, 0 },
2823 { "setbe", { Eb
}, 0 },
2824 { "seta", { Eb
}, 0 },
2826 { "sets", { Eb
}, 0 },
2827 { "setns", { Eb
}, 0 },
2828 { "setp", { Eb
}, 0 },
2829 { "setnp", { Eb
}, 0 },
2830 { "setl", { Eb
}, 0 },
2831 { "setge", { Eb
}, 0 },
2832 { "setle", { Eb
}, 0 },
2833 { "setg", { Eb
}, 0 },
2835 { "pushT", { fs
}, 0 },
2836 { "popT", { fs
}, 0 },
2837 { "cpuid", { XX
}, 0 },
2838 { "btS", { Ev
, Gv
}, 0 },
2839 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2840 { "shldS", { Ev
, Gv
, CL
}, 0 },
2841 { REG_TABLE (REG_0FA6
) },
2842 { REG_TABLE (REG_0FA7
) },
2844 { "pushT", { gs
}, 0 },
2845 { "popT", { gs
}, 0 },
2846 { "rsm", { XX
}, 0 },
2847 { "btsS", { Evh1
, Gv
}, 0 },
2848 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2849 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2850 { REG_TABLE (REG_0FAE
) },
2851 { "imulS", { Gv
, Ev
}, 0 },
2853 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2854 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2855 { MOD_TABLE (MOD_0FB2
) },
2856 { "btrS", { Evh1
, Gv
}, 0 },
2857 { MOD_TABLE (MOD_0FB4
) },
2858 { MOD_TABLE (MOD_0FB5
) },
2859 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2860 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2862 { PREFIX_TABLE (PREFIX_0FB8
) },
2863 { "ud1S", { Gv
, Ev
}, 0 },
2864 { REG_TABLE (REG_0FBA
) },
2865 { "btcS", { Evh1
, Gv
}, 0 },
2866 { PREFIX_TABLE (PREFIX_0FBC
) },
2867 { PREFIX_TABLE (PREFIX_0FBD
) },
2868 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2869 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2871 { "xaddB", { Ebh1
, Gb
}, 0 },
2872 { "xaddS", { Evh1
, Gv
}, 0 },
2873 { PREFIX_TABLE (PREFIX_0FC2
) },
2874 { MOD_TABLE (MOD_0FC3
) },
2875 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2876 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2877 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2878 { REG_TABLE (REG_0FC7
) },
2880 { "bswap", { RMeAX
}, 0 },
2881 { "bswap", { RMeCX
}, 0 },
2882 { "bswap", { RMeDX
}, 0 },
2883 { "bswap", { RMeBX
}, 0 },
2884 { "bswap", { RMeSP
}, 0 },
2885 { "bswap", { RMeBP
}, 0 },
2886 { "bswap", { RMeSI
}, 0 },
2887 { "bswap", { RMeDI
}, 0 },
2889 { PREFIX_TABLE (PREFIX_0FD0
) },
2890 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2891 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2892 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2895 { PREFIX_TABLE (PREFIX_0FD6
) },
2896 { MOD_TABLE (MOD_0FD7
) },
2898 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { PREFIX_TABLE (PREFIX_0FE6
) },
2914 { PREFIX_TABLE (PREFIX_0FE7
) },
2916 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2925 { PREFIX_TABLE (PREFIX_0FF0
) },
2926 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { PREFIX_TABLE (PREFIX_0FF7
) },
2934 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "ud0S", { Gv
, Ev
}, 0 },
2944 static const unsigned char onebyte_has_modrm
[256] = {
2945 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2946 /* ------------------------------- */
2947 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2948 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2949 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2950 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2951 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2952 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2953 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2954 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2955 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2956 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2957 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2958 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2959 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2960 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2961 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2962 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2963 /* ------------------------------- */
2964 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2967 static const unsigned char twobyte_has_modrm
[256] = {
2968 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2969 /* ------------------------------- */
2970 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2971 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2972 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2973 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2974 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2975 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2976 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2977 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2978 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2979 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2980 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2981 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2982 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2983 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2984 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2985 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2986 /* ------------------------------- */
2987 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2990 static char obuf
[100];
2992 static char *mnemonicendp
;
2993 static char scratchbuf
[100];
2994 static unsigned char *start_codep
;
2995 static unsigned char *insn_codep
;
2996 static unsigned char *codep
;
2997 static unsigned char *end_codep
;
2998 static int last_lock_prefix
;
2999 static int last_repz_prefix
;
3000 static int last_repnz_prefix
;
3001 static int last_data_prefix
;
3002 static int last_addr_prefix
;
3003 static int last_rex_prefix
;
3004 static int last_seg_prefix
;
3005 static int fwait_prefix
;
3006 /* The active segment register prefix. */
3007 static int active_seg_prefix
;
3008 #define MAX_CODE_LENGTH 15
3009 /* We can up to 14 prefixes since the maximum instruction length is
3011 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3012 static disassemble_info
*the_info
;
3020 static unsigned char need_modrm
;
3030 int register_specifier
;
3037 int mask_register_specifier
;
3043 static unsigned char need_vex
;
3044 static unsigned char need_vex_reg
;
3045 static unsigned char vex_w_done
;
3053 /* If we are accessing mod/rm/reg without need_modrm set, then the
3054 values are stale. Hitting this abort likely indicates that you
3055 need to update onebyte_has_modrm or twobyte_has_modrm. */
3056 #define MODRM_CHECK if (!need_modrm) abort ()
3058 static const char **names64
;
3059 static const char **names32
;
3060 static const char **names16
;
3061 static const char **names8
;
3062 static const char **names8rex
;
3063 static const char **names_seg
;
3064 static const char *index64
;
3065 static const char *index32
;
3066 static const char **index16
;
3067 static const char **names_bnd
;
3069 static const char *intel_names64
[] = {
3070 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3071 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3073 static const char *intel_names32
[] = {
3074 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3075 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3077 static const char *intel_names16
[] = {
3078 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3079 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3081 static const char *intel_names8
[] = {
3082 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3084 static const char *intel_names8rex
[] = {
3085 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3086 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3088 static const char *intel_names_seg
[] = {
3089 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3091 static const char *intel_index64
= "riz";
3092 static const char *intel_index32
= "eiz";
3093 static const char *intel_index16
[] = {
3094 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3097 static const char *att_names64
[] = {
3098 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3099 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3101 static const char *att_names32
[] = {
3102 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3103 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3105 static const char *att_names16
[] = {
3106 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3107 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3109 static const char *att_names8
[] = {
3110 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3112 static const char *att_names8rex
[] = {
3113 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3114 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3116 static const char *att_names_seg
[] = {
3117 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3119 static const char *att_index64
= "%riz";
3120 static const char *att_index32
= "%eiz";
3121 static const char *att_index16
[] = {
3122 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3125 static const char **names_mm
;
3126 static const char *intel_names_mm
[] = {
3127 "mm0", "mm1", "mm2", "mm3",
3128 "mm4", "mm5", "mm6", "mm7"
3130 static const char *att_names_mm
[] = {
3131 "%mm0", "%mm1", "%mm2", "%mm3",
3132 "%mm4", "%mm5", "%mm6", "%mm7"
3135 static const char *intel_names_bnd
[] = {
3136 "bnd0", "bnd1", "bnd2", "bnd3"
3139 static const char *att_names_bnd
[] = {
3140 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3143 static const char **names_xmm
;
3144 static const char *intel_names_xmm
[] = {
3145 "xmm0", "xmm1", "xmm2", "xmm3",
3146 "xmm4", "xmm5", "xmm6", "xmm7",
3147 "xmm8", "xmm9", "xmm10", "xmm11",
3148 "xmm12", "xmm13", "xmm14", "xmm15",
3149 "xmm16", "xmm17", "xmm18", "xmm19",
3150 "xmm20", "xmm21", "xmm22", "xmm23",
3151 "xmm24", "xmm25", "xmm26", "xmm27",
3152 "xmm28", "xmm29", "xmm30", "xmm31"
3154 static const char *att_names_xmm
[] = {
3155 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3156 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3157 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3158 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3159 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3160 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3161 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3162 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3165 static const char **names_ymm
;
3166 static const char *intel_names_ymm
[] = {
3167 "ymm0", "ymm1", "ymm2", "ymm3",
3168 "ymm4", "ymm5", "ymm6", "ymm7",
3169 "ymm8", "ymm9", "ymm10", "ymm11",
3170 "ymm12", "ymm13", "ymm14", "ymm15",
3171 "ymm16", "ymm17", "ymm18", "ymm19",
3172 "ymm20", "ymm21", "ymm22", "ymm23",
3173 "ymm24", "ymm25", "ymm26", "ymm27",
3174 "ymm28", "ymm29", "ymm30", "ymm31"
3176 static const char *att_names_ymm
[] = {
3177 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3178 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3179 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3180 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3181 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3182 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3183 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3184 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3187 static const char **names_zmm
;
3188 static const char *intel_names_zmm
[] = {
3189 "zmm0", "zmm1", "zmm2", "zmm3",
3190 "zmm4", "zmm5", "zmm6", "zmm7",
3191 "zmm8", "zmm9", "zmm10", "zmm11",
3192 "zmm12", "zmm13", "zmm14", "zmm15",
3193 "zmm16", "zmm17", "zmm18", "zmm19",
3194 "zmm20", "zmm21", "zmm22", "zmm23",
3195 "zmm24", "zmm25", "zmm26", "zmm27",
3196 "zmm28", "zmm29", "zmm30", "zmm31"
3198 static const char *att_names_zmm
[] = {
3199 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3200 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3201 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3202 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3203 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3204 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3205 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3206 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3209 static const char **names_mask
;
3210 static const char *intel_names_mask
[] = {
3211 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3213 static const char *att_names_mask
[] = {
3214 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3217 static const char *names_rounding
[] =
3225 static const struct dis386 reg_table
[][8] = {
3228 { "addA", { Ebh1
, Ib
}, 0 },
3229 { "orA", { Ebh1
, Ib
}, 0 },
3230 { "adcA", { Ebh1
, Ib
}, 0 },
3231 { "sbbA", { Ebh1
, Ib
}, 0 },
3232 { "andA", { Ebh1
, Ib
}, 0 },
3233 { "subA", { Ebh1
, Ib
}, 0 },
3234 { "xorA", { Ebh1
, Ib
}, 0 },
3235 { "cmpA", { Eb
, Ib
}, 0 },
3239 { "addQ", { Evh1
, Iv
}, 0 },
3240 { "orQ", { Evh1
, Iv
}, 0 },
3241 { "adcQ", { Evh1
, Iv
}, 0 },
3242 { "sbbQ", { Evh1
, Iv
}, 0 },
3243 { "andQ", { Evh1
, Iv
}, 0 },
3244 { "subQ", { Evh1
, Iv
}, 0 },
3245 { "xorQ", { Evh1
, Iv
}, 0 },
3246 { "cmpQ", { Ev
, Iv
}, 0 },
3250 { "addQ", { Evh1
, sIb
}, 0 },
3251 { "orQ", { Evh1
, sIb
}, 0 },
3252 { "adcQ", { Evh1
, sIb
}, 0 },
3253 { "sbbQ", { Evh1
, sIb
}, 0 },
3254 { "andQ", { Evh1
, sIb
}, 0 },
3255 { "subQ", { Evh1
, sIb
}, 0 },
3256 { "xorQ", { Evh1
, sIb
}, 0 },
3257 { "cmpQ", { Ev
, sIb
}, 0 },
3261 { "popU", { stackEv
}, 0 },
3262 { XOP_8F_TABLE (XOP_09
) },
3266 { XOP_8F_TABLE (XOP_09
) },
3270 { "rolA", { Eb
, Ib
}, 0 },
3271 { "rorA", { Eb
, Ib
}, 0 },
3272 { "rclA", { Eb
, Ib
}, 0 },
3273 { "rcrA", { Eb
, Ib
}, 0 },
3274 { "shlA", { Eb
, Ib
}, 0 },
3275 { "shrA", { Eb
, Ib
}, 0 },
3276 { "shlA", { Eb
, Ib
}, 0 },
3277 { "sarA", { Eb
, Ib
}, 0 },
3281 { "rolQ", { Ev
, Ib
}, 0 },
3282 { "rorQ", { Ev
, Ib
}, 0 },
3283 { "rclQ", { Ev
, Ib
}, 0 },
3284 { "rcrQ", { Ev
, Ib
}, 0 },
3285 { "shlQ", { Ev
, Ib
}, 0 },
3286 { "shrQ", { Ev
, Ib
}, 0 },
3287 { "shlQ", { Ev
, Ib
}, 0 },
3288 { "sarQ", { Ev
, Ib
}, 0 },
3292 { "movA", { Ebh3
, Ib
}, 0 },
3299 { MOD_TABLE (MOD_C6_REG_7
) },
3303 { "movQ", { Evh3
, Iv
}, 0 },
3310 { MOD_TABLE (MOD_C7_REG_7
) },
3314 { "rolA", { Eb
, I1
}, 0 },
3315 { "rorA", { Eb
, I1
}, 0 },
3316 { "rclA", { Eb
, I1
}, 0 },
3317 { "rcrA", { Eb
, I1
}, 0 },
3318 { "shlA", { Eb
, I1
}, 0 },
3319 { "shrA", { Eb
, I1
}, 0 },
3320 { "shlA", { Eb
, I1
}, 0 },
3321 { "sarA", { Eb
, I1
}, 0 },
3325 { "rolQ", { Ev
, I1
}, 0 },
3326 { "rorQ", { Ev
, I1
}, 0 },
3327 { "rclQ", { Ev
, I1
}, 0 },
3328 { "rcrQ", { Ev
, I1
}, 0 },
3329 { "shlQ", { Ev
, I1
}, 0 },
3330 { "shrQ", { Ev
, I1
}, 0 },
3331 { "shlQ", { Ev
, I1
}, 0 },
3332 { "sarQ", { Ev
, I1
}, 0 },
3336 { "rolA", { Eb
, CL
}, 0 },
3337 { "rorA", { Eb
, CL
}, 0 },
3338 { "rclA", { Eb
, CL
}, 0 },
3339 { "rcrA", { Eb
, CL
}, 0 },
3340 { "shlA", { Eb
, CL
}, 0 },
3341 { "shrA", { Eb
, CL
}, 0 },
3342 { "shlA", { Eb
, CL
}, 0 },
3343 { "sarA", { Eb
, CL
}, 0 },
3347 { "rolQ", { Ev
, CL
}, 0 },
3348 { "rorQ", { Ev
, CL
}, 0 },
3349 { "rclQ", { Ev
, CL
}, 0 },
3350 { "rcrQ", { Ev
, CL
}, 0 },
3351 { "shlQ", { Ev
, CL
}, 0 },
3352 { "shrQ", { Ev
, CL
}, 0 },
3353 { "shlQ", { Ev
, CL
}, 0 },
3354 { "sarQ", { Ev
, CL
}, 0 },
3358 { "testA", { Eb
, Ib
}, 0 },
3359 { "testA", { Eb
, Ib
}, 0 },
3360 { "notA", { Ebh1
}, 0 },
3361 { "negA", { Ebh1
}, 0 },
3362 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3363 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3364 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3365 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3369 { "testQ", { Ev
, Iv
}, 0 },
3370 { "testQ", { Ev
, Iv
}, 0 },
3371 { "notQ", { Evh1
}, 0 },
3372 { "negQ", { Evh1
}, 0 },
3373 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3374 { "imulQ", { Ev
}, 0 },
3375 { "divQ", { Ev
}, 0 },
3376 { "idivQ", { Ev
}, 0 },
3380 { "incA", { Ebh1
}, 0 },
3381 { "decA", { Ebh1
}, 0 },
3385 { "incQ", { Evh1
}, 0 },
3386 { "decQ", { Evh1
}, 0 },
3387 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3388 { MOD_TABLE (MOD_FF_REG_3
) },
3389 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3390 { MOD_TABLE (MOD_FF_REG_5
) },
3391 { "pushU", { stackEv
}, 0 },
3396 { "sldtD", { Sv
}, 0 },
3397 { "strD", { Sv
}, 0 },
3398 { "lldt", { Ew
}, 0 },
3399 { "ltr", { Ew
}, 0 },
3400 { "verr", { Ew
}, 0 },
3401 { "verw", { Ew
}, 0 },
3407 { MOD_TABLE (MOD_0F01_REG_0
) },
3408 { MOD_TABLE (MOD_0F01_REG_1
) },
3409 { MOD_TABLE (MOD_0F01_REG_2
) },
3410 { MOD_TABLE (MOD_0F01_REG_3
) },
3411 { "smswD", { Sv
}, 0 },
3412 { MOD_TABLE (MOD_0F01_REG_5
) },
3413 { "lmsw", { Ew
}, 0 },
3414 { MOD_TABLE (MOD_0F01_REG_7
) },
3418 { "prefetch", { Mb
}, 0 },
3419 { "prefetchw", { Mb
}, 0 },
3420 { "prefetchwt1", { Mb
}, 0 },
3421 { "prefetch", { Mb
}, 0 },
3422 { "prefetch", { Mb
}, 0 },
3423 { "prefetch", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3429 { MOD_TABLE (MOD_0F18_REG_0
) },
3430 { MOD_TABLE (MOD_0F18_REG_1
) },
3431 { MOD_TABLE (MOD_0F18_REG_2
) },
3432 { MOD_TABLE (MOD_0F18_REG_3
) },
3433 { MOD_TABLE (MOD_0F18_REG_4
) },
3434 { MOD_TABLE (MOD_0F18_REG_5
) },
3435 { MOD_TABLE (MOD_0F18_REG_6
) },
3436 { MOD_TABLE (MOD_0F18_REG_7
) },
3438 /* REG_0F1C_MOD_0 */
3440 { "cldemote", { Mb
}, 0 },
3441 { "nopQ", { Ev
}, 0 },
3442 { "nopQ", { Ev
}, 0 },
3443 { "nopQ", { Ev
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3449 /* REG_0F1E_MOD_3 */
3451 { "nopQ", { Ev
}, 0 },
3452 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3453 { "nopQ", { Ev
}, 0 },
3454 { "nopQ", { Ev
}, 0 },
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3464 { MOD_TABLE (MOD_0F71_REG_2
) },
3466 { MOD_TABLE (MOD_0F71_REG_4
) },
3468 { MOD_TABLE (MOD_0F71_REG_6
) },
3474 { MOD_TABLE (MOD_0F72_REG_2
) },
3476 { MOD_TABLE (MOD_0F72_REG_4
) },
3478 { MOD_TABLE (MOD_0F72_REG_6
) },
3484 { MOD_TABLE (MOD_0F73_REG_2
) },
3485 { MOD_TABLE (MOD_0F73_REG_3
) },
3488 { MOD_TABLE (MOD_0F73_REG_6
) },
3489 { MOD_TABLE (MOD_0F73_REG_7
) },
3493 { "montmul", { { OP_0f07
, 0 } }, 0 },
3494 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3495 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3499 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3500 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3501 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3502 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3508 { MOD_TABLE (MOD_0FAE_REG_0
) },
3509 { MOD_TABLE (MOD_0FAE_REG_1
) },
3510 { MOD_TABLE (MOD_0FAE_REG_2
) },
3511 { MOD_TABLE (MOD_0FAE_REG_3
) },
3512 { MOD_TABLE (MOD_0FAE_REG_4
) },
3513 { MOD_TABLE (MOD_0FAE_REG_5
) },
3514 { MOD_TABLE (MOD_0FAE_REG_6
) },
3515 { MOD_TABLE (MOD_0FAE_REG_7
) },
3523 { "btQ", { Ev
, Ib
}, 0 },
3524 { "btsQ", { Evh1
, Ib
}, 0 },
3525 { "btrQ", { Evh1
, Ib
}, 0 },
3526 { "btcQ", { Evh1
, Ib
}, 0 },
3531 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3533 { MOD_TABLE (MOD_0FC7_REG_3
) },
3534 { MOD_TABLE (MOD_0FC7_REG_4
) },
3535 { MOD_TABLE (MOD_0FC7_REG_5
) },
3536 { MOD_TABLE (MOD_0FC7_REG_6
) },
3537 { MOD_TABLE (MOD_0FC7_REG_7
) },
3543 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3545 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3547 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3553 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3555 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3557 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3563 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3564 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3567 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3568 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3574 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3575 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3577 /* REG_VEX_0F38F3 */
3580 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3581 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3582 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3586 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3587 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3591 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3592 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3594 /* REG_XOP_TBM_01 */
3597 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3598 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3599 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3600 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 /* REG_XOP_TBM_02 */
3608 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3613 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3616 #include "i386-dis-evex-reg.h"
3619 static const struct dis386 prefix_table
[][4] = {
3622 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3623 { "pause", { XX
}, 0 },
3624 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3625 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3628 /* PREFIX_MOD_0_0F01_REG_5 */
3631 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3634 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3637 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3640 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3643 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3648 { "wbinvd", { XX
}, 0 },
3649 { "wbnoinvd", { XX
}, 0 },
3654 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3655 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3656 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3657 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3662 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3663 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3664 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3665 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3670 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3671 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3672 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3673 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3678 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3679 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3680 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3685 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3686 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3687 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3688 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3693 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3694 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3695 { "bndmov", { EbndS
, Gbnd
}, 0 },
3696 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3701 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3702 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3703 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3704 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3709 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3710 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3711 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3712 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3717 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3718 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3719 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3720 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3725 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3726 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3727 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3728 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3733 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3734 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3735 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3736 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3741 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3742 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3743 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3744 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3749 { "ucomiss",{ XM
, EXd
}, 0 },
3751 { "ucomisd",{ XM
, EXq
}, 0 },
3756 { "comiss", { XM
, EXd
}, 0 },
3758 { "comisd", { XM
, EXq
}, 0 },
3763 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3764 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3765 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3766 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3771 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3772 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3777 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3778 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3783 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3785 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3786 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3791 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3792 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3793 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3794 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3799 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3800 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3801 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3807 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3808 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3809 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3814 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3815 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3816 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3822 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3824 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3830 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3831 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3832 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3838 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3839 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3840 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3841 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3846 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3848 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3853 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3855 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3860 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3862 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3869 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3876 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3881 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3882 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3883 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3888 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3889 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3890 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3891 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3894 /* PREFIX_0F73_REG_3 */
3898 { "psrldq", { XS
, Ib
}, 0 },
3901 /* PREFIX_0F73_REG_7 */
3905 { "pslldq", { XS
, Ib
}, 0 },
3910 {"vmread", { Em
, Gm
}, 0 },
3912 {"extrq", { XS
, Ib
, Ib
}, 0 },
3913 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3918 {"vmwrite", { Gm
, Em
}, 0 },
3920 {"extrq", { XM
, XS
}, 0 },
3921 {"insertq", { XM
, XS
}, 0 },
3928 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3929 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3936 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3937 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3942 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3943 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3944 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3949 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3950 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3951 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3954 /* PREFIX_0FAE_REG_0 */
3957 { "rdfsbase", { Ev
}, 0 },
3960 /* PREFIX_0FAE_REG_1 */
3963 { "rdgsbase", { Ev
}, 0 },
3966 /* PREFIX_0FAE_REG_2 */
3969 { "wrfsbase", { Ev
}, 0 },
3972 /* PREFIX_0FAE_REG_3 */
3975 { "wrgsbase", { Ev
}, 0 },
3978 /* PREFIX_MOD_0_0FAE_REG_4 */
3980 { "xsave", { FXSAVE
}, 0 },
3981 { "ptwrite%LQ", { Edq
}, 0 },
3984 /* PREFIX_MOD_3_0FAE_REG_4 */
3987 { "ptwrite%LQ", { Edq
}, 0 },
3990 /* PREFIX_MOD_0_0FAE_REG_5 */
3992 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
3995 /* PREFIX_MOD_3_0FAE_REG_5 */
3997 { "lfence", { Skip_MODRM
}, 0 },
3998 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4001 /* PREFIX_MOD_0_0FAE_REG_6 */
4003 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4004 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4005 { "clwb", { Mb
}, PREFIX_OPCODE
},
4008 /* PREFIX_MOD_1_0FAE_REG_6 */
4010 { RM_TABLE (RM_0FAE_REG_6
) },
4011 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4012 { "tpause", { Edq
}, PREFIX_OPCODE
},
4013 { "umwait", { Edq
}, PREFIX_OPCODE
},
4016 /* PREFIX_0FAE_REG_7 */
4018 { "clflush", { Mb
}, 0 },
4020 { "clflushopt", { Mb
}, 0 },
4026 { "popcntS", { Gv
, Ev
}, 0 },
4031 { "bsfS", { Gv
, Ev
}, 0 },
4032 { "tzcntS", { Gv
, Ev
}, 0 },
4033 { "bsfS", { Gv
, Ev
}, 0 },
4038 { "bsrS", { Gv
, Ev
}, 0 },
4039 { "lzcntS", { Gv
, Ev
}, 0 },
4040 { "bsrS", { Gv
, Ev
}, 0 },
4045 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4046 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4047 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4048 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4051 /* PREFIX_MOD_0_0FC3 */
4053 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4056 /* PREFIX_MOD_0_0FC7_REG_6 */
4058 { "vmptrld",{ Mq
}, 0 },
4059 { "vmxon", { Mq
}, 0 },
4060 { "vmclear",{ Mq
}, 0 },
4063 /* PREFIX_MOD_3_0FC7_REG_6 */
4065 { "rdrand", { Ev
}, 0 },
4067 { "rdrand", { Ev
}, 0 }
4070 /* PREFIX_MOD_3_0FC7_REG_7 */
4072 { "rdseed", { Ev
}, 0 },
4073 { "rdpid", { Em
}, 0 },
4074 { "rdseed", { Ev
}, 0 },
4081 { "addsubpd", { XM
, EXx
}, 0 },
4082 { "addsubps", { XM
, EXx
}, 0 },
4088 { "movq2dq",{ XM
, MS
}, 0 },
4089 { "movq", { EXqS
, XM
}, 0 },
4090 { "movdq2q",{ MX
, XS
}, 0 },
4096 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4097 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4098 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4103 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4105 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4113 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4118 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4120 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4127 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4134 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4141 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4148 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4155 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4162 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4169 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4176 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4183 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4190 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4197 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4204 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4211 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4218 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4225 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4232 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4239 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4246 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4253 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4260 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4267 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4274 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4281 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4288 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4295 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4302 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4309 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4316 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4323 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4330 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4337 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4344 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4351 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4358 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4363 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4368 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4373 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4378 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4383 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4388 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4395 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4402 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4409 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4416 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4423 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4430 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4435 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4437 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4438 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4443 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4445 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4446 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4453 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4458 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4459 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4460 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4467 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4468 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4469 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4474 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4481 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4488 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4495 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4502 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4509 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4516 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4523 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4530 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4537 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4544 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4551 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4558 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4565 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4572 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4579 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4586 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4593 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4600 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4607 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4614 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4621 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4628 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4633 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4640 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4647 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4654 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4657 /* PREFIX_VEX_0F10 */
4659 { "vmovups", { XM
, EXx
}, 0 },
4660 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4661 { "vmovupd", { XM
, EXx
}, 0 },
4662 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4665 /* PREFIX_VEX_0F11 */
4667 { "vmovups", { EXxS
, XM
}, 0 },
4668 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4669 { "vmovupd", { EXxS
, XM
}, 0 },
4670 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4673 /* PREFIX_VEX_0F12 */
4675 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4676 { "vmovsldup", { XM
, EXx
}, 0 },
4677 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4678 { "vmovddup", { XM
, EXymmq
}, 0 },
4681 /* PREFIX_VEX_0F16 */
4683 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4684 { "vmovshdup", { XM
, EXx
}, 0 },
4685 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4688 /* PREFIX_VEX_0F2A */
4691 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4693 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4696 /* PREFIX_VEX_0F2C */
4699 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4701 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4704 /* PREFIX_VEX_0F2D */
4707 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4709 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4712 /* PREFIX_VEX_0F2E */
4714 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4716 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4719 /* PREFIX_VEX_0F2F */
4721 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4723 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4726 /* PREFIX_VEX_0F41 */
4728 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4730 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4733 /* PREFIX_VEX_0F42 */
4735 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4737 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4740 /* PREFIX_VEX_0F44 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4747 /* PREFIX_VEX_0F45 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4754 /* PREFIX_VEX_0F46 */
4756 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4761 /* PREFIX_VEX_0F47 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4768 /* PREFIX_VEX_0F4A */
4770 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4775 /* PREFIX_VEX_0F4B */
4777 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4782 /* PREFIX_VEX_0F51 */
4784 { "vsqrtps", { XM
, EXx
}, 0 },
4785 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4786 { "vsqrtpd", { XM
, EXx
}, 0 },
4787 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4790 /* PREFIX_VEX_0F52 */
4792 { "vrsqrtps", { XM
, EXx
}, 0 },
4793 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4796 /* PREFIX_VEX_0F53 */
4798 { "vrcpps", { XM
, EXx
}, 0 },
4799 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4802 /* PREFIX_VEX_0F58 */
4804 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4805 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4806 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4807 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4810 /* PREFIX_VEX_0F59 */
4812 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4813 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4814 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4815 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4818 /* PREFIX_VEX_0F5A */
4820 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4821 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4822 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4823 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4826 /* PREFIX_VEX_0F5B */
4828 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4829 { "vcvttps2dq", { XM
, EXx
}, 0 },
4830 { "vcvtps2dq", { XM
, EXx
}, 0 },
4833 /* PREFIX_VEX_0F5C */
4835 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4836 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4837 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4838 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4841 /* PREFIX_VEX_0F5D */
4843 { "vminps", { XM
, Vex
, EXx
}, 0 },
4844 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4845 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4846 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4849 /* PREFIX_VEX_0F5E */
4851 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4852 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4853 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4854 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4857 /* PREFIX_VEX_0F5F */
4859 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4860 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4861 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4862 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4865 /* PREFIX_VEX_0F60 */
4869 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4872 /* PREFIX_VEX_0F61 */
4876 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4879 /* PREFIX_VEX_0F62 */
4883 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4886 /* PREFIX_VEX_0F63 */
4890 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4893 /* PREFIX_VEX_0F64 */
4897 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4900 /* PREFIX_VEX_0F65 */
4904 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4907 /* PREFIX_VEX_0F66 */
4911 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4914 /* PREFIX_VEX_0F67 */
4918 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4921 /* PREFIX_VEX_0F68 */
4925 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4928 /* PREFIX_VEX_0F69 */
4932 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4935 /* PREFIX_VEX_0F6A */
4939 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4942 /* PREFIX_VEX_0F6B */
4946 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4949 /* PREFIX_VEX_0F6C */
4953 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4956 /* PREFIX_VEX_0F6D */
4960 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4963 /* PREFIX_VEX_0F6E */
4967 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4970 /* PREFIX_VEX_0F6F */
4973 { "vmovdqu", { XM
, EXx
}, 0 },
4974 { "vmovdqa", { XM
, EXx
}, 0 },
4977 /* PREFIX_VEX_0F70 */
4980 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4981 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4982 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4985 /* PREFIX_VEX_0F71_REG_2 */
4989 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
4992 /* PREFIX_VEX_0F71_REG_4 */
4996 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
4999 /* PREFIX_VEX_0F71_REG_6 */
5003 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5006 /* PREFIX_VEX_0F72_REG_2 */
5010 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5013 /* PREFIX_VEX_0F72_REG_4 */
5017 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5020 /* PREFIX_VEX_0F72_REG_6 */
5024 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5027 /* PREFIX_VEX_0F73_REG_2 */
5031 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5034 /* PREFIX_VEX_0F73_REG_3 */
5038 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5041 /* PREFIX_VEX_0F73_REG_6 */
5045 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5048 /* PREFIX_VEX_0F73_REG_7 */
5052 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5055 /* PREFIX_VEX_0F74 */
5059 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5062 /* PREFIX_VEX_0F75 */
5066 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5069 /* PREFIX_VEX_0F76 */
5073 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5076 /* PREFIX_VEX_0F77 */
5078 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5081 /* PREFIX_VEX_0F7C */
5085 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5086 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5089 /* PREFIX_VEX_0F7D */
5093 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5094 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5097 /* PREFIX_VEX_0F7E */
5100 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5101 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5104 /* PREFIX_VEX_0F7F */
5107 { "vmovdqu", { EXxS
, XM
}, 0 },
5108 { "vmovdqa", { EXxS
, XM
}, 0 },
5111 /* PREFIX_VEX_0F90 */
5113 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5115 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5118 /* PREFIX_VEX_0F91 */
5120 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5122 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5125 /* PREFIX_VEX_0F92 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5130 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5133 /* PREFIX_VEX_0F93 */
5135 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5137 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5138 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5141 /* PREFIX_VEX_0F98 */
5143 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5145 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5148 /* PREFIX_VEX_0F99 */
5150 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5152 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5155 /* PREFIX_VEX_0FC2 */
5157 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5158 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5159 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5160 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5163 /* PREFIX_VEX_0FC4 */
5167 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5170 /* PREFIX_VEX_0FC5 */
5174 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5177 /* PREFIX_VEX_0FD0 */
5181 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5182 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5185 /* PREFIX_VEX_0FD1 */
5189 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5192 /* PREFIX_VEX_0FD2 */
5196 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5199 /* PREFIX_VEX_0FD3 */
5203 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5206 /* PREFIX_VEX_0FD4 */
5210 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5213 /* PREFIX_VEX_0FD5 */
5217 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5220 /* PREFIX_VEX_0FD6 */
5224 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5227 /* PREFIX_VEX_0FD7 */
5231 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5234 /* PREFIX_VEX_0FD8 */
5238 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5241 /* PREFIX_VEX_0FD9 */
5245 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5248 /* PREFIX_VEX_0FDA */
5252 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5255 /* PREFIX_VEX_0FDB */
5259 { "vpand", { XM
, Vex
, EXx
}, 0 },
5262 /* PREFIX_VEX_0FDC */
5266 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5269 /* PREFIX_VEX_0FDD */
5273 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5276 /* PREFIX_VEX_0FDE */
5280 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5283 /* PREFIX_VEX_0FDF */
5287 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5290 /* PREFIX_VEX_0FE0 */
5294 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5297 /* PREFIX_VEX_0FE1 */
5301 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5304 /* PREFIX_VEX_0FE2 */
5308 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5311 /* PREFIX_VEX_0FE3 */
5315 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5318 /* PREFIX_VEX_0FE4 */
5322 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5325 /* PREFIX_VEX_0FE5 */
5329 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5332 /* PREFIX_VEX_0FE6 */
5335 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5336 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5337 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5340 /* PREFIX_VEX_0FE7 */
5344 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5347 /* PREFIX_VEX_0FE8 */
5351 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5354 /* PREFIX_VEX_0FE9 */
5358 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5361 /* PREFIX_VEX_0FEA */
5365 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5368 /* PREFIX_VEX_0FEB */
5372 { "vpor", { XM
, Vex
, EXx
}, 0 },
5375 /* PREFIX_VEX_0FEC */
5379 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5382 /* PREFIX_VEX_0FED */
5386 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5389 /* PREFIX_VEX_0FEE */
5393 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5396 /* PREFIX_VEX_0FEF */
5400 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5403 /* PREFIX_VEX_0FF0 */
5408 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5411 /* PREFIX_VEX_0FF1 */
5415 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5418 /* PREFIX_VEX_0FF2 */
5422 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5425 /* PREFIX_VEX_0FF3 */
5429 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5432 /* PREFIX_VEX_0FF4 */
5436 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5439 /* PREFIX_VEX_0FF5 */
5443 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5446 /* PREFIX_VEX_0FF6 */
5450 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5453 /* PREFIX_VEX_0FF7 */
5457 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5460 /* PREFIX_VEX_0FF8 */
5464 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5467 /* PREFIX_VEX_0FF9 */
5471 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5474 /* PREFIX_VEX_0FFA */
5478 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5481 /* PREFIX_VEX_0FFB */
5485 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5488 /* PREFIX_VEX_0FFC */
5492 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5495 /* PREFIX_VEX_0FFD */
5499 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5502 /* PREFIX_VEX_0FFE */
5506 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5509 /* PREFIX_VEX_0F3800 */
5513 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5516 /* PREFIX_VEX_0F3801 */
5520 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5523 /* PREFIX_VEX_0F3802 */
5527 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5530 /* PREFIX_VEX_0F3803 */
5534 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5537 /* PREFIX_VEX_0F3804 */
5541 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5544 /* PREFIX_VEX_0F3805 */
5548 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5551 /* PREFIX_VEX_0F3806 */
5555 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5558 /* PREFIX_VEX_0F3807 */
5562 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5565 /* PREFIX_VEX_0F3808 */
5569 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5572 /* PREFIX_VEX_0F3809 */
5576 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5579 /* PREFIX_VEX_0F380A */
5583 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5586 /* PREFIX_VEX_0F380B */
5590 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5593 /* PREFIX_VEX_0F380C */
5597 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5600 /* PREFIX_VEX_0F380D */
5604 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5607 /* PREFIX_VEX_0F380E */
5611 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5614 /* PREFIX_VEX_0F380F */
5618 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5621 /* PREFIX_VEX_0F3813 */
5625 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5628 /* PREFIX_VEX_0F3816 */
5632 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5635 /* PREFIX_VEX_0F3817 */
5639 { "vptest", { XM
, EXx
}, 0 },
5642 /* PREFIX_VEX_0F3818 */
5646 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5649 /* PREFIX_VEX_0F3819 */
5653 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5656 /* PREFIX_VEX_0F381A */
5660 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5663 /* PREFIX_VEX_0F381C */
5667 { "vpabsb", { XM
, EXx
}, 0 },
5670 /* PREFIX_VEX_0F381D */
5674 { "vpabsw", { XM
, EXx
}, 0 },
5677 /* PREFIX_VEX_0F381E */
5681 { "vpabsd", { XM
, EXx
}, 0 },
5684 /* PREFIX_VEX_0F3820 */
5688 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5691 /* PREFIX_VEX_0F3821 */
5695 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5698 /* PREFIX_VEX_0F3822 */
5702 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5705 /* PREFIX_VEX_0F3823 */
5709 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5712 /* PREFIX_VEX_0F3824 */
5716 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5719 /* PREFIX_VEX_0F3825 */
5723 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5726 /* PREFIX_VEX_0F3828 */
5730 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5733 /* PREFIX_VEX_0F3829 */
5737 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5740 /* PREFIX_VEX_0F382A */
5744 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5747 /* PREFIX_VEX_0F382B */
5751 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5754 /* PREFIX_VEX_0F382C */
5758 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5761 /* PREFIX_VEX_0F382D */
5765 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5768 /* PREFIX_VEX_0F382E */
5772 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5775 /* PREFIX_VEX_0F382F */
5779 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5782 /* PREFIX_VEX_0F3830 */
5786 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5789 /* PREFIX_VEX_0F3831 */
5793 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5796 /* PREFIX_VEX_0F3832 */
5800 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5803 /* PREFIX_VEX_0F3833 */
5807 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5810 /* PREFIX_VEX_0F3834 */
5814 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5817 /* PREFIX_VEX_0F3835 */
5821 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5824 /* PREFIX_VEX_0F3836 */
5828 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5831 /* PREFIX_VEX_0F3837 */
5835 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5838 /* PREFIX_VEX_0F3838 */
5842 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5845 /* PREFIX_VEX_0F3839 */
5849 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5852 /* PREFIX_VEX_0F383A */
5856 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5859 /* PREFIX_VEX_0F383B */
5863 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5866 /* PREFIX_VEX_0F383C */
5870 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5873 /* PREFIX_VEX_0F383D */
5877 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5880 /* PREFIX_VEX_0F383E */
5884 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5887 /* PREFIX_VEX_0F383F */
5891 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5894 /* PREFIX_VEX_0F3840 */
5898 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5901 /* PREFIX_VEX_0F3841 */
5905 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5908 /* PREFIX_VEX_0F3845 */
5912 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5915 /* PREFIX_VEX_0F3846 */
5919 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5922 /* PREFIX_VEX_0F3847 */
5926 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5929 /* PREFIX_VEX_0F3858 */
5933 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5936 /* PREFIX_VEX_0F3859 */
5940 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5943 /* PREFIX_VEX_0F385A */
5947 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5950 /* PREFIX_VEX_0F3878 */
5954 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5957 /* PREFIX_VEX_0F3879 */
5961 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5964 /* PREFIX_VEX_0F388C */
5968 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5971 /* PREFIX_VEX_0F388E */
5975 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5978 /* PREFIX_VEX_0F3890 */
5982 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5985 /* PREFIX_VEX_0F3891 */
5989 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
5992 /* PREFIX_VEX_0F3892 */
5996 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5999 /* PREFIX_VEX_0F3893 */
6003 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6006 /* PREFIX_VEX_0F3896 */
6010 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6013 /* PREFIX_VEX_0F3897 */
6017 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6020 /* PREFIX_VEX_0F3898 */
6024 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6027 /* PREFIX_VEX_0F3899 */
6031 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6034 /* PREFIX_VEX_0F389A */
6038 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6041 /* PREFIX_VEX_0F389B */
6045 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6048 /* PREFIX_VEX_0F389C */
6052 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6055 /* PREFIX_VEX_0F389D */
6059 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6062 /* PREFIX_VEX_0F389E */
6066 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6069 /* PREFIX_VEX_0F389F */
6073 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6076 /* PREFIX_VEX_0F38A6 */
6080 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6084 /* PREFIX_VEX_0F38A7 */
6088 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6091 /* PREFIX_VEX_0F38A8 */
6095 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6098 /* PREFIX_VEX_0F38A9 */
6102 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6105 /* PREFIX_VEX_0F38AA */
6109 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6112 /* PREFIX_VEX_0F38AB */
6116 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6119 /* PREFIX_VEX_0F38AC */
6123 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6126 /* PREFIX_VEX_0F38AD */
6130 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6133 /* PREFIX_VEX_0F38AE */
6137 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6140 /* PREFIX_VEX_0F38AF */
6144 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6147 /* PREFIX_VEX_0F38B6 */
6151 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6154 /* PREFIX_VEX_0F38B7 */
6158 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6161 /* PREFIX_VEX_0F38B8 */
6165 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6168 /* PREFIX_VEX_0F38B9 */
6172 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6175 /* PREFIX_VEX_0F38BA */
6179 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6182 /* PREFIX_VEX_0F38BB */
6186 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6189 /* PREFIX_VEX_0F38BC */
6193 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6196 /* PREFIX_VEX_0F38BD */
6200 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6203 /* PREFIX_VEX_0F38BE */
6207 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6210 /* PREFIX_VEX_0F38BF */
6214 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6217 /* PREFIX_VEX_0F38CF */
6221 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6224 /* PREFIX_VEX_0F38DB */
6228 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6231 /* PREFIX_VEX_0F38DC */
6235 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6238 /* PREFIX_VEX_0F38DD */
6242 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6245 /* PREFIX_VEX_0F38DE */
6249 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6252 /* PREFIX_VEX_0F38DF */
6256 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6259 /* PREFIX_VEX_0F38F2 */
6261 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6264 /* PREFIX_VEX_0F38F3_REG_1 */
6266 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6269 /* PREFIX_VEX_0F38F3_REG_2 */
6271 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6274 /* PREFIX_VEX_0F38F3_REG_3 */
6276 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6279 /* PREFIX_VEX_0F38F5 */
6281 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6287 /* PREFIX_VEX_0F38F6 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6295 /* PREFIX_VEX_0F38F7 */
6297 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6300 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6303 /* PREFIX_VEX_0F3A00 */
6307 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6310 /* PREFIX_VEX_0F3A01 */
6314 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6317 /* PREFIX_VEX_0F3A02 */
6321 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6324 /* PREFIX_VEX_0F3A04 */
6328 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6331 /* PREFIX_VEX_0F3A05 */
6335 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6338 /* PREFIX_VEX_0F3A06 */
6342 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6345 /* PREFIX_VEX_0F3A08 */
6349 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6352 /* PREFIX_VEX_0F3A09 */
6356 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6359 /* PREFIX_VEX_0F3A0A */
6363 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6366 /* PREFIX_VEX_0F3A0B */
6370 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6373 /* PREFIX_VEX_0F3A0C */
6377 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6380 /* PREFIX_VEX_0F3A0D */
6384 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6387 /* PREFIX_VEX_0F3A0E */
6391 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6394 /* PREFIX_VEX_0F3A0F */
6398 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6401 /* PREFIX_VEX_0F3A14 */
6405 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6408 /* PREFIX_VEX_0F3A15 */
6412 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6415 /* PREFIX_VEX_0F3A16 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6422 /* PREFIX_VEX_0F3A17 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6429 /* PREFIX_VEX_0F3A18 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6436 /* PREFIX_VEX_0F3A19 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6443 /* PREFIX_VEX_0F3A1D */
6447 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6450 /* PREFIX_VEX_0F3A20 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6457 /* PREFIX_VEX_0F3A21 */
6461 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6464 /* PREFIX_VEX_0F3A22 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6471 /* PREFIX_VEX_0F3A30 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6478 /* PREFIX_VEX_0F3A31 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6485 /* PREFIX_VEX_0F3A32 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6492 /* PREFIX_VEX_0F3A33 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6499 /* PREFIX_VEX_0F3A38 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6506 /* PREFIX_VEX_0F3A39 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6513 /* PREFIX_VEX_0F3A40 */
6517 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6520 /* PREFIX_VEX_0F3A41 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6527 /* PREFIX_VEX_0F3A42 */
6531 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6534 /* PREFIX_VEX_0F3A44 */
6538 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6541 /* PREFIX_VEX_0F3A46 */
6545 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6548 /* PREFIX_VEX_0F3A48 */
6552 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6555 /* PREFIX_VEX_0F3A49 */
6559 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6562 /* PREFIX_VEX_0F3A4A */
6566 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6569 /* PREFIX_VEX_0F3A4B */
6573 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6576 /* PREFIX_VEX_0F3A4C */
6580 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6583 /* PREFIX_VEX_0F3A5C */
6587 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6590 /* PREFIX_VEX_0F3A5D */
6594 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6597 /* PREFIX_VEX_0F3A5E */
6601 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6604 /* PREFIX_VEX_0F3A5F */
6608 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6611 /* PREFIX_VEX_0F3A60 */
6615 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6619 /* PREFIX_VEX_0F3A61 */
6623 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6626 /* PREFIX_VEX_0F3A62 */
6630 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6633 /* PREFIX_VEX_0F3A63 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6640 /* PREFIX_VEX_0F3A68 */
6644 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6647 /* PREFIX_VEX_0F3A69 */
6651 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6654 /* PREFIX_VEX_0F3A6A */
6658 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6661 /* PREFIX_VEX_0F3A6B */
6665 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6668 /* PREFIX_VEX_0F3A6C */
6672 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6675 /* PREFIX_VEX_0F3A6D */
6679 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6682 /* PREFIX_VEX_0F3A6E */
6686 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6689 /* PREFIX_VEX_0F3A6F */
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6696 /* PREFIX_VEX_0F3A78 */
6700 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6703 /* PREFIX_VEX_0F3A79 */
6707 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6710 /* PREFIX_VEX_0F3A7A */
6714 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6717 /* PREFIX_VEX_0F3A7B */
6721 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6724 /* PREFIX_VEX_0F3A7C */
6728 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6732 /* PREFIX_VEX_0F3A7D */
6736 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6739 /* PREFIX_VEX_0F3A7E */
6743 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6746 /* PREFIX_VEX_0F3A7F */
6750 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6753 /* PREFIX_VEX_0F3ACE */
6757 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6760 /* PREFIX_VEX_0F3ACF */
6764 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6767 /* PREFIX_VEX_0F3ADF */
6771 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6774 /* PREFIX_VEX_0F3AF0 */
6779 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6782 #include "i386-dis-evex-prefix.h"
6785 static const struct dis386 x86_64_table
[][2] = {
6788 { "pushP", { es
}, 0 },
6793 { "popP", { es
}, 0 },
6798 { "pushP", { cs
}, 0 },
6803 { "pushP", { ss
}, 0 },
6808 { "popP", { ss
}, 0 },
6813 { "pushP", { ds
}, 0 },
6818 { "popP", { ds
}, 0 },
6823 { "daa", { XX
}, 0 },
6828 { "das", { XX
}, 0 },
6833 { "aaa", { XX
}, 0 },
6838 { "aas", { XX
}, 0 },
6843 { "pushaP", { XX
}, 0 },
6848 { "popaP", { XX
}, 0 },
6853 { MOD_TABLE (MOD_62_32BIT
) },
6854 { EVEX_TABLE (EVEX_0F
) },
6859 { "arpl", { Ew
, Gw
}, 0 },
6860 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6865 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6866 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6871 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6872 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6877 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6878 { REG_TABLE (REG_80
) },
6883 { "Jcall{T|}", { Ap
}, 0 },
6888 { MOD_TABLE (MOD_C4_32BIT
) },
6889 { VEX_C4_TABLE (VEX_0F
) },
6894 { MOD_TABLE (MOD_C5_32BIT
) },
6895 { VEX_C5_TABLE (VEX_0F
) },
6900 { "into", { XX
}, 0 },
6905 { "aam", { Ib
}, 0 },
6910 { "aad", { Ib
}, 0 },
6915 { "callP", { Jv
, BND
}, 0 },
6916 { "call@", { Jv
, BND
}, 0 }
6921 { "jmpP", { Jv
, BND
}, 0 },
6922 { "jmp@", { Jv
, BND
}, 0 }
6927 { "Jjmp{T|}", { Ap
}, 0 },
6930 /* X86_64_0F01_REG_0 */
6932 { "sgdt{Q|IQ}", { M
}, 0 },
6933 { "sgdt", { M
}, 0 },
6936 /* X86_64_0F01_REG_1 */
6938 { "sidt{Q|IQ}", { M
}, 0 },
6939 { "sidt", { M
}, 0 },
6942 /* X86_64_0F01_REG_2 */
6944 { "lgdt{Q|Q}", { M
}, 0 },
6945 { "lgdt", { M
}, 0 },
6948 /* X86_64_0F01_REG_3 */
6950 { "lidt{Q|Q}", { M
}, 0 },
6951 { "lidt", { M
}, 0 },
6955 static const struct dis386 three_byte_table
[][256] = {
6957 /* THREE_BYTE_0F38 */
6960 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6961 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6962 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6963 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6964 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6965 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6966 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6967 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6969 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6970 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6971 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6972 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { PREFIX_TABLE (PREFIX_0F3810
) },
6982 { PREFIX_TABLE (PREFIX_0F3814
) },
6983 { PREFIX_TABLE (PREFIX_0F3815
) },
6985 { PREFIX_TABLE (PREFIX_0F3817
) },
6991 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
6992 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
6993 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
6996 { PREFIX_TABLE (PREFIX_0F3820
) },
6997 { PREFIX_TABLE (PREFIX_0F3821
) },
6998 { PREFIX_TABLE (PREFIX_0F3822
) },
6999 { PREFIX_TABLE (PREFIX_0F3823
) },
7000 { PREFIX_TABLE (PREFIX_0F3824
) },
7001 { PREFIX_TABLE (PREFIX_0F3825
) },
7005 { PREFIX_TABLE (PREFIX_0F3828
) },
7006 { PREFIX_TABLE (PREFIX_0F3829
) },
7007 { PREFIX_TABLE (PREFIX_0F382A
) },
7008 { PREFIX_TABLE (PREFIX_0F382B
) },
7014 { PREFIX_TABLE (PREFIX_0F3830
) },
7015 { PREFIX_TABLE (PREFIX_0F3831
) },
7016 { PREFIX_TABLE (PREFIX_0F3832
) },
7017 { PREFIX_TABLE (PREFIX_0F3833
) },
7018 { PREFIX_TABLE (PREFIX_0F3834
) },
7019 { PREFIX_TABLE (PREFIX_0F3835
) },
7021 { PREFIX_TABLE (PREFIX_0F3837
) },
7023 { PREFIX_TABLE (PREFIX_0F3838
) },
7024 { PREFIX_TABLE (PREFIX_0F3839
) },
7025 { PREFIX_TABLE (PREFIX_0F383A
) },
7026 { PREFIX_TABLE (PREFIX_0F383B
) },
7027 { PREFIX_TABLE (PREFIX_0F383C
) },
7028 { PREFIX_TABLE (PREFIX_0F383D
) },
7029 { PREFIX_TABLE (PREFIX_0F383E
) },
7030 { PREFIX_TABLE (PREFIX_0F383F
) },
7032 { PREFIX_TABLE (PREFIX_0F3840
) },
7033 { PREFIX_TABLE (PREFIX_0F3841
) },
7104 { PREFIX_TABLE (PREFIX_0F3880
) },
7105 { PREFIX_TABLE (PREFIX_0F3881
) },
7106 { PREFIX_TABLE (PREFIX_0F3882
) },
7185 { PREFIX_TABLE (PREFIX_0F38C8
) },
7186 { PREFIX_TABLE (PREFIX_0F38C9
) },
7187 { PREFIX_TABLE (PREFIX_0F38CA
) },
7188 { PREFIX_TABLE (PREFIX_0F38CB
) },
7189 { PREFIX_TABLE (PREFIX_0F38CC
) },
7190 { PREFIX_TABLE (PREFIX_0F38CD
) },
7192 { PREFIX_TABLE (PREFIX_0F38CF
) },
7206 { PREFIX_TABLE (PREFIX_0F38DB
) },
7207 { PREFIX_TABLE (PREFIX_0F38DC
) },
7208 { PREFIX_TABLE (PREFIX_0F38DD
) },
7209 { PREFIX_TABLE (PREFIX_0F38DE
) },
7210 { PREFIX_TABLE (PREFIX_0F38DF
) },
7230 { PREFIX_TABLE (PREFIX_0F38F0
) },
7231 { PREFIX_TABLE (PREFIX_0F38F1
) },
7235 { PREFIX_TABLE (PREFIX_0F38F5
) },
7236 { PREFIX_TABLE (PREFIX_0F38F6
) },
7239 { PREFIX_TABLE (PREFIX_0F38F8
) },
7240 { PREFIX_TABLE (PREFIX_0F38F9
) },
7248 /* THREE_BYTE_0F3A */
7260 { PREFIX_TABLE (PREFIX_0F3A08
) },
7261 { PREFIX_TABLE (PREFIX_0F3A09
) },
7262 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7263 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7264 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7265 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7266 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7267 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7273 { PREFIX_TABLE (PREFIX_0F3A14
) },
7274 { PREFIX_TABLE (PREFIX_0F3A15
) },
7275 { PREFIX_TABLE (PREFIX_0F3A16
) },
7276 { PREFIX_TABLE (PREFIX_0F3A17
) },
7287 { PREFIX_TABLE (PREFIX_0F3A20
) },
7288 { PREFIX_TABLE (PREFIX_0F3A21
) },
7289 { PREFIX_TABLE (PREFIX_0F3A22
) },
7323 { PREFIX_TABLE (PREFIX_0F3A40
) },
7324 { PREFIX_TABLE (PREFIX_0F3A41
) },
7325 { PREFIX_TABLE (PREFIX_0F3A42
) },
7327 { PREFIX_TABLE (PREFIX_0F3A44
) },
7359 { PREFIX_TABLE (PREFIX_0F3A60
) },
7360 { PREFIX_TABLE (PREFIX_0F3A61
) },
7361 { PREFIX_TABLE (PREFIX_0F3A62
) },
7362 { PREFIX_TABLE (PREFIX_0F3A63
) },
7480 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7482 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7483 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7501 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7541 static const struct dis386 xop_table
[][256] = {
7694 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7695 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7696 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7704 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7705 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7712 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7713 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7714 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7722 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7723 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7727 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7728 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7731 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7749 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7761 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7762 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7763 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7764 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7774 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7775 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7776 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7777 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7810 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7811 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7812 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7813 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7837 { REG_TABLE (REG_XOP_TBM_01
) },
7838 { REG_TABLE (REG_XOP_TBM_02
) },
7856 { REG_TABLE (REG_XOP_LWPCB
) },
7980 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7981 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7982 { "vfrczss", { XM
, EXd
}, 0 },
7983 { "vfrczsd", { XM
, EXq
}, 0 },
7998 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
7999 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8000 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8001 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8002 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8003 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8004 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8005 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8007 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8008 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8009 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8010 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8053 { "vphaddbw", { XM
, EXxmm
}, 0 },
8054 { "vphaddbd", { XM
, EXxmm
}, 0 },
8055 { "vphaddbq", { XM
, EXxmm
}, 0 },
8058 { "vphaddwd", { XM
, EXxmm
}, 0 },
8059 { "vphaddwq", { XM
, EXxmm
}, 0 },
8064 { "vphadddq", { XM
, EXxmm
}, 0 },
8071 { "vphaddubw", { XM
, EXxmm
}, 0 },
8072 { "vphaddubd", { XM
, EXxmm
}, 0 },
8073 { "vphaddubq", { XM
, EXxmm
}, 0 },
8076 { "vphadduwd", { XM
, EXxmm
}, 0 },
8077 { "vphadduwq", { XM
, EXxmm
}, 0 },
8082 { "vphaddudq", { XM
, EXxmm
}, 0 },
8089 { "vphsubbw", { XM
, EXxmm
}, 0 },
8090 { "vphsubwd", { XM
, EXxmm
}, 0 },
8091 { "vphsubdq", { XM
, EXxmm
}, 0 },
8145 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8147 { REG_TABLE (REG_XOP_LWP
) },
8417 static const struct dis386 vex_table
[][256] = {
8439 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8440 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8441 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8442 { MOD_TABLE (MOD_VEX_0F13
) },
8443 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8444 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8445 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8446 { MOD_TABLE (MOD_VEX_0F17
) },
8466 { "vmovapX", { XM
, EXx
}, 0 },
8467 { "vmovapX", { EXxS
, XM
}, 0 },
8468 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8469 { MOD_TABLE (MOD_VEX_0F2B
) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8494 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8495 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8497 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8498 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8499 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8500 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8511 { MOD_TABLE (MOD_VEX_0F50
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8515 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8516 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8517 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8518 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8520 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8548 { REG_TABLE (REG_VEX_0F71
) },
8549 { REG_TABLE (REG_VEX_0F72
) },
8550 { REG_TABLE (REG_VEX_0F73
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8583 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8584 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8585 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8586 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8616 { REG_TABLE (REG_VEX_0FAE
) },
8639 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8642 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8643 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8655 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8661 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8662 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8813 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8985 { REG_TABLE (REG_VEX_0F38F3
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9234 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9235 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9253 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9293 #include "i386-dis-evex.h"
9295 static const struct dis386 vex_len_table
[][2] = {
9296 /* VEX_LEN_0F12_P_0_M_0 */
9298 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9301 /* VEX_LEN_0F12_P_0_M_1 */
9303 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9306 /* VEX_LEN_0F12_P_2 */
9308 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9311 /* VEX_LEN_0F13_M_0 */
9313 { "vmovlpX", { EXq
, XM
}, 0 },
9316 /* VEX_LEN_0F16_P_0_M_0 */
9318 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9321 /* VEX_LEN_0F16_P_0_M_1 */
9323 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9326 /* VEX_LEN_0F16_P_2 */
9328 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9331 /* VEX_LEN_0F17_M_0 */
9333 { "vmovhpX", { EXq
, XM
}, 0 },
9336 /* VEX_LEN_0F41_P_0 */
9339 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9341 /* VEX_LEN_0F41_P_2 */
9344 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9346 /* VEX_LEN_0F42_P_0 */
9349 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9351 /* VEX_LEN_0F42_P_2 */
9354 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9356 /* VEX_LEN_0F44_P_0 */
9358 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9360 /* VEX_LEN_0F44_P_2 */
9362 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9364 /* VEX_LEN_0F45_P_0 */
9367 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9369 /* VEX_LEN_0F45_P_2 */
9372 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9374 /* VEX_LEN_0F46_P_0 */
9377 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9379 /* VEX_LEN_0F46_P_2 */
9382 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9384 /* VEX_LEN_0F47_P_0 */
9387 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9389 /* VEX_LEN_0F47_P_2 */
9392 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9394 /* VEX_LEN_0F4A_P_0 */
9397 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9399 /* VEX_LEN_0F4A_P_2 */
9402 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9404 /* VEX_LEN_0F4B_P_0 */
9407 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9409 /* VEX_LEN_0F4B_P_2 */
9412 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9415 /* VEX_LEN_0F6E_P_2 */
9417 { "vmovK", { XMScalar
, Edq
}, 0 },
9420 /* VEX_LEN_0F77_P_1 */
9422 { "vzeroupper", { XX
}, 0 },
9423 { "vzeroall", { XX
}, 0 },
9426 /* VEX_LEN_0F7E_P_1 */
9428 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9431 /* VEX_LEN_0F7E_P_2 */
9433 { "vmovK", { Edq
, XMScalar
}, 0 },
9436 /* VEX_LEN_0F90_P_0 */
9438 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9441 /* VEX_LEN_0F90_P_2 */
9443 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9446 /* VEX_LEN_0F91_P_0 */
9448 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9451 /* VEX_LEN_0F91_P_2 */
9453 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9456 /* VEX_LEN_0F92_P_0 */
9458 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9461 /* VEX_LEN_0F92_P_2 */
9463 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9466 /* VEX_LEN_0F92_P_3 */
9468 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9471 /* VEX_LEN_0F93_P_0 */
9473 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9476 /* VEX_LEN_0F93_P_2 */
9478 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9481 /* VEX_LEN_0F93_P_3 */
9483 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9486 /* VEX_LEN_0F98_P_0 */
9488 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9491 /* VEX_LEN_0F98_P_2 */
9493 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9496 /* VEX_LEN_0F99_P_0 */
9498 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9501 /* VEX_LEN_0F99_P_2 */
9503 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9506 /* VEX_LEN_0FAE_R_2_M_0 */
9508 { "vldmxcsr", { Md
}, 0 },
9511 /* VEX_LEN_0FAE_R_3_M_0 */
9513 { "vstmxcsr", { Md
}, 0 },
9516 /* VEX_LEN_0FC4_P_2 */
9518 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9521 /* VEX_LEN_0FC5_P_2 */
9523 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9526 /* VEX_LEN_0FD6_P_2 */
9528 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9531 /* VEX_LEN_0FF7_P_2 */
9533 { "vmaskmovdqu", { XM
, XS
}, 0 },
9536 /* VEX_LEN_0F3816_P_2 */
9539 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9542 /* VEX_LEN_0F3819_P_2 */
9545 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9548 /* VEX_LEN_0F381A_P_2_M_0 */
9551 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9554 /* VEX_LEN_0F3836_P_2 */
9557 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9560 /* VEX_LEN_0F3841_P_2 */
9562 { "vphminposuw", { XM
, EXx
}, 0 },
9565 /* VEX_LEN_0F385A_P_2_M_0 */
9568 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9571 /* VEX_LEN_0F38DB_P_2 */
9573 { "vaesimc", { XM
, EXx
}, 0 },
9576 /* VEX_LEN_0F38F2_P_0 */
9578 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9581 /* VEX_LEN_0F38F3_R_1_P_0 */
9583 { "blsrS", { VexGdq
, Edq
}, 0 },
9586 /* VEX_LEN_0F38F3_R_2_P_0 */
9588 { "blsmskS", { VexGdq
, Edq
}, 0 },
9591 /* VEX_LEN_0F38F3_R_3_P_0 */
9593 { "blsiS", { VexGdq
, Edq
}, 0 },
9596 /* VEX_LEN_0F38F5_P_0 */
9598 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9601 /* VEX_LEN_0F38F5_P_1 */
9603 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9606 /* VEX_LEN_0F38F5_P_3 */
9608 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9611 /* VEX_LEN_0F38F6_P_3 */
9613 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9616 /* VEX_LEN_0F38F7_P_0 */
9618 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9621 /* VEX_LEN_0F38F7_P_1 */
9623 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9626 /* VEX_LEN_0F38F7_P_2 */
9628 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9631 /* VEX_LEN_0F38F7_P_3 */
9633 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9636 /* VEX_LEN_0F3A00_P_2 */
9639 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9642 /* VEX_LEN_0F3A01_P_2 */
9645 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9648 /* VEX_LEN_0F3A06_P_2 */
9651 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9654 /* VEX_LEN_0F3A14_P_2 */
9656 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9659 /* VEX_LEN_0F3A15_P_2 */
9661 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9664 /* VEX_LEN_0F3A16_P_2 */
9666 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9669 /* VEX_LEN_0F3A17_P_2 */
9671 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9674 /* VEX_LEN_0F3A18_P_2 */
9677 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9680 /* VEX_LEN_0F3A19_P_2 */
9683 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9686 /* VEX_LEN_0F3A20_P_2 */
9688 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9691 /* VEX_LEN_0F3A21_P_2 */
9693 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9696 /* VEX_LEN_0F3A22_P_2 */
9698 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9701 /* VEX_LEN_0F3A30_P_2 */
9703 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9706 /* VEX_LEN_0F3A31_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9711 /* VEX_LEN_0F3A32_P_2 */
9713 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9716 /* VEX_LEN_0F3A33_P_2 */
9718 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9721 /* VEX_LEN_0F3A38_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9727 /* VEX_LEN_0F3A39_P_2 */
9730 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9733 /* VEX_LEN_0F3A41_P_2 */
9735 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9738 /* VEX_LEN_0F3A46_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9744 /* VEX_LEN_0F3A60_P_2 */
9746 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9749 /* VEX_LEN_0F3A61_P_2 */
9751 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9754 /* VEX_LEN_0F3A62_P_2 */
9756 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9759 /* VEX_LEN_0F3A63_P_2 */
9761 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9764 /* VEX_LEN_0F3A6A_P_2 */
9766 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9769 /* VEX_LEN_0F3A6B_P_2 */
9771 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9774 /* VEX_LEN_0F3A6E_P_2 */
9776 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9779 /* VEX_LEN_0F3A6F_P_2 */
9781 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9784 /* VEX_LEN_0F3A7A_P_2 */
9786 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9789 /* VEX_LEN_0F3A7B_P_2 */
9791 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9794 /* VEX_LEN_0F3A7E_P_2 */
9796 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9799 /* VEX_LEN_0F3A7F_P_2 */
9801 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9804 /* VEX_LEN_0F3ADF_P_2 */
9806 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9809 /* VEX_LEN_0F3AF0_P_3 */
9811 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9814 /* VEX_LEN_0FXOP_08_CC */
9816 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9819 /* VEX_LEN_0FXOP_08_CD */
9821 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9824 /* VEX_LEN_0FXOP_08_CE */
9826 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9829 /* VEX_LEN_0FXOP_08_CF */
9831 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9834 /* VEX_LEN_0FXOP_08_EC */
9836 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9839 /* VEX_LEN_0FXOP_08_ED */
9841 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9844 /* VEX_LEN_0FXOP_08_EE */
9846 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9849 /* VEX_LEN_0FXOP_08_EF */
9851 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9854 /* VEX_LEN_0FXOP_09_80 */
9856 { "vfrczps", { XM
, EXxmm
}, 0 },
9857 { "vfrczps", { XM
, EXymmq
}, 0 },
9860 /* VEX_LEN_0FXOP_09_81 */
9862 { "vfrczpd", { XM
, EXxmm
}, 0 },
9863 { "vfrczpd", { XM
, EXymmq
}, 0 },
9867 #include "i386-dis-evex-len.h"
9869 static const struct dis386 vex_w_table
[][2] = {
9871 /* VEX_W_0F41_P_0_LEN_1 */
9872 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9873 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9876 /* VEX_W_0F41_P_2_LEN_1 */
9877 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9878 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9881 /* VEX_W_0F42_P_0_LEN_1 */
9882 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9883 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9886 /* VEX_W_0F42_P_2_LEN_1 */
9887 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9888 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9891 /* VEX_W_0F44_P_0_LEN_0 */
9892 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9893 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9896 /* VEX_W_0F44_P_2_LEN_0 */
9897 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9898 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9901 /* VEX_W_0F45_P_0_LEN_1 */
9902 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9903 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9906 /* VEX_W_0F45_P_2_LEN_1 */
9907 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9908 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9911 /* VEX_W_0F46_P_0_LEN_1 */
9912 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9913 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9916 /* VEX_W_0F46_P_2_LEN_1 */
9917 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9918 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9921 /* VEX_W_0F47_P_0_LEN_1 */
9922 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9923 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9926 /* VEX_W_0F47_P_2_LEN_1 */
9927 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9928 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9931 /* VEX_W_0F4A_P_0_LEN_1 */
9932 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9933 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9936 /* VEX_W_0F4A_P_2_LEN_1 */
9937 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9938 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9941 /* VEX_W_0F4B_P_0_LEN_1 */
9942 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9943 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9946 /* VEX_W_0F4B_P_2_LEN_1 */
9947 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9950 /* VEX_W_0F90_P_0_LEN_0 */
9951 { "kmovw", { MaskG
, MaskE
}, 0 },
9952 { "kmovq", { MaskG
, MaskE
}, 0 },
9955 /* VEX_W_0F90_P_2_LEN_0 */
9956 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9957 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9960 /* VEX_W_0F91_P_0_LEN_0 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9962 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9965 /* VEX_W_0F91_P_2_LEN_0 */
9966 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9967 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9970 /* VEX_W_0F92_P_0_LEN_0 */
9971 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9974 /* VEX_W_0F92_P_2_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9978 /* VEX_W_0F93_P_0_LEN_0 */
9979 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9982 /* VEX_W_0F93_P_2_LEN_0 */
9983 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9986 /* VEX_W_0F98_P_0_LEN_0 */
9987 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9988 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
9991 /* VEX_W_0F98_P_2_LEN_0 */
9992 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
9993 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
9996 /* VEX_W_0F99_P_0_LEN_0 */
9997 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
9998 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10001 /* VEX_W_0F99_P_2_LEN_0 */
10002 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10003 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10006 /* VEX_W_0F380C_P_2 */
10007 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10010 /* VEX_W_0F380D_P_2 */
10011 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10014 /* VEX_W_0F380E_P_2 */
10015 { "vtestps", { XM
, EXx
}, 0 },
10018 /* VEX_W_0F380F_P_2 */
10019 { "vtestpd", { XM
, EXx
}, 0 },
10022 /* VEX_W_0F3816_P_2 */
10023 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10026 /* VEX_W_0F3818_P_2 */
10027 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10030 /* VEX_W_0F3819_P_2 */
10031 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10034 /* VEX_W_0F381A_P_2_M_0 */
10035 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10038 /* VEX_W_0F382C_P_2_M_0 */
10039 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10042 /* VEX_W_0F382D_P_2_M_0 */
10043 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10046 /* VEX_W_0F382E_P_2_M_0 */
10047 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10050 /* VEX_W_0F382F_P_2_M_0 */
10051 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10054 /* VEX_W_0F3836_P_2 */
10055 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10058 /* VEX_W_0F3846_P_2 */
10059 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10062 /* VEX_W_0F3858_P_2 */
10063 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10066 /* VEX_W_0F3859_P_2 */
10067 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10070 /* VEX_W_0F385A_P_2_M_0 */
10071 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10074 /* VEX_W_0F3878_P_2 */
10075 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10078 /* VEX_W_0F3879_P_2 */
10079 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10082 /* VEX_W_0F38CF_P_2 */
10083 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10086 /* VEX_W_0F3A00_P_2 */
10088 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10091 /* VEX_W_0F3A01_P_2 */
10093 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10096 /* VEX_W_0F3A02_P_2 */
10097 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10100 /* VEX_W_0F3A04_P_2 */
10101 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10104 /* VEX_W_0F3A05_P_2 */
10105 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10108 /* VEX_W_0F3A06_P_2 */
10109 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10112 /* VEX_W_0F3A18_P_2 */
10113 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10116 /* VEX_W_0F3A19_P_2 */
10117 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10120 /* VEX_W_0F3A30_P_2_LEN_0 */
10121 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10122 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10125 /* VEX_W_0F3A31_P_2_LEN_0 */
10126 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10127 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10130 /* VEX_W_0F3A32_P_2_LEN_0 */
10131 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10132 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10135 /* VEX_W_0F3A33_P_2_LEN_0 */
10136 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10137 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10140 /* VEX_W_0F3A38_P_2 */
10141 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10144 /* VEX_W_0F3A39_P_2 */
10145 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10148 /* VEX_W_0F3A46_P_2 */
10149 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10152 /* VEX_W_0F3A48_P_2 */
10153 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10154 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10157 /* VEX_W_0F3A49_P_2 */
10158 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10159 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10162 /* VEX_W_0F3A4A_P_2 */
10163 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10166 /* VEX_W_0F3A4B_P_2 */
10167 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10170 /* VEX_W_0F3A4C_P_2 */
10171 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10174 /* VEX_W_0F3ACE_P_2 */
10176 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10179 /* VEX_W_0F3ACF_P_2 */
10181 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10184 #include "i386-dis-evex-w.h"
10187 static const struct dis386 mod_table
[][2] = {
10190 { "leaS", { Gv
, M
}, 0 },
10195 { RM_TABLE (RM_C6_REG_7
) },
10200 { RM_TABLE (RM_C7_REG_7
) },
10204 { "Jcall^", { indirEp
}, 0 },
10208 { "Jjmp^", { indirEp
}, 0 },
10211 /* MOD_0F01_REG_0 */
10212 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10213 { RM_TABLE (RM_0F01_REG_0
) },
10216 /* MOD_0F01_REG_1 */
10217 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10218 { RM_TABLE (RM_0F01_REG_1
) },
10221 /* MOD_0F01_REG_2 */
10222 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10223 { RM_TABLE (RM_0F01_REG_2
) },
10226 /* MOD_0F01_REG_3 */
10227 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10228 { RM_TABLE (RM_0F01_REG_3
) },
10231 /* MOD_0F01_REG_5 */
10232 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10233 { RM_TABLE (RM_0F01_REG_5
) },
10236 /* MOD_0F01_REG_7 */
10237 { "invlpg", { Mb
}, 0 },
10238 { RM_TABLE (RM_0F01_REG_7
) },
10241 /* MOD_0F12_PREFIX_0 */
10242 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10243 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10247 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10250 /* MOD_0F16_PREFIX_0 */
10251 { "movhps", { XM
, EXq
}, 0 },
10252 { "movlhps", { XM
, EXq
}, 0 },
10256 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10259 /* MOD_0F18_REG_0 */
10260 { "prefetchnta", { Mb
}, 0 },
10263 /* MOD_0F18_REG_1 */
10264 { "prefetcht0", { Mb
}, 0 },
10267 /* MOD_0F18_REG_2 */
10268 { "prefetcht1", { Mb
}, 0 },
10271 /* MOD_0F18_REG_3 */
10272 { "prefetcht2", { Mb
}, 0 },
10275 /* MOD_0F18_REG_4 */
10276 { "nop/reserved", { Mb
}, 0 },
10279 /* MOD_0F18_REG_5 */
10280 { "nop/reserved", { Mb
}, 0 },
10283 /* MOD_0F18_REG_6 */
10284 { "nop/reserved", { Mb
}, 0 },
10287 /* MOD_0F18_REG_7 */
10288 { "nop/reserved", { Mb
}, 0 },
10291 /* MOD_0F1A_PREFIX_0 */
10292 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10293 { "nopQ", { Ev
}, 0 },
10296 /* MOD_0F1B_PREFIX_0 */
10297 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10298 { "nopQ", { Ev
}, 0 },
10301 /* MOD_0F1B_PREFIX_1 */
10302 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10303 { "nopQ", { Ev
}, 0 },
10306 /* MOD_0F1C_PREFIX_0 */
10307 { REG_TABLE (REG_0F1C_MOD_0
) },
10308 { "nopQ", { Ev
}, 0 },
10311 /* MOD_0F1E_PREFIX_1 */
10312 { "nopQ", { Ev
}, 0 },
10313 { REG_TABLE (REG_0F1E_MOD_3
) },
10318 { "movL", { Rd
, Td
}, 0 },
10323 { "movL", { Td
, Rd
}, 0 },
10326 /* MOD_0F2B_PREFIX_0 */
10327 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10330 /* MOD_0F2B_PREFIX_1 */
10331 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10334 /* MOD_0F2B_PREFIX_2 */
10335 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10338 /* MOD_0F2B_PREFIX_3 */
10339 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10344 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10347 /* MOD_0F71_REG_2 */
10349 { "psrlw", { MS
, Ib
}, 0 },
10352 /* MOD_0F71_REG_4 */
10354 { "psraw", { MS
, Ib
}, 0 },
10357 /* MOD_0F71_REG_6 */
10359 { "psllw", { MS
, Ib
}, 0 },
10362 /* MOD_0F72_REG_2 */
10364 { "psrld", { MS
, Ib
}, 0 },
10367 /* MOD_0F72_REG_4 */
10369 { "psrad", { MS
, Ib
}, 0 },
10372 /* MOD_0F72_REG_6 */
10374 { "pslld", { MS
, Ib
}, 0 },
10377 /* MOD_0F73_REG_2 */
10379 { "psrlq", { MS
, Ib
}, 0 },
10382 /* MOD_0F73_REG_3 */
10384 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10387 /* MOD_0F73_REG_6 */
10389 { "psllq", { MS
, Ib
}, 0 },
10392 /* MOD_0F73_REG_7 */
10394 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10397 /* MOD_0FAE_REG_0 */
10398 { "fxsave", { FXSAVE
}, 0 },
10399 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10402 /* MOD_0FAE_REG_1 */
10403 { "fxrstor", { FXSAVE
}, 0 },
10404 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10407 /* MOD_0FAE_REG_2 */
10408 { "ldmxcsr", { Md
}, 0 },
10409 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10412 /* MOD_0FAE_REG_3 */
10413 { "stmxcsr", { Md
}, 0 },
10414 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10417 /* MOD_0FAE_REG_4 */
10418 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10419 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10422 /* MOD_0FAE_REG_5 */
10423 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10424 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10427 /* MOD_0FAE_REG_6 */
10428 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10429 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10432 /* MOD_0FAE_REG_7 */
10433 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10434 { RM_TABLE (RM_0FAE_REG_7
) },
10438 { "lssS", { Gv
, Mp
}, 0 },
10442 { "lfsS", { Gv
, Mp
}, 0 },
10446 { "lgsS", { Gv
, Mp
}, 0 },
10450 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10453 /* MOD_0FC7_REG_3 */
10454 { "xrstors", { FXSAVE
}, 0 },
10457 /* MOD_0FC7_REG_4 */
10458 { "xsavec", { FXSAVE
}, 0 },
10461 /* MOD_0FC7_REG_5 */
10462 { "xsaves", { FXSAVE
}, 0 },
10465 /* MOD_0FC7_REG_6 */
10466 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10467 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10470 /* MOD_0FC7_REG_7 */
10471 { "vmptrst", { Mq
}, 0 },
10472 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10477 { "pmovmskb", { Gdq
, MS
}, 0 },
10480 /* MOD_0FE7_PREFIX_2 */
10481 { "movntdq", { Mx
, XM
}, 0 },
10484 /* MOD_0FF0_PREFIX_3 */
10485 { "lddqu", { XM
, M
}, 0 },
10488 /* MOD_0F382A_PREFIX_2 */
10489 { "movntdqa", { XM
, Mx
}, 0 },
10492 /* MOD_0F38F5_PREFIX_2 */
10493 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10496 /* MOD_0F38F6_PREFIX_0 */
10497 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10500 /* MOD_0F38F8_PREFIX_1 */
10501 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10504 /* MOD_0F38F8_PREFIX_2 */
10505 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10508 /* MOD_0F38F8_PREFIX_3 */
10509 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10512 /* MOD_0F38F9_PREFIX_0 */
10513 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10517 { "bound{S|}", { Gv
, Ma
}, 0 },
10518 { EVEX_TABLE (EVEX_0F
) },
10522 { "lesS", { Gv
, Mp
}, 0 },
10523 { VEX_C4_TABLE (VEX_0F
) },
10527 { "ldsS", { Gv
, Mp
}, 0 },
10528 { VEX_C5_TABLE (VEX_0F
) },
10531 /* MOD_VEX_0F12_PREFIX_0 */
10532 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10533 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10537 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10540 /* MOD_VEX_0F16_PREFIX_0 */
10541 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10542 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10546 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10550 { "vmovntpX", { Mx
, XM
}, 0 },
10553 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10555 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10558 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10560 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10563 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10565 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10568 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10570 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10573 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10575 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10578 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10580 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10583 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10585 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10588 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10590 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10593 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10595 { "knotw", { MaskG
, MaskR
}, 0 },
10598 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10600 { "knotq", { MaskG
, MaskR
}, 0 },
10603 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10605 { "knotb", { MaskG
, MaskR
}, 0 },
10608 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10610 { "knotd", { MaskG
, MaskR
}, 0 },
10613 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10615 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10618 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10620 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10623 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10625 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10628 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10630 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10633 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10635 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10638 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10640 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10643 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10645 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10648 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10650 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10653 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10655 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10658 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10660 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10663 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10665 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10668 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10670 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10673 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10675 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10678 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10680 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10683 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10685 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10688 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10690 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10693 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10695 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10698 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10700 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10703 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10705 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10710 { "vmovmskpX", { Gdq
, XS
}, 0 },
10713 /* MOD_VEX_0F71_REG_2 */
10715 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10718 /* MOD_VEX_0F71_REG_4 */
10720 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10723 /* MOD_VEX_0F71_REG_6 */
10725 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10728 /* MOD_VEX_0F72_REG_2 */
10730 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10733 /* MOD_VEX_0F72_REG_4 */
10735 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10738 /* MOD_VEX_0F72_REG_6 */
10740 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10743 /* MOD_VEX_0F73_REG_2 */
10745 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10748 /* MOD_VEX_0F73_REG_3 */
10750 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10753 /* MOD_VEX_0F73_REG_6 */
10755 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10758 /* MOD_VEX_0F73_REG_7 */
10760 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10763 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10764 { "kmovw", { Ew
, MaskG
}, 0 },
10768 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10769 { "kmovq", { Eq
, MaskG
}, 0 },
10773 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10774 { "kmovb", { Eb
, MaskG
}, 0 },
10778 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10779 { "kmovd", { Ed
, MaskG
}, 0 },
10783 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10785 { "kmovw", { MaskG
, Rdq
}, 0 },
10788 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10790 { "kmovb", { MaskG
, Rdq
}, 0 },
10793 /* MOD_VEX_0F92_P_3_LEN_0 */
10795 { "kmovK", { MaskG
, Rdq
}, 0 },
10798 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10800 { "kmovw", { Gdq
, MaskR
}, 0 },
10803 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10805 { "kmovb", { Gdq
, MaskR
}, 0 },
10808 /* MOD_VEX_0F93_P_3_LEN_0 */
10810 { "kmovK", { Gdq
, MaskR
}, 0 },
10813 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10815 { "kortestw", { MaskG
, MaskR
}, 0 },
10818 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10820 { "kortestq", { MaskG
, MaskR
}, 0 },
10823 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10825 { "kortestb", { MaskG
, MaskR
}, 0 },
10828 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10830 { "kortestd", { MaskG
, MaskR
}, 0 },
10833 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10835 { "ktestw", { MaskG
, MaskR
}, 0 },
10838 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10840 { "ktestq", { MaskG
, MaskR
}, 0 },
10843 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10845 { "ktestb", { MaskG
, MaskR
}, 0 },
10848 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10850 { "ktestd", { MaskG
, MaskR
}, 0 },
10853 /* MOD_VEX_0FAE_REG_2 */
10854 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10857 /* MOD_VEX_0FAE_REG_3 */
10858 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10861 /* MOD_VEX_0FD7_PREFIX_2 */
10863 { "vpmovmskb", { Gdq
, XS
}, 0 },
10866 /* MOD_VEX_0FE7_PREFIX_2 */
10867 { "vmovntdq", { Mx
, XM
}, 0 },
10870 /* MOD_VEX_0FF0_PREFIX_3 */
10871 { "vlddqu", { XM
, M
}, 0 },
10874 /* MOD_VEX_0F381A_PREFIX_2 */
10875 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10878 /* MOD_VEX_0F382A_PREFIX_2 */
10879 { "vmovntdqa", { XM
, Mx
}, 0 },
10882 /* MOD_VEX_0F382C_PREFIX_2 */
10883 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10886 /* MOD_VEX_0F382D_PREFIX_2 */
10887 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10890 /* MOD_VEX_0F382E_PREFIX_2 */
10891 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10894 /* MOD_VEX_0F382F_PREFIX_2 */
10895 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10898 /* MOD_VEX_0F385A_PREFIX_2 */
10899 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10902 /* MOD_VEX_0F388C_PREFIX_2 */
10903 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10906 /* MOD_VEX_0F388E_PREFIX_2 */
10907 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10910 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10912 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10915 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10917 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10920 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10922 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10925 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10927 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10930 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10932 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10935 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10937 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10940 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10942 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10945 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10947 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10950 #include "i386-dis-evex-mod.h"
10953 static const struct dis386 rm_table
[][8] = {
10956 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10960 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10963 /* RM_0F01_REG_0 */
10964 { "enclv", { Skip_MODRM
}, 0 },
10965 { "vmcall", { Skip_MODRM
}, 0 },
10966 { "vmlaunch", { Skip_MODRM
}, 0 },
10967 { "vmresume", { Skip_MODRM
}, 0 },
10968 { "vmxoff", { Skip_MODRM
}, 0 },
10969 { "pconfig", { Skip_MODRM
}, 0 },
10972 /* RM_0F01_REG_1 */
10973 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10974 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10975 { "clac", { Skip_MODRM
}, 0 },
10976 { "stac", { Skip_MODRM
}, 0 },
10980 { "encls", { Skip_MODRM
}, 0 },
10983 /* RM_0F01_REG_2 */
10984 { "xgetbv", { Skip_MODRM
}, 0 },
10985 { "xsetbv", { Skip_MODRM
}, 0 },
10988 { "vmfunc", { Skip_MODRM
}, 0 },
10989 { "xend", { Skip_MODRM
}, 0 },
10990 { "xtest", { Skip_MODRM
}, 0 },
10991 { "enclu", { Skip_MODRM
}, 0 },
10994 /* RM_0F01_REG_3 */
10995 { "vmrun", { Skip_MODRM
}, 0 },
10996 { "vmmcall", { Skip_MODRM
}, 0 },
10997 { "vmload", { Skip_MODRM
}, 0 },
10998 { "vmsave", { Skip_MODRM
}, 0 },
10999 { "stgi", { Skip_MODRM
}, 0 },
11000 { "clgi", { Skip_MODRM
}, 0 },
11001 { "skinit", { Skip_MODRM
}, 0 },
11002 { "invlpga", { Skip_MODRM
}, 0 },
11005 /* RM_0F01_REG_5 */
11006 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11008 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11012 { "rdpkru", { Skip_MODRM
}, 0 },
11013 { "wrpkru", { Skip_MODRM
}, 0 },
11016 /* RM_0F01_REG_7 */
11017 { "swapgs", { Skip_MODRM
}, 0 },
11018 { "rdtscp", { Skip_MODRM
}, 0 },
11019 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11020 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11021 { "clzero", { Skip_MODRM
}, 0 },
11024 /* RM_0F1E_MOD_3_REG_7 */
11025 { "nopQ", { Ev
}, 0 },
11026 { "nopQ", { Ev
}, 0 },
11027 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11028 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11029 { "nopQ", { Ev
}, 0 },
11030 { "nopQ", { Ev
}, 0 },
11031 { "nopQ", { Ev
}, 0 },
11032 { "nopQ", { Ev
}, 0 },
11035 /* RM_0FAE_REG_6 */
11036 { "mfence", { Skip_MODRM
}, 0 },
11039 /* RM_0FAE_REG_7 */
11040 { "sfence", { Skip_MODRM
}, 0 },
11045 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11047 /* We use the high bit to indicate different name for the same
11049 #define REP_PREFIX (0xf3 | 0x100)
11050 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11051 #define XRELEASE_PREFIX (0xf3 | 0x400)
11052 #define BND_PREFIX (0xf2 | 0x400)
11053 #define NOTRACK_PREFIX (0x3e | 0x100)
11058 int newrex
, i
, length
;
11064 last_lock_prefix
= -1;
11065 last_repz_prefix
= -1;
11066 last_repnz_prefix
= -1;
11067 last_data_prefix
= -1;
11068 last_addr_prefix
= -1;
11069 last_rex_prefix
= -1;
11070 last_seg_prefix
= -1;
11072 active_seg_prefix
= 0;
11073 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11074 all_prefixes
[i
] = 0;
11077 /* The maximum instruction length is 15bytes. */
11078 while (length
< MAX_CODE_LENGTH
- 1)
11080 FETCH_DATA (the_info
, codep
+ 1);
11084 /* REX prefixes family. */
11101 if (address_mode
== mode_64bit
)
11105 last_rex_prefix
= i
;
11108 prefixes
|= PREFIX_REPZ
;
11109 last_repz_prefix
= i
;
11112 prefixes
|= PREFIX_REPNZ
;
11113 last_repnz_prefix
= i
;
11116 prefixes
|= PREFIX_LOCK
;
11117 last_lock_prefix
= i
;
11120 prefixes
|= PREFIX_CS
;
11121 last_seg_prefix
= i
;
11122 active_seg_prefix
= PREFIX_CS
;
11125 prefixes
|= PREFIX_SS
;
11126 last_seg_prefix
= i
;
11127 active_seg_prefix
= PREFIX_SS
;
11130 prefixes
|= PREFIX_DS
;
11131 last_seg_prefix
= i
;
11132 active_seg_prefix
= PREFIX_DS
;
11135 prefixes
|= PREFIX_ES
;
11136 last_seg_prefix
= i
;
11137 active_seg_prefix
= PREFIX_ES
;
11140 prefixes
|= PREFIX_FS
;
11141 last_seg_prefix
= i
;
11142 active_seg_prefix
= PREFIX_FS
;
11145 prefixes
|= PREFIX_GS
;
11146 last_seg_prefix
= i
;
11147 active_seg_prefix
= PREFIX_GS
;
11150 prefixes
|= PREFIX_DATA
;
11151 last_data_prefix
= i
;
11154 prefixes
|= PREFIX_ADDR
;
11155 last_addr_prefix
= i
;
11158 /* fwait is really an instruction. If there are prefixes
11159 before the fwait, they belong to the fwait, *not* to the
11160 following instruction. */
11162 if (prefixes
|| rex
)
11164 prefixes
|= PREFIX_FWAIT
;
11166 /* This ensures that the previous REX prefixes are noticed
11167 as unused prefixes, as in the return case below. */
11171 prefixes
= PREFIX_FWAIT
;
11176 /* Rex is ignored when followed by another prefix. */
11182 if (*codep
!= FWAIT_OPCODE
)
11183 all_prefixes
[i
++] = *codep
;
11191 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11194 static const char *
11195 prefix_name (int pref
, int sizeflag
)
11197 static const char *rexes
[16] =
11200 "rex.B", /* 0x41 */
11201 "rex.X", /* 0x42 */
11202 "rex.XB", /* 0x43 */
11203 "rex.R", /* 0x44 */
11204 "rex.RB", /* 0x45 */
11205 "rex.RX", /* 0x46 */
11206 "rex.RXB", /* 0x47 */
11207 "rex.W", /* 0x48 */
11208 "rex.WB", /* 0x49 */
11209 "rex.WX", /* 0x4a */
11210 "rex.WXB", /* 0x4b */
11211 "rex.WR", /* 0x4c */
11212 "rex.WRB", /* 0x4d */
11213 "rex.WRX", /* 0x4e */
11214 "rex.WRXB", /* 0x4f */
11219 /* REX prefixes family. */
11236 return rexes
[pref
- 0x40];
11256 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11258 if (address_mode
== mode_64bit
)
11259 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11261 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11266 case XACQUIRE_PREFIX
:
11268 case XRELEASE_PREFIX
:
11272 case NOTRACK_PREFIX
:
11279 static char op_out
[MAX_OPERANDS
][100];
11280 static int op_ad
, op_index
[MAX_OPERANDS
];
11281 static int two_source_ops
;
11282 static bfd_vma op_address
[MAX_OPERANDS
];
11283 static bfd_vma op_riprel
[MAX_OPERANDS
];
11284 static bfd_vma start_pc
;
11287 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11288 * (see topic "Redundant prefixes" in the "Differences from 8086"
11289 * section of the "Virtual 8086 Mode" chapter.)
11290 * 'pc' should be the address of this instruction, it will
11291 * be used to print the target address if this is a relative jump or call
11292 * The function returns the length of this instruction in bytes.
11295 static char intel_syntax
;
11296 static char intel_mnemonic
= !SYSV386_COMPAT
;
11297 static char open_char
;
11298 static char close_char
;
11299 static char separator_char
;
11300 static char scale_char
;
11308 static enum x86_64_isa isa64
;
11310 /* Here for backwards compatibility. When gdb stops using
11311 print_insn_i386_att and print_insn_i386_intel these functions can
11312 disappear, and print_insn_i386 be merged into print_insn. */
11314 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11318 return print_insn (pc
, info
);
11322 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11326 return print_insn (pc
, info
);
11330 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11334 return print_insn (pc
, info
);
11338 print_i386_disassembler_options (FILE *stream
)
11340 fprintf (stream
, _("\n\
11341 The following i386/x86-64 specific disassembler options are supported for use\n\
11342 with the -M switch (multiple options should be separated by commas):\n"));
11344 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11345 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11346 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11347 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11348 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11349 fprintf (stream
, _(" att-mnemonic\n"
11350 " Display instruction in AT&T mnemonic\n"));
11351 fprintf (stream
, _(" intel-mnemonic\n"
11352 " Display instruction in Intel mnemonic\n"));
11353 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11354 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11355 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11356 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11357 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11358 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11359 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11360 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11364 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11366 /* Get a pointer to struct dis386 with a valid name. */
11368 static const struct dis386
*
11369 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11371 int vindex
, vex_table_index
;
11373 if (dp
->name
!= NULL
)
11376 switch (dp
->op
[0].bytemode
)
11378 case USE_REG_TABLE
:
11379 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11382 case USE_MOD_TABLE
:
11383 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11384 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11388 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11391 case USE_PREFIX_TABLE
:
11394 /* The prefix in VEX is implicit. */
11395 switch (vex
.prefix
)
11400 case REPE_PREFIX_OPCODE
:
11403 case DATA_PREFIX_OPCODE
:
11406 case REPNE_PREFIX_OPCODE
:
11416 int last_prefix
= -1;
11419 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11420 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11422 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11424 if (last_repz_prefix
> last_repnz_prefix
)
11427 prefix
= PREFIX_REPZ
;
11428 last_prefix
= last_repz_prefix
;
11433 prefix
= PREFIX_REPNZ
;
11434 last_prefix
= last_repnz_prefix
;
11437 /* Check if prefix should be ignored. */
11438 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11439 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11444 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11447 prefix
= PREFIX_DATA
;
11448 last_prefix
= last_data_prefix
;
11453 used_prefixes
|= prefix
;
11454 all_prefixes
[last_prefix
] = 0;
11457 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11460 case USE_X86_64_TABLE
:
11461 vindex
= address_mode
== mode_64bit
? 1 : 0;
11462 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11465 case USE_3BYTE_TABLE
:
11466 FETCH_DATA (info
, codep
+ 2);
11468 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11470 modrm
.mod
= (*codep
>> 6) & 3;
11471 modrm
.reg
= (*codep
>> 3) & 7;
11472 modrm
.rm
= *codep
& 7;
11475 case USE_VEX_LEN_TABLE
:
11479 switch (vex
.length
)
11492 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11495 case USE_EVEX_LEN_TABLE
:
11499 switch (vex
.length
)
11515 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11518 case USE_XOP_8F_TABLE
:
11519 FETCH_DATA (info
, codep
+ 3);
11520 /* All bits in the REX prefix are ignored. */
11522 rex
= ~(*codep
>> 5) & 0x7;
11524 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11525 switch ((*codep
& 0x1f))
11531 vex_table_index
= XOP_08
;
11534 vex_table_index
= XOP_09
;
11537 vex_table_index
= XOP_0A
;
11541 vex
.w
= *codep
& 0x80;
11542 if (vex
.w
&& address_mode
== mode_64bit
)
11545 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11546 if (address_mode
!= mode_64bit
)
11548 /* In 16/32-bit mode REX_B is silently ignored. */
11552 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11553 switch ((*codep
& 0x3))
11558 vex
.prefix
= DATA_PREFIX_OPCODE
;
11561 vex
.prefix
= REPE_PREFIX_OPCODE
;
11564 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11571 dp
= &xop_table
[vex_table_index
][vindex
];
11574 FETCH_DATA (info
, codep
+ 1);
11575 modrm
.mod
= (*codep
>> 6) & 3;
11576 modrm
.reg
= (*codep
>> 3) & 7;
11577 modrm
.rm
= *codep
& 7;
11580 case USE_VEX_C4_TABLE
:
11582 FETCH_DATA (info
, codep
+ 3);
11583 /* All bits in the REX prefix are ignored. */
11585 rex
= ~(*codep
>> 5) & 0x7;
11586 switch ((*codep
& 0x1f))
11592 vex_table_index
= VEX_0F
;
11595 vex_table_index
= VEX_0F38
;
11598 vex_table_index
= VEX_0F3A
;
11602 vex
.w
= *codep
& 0x80;
11603 if (address_mode
== mode_64bit
)
11610 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11611 is ignored, other REX bits are 0 and the highest bit in
11612 VEX.vvvv is also ignored (but we mustn't clear it here). */
11615 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11616 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11617 switch ((*codep
& 0x3))
11622 vex
.prefix
= DATA_PREFIX_OPCODE
;
11625 vex
.prefix
= REPE_PREFIX_OPCODE
;
11628 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11635 dp
= &vex_table
[vex_table_index
][vindex
];
11637 /* There is no MODRM byte for VEX0F 77. */
11638 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11640 FETCH_DATA (info
, codep
+ 1);
11641 modrm
.mod
= (*codep
>> 6) & 3;
11642 modrm
.reg
= (*codep
>> 3) & 7;
11643 modrm
.rm
= *codep
& 7;
11647 case USE_VEX_C5_TABLE
:
11649 FETCH_DATA (info
, codep
+ 2);
11650 /* All bits in the REX prefix are ignored. */
11652 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11654 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11656 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11657 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11658 switch ((*codep
& 0x3))
11663 vex
.prefix
= DATA_PREFIX_OPCODE
;
11666 vex
.prefix
= REPE_PREFIX_OPCODE
;
11669 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11676 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11678 /* There is no MODRM byte for VEX 77. */
11679 if (vindex
!= 0x77)
11681 FETCH_DATA (info
, codep
+ 1);
11682 modrm
.mod
= (*codep
>> 6) & 3;
11683 modrm
.reg
= (*codep
>> 3) & 7;
11684 modrm
.rm
= *codep
& 7;
11688 case USE_VEX_W_TABLE
:
11692 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11695 case USE_EVEX_TABLE
:
11696 two_source_ops
= 0;
11699 FETCH_DATA (info
, codep
+ 4);
11700 /* All bits in the REX prefix are ignored. */
11702 /* The first byte after 0x62. */
11703 rex
= ~(*codep
>> 5) & 0x7;
11704 vex
.r
= *codep
& 0x10;
11705 switch ((*codep
& 0xf))
11708 return &bad_opcode
;
11710 vex_table_index
= EVEX_0F
;
11713 vex_table_index
= EVEX_0F38
;
11716 vex_table_index
= EVEX_0F3A
;
11720 /* The second byte after 0x62. */
11722 vex
.w
= *codep
& 0x80;
11723 if (vex
.w
&& address_mode
== mode_64bit
)
11726 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11729 if (!(*codep
& 0x4))
11730 return &bad_opcode
;
11732 switch ((*codep
& 0x3))
11737 vex
.prefix
= DATA_PREFIX_OPCODE
;
11740 vex
.prefix
= REPE_PREFIX_OPCODE
;
11743 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11747 /* The third byte after 0x62. */
11750 /* Remember the static rounding bits. */
11751 vex
.ll
= (*codep
>> 5) & 3;
11752 vex
.b
= (*codep
& 0x10) != 0;
11754 vex
.v
= *codep
& 0x8;
11755 vex
.mask_register_specifier
= *codep
& 0x7;
11756 vex
.zeroing
= *codep
& 0x80;
11758 if (address_mode
!= mode_64bit
)
11760 /* In 16/32-bit mode silently ignore following bits. */
11770 dp
= &evex_table
[vex_table_index
][vindex
];
11772 FETCH_DATA (info
, codep
+ 1);
11773 modrm
.mod
= (*codep
>> 6) & 3;
11774 modrm
.reg
= (*codep
>> 3) & 7;
11775 modrm
.rm
= *codep
& 7;
11777 /* Set vector length. */
11778 if (modrm
.mod
== 3 && vex
.b
)
11794 return &bad_opcode
;
11807 if (dp
->name
!= NULL
)
11810 return get_valid_dis386 (dp
, info
);
11814 get_sib (disassemble_info
*info
, int sizeflag
)
11816 /* If modrm.mod == 3, operand must be register. */
11818 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11822 FETCH_DATA (info
, codep
+ 2);
11823 sib
.index
= (codep
[1] >> 3) & 7;
11824 sib
.scale
= (codep
[1] >> 6) & 3;
11825 sib
.base
= codep
[1] & 7;
11830 print_insn (bfd_vma pc
, disassemble_info
*info
)
11832 const struct dis386
*dp
;
11834 char *op_txt
[MAX_OPERANDS
];
11836 int sizeflag
, orig_sizeflag
;
11838 struct dis_private priv
;
11841 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11842 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11843 address_mode
= mode_32bit
;
11844 else if (info
->mach
== bfd_mach_i386_i8086
)
11846 address_mode
= mode_16bit
;
11847 priv
.orig_sizeflag
= 0;
11850 address_mode
= mode_64bit
;
11852 if (intel_syntax
== (char) -1)
11853 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11855 for (p
= info
->disassembler_options
; p
!= NULL
; )
11857 if (CONST_STRNEQ (p
, "amd64"))
11859 else if (CONST_STRNEQ (p
, "intel64"))
11861 else if (CONST_STRNEQ (p
, "x86-64"))
11863 address_mode
= mode_64bit
;
11864 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11866 else if (CONST_STRNEQ (p
, "i386"))
11868 address_mode
= mode_32bit
;
11869 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11871 else if (CONST_STRNEQ (p
, "i8086"))
11873 address_mode
= mode_16bit
;
11874 priv
.orig_sizeflag
= 0;
11876 else if (CONST_STRNEQ (p
, "intel"))
11879 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11880 intel_mnemonic
= 1;
11882 else if (CONST_STRNEQ (p
, "att"))
11885 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11886 intel_mnemonic
= 0;
11888 else if (CONST_STRNEQ (p
, "addr"))
11890 if (address_mode
== mode_64bit
)
11892 if (p
[4] == '3' && p
[5] == '2')
11893 priv
.orig_sizeflag
&= ~AFLAG
;
11894 else if (p
[4] == '6' && p
[5] == '4')
11895 priv
.orig_sizeflag
|= AFLAG
;
11899 if (p
[4] == '1' && p
[5] == '6')
11900 priv
.orig_sizeflag
&= ~AFLAG
;
11901 else if (p
[4] == '3' && p
[5] == '2')
11902 priv
.orig_sizeflag
|= AFLAG
;
11905 else if (CONST_STRNEQ (p
, "data"))
11907 if (p
[4] == '1' && p
[5] == '6')
11908 priv
.orig_sizeflag
&= ~DFLAG
;
11909 else if (p
[4] == '3' && p
[5] == '2')
11910 priv
.orig_sizeflag
|= DFLAG
;
11912 else if (CONST_STRNEQ (p
, "suffix"))
11913 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11915 p
= strchr (p
, ',');
11920 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11922 (*info
->fprintf_func
) (info
->stream
,
11923 _("64-bit address is disabled"));
11929 names64
= intel_names64
;
11930 names32
= intel_names32
;
11931 names16
= intel_names16
;
11932 names8
= intel_names8
;
11933 names8rex
= intel_names8rex
;
11934 names_seg
= intel_names_seg
;
11935 names_mm
= intel_names_mm
;
11936 names_bnd
= intel_names_bnd
;
11937 names_xmm
= intel_names_xmm
;
11938 names_ymm
= intel_names_ymm
;
11939 names_zmm
= intel_names_zmm
;
11940 index64
= intel_index64
;
11941 index32
= intel_index32
;
11942 names_mask
= intel_names_mask
;
11943 index16
= intel_index16
;
11946 separator_char
= '+';
11951 names64
= att_names64
;
11952 names32
= att_names32
;
11953 names16
= att_names16
;
11954 names8
= att_names8
;
11955 names8rex
= att_names8rex
;
11956 names_seg
= att_names_seg
;
11957 names_mm
= att_names_mm
;
11958 names_bnd
= att_names_bnd
;
11959 names_xmm
= att_names_xmm
;
11960 names_ymm
= att_names_ymm
;
11961 names_zmm
= att_names_zmm
;
11962 index64
= att_index64
;
11963 index32
= att_index32
;
11964 names_mask
= att_names_mask
;
11965 index16
= att_index16
;
11968 separator_char
= ',';
11972 /* The output looks better if we put 7 bytes on a line, since that
11973 puts most long word instructions on a single line. Use 8 bytes
11975 if ((info
->mach
& bfd_mach_l1om
) != 0)
11976 info
->bytes_per_line
= 8;
11978 info
->bytes_per_line
= 7;
11980 info
->private_data
= &priv
;
11981 priv
.max_fetched
= priv
.the_buffer
;
11982 priv
.insn_start
= pc
;
11985 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11993 start_codep
= priv
.the_buffer
;
11994 codep
= priv
.the_buffer
;
11996 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12000 /* Getting here means we tried for data but didn't get it. That
12001 means we have an incomplete instruction of some sort. Just
12002 print the first byte as a prefix or a .byte pseudo-op. */
12003 if (codep
> priv
.the_buffer
)
12005 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12007 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12010 /* Just print the first byte as a .byte instruction. */
12011 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12012 (unsigned int) priv
.the_buffer
[0]);
12022 sizeflag
= priv
.orig_sizeflag
;
12024 if (!ckprefix () || rex_used
)
12026 /* Too many prefixes or unused REX prefixes. */
12028 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12030 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12032 prefix_name (all_prefixes
[i
], sizeflag
));
12036 insn_codep
= codep
;
12038 FETCH_DATA (info
, codep
+ 1);
12039 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12041 if (((prefixes
& PREFIX_FWAIT
)
12042 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12044 /* Handle prefixes before fwait. */
12045 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12047 (*info
->fprintf_func
) (info
->stream
, "%s ",
12048 prefix_name (all_prefixes
[i
], sizeflag
));
12049 (*info
->fprintf_func
) (info
->stream
, "fwait");
12053 if (*codep
== 0x0f)
12055 unsigned char threebyte
;
12058 FETCH_DATA (info
, codep
+ 1);
12059 threebyte
= *codep
;
12060 dp
= &dis386_twobyte
[threebyte
];
12061 need_modrm
= twobyte_has_modrm
[*codep
];
12066 dp
= &dis386
[*codep
];
12067 need_modrm
= onebyte_has_modrm
[*codep
];
12071 /* Save sizeflag for printing the extra prefixes later before updating
12072 it for mnemonic and operand processing. The prefix names depend
12073 only on the address mode. */
12074 orig_sizeflag
= sizeflag
;
12075 if (prefixes
& PREFIX_ADDR
)
12077 if ((prefixes
& PREFIX_DATA
))
12083 FETCH_DATA (info
, codep
+ 1);
12084 modrm
.mod
= (*codep
>> 6) & 3;
12085 modrm
.reg
= (*codep
>> 3) & 7;
12086 modrm
.rm
= *codep
& 7;
12092 memset (&vex
, 0, sizeof (vex
));
12094 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12096 get_sib (info
, sizeflag
);
12097 dofloat (sizeflag
);
12101 dp
= get_valid_dis386 (dp
, info
);
12102 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12104 get_sib (info
, sizeflag
);
12105 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12108 op_ad
= MAX_OPERANDS
- 1 - i
;
12110 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12111 /* For EVEX instruction after the last operand masking
12112 should be printed. */
12113 if (i
== 0 && vex
.evex
)
12115 /* Don't print {%k0}. */
12116 if (vex
.mask_register_specifier
)
12119 oappend (names_mask
[vex
.mask_register_specifier
]);
12129 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12130 are all 0s in inverted form. */
12131 if (need_vex
&& vex
.register_specifier
!= 0)
12133 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12134 return end_codep
- priv
.the_buffer
;
12137 /* Check if the REX prefix is used. */
12138 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12139 all_prefixes
[last_rex_prefix
] = 0;
12141 /* Check if the SEG prefix is used. */
12142 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12143 | PREFIX_FS
| PREFIX_GS
)) != 0
12144 && (used_prefixes
& active_seg_prefix
) != 0)
12145 all_prefixes
[last_seg_prefix
] = 0;
12147 /* Check if the ADDR prefix is used. */
12148 if ((prefixes
& PREFIX_ADDR
) != 0
12149 && (used_prefixes
& PREFIX_ADDR
) != 0)
12150 all_prefixes
[last_addr_prefix
] = 0;
12152 /* Check if the DATA prefix is used. */
12153 if ((prefixes
& PREFIX_DATA
) != 0
12154 && (used_prefixes
& PREFIX_DATA
) != 0)
12155 all_prefixes
[last_data_prefix
] = 0;
12157 /* Print the extra prefixes. */
12159 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12160 if (all_prefixes
[i
])
12163 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12166 prefix_length
+= strlen (name
) + 1;
12167 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12170 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12171 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12172 used by putop and MMX/SSE operand and may be overriden by the
12173 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12175 if (dp
->prefix_requirement
== PREFIX_OPCODE
12176 && dp
!= &bad_opcode
12178 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12180 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12182 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12184 && (used_prefixes
& PREFIX_DATA
) == 0))))
12186 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12187 return end_codep
- priv
.the_buffer
;
12190 /* Check maximum code length. */
12191 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12193 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12194 return MAX_CODE_LENGTH
;
12197 obufp
= mnemonicendp
;
12198 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12201 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12203 /* The enter and bound instructions are printed with operands in the same
12204 order as the intel book; everything else is printed in reverse order. */
12205 if (intel_syntax
|| two_source_ops
)
12209 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12210 op_txt
[i
] = op_out
[i
];
12212 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12213 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12215 op_txt
[2] = op_out
[3];
12216 op_txt
[3] = op_out
[2];
12219 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12221 op_ad
= op_index
[i
];
12222 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12223 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12224 riprel
= op_riprel
[i
];
12225 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12226 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12231 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12232 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12236 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12240 (*info
->fprintf_func
) (info
->stream
, ",");
12241 if (op_index
[i
] != -1 && !op_riprel
[i
])
12242 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12244 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12248 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12249 if (op_index
[i
] != -1 && op_riprel
[i
])
12251 (*info
->fprintf_func
) (info
->stream
, " # ");
12252 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12253 + op_address
[op_index
[i
]]), info
);
12256 return codep
- priv
.the_buffer
;
12259 static const char *float_mem
[] = {
12334 static const unsigned char float_mem_mode
[] = {
12409 #define ST { OP_ST, 0 }
12410 #define STi { OP_STi, 0 }
12412 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12413 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12414 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12415 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12416 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12417 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12418 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12419 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12420 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12422 static const struct dis386 float_reg
[][8] = {
12425 { "fadd", { ST
, STi
}, 0 },
12426 { "fmul", { ST
, STi
}, 0 },
12427 { "fcom", { STi
}, 0 },
12428 { "fcomp", { STi
}, 0 },
12429 { "fsub", { ST
, STi
}, 0 },
12430 { "fsubr", { ST
, STi
}, 0 },
12431 { "fdiv", { ST
, STi
}, 0 },
12432 { "fdivr", { ST
, STi
}, 0 },
12436 { "fld", { STi
}, 0 },
12437 { "fxch", { STi
}, 0 },
12447 { "fcmovb", { ST
, STi
}, 0 },
12448 { "fcmove", { ST
, STi
}, 0 },
12449 { "fcmovbe",{ ST
, STi
}, 0 },
12450 { "fcmovu", { ST
, STi
}, 0 },
12458 { "fcmovnb",{ ST
, STi
}, 0 },
12459 { "fcmovne",{ ST
, STi
}, 0 },
12460 { "fcmovnbe",{ ST
, STi
}, 0 },
12461 { "fcmovnu",{ ST
, STi
}, 0 },
12463 { "fucomi", { ST
, STi
}, 0 },
12464 { "fcomi", { ST
, STi
}, 0 },
12469 { "fadd", { STi
, ST
}, 0 },
12470 { "fmul", { STi
, ST
}, 0 },
12473 { "fsub{!M|r}", { STi
, ST
}, 0 },
12474 { "fsub{M|}", { STi
, ST
}, 0 },
12475 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12476 { "fdiv{M|}", { STi
, ST
}, 0 },
12480 { "ffree", { STi
}, 0 },
12482 { "fst", { STi
}, 0 },
12483 { "fstp", { STi
}, 0 },
12484 { "fucom", { STi
}, 0 },
12485 { "fucomp", { STi
}, 0 },
12491 { "faddp", { STi
, ST
}, 0 },
12492 { "fmulp", { STi
, ST
}, 0 },
12495 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12496 { "fsub{M|}p", { STi
, ST
}, 0 },
12497 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12498 { "fdiv{M|}p", { STi
, ST
}, 0 },
12502 { "ffreep", { STi
}, 0 },
12507 { "fucomip", { ST
, STi
}, 0 },
12508 { "fcomip", { ST
, STi
}, 0 },
12513 static char *fgrps
[][8] = {
12516 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12521 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12526 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12531 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12536 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12541 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12546 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12551 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12552 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12557 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12562 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12567 swap_operand (void)
12569 mnemonicendp
[0] = '.';
12570 mnemonicendp
[1] = 's';
12575 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12576 int sizeflag ATTRIBUTE_UNUSED
)
12578 /* Skip mod/rm byte. */
12584 dofloat (int sizeflag
)
12586 const struct dis386
*dp
;
12587 unsigned char floatop
;
12589 floatop
= codep
[-1];
12591 if (modrm
.mod
!= 3)
12593 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12595 putop (float_mem
[fp_indx
], sizeflag
);
12598 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12601 /* Skip mod/rm byte. */
12605 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12606 if (dp
->name
== NULL
)
12608 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12610 /* Instruction fnstsw is only one with strange arg. */
12611 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12612 strcpy (op_out
[0], names16
[0]);
12616 putop (dp
->name
, sizeflag
);
12621 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12626 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12630 /* Like oappend (below), but S is a string starting with '%'.
12631 In Intel syntax, the '%' is elided. */
12633 oappend_maybe_intel (const char *s
)
12635 oappend (s
+ intel_syntax
);
12639 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12641 oappend_maybe_intel ("%st");
12645 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12647 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12648 oappend_maybe_intel (scratchbuf
);
12651 /* Capital letters in template are macros. */
12653 putop (const char *in_template
, int sizeflag
)
12658 unsigned int l
= 0, len
= 1;
12661 #define SAVE_LAST(c) \
12662 if (l < len && l < sizeof (last)) \
12667 for (p
= in_template
; *p
; p
++)
12683 while (*++p
!= '|')
12684 if (*p
== '}' || *p
== '\0')
12687 /* Fall through. */
12692 while (*++p
!= '}')
12703 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12707 if (l
== 0 && len
== 1)
12712 if (sizeflag
& SUFFIX_ALWAYS
)
12725 if (address_mode
== mode_64bit
12726 && !(prefixes
& PREFIX_ADDR
))
12737 if (intel_syntax
&& !alt
)
12739 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12741 if (sizeflag
& DFLAG
)
12742 *obufp
++ = intel_syntax
? 'd' : 'l';
12744 *obufp
++ = intel_syntax
? 'w' : 's';
12745 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12749 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12752 if (modrm
.mod
== 3)
12758 if (sizeflag
& DFLAG
)
12759 *obufp
++ = intel_syntax
? 'd' : 'l';
12762 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12768 case 'E': /* For jcxz/jecxz */
12769 if (address_mode
== mode_64bit
)
12771 if (sizeflag
& AFLAG
)
12777 if (sizeflag
& AFLAG
)
12779 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12784 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12786 if (sizeflag
& AFLAG
)
12787 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12789 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12790 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12794 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12796 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12800 if (!(rex
& REX_W
))
12801 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12806 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12807 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12809 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12812 if (prefixes
& PREFIX_DS
)
12831 if (l
!= 0 || len
!= 1)
12833 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12838 if (!need_vex
|| !vex
.evex
)
12841 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12843 switch (vex
.length
)
12861 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12866 /* Fall through. */
12869 if (l
!= 0 || len
!= 1)
12877 if (sizeflag
& SUFFIX_ALWAYS
)
12881 if (intel_mnemonic
!= cond
)
12885 if ((prefixes
& PREFIX_FWAIT
) == 0)
12888 used_prefixes
|= PREFIX_FWAIT
;
12894 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12898 if (!(rex
& REX_W
))
12899 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12903 && address_mode
== mode_64bit
12904 && isa64
== intel64
)
12909 /* Fall through. */
12912 && address_mode
== mode_64bit
12913 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12918 /* Fall through. */
12921 if (l
== 0 && len
== 1)
12926 if ((rex
& REX_W
) == 0
12927 && (prefixes
& PREFIX_DATA
))
12929 if ((sizeflag
& DFLAG
) == 0)
12931 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12935 if ((prefixes
& PREFIX_DATA
)
12937 || (sizeflag
& SUFFIX_ALWAYS
))
12944 if (sizeflag
& DFLAG
)
12948 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12954 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12960 if ((prefixes
& PREFIX_DATA
)
12962 || (sizeflag
& SUFFIX_ALWAYS
))
12969 if (sizeflag
& DFLAG
)
12970 *obufp
++ = intel_syntax
? 'd' : 'l';
12973 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12981 if (address_mode
== mode_64bit
12982 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12984 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12988 /* Fall through. */
12991 if (l
== 0 && len
== 1)
12994 if (intel_syntax
&& !alt
)
12997 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13003 if (sizeflag
& DFLAG
)
13004 *obufp
++ = intel_syntax
? 'd' : 'l';
13007 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13013 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13019 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13034 else if (sizeflag
& DFLAG
)
13043 if (intel_syntax
&& !p
[1]
13044 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13046 if (!(rex
& REX_W
))
13047 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13050 if (l
== 0 && len
== 1)
13054 if (address_mode
== mode_64bit
13055 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13057 if (sizeflag
& SUFFIX_ALWAYS
)
13079 /* Fall through. */
13082 if (l
== 0 && len
== 1)
13087 if (sizeflag
& SUFFIX_ALWAYS
)
13093 if (sizeflag
& DFLAG
)
13097 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13111 if (address_mode
== mode_64bit
13112 && !(prefixes
& PREFIX_ADDR
))
13123 if (l
!= 0 || len
!= 1)
13128 if (need_vex
&& vex
.prefix
)
13130 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13137 if (prefixes
& PREFIX_DATA
)
13141 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13145 if (l
== 0 && len
== 1)
13149 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13157 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13159 switch (vex
.length
)
13175 if (l
== 0 && len
== 1)
13177 /* operand size flag for cwtl, cbtw */
13186 else if (sizeflag
& DFLAG
)
13190 if (!(rex
& REX_W
))
13191 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13198 && last
[0] != 'L'))
13205 if (last
[0] == 'X')
13206 *obufp
++ = vex
.w
? 'd': 's';
13208 *obufp
++ = vex
.w
? 'q': 'd';
13214 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13216 if (sizeflag
& DFLAG
)
13220 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13226 if (address_mode
== mode_64bit
13227 && (isa64
== intel64
13228 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13230 else if ((prefixes
& PREFIX_DATA
))
13232 if (!(sizeflag
& DFLAG
))
13234 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13241 mnemonicendp
= obufp
;
13246 oappend (const char *s
)
13248 obufp
= stpcpy (obufp
, s
);
13254 /* Only print the active segment register. */
13255 if (!active_seg_prefix
)
13258 used_prefixes
|= active_seg_prefix
;
13259 switch (active_seg_prefix
)
13262 oappend_maybe_intel ("%cs:");
13265 oappend_maybe_intel ("%ds:");
13268 oappend_maybe_intel ("%ss:");
13271 oappend_maybe_intel ("%es:");
13274 oappend_maybe_intel ("%fs:");
13277 oappend_maybe_intel ("%gs:");
13285 OP_indirE (int bytemode
, int sizeflag
)
13289 OP_E (bytemode
, sizeflag
);
13293 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13295 if (address_mode
== mode_64bit
)
13303 sprintf_vma (tmp
, disp
);
13304 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13305 strcpy (buf
+ 2, tmp
+ i
);
13309 bfd_signed_vma v
= disp
;
13316 /* Check for possible overflow on 0x8000000000000000. */
13319 strcpy (buf
, "9223372036854775808");
13333 tmp
[28 - i
] = (v
% 10) + '0';
13337 strcpy (buf
, tmp
+ 29 - i
);
13343 sprintf (buf
, "0x%x", (unsigned int) disp
);
13345 sprintf (buf
, "%d", (int) disp
);
13349 /* Put DISP in BUF as signed hex number. */
13352 print_displacement (char *buf
, bfd_vma disp
)
13354 bfd_signed_vma val
= disp
;
13363 /* Check for possible overflow. */
13366 switch (address_mode
)
13369 strcpy (buf
+ j
, "0x8000000000000000");
13372 strcpy (buf
+ j
, "0x80000000");
13375 strcpy (buf
+ j
, "0x8000");
13385 sprintf_vma (tmp
, (bfd_vma
) val
);
13386 for (i
= 0; tmp
[i
] == '0'; i
++)
13388 if (tmp
[i
] == '\0')
13390 strcpy (buf
+ j
, tmp
+ i
);
13394 intel_operand_size (int bytemode
, int sizeflag
)
13398 && (bytemode
== x_mode
13399 || bytemode
== evex_half_bcst_xmmq_mode
))
13402 oappend ("QWORD PTR ");
13404 oappend ("DWORD PTR ");
13413 oappend ("BYTE PTR ");
13418 oappend ("WORD PTR ");
13421 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13423 oappend ("QWORD PTR ");
13426 /* Fall through. */
13428 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13430 oappend ("QWORD PTR ");
13433 /* Fall through. */
13439 oappend ("QWORD PTR ");
13442 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13443 oappend ("DWORD PTR ");
13445 oappend ("WORD PTR ");
13446 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13450 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13452 oappend ("WORD PTR ");
13453 if (!(rex
& REX_W
))
13454 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13457 if (sizeflag
& DFLAG
)
13458 oappend ("QWORD PTR ");
13460 oappend ("DWORD PTR ");
13461 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13464 case d_scalar_mode
:
13465 case d_scalar_swap_mode
:
13468 oappend ("DWORD PTR ");
13471 case q_scalar_mode
:
13472 case q_scalar_swap_mode
:
13474 oappend ("QWORD PTR ");
13477 if (address_mode
== mode_64bit
)
13478 oappend ("QWORD PTR ");
13480 oappend ("DWORD PTR ");
13483 if (sizeflag
& DFLAG
)
13484 oappend ("FWORD PTR ");
13486 oappend ("DWORD PTR ");
13487 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13490 oappend ("TBYTE PTR ");
13494 case evex_x_gscat_mode
:
13495 case evex_x_nobcst_mode
:
13496 case b_scalar_mode
:
13497 case w_scalar_mode
:
13500 switch (vex
.length
)
13503 oappend ("XMMWORD PTR ");
13506 oappend ("YMMWORD PTR ");
13509 oappend ("ZMMWORD PTR ");
13516 oappend ("XMMWORD PTR ");
13519 oappend ("XMMWORD PTR ");
13522 oappend ("YMMWORD PTR ");
13525 case evex_half_bcst_xmmq_mode
:
13529 switch (vex
.length
)
13532 oappend ("QWORD PTR ");
13535 oappend ("XMMWORD PTR ");
13538 oappend ("YMMWORD PTR ");
13548 switch (vex
.length
)
13553 oappend ("BYTE PTR ");
13563 switch (vex
.length
)
13568 oappend ("WORD PTR ");
13578 switch (vex
.length
)
13583 oappend ("DWORD PTR ");
13593 switch (vex
.length
)
13598 oappend ("QWORD PTR ");
13608 switch (vex
.length
)
13611 oappend ("WORD PTR ");
13614 oappend ("DWORD PTR ");
13617 oappend ("QWORD PTR ");
13627 switch (vex
.length
)
13630 oappend ("DWORD PTR ");
13633 oappend ("QWORD PTR ");
13636 oappend ("XMMWORD PTR ");
13646 switch (vex
.length
)
13649 oappend ("QWORD PTR ");
13652 oappend ("YMMWORD PTR ");
13655 oappend ("ZMMWORD PTR ");
13665 switch (vex
.length
)
13669 oappend ("XMMWORD PTR ");
13676 oappend ("OWORD PTR ");
13679 case vex_w_dq_mode
:
13680 case vex_scalar_w_dq_mode
:
13685 oappend ("QWORD PTR ");
13687 oappend ("DWORD PTR ");
13689 case vex_vsib_d_w_dq_mode
:
13690 case vex_vsib_q_w_dq_mode
:
13697 oappend ("QWORD PTR ");
13699 oappend ("DWORD PTR ");
13703 switch (vex
.length
)
13706 oappend ("XMMWORD PTR ");
13709 oappend ("YMMWORD PTR ");
13712 oappend ("ZMMWORD PTR ");
13719 case vex_vsib_q_w_d_mode
:
13720 case vex_vsib_d_w_d_mode
:
13721 if (!need_vex
|| !vex
.evex
)
13724 switch (vex
.length
)
13727 oappend ("QWORD PTR ");
13730 oappend ("XMMWORD PTR ");
13733 oappend ("YMMWORD PTR ");
13741 if (!need_vex
|| vex
.length
!= 128)
13744 oappend ("DWORD PTR ");
13746 oappend ("BYTE PTR ");
13752 oappend ("QWORD PTR ");
13754 oappend ("WORD PTR ");
13764 OP_E_register (int bytemode
, int sizeflag
)
13766 int reg
= modrm
.rm
;
13767 const char **names
;
13773 if ((sizeflag
& SUFFIX_ALWAYS
)
13774 && (bytemode
== b_swap_mode
13775 || bytemode
== bnd_swap_mode
13776 || bytemode
== v_swap_mode
))
13802 names
= address_mode
== mode_64bit
? names64
: names32
;
13805 case bnd_swap_mode
:
13814 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13819 /* Fall through. */
13821 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13827 /* Fall through. */
13839 if ((sizeflag
& DFLAG
)
13840 || (bytemode
!= v_mode
13841 && bytemode
!= v_swap_mode
))
13845 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13849 names
= (address_mode
== mode_64bit
13850 ? names64
: names32
);
13851 if (!(prefixes
& PREFIX_ADDR
))
13852 names
= (address_mode
== mode_16bit
13853 ? names16
: names
);
13856 /* Remove "addr16/addr32". */
13857 all_prefixes
[last_addr_prefix
] = 0;
13858 names
= (address_mode
!= mode_32bit
13859 ? names32
: names16
);
13860 used_prefixes
|= PREFIX_ADDR
;
13870 names
= names_mask
;
13875 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13878 oappend (names
[reg
]);
13882 OP_E_memory (int bytemode
, int sizeflag
)
13885 int add
= (rex
& REX_B
) ? 8 : 0;
13891 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13893 && bytemode
!= x_mode
13894 && bytemode
!= xmmq_mode
13895 && bytemode
!= evex_half_bcst_xmmq_mode
)
13911 if (address_mode
!= mode_64bit
)
13917 case vex_vsib_d_w_dq_mode
:
13918 case vex_vsib_d_w_d_mode
:
13919 case vex_vsib_q_w_dq_mode
:
13920 case vex_vsib_q_w_d_mode
:
13921 case evex_x_gscat_mode
:
13923 shift
= vex
.w
? 3 : 2;
13926 case evex_half_bcst_xmmq_mode
:
13930 shift
= vex
.w
? 3 : 2;
13933 /* Fall through. */
13937 case evex_x_nobcst_mode
:
13939 switch (vex
.length
)
13962 case q_scalar_mode
:
13964 case q_scalar_swap_mode
:
13970 case d_scalar_mode
:
13972 case d_scalar_swap_mode
:
13975 case w_scalar_mode
:
13979 case b_scalar_mode
:
13986 /* Make necessary corrections to shift for modes that need it.
13987 For these modes we currently have shift 4, 5 or 6 depending on
13988 vex.length (it corresponds to xmmword, ymmword or zmmword
13989 operand). We might want to make it 3, 4 or 5 (e.g. for
13990 xmmq_mode). In case of broadcast enabled the corrections
13991 aren't needed, as element size is always 32 or 64 bits. */
13993 && (bytemode
== xmmq_mode
13994 || bytemode
== evex_half_bcst_xmmq_mode
))
13996 else if (bytemode
== xmmqd_mode
)
13998 else if (bytemode
== xmmdw_mode
)
14000 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14008 intel_operand_size (bytemode
, sizeflag
);
14011 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14013 /* 32/64 bit address mode */
14023 int addr32flag
= !((sizeflag
& AFLAG
)
14024 || bytemode
== v_bnd_mode
14025 || bytemode
== v_bndmk_mode
14026 || bytemode
== bnd_mode
14027 || bytemode
== bnd_swap_mode
);
14028 const char **indexes64
= names64
;
14029 const char **indexes32
= names32
;
14039 vindex
= sib
.index
;
14045 case vex_vsib_d_w_dq_mode
:
14046 case vex_vsib_d_w_d_mode
:
14047 case vex_vsib_q_w_dq_mode
:
14048 case vex_vsib_q_w_d_mode
:
14058 switch (vex
.length
)
14061 indexes64
= indexes32
= names_xmm
;
14065 || bytemode
== vex_vsib_q_w_dq_mode
14066 || bytemode
== vex_vsib_q_w_d_mode
)
14067 indexes64
= indexes32
= names_ymm
;
14069 indexes64
= indexes32
= names_xmm
;
14073 || bytemode
== vex_vsib_q_w_dq_mode
14074 || bytemode
== vex_vsib_q_w_d_mode
)
14075 indexes64
= indexes32
= names_zmm
;
14077 indexes64
= indexes32
= names_ymm
;
14084 haveindex
= vindex
!= 4;
14091 rbase
= base
+ add
;
14099 if (address_mode
== mode_64bit
&& !havesib
)
14102 if (riprel
&& bytemode
== v_bndmk_mode
)
14110 FETCH_DATA (the_info
, codep
+ 1);
14112 if ((disp
& 0x80) != 0)
14114 if (vex
.evex
&& shift
> 0)
14127 && address_mode
!= mode_16bit
)
14129 if (address_mode
== mode_64bit
)
14131 /* Display eiz instead of addr32. */
14132 needindex
= addr32flag
;
14137 /* In 32-bit mode, we need index register to tell [offset]
14138 from [eiz*1 + offset]. */
14143 havedisp
= (havebase
14145 || (havesib
&& (haveindex
|| scale
!= 0)));
14148 if (modrm
.mod
!= 0 || base
== 5)
14150 if (havedisp
|| riprel
)
14151 print_displacement (scratchbuf
, disp
);
14153 print_operand_value (scratchbuf
, 1, disp
);
14154 oappend (scratchbuf
);
14158 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14162 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14163 && (bytemode
!= v_bnd_mode
)
14164 && (bytemode
!= v_bndmk_mode
)
14165 && (bytemode
!= bnd_mode
)
14166 && (bytemode
!= bnd_swap_mode
))
14167 used_prefixes
|= PREFIX_ADDR
;
14169 if (havedisp
|| (intel_syntax
&& riprel
))
14171 *obufp
++ = open_char
;
14172 if (intel_syntax
&& riprel
)
14175 oappend (!addr32flag
? "rip" : "eip");
14179 oappend (address_mode
== mode_64bit
&& !addr32flag
14180 ? names64
[rbase
] : names32
[rbase
]);
14183 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14184 print index to tell base + index from base. */
14188 || (havebase
&& base
!= ESP_REG_NUM
))
14190 if (!intel_syntax
|| havebase
)
14192 *obufp
++ = separator_char
;
14196 oappend (address_mode
== mode_64bit
&& !addr32flag
14197 ? indexes64
[vindex
] : indexes32
[vindex
]);
14199 oappend (address_mode
== mode_64bit
&& !addr32flag
14200 ? index64
: index32
);
14202 *obufp
++ = scale_char
;
14204 sprintf (scratchbuf
, "%d", 1 << scale
);
14205 oappend (scratchbuf
);
14209 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14211 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14216 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14220 disp
= - (bfd_signed_vma
) disp
;
14224 print_displacement (scratchbuf
, disp
);
14226 print_operand_value (scratchbuf
, 1, disp
);
14227 oappend (scratchbuf
);
14230 *obufp
++ = close_char
;
14233 else if (intel_syntax
)
14235 if (modrm
.mod
!= 0 || base
== 5)
14237 if (!active_seg_prefix
)
14239 oappend (names_seg
[ds_reg
- es_reg
]);
14242 print_operand_value (scratchbuf
, 1, disp
);
14243 oappend (scratchbuf
);
14249 /* 16 bit address mode */
14250 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14257 if ((disp
& 0x8000) != 0)
14262 FETCH_DATA (the_info
, codep
+ 1);
14264 if ((disp
& 0x80) != 0)
14266 if (vex
.evex
&& shift
> 0)
14271 if ((disp
& 0x8000) != 0)
14277 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14279 print_displacement (scratchbuf
, disp
);
14280 oappend (scratchbuf
);
14283 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14285 *obufp
++ = open_char
;
14287 oappend (index16
[modrm
.rm
]);
14289 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14291 if ((bfd_signed_vma
) disp
>= 0)
14296 else if (modrm
.mod
!= 1)
14300 disp
= - (bfd_signed_vma
) disp
;
14303 print_displacement (scratchbuf
, disp
);
14304 oappend (scratchbuf
);
14307 *obufp
++ = close_char
;
14310 else if (intel_syntax
)
14312 if (!active_seg_prefix
)
14314 oappend (names_seg
[ds_reg
- es_reg
]);
14317 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14318 oappend (scratchbuf
);
14321 if (vex
.evex
&& vex
.b
14322 && (bytemode
== x_mode
14323 || bytemode
== xmmq_mode
14324 || bytemode
== evex_half_bcst_xmmq_mode
))
14327 || bytemode
== xmmq_mode
14328 || bytemode
== evex_half_bcst_xmmq_mode
)
14330 switch (vex
.length
)
14333 oappend ("{1to2}");
14336 oappend ("{1to4}");
14339 oappend ("{1to8}");
14347 switch (vex
.length
)
14350 oappend ("{1to4}");
14353 oappend ("{1to8}");
14356 oappend ("{1to16}");
14366 OP_E (int bytemode
, int sizeflag
)
14368 /* Skip mod/rm byte. */
14372 if (modrm
.mod
== 3)
14373 OP_E_register (bytemode
, sizeflag
);
14375 OP_E_memory (bytemode
, sizeflag
);
14379 OP_G (int bytemode
, int sizeflag
)
14382 const char **names
;
14391 oappend (names8rex
[modrm
.reg
+ add
]);
14393 oappend (names8
[modrm
.reg
+ add
]);
14396 oappend (names16
[modrm
.reg
+ add
]);
14401 oappend (names32
[modrm
.reg
+ add
]);
14404 oappend (names64
[modrm
.reg
+ add
]);
14407 if (modrm
.reg
> 0x3)
14412 oappend (names_bnd
[modrm
.reg
]);
14421 oappend (names64
[modrm
.reg
+ add
]);
14424 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14425 oappend (names32
[modrm
.reg
+ add
]);
14427 oappend (names16
[modrm
.reg
+ add
]);
14428 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14432 names
= (address_mode
== mode_64bit
14433 ? names64
: names32
);
14434 if (!(prefixes
& PREFIX_ADDR
))
14436 if (address_mode
== mode_16bit
)
14441 /* Remove "addr16/addr32". */
14442 all_prefixes
[last_addr_prefix
] = 0;
14443 names
= (address_mode
!= mode_32bit
14444 ? names32
: names16
);
14445 used_prefixes
|= PREFIX_ADDR
;
14447 oappend (names
[modrm
.reg
+ add
]);
14450 if (address_mode
== mode_64bit
)
14451 oappend (names64
[modrm
.reg
+ add
]);
14453 oappend (names32
[modrm
.reg
+ add
]);
14457 if ((modrm
.reg
+ add
) > 0x7)
14462 oappend (names_mask
[modrm
.reg
+ add
]);
14465 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14478 FETCH_DATA (the_info
, codep
+ 8);
14479 a
= *codep
++ & 0xff;
14480 a
|= (*codep
++ & 0xff) << 8;
14481 a
|= (*codep
++ & 0xff) << 16;
14482 a
|= (*codep
++ & 0xffu
) << 24;
14483 b
= *codep
++ & 0xff;
14484 b
|= (*codep
++ & 0xff) << 8;
14485 b
|= (*codep
++ & 0xff) << 16;
14486 b
|= (*codep
++ & 0xffu
) << 24;
14487 x
= a
+ ((bfd_vma
) b
<< 32);
14495 static bfd_signed_vma
14498 bfd_signed_vma x
= 0;
14500 FETCH_DATA (the_info
, codep
+ 4);
14501 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14502 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14503 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14504 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14508 static bfd_signed_vma
14511 bfd_signed_vma x
= 0;
14513 FETCH_DATA (the_info
, codep
+ 4);
14514 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14515 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14516 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14517 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14519 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14529 FETCH_DATA (the_info
, codep
+ 2);
14530 x
= *codep
++ & 0xff;
14531 x
|= (*codep
++ & 0xff) << 8;
14536 set_op (bfd_vma op
, int riprel
)
14538 op_index
[op_ad
] = op_ad
;
14539 if (address_mode
== mode_64bit
)
14541 op_address
[op_ad
] = op
;
14542 op_riprel
[op_ad
] = riprel
;
14546 /* Mask to get a 32-bit address. */
14547 op_address
[op_ad
] = op
& 0xffffffff;
14548 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14553 OP_REG (int code
, int sizeflag
)
14560 case es_reg
: case ss_reg
: case cs_reg
:
14561 case ds_reg
: case fs_reg
: case gs_reg
:
14562 oappend (names_seg
[code
- es_reg
]);
14574 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14575 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14576 s
= names16
[code
- ax_reg
+ add
];
14578 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14579 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14582 s
= names8rex
[code
- al_reg
+ add
];
14584 s
= names8
[code
- al_reg
];
14586 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14587 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14588 if (address_mode
== mode_64bit
14589 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14591 s
= names64
[code
- rAX_reg
+ add
];
14594 code
+= eAX_reg
- rAX_reg
;
14595 /* Fall through. */
14596 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14597 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14600 s
= names64
[code
- eAX_reg
+ add
];
14603 if (sizeflag
& DFLAG
)
14604 s
= names32
[code
- eAX_reg
+ add
];
14606 s
= names16
[code
- eAX_reg
+ add
];
14607 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14611 s
= INTERNAL_DISASSEMBLER_ERROR
;
14618 OP_IMREG (int code
, int sizeflag
)
14630 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14631 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14632 s
= names16
[code
- ax_reg
];
14634 case es_reg
: case ss_reg
: case cs_reg
:
14635 case ds_reg
: case fs_reg
: case gs_reg
:
14636 s
= names_seg
[code
- es_reg
];
14638 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14639 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14642 s
= names8rex
[code
- al_reg
];
14644 s
= names8
[code
- al_reg
];
14646 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14647 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14650 s
= names64
[code
- eAX_reg
];
14653 if (sizeflag
& DFLAG
)
14654 s
= names32
[code
- eAX_reg
];
14656 s
= names16
[code
- eAX_reg
];
14657 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14660 case z_mode_ax_reg
:
14661 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14665 if (!(rex
& REX_W
))
14666 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14669 s
= INTERNAL_DISASSEMBLER_ERROR
;
14676 OP_I (int bytemode
, int sizeflag
)
14679 bfd_signed_vma mask
= -1;
14684 FETCH_DATA (the_info
, codep
+ 1);
14694 if (sizeflag
& DFLAG
)
14704 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14720 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14725 scratchbuf
[0] = '$';
14726 print_operand_value (scratchbuf
+ 1, 1, op
);
14727 oappend_maybe_intel (scratchbuf
);
14728 scratchbuf
[0] = '\0';
14732 OP_I64 (int bytemode
, int sizeflag
)
14734 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14736 OP_I (bytemode
, sizeflag
);
14742 scratchbuf
[0] = '$';
14743 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14744 oappend_maybe_intel (scratchbuf
);
14745 scratchbuf
[0] = '\0';
14749 OP_sI (int bytemode
, int sizeflag
)
14757 FETCH_DATA (the_info
, codep
+ 1);
14759 if ((op
& 0x80) != 0)
14761 if (bytemode
== b_T_mode
)
14763 if (address_mode
!= mode_64bit
14764 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14766 /* The operand-size prefix is overridden by a REX prefix. */
14767 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14775 if (!(rex
& REX_W
))
14777 if (sizeflag
& DFLAG
)
14785 /* The operand-size prefix is overridden by a REX prefix. */
14786 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14792 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14796 scratchbuf
[0] = '$';
14797 print_operand_value (scratchbuf
+ 1, 1, op
);
14798 oappend_maybe_intel (scratchbuf
);
14802 OP_J (int bytemode
, int sizeflag
)
14806 bfd_vma segment
= 0;
14811 FETCH_DATA (the_info
, codep
+ 1);
14813 if ((disp
& 0x80) != 0)
14817 if (isa64
== amd64
)
14819 if ((sizeflag
& DFLAG
)
14820 || (address_mode
== mode_64bit
14821 && (isa64
!= amd64
|| (rex
& REX_W
))))
14826 if ((disp
& 0x8000) != 0)
14828 /* In 16bit mode, address is wrapped around at 64k within
14829 the same segment. Otherwise, a data16 prefix on a jump
14830 instruction means that the pc is masked to 16 bits after
14831 the displacement is added! */
14833 if ((prefixes
& PREFIX_DATA
) == 0)
14834 segment
= ((start_pc
+ (codep
- start_codep
))
14835 & ~((bfd_vma
) 0xffff));
14837 if (address_mode
!= mode_64bit
14838 || (isa64
== amd64
&& !(rex
& REX_W
)))
14839 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14842 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14845 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14847 print_operand_value (scratchbuf
, 1, disp
);
14848 oappend (scratchbuf
);
14852 OP_SEG (int bytemode
, int sizeflag
)
14854 if (bytemode
== w_mode
)
14855 oappend (names_seg
[modrm
.reg
]);
14857 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14861 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14865 if (sizeflag
& DFLAG
)
14875 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14877 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14879 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14880 oappend (scratchbuf
);
14884 OP_OFF (int bytemode
, int sizeflag
)
14888 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14889 intel_operand_size (bytemode
, sizeflag
);
14892 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14899 if (!active_seg_prefix
)
14901 oappend (names_seg
[ds_reg
- es_reg
]);
14905 print_operand_value (scratchbuf
, 1, off
);
14906 oappend (scratchbuf
);
14910 OP_OFF64 (int bytemode
, int sizeflag
)
14914 if (address_mode
!= mode_64bit
14915 || (prefixes
& PREFIX_ADDR
))
14917 OP_OFF (bytemode
, sizeflag
);
14921 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14922 intel_operand_size (bytemode
, sizeflag
);
14929 if (!active_seg_prefix
)
14931 oappend (names_seg
[ds_reg
- es_reg
]);
14935 print_operand_value (scratchbuf
, 1, off
);
14936 oappend (scratchbuf
);
14940 ptr_reg (int code
, int sizeflag
)
14944 *obufp
++ = open_char
;
14945 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14946 if (address_mode
== mode_64bit
)
14948 if (!(sizeflag
& AFLAG
))
14949 s
= names32
[code
- eAX_reg
];
14951 s
= names64
[code
- eAX_reg
];
14953 else if (sizeflag
& AFLAG
)
14954 s
= names32
[code
- eAX_reg
];
14956 s
= names16
[code
- eAX_reg
];
14958 *obufp
++ = close_char
;
14963 OP_ESreg (int code
, int sizeflag
)
14969 case 0x6d: /* insw/insl */
14970 intel_operand_size (z_mode
, sizeflag
);
14972 case 0xa5: /* movsw/movsl/movsq */
14973 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14974 case 0xab: /* stosw/stosl */
14975 case 0xaf: /* scasw/scasl */
14976 intel_operand_size (v_mode
, sizeflag
);
14979 intel_operand_size (b_mode
, sizeflag
);
14982 oappend_maybe_intel ("%es:");
14983 ptr_reg (code
, sizeflag
);
14987 OP_DSreg (int code
, int sizeflag
)
14993 case 0x6f: /* outsw/outsl */
14994 intel_operand_size (z_mode
, sizeflag
);
14996 case 0xa5: /* movsw/movsl/movsq */
14997 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14998 case 0xad: /* lodsw/lodsl/lodsq */
14999 intel_operand_size (v_mode
, sizeflag
);
15002 intel_operand_size (b_mode
, sizeflag
);
15005 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15006 default segment register DS is printed. */
15007 if (!active_seg_prefix
)
15008 active_seg_prefix
= PREFIX_DS
;
15010 ptr_reg (code
, sizeflag
);
15014 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15022 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15024 all_prefixes
[last_lock_prefix
] = 0;
15025 used_prefixes
|= PREFIX_LOCK
;
15030 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15031 oappend_maybe_intel (scratchbuf
);
15035 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15044 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15046 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15047 oappend (scratchbuf
);
15051 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15053 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15054 oappend_maybe_intel (scratchbuf
);
15058 OP_R (int bytemode
, int sizeflag
)
15060 /* Skip mod/rm byte. */
15063 OP_E_register (bytemode
, sizeflag
);
15067 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15069 int reg
= modrm
.reg
;
15070 const char **names
;
15072 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15073 if (prefixes
& PREFIX_DATA
)
15082 oappend (names
[reg
]);
15086 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15088 int reg
= modrm
.reg
;
15089 const char **names
;
15101 && bytemode
!= xmm_mode
15102 && bytemode
!= xmmq_mode
15103 && bytemode
!= evex_half_bcst_xmmq_mode
15104 && bytemode
!= ymm_mode
15105 && bytemode
!= scalar_mode
)
15107 switch (vex
.length
)
15114 || (bytemode
!= vex_vsib_q_w_dq_mode
15115 && bytemode
!= vex_vsib_q_w_d_mode
))
15127 else if (bytemode
== xmmq_mode
15128 || bytemode
== evex_half_bcst_xmmq_mode
)
15130 switch (vex
.length
)
15143 else if (bytemode
== ymm_mode
)
15147 oappend (names
[reg
]);
15151 OP_EM (int bytemode
, int sizeflag
)
15154 const char **names
;
15156 if (modrm
.mod
!= 3)
15159 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15161 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15162 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15164 OP_E (bytemode
, sizeflag
);
15168 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15171 /* Skip mod/rm byte. */
15174 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15176 if (prefixes
& PREFIX_DATA
)
15185 oappend (names
[reg
]);
15188 /* cvt* are the only instructions in sse2 which have
15189 both SSE and MMX operands and also have 0x66 prefix
15190 in their opcode. 0x66 was originally used to differentiate
15191 between SSE and MMX instruction(operands). So we have to handle the
15192 cvt* separately using OP_EMC and OP_MXC */
15194 OP_EMC (int bytemode
, int sizeflag
)
15196 if (modrm
.mod
!= 3)
15198 if (intel_syntax
&& bytemode
== v_mode
)
15200 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15201 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15203 OP_E (bytemode
, sizeflag
);
15207 /* Skip mod/rm byte. */
15210 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15211 oappend (names_mm
[modrm
.rm
]);
15215 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15217 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15218 oappend (names_mm
[modrm
.reg
]);
15222 OP_EX (int bytemode
, int sizeflag
)
15225 const char **names
;
15227 /* Skip mod/rm byte. */
15231 if (modrm
.mod
!= 3)
15233 OP_E_memory (bytemode
, sizeflag
);
15248 if ((sizeflag
& SUFFIX_ALWAYS
)
15249 && (bytemode
== x_swap_mode
15250 || bytemode
== d_swap_mode
15251 || bytemode
== d_scalar_swap_mode
15252 || bytemode
== q_swap_mode
15253 || bytemode
== q_scalar_swap_mode
))
15257 && bytemode
!= xmm_mode
15258 && bytemode
!= xmmdw_mode
15259 && bytemode
!= xmmqd_mode
15260 && bytemode
!= xmm_mb_mode
15261 && bytemode
!= xmm_mw_mode
15262 && bytemode
!= xmm_md_mode
15263 && bytemode
!= xmm_mq_mode
15264 && bytemode
!= xmm_mdq_mode
15265 && bytemode
!= xmmq_mode
15266 && bytemode
!= evex_half_bcst_xmmq_mode
15267 && bytemode
!= ymm_mode
15268 && bytemode
!= d_scalar_mode
15269 && bytemode
!= d_scalar_swap_mode
15270 && bytemode
!= q_scalar_mode
15271 && bytemode
!= q_scalar_swap_mode
15272 && bytemode
!= vex_scalar_w_dq_mode
)
15274 switch (vex
.length
)
15289 else if (bytemode
== xmmq_mode
15290 || bytemode
== evex_half_bcst_xmmq_mode
)
15292 switch (vex
.length
)
15305 else if (bytemode
== ymm_mode
)
15309 oappend (names
[reg
]);
15313 OP_MS (int bytemode
, int sizeflag
)
15315 if (modrm
.mod
== 3)
15316 OP_EM (bytemode
, sizeflag
);
15322 OP_XS (int bytemode
, int sizeflag
)
15324 if (modrm
.mod
== 3)
15325 OP_EX (bytemode
, sizeflag
);
15331 OP_M (int bytemode
, int sizeflag
)
15333 if (modrm
.mod
== 3)
15334 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15337 OP_E (bytemode
, sizeflag
);
15341 OP_0f07 (int bytemode
, int sizeflag
)
15343 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15346 OP_E (bytemode
, sizeflag
);
15349 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15350 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15353 NOP_Fixup1 (int bytemode
, int sizeflag
)
15355 if ((prefixes
& PREFIX_DATA
) != 0
15358 && address_mode
== mode_64bit
))
15359 OP_REG (bytemode
, sizeflag
);
15361 strcpy (obuf
, "nop");
15365 NOP_Fixup2 (int bytemode
, int sizeflag
)
15367 if ((prefixes
& PREFIX_DATA
) != 0
15370 && address_mode
== mode_64bit
))
15371 OP_IMREG (bytemode
, sizeflag
);
15374 static const char *const Suffix3DNow
[] = {
15375 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15376 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15377 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15378 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15379 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15380 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15381 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15382 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15383 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15384 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15385 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15386 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15387 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15388 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15389 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15390 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15391 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15392 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15393 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15394 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15395 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15396 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15397 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15398 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15399 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15400 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15401 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15402 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15403 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15404 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15405 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15406 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15407 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15408 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15409 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15410 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15411 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15412 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15413 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15414 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15415 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15416 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15417 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15418 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15419 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15420 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15421 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15422 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15423 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15424 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15425 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15426 /* CC */ NULL
, NULL
, NULL
, NULL
,
15427 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15428 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15429 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15430 /* DC */ NULL
, NULL
, NULL
, NULL
,
15431 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15432 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15433 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15434 /* EC */ NULL
, NULL
, NULL
, NULL
,
15435 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15436 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15437 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15438 /* FC */ NULL
, NULL
, NULL
, NULL
,
15442 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15444 const char *mnemonic
;
15446 FETCH_DATA (the_info
, codep
+ 1);
15447 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15448 place where an 8-bit immediate would normally go. ie. the last
15449 byte of the instruction. */
15450 obufp
= mnemonicendp
;
15451 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15453 oappend (mnemonic
);
15456 /* Since a variable sized modrm/sib chunk is between the start
15457 of the opcode (0x0f0f) and the opcode suffix, we need to do
15458 all the modrm processing first, and don't know until now that
15459 we have a bad opcode. This necessitates some cleaning up. */
15460 op_out
[0][0] = '\0';
15461 op_out
[1][0] = '\0';
15464 mnemonicendp
= obufp
;
15467 static struct op simd_cmp_op
[] =
15469 { STRING_COMMA_LEN ("eq") },
15470 { STRING_COMMA_LEN ("lt") },
15471 { STRING_COMMA_LEN ("le") },
15472 { STRING_COMMA_LEN ("unord") },
15473 { STRING_COMMA_LEN ("neq") },
15474 { STRING_COMMA_LEN ("nlt") },
15475 { STRING_COMMA_LEN ("nle") },
15476 { STRING_COMMA_LEN ("ord") }
15480 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15482 unsigned int cmp_type
;
15484 FETCH_DATA (the_info
, codep
+ 1);
15485 cmp_type
= *codep
++ & 0xff;
15486 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15489 char *p
= mnemonicendp
- 2;
15493 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15494 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15498 /* We have a reserved extension byte. Output it directly. */
15499 scratchbuf
[0] = '$';
15500 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15501 oappend_maybe_intel (scratchbuf
);
15502 scratchbuf
[0] = '\0';
15507 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15508 int sizeflag ATTRIBUTE_UNUSED
)
15510 /* mwaitx %eax,%ecx,%ebx */
15513 const char **names
= (address_mode
== mode_64bit
15514 ? names64
: names32
);
15515 strcpy (op_out
[0], names
[0]);
15516 strcpy (op_out
[1], names
[1]);
15517 strcpy (op_out
[2], names
[3]);
15518 two_source_ops
= 1;
15520 /* Skip mod/rm byte. */
15526 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15527 int sizeflag ATTRIBUTE_UNUSED
)
15529 /* mwait %eax,%ecx */
15532 const char **names
= (address_mode
== mode_64bit
15533 ? names64
: names32
);
15534 strcpy (op_out
[0], names
[0]);
15535 strcpy (op_out
[1], names
[1]);
15536 two_source_ops
= 1;
15538 /* Skip mod/rm byte. */
15544 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15545 int sizeflag ATTRIBUTE_UNUSED
)
15547 /* monitor %eax,%ecx,%edx" */
15550 const char **op1_names
;
15551 const char **names
= (address_mode
== mode_64bit
15552 ? names64
: names32
);
15554 if (!(prefixes
& PREFIX_ADDR
))
15555 op1_names
= (address_mode
== mode_16bit
15556 ? names16
: names
);
15559 /* Remove "addr16/addr32". */
15560 all_prefixes
[last_addr_prefix
] = 0;
15561 op1_names
= (address_mode
!= mode_32bit
15562 ? names32
: names16
);
15563 used_prefixes
|= PREFIX_ADDR
;
15565 strcpy (op_out
[0], op1_names
[0]);
15566 strcpy (op_out
[1], names
[1]);
15567 strcpy (op_out
[2], names
[2]);
15568 two_source_ops
= 1;
15570 /* Skip mod/rm byte. */
15578 /* Throw away prefixes and 1st. opcode byte. */
15579 codep
= insn_codep
+ 1;
15584 REP_Fixup (int bytemode
, int sizeflag
)
15586 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15588 if (prefixes
& PREFIX_REPZ
)
15589 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15596 OP_IMREG (bytemode
, sizeflag
);
15599 OP_ESreg (bytemode
, sizeflag
);
15602 OP_DSreg (bytemode
, sizeflag
);
15610 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15614 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15616 if (prefixes
& PREFIX_REPNZ
)
15617 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15620 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15624 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15625 int sizeflag ATTRIBUTE_UNUSED
)
15627 if (active_seg_prefix
== PREFIX_DS
15628 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15630 /* NOTRACK prefix is only valid on indirect branch instructions.
15631 NB: DATA prefix is unsupported for Intel64. */
15632 active_seg_prefix
= 0;
15633 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15637 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15638 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15642 HLE_Fixup1 (int bytemode
, int sizeflag
)
15645 && (prefixes
& PREFIX_LOCK
) != 0)
15647 if (prefixes
& PREFIX_REPZ
)
15648 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15649 if (prefixes
& PREFIX_REPNZ
)
15650 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15653 OP_E (bytemode
, sizeflag
);
15656 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15657 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15661 HLE_Fixup2 (int bytemode
, int sizeflag
)
15663 if (modrm
.mod
!= 3)
15665 if (prefixes
& PREFIX_REPZ
)
15666 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15667 if (prefixes
& PREFIX_REPNZ
)
15668 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15671 OP_E (bytemode
, sizeflag
);
15674 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15675 "xrelease" for memory operand. No check for LOCK prefix. */
15678 HLE_Fixup3 (int bytemode
, int sizeflag
)
15681 && last_repz_prefix
> last_repnz_prefix
15682 && (prefixes
& PREFIX_REPZ
) != 0)
15683 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15685 OP_E (bytemode
, sizeflag
);
15689 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15694 /* Change cmpxchg8b to cmpxchg16b. */
15695 char *p
= mnemonicendp
- 2;
15696 mnemonicendp
= stpcpy (p
, "16b");
15699 else if ((prefixes
& PREFIX_LOCK
) != 0)
15701 if (prefixes
& PREFIX_REPZ
)
15702 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15703 if (prefixes
& PREFIX_REPNZ
)
15704 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15707 OP_M (bytemode
, sizeflag
);
15711 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15713 const char **names
;
15717 switch (vex
.length
)
15731 oappend (names
[reg
]);
15735 CRC32_Fixup (int bytemode
, int sizeflag
)
15737 /* Add proper suffix to "crc32". */
15738 char *p
= mnemonicendp
;
15757 if (sizeflag
& DFLAG
)
15761 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15765 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15772 if (modrm
.mod
== 3)
15776 /* Skip mod/rm byte. */
15781 add
= (rex
& REX_B
) ? 8 : 0;
15782 if (bytemode
== b_mode
)
15786 oappend (names8rex
[modrm
.rm
+ add
]);
15788 oappend (names8
[modrm
.rm
+ add
]);
15794 oappend (names64
[modrm
.rm
+ add
]);
15795 else if ((prefixes
& PREFIX_DATA
))
15796 oappend (names16
[modrm
.rm
+ add
]);
15798 oappend (names32
[modrm
.rm
+ add
]);
15802 OP_E (bytemode
, sizeflag
);
15806 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15808 /* Add proper suffix to "fxsave" and "fxrstor". */
15812 char *p
= mnemonicendp
;
15818 OP_M (bytemode
, sizeflag
);
15822 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15824 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15827 char *p
= mnemonicendp
;
15832 else if (sizeflag
& SUFFIX_ALWAYS
)
15839 OP_EX (bytemode
, sizeflag
);
15842 /* Display the destination register operand for instructions with
15846 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15849 const char **names
;
15857 reg
= vex
.register_specifier
;
15858 vex
.register_specifier
= 0;
15859 if (address_mode
!= mode_64bit
)
15861 else if (vex
.evex
&& !vex
.v
)
15864 if (bytemode
== vex_scalar_mode
)
15866 oappend (names_xmm
[reg
]);
15870 switch (vex
.length
)
15877 case vex_vsib_q_w_dq_mode
:
15878 case vex_vsib_q_w_d_mode
:
15894 names
= names_mask
;
15908 case vex_vsib_q_w_dq_mode
:
15909 case vex_vsib_q_w_d_mode
:
15910 names
= vex
.w
? names_ymm
: names_xmm
;
15919 names
= names_mask
;
15922 /* See PR binutils/20893 for a reproducer. */
15934 oappend (names
[reg
]);
15937 /* Get the VEX immediate byte without moving codep. */
15939 static unsigned char
15940 get_vex_imm8 (int sizeflag
, int opnum
)
15942 int bytes_before_imm
= 0;
15944 if (modrm
.mod
!= 3)
15946 /* There are SIB/displacement bytes. */
15947 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15949 /* 32/64 bit address mode */
15950 int base
= modrm
.rm
;
15952 /* Check SIB byte. */
15955 FETCH_DATA (the_info
, codep
+ 1);
15957 /* When decoding the third source, don't increase
15958 bytes_before_imm as this has already been incremented
15959 by one in OP_E_memory while decoding the second
15962 bytes_before_imm
++;
15965 /* Don't increase bytes_before_imm when decoding the third source,
15966 it has already been incremented by OP_E_memory while decoding
15967 the second source operand. */
15973 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15974 SIB == 5, there is a 4 byte displacement. */
15976 /* No displacement. */
15978 /* Fall through. */
15980 /* 4 byte displacement. */
15981 bytes_before_imm
+= 4;
15984 /* 1 byte displacement. */
15985 bytes_before_imm
++;
15992 /* 16 bit address mode */
15993 /* Don't increase bytes_before_imm when decoding the third source,
15994 it has already been incremented by OP_E_memory while decoding
15995 the second source operand. */
16001 /* When modrm.rm == 6, there is a 2 byte displacement. */
16003 /* No displacement. */
16005 /* Fall through. */
16007 /* 2 byte displacement. */
16008 bytes_before_imm
+= 2;
16011 /* 1 byte displacement: when decoding the third source,
16012 don't increase bytes_before_imm as this has already
16013 been incremented by one in OP_E_memory while decoding
16014 the second source operand. */
16016 bytes_before_imm
++;
16024 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16025 return codep
[bytes_before_imm
];
16029 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16031 const char **names
;
16033 if (reg
== -1 && modrm
.mod
!= 3)
16035 OP_E_memory (bytemode
, sizeflag
);
16047 if (address_mode
!= mode_64bit
)
16051 switch (vex
.length
)
16062 oappend (names
[reg
]);
16066 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16069 static unsigned char vex_imm8
;
16071 if (vex_w_done
== 0)
16075 /* Skip mod/rm byte. */
16079 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16082 reg
= vex_imm8
>> 4;
16084 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16086 else if (vex_w_done
== 1)
16091 reg
= vex_imm8
>> 4;
16093 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16097 /* Output the imm8 directly. */
16098 scratchbuf
[0] = '$';
16099 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16100 oappend_maybe_intel (scratchbuf
);
16101 scratchbuf
[0] = '\0';
16107 OP_Vex_2src (int bytemode
, int sizeflag
)
16109 if (modrm
.mod
== 3)
16111 int reg
= modrm
.rm
;
16115 oappend (names_xmm
[reg
]);
16120 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16122 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16123 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16125 OP_E (bytemode
, sizeflag
);
16130 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16132 if (modrm
.mod
== 3)
16134 /* Skip mod/rm byte. */
16141 unsigned int reg
= vex
.register_specifier
;
16142 vex
.register_specifier
= 0;
16144 if (address_mode
!= mode_64bit
)
16146 oappend (names_xmm
[reg
]);
16149 OP_Vex_2src (bytemode
, sizeflag
);
16153 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16156 OP_Vex_2src (bytemode
, sizeflag
);
16159 unsigned int reg
= vex
.register_specifier
;
16160 vex
.register_specifier
= 0;
16162 if (address_mode
!= mode_64bit
)
16164 oappend (names_xmm
[reg
]);
16169 OP_EX_VexW (int bytemode
, int sizeflag
)
16175 /* Skip mod/rm byte. */
16180 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16185 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16188 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16196 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16199 const char **names
;
16201 FETCH_DATA (the_info
, codep
+ 1);
16204 if (bytemode
!= x_mode
)
16208 if (address_mode
!= mode_64bit
)
16211 switch (vex
.length
)
16222 oappend (names
[reg
]);
16226 OP_XMM_VexW (int bytemode
, int sizeflag
)
16228 /* Turn off the REX.W bit since it is used for swapping operands
16231 OP_XMM (bytemode
, sizeflag
);
16235 OP_EX_Vex (int bytemode
, int sizeflag
)
16237 if (modrm
.mod
!= 3)
16239 OP_EX (bytemode
, sizeflag
);
16243 OP_XMM_Vex (int bytemode
, int sizeflag
)
16245 if (modrm
.mod
!= 3)
16247 OP_XMM (bytemode
, sizeflag
);
16250 static struct op vex_cmp_op
[] =
16252 { STRING_COMMA_LEN ("eq") },
16253 { STRING_COMMA_LEN ("lt") },
16254 { STRING_COMMA_LEN ("le") },
16255 { STRING_COMMA_LEN ("unord") },
16256 { STRING_COMMA_LEN ("neq") },
16257 { STRING_COMMA_LEN ("nlt") },
16258 { STRING_COMMA_LEN ("nle") },
16259 { STRING_COMMA_LEN ("ord") },
16260 { STRING_COMMA_LEN ("eq_uq") },
16261 { STRING_COMMA_LEN ("nge") },
16262 { STRING_COMMA_LEN ("ngt") },
16263 { STRING_COMMA_LEN ("false") },
16264 { STRING_COMMA_LEN ("neq_oq") },
16265 { STRING_COMMA_LEN ("ge") },
16266 { STRING_COMMA_LEN ("gt") },
16267 { STRING_COMMA_LEN ("true") },
16268 { STRING_COMMA_LEN ("eq_os") },
16269 { STRING_COMMA_LEN ("lt_oq") },
16270 { STRING_COMMA_LEN ("le_oq") },
16271 { STRING_COMMA_LEN ("unord_s") },
16272 { STRING_COMMA_LEN ("neq_us") },
16273 { STRING_COMMA_LEN ("nlt_uq") },
16274 { STRING_COMMA_LEN ("nle_uq") },
16275 { STRING_COMMA_LEN ("ord_s") },
16276 { STRING_COMMA_LEN ("eq_us") },
16277 { STRING_COMMA_LEN ("nge_uq") },
16278 { STRING_COMMA_LEN ("ngt_uq") },
16279 { STRING_COMMA_LEN ("false_os") },
16280 { STRING_COMMA_LEN ("neq_os") },
16281 { STRING_COMMA_LEN ("ge_oq") },
16282 { STRING_COMMA_LEN ("gt_oq") },
16283 { STRING_COMMA_LEN ("true_us") },
16287 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16289 unsigned int cmp_type
;
16291 FETCH_DATA (the_info
, codep
+ 1);
16292 cmp_type
= *codep
++ & 0xff;
16293 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16296 char *p
= mnemonicendp
- 2;
16300 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16301 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16305 /* We have a reserved extension byte. Output it directly. */
16306 scratchbuf
[0] = '$';
16307 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16308 oappend_maybe_intel (scratchbuf
);
16309 scratchbuf
[0] = '\0';
16314 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16315 int sizeflag ATTRIBUTE_UNUSED
)
16317 unsigned int cmp_type
;
16322 FETCH_DATA (the_info
, codep
+ 1);
16323 cmp_type
= *codep
++ & 0xff;
16324 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16325 If it's the case, print suffix, otherwise - print the immediate. */
16326 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16331 char *p
= mnemonicendp
- 2;
16333 /* vpcmp* can have both one- and two-lettered suffix. */
16347 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16348 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16352 /* We have a reserved extension byte. Output it directly. */
16353 scratchbuf
[0] = '$';
16354 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16355 oappend_maybe_intel (scratchbuf
);
16356 scratchbuf
[0] = '\0';
16360 static const struct op xop_cmp_op
[] =
16362 { STRING_COMMA_LEN ("lt") },
16363 { STRING_COMMA_LEN ("le") },
16364 { STRING_COMMA_LEN ("gt") },
16365 { STRING_COMMA_LEN ("ge") },
16366 { STRING_COMMA_LEN ("eq") },
16367 { STRING_COMMA_LEN ("neq") },
16368 { STRING_COMMA_LEN ("false") },
16369 { STRING_COMMA_LEN ("true") }
16373 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16374 int sizeflag ATTRIBUTE_UNUSED
)
16376 unsigned int cmp_type
;
16378 FETCH_DATA (the_info
, codep
+ 1);
16379 cmp_type
= *codep
++ & 0xff;
16380 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16383 char *p
= mnemonicendp
- 2;
16385 /* vpcom* can have both one- and two-lettered suffix. */
16399 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16400 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16404 /* We have a reserved extension byte. Output it directly. */
16405 scratchbuf
[0] = '$';
16406 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16407 oappend_maybe_intel (scratchbuf
);
16408 scratchbuf
[0] = '\0';
16412 static const struct op pclmul_op
[] =
16414 { STRING_COMMA_LEN ("lql") },
16415 { STRING_COMMA_LEN ("hql") },
16416 { STRING_COMMA_LEN ("lqh") },
16417 { STRING_COMMA_LEN ("hqh") }
16421 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16422 int sizeflag ATTRIBUTE_UNUSED
)
16424 unsigned int pclmul_type
;
16426 FETCH_DATA (the_info
, codep
+ 1);
16427 pclmul_type
= *codep
++ & 0xff;
16428 switch (pclmul_type
)
16439 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16442 char *p
= mnemonicendp
- 3;
16447 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16448 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16452 /* We have a reserved extension byte. Output it directly. */
16453 scratchbuf
[0] = '$';
16454 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16455 oappend_maybe_intel (scratchbuf
);
16456 scratchbuf
[0] = '\0';
16461 MOVBE_Fixup (int bytemode
, int sizeflag
)
16463 /* Add proper suffix to "movbe". */
16464 char *p
= mnemonicendp
;
16473 if (sizeflag
& SUFFIX_ALWAYS
)
16479 if (sizeflag
& DFLAG
)
16483 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16488 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16495 OP_M (bytemode
, sizeflag
);
16499 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16502 const char **names
;
16504 /* Skip mod/rm byte. */
16518 oappend (names
[reg
]);
16522 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16524 const char **names
;
16525 unsigned int reg
= vex
.register_specifier
;
16526 vex
.register_specifier
= 0;
16533 if (address_mode
!= mode_64bit
)
16535 oappend (names
[reg
]);
16539 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16542 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16546 if ((rex
& REX_R
) != 0 || !vex
.r
)
16552 oappend (names_mask
[modrm
.reg
]);
16556 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16559 || (bytemode
!= evex_rounding_mode
16560 && bytemode
!= evex_rounding_64_mode
16561 && bytemode
!= evex_sae_mode
))
16563 if (modrm
.mod
== 3 && vex
.b
)
16566 case evex_rounding_64_mode
:
16567 if (address_mode
!= mode_64bit
)
16572 /* Fall through. */
16573 case evex_rounding_mode
:
16574 oappend (names_rounding
[vex
.ll
]);
16576 case evex_sae_mode
: