1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2020 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void SEP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
127 static void MOVSXD_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iv64 { OP_I64, v_mode }
296 #define Id { OP_I, d_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Jdqw { OP_J, dqw_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define SEP { SEP_Fixup, 0 }
418 #define CMP { CMP_Fixup, 0 }
419 #define XMM0 { XMM_Fixup, 0 }
420 #define FXSAVE { FXSAVE_Fixup, 0 }
421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
424 #define Vex { OP_VEX, vex_mode }
425 #define VexScalar { OP_VEX, vex_scalar_mode }
426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
427 #define Vex128 { OP_VEX, vex128_mode }
428 #define Vex256 { OP_VEX, vex256_mode }
429 #define VexGdq { OP_VEX, dq_mode }
430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
437 #define XMVexW { OP_XMM_VexW, 0 }
438 #define XMVexI4 { OP_REG_VexI4, x_mode }
439 #define PCLMUL { PCLMUL_Fixup, 0 }
440 #define VCMP { VCMP_Fixup, 0 }
441 #define VPCMP { VPCMP_Fixup, 0 }
442 #define VPCOM { VPCOM_Fixup, 0 }
444 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
445 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
501 /* operand size depends on address prefix */
505 /* double word operand */
507 /* double word operand with operand swapped */
509 /* quad word operand */
511 /* quad word operand with operand swapped */
513 /* ten-byte operand */
515 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
516 broadcast enabled. */
518 /* Similar to x_mode, but with different EVEX mem shifts. */
520 /* Similar to x_mode, but with disabled broadcast. */
522 /* Similar to x_mode, but with operands swapped and disabled broadcast
525 /* 16-byte XMM operand */
527 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
528 memory operand (depending on vector length). Broadcast isn't
531 /* Same as xmmq_mode, but broadcast is allowed. */
532 evex_half_bcst_xmmq_mode
,
533 /* XMM register or byte memory operand */
535 /* XMM register or word memory operand */
537 /* XMM register or double word memory operand */
539 /* XMM register or quad word memory operand */
541 /* XMM register or double/quad word memory operand, depending on
544 /* 16-byte XMM, word, double word or quad word operand. */
546 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
548 /* 32-byte YMM operand */
550 /* quad word, ymmword or zmmword memory operand. */
552 /* 32-byte YMM or 16-byte word operand */
554 /* d_mode in 32bit, q_mode in 64bit mode. */
556 /* pair of v_mode operands */
562 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
564 /* operand size depends on REX prefixes. */
566 /* registers like dq_mode, memory like w_mode, displacements like
567 v_mode without considering Intel64 ISA. */
571 /* bounds operand with operand swapped */
573 /* 4- or 6-byte pointer operand */
576 /* v_mode for indirect branch opcodes. */
578 /* v_mode for stack-related opcodes. */
580 /* non-quad operand size depends on prefixes */
582 /* 16-byte operand */
584 /* registers like dq_mode, memory like b_mode. */
586 /* registers like d_mode, memory like b_mode. */
588 /* registers like d_mode, memory like w_mode. */
590 /* registers like dq_mode, memory like d_mode. */
592 /* normal vex mode */
594 /* 128bit vex mode */
596 /* 256bit vex mode */
598 /* operand size depends on the VEX.W bit. */
601 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
602 vex_vsib_d_w_dq_mode
,
603 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
605 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
606 vex_vsib_q_w_dq_mode
,
607 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
610 /* scalar, ignore vector length. */
612 /* like b_mode, ignore vector length. */
614 /* like w_mode, ignore vector length. */
616 /* like d_mode, ignore vector length. */
618 /* like d_swap_mode, ignore vector length. */
620 /* like q_mode, ignore vector length. */
622 /* like q_swap_mode, ignore vector length. */
624 /* like vex_mode, ignore vector length. */
626 /* like vex_w_dq_mode, ignore vector length. */
627 vex_scalar_w_dq_mode
,
629 /* Static rounding. */
631 /* Static rounding, 64-bit mode only. */
632 evex_rounding_64_mode
,
633 /* Supress all exceptions. */
636 /* Mask register operand. */
638 /* Mask register operand. */
706 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
708 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
709 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
710 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
711 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
712 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
713 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
714 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
715 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
716 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
717 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
718 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
719 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
720 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
721 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
722 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
723 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
851 MOD_VEX_0F12_PREFIX_0
,
853 MOD_VEX_0F16_PREFIX_0
,
856 MOD_VEX_W_0_0F41_P_0_LEN_1
,
857 MOD_VEX_W_1_0F41_P_0_LEN_1
,
858 MOD_VEX_W_0_0F41_P_2_LEN_1
,
859 MOD_VEX_W_1_0F41_P_2_LEN_1
,
860 MOD_VEX_W_0_0F42_P_0_LEN_1
,
861 MOD_VEX_W_1_0F42_P_0_LEN_1
,
862 MOD_VEX_W_0_0F42_P_2_LEN_1
,
863 MOD_VEX_W_1_0F42_P_2_LEN_1
,
864 MOD_VEX_W_0_0F44_P_0_LEN_1
,
865 MOD_VEX_W_1_0F44_P_0_LEN_1
,
866 MOD_VEX_W_0_0F44_P_2_LEN_1
,
867 MOD_VEX_W_1_0F44_P_2_LEN_1
,
868 MOD_VEX_W_0_0F45_P_0_LEN_1
,
869 MOD_VEX_W_1_0F45_P_0_LEN_1
,
870 MOD_VEX_W_0_0F45_P_2_LEN_1
,
871 MOD_VEX_W_1_0F45_P_2_LEN_1
,
872 MOD_VEX_W_0_0F46_P_0_LEN_1
,
873 MOD_VEX_W_1_0F46_P_0_LEN_1
,
874 MOD_VEX_W_0_0F46_P_2_LEN_1
,
875 MOD_VEX_W_1_0F46_P_2_LEN_1
,
876 MOD_VEX_W_0_0F47_P_0_LEN_1
,
877 MOD_VEX_W_1_0F47_P_0_LEN_1
,
878 MOD_VEX_W_0_0F47_P_2_LEN_1
,
879 MOD_VEX_W_1_0F47_P_2_LEN_1
,
880 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
881 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
882 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
883 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
884 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
885 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
886 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
898 MOD_VEX_W_0_0F91_P_0_LEN_0
,
899 MOD_VEX_W_1_0F91_P_0_LEN_0
,
900 MOD_VEX_W_0_0F91_P_2_LEN_0
,
901 MOD_VEX_W_1_0F91_P_2_LEN_0
,
902 MOD_VEX_W_0_0F92_P_0_LEN_0
,
903 MOD_VEX_W_0_0F92_P_2_LEN_0
,
904 MOD_VEX_0F92_P_3_LEN_0
,
905 MOD_VEX_W_0_0F93_P_0_LEN_0
,
906 MOD_VEX_W_0_0F93_P_2_LEN_0
,
907 MOD_VEX_0F93_P_3_LEN_0
,
908 MOD_VEX_W_0_0F98_P_0_LEN_0
,
909 MOD_VEX_W_1_0F98_P_0_LEN_0
,
910 MOD_VEX_W_0_0F98_P_2_LEN_0
,
911 MOD_VEX_W_1_0F98_P_2_LEN_0
,
912 MOD_VEX_W_0_0F99_P_0_LEN_0
,
913 MOD_VEX_W_1_0F99_P_0_LEN_0
,
914 MOD_VEX_W_0_0F99_P_2_LEN_0
,
915 MOD_VEX_W_1_0F99_P_2_LEN_0
,
918 MOD_VEX_0FD7_PREFIX_2
,
919 MOD_VEX_0FE7_PREFIX_2
,
920 MOD_VEX_0FF0_PREFIX_3
,
921 MOD_VEX_0F381A_PREFIX_2
,
922 MOD_VEX_0F382A_PREFIX_2
,
923 MOD_VEX_0F382C_PREFIX_2
,
924 MOD_VEX_0F382D_PREFIX_2
,
925 MOD_VEX_0F382E_PREFIX_2
,
926 MOD_VEX_0F382F_PREFIX_2
,
927 MOD_VEX_0F385A_PREFIX_2
,
928 MOD_VEX_0F388C_PREFIX_2
,
929 MOD_VEX_0F388E_PREFIX_2
,
930 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
932 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
934 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
935 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
936 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
937 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
939 MOD_EVEX_0F12_PREFIX_0
,
940 MOD_EVEX_0F16_PREFIX_0
,
941 MOD_EVEX_0F38C6_REG_1
,
942 MOD_EVEX_0F38C6_REG_2
,
943 MOD_EVEX_0F38C6_REG_5
,
944 MOD_EVEX_0F38C6_REG_6
,
945 MOD_EVEX_0F38C7_REG_1
,
946 MOD_EVEX_0F38C7_REG_2
,
947 MOD_EVEX_0F38C7_REG_5
,
948 MOD_EVEX_0F38C7_REG_6
961 RM_0F1E_P_1_MOD_3_REG_7
,
962 RM_0FAE_REG_6_MOD_3_P_0
,
969 PREFIX_0F01_REG_5_MOD_0
,
970 PREFIX_0F01_REG_5_MOD_3_RM_0
,
971 PREFIX_0F01_REG_5_MOD_3_RM_2
,
972 PREFIX_0F01_REG_7_MOD_3_RM_2
,
973 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1015 PREFIX_0FAE_REG_0_MOD_3
,
1016 PREFIX_0FAE_REG_1_MOD_3
,
1017 PREFIX_0FAE_REG_2_MOD_3
,
1018 PREFIX_0FAE_REG_3_MOD_3
,
1019 PREFIX_0FAE_REG_4_MOD_0
,
1020 PREFIX_0FAE_REG_4_MOD_3
,
1021 PREFIX_0FAE_REG_5_MOD_0
,
1022 PREFIX_0FAE_REG_5_MOD_3
,
1023 PREFIX_0FAE_REG_6_MOD_0
,
1024 PREFIX_0FAE_REG_6_MOD_3
,
1025 PREFIX_0FAE_REG_7_MOD_0
,
1031 PREFIX_0FC7_REG_6_MOD_0
,
1032 PREFIX_0FC7_REG_6_MOD_3
,
1033 PREFIX_0FC7_REG_7_MOD_3
,
1163 PREFIX_VEX_0F71_REG_2
,
1164 PREFIX_VEX_0F71_REG_4
,
1165 PREFIX_VEX_0F71_REG_6
,
1166 PREFIX_VEX_0F72_REG_2
,
1167 PREFIX_VEX_0F72_REG_4
,
1168 PREFIX_VEX_0F72_REG_6
,
1169 PREFIX_VEX_0F73_REG_2
,
1170 PREFIX_VEX_0F73_REG_3
,
1171 PREFIX_VEX_0F73_REG_6
,
1172 PREFIX_VEX_0F73_REG_7
,
1345 PREFIX_VEX_0F38F3_REG_1
,
1346 PREFIX_VEX_0F38F3_REG_2
,
1347 PREFIX_VEX_0F38F3_REG_3
,
1466 PREFIX_EVEX_0F71_REG_2
,
1467 PREFIX_EVEX_0F71_REG_4
,
1468 PREFIX_EVEX_0F71_REG_6
,
1469 PREFIX_EVEX_0F72_REG_0
,
1470 PREFIX_EVEX_0F72_REG_1
,
1471 PREFIX_EVEX_0F72_REG_2
,
1472 PREFIX_EVEX_0F72_REG_4
,
1473 PREFIX_EVEX_0F72_REG_6
,
1474 PREFIX_EVEX_0F73_REG_2
,
1475 PREFIX_EVEX_0F73_REG_3
,
1476 PREFIX_EVEX_0F73_REG_6
,
1477 PREFIX_EVEX_0F73_REG_7
,
1674 PREFIX_EVEX_0F38C6_REG_1
,
1675 PREFIX_EVEX_0F38C6_REG_2
,
1676 PREFIX_EVEX_0F38C6_REG_5
,
1677 PREFIX_EVEX_0F38C6_REG_6
,
1678 PREFIX_EVEX_0F38C7_REG_1
,
1679 PREFIX_EVEX_0F38C7_REG_2
,
1680 PREFIX_EVEX_0F38C7_REG_5
,
1681 PREFIX_EVEX_0F38C7_REG_6
,
1783 THREE_BYTE_0F38
= 0,
1810 VEX_LEN_0F12_P_0_M_0
= 0,
1811 VEX_LEN_0F12_P_0_M_1
,
1814 VEX_LEN_0F16_P_0_M_0
,
1815 VEX_LEN_0F16_P_0_M_1
,
1852 VEX_LEN_0FAE_R_2_M_0
,
1853 VEX_LEN_0FAE_R_3_M_0
,
1860 VEX_LEN_0F381A_P_2_M_0
,
1863 VEX_LEN_0F385A_P_2_M_0
,
1866 VEX_LEN_0F38F3_R_1_P_0
,
1867 VEX_LEN_0F38F3_R_2_P_0
,
1868 VEX_LEN_0F38F3_R_3_P_0
,
1911 VEX_LEN_0FXOP_08_CC
,
1912 VEX_LEN_0FXOP_08_CD
,
1913 VEX_LEN_0FXOP_08_CE
,
1914 VEX_LEN_0FXOP_08_CF
,
1915 VEX_LEN_0FXOP_08_EC
,
1916 VEX_LEN_0FXOP_08_ED
,
1917 VEX_LEN_0FXOP_08_EE
,
1918 VEX_LEN_0FXOP_08_EF
,
1919 VEX_LEN_0FXOP_09_80
,
1925 EVEX_LEN_0F6E_P_2
= 0,
1929 EVEX_LEN_0F3819_P_2_W_0
,
1930 EVEX_LEN_0F3819_P_2_W_1
,
1931 EVEX_LEN_0F381A_P_2_W_0
,
1932 EVEX_LEN_0F381A_P_2_W_1
,
1933 EVEX_LEN_0F381B_P_2_W_0
,
1934 EVEX_LEN_0F381B_P_2_W_1
,
1935 EVEX_LEN_0F385A_P_2_W_0
,
1936 EVEX_LEN_0F385A_P_2_W_1
,
1937 EVEX_LEN_0F385B_P_2_W_0
,
1938 EVEX_LEN_0F385B_P_2_W_1
,
1939 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1940 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1941 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1942 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1943 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1945 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1947 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1948 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1949 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1950 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1951 EVEX_LEN_0F3A18_P_2_W_0
,
1952 EVEX_LEN_0F3A18_P_2_W_1
,
1953 EVEX_LEN_0F3A19_P_2_W_0
,
1954 EVEX_LEN_0F3A19_P_2_W_1
,
1955 EVEX_LEN_0F3A1A_P_2_W_0
,
1956 EVEX_LEN_0F3A1A_P_2_W_1
,
1957 EVEX_LEN_0F3A1B_P_2_W_0
,
1958 EVEX_LEN_0F3A1B_P_2_W_1
,
1959 EVEX_LEN_0F3A23_P_2_W_0
,
1960 EVEX_LEN_0F3A23_P_2_W_1
,
1961 EVEX_LEN_0F3A38_P_2_W_0
,
1962 EVEX_LEN_0F3A38_P_2_W_1
,
1963 EVEX_LEN_0F3A39_P_2_W_0
,
1964 EVEX_LEN_0F3A39_P_2_W_1
,
1965 EVEX_LEN_0F3A3A_P_2_W_0
,
1966 EVEX_LEN_0F3A3A_P_2_W_1
,
1967 EVEX_LEN_0F3A3B_P_2_W_0
,
1968 EVEX_LEN_0F3A3B_P_2_W_1
,
1969 EVEX_LEN_0F3A43_P_2_W_0
,
1970 EVEX_LEN_0F3A43_P_2_W_1
1975 VEX_W_0F41_P_0_LEN_1
= 0,
1976 VEX_W_0F41_P_2_LEN_1
,
1977 VEX_W_0F42_P_0_LEN_1
,
1978 VEX_W_0F42_P_2_LEN_1
,
1979 VEX_W_0F44_P_0_LEN_0
,
1980 VEX_W_0F44_P_2_LEN_0
,
1981 VEX_W_0F45_P_0_LEN_1
,
1982 VEX_W_0F45_P_2_LEN_1
,
1983 VEX_W_0F46_P_0_LEN_1
,
1984 VEX_W_0F46_P_2_LEN_1
,
1985 VEX_W_0F47_P_0_LEN_1
,
1986 VEX_W_0F47_P_2_LEN_1
,
1987 VEX_W_0F4A_P_0_LEN_1
,
1988 VEX_W_0F4A_P_2_LEN_1
,
1989 VEX_W_0F4B_P_0_LEN_1
,
1990 VEX_W_0F4B_P_2_LEN_1
,
1991 VEX_W_0F90_P_0_LEN_0
,
1992 VEX_W_0F90_P_2_LEN_0
,
1993 VEX_W_0F91_P_0_LEN_0
,
1994 VEX_W_0F91_P_2_LEN_0
,
1995 VEX_W_0F92_P_0_LEN_0
,
1996 VEX_W_0F92_P_2_LEN_0
,
1997 VEX_W_0F93_P_0_LEN_0
,
1998 VEX_W_0F93_P_2_LEN_0
,
1999 VEX_W_0F98_P_0_LEN_0
,
2000 VEX_W_0F98_P_2_LEN_0
,
2001 VEX_W_0F99_P_0_LEN_0
,
2002 VEX_W_0F99_P_2_LEN_0
,
2010 VEX_W_0F381A_P_2_M_0
,
2011 VEX_W_0F382C_P_2_M_0
,
2012 VEX_W_0F382D_P_2_M_0
,
2013 VEX_W_0F382E_P_2_M_0
,
2014 VEX_W_0F382F_P_2_M_0
,
2019 VEX_W_0F385A_P_2_M_0
,
2031 VEX_W_0F3A30_P_2_LEN_0
,
2032 VEX_W_0F3A31_P_2_LEN_0
,
2033 VEX_W_0F3A32_P_2_LEN_0
,
2034 VEX_W_0F3A33_P_2_LEN_0
,
2054 EVEX_W_0F12_P_0_M_0
,
2055 EVEX_W_0F12_P_0_M_1
,
2065 EVEX_W_0F16_P_0_M_0
,
2066 EVEX_W_0F16_P_0_M_1
,
2135 EVEX_W_0F72_R_2_P_2
,
2136 EVEX_W_0F72_R_6_P_2
,
2137 EVEX_W_0F73_R_2_P_2
,
2138 EVEX_W_0F73_R_6_P_2
,
2248 EVEX_W_0F38C7_R_1_P_2
,
2249 EVEX_W_0F38C7_R_2_P_2
,
2250 EVEX_W_0F38C7_R_5_P_2
,
2251 EVEX_W_0F38C7_R_6_P_2
,
2290 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2299 unsigned int prefix_requirement
;
2302 /* Upper case letters in the instruction names here are macros.
2303 'A' => print 'b' if no register operands or suffix_always is true
2304 'B' => print 'b' if suffix_always is true
2305 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2307 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2308 suffix_always is true
2309 'E' => print 'e' if 32-bit form of jcxz
2310 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2311 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2312 'H' => print ",pt" or ",pn" branch hint
2313 'I' => honor following macro letter even in Intel mode (implemented only
2314 for some of the macro letters)
2316 'K' => print 'd' or 'q' if rex prefix is present.
2317 'L' => print 'l' if suffix_always is true
2318 'M' => print 'r' if intel_mnemonic is false.
2319 'N' => print 'n' if instruction has no wait "prefix"
2320 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2321 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2322 or suffix_always is true. print 'q' if rex prefix is present.
2323 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2325 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2326 'S' => print 'w', 'l' or 'q' if suffix_always is true
2327 'T' => print 'q' in 64bit mode if instruction has no operand size
2328 prefix and behave as 'P' otherwise
2329 'U' => print 'q' in 64bit mode if instruction has no operand size
2330 prefix and behave as 'Q' otherwise
2331 'V' => print 'q' in 64bit mode if instruction has no operand size
2332 prefix and behave as 'S' otherwise
2333 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2334 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2336 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2337 '!' => change condition from true to false or from false to true.
2338 '%' => add 1 upper case letter to the macro.
2339 '^' => print 'w' or 'l' depending on operand size prefix or
2340 suffix_always is true (lcall/ljmp).
2341 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2342 on operand size prefix.
2343 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2344 has no operand size prefix for AMD64 ISA, behave as 'P'
2347 2 upper case letter macros:
2348 "XY" => print 'x' or 'y' if suffix_always is true or no register
2349 operands and no broadcast.
2350 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2351 register operands and no broadcast.
2352 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2353 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2354 or suffix_always is true
2355 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2356 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2357 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2358 "LW" => print 'd', 'q' depending on the VEX.W bit
2359 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2360 an operand size prefix, or suffix_always is true. print
2361 'q' if rex prefix is present.
2363 Many of the above letters print nothing in Intel mode. See "putop"
2366 Braces '{' and '}', and vertical bars '|', indicate alternative
2367 mnemonic strings for AT&T and Intel. */
2369 static const struct dis386 dis386
[] = {
2371 { "addB", { Ebh1
, Gb
}, 0 },
2372 { "addS", { Evh1
, Gv
}, 0 },
2373 { "addB", { Gb
, EbS
}, 0 },
2374 { "addS", { Gv
, EvS
}, 0 },
2375 { "addB", { AL
, Ib
}, 0 },
2376 { "addS", { eAX
, Iv
}, 0 },
2377 { X86_64_TABLE (X86_64_06
) },
2378 { X86_64_TABLE (X86_64_07
) },
2380 { "orB", { Ebh1
, Gb
}, 0 },
2381 { "orS", { Evh1
, Gv
}, 0 },
2382 { "orB", { Gb
, EbS
}, 0 },
2383 { "orS", { Gv
, EvS
}, 0 },
2384 { "orB", { AL
, Ib
}, 0 },
2385 { "orS", { eAX
, Iv
}, 0 },
2386 { X86_64_TABLE (X86_64_0D
) },
2387 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2389 { "adcB", { Ebh1
, Gb
}, 0 },
2390 { "adcS", { Evh1
, Gv
}, 0 },
2391 { "adcB", { Gb
, EbS
}, 0 },
2392 { "adcS", { Gv
, EvS
}, 0 },
2393 { "adcB", { AL
, Ib
}, 0 },
2394 { "adcS", { eAX
, Iv
}, 0 },
2395 { X86_64_TABLE (X86_64_16
) },
2396 { X86_64_TABLE (X86_64_17
) },
2398 { "sbbB", { Ebh1
, Gb
}, 0 },
2399 { "sbbS", { Evh1
, Gv
}, 0 },
2400 { "sbbB", { Gb
, EbS
}, 0 },
2401 { "sbbS", { Gv
, EvS
}, 0 },
2402 { "sbbB", { AL
, Ib
}, 0 },
2403 { "sbbS", { eAX
, Iv
}, 0 },
2404 { X86_64_TABLE (X86_64_1E
) },
2405 { X86_64_TABLE (X86_64_1F
) },
2407 { "andB", { Ebh1
, Gb
}, 0 },
2408 { "andS", { Evh1
, Gv
}, 0 },
2409 { "andB", { Gb
, EbS
}, 0 },
2410 { "andS", { Gv
, EvS
}, 0 },
2411 { "andB", { AL
, Ib
}, 0 },
2412 { "andS", { eAX
, Iv
}, 0 },
2413 { Bad_Opcode
}, /* SEG ES prefix */
2414 { X86_64_TABLE (X86_64_27
) },
2416 { "subB", { Ebh1
, Gb
}, 0 },
2417 { "subS", { Evh1
, Gv
}, 0 },
2418 { "subB", { Gb
, EbS
}, 0 },
2419 { "subS", { Gv
, EvS
}, 0 },
2420 { "subB", { AL
, Ib
}, 0 },
2421 { "subS", { eAX
, Iv
}, 0 },
2422 { Bad_Opcode
}, /* SEG CS prefix */
2423 { X86_64_TABLE (X86_64_2F
) },
2425 { "xorB", { Ebh1
, Gb
}, 0 },
2426 { "xorS", { Evh1
, Gv
}, 0 },
2427 { "xorB", { Gb
, EbS
}, 0 },
2428 { "xorS", { Gv
, EvS
}, 0 },
2429 { "xorB", { AL
, Ib
}, 0 },
2430 { "xorS", { eAX
, Iv
}, 0 },
2431 { Bad_Opcode
}, /* SEG SS prefix */
2432 { X86_64_TABLE (X86_64_37
) },
2434 { "cmpB", { Eb
, Gb
}, 0 },
2435 { "cmpS", { Ev
, Gv
}, 0 },
2436 { "cmpB", { Gb
, EbS
}, 0 },
2437 { "cmpS", { Gv
, EvS
}, 0 },
2438 { "cmpB", { AL
, Ib
}, 0 },
2439 { "cmpS", { eAX
, Iv
}, 0 },
2440 { Bad_Opcode
}, /* SEG DS prefix */
2441 { X86_64_TABLE (X86_64_3F
) },
2443 { "inc{S|}", { RMeAX
}, 0 },
2444 { "inc{S|}", { RMeCX
}, 0 },
2445 { "inc{S|}", { RMeDX
}, 0 },
2446 { "inc{S|}", { RMeBX
}, 0 },
2447 { "inc{S|}", { RMeSP
}, 0 },
2448 { "inc{S|}", { RMeBP
}, 0 },
2449 { "inc{S|}", { RMeSI
}, 0 },
2450 { "inc{S|}", { RMeDI
}, 0 },
2452 { "dec{S|}", { RMeAX
}, 0 },
2453 { "dec{S|}", { RMeCX
}, 0 },
2454 { "dec{S|}", { RMeDX
}, 0 },
2455 { "dec{S|}", { RMeBX
}, 0 },
2456 { "dec{S|}", { RMeSP
}, 0 },
2457 { "dec{S|}", { RMeBP
}, 0 },
2458 { "dec{S|}", { RMeSI
}, 0 },
2459 { "dec{S|}", { RMeDI
}, 0 },
2461 { "pushV", { RMrAX
}, 0 },
2462 { "pushV", { RMrCX
}, 0 },
2463 { "pushV", { RMrDX
}, 0 },
2464 { "pushV", { RMrBX
}, 0 },
2465 { "pushV", { RMrSP
}, 0 },
2466 { "pushV", { RMrBP
}, 0 },
2467 { "pushV", { RMrSI
}, 0 },
2468 { "pushV", { RMrDI
}, 0 },
2470 { "popV", { RMrAX
}, 0 },
2471 { "popV", { RMrCX
}, 0 },
2472 { "popV", { RMrDX
}, 0 },
2473 { "popV", { RMrBX
}, 0 },
2474 { "popV", { RMrSP
}, 0 },
2475 { "popV", { RMrBP
}, 0 },
2476 { "popV", { RMrSI
}, 0 },
2477 { "popV", { RMrDI
}, 0 },
2479 { X86_64_TABLE (X86_64_60
) },
2480 { X86_64_TABLE (X86_64_61
) },
2481 { X86_64_TABLE (X86_64_62
) },
2482 { X86_64_TABLE (X86_64_63
) },
2483 { Bad_Opcode
}, /* seg fs */
2484 { Bad_Opcode
}, /* seg gs */
2485 { Bad_Opcode
}, /* op size prefix */
2486 { Bad_Opcode
}, /* adr size prefix */
2488 { "pushT", { sIv
}, 0 },
2489 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2490 { "pushT", { sIbT
}, 0 },
2491 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2492 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2493 { X86_64_TABLE (X86_64_6D
) },
2494 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2495 { X86_64_TABLE (X86_64_6F
) },
2497 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2499 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2512 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2513 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2515 { REG_TABLE (REG_80
) },
2516 { REG_TABLE (REG_81
) },
2517 { X86_64_TABLE (X86_64_82
) },
2518 { REG_TABLE (REG_83
) },
2519 { "testB", { Eb
, Gb
}, 0 },
2520 { "testS", { Ev
, Gv
}, 0 },
2521 { "xchgB", { Ebh2
, Gb
}, 0 },
2522 { "xchgS", { Evh2
, Gv
}, 0 },
2524 { "movB", { Ebh3
, Gb
}, 0 },
2525 { "movS", { Evh3
, Gv
}, 0 },
2526 { "movB", { Gb
, EbS
}, 0 },
2527 { "movS", { Gv
, EvS
}, 0 },
2528 { "movD", { Sv
, Sw
}, 0 },
2529 { MOD_TABLE (MOD_8D
) },
2530 { "movD", { Sw
, Sv
}, 0 },
2531 { REG_TABLE (REG_8F
) },
2533 { PREFIX_TABLE (PREFIX_90
) },
2534 { "xchgS", { RMeCX
, eAX
}, 0 },
2535 { "xchgS", { RMeDX
, eAX
}, 0 },
2536 { "xchgS", { RMeBX
, eAX
}, 0 },
2537 { "xchgS", { RMeSP
, eAX
}, 0 },
2538 { "xchgS", { RMeBP
, eAX
}, 0 },
2539 { "xchgS", { RMeSI
, eAX
}, 0 },
2540 { "xchgS", { RMeDI
, eAX
}, 0 },
2542 { "cW{t|}R", { XX
}, 0 },
2543 { "cR{t|}O", { XX
}, 0 },
2544 { X86_64_TABLE (X86_64_9A
) },
2545 { Bad_Opcode
}, /* fwait */
2546 { "pushfT", { XX
}, 0 },
2547 { "popfT", { XX
}, 0 },
2548 { "sahf", { XX
}, 0 },
2549 { "lahf", { XX
}, 0 },
2551 { "mov%LB", { AL
, Ob
}, 0 },
2552 { "mov%LS", { eAX
, Ov
}, 0 },
2553 { "mov%LB", { Ob
, AL
}, 0 },
2554 { "mov%LS", { Ov
, eAX
}, 0 },
2555 { "movs{b|}", { Ybr
, Xb
}, 0 },
2556 { "movs{R|}", { Yvr
, Xv
}, 0 },
2557 { "cmps{b|}", { Xb
, Yb
}, 0 },
2558 { "cmps{R|}", { Xv
, Yv
}, 0 },
2560 { "testB", { AL
, Ib
}, 0 },
2561 { "testS", { eAX
, Iv
}, 0 },
2562 { "stosB", { Ybr
, AL
}, 0 },
2563 { "stosS", { Yvr
, eAX
}, 0 },
2564 { "lodsB", { ALr
, Xb
}, 0 },
2565 { "lodsS", { eAXr
, Xv
}, 0 },
2566 { "scasB", { AL
, Yb
}, 0 },
2567 { "scasS", { eAX
, Yv
}, 0 },
2569 { "movB", { RMAL
, Ib
}, 0 },
2570 { "movB", { RMCL
, Ib
}, 0 },
2571 { "movB", { RMDL
, Ib
}, 0 },
2572 { "movB", { RMBL
, Ib
}, 0 },
2573 { "movB", { RMAH
, Ib
}, 0 },
2574 { "movB", { RMCH
, Ib
}, 0 },
2575 { "movB", { RMDH
, Ib
}, 0 },
2576 { "movB", { RMBH
, Ib
}, 0 },
2578 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2579 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2580 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2581 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2582 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2583 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2584 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2585 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2587 { REG_TABLE (REG_C0
) },
2588 { REG_TABLE (REG_C1
) },
2589 { "retT", { Iw
, BND
}, 0 },
2590 { "retT", { BND
}, 0 },
2591 { X86_64_TABLE (X86_64_C4
) },
2592 { X86_64_TABLE (X86_64_C5
) },
2593 { REG_TABLE (REG_C6
) },
2594 { REG_TABLE (REG_C7
) },
2596 { "enterT", { Iw
, Ib
}, 0 },
2597 { "leaveT", { XX
}, 0 },
2598 { "Jret{|f}P", { Iw
}, 0 },
2599 { "Jret{|f}P", { XX
}, 0 },
2600 { "int3", { XX
}, 0 },
2601 { "int", { Ib
}, 0 },
2602 { X86_64_TABLE (X86_64_CE
) },
2603 { "iret%LP", { XX
}, 0 },
2605 { REG_TABLE (REG_D0
) },
2606 { REG_TABLE (REG_D1
) },
2607 { REG_TABLE (REG_D2
) },
2608 { REG_TABLE (REG_D3
) },
2609 { X86_64_TABLE (X86_64_D4
) },
2610 { X86_64_TABLE (X86_64_D5
) },
2612 { "xlat", { DSBX
}, 0 },
2623 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2624 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2625 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2626 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2627 { "inB", { AL
, Ib
}, 0 },
2628 { "inG", { zAX
, Ib
}, 0 },
2629 { "outB", { Ib
, AL
}, 0 },
2630 { "outG", { Ib
, zAX
}, 0 },
2632 { X86_64_TABLE (X86_64_E8
) },
2633 { X86_64_TABLE (X86_64_E9
) },
2634 { X86_64_TABLE (X86_64_EA
) },
2635 { "jmp", { Jb
, BND
}, 0 },
2636 { "inB", { AL
, indirDX
}, 0 },
2637 { "inG", { zAX
, indirDX
}, 0 },
2638 { "outB", { indirDX
, AL
}, 0 },
2639 { "outG", { indirDX
, zAX
}, 0 },
2641 { Bad_Opcode
}, /* lock prefix */
2642 { "icebp", { XX
}, 0 },
2643 { Bad_Opcode
}, /* repne */
2644 { Bad_Opcode
}, /* repz */
2645 { "hlt", { XX
}, 0 },
2646 { "cmc", { XX
}, 0 },
2647 { REG_TABLE (REG_F6
) },
2648 { REG_TABLE (REG_F7
) },
2650 { "clc", { XX
}, 0 },
2651 { "stc", { XX
}, 0 },
2652 { "cli", { XX
}, 0 },
2653 { "sti", { XX
}, 0 },
2654 { "cld", { XX
}, 0 },
2655 { "std", { XX
}, 0 },
2656 { REG_TABLE (REG_FE
) },
2657 { REG_TABLE (REG_FF
) },
2660 static const struct dis386 dis386_twobyte
[] = {
2662 { REG_TABLE (REG_0F00
) },
2663 { REG_TABLE (REG_0F01
) },
2664 { "larS", { Gv
, Ew
}, 0 },
2665 { "lslS", { Gv
, Ew
}, 0 },
2667 { "syscall", { XX
}, 0 },
2668 { "clts", { XX
}, 0 },
2669 { "sysret%LP", { XX
}, 0 },
2671 { "invd", { XX
}, 0 },
2672 { PREFIX_TABLE (PREFIX_0F09
) },
2674 { "ud2", { XX
}, 0 },
2676 { REG_TABLE (REG_0F0D
) },
2677 { "femms", { XX
}, 0 },
2678 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2680 { PREFIX_TABLE (PREFIX_0F10
) },
2681 { PREFIX_TABLE (PREFIX_0F11
) },
2682 { PREFIX_TABLE (PREFIX_0F12
) },
2683 { MOD_TABLE (MOD_0F13
) },
2684 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2685 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2686 { PREFIX_TABLE (PREFIX_0F16
) },
2687 { MOD_TABLE (MOD_0F17
) },
2689 { REG_TABLE (REG_0F18
) },
2690 { "nopQ", { Ev
}, 0 },
2691 { PREFIX_TABLE (PREFIX_0F1A
) },
2692 { PREFIX_TABLE (PREFIX_0F1B
) },
2693 { PREFIX_TABLE (PREFIX_0F1C
) },
2694 { "nopQ", { Ev
}, 0 },
2695 { PREFIX_TABLE (PREFIX_0F1E
) },
2696 { "nopQ", { Ev
}, 0 },
2698 { "movZ", { Rm
, Cm
}, 0 },
2699 { "movZ", { Rm
, Dm
}, 0 },
2700 { "movZ", { Cm
, Rm
}, 0 },
2701 { "movZ", { Dm
, Rm
}, 0 },
2702 { MOD_TABLE (MOD_0F24
) },
2704 { MOD_TABLE (MOD_0F26
) },
2707 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2708 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2709 { PREFIX_TABLE (PREFIX_0F2A
) },
2710 { PREFIX_TABLE (PREFIX_0F2B
) },
2711 { PREFIX_TABLE (PREFIX_0F2C
) },
2712 { PREFIX_TABLE (PREFIX_0F2D
) },
2713 { PREFIX_TABLE (PREFIX_0F2E
) },
2714 { PREFIX_TABLE (PREFIX_0F2F
) },
2716 { "wrmsr", { XX
}, 0 },
2717 { "rdtsc", { XX
}, 0 },
2718 { "rdmsr", { XX
}, 0 },
2719 { "rdpmc", { XX
}, 0 },
2720 { "sysenter", { SEP
}, 0 },
2721 { "sysexit", { SEP
}, 0 },
2723 { "getsec", { XX
}, 0 },
2725 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2727 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2734 { "cmovoS", { Gv
, Ev
}, 0 },
2735 { "cmovnoS", { Gv
, Ev
}, 0 },
2736 { "cmovbS", { Gv
, Ev
}, 0 },
2737 { "cmovaeS", { Gv
, Ev
}, 0 },
2738 { "cmoveS", { Gv
, Ev
}, 0 },
2739 { "cmovneS", { Gv
, Ev
}, 0 },
2740 { "cmovbeS", { Gv
, Ev
}, 0 },
2741 { "cmovaS", { Gv
, Ev
}, 0 },
2743 { "cmovsS", { Gv
, Ev
}, 0 },
2744 { "cmovnsS", { Gv
, Ev
}, 0 },
2745 { "cmovpS", { Gv
, Ev
}, 0 },
2746 { "cmovnpS", { Gv
, Ev
}, 0 },
2747 { "cmovlS", { Gv
, Ev
}, 0 },
2748 { "cmovgeS", { Gv
, Ev
}, 0 },
2749 { "cmovleS", { Gv
, Ev
}, 0 },
2750 { "cmovgS", { Gv
, Ev
}, 0 },
2752 { MOD_TABLE (MOD_0F51
) },
2753 { PREFIX_TABLE (PREFIX_0F51
) },
2754 { PREFIX_TABLE (PREFIX_0F52
) },
2755 { PREFIX_TABLE (PREFIX_0F53
) },
2756 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2757 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2758 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2759 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2761 { PREFIX_TABLE (PREFIX_0F58
) },
2762 { PREFIX_TABLE (PREFIX_0F59
) },
2763 { PREFIX_TABLE (PREFIX_0F5A
) },
2764 { PREFIX_TABLE (PREFIX_0F5B
) },
2765 { PREFIX_TABLE (PREFIX_0F5C
) },
2766 { PREFIX_TABLE (PREFIX_0F5D
) },
2767 { PREFIX_TABLE (PREFIX_0F5E
) },
2768 { PREFIX_TABLE (PREFIX_0F5F
) },
2770 { PREFIX_TABLE (PREFIX_0F60
) },
2771 { PREFIX_TABLE (PREFIX_0F61
) },
2772 { PREFIX_TABLE (PREFIX_0F62
) },
2773 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2780 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2783 { PREFIX_TABLE (PREFIX_0F6C
) },
2784 { PREFIX_TABLE (PREFIX_0F6D
) },
2785 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2786 { PREFIX_TABLE (PREFIX_0F6F
) },
2788 { PREFIX_TABLE (PREFIX_0F70
) },
2789 { REG_TABLE (REG_0F71
) },
2790 { REG_TABLE (REG_0F72
) },
2791 { REG_TABLE (REG_0F73
) },
2792 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2793 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2794 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2795 { "emms", { XX
}, PREFIX_OPCODE
},
2797 { PREFIX_TABLE (PREFIX_0F78
) },
2798 { PREFIX_TABLE (PREFIX_0F79
) },
2801 { PREFIX_TABLE (PREFIX_0F7C
) },
2802 { PREFIX_TABLE (PREFIX_0F7D
) },
2803 { PREFIX_TABLE (PREFIX_0F7E
) },
2804 { PREFIX_TABLE (PREFIX_0F7F
) },
2806 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2808 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2821 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2822 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2824 { "seto", { Eb
}, 0 },
2825 { "setno", { Eb
}, 0 },
2826 { "setb", { Eb
}, 0 },
2827 { "setae", { Eb
}, 0 },
2828 { "sete", { Eb
}, 0 },
2829 { "setne", { Eb
}, 0 },
2830 { "setbe", { Eb
}, 0 },
2831 { "seta", { Eb
}, 0 },
2833 { "sets", { Eb
}, 0 },
2834 { "setns", { Eb
}, 0 },
2835 { "setp", { Eb
}, 0 },
2836 { "setnp", { Eb
}, 0 },
2837 { "setl", { Eb
}, 0 },
2838 { "setge", { Eb
}, 0 },
2839 { "setle", { Eb
}, 0 },
2840 { "setg", { Eb
}, 0 },
2842 { "pushT", { fs
}, 0 },
2843 { "popT", { fs
}, 0 },
2844 { "cpuid", { XX
}, 0 },
2845 { "btS", { Ev
, Gv
}, 0 },
2846 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2847 { "shldS", { Ev
, Gv
, CL
}, 0 },
2848 { REG_TABLE (REG_0FA6
) },
2849 { REG_TABLE (REG_0FA7
) },
2851 { "pushT", { gs
}, 0 },
2852 { "popT", { gs
}, 0 },
2853 { "rsm", { XX
}, 0 },
2854 { "btsS", { Evh1
, Gv
}, 0 },
2855 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2856 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2857 { REG_TABLE (REG_0FAE
) },
2858 { "imulS", { Gv
, Ev
}, 0 },
2860 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2861 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2862 { MOD_TABLE (MOD_0FB2
) },
2863 { "btrS", { Evh1
, Gv
}, 0 },
2864 { MOD_TABLE (MOD_0FB4
) },
2865 { MOD_TABLE (MOD_0FB5
) },
2866 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2867 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2869 { PREFIX_TABLE (PREFIX_0FB8
) },
2870 { "ud1S", { Gv
, Ev
}, 0 },
2871 { REG_TABLE (REG_0FBA
) },
2872 { "btcS", { Evh1
, Gv
}, 0 },
2873 { PREFIX_TABLE (PREFIX_0FBC
) },
2874 { PREFIX_TABLE (PREFIX_0FBD
) },
2875 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2876 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2878 { "xaddB", { Ebh1
, Gb
}, 0 },
2879 { "xaddS", { Evh1
, Gv
}, 0 },
2880 { PREFIX_TABLE (PREFIX_0FC2
) },
2881 { MOD_TABLE (MOD_0FC3
) },
2882 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2883 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2884 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2885 { REG_TABLE (REG_0FC7
) },
2887 { "bswap", { RMeAX
}, 0 },
2888 { "bswap", { RMeCX
}, 0 },
2889 { "bswap", { RMeDX
}, 0 },
2890 { "bswap", { RMeBX
}, 0 },
2891 { "bswap", { RMeSP
}, 0 },
2892 { "bswap", { RMeBP
}, 0 },
2893 { "bswap", { RMeSI
}, 0 },
2894 { "bswap", { RMeDI
}, 0 },
2896 { PREFIX_TABLE (PREFIX_0FD0
) },
2897 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2898 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2899 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2902 { PREFIX_TABLE (PREFIX_0FD6
) },
2903 { MOD_TABLE (MOD_0FD7
) },
2905 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2907 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2915 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { PREFIX_TABLE (PREFIX_0FE6
) },
2921 { PREFIX_TABLE (PREFIX_0FE7
) },
2923 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2925 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2932 { PREFIX_TABLE (PREFIX_0FF0
) },
2933 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2934 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2935 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2939 { PREFIX_TABLE (PREFIX_0FF7
) },
2941 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2943 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2945 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2946 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2947 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2948 { "ud0S", { Gv
, Ev
}, 0 },
2951 static const unsigned char onebyte_has_modrm
[256] = {
2952 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2953 /* ------------------------------- */
2954 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2955 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2956 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2957 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2958 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2959 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2960 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2961 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2962 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2963 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2964 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2965 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2966 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2967 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2968 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2969 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2970 /* ------------------------------- */
2971 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2974 static const unsigned char twobyte_has_modrm
[256] = {
2975 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2976 /* ------------------------------- */
2977 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2978 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2979 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2980 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2981 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2982 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2983 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2984 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2985 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2986 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2987 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2988 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2989 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2990 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2991 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2992 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2993 /* ------------------------------- */
2994 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2997 static char obuf
[100];
2999 static char *mnemonicendp
;
3000 static char scratchbuf
[100];
3001 static unsigned char *start_codep
;
3002 static unsigned char *insn_codep
;
3003 static unsigned char *codep
;
3004 static unsigned char *end_codep
;
3005 static int last_lock_prefix
;
3006 static int last_repz_prefix
;
3007 static int last_repnz_prefix
;
3008 static int last_data_prefix
;
3009 static int last_addr_prefix
;
3010 static int last_rex_prefix
;
3011 static int last_seg_prefix
;
3012 static int fwait_prefix
;
3013 /* The active segment register prefix. */
3014 static int active_seg_prefix
;
3015 #define MAX_CODE_LENGTH 15
3016 /* We can up to 14 prefixes since the maximum instruction length is
3018 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3019 static disassemble_info
*the_info
;
3027 static unsigned char need_modrm
;
3037 int register_specifier
;
3044 int mask_register_specifier
;
3050 static unsigned char need_vex
;
3051 static unsigned char need_vex_reg
;
3052 static unsigned char vex_w_done
;
3060 /* If we are accessing mod/rm/reg without need_modrm set, then the
3061 values are stale. Hitting this abort likely indicates that you
3062 need to update onebyte_has_modrm or twobyte_has_modrm. */
3063 #define MODRM_CHECK if (!need_modrm) abort ()
3065 static const char **names64
;
3066 static const char **names32
;
3067 static const char **names16
;
3068 static const char **names8
;
3069 static const char **names8rex
;
3070 static const char **names_seg
;
3071 static const char *index64
;
3072 static const char *index32
;
3073 static const char **index16
;
3074 static const char **names_bnd
;
3076 static const char *intel_names64
[] = {
3077 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3078 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3080 static const char *intel_names32
[] = {
3081 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3082 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3084 static const char *intel_names16
[] = {
3085 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3086 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3088 static const char *intel_names8
[] = {
3089 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3091 static const char *intel_names8rex
[] = {
3092 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3093 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3095 static const char *intel_names_seg
[] = {
3096 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3098 static const char *intel_index64
= "riz";
3099 static const char *intel_index32
= "eiz";
3100 static const char *intel_index16
[] = {
3101 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3104 static const char *att_names64
[] = {
3105 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3106 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3108 static const char *att_names32
[] = {
3109 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3110 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3112 static const char *att_names16
[] = {
3113 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3114 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3116 static const char *att_names8
[] = {
3117 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3119 static const char *att_names8rex
[] = {
3120 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3121 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3123 static const char *att_names_seg
[] = {
3124 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3126 static const char *att_index64
= "%riz";
3127 static const char *att_index32
= "%eiz";
3128 static const char *att_index16
[] = {
3129 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3132 static const char **names_mm
;
3133 static const char *intel_names_mm
[] = {
3134 "mm0", "mm1", "mm2", "mm3",
3135 "mm4", "mm5", "mm6", "mm7"
3137 static const char *att_names_mm
[] = {
3138 "%mm0", "%mm1", "%mm2", "%mm3",
3139 "%mm4", "%mm5", "%mm6", "%mm7"
3142 static const char *intel_names_bnd
[] = {
3143 "bnd0", "bnd1", "bnd2", "bnd3"
3146 static const char *att_names_bnd
[] = {
3147 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3150 static const char **names_xmm
;
3151 static const char *intel_names_xmm
[] = {
3152 "xmm0", "xmm1", "xmm2", "xmm3",
3153 "xmm4", "xmm5", "xmm6", "xmm7",
3154 "xmm8", "xmm9", "xmm10", "xmm11",
3155 "xmm12", "xmm13", "xmm14", "xmm15",
3156 "xmm16", "xmm17", "xmm18", "xmm19",
3157 "xmm20", "xmm21", "xmm22", "xmm23",
3158 "xmm24", "xmm25", "xmm26", "xmm27",
3159 "xmm28", "xmm29", "xmm30", "xmm31"
3161 static const char *att_names_xmm
[] = {
3162 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3163 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3164 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3165 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3166 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3167 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3168 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3169 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3172 static const char **names_ymm
;
3173 static const char *intel_names_ymm
[] = {
3174 "ymm0", "ymm1", "ymm2", "ymm3",
3175 "ymm4", "ymm5", "ymm6", "ymm7",
3176 "ymm8", "ymm9", "ymm10", "ymm11",
3177 "ymm12", "ymm13", "ymm14", "ymm15",
3178 "ymm16", "ymm17", "ymm18", "ymm19",
3179 "ymm20", "ymm21", "ymm22", "ymm23",
3180 "ymm24", "ymm25", "ymm26", "ymm27",
3181 "ymm28", "ymm29", "ymm30", "ymm31"
3183 static const char *att_names_ymm
[] = {
3184 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3185 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3186 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3187 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3188 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3189 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3190 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3191 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3194 static const char **names_zmm
;
3195 static const char *intel_names_zmm
[] = {
3196 "zmm0", "zmm1", "zmm2", "zmm3",
3197 "zmm4", "zmm5", "zmm6", "zmm7",
3198 "zmm8", "zmm9", "zmm10", "zmm11",
3199 "zmm12", "zmm13", "zmm14", "zmm15",
3200 "zmm16", "zmm17", "zmm18", "zmm19",
3201 "zmm20", "zmm21", "zmm22", "zmm23",
3202 "zmm24", "zmm25", "zmm26", "zmm27",
3203 "zmm28", "zmm29", "zmm30", "zmm31"
3205 static const char *att_names_zmm
[] = {
3206 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3207 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3208 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3209 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3210 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3211 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3212 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3213 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3216 static const char **names_mask
;
3217 static const char *intel_names_mask
[] = {
3218 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3220 static const char *att_names_mask
[] = {
3221 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3224 static const char *names_rounding
[] =
3232 static const struct dis386 reg_table
[][8] = {
3235 { "addA", { Ebh1
, Ib
}, 0 },
3236 { "orA", { Ebh1
, Ib
}, 0 },
3237 { "adcA", { Ebh1
, Ib
}, 0 },
3238 { "sbbA", { Ebh1
, Ib
}, 0 },
3239 { "andA", { Ebh1
, Ib
}, 0 },
3240 { "subA", { Ebh1
, Ib
}, 0 },
3241 { "xorA", { Ebh1
, Ib
}, 0 },
3242 { "cmpA", { Eb
, Ib
}, 0 },
3246 { "addQ", { Evh1
, Iv
}, 0 },
3247 { "orQ", { Evh1
, Iv
}, 0 },
3248 { "adcQ", { Evh1
, Iv
}, 0 },
3249 { "sbbQ", { Evh1
, Iv
}, 0 },
3250 { "andQ", { Evh1
, Iv
}, 0 },
3251 { "subQ", { Evh1
, Iv
}, 0 },
3252 { "xorQ", { Evh1
, Iv
}, 0 },
3253 { "cmpQ", { Ev
, Iv
}, 0 },
3257 { "addQ", { Evh1
, sIb
}, 0 },
3258 { "orQ", { Evh1
, sIb
}, 0 },
3259 { "adcQ", { Evh1
, sIb
}, 0 },
3260 { "sbbQ", { Evh1
, sIb
}, 0 },
3261 { "andQ", { Evh1
, sIb
}, 0 },
3262 { "subQ", { Evh1
, sIb
}, 0 },
3263 { "xorQ", { Evh1
, sIb
}, 0 },
3264 { "cmpQ", { Ev
, sIb
}, 0 },
3268 { "popU", { stackEv
}, 0 },
3269 { XOP_8F_TABLE (XOP_09
) },
3273 { XOP_8F_TABLE (XOP_09
) },
3277 { "rolA", { Eb
, Ib
}, 0 },
3278 { "rorA", { Eb
, Ib
}, 0 },
3279 { "rclA", { Eb
, Ib
}, 0 },
3280 { "rcrA", { Eb
, Ib
}, 0 },
3281 { "shlA", { Eb
, Ib
}, 0 },
3282 { "shrA", { Eb
, Ib
}, 0 },
3283 { "shlA", { Eb
, Ib
}, 0 },
3284 { "sarA", { Eb
, Ib
}, 0 },
3288 { "rolQ", { Ev
, Ib
}, 0 },
3289 { "rorQ", { Ev
, Ib
}, 0 },
3290 { "rclQ", { Ev
, Ib
}, 0 },
3291 { "rcrQ", { Ev
, Ib
}, 0 },
3292 { "shlQ", { Ev
, Ib
}, 0 },
3293 { "shrQ", { Ev
, Ib
}, 0 },
3294 { "shlQ", { Ev
, Ib
}, 0 },
3295 { "sarQ", { Ev
, Ib
}, 0 },
3299 { "movA", { Ebh3
, Ib
}, 0 },
3306 { MOD_TABLE (MOD_C6_REG_7
) },
3310 { "movQ", { Evh3
, Iv
}, 0 },
3317 { MOD_TABLE (MOD_C7_REG_7
) },
3321 { "rolA", { Eb
, I1
}, 0 },
3322 { "rorA", { Eb
, I1
}, 0 },
3323 { "rclA", { Eb
, I1
}, 0 },
3324 { "rcrA", { Eb
, I1
}, 0 },
3325 { "shlA", { Eb
, I1
}, 0 },
3326 { "shrA", { Eb
, I1
}, 0 },
3327 { "shlA", { Eb
, I1
}, 0 },
3328 { "sarA", { Eb
, I1
}, 0 },
3332 { "rolQ", { Ev
, I1
}, 0 },
3333 { "rorQ", { Ev
, I1
}, 0 },
3334 { "rclQ", { Ev
, I1
}, 0 },
3335 { "rcrQ", { Ev
, I1
}, 0 },
3336 { "shlQ", { Ev
, I1
}, 0 },
3337 { "shrQ", { Ev
, I1
}, 0 },
3338 { "shlQ", { Ev
, I1
}, 0 },
3339 { "sarQ", { Ev
, I1
}, 0 },
3343 { "rolA", { Eb
, CL
}, 0 },
3344 { "rorA", { Eb
, CL
}, 0 },
3345 { "rclA", { Eb
, CL
}, 0 },
3346 { "rcrA", { Eb
, CL
}, 0 },
3347 { "shlA", { Eb
, CL
}, 0 },
3348 { "shrA", { Eb
, CL
}, 0 },
3349 { "shlA", { Eb
, CL
}, 0 },
3350 { "sarA", { Eb
, CL
}, 0 },
3354 { "rolQ", { Ev
, CL
}, 0 },
3355 { "rorQ", { Ev
, CL
}, 0 },
3356 { "rclQ", { Ev
, CL
}, 0 },
3357 { "rcrQ", { Ev
, CL
}, 0 },
3358 { "shlQ", { Ev
, CL
}, 0 },
3359 { "shrQ", { Ev
, CL
}, 0 },
3360 { "shlQ", { Ev
, CL
}, 0 },
3361 { "sarQ", { Ev
, CL
}, 0 },
3365 { "testA", { Eb
, Ib
}, 0 },
3366 { "testA", { Eb
, Ib
}, 0 },
3367 { "notA", { Ebh1
}, 0 },
3368 { "negA", { Ebh1
}, 0 },
3369 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3370 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3371 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3372 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3376 { "testQ", { Ev
, Iv
}, 0 },
3377 { "testQ", { Ev
, Iv
}, 0 },
3378 { "notQ", { Evh1
}, 0 },
3379 { "negQ", { Evh1
}, 0 },
3380 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3381 { "imulQ", { Ev
}, 0 },
3382 { "divQ", { Ev
}, 0 },
3383 { "idivQ", { Ev
}, 0 },
3387 { "incA", { Ebh1
}, 0 },
3388 { "decA", { Ebh1
}, 0 },
3392 { "incQ", { Evh1
}, 0 },
3393 { "decQ", { Evh1
}, 0 },
3394 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3395 { MOD_TABLE (MOD_FF_REG_3
) },
3396 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3397 { MOD_TABLE (MOD_FF_REG_5
) },
3398 { "pushU", { stackEv
}, 0 },
3403 { "sldtD", { Sv
}, 0 },
3404 { "strD", { Sv
}, 0 },
3405 { "lldt", { Ew
}, 0 },
3406 { "ltr", { Ew
}, 0 },
3407 { "verr", { Ew
}, 0 },
3408 { "verw", { Ew
}, 0 },
3414 { MOD_TABLE (MOD_0F01_REG_0
) },
3415 { MOD_TABLE (MOD_0F01_REG_1
) },
3416 { MOD_TABLE (MOD_0F01_REG_2
) },
3417 { MOD_TABLE (MOD_0F01_REG_3
) },
3418 { "smswD", { Sv
}, 0 },
3419 { MOD_TABLE (MOD_0F01_REG_5
) },
3420 { "lmsw", { Ew
}, 0 },
3421 { MOD_TABLE (MOD_0F01_REG_7
) },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetchw", { Mb
}, 0 },
3427 { "prefetchwt1", { Mb
}, 0 },
3428 { "prefetch", { Mb
}, 0 },
3429 { "prefetch", { Mb
}, 0 },
3430 { "prefetch", { Mb
}, 0 },
3431 { "prefetch", { Mb
}, 0 },
3432 { "prefetch", { Mb
}, 0 },
3436 { MOD_TABLE (MOD_0F18_REG_0
) },
3437 { MOD_TABLE (MOD_0F18_REG_1
) },
3438 { MOD_TABLE (MOD_0F18_REG_2
) },
3439 { MOD_TABLE (MOD_0F18_REG_3
) },
3440 { MOD_TABLE (MOD_0F18_REG_4
) },
3441 { MOD_TABLE (MOD_0F18_REG_5
) },
3442 { MOD_TABLE (MOD_0F18_REG_6
) },
3443 { MOD_TABLE (MOD_0F18_REG_7
) },
3445 /* REG_0F1C_P_0_MOD_0 */
3447 { "cldemote", { Mb
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3449 { "nopQ", { Ev
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3451 { "nopQ", { Ev
}, 0 },
3452 { "nopQ", { Ev
}, 0 },
3453 { "nopQ", { Ev
}, 0 },
3454 { "nopQ", { Ev
}, 0 },
3456 /* REG_0F1E_P_1_MOD_3 */
3458 { "nopQ", { Ev
}, 0 },
3459 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3460 { "nopQ", { Ev
}, 0 },
3461 { "nopQ", { Ev
}, 0 },
3462 { "nopQ", { Ev
}, 0 },
3463 { "nopQ", { Ev
}, 0 },
3464 { "nopQ", { Ev
}, 0 },
3465 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3471 { MOD_TABLE (MOD_0F71_REG_2
) },
3473 { MOD_TABLE (MOD_0F71_REG_4
) },
3475 { MOD_TABLE (MOD_0F71_REG_6
) },
3481 { MOD_TABLE (MOD_0F72_REG_2
) },
3483 { MOD_TABLE (MOD_0F72_REG_4
) },
3485 { MOD_TABLE (MOD_0F72_REG_6
) },
3491 { MOD_TABLE (MOD_0F73_REG_2
) },
3492 { MOD_TABLE (MOD_0F73_REG_3
) },
3495 { MOD_TABLE (MOD_0F73_REG_6
) },
3496 { MOD_TABLE (MOD_0F73_REG_7
) },
3500 { "montmul", { { OP_0f07
, 0 } }, 0 },
3501 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3502 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3506 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3507 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3508 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3509 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3510 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3511 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3515 { MOD_TABLE (MOD_0FAE_REG_0
) },
3516 { MOD_TABLE (MOD_0FAE_REG_1
) },
3517 { MOD_TABLE (MOD_0FAE_REG_2
) },
3518 { MOD_TABLE (MOD_0FAE_REG_3
) },
3519 { MOD_TABLE (MOD_0FAE_REG_4
) },
3520 { MOD_TABLE (MOD_0FAE_REG_5
) },
3521 { MOD_TABLE (MOD_0FAE_REG_6
) },
3522 { MOD_TABLE (MOD_0FAE_REG_7
) },
3530 { "btQ", { Ev
, Ib
}, 0 },
3531 { "btsQ", { Evh1
, Ib
}, 0 },
3532 { "btrQ", { Evh1
, Ib
}, 0 },
3533 { "btcQ", { Evh1
, Ib
}, 0 },
3538 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3540 { MOD_TABLE (MOD_0FC7_REG_3
) },
3541 { MOD_TABLE (MOD_0FC7_REG_4
) },
3542 { MOD_TABLE (MOD_0FC7_REG_5
) },
3543 { MOD_TABLE (MOD_0FC7_REG_6
) },
3544 { MOD_TABLE (MOD_0FC7_REG_7
) },
3550 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3552 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3554 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3560 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3562 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3564 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3570 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3571 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3574 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3575 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3581 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3582 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3584 /* REG_VEX_0F38F3 */
3587 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3588 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3589 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3593 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3594 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3598 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3599 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3601 /* REG_XOP_TBM_01 */
3604 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3605 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3609 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3610 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3612 /* REG_XOP_TBM_02 */
3615 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3620 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3623 #include "i386-dis-evex-reg.h"
3626 static const struct dis386 prefix_table
[][4] = {
3629 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3630 { "pause", { XX
}, 0 },
3631 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3632 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3635 /* PREFIX_0F01_REG_5_MOD_0 */
3638 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3641 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3644 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3647 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3650 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3653 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3655 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3656 { "mcommit", { Skip_MODRM
}, 0 },
3659 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3661 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3666 { "wbinvd", { XX
}, 0 },
3667 { "wbnoinvd", { XX
}, 0 },
3672 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3673 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3674 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3675 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3680 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3681 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3682 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3683 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3688 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3689 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3690 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3691 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3696 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3697 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3698 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3703 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3704 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3705 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3706 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3711 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3712 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3713 { "bndmov", { EbndS
, Gbnd
}, 0 },
3714 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3719 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3720 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3721 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3722 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3727 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3728 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3729 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3730 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3735 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3736 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3737 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3738 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3743 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3744 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3745 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3746 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3751 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3752 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3753 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3754 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3759 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3760 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3761 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3762 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3767 { "ucomiss",{ XM
, EXd
}, 0 },
3769 { "ucomisd",{ XM
, EXq
}, 0 },
3774 { "comiss", { XM
, EXd
}, 0 },
3776 { "comisd", { XM
, EXq
}, 0 },
3781 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3782 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3783 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3784 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3789 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3790 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3795 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3796 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3801 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3802 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3803 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3804 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3809 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3810 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3811 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3812 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3817 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3818 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3819 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3820 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3825 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3826 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3827 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3832 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3833 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3834 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3835 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3840 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3841 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3842 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3843 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3848 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3849 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3850 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3851 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3856 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3858 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3864 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3866 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3871 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3873 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3878 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3880 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3887 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3894 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3899 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3900 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3901 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3906 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3907 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3908 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3909 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3912 /* PREFIX_0F73_REG_3 */
3916 { "psrldq", { XS
, Ib
}, 0 },
3919 /* PREFIX_0F73_REG_7 */
3923 { "pslldq", { XS
, Ib
}, 0 },
3928 {"vmread", { Em
, Gm
}, 0 },
3930 {"extrq", { XS
, Ib
, Ib
}, 0 },
3931 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3936 {"vmwrite", { Gm
, Em
}, 0 },
3938 {"extrq", { XM
, XS
}, 0 },
3939 {"insertq", { XM
, XS
}, 0 },
3946 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3947 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3954 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3955 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3960 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3961 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3962 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3967 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3968 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3969 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3972 /* PREFIX_0FAE_REG_0_MOD_3 */
3975 { "rdfsbase", { Ev
}, 0 },
3978 /* PREFIX_0FAE_REG_1_MOD_3 */
3981 { "rdgsbase", { Ev
}, 0 },
3984 /* PREFIX_0FAE_REG_2_MOD_3 */
3987 { "wrfsbase", { Ev
}, 0 },
3990 /* PREFIX_0FAE_REG_3_MOD_3 */
3993 { "wrgsbase", { Ev
}, 0 },
3996 /* PREFIX_0FAE_REG_4_MOD_0 */
3998 { "xsave", { FXSAVE
}, 0 },
3999 { "ptwrite%LQ", { Edq
}, 0 },
4002 /* PREFIX_0FAE_REG_4_MOD_3 */
4005 { "ptwrite%LQ", { Edq
}, 0 },
4008 /* PREFIX_0FAE_REG_5_MOD_0 */
4010 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4013 /* PREFIX_0FAE_REG_5_MOD_3 */
4015 { "lfence", { Skip_MODRM
}, 0 },
4016 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4019 /* PREFIX_0FAE_REG_6_MOD_0 */
4021 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4022 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4023 { "clwb", { Mb
}, PREFIX_OPCODE
},
4026 /* PREFIX_0FAE_REG_6_MOD_3 */
4028 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4029 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4030 { "tpause", { Edq
}, PREFIX_OPCODE
},
4031 { "umwait", { Edq
}, PREFIX_OPCODE
},
4034 /* PREFIX_0FAE_REG_7_MOD_0 */
4036 { "clflush", { Mb
}, 0 },
4038 { "clflushopt", { Mb
}, 0 },
4044 { "popcntS", { Gv
, Ev
}, 0 },
4049 { "bsfS", { Gv
, Ev
}, 0 },
4050 { "tzcntS", { Gv
, Ev
}, 0 },
4051 { "bsfS", { Gv
, Ev
}, 0 },
4056 { "bsrS", { Gv
, Ev
}, 0 },
4057 { "lzcntS", { Gv
, Ev
}, 0 },
4058 { "bsrS", { Gv
, Ev
}, 0 },
4063 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4064 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4065 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4066 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4069 /* PREFIX_0FC3_MOD_0 */
4071 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4074 /* PREFIX_0FC7_REG_6_MOD_0 */
4076 { "vmptrld",{ Mq
}, 0 },
4077 { "vmxon", { Mq
}, 0 },
4078 { "vmclear",{ Mq
}, 0 },
4081 /* PREFIX_0FC7_REG_6_MOD_3 */
4083 { "rdrand", { Ev
}, 0 },
4085 { "rdrand", { Ev
}, 0 }
4088 /* PREFIX_0FC7_REG_7_MOD_3 */
4090 { "rdseed", { Ev
}, 0 },
4091 { "rdpid", { Em
}, 0 },
4092 { "rdseed", { Ev
}, 0 },
4099 { "addsubpd", { XM
, EXx
}, 0 },
4100 { "addsubps", { XM
, EXx
}, 0 },
4106 { "movq2dq",{ XM
, MS
}, 0 },
4107 { "movq", { EXqS
, XM
}, 0 },
4108 { "movdq2q",{ MX
, XS
}, 0 },
4114 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4115 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4116 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4121 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4123 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4131 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4136 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4138 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4145 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4152 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4159 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4166 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4173 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4180 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4187 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4194 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4201 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4208 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4215 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4222 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4229 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4236 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4243 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4250 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4257 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4264 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4271 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4278 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4285 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4313 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4320 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4327 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4334 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4341 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4348 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4355 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4362 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4369 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4376 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4381 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4386 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4391 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4396 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4401 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4406 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4413 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4420 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4427 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4434 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4441 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4448 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4453 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4455 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4456 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4461 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4463 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4464 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4471 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4476 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4477 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4478 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4485 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4486 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4487 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4492 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4499 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4513 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4520 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4527 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4534 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4541 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4548 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4555 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4562 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4569 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4576 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4583 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4590 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4597 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4604 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4611 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4618 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4625 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4632 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4639 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4646 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4651 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4658 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4665 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4672 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4675 /* PREFIX_VEX_0F10 */
4677 { "vmovups", { XM
, EXx
}, 0 },
4678 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4679 { "vmovupd", { XM
, EXx
}, 0 },
4680 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4683 /* PREFIX_VEX_0F11 */
4685 { "vmovups", { EXxS
, XM
}, 0 },
4686 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4687 { "vmovupd", { EXxS
, XM
}, 0 },
4688 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4691 /* PREFIX_VEX_0F12 */
4693 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4694 { "vmovsldup", { XM
, EXx
}, 0 },
4695 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4696 { "vmovddup", { XM
, EXymmq
}, 0 },
4699 /* PREFIX_VEX_0F16 */
4701 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4702 { "vmovshdup", { XM
, EXx
}, 0 },
4703 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4706 /* PREFIX_VEX_0F2A */
4709 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4711 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4714 /* PREFIX_VEX_0F2C */
4717 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4719 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4722 /* PREFIX_VEX_0F2D */
4725 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4727 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4730 /* PREFIX_VEX_0F2E */
4732 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4734 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4737 /* PREFIX_VEX_0F2F */
4739 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4741 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4744 /* PREFIX_VEX_0F41 */
4746 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4751 /* PREFIX_VEX_0F42 */
4753 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4758 /* PREFIX_VEX_0F44 */
4760 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4765 /* PREFIX_VEX_0F45 */
4767 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4772 /* PREFIX_VEX_0F46 */
4774 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4779 /* PREFIX_VEX_0F47 */
4781 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4786 /* PREFIX_VEX_0F4A */
4788 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4793 /* PREFIX_VEX_0F4B */
4795 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4797 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4800 /* PREFIX_VEX_0F51 */
4802 { "vsqrtps", { XM
, EXx
}, 0 },
4803 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4804 { "vsqrtpd", { XM
, EXx
}, 0 },
4805 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4808 /* PREFIX_VEX_0F52 */
4810 { "vrsqrtps", { XM
, EXx
}, 0 },
4811 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4814 /* PREFIX_VEX_0F53 */
4816 { "vrcpps", { XM
, EXx
}, 0 },
4817 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4820 /* PREFIX_VEX_0F58 */
4822 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4823 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4824 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4825 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4828 /* PREFIX_VEX_0F59 */
4830 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4831 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4832 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4833 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4836 /* PREFIX_VEX_0F5A */
4838 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4839 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4840 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4841 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4844 /* PREFIX_VEX_0F5B */
4846 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4847 { "vcvttps2dq", { XM
, EXx
}, 0 },
4848 { "vcvtps2dq", { XM
, EXx
}, 0 },
4851 /* PREFIX_VEX_0F5C */
4853 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4854 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4855 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4856 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4859 /* PREFIX_VEX_0F5D */
4861 { "vminps", { XM
, Vex
, EXx
}, 0 },
4862 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4863 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4864 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4867 /* PREFIX_VEX_0F5E */
4869 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4870 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4871 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4872 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4875 /* PREFIX_VEX_0F5F */
4877 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4878 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4879 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4880 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4883 /* PREFIX_VEX_0F60 */
4887 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4890 /* PREFIX_VEX_0F61 */
4894 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4897 /* PREFIX_VEX_0F62 */
4901 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4904 /* PREFIX_VEX_0F63 */
4908 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4911 /* PREFIX_VEX_0F64 */
4915 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4918 /* PREFIX_VEX_0F65 */
4922 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4925 /* PREFIX_VEX_0F66 */
4929 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4932 /* PREFIX_VEX_0F67 */
4936 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4939 /* PREFIX_VEX_0F68 */
4943 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4946 /* PREFIX_VEX_0F69 */
4950 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F6A */
4957 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4960 /* PREFIX_VEX_0F6B */
4964 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4967 /* PREFIX_VEX_0F6C */
4971 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4974 /* PREFIX_VEX_0F6D */
4978 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4981 /* PREFIX_VEX_0F6E */
4985 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4988 /* PREFIX_VEX_0F6F */
4991 { "vmovdqu", { XM
, EXx
}, 0 },
4992 { "vmovdqa", { XM
, EXx
}, 0 },
4995 /* PREFIX_VEX_0F70 */
4998 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4999 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
5000 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
5003 /* PREFIX_VEX_0F71_REG_2 */
5007 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5010 /* PREFIX_VEX_0F71_REG_4 */
5014 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5017 /* PREFIX_VEX_0F71_REG_6 */
5021 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5024 /* PREFIX_VEX_0F72_REG_2 */
5028 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5031 /* PREFIX_VEX_0F72_REG_4 */
5035 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5038 /* PREFIX_VEX_0F72_REG_6 */
5042 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5045 /* PREFIX_VEX_0F73_REG_2 */
5049 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5052 /* PREFIX_VEX_0F73_REG_3 */
5056 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5059 /* PREFIX_VEX_0F73_REG_6 */
5063 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5066 /* PREFIX_VEX_0F73_REG_7 */
5070 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5073 /* PREFIX_VEX_0F74 */
5077 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5080 /* PREFIX_VEX_0F75 */
5084 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5087 /* PREFIX_VEX_0F76 */
5091 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5094 /* PREFIX_VEX_0F77 */
5096 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5099 /* PREFIX_VEX_0F7C */
5103 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5104 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5107 /* PREFIX_VEX_0F7D */
5111 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5112 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5115 /* PREFIX_VEX_0F7E */
5118 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5119 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5122 /* PREFIX_VEX_0F7F */
5125 { "vmovdqu", { EXxS
, XM
}, 0 },
5126 { "vmovdqa", { EXxS
, XM
}, 0 },
5129 /* PREFIX_VEX_0F90 */
5131 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5133 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5136 /* PREFIX_VEX_0F91 */
5138 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5140 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5143 /* PREFIX_VEX_0F92 */
5145 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5147 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5151 /* PREFIX_VEX_0F93 */
5153 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5155 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5156 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5159 /* PREFIX_VEX_0F98 */
5161 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5163 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5166 /* PREFIX_VEX_0F99 */
5168 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5170 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5173 /* PREFIX_VEX_0FC2 */
5175 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5176 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5177 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5178 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5181 /* PREFIX_VEX_0FC4 */
5185 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5188 /* PREFIX_VEX_0FC5 */
5192 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5195 /* PREFIX_VEX_0FD0 */
5199 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5200 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5203 /* PREFIX_VEX_0FD1 */
5207 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5210 /* PREFIX_VEX_0FD2 */
5214 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5217 /* PREFIX_VEX_0FD3 */
5221 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5224 /* PREFIX_VEX_0FD4 */
5228 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FD5 */
5235 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5238 /* PREFIX_VEX_0FD6 */
5242 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5245 /* PREFIX_VEX_0FD7 */
5249 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5252 /* PREFIX_VEX_0FD8 */
5256 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FD9 */
5263 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FDA */
5270 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FDB */
5277 { "vpand", { XM
, Vex
, EXx
}, 0 },
5280 /* PREFIX_VEX_0FDC */
5284 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5287 /* PREFIX_VEX_0FDD */
5291 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5294 /* PREFIX_VEX_0FDE */
5298 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5301 /* PREFIX_VEX_0FDF */
5305 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE0 */
5312 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5315 /* PREFIX_VEX_0FE1 */
5319 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5322 /* PREFIX_VEX_0FE2 */
5326 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5329 /* PREFIX_VEX_0FE3 */
5333 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5336 /* PREFIX_VEX_0FE4 */
5340 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5343 /* PREFIX_VEX_0FE5 */
5347 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5350 /* PREFIX_VEX_0FE6 */
5353 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5354 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5355 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5358 /* PREFIX_VEX_0FE7 */
5362 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5365 /* PREFIX_VEX_0FE8 */
5369 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FE9 */
5376 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FEA */
5383 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5386 /* PREFIX_VEX_0FEB */
5390 { "vpor", { XM
, Vex
, EXx
}, 0 },
5393 /* PREFIX_VEX_0FEC */
5397 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5400 /* PREFIX_VEX_0FED */
5404 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5407 /* PREFIX_VEX_0FEE */
5411 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5414 /* PREFIX_VEX_0FEF */
5418 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5421 /* PREFIX_VEX_0FF0 */
5426 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5429 /* PREFIX_VEX_0FF1 */
5433 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5436 /* PREFIX_VEX_0FF2 */
5440 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5443 /* PREFIX_VEX_0FF3 */
5447 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5450 /* PREFIX_VEX_0FF4 */
5454 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5457 /* PREFIX_VEX_0FF5 */
5461 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5464 /* PREFIX_VEX_0FF6 */
5468 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5471 /* PREFIX_VEX_0FF7 */
5475 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5478 /* PREFIX_VEX_0FF8 */
5482 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5485 /* PREFIX_VEX_0FF9 */
5489 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5492 /* PREFIX_VEX_0FFA */
5496 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5499 /* PREFIX_VEX_0FFB */
5503 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5506 /* PREFIX_VEX_0FFC */
5510 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5513 /* PREFIX_VEX_0FFD */
5517 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5520 /* PREFIX_VEX_0FFE */
5524 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5527 /* PREFIX_VEX_0F3800 */
5531 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5534 /* PREFIX_VEX_0F3801 */
5538 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5541 /* PREFIX_VEX_0F3802 */
5545 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5548 /* PREFIX_VEX_0F3803 */
5552 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5555 /* PREFIX_VEX_0F3804 */
5559 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5562 /* PREFIX_VEX_0F3805 */
5566 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5569 /* PREFIX_VEX_0F3806 */
5573 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5576 /* PREFIX_VEX_0F3807 */
5580 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5583 /* PREFIX_VEX_0F3808 */
5587 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5590 /* PREFIX_VEX_0F3809 */
5594 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5597 /* PREFIX_VEX_0F380A */
5601 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5604 /* PREFIX_VEX_0F380B */
5608 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5611 /* PREFIX_VEX_0F380C */
5615 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5618 /* PREFIX_VEX_0F380D */
5622 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5625 /* PREFIX_VEX_0F380E */
5629 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5632 /* PREFIX_VEX_0F380F */
5636 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5639 /* PREFIX_VEX_0F3813 */
5643 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5646 /* PREFIX_VEX_0F3816 */
5650 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5653 /* PREFIX_VEX_0F3817 */
5657 { "vptest", { XM
, EXx
}, 0 },
5660 /* PREFIX_VEX_0F3818 */
5664 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5667 /* PREFIX_VEX_0F3819 */
5671 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5674 /* PREFIX_VEX_0F381A */
5678 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5681 /* PREFIX_VEX_0F381C */
5685 { "vpabsb", { XM
, EXx
}, 0 },
5688 /* PREFIX_VEX_0F381D */
5692 { "vpabsw", { XM
, EXx
}, 0 },
5695 /* PREFIX_VEX_0F381E */
5699 { "vpabsd", { XM
, EXx
}, 0 },
5702 /* PREFIX_VEX_0F3820 */
5706 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5709 /* PREFIX_VEX_0F3821 */
5713 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5716 /* PREFIX_VEX_0F3822 */
5720 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5723 /* PREFIX_VEX_0F3823 */
5727 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5730 /* PREFIX_VEX_0F3824 */
5734 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5737 /* PREFIX_VEX_0F3825 */
5741 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5744 /* PREFIX_VEX_0F3828 */
5748 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5751 /* PREFIX_VEX_0F3829 */
5755 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5758 /* PREFIX_VEX_0F382A */
5762 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5765 /* PREFIX_VEX_0F382B */
5769 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5772 /* PREFIX_VEX_0F382C */
5776 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5779 /* PREFIX_VEX_0F382D */
5783 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5786 /* PREFIX_VEX_0F382E */
5790 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5793 /* PREFIX_VEX_0F382F */
5797 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5800 /* PREFIX_VEX_0F3830 */
5804 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5807 /* PREFIX_VEX_0F3831 */
5811 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5814 /* PREFIX_VEX_0F3832 */
5818 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5821 /* PREFIX_VEX_0F3833 */
5825 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5828 /* PREFIX_VEX_0F3834 */
5832 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5835 /* PREFIX_VEX_0F3835 */
5839 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5842 /* PREFIX_VEX_0F3836 */
5846 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5849 /* PREFIX_VEX_0F3837 */
5853 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5856 /* PREFIX_VEX_0F3838 */
5860 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5863 /* PREFIX_VEX_0F3839 */
5867 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5870 /* PREFIX_VEX_0F383A */
5874 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5877 /* PREFIX_VEX_0F383B */
5881 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5884 /* PREFIX_VEX_0F383C */
5888 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5891 /* PREFIX_VEX_0F383D */
5895 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5898 /* PREFIX_VEX_0F383E */
5902 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5905 /* PREFIX_VEX_0F383F */
5909 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5912 /* PREFIX_VEX_0F3840 */
5916 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5919 /* PREFIX_VEX_0F3841 */
5923 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5926 /* PREFIX_VEX_0F3845 */
5930 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5933 /* PREFIX_VEX_0F3846 */
5937 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5940 /* PREFIX_VEX_0F3847 */
5944 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5947 /* PREFIX_VEX_0F3858 */
5951 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5954 /* PREFIX_VEX_0F3859 */
5958 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5961 /* PREFIX_VEX_0F385A */
5965 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5968 /* PREFIX_VEX_0F3878 */
5972 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5975 /* PREFIX_VEX_0F3879 */
5979 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5982 /* PREFIX_VEX_0F388C */
5986 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5989 /* PREFIX_VEX_0F388E */
5993 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5996 /* PREFIX_VEX_0F3890 */
6000 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6003 /* PREFIX_VEX_0F3891 */
6007 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6010 /* PREFIX_VEX_0F3892 */
6014 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6017 /* PREFIX_VEX_0F3893 */
6021 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6024 /* PREFIX_VEX_0F3896 */
6028 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6031 /* PREFIX_VEX_0F3897 */
6035 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6038 /* PREFIX_VEX_0F3898 */
6042 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6045 /* PREFIX_VEX_0F3899 */
6049 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6052 /* PREFIX_VEX_0F389A */
6056 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6059 /* PREFIX_VEX_0F389B */
6063 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6066 /* PREFIX_VEX_0F389C */
6070 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6073 /* PREFIX_VEX_0F389D */
6077 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6080 /* PREFIX_VEX_0F389E */
6084 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6087 /* PREFIX_VEX_0F389F */
6091 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6094 /* PREFIX_VEX_0F38A6 */
6098 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F38A7 */
6106 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6109 /* PREFIX_VEX_0F38A8 */
6113 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6116 /* PREFIX_VEX_0F38A9 */
6120 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6123 /* PREFIX_VEX_0F38AA */
6127 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6130 /* PREFIX_VEX_0F38AB */
6134 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6137 /* PREFIX_VEX_0F38AC */
6141 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6144 /* PREFIX_VEX_0F38AD */
6148 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6151 /* PREFIX_VEX_0F38AE */
6155 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6158 /* PREFIX_VEX_0F38AF */
6162 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6165 /* PREFIX_VEX_0F38B6 */
6169 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6172 /* PREFIX_VEX_0F38B7 */
6176 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6179 /* PREFIX_VEX_0F38B8 */
6183 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6186 /* PREFIX_VEX_0F38B9 */
6190 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6193 /* PREFIX_VEX_0F38BA */
6197 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6200 /* PREFIX_VEX_0F38BB */
6204 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6207 /* PREFIX_VEX_0F38BC */
6211 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6214 /* PREFIX_VEX_0F38BD */
6218 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6221 /* PREFIX_VEX_0F38BE */
6225 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6228 /* PREFIX_VEX_0F38BF */
6232 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6235 /* PREFIX_VEX_0F38CF */
6239 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6242 /* PREFIX_VEX_0F38DB */
6246 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6249 /* PREFIX_VEX_0F38DC */
6253 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6256 /* PREFIX_VEX_0F38DD */
6260 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6263 /* PREFIX_VEX_0F38DE */
6267 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6270 /* PREFIX_VEX_0F38DF */
6274 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6277 /* PREFIX_VEX_0F38F2 */
6279 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6282 /* PREFIX_VEX_0F38F3_REG_1 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6287 /* PREFIX_VEX_0F38F3_REG_2 */
6289 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6292 /* PREFIX_VEX_0F38F3_REG_3 */
6294 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6297 /* PREFIX_VEX_0F38F5 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6300 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6302 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6305 /* PREFIX_VEX_0F38F6 */
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6313 /* PREFIX_VEX_0F38F7 */
6315 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6316 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6317 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6318 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6321 /* PREFIX_VEX_0F3A00 */
6325 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6328 /* PREFIX_VEX_0F3A01 */
6332 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6335 /* PREFIX_VEX_0F3A02 */
6339 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6342 /* PREFIX_VEX_0F3A04 */
6346 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6349 /* PREFIX_VEX_0F3A05 */
6353 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6356 /* PREFIX_VEX_0F3A06 */
6360 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6363 /* PREFIX_VEX_0F3A08 */
6367 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6370 /* PREFIX_VEX_0F3A09 */
6374 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6377 /* PREFIX_VEX_0F3A0A */
6381 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6384 /* PREFIX_VEX_0F3A0B */
6388 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6391 /* PREFIX_VEX_0F3A0C */
6395 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6398 /* PREFIX_VEX_0F3A0D */
6402 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6405 /* PREFIX_VEX_0F3A0E */
6409 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6412 /* PREFIX_VEX_0F3A0F */
6416 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6419 /* PREFIX_VEX_0F3A14 */
6423 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6426 /* PREFIX_VEX_0F3A15 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6433 /* PREFIX_VEX_0F3A16 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6440 /* PREFIX_VEX_0F3A17 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6447 /* PREFIX_VEX_0F3A18 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6454 /* PREFIX_VEX_0F3A19 */
6458 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6461 /* PREFIX_VEX_0F3A1D */
6465 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6468 /* PREFIX_VEX_0F3A20 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6475 /* PREFIX_VEX_0F3A21 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6482 /* PREFIX_VEX_0F3A22 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6489 /* PREFIX_VEX_0F3A30 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6496 /* PREFIX_VEX_0F3A31 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6503 /* PREFIX_VEX_0F3A32 */
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6510 /* PREFIX_VEX_0F3A33 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6517 /* PREFIX_VEX_0F3A38 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6524 /* PREFIX_VEX_0F3A39 */
6528 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6531 /* PREFIX_VEX_0F3A40 */
6535 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6538 /* PREFIX_VEX_0F3A41 */
6542 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6545 /* PREFIX_VEX_0F3A42 */
6549 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6552 /* PREFIX_VEX_0F3A44 */
6556 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6559 /* PREFIX_VEX_0F3A46 */
6563 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6566 /* PREFIX_VEX_0F3A48 */
6570 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6573 /* PREFIX_VEX_0F3A49 */
6577 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6580 /* PREFIX_VEX_0F3A4A */
6584 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6587 /* PREFIX_VEX_0F3A4B */
6591 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6594 /* PREFIX_VEX_0F3A4C */
6598 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6601 /* PREFIX_VEX_0F3A5C */
6605 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6608 /* PREFIX_VEX_0F3A5D */
6612 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6615 /* PREFIX_VEX_0F3A5E */
6619 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6622 /* PREFIX_VEX_0F3A5F */
6626 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6629 /* PREFIX_VEX_0F3A60 */
6633 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6637 /* PREFIX_VEX_0F3A61 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6644 /* PREFIX_VEX_0F3A62 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6651 /* PREFIX_VEX_0F3A63 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6658 /* PREFIX_VEX_0F3A68 */
6662 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6665 /* PREFIX_VEX_0F3A69 */
6669 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6672 /* PREFIX_VEX_0F3A6A */
6676 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6679 /* PREFIX_VEX_0F3A6B */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6686 /* PREFIX_VEX_0F3A6C */
6690 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6693 /* PREFIX_VEX_0F3A6D */
6697 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6700 /* PREFIX_VEX_0F3A6E */
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6707 /* PREFIX_VEX_0F3A6F */
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6714 /* PREFIX_VEX_0F3A78 */
6718 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6721 /* PREFIX_VEX_0F3A79 */
6725 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6728 /* PREFIX_VEX_0F3A7A */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6735 /* PREFIX_VEX_0F3A7B */
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6742 /* PREFIX_VEX_0F3A7C */
6746 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6750 /* PREFIX_VEX_0F3A7D */
6754 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6757 /* PREFIX_VEX_0F3A7E */
6761 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6764 /* PREFIX_VEX_0F3A7F */
6768 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6771 /* PREFIX_VEX_0F3ACE */
6775 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6778 /* PREFIX_VEX_0F3ACF */
6782 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6785 /* PREFIX_VEX_0F3ADF */
6789 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6792 /* PREFIX_VEX_0F3AF0 */
6797 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6800 #include "i386-dis-evex-prefix.h"
6803 static const struct dis386 x86_64_table
[][2] = {
6806 { "pushP", { es
}, 0 },
6811 { "popP", { es
}, 0 },
6816 { "pushP", { cs
}, 0 },
6821 { "pushP", { ss
}, 0 },
6826 { "popP", { ss
}, 0 },
6831 { "pushP", { ds
}, 0 },
6836 { "popP", { ds
}, 0 },
6841 { "daa", { XX
}, 0 },
6846 { "das", { XX
}, 0 },
6851 { "aaa", { XX
}, 0 },
6856 { "aas", { XX
}, 0 },
6861 { "pushaP", { XX
}, 0 },
6866 { "popaP", { XX
}, 0 },
6871 { MOD_TABLE (MOD_62_32BIT
) },
6872 { EVEX_TABLE (EVEX_0F
) },
6877 { "arpl", { Ew
, Gw
}, 0 },
6878 { "movs", { { OP_G
, movsxd_mode
}, { MOVSXD_Fixup
, movsxd_mode
} }, 0 },
6883 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6884 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6889 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6890 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6895 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6896 { REG_TABLE (REG_80
) },
6901 { "Jcall{T|}", { Ap
}, 0 },
6906 { MOD_TABLE (MOD_C4_32BIT
) },
6907 { VEX_C4_TABLE (VEX_0F
) },
6912 { MOD_TABLE (MOD_C5_32BIT
) },
6913 { VEX_C5_TABLE (VEX_0F
) },
6918 { "into", { XX
}, 0 },
6923 { "aam", { Ib
}, 0 },
6928 { "aad", { Ib
}, 0 },
6933 { "callP", { Jv
, BND
}, 0 },
6934 { "call@", { Jv
, BND
}, 0 }
6939 { "jmpP", { Jv
, BND
}, 0 },
6940 { "jmp@", { Jv
, BND
}, 0 }
6945 { "Jjmp{T|}", { Ap
}, 0 },
6948 /* X86_64_0F01_REG_0 */
6950 { "sgdt{Q|IQ}", { M
}, 0 },
6951 { "sgdt", { M
}, 0 },
6954 /* X86_64_0F01_REG_1 */
6956 { "sidt{Q|IQ}", { M
}, 0 },
6957 { "sidt", { M
}, 0 },
6960 /* X86_64_0F01_REG_2 */
6962 { "lgdt{Q|Q}", { M
}, 0 },
6963 { "lgdt", { M
}, 0 },
6966 /* X86_64_0F01_REG_3 */
6968 { "lidt{Q|Q}", { M
}, 0 },
6969 { "lidt", { M
}, 0 },
6973 static const struct dis386 three_byte_table
[][256] = {
6975 /* THREE_BYTE_0F38 */
6978 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6984 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6985 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6988 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6989 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6990 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6996 { PREFIX_TABLE (PREFIX_0F3810
) },
7000 { PREFIX_TABLE (PREFIX_0F3814
) },
7001 { PREFIX_TABLE (PREFIX_0F3815
) },
7003 { PREFIX_TABLE (PREFIX_0F3817
) },
7009 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7010 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7011 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7014 { PREFIX_TABLE (PREFIX_0F3820
) },
7015 { PREFIX_TABLE (PREFIX_0F3821
) },
7016 { PREFIX_TABLE (PREFIX_0F3822
) },
7017 { PREFIX_TABLE (PREFIX_0F3823
) },
7018 { PREFIX_TABLE (PREFIX_0F3824
) },
7019 { PREFIX_TABLE (PREFIX_0F3825
) },
7023 { PREFIX_TABLE (PREFIX_0F3828
) },
7024 { PREFIX_TABLE (PREFIX_0F3829
) },
7025 { PREFIX_TABLE (PREFIX_0F382A
) },
7026 { PREFIX_TABLE (PREFIX_0F382B
) },
7032 { PREFIX_TABLE (PREFIX_0F3830
) },
7033 { PREFIX_TABLE (PREFIX_0F3831
) },
7034 { PREFIX_TABLE (PREFIX_0F3832
) },
7035 { PREFIX_TABLE (PREFIX_0F3833
) },
7036 { PREFIX_TABLE (PREFIX_0F3834
) },
7037 { PREFIX_TABLE (PREFIX_0F3835
) },
7039 { PREFIX_TABLE (PREFIX_0F3837
) },
7041 { PREFIX_TABLE (PREFIX_0F3838
) },
7042 { PREFIX_TABLE (PREFIX_0F3839
) },
7043 { PREFIX_TABLE (PREFIX_0F383A
) },
7044 { PREFIX_TABLE (PREFIX_0F383B
) },
7045 { PREFIX_TABLE (PREFIX_0F383C
) },
7046 { PREFIX_TABLE (PREFIX_0F383D
) },
7047 { PREFIX_TABLE (PREFIX_0F383E
) },
7048 { PREFIX_TABLE (PREFIX_0F383F
) },
7050 { PREFIX_TABLE (PREFIX_0F3840
) },
7051 { PREFIX_TABLE (PREFIX_0F3841
) },
7122 { PREFIX_TABLE (PREFIX_0F3880
) },
7123 { PREFIX_TABLE (PREFIX_0F3881
) },
7124 { PREFIX_TABLE (PREFIX_0F3882
) },
7203 { PREFIX_TABLE (PREFIX_0F38C8
) },
7204 { PREFIX_TABLE (PREFIX_0F38C9
) },
7205 { PREFIX_TABLE (PREFIX_0F38CA
) },
7206 { PREFIX_TABLE (PREFIX_0F38CB
) },
7207 { PREFIX_TABLE (PREFIX_0F38CC
) },
7208 { PREFIX_TABLE (PREFIX_0F38CD
) },
7210 { PREFIX_TABLE (PREFIX_0F38CF
) },
7224 { PREFIX_TABLE (PREFIX_0F38DB
) },
7225 { PREFIX_TABLE (PREFIX_0F38DC
) },
7226 { PREFIX_TABLE (PREFIX_0F38DD
) },
7227 { PREFIX_TABLE (PREFIX_0F38DE
) },
7228 { PREFIX_TABLE (PREFIX_0F38DF
) },
7248 { PREFIX_TABLE (PREFIX_0F38F0
) },
7249 { PREFIX_TABLE (PREFIX_0F38F1
) },
7253 { PREFIX_TABLE (PREFIX_0F38F5
) },
7254 { PREFIX_TABLE (PREFIX_0F38F6
) },
7257 { PREFIX_TABLE (PREFIX_0F38F8
) },
7258 { PREFIX_TABLE (PREFIX_0F38F9
) },
7266 /* THREE_BYTE_0F3A */
7278 { PREFIX_TABLE (PREFIX_0F3A08
) },
7279 { PREFIX_TABLE (PREFIX_0F3A09
) },
7280 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7281 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7282 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7283 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7284 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7285 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7291 { PREFIX_TABLE (PREFIX_0F3A14
) },
7292 { PREFIX_TABLE (PREFIX_0F3A15
) },
7293 { PREFIX_TABLE (PREFIX_0F3A16
) },
7294 { PREFIX_TABLE (PREFIX_0F3A17
) },
7305 { PREFIX_TABLE (PREFIX_0F3A20
) },
7306 { PREFIX_TABLE (PREFIX_0F3A21
) },
7307 { PREFIX_TABLE (PREFIX_0F3A22
) },
7341 { PREFIX_TABLE (PREFIX_0F3A40
) },
7342 { PREFIX_TABLE (PREFIX_0F3A41
) },
7343 { PREFIX_TABLE (PREFIX_0F3A42
) },
7345 { PREFIX_TABLE (PREFIX_0F3A44
) },
7377 { PREFIX_TABLE (PREFIX_0F3A60
) },
7378 { PREFIX_TABLE (PREFIX_0F3A61
) },
7379 { PREFIX_TABLE (PREFIX_0F3A62
) },
7380 { PREFIX_TABLE (PREFIX_0F3A63
) },
7498 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7500 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7501 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7519 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7559 static const struct dis386 xop_table
[][256] = {
7712 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7713 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7714 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7722 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7723 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7730 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7731 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7732 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7740 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7741 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7745 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7746 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7749 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7767 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7779 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7780 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7781 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7782 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7794 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7795 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7828 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7829 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7830 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7831 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7855 { REG_TABLE (REG_XOP_TBM_01
) },
7856 { REG_TABLE (REG_XOP_TBM_02
) },
7874 { REG_TABLE (REG_XOP_LWPCB
) },
7998 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8000 { "vfrczss", { XM
, EXd
}, 0 },
8001 { "vfrczsd", { XM
, EXq
}, 0 },
8016 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8020 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8022 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8023 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8025 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8026 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8027 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8028 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8071 { "vphaddbw", { XM
, EXxmm
}, 0 },
8072 { "vphaddbd", { XM
, EXxmm
}, 0 },
8073 { "vphaddbq", { XM
, EXxmm
}, 0 },
8076 { "vphaddwd", { XM
, EXxmm
}, 0 },
8077 { "vphaddwq", { XM
, EXxmm
}, 0 },
8082 { "vphadddq", { XM
, EXxmm
}, 0 },
8089 { "vphaddubw", { XM
, EXxmm
}, 0 },
8090 { "vphaddubd", { XM
, EXxmm
}, 0 },
8091 { "vphaddubq", { XM
, EXxmm
}, 0 },
8094 { "vphadduwd", { XM
, EXxmm
}, 0 },
8095 { "vphadduwq", { XM
, EXxmm
}, 0 },
8100 { "vphaddudq", { XM
, EXxmm
}, 0 },
8107 { "vphsubbw", { XM
, EXxmm
}, 0 },
8108 { "vphsubwd", { XM
, EXxmm
}, 0 },
8109 { "vphsubdq", { XM
, EXxmm
}, 0 },
8163 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8165 { REG_TABLE (REG_XOP_LWP
) },
8435 static const struct dis386 vex_table
[][256] = {
8457 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8459 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8460 { MOD_TABLE (MOD_VEX_0F13
) },
8461 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8462 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8463 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8464 { MOD_TABLE (MOD_VEX_0F17
) },
8484 { "vmovapX", { XM
, EXx
}, 0 },
8485 { "vmovapX", { EXxS
, XM
}, 0 },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8487 { MOD_TABLE (MOD_VEX_0F2B
) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8490 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8529 { MOD_TABLE (MOD_VEX_0F50
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8533 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8534 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8535 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8536 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8538 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8566 { REG_TABLE (REG_VEX_0F71
) },
8567 { REG_TABLE (REG_VEX_0F72
) },
8568 { REG_TABLE (REG_VEX_0F73
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8580 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8581 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8634 { REG_TABLE (REG_VEX_0FAE
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8660 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8661 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8809 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9003 { REG_TABLE (REG_VEX_0F38F3
) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9144 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9145 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9252 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9253 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9311 #include "i386-dis-evex.h"
9313 static const struct dis386 vex_len_table
[][2] = {
9314 /* VEX_LEN_0F12_P_0_M_0 */
9316 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9319 /* VEX_LEN_0F12_P_0_M_1 */
9321 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9324 /* VEX_LEN_0F12_P_2 */
9326 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9329 /* VEX_LEN_0F13_M_0 */
9331 { "vmovlpX", { EXq
, XM
}, 0 },
9334 /* VEX_LEN_0F16_P_0_M_0 */
9336 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9339 /* VEX_LEN_0F16_P_0_M_1 */
9341 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9344 /* VEX_LEN_0F16_P_2 */
9346 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9349 /* VEX_LEN_0F17_M_0 */
9351 { "vmovhpX", { EXq
, XM
}, 0 },
9354 /* VEX_LEN_0F41_P_0 */
9357 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9359 /* VEX_LEN_0F41_P_2 */
9362 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9364 /* VEX_LEN_0F42_P_0 */
9367 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9369 /* VEX_LEN_0F42_P_2 */
9372 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9374 /* VEX_LEN_0F44_P_0 */
9376 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9378 /* VEX_LEN_0F44_P_2 */
9380 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9382 /* VEX_LEN_0F45_P_0 */
9385 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9387 /* VEX_LEN_0F45_P_2 */
9390 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9392 /* VEX_LEN_0F46_P_0 */
9395 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9397 /* VEX_LEN_0F46_P_2 */
9400 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9402 /* VEX_LEN_0F47_P_0 */
9405 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9407 /* VEX_LEN_0F47_P_2 */
9410 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9412 /* VEX_LEN_0F4A_P_0 */
9415 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9417 /* VEX_LEN_0F4A_P_2 */
9420 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9422 /* VEX_LEN_0F4B_P_0 */
9425 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9427 /* VEX_LEN_0F4B_P_2 */
9430 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9433 /* VEX_LEN_0F6E_P_2 */
9435 { "vmovK", { XMScalar
, Edq
}, 0 },
9438 /* VEX_LEN_0F77_P_1 */
9440 { "vzeroupper", { XX
}, 0 },
9441 { "vzeroall", { XX
}, 0 },
9444 /* VEX_LEN_0F7E_P_1 */
9446 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9449 /* VEX_LEN_0F7E_P_2 */
9451 { "vmovK", { Edq
, XMScalar
}, 0 },
9454 /* VEX_LEN_0F90_P_0 */
9456 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9459 /* VEX_LEN_0F90_P_2 */
9461 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9464 /* VEX_LEN_0F91_P_0 */
9466 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9469 /* VEX_LEN_0F91_P_2 */
9471 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9474 /* VEX_LEN_0F92_P_0 */
9476 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9479 /* VEX_LEN_0F92_P_2 */
9481 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9484 /* VEX_LEN_0F92_P_3 */
9486 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9489 /* VEX_LEN_0F93_P_0 */
9491 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9494 /* VEX_LEN_0F93_P_2 */
9496 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9499 /* VEX_LEN_0F93_P_3 */
9501 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9504 /* VEX_LEN_0F98_P_0 */
9506 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9509 /* VEX_LEN_0F98_P_2 */
9511 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9514 /* VEX_LEN_0F99_P_0 */
9516 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9519 /* VEX_LEN_0F99_P_2 */
9521 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9524 /* VEX_LEN_0FAE_R_2_M_0 */
9526 { "vldmxcsr", { Md
}, 0 },
9529 /* VEX_LEN_0FAE_R_3_M_0 */
9531 { "vstmxcsr", { Md
}, 0 },
9534 /* VEX_LEN_0FC4_P_2 */
9536 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9539 /* VEX_LEN_0FC5_P_2 */
9541 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9544 /* VEX_LEN_0FD6_P_2 */
9546 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9549 /* VEX_LEN_0FF7_P_2 */
9551 { "vmaskmovdqu", { XM
, XS
}, 0 },
9554 /* VEX_LEN_0F3816_P_2 */
9557 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9560 /* VEX_LEN_0F3819_P_2 */
9563 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9566 /* VEX_LEN_0F381A_P_2_M_0 */
9569 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9572 /* VEX_LEN_0F3836_P_2 */
9575 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9578 /* VEX_LEN_0F3841_P_2 */
9580 { "vphminposuw", { XM
, EXx
}, 0 },
9583 /* VEX_LEN_0F385A_P_2_M_0 */
9586 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9589 /* VEX_LEN_0F38DB_P_2 */
9591 { "vaesimc", { XM
, EXx
}, 0 },
9594 /* VEX_LEN_0F38F2_P_0 */
9596 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9599 /* VEX_LEN_0F38F3_R_1_P_0 */
9601 { "blsrS", { VexGdq
, Edq
}, 0 },
9604 /* VEX_LEN_0F38F3_R_2_P_0 */
9606 { "blsmskS", { VexGdq
, Edq
}, 0 },
9609 /* VEX_LEN_0F38F3_R_3_P_0 */
9611 { "blsiS", { VexGdq
, Edq
}, 0 },
9614 /* VEX_LEN_0F38F5_P_0 */
9616 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9619 /* VEX_LEN_0F38F5_P_1 */
9621 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9624 /* VEX_LEN_0F38F5_P_3 */
9626 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9629 /* VEX_LEN_0F38F6_P_3 */
9631 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9634 /* VEX_LEN_0F38F7_P_0 */
9636 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9639 /* VEX_LEN_0F38F7_P_1 */
9641 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9644 /* VEX_LEN_0F38F7_P_2 */
9646 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9649 /* VEX_LEN_0F38F7_P_3 */
9651 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9654 /* VEX_LEN_0F3A00_P_2 */
9657 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9660 /* VEX_LEN_0F3A01_P_2 */
9663 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9666 /* VEX_LEN_0F3A06_P_2 */
9669 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9672 /* VEX_LEN_0F3A14_P_2 */
9674 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9677 /* VEX_LEN_0F3A15_P_2 */
9679 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9682 /* VEX_LEN_0F3A16_P_2 */
9684 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9687 /* VEX_LEN_0F3A17_P_2 */
9689 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9692 /* VEX_LEN_0F3A18_P_2 */
9695 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9698 /* VEX_LEN_0F3A19_P_2 */
9701 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9704 /* VEX_LEN_0F3A20_P_2 */
9706 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9709 /* VEX_LEN_0F3A21_P_2 */
9711 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9714 /* VEX_LEN_0F3A22_P_2 */
9716 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9719 /* VEX_LEN_0F3A30_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9724 /* VEX_LEN_0F3A31_P_2 */
9726 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9729 /* VEX_LEN_0F3A32_P_2 */
9731 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9734 /* VEX_LEN_0F3A33_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9739 /* VEX_LEN_0F3A38_P_2 */
9742 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9745 /* VEX_LEN_0F3A39_P_2 */
9748 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9751 /* VEX_LEN_0F3A41_P_2 */
9753 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9756 /* VEX_LEN_0F3A46_P_2 */
9759 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9762 /* VEX_LEN_0F3A60_P_2 */
9764 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9767 /* VEX_LEN_0F3A61_P_2 */
9769 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9772 /* VEX_LEN_0F3A62_P_2 */
9774 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9777 /* VEX_LEN_0F3A63_P_2 */
9779 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9782 /* VEX_LEN_0F3A6A_P_2 */
9784 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9787 /* VEX_LEN_0F3A6B_P_2 */
9789 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9792 /* VEX_LEN_0F3A6E_P_2 */
9794 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9797 /* VEX_LEN_0F3A6F_P_2 */
9799 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9802 /* VEX_LEN_0F3A7A_P_2 */
9804 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9807 /* VEX_LEN_0F3A7B_P_2 */
9809 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9812 /* VEX_LEN_0F3A7E_P_2 */
9814 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9817 /* VEX_LEN_0F3A7F_P_2 */
9819 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9822 /* VEX_LEN_0F3ADF_P_2 */
9824 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9827 /* VEX_LEN_0F3AF0_P_3 */
9829 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9832 /* VEX_LEN_0FXOP_08_CC */
9834 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9837 /* VEX_LEN_0FXOP_08_CD */
9839 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9842 /* VEX_LEN_0FXOP_08_CE */
9844 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9847 /* VEX_LEN_0FXOP_08_CF */
9849 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9852 /* VEX_LEN_0FXOP_08_EC */
9854 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9857 /* VEX_LEN_0FXOP_08_ED */
9859 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9862 /* VEX_LEN_0FXOP_08_EE */
9864 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9867 /* VEX_LEN_0FXOP_08_EF */
9869 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9872 /* VEX_LEN_0FXOP_09_80 */
9874 { "vfrczps", { XM
, EXxmm
}, 0 },
9875 { "vfrczps", { XM
, EXymmq
}, 0 },
9878 /* VEX_LEN_0FXOP_09_81 */
9880 { "vfrczpd", { XM
, EXxmm
}, 0 },
9881 { "vfrczpd", { XM
, EXymmq
}, 0 },
9885 #include "i386-dis-evex-len.h"
9887 static const struct dis386 vex_w_table
[][2] = {
9889 /* VEX_W_0F41_P_0_LEN_1 */
9890 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9891 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9894 /* VEX_W_0F41_P_2_LEN_1 */
9895 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9896 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9899 /* VEX_W_0F42_P_0_LEN_1 */
9900 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9901 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9904 /* VEX_W_0F42_P_2_LEN_1 */
9905 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9906 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9909 /* VEX_W_0F44_P_0_LEN_0 */
9910 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9911 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9914 /* VEX_W_0F44_P_2_LEN_0 */
9915 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9916 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9919 /* VEX_W_0F45_P_0_LEN_1 */
9920 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9921 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9924 /* VEX_W_0F45_P_2_LEN_1 */
9925 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9926 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9929 /* VEX_W_0F46_P_0_LEN_1 */
9930 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9931 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9934 /* VEX_W_0F46_P_2_LEN_1 */
9935 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9936 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9939 /* VEX_W_0F47_P_0_LEN_1 */
9940 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9941 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9944 /* VEX_W_0F47_P_2_LEN_1 */
9945 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9946 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9949 /* VEX_W_0F4A_P_0_LEN_1 */
9950 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9951 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9954 /* VEX_W_0F4A_P_2_LEN_1 */
9955 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9956 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9959 /* VEX_W_0F4B_P_0_LEN_1 */
9960 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9961 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9964 /* VEX_W_0F4B_P_2_LEN_1 */
9965 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9968 /* VEX_W_0F90_P_0_LEN_0 */
9969 { "kmovw", { MaskG
, MaskE
}, 0 },
9970 { "kmovq", { MaskG
, MaskE
}, 0 },
9973 /* VEX_W_0F90_P_2_LEN_0 */
9974 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9975 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9978 /* VEX_W_0F91_P_0_LEN_0 */
9979 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9980 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9983 /* VEX_W_0F91_P_2_LEN_0 */
9984 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9985 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9988 /* VEX_W_0F92_P_0_LEN_0 */
9989 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9992 /* VEX_W_0F92_P_2_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9996 /* VEX_W_0F93_P_0_LEN_0 */
9997 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10000 /* VEX_W_0F93_P_2_LEN_0 */
10001 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10004 /* VEX_W_0F98_P_0_LEN_0 */
10005 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10006 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10009 /* VEX_W_0F98_P_2_LEN_0 */
10010 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10011 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10014 /* VEX_W_0F99_P_0_LEN_0 */
10015 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10016 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10019 /* VEX_W_0F99_P_2_LEN_0 */
10020 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10021 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10024 /* VEX_W_0F380C_P_2 */
10025 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10028 /* VEX_W_0F380D_P_2 */
10029 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10032 /* VEX_W_0F380E_P_2 */
10033 { "vtestps", { XM
, EXx
}, 0 },
10036 /* VEX_W_0F380F_P_2 */
10037 { "vtestpd", { XM
, EXx
}, 0 },
10040 /* VEX_W_0F3816_P_2 */
10041 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10044 /* VEX_W_0F3818_P_2 */
10045 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10048 /* VEX_W_0F3819_P_2 */
10049 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10052 /* VEX_W_0F381A_P_2_M_0 */
10053 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10056 /* VEX_W_0F382C_P_2_M_0 */
10057 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10060 /* VEX_W_0F382D_P_2_M_0 */
10061 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10064 /* VEX_W_0F382E_P_2_M_0 */
10065 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10068 /* VEX_W_0F382F_P_2_M_0 */
10069 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10072 /* VEX_W_0F3836_P_2 */
10073 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10076 /* VEX_W_0F3846_P_2 */
10077 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10080 /* VEX_W_0F3858_P_2 */
10081 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10084 /* VEX_W_0F3859_P_2 */
10085 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10088 /* VEX_W_0F385A_P_2_M_0 */
10089 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10092 /* VEX_W_0F3878_P_2 */
10093 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10096 /* VEX_W_0F3879_P_2 */
10097 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10100 /* VEX_W_0F38CF_P_2 */
10101 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10104 /* VEX_W_0F3A00_P_2 */
10106 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10109 /* VEX_W_0F3A01_P_2 */
10111 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10114 /* VEX_W_0F3A02_P_2 */
10115 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10118 /* VEX_W_0F3A04_P_2 */
10119 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10122 /* VEX_W_0F3A05_P_2 */
10123 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10126 /* VEX_W_0F3A06_P_2 */
10127 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10130 /* VEX_W_0F3A18_P_2 */
10131 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10134 /* VEX_W_0F3A19_P_2 */
10135 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10138 /* VEX_W_0F3A30_P_2_LEN_0 */
10139 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10140 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10143 /* VEX_W_0F3A31_P_2_LEN_0 */
10144 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10145 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10148 /* VEX_W_0F3A32_P_2_LEN_0 */
10149 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10150 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10153 /* VEX_W_0F3A33_P_2_LEN_0 */
10154 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10155 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10158 /* VEX_W_0F3A38_P_2 */
10159 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10162 /* VEX_W_0F3A39_P_2 */
10163 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10166 /* VEX_W_0F3A46_P_2 */
10167 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10170 /* VEX_W_0F3A48_P_2 */
10171 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10172 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10175 /* VEX_W_0F3A49_P_2 */
10176 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10177 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10180 /* VEX_W_0F3A4A_P_2 */
10181 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10184 /* VEX_W_0F3A4B_P_2 */
10185 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10188 /* VEX_W_0F3A4C_P_2 */
10189 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10192 /* VEX_W_0F3ACE_P_2 */
10194 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10197 /* VEX_W_0F3ACF_P_2 */
10199 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10202 #include "i386-dis-evex-w.h"
10205 static const struct dis386 mod_table
[][2] = {
10208 { "leaS", { Gv
, M
}, 0 },
10213 { RM_TABLE (RM_C6_REG_7
) },
10218 { RM_TABLE (RM_C7_REG_7
) },
10222 { "Jcall^", { indirEp
}, 0 },
10226 { "Jjmp^", { indirEp
}, 0 },
10229 /* MOD_0F01_REG_0 */
10230 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10231 { RM_TABLE (RM_0F01_REG_0
) },
10234 /* MOD_0F01_REG_1 */
10235 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10236 { RM_TABLE (RM_0F01_REG_1
) },
10239 /* MOD_0F01_REG_2 */
10240 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10241 { RM_TABLE (RM_0F01_REG_2
) },
10244 /* MOD_0F01_REG_3 */
10245 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10246 { RM_TABLE (RM_0F01_REG_3
) },
10249 /* MOD_0F01_REG_5 */
10250 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10251 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10254 /* MOD_0F01_REG_7 */
10255 { "invlpg", { Mb
}, 0 },
10256 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10259 /* MOD_0F12_PREFIX_0 */
10260 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10261 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10265 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10268 /* MOD_0F16_PREFIX_0 */
10269 { "movhps", { XM
, EXq
}, 0 },
10270 { "movlhps", { XM
, EXq
}, 0 },
10274 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10277 /* MOD_0F18_REG_0 */
10278 { "prefetchnta", { Mb
}, 0 },
10281 /* MOD_0F18_REG_1 */
10282 { "prefetcht0", { Mb
}, 0 },
10285 /* MOD_0F18_REG_2 */
10286 { "prefetcht1", { Mb
}, 0 },
10289 /* MOD_0F18_REG_3 */
10290 { "prefetcht2", { Mb
}, 0 },
10293 /* MOD_0F18_REG_4 */
10294 { "nop/reserved", { Mb
}, 0 },
10297 /* MOD_0F18_REG_5 */
10298 { "nop/reserved", { Mb
}, 0 },
10301 /* MOD_0F18_REG_6 */
10302 { "nop/reserved", { Mb
}, 0 },
10305 /* MOD_0F18_REG_7 */
10306 { "nop/reserved", { Mb
}, 0 },
10309 /* MOD_0F1A_PREFIX_0 */
10310 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10311 { "nopQ", { Ev
}, 0 },
10314 /* MOD_0F1B_PREFIX_0 */
10315 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10316 { "nopQ", { Ev
}, 0 },
10319 /* MOD_0F1B_PREFIX_1 */
10320 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10321 { "nopQ", { Ev
}, 0 },
10324 /* MOD_0F1C_PREFIX_0 */
10325 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10326 { "nopQ", { Ev
}, 0 },
10329 /* MOD_0F1E_PREFIX_1 */
10330 { "nopQ", { Ev
}, 0 },
10331 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10336 { "movL", { Rd
, Td
}, 0 },
10341 { "movL", { Td
, Rd
}, 0 },
10344 /* MOD_0F2B_PREFIX_0 */
10345 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10348 /* MOD_0F2B_PREFIX_1 */
10349 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10352 /* MOD_0F2B_PREFIX_2 */
10353 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10356 /* MOD_0F2B_PREFIX_3 */
10357 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10362 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10365 /* MOD_0F71_REG_2 */
10367 { "psrlw", { MS
, Ib
}, 0 },
10370 /* MOD_0F71_REG_4 */
10372 { "psraw", { MS
, Ib
}, 0 },
10375 /* MOD_0F71_REG_6 */
10377 { "psllw", { MS
, Ib
}, 0 },
10380 /* MOD_0F72_REG_2 */
10382 { "psrld", { MS
, Ib
}, 0 },
10385 /* MOD_0F72_REG_4 */
10387 { "psrad", { MS
, Ib
}, 0 },
10390 /* MOD_0F72_REG_6 */
10392 { "pslld", { MS
, Ib
}, 0 },
10395 /* MOD_0F73_REG_2 */
10397 { "psrlq", { MS
, Ib
}, 0 },
10400 /* MOD_0F73_REG_3 */
10402 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10405 /* MOD_0F73_REG_6 */
10407 { "psllq", { MS
, Ib
}, 0 },
10410 /* MOD_0F73_REG_7 */
10412 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10415 /* MOD_0FAE_REG_0 */
10416 { "fxsave", { FXSAVE
}, 0 },
10417 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10420 /* MOD_0FAE_REG_1 */
10421 { "fxrstor", { FXSAVE
}, 0 },
10422 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10425 /* MOD_0FAE_REG_2 */
10426 { "ldmxcsr", { Md
}, 0 },
10427 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10430 /* MOD_0FAE_REG_3 */
10431 { "stmxcsr", { Md
}, 0 },
10432 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10435 /* MOD_0FAE_REG_4 */
10436 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10437 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10440 /* MOD_0FAE_REG_5 */
10441 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10442 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10445 /* MOD_0FAE_REG_6 */
10446 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10447 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10450 /* MOD_0FAE_REG_7 */
10451 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10452 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10456 { "lssS", { Gv
, Mp
}, 0 },
10460 { "lfsS", { Gv
, Mp
}, 0 },
10464 { "lgsS", { Gv
, Mp
}, 0 },
10468 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10471 /* MOD_0FC7_REG_3 */
10472 { "xrstors", { FXSAVE
}, 0 },
10475 /* MOD_0FC7_REG_4 */
10476 { "xsavec", { FXSAVE
}, 0 },
10479 /* MOD_0FC7_REG_5 */
10480 { "xsaves", { FXSAVE
}, 0 },
10483 /* MOD_0FC7_REG_6 */
10484 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10485 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10488 /* MOD_0FC7_REG_7 */
10489 { "vmptrst", { Mq
}, 0 },
10490 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10495 { "pmovmskb", { Gdq
, MS
}, 0 },
10498 /* MOD_0FE7_PREFIX_2 */
10499 { "movntdq", { Mx
, XM
}, 0 },
10502 /* MOD_0FF0_PREFIX_3 */
10503 { "lddqu", { XM
, M
}, 0 },
10506 /* MOD_0F382A_PREFIX_2 */
10507 { "movntdqa", { XM
, Mx
}, 0 },
10510 /* MOD_0F38F5_PREFIX_2 */
10511 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10514 /* MOD_0F38F6_PREFIX_0 */
10515 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10518 /* MOD_0F38F8_PREFIX_1 */
10519 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10522 /* MOD_0F38F8_PREFIX_2 */
10523 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10526 /* MOD_0F38F8_PREFIX_3 */
10527 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10530 /* MOD_0F38F9_PREFIX_0 */
10531 { "movdiri", { Ev
, Gv
}, PREFIX_OPCODE
},
10535 { "bound{S|}", { Gv
, Ma
}, 0 },
10536 { EVEX_TABLE (EVEX_0F
) },
10540 { "lesS", { Gv
, Mp
}, 0 },
10541 { VEX_C4_TABLE (VEX_0F
) },
10545 { "ldsS", { Gv
, Mp
}, 0 },
10546 { VEX_C5_TABLE (VEX_0F
) },
10549 /* MOD_VEX_0F12_PREFIX_0 */
10550 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10551 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10555 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10558 /* MOD_VEX_0F16_PREFIX_0 */
10559 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10560 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10564 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10568 { "vmovntpX", { Mx
, XM
}, 0 },
10571 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10573 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10576 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10578 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10581 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10583 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10586 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10588 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10591 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10593 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10596 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10598 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10601 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10603 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10606 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10608 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10611 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10613 { "knotw", { MaskG
, MaskR
}, 0 },
10616 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10618 { "knotq", { MaskG
, MaskR
}, 0 },
10621 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10623 { "knotb", { MaskG
, MaskR
}, 0 },
10626 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10628 { "knotd", { MaskG
, MaskR
}, 0 },
10631 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10633 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10636 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10638 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10641 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10643 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10646 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10648 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10651 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10653 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10656 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10658 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10661 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10663 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10666 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10668 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10671 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10673 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10676 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10678 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10681 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10683 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10686 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10688 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10691 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10693 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10696 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10698 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10701 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10703 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10706 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10708 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10711 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10713 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10716 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10718 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10721 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10723 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10728 { "vmovmskpX", { Gdq
, XS
}, 0 },
10731 /* MOD_VEX_0F71_REG_2 */
10733 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10736 /* MOD_VEX_0F71_REG_4 */
10738 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10741 /* MOD_VEX_0F71_REG_6 */
10743 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10746 /* MOD_VEX_0F72_REG_2 */
10748 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10751 /* MOD_VEX_0F72_REG_4 */
10753 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10756 /* MOD_VEX_0F72_REG_6 */
10758 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10761 /* MOD_VEX_0F73_REG_2 */
10763 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10766 /* MOD_VEX_0F73_REG_3 */
10768 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10771 /* MOD_VEX_0F73_REG_6 */
10773 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10776 /* MOD_VEX_0F73_REG_7 */
10778 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10781 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10782 { "kmovw", { Ew
, MaskG
}, 0 },
10786 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10787 { "kmovq", { Eq
, MaskG
}, 0 },
10791 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10792 { "kmovb", { Eb
, MaskG
}, 0 },
10796 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10797 { "kmovd", { Ed
, MaskG
}, 0 },
10801 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10803 { "kmovw", { MaskG
, Rdq
}, 0 },
10806 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10808 { "kmovb", { MaskG
, Rdq
}, 0 },
10811 /* MOD_VEX_0F92_P_3_LEN_0 */
10813 { "kmovK", { MaskG
, Rdq
}, 0 },
10816 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10818 { "kmovw", { Gdq
, MaskR
}, 0 },
10821 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10823 { "kmovb", { Gdq
, MaskR
}, 0 },
10826 /* MOD_VEX_0F93_P_3_LEN_0 */
10828 { "kmovK", { Gdq
, MaskR
}, 0 },
10831 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10833 { "kortestw", { MaskG
, MaskR
}, 0 },
10836 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10838 { "kortestq", { MaskG
, MaskR
}, 0 },
10841 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10843 { "kortestb", { MaskG
, MaskR
}, 0 },
10846 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10848 { "kortestd", { MaskG
, MaskR
}, 0 },
10851 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10853 { "ktestw", { MaskG
, MaskR
}, 0 },
10856 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10858 { "ktestq", { MaskG
, MaskR
}, 0 },
10861 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10863 { "ktestb", { MaskG
, MaskR
}, 0 },
10866 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10868 { "ktestd", { MaskG
, MaskR
}, 0 },
10871 /* MOD_VEX_0FAE_REG_2 */
10872 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10875 /* MOD_VEX_0FAE_REG_3 */
10876 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10879 /* MOD_VEX_0FD7_PREFIX_2 */
10881 { "vpmovmskb", { Gdq
, XS
}, 0 },
10884 /* MOD_VEX_0FE7_PREFIX_2 */
10885 { "vmovntdq", { Mx
, XM
}, 0 },
10888 /* MOD_VEX_0FF0_PREFIX_3 */
10889 { "vlddqu", { XM
, M
}, 0 },
10892 /* MOD_VEX_0F381A_PREFIX_2 */
10893 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10896 /* MOD_VEX_0F382A_PREFIX_2 */
10897 { "vmovntdqa", { XM
, Mx
}, 0 },
10900 /* MOD_VEX_0F382C_PREFIX_2 */
10901 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10904 /* MOD_VEX_0F382D_PREFIX_2 */
10905 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10908 /* MOD_VEX_0F382E_PREFIX_2 */
10909 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10912 /* MOD_VEX_0F382F_PREFIX_2 */
10913 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10916 /* MOD_VEX_0F385A_PREFIX_2 */
10917 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10920 /* MOD_VEX_0F388C_PREFIX_2 */
10921 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10924 /* MOD_VEX_0F388E_PREFIX_2 */
10925 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10928 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10930 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10933 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10935 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10938 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10940 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10943 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10945 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10948 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10950 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10953 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10955 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10958 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10960 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10963 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10965 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10968 #include "i386-dis-evex-mod.h"
10971 static const struct dis386 rm_table
[][8] = {
10974 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10978 { "xbeginT", { Skip_MODRM
, Jdqw
}, 0 },
10981 /* RM_0F01_REG_0 */
10982 { "enclv", { Skip_MODRM
}, 0 },
10983 { "vmcall", { Skip_MODRM
}, 0 },
10984 { "vmlaunch", { Skip_MODRM
}, 0 },
10985 { "vmresume", { Skip_MODRM
}, 0 },
10986 { "vmxoff", { Skip_MODRM
}, 0 },
10987 { "pconfig", { Skip_MODRM
}, 0 },
10990 /* RM_0F01_REG_1 */
10991 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10992 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10993 { "clac", { Skip_MODRM
}, 0 },
10994 { "stac", { Skip_MODRM
}, 0 },
10998 { "encls", { Skip_MODRM
}, 0 },
11001 /* RM_0F01_REG_2 */
11002 { "xgetbv", { Skip_MODRM
}, 0 },
11003 { "xsetbv", { Skip_MODRM
}, 0 },
11006 { "vmfunc", { Skip_MODRM
}, 0 },
11007 { "xend", { Skip_MODRM
}, 0 },
11008 { "xtest", { Skip_MODRM
}, 0 },
11009 { "enclu", { Skip_MODRM
}, 0 },
11012 /* RM_0F01_REG_3 */
11013 { "vmrun", { Skip_MODRM
}, 0 },
11014 { "vmmcall", { Skip_MODRM
}, 0 },
11015 { "vmload", { Skip_MODRM
}, 0 },
11016 { "vmsave", { Skip_MODRM
}, 0 },
11017 { "stgi", { Skip_MODRM
}, 0 },
11018 { "clgi", { Skip_MODRM
}, 0 },
11019 { "skinit", { Skip_MODRM
}, 0 },
11020 { "invlpga", { Skip_MODRM
}, 0 },
11023 /* RM_0F01_REG_5_MOD_3 */
11024 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11026 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11030 { "rdpkru", { Skip_MODRM
}, 0 },
11031 { "wrpkru", { Skip_MODRM
}, 0 },
11034 /* RM_0F01_REG_7_MOD_3 */
11035 { "swapgs", { Skip_MODRM
}, 0 },
11036 { "rdtscp", { Skip_MODRM
}, 0 },
11037 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11038 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11039 { "clzero", { Skip_MODRM
}, 0 },
11040 { "rdpru", { Skip_MODRM
}, 0 },
11043 /* RM_0F1E_P_1_MOD_3_REG_7 */
11044 { "nopQ", { Ev
}, 0 },
11045 { "nopQ", { Ev
}, 0 },
11046 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11047 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11048 { "nopQ", { Ev
}, 0 },
11049 { "nopQ", { Ev
}, 0 },
11050 { "nopQ", { Ev
}, 0 },
11051 { "nopQ", { Ev
}, 0 },
11054 /* RM_0FAE_REG_6_MOD_3 */
11055 { "mfence", { Skip_MODRM
}, 0 },
11058 /* RM_0FAE_REG_7_MOD_3 */
11059 { "sfence", { Skip_MODRM
}, 0 },
11064 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11066 /* We use the high bit to indicate different name for the same
11068 #define REP_PREFIX (0xf3 | 0x100)
11069 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11070 #define XRELEASE_PREFIX (0xf3 | 0x400)
11071 #define BND_PREFIX (0xf2 | 0x400)
11072 #define NOTRACK_PREFIX (0x3e | 0x100)
11074 /* Remember if the current op is a jump instruction. */
11075 static bfd_boolean op_is_jump
= FALSE
;
11080 int newrex
, i
, length
;
11086 last_lock_prefix
= -1;
11087 last_repz_prefix
= -1;
11088 last_repnz_prefix
= -1;
11089 last_data_prefix
= -1;
11090 last_addr_prefix
= -1;
11091 last_rex_prefix
= -1;
11092 last_seg_prefix
= -1;
11094 active_seg_prefix
= 0;
11095 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11096 all_prefixes
[i
] = 0;
11099 /* The maximum instruction length is 15bytes. */
11100 while (length
< MAX_CODE_LENGTH
- 1)
11102 FETCH_DATA (the_info
, codep
+ 1);
11106 /* REX prefixes family. */
11123 if (address_mode
== mode_64bit
)
11127 last_rex_prefix
= i
;
11130 prefixes
|= PREFIX_REPZ
;
11131 last_repz_prefix
= i
;
11134 prefixes
|= PREFIX_REPNZ
;
11135 last_repnz_prefix
= i
;
11138 prefixes
|= PREFIX_LOCK
;
11139 last_lock_prefix
= i
;
11142 prefixes
|= PREFIX_CS
;
11143 last_seg_prefix
= i
;
11144 active_seg_prefix
= PREFIX_CS
;
11147 prefixes
|= PREFIX_SS
;
11148 last_seg_prefix
= i
;
11149 active_seg_prefix
= PREFIX_SS
;
11152 prefixes
|= PREFIX_DS
;
11153 last_seg_prefix
= i
;
11154 active_seg_prefix
= PREFIX_DS
;
11157 prefixes
|= PREFIX_ES
;
11158 last_seg_prefix
= i
;
11159 active_seg_prefix
= PREFIX_ES
;
11162 prefixes
|= PREFIX_FS
;
11163 last_seg_prefix
= i
;
11164 active_seg_prefix
= PREFIX_FS
;
11167 prefixes
|= PREFIX_GS
;
11168 last_seg_prefix
= i
;
11169 active_seg_prefix
= PREFIX_GS
;
11172 prefixes
|= PREFIX_DATA
;
11173 last_data_prefix
= i
;
11176 prefixes
|= PREFIX_ADDR
;
11177 last_addr_prefix
= i
;
11180 /* fwait is really an instruction. If there are prefixes
11181 before the fwait, they belong to the fwait, *not* to the
11182 following instruction. */
11184 if (prefixes
|| rex
)
11186 prefixes
|= PREFIX_FWAIT
;
11188 /* This ensures that the previous REX prefixes are noticed
11189 as unused prefixes, as in the return case below. */
11193 prefixes
= PREFIX_FWAIT
;
11198 /* Rex is ignored when followed by another prefix. */
11204 if (*codep
!= FWAIT_OPCODE
)
11205 all_prefixes
[i
++] = *codep
;
11213 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11216 static const char *
11217 prefix_name (int pref
, int sizeflag
)
11219 static const char *rexes
[16] =
11222 "rex.B", /* 0x41 */
11223 "rex.X", /* 0x42 */
11224 "rex.XB", /* 0x43 */
11225 "rex.R", /* 0x44 */
11226 "rex.RB", /* 0x45 */
11227 "rex.RX", /* 0x46 */
11228 "rex.RXB", /* 0x47 */
11229 "rex.W", /* 0x48 */
11230 "rex.WB", /* 0x49 */
11231 "rex.WX", /* 0x4a */
11232 "rex.WXB", /* 0x4b */
11233 "rex.WR", /* 0x4c */
11234 "rex.WRB", /* 0x4d */
11235 "rex.WRX", /* 0x4e */
11236 "rex.WRXB", /* 0x4f */
11241 /* REX prefixes family. */
11258 return rexes
[pref
- 0x40];
11278 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11280 if (address_mode
== mode_64bit
)
11281 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11283 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11288 case XACQUIRE_PREFIX
:
11290 case XRELEASE_PREFIX
:
11294 case NOTRACK_PREFIX
:
11301 static char op_out
[MAX_OPERANDS
][100];
11302 static int op_ad
, op_index
[MAX_OPERANDS
];
11303 static int two_source_ops
;
11304 static bfd_vma op_address
[MAX_OPERANDS
];
11305 static bfd_vma op_riprel
[MAX_OPERANDS
];
11306 static bfd_vma start_pc
;
11309 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11310 * (see topic "Redundant prefixes" in the "Differences from 8086"
11311 * section of the "Virtual 8086 Mode" chapter.)
11312 * 'pc' should be the address of this instruction, it will
11313 * be used to print the target address if this is a relative jump or call
11314 * The function returns the length of this instruction in bytes.
11317 static char intel_syntax
;
11318 static char intel_mnemonic
= !SYSV386_COMPAT
;
11319 static char open_char
;
11320 static char close_char
;
11321 static char separator_char
;
11322 static char scale_char
;
11330 static enum x86_64_isa isa64
;
11332 /* Here for backwards compatibility. When gdb stops using
11333 print_insn_i386_att and print_insn_i386_intel these functions can
11334 disappear, and print_insn_i386 be merged into print_insn. */
11336 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11340 return print_insn (pc
, info
);
11344 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11348 return print_insn (pc
, info
);
11352 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11356 return print_insn (pc
, info
);
11360 print_i386_disassembler_options (FILE *stream
)
11362 fprintf (stream
, _("\n\
11363 The following i386/x86-64 specific disassembler options are supported for use\n\
11364 with the -M switch (multiple options should be separated by commas):\n"));
11366 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11367 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11368 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11369 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11370 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11371 fprintf (stream
, _(" att-mnemonic\n"
11372 " Display instruction in AT&T mnemonic\n"));
11373 fprintf (stream
, _(" intel-mnemonic\n"
11374 " Display instruction in Intel mnemonic\n"));
11375 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11376 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11377 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11378 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11379 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11380 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11381 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11382 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11386 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11388 /* Get a pointer to struct dis386 with a valid name. */
11390 static const struct dis386
*
11391 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11393 int vindex
, vex_table_index
;
11395 if (dp
->name
!= NULL
)
11398 switch (dp
->op
[0].bytemode
)
11400 case USE_REG_TABLE
:
11401 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11404 case USE_MOD_TABLE
:
11405 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11406 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11410 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11413 case USE_PREFIX_TABLE
:
11416 /* The prefix in VEX is implicit. */
11417 switch (vex
.prefix
)
11422 case REPE_PREFIX_OPCODE
:
11425 case DATA_PREFIX_OPCODE
:
11428 case REPNE_PREFIX_OPCODE
:
11438 int last_prefix
= -1;
11441 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11442 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11444 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11446 if (last_repz_prefix
> last_repnz_prefix
)
11449 prefix
= PREFIX_REPZ
;
11450 last_prefix
= last_repz_prefix
;
11455 prefix
= PREFIX_REPNZ
;
11456 last_prefix
= last_repnz_prefix
;
11459 /* Check if prefix should be ignored. */
11460 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11461 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11466 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11469 prefix
= PREFIX_DATA
;
11470 last_prefix
= last_data_prefix
;
11475 used_prefixes
|= prefix
;
11476 all_prefixes
[last_prefix
] = 0;
11479 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11482 case USE_X86_64_TABLE
:
11483 vindex
= address_mode
== mode_64bit
? 1 : 0;
11484 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11487 case USE_3BYTE_TABLE
:
11488 FETCH_DATA (info
, codep
+ 2);
11490 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11492 modrm
.mod
= (*codep
>> 6) & 3;
11493 modrm
.reg
= (*codep
>> 3) & 7;
11494 modrm
.rm
= *codep
& 7;
11497 case USE_VEX_LEN_TABLE
:
11501 switch (vex
.length
)
11514 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11517 case USE_EVEX_LEN_TABLE
:
11521 switch (vex
.length
)
11537 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11540 case USE_XOP_8F_TABLE
:
11541 FETCH_DATA (info
, codep
+ 3);
11542 /* All bits in the REX prefix are ignored. */
11544 rex
= ~(*codep
>> 5) & 0x7;
11546 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11547 switch ((*codep
& 0x1f))
11553 vex_table_index
= XOP_08
;
11556 vex_table_index
= XOP_09
;
11559 vex_table_index
= XOP_0A
;
11563 vex
.w
= *codep
& 0x80;
11564 if (vex
.w
&& address_mode
== mode_64bit
)
11567 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11568 if (address_mode
!= mode_64bit
)
11570 /* In 16/32-bit mode REX_B is silently ignored. */
11574 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11575 switch ((*codep
& 0x3))
11580 vex
.prefix
= DATA_PREFIX_OPCODE
;
11583 vex
.prefix
= REPE_PREFIX_OPCODE
;
11586 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11593 dp
= &xop_table
[vex_table_index
][vindex
];
11596 FETCH_DATA (info
, codep
+ 1);
11597 modrm
.mod
= (*codep
>> 6) & 3;
11598 modrm
.reg
= (*codep
>> 3) & 7;
11599 modrm
.rm
= *codep
& 7;
11602 case USE_VEX_C4_TABLE
:
11604 FETCH_DATA (info
, codep
+ 3);
11605 /* All bits in the REX prefix are ignored. */
11607 rex
= ~(*codep
>> 5) & 0x7;
11608 switch ((*codep
& 0x1f))
11614 vex_table_index
= VEX_0F
;
11617 vex_table_index
= VEX_0F38
;
11620 vex_table_index
= VEX_0F3A
;
11624 vex
.w
= *codep
& 0x80;
11625 if (address_mode
== mode_64bit
)
11632 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11633 is ignored, other REX bits are 0 and the highest bit in
11634 VEX.vvvv is also ignored (but we mustn't clear it here). */
11637 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11638 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11639 switch ((*codep
& 0x3))
11644 vex
.prefix
= DATA_PREFIX_OPCODE
;
11647 vex
.prefix
= REPE_PREFIX_OPCODE
;
11650 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11657 dp
= &vex_table
[vex_table_index
][vindex
];
11659 /* There is no MODRM byte for VEX0F 77. */
11660 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11662 FETCH_DATA (info
, codep
+ 1);
11663 modrm
.mod
= (*codep
>> 6) & 3;
11664 modrm
.reg
= (*codep
>> 3) & 7;
11665 modrm
.rm
= *codep
& 7;
11669 case USE_VEX_C5_TABLE
:
11671 FETCH_DATA (info
, codep
+ 2);
11672 /* All bits in the REX prefix are ignored. */
11674 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11676 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11678 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11679 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11680 switch ((*codep
& 0x3))
11685 vex
.prefix
= DATA_PREFIX_OPCODE
;
11688 vex
.prefix
= REPE_PREFIX_OPCODE
;
11691 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11698 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11700 /* There is no MODRM byte for VEX 77. */
11701 if (vindex
!= 0x77)
11703 FETCH_DATA (info
, codep
+ 1);
11704 modrm
.mod
= (*codep
>> 6) & 3;
11705 modrm
.reg
= (*codep
>> 3) & 7;
11706 modrm
.rm
= *codep
& 7;
11710 case USE_VEX_W_TABLE
:
11714 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11717 case USE_EVEX_TABLE
:
11718 two_source_ops
= 0;
11721 FETCH_DATA (info
, codep
+ 4);
11722 /* All bits in the REX prefix are ignored. */
11724 /* The first byte after 0x62. */
11725 rex
= ~(*codep
>> 5) & 0x7;
11726 vex
.r
= *codep
& 0x10;
11727 switch ((*codep
& 0xf))
11730 return &bad_opcode
;
11732 vex_table_index
= EVEX_0F
;
11735 vex_table_index
= EVEX_0F38
;
11738 vex_table_index
= EVEX_0F3A
;
11742 /* The second byte after 0x62. */
11744 vex
.w
= *codep
& 0x80;
11745 if (vex
.w
&& address_mode
== mode_64bit
)
11748 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11751 if (!(*codep
& 0x4))
11752 return &bad_opcode
;
11754 switch ((*codep
& 0x3))
11759 vex
.prefix
= DATA_PREFIX_OPCODE
;
11762 vex
.prefix
= REPE_PREFIX_OPCODE
;
11765 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11769 /* The third byte after 0x62. */
11772 /* Remember the static rounding bits. */
11773 vex
.ll
= (*codep
>> 5) & 3;
11774 vex
.b
= (*codep
& 0x10) != 0;
11776 vex
.v
= *codep
& 0x8;
11777 vex
.mask_register_specifier
= *codep
& 0x7;
11778 vex
.zeroing
= *codep
& 0x80;
11780 if (address_mode
!= mode_64bit
)
11782 /* In 16/32-bit mode silently ignore following bits. */
11792 dp
= &evex_table
[vex_table_index
][vindex
];
11794 FETCH_DATA (info
, codep
+ 1);
11795 modrm
.mod
= (*codep
>> 6) & 3;
11796 modrm
.reg
= (*codep
>> 3) & 7;
11797 modrm
.rm
= *codep
& 7;
11799 /* Set vector length. */
11800 if (modrm
.mod
== 3 && vex
.b
)
11816 return &bad_opcode
;
11829 if (dp
->name
!= NULL
)
11832 return get_valid_dis386 (dp
, info
);
11836 get_sib (disassemble_info
*info
, int sizeflag
)
11838 /* If modrm.mod == 3, operand must be register. */
11840 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11844 FETCH_DATA (info
, codep
+ 2);
11845 sib
.index
= (codep
[1] >> 3) & 7;
11846 sib
.scale
= (codep
[1] >> 6) & 3;
11847 sib
.base
= codep
[1] & 7;
11852 print_insn (bfd_vma pc
, disassemble_info
*info
)
11854 const struct dis386
*dp
;
11856 char *op_txt
[MAX_OPERANDS
];
11858 int sizeflag
, orig_sizeflag
;
11860 struct dis_private priv
;
11863 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11864 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11865 address_mode
= mode_32bit
;
11866 else if (info
->mach
== bfd_mach_i386_i8086
)
11868 address_mode
= mode_16bit
;
11869 priv
.orig_sizeflag
= 0;
11872 address_mode
= mode_64bit
;
11874 if (intel_syntax
== (char) -1)
11875 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11877 for (p
= info
->disassembler_options
; p
!= NULL
; )
11879 if (CONST_STRNEQ (p
, "amd64"))
11881 else if (CONST_STRNEQ (p
, "intel64"))
11883 else if (CONST_STRNEQ (p
, "x86-64"))
11885 address_mode
= mode_64bit
;
11886 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11888 else if (CONST_STRNEQ (p
, "i386"))
11890 address_mode
= mode_32bit
;
11891 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11893 else if (CONST_STRNEQ (p
, "i8086"))
11895 address_mode
= mode_16bit
;
11896 priv
.orig_sizeflag
= 0;
11898 else if (CONST_STRNEQ (p
, "intel"))
11901 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11902 intel_mnemonic
= 1;
11904 else if (CONST_STRNEQ (p
, "att"))
11907 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11908 intel_mnemonic
= 0;
11910 else if (CONST_STRNEQ (p
, "addr"))
11912 if (address_mode
== mode_64bit
)
11914 if (p
[4] == '3' && p
[5] == '2')
11915 priv
.orig_sizeflag
&= ~AFLAG
;
11916 else if (p
[4] == '6' && p
[5] == '4')
11917 priv
.orig_sizeflag
|= AFLAG
;
11921 if (p
[4] == '1' && p
[5] == '6')
11922 priv
.orig_sizeflag
&= ~AFLAG
;
11923 else if (p
[4] == '3' && p
[5] == '2')
11924 priv
.orig_sizeflag
|= AFLAG
;
11927 else if (CONST_STRNEQ (p
, "data"))
11929 if (p
[4] == '1' && p
[5] == '6')
11930 priv
.orig_sizeflag
&= ~DFLAG
;
11931 else if (p
[4] == '3' && p
[5] == '2')
11932 priv
.orig_sizeflag
|= DFLAG
;
11934 else if (CONST_STRNEQ (p
, "suffix"))
11935 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11937 p
= strchr (p
, ',');
11942 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11944 (*info
->fprintf_func
) (info
->stream
,
11945 _("64-bit address is disabled"));
11951 names64
= intel_names64
;
11952 names32
= intel_names32
;
11953 names16
= intel_names16
;
11954 names8
= intel_names8
;
11955 names8rex
= intel_names8rex
;
11956 names_seg
= intel_names_seg
;
11957 names_mm
= intel_names_mm
;
11958 names_bnd
= intel_names_bnd
;
11959 names_xmm
= intel_names_xmm
;
11960 names_ymm
= intel_names_ymm
;
11961 names_zmm
= intel_names_zmm
;
11962 index64
= intel_index64
;
11963 index32
= intel_index32
;
11964 names_mask
= intel_names_mask
;
11965 index16
= intel_index16
;
11968 separator_char
= '+';
11973 names64
= att_names64
;
11974 names32
= att_names32
;
11975 names16
= att_names16
;
11976 names8
= att_names8
;
11977 names8rex
= att_names8rex
;
11978 names_seg
= att_names_seg
;
11979 names_mm
= att_names_mm
;
11980 names_bnd
= att_names_bnd
;
11981 names_xmm
= att_names_xmm
;
11982 names_ymm
= att_names_ymm
;
11983 names_zmm
= att_names_zmm
;
11984 index64
= att_index64
;
11985 index32
= att_index32
;
11986 names_mask
= att_names_mask
;
11987 index16
= att_index16
;
11990 separator_char
= ',';
11994 /* The output looks better if we put 7 bytes on a line, since that
11995 puts most long word instructions on a single line. Use 8 bytes
11997 if ((info
->mach
& bfd_mach_l1om
) != 0)
11998 info
->bytes_per_line
= 8;
12000 info
->bytes_per_line
= 7;
12002 info
->private_data
= &priv
;
12003 priv
.max_fetched
= priv
.the_buffer
;
12004 priv
.insn_start
= pc
;
12007 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12015 start_codep
= priv
.the_buffer
;
12016 codep
= priv
.the_buffer
;
12018 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12022 /* Getting here means we tried for data but didn't get it. That
12023 means we have an incomplete instruction of some sort. Just
12024 print the first byte as a prefix or a .byte pseudo-op. */
12025 if (codep
> priv
.the_buffer
)
12027 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12029 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12032 /* Just print the first byte as a .byte instruction. */
12033 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12034 (unsigned int) priv
.the_buffer
[0]);
12044 sizeflag
= priv
.orig_sizeflag
;
12046 if (!ckprefix () || rex_used
)
12048 /* Too many prefixes or unused REX prefixes. */
12050 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12052 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12054 prefix_name (all_prefixes
[i
], sizeflag
));
12058 insn_codep
= codep
;
12060 FETCH_DATA (info
, codep
+ 1);
12061 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12063 if (((prefixes
& PREFIX_FWAIT
)
12064 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12066 /* Handle prefixes before fwait. */
12067 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12069 (*info
->fprintf_func
) (info
->stream
, "%s ",
12070 prefix_name (all_prefixes
[i
], sizeflag
));
12071 (*info
->fprintf_func
) (info
->stream
, "fwait");
12075 if (*codep
== 0x0f)
12077 unsigned char threebyte
;
12080 FETCH_DATA (info
, codep
+ 1);
12081 threebyte
= *codep
;
12082 dp
= &dis386_twobyte
[threebyte
];
12083 need_modrm
= twobyte_has_modrm
[*codep
];
12088 dp
= &dis386
[*codep
];
12089 need_modrm
= onebyte_has_modrm
[*codep
];
12093 /* Save sizeflag for printing the extra prefixes later before updating
12094 it for mnemonic and operand processing. The prefix names depend
12095 only on the address mode. */
12096 orig_sizeflag
= sizeflag
;
12097 if (prefixes
& PREFIX_ADDR
)
12099 if ((prefixes
& PREFIX_DATA
))
12105 FETCH_DATA (info
, codep
+ 1);
12106 modrm
.mod
= (*codep
>> 6) & 3;
12107 modrm
.reg
= (*codep
>> 3) & 7;
12108 modrm
.rm
= *codep
& 7;
12114 memset (&vex
, 0, sizeof (vex
));
12116 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12118 get_sib (info
, sizeflag
);
12119 dofloat (sizeflag
);
12123 dp
= get_valid_dis386 (dp
, info
);
12124 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12126 get_sib (info
, sizeflag
);
12127 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12130 op_ad
= MAX_OPERANDS
- 1 - i
;
12132 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12133 /* For EVEX instruction after the last operand masking
12134 should be printed. */
12135 if (i
== 0 && vex
.evex
)
12137 /* Don't print {%k0}. */
12138 if (vex
.mask_register_specifier
)
12141 oappend (names_mask
[vex
.mask_register_specifier
]);
12151 /* Clear instruction information. */
12154 the_info
->insn_info_valid
= 0;
12155 the_info
->branch_delay_insns
= 0;
12156 the_info
->data_size
= 0;
12157 the_info
->insn_type
= dis_noninsn
;
12158 the_info
->target
= 0;
12159 the_info
->target2
= 0;
12162 /* Reset jump operation indicator. */
12163 op_is_jump
= FALSE
;
12166 int jump_detection
= 0;
12168 /* Extract flags. */
12169 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12171 if ((dp
->op
[i
].rtn
== OP_J
)
12172 || (dp
->op
[i
].rtn
== OP_indirE
))
12173 jump_detection
|= 1;
12174 else if ((dp
->op
[i
].rtn
== BND_Fixup
)
12175 || (!dp
->op
[i
].rtn
&& !dp
->op
[i
].bytemode
))
12176 jump_detection
|= 2;
12177 else if ((dp
->op
[i
].bytemode
== cond_jump_mode
)
12178 || (dp
->op
[i
].bytemode
== loop_jcxz_mode
))
12179 jump_detection
|= 4;
12182 /* Determine if this is a jump or branch. */
12183 if ((jump_detection
& 0x3) == 0x3)
12186 if (jump_detection
& 0x4)
12187 the_info
->insn_type
= dis_condbranch
;
12189 the_info
->insn_type
=
12190 (dp
->name
&& !strncmp(dp
->name
, "call", 4))
12191 ? dis_jsr
: dis_branch
;
12195 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12196 are all 0s in inverted form. */
12197 if (need_vex
&& vex
.register_specifier
!= 0)
12199 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12200 return end_codep
- priv
.the_buffer
;
12203 /* Check if the REX prefix is used. */
12204 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12205 all_prefixes
[last_rex_prefix
] = 0;
12207 /* Check if the SEG prefix is used. */
12208 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12209 | PREFIX_FS
| PREFIX_GS
)) != 0
12210 && (used_prefixes
& active_seg_prefix
) != 0)
12211 all_prefixes
[last_seg_prefix
] = 0;
12213 /* Check if the ADDR prefix is used. */
12214 if ((prefixes
& PREFIX_ADDR
) != 0
12215 && (used_prefixes
& PREFIX_ADDR
) != 0)
12216 all_prefixes
[last_addr_prefix
] = 0;
12218 /* Check if the DATA prefix is used. */
12219 if ((prefixes
& PREFIX_DATA
) != 0
12220 && (used_prefixes
& PREFIX_DATA
) != 0)
12221 all_prefixes
[last_data_prefix
] = 0;
12223 /* Print the extra prefixes. */
12225 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12226 if (all_prefixes
[i
])
12229 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12232 prefix_length
+= strlen (name
) + 1;
12233 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12236 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12237 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12238 used by putop and MMX/SSE operand and may be overriden by the
12239 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12241 if (dp
->prefix_requirement
== PREFIX_OPCODE
12242 && dp
!= &bad_opcode
12244 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12246 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12248 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12250 && (used_prefixes
& PREFIX_DATA
) == 0))))
12252 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12253 return end_codep
- priv
.the_buffer
;
12256 /* Check maximum code length. */
12257 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12259 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12260 return MAX_CODE_LENGTH
;
12263 obufp
= mnemonicendp
;
12264 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12267 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12269 /* The enter and bound instructions are printed with operands in the same
12270 order as the intel book; everything else is printed in reverse order. */
12271 if (intel_syntax
|| two_source_ops
)
12275 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12276 op_txt
[i
] = op_out
[i
];
12278 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12279 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12281 op_txt
[2] = op_out
[3];
12282 op_txt
[3] = op_out
[2];
12285 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12287 op_ad
= op_index
[i
];
12288 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12289 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12290 riprel
= op_riprel
[i
];
12291 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12292 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12297 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12298 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12302 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12306 (*info
->fprintf_func
) (info
->stream
, ",");
12307 if (op_index
[i
] != -1 && !op_riprel
[i
])
12309 bfd_vma target
= (bfd_vma
) op_address
[op_index
[i
]];
12311 if (the_info
&& op_is_jump
)
12313 the_info
->insn_info_valid
= 1;
12314 the_info
->branch_delay_insns
= 0;
12315 the_info
->data_size
= 0;
12316 the_info
->target
= target
;
12317 the_info
->target2
= 0;
12319 (*info
->print_address_func
) (target
, info
);
12322 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12326 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12327 if (op_index
[i
] != -1 && op_riprel
[i
])
12329 (*info
->fprintf_func
) (info
->stream
, " # ");
12330 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12331 + op_address
[op_index
[i
]]), info
);
12334 return codep
- priv
.the_buffer
;
12337 static const char *float_mem
[] = {
12412 static const unsigned char float_mem_mode
[] = {
12487 #define ST { OP_ST, 0 }
12488 #define STi { OP_STi, 0 }
12490 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12491 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12492 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12493 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12494 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12495 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12496 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12497 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12498 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12500 static const struct dis386 float_reg
[][8] = {
12503 { "fadd", { ST
, STi
}, 0 },
12504 { "fmul", { ST
, STi
}, 0 },
12505 { "fcom", { STi
}, 0 },
12506 { "fcomp", { STi
}, 0 },
12507 { "fsub", { ST
, STi
}, 0 },
12508 { "fsubr", { ST
, STi
}, 0 },
12509 { "fdiv", { ST
, STi
}, 0 },
12510 { "fdivr", { ST
, STi
}, 0 },
12514 { "fld", { STi
}, 0 },
12515 { "fxch", { STi
}, 0 },
12525 { "fcmovb", { ST
, STi
}, 0 },
12526 { "fcmove", { ST
, STi
}, 0 },
12527 { "fcmovbe",{ ST
, STi
}, 0 },
12528 { "fcmovu", { ST
, STi
}, 0 },
12536 { "fcmovnb",{ ST
, STi
}, 0 },
12537 { "fcmovne",{ ST
, STi
}, 0 },
12538 { "fcmovnbe",{ ST
, STi
}, 0 },
12539 { "fcmovnu",{ ST
, STi
}, 0 },
12541 { "fucomi", { ST
, STi
}, 0 },
12542 { "fcomi", { ST
, STi
}, 0 },
12547 { "fadd", { STi
, ST
}, 0 },
12548 { "fmul", { STi
, ST
}, 0 },
12551 { "fsub{!M|r}", { STi
, ST
}, 0 },
12552 { "fsub{M|}", { STi
, ST
}, 0 },
12553 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12554 { "fdiv{M|}", { STi
, ST
}, 0 },
12558 { "ffree", { STi
}, 0 },
12560 { "fst", { STi
}, 0 },
12561 { "fstp", { STi
}, 0 },
12562 { "fucom", { STi
}, 0 },
12563 { "fucomp", { STi
}, 0 },
12569 { "faddp", { STi
, ST
}, 0 },
12570 { "fmulp", { STi
, ST
}, 0 },
12573 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12574 { "fsub{M|}p", { STi
, ST
}, 0 },
12575 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12576 { "fdiv{M|}p", { STi
, ST
}, 0 },
12580 { "ffreep", { STi
}, 0 },
12585 { "fucomip", { ST
, STi
}, 0 },
12586 { "fcomip", { ST
, STi
}, 0 },
12591 static char *fgrps
[][8] = {
12594 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12599 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12604 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12609 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12614 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12619 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12624 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12629 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12630 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12635 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12640 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12645 swap_operand (void)
12647 mnemonicendp
[0] = '.';
12648 mnemonicendp
[1] = 's';
12653 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12654 int sizeflag ATTRIBUTE_UNUSED
)
12656 /* Skip mod/rm byte. */
12662 dofloat (int sizeflag
)
12664 const struct dis386
*dp
;
12665 unsigned char floatop
;
12667 floatop
= codep
[-1];
12669 if (modrm
.mod
!= 3)
12671 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12673 putop (float_mem
[fp_indx
], sizeflag
);
12676 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12679 /* Skip mod/rm byte. */
12683 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12684 if (dp
->name
== NULL
)
12686 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12688 /* Instruction fnstsw is only one with strange arg. */
12689 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12690 strcpy (op_out
[0], names16
[0]);
12694 putop (dp
->name
, sizeflag
);
12699 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12704 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12708 /* Like oappend (below), but S is a string starting with '%'.
12709 In Intel syntax, the '%' is elided. */
12711 oappend_maybe_intel (const char *s
)
12713 oappend (s
+ intel_syntax
);
12717 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12719 oappend_maybe_intel ("%st");
12723 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12725 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12726 oappend_maybe_intel (scratchbuf
);
12729 /* Capital letters in template are macros. */
12731 putop (const char *in_template
, int sizeflag
)
12736 unsigned int l
= 0, len
= 1;
12739 #define SAVE_LAST(c) \
12740 if (l < len && l < sizeof (last)) \
12745 for (p
= in_template
; *p
; p
++)
12761 while (*++p
!= '|')
12762 if (*p
== '}' || *p
== '\0')
12765 /* Fall through. */
12770 while (*++p
!= '}')
12781 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12785 if (l
== 0 && len
== 1)
12790 if (sizeflag
& SUFFIX_ALWAYS
)
12803 if (address_mode
== mode_64bit
12804 && !(prefixes
& PREFIX_ADDR
))
12815 if (intel_syntax
&& !alt
)
12817 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12819 if (sizeflag
& DFLAG
)
12820 *obufp
++ = intel_syntax
? 'd' : 'l';
12822 *obufp
++ = intel_syntax
? 'w' : 's';
12823 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12827 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12830 if (modrm
.mod
== 3)
12836 if (sizeflag
& DFLAG
)
12837 *obufp
++ = intel_syntax
? 'd' : 'l';
12840 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12846 case 'E': /* For jcxz/jecxz */
12847 if (address_mode
== mode_64bit
)
12849 if (sizeflag
& AFLAG
)
12855 if (sizeflag
& AFLAG
)
12857 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12862 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12864 if (sizeflag
& AFLAG
)
12865 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12867 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12868 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12872 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12874 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12878 if (!(rex
& REX_W
))
12879 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12884 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12885 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12887 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12890 if (prefixes
& PREFIX_DS
)
12909 if (l
!= 0 || len
!= 1)
12911 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12916 if (!need_vex
|| !vex
.evex
)
12919 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12921 switch (vex
.length
)
12939 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12944 /* Fall through. */
12947 if (l
!= 0 || len
!= 1)
12955 if (sizeflag
& SUFFIX_ALWAYS
)
12959 if (intel_mnemonic
!= cond
)
12963 if ((prefixes
& PREFIX_FWAIT
) == 0)
12966 used_prefixes
|= PREFIX_FWAIT
;
12972 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12976 if (!(rex
& REX_W
))
12977 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12981 && address_mode
== mode_64bit
12982 && isa64
== intel64
)
12987 /* Fall through. */
12990 && address_mode
== mode_64bit
12991 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12996 /* Fall through. */
12999 if (l
== 0 && len
== 1)
13004 if ((rex
& REX_W
) == 0
13005 && (prefixes
& PREFIX_DATA
))
13007 if ((sizeflag
& DFLAG
) == 0)
13009 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13013 if ((prefixes
& PREFIX_DATA
)
13015 || (sizeflag
& SUFFIX_ALWAYS
))
13022 if (sizeflag
& DFLAG
)
13026 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13032 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13038 if ((prefixes
& PREFIX_DATA
)
13040 || (sizeflag
& SUFFIX_ALWAYS
))
13047 if (sizeflag
& DFLAG
)
13048 *obufp
++ = intel_syntax
? 'd' : 'l';
13051 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13059 if (address_mode
== mode_64bit
13060 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13062 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13066 /* Fall through. */
13069 if (l
== 0 && len
== 1)
13072 if (intel_syntax
&& !alt
)
13075 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13081 if (sizeflag
& DFLAG
)
13082 *obufp
++ = intel_syntax
? 'd' : 'l';
13085 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13091 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13097 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13112 else if (sizeflag
& DFLAG
)
13121 if (intel_syntax
&& !p
[1]
13122 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13124 if (!(rex
& REX_W
))
13125 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13128 if (l
== 0 && len
== 1)
13132 if (address_mode
== mode_64bit
13133 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13135 if (sizeflag
& SUFFIX_ALWAYS
)
13157 /* Fall through. */
13160 if (l
== 0 && len
== 1)
13165 if (sizeflag
& SUFFIX_ALWAYS
)
13171 if (sizeflag
& DFLAG
)
13175 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13189 if (address_mode
== mode_64bit
13190 && !(prefixes
& PREFIX_ADDR
))
13201 if (l
!= 0 || len
!= 1)
13206 if (need_vex
&& vex
.prefix
)
13208 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13215 if (prefixes
& PREFIX_DATA
)
13219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13223 if (l
== 0 && len
== 1)
13227 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13235 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13237 switch (vex
.length
)
13253 if (l
== 0 && len
== 1)
13255 /* operand size flag for cwtl, cbtw */
13264 else if (sizeflag
& DFLAG
)
13268 if (!(rex
& REX_W
))
13269 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13276 && last
[0] != 'L'))
13283 if (last
[0] == 'X')
13284 *obufp
++ = vex
.w
? 'd': 's';
13286 *obufp
++ = vex
.w
? 'q': 'd';
13292 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13294 if (sizeflag
& DFLAG
)
13298 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13304 if (address_mode
== mode_64bit
13305 && (isa64
== intel64
13306 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13308 else if ((prefixes
& PREFIX_DATA
))
13310 if (!(sizeflag
& DFLAG
))
13312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13319 mnemonicendp
= obufp
;
13324 oappend (const char *s
)
13326 obufp
= stpcpy (obufp
, s
);
13332 /* Only print the active segment register. */
13333 if (!active_seg_prefix
)
13336 used_prefixes
|= active_seg_prefix
;
13337 switch (active_seg_prefix
)
13340 oappend_maybe_intel ("%cs:");
13343 oappend_maybe_intel ("%ds:");
13346 oappend_maybe_intel ("%ss:");
13349 oappend_maybe_intel ("%es:");
13352 oappend_maybe_intel ("%fs:");
13355 oappend_maybe_intel ("%gs:");
13363 OP_indirE (int bytemode
, int sizeflag
)
13367 OP_E (bytemode
, sizeflag
);
13371 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13373 if (address_mode
== mode_64bit
)
13381 sprintf_vma (tmp
, disp
);
13382 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13383 strcpy (buf
+ 2, tmp
+ i
);
13387 bfd_signed_vma v
= disp
;
13394 /* Check for possible overflow on 0x8000000000000000. */
13397 strcpy (buf
, "9223372036854775808");
13411 tmp
[28 - i
] = (v
% 10) + '0';
13415 strcpy (buf
, tmp
+ 29 - i
);
13421 sprintf (buf
, "0x%x", (unsigned int) disp
);
13423 sprintf (buf
, "%d", (int) disp
);
13427 /* Put DISP in BUF as signed hex number. */
13430 print_displacement (char *buf
, bfd_vma disp
)
13432 bfd_signed_vma val
= disp
;
13441 /* Check for possible overflow. */
13444 switch (address_mode
)
13447 strcpy (buf
+ j
, "0x8000000000000000");
13450 strcpy (buf
+ j
, "0x80000000");
13453 strcpy (buf
+ j
, "0x8000");
13463 sprintf_vma (tmp
, (bfd_vma
) val
);
13464 for (i
= 0; tmp
[i
] == '0'; i
++)
13466 if (tmp
[i
] == '\0')
13468 strcpy (buf
+ j
, tmp
+ i
);
13472 intel_operand_size (int bytemode
, int sizeflag
)
13476 && (bytemode
== x_mode
13477 || bytemode
== evex_half_bcst_xmmq_mode
))
13480 oappend ("QWORD PTR ");
13482 oappend ("DWORD PTR ");
13491 oappend ("BYTE PTR ");
13496 oappend ("WORD PTR ");
13499 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13501 oappend ("QWORD PTR ");
13504 /* Fall through. */
13506 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13508 oappend ("QWORD PTR ");
13511 /* Fall through. */
13517 oappend ("QWORD PTR ");
13520 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13521 oappend ("DWORD PTR ");
13523 oappend ("WORD PTR ");
13524 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13528 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13530 oappend ("WORD PTR ");
13531 if (!(rex
& REX_W
))
13532 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13535 if (sizeflag
& DFLAG
)
13536 oappend ("QWORD PTR ");
13538 oappend ("DWORD PTR ");
13539 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13542 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13543 oappend ("WORD PTR ");
13545 oappend ("DWORD PTR ");
13546 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13549 case d_scalar_mode
:
13550 case d_scalar_swap_mode
:
13553 oappend ("DWORD PTR ");
13556 case q_scalar_mode
:
13557 case q_scalar_swap_mode
:
13559 oappend ("QWORD PTR ");
13562 if (address_mode
== mode_64bit
)
13563 oappend ("QWORD PTR ");
13565 oappend ("DWORD PTR ");
13568 if (sizeflag
& DFLAG
)
13569 oappend ("FWORD PTR ");
13571 oappend ("DWORD PTR ");
13572 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13575 oappend ("TBYTE PTR ");
13579 case evex_x_gscat_mode
:
13580 case evex_x_nobcst_mode
:
13581 case b_scalar_mode
:
13582 case w_scalar_mode
:
13585 switch (vex
.length
)
13588 oappend ("XMMWORD PTR ");
13591 oappend ("YMMWORD PTR ");
13594 oappend ("ZMMWORD PTR ");
13601 oappend ("XMMWORD PTR ");
13604 oappend ("XMMWORD PTR ");
13607 oappend ("YMMWORD PTR ");
13610 case evex_half_bcst_xmmq_mode
:
13614 switch (vex
.length
)
13617 oappend ("QWORD PTR ");
13620 oappend ("XMMWORD PTR ");
13623 oappend ("YMMWORD PTR ");
13633 switch (vex
.length
)
13638 oappend ("BYTE PTR ");
13648 switch (vex
.length
)
13653 oappend ("WORD PTR ");
13663 switch (vex
.length
)
13668 oappend ("DWORD PTR ");
13678 switch (vex
.length
)
13683 oappend ("QWORD PTR ");
13693 switch (vex
.length
)
13696 oappend ("WORD PTR ");
13699 oappend ("DWORD PTR ");
13702 oappend ("QWORD PTR ");
13712 switch (vex
.length
)
13715 oappend ("DWORD PTR ");
13718 oappend ("QWORD PTR ");
13721 oappend ("XMMWORD PTR ");
13731 switch (vex
.length
)
13734 oappend ("QWORD PTR ");
13737 oappend ("YMMWORD PTR ");
13740 oappend ("ZMMWORD PTR ");
13750 switch (vex
.length
)
13754 oappend ("XMMWORD PTR ");
13761 oappend ("OWORD PTR ");
13764 case vex_w_dq_mode
:
13765 case vex_scalar_w_dq_mode
:
13770 oappend ("QWORD PTR ");
13772 oappend ("DWORD PTR ");
13774 case vex_vsib_d_w_dq_mode
:
13775 case vex_vsib_q_w_dq_mode
:
13782 oappend ("QWORD PTR ");
13784 oappend ("DWORD PTR ");
13788 switch (vex
.length
)
13791 oappend ("XMMWORD PTR ");
13794 oappend ("YMMWORD PTR ");
13797 oappend ("ZMMWORD PTR ");
13804 case vex_vsib_q_w_d_mode
:
13805 case vex_vsib_d_w_d_mode
:
13806 if (!need_vex
|| !vex
.evex
)
13809 switch (vex
.length
)
13812 oappend ("QWORD PTR ");
13815 oappend ("XMMWORD PTR ");
13818 oappend ("YMMWORD PTR ");
13826 if (!need_vex
|| vex
.length
!= 128)
13829 oappend ("DWORD PTR ");
13831 oappend ("BYTE PTR ");
13837 oappend ("QWORD PTR ");
13839 oappend ("WORD PTR ");
13849 OP_E_register (int bytemode
, int sizeflag
)
13851 int reg
= modrm
.rm
;
13852 const char **names
;
13858 if ((sizeflag
& SUFFIX_ALWAYS
)
13859 && (bytemode
== b_swap_mode
13860 || bytemode
== bnd_swap_mode
13861 || bytemode
== v_swap_mode
))
13887 names
= address_mode
== mode_64bit
? names64
: names32
;
13890 case bnd_swap_mode
:
13899 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13904 /* Fall through. */
13906 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13912 /* Fall through. */
13924 if ((sizeflag
& DFLAG
)
13925 || (bytemode
!= v_mode
13926 && bytemode
!= v_swap_mode
))
13930 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13934 if (!(sizeflag
& DFLAG
) && isa64
== intel64
)
13938 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13941 names
= (address_mode
== mode_64bit
13942 ? names64
: names32
);
13943 if (!(prefixes
& PREFIX_ADDR
))
13944 names
= (address_mode
== mode_16bit
13945 ? names16
: names
);
13948 /* Remove "addr16/addr32". */
13949 all_prefixes
[last_addr_prefix
] = 0;
13950 names
= (address_mode
!= mode_32bit
13951 ? names32
: names16
);
13952 used_prefixes
|= PREFIX_ADDR
;
13962 names
= names_mask
;
13967 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13970 oappend (names
[reg
]);
13974 OP_E_memory (int bytemode
, int sizeflag
)
13977 int add
= (rex
& REX_B
) ? 8 : 0;
13983 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13985 && bytemode
!= x_mode
13986 && bytemode
!= xmmq_mode
13987 && bytemode
!= evex_half_bcst_xmmq_mode
)
14003 if (address_mode
!= mode_64bit
)
14009 case vex_vsib_d_w_dq_mode
:
14010 case vex_vsib_d_w_d_mode
:
14011 case vex_vsib_q_w_dq_mode
:
14012 case vex_vsib_q_w_d_mode
:
14013 case evex_x_gscat_mode
:
14015 shift
= vex
.w
? 3 : 2;
14018 case evex_half_bcst_xmmq_mode
:
14022 shift
= vex
.w
? 3 : 2;
14025 /* Fall through. */
14029 case evex_x_nobcst_mode
:
14031 switch (vex
.length
)
14054 case q_scalar_mode
:
14056 case q_scalar_swap_mode
:
14062 case d_scalar_mode
:
14064 case d_scalar_swap_mode
:
14067 case w_scalar_mode
:
14071 case b_scalar_mode
:
14078 /* Make necessary corrections to shift for modes that need it.
14079 For these modes we currently have shift 4, 5 or 6 depending on
14080 vex.length (it corresponds to xmmword, ymmword or zmmword
14081 operand). We might want to make it 3, 4 or 5 (e.g. for
14082 xmmq_mode). In case of broadcast enabled the corrections
14083 aren't needed, as element size is always 32 or 64 bits. */
14085 && (bytemode
== xmmq_mode
14086 || bytemode
== evex_half_bcst_xmmq_mode
))
14088 else if (bytemode
== xmmqd_mode
)
14090 else if (bytemode
== xmmdw_mode
)
14092 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14100 intel_operand_size (bytemode
, sizeflag
);
14103 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14105 /* 32/64 bit address mode */
14115 int addr32flag
= !((sizeflag
& AFLAG
)
14116 || bytemode
== v_bnd_mode
14117 || bytemode
== v_bndmk_mode
14118 || bytemode
== bnd_mode
14119 || bytemode
== bnd_swap_mode
);
14120 const char **indexes64
= names64
;
14121 const char **indexes32
= names32
;
14131 vindex
= sib
.index
;
14137 case vex_vsib_d_w_dq_mode
:
14138 case vex_vsib_d_w_d_mode
:
14139 case vex_vsib_q_w_dq_mode
:
14140 case vex_vsib_q_w_d_mode
:
14150 switch (vex
.length
)
14153 indexes64
= indexes32
= names_xmm
;
14157 || bytemode
== vex_vsib_q_w_dq_mode
14158 || bytemode
== vex_vsib_q_w_d_mode
)
14159 indexes64
= indexes32
= names_ymm
;
14161 indexes64
= indexes32
= names_xmm
;
14165 || bytemode
== vex_vsib_q_w_dq_mode
14166 || bytemode
== vex_vsib_q_w_d_mode
)
14167 indexes64
= indexes32
= names_zmm
;
14169 indexes64
= indexes32
= names_ymm
;
14176 haveindex
= vindex
!= 4;
14183 rbase
= base
+ add
;
14191 if (address_mode
== mode_64bit
&& !havesib
)
14194 if (riprel
&& bytemode
== v_bndmk_mode
)
14202 FETCH_DATA (the_info
, codep
+ 1);
14204 if ((disp
& 0x80) != 0)
14206 if (vex
.evex
&& shift
> 0)
14219 && address_mode
!= mode_16bit
)
14221 if (address_mode
== mode_64bit
)
14223 /* Display eiz instead of addr32. */
14224 needindex
= addr32flag
;
14229 /* In 32-bit mode, we need index register to tell [offset]
14230 from [eiz*1 + offset]. */
14235 havedisp
= (havebase
14237 || (havesib
&& (haveindex
|| scale
!= 0)));
14240 if (modrm
.mod
!= 0 || base
== 5)
14242 if (havedisp
|| riprel
)
14243 print_displacement (scratchbuf
, disp
);
14245 print_operand_value (scratchbuf
, 1, disp
);
14246 oappend (scratchbuf
);
14250 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14254 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14255 && (bytemode
!= v_bnd_mode
)
14256 && (bytemode
!= v_bndmk_mode
)
14257 && (bytemode
!= bnd_mode
)
14258 && (bytemode
!= bnd_swap_mode
))
14259 used_prefixes
|= PREFIX_ADDR
;
14261 if (havedisp
|| (intel_syntax
&& riprel
))
14263 *obufp
++ = open_char
;
14264 if (intel_syntax
&& riprel
)
14267 oappend (!addr32flag
? "rip" : "eip");
14271 oappend (address_mode
== mode_64bit
&& !addr32flag
14272 ? names64
[rbase
] : names32
[rbase
]);
14275 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14276 print index to tell base + index from base. */
14280 || (havebase
&& base
!= ESP_REG_NUM
))
14282 if (!intel_syntax
|| havebase
)
14284 *obufp
++ = separator_char
;
14288 oappend (address_mode
== mode_64bit
&& !addr32flag
14289 ? indexes64
[vindex
] : indexes32
[vindex
]);
14291 oappend (address_mode
== mode_64bit
&& !addr32flag
14292 ? index64
: index32
);
14294 *obufp
++ = scale_char
;
14296 sprintf (scratchbuf
, "%d", 1 << scale
);
14297 oappend (scratchbuf
);
14301 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14303 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14308 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14312 disp
= - (bfd_signed_vma
) disp
;
14316 print_displacement (scratchbuf
, disp
);
14318 print_operand_value (scratchbuf
, 1, disp
);
14319 oappend (scratchbuf
);
14322 *obufp
++ = close_char
;
14325 else if (intel_syntax
)
14327 if (modrm
.mod
!= 0 || base
== 5)
14329 if (!active_seg_prefix
)
14331 oappend (names_seg
[ds_reg
- es_reg
]);
14334 print_operand_value (scratchbuf
, 1, disp
);
14335 oappend (scratchbuf
);
14341 /* 16 bit address mode */
14342 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14349 if ((disp
& 0x8000) != 0)
14354 FETCH_DATA (the_info
, codep
+ 1);
14356 if ((disp
& 0x80) != 0)
14358 if (vex
.evex
&& shift
> 0)
14363 if ((disp
& 0x8000) != 0)
14369 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14371 print_displacement (scratchbuf
, disp
);
14372 oappend (scratchbuf
);
14375 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14377 *obufp
++ = open_char
;
14379 oappend (index16
[modrm
.rm
]);
14381 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14383 if ((bfd_signed_vma
) disp
>= 0)
14388 else if (modrm
.mod
!= 1)
14392 disp
= - (bfd_signed_vma
) disp
;
14395 print_displacement (scratchbuf
, disp
);
14396 oappend (scratchbuf
);
14399 *obufp
++ = close_char
;
14402 else if (intel_syntax
)
14404 if (!active_seg_prefix
)
14406 oappend (names_seg
[ds_reg
- es_reg
]);
14409 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14410 oappend (scratchbuf
);
14413 if (vex
.evex
&& vex
.b
14414 && (bytemode
== x_mode
14415 || bytemode
== xmmq_mode
14416 || bytemode
== evex_half_bcst_xmmq_mode
))
14419 || bytemode
== xmmq_mode
14420 || bytemode
== evex_half_bcst_xmmq_mode
)
14422 switch (vex
.length
)
14425 oappend ("{1to2}");
14428 oappend ("{1to4}");
14431 oappend ("{1to8}");
14439 switch (vex
.length
)
14442 oappend ("{1to4}");
14445 oappend ("{1to8}");
14448 oappend ("{1to16}");
14458 OP_E (int bytemode
, int sizeflag
)
14460 /* Skip mod/rm byte. */
14464 if (modrm
.mod
== 3)
14465 OP_E_register (bytemode
, sizeflag
);
14467 OP_E_memory (bytemode
, sizeflag
);
14471 OP_G (int bytemode
, int sizeflag
)
14474 const char **names
;
14483 oappend (names8rex
[modrm
.reg
+ add
]);
14485 oappend (names8
[modrm
.reg
+ add
]);
14488 oappend (names16
[modrm
.reg
+ add
]);
14493 oappend (names32
[modrm
.reg
+ add
]);
14496 oappend (names64
[modrm
.reg
+ add
]);
14499 if (modrm
.reg
> 0x3)
14504 oappend (names_bnd
[modrm
.reg
]);
14514 oappend (names64
[modrm
.reg
+ add
]);
14517 if ((sizeflag
& DFLAG
)
14518 || (bytemode
!= v_mode
&& bytemode
!= movsxd_mode
))
14519 oappend (names32
[modrm
.reg
+ add
]);
14521 oappend (names16
[modrm
.reg
+ add
]);
14522 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14526 names
= (address_mode
== mode_64bit
14527 ? names64
: names32
);
14528 if (!(prefixes
& PREFIX_ADDR
))
14530 if (address_mode
== mode_16bit
)
14535 /* Remove "addr16/addr32". */
14536 all_prefixes
[last_addr_prefix
] = 0;
14537 names
= (address_mode
!= mode_32bit
14538 ? names32
: names16
);
14539 used_prefixes
|= PREFIX_ADDR
;
14541 oappend (names
[modrm
.reg
+ add
]);
14544 if (address_mode
== mode_64bit
)
14545 oappend (names64
[modrm
.reg
+ add
]);
14547 oappend (names32
[modrm
.reg
+ add
]);
14551 if ((modrm
.reg
+ add
) > 0x7)
14556 oappend (names_mask
[modrm
.reg
+ add
]);
14559 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14572 FETCH_DATA (the_info
, codep
+ 8);
14573 a
= *codep
++ & 0xff;
14574 a
|= (*codep
++ & 0xff) << 8;
14575 a
|= (*codep
++ & 0xff) << 16;
14576 a
|= (*codep
++ & 0xffu
) << 24;
14577 b
= *codep
++ & 0xff;
14578 b
|= (*codep
++ & 0xff) << 8;
14579 b
|= (*codep
++ & 0xff) << 16;
14580 b
|= (*codep
++ & 0xffu
) << 24;
14581 x
= a
+ ((bfd_vma
) b
<< 32);
14589 static bfd_signed_vma
14592 bfd_signed_vma x
= 0;
14594 FETCH_DATA (the_info
, codep
+ 4);
14595 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14596 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14597 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14598 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14602 static bfd_signed_vma
14605 bfd_signed_vma x
= 0;
14607 FETCH_DATA (the_info
, codep
+ 4);
14608 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14609 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14610 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14611 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14613 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14623 FETCH_DATA (the_info
, codep
+ 2);
14624 x
= *codep
++ & 0xff;
14625 x
|= (*codep
++ & 0xff) << 8;
14630 set_op (bfd_vma op
, int riprel
)
14632 op_index
[op_ad
] = op_ad
;
14633 if (address_mode
== mode_64bit
)
14635 op_address
[op_ad
] = op
;
14636 op_riprel
[op_ad
] = riprel
;
14640 /* Mask to get a 32-bit address. */
14641 op_address
[op_ad
] = op
& 0xffffffff;
14642 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14647 OP_REG (int code
, int sizeflag
)
14654 case es_reg
: case ss_reg
: case cs_reg
:
14655 case ds_reg
: case fs_reg
: case gs_reg
:
14656 oappend (names_seg
[code
- es_reg
]);
14668 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14669 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14670 s
= names16
[code
- ax_reg
+ add
];
14672 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14673 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14676 s
= names8rex
[code
- al_reg
+ add
];
14678 s
= names8
[code
- al_reg
];
14680 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14681 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14682 if (address_mode
== mode_64bit
14683 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14685 s
= names64
[code
- rAX_reg
+ add
];
14688 code
+= eAX_reg
- rAX_reg
;
14689 /* Fall through. */
14690 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14691 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14694 s
= names64
[code
- eAX_reg
+ add
];
14697 if (sizeflag
& DFLAG
)
14698 s
= names32
[code
- eAX_reg
+ add
];
14700 s
= names16
[code
- eAX_reg
+ add
];
14701 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14705 s
= INTERNAL_DISASSEMBLER_ERROR
;
14712 OP_IMREG (int code
, int sizeflag
)
14724 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14725 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14726 s
= names16
[code
- ax_reg
];
14728 case es_reg
: case ss_reg
: case cs_reg
:
14729 case ds_reg
: case fs_reg
: case gs_reg
:
14730 s
= names_seg
[code
- es_reg
];
14732 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14733 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14736 s
= names8rex
[code
- al_reg
];
14738 s
= names8
[code
- al_reg
];
14740 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14741 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14744 s
= names64
[code
- eAX_reg
];
14747 if (sizeflag
& DFLAG
)
14748 s
= names32
[code
- eAX_reg
];
14750 s
= names16
[code
- eAX_reg
];
14751 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14754 case z_mode_ax_reg
:
14755 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14759 if (!(rex
& REX_W
))
14760 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14763 s
= INTERNAL_DISASSEMBLER_ERROR
;
14770 OP_I (int bytemode
, int sizeflag
)
14773 bfd_signed_vma mask
= -1;
14778 FETCH_DATA (the_info
, codep
+ 1);
14788 if (sizeflag
& DFLAG
)
14798 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14814 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14819 scratchbuf
[0] = '$';
14820 print_operand_value (scratchbuf
+ 1, 1, op
);
14821 oappend_maybe_intel (scratchbuf
);
14822 scratchbuf
[0] = '\0';
14826 OP_I64 (int bytemode
, int sizeflag
)
14828 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14830 OP_I (bytemode
, sizeflag
);
14836 scratchbuf
[0] = '$';
14837 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14838 oappend_maybe_intel (scratchbuf
);
14839 scratchbuf
[0] = '\0';
14843 OP_sI (int bytemode
, int sizeflag
)
14851 FETCH_DATA (the_info
, codep
+ 1);
14853 if ((op
& 0x80) != 0)
14855 if (bytemode
== b_T_mode
)
14857 if (address_mode
!= mode_64bit
14858 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14860 /* The operand-size prefix is overridden by a REX prefix. */
14861 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14869 if (!(rex
& REX_W
))
14871 if (sizeflag
& DFLAG
)
14879 /* The operand-size prefix is overridden by a REX prefix. */
14880 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14886 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14890 scratchbuf
[0] = '$';
14891 print_operand_value (scratchbuf
+ 1, 1, op
);
14892 oappend_maybe_intel (scratchbuf
);
14896 OP_J (int bytemode
, int sizeflag
)
14900 bfd_vma segment
= 0;
14905 FETCH_DATA (the_info
, codep
+ 1);
14907 if ((disp
& 0x80) != 0)
14911 if (isa64
!= intel64
)
14914 if ((sizeflag
& DFLAG
)
14915 || (address_mode
== mode_64bit
14916 && ((isa64
== intel64
&& bytemode
!= dqw_mode
)
14917 || (rex
& REX_W
))))
14922 if ((disp
& 0x8000) != 0)
14924 /* In 16bit mode, address is wrapped around at 64k within
14925 the same segment. Otherwise, a data16 prefix on a jump
14926 instruction means that the pc is masked to 16 bits after
14927 the displacement is added! */
14929 if ((prefixes
& PREFIX_DATA
) == 0)
14930 segment
= ((start_pc
+ (codep
- start_codep
))
14931 & ~((bfd_vma
) 0xffff));
14933 if (address_mode
!= mode_64bit
14934 || (isa64
!= intel64
&& !(rex
& REX_W
)))
14935 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14938 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14941 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14943 print_operand_value (scratchbuf
, 1, disp
);
14944 oappend (scratchbuf
);
14948 OP_SEG (int bytemode
, int sizeflag
)
14950 if (bytemode
== w_mode
)
14951 oappend (names_seg
[modrm
.reg
]);
14953 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14957 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14961 if (sizeflag
& DFLAG
)
14971 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14973 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14975 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14976 oappend (scratchbuf
);
14980 OP_OFF (int bytemode
, int sizeflag
)
14984 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14985 intel_operand_size (bytemode
, sizeflag
);
14988 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14995 if (!active_seg_prefix
)
14997 oappend (names_seg
[ds_reg
- es_reg
]);
15001 print_operand_value (scratchbuf
, 1, off
);
15002 oappend (scratchbuf
);
15006 OP_OFF64 (int bytemode
, int sizeflag
)
15010 if (address_mode
!= mode_64bit
15011 || (prefixes
& PREFIX_ADDR
))
15013 OP_OFF (bytemode
, sizeflag
);
15017 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15018 intel_operand_size (bytemode
, sizeflag
);
15025 if (!active_seg_prefix
)
15027 oappend (names_seg
[ds_reg
- es_reg
]);
15031 print_operand_value (scratchbuf
, 1, off
);
15032 oappend (scratchbuf
);
15036 ptr_reg (int code
, int sizeflag
)
15040 *obufp
++ = open_char
;
15041 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15042 if (address_mode
== mode_64bit
)
15044 if (!(sizeflag
& AFLAG
))
15045 s
= names32
[code
- eAX_reg
];
15047 s
= names64
[code
- eAX_reg
];
15049 else if (sizeflag
& AFLAG
)
15050 s
= names32
[code
- eAX_reg
];
15052 s
= names16
[code
- eAX_reg
];
15054 *obufp
++ = close_char
;
15059 OP_ESreg (int code
, int sizeflag
)
15065 case 0x6d: /* insw/insl */
15066 intel_operand_size (z_mode
, sizeflag
);
15068 case 0xa5: /* movsw/movsl/movsq */
15069 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15070 case 0xab: /* stosw/stosl */
15071 case 0xaf: /* scasw/scasl */
15072 intel_operand_size (v_mode
, sizeflag
);
15075 intel_operand_size (b_mode
, sizeflag
);
15078 oappend_maybe_intel ("%es:");
15079 ptr_reg (code
, sizeflag
);
15083 OP_DSreg (int code
, int sizeflag
)
15089 case 0x6f: /* outsw/outsl */
15090 intel_operand_size (z_mode
, sizeflag
);
15092 case 0xa5: /* movsw/movsl/movsq */
15093 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15094 case 0xad: /* lodsw/lodsl/lodsq */
15095 intel_operand_size (v_mode
, sizeflag
);
15098 intel_operand_size (b_mode
, sizeflag
);
15101 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15102 default segment register DS is printed. */
15103 if (!active_seg_prefix
)
15104 active_seg_prefix
= PREFIX_DS
;
15106 ptr_reg (code
, sizeflag
);
15110 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15118 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15120 all_prefixes
[last_lock_prefix
] = 0;
15121 used_prefixes
|= PREFIX_LOCK
;
15126 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15127 oappend_maybe_intel (scratchbuf
);
15131 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15140 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15142 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15143 oappend (scratchbuf
);
15147 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15149 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15150 oappend_maybe_intel (scratchbuf
);
15154 OP_R (int bytemode
, int sizeflag
)
15156 /* Skip mod/rm byte. */
15159 OP_E_register (bytemode
, sizeflag
);
15163 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15165 int reg
= modrm
.reg
;
15166 const char **names
;
15168 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15169 if (prefixes
& PREFIX_DATA
)
15178 oappend (names
[reg
]);
15182 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15184 int reg
= modrm
.reg
;
15185 const char **names
;
15197 && bytemode
!= xmm_mode
15198 && bytemode
!= xmmq_mode
15199 && bytemode
!= evex_half_bcst_xmmq_mode
15200 && bytemode
!= ymm_mode
15201 && bytemode
!= scalar_mode
)
15203 switch (vex
.length
)
15210 || (bytemode
!= vex_vsib_q_w_dq_mode
15211 && bytemode
!= vex_vsib_q_w_d_mode
))
15223 else if (bytemode
== xmmq_mode
15224 || bytemode
== evex_half_bcst_xmmq_mode
)
15226 switch (vex
.length
)
15239 else if (bytemode
== ymm_mode
)
15243 oappend (names
[reg
]);
15247 OP_EM (int bytemode
, int sizeflag
)
15250 const char **names
;
15252 if (modrm
.mod
!= 3)
15255 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15257 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15258 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15260 OP_E (bytemode
, sizeflag
);
15264 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15267 /* Skip mod/rm byte. */
15270 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15272 if (prefixes
& PREFIX_DATA
)
15281 oappend (names
[reg
]);
15284 /* cvt* are the only instructions in sse2 which have
15285 both SSE and MMX operands and also have 0x66 prefix
15286 in their opcode. 0x66 was originally used to differentiate
15287 between SSE and MMX instruction(operands). So we have to handle the
15288 cvt* separately using OP_EMC and OP_MXC */
15290 OP_EMC (int bytemode
, int sizeflag
)
15292 if (modrm
.mod
!= 3)
15294 if (intel_syntax
&& bytemode
== v_mode
)
15296 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15297 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15299 OP_E (bytemode
, sizeflag
);
15303 /* Skip mod/rm byte. */
15306 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15307 oappend (names_mm
[modrm
.rm
]);
15311 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15313 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15314 oappend (names_mm
[modrm
.reg
]);
15318 OP_EX (int bytemode
, int sizeflag
)
15321 const char **names
;
15323 /* Skip mod/rm byte. */
15327 if (modrm
.mod
!= 3)
15329 OP_E_memory (bytemode
, sizeflag
);
15344 if ((sizeflag
& SUFFIX_ALWAYS
)
15345 && (bytemode
== x_swap_mode
15346 || bytemode
== d_swap_mode
15347 || bytemode
== d_scalar_swap_mode
15348 || bytemode
== q_swap_mode
15349 || bytemode
== q_scalar_swap_mode
))
15353 && bytemode
!= xmm_mode
15354 && bytemode
!= xmmdw_mode
15355 && bytemode
!= xmmqd_mode
15356 && bytemode
!= xmm_mb_mode
15357 && bytemode
!= xmm_mw_mode
15358 && bytemode
!= xmm_md_mode
15359 && bytemode
!= xmm_mq_mode
15360 && bytemode
!= xmm_mdq_mode
15361 && bytemode
!= xmmq_mode
15362 && bytemode
!= evex_half_bcst_xmmq_mode
15363 && bytemode
!= ymm_mode
15364 && bytemode
!= d_scalar_mode
15365 && bytemode
!= d_scalar_swap_mode
15366 && bytemode
!= q_scalar_mode
15367 && bytemode
!= q_scalar_swap_mode
15368 && bytemode
!= vex_scalar_w_dq_mode
)
15370 switch (vex
.length
)
15385 else if (bytemode
== xmmq_mode
15386 || bytemode
== evex_half_bcst_xmmq_mode
)
15388 switch (vex
.length
)
15401 else if (bytemode
== ymm_mode
)
15405 oappend (names
[reg
]);
15409 OP_MS (int bytemode
, int sizeflag
)
15411 if (modrm
.mod
== 3)
15412 OP_EM (bytemode
, sizeflag
);
15418 OP_XS (int bytemode
, int sizeflag
)
15420 if (modrm
.mod
== 3)
15421 OP_EX (bytemode
, sizeflag
);
15427 OP_M (int bytemode
, int sizeflag
)
15429 if (modrm
.mod
== 3)
15430 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15433 OP_E (bytemode
, sizeflag
);
15437 OP_0f07 (int bytemode
, int sizeflag
)
15439 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15442 OP_E (bytemode
, sizeflag
);
15445 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15446 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15449 NOP_Fixup1 (int bytemode
, int sizeflag
)
15451 if ((prefixes
& PREFIX_DATA
) != 0
15454 && address_mode
== mode_64bit
))
15455 OP_REG (bytemode
, sizeflag
);
15457 strcpy (obuf
, "nop");
15461 NOP_Fixup2 (int bytemode
, int sizeflag
)
15463 if ((prefixes
& PREFIX_DATA
) != 0
15466 && address_mode
== mode_64bit
))
15467 OP_IMREG (bytemode
, sizeflag
);
15470 static const char *const Suffix3DNow
[] = {
15471 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15472 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15473 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15474 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15475 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15476 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15477 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15478 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15479 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15480 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15481 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15482 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15483 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15484 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15485 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15486 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15487 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15488 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15489 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15490 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15491 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15492 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15493 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15494 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15495 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15496 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15497 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15498 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15499 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15500 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15501 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15502 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15503 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15504 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15505 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15506 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15507 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15508 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15509 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15510 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15511 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15512 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15513 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15514 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15515 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15516 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15517 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15518 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15519 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15520 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15521 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15522 /* CC */ NULL
, NULL
, NULL
, NULL
,
15523 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15524 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15525 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15526 /* DC */ NULL
, NULL
, NULL
, NULL
,
15527 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15528 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15529 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15530 /* EC */ NULL
, NULL
, NULL
, NULL
,
15531 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15532 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15533 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15534 /* FC */ NULL
, NULL
, NULL
, NULL
,
15538 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15540 const char *mnemonic
;
15542 FETCH_DATA (the_info
, codep
+ 1);
15543 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15544 place where an 8-bit immediate would normally go. ie. the last
15545 byte of the instruction. */
15546 obufp
= mnemonicendp
;
15547 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15549 oappend (mnemonic
);
15552 /* Since a variable sized modrm/sib chunk is between the start
15553 of the opcode (0x0f0f) and the opcode suffix, we need to do
15554 all the modrm processing first, and don't know until now that
15555 we have a bad opcode. This necessitates some cleaning up. */
15556 op_out
[0][0] = '\0';
15557 op_out
[1][0] = '\0';
15560 mnemonicendp
= obufp
;
15563 static struct op simd_cmp_op
[] =
15565 { STRING_COMMA_LEN ("eq") },
15566 { STRING_COMMA_LEN ("lt") },
15567 { STRING_COMMA_LEN ("le") },
15568 { STRING_COMMA_LEN ("unord") },
15569 { STRING_COMMA_LEN ("neq") },
15570 { STRING_COMMA_LEN ("nlt") },
15571 { STRING_COMMA_LEN ("nle") },
15572 { STRING_COMMA_LEN ("ord") }
15576 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15578 unsigned int cmp_type
;
15580 FETCH_DATA (the_info
, codep
+ 1);
15581 cmp_type
= *codep
++ & 0xff;
15582 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15585 char *p
= mnemonicendp
- 2;
15589 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15590 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15594 /* We have a reserved extension byte. Output it directly. */
15595 scratchbuf
[0] = '$';
15596 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15597 oappend_maybe_intel (scratchbuf
);
15598 scratchbuf
[0] = '\0';
15603 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15605 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15608 strcpy (op_out
[0], names32
[0]);
15609 strcpy (op_out
[1], names32
[1]);
15610 if (bytemode
== eBX_reg
)
15611 strcpy (op_out
[2], names32
[3]);
15612 two_source_ops
= 1;
15614 /* Skip mod/rm byte. */
15620 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15621 int sizeflag ATTRIBUTE_UNUSED
)
15623 /* monitor %{e,r,}ax,%ecx,%edx" */
15626 const char **names
= (address_mode
== mode_64bit
15627 ? names64
: names32
);
15629 if (prefixes
& PREFIX_ADDR
)
15631 /* Remove "addr16/addr32". */
15632 all_prefixes
[last_addr_prefix
] = 0;
15633 names
= (address_mode
!= mode_32bit
15634 ? names32
: names16
);
15635 used_prefixes
|= PREFIX_ADDR
;
15637 else if (address_mode
== mode_16bit
)
15639 strcpy (op_out
[0], names
[0]);
15640 strcpy (op_out
[1], names32
[1]);
15641 strcpy (op_out
[2], names32
[2]);
15642 two_source_ops
= 1;
15644 /* Skip mod/rm byte. */
15652 /* Throw away prefixes and 1st. opcode byte. */
15653 codep
= insn_codep
+ 1;
15658 REP_Fixup (int bytemode
, int sizeflag
)
15660 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15662 if (prefixes
& PREFIX_REPZ
)
15663 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15670 OP_IMREG (bytemode
, sizeflag
);
15673 OP_ESreg (bytemode
, sizeflag
);
15676 OP_DSreg (bytemode
, sizeflag
);
15685 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15687 if ( isa64
!= amd64
)
15692 mnemonicendp
= obufp
;
15696 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15700 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15702 if (prefixes
& PREFIX_REPNZ
)
15703 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15706 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15710 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15711 int sizeflag ATTRIBUTE_UNUSED
)
15713 if (active_seg_prefix
== PREFIX_DS
15714 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15716 /* NOTRACK prefix is only valid on indirect branch instructions.
15717 NB: DATA prefix is unsupported for Intel64. */
15718 active_seg_prefix
= 0;
15719 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15723 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15724 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15728 HLE_Fixup1 (int bytemode
, int sizeflag
)
15731 && (prefixes
& PREFIX_LOCK
) != 0)
15733 if (prefixes
& PREFIX_REPZ
)
15734 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15735 if (prefixes
& PREFIX_REPNZ
)
15736 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15739 OP_E (bytemode
, sizeflag
);
15742 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15743 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15747 HLE_Fixup2 (int bytemode
, int sizeflag
)
15749 if (modrm
.mod
!= 3)
15751 if (prefixes
& PREFIX_REPZ
)
15752 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15753 if (prefixes
& PREFIX_REPNZ
)
15754 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15757 OP_E (bytemode
, sizeflag
);
15760 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15761 "xrelease" for memory operand. No check for LOCK prefix. */
15764 HLE_Fixup3 (int bytemode
, int sizeflag
)
15767 && last_repz_prefix
> last_repnz_prefix
15768 && (prefixes
& PREFIX_REPZ
) != 0)
15769 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15771 OP_E (bytemode
, sizeflag
);
15775 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15780 /* Change cmpxchg8b to cmpxchg16b. */
15781 char *p
= mnemonicendp
- 2;
15782 mnemonicendp
= stpcpy (p
, "16b");
15785 else if ((prefixes
& PREFIX_LOCK
) != 0)
15787 if (prefixes
& PREFIX_REPZ
)
15788 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15789 if (prefixes
& PREFIX_REPNZ
)
15790 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15793 OP_M (bytemode
, sizeflag
);
15797 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15799 const char **names
;
15803 switch (vex
.length
)
15817 oappend (names
[reg
]);
15821 CRC32_Fixup (int bytemode
, int sizeflag
)
15823 /* Add proper suffix to "crc32". */
15824 char *p
= mnemonicendp
;
15843 if (sizeflag
& DFLAG
)
15847 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15851 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15858 if (modrm
.mod
== 3)
15862 /* Skip mod/rm byte. */
15867 add
= (rex
& REX_B
) ? 8 : 0;
15868 if (bytemode
== b_mode
)
15872 oappend (names8rex
[modrm
.rm
+ add
]);
15874 oappend (names8
[modrm
.rm
+ add
]);
15880 oappend (names64
[modrm
.rm
+ add
]);
15881 else if ((prefixes
& PREFIX_DATA
))
15882 oappend (names16
[modrm
.rm
+ add
]);
15884 oappend (names32
[modrm
.rm
+ add
]);
15888 OP_E (bytemode
, sizeflag
);
15892 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15894 /* Add proper suffix to "fxsave" and "fxrstor". */
15898 char *p
= mnemonicendp
;
15904 OP_M (bytemode
, sizeflag
);
15908 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15910 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15913 char *p
= mnemonicendp
;
15918 else if (sizeflag
& SUFFIX_ALWAYS
)
15925 OP_EX (bytemode
, sizeflag
);
15928 /* Display the destination register operand for instructions with
15932 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15935 const char **names
;
15943 reg
= vex
.register_specifier
;
15944 vex
.register_specifier
= 0;
15945 if (address_mode
!= mode_64bit
)
15947 else if (vex
.evex
&& !vex
.v
)
15950 if (bytemode
== vex_scalar_mode
)
15952 oappend (names_xmm
[reg
]);
15956 switch (vex
.length
)
15963 case vex_vsib_q_w_dq_mode
:
15964 case vex_vsib_q_w_d_mode
:
15980 names
= names_mask
;
15994 case vex_vsib_q_w_dq_mode
:
15995 case vex_vsib_q_w_d_mode
:
15996 names
= vex
.w
? names_ymm
: names_xmm
;
16005 names
= names_mask
;
16008 /* See PR binutils/20893 for a reproducer. */
16020 oappend (names
[reg
]);
16023 /* Get the VEX immediate byte without moving codep. */
16025 static unsigned char
16026 get_vex_imm8 (int sizeflag
, int opnum
)
16028 int bytes_before_imm
= 0;
16030 if (modrm
.mod
!= 3)
16032 /* There are SIB/displacement bytes. */
16033 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16035 /* 32/64 bit address mode */
16036 int base
= modrm
.rm
;
16038 /* Check SIB byte. */
16041 FETCH_DATA (the_info
, codep
+ 1);
16043 /* When decoding the third source, don't increase
16044 bytes_before_imm as this has already been incremented
16045 by one in OP_E_memory while decoding the second
16048 bytes_before_imm
++;
16051 /* Don't increase bytes_before_imm when decoding the third source,
16052 it has already been incremented by OP_E_memory while decoding
16053 the second source operand. */
16059 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16060 SIB == 5, there is a 4 byte displacement. */
16062 /* No displacement. */
16064 /* Fall through. */
16066 /* 4 byte displacement. */
16067 bytes_before_imm
+= 4;
16070 /* 1 byte displacement. */
16071 bytes_before_imm
++;
16078 /* 16 bit address mode */
16079 /* Don't increase bytes_before_imm when decoding the third source,
16080 it has already been incremented by OP_E_memory while decoding
16081 the second source operand. */
16087 /* When modrm.rm == 6, there is a 2 byte displacement. */
16089 /* No displacement. */
16091 /* Fall through. */
16093 /* 2 byte displacement. */
16094 bytes_before_imm
+= 2;
16097 /* 1 byte displacement: when decoding the third source,
16098 don't increase bytes_before_imm as this has already
16099 been incremented by one in OP_E_memory while decoding
16100 the second source operand. */
16102 bytes_before_imm
++;
16110 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16111 return codep
[bytes_before_imm
];
16115 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16117 const char **names
;
16119 if (reg
== -1 && modrm
.mod
!= 3)
16121 OP_E_memory (bytemode
, sizeflag
);
16133 if (address_mode
!= mode_64bit
)
16137 switch (vex
.length
)
16148 oappend (names
[reg
]);
16152 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16155 static unsigned char vex_imm8
;
16157 if (vex_w_done
== 0)
16161 /* Skip mod/rm byte. */
16165 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16168 reg
= vex_imm8
>> 4;
16170 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16172 else if (vex_w_done
== 1)
16177 reg
= vex_imm8
>> 4;
16179 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16183 /* Output the imm8 directly. */
16184 scratchbuf
[0] = '$';
16185 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16186 oappend_maybe_intel (scratchbuf
);
16187 scratchbuf
[0] = '\0';
16193 OP_Vex_2src (int bytemode
, int sizeflag
)
16195 if (modrm
.mod
== 3)
16197 int reg
= modrm
.rm
;
16201 oappend (names_xmm
[reg
]);
16206 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16208 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16209 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16211 OP_E (bytemode
, sizeflag
);
16216 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16218 if (modrm
.mod
== 3)
16220 /* Skip mod/rm byte. */
16227 unsigned int reg
= vex
.register_specifier
;
16228 vex
.register_specifier
= 0;
16230 if (address_mode
!= mode_64bit
)
16232 oappend (names_xmm
[reg
]);
16235 OP_Vex_2src (bytemode
, sizeflag
);
16239 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16242 OP_Vex_2src (bytemode
, sizeflag
);
16245 unsigned int reg
= vex
.register_specifier
;
16246 vex
.register_specifier
= 0;
16248 if (address_mode
!= mode_64bit
)
16250 oappend (names_xmm
[reg
]);
16255 OP_EX_VexW (int bytemode
, int sizeflag
)
16261 /* Skip mod/rm byte. */
16266 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16271 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16274 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16282 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16285 const char **names
;
16287 FETCH_DATA (the_info
, codep
+ 1);
16290 if (bytemode
!= x_mode
)
16294 if (address_mode
!= mode_64bit
)
16297 switch (vex
.length
)
16308 oappend (names
[reg
]);
16312 OP_XMM_VexW (int bytemode
, int sizeflag
)
16314 /* Turn off the REX.W bit since it is used for swapping operands
16317 OP_XMM (bytemode
, sizeflag
);
16321 OP_EX_Vex (int bytemode
, int sizeflag
)
16323 if (modrm
.mod
!= 3)
16325 OP_EX (bytemode
, sizeflag
);
16329 OP_XMM_Vex (int bytemode
, int sizeflag
)
16331 if (modrm
.mod
!= 3)
16333 OP_XMM (bytemode
, sizeflag
);
16336 static struct op vex_cmp_op
[] =
16338 { STRING_COMMA_LEN ("eq") },
16339 { STRING_COMMA_LEN ("lt") },
16340 { STRING_COMMA_LEN ("le") },
16341 { STRING_COMMA_LEN ("unord") },
16342 { STRING_COMMA_LEN ("neq") },
16343 { STRING_COMMA_LEN ("nlt") },
16344 { STRING_COMMA_LEN ("nle") },
16345 { STRING_COMMA_LEN ("ord") },
16346 { STRING_COMMA_LEN ("eq_uq") },
16347 { STRING_COMMA_LEN ("nge") },
16348 { STRING_COMMA_LEN ("ngt") },
16349 { STRING_COMMA_LEN ("false") },
16350 { STRING_COMMA_LEN ("neq_oq") },
16351 { STRING_COMMA_LEN ("ge") },
16352 { STRING_COMMA_LEN ("gt") },
16353 { STRING_COMMA_LEN ("true") },
16354 { STRING_COMMA_LEN ("eq_os") },
16355 { STRING_COMMA_LEN ("lt_oq") },
16356 { STRING_COMMA_LEN ("le_oq") },
16357 { STRING_COMMA_LEN ("unord_s") },
16358 { STRING_COMMA_LEN ("neq_us") },
16359 { STRING_COMMA_LEN ("nlt_uq") },
16360 { STRING_COMMA_LEN ("nle_uq") },
16361 { STRING_COMMA_LEN ("ord_s") },
16362 { STRING_COMMA_LEN ("eq_us") },
16363 { STRING_COMMA_LEN ("nge_uq") },
16364 { STRING_COMMA_LEN ("ngt_uq") },
16365 { STRING_COMMA_LEN ("false_os") },
16366 { STRING_COMMA_LEN ("neq_os") },
16367 { STRING_COMMA_LEN ("ge_oq") },
16368 { STRING_COMMA_LEN ("gt_oq") },
16369 { STRING_COMMA_LEN ("true_us") },
16373 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16375 unsigned int cmp_type
;
16377 FETCH_DATA (the_info
, codep
+ 1);
16378 cmp_type
= *codep
++ & 0xff;
16379 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16382 char *p
= mnemonicendp
- 2;
16386 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16387 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16391 /* We have a reserved extension byte. Output it directly. */
16392 scratchbuf
[0] = '$';
16393 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16394 oappend_maybe_intel (scratchbuf
);
16395 scratchbuf
[0] = '\0';
16400 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16401 int sizeflag ATTRIBUTE_UNUSED
)
16403 unsigned int cmp_type
;
16408 FETCH_DATA (the_info
, codep
+ 1);
16409 cmp_type
= *codep
++ & 0xff;
16410 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16411 If it's the case, print suffix, otherwise - print the immediate. */
16412 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16417 char *p
= mnemonicendp
- 2;
16419 /* vpcmp* can have both one- and two-lettered suffix. */
16433 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16434 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16438 /* We have a reserved extension byte. Output it directly. */
16439 scratchbuf
[0] = '$';
16440 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16441 oappend_maybe_intel (scratchbuf
);
16442 scratchbuf
[0] = '\0';
16446 static const struct op xop_cmp_op
[] =
16448 { STRING_COMMA_LEN ("lt") },
16449 { STRING_COMMA_LEN ("le") },
16450 { STRING_COMMA_LEN ("gt") },
16451 { STRING_COMMA_LEN ("ge") },
16452 { STRING_COMMA_LEN ("eq") },
16453 { STRING_COMMA_LEN ("neq") },
16454 { STRING_COMMA_LEN ("false") },
16455 { STRING_COMMA_LEN ("true") }
16459 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16460 int sizeflag ATTRIBUTE_UNUSED
)
16462 unsigned int cmp_type
;
16464 FETCH_DATA (the_info
, codep
+ 1);
16465 cmp_type
= *codep
++ & 0xff;
16466 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16469 char *p
= mnemonicendp
- 2;
16471 /* vpcom* can have both one- and two-lettered suffix. */
16485 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16486 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16490 /* We have a reserved extension byte. Output it directly. */
16491 scratchbuf
[0] = '$';
16492 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16493 oappend_maybe_intel (scratchbuf
);
16494 scratchbuf
[0] = '\0';
16498 static const struct op pclmul_op
[] =
16500 { STRING_COMMA_LEN ("lql") },
16501 { STRING_COMMA_LEN ("hql") },
16502 { STRING_COMMA_LEN ("lqh") },
16503 { STRING_COMMA_LEN ("hqh") }
16507 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16508 int sizeflag ATTRIBUTE_UNUSED
)
16510 unsigned int pclmul_type
;
16512 FETCH_DATA (the_info
, codep
+ 1);
16513 pclmul_type
= *codep
++ & 0xff;
16514 switch (pclmul_type
)
16525 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16528 char *p
= mnemonicendp
- 3;
16533 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16534 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16538 /* We have a reserved extension byte. Output it directly. */
16539 scratchbuf
[0] = '$';
16540 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16541 oappend_maybe_intel (scratchbuf
);
16542 scratchbuf
[0] = '\0';
16547 MOVBE_Fixup (int bytemode
, int sizeflag
)
16549 /* Add proper suffix to "movbe". */
16550 char *p
= mnemonicendp
;
16559 if (sizeflag
& SUFFIX_ALWAYS
)
16565 if (sizeflag
& DFLAG
)
16569 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16574 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16581 OP_M (bytemode
, sizeflag
);
16585 MOVSXD_Fixup (int bytemode
, int sizeflag
)
16587 /* Add proper suffix to "movsxd". */
16588 char *p
= mnemonicendp
;
16613 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16620 OP_E (bytemode
, sizeflag
);
16624 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16627 const char **names
;
16629 /* Skip mod/rm byte. */
16643 oappend (names
[reg
]);
16647 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16649 const char **names
;
16650 unsigned int reg
= vex
.register_specifier
;
16651 vex
.register_specifier
= 0;
16658 if (address_mode
!= mode_64bit
)
16660 oappend (names
[reg
]);
16664 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16667 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16671 if ((rex
& REX_R
) != 0 || !vex
.r
)
16677 oappend (names_mask
[modrm
.reg
]);
16681 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16684 || (bytemode
!= evex_rounding_mode
16685 && bytemode
!= evex_rounding_64_mode
16686 && bytemode
!= evex_sae_mode
))
16688 if (modrm
.mod
== 3 && vex
.b
)
16691 case evex_rounding_64_mode
:
16692 if (address_mode
!= mode_64bit
)
16697 /* Fall through. */
16698 case evex_rounding_mode
:
16699 oappend (names_rounding
[vex
.ll
]);
16701 case evex_sae_mode
: