1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma
, disassemble_info
*);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma
);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma
);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma
get64 (void);
60 static bfd_signed_vma
get32 (void);
61 static bfd_signed_vma
get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma
, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void CMPXCHG8B_Fixup (int, int);
112 static void XMM_Fixup (int, int);
113 static void CRC32_Fixup (int, int);
114 static void FXSAVE_Fixup (int, int);
115 static void OP_LWPCB_E (int, int);
116 static void OP_LWP_E (int, int);
117 static void OP_Vex_2src_1 (int, int);
118 static void OP_Vex_2src_2 (int, int);
120 static void MOVBE_Fixup (int, int);
123 /* Points to first byte not fetched. */
124 bfd_byte
*max_fetched
;
125 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
138 enum address_mode address_mode
;
140 /* Flags for the prefixes for the current instruction. See below. */
143 /* REX prefix the current instruction. See below. */
145 /* Bits of REX we've already used. */
147 /* REX bits in original REX prefix ignored. */
148 static int rex_ignored
;
149 /* Mark parts used in the REX prefix. When we are testing for
150 empty prefix (for 8bit register REX extension), just mask it
151 out. Otherwise test for REX bit is excuse for existence of REX
152 only in case value is nonzero. */
153 #define USED_REX(value) \
158 rex_used |= (value) | REX_OPCODE; \
161 rex_used |= REX_OPCODE; \
164 /* Flags for prefixes which we somehow handled when printing the
165 current instruction. */
166 static int used_prefixes
;
168 /* Flags stored in PREFIXES. */
169 #define PREFIX_REPZ 1
170 #define PREFIX_REPNZ 2
171 #define PREFIX_LOCK 4
173 #define PREFIX_SS 0x10
174 #define PREFIX_DS 0x20
175 #define PREFIX_ES 0x40
176 #define PREFIX_FS 0x80
177 #define PREFIX_GS 0x100
178 #define PREFIX_DATA 0x200
179 #define PREFIX_ADDR 0x400
180 #define PREFIX_FWAIT 0x800
182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
183 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
185 #define FETCH_DATA(info, addr) \
186 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
187 ? 1 : fetch_data ((info), (addr)))
190 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
193 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
194 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
196 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
197 status
= (*info
->read_memory_func
) (start
,
199 addr
- priv
->max_fetched
,
205 /* If we did manage to read at least one byte, then
206 print_insn_i386 will do something sensible. Otherwise, print
207 an error. We do that here because this is where we know
209 if (priv
->max_fetched
== priv
->the_buffer
)
210 (*info
->memory_error_func
) (status
, start
, info
);
211 longjmp (priv
->bailout
, 1);
214 priv
->max_fetched
= addr
;
218 #define XX { NULL, 0 }
219 #define Bad_Opcode NULL, { { NULL, 0 } }
221 #define Eb { OP_E, b_mode }
222 #define EbS { OP_E, b_swap_mode }
223 #define Ev { OP_E, v_mode }
224 #define EvS { OP_E, v_swap_mode }
225 #define Ed { OP_E, d_mode }
226 #define Edq { OP_E, dq_mode }
227 #define Edqw { OP_E, dqw_mode }
228 #define Edqb { OP_E, dqb_mode }
229 #define Edqd { OP_E, dqd_mode }
230 #define Eq { OP_E, q_mode }
231 #define indirEv { OP_indirE, stack_v_mode }
232 #define indirEp { OP_indirE, f_mode }
233 #define stackEv { OP_E, stack_v_mode }
234 #define Em { OP_E, m_mode }
235 #define Ew { OP_E, w_mode }
236 #define M { OP_M, 0 } /* lea, lgdt, etc. */
237 #define Ma { OP_M, a_mode }
238 #define Mb { OP_M, b_mode }
239 #define Md { OP_M, d_mode }
240 #define Mo { OP_M, o_mode }
241 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
242 #define Mq { OP_M, q_mode }
243 #define Mx { OP_M, x_mode }
244 #define Mxmm { OP_M, xmm_mode }
245 #define Gb { OP_G, b_mode }
246 #define Gv { OP_G, v_mode }
247 #define Gd { OP_G, d_mode }
248 #define Gdq { OP_G, dq_mode }
249 #define Gm { OP_G, m_mode }
250 #define Gw { OP_G, w_mode }
251 #define Rd { OP_R, d_mode }
252 #define Rm { OP_R, m_mode }
253 #define Ib { OP_I, b_mode }
254 #define sIb { OP_sI, b_mode } /* sign extened byte */
255 #define Iv { OP_I, v_mode }
256 #define Iq { OP_I, q_mode }
257 #define Iv64 { OP_I64, v_mode }
258 #define Iw { OP_I, w_mode }
259 #define I1 { OP_I, const_1_mode }
260 #define Jb { OP_J, b_mode }
261 #define Jv { OP_J, v_mode }
262 #define Cm { OP_C, m_mode }
263 #define Dm { OP_D, m_mode }
264 #define Td { OP_T, d_mode }
265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
267 #define RMeAX { OP_REG, eAX_reg }
268 #define RMeBX { OP_REG, eBX_reg }
269 #define RMeCX { OP_REG, eCX_reg }
270 #define RMeDX { OP_REG, eDX_reg }
271 #define RMeSP { OP_REG, eSP_reg }
272 #define RMeBP { OP_REG, eBP_reg }
273 #define RMeSI { OP_REG, eSI_reg }
274 #define RMeDI { OP_REG, eDI_reg }
275 #define RMrAX { OP_REG, rAX_reg }
276 #define RMrBX { OP_REG, rBX_reg }
277 #define RMrCX { OP_REG, rCX_reg }
278 #define RMrDX { OP_REG, rDX_reg }
279 #define RMrSP { OP_REG, rSP_reg }
280 #define RMrBP { OP_REG, rBP_reg }
281 #define RMrSI { OP_REG, rSI_reg }
282 #define RMrDI { OP_REG, rDI_reg }
283 #define RMAL { OP_REG, al_reg }
284 #define RMAL { OP_REG, al_reg }
285 #define RMCL { OP_REG, cl_reg }
286 #define RMDL { OP_REG, dl_reg }
287 #define RMBL { OP_REG, bl_reg }
288 #define RMAH { OP_REG, ah_reg }
289 #define RMCH { OP_REG, ch_reg }
290 #define RMDH { OP_REG, dh_reg }
291 #define RMBH { OP_REG, bh_reg }
292 #define RMAX { OP_REG, ax_reg }
293 #define RMDX { OP_REG, dx_reg }
295 #define eAX { OP_IMREG, eAX_reg }
296 #define eBX { OP_IMREG, eBX_reg }
297 #define eCX { OP_IMREG, eCX_reg }
298 #define eDX { OP_IMREG, eDX_reg }
299 #define eSP { OP_IMREG, eSP_reg }
300 #define eBP { OP_IMREG, eBP_reg }
301 #define eSI { OP_IMREG, eSI_reg }
302 #define eDI { OP_IMREG, eDI_reg }
303 #define AL { OP_IMREG, al_reg }
304 #define CL { OP_IMREG, cl_reg }
305 #define DL { OP_IMREG, dl_reg }
306 #define BL { OP_IMREG, bl_reg }
307 #define AH { OP_IMREG, ah_reg }
308 #define CH { OP_IMREG, ch_reg }
309 #define DH { OP_IMREG, dh_reg }
310 #define BH { OP_IMREG, bh_reg }
311 #define AX { OP_IMREG, ax_reg }
312 #define DX { OP_IMREG, dx_reg }
313 #define zAX { OP_IMREG, z_mode_ax_reg }
314 #define indirDX { OP_IMREG, indir_dx_reg }
316 #define Sw { OP_SEG, w_mode }
317 #define Sv { OP_SEG, v_mode }
318 #define Ap { OP_DIR, 0 }
319 #define Ob { OP_OFF64, b_mode }
320 #define Ov { OP_OFF64, v_mode }
321 #define Xb { OP_DSreg, eSI_reg }
322 #define Xv { OP_DSreg, eSI_reg }
323 #define Xz { OP_DSreg, eSI_reg }
324 #define Yb { OP_ESreg, eDI_reg }
325 #define Yv { OP_ESreg, eDI_reg }
326 #define DSBX { OP_DSreg, eBX_reg }
328 #define es { OP_REG, es_reg }
329 #define ss { OP_REG, ss_reg }
330 #define cs { OP_REG, cs_reg }
331 #define ds { OP_REG, ds_reg }
332 #define fs { OP_REG, fs_reg }
333 #define gs { OP_REG, gs_reg }
335 #define MX { OP_MMX, 0 }
336 #define XM { OP_XMM, 0 }
337 #define XMScalar { OP_XMM, scalar_mode }
338 #define XMM { OP_XMM, xmm_mode }
339 #define EM { OP_EM, v_mode }
340 #define EMS { OP_EM, v_swap_mode }
341 #define EMd { OP_EM, d_mode }
342 #define EMx { OP_EM, x_mode }
343 #define EXw { OP_EX, w_mode }
344 #define EXd { OP_EX, d_mode }
345 #define EXdScalar { OP_EX, d_scalar_mode }
346 #define EXdS { OP_EX, d_swap_mode }
347 #define EXq { OP_EX, q_mode }
348 #define EXqScalar { OP_EX, q_scalar_mode }
349 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
350 #define EXqS { OP_EX, q_swap_mode }
351 #define EXx { OP_EX, x_mode }
352 #define EXxS { OP_EX, x_swap_mode }
353 #define EXxmm { OP_EX, xmm_mode }
354 #define EXxmmq { OP_EX, xmmq_mode }
355 #define EXymmq { OP_EX, ymmq_mode }
356 #define EXVexWdq { OP_EX, vex_w_dq_mode }
357 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
358 #define MS { OP_MS, v_mode }
359 #define XS { OP_XS, v_mode }
360 #define EMCq { OP_EMC, q_mode }
361 #define MXC { OP_MXC, 0 }
362 #define OPSUF { OP_3DNowSuffix, 0 }
363 #define CMP { CMP_Fixup, 0 }
364 #define XMM0 { XMM_Fixup, 0 }
365 #define FXSAVE { FXSAVE_Fixup, 0 }
366 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
367 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
369 #define Vex { OP_VEX, vex_mode }
370 #define VexScalar { OP_VEX, vex_scalar_mode }
371 #define Vex128 { OP_VEX, vex128_mode }
372 #define Vex256 { OP_VEX, vex256_mode }
373 #define VexI4 { VEXI4_Fixup, 0}
374 #define EXdVex { OP_EX_Vex, d_mode }
375 #define EXdVexS { OP_EX_Vex, d_swap_mode }
376 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
377 #define EXqVex { OP_EX_Vex, q_mode }
378 #define EXqVexS { OP_EX_Vex, q_swap_mode }
379 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
380 #define EXVexW { OP_EX_VexW, x_mode }
381 #define EXdVexW { OP_EX_VexW, d_mode }
382 #define EXqVexW { OP_EX_VexW, q_mode }
383 #define EXVexImmW { OP_EX_VexImmW, x_mode }
384 #define XMVex { OP_XMM_Vex, 0 }
385 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
386 #define XMVexW { OP_XMM_VexW, 0 }
387 #define XMVexI4 { OP_REG_VexI4, x_mode }
388 #define PCLMUL { PCLMUL_Fixup, 0 }
389 #define VZERO { VZERO_Fixup, 0 }
390 #define VCMP { VCMP_Fixup, 0 }
392 /* Used handle "rep" prefix for string instructions. */
393 #define Xbr { REP_Fixup, eSI_reg }
394 #define Xvr { REP_Fixup, eSI_reg }
395 #define Ybr { REP_Fixup, eDI_reg }
396 #define Yvr { REP_Fixup, eDI_reg }
397 #define Yzr { REP_Fixup, eDI_reg }
398 #define indirDXr { REP_Fixup, indir_dx_reg }
399 #define ALr { REP_Fixup, al_reg }
400 #define eAXr { REP_Fixup, eAX_reg }
402 #define cond_jump_flag { NULL, cond_jump_mode }
403 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
405 /* bits in sizeflag */
406 #define SUFFIX_ALWAYS 4
414 /* byte operand with operand swapped */
416 /* operand size depends on prefixes */
418 /* operand size depends on prefixes with operand swapped */
422 /* double word operand */
424 /* double word operand with operand swapped */
426 /* quad word operand */
428 /* quad word operand with operand swapped */
430 /* ten-byte operand */
432 /* 16-byte XMM or 32-byte YMM operand */
434 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
436 /* 16-byte XMM operand */
438 /* 16-byte XMM or quad word operand */
440 /* 32-byte YMM or quad word operand */
442 /* d_mode in 32bit, q_mode in 64bit mode. */
444 /* pair of v_mode operands */
448 /* operand size depends on REX prefixes. */
450 /* registers like dq_mode, memory like w_mode. */
452 /* 4- or 6-byte pointer operand */
455 /* v_mode for stack-related opcodes. */
457 /* non-quad operand size depends on prefixes */
459 /* 16-byte operand */
461 /* registers like dq_mode, memory like b_mode. */
463 /* registers like dq_mode, memory like d_mode. */
465 /* normal vex mode */
467 /* 128bit vex mode */
469 /* 256bit vex mode */
471 /* operand size depends on the VEX.W bit. */
474 /* scalar, ignore vector length. */
476 /* like d_mode, ignore vector length. */
478 /* like d_swap_mode, ignore vector length. */
480 /* like q_mode, ignore vector length. */
482 /* like q_swap_mode, ignore vector length. */
484 /* like vex_mode, ignore vector length. */
486 /* like vex_w_dq_mode, ignore vector length. */
487 vex_scalar_w_dq_mode
,
552 #define FLOAT NULL, { { NULL, FLOATCODE } }
554 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
555 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
556 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
557 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
558 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
559 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
560 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
561 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
562 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
563 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
564 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
565 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
683 MOD_VEX_3818_PREFIX_2
,
684 MOD_VEX_3819_PREFIX_2
,
685 MOD_VEX_381A_PREFIX_2
,
686 MOD_VEX_382A_PREFIX_2
,
687 MOD_VEX_382C_PREFIX_2
,
688 MOD_VEX_382D_PREFIX_2
,
689 MOD_VEX_382E_PREFIX_2
,
690 MOD_VEX_382F_PREFIX_2
1102 THREE_BYTE_0F38
= 0,
1257 VEX_LEN_3819_P_2_M_0
,
1258 VEX_LEN_381A_P_2_M_0
,
1270 VEX_LEN_382A_P_2_M_0
,
1588 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
1599 /* Upper case letters in the instruction names here are macros.
1600 'A' => print 'b' if no register operands or suffix_always is true
1601 'B' => print 'b' if suffix_always is true
1602 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1604 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1605 suffix_always is true
1606 'E' => print 'e' if 32-bit form of jcxz
1607 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1608 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1609 'H' => print ",pt" or ",pn" branch hint
1610 'I' => honor following macro letter even in Intel mode (implemented only
1611 for some of the macro letters)
1613 'K' => print 'd' or 'q' if rex prefix is present.
1614 'L' => print 'l' if suffix_always is true
1615 'M' => print 'r' if intel_mnemonic is false.
1616 'N' => print 'n' if instruction has no wait "prefix"
1617 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1618 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1619 or suffix_always is true. print 'q' if rex prefix is present.
1620 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1622 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1623 'S' => print 'w', 'l' or 'q' if suffix_always is true
1624 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1625 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1626 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1627 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1628 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1629 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1630 suffix_always is true.
1631 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1632 '!' => change condition from true to false or from false to true.
1633 '%' => add 1 upper case letter to the macro.
1635 2 upper case letter macros:
1636 "XY" => print 'x' or 'y' if no register operands or suffix_always
1638 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1639 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1640 or suffix_always is true
1641 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1642 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1643 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1645 Many of the above letters print nothing in Intel mode. See "putop"
1648 Braces '{' and '}', and vertical bars '|', indicate alternative
1649 mnemonic strings for AT&T and Intel. */
1651 static const struct dis386 dis386
[] = {
1653 { "addB", { Eb
, Gb
} },
1654 { "addS", { Ev
, Gv
} },
1655 { "addB", { Gb
, EbS
} },
1656 { "addS", { Gv
, EvS
} },
1657 { "addB", { AL
, Ib
} },
1658 { "addS", { eAX
, Iv
} },
1659 { X86_64_TABLE (X86_64_06
) },
1660 { X86_64_TABLE (X86_64_07
) },
1662 { "orB", { Eb
, Gb
} },
1663 { "orS", { Ev
, Gv
} },
1664 { "orB", { Gb
, EbS
} },
1665 { "orS", { Gv
, EvS
} },
1666 { "orB", { AL
, Ib
} },
1667 { "orS", { eAX
, Iv
} },
1668 { X86_64_TABLE (X86_64_0D
) },
1669 { Bad_Opcode
}, /* 0x0f extended opcode escape */
1671 { "adcB", { Eb
, Gb
} },
1672 { "adcS", { Ev
, Gv
} },
1673 { "adcB", { Gb
, EbS
} },
1674 { "adcS", { Gv
, EvS
} },
1675 { "adcB", { AL
, Ib
} },
1676 { "adcS", { eAX
, Iv
} },
1677 { X86_64_TABLE (X86_64_16
) },
1678 { X86_64_TABLE (X86_64_17
) },
1680 { "sbbB", { Eb
, Gb
} },
1681 { "sbbS", { Ev
, Gv
} },
1682 { "sbbB", { Gb
, EbS
} },
1683 { "sbbS", { Gv
, EvS
} },
1684 { "sbbB", { AL
, Ib
} },
1685 { "sbbS", { eAX
, Iv
} },
1686 { X86_64_TABLE (X86_64_1E
) },
1687 { X86_64_TABLE (X86_64_1F
) },
1689 { "andB", { Eb
, Gb
} },
1690 { "andS", { Ev
, Gv
} },
1691 { "andB", { Gb
, EbS
} },
1692 { "andS", { Gv
, EvS
} },
1693 { "andB", { AL
, Ib
} },
1694 { "andS", { eAX
, Iv
} },
1695 { Bad_Opcode
}, /* SEG ES prefix */
1696 { X86_64_TABLE (X86_64_27
) },
1698 { "subB", { Eb
, Gb
} },
1699 { "subS", { Ev
, Gv
} },
1700 { "subB", { Gb
, EbS
} },
1701 { "subS", { Gv
, EvS
} },
1702 { "subB", { AL
, Ib
} },
1703 { "subS", { eAX
, Iv
} },
1704 { Bad_Opcode
}, /* SEG CS prefix */
1705 { X86_64_TABLE (X86_64_2F
) },
1707 { "xorB", { Eb
, Gb
} },
1708 { "xorS", { Ev
, Gv
} },
1709 { "xorB", { Gb
, EbS
} },
1710 { "xorS", { Gv
, EvS
} },
1711 { "xorB", { AL
, Ib
} },
1712 { "xorS", { eAX
, Iv
} },
1713 { Bad_Opcode
}, /* SEG SS prefix */
1714 { X86_64_TABLE (X86_64_37
) },
1716 { "cmpB", { Eb
, Gb
} },
1717 { "cmpS", { Ev
, Gv
} },
1718 { "cmpB", { Gb
, EbS
} },
1719 { "cmpS", { Gv
, EvS
} },
1720 { "cmpB", { AL
, Ib
} },
1721 { "cmpS", { eAX
, Iv
} },
1722 { Bad_Opcode
}, /* SEG DS prefix */
1723 { X86_64_TABLE (X86_64_3F
) },
1725 { "inc{S|}", { RMeAX
} },
1726 { "inc{S|}", { RMeCX
} },
1727 { "inc{S|}", { RMeDX
} },
1728 { "inc{S|}", { RMeBX
} },
1729 { "inc{S|}", { RMeSP
} },
1730 { "inc{S|}", { RMeBP
} },
1731 { "inc{S|}", { RMeSI
} },
1732 { "inc{S|}", { RMeDI
} },
1734 { "dec{S|}", { RMeAX
} },
1735 { "dec{S|}", { RMeCX
} },
1736 { "dec{S|}", { RMeDX
} },
1737 { "dec{S|}", { RMeBX
} },
1738 { "dec{S|}", { RMeSP
} },
1739 { "dec{S|}", { RMeBP
} },
1740 { "dec{S|}", { RMeSI
} },
1741 { "dec{S|}", { RMeDI
} },
1743 { "pushV", { RMrAX
} },
1744 { "pushV", { RMrCX
} },
1745 { "pushV", { RMrDX
} },
1746 { "pushV", { RMrBX
} },
1747 { "pushV", { RMrSP
} },
1748 { "pushV", { RMrBP
} },
1749 { "pushV", { RMrSI
} },
1750 { "pushV", { RMrDI
} },
1752 { "popV", { RMrAX
} },
1753 { "popV", { RMrCX
} },
1754 { "popV", { RMrDX
} },
1755 { "popV", { RMrBX
} },
1756 { "popV", { RMrSP
} },
1757 { "popV", { RMrBP
} },
1758 { "popV", { RMrSI
} },
1759 { "popV", { RMrDI
} },
1761 { X86_64_TABLE (X86_64_60
) },
1762 { X86_64_TABLE (X86_64_61
) },
1763 { X86_64_TABLE (X86_64_62
) },
1764 { X86_64_TABLE (X86_64_63
) },
1765 { Bad_Opcode
}, /* seg fs */
1766 { Bad_Opcode
}, /* seg gs */
1767 { Bad_Opcode
}, /* op size prefix */
1768 { Bad_Opcode
}, /* adr size prefix */
1770 { "pushT", { Iq
} },
1771 { "imulS", { Gv
, Ev
, Iv
} },
1772 { "pushT", { sIb
} },
1773 { "imulS", { Gv
, Ev
, sIb
} },
1774 { "ins{b|}", { Ybr
, indirDX
} },
1775 { X86_64_TABLE (X86_64_6D
) },
1776 { "outs{b|}", { indirDXr
, Xb
} },
1777 { X86_64_TABLE (X86_64_6F
) },
1779 { "joH", { Jb
, XX
, cond_jump_flag
} },
1780 { "jnoH", { Jb
, XX
, cond_jump_flag
} },
1781 { "jbH", { Jb
, XX
, cond_jump_flag
} },
1782 { "jaeH", { Jb
, XX
, cond_jump_flag
} },
1783 { "jeH", { Jb
, XX
, cond_jump_flag
} },
1784 { "jneH", { Jb
, XX
, cond_jump_flag
} },
1785 { "jbeH", { Jb
, XX
, cond_jump_flag
} },
1786 { "jaH", { Jb
, XX
, cond_jump_flag
} },
1788 { "jsH", { Jb
, XX
, cond_jump_flag
} },
1789 { "jnsH", { Jb
, XX
, cond_jump_flag
} },
1790 { "jpH", { Jb
, XX
, cond_jump_flag
} },
1791 { "jnpH", { Jb
, XX
, cond_jump_flag
} },
1792 { "jlH", { Jb
, XX
, cond_jump_flag
} },
1793 { "jgeH", { Jb
, XX
, cond_jump_flag
} },
1794 { "jleH", { Jb
, XX
, cond_jump_flag
} },
1795 { "jgH", { Jb
, XX
, cond_jump_flag
} },
1797 { REG_TABLE (REG_80
) },
1798 { REG_TABLE (REG_81
) },
1800 { REG_TABLE (REG_82
) },
1801 { "testB", { Eb
, Gb
} },
1802 { "testS", { Ev
, Gv
} },
1803 { "xchgB", { Eb
, Gb
} },
1804 { "xchgS", { Ev
, Gv
} },
1806 { "movB", { Eb
, Gb
} },
1807 { "movS", { Ev
, Gv
} },
1808 { "movB", { Gb
, EbS
} },
1809 { "movS", { Gv
, EvS
} },
1810 { "movD", { Sv
, Sw
} },
1811 { MOD_TABLE (MOD_8D
) },
1812 { "movD", { Sw
, Sv
} },
1813 { REG_TABLE (REG_8F
) },
1815 { PREFIX_TABLE (PREFIX_90
) },
1816 { "xchgS", { RMeCX
, eAX
} },
1817 { "xchgS", { RMeDX
, eAX
} },
1818 { "xchgS", { RMeBX
, eAX
} },
1819 { "xchgS", { RMeSP
, eAX
} },
1820 { "xchgS", { RMeBP
, eAX
} },
1821 { "xchgS", { RMeSI
, eAX
} },
1822 { "xchgS", { RMeDI
, eAX
} },
1824 { "cW{t|}R", { XX
} },
1825 { "cR{t|}O", { XX
} },
1826 { X86_64_TABLE (X86_64_9A
) },
1827 { Bad_Opcode
}, /* fwait */
1828 { "pushfT", { XX
} },
1829 { "popfT", { XX
} },
1833 { "mov%LB", { AL
, Ob
} },
1834 { "mov%LS", { eAX
, Ov
} },
1835 { "mov%LB", { Ob
, AL
} },
1836 { "mov%LS", { Ov
, eAX
} },
1837 { "movs{b|}", { Ybr
, Xb
} },
1838 { "movs{R|}", { Yvr
, Xv
} },
1839 { "cmps{b|}", { Xb
, Yb
} },
1840 { "cmps{R|}", { Xv
, Yv
} },
1842 { "testB", { AL
, Ib
} },
1843 { "testS", { eAX
, Iv
} },
1844 { "stosB", { Ybr
, AL
} },
1845 { "stosS", { Yvr
, eAX
} },
1846 { "lodsB", { ALr
, Xb
} },
1847 { "lodsS", { eAXr
, Xv
} },
1848 { "scasB", { AL
, Yb
} },
1849 { "scasS", { eAX
, Yv
} },
1851 { "movB", { RMAL
, Ib
} },
1852 { "movB", { RMCL
, Ib
} },
1853 { "movB", { RMDL
, Ib
} },
1854 { "movB", { RMBL
, Ib
} },
1855 { "movB", { RMAH
, Ib
} },
1856 { "movB", { RMCH
, Ib
} },
1857 { "movB", { RMDH
, Ib
} },
1858 { "movB", { RMBH
, Ib
} },
1860 { "mov%LV", { RMeAX
, Iv64
} },
1861 { "mov%LV", { RMeCX
, Iv64
} },
1862 { "mov%LV", { RMeDX
, Iv64
} },
1863 { "mov%LV", { RMeBX
, Iv64
} },
1864 { "mov%LV", { RMeSP
, Iv64
} },
1865 { "mov%LV", { RMeBP
, Iv64
} },
1866 { "mov%LV", { RMeSI
, Iv64
} },
1867 { "mov%LV", { RMeDI
, Iv64
} },
1869 { REG_TABLE (REG_C0
) },
1870 { REG_TABLE (REG_C1
) },
1873 { X86_64_TABLE (X86_64_C4
) },
1874 { X86_64_TABLE (X86_64_C5
) },
1875 { REG_TABLE (REG_C6
) },
1876 { REG_TABLE (REG_C7
) },
1878 { "enterT", { Iw
, Ib
} },
1879 { "leaveT", { XX
} },
1880 { "Jret{|f}P", { Iw
} },
1881 { "Jret{|f}P", { XX
} },
1884 { X86_64_TABLE (X86_64_CE
) },
1885 { "iretP", { XX
} },
1887 { REG_TABLE (REG_D0
) },
1888 { REG_TABLE (REG_D1
) },
1889 { REG_TABLE (REG_D2
) },
1890 { REG_TABLE (REG_D3
) },
1891 { X86_64_TABLE (X86_64_D4
) },
1892 { X86_64_TABLE (X86_64_D5
) },
1894 { "xlat", { DSBX
} },
1905 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
1906 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
1907 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
1908 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
1909 { "inB", { AL
, Ib
} },
1910 { "inG", { zAX
, Ib
} },
1911 { "outB", { Ib
, AL
} },
1912 { "outG", { Ib
, zAX
} },
1914 { "callT", { Jv
} },
1916 { X86_64_TABLE (X86_64_EA
) },
1918 { "inB", { AL
, indirDX
} },
1919 { "inG", { zAX
, indirDX
} },
1920 { "outB", { indirDX
, AL
} },
1921 { "outG", { indirDX
, zAX
} },
1923 { Bad_Opcode
}, /* lock prefix */
1924 { "icebp", { XX
} },
1925 { Bad_Opcode
}, /* repne */
1926 { Bad_Opcode
}, /* repz */
1929 { REG_TABLE (REG_F6
) },
1930 { REG_TABLE (REG_F7
) },
1938 { REG_TABLE (REG_FE
) },
1939 { REG_TABLE (REG_FF
) },
1942 static const struct dis386 dis386_twobyte
[] = {
1944 { REG_TABLE (REG_0F00
) },
1945 { REG_TABLE (REG_0F01
) },
1946 { "larS", { Gv
, Ew
} },
1947 { "lslS", { Gv
, Ew
} },
1949 { "syscall", { XX
} },
1951 { "sysretP", { XX
} },
1954 { "wbinvd", { XX
} },
1958 { REG_TABLE (REG_0F0D
) },
1959 { "femms", { XX
} },
1960 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
1962 { PREFIX_TABLE (PREFIX_0F10
) },
1963 { PREFIX_TABLE (PREFIX_0F11
) },
1964 { PREFIX_TABLE (PREFIX_0F12
) },
1965 { MOD_TABLE (MOD_0F13
) },
1966 { "unpcklpX", { XM
, EXx
} },
1967 { "unpckhpX", { XM
, EXx
} },
1968 { PREFIX_TABLE (PREFIX_0F16
) },
1969 { MOD_TABLE (MOD_0F17
) },
1971 { REG_TABLE (REG_0F18
) },
1980 { MOD_TABLE (MOD_0F20
) },
1981 { MOD_TABLE (MOD_0F21
) },
1982 { MOD_TABLE (MOD_0F22
) },
1983 { MOD_TABLE (MOD_0F23
) },
1984 { MOD_TABLE (MOD_0F24
) },
1986 { MOD_TABLE (MOD_0F26
) },
1989 { "movapX", { XM
, EXx
} },
1990 { "movapX", { EXxS
, XM
} },
1991 { PREFIX_TABLE (PREFIX_0F2A
) },
1992 { PREFIX_TABLE (PREFIX_0F2B
) },
1993 { PREFIX_TABLE (PREFIX_0F2C
) },
1994 { PREFIX_TABLE (PREFIX_0F2D
) },
1995 { PREFIX_TABLE (PREFIX_0F2E
) },
1996 { PREFIX_TABLE (PREFIX_0F2F
) },
1998 { "wrmsr", { XX
} },
1999 { "rdtsc", { XX
} },
2000 { "rdmsr", { XX
} },
2001 { "rdpmc", { XX
} },
2002 { "sysenter", { XX
} },
2003 { "sysexit", { XX
} },
2005 { "getsec", { XX
} },
2007 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2009 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2016 { "cmovoS", { Gv
, Ev
} },
2017 { "cmovnoS", { Gv
, Ev
} },
2018 { "cmovbS", { Gv
, Ev
} },
2019 { "cmovaeS", { Gv
, Ev
} },
2020 { "cmoveS", { Gv
, Ev
} },
2021 { "cmovneS", { Gv
, Ev
} },
2022 { "cmovbeS", { Gv
, Ev
} },
2023 { "cmovaS", { Gv
, Ev
} },
2025 { "cmovsS", { Gv
, Ev
} },
2026 { "cmovnsS", { Gv
, Ev
} },
2027 { "cmovpS", { Gv
, Ev
} },
2028 { "cmovnpS", { Gv
, Ev
} },
2029 { "cmovlS", { Gv
, Ev
} },
2030 { "cmovgeS", { Gv
, Ev
} },
2031 { "cmovleS", { Gv
, Ev
} },
2032 { "cmovgS", { Gv
, Ev
} },
2034 { MOD_TABLE (MOD_0F51
) },
2035 { PREFIX_TABLE (PREFIX_0F51
) },
2036 { PREFIX_TABLE (PREFIX_0F52
) },
2037 { PREFIX_TABLE (PREFIX_0F53
) },
2038 { "andpX", { XM
, EXx
} },
2039 { "andnpX", { XM
, EXx
} },
2040 { "orpX", { XM
, EXx
} },
2041 { "xorpX", { XM
, EXx
} },
2043 { PREFIX_TABLE (PREFIX_0F58
) },
2044 { PREFIX_TABLE (PREFIX_0F59
) },
2045 { PREFIX_TABLE (PREFIX_0F5A
) },
2046 { PREFIX_TABLE (PREFIX_0F5B
) },
2047 { PREFIX_TABLE (PREFIX_0F5C
) },
2048 { PREFIX_TABLE (PREFIX_0F5D
) },
2049 { PREFIX_TABLE (PREFIX_0F5E
) },
2050 { PREFIX_TABLE (PREFIX_0F5F
) },
2052 { PREFIX_TABLE (PREFIX_0F60
) },
2053 { PREFIX_TABLE (PREFIX_0F61
) },
2054 { PREFIX_TABLE (PREFIX_0F62
) },
2055 { "packsswb", { MX
, EM
} },
2056 { "pcmpgtb", { MX
, EM
} },
2057 { "pcmpgtw", { MX
, EM
} },
2058 { "pcmpgtd", { MX
, EM
} },
2059 { "packuswb", { MX
, EM
} },
2061 { "punpckhbw", { MX
, EM
} },
2062 { "punpckhwd", { MX
, EM
} },
2063 { "punpckhdq", { MX
, EM
} },
2064 { "packssdw", { MX
, EM
} },
2065 { PREFIX_TABLE (PREFIX_0F6C
) },
2066 { PREFIX_TABLE (PREFIX_0F6D
) },
2067 { "movK", { MX
, Edq
} },
2068 { PREFIX_TABLE (PREFIX_0F6F
) },
2070 { PREFIX_TABLE (PREFIX_0F70
) },
2071 { REG_TABLE (REG_0F71
) },
2072 { REG_TABLE (REG_0F72
) },
2073 { REG_TABLE (REG_0F73
) },
2074 { "pcmpeqb", { MX
, EM
} },
2075 { "pcmpeqw", { MX
, EM
} },
2076 { "pcmpeqd", { MX
, EM
} },
2079 { PREFIX_TABLE (PREFIX_0F78
) },
2080 { PREFIX_TABLE (PREFIX_0F79
) },
2081 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2083 { PREFIX_TABLE (PREFIX_0F7C
) },
2084 { PREFIX_TABLE (PREFIX_0F7D
) },
2085 { PREFIX_TABLE (PREFIX_0F7E
) },
2086 { PREFIX_TABLE (PREFIX_0F7F
) },
2088 { "joH", { Jv
, XX
, cond_jump_flag
} },
2089 { "jnoH", { Jv
, XX
, cond_jump_flag
} },
2090 { "jbH", { Jv
, XX
, cond_jump_flag
} },
2091 { "jaeH", { Jv
, XX
, cond_jump_flag
} },
2092 { "jeH", { Jv
, XX
, cond_jump_flag
} },
2093 { "jneH", { Jv
, XX
, cond_jump_flag
} },
2094 { "jbeH", { Jv
, XX
, cond_jump_flag
} },
2095 { "jaH", { Jv
, XX
, cond_jump_flag
} },
2097 { "jsH", { Jv
, XX
, cond_jump_flag
} },
2098 { "jnsH", { Jv
, XX
, cond_jump_flag
} },
2099 { "jpH", { Jv
, XX
, cond_jump_flag
} },
2100 { "jnpH", { Jv
, XX
, cond_jump_flag
} },
2101 { "jlH", { Jv
, XX
, cond_jump_flag
} },
2102 { "jgeH", { Jv
, XX
, cond_jump_flag
} },
2103 { "jleH", { Jv
, XX
, cond_jump_flag
} },
2104 { "jgH", { Jv
, XX
, cond_jump_flag
} },
2107 { "setno", { Eb
} },
2109 { "setae", { Eb
} },
2111 { "setne", { Eb
} },
2112 { "setbe", { Eb
} },
2116 { "setns", { Eb
} },
2118 { "setnp", { Eb
} },
2120 { "setge", { Eb
} },
2121 { "setle", { Eb
} },
2124 { "pushT", { fs
} },
2126 { "cpuid", { XX
} },
2127 { "btS", { Ev
, Gv
} },
2128 { "shldS", { Ev
, Gv
, Ib
} },
2129 { "shldS", { Ev
, Gv
, CL
} },
2130 { REG_TABLE (REG_0FA6
) },
2131 { REG_TABLE (REG_0FA7
) },
2133 { "pushT", { gs
} },
2136 { "btsS", { Ev
, Gv
} },
2137 { "shrdS", { Ev
, Gv
, Ib
} },
2138 { "shrdS", { Ev
, Gv
, CL
} },
2139 { REG_TABLE (REG_0FAE
) },
2140 { "imulS", { Gv
, Ev
} },
2142 { "cmpxchgB", { Eb
, Gb
} },
2143 { "cmpxchgS", { Ev
, Gv
} },
2144 { MOD_TABLE (MOD_0FB2
) },
2145 { "btrS", { Ev
, Gv
} },
2146 { MOD_TABLE (MOD_0FB4
) },
2147 { MOD_TABLE (MOD_0FB5
) },
2148 { "movz{bR|x}", { Gv
, Eb
} },
2149 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2151 { PREFIX_TABLE (PREFIX_0FB8
) },
2153 { REG_TABLE (REG_0FBA
) },
2154 { "btcS", { Ev
, Gv
} },
2155 { "bsfS", { Gv
, Ev
} },
2156 { PREFIX_TABLE (PREFIX_0FBD
) },
2157 { "movs{bR|x}", { Gv
, Eb
} },
2158 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2160 { "xaddB", { Eb
, Gb
} },
2161 { "xaddS", { Ev
, Gv
} },
2162 { PREFIX_TABLE (PREFIX_0FC2
) },
2163 { PREFIX_TABLE (PREFIX_0FC3
) },
2164 { "pinsrw", { MX
, Edqw
, Ib
} },
2165 { "pextrw", { Gdq
, MS
, Ib
} },
2166 { "shufpX", { XM
, EXx
, Ib
} },
2167 { REG_TABLE (REG_0FC7
) },
2169 { "bswap", { RMeAX
} },
2170 { "bswap", { RMeCX
} },
2171 { "bswap", { RMeDX
} },
2172 { "bswap", { RMeBX
} },
2173 { "bswap", { RMeSP
} },
2174 { "bswap", { RMeBP
} },
2175 { "bswap", { RMeSI
} },
2176 { "bswap", { RMeDI
} },
2178 { PREFIX_TABLE (PREFIX_0FD0
) },
2179 { "psrlw", { MX
, EM
} },
2180 { "psrld", { MX
, EM
} },
2181 { "psrlq", { MX
, EM
} },
2182 { "paddq", { MX
, EM
} },
2183 { "pmullw", { MX
, EM
} },
2184 { PREFIX_TABLE (PREFIX_0FD6
) },
2185 { MOD_TABLE (MOD_0FD7
) },
2187 { "psubusb", { MX
, EM
} },
2188 { "psubusw", { MX
, EM
} },
2189 { "pminub", { MX
, EM
} },
2190 { "pand", { MX
, EM
} },
2191 { "paddusb", { MX
, EM
} },
2192 { "paddusw", { MX
, EM
} },
2193 { "pmaxub", { MX
, EM
} },
2194 { "pandn", { MX
, EM
} },
2196 { "pavgb", { MX
, EM
} },
2197 { "psraw", { MX
, EM
} },
2198 { "psrad", { MX
, EM
} },
2199 { "pavgw", { MX
, EM
} },
2200 { "pmulhuw", { MX
, EM
} },
2201 { "pmulhw", { MX
, EM
} },
2202 { PREFIX_TABLE (PREFIX_0FE6
) },
2203 { PREFIX_TABLE (PREFIX_0FE7
) },
2205 { "psubsb", { MX
, EM
} },
2206 { "psubsw", { MX
, EM
} },
2207 { "pminsw", { MX
, EM
} },
2208 { "por", { MX
, EM
} },
2209 { "paddsb", { MX
, EM
} },
2210 { "paddsw", { MX
, EM
} },
2211 { "pmaxsw", { MX
, EM
} },
2212 { "pxor", { MX
, EM
} },
2214 { PREFIX_TABLE (PREFIX_0FF0
) },
2215 { "psllw", { MX
, EM
} },
2216 { "pslld", { MX
, EM
} },
2217 { "psllq", { MX
, EM
} },
2218 { "pmuludq", { MX
, EM
} },
2219 { "pmaddwd", { MX
, EM
} },
2220 { "psadbw", { MX
, EM
} },
2221 { PREFIX_TABLE (PREFIX_0FF7
) },
2223 { "psubb", { MX
, EM
} },
2224 { "psubw", { MX
, EM
} },
2225 { "psubd", { MX
, EM
} },
2226 { "psubq", { MX
, EM
} },
2227 { "paddb", { MX
, EM
} },
2228 { "paddw", { MX
, EM
} },
2229 { "paddd", { MX
, EM
} },
2233 static const unsigned char onebyte_has_modrm
[256] = {
2234 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2235 /* ------------------------------- */
2236 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2237 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2238 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2239 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2240 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2241 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2242 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2243 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2244 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2245 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2246 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2247 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2248 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2249 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2250 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2251 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2252 /* ------------------------------- */
2253 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2256 static const unsigned char twobyte_has_modrm
[256] = {
2257 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2258 /* ------------------------------- */
2259 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2260 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2261 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2262 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2263 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2264 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2265 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2266 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2267 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2268 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2269 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2270 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2271 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2272 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2273 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2274 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2275 /* ------------------------------- */
2276 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2279 static char obuf
[100];
2281 static char *mnemonicendp
;
2282 static char scratchbuf
[100];
2283 static unsigned char *start_codep
;
2284 static unsigned char *insn_codep
;
2285 static unsigned char *codep
;
2286 static int last_lock_prefix
;
2287 static int last_repz_prefix
;
2288 static int last_repnz_prefix
;
2289 static int last_data_prefix
;
2290 static int last_addr_prefix
;
2291 static int last_rex_prefix
;
2292 static int last_seg_prefix
;
2293 #define MAX_CODE_LENGTH 15
2294 /* We can up to 14 prefixes since the maximum instruction length is
2296 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2297 static disassemble_info
*the_info
;
2305 static unsigned char need_modrm
;
2315 int register_specifier
;
2321 static unsigned char need_vex
;
2322 static unsigned char need_vex_reg
;
2323 static unsigned char vex_w_done
;
2331 /* If we are accessing mod/rm/reg without need_modrm set, then the
2332 values are stale. Hitting this abort likely indicates that you
2333 need to update onebyte_has_modrm or twobyte_has_modrm. */
2334 #define MODRM_CHECK if (!need_modrm) abort ()
2336 static const char **names64
;
2337 static const char **names32
;
2338 static const char **names16
;
2339 static const char **names8
;
2340 static const char **names8rex
;
2341 static const char **names_seg
;
2342 static const char *index64
;
2343 static const char *index32
;
2344 static const char **index16
;
2346 static const char *intel_names64
[] = {
2347 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2348 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2350 static const char *intel_names32
[] = {
2351 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2352 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2354 static const char *intel_names16
[] = {
2355 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2356 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2358 static const char *intel_names8
[] = {
2359 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2361 static const char *intel_names8rex
[] = {
2362 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2363 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2365 static const char *intel_names_seg
[] = {
2366 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2368 static const char *intel_index64
= "riz";
2369 static const char *intel_index32
= "eiz";
2370 static const char *intel_index16
[] = {
2371 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2374 static const char *att_names64
[] = {
2375 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2376 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2378 static const char *att_names32
[] = {
2379 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2380 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2382 static const char *att_names16
[] = {
2383 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2384 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2386 static const char *att_names8
[] = {
2387 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2389 static const char *att_names8rex
[] = {
2390 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2391 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2393 static const char *att_names_seg
[] = {
2394 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2396 static const char *att_index64
= "%riz";
2397 static const char *att_index32
= "%eiz";
2398 static const char *att_index16
[] = {
2399 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2402 static const char **names_mm
;
2403 static const char *intel_names_mm
[] = {
2404 "mm0", "mm1", "mm2", "mm3",
2405 "mm4", "mm5", "mm6", "mm7"
2407 static const char *att_names_mm
[] = {
2408 "%mm0", "%mm1", "%mm2", "%mm3",
2409 "%mm4", "%mm5", "%mm6", "%mm7"
2412 static const char **names_xmm
;
2413 static const char *intel_names_xmm
[] = {
2414 "xmm0", "xmm1", "xmm2", "xmm3",
2415 "xmm4", "xmm5", "xmm6", "xmm7",
2416 "xmm8", "xmm9", "xmm10", "xmm11",
2417 "xmm12", "xmm13", "xmm14", "xmm15"
2419 static const char *att_names_xmm
[] = {
2420 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2421 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2422 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2423 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2426 static const char **names_ymm
;
2427 static const char *intel_names_ymm
[] = {
2428 "ymm0", "ymm1", "ymm2", "ymm3",
2429 "ymm4", "ymm5", "ymm6", "ymm7",
2430 "ymm8", "ymm9", "ymm10", "ymm11",
2431 "ymm12", "ymm13", "ymm14", "ymm15"
2433 static const char *att_names_ymm
[] = {
2434 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2435 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2436 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2437 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2440 static const struct dis386 reg_table
[][8] = {
2443 { "addA", { Eb
, Ib
} },
2444 { "orA", { Eb
, Ib
} },
2445 { "adcA", { Eb
, Ib
} },
2446 { "sbbA", { Eb
, Ib
} },
2447 { "andA", { Eb
, Ib
} },
2448 { "subA", { Eb
, Ib
} },
2449 { "xorA", { Eb
, Ib
} },
2450 { "cmpA", { Eb
, Ib
} },
2454 { "addQ", { Ev
, Iv
} },
2455 { "orQ", { Ev
, Iv
} },
2456 { "adcQ", { Ev
, Iv
} },
2457 { "sbbQ", { Ev
, Iv
} },
2458 { "andQ", { Ev
, Iv
} },
2459 { "subQ", { Ev
, Iv
} },
2460 { "xorQ", { Ev
, Iv
} },
2461 { "cmpQ", { Ev
, Iv
} },
2465 { "addQ", { Ev
, sIb
} },
2466 { "orQ", { Ev
, sIb
} },
2467 { "adcQ", { Ev
, sIb
} },
2468 { "sbbQ", { Ev
, sIb
} },
2469 { "andQ", { Ev
, sIb
} },
2470 { "subQ", { Ev
, sIb
} },
2471 { "xorQ", { Ev
, sIb
} },
2472 { "cmpQ", { Ev
, sIb
} },
2476 { "popU", { stackEv
} },
2477 { XOP_8F_TABLE (XOP_09
) },
2481 { XOP_8F_TABLE (XOP_09
) },
2485 { "rolA", { Eb
, Ib
} },
2486 { "rorA", { Eb
, Ib
} },
2487 { "rclA", { Eb
, Ib
} },
2488 { "rcrA", { Eb
, Ib
} },
2489 { "shlA", { Eb
, Ib
} },
2490 { "shrA", { Eb
, Ib
} },
2492 { "sarA", { Eb
, Ib
} },
2496 { "rolQ", { Ev
, Ib
} },
2497 { "rorQ", { Ev
, Ib
} },
2498 { "rclQ", { Ev
, Ib
} },
2499 { "rcrQ", { Ev
, Ib
} },
2500 { "shlQ", { Ev
, Ib
} },
2501 { "shrQ", { Ev
, Ib
} },
2503 { "sarQ", { Ev
, Ib
} },
2507 { "movA", { Eb
, Ib
} },
2511 { "movQ", { Ev
, Iv
} },
2515 { "rolA", { Eb
, I1
} },
2516 { "rorA", { Eb
, I1
} },
2517 { "rclA", { Eb
, I1
} },
2518 { "rcrA", { Eb
, I1
} },
2519 { "shlA", { Eb
, I1
} },
2520 { "shrA", { Eb
, I1
} },
2522 { "sarA", { Eb
, I1
} },
2526 { "rolQ", { Ev
, I1
} },
2527 { "rorQ", { Ev
, I1
} },
2528 { "rclQ", { Ev
, I1
} },
2529 { "rcrQ", { Ev
, I1
} },
2530 { "shlQ", { Ev
, I1
} },
2531 { "shrQ", { Ev
, I1
} },
2533 { "sarQ", { Ev
, I1
} },
2537 { "rolA", { Eb
, CL
} },
2538 { "rorA", { Eb
, CL
} },
2539 { "rclA", { Eb
, CL
} },
2540 { "rcrA", { Eb
, CL
} },
2541 { "shlA", { Eb
, CL
} },
2542 { "shrA", { Eb
, CL
} },
2544 { "sarA", { Eb
, CL
} },
2548 { "rolQ", { Ev
, CL
} },
2549 { "rorQ", { Ev
, CL
} },
2550 { "rclQ", { Ev
, CL
} },
2551 { "rcrQ", { Ev
, CL
} },
2552 { "shlQ", { Ev
, CL
} },
2553 { "shrQ", { Ev
, CL
} },
2555 { "sarQ", { Ev
, CL
} },
2559 { "testA", { Eb
, Ib
} },
2563 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
2564 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
2565 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
2566 { "idivA", { Eb
} }, /* and idiv for consistency. */
2570 { "testQ", { Ev
, Iv
} },
2574 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
2575 { "imulQ", { Ev
} },
2577 { "idivQ", { Ev
} },
2588 { "callT", { indirEv
} },
2589 { "JcallT", { indirEp
} },
2590 { "jmpT", { indirEv
} },
2591 { "JjmpT", { indirEp
} },
2592 { "pushU", { stackEv
} },
2597 { "sldtD", { Sv
} },
2608 { MOD_TABLE (MOD_0F01_REG_0
) },
2609 { MOD_TABLE (MOD_0F01_REG_1
) },
2610 { MOD_TABLE (MOD_0F01_REG_2
) },
2611 { MOD_TABLE (MOD_0F01_REG_3
) },
2612 { "smswD", { Sv
} },
2615 { MOD_TABLE (MOD_0F01_REG_7
) },
2619 { "prefetch", { Eb
} },
2620 { "prefetchw", { Eb
} },
2624 { MOD_TABLE (MOD_0F18_REG_0
) },
2625 { MOD_TABLE (MOD_0F18_REG_1
) },
2626 { MOD_TABLE (MOD_0F18_REG_2
) },
2627 { MOD_TABLE (MOD_0F18_REG_3
) },
2633 { MOD_TABLE (MOD_0F71_REG_2
) },
2635 { MOD_TABLE (MOD_0F71_REG_4
) },
2637 { MOD_TABLE (MOD_0F71_REG_6
) },
2643 { MOD_TABLE (MOD_0F72_REG_2
) },
2645 { MOD_TABLE (MOD_0F72_REG_4
) },
2647 { MOD_TABLE (MOD_0F72_REG_6
) },
2653 { MOD_TABLE (MOD_0F73_REG_2
) },
2654 { MOD_TABLE (MOD_0F73_REG_3
) },
2657 { MOD_TABLE (MOD_0F73_REG_6
) },
2658 { MOD_TABLE (MOD_0F73_REG_7
) },
2662 { "montmul", { { OP_0f07
, 0 } } },
2663 { "xsha1", { { OP_0f07
, 0 } } },
2664 { "xsha256", { { OP_0f07
, 0 } } },
2668 { "xstore-rng", { { OP_0f07
, 0 } } },
2669 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
2670 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
2671 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
2672 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
2673 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
2677 { MOD_TABLE (MOD_0FAE_REG_0
) },
2678 { MOD_TABLE (MOD_0FAE_REG_1
) },
2679 { MOD_TABLE (MOD_0FAE_REG_2
) },
2680 { MOD_TABLE (MOD_0FAE_REG_3
) },
2681 { MOD_TABLE (MOD_0FAE_REG_4
) },
2682 { MOD_TABLE (MOD_0FAE_REG_5
) },
2683 { MOD_TABLE (MOD_0FAE_REG_6
) },
2684 { MOD_TABLE (MOD_0FAE_REG_7
) },
2692 { "btQ", { Ev
, Ib
} },
2693 { "btsQ", { Ev
, Ib
} },
2694 { "btrQ", { Ev
, Ib
} },
2695 { "btcQ", { Ev
, Ib
} },
2700 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
2705 { MOD_TABLE (MOD_0FC7_REG_6
) },
2706 { MOD_TABLE (MOD_0FC7_REG_7
) },
2712 { MOD_TABLE (MOD_VEX_71_REG_2
) },
2714 { MOD_TABLE (MOD_VEX_71_REG_4
) },
2716 { MOD_TABLE (MOD_VEX_71_REG_6
) },
2722 { MOD_TABLE (MOD_VEX_72_REG_2
) },
2724 { MOD_TABLE (MOD_VEX_72_REG_4
) },
2726 { MOD_TABLE (MOD_VEX_72_REG_6
) },
2732 { MOD_TABLE (MOD_VEX_73_REG_2
) },
2733 { MOD_TABLE (MOD_VEX_73_REG_3
) },
2736 { MOD_TABLE (MOD_VEX_73_REG_6
) },
2737 { MOD_TABLE (MOD_VEX_73_REG_7
) },
2743 { MOD_TABLE (MOD_VEX_AE_REG_2
) },
2744 { MOD_TABLE (MOD_VEX_AE_REG_3
) },
2748 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
2749 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
2753 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2754 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
2758 static const struct dis386 prefix_table
[][4] = {
2761 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2762 { "pause", { XX
} },
2763 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
2768 { "movups", { XM
, EXx
} },
2769 { "movss", { XM
, EXd
} },
2770 { "movupd", { XM
, EXx
} },
2771 { "movsd", { XM
, EXq
} },
2776 { "movups", { EXxS
, XM
} },
2777 { "movss", { EXdS
, XM
} },
2778 { "movupd", { EXxS
, XM
} },
2779 { "movsd", { EXqS
, XM
} },
2784 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
2785 { "movsldup", { XM
, EXx
} },
2786 { "movlpd", { XM
, EXq
} },
2787 { "movddup", { XM
, EXq
} },
2792 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
2793 { "movshdup", { XM
, EXx
} },
2794 { "movhpd", { XM
, EXq
} },
2799 { "cvtpi2ps", { XM
, EMCq
} },
2800 { "cvtsi2ss%LQ", { XM
, Ev
} },
2801 { "cvtpi2pd", { XM
, EMCq
} },
2802 { "cvtsi2sd%LQ", { XM
, Ev
} },
2807 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
2808 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
2809 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
2810 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
2815 { "cvttps2pi", { MXC
, EXq
} },
2816 { "cvttss2siY", { Gv
, EXd
} },
2817 { "cvttpd2pi", { MXC
, EXx
} },
2818 { "cvttsd2siY", { Gv
, EXq
} },
2823 { "cvtps2pi", { MXC
, EXq
} },
2824 { "cvtss2siY", { Gv
, EXd
} },
2825 { "cvtpd2pi", { MXC
, EXx
} },
2826 { "cvtsd2siY", { Gv
, EXq
} },
2831 { "ucomiss",{ XM
, EXd
} },
2833 { "ucomisd",{ XM
, EXq
} },
2838 { "comiss", { XM
, EXd
} },
2840 { "comisd", { XM
, EXq
} },
2845 { "sqrtps", { XM
, EXx
} },
2846 { "sqrtss", { XM
, EXd
} },
2847 { "sqrtpd", { XM
, EXx
} },
2848 { "sqrtsd", { XM
, EXq
} },
2853 { "rsqrtps",{ XM
, EXx
} },
2854 { "rsqrtss",{ XM
, EXd
} },
2859 { "rcpps", { XM
, EXx
} },
2860 { "rcpss", { XM
, EXd
} },
2865 { "addps", { XM
, EXx
} },
2866 { "addss", { XM
, EXd
} },
2867 { "addpd", { XM
, EXx
} },
2868 { "addsd", { XM
, EXq
} },
2873 { "mulps", { XM
, EXx
} },
2874 { "mulss", { XM
, EXd
} },
2875 { "mulpd", { XM
, EXx
} },
2876 { "mulsd", { XM
, EXq
} },
2881 { "cvtps2pd", { XM
, EXq
} },
2882 { "cvtss2sd", { XM
, EXd
} },
2883 { "cvtpd2ps", { XM
, EXx
} },
2884 { "cvtsd2ss", { XM
, EXq
} },
2889 { "cvtdq2ps", { XM
, EXx
} },
2890 { "cvttps2dq", { XM
, EXx
} },
2891 { "cvtps2dq", { XM
, EXx
} },
2896 { "subps", { XM
, EXx
} },
2897 { "subss", { XM
, EXd
} },
2898 { "subpd", { XM
, EXx
} },
2899 { "subsd", { XM
, EXq
} },
2904 { "minps", { XM
, EXx
} },
2905 { "minss", { XM
, EXd
} },
2906 { "minpd", { XM
, EXx
} },
2907 { "minsd", { XM
, EXq
} },
2912 { "divps", { XM
, EXx
} },
2913 { "divss", { XM
, EXd
} },
2914 { "divpd", { XM
, EXx
} },
2915 { "divsd", { XM
, EXq
} },
2920 { "maxps", { XM
, EXx
} },
2921 { "maxss", { XM
, EXd
} },
2922 { "maxpd", { XM
, EXx
} },
2923 { "maxsd", { XM
, EXq
} },
2928 { "punpcklbw",{ MX
, EMd
} },
2930 { "punpcklbw",{ MX
, EMx
} },
2935 { "punpcklwd",{ MX
, EMd
} },
2937 { "punpcklwd",{ MX
, EMx
} },
2942 { "punpckldq",{ MX
, EMd
} },
2944 { "punpckldq",{ MX
, EMx
} },
2951 { "punpcklqdq", { XM
, EXx
} },
2958 { "punpckhqdq", { XM
, EXx
} },
2963 { "movq", { MX
, EM
} },
2964 { "movdqu", { XM
, EXx
} },
2965 { "movdqa", { XM
, EXx
} },
2970 { "pshufw", { MX
, EM
, Ib
} },
2971 { "pshufhw",{ XM
, EXx
, Ib
} },
2972 { "pshufd", { XM
, EXx
, Ib
} },
2973 { "pshuflw",{ XM
, EXx
, Ib
} },
2976 /* PREFIX_0F73_REG_3 */
2980 { "psrldq", { XS
, Ib
} },
2983 /* PREFIX_0F73_REG_7 */
2987 { "pslldq", { XS
, Ib
} },
2992 {"vmread", { Em
, Gm
} },
2994 {"extrq", { XS
, Ib
, Ib
} },
2995 {"insertq", { XM
, XS
, Ib
, Ib
} },
3000 {"vmwrite", { Gm
, Em
} },
3002 {"extrq", { XM
, XS
} },
3003 {"insertq", { XM
, XS
} },
3010 { "haddpd", { XM
, EXx
} },
3011 { "haddps", { XM
, EXx
} },
3018 { "hsubpd", { XM
, EXx
} },
3019 { "hsubps", { XM
, EXx
} },
3024 { "movK", { Edq
, MX
} },
3025 { "movq", { XM
, EXq
} },
3026 { "movK", { Edq
, XM
} },
3031 { "movq", { EMS
, MX
} },
3032 { "movdqu", { EXxS
, XM
} },
3033 { "movdqa", { EXxS
, XM
} },
3039 { "popcntS", { Gv
, Ev
} },
3044 { "bsrS", { Gv
, Ev
} },
3045 { "lzcntS", { Gv
, Ev
} },
3046 { "bsrS", { Gv
, Ev
} },
3051 { "cmpps", { XM
, EXx
, CMP
} },
3052 { "cmpss", { XM
, EXd
, CMP
} },
3053 { "cmppd", { XM
, EXx
, CMP
} },
3054 { "cmpsd", { XM
, EXq
, CMP
} },
3059 { "movntiS", { Ma
, Gv
} },
3062 /* PREFIX_0FC7_REG_6 */
3064 { "vmptrld",{ Mq
} },
3065 { "vmxon", { Mq
} },
3066 { "vmclear",{ Mq
} },
3073 { "addsubpd", { XM
, EXx
} },
3074 { "addsubps", { XM
, EXx
} },
3080 { "movq2dq",{ XM
, MS
} },
3081 { "movq", { EXqS
, XM
} },
3082 { "movdq2q",{ MX
, XS
} },
3088 { "cvtdq2pd", { XM
, EXq
} },
3089 { "cvttpd2dq", { XM
, EXx
} },
3090 { "cvtpd2dq", { XM
, EXx
} },
3095 { "movntq", { Mq
, MX
} },
3097 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3105 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3110 { "maskmovq", { MX
, MS
} },
3112 { "maskmovdqu", { XM
, XS
} },
3119 { "pblendvb", { XM
, EXx
, XMM0
} },
3126 { "blendvps", { XM
, EXx
, XMM0
} },
3133 { "blendvpd", { XM
, EXx
, XMM0
} },
3140 { "ptest", { XM
, EXx
} },
3147 { "pmovsxbw", { XM
, EXq
} },
3154 { "pmovsxbd", { XM
, EXd
} },
3161 { "pmovsxbq", { XM
, EXw
} },
3168 { "pmovsxwd", { XM
, EXq
} },
3175 { "pmovsxwq", { XM
, EXd
} },
3182 { "pmovsxdq", { XM
, EXq
} },
3189 { "pmuldq", { XM
, EXx
} },
3196 { "pcmpeqq", { XM
, EXx
} },
3203 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3210 { "packusdw", { XM
, EXx
} },
3217 { "pmovzxbw", { XM
, EXq
} },
3224 { "pmovzxbd", { XM
, EXd
} },
3231 { "pmovzxbq", { XM
, EXw
} },
3238 { "pmovzxwd", { XM
, EXq
} },
3245 { "pmovzxwq", { XM
, EXd
} },
3252 { "pmovzxdq", { XM
, EXq
} },
3259 { "pcmpgtq", { XM
, EXx
} },
3266 { "pminsb", { XM
, EXx
} },
3273 { "pminsd", { XM
, EXx
} },
3280 { "pminuw", { XM
, EXx
} },
3287 { "pminud", { XM
, EXx
} },
3294 { "pmaxsb", { XM
, EXx
} },
3301 { "pmaxsd", { XM
, EXx
} },
3308 { "pmaxuw", { XM
, EXx
} },
3315 { "pmaxud", { XM
, EXx
} },
3322 { "pmulld", { XM
, EXx
} },
3329 { "phminposuw", { XM
, EXx
} },
3336 { "invept", { Gm
, Mo
} },
3343 { "invvpid", { Gm
, Mo
} },
3350 { "aesimc", { XM
, EXx
} },
3357 { "aesenc", { XM
, EXx
} },
3364 { "aesenclast", { XM
, EXx
} },
3371 { "aesdec", { XM
, EXx
} },
3378 { "aesdeclast", { XM
, EXx
} },
3383 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3385 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
3386 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
3391 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3393 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
3394 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
3401 { "roundps", { XM
, EXx
, Ib
} },
3408 { "roundpd", { XM
, EXx
, Ib
} },
3415 { "roundss", { XM
, EXd
, Ib
} },
3422 { "roundsd", { XM
, EXq
, Ib
} },
3429 { "blendps", { XM
, EXx
, Ib
} },
3436 { "blendpd", { XM
, EXx
, Ib
} },
3443 { "pblendw", { XM
, EXx
, Ib
} },
3450 { "pextrb", { Edqb
, XM
, Ib
} },
3457 { "pextrw", { Edqw
, XM
, Ib
} },
3464 { "pextrK", { Edq
, XM
, Ib
} },
3471 { "extractps", { Edqd
, XM
, Ib
} },
3478 { "pinsrb", { XM
, Edqb
, Ib
} },
3485 { "insertps", { XM
, EXd
, Ib
} },
3492 { "pinsrK", { XM
, Edq
, Ib
} },
3499 { "dpps", { XM
, EXx
, Ib
} },
3506 { "dppd", { XM
, EXx
, Ib
} },
3513 { "mpsadbw", { XM
, EXx
, Ib
} },
3520 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
3527 { "pcmpestrm", { XM
, EXx
, Ib
} },
3534 { "pcmpestri", { XM
, EXx
, Ib
} },
3541 { "pcmpistrm", { XM
, EXx
, Ib
} },
3548 { "pcmpistri", { XM
, EXx
, Ib
} },
3555 { "aeskeygenassist", { XM
, EXx
, Ib
} },
3560 { VEX_W_TABLE (VEX_W_10_P_0
) },
3561 { VEX_LEN_TABLE (VEX_LEN_10_P_1
) },
3562 { VEX_W_TABLE (VEX_W_10_P_2
) },
3563 { VEX_LEN_TABLE (VEX_LEN_10_P_3
) },
3568 { VEX_W_TABLE (VEX_W_11_P_0
) },
3569 { VEX_LEN_TABLE (VEX_LEN_11_P_1
) },
3570 { VEX_W_TABLE (VEX_W_11_P_2
) },
3571 { VEX_LEN_TABLE (VEX_LEN_11_P_3
) },
3576 { MOD_TABLE (MOD_VEX_12_PREFIX_0
) },
3577 { VEX_W_TABLE (VEX_W_12_P_1
) },
3578 { VEX_LEN_TABLE (VEX_LEN_12_P_2
) },
3579 { VEX_W_TABLE (VEX_W_12_P_3
) },
3584 { MOD_TABLE (MOD_VEX_16_PREFIX_0
) },
3585 { VEX_W_TABLE (VEX_W_16_P_1
) },
3586 { VEX_LEN_TABLE (VEX_LEN_16_P_2
) },
3592 { VEX_LEN_TABLE (VEX_LEN_2A_P_1
) },
3594 { VEX_LEN_TABLE (VEX_LEN_2A_P_3
) },
3600 { VEX_LEN_TABLE (VEX_LEN_2C_P_1
) },
3602 { VEX_LEN_TABLE (VEX_LEN_2C_P_3
) },
3608 { VEX_LEN_TABLE (VEX_LEN_2D_P_1
) },
3610 { VEX_LEN_TABLE (VEX_LEN_2D_P_3
) },
3615 { VEX_LEN_TABLE (VEX_LEN_2E_P_0
) },
3617 { VEX_LEN_TABLE (VEX_LEN_2E_P_2
) },
3622 { VEX_LEN_TABLE (VEX_LEN_2F_P_0
) },
3624 { VEX_LEN_TABLE (VEX_LEN_2F_P_2
) },
3629 { VEX_W_TABLE (VEX_W_51_P_0
) },
3630 { VEX_LEN_TABLE (VEX_LEN_51_P_1
) },
3631 { VEX_W_TABLE (VEX_W_51_P_2
) },
3632 { VEX_LEN_TABLE (VEX_LEN_51_P_3
) },
3637 { VEX_W_TABLE (VEX_W_52_P_0
) },
3638 { VEX_LEN_TABLE (VEX_LEN_52_P_1
) },
3643 { VEX_W_TABLE (VEX_W_53_P_0
) },
3644 { VEX_LEN_TABLE (VEX_LEN_53_P_1
) },
3649 { VEX_W_TABLE (VEX_W_58_P_0
) },
3650 { VEX_LEN_TABLE (VEX_LEN_58_P_1
) },
3651 { VEX_W_TABLE (VEX_W_58_P_2
) },
3652 { VEX_LEN_TABLE (VEX_LEN_58_P_3
) },
3657 { VEX_W_TABLE (VEX_W_59_P_0
) },
3658 { VEX_LEN_TABLE (VEX_LEN_59_P_1
) },
3659 { VEX_W_TABLE (VEX_W_59_P_2
) },
3660 { VEX_LEN_TABLE (VEX_LEN_59_P_3
) },
3665 { VEX_W_TABLE (VEX_W_5A_P_0
) },
3666 { VEX_LEN_TABLE (VEX_LEN_5A_P_1
) },
3667 { "vcvtpd2ps%XY", { XMM
, EXx
} },
3668 { VEX_LEN_TABLE (VEX_LEN_5A_P_3
) },
3673 { VEX_W_TABLE (VEX_W_5B_P_0
) },
3674 { VEX_W_TABLE (VEX_W_5B_P_1
) },
3675 { VEX_W_TABLE (VEX_W_5B_P_2
) },
3680 { VEX_W_TABLE (VEX_W_5C_P_0
) },
3681 { VEX_LEN_TABLE (VEX_LEN_5C_P_1
) },
3682 { VEX_W_TABLE (VEX_W_5C_P_2
) },
3683 { VEX_LEN_TABLE (VEX_LEN_5C_P_3
) },
3688 { VEX_W_TABLE (VEX_W_5D_P_0
) },
3689 { VEX_LEN_TABLE (VEX_LEN_5D_P_1
) },
3690 { VEX_W_TABLE (VEX_W_5D_P_2
) },
3691 { VEX_LEN_TABLE (VEX_LEN_5D_P_3
) },
3696 { VEX_W_TABLE (VEX_W_5E_P_0
) },
3697 { VEX_LEN_TABLE (VEX_LEN_5E_P_1
) },
3698 { VEX_W_TABLE (VEX_W_5E_P_2
) },
3699 { VEX_LEN_TABLE (VEX_LEN_5E_P_3
) },
3704 { VEX_W_TABLE (VEX_W_5F_P_0
) },
3705 { VEX_LEN_TABLE (VEX_LEN_5F_P_1
) },
3706 { VEX_W_TABLE (VEX_W_5F_P_2
) },
3707 { VEX_LEN_TABLE (VEX_LEN_5F_P_3
) },
3714 { VEX_LEN_TABLE (VEX_LEN_60_P_2
) },
3721 { VEX_LEN_TABLE (VEX_LEN_61_P_2
) },
3728 { VEX_LEN_TABLE (VEX_LEN_62_P_2
) },
3735 { VEX_LEN_TABLE (VEX_LEN_63_P_2
) },
3742 { VEX_LEN_TABLE (VEX_LEN_64_P_2
) },
3749 { VEX_LEN_TABLE (VEX_LEN_65_P_2
) },
3756 { VEX_LEN_TABLE (VEX_LEN_66_P_2
) },
3763 { VEX_LEN_TABLE (VEX_LEN_67_P_2
) },
3770 { VEX_LEN_TABLE (VEX_LEN_68_P_2
) },
3777 { VEX_LEN_TABLE (VEX_LEN_69_P_2
) },
3784 { VEX_LEN_TABLE (VEX_LEN_6A_P_2
) },
3791 { VEX_LEN_TABLE (VEX_LEN_6B_P_2
) },
3798 { VEX_LEN_TABLE (VEX_LEN_6C_P_2
) },
3805 { VEX_LEN_TABLE (VEX_LEN_6D_P_2
) },
3812 { VEX_LEN_TABLE (VEX_LEN_6E_P_2
) },
3818 { VEX_W_TABLE (VEX_W_6F_P_1
) },
3819 { VEX_W_TABLE (VEX_W_6F_P_2
) },
3825 { VEX_LEN_TABLE (VEX_LEN_70_P_1
) },
3826 { VEX_LEN_TABLE (VEX_LEN_70_P_2
) },
3827 { VEX_LEN_TABLE (VEX_LEN_70_P_3
) },
3830 /* PREFIX_VEX_71_REG_2 */
3834 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2
) },
3837 /* PREFIX_VEX_71_REG_4 */
3841 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2
) },
3844 /* PREFIX_VEX_71_REG_6 */
3848 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2
) },
3851 /* PREFIX_VEX_72_REG_2 */
3855 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2
) },
3858 /* PREFIX_VEX_72_REG_4 */
3862 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2
) },
3865 /* PREFIX_VEX_72_REG_6 */
3869 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2
) },
3872 /* PREFIX_VEX_73_REG_2 */
3876 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2
) },
3879 /* PREFIX_VEX_73_REG_3 */
3883 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2
) },
3886 /* PREFIX_VEX_73_REG_6 */
3890 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2
) },
3893 /* PREFIX_VEX_73_REG_7 */
3897 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2
) },
3904 { VEX_LEN_TABLE (VEX_LEN_74_P_2
) },
3911 { VEX_LEN_TABLE (VEX_LEN_75_P_2
) },
3918 { VEX_LEN_TABLE (VEX_LEN_76_P_2
) },
3923 { VEX_W_TABLE (VEX_W_77_P_0
) },
3930 { VEX_W_TABLE (VEX_W_7C_P_2
) },
3931 { VEX_W_TABLE (VEX_W_7C_P_3
) },
3938 { VEX_W_TABLE (VEX_W_7D_P_2
) },
3939 { VEX_W_TABLE (VEX_W_7D_P_3
) },
3945 { VEX_LEN_TABLE (VEX_LEN_7E_P_1
) },
3946 { VEX_LEN_TABLE (VEX_LEN_7E_P_2
) },
3952 { VEX_W_TABLE (VEX_W_7F_P_1
) },
3953 { VEX_W_TABLE (VEX_W_7F_P_2
) },
3958 { VEX_W_TABLE (VEX_W_C2_P_0
) },
3959 { VEX_LEN_TABLE (VEX_LEN_C2_P_1
) },
3960 { VEX_W_TABLE (VEX_W_C2_P_2
) },
3961 { VEX_LEN_TABLE (VEX_LEN_C2_P_3
) },
3968 { VEX_LEN_TABLE (VEX_LEN_C4_P_2
) },
3975 { VEX_LEN_TABLE (VEX_LEN_C5_P_2
) },
3982 { VEX_W_TABLE (VEX_W_D0_P_2
) },
3983 { VEX_W_TABLE (VEX_W_D0_P_3
) },
3990 { VEX_LEN_TABLE (VEX_LEN_D1_P_2
) },
3997 { VEX_LEN_TABLE (VEX_LEN_D2_P_2
) },
4004 { VEX_LEN_TABLE (VEX_LEN_D3_P_2
) },
4011 { VEX_LEN_TABLE (VEX_LEN_D4_P_2
) },
4018 { VEX_LEN_TABLE (VEX_LEN_D5_P_2
) },
4025 { VEX_LEN_TABLE (VEX_LEN_D6_P_2
) },
4032 { MOD_TABLE (MOD_VEX_D7_PREFIX_2
) },
4039 { VEX_LEN_TABLE (VEX_LEN_D8_P_2
) },
4046 { VEX_LEN_TABLE (VEX_LEN_D9_P_2
) },
4053 { VEX_LEN_TABLE (VEX_LEN_DA_P_2
) },
4060 { VEX_LEN_TABLE (VEX_LEN_DB_P_2
) },
4067 { VEX_LEN_TABLE (VEX_LEN_DC_P_2
) },
4074 { VEX_LEN_TABLE (VEX_LEN_DD_P_2
) },
4081 { VEX_LEN_TABLE (VEX_LEN_DE_P_2
) },
4088 { VEX_LEN_TABLE (VEX_LEN_DF_P_2
) },
4095 { VEX_LEN_TABLE (VEX_LEN_E0_P_2
) },
4102 { VEX_LEN_TABLE (VEX_LEN_E1_P_2
) },
4109 { VEX_LEN_TABLE (VEX_LEN_E2_P_2
) },
4116 { VEX_LEN_TABLE (VEX_LEN_E3_P_2
) },
4123 { VEX_LEN_TABLE (VEX_LEN_E4_P_2
) },
4130 { VEX_LEN_TABLE (VEX_LEN_E5_P_2
) },
4136 { VEX_W_TABLE (VEX_W_E6_P_1
) },
4137 { VEX_W_TABLE (VEX_W_E6_P_2
) },
4138 { VEX_W_TABLE (VEX_W_E6_P_3
) },
4145 { MOD_TABLE (MOD_VEX_E7_PREFIX_2
) },
4152 { VEX_LEN_TABLE (VEX_LEN_E8_P_2
) },
4159 { VEX_LEN_TABLE (VEX_LEN_E9_P_2
) },
4166 { VEX_LEN_TABLE (VEX_LEN_EA_P_2
) },
4173 { VEX_LEN_TABLE (VEX_LEN_EB_P_2
) },
4180 { VEX_LEN_TABLE (VEX_LEN_EC_P_2
) },
4187 { VEX_LEN_TABLE (VEX_LEN_ED_P_2
) },
4194 { VEX_LEN_TABLE (VEX_LEN_EE_P_2
) },
4201 { VEX_LEN_TABLE (VEX_LEN_EF_P_2
) },
4209 { MOD_TABLE (MOD_VEX_F0_PREFIX_3
) },
4216 { VEX_LEN_TABLE (VEX_LEN_F1_P_2
) },
4223 { VEX_LEN_TABLE (VEX_LEN_F2_P_2
) },
4230 { VEX_LEN_TABLE (VEX_LEN_F3_P_2
) },
4237 { VEX_LEN_TABLE (VEX_LEN_F4_P_2
) },
4244 { VEX_LEN_TABLE (VEX_LEN_F5_P_2
) },
4251 { VEX_LEN_TABLE (VEX_LEN_F6_P_2
) },
4258 { VEX_LEN_TABLE (VEX_LEN_F7_P_2
) },
4265 { VEX_LEN_TABLE (VEX_LEN_F8_P_2
) },
4272 { VEX_LEN_TABLE (VEX_LEN_F9_P_2
) },
4279 { VEX_LEN_TABLE (VEX_LEN_FA_P_2
) },
4286 { VEX_LEN_TABLE (VEX_LEN_FB_P_2
) },
4293 { VEX_LEN_TABLE (VEX_LEN_FC_P_2
) },
4300 { VEX_LEN_TABLE (VEX_LEN_FD_P_2
) },
4307 { VEX_LEN_TABLE (VEX_LEN_FE_P_2
) },
4310 /* PREFIX_VEX_3800 */
4314 { VEX_LEN_TABLE (VEX_LEN_3800_P_2
) },
4317 /* PREFIX_VEX_3801 */
4321 { VEX_LEN_TABLE (VEX_LEN_3801_P_2
) },
4324 /* PREFIX_VEX_3802 */
4328 { VEX_LEN_TABLE (VEX_LEN_3802_P_2
) },
4331 /* PREFIX_VEX_3803 */
4335 { VEX_LEN_TABLE (VEX_LEN_3803_P_2
) },
4338 /* PREFIX_VEX_3804 */
4342 { VEX_LEN_TABLE (VEX_LEN_3804_P_2
) },
4345 /* PREFIX_VEX_3805 */
4349 { VEX_LEN_TABLE (VEX_LEN_3805_P_2
) },
4352 /* PREFIX_VEX_3806 */
4356 { VEX_LEN_TABLE (VEX_LEN_3806_P_2
) },
4359 /* PREFIX_VEX_3807 */
4363 { VEX_LEN_TABLE (VEX_LEN_3807_P_2
) },
4366 /* PREFIX_VEX_3808 */
4370 { VEX_LEN_TABLE (VEX_LEN_3808_P_2
) },
4373 /* PREFIX_VEX_3809 */
4377 { VEX_LEN_TABLE (VEX_LEN_3809_P_2
) },
4380 /* PREFIX_VEX_380A */
4384 { VEX_LEN_TABLE (VEX_LEN_380A_P_2
) },
4387 /* PREFIX_VEX_380B */
4391 { VEX_LEN_TABLE (VEX_LEN_380B_P_2
) },
4394 /* PREFIX_VEX_380C */
4398 { VEX_W_TABLE (VEX_W_380C_P_2
) },
4401 /* PREFIX_VEX_380D */
4405 { VEX_W_TABLE (VEX_W_380D_P_2
) },
4408 /* PREFIX_VEX_380E */
4412 { VEX_W_TABLE (VEX_W_380E_P_2
) },
4415 /* PREFIX_VEX_380F */
4419 { VEX_W_TABLE (VEX_W_380F_P_2
) },
4422 /* PREFIX_VEX_3817 */
4426 { VEX_W_TABLE (VEX_W_3817_P_2
) },
4429 /* PREFIX_VEX_3818 */
4433 { MOD_TABLE (MOD_VEX_3818_PREFIX_2
) },
4436 /* PREFIX_VEX_3819 */
4440 { MOD_TABLE (MOD_VEX_3819_PREFIX_2
) },
4443 /* PREFIX_VEX_381A */
4447 { MOD_TABLE (MOD_VEX_381A_PREFIX_2
) },
4450 /* PREFIX_VEX_381C */
4454 { VEX_LEN_TABLE (VEX_LEN_381C_P_2
) },
4457 /* PREFIX_VEX_381D */
4461 { VEX_LEN_TABLE (VEX_LEN_381D_P_2
) },
4464 /* PREFIX_VEX_381E */
4468 { VEX_LEN_TABLE (VEX_LEN_381E_P_2
) },
4471 /* PREFIX_VEX_3820 */
4475 { VEX_LEN_TABLE (VEX_LEN_3820_P_2
) },
4478 /* PREFIX_VEX_3821 */
4482 { VEX_LEN_TABLE (VEX_LEN_3821_P_2
) },
4485 /* PREFIX_VEX_3822 */
4489 { VEX_LEN_TABLE (VEX_LEN_3822_P_2
) },
4492 /* PREFIX_VEX_3823 */
4496 { VEX_LEN_TABLE (VEX_LEN_3823_P_2
) },
4499 /* PREFIX_VEX_3824 */
4503 { VEX_LEN_TABLE (VEX_LEN_3824_P_2
) },
4506 /* PREFIX_VEX_3825 */
4510 { VEX_LEN_TABLE (VEX_LEN_3825_P_2
) },
4513 /* PREFIX_VEX_3828 */
4517 { VEX_LEN_TABLE (VEX_LEN_3828_P_2
) },
4520 /* PREFIX_VEX_3829 */
4524 { VEX_LEN_TABLE (VEX_LEN_3829_P_2
) },
4527 /* PREFIX_VEX_382A */
4531 { MOD_TABLE (MOD_VEX_382A_PREFIX_2
) },
4534 /* PREFIX_VEX_382B */
4538 { VEX_LEN_TABLE (VEX_LEN_382B_P_2
) },
4541 /* PREFIX_VEX_382C */
4545 { MOD_TABLE (MOD_VEX_382C_PREFIX_2
) },
4548 /* PREFIX_VEX_382D */
4552 { MOD_TABLE (MOD_VEX_382D_PREFIX_2
) },
4555 /* PREFIX_VEX_382E */
4559 { MOD_TABLE (MOD_VEX_382E_PREFIX_2
) },
4562 /* PREFIX_VEX_382F */
4566 { MOD_TABLE (MOD_VEX_382F_PREFIX_2
) },
4569 /* PREFIX_VEX_3830 */
4573 { VEX_LEN_TABLE (VEX_LEN_3830_P_2
) },
4576 /* PREFIX_VEX_3831 */
4580 { VEX_LEN_TABLE (VEX_LEN_3831_P_2
) },
4583 /* PREFIX_VEX_3832 */
4587 { VEX_LEN_TABLE (VEX_LEN_3832_P_2
) },
4590 /* PREFIX_VEX_3833 */
4594 { VEX_LEN_TABLE (VEX_LEN_3833_P_2
) },
4597 /* PREFIX_VEX_3834 */
4601 { VEX_LEN_TABLE (VEX_LEN_3834_P_2
) },
4604 /* PREFIX_VEX_3835 */
4608 { VEX_LEN_TABLE (VEX_LEN_3835_P_2
) },
4611 /* PREFIX_VEX_3837 */
4615 { VEX_LEN_TABLE (VEX_LEN_3837_P_2
) },
4618 /* PREFIX_VEX_3838 */
4622 { VEX_LEN_TABLE (VEX_LEN_3838_P_2
) },
4625 /* PREFIX_VEX_3839 */
4629 { VEX_LEN_TABLE (VEX_LEN_3839_P_2
) },
4632 /* PREFIX_VEX_383A */
4636 { VEX_LEN_TABLE (VEX_LEN_383A_P_2
) },
4639 /* PREFIX_VEX_383B */
4643 { VEX_LEN_TABLE (VEX_LEN_383B_P_2
) },
4646 /* PREFIX_VEX_383C */
4650 { VEX_LEN_TABLE (VEX_LEN_383C_P_2
) },
4653 /* PREFIX_VEX_383D */
4657 { VEX_LEN_TABLE (VEX_LEN_383D_P_2
) },
4660 /* PREFIX_VEX_383E */
4664 { VEX_LEN_TABLE (VEX_LEN_383E_P_2
) },
4667 /* PREFIX_VEX_383F */
4671 { VEX_LEN_TABLE (VEX_LEN_383F_P_2
) },
4674 /* PREFIX_VEX_3840 */
4678 { VEX_LEN_TABLE (VEX_LEN_3840_P_2
) },
4681 /* PREFIX_VEX_3841 */
4685 { VEX_LEN_TABLE (VEX_LEN_3841_P_2
) },
4688 /* PREFIX_VEX_3896 */
4692 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
4695 /* PREFIX_VEX_3897 */
4699 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
4702 /* PREFIX_VEX_3898 */
4706 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
4709 /* PREFIX_VEX_3899 */
4713 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4716 /* PREFIX_VEX_389A */
4720 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
4723 /* PREFIX_VEX_389B */
4727 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4730 /* PREFIX_VEX_389C */
4734 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
4737 /* PREFIX_VEX_389D */
4741 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4744 /* PREFIX_VEX_389E */
4748 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
4751 /* PREFIX_VEX_389F */
4755 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4758 /* PREFIX_VEX_38A6 */
4762 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
4766 /* PREFIX_VEX_38A7 */
4770 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
4773 /* PREFIX_VEX_38A8 */
4777 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
4780 /* PREFIX_VEX_38A9 */
4784 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4787 /* PREFIX_VEX_38AA */
4791 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
4794 /* PREFIX_VEX_38AB */
4798 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4801 /* PREFIX_VEX_38AC */
4805 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
4808 /* PREFIX_VEX_38AD */
4812 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4815 /* PREFIX_VEX_38AE */
4819 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
4822 /* PREFIX_VEX_38AF */
4826 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4829 /* PREFIX_VEX_38B6 */
4833 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
4836 /* PREFIX_VEX_38B7 */
4840 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
4843 /* PREFIX_VEX_38B8 */
4847 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
4850 /* PREFIX_VEX_38B9 */
4854 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4857 /* PREFIX_VEX_38BA */
4861 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
4864 /* PREFIX_VEX_38BB */
4868 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4871 /* PREFIX_VEX_38BC */
4875 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
4878 /* PREFIX_VEX_38BD */
4882 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4885 /* PREFIX_VEX_38BE */
4889 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
4892 /* PREFIX_VEX_38BF */
4896 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
4899 /* PREFIX_VEX_38DB */
4903 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2
) },
4906 /* PREFIX_VEX_38DC */
4910 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2
) },
4913 /* PREFIX_VEX_38DD */
4917 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2
) },
4920 /* PREFIX_VEX_38DE */
4924 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2
) },
4927 /* PREFIX_VEX_38DF */
4931 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2
) },
4934 /* PREFIX_VEX_3A04 */
4938 { VEX_W_TABLE (VEX_W_3A04_P_2
) },
4941 /* PREFIX_VEX_3A05 */
4945 { VEX_W_TABLE (VEX_W_3A05_P_2
) },
4948 /* PREFIX_VEX_3A06 */
4952 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2
) },
4955 /* PREFIX_VEX_3A08 */
4959 { VEX_W_TABLE (VEX_W_3A08_P_2
) },
4962 /* PREFIX_VEX_3A09 */
4966 { VEX_W_TABLE (VEX_W_3A09_P_2
) },
4969 /* PREFIX_VEX_3A0A */
4973 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2
) },
4976 /* PREFIX_VEX_3A0B */
4980 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2
) },
4983 /* PREFIX_VEX_3A0C */
4987 { VEX_W_TABLE (VEX_W_3A0C_P_2
) },
4990 /* PREFIX_VEX_3A0D */
4994 { VEX_W_TABLE (VEX_W_3A0D_P_2
) },
4997 /* PREFIX_VEX_3A0E */
5001 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2
) },
5004 /* PREFIX_VEX_3A0F */
5008 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2
) },
5011 /* PREFIX_VEX_3A14 */
5015 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2
) },
5018 /* PREFIX_VEX_3A15 */
5022 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2
) },
5025 /* PREFIX_VEX_3A16 */
5029 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2
) },
5032 /* PREFIX_VEX_3A17 */
5036 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2
) },
5039 /* PREFIX_VEX_3A18 */
5043 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2
) },
5046 /* PREFIX_VEX_3A19 */
5050 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2
) },
5053 /* PREFIX_VEX_3A20 */
5057 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2
) },
5060 /* PREFIX_VEX_3A21 */
5064 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2
) },
5067 /* PREFIX_VEX_3A22 */
5071 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2
) },
5074 /* PREFIX_VEX_3A40 */
5078 { VEX_W_TABLE (VEX_W_3A40_P_2
) },
5081 /* PREFIX_VEX_3A41 */
5085 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2
) },
5088 /* PREFIX_VEX_3A42 */
5092 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2
) },
5095 /* PREFIX_VEX_3A44 */
5099 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2
) },
5102 /* PREFIX_VEX_3A48 */
5106 { VEX_W_TABLE (VEX_W_3A48_P_2
) },
5109 /* PREFIX_VEX_3A49 */
5113 { VEX_W_TABLE (VEX_W_3A49_P_2
) },
5116 /* PREFIX_VEX_3A4A */
5120 { VEX_W_TABLE (VEX_W_3A4A_P_2
) },
5123 /* PREFIX_VEX_3A4B */
5127 { VEX_W_TABLE (VEX_W_3A4B_P_2
) },
5130 /* PREFIX_VEX_3A4C */
5134 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2
) },
5137 /* PREFIX_VEX_3A5C */
5141 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5144 /* PREFIX_VEX_3A5D */
5148 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5151 /* PREFIX_VEX_3A5E */
5155 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5158 /* PREFIX_VEX_3A5F */
5162 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5165 /* PREFIX_VEX_3A60 */
5169 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2
) },
5173 /* PREFIX_VEX_3A61 */
5177 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2
) },
5180 /* PREFIX_VEX_3A62 */
5184 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2
) },
5187 /* PREFIX_VEX_3A63 */
5191 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2
) },
5194 /* PREFIX_VEX_3A68 */
5198 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5201 /* PREFIX_VEX_3A69 */
5205 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5208 /* PREFIX_VEX_3A6A */
5212 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2
) },
5215 /* PREFIX_VEX_3A6B */
5219 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2
) },
5222 /* PREFIX_VEX_3A6C */
5226 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5229 /* PREFIX_VEX_3A6D */
5233 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5236 /* PREFIX_VEX_3A6E */
5240 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2
) },
5243 /* PREFIX_VEX_3A6F */
5247 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2
) },
5250 /* PREFIX_VEX_3A78 */
5254 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5257 /* PREFIX_VEX_3A79 */
5261 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5264 /* PREFIX_VEX_3A7A */
5268 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2
) },
5271 /* PREFIX_VEX_3A7B */
5275 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2
) },
5278 /* PREFIX_VEX_3A7C */
5282 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5286 /* PREFIX_VEX_3A7D */
5290 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
5293 /* PREFIX_VEX_3A7E */
5297 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2
) },
5300 /* PREFIX_VEX_3A7F */
5304 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2
) },
5307 /* PREFIX_VEX_3ADF */
5311 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2
) },
5315 static const struct dis386 x86_64_table
[][2] = {
5318 { "push{T|}", { es
} },
5323 { "pop{T|}", { es
} },
5328 { "push{T|}", { cs
} },
5333 { "push{T|}", { ss
} },
5338 { "pop{T|}", { ss
} },
5343 { "push{T|}", { ds
} },
5348 { "pop{T|}", { ds
} },
5373 { "pusha{P|}", { XX
} },
5378 { "popa{P|}", { XX
} },
5383 { MOD_TABLE (MOD_62_32BIT
) },
5388 { "arpl", { Ew
, Gw
} },
5389 { "movs{lq|xd}", { Gv
, Ed
} },
5394 { "ins{R|}", { Yzr
, indirDX
} },
5395 { "ins{G|}", { Yzr
, indirDX
} },
5400 { "outs{R|}", { indirDXr
, Xz
} },
5401 { "outs{G|}", { indirDXr
, Xz
} },
5406 { "Jcall{T|}", { Ap
} },
5411 { MOD_TABLE (MOD_C4_32BIT
) },
5412 { VEX_C4_TABLE (VEX_0F
) },
5417 { MOD_TABLE (MOD_C5_32BIT
) },
5418 { VEX_C5_TABLE (VEX_0F
) },
5438 { "Jjmp{T|}", { Ap
} },
5441 /* X86_64_0F01_REG_0 */
5443 { "sgdt{Q|IQ}", { M
} },
5447 /* X86_64_0F01_REG_1 */
5449 { "sidt{Q|IQ}", { M
} },
5453 /* X86_64_0F01_REG_2 */
5455 { "lgdt{Q|Q}", { M
} },
5459 /* X86_64_0F01_REG_3 */
5461 { "lidt{Q|Q}", { M
} },
5466 static const struct dis386 three_byte_table
[][256] = {
5468 /* THREE_BYTE_0F38 */
5471 { "pshufb", { MX
, EM
} },
5472 { "phaddw", { MX
, EM
} },
5473 { "phaddd", { MX
, EM
} },
5474 { "phaddsw", { MX
, EM
} },
5475 { "pmaddubsw", { MX
, EM
} },
5476 { "phsubw", { MX
, EM
} },
5477 { "phsubd", { MX
, EM
} },
5478 { "phsubsw", { MX
, EM
} },
5480 { "psignb", { MX
, EM
} },
5481 { "psignw", { MX
, EM
} },
5482 { "psignd", { MX
, EM
} },
5483 { "pmulhrsw", { MX
, EM
} },
5489 { PREFIX_TABLE (PREFIX_0F3810
) },
5493 { PREFIX_TABLE (PREFIX_0F3814
) },
5494 { PREFIX_TABLE (PREFIX_0F3815
) },
5496 { PREFIX_TABLE (PREFIX_0F3817
) },
5502 { "pabsb", { MX
, EM
} },
5503 { "pabsw", { MX
, EM
} },
5504 { "pabsd", { MX
, EM
} },
5507 { PREFIX_TABLE (PREFIX_0F3820
) },
5508 { PREFIX_TABLE (PREFIX_0F3821
) },
5509 { PREFIX_TABLE (PREFIX_0F3822
) },
5510 { PREFIX_TABLE (PREFIX_0F3823
) },
5511 { PREFIX_TABLE (PREFIX_0F3824
) },
5512 { PREFIX_TABLE (PREFIX_0F3825
) },
5516 { PREFIX_TABLE (PREFIX_0F3828
) },
5517 { PREFIX_TABLE (PREFIX_0F3829
) },
5518 { PREFIX_TABLE (PREFIX_0F382A
) },
5519 { PREFIX_TABLE (PREFIX_0F382B
) },
5525 { PREFIX_TABLE (PREFIX_0F3830
) },
5526 { PREFIX_TABLE (PREFIX_0F3831
) },
5527 { PREFIX_TABLE (PREFIX_0F3832
) },
5528 { PREFIX_TABLE (PREFIX_0F3833
) },
5529 { PREFIX_TABLE (PREFIX_0F3834
) },
5530 { PREFIX_TABLE (PREFIX_0F3835
) },
5532 { PREFIX_TABLE (PREFIX_0F3837
) },
5534 { PREFIX_TABLE (PREFIX_0F3838
) },
5535 { PREFIX_TABLE (PREFIX_0F3839
) },
5536 { PREFIX_TABLE (PREFIX_0F383A
) },
5537 { PREFIX_TABLE (PREFIX_0F383B
) },
5538 { PREFIX_TABLE (PREFIX_0F383C
) },
5539 { PREFIX_TABLE (PREFIX_0F383D
) },
5540 { PREFIX_TABLE (PREFIX_0F383E
) },
5541 { PREFIX_TABLE (PREFIX_0F383F
) },
5543 { PREFIX_TABLE (PREFIX_0F3840
) },
5544 { PREFIX_TABLE (PREFIX_0F3841
) },
5615 { PREFIX_TABLE (PREFIX_0F3880
) },
5616 { PREFIX_TABLE (PREFIX_0F3881
) },
5717 { PREFIX_TABLE (PREFIX_0F38DB
) },
5718 { PREFIX_TABLE (PREFIX_0F38DC
) },
5719 { PREFIX_TABLE (PREFIX_0F38DD
) },
5720 { PREFIX_TABLE (PREFIX_0F38DE
) },
5721 { PREFIX_TABLE (PREFIX_0F38DF
) },
5741 { PREFIX_TABLE (PREFIX_0F38F0
) },
5742 { PREFIX_TABLE (PREFIX_0F38F1
) },
5759 /* THREE_BYTE_0F3A */
5771 { PREFIX_TABLE (PREFIX_0F3A08
) },
5772 { PREFIX_TABLE (PREFIX_0F3A09
) },
5773 { PREFIX_TABLE (PREFIX_0F3A0A
) },
5774 { PREFIX_TABLE (PREFIX_0F3A0B
) },
5775 { PREFIX_TABLE (PREFIX_0F3A0C
) },
5776 { PREFIX_TABLE (PREFIX_0F3A0D
) },
5777 { PREFIX_TABLE (PREFIX_0F3A0E
) },
5778 { "palignr", { MX
, EM
, Ib
} },
5784 { PREFIX_TABLE (PREFIX_0F3A14
) },
5785 { PREFIX_TABLE (PREFIX_0F3A15
) },
5786 { PREFIX_TABLE (PREFIX_0F3A16
) },
5787 { PREFIX_TABLE (PREFIX_0F3A17
) },
5798 { PREFIX_TABLE (PREFIX_0F3A20
) },
5799 { PREFIX_TABLE (PREFIX_0F3A21
) },
5800 { PREFIX_TABLE (PREFIX_0F3A22
) },
5834 { PREFIX_TABLE (PREFIX_0F3A40
) },
5835 { PREFIX_TABLE (PREFIX_0F3A41
) },
5836 { PREFIX_TABLE (PREFIX_0F3A42
) },
5838 { PREFIX_TABLE (PREFIX_0F3A44
) },
5870 { PREFIX_TABLE (PREFIX_0F3A60
) },
5871 { PREFIX_TABLE (PREFIX_0F3A61
) },
5872 { PREFIX_TABLE (PREFIX_0F3A62
) },
5873 { PREFIX_TABLE (PREFIX_0F3A63
) },
6012 { PREFIX_TABLE (PREFIX_0F3ADF
) },
6051 /* THREE_BYTE_0F7A */
6090 { "ptest", { XX
} },
6127 { "phaddbw", { XM
, EXq
} },
6128 { "phaddbd", { XM
, EXq
} },
6129 { "phaddbq", { XM
, EXq
} },
6132 { "phaddwd", { XM
, EXq
} },
6133 { "phaddwq", { XM
, EXq
} },
6138 { "phadddq", { XM
, EXq
} },
6145 { "phaddubw", { XM
, EXq
} },
6146 { "phaddubd", { XM
, EXq
} },
6147 { "phaddubq", { XM
, EXq
} },
6150 { "phadduwd", { XM
, EXq
} },
6151 { "phadduwq", { XM
, EXq
} },
6156 { "phaddudq", { XM
, EXq
} },
6163 { "phsubbw", { XM
, EXq
} },
6164 { "phsubbd", { XM
, EXq
} },
6165 { "phsubbq", { XM
, EXq
} },
6344 static const struct dis386 xop_table
[][256] = {
6497 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6498 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6499 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6507 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6508 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6515 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6516 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6517 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6525 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6526 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6530 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6531 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6534 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6552 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6564 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
6565 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
6566 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
6567 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
6577 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
6578 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
6579 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
6580 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
6613 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
6614 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
6615 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
6616 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
6659 { REG_TABLE (REG_XOP_LWPCB
) },
6783 { VEX_LEN_TABLE (VEX_LEN_XOP_09_80
) },
6784 { VEX_LEN_TABLE (VEX_LEN_XOP_09_81
) },
6785 { "vfrczss", { XM
, EXd
} },
6786 { "vfrczsd", { XM
, EXq
} },
6801 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6802 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6803 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
6804 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6805 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
6806 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6807 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
6808 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6810 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
6811 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
6812 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
6813 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
6856 { "vphaddbw", { XM
, EXxmm
} },
6857 { "vphaddbd", { XM
, EXxmm
} },
6858 { "vphaddbq", { XM
, EXxmm
} },
6861 { "vphaddwd", { XM
, EXxmm
} },
6862 { "vphaddwq", { XM
, EXxmm
} },
6867 { "vphadddq", { XM
, EXxmm
} },
6874 { "vphaddubw", { XM
, EXxmm
} },
6875 { "vphaddubd", { XM
, EXxmm
} },
6876 { "vphaddubq", { XM
, EXxmm
} },
6879 { "vphadduwd", { XM
, EXxmm
} },
6880 { "vphadduwq", { XM
, EXxmm
} },
6885 { "vphaddudq", { XM
, EXxmm
} },
6892 { "vphsubbw", { XM
, EXxmm
} },
6893 { "vphsubwd", { XM
, EXxmm
} },
6894 { "vphsubdq", { XM
, EXxmm
} },
6950 { REG_TABLE (REG_XOP_LWP
) },
7220 static const struct dis386 vex_table
[][256] = {
7242 { PREFIX_TABLE (PREFIX_VEX_10
) },
7243 { PREFIX_TABLE (PREFIX_VEX_11
) },
7244 { PREFIX_TABLE (PREFIX_VEX_12
) },
7245 { MOD_TABLE (MOD_VEX_13
) },
7246 { VEX_W_TABLE (VEX_W_14
) },
7247 { VEX_W_TABLE (VEX_W_15
) },
7248 { PREFIX_TABLE (PREFIX_VEX_16
) },
7249 { MOD_TABLE (MOD_VEX_17
) },
7269 { VEX_W_TABLE (VEX_W_28
) },
7270 { VEX_W_TABLE (VEX_W_29
) },
7271 { PREFIX_TABLE (PREFIX_VEX_2A
) },
7272 { MOD_TABLE (MOD_VEX_2B
) },
7273 { PREFIX_TABLE (PREFIX_VEX_2C
) },
7274 { PREFIX_TABLE (PREFIX_VEX_2D
) },
7275 { PREFIX_TABLE (PREFIX_VEX_2E
) },
7276 { PREFIX_TABLE (PREFIX_VEX_2F
) },
7314 { MOD_TABLE (MOD_VEX_50
) },
7315 { PREFIX_TABLE (PREFIX_VEX_51
) },
7316 { PREFIX_TABLE (PREFIX_VEX_52
) },
7317 { PREFIX_TABLE (PREFIX_VEX_53
) },
7318 { "vandpX", { XM
, Vex
, EXx
} },
7319 { "vandnpX", { XM
, Vex
, EXx
} },
7320 { "vorpX", { XM
, Vex
, EXx
} },
7321 { "vxorpX", { XM
, Vex
, EXx
} },
7323 { PREFIX_TABLE (PREFIX_VEX_58
) },
7324 { PREFIX_TABLE (PREFIX_VEX_59
) },
7325 { PREFIX_TABLE (PREFIX_VEX_5A
) },
7326 { PREFIX_TABLE (PREFIX_VEX_5B
) },
7327 { PREFIX_TABLE (PREFIX_VEX_5C
) },
7328 { PREFIX_TABLE (PREFIX_VEX_5D
) },
7329 { PREFIX_TABLE (PREFIX_VEX_5E
) },
7330 { PREFIX_TABLE (PREFIX_VEX_5F
) },
7332 { PREFIX_TABLE (PREFIX_VEX_60
) },
7333 { PREFIX_TABLE (PREFIX_VEX_61
) },
7334 { PREFIX_TABLE (PREFIX_VEX_62
) },
7335 { PREFIX_TABLE (PREFIX_VEX_63
) },
7336 { PREFIX_TABLE (PREFIX_VEX_64
) },
7337 { PREFIX_TABLE (PREFIX_VEX_65
) },
7338 { PREFIX_TABLE (PREFIX_VEX_66
) },
7339 { PREFIX_TABLE (PREFIX_VEX_67
) },
7341 { PREFIX_TABLE (PREFIX_VEX_68
) },
7342 { PREFIX_TABLE (PREFIX_VEX_69
) },
7343 { PREFIX_TABLE (PREFIX_VEX_6A
) },
7344 { PREFIX_TABLE (PREFIX_VEX_6B
) },
7345 { PREFIX_TABLE (PREFIX_VEX_6C
) },
7346 { PREFIX_TABLE (PREFIX_VEX_6D
) },
7347 { PREFIX_TABLE (PREFIX_VEX_6E
) },
7348 { PREFIX_TABLE (PREFIX_VEX_6F
) },
7350 { PREFIX_TABLE (PREFIX_VEX_70
) },
7351 { REG_TABLE (REG_VEX_71
) },
7352 { REG_TABLE (REG_VEX_72
) },
7353 { REG_TABLE (REG_VEX_73
) },
7354 { PREFIX_TABLE (PREFIX_VEX_74
) },
7355 { PREFIX_TABLE (PREFIX_VEX_75
) },
7356 { PREFIX_TABLE (PREFIX_VEX_76
) },
7357 { PREFIX_TABLE (PREFIX_VEX_77
) },
7363 { PREFIX_TABLE (PREFIX_VEX_7C
) },
7364 { PREFIX_TABLE (PREFIX_VEX_7D
) },
7365 { PREFIX_TABLE (PREFIX_VEX_7E
) },
7366 { PREFIX_TABLE (PREFIX_VEX_7F
) },
7419 { REG_TABLE (REG_VEX_AE
) },
7442 { PREFIX_TABLE (PREFIX_VEX_C2
) },
7444 { PREFIX_TABLE (PREFIX_VEX_C4
) },
7445 { PREFIX_TABLE (PREFIX_VEX_C5
) },
7446 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
7458 { PREFIX_TABLE (PREFIX_VEX_D0
) },
7459 { PREFIX_TABLE (PREFIX_VEX_D1
) },
7460 { PREFIX_TABLE (PREFIX_VEX_D2
) },
7461 { PREFIX_TABLE (PREFIX_VEX_D3
) },
7462 { PREFIX_TABLE (PREFIX_VEX_D4
) },
7463 { PREFIX_TABLE (PREFIX_VEX_D5
) },
7464 { PREFIX_TABLE (PREFIX_VEX_D6
) },
7465 { PREFIX_TABLE (PREFIX_VEX_D7
) },
7467 { PREFIX_TABLE (PREFIX_VEX_D8
) },
7468 { PREFIX_TABLE (PREFIX_VEX_D9
) },
7469 { PREFIX_TABLE (PREFIX_VEX_DA
) },
7470 { PREFIX_TABLE (PREFIX_VEX_DB
) },
7471 { PREFIX_TABLE (PREFIX_VEX_DC
) },
7472 { PREFIX_TABLE (PREFIX_VEX_DD
) },
7473 { PREFIX_TABLE (PREFIX_VEX_DE
) },
7474 { PREFIX_TABLE (PREFIX_VEX_DF
) },
7476 { PREFIX_TABLE (PREFIX_VEX_E0
) },
7477 { PREFIX_TABLE (PREFIX_VEX_E1
) },
7478 { PREFIX_TABLE (PREFIX_VEX_E2
) },
7479 { PREFIX_TABLE (PREFIX_VEX_E3
) },
7480 { PREFIX_TABLE (PREFIX_VEX_E4
) },
7481 { PREFIX_TABLE (PREFIX_VEX_E5
) },
7482 { PREFIX_TABLE (PREFIX_VEX_E6
) },
7483 { PREFIX_TABLE (PREFIX_VEX_E7
) },
7485 { PREFIX_TABLE (PREFIX_VEX_E8
) },
7486 { PREFIX_TABLE (PREFIX_VEX_E9
) },
7487 { PREFIX_TABLE (PREFIX_VEX_EA
) },
7488 { PREFIX_TABLE (PREFIX_VEX_EB
) },
7489 { PREFIX_TABLE (PREFIX_VEX_EC
) },
7490 { PREFIX_TABLE (PREFIX_VEX_ED
) },
7491 { PREFIX_TABLE (PREFIX_VEX_EE
) },
7492 { PREFIX_TABLE (PREFIX_VEX_EF
) },
7494 { PREFIX_TABLE (PREFIX_VEX_F0
) },
7495 { PREFIX_TABLE (PREFIX_VEX_F1
) },
7496 { PREFIX_TABLE (PREFIX_VEX_F2
) },
7497 { PREFIX_TABLE (PREFIX_VEX_F3
) },
7498 { PREFIX_TABLE (PREFIX_VEX_F4
) },
7499 { PREFIX_TABLE (PREFIX_VEX_F5
) },
7500 { PREFIX_TABLE (PREFIX_VEX_F6
) },
7501 { PREFIX_TABLE (PREFIX_VEX_F7
) },
7503 { PREFIX_TABLE (PREFIX_VEX_F8
) },
7504 { PREFIX_TABLE (PREFIX_VEX_F9
) },
7505 { PREFIX_TABLE (PREFIX_VEX_FA
) },
7506 { PREFIX_TABLE (PREFIX_VEX_FB
) },
7507 { PREFIX_TABLE (PREFIX_VEX_FC
) },
7508 { PREFIX_TABLE (PREFIX_VEX_FD
) },
7509 { PREFIX_TABLE (PREFIX_VEX_FE
) },
7515 { PREFIX_TABLE (PREFIX_VEX_3800
) },
7516 { PREFIX_TABLE (PREFIX_VEX_3801
) },
7517 { PREFIX_TABLE (PREFIX_VEX_3802
) },
7518 { PREFIX_TABLE (PREFIX_VEX_3803
) },
7519 { PREFIX_TABLE (PREFIX_VEX_3804
) },
7520 { PREFIX_TABLE (PREFIX_VEX_3805
) },
7521 { PREFIX_TABLE (PREFIX_VEX_3806
) },
7522 { PREFIX_TABLE (PREFIX_VEX_3807
) },
7524 { PREFIX_TABLE (PREFIX_VEX_3808
) },
7525 { PREFIX_TABLE (PREFIX_VEX_3809
) },
7526 { PREFIX_TABLE (PREFIX_VEX_380A
) },
7527 { PREFIX_TABLE (PREFIX_VEX_380B
) },
7528 { PREFIX_TABLE (PREFIX_VEX_380C
) },
7529 { PREFIX_TABLE (PREFIX_VEX_380D
) },
7530 { PREFIX_TABLE (PREFIX_VEX_380E
) },
7531 { PREFIX_TABLE (PREFIX_VEX_380F
) },
7540 { PREFIX_TABLE (PREFIX_VEX_3817
) },
7542 { PREFIX_TABLE (PREFIX_VEX_3818
) },
7543 { PREFIX_TABLE (PREFIX_VEX_3819
) },
7544 { PREFIX_TABLE (PREFIX_VEX_381A
) },
7546 { PREFIX_TABLE (PREFIX_VEX_381C
) },
7547 { PREFIX_TABLE (PREFIX_VEX_381D
) },
7548 { PREFIX_TABLE (PREFIX_VEX_381E
) },
7551 { PREFIX_TABLE (PREFIX_VEX_3820
) },
7552 { PREFIX_TABLE (PREFIX_VEX_3821
) },
7553 { PREFIX_TABLE (PREFIX_VEX_3822
) },
7554 { PREFIX_TABLE (PREFIX_VEX_3823
) },
7555 { PREFIX_TABLE (PREFIX_VEX_3824
) },
7556 { PREFIX_TABLE (PREFIX_VEX_3825
) },
7560 { PREFIX_TABLE (PREFIX_VEX_3828
) },
7561 { PREFIX_TABLE (PREFIX_VEX_3829
) },
7562 { PREFIX_TABLE (PREFIX_VEX_382A
) },
7563 { PREFIX_TABLE (PREFIX_VEX_382B
) },
7564 { PREFIX_TABLE (PREFIX_VEX_382C
) },
7565 { PREFIX_TABLE (PREFIX_VEX_382D
) },
7566 { PREFIX_TABLE (PREFIX_VEX_382E
) },
7567 { PREFIX_TABLE (PREFIX_VEX_382F
) },
7569 { PREFIX_TABLE (PREFIX_VEX_3830
) },
7570 { PREFIX_TABLE (PREFIX_VEX_3831
) },
7571 { PREFIX_TABLE (PREFIX_VEX_3832
) },
7572 { PREFIX_TABLE (PREFIX_VEX_3833
) },
7573 { PREFIX_TABLE (PREFIX_VEX_3834
) },
7574 { PREFIX_TABLE (PREFIX_VEX_3835
) },
7576 { PREFIX_TABLE (PREFIX_VEX_3837
) },
7578 { PREFIX_TABLE (PREFIX_VEX_3838
) },
7579 { PREFIX_TABLE (PREFIX_VEX_3839
) },
7580 { PREFIX_TABLE (PREFIX_VEX_383A
) },
7581 { PREFIX_TABLE (PREFIX_VEX_383B
) },
7582 { PREFIX_TABLE (PREFIX_VEX_383C
) },
7583 { PREFIX_TABLE (PREFIX_VEX_383D
) },
7584 { PREFIX_TABLE (PREFIX_VEX_383E
) },
7585 { PREFIX_TABLE (PREFIX_VEX_383F
) },
7587 { PREFIX_TABLE (PREFIX_VEX_3840
) },
7588 { PREFIX_TABLE (PREFIX_VEX_3841
) },
7683 { PREFIX_TABLE (PREFIX_VEX_3896
) },
7684 { PREFIX_TABLE (PREFIX_VEX_3897
) },
7686 { PREFIX_TABLE (PREFIX_VEX_3898
) },
7687 { PREFIX_TABLE (PREFIX_VEX_3899
) },
7688 { PREFIX_TABLE (PREFIX_VEX_389A
) },
7689 { PREFIX_TABLE (PREFIX_VEX_389B
) },
7690 { PREFIX_TABLE (PREFIX_VEX_389C
) },
7691 { PREFIX_TABLE (PREFIX_VEX_389D
) },
7692 { PREFIX_TABLE (PREFIX_VEX_389E
) },
7693 { PREFIX_TABLE (PREFIX_VEX_389F
) },
7701 { PREFIX_TABLE (PREFIX_VEX_38A6
) },
7702 { PREFIX_TABLE (PREFIX_VEX_38A7
) },
7704 { PREFIX_TABLE (PREFIX_VEX_38A8
) },
7705 { PREFIX_TABLE (PREFIX_VEX_38A9
) },
7706 { PREFIX_TABLE (PREFIX_VEX_38AA
) },
7707 { PREFIX_TABLE (PREFIX_VEX_38AB
) },
7708 { PREFIX_TABLE (PREFIX_VEX_38AC
) },
7709 { PREFIX_TABLE (PREFIX_VEX_38AD
) },
7710 { PREFIX_TABLE (PREFIX_VEX_38AE
) },
7711 { PREFIX_TABLE (PREFIX_VEX_38AF
) },
7719 { PREFIX_TABLE (PREFIX_VEX_38B6
) },
7720 { PREFIX_TABLE (PREFIX_VEX_38B7
) },
7722 { PREFIX_TABLE (PREFIX_VEX_38B8
) },
7723 { PREFIX_TABLE (PREFIX_VEX_38B9
) },
7724 { PREFIX_TABLE (PREFIX_VEX_38BA
) },
7725 { PREFIX_TABLE (PREFIX_VEX_38BB
) },
7726 { PREFIX_TABLE (PREFIX_VEX_38BC
) },
7727 { PREFIX_TABLE (PREFIX_VEX_38BD
) },
7728 { PREFIX_TABLE (PREFIX_VEX_38BE
) },
7729 { PREFIX_TABLE (PREFIX_VEX_38BF
) },
7761 { PREFIX_TABLE (PREFIX_VEX_38DB
) },
7762 { PREFIX_TABLE (PREFIX_VEX_38DC
) },
7763 { PREFIX_TABLE (PREFIX_VEX_38DD
) },
7764 { PREFIX_TABLE (PREFIX_VEX_38DE
) },
7765 { PREFIX_TABLE (PREFIX_VEX_38DF
) },
7810 { PREFIX_TABLE (PREFIX_VEX_3A04
) },
7811 { PREFIX_TABLE (PREFIX_VEX_3A05
) },
7812 { PREFIX_TABLE (PREFIX_VEX_3A06
) },
7815 { PREFIX_TABLE (PREFIX_VEX_3A08
) },
7816 { PREFIX_TABLE (PREFIX_VEX_3A09
) },
7817 { PREFIX_TABLE (PREFIX_VEX_3A0A
) },
7818 { PREFIX_TABLE (PREFIX_VEX_3A0B
) },
7819 { PREFIX_TABLE (PREFIX_VEX_3A0C
) },
7820 { PREFIX_TABLE (PREFIX_VEX_3A0D
) },
7821 { PREFIX_TABLE (PREFIX_VEX_3A0E
) },
7822 { PREFIX_TABLE (PREFIX_VEX_3A0F
) },
7828 { PREFIX_TABLE (PREFIX_VEX_3A14
) },
7829 { PREFIX_TABLE (PREFIX_VEX_3A15
) },
7830 { PREFIX_TABLE (PREFIX_VEX_3A16
) },
7831 { PREFIX_TABLE (PREFIX_VEX_3A17
) },
7833 { PREFIX_TABLE (PREFIX_VEX_3A18
) },
7834 { PREFIX_TABLE (PREFIX_VEX_3A19
) },
7842 { PREFIX_TABLE (PREFIX_VEX_3A20
) },
7843 { PREFIX_TABLE (PREFIX_VEX_3A21
) },
7844 { PREFIX_TABLE (PREFIX_VEX_3A22
) },
7878 { PREFIX_TABLE (PREFIX_VEX_3A40
) },
7879 { PREFIX_TABLE (PREFIX_VEX_3A41
) },
7880 { PREFIX_TABLE (PREFIX_VEX_3A42
) },
7882 { PREFIX_TABLE (PREFIX_VEX_3A44
) },
7887 { PREFIX_TABLE (PREFIX_VEX_3A48
) },
7888 { PREFIX_TABLE (PREFIX_VEX_3A49
) },
7889 { PREFIX_TABLE (PREFIX_VEX_3A4A
) },
7890 { PREFIX_TABLE (PREFIX_VEX_3A4B
) },
7891 { PREFIX_TABLE (PREFIX_VEX_3A4C
) },
7909 { PREFIX_TABLE (PREFIX_VEX_3A5C
) },
7910 { PREFIX_TABLE (PREFIX_VEX_3A5D
) },
7911 { PREFIX_TABLE (PREFIX_VEX_3A5E
) },
7912 { PREFIX_TABLE (PREFIX_VEX_3A5F
) },
7914 { PREFIX_TABLE (PREFIX_VEX_3A60
) },
7915 { PREFIX_TABLE (PREFIX_VEX_3A61
) },
7916 { PREFIX_TABLE (PREFIX_VEX_3A62
) },
7917 { PREFIX_TABLE (PREFIX_VEX_3A63
) },
7923 { PREFIX_TABLE (PREFIX_VEX_3A68
) },
7924 { PREFIX_TABLE (PREFIX_VEX_3A69
) },
7925 { PREFIX_TABLE (PREFIX_VEX_3A6A
) },
7926 { PREFIX_TABLE (PREFIX_VEX_3A6B
) },
7927 { PREFIX_TABLE (PREFIX_VEX_3A6C
) },
7928 { PREFIX_TABLE (PREFIX_VEX_3A6D
) },
7929 { PREFIX_TABLE (PREFIX_VEX_3A6E
) },
7930 { PREFIX_TABLE (PREFIX_VEX_3A6F
) },
7941 { PREFIX_TABLE (PREFIX_VEX_3A78
) },
7942 { PREFIX_TABLE (PREFIX_VEX_3A79
) },
7943 { PREFIX_TABLE (PREFIX_VEX_3A7A
) },
7944 { PREFIX_TABLE (PREFIX_VEX_3A7B
) },
7945 { PREFIX_TABLE (PREFIX_VEX_3A7C
) },
7946 { PREFIX_TABLE (PREFIX_VEX_3A7D
) },
7947 { PREFIX_TABLE (PREFIX_VEX_3A7E
) },
7948 { PREFIX_TABLE (PREFIX_VEX_3A7F
) },
8056 { PREFIX_TABLE (PREFIX_VEX_3ADF
) },
8096 static const struct dis386 vex_len_table
[][2] = {
8097 /* VEX_LEN_10_P_1 */
8099 { VEX_W_TABLE (VEX_W_10_P_1
) },
8100 { VEX_W_TABLE (VEX_W_10_P_1
) },
8103 /* VEX_LEN_10_P_3 */
8105 { VEX_W_TABLE (VEX_W_10_P_3
) },
8106 { VEX_W_TABLE (VEX_W_10_P_3
) },
8109 /* VEX_LEN_11_P_1 */
8111 { VEX_W_TABLE (VEX_W_11_P_1
) },
8112 { VEX_W_TABLE (VEX_W_11_P_1
) },
8115 /* VEX_LEN_11_P_3 */
8117 { VEX_W_TABLE (VEX_W_11_P_3
) },
8118 { VEX_W_TABLE (VEX_W_11_P_3
) },
8121 /* VEX_LEN_12_P_0_M_0 */
8123 { VEX_W_TABLE (VEX_W_12_P_0_M_0
) },
8126 /* VEX_LEN_12_P_0_M_1 */
8128 { VEX_W_TABLE (VEX_W_12_P_0_M_1
) },
8131 /* VEX_LEN_12_P_2 */
8133 { VEX_W_TABLE (VEX_W_12_P_2
) },
8136 /* VEX_LEN_13_M_0 */
8138 { VEX_W_TABLE (VEX_W_13_M_0
) },
8141 /* VEX_LEN_16_P_0_M_0 */
8143 { VEX_W_TABLE (VEX_W_16_P_0_M_0
) },
8146 /* VEX_LEN_16_P_0_M_1 */
8148 { VEX_W_TABLE (VEX_W_16_P_0_M_1
) },
8151 /* VEX_LEN_16_P_2 */
8153 { VEX_W_TABLE (VEX_W_16_P_2
) },
8156 /* VEX_LEN_17_M_0 */
8158 { VEX_W_TABLE (VEX_W_17_M_0
) },
8161 /* VEX_LEN_2A_P_1 */
8163 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8164 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
8167 /* VEX_LEN_2A_P_3 */
8169 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8170 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
8173 /* VEX_LEN_2C_P_1 */
8175 { "vcvttss2siY", { Gv
, EXdScalar
} },
8176 { "vcvttss2siY", { Gv
, EXdScalar
} },
8179 /* VEX_LEN_2C_P_3 */
8181 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8182 { "vcvttsd2siY", { Gv
, EXqScalar
} },
8185 /* VEX_LEN_2D_P_1 */
8187 { "vcvtss2siY", { Gv
, EXdScalar
} },
8188 { "vcvtss2siY", { Gv
, EXdScalar
} },
8191 /* VEX_LEN_2D_P_3 */
8193 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8194 { "vcvtsd2siY", { Gv
, EXqScalar
} },
8197 /* VEX_LEN_2E_P_0 */
8199 { VEX_W_TABLE (VEX_W_2E_P_0
) },
8200 { VEX_W_TABLE (VEX_W_2E_P_0
) },
8203 /* VEX_LEN_2E_P_2 */
8205 { VEX_W_TABLE (VEX_W_2E_P_2
) },
8206 { VEX_W_TABLE (VEX_W_2E_P_2
) },
8209 /* VEX_LEN_2F_P_0 */
8211 { VEX_W_TABLE (VEX_W_2F_P_0
) },
8212 { VEX_W_TABLE (VEX_W_2F_P_0
) },
8215 /* VEX_LEN_2F_P_2 */
8217 { VEX_W_TABLE (VEX_W_2F_P_2
) },
8218 { VEX_W_TABLE (VEX_W_2F_P_2
) },
8221 /* VEX_LEN_51_P_1 */
8223 { VEX_W_TABLE (VEX_W_51_P_1
) },
8224 { VEX_W_TABLE (VEX_W_51_P_1
) },
8227 /* VEX_LEN_51_P_3 */
8229 { VEX_W_TABLE (VEX_W_51_P_3
) },
8230 { VEX_W_TABLE (VEX_W_51_P_3
) },
8233 /* VEX_LEN_52_P_1 */
8235 { VEX_W_TABLE (VEX_W_52_P_1
) },
8236 { VEX_W_TABLE (VEX_W_52_P_1
) },
8239 /* VEX_LEN_53_P_1 */
8241 { VEX_W_TABLE (VEX_W_53_P_1
) },
8242 { VEX_W_TABLE (VEX_W_53_P_1
) },
8245 /* VEX_LEN_58_P_1 */
8247 { VEX_W_TABLE (VEX_W_58_P_1
) },
8248 { VEX_W_TABLE (VEX_W_58_P_1
) },
8251 /* VEX_LEN_58_P_3 */
8253 { VEX_W_TABLE (VEX_W_58_P_3
) },
8254 { VEX_W_TABLE (VEX_W_58_P_3
) },
8257 /* VEX_LEN_59_P_1 */
8259 { VEX_W_TABLE (VEX_W_59_P_1
) },
8260 { VEX_W_TABLE (VEX_W_59_P_1
) },
8263 /* VEX_LEN_59_P_3 */
8265 { VEX_W_TABLE (VEX_W_59_P_3
) },
8266 { VEX_W_TABLE (VEX_W_59_P_3
) },
8269 /* VEX_LEN_5A_P_1 */
8271 { VEX_W_TABLE (VEX_W_5A_P_1
) },
8272 { VEX_W_TABLE (VEX_W_5A_P_1
) },
8275 /* VEX_LEN_5A_P_3 */
8277 { VEX_W_TABLE (VEX_W_5A_P_3
) },
8278 { VEX_W_TABLE (VEX_W_5A_P_3
) },
8281 /* VEX_LEN_5C_P_1 */
8283 { VEX_W_TABLE (VEX_W_5C_P_1
) },
8284 { VEX_W_TABLE (VEX_W_5C_P_1
) },
8287 /* VEX_LEN_5C_P_3 */
8289 { VEX_W_TABLE (VEX_W_5C_P_3
) },
8290 { VEX_W_TABLE (VEX_W_5C_P_3
) },
8293 /* VEX_LEN_5D_P_1 */
8295 { VEX_W_TABLE (VEX_W_5D_P_1
) },
8296 { VEX_W_TABLE (VEX_W_5D_P_1
) },
8299 /* VEX_LEN_5D_P_3 */
8301 { VEX_W_TABLE (VEX_W_5D_P_3
) },
8302 { VEX_W_TABLE (VEX_W_5D_P_3
) },
8305 /* VEX_LEN_5E_P_1 */
8307 { VEX_W_TABLE (VEX_W_5E_P_1
) },
8308 { VEX_W_TABLE (VEX_W_5E_P_1
) },
8311 /* VEX_LEN_5E_P_3 */
8313 { VEX_W_TABLE (VEX_W_5E_P_3
) },
8314 { VEX_W_TABLE (VEX_W_5E_P_3
) },
8317 /* VEX_LEN_5F_P_1 */
8319 { VEX_W_TABLE (VEX_W_5F_P_1
) },
8320 { VEX_W_TABLE (VEX_W_5F_P_1
) },
8323 /* VEX_LEN_5F_P_3 */
8325 { VEX_W_TABLE (VEX_W_5F_P_3
) },
8326 { VEX_W_TABLE (VEX_W_5F_P_3
) },
8329 /* VEX_LEN_60_P_2 */
8331 { VEX_W_TABLE (VEX_W_60_P_2
) },
8334 /* VEX_LEN_61_P_2 */
8336 { VEX_W_TABLE (VEX_W_61_P_2
) },
8339 /* VEX_LEN_62_P_2 */
8341 { VEX_W_TABLE (VEX_W_62_P_2
) },
8344 /* VEX_LEN_63_P_2 */
8346 { VEX_W_TABLE (VEX_W_63_P_2
) },
8349 /* VEX_LEN_64_P_2 */
8351 { VEX_W_TABLE (VEX_W_64_P_2
) },
8354 /* VEX_LEN_65_P_2 */
8356 { VEX_W_TABLE (VEX_W_65_P_2
) },
8359 /* VEX_LEN_66_P_2 */
8361 { VEX_W_TABLE (VEX_W_66_P_2
) },
8364 /* VEX_LEN_67_P_2 */
8366 { VEX_W_TABLE (VEX_W_67_P_2
) },
8369 /* VEX_LEN_68_P_2 */
8371 { VEX_W_TABLE (VEX_W_68_P_2
) },
8374 /* VEX_LEN_69_P_2 */
8376 { VEX_W_TABLE (VEX_W_69_P_2
) },
8379 /* VEX_LEN_6A_P_2 */
8381 { VEX_W_TABLE (VEX_W_6A_P_2
) },
8384 /* VEX_LEN_6B_P_2 */
8386 { VEX_W_TABLE (VEX_W_6B_P_2
) },
8389 /* VEX_LEN_6C_P_2 */
8391 { VEX_W_TABLE (VEX_W_6C_P_2
) },
8394 /* VEX_LEN_6D_P_2 */
8396 { VEX_W_TABLE (VEX_W_6D_P_2
) },
8399 /* VEX_LEN_6E_P_2 */
8401 { "vmovK", { XMScalar
, Edq
} },
8402 { "vmovK", { XMScalar
, Edq
} },
8405 /* VEX_LEN_70_P_1 */
8407 { VEX_W_TABLE (VEX_W_70_P_1
) },
8410 /* VEX_LEN_70_P_2 */
8412 { VEX_W_TABLE (VEX_W_70_P_2
) },
8415 /* VEX_LEN_70_P_3 */
8417 { VEX_W_TABLE (VEX_W_70_P_3
) },
8420 /* VEX_LEN_71_R_2_P_2 */
8422 { VEX_W_TABLE (VEX_W_71_R_2_P_2
) },
8425 /* VEX_LEN_71_R_4_P_2 */
8427 { VEX_W_TABLE (VEX_W_71_R_4_P_2
) },
8430 /* VEX_LEN_71_R_6_P_2 */
8432 { VEX_W_TABLE (VEX_W_71_R_6_P_2
) },
8435 /* VEX_LEN_72_R_2_P_2 */
8437 { VEX_W_TABLE (VEX_W_72_R_2_P_2
) },
8440 /* VEX_LEN_72_R_4_P_2 */
8442 { VEX_W_TABLE (VEX_W_72_R_4_P_2
) },
8445 /* VEX_LEN_72_R_6_P_2 */
8447 { VEX_W_TABLE (VEX_W_72_R_6_P_2
) },
8450 /* VEX_LEN_73_R_2_P_2 */
8452 { VEX_W_TABLE (VEX_W_73_R_2_P_2
) },
8455 /* VEX_LEN_73_R_3_P_2 */
8457 { VEX_W_TABLE (VEX_W_73_R_3_P_2
) },
8460 /* VEX_LEN_73_R_6_P_2 */
8462 { VEX_W_TABLE (VEX_W_73_R_6_P_2
) },
8465 /* VEX_LEN_73_R_7_P_2 */
8467 { VEX_W_TABLE (VEX_W_73_R_7_P_2
) },
8470 /* VEX_LEN_74_P_2 */
8472 { VEX_W_TABLE (VEX_W_74_P_2
) },
8475 /* VEX_LEN_75_P_2 */
8477 { VEX_W_TABLE (VEX_W_75_P_2
) },
8480 /* VEX_LEN_76_P_2 */
8482 { VEX_W_TABLE (VEX_W_76_P_2
) },
8485 /* VEX_LEN_7E_P_1 */
8487 { VEX_W_TABLE (VEX_W_7E_P_1
) },
8488 { VEX_W_TABLE (VEX_W_7E_P_1
) },
8491 /* VEX_LEN_7E_P_2 */
8493 { "vmovK", { Edq
, XMScalar
} },
8494 { "vmovK", { Edq
, XMScalar
} },
8497 /* VEX_LEN_AE_R_2_M_0 */
8499 { VEX_W_TABLE (VEX_W_AE_R_2_M_0
) },
8502 /* VEX_LEN_AE_R_3_M_0 */
8504 { VEX_W_TABLE (VEX_W_AE_R_3_M_0
) },
8507 /* VEX_LEN_C2_P_1 */
8509 { VEX_W_TABLE (VEX_W_C2_P_1
) },
8510 { VEX_W_TABLE (VEX_W_C2_P_1
) },
8513 /* VEX_LEN_C2_P_3 */
8515 { VEX_W_TABLE (VEX_W_C2_P_3
) },
8516 { VEX_W_TABLE (VEX_W_C2_P_3
) },
8519 /* VEX_LEN_C4_P_2 */
8521 { VEX_W_TABLE (VEX_W_C4_P_2
) },
8524 /* VEX_LEN_C5_P_2 */
8526 { VEX_W_TABLE (VEX_W_C5_P_2
) },
8529 /* VEX_LEN_D1_P_2 */
8531 { VEX_W_TABLE (VEX_W_D1_P_2
) },
8534 /* VEX_LEN_D2_P_2 */
8536 { VEX_W_TABLE (VEX_W_D2_P_2
) },
8539 /* VEX_LEN_D3_P_2 */
8541 { VEX_W_TABLE (VEX_W_D3_P_2
) },
8544 /* VEX_LEN_D4_P_2 */
8546 { VEX_W_TABLE (VEX_W_D4_P_2
) },
8549 /* VEX_LEN_D5_P_2 */
8551 { VEX_W_TABLE (VEX_W_D5_P_2
) },
8554 /* VEX_LEN_D6_P_2 */
8556 { VEX_W_TABLE (VEX_W_D6_P_2
) },
8557 { VEX_W_TABLE (VEX_W_D6_P_2
) },
8560 /* VEX_LEN_D7_P_2_M_1 */
8562 { VEX_W_TABLE (VEX_W_D7_P_2_M_1
) },
8565 /* VEX_LEN_D8_P_2 */
8567 { VEX_W_TABLE (VEX_W_D8_P_2
) },
8570 /* VEX_LEN_D9_P_2 */
8572 { VEX_W_TABLE (VEX_W_D9_P_2
) },
8575 /* VEX_LEN_DA_P_2 */
8577 { VEX_W_TABLE (VEX_W_DA_P_2
) },
8580 /* VEX_LEN_DB_P_2 */
8582 { VEX_W_TABLE (VEX_W_DB_P_2
) },
8585 /* VEX_LEN_DC_P_2 */
8587 { VEX_W_TABLE (VEX_W_DC_P_2
) },
8590 /* VEX_LEN_DD_P_2 */
8592 { VEX_W_TABLE (VEX_W_DD_P_2
) },
8595 /* VEX_LEN_DE_P_2 */
8597 { VEX_W_TABLE (VEX_W_DE_P_2
) },
8600 /* VEX_LEN_DF_P_2 */
8602 { VEX_W_TABLE (VEX_W_DF_P_2
) },
8605 /* VEX_LEN_E0_P_2 */
8607 { VEX_W_TABLE (VEX_W_E0_P_2
) },
8610 /* VEX_LEN_E1_P_2 */
8612 { VEX_W_TABLE (VEX_W_E1_P_2
) },
8615 /* VEX_LEN_E2_P_2 */
8617 { VEX_W_TABLE (VEX_W_E2_P_2
) },
8620 /* VEX_LEN_E3_P_2 */
8622 { VEX_W_TABLE (VEX_W_E3_P_2
) },
8625 /* VEX_LEN_E4_P_2 */
8627 { VEX_W_TABLE (VEX_W_E4_P_2
) },
8630 /* VEX_LEN_E5_P_2 */
8632 { VEX_W_TABLE (VEX_W_E5_P_2
) },
8635 /* VEX_LEN_E8_P_2 */
8637 { VEX_W_TABLE (VEX_W_E8_P_2
) },
8640 /* VEX_LEN_E9_P_2 */
8642 { VEX_W_TABLE (VEX_W_E9_P_2
) },
8645 /* VEX_LEN_EA_P_2 */
8647 { VEX_W_TABLE (VEX_W_EA_P_2
) },
8650 /* VEX_LEN_EB_P_2 */
8652 { VEX_W_TABLE (VEX_W_EB_P_2
) },
8655 /* VEX_LEN_EC_P_2 */
8657 { VEX_W_TABLE (VEX_W_EC_P_2
) },
8660 /* VEX_LEN_ED_P_2 */
8662 { VEX_W_TABLE (VEX_W_ED_P_2
) },
8665 /* VEX_LEN_EE_P_2 */
8667 { VEX_W_TABLE (VEX_W_EE_P_2
) },
8670 /* VEX_LEN_EF_P_2 */
8672 { VEX_W_TABLE (VEX_W_EF_P_2
) },
8675 /* VEX_LEN_F1_P_2 */
8677 { VEX_W_TABLE (VEX_W_F1_P_2
) },
8680 /* VEX_LEN_F2_P_2 */
8682 { VEX_W_TABLE (VEX_W_F2_P_2
) },
8685 /* VEX_LEN_F3_P_2 */
8687 { VEX_W_TABLE (VEX_W_F3_P_2
) },
8690 /* VEX_LEN_F4_P_2 */
8692 { VEX_W_TABLE (VEX_W_F4_P_2
) },
8695 /* VEX_LEN_F5_P_2 */
8697 { VEX_W_TABLE (VEX_W_F5_P_2
) },
8700 /* VEX_LEN_F6_P_2 */
8702 { VEX_W_TABLE (VEX_W_F6_P_2
) },
8705 /* VEX_LEN_F7_P_2 */
8707 { VEX_W_TABLE (VEX_W_F7_P_2
) },
8710 /* VEX_LEN_F8_P_2 */
8712 { VEX_W_TABLE (VEX_W_F8_P_2
) },
8715 /* VEX_LEN_F9_P_2 */
8717 { VEX_W_TABLE (VEX_W_F9_P_2
) },
8720 /* VEX_LEN_FA_P_2 */
8722 { VEX_W_TABLE (VEX_W_FA_P_2
) },
8725 /* VEX_LEN_FB_P_2 */
8727 { VEX_W_TABLE (VEX_W_FB_P_2
) },
8730 /* VEX_LEN_FC_P_2 */
8732 { VEX_W_TABLE (VEX_W_FC_P_2
) },
8735 /* VEX_LEN_FD_P_2 */
8737 { VEX_W_TABLE (VEX_W_FD_P_2
) },
8740 /* VEX_LEN_FE_P_2 */
8742 { VEX_W_TABLE (VEX_W_FE_P_2
) },
8745 /* VEX_LEN_3800_P_2 */
8747 { VEX_W_TABLE (VEX_W_3800_P_2
) },
8750 /* VEX_LEN_3801_P_2 */
8752 { VEX_W_TABLE (VEX_W_3801_P_2
) },
8755 /* VEX_LEN_3802_P_2 */
8757 { VEX_W_TABLE (VEX_W_3802_P_2
) },
8760 /* VEX_LEN_3803_P_2 */
8762 { VEX_W_TABLE (VEX_W_3803_P_2
) },
8765 /* VEX_LEN_3804_P_2 */
8767 { VEX_W_TABLE (VEX_W_3804_P_2
) },
8770 /* VEX_LEN_3805_P_2 */
8772 { VEX_W_TABLE (VEX_W_3805_P_2
) },
8775 /* VEX_LEN_3806_P_2 */
8777 { VEX_W_TABLE (VEX_W_3806_P_2
) },
8780 /* VEX_LEN_3807_P_2 */
8782 { VEX_W_TABLE (VEX_W_3807_P_2
) },
8785 /* VEX_LEN_3808_P_2 */
8787 { VEX_W_TABLE (VEX_W_3808_P_2
) },
8790 /* VEX_LEN_3809_P_2 */
8792 { VEX_W_TABLE (VEX_W_3809_P_2
) },
8795 /* VEX_LEN_380A_P_2 */
8797 { VEX_W_TABLE (VEX_W_380A_P_2
) },
8800 /* VEX_LEN_380B_P_2 */
8802 { VEX_W_TABLE (VEX_W_380B_P_2
) },
8805 /* VEX_LEN_3819_P_2_M_0 */
8808 { VEX_W_TABLE (VEX_W_3819_P_2_M_0
) },
8811 /* VEX_LEN_381A_P_2_M_0 */
8814 { VEX_W_TABLE (VEX_W_381A_P_2_M_0
) },
8817 /* VEX_LEN_381C_P_2 */
8819 { VEX_W_TABLE (VEX_W_381C_P_2
) },
8822 /* VEX_LEN_381D_P_2 */
8824 { VEX_W_TABLE (VEX_W_381D_P_2
) },
8827 /* VEX_LEN_381E_P_2 */
8829 { VEX_W_TABLE (VEX_W_381E_P_2
) },
8832 /* VEX_LEN_3820_P_2 */
8834 { VEX_W_TABLE (VEX_W_3820_P_2
) },
8837 /* VEX_LEN_3821_P_2 */
8839 { VEX_W_TABLE (VEX_W_3821_P_2
) },
8842 /* VEX_LEN_3822_P_2 */
8844 { VEX_W_TABLE (VEX_W_3822_P_2
) },
8847 /* VEX_LEN_3823_P_2 */
8849 { VEX_W_TABLE (VEX_W_3823_P_2
) },
8852 /* VEX_LEN_3824_P_2 */
8854 { VEX_W_TABLE (VEX_W_3824_P_2
) },
8857 /* VEX_LEN_3825_P_2 */
8859 { VEX_W_TABLE (VEX_W_3825_P_2
) },
8862 /* VEX_LEN_3828_P_2 */
8864 { VEX_W_TABLE (VEX_W_3828_P_2
) },
8867 /* VEX_LEN_3829_P_2 */
8869 { VEX_W_TABLE (VEX_W_3829_P_2
) },
8872 /* VEX_LEN_382A_P_2_M_0 */
8874 { VEX_W_TABLE (VEX_W_382A_P_2_M_0
) },
8877 /* VEX_LEN_382B_P_2 */
8879 { VEX_W_TABLE (VEX_W_382B_P_2
) },
8882 /* VEX_LEN_3830_P_2 */
8884 { VEX_W_TABLE (VEX_W_3830_P_2
) },
8887 /* VEX_LEN_3831_P_2 */
8889 { VEX_W_TABLE (VEX_W_3831_P_2
) },
8892 /* VEX_LEN_3832_P_2 */
8894 { VEX_W_TABLE (VEX_W_3832_P_2
) },
8897 /* VEX_LEN_3833_P_2 */
8899 { VEX_W_TABLE (VEX_W_3833_P_2
) },
8902 /* VEX_LEN_3834_P_2 */
8904 { VEX_W_TABLE (VEX_W_3834_P_2
) },
8907 /* VEX_LEN_3835_P_2 */
8909 { VEX_W_TABLE (VEX_W_3835_P_2
) },
8912 /* VEX_LEN_3837_P_2 */
8914 { VEX_W_TABLE (VEX_W_3837_P_2
) },
8917 /* VEX_LEN_3838_P_2 */
8919 { VEX_W_TABLE (VEX_W_3838_P_2
) },
8922 /* VEX_LEN_3839_P_2 */
8924 { VEX_W_TABLE (VEX_W_3839_P_2
) },
8927 /* VEX_LEN_383A_P_2 */
8929 { VEX_W_TABLE (VEX_W_383A_P_2
) },
8932 /* VEX_LEN_383B_P_2 */
8934 { VEX_W_TABLE (VEX_W_383B_P_2
) },
8937 /* VEX_LEN_383C_P_2 */
8939 { VEX_W_TABLE (VEX_W_383C_P_2
) },
8942 /* VEX_LEN_383D_P_2 */
8944 { VEX_W_TABLE (VEX_W_383D_P_2
) },
8947 /* VEX_LEN_383E_P_2 */
8949 { VEX_W_TABLE (VEX_W_383E_P_2
) },
8952 /* VEX_LEN_383F_P_2 */
8954 { VEX_W_TABLE (VEX_W_383F_P_2
) },
8957 /* VEX_LEN_3840_P_2 */
8959 { VEX_W_TABLE (VEX_W_3840_P_2
) },
8962 /* VEX_LEN_3841_P_2 */
8964 { VEX_W_TABLE (VEX_W_3841_P_2
) },
8967 /* VEX_LEN_38DB_P_2 */
8969 { VEX_W_TABLE (VEX_W_38DB_P_2
) },
8972 /* VEX_LEN_38DC_P_2 */
8974 { VEX_W_TABLE (VEX_W_38DC_P_2
) },
8977 /* VEX_LEN_38DD_P_2 */
8979 { VEX_W_TABLE (VEX_W_38DD_P_2
) },
8982 /* VEX_LEN_38DE_P_2 */
8984 { VEX_W_TABLE (VEX_W_38DE_P_2
) },
8987 /* VEX_LEN_38DF_P_2 */
8989 { VEX_W_TABLE (VEX_W_38DF_P_2
) },
8992 /* VEX_LEN_3A06_P_2 */
8995 { VEX_W_TABLE (VEX_W_3A06_P_2
) },
8998 /* VEX_LEN_3A0A_P_2 */
9000 { VEX_W_TABLE (VEX_W_3A0A_P_2
) },
9001 { VEX_W_TABLE (VEX_W_3A0A_P_2
) },
9004 /* VEX_LEN_3A0B_P_2 */
9006 { VEX_W_TABLE (VEX_W_3A0B_P_2
) },
9007 { VEX_W_TABLE (VEX_W_3A0B_P_2
) },
9010 /* VEX_LEN_3A0E_P_2 */
9012 { VEX_W_TABLE (VEX_W_3A0E_P_2
) },
9015 /* VEX_LEN_3A0F_P_2 */
9017 { VEX_W_TABLE (VEX_W_3A0F_P_2
) },
9020 /* VEX_LEN_3A14_P_2 */
9022 { VEX_W_TABLE (VEX_W_3A14_P_2
) },
9025 /* VEX_LEN_3A15_P_2 */
9027 { VEX_W_TABLE (VEX_W_3A15_P_2
) },
9030 /* VEX_LEN_3A16_P_2 */
9032 { "vpextrK", { Edq
, XM
, Ib
} },
9035 /* VEX_LEN_3A17_P_2 */
9037 { "vextractps", { Edqd
, XM
, Ib
} },
9040 /* VEX_LEN_3A18_P_2 */
9043 { VEX_W_TABLE (VEX_W_3A18_P_2
) },
9046 /* VEX_LEN_3A19_P_2 */
9049 { VEX_W_TABLE (VEX_W_3A19_P_2
) },
9052 /* VEX_LEN_3A20_P_2 */
9054 { VEX_W_TABLE (VEX_W_3A20_P_2
) },
9057 /* VEX_LEN_3A21_P_2 */
9059 { VEX_W_TABLE (VEX_W_3A21_P_2
) },
9062 /* VEX_LEN_3A22_P_2 */
9064 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9067 /* VEX_LEN_3A41_P_2 */
9069 { VEX_W_TABLE (VEX_W_3A41_P_2
) },
9072 /* VEX_LEN_3A42_P_2 */
9074 { VEX_W_TABLE (VEX_W_3A42_P_2
) },
9077 /* VEX_LEN_3A44_P_2 */
9079 { VEX_W_TABLE (VEX_W_3A44_P_2
) },
9082 /* VEX_LEN_3A4C_P_2 */
9084 { VEX_W_TABLE (VEX_W_3A4C_P_2
) },
9087 /* VEX_LEN_3A60_P_2 */
9089 { VEX_W_TABLE (VEX_W_3A60_P_2
) },
9092 /* VEX_LEN_3A61_P_2 */
9094 { VEX_W_TABLE (VEX_W_3A61_P_2
) },
9097 /* VEX_LEN_3A62_P_2 */
9099 { VEX_W_TABLE (VEX_W_3A62_P_2
) },
9102 /* VEX_LEN_3A63_P_2 */
9104 { VEX_W_TABLE (VEX_W_3A63_P_2
) },
9107 /* VEX_LEN_3A6A_P_2 */
9109 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9112 /* VEX_LEN_3A6B_P_2 */
9114 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9117 /* VEX_LEN_3A6E_P_2 */
9119 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9122 /* VEX_LEN_3A6F_P_2 */
9124 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9127 /* VEX_LEN_3A7A_P_2 */
9129 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9132 /* VEX_LEN_3A7B_P_2 */
9134 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9137 /* VEX_LEN_3A7E_P_2 */
9139 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9142 /* VEX_LEN_3A7F_P_2 */
9144 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9147 /* VEX_LEN_3ADF_P_2 */
9149 { VEX_W_TABLE (VEX_W_3ADF_P_2
) },
9152 /* VEX_LEN_XOP_09_80 */
9154 { "vfrczps", { XM
, EXxmm
} },
9155 { "vfrczps", { XM
, EXymmq
} },
9158 /* VEX_LEN_XOP_09_81 */
9160 { "vfrczpd", { XM
, EXxmm
} },
9161 { "vfrczpd", { XM
, EXymmq
} },
9165 static const struct dis386 vex_w_table
[][2] = {
9168 { "vmovups", { XM
, EXx
} },
9172 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9176 { "vmovupd", { XM
, EXx
} },
9180 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9184 { "vmovups", { EXxS
, XM
} },
9188 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9192 { "vmovupd", { EXxS
, XM
} },
9196 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9199 /* VEX_W_12_P_0_M_0 */
9200 { "vmovlps", { XM
, Vex128
, EXq
} },
9203 /* VEX_W_12_P_0_M_1 */
9204 { "vmovhlps", { XM
, Vex128
, EXq
} },
9208 { "vmovsldup", { XM
, EXx
} },
9212 { "vmovlpd", { XM
, Vex128
, EXq
} },
9216 { "vmovddup", { XM
, EXymmq
} },
9220 { "vmovlpX", { EXq
, XM
} },
9224 { "vunpcklpX", { XM
, Vex
, EXx
} },
9228 { "vunpckhpX", { XM
, Vex
, EXx
} },
9231 /* VEX_W_16_P_0_M_0 */
9232 { "vmovhps", { XM
, Vex128
, EXq
} },
9235 /* VEX_W_16_P_0_M_1 */
9236 { "vmovlhps", { XM
, Vex128
, EXq
} },
9240 { "vmovshdup", { XM
, EXx
} },
9244 { "vmovhpd", { XM
, Vex128
, EXq
} },
9248 { "vmovhpX", { EXq
, XM
} },
9252 { "vmovapX", { XM
, EXx
} },
9256 { "vmovapX", { EXxS
, XM
} },
9260 { "vmovntpX", { Mx
, XM
} },
9264 { "vucomiss", { XMScalar
, EXdScalar
} },
9268 { "vucomisd", { XMScalar
, EXqScalar
} },
9272 { "vcomiss", { XMScalar
, EXdScalar
} },
9276 { "vcomisd", { XMScalar
, EXqScalar
} },
9280 { "vmovmskpX", { Gdq
, XS
} },
9284 { "vsqrtps", { XM
, EXx
} },
9288 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9292 { "vsqrtpd", { XM
, EXx
} },
9296 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
9300 { "vrsqrtps", { XM
, EXx
} },
9304 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
9308 { "vrcpps", { XM
, EXx
} },
9312 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
9316 { "vaddps", { XM
, Vex
, EXx
} },
9320 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
9324 { "vaddpd", { XM
, Vex
, EXx
} },
9328 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
9332 { "vmulps", { XM
, Vex
, EXx
} },
9336 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
9340 { "vmulpd", { XM
, Vex
, EXx
} },
9344 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
9348 { "vcvtps2pd", { XM
, EXxmmq
} },
9352 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
9356 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
9360 { "vcvtdq2ps", { XM
, EXx
} },
9364 { "vcvttps2dq", { XM
, EXx
} },
9368 { "vcvtps2dq", { XM
, EXx
} },
9372 { "vsubps", { XM
, Vex
, EXx
} },
9376 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
9380 { "vsubpd", { XM
, Vex
, EXx
} },
9384 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
9388 { "vminps", { XM
, Vex
, EXx
} },
9392 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
9396 { "vminpd", { XM
, Vex
, EXx
} },
9400 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
9404 { "vdivps", { XM
, Vex
, EXx
} },
9408 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
9412 { "vdivpd", { XM
, Vex
, EXx
} },
9416 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
9420 { "vmaxps", { XM
, Vex
, EXx
} },
9424 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
9428 { "vmaxpd", { XM
, Vex
, EXx
} },
9432 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
9436 { "vpunpcklbw", { XM
, Vex128
, EXx
} },
9440 { "vpunpcklwd", { XM
, Vex128
, EXx
} },
9444 { "vpunpckldq", { XM
, Vex128
, EXx
} },
9448 { "vpacksswb", { XM
, Vex128
, EXx
} },
9452 { "vpcmpgtb", { XM
, Vex128
, EXx
} },
9456 { "vpcmpgtw", { XM
, Vex128
, EXx
} },
9460 { "vpcmpgtd", { XM
, Vex128
, EXx
} },
9464 { "vpackuswb", { XM
, Vex128
, EXx
} },
9468 { "vpunpckhbw", { XM
, Vex128
, EXx
} },
9472 { "vpunpckhwd", { XM
, Vex128
, EXx
} },
9476 { "vpunpckhdq", { XM
, Vex128
, EXx
} },
9480 { "vpackssdw", { XM
, Vex128
, EXx
} },
9484 { "vpunpcklqdq", { XM
, Vex128
, EXx
} },
9488 { "vpunpckhqdq", { XM
, Vex128
, EXx
} },
9492 { "vmovdqu", { XM
, EXx
} },
9496 { "vmovdqa", { XM
, EXx
} },
9500 { "vpshufhw", { XM
, EXx
, Ib
} },
9504 { "vpshufd", { XM
, EXx
, Ib
} },
9508 { "vpshuflw", { XM
, EXx
, Ib
} },
9511 /* VEX_W_71_R_2_P_2 */
9512 { "vpsrlw", { Vex128
, XS
, Ib
} },
9515 /* VEX_W_71_R_4_P_2 */
9516 { "vpsraw", { Vex128
, XS
, Ib
} },
9519 /* VEX_W_71_R_6_P_2 */
9520 { "vpsllw", { Vex128
, XS
, Ib
} },
9523 /* VEX_W_72_R_2_P_2 */
9524 { "vpsrld", { Vex128
, XS
, Ib
} },
9527 /* VEX_W_72_R_4_P_2 */
9528 { "vpsrad", { Vex128
, XS
, Ib
} },
9531 /* VEX_W_72_R_6_P_2 */
9532 { "vpslld", { Vex128
, XS
, Ib
} },
9535 /* VEX_W_73_R_2_P_2 */
9536 { "vpsrlq", { Vex128
, XS
, Ib
} },
9539 /* VEX_W_73_R_3_P_2 */
9540 { "vpsrldq", { Vex128
, XS
, Ib
} },
9543 /* VEX_W_73_R_6_P_2 */
9544 { "vpsllq", { Vex128
, XS
, Ib
} },
9547 /* VEX_W_73_R_7_P_2 */
9548 { "vpslldq", { Vex128
, XS
, Ib
} },
9552 { "vpcmpeqb", { XM
, Vex128
, EXx
} },
9556 { "vpcmpeqw", { XM
, Vex128
, EXx
} },
9560 { "vpcmpeqd", { XM
, Vex128
, EXx
} },
9568 { "vhaddpd", { XM
, Vex
, EXx
} },
9572 { "vhaddps", { XM
, Vex
, EXx
} },
9576 { "vhsubpd", { XM
, Vex
, EXx
} },
9580 { "vhsubps", { XM
, Vex
, EXx
} },
9584 { "vmovq", { XMScalar
, EXqScalar
} },
9588 { "vmovdqu", { EXxS
, XM
} },
9592 { "vmovdqa", { EXxS
, XM
} },
9595 /* VEX_W_AE_R_2_M_0 */
9596 { "vldmxcsr", { Md
} },
9599 /* VEX_W_AE_R_3_M_0 */
9600 { "vstmxcsr", { Md
} },
9604 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
9608 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
9612 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
9616 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
9620 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
9624 { "vpextrw", { Gdq
, XS
, Ib
} },
9628 { "vaddsubpd", { XM
, Vex
, EXx
} },
9632 { "vaddsubps", { XM
, Vex
, EXx
} },
9636 { "vpsrlw", { XM
, Vex128
, EXx
} },
9640 { "vpsrld", { XM
, Vex128
, EXx
} },
9644 { "vpsrlq", { XM
, Vex128
, EXx
} },
9648 { "vpaddq", { XM
, Vex128
, EXx
} },
9652 { "vpmullw", { XM
, Vex128
, EXx
} },
9656 { "vmovq", { EXqScalarS
, XMScalar
} },
9659 /* VEX_W_D7_P_2_M_1 */
9660 { "vpmovmskb", { Gdq
, XS
} },
9664 { "vpsubusb", { XM
, Vex128
, EXx
} },
9668 { "vpsubusw", { XM
, Vex128
, EXx
} },
9672 { "vpminub", { XM
, Vex128
, EXx
} },
9676 { "vpand", { XM
, Vex128
, EXx
} },
9680 { "vpaddusb", { XM
, Vex128
, EXx
} },
9684 { "vpaddusw", { XM
, Vex128
, EXx
} },
9688 { "vpmaxub", { XM
, Vex128
, EXx
} },
9692 { "vpandn", { XM
, Vex128
, EXx
} },
9696 { "vpavgb", { XM
, Vex128
, EXx
} },
9700 { "vpsraw", { XM
, Vex128
, EXx
} },
9704 { "vpsrad", { XM
, Vex128
, EXx
} },
9708 { "vpavgw", { XM
, Vex128
, EXx
} },
9712 { "vpmulhuw", { XM
, Vex128
, EXx
} },
9716 { "vpmulhw", { XM
, Vex128
, EXx
} },
9720 { "vcvtdq2pd", { XM
, EXxmmq
} },
9724 { "vcvttpd2dq%XY", { XMM
, EXx
} },
9728 { "vcvtpd2dq%XY", { XMM
, EXx
} },
9731 /* VEX_W_E7_P_2_M_0 */
9732 { "vmovntdq", { Mx
, XM
} },
9736 { "vpsubsb", { XM
, Vex128
, EXx
} },
9740 { "vpsubsw", { XM
, Vex128
, EXx
} },
9744 { "vpminsw", { XM
, Vex128
, EXx
} },
9748 { "vpor", { XM
, Vex128
, EXx
} },
9752 { "vpaddsb", { XM
, Vex128
, EXx
} },
9756 { "vpaddsw", { XM
, Vex128
, EXx
} },
9760 { "vpmaxsw", { XM
, Vex128
, EXx
} },
9764 { "vpxor", { XM
, Vex128
, EXx
} },
9767 /* VEX_W_F0_P_3_M_0 */
9768 { "vlddqu", { XM
, M
} },
9772 { "vpsllw", { XM
, Vex128
, EXx
} },
9776 { "vpslld", { XM
, Vex128
, EXx
} },
9780 { "vpsllq", { XM
, Vex128
, EXx
} },
9784 { "vpmuludq", { XM
, Vex128
, EXx
} },
9788 { "vpmaddwd", { XM
, Vex128
, EXx
} },
9792 { "vpsadbw", { XM
, Vex128
, EXx
} },
9796 { "vmaskmovdqu", { XM
, XS
} },
9800 { "vpsubb", { XM
, Vex128
, EXx
} },
9804 { "vpsubw", { XM
, Vex128
, EXx
} },
9808 { "vpsubd", { XM
, Vex128
, EXx
} },
9812 { "vpsubq", { XM
, Vex128
, EXx
} },
9816 { "vpaddb", { XM
, Vex128
, EXx
} },
9820 { "vpaddw", { XM
, Vex128
, EXx
} },
9824 { "vpaddd", { XM
, Vex128
, EXx
} },
9827 /* VEX_W_3800_P_2 */
9828 { "vpshufb", { XM
, Vex128
, EXx
} },
9831 /* VEX_W_3801_P_2 */
9832 { "vphaddw", { XM
, Vex128
, EXx
} },
9835 /* VEX_W_3802_P_2 */
9836 { "vphaddd", { XM
, Vex128
, EXx
} },
9839 /* VEX_W_3803_P_2 */
9840 { "vphaddsw", { XM
, Vex128
, EXx
} },
9843 /* VEX_W_3804_P_2 */
9844 { "vpmaddubsw", { XM
, Vex128
, EXx
} },
9847 /* VEX_W_3805_P_2 */
9848 { "vphsubw", { XM
, Vex128
, EXx
} },
9851 /* VEX_W_3806_P_2 */
9852 { "vphsubd", { XM
, Vex128
, EXx
} },
9855 /* VEX_W_3807_P_2 */
9856 { "vphsubsw", { XM
, Vex128
, EXx
} },
9859 /* VEX_W_3808_P_2 */
9860 { "vpsignb", { XM
, Vex128
, EXx
} },
9863 /* VEX_W_3809_P_2 */
9864 { "vpsignw", { XM
, Vex128
, EXx
} },
9867 /* VEX_W_380A_P_2 */
9868 { "vpsignd", { XM
, Vex128
, EXx
} },
9871 /* VEX_W_380B_P_2 */
9872 { "vpmulhrsw", { XM
, Vex128
, EXx
} },
9875 /* VEX_W_380C_P_2 */
9876 { "vpermilps", { XM
, Vex
, EXx
} },
9879 /* VEX_W_380D_P_2 */
9880 { "vpermilpd", { XM
, Vex
, EXx
} },
9883 /* VEX_W_380E_P_2 */
9884 { "vtestps", { XM
, EXx
} },
9887 /* VEX_W_380F_P_2 */
9888 { "vtestpd", { XM
, EXx
} },
9891 /* VEX_W_3817_P_2 */
9892 { "vptest", { XM
, EXx
} },
9895 /* VEX_W_3818_P_2_M_0 */
9896 { "vbroadcastss", { XM
, Md
} },
9899 /* VEX_W_3819_P_2_M_0 */
9900 { "vbroadcastsd", { XM
, Mq
} },
9903 /* VEX_W_381A_P_2_M_0 */
9904 { "vbroadcastf128", { XM
, Mxmm
} },
9907 /* VEX_W_381C_P_2 */
9908 { "vpabsb", { XM
, EXx
} },
9911 /* VEX_W_381D_P_2 */
9912 { "vpabsw", { XM
, EXx
} },
9915 /* VEX_W_381E_P_2 */
9916 { "vpabsd", { XM
, EXx
} },
9919 /* VEX_W_3820_P_2 */
9920 { "vpmovsxbw", { XM
, EXq
} },
9923 /* VEX_W_3821_P_2 */
9924 { "vpmovsxbd", { XM
, EXd
} },
9927 /* VEX_W_3822_P_2 */
9928 { "vpmovsxbq", { XM
, EXw
} },
9931 /* VEX_W_3823_P_2 */
9932 { "vpmovsxwd", { XM
, EXq
} },
9935 /* VEX_W_3824_P_2 */
9936 { "vpmovsxwq", { XM
, EXd
} },
9939 /* VEX_W_3825_P_2 */
9940 { "vpmovsxdq", { XM
, EXq
} },
9943 /* VEX_W_3828_P_2 */
9944 { "vpmuldq", { XM
, Vex128
, EXx
} },
9947 /* VEX_W_3829_P_2 */
9948 { "vpcmpeqq", { XM
, Vex128
, EXx
} },
9951 /* VEX_W_382A_P_2_M_0 */
9952 { "vmovntdqa", { XM
, Mx
} },
9955 /* VEX_W_382B_P_2 */
9956 { "vpackusdw", { XM
, Vex128
, EXx
} },
9959 /* VEX_W_382C_P_2_M_0 */
9960 { "vmaskmovps", { XM
, Vex
, Mx
} },
9963 /* VEX_W_382D_P_2_M_0 */
9964 { "vmaskmovpd", { XM
, Vex
, Mx
} },
9967 /* VEX_W_382E_P_2_M_0 */
9968 { "vmaskmovps", { Mx
, Vex
, XM
} },
9971 /* VEX_W_382F_P_2_M_0 */
9972 { "vmaskmovpd", { Mx
, Vex
, XM
} },
9975 /* VEX_W_3830_P_2 */
9976 { "vpmovzxbw", { XM
, EXq
} },
9979 /* VEX_W_3831_P_2 */
9980 { "vpmovzxbd", { XM
, EXd
} },
9983 /* VEX_W_3832_P_2 */
9984 { "vpmovzxbq", { XM
, EXw
} },
9987 /* VEX_W_3833_P_2 */
9988 { "vpmovzxwd", { XM
, EXq
} },
9991 /* VEX_W_3834_P_2 */
9992 { "vpmovzxwq", { XM
, EXd
} },
9995 /* VEX_W_3835_P_2 */
9996 { "vpmovzxdq", { XM
, EXq
} },
9999 /* VEX_W_3837_P_2 */
10000 { "vpcmpgtq", { XM
, Vex128
, EXx
} },
10003 /* VEX_W_3838_P_2 */
10004 { "vpminsb", { XM
, Vex128
, EXx
} },
10007 /* VEX_W_3839_P_2 */
10008 { "vpminsd", { XM
, Vex128
, EXx
} },
10011 /* VEX_W_383A_P_2 */
10012 { "vpminuw", { XM
, Vex128
, EXx
} },
10015 /* VEX_W_383B_P_2 */
10016 { "vpminud", { XM
, Vex128
, EXx
} },
10019 /* VEX_W_383C_P_2 */
10020 { "vpmaxsb", { XM
, Vex128
, EXx
} },
10023 /* VEX_W_383D_P_2 */
10024 { "vpmaxsd", { XM
, Vex128
, EXx
} },
10027 /* VEX_W_383E_P_2 */
10028 { "vpmaxuw", { XM
, Vex128
, EXx
} },
10031 /* VEX_W_383F_P_2 */
10032 { "vpmaxud", { XM
, Vex128
, EXx
} },
10035 /* VEX_W_3840_P_2 */
10036 { "vpmulld", { XM
, Vex128
, EXx
} },
10039 /* VEX_W_3841_P_2 */
10040 { "vphminposuw", { XM
, EXx
} },
10043 /* VEX_W_38DB_P_2 */
10044 { "vaesimc", { XM
, EXx
} },
10047 /* VEX_W_38DC_P_2 */
10048 { "vaesenc", { XM
, Vex128
, EXx
} },
10051 /* VEX_W_38DD_P_2 */
10052 { "vaesenclast", { XM
, Vex128
, EXx
} },
10055 /* VEX_W_38DE_P_2 */
10056 { "vaesdec", { XM
, Vex128
, EXx
} },
10059 /* VEX_W_38DF_P_2 */
10060 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10063 /* VEX_W_3A04_P_2 */
10064 { "vpermilps", { XM
, EXx
, Ib
} },
10067 /* VEX_W_3A05_P_2 */
10068 { "vpermilpd", { XM
, EXx
, Ib
} },
10071 /* VEX_W_3A06_P_2 */
10072 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10075 /* VEX_W_3A08_P_2 */
10076 { "vroundps", { XM
, EXx
, Ib
} },
10079 /* VEX_W_3A09_P_2 */
10080 { "vroundpd", { XM
, EXx
, Ib
} },
10083 /* VEX_W_3A0A_P_2 */
10084 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10087 /* VEX_W_3A0B_P_2 */
10088 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10091 /* VEX_W_3A0C_P_2 */
10092 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10095 /* VEX_W_3A0D_P_2 */
10096 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10099 /* VEX_W_3A0E_P_2 */
10100 { "vpblendw", { XM
, Vex128
, EXx
, Ib
} },
10103 /* VEX_W_3A0F_P_2 */
10104 { "vpalignr", { XM
, Vex128
, EXx
, Ib
} },
10107 /* VEX_W_3A14_P_2 */
10108 { "vpextrb", { Edqb
, XM
, Ib
} },
10111 /* VEX_W_3A15_P_2 */
10112 { "vpextrw", { Edqw
, XM
, Ib
} },
10115 /* VEX_W_3A18_P_2 */
10116 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10119 /* VEX_W_3A19_P_2 */
10120 { "vextractf128", { EXxmm
, XM
, Ib
} },
10123 /* VEX_W_3A20_P_2 */
10124 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10127 /* VEX_W_3A21_P_2 */
10128 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10131 /* VEX_W_3A40_P_2 */
10132 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
10135 /* VEX_W_3A41_P_2 */
10136 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
10139 /* VEX_W_3A42_P_2 */
10140 { "vmpsadbw", { XM
, Vex128
, EXx
, Ib
} },
10143 /* VEX_W_3A44_P_2 */
10144 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
10147 /* VEX_W_3A48_P_2 */
10148 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10149 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10152 /* VEX_W_3A49_P_2 */
10153 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10154 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
10157 /* VEX_W_3A4A_P_2 */
10158 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
10161 /* VEX_W_3A4B_P_2 */
10162 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
10165 /* VEX_W_3A4C_P_2 */
10166 { "vpblendvb", { XM
, Vex128
, EXx
, XMVexI4
} },
10169 /* VEX_W_3A60_P_2 */
10170 { "vpcmpestrm", { XM
, EXx
, Ib
} },
10173 /* VEX_W_3A61_P_2 */
10174 { "vpcmpestri", { XM
, EXx
, Ib
} },
10177 /* VEX_W_3A62_P_2 */
10178 { "vpcmpistrm", { XM
, EXx
, Ib
} },
10181 /* VEX_W_3A63_P_2 */
10182 { "vpcmpistri", { XM
, EXx
, Ib
} },
10185 /* VEX_W_3ADF_P_2 */
10186 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
10190 static const struct dis386 mod_table
[][2] = {
10193 { "leaS", { Gv
, M
} },
10196 /* MOD_0F01_REG_0 */
10197 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10198 { RM_TABLE (RM_0F01_REG_0
) },
10201 /* MOD_0F01_REG_1 */
10202 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10203 { RM_TABLE (RM_0F01_REG_1
) },
10206 /* MOD_0F01_REG_2 */
10207 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10208 { RM_TABLE (RM_0F01_REG_2
) },
10211 /* MOD_0F01_REG_3 */
10212 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10213 { RM_TABLE (RM_0F01_REG_3
) },
10216 /* MOD_0F01_REG_7 */
10217 { "invlpg", { Mb
} },
10218 { RM_TABLE (RM_0F01_REG_7
) },
10221 /* MOD_0F12_PREFIX_0 */
10222 { "movlps", { XM
, EXq
} },
10223 { "movhlps", { XM
, EXq
} },
10227 { "movlpX", { EXq
, XM
} },
10230 /* MOD_0F16_PREFIX_0 */
10231 { "movhps", { XM
, EXq
} },
10232 { "movlhps", { XM
, EXq
} },
10236 { "movhpX", { EXq
, XM
} },
10239 /* MOD_0F18_REG_0 */
10240 { "prefetchnta", { Mb
} },
10243 /* MOD_0F18_REG_1 */
10244 { "prefetcht0", { Mb
} },
10247 /* MOD_0F18_REG_2 */
10248 { "prefetcht1", { Mb
} },
10251 /* MOD_0F18_REG_3 */
10252 { "prefetcht2", { Mb
} },
10257 { "movZ", { Rm
, Cm
} },
10262 { "movZ", { Rm
, Dm
} },
10267 { "movZ", { Cm
, Rm
} },
10272 { "movZ", { Dm
, Rm
} },
10277 { "movL", { Rd
, Td
} },
10282 { "movL", { Td
, Rd
} },
10285 /* MOD_0F2B_PREFIX_0 */
10286 {"movntps", { Mx
, XM
} },
10289 /* MOD_0F2B_PREFIX_1 */
10290 {"movntss", { Md
, XM
} },
10293 /* MOD_0F2B_PREFIX_2 */
10294 {"movntpd", { Mx
, XM
} },
10297 /* MOD_0F2B_PREFIX_3 */
10298 {"movntsd", { Mq
, XM
} },
10303 { "movmskpX", { Gdq
, XS
} },
10306 /* MOD_0F71_REG_2 */
10308 { "psrlw", { MS
, Ib
} },
10311 /* MOD_0F71_REG_4 */
10313 { "psraw", { MS
, Ib
} },
10316 /* MOD_0F71_REG_6 */
10318 { "psllw", { MS
, Ib
} },
10321 /* MOD_0F72_REG_2 */
10323 { "psrld", { MS
, Ib
} },
10326 /* MOD_0F72_REG_4 */
10328 { "psrad", { MS
, Ib
} },
10331 /* MOD_0F72_REG_6 */
10333 { "pslld", { MS
, Ib
} },
10336 /* MOD_0F73_REG_2 */
10338 { "psrlq", { MS
, Ib
} },
10341 /* MOD_0F73_REG_3 */
10343 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10346 /* MOD_0F73_REG_6 */
10348 { "psllq", { MS
, Ib
} },
10351 /* MOD_0F73_REG_7 */
10353 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10356 /* MOD_0FAE_REG_0 */
10357 { "fxsave", { FXSAVE
} },
10360 /* MOD_0FAE_REG_1 */
10361 { "fxrstor", { FXSAVE
} },
10364 /* MOD_0FAE_REG_2 */
10365 { "ldmxcsr", { Md
} },
10368 /* MOD_0FAE_REG_3 */
10369 { "stmxcsr", { Md
} },
10372 /* MOD_0FAE_REG_4 */
10373 { "xsave", { FXSAVE
} },
10376 /* MOD_0FAE_REG_5 */
10377 { "xrstor", { FXSAVE
} },
10378 { RM_TABLE (RM_0FAE_REG_5
) },
10381 /* MOD_0FAE_REG_6 */
10383 { RM_TABLE (RM_0FAE_REG_6
) },
10386 /* MOD_0FAE_REG_7 */
10387 { "clflush", { Mb
} },
10388 { RM_TABLE (RM_0FAE_REG_7
) },
10392 { "lssS", { Gv
, Mp
} },
10396 { "lfsS", { Gv
, Mp
} },
10400 { "lgsS", { Gv
, Mp
} },
10403 /* MOD_0FC7_REG_6 */
10404 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
10407 /* MOD_0FC7_REG_7 */
10408 { "vmptrst", { Mq
} },
10413 { "pmovmskb", { Gdq
, MS
} },
10416 /* MOD_0FE7_PREFIX_2 */
10417 { "movntdq", { Mx
, XM
} },
10420 /* MOD_0FF0_PREFIX_3 */
10421 { "lddqu", { XM
, M
} },
10424 /* MOD_0F382A_PREFIX_2 */
10425 { "movntdqa", { XM
, Mx
} },
10429 { "bound{S|}", { Gv
, Ma
} },
10433 { "lesS", { Gv
, Mp
} },
10434 { VEX_C4_TABLE (VEX_0F
) },
10438 { "ldsS", { Gv
, Mp
} },
10439 { VEX_C5_TABLE (VEX_0F
) },
10442 /* MOD_VEX_12_PREFIX_0 */
10443 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0
) },
10444 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1
) },
10448 { VEX_LEN_TABLE (VEX_LEN_13_M_0
) },
10451 /* MOD_VEX_16_PREFIX_0 */
10452 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0
) },
10453 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1
) },
10457 { VEX_LEN_TABLE (VEX_LEN_17_M_0
) },
10461 { VEX_W_TABLE (VEX_W_2B_M_0
) },
10466 { VEX_W_TABLE (VEX_W_50_M_0
) },
10469 /* MOD_VEX_71_REG_2 */
10471 { PREFIX_TABLE (PREFIX_VEX_71_REG_2
) },
10474 /* MOD_VEX_71_REG_4 */
10476 { PREFIX_TABLE (PREFIX_VEX_71_REG_4
) },
10479 /* MOD_VEX_71_REG_6 */
10481 { PREFIX_TABLE (PREFIX_VEX_71_REG_6
) },
10484 /* MOD_VEX_72_REG_2 */
10486 { PREFIX_TABLE (PREFIX_VEX_72_REG_2
) },
10489 /* MOD_VEX_72_REG_4 */
10491 { PREFIX_TABLE (PREFIX_VEX_72_REG_4
) },
10494 /* MOD_VEX_72_REG_6 */
10496 { PREFIX_TABLE (PREFIX_VEX_72_REG_6
) },
10499 /* MOD_VEX_73_REG_2 */
10501 { PREFIX_TABLE (PREFIX_VEX_73_REG_2
) },
10504 /* MOD_VEX_73_REG_3 */
10506 { PREFIX_TABLE (PREFIX_VEX_73_REG_3
) },
10509 /* MOD_VEX_73_REG_6 */
10511 { PREFIX_TABLE (PREFIX_VEX_73_REG_6
) },
10514 /* MOD_VEX_73_REG_7 */
10516 { PREFIX_TABLE (PREFIX_VEX_73_REG_7
) },
10519 /* MOD_VEX_AE_REG_2 */
10520 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0
) },
10523 /* MOD_VEX_AE_REG_3 */
10524 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0
) },
10527 /* MOD_VEX_D7_PREFIX_2 */
10529 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1
) },
10532 /* MOD_VEX_E7_PREFIX_2 */
10533 { VEX_W_TABLE (VEX_W_E7_P_2_M_0
) },
10536 /* MOD_VEX_F0_PREFIX_3 */
10537 { VEX_W_TABLE (VEX_W_F0_P_3_M_0
) },
10540 /* MOD_VEX_3818_PREFIX_2 */
10541 { VEX_W_TABLE (VEX_W_3818_P_2_M_0
) },
10544 /* MOD_VEX_3819_PREFIX_2 */
10545 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0
) },
10548 /* MOD_VEX_381A_PREFIX_2 */
10549 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0
) },
10552 /* MOD_VEX_382A_PREFIX_2 */
10553 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0
) },
10556 /* MOD_VEX_382C_PREFIX_2 */
10557 { VEX_W_TABLE (VEX_W_382C_P_2_M_0
) },
10560 /* MOD_VEX_382D_PREFIX_2 */
10561 { VEX_W_TABLE (VEX_W_382D_P_2_M_0
) },
10564 /* MOD_VEX_382E_PREFIX_2 */
10565 { VEX_W_TABLE (VEX_W_382E_P_2_M_0
) },
10568 /* MOD_VEX_382F_PREFIX_2 */
10569 { VEX_W_TABLE (VEX_W_382F_P_2_M_0
) },
10573 static const struct dis386 rm_table
[][8] = {
10575 /* RM_0F01_REG_0 */
10577 { "vmcall", { Skip_MODRM
} },
10578 { "vmlaunch", { Skip_MODRM
} },
10579 { "vmresume", { Skip_MODRM
} },
10580 { "vmxoff", { Skip_MODRM
} },
10583 /* RM_0F01_REG_1 */
10584 { "monitor", { { OP_Monitor
, 0 } } },
10585 { "mwait", { { OP_Mwait
, 0 } } },
10588 /* RM_0F01_REG_2 */
10589 { "xgetbv", { Skip_MODRM
} },
10590 { "xsetbv", { Skip_MODRM
} },
10593 /* RM_0F01_REG_3 */
10594 { "vmrun", { Skip_MODRM
} },
10595 { "vmmcall", { Skip_MODRM
} },
10596 { "vmload", { Skip_MODRM
} },
10597 { "vmsave", { Skip_MODRM
} },
10598 { "stgi", { Skip_MODRM
} },
10599 { "clgi", { Skip_MODRM
} },
10600 { "skinit", { Skip_MODRM
} },
10601 { "invlpga", { Skip_MODRM
} },
10604 /* RM_0F01_REG_7 */
10605 { "swapgs", { Skip_MODRM
} },
10606 { "rdtscp", { Skip_MODRM
} },
10609 /* RM_0FAE_REG_5 */
10610 { "lfence", { Skip_MODRM
} },
10613 /* RM_0FAE_REG_6 */
10614 { "mfence", { Skip_MODRM
} },
10617 /* RM_0FAE_REG_7 */
10618 { "sfence", { Skip_MODRM
} },
10622 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10624 /* We use the high bit to indicate different name for the same
10626 #define ADDR16_PREFIX (0x67 | 0x100)
10627 #define ADDR32_PREFIX (0x67 | 0x200)
10628 #define DATA16_PREFIX (0x66 | 0x100)
10629 #define DATA32_PREFIX (0x66 | 0x200)
10630 #define REP_PREFIX (0xf3 | 0x100)
10635 int newrex
, i
, length
;
10641 last_lock_prefix
= -1;
10642 last_repz_prefix
= -1;
10643 last_repnz_prefix
= -1;
10644 last_data_prefix
= -1;
10645 last_addr_prefix
= -1;
10646 last_rex_prefix
= -1;
10647 last_seg_prefix
= -1;
10648 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
10649 all_prefixes
[i
] = 0;
10652 /* The maximum instruction length is 15bytes. */
10653 while (length
< MAX_CODE_LENGTH
- 1)
10655 FETCH_DATA (the_info
, codep
+ 1);
10659 /* REX prefixes family. */
10676 if (address_mode
== mode_64bit
)
10680 last_rex_prefix
= i
;
10683 prefixes
|= PREFIX_REPZ
;
10684 last_repz_prefix
= i
;
10687 prefixes
|= PREFIX_REPNZ
;
10688 last_repnz_prefix
= i
;
10691 prefixes
|= PREFIX_LOCK
;
10692 last_lock_prefix
= i
;
10695 prefixes
|= PREFIX_CS
;
10696 last_seg_prefix
= i
;
10699 prefixes
|= PREFIX_SS
;
10700 last_seg_prefix
= i
;
10703 prefixes
|= PREFIX_DS
;
10704 last_seg_prefix
= i
;
10707 prefixes
|= PREFIX_ES
;
10708 last_seg_prefix
= i
;
10711 prefixes
|= PREFIX_FS
;
10712 last_seg_prefix
= i
;
10715 prefixes
|= PREFIX_GS
;
10716 last_seg_prefix
= i
;
10719 prefixes
|= PREFIX_DATA
;
10720 last_data_prefix
= i
;
10723 prefixes
|= PREFIX_ADDR
;
10724 last_addr_prefix
= i
;
10727 /* fwait is really an instruction. If there are prefixes
10728 before the fwait, they belong to the fwait, *not* to the
10729 following instruction. */
10730 if (prefixes
|| rex
)
10732 prefixes
|= PREFIX_FWAIT
;
10736 prefixes
= PREFIX_FWAIT
;
10741 /* Rex is ignored when followed by another prefix. */
10747 if (*codep
!= FWAIT_OPCODE
)
10748 all_prefixes
[i
++] = *codep
;
10757 seg_prefix (int pref
)
10778 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10781 static const char *
10782 prefix_name (int pref
, int sizeflag
)
10784 static const char *rexes
[16] =
10787 "rex.B", /* 0x41 */
10788 "rex.X", /* 0x42 */
10789 "rex.XB", /* 0x43 */
10790 "rex.R", /* 0x44 */
10791 "rex.RB", /* 0x45 */
10792 "rex.RX", /* 0x46 */
10793 "rex.RXB", /* 0x47 */
10794 "rex.W", /* 0x48 */
10795 "rex.WB", /* 0x49 */
10796 "rex.WX", /* 0x4a */
10797 "rex.WXB", /* 0x4b */
10798 "rex.WR", /* 0x4c */
10799 "rex.WRB", /* 0x4d */
10800 "rex.WRX", /* 0x4e */
10801 "rex.WRXB", /* 0x4f */
10806 /* REX prefixes family. */
10823 return rexes
[pref
- 0x40];
10843 return (sizeflag
& DFLAG
) ? "data16" : "data32";
10845 if (address_mode
== mode_64bit
)
10846 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
10848 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
10851 case ADDR16_PREFIX
:
10853 case ADDR32_PREFIX
:
10855 case DATA16_PREFIX
:
10857 case DATA32_PREFIX
:
10866 static char op_out
[MAX_OPERANDS
][100];
10867 static int op_ad
, op_index
[MAX_OPERANDS
];
10868 static int two_source_ops
;
10869 static bfd_vma op_address
[MAX_OPERANDS
];
10870 static bfd_vma op_riprel
[MAX_OPERANDS
];
10871 static bfd_vma start_pc
;
10874 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10875 * (see topic "Redundant prefixes" in the "Differences from 8086"
10876 * section of the "Virtual 8086 Mode" chapter.)
10877 * 'pc' should be the address of this instruction, it will
10878 * be used to print the target address if this is a relative jump or call
10879 * The function returns the length of this instruction in bytes.
10882 static char intel_syntax
;
10883 static char intel_mnemonic
= !SYSV386_COMPAT
;
10884 static char open_char
;
10885 static char close_char
;
10886 static char separator_char
;
10887 static char scale_char
;
10889 /* Here for backwards compatibility. When gdb stops using
10890 print_insn_i386_att and print_insn_i386_intel these functions can
10891 disappear, and print_insn_i386 be merged into print_insn. */
10893 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
10897 return print_insn (pc
, info
);
10901 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
10905 return print_insn (pc
, info
);
10909 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
10913 return print_insn (pc
, info
);
10917 print_i386_disassembler_options (FILE *stream
)
10919 fprintf (stream
, _("\n\
10920 The following i386/x86-64 specific disassembler options are supported for use\n\
10921 with the -M switch (multiple options should be separated by commas):\n"));
10923 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
10924 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
10925 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
10926 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
10927 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
10928 fprintf (stream
, _(" att-mnemonic\n"
10929 " Display instruction in AT&T mnemonic\n"));
10930 fprintf (stream
, _(" intel-mnemonic\n"
10931 " Display instruction in Intel mnemonic\n"));
10932 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
10933 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
10934 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
10935 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
10936 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
10937 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10941 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
10943 /* Get a pointer to struct dis386 with a valid name. */
10945 static const struct dis386
*
10946 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
10948 int vindex
, vex_table_index
;
10950 if (dp
->name
!= NULL
)
10953 switch (dp
->op
[0].bytemode
)
10955 case USE_REG_TABLE
:
10956 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
10959 case USE_MOD_TABLE
:
10960 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
10961 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
10965 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
10968 case USE_PREFIX_TABLE
:
10971 /* The prefix in VEX is implicit. */
10972 switch (vex
.prefix
)
10977 case REPE_PREFIX_OPCODE
:
10980 case DATA_PREFIX_OPCODE
:
10983 case REPNE_PREFIX_OPCODE
:
10994 used_prefixes
|= (prefixes
& PREFIX_REPZ
);
10995 if (prefixes
& PREFIX_REPZ
)
10998 all_prefixes
[last_repz_prefix
] = 0;
11002 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11004 used_prefixes
|= (prefixes
& PREFIX_REPNZ
);
11005 if (prefixes
& PREFIX_REPNZ
)
11008 all_prefixes
[last_repnz_prefix
] = 0;
11012 used_prefixes
|= (prefixes
& PREFIX_DATA
);
11013 if (prefixes
& PREFIX_DATA
)
11016 all_prefixes
[last_data_prefix
] = 0;
11021 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11024 case USE_X86_64_TABLE
:
11025 vindex
= address_mode
== mode_64bit
? 1 : 0;
11026 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11029 case USE_3BYTE_TABLE
:
11030 FETCH_DATA (info
, codep
+ 2);
11032 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11033 modrm
.mod
= (*codep
>> 6) & 3;
11034 modrm
.reg
= (*codep
>> 3) & 7;
11035 modrm
.rm
= *codep
& 7;
11038 case USE_VEX_LEN_TABLE
:
11042 switch (vex
.length
)
11055 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11058 case USE_XOP_8F_TABLE
:
11059 FETCH_DATA (info
, codep
+ 3);
11060 /* All bits in the REX prefix are ignored. */
11062 rex
= ~(*codep
>> 5) & 0x7;
11064 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11065 switch ((*codep
& 0x1f))
11071 vex_table_index
= XOP_08
;
11074 vex_table_index
= XOP_09
;
11077 vex_table_index
= XOP_0A
;
11081 vex
.w
= *codep
& 0x80;
11082 if (vex
.w
&& address_mode
== mode_64bit
)
11085 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11086 if (address_mode
!= mode_64bit
11087 && vex
.register_specifier
> 0x7)
11093 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11094 switch ((*codep
& 0x3))
11100 vex
.prefix
= DATA_PREFIX_OPCODE
;
11103 vex
.prefix
= REPE_PREFIX_OPCODE
;
11106 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11113 dp
= &xop_table
[vex_table_index
][vindex
];
11115 FETCH_DATA (info
, codep
+ 1);
11116 modrm
.mod
= (*codep
>> 6) & 3;
11117 modrm
.reg
= (*codep
>> 3) & 7;
11118 modrm
.rm
= *codep
& 7;
11121 case USE_VEX_C4_TABLE
:
11122 FETCH_DATA (info
, codep
+ 3);
11123 /* All bits in the REX prefix are ignored. */
11125 rex
= ~(*codep
>> 5) & 0x7;
11126 switch ((*codep
& 0x1f))
11132 vex_table_index
= VEX_0F
;
11135 vex_table_index
= VEX_0F38
;
11138 vex_table_index
= VEX_0F3A
;
11142 vex
.w
= *codep
& 0x80;
11143 if (vex
.w
&& address_mode
== mode_64bit
)
11146 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11147 if (address_mode
!= mode_64bit
11148 && vex
.register_specifier
> 0x7)
11154 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11155 switch ((*codep
& 0x3))
11161 vex
.prefix
= DATA_PREFIX_OPCODE
;
11164 vex
.prefix
= REPE_PREFIX_OPCODE
;
11167 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11174 dp
= &vex_table
[vex_table_index
][vindex
];
11175 /* There is no MODRM byte for VEX [82|77]. */
11176 if (vindex
!= 0x77 && vindex
!= 0x82)
11178 FETCH_DATA (info
, codep
+ 1);
11179 modrm
.mod
= (*codep
>> 6) & 3;
11180 modrm
.reg
= (*codep
>> 3) & 7;
11181 modrm
.rm
= *codep
& 7;
11185 case USE_VEX_C5_TABLE
:
11186 FETCH_DATA (info
, codep
+ 2);
11187 /* All bits in the REX prefix are ignored. */
11189 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11191 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11192 if (address_mode
!= mode_64bit
11193 && vex
.register_specifier
> 0x7)
11201 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11202 switch ((*codep
& 0x3))
11208 vex
.prefix
= DATA_PREFIX_OPCODE
;
11211 vex
.prefix
= REPE_PREFIX_OPCODE
;
11214 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11221 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11222 /* There is no MODRM byte for VEX [82|77]. */
11223 if (vindex
!= 0x77 && vindex
!= 0x82)
11225 FETCH_DATA (info
, codep
+ 1);
11226 modrm
.mod
= (*codep
>> 6) & 3;
11227 modrm
.reg
= (*codep
>> 3) & 7;
11228 modrm
.rm
= *codep
& 7;
11232 case USE_VEX_W_TABLE
:
11236 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11247 if (dp
->name
!= NULL
)
11250 return get_valid_dis386 (dp
, info
);
11254 get_sib (disassemble_info
*info
)
11256 /* If modrm.mod == 3, operand must be register. */
11258 && address_mode
!= mode_16bit
11262 FETCH_DATA (info
, codep
+ 2);
11263 sib
.index
= (codep
[1] >> 3) & 7;
11264 sib
.scale
= (codep
[1] >> 6) & 3;
11265 sib
.base
= codep
[1] & 7;
11270 print_insn (bfd_vma pc
, disassemble_info
*info
)
11272 const struct dis386
*dp
;
11274 char *op_txt
[MAX_OPERANDS
];
11278 struct dis_private priv
;
11280 int default_prefixes
;
11282 if (info
->mach
== bfd_mach_x86_64_intel_syntax
11283 || info
->mach
== bfd_mach_x86_64
11284 || info
->mach
== bfd_mach_l1om
11285 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11286 address_mode
= mode_64bit
;
11288 address_mode
= mode_32bit
;
11290 if (intel_syntax
== (char) -1)
11291 intel_syntax
= (info
->mach
== bfd_mach_i386_i386_intel_syntax
11292 || info
->mach
== bfd_mach_x86_64_intel_syntax
11293 || info
->mach
== bfd_mach_l1om_intel_syntax
);
11295 if (info
->mach
== bfd_mach_i386_i386
11296 || info
->mach
== bfd_mach_x86_64
11297 || info
->mach
== bfd_mach_l1om
11298 || info
->mach
== bfd_mach_i386_i386_intel_syntax
11299 || info
->mach
== bfd_mach_x86_64_intel_syntax
11300 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11301 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11302 else if (info
->mach
== bfd_mach_i386_i8086
)
11303 priv
.orig_sizeflag
= 0;
11307 for (p
= info
->disassembler_options
; p
!= NULL
; )
11309 if (CONST_STRNEQ (p
, "x86-64"))
11311 address_mode
= mode_64bit
;
11312 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11314 else if (CONST_STRNEQ (p
, "i386"))
11316 address_mode
= mode_32bit
;
11317 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11319 else if (CONST_STRNEQ (p
, "i8086"))
11321 address_mode
= mode_16bit
;
11322 priv
.orig_sizeflag
= 0;
11324 else if (CONST_STRNEQ (p
, "intel"))
11327 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11328 intel_mnemonic
= 1;
11330 else if (CONST_STRNEQ (p
, "att"))
11333 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11334 intel_mnemonic
= 0;
11336 else if (CONST_STRNEQ (p
, "addr"))
11338 if (address_mode
== mode_64bit
)
11340 if (p
[4] == '3' && p
[5] == '2')
11341 priv
.orig_sizeflag
&= ~AFLAG
;
11342 else if (p
[4] == '6' && p
[5] == '4')
11343 priv
.orig_sizeflag
|= AFLAG
;
11347 if (p
[4] == '1' && p
[5] == '6')
11348 priv
.orig_sizeflag
&= ~AFLAG
;
11349 else if (p
[4] == '3' && p
[5] == '2')
11350 priv
.orig_sizeflag
|= AFLAG
;
11353 else if (CONST_STRNEQ (p
, "data"))
11355 if (p
[4] == '1' && p
[5] == '6')
11356 priv
.orig_sizeflag
&= ~DFLAG
;
11357 else if (p
[4] == '3' && p
[5] == '2')
11358 priv
.orig_sizeflag
|= DFLAG
;
11360 else if (CONST_STRNEQ (p
, "suffix"))
11361 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11363 p
= strchr (p
, ',');
11370 names64
= intel_names64
;
11371 names32
= intel_names32
;
11372 names16
= intel_names16
;
11373 names8
= intel_names8
;
11374 names8rex
= intel_names8rex
;
11375 names_seg
= intel_names_seg
;
11376 names_mm
= intel_names_mm
;
11377 names_xmm
= intel_names_xmm
;
11378 names_ymm
= intel_names_ymm
;
11379 index64
= intel_index64
;
11380 index32
= intel_index32
;
11381 index16
= intel_index16
;
11384 separator_char
= '+';
11389 names64
= att_names64
;
11390 names32
= att_names32
;
11391 names16
= att_names16
;
11392 names8
= att_names8
;
11393 names8rex
= att_names8rex
;
11394 names_seg
= att_names_seg
;
11395 names_mm
= att_names_mm
;
11396 names_xmm
= att_names_xmm
;
11397 names_ymm
= att_names_ymm
;
11398 index64
= att_index64
;
11399 index32
= att_index32
;
11400 index16
= att_index16
;
11403 separator_char
= ',';
11407 /* The output looks better if we put 7 bytes on a line, since that
11408 puts most long word instructions on a single line. Use 8 bytes
11410 if (info
->mach
== bfd_mach_l1om
11411 || info
->mach
== bfd_mach_l1om_intel_syntax
)
11412 info
->bytes_per_line
= 8;
11414 info
->bytes_per_line
= 7;
11416 info
->private_data
= &priv
;
11417 priv
.max_fetched
= priv
.the_buffer
;
11418 priv
.insn_start
= pc
;
11421 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11429 start_codep
= priv
.the_buffer
;
11430 codep
= priv
.the_buffer
;
11432 if (setjmp (priv
.bailout
) != 0)
11436 /* Getting here means we tried for data but didn't get it. That
11437 means we have an incomplete instruction of some sort. Just
11438 print the first byte as a prefix or a .byte pseudo-op. */
11439 if (codep
> priv
.the_buffer
)
11441 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
11443 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11446 /* Just print the first byte as a .byte instruction. */
11447 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
11448 (unsigned int) priv
.the_buffer
[0]);
11458 sizeflag
= priv
.orig_sizeflag
;
11460 if (!ckprefix () || rex_used
)
11462 /* Too many prefixes or unused REX prefixes. */
11464 all_prefixes
[i
] && i
< (int) ARRAY_SIZE (all_prefixes
);
11466 (*info
->fprintf_func
) (info
->stream
, "%s",
11467 prefix_name (all_prefixes
[i
], sizeflag
));
11471 insn_codep
= codep
;
11473 FETCH_DATA (info
, codep
+ 1);
11474 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
11476 if (((prefixes
& PREFIX_FWAIT
)
11477 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
11479 (*info
->fprintf_func
) (info
->stream
, "fwait");
11483 if (*codep
== 0x0f)
11485 unsigned char threebyte
;
11486 FETCH_DATA (info
, codep
+ 2);
11487 threebyte
= *++codep
;
11488 dp
= &dis386_twobyte
[threebyte
];
11489 need_modrm
= twobyte_has_modrm
[*codep
];
11494 dp
= &dis386
[*codep
];
11495 need_modrm
= onebyte_has_modrm
[*codep
];
11499 if ((prefixes
& PREFIX_REPZ
))
11500 used_prefixes
|= PREFIX_REPZ
;
11501 if ((prefixes
& PREFIX_REPNZ
))
11502 used_prefixes
|= PREFIX_REPNZ
;
11503 if ((prefixes
& PREFIX_LOCK
))
11504 used_prefixes
|= PREFIX_LOCK
;
11506 default_prefixes
= 0;
11507 if (prefixes
& PREFIX_ADDR
)
11510 if (dp
->op
[2].bytemode
!= loop_jcxz_mode
|| intel_syntax
)
11512 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11513 all_prefixes
[last_addr_prefix
] = ADDR32_PREFIX
;
11515 all_prefixes
[last_addr_prefix
] = ADDR16_PREFIX
;
11516 default_prefixes
|= PREFIX_ADDR
;
11520 if ((prefixes
& PREFIX_DATA
))
11523 if (dp
->op
[2].bytemode
== cond_jump_mode
11524 && dp
->op
[0].bytemode
== v_mode
11527 if (sizeflag
& DFLAG
)
11528 all_prefixes
[last_data_prefix
] = DATA32_PREFIX
;
11530 all_prefixes
[last_data_prefix
] = DATA16_PREFIX
;
11531 default_prefixes
|= PREFIX_DATA
;
11533 else if (rex
& REX_W
)
11535 /* REX_W will override PREFIX_DATA. */
11536 default_prefixes
|= PREFIX_DATA
;
11542 FETCH_DATA (info
, codep
+ 1);
11543 modrm
.mod
= (*codep
>> 6) & 3;
11544 modrm
.reg
= (*codep
>> 3) & 7;
11545 modrm
.rm
= *codep
& 7;
11552 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
11555 dofloat (sizeflag
);
11559 dp
= get_valid_dis386 (dp
, info
);
11560 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
11563 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11566 op_ad
= MAX_OPERANDS
- 1 - i
;
11568 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
11573 /* See if any prefixes were not used. If so, print the first one
11574 separately. If we don't do this, we'll wind up printing an
11575 instruction stream which does not precisely correspond to the
11576 bytes we are disassembling. */
11577 if ((prefixes
& ~(used_prefixes
| default_prefixes
)) != 0)
11579 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11580 if (all_prefixes
[i
])
11583 name
= prefix_name (all_prefixes
[i
], priv
.orig_sizeflag
);
11585 name
= INTERNAL_DISASSEMBLER_ERROR
;
11586 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
11591 /* Check if the REX prefix is used. */
11592 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0)
11593 all_prefixes
[last_rex_prefix
] = 0;
11595 /* Check if the SEG prefix is used. */
11596 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
11597 | PREFIX_FS
| PREFIX_GS
)) != 0
11599 & seg_prefix (all_prefixes
[last_seg_prefix
])) != 0)
11600 all_prefixes
[last_seg_prefix
] = 0;
11602 /* Check if the ADDR prefix is used. */
11603 if ((prefixes
& PREFIX_ADDR
) != 0
11604 && (used_prefixes
& PREFIX_ADDR
) != 0)
11605 all_prefixes
[last_addr_prefix
] = 0;
11607 /* Check if the DATA prefix is used. */
11608 if ((prefixes
& PREFIX_DATA
) != 0
11609 && (used_prefixes
& PREFIX_DATA
) != 0)
11610 all_prefixes
[last_data_prefix
] = 0;
11613 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11614 if (all_prefixes
[i
])
11617 name
= prefix_name (all_prefixes
[i
], sizeflag
);
11620 prefix_length
+= strlen (name
) + 1;
11621 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
11624 /* Check maximum code length. */
11625 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
11627 (*info
->fprintf_func
) (info
->stream
, "(bad)");
11628 return MAX_CODE_LENGTH
;
11631 obufp
= mnemonicendp
;
11632 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
11635 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
11637 /* The enter and bound instructions are printed with operands in the same
11638 order as the intel book; everything else is printed in reverse order. */
11639 if (intel_syntax
|| two_source_ops
)
11643 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11644 op_txt
[i
] = op_out
[i
];
11646 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
11648 op_ad
= op_index
[i
];
11649 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
11650 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
11651 riprel
= op_riprel
[i
];
11652 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
11653 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
11658 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11659 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
11663 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
11667 (*info
->fprintf_func
) (info
->stream
, ",");
11668 if (op_index
[i
] != -1 && !op_riprel
[i
])
11669 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
11671 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
11675 for (i
= 0; i
< MAX_OPERANDS
; i
++)
11676 if (op_index
[i
] != -1 && op_riprel
[i
])
11678 (*info
->fprintf_func
) (info
->stream
, " # ");
11679 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
11680 + op_address
[op_index
[i
]]), info
);
11683 return codep
- priv
.the_buffer
;
11686 static const char *float_mem
[] = {
11761 static const unsigned char float_mem_mode
[] = {
11836 #define ST { OP_ST, 0 }
11837 #define STi { OP_STi, 0 }
11839 #define FGRPd9_2 NULL, { { NULL, 0 } }
11840 #define FGRPd9_4 NULL, { { NULL, 1 } }
11841 #define FGRPd9_5 NULL, { { NULL, 2 } }
11842 #define FGRPd9_6 NULL, { { NULL, 3 } }
11843 #define FGRPd9_7 NULL, { { NULL, 4 } }
11844 #define FGRPda_5 NULL, { { NULL, 5 } }
11845 #define FGRPdb_4 NULL, { { NULL, 6 } }
11846 #define FGRPde_3 NULL, { { NULL, 7 } }
11847 #define FGRPdf_4 NULL, { { NULL, 8 } }
11849 static const struct dis386 float_reg
[][8] = {
11852 { "fadd", { ST
, STi
} },
11853 { "fmul", { ST
, STi
} },
11854 { "fcom", { STi
} },
11855 { "fcomp", { STi
} },
11856 { "fsub", { ST
, STi
} },
11857 { "fsubr", { ST
, STi
} },
11858 { "fdiv", { ST
, STi
} },
11859 { "fdivr", { ST
, STi
} },
11863 { "fld", { STi
} },
11864 { "fxch", { STi
} },
11874 { "fcmovb", { ST
, STi
} },
11875 { "fcmove", { ST
, STi
} },
11876 { "fcmovbe",{ ST
, STi
} },
11877 { "fcmovu", { ST
, STi
} },
11885 { "fcmovnb",{ ST
, STi
} },
11886 { "fcmovne",{ ST
, STi
} },
11887 { "fcmovnbe",{ ST
, STi
} },
11888 { "fcmovnu",{ ST
, STi
} },
11890 { "fucomi", { ST
, STi
} },
11891 { "fcomi", { ST
, STi
} },
11896 { "fadd", { STi
, ST
} },
11897 { "fmul", { STi
, ST
} },
11900 { "fsub!M", { STi
, ST
} },
11901 { "fsubM", { STi
, ST
} },
11902 { "fdiv!M", { STi
, ST
} },
11903 { "fdivM", { STi
, ST
} },
11907 { "ffree", { STi
} },
11909 { "fst", { STi
} },
11910 { "fstp", { STi
} },
11911 { "fucom", { STi
} },
11912 { "fucomp", { STi
} },
11918 { "faddp", { STi
, ST
} },
11919 { "fmulp", { STi
, ST
} },
11922 { "fsub!Mp", { STi
, ST
} },
11923 { "fsubMp", { STi
, ST
} },
11924 { "fdiv!Mp", { STi
, ST
} },
11925 { "fdivMp", { STi
, ST
} },
11929 { "ffreep", { STi
} },
11934 { "fucomip", { ST
, STi
} },
11935 { "fcomip", { ST
, STi
} },
11940 static char *fgrps
[][8] = {
11943 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11948 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11953 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11958 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11963 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11968 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11973 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11974 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11979 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11984 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11989 swap_operand (void)
11991 mnemonicendp
[0] = '.';
11992 mnemonicendp
[1] = 's';
11997 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
11998 int sizeflag ATTRIBUTE_UNUSED
)
12000 /* Skip mod/rm byte. */
12006 dofloat (int sizeflag
)
12008 const struct dis386
*dp
;
12009 unsigned char floatop
;
12011 floatop
= codep
[-1];
12013 if (modrm
.mod
!= 3)
12015 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12017 putop (float_mem
[fp_indx
], sizeflag
);
12020 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12023 /* Skip mod/rm byte. */
12027 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12028 if (dp
->name
== NULL
)
12030 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12032 /* Instruction fnstsw is only one with strange arg. */
12033 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12034 strcpy (op_out
[0], names16
[0]);
12038 putop (dp
->name
, sizeflag
);
12043 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12048 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12053 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12055 oappend ("%st" + intel_syntax
);
12059 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12061 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12062 oappend (scratchbuf
+ intel_syntax
);
12065 /* Capital letters in template are macros. */
12067 putop (const char *in_template
, int sizeflag
)
12072 unsigned int l
= 0, len
= 1;
12075 #define SAVE_LAST(c) \
12076 if (l < len && l < sizeof (last)) \
12081 for (p
= in_template
; *p
; p
++)
12098 while (*++p
!= '|')
12099 if (*p
== '}' || *p
== '\0')
12102 /* Fall through. */
12107 while (*++p
!= '}')
12118 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12122 if (l
== 0 && len
== 1)
12127 if (sizeflag
& SUFFIX_ALWAYS
)
12140 if (address_mode
== mode_64bit
12141 && !(prefixes
& PREFIX_ADDR
))
12152 if (intel_syntax
&& !alt
)
12154 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12156 if (sizeflag
& DFLAG
)
12157 *obufp
++ = intel_syntax
? 'd' : 'l';
12159 *obufp
++ = intel_syntax
? 'w' : 's';
12160 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12164 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12167 if (modrm
.mod
== 3)
12173 if (sizeflag
& DFLAG
)
12174 *obufp
++ = intel_syntax
? 'd' : 'l';
12177 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12183 case 'E': /* For jcxz/jecxz */
12184 if (address_mode
== mode_64bit
)
12186 if (sizeflag
& AFLAG
)
12192 if (sizeflag
& AFLAG
)
12194 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12199 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12201 if (sizeflag
& AFLAG
)
12202 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12204 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12205 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12209 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12211 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12215 if (!(rex
& REX_W
))
12216 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12221 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12222 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12224 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12227 if (prefixes
& PREFIX_DS
)
12248 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12253 /* Fall through. */
12256 if (l
!= 0 || len
!= 1)
12264 if (sizeflag
& SUFFIX_ALWAYS
)
12268 if (intel_mnemonic
!= cond
)
12272 if ((prefixes
& PREFIX_FWAIT
) == 0)
12275 used_prefixes
|= PREFIX_FWAIT
;
12281 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12285 if (!(rex
& REX_W
))
12286 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12291 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12296 /* Fall through. */
12300 if ((prefixes
& PREFIX_DATA
)
12302 || (sizeflag
& SUFFIX_ALWAYS
))
12309 if (sizeflag
& DFLAG
)
12313 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12320 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12322 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12326 /* Fall through. */
12329 if (l
== 0 && len
== 1)
12332 if (intel_syntax
&& !alt
)
12335 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12341 if (sizeflag
& DFLAG
)
12342 *obufp
++ = intel_syntax
? 'd' : 'l';
12345 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12351 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12357 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12372 else if (sizeflag
& DFLAG
)
12381 if (intel_syntax
&& !p
[1]
12382 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
12384 if (!(rex
& REX_W
))
12385 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12388 if (l
== 0 && len
== 1)
12392 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12394 if (sizeflag
& SUFFIX_ALWAYS
)
12416 /* Fall through. */
12419 if (l
== 0 && len
== 1)
12424 if (sizeflag
& SUFFIX_ALWAYS
)
12430 if (sizeflag
& DFLAG
)
12434 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12448 if (address_mode
== mode_64bit
12449 && !(prefixes
& PREFIX_ADDR
))
12460 if (l
!= 0 || len
!= 1)
12465 if (need_vex
&& vex
.prefix
)
12467 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
12474 if (prefixes
& PREFIX_DATA
)
12478 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12482 if (l
== 0 && len
== 1)
12484 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12495 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12503 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
12505 switch (vex
.length
)
12519 if (l
== 0 && len
== 1)
12521 /* operand size flag for cwtl, cbtw */
12530 else if (sizeflag
& DFLAG
)
12534 if (!(rex
& REX_W
))
12535 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12539 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12546 *obufp
++ = vex
.w
? 'd': 's';
12553 mnemonicendp
= obufp
;
12558 oappend (const char *s
)
12560 obufp
= stpcpy (obufp
, s
);
12566 if (prefixes
& PREFIX_CS
)
12568 used_prefixes
|= PREFIX_CS
;
12569 oappend ("%cs:" + intel_syntax
);
12571 if (prefixes
& PREFIX_DS
)
12573 used_prefixes
|= PREFIX_DS
;
12574 oappend ("%ds:" + intel_syntax
);
12576 if (prefixes
& PREFIX_SS
)
12578 used_prefixes
|= PREFIX_SS
;
12579 oappend ("%ss:" + intel_syntax
);
12581 if (prefixes
& PREFIX_ES
)
12583 used_prefixes
|= PREFIX_ES
;
12584 oappend ("%es:" + intel_syntax
);
12586 if (prefixes
& PREFIX_FS
)
12588 used_prefixes
|= PREFIX_FS
;
12589 oappend ("%fs:" + intel_syntax
);
12591 if (prefixes
& PREFIX_GS
)
12593 used_prefixes
|= PREFIX_GS
;
12594 oappend ("%gs:" + intel_syntax
);
12599 OP_indirE (int bytemode
, int sizeflag
)
12603 OP_E (bytemode
, sizeflag
);
12607 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
12609 if (address_mode
== mode_64bit
)
12617 sprintf_vma (tmp
, disp
);
12618 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
12619 strcpy (buf
+ 2, tmp
+ i
);
12623 bfd_signed_vma v
= disp
;
12630 /* Check for possible overflow on 0x8000000000000000. */
12633 strcpy (buf
, "9223372036854775808");
12647 tmp
[28 - i
] = (v
% 10) + '0';
12651 strcpy (buf
, tmp
+ 29 - i
);
12657 sprintf (buf
, "0x%x", (unsigned int) disp
);
12659 sprintf (buf
, "%d", (int) disp
);
12663 /* Put DISP in BUF as signed hex number. */
12666 print_displacement (char *buf
, bfd_vma disp
)
12668 bfd_signed_vma val
= disp
;
12677 /* Check for possible overflow. */
12680 switch (address_mode
)
12683 strcpy (buf
+ j
, "0x8000000000000000");
12686 strcpy (buf
+ j
, "0x80000000");
12689 strcpy (buf
+ j
, "0x8000");
12699 sprintf_vma (tmp
, (bfd_vma
) val
);
12700 for (i
= 0; tmp
[i
] == '0'; i
++)
12702 if (tmp
[i
] == '\0')
12704 strcpy (buf
+ j
, tmp
+ i
);
12708 intel_operand_size (int bytemode
, int sizeflag
)
12715 oappend ("BYTE PTR ");
12719 oappend ("WORD PTR ");
12722 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12724 oappend ("QWORD PTR ");
12733 oappend ("QWORD PTR ");
12736 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
12737 oappend ("DWORD PTR ");
12739 oappend ("WORD PTR ");
12740 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12744 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12746 oappend ("WORD PTR ");
12747 if (!(rex
& REX_W
))
12748 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12751 if (sizeflag
& DFLAG
)
12752 oappend ("QWORD PTR ");
12754 oappend ("DWORD PTR ");
12755 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12758 case d_scalar_mode
:
12759 case d_scalar_swap_mode
:
12762 oappend ("DWORD PTR ");
12765 case q_scalar_mode
:
12766 case q_scalar_swap_mode
:
12768 oappend ("QWORD PTR ");
12771 if (address_mode
== mode_64bit
)
12772 oappend ("QWORD PTR ");
12774 oappend ("DWORD PTR ");
12777 if (sizeflag
& DFLAG
)
12778 oappend ("FWORD PTR ");
12780 oappend ("DWORD PTR ");
12781 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12784 oappend ("TBYTE PTR ");
12790 switch (vex
.length
)
12793 oappend ("XMMWORD PTR ");
12796 oappend ("YMMWORD PTR ");
12803 oappend ("XMMWORD PTR ");
12806 oappend ("XMMWORD PTR ");
12812 switch (vex
.length
)
12815 oappend ("QWORD PTR ");
12818 oappend ("XMMWORD PTR ");
12828 switch (vex
.length
)
12831 oappend ("QWORD PTR ");
12834 oappend ("YMMWORD PTR ");
12841 oappend ("OWORD PTR ");
12843 case vex_w_dq_mode
:
12844 case vex_scalar_w_dq_mode
:
12849 oappend ("QWORD PTR ");
12851 oappend ("DWORD PTR ");
12859 OP_E_register (int bytemode
, int sizeflag
)
12861 int reg
= modrm
.rm
;
12862 const char **names
;
12868 if ((sizeflag
& SUFFIX_ALWAYS
)
12869 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
12892 names
= address_mode
== mode_64bit
? names64
: names32
;
12895 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
12913 if ((sizeflag
& DFLAG
)
12914 || (bytemode
!= v_mode
12915 && bytemode
!= v_swap_mode
))
12919 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12925 oappend (INTERNAL_DISASSEMBLER_ERROR
);
12928 oappend (names
[reg
]);
12932 OP_E_memory (int bytemode
, int sizeflag
)
12935 int add
= (rex
& REX_B
) ? 8 : 0;
12940 intel_operand_size (bytemode
, sizeflag
);
12943 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12945 /* 32/64 bit address mode */
12963 vindex
= sib
.index
;
12969 haveindex
= vindex
!= 4;
12972 rbase
= base
+ add
;
12980 if (address_mode
== mode_64bit
&& !havesib
)
12986 FETCH_DATA (the_info
, codep
+ 1);
12988 if ((disp
& 0x80) != 0)
12996 /* In 32bit mode, we need index register to tell [offset] from
12997 [eiz*1 + offset]. */
12998 needindex
= (havesib
13001 && address_mode
== mode_32bit
);
13002 havedisp
= (havebase
13004 || (havesib
&& (haveindex
|| scale
!= 0)));
13007 if (modrm
.mod
!= 0 || base
== 5)
13009 if (havedisp
|| riprel
)
13010 print_displacement (scratchbuf
, disp
);
13012 print_operand_value (scratchbuf
, 1, disp
);
13013 oappend (scratchbuf
);
13017 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
13021 if (havebase
|| haveindex
|| riprel
)
13022 used_prefixes
|= PREFIX_ADDR
;
13024 if (havedisp
|| (intel_syntax
&& riprel
))
13026 *obufp
++ = open_char
;
13027 if (intel_syntax
&& riprel
)
13030 oappend (sizeflag
& AFLAG
? "rip" : "eip");
13034 oappend (address_mode
== mode_64bit
&& (sizeflag
& AFLAG
)
13035 ? names64
[rbase
] : names32
[rbase
]);
13038 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13039 print index to tell base + index from base. */
13043 || (havebase
&& base
!= ESP_REG_NUM
))
13045 if (!intel_syntax
|| havebase
)
13047 *obufp
++ = separator_char
;
13051 oappend (address_mode
== mode_64bit
13052 && (sizeflag
& AFLAG
)
13053 ? names64
[vindex
] : names32
[vindex
]);
13055 oappend (address_mode
== mode_64bit
13056 && (sizeflag
& AFLAG
)
13057 ? index64
: index32
);
13059 *obufp
++ = scale_char
;
13061 sprintf (scratchbuf
, "%d", 1 << scale
);
13062 oappend (scratchbuf
);
13066 && (disp
|| modrm
.mod
!= 0 || base
== 5))
13068 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
13073 else if (modrm
.mod
!= 1 && disp
!= -disp
)
13077 disp
= - (bfd_signed_vma
) disp
;
13081 print_displacement (scratchbuf
, disp
);
13083 print_operand_value (scratchbuf
, 1, disp
);
13084 oappend (scratchbuf
);
13087 *obufp
++ = close_char
;
13090 else if (intel_syntax
)
13092 if (modrm
.mod
!= 0 || base
== 5)
13094 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13095 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13099 oappend (names_seg
[ds_reg
- es_reg
]);
13102 print_operand_value (scratchbuf
, 1, disp
);
13103 oappend (scratchbuf
);
13109 /* 16 bit address mode */
13110 used_prefixes
|= prefixes
& PREFIX_ADDR
;
13117 if ((disp
& 0x8000) != 0)
13122 FETCH_DATA (the_info
, codep
+ 1);
13124 if ((disp
& 0x80) != 0)
13129 if ((disp
& 0x8000) != 0)
13135 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
13137 print_displacement (scratchbuf
, disp
);
13138 oappend (scratchbuf
);
13141 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
13143 *obufp
++ = open_char
;
13145 oappend (index16
[modrm
.rm
]);
13147 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
13149 if ((bfd_signed_vma
) disp
>= 0)
13154 else if (modrm
.mod
!= 1)
13158 disp
= - (bfd_signed_vma
) disp
;
13161 print_displacement (scratchbuf
, disp
);
13162 oappend (scratchbuf
);
13165 *obufp
++ = close_char
;
13168 else if (intel_syntax
)
13170 if (prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13171 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
))
13175 oappend (names_seg
[ds_reg
- es_reg
]);
13178 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
13179 oappend (scratchbuf
);
13185 OP_E (int bytemode
, int sizeflag
)
13187 /* Skip mod/rm byte. */
13191 if (modrm
.mod
== 3)
13192 OP_E_register (bytemode
, sizeflag
);
13194 OP_E_memory (bytemode
, sizeflag
);
13198 OP_G (int bytemode
, int sizeflag
)
13209 oappend (names8rex
[modrm
.reg
+ add
]);
13211 oappend (names8
[modrm
.reg
+ add
]);
13214 oappend (names16
[modrm
.reg
+ add
]);
13217 oappend (names32
[modrm
.reg
+ add
]);
13220 oappend (names64
[modrm
.reg
+ add
]);
13229 oappend (names64
[modrm
.reg
+ add
]);
13232 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
13233 oappend (names32
[modrm
.reg
+ add
]);
13235 oappend (names16
[modrm
.reg
+ add
]);
13236 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13240 if (address_mode
== mode_64bit
)
13241 oappend (names64
[modrm
.reg
+ add
]);
13243 oappend (names32
[modrm
.reg
+ add
]);
13246 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13259 FETCH_DATA (the_info
, codep
+ 8);
13260 a
= *codep
++ & 0xff;
13261 a
|= (*codep
++ & 0xff) << 8;
13262 a
|= (*codep
++ & 0xff) << 16;
13263 a
|= (*codep
++ & 0xff) << 24;
13264 b
= *codep
++ & 0xff;
13265 b
|= (*codep
++ & 0xff) << 8;
13266 b
|= (*codep
++ & 0xff) << 16;
13267 b
|= (*codep
++ & 0xff) << 24;
13268 x
= a
+ ((bfd_vma
) b
<< 32);
13276 static bfd_signed_vma
13279 bfd_signed_vma x
= 0;
13281 FETCH_DATA (the_info
, codep
+ 4);
13282 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13283 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13284 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13285 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13289 static bfd_signed_vma
13292 bfd_signed_vma x
= 0;
13294 FETCH_DATA (the_info
, codep
+ 4);
13295 x
= *codep
++ & (bfd_signed_vma
) 0xff;
13296 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
13297 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
13298 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
13300 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
13310 FETCH_DATA (the_info
, codep
+ 2);
13311 x
= *codep
++ & 0xff;
13312 x
|= (*codep
++ & 0xff) << 8;
13317 set_op (bfd_vma op
, int riprel
)
13319 op_index
[op_ad
] = op_ad
;
13320 if (address_mode
== mode_64bit
)
13322 op_address
[op_ad
] = op
;
13323 op_riprel
[op_ad
] = riprel
;
13327 /* Mask to get a 32-bit address. */
13328 op_address
[op_ad
] = op
& 0xffffffff;
13329 op_riprel
[op_ad
] = riprel
& 0xffffffff;
13334 OP_REG (int code
, int sizeflag
)
13346 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13347 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13348 s
= names16
[code
- ax_reg
+ add
];
13350 case es_reg
: case ss_reg
: case cs_reg
:
13351 case ds_reg
: case fs_reg
: case gs_reg
:
13352 s
= names_seg
[code
- es_reg
+ add
];
13354 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13355 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13358 s
= names8rex
[code
- al_reg
+ add
];
13360 s
= names8
[code
- al_reg
];
13362 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
13363 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
13364 if (address_mode
== mode_64bit
&& (sizeflag
& DFLAG
))
13366 s
= names64
[code
- rAX_reg
+ add
];
13369 code
+= eAX_reg
- rAX_reg
;
13370 /* Fall through. */
13371 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13372 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13375 s
= names64
[code
- eAX_reg
+ add
];
13378 if (sizeflag
& DFLAG
)
13379 s
= names32
[code
- eAX_reg
+ add
];
13381 s
= names16
[code
- eAX_reg
+ add
];
13382 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13386 s
= INTERNAL_DISASSEMBLER_ERROR
;
13393 OP_IMREG (int code
, int sizeflag
)
13405 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
13406 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
13407 s
= names16
[code
- ax_reg
];
13409 case es_reg
: case ss_reg
: case cs_reg
:
13410 case ds_reg
: case fs_reg
: case gs_reg
:
13411 s
= names_seg
[code
- es_reg
];
13413 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
13414 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
13417 s
= names8rex
[code
- al_reg
];
13419 s
= names8
[code
- al_reg
];
13421 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
13422 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
13425 s
= names64
[code
- eAX_reg
];
13428 if (sizeflag
& DFLAG
)
13429 s
= names32
[code
- eAX_reg
];
13431 s
= names16
[code
- eAX_reg
];
13432 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13435 case z_mode_ax_reg
:
13436 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13440 if (!(rex
& REX_W
))
13441 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13444 s
= INTERNAL_DISASSEMBLER_ERROR
;
13451 OP_I (int bytemode
, int sizeflag
)
13454 bfd_signed_vma mask
= -1;
13459 FETCH_DATA (the_info
, codep
+ 1);
13464 if (address_mode
== mode_64bit
)
13469 /* Fall through. */
13476 if (sizeflag
& DFLAG
)
13486 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13498 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13503 scratchbuf
[0] = '$';
13504 print_operand_value (scratchbuf
+ 1, 1, op
);
13505 oappend (scratchbuf
+ intel_syntax
);
13506 scratchbuf
[0] = '\0';
13510 OP_I64 (int bytemode
, int sizeflag
)
13513 bfd_signed_vma mask
= -1;
13515 if (address_mode
!= mode_64bit
)
13517 OP_I (bytemode
, sizeflag
);
13524 FETCH_DATA (the_info
, codep
+ 1);
13534 if (sizeflag
& DFLAG
)
13544 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13552 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13557 scratchbuf
[0] = '$';
13558 print_operand_value (scratchbuf
+ 1, 1, op
);
13559 oappend (scratchbuf
+ intel_syntax
);
13560 scratchbuf
[0] = '\0';
13564 OP_sI (int bytemode
, int sizeflag
)
13571 FETCH_DATA (the_info
, codep
+ 1);
13573 if ((op
& 0x80) != 0)
13582 if (sizeflag
& DFLAG
)
13589 if ((op
& 0x8000) != 0)
13592 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13597 if ((op
& 0x8000) != 0)
13601 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13605 scratchbuf
[0] = '$';
13606 print_operand_value (scratchbuf
+ 1, 1, op
);
13607 oappend (scratchbuf
+ intel_syntax
);
13611 OP_J (int bytemode
, int sizeflag
)
13615 bfd_vma segment
= 0;
13620 FETCH_DATA (the_info
, codep
+ 1);
13622 if ((disp
& 0x80) != 0)
13627 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
13632 if ((disp
& 0x8000) != 0)
13634 /* In 16bit mode, address is wrapped around at 64k within
13635 the same segment. Otherwise, a data16 prefix on a jump
13636 instruction means that the pc is masked to 16 bits after
13637 the displacement is added! */
13639 if ((prefixes
& PREFIX_DATA
) == 0)
13640 segment
= ((start_pc
+ codep
- start_codep
)
13641 & ~((bfd_vma
) 0xffff));
13643 if (!(rex
& REX_W
))
13644 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13647 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13650 disp
= ((start_pc
+ codep
- start_codep
+ disp
) & mask
) | segment
;
13652 print_operand_value (scratchbuf
, 1, disp
);
13653 oappend (scratchbuf
);
13657 OP_SEG (int bytemode
, int sizeflag
)
13659 if (bytemode
== w_mode
)
13660 oappend (names_seg
[modrm
.reg
]);
13662 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
13666 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
13670 if (sizeflag
& DFLAG
)
13680 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13682 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
13684 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
13685 oappend (scratchbuf
);
13689 OP_OFF (int bytemode
, int sizeflag
)
13693 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13694 intel_operand_size (bytemode
, sizeflag
);
13697 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13704 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13705 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13707 oappend (names_seg
[ds_reg
- es_reg
]);
13711 print_operand_value (scratchbuf
, 1, off
);
13712 oappend (scratchbuf
);
13716 OP_OFF64 (int bytemode
, int sizeflag
)
13720 if (address_mode
!= mode_64bit
13721 || (prefixes
& PREFIX_ADDR
))
13723 OP_OFF (bytemode
, sizeflag
);
13727 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
13728 intel_operand_size (bytemode
, sizeflag
);
13735 if (!(prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
13736 | PREFIX_ES
| PREFIX_FS
| PREFIX_GS
)))
13738 oappend (names_seg
[ds_reg
- es_reg
]);
13742 print_operand_value (scratchbuf
, 1, off
);
13743 oappend (scratchbuf
);
13747 ptr_reg (int code
, int sizeflag
)
13751 *obufp
++ = open_char
;
13752 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13753 if (address_mode
== mode_64bit
)
13755 if (!(sizeflag
& AFLAG
))
13756 s
= names32
[code
- eAX_reg
];
13758 s
= names64
[code
- eAX_reg
];
13760 else if (sizeflag
& AFLAG
)
13761 s
= names32
[code
- eAX_reg
];
13763 s
= names16
[code
- eAX_reg
];
13765 *obufp
++ = close_char
;
13770 OP_ESreg (int code
, int sizeflag
)
13776 case 0x6d: /* insw/insl */
13777 intel_operand_size (z_mode
, sizeflag
);
13779 case 0xa5: /* movsw/movsl/movsq */
13780 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13781 case 0xab: /* stosw/stosl */
13782 case 0xaf: /* scasw/scasl */
13783 intel_operand_size (v_mode
, sizeflag
);
13786 intel_operand_size (b_mode
, sizeflag
);
13789 oappend ("%es:" + intel_syntax
);
13790 ptr_reg (code
, sizeflag
);
13794 OP_DSreg (int code
, int sizeflag
)
13800 case 0x6f: /* outsw/outsl */
13801 intel_operand_size (z_mode
, sizeflag
);
13803 case 0xa5: /* movsw/movsl/movsq */
13804 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13805 case 0xad: /* lodsw/lodsl/lodsq */
13806 intel_operand_size (v_mode
, sizeflag
);
13809 intel_operand_size (b_mode
, sizeflag
);
13818 | PREFIX_GS
)) == 0)
13819 prefixes
|= PREFIX_DS
;
13821 ptr_reg (code
, sizeflag
);
13825 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13833 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
13835 all_prefixes
[last_lock_prefix
] = 0;
13836 used_prefixes
|= PREFIX_LOCK
;
13841 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
13842 oappend (scratchbuf
+ intel_syntax
);
13846 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13855 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
13857 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
13858 oappend (scratchbuf
);
13862 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13864 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
13865 oappend (scratchbuf
+ intel_syntax
);
13869 OP_R (int bytemode
, int sizeflag
)
13871 if (modrm
.mod
== 3)
13872 OP_E (bytemode
, sizeflag
);
13878 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13880 int reg
= modrm
.reg
;
13881 const char **names
;
13883 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13884 if (prefixes
& PREFIX_DATA
)
13893 oappend (names
[reg
]);
13897 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
13899 int reg
= modrm
.reg
;
13900 const char **names
;
13906 && bytemode
!= xmm_mode
13907 && bytemode
!= scalar_mode
)
13909 switch (vex
.length
)
13923 oappend (names
[reg
]);
13927 OP_EM (int bytemode
, int sizeflag
)
13930 const char **names
;
13932 if (modrm
.mod
!= 3)
13935 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
13937 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13938 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13940 OP_E (bytemode
, sizeflag
);
13944 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
13947 /* Skip mod/rm byte. */
13950 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13952 if (prefixes
& PREFIX_DATA
)
13961 oappend (names
[reg
]);
13964 /* cvt* are the only instructions in sse2 which have
13965 both SSE and MMX operands and also have 0x66 prefix
13966 in their opcode. 0x66 was originally used to differentiate
13967 between SSE and MMX instruction(operands). So we have to handle the
13968 cvt* separately using OP_EMC and OP_MXC */
13970 OP_EMC (int bytemode
, int sizeflag
)
13972 if (modrm
.mod
!= 3)
13974 if (intel_syntax
&& bytemode
== v_mode
)
13976 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
13977 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13979 OP_E (bytemode
, sizeflag
);
13983 /* Skip mod/rm byte. */
13986 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13987 oappend (names_mm
[modrm
.rm
]);
13991 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13993 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13994 oappend (names_mm
[modrm
.reg
]);
13998 OP_EX (int bytemode
, int sizeflag
)
14001 const char **names
;
14003 /* Skip mod/rm byte. */
14007 if (modrm
.mod
!= 3)
14009 OP_E_memory (bytemode
, sizeflag
);
14018 if ((sizeflag
& SUFFIX_ALWAYS
)
14019 && (bytemode
== x_swap_mode
14020 || bytemode
== d_swap_mode
14021 || bytemode
== d_scalar_swap_mode
14022 || bytemode
== q_swap_mode
14023 || bytemode
== q_scalar_swap_mode
))
14027 && bytemode
!= xmm_mode
14028 && bytemode
!= xmmq_mode
14029 && bytemode
!= d_scalar_mode
14030 && bytemode
!= d_scalar_swap_mode
14031 && bytemode
!= q_scalar_mode
14032 && bytemode
!= q_scalar_swap_mode
14033 && bytemode
!= vex_scalar_w_dq_mode
)
14035 switch (vex
.length
)
14049 oappend (names
[reg
]);
14053 OP_MS (int bytemode
, int sizeflag
)
14055 if (modrm
.mod
== 3)
14056 OP_EM (bytemode
, sizeflag
);
14062 OP_XS (int bytemode
, int sizeflag
)
14064 if (modrm
.mod
== 3)
14065 OP_EX (bytemode
, sizeflag
);
14071 OP_M (int bytemode
, int sizeflag
)
14073 if (modrm
.mod
== 3)
14074 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14077 OP_E (bytemode
, sizeflag
);
14081 OP_0f07 (int bytemode
, int sizeflag
)
14083 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
14086 OP_E (bytemode
, sizeflag
);
14089 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14090 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14093 NOP_Fixup1 (int bytemode
, int sizeflag
)
14095 if ((prefixes
& PREFIX_DATA
) != 0
14098 && address_mode
== mode_64bit
))
14099 OP_REG (bytemode
, sizeflag
);
14101 strcpy (obuf
, "nop");
14105 NOP_Fixup2 (int bytemode
, int sizeflag
)
14107 if ((prefixes
& PREFIX_DATA
) != 0
14110 && address_mode
== mode_64bit
))
14111 OP_IMREG (bytemode
, sizeflag
);
14114 static const char *const Suffix3DNow
[] = {
14115 /* 00 */ NULL
, NULL
, NULL
, NULL
,
14116 /* 04 */ NULL
, NULL
, NULL
, NULL
,
14117 /* 08 */ NULL
, NULL
, NULL
, NULL
,
14118 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
14119 /* 10 */ NULL
, NULL
, NULL
, NULL
,
14120 /* 14 */ NULL
, NULL
, NULL
, NULL
,
14121 /* 18 */ NULL
, NULL
, NULL
, NULL
,
14122 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
14123 /* 20 */ NULL
, NULL
, NULL
, NULL
,
14124 /* 24 */ NULL
, NULL
, NULL
, NULL
,
14125 /* 28 */ NULL
, NULL
, NULL
, NULL
,
14126 /* 2C */ NULL
, NULL
, NULL
, NULL
,
14127 /* 30 */ NULL
, NULL
, NULL
, NULL
,
14128 /* 34 */ NULL
, NULL
, NULL
, NULL
,
14129 /* 38 */ NULL
, NULL
, NULL
, NULL
,
14130 /* 3C */ NULL
, NULL
, NULL
, NULL
,
14131 /* 40 */ NULL
, NULL
, NULL
, NULL
,
14132 /* 44 */ NULL
, NULL
, NULL
, NULL
,
14133 /* 48 */ NULL
, NULL
, NULL
, NULL
,
14134 /* 4C */ NULL
, NULL
, NULL
, NULL
,
14135 /* 50 */ NULL
, NULL
, NULL
, NULL
,
14136 /* 54 */ NULL
, NULL
, NULL
, NULL
,
14137 /* 58 */ NULL
, NULL
, NULL
, NULL
,
14138 /* 5C */ NULL
, NULL
, NULL
, NULL
,
14139 /* 60 */ NULL
, NULL
, NULL
, NULL
,
14140 /* 64 */ NULL
, NULL
, NULL
, NULL
,
14141 /* 68 */ NULL
, NULL
, NULL
, NULL
,
14142 /* 6C */ NULL
, NULL
, NULL
, NULL
,
14143 /* 70 */ NULL
, NULL
, NULL
, NULL
,
14144 /* 74 */ NULL
, NULL
, NULL
, NULL
,
14145 /* 78 */ NULL
, NULL
, NULL
, NULL
,
14146 /* 7C */ NULL
, NULL
, NULL
, NULL
,
14147 /* 80 */ NULL
, NULL
, NULL
, NULL
,
14148 /* 84 */ NULL
, NULL
, NULL
, NULL
,
14149 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
14150 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
14151 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
14152 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
14153 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
14154 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
14155 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
14156 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
14157 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
14158 /* AC */ NULL
, NULL
, "pfacc", NULL
,
14159 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
14160 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
14161 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
14162 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
14163 /* C0 */ NULL
, NULL
, NULL
, NULL
,
14164 /* C4 */ NULL
, NULL
, NULL
, NULL
,
14165 /* C8 */ NULL
, NULL
, NULL
, NULL
,
14166 /* CC */ NULL
, NULL
, NULL
, NULL
,
14167 /* D0 */ NULL
, NULL
, NULL
, NULL
,
14168 /* D4 */ NULL
, NULL
, NULL
, NULL
,
14169 /* D8 */ NULL
, NULL
, NULL
, NULL
,
14170 /* DC */ NULL
, NULL
, NULL
, NULL
,
14171 /* E0 */ NULL
, NULL
, NULL
, NULL
,
14172 /* E4 */ NULL
, NULL
, NULL
, NULL
,
14173 /* E8 */ NULL
, NULL
, NULL
, NULL
,
14174 /* EC */ NULL
, NULL
, NULL
, NULL
,
14175 /* F0 */ NULL
, NULL
, NULL
, NULL
,
14176 /* F4 */ NULL
, NULL
, NULL
, NULL
,
14177 /* F8 */ NULL
, NULL
, NULL
, NULL
,
14178 /* FC */ NULL
, NULL
, NULL
, NULL
,
14182 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14184 const char *mnemonic
;
14186 FETCH_DATA (the_info
, codep
+ 1);
14187 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14188 place where an 8-bit immediate would normally go. ie. the last
14189 byte of the instruction. */
14190 obufp
= mnemonicendp
;
14191 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
14193 oappend (mnemonic
);
14196 /* Since a variable sized modrm/sib chunk is between the start
14197 of the opcode (0x0f0f) and the opcode suffix, we need to do
14198 all the modrm processing first, and don't know until now that
14199 we have a bad opcode. This necessitates some cleaning up. */
14200 op_out
[0][0] = '\0';
14201 op_out
[1][0] = '\0';
14204 mnemonicendp
= obufp
;
14207 static struct op simd_cmp_op
[] =
14209 { STRING_COMMA_LEN ("eq") },
14210 { STRING_COMMA_LEN ("lt") },
14211 { STRING_COMMA_LEN ("le") },
14212 { STRING_COMMA_LEN ("unord") },
14213 { STRING_COMMA_LEN ("neq") },
14214 { STRING_COMMA_LEN ("nlt") },
14215 { STRING_COMMA_LEN ("nle") },
14216 { STRING_COMMA_LEN ("ord") }
14220 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14222 unsigned int cmp_type
;
14224 FETCH_DATA (the_info
, codep
+ 1);
14225 cmp_type
= *codep
++ & 0xff;
14226 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
14229 char *p
= mnemonicendp
- 2;
14233 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
14234 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
14238 /* We have a reserved extension byte. Output it directly. */
14239 scratchbuf
[0] = '$';
14240 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14241 oappend (scratchbuf
+ intel_syntax
);
14242 scratchbuf
[0] = '\0';
14247 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
14248 int sizeflag ATTRIBUTE_UNUSED
)
14250 /* mwait %eax,%ecx */
14253 const char **names
= (address_mode
== mode_64bit
14254 ? names64
: names32
);
14255 strcpy (op_out
[0], names
[0]);
14256 strcpy (op_out
[1], names
[1]);
14257 two_source_ops
= 1;
14259 /* Skip mod/rm byte. */
14265 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
14266 int sizeflag ATTRIBUTE_UNUSED
)
14268 /* monitor %eax,%ecx,%edx" */
14271 const char **op1_names
;
14272 const char **names
= (address_mode
== mode_64bit
14273 ? names64
: names32
);
14275 if (!(prefixes
& PREFIX_ADDR
))
14276 op1_names
= (address_mode
== mode_16bit
14277 ? names16
: names
);
14280 /* Remove "addr16/addr32". */
14281 all_prefixes
[last_addr_prefix
] = 0;
14282 op1_names
= (address_mode
!= mode_32bit
14283 ? names32
: names16
);
14284 used_prefixes
|= PREFIX_ADDR
;
14286 strcpy (op_out
[0], op1_names
[0]);
14287 strcpy (op_out
[1], names
[1]);
14288 strcpy (op_out
[2], names
[2]);
14289 two_source_ops
= 1;
14291 /* Skip mod/rm byte. */
14299 /* Throw away prefixes and 1st. opcode byte. */
14300 codep
= insn_codep
+ 1;
14305 REP_Fixup (int bytemode
, int sizeflag
)
14307 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14309 if (prefixes
& PREFIX_REPZ
)
14310 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
14317 OP_IMREG (bytemode
, sizeflag
);
14320 OP_ESreg (bytemode
, sizeflag
);
14323 OP_DSreg (bytemode
, sizeflag
);
14332 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
14337 /* Change cmpxchg8b to cmpxchg16b. */
14338 char *p
= mnemonicendp
- 2;
14339 mnemonicendp
= stpcpy (p
, "16b");
14342 OP_M (bytemode
, sizeflag
);
14346 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
14348 const char **names
;
14352 switch (vex
.length
)
14366 oappend (names
[reg
]);
14370 CRC32_Fixup (int bytemode
, int sizeflag
)
14372 /* Add proper suffix to "crc32". */
14373 char *p
= mnemonicendp
;
14392 if (sizeflag
& DFLAG
)
14396 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14400 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14407 if (modrm
.mod
== 3)
14411 /* Skip mod/rm byte. */
14416 add
= (rex
& REX_B
) ? 8 : 0;
14417 if (bytemode
== b_mode
)
14421 oappend (names8rex
[modrm
.rm
+ add
]);
14423 oappend (names8
[modrm
.rm
+ add
]);
14429 oappend (names64
[modrm
.rm
+ add
]);
14430 else if ((prefixes
& PREFIX_DATA
))
14431 oappend (names16
[modrm
.rm
+ add
]);
14433 oappend (names32
[modrm
.rm
+ add
]);
14437 OP_E (bytemode
, sizeflag
);
14441 FXSAVE_Fixup (int bytemode
, int sizeflag
)
14443 /* Add proper suffix to "fxsave" and "fxrstor". */
14447 char *p
= mnemonicendp
;
14453 OP_M (bytemode
, sizeflag
);
14456 /* Display the destination register operand for instructions with
14460 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14463 const char **names
;
14471 reg
= vex
.register_specifier
;
14472 if (bytemode
== vex_scalar_mode
)
14474 oappend (names_xmm
[reg
]);
14478 switch (vex
.length
)
14510 oappend (names
[reg
]);
14513 /* Get the VEX immediate byte without moving codep. */
14515 static unsigned char
14516 get_vex_imm8 (int sizeflag
, int opnum
)
14518 int bytes_before_imm
= 0;
14520 if (modrm
.mod
!= 3)
14522 /* There are SIB/displacement bytes. */
14523 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14525 /* 32/64 bit address mode */
14526 int base
= modrm
.rm
;
14528 /* Check SIB byte. */
14531 FETCH_DATA (the_info
, codep
+ 1);
14533 /* When decoding the third source, don't increase
14534 bytes_before_imm as this has already been incremented
14535 by one in OP_E_memory while decoding the second
14538 bytes_before_imm
++;
14541 /* Don't increase bytes_before_imm when decoding the third source,
14542 it has already been incremented by OP_E_memory while decoding
14543 the second source operand. */
14549 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14550 SIB == 5, there is a 4 byte displacement. */
14552 /* No displacement. */
14555 /* 4 byte displacement. */
14556 bytes_before_imm
+= 4;
14559 /* 1 byte displacement. */
14560 bytes_before_imm
++;
14567 /* 16 bit address mode */
14568 /* Don't increase bytes_before_imm when decoding the third source,
14569 it has already been incremented by OP_E_memory while decoding
14570 the second source operand. */
14576 /* When modrm.rm == 6, there is a 2 byte displacement. */
14578 /* No displacement. */
14581 /* 2 byte displacement. */
14582 bytes_before_imm
+= 2;
14585 /* 1 byte displacement: when decoding the third source,
14586 don't increase bytes_before_imm as this has already
14587 been incremented by one in OP_E_memory while decoding
14588 the second source operand. */
14590 bytes_before_imm
++;
14598 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
14599 return codep
[bytes_before_imm
];
14603 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
14605 const char **names
;
14607 if (reg
== -1 && modrm
.mod
!= 3)
14609 OP_E_memory (bytemode
, sizeflag
);
14621 else if (reg
> 7 && address_mode
!= mode_64bit
)
14625 switch (vex
.length
)
14636 oappend (names
[reg
]);
14640 OP_EX_VexImmW (int bytemode
, int sizeflag
)
14643 static unsigned char vex_imm8
;
14645 if (vex_w_done
== 0)
14649 /* Skip mod/rm byte. */
14653 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
14656 reg
= vex_imm8
>> 4;
14658 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14660 else if (vex_w_done
== 1)
14665 reg
= vex_imm8
>> 4;
14667 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14671 /* Output the imm8 directly. */
14672 scratchbuf
[0] = '$';
14673 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
14674 oappend (scratchbuf
+ intel_syntax
);
14675 scratchbuf
[0] = '\0';
14681 OP_Vex_2src (int bytemode
, int sizeflag
)
14683 if (modrm
.mod
== 3)
14685 int reg
= modrm
.rm
;
14689 oappend (names_xmm
[reg
]);
14694 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
14696 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
14697 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14699 OP_E (bytemode
, sizeflag
);
14704 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
14706 if (modrm
.mod
== 3)
14708 /* Skip mod/rm byte. */
14714 oappend (names_xmm
[vex
.register_specifier
]);
14716 OP_Vex_2src (bytemode
, sizeflag
);
14720 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
14723 OP_Vex_2src (bytemode
, sizeflag
);
14725 oappend (names_xmm
[vex
.register_specifier
]);
14729 OP_EX_VexW (int bytemode
, int sizeflag
)
14737 /* Skip mod/rm byte. */
14742 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
14747 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
14750 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
14754 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14755 int sizeflag ATTRIBUTE_UNUSED
)
14757 /* Skip the immediate byte and check for invalid bits. */
14758 FETCH_DATA (the_info
, codep
+ 1);
14759 if (*codep
++ & 0xf)
14764 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
14767 const char **names
;
14769 FETCH_DATA (the_info
, codep
+ 1);
14772 if (bytemode
!= x_mode
)
14779 if (reg
> 7 && address_mode
!= mode_64bit
)
14782 switch (vex
.length
)
14793 oappend (names
[reg
]);
14797 OP_XMM_VexW (int bytemode
, int sizeflag
)
14799 /* Turn off the REX.W bit since it is used for swapping operands
14802 OP_XMM (bytemode
, sizeflag
);
14806 OP_EX_Vex (int bytemode
, int sizeflag
)
14808 if (modrm
.mod
!= 3)
14810 if (vex
.register_specifier
!= 0)
14814 OP_EX (bytemode
, sizeflag
);
14818 OP_XMM_Vex (int bytemode
, int sizeflag
)
14820 if (modrm
.mod
!= 3)
14822 if (vex
.register_specifier
!= 0)
14826 OP_XMM (bytemode
, sizeflag
);
14830 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14832 switch (vex
.length
)
14835 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
14838 mnemonicendp
= stpcpy (obuf
, "vzeroall");
14845 static struct op vex_cmp_op
[] =
14847 { STRING_COMMA_LEN ("eq") },
14848 { STRING_COMMA_LEN ("lt") },
14849 { STRING_COMMA_LEN ("le") },
14850 { STRING_COMMA_LEN ("unord") },
14851 { STRING_COMMA_LEN ("neq") },
14852 { STRING_COMMA_LEN ("nlt") },
14853 { STRING_COMMA_LEN ("nle") },
14854 { STRING_COMMA_LEN ("ord") },
14855 { STRING_COMMA_LEN ("eq_uq") },
14856 { STRING_COMMA_LEN ("nge") },
14857 { STRING_COMMA_LEN ("ngt") },
14858 { STRING_COMMA_LEN ("false") },
14859 { STRING_COMMA_LEN ("neq_oq") },
14860 { STRING_COMMA_LEN ("ge") },
14861 { STRING_COMMA_LEN ("gt") },
14862 { STRING_COMMA_LEN ("true") },
14863 { STRING_COMMA_LEN ("eq_os") },
14864 { STRING_COMMA_LEN ("lt_oq") },
14865 { STRING_COMMA_LEN ("le_oq") },
14866 { STRING_COMMA_LEN ("unord_s") },
14867 { STRING_COMMA_LEN ("neq_us") },
14868 { STRING_COMMA_LEN ("nlt_uq") },
14869 { STRING_COMMA_LEN ("nle_uq") },
14870 { STRING_COMMA_LEN ("ord_s") },
14871 { STRING_COMMA_LEN ("eq_us") },
14872 { STRING_COMMA_LEN ("nge_uq") },
14873 { STRING_COMMA_LEN ("ngt_uq") },
14874 { STRING_COMMA_LEN ("false_os") },
14875 { STRING_COMMA_LEN ("neq_os") },
14876 { STRING_COMMA_LEN ("ge_oq") },
14877 { STRING_COMMA_LEN ("gt_oq") },
14878 { STRING_COMMA_LEN ("true_us") },
14882 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14884 unsigned int cmp_type
;
14886 FETCH_DATA (the_info
, codep
+ 1);
14887 cmp_type
= *codep
++ & 0xff;
14888 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
14891 char *p
= mnemonicendp
- 2;
14895 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
14896 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
14900 /* We have a reserved extension byte. Output it directly. */
14901 scratchbuf
[0] = '$';
14902 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
14903 oappend (scratchbuf
+ intel_syntax
);
14904 scratchbuf
[0] = '\0';
14908 static const struct op pclmul_op
[] =
14910 { STRING_COMMA_LEN ("lql") },
14911 { STRING_COMMA_LEN ("hql") },
14912 { STRING_COMMA_LEN ("lqh") },
14913 { STRING_COMMA_LEN ("hqh") }
14917 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
14918 int sizeflag ATTRIBUTE_UNUSED
)
14920 unsigned int pclmul_type
;
14922 FETCH_DATA (the_info
, codep
+ 1);
14923 pclmul_type
= *codep
++ & 0xff;
14924 switch (pclmul_type
)
14935 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
14938 char *p
= mnemonicendp
- 3;
14943 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
14944 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
14948 /* We have a reserved extension byte. Output it directly. */
14949 scratchbuf
[0] = '$';
14950 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
14951 oappend (scratchbuf
+ intel_syntax
);
14952 scratchbuf
[0] = '\0';
14957 MOVBE_Fixup (int bytemode
, int sizeflag
)
14959 /* Add proper suffix to "movbe". */
14960 char *p
= mnemonicendp
;
14969 if (sizeflag
& SUFFIX_ALWAYS
)
14975 if (sizeflag
& DFLAG
)
14979 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14984 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14991 OP_M (bytemode
, sizeflag
);
14995 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
14998 const char **names
;
15000 /* Skip mod/rm byte. */
15014 oappend (names
[reg
]);
15018 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15020 const char **names
;
15027 oappend (names
[vex
.register_specifier
]);