opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 #define XX { NULL, 0 }
 225 #define Bad_Opcode NULL, { { NULL, 0 } }
 226
 227 #define Eb { OP_E, b_mode }
 228 #define Ebnd { OP_E, bnd_mode }
 229 #define EbS { OP_E, b_swap_mode }
 230 #define Ev { OP_E, v_mode }
 231 #define Ev_bnd { OP_E, v_bnd_mode }
 232 #define EvS { OP_E, v_swap_mode }
 233 #define Ed { OP_E, d_mode }
 234 #define Edq { OP_E, dq_mode }
 235 #define Edqw { OP_E, dqw_mode }
 236 #define EdqwS { OP_E, dqw_swap_mode }
 237 #define Edqb { OP_E, dqb_mode }
 238 #define Edb { OP_E, db_mode }
 239 #define Edw { OP_E, dw_mode }
 240 #define Edqd { OP_E, dqd_mode }
 241 #define Eq { OP_E, q_mode }
 242 #define indirEv { OP_indirE, stack_v_mode }
 243 #define indirEp { OP_indirE, f_mode }
 244 #define stackEv { OP_E, stack_v_mode }
 245 #define Em { OP_E, m_mode }
 246 #define Ew { OP_E, w_mode }
 247 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 248 #define Ma { OP_M, a_mode }
 249 #define Mb { OP_M, b_mode }
 250 #define Md { OP_M, d_mode }
 251 #define Mo { OP_M, o_mode }
 252 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 253 #define Mq { OP_M, q_mode }
 254 #define Mx { OP_M, x_mode }
 255 #define Mxmm { OP_M, xmm_mode }
 256 #define Gb { OP_G, b_mode }
 257 #define Gbnd { OP_G, bnd_mode }
 258 #define Gv { OP_G, v_mode }
 259 #define Gd { OP_G, d_mode }
 260 #define Gdq { OP_G, dq_mode }
 261 #define Gm { OP_G, m_mode }
 262 #define Gw { OP_G, w_mode }
 263 #define Rd { OP_R, d_mode }
 264 #define Rdq { OP_R, dq_mode }
 265 #define Rm { OP_R, m_mode }
 266 #define Ib { OP_I, b_mode }
 267 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 269 #define Iv { OP_I, v_mode }
 270 #define sIv { OP_sI, v_mode }
 271 #define Iq { OP_I, q_mode }
 272 #define Iv64 { OP_I64, v_mode }
 273 #define Iw { OP_I, w_mode }
 274 #define I1 { OP_I, const_1_mode }
 275 #define Jb { OP_J, b_mode }
 276 #define Jv { OP_J, v_mode }
 277 #define Cm { OP_C, m_mode }
 278 #define Dm { OP_D, m_mode }
 279 #define Td { OP_T, d_mode }
 280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 281
 282 #define RMeAX { OP_REG, eAX_reg }
 283 #define RMeBX { OP_REG, eBX_reg }
 284 #define RMeCX { OP_REG, eCX_reg }
 285 #define RMeDX { OP_REG, eDX_reg }
 286 #define RMeSP { OP_REG, eSP_reg }
 287 #define RMeBP { OP_REG, eBP_reg }
 288 #define RMeSI { OP_REG, eSI_reg }
 289 #define RMeDI { OP_REG, eDI_reg }
 290 #define RMrAX { OP_REG, rAX_reg }
 291 #define RMrBX { OP_REG, rBX_reg }
 292 #define RMrCX { OP_REG, rCX_reg }
 293 #define RMrDX { OP_REG, rDX_reg }
 294 #define RMrSP { OP_REG, rSP_reg }
 295 #define RMrBP { OP_REG, rBP_reg }
 296 #define RMrSI { OP_REG, rSI_reg }
 297 #define RMrDI { OP_REG, rDI_reg }
 298 #define RMAL { OP_REG, al_reg }
 299 #define RMCL { OP_REG, cl_reg }
 300 #define RMDL { OP_REG, dl_reg }
 301 #define RMBL { OP_REG, bl_reg }
 302 #define RMAH { OP_REG, ah_reg }
 303 #define RMCH { OP_REG, ch_reg }
 304 #define RMDH { OP_REG, dh_reg }
 305 #define RMBH { OP_REG, bh_reg }
 306 #define RMAX { OP_REG, ax_reg }
 307 #define RMDX { OP_REG, dx_reg }
 308
 309 #define eAX { OP_IMREG, eAX_reg }
 310 #define eBX { OP_IMREG, eBX_reg }
 311 #define eCX { OP_IMREG, eCX_reg }
 312 #define eDX { OP_IMREG, eDX_reg }
 313 #define eSP { OP_IMREG, eSP_reg }
 314 #define eBP { OP_IMREG, eBP_reg }
 315 #define eSI { OP_IMREG, eSI_reg }
 316 #define eDI { OP_IMREG, eDI_reg }
 317 #define AL { OP_IMREG, al_reg }
 318 #define CL { OP_IMREG, cl_reg }
 319 #define DL { OP_IMREG, dl_reg }
 320 #define BL { OP_IMREG, bl_reg }
 321 #define AH { OP_IMREG, ah_reg }
 322 #define CH { OP_IMREG, ch_reg }
 323 #define DH { OP_IMREG, dh_reg }
 324 #define BH { OP_IMREG, bh_reg }
 325 #define AX { OP_IMREG, ax_reg }
 326 #define DX { OP_IMREG, dx_reg }
 327 #define zAX { OP_IMREG, z_mode_ax_reg }
 328 #define indirDX { OP_IMREG, indir_dx_reg }
 329
 330 #define Sw { OP_SEG, w_mode }
 331 #define Sv { OP_SEG, v_mode }
 332 #define Ap { OP_DIR, 0 }
 333 #define Ob { OP_OFF64, b_mode }
 334 #define Ov { OP_OFF64, v_mode }
 335 #define Xb { OP_DSreg, eSI_reg }
 336 #define Xv { OP_DSreg, eSI_reg }
 337 #define Xz { OP_DSreg, eSI_reg }
 338 #define Yb { OP_ESreg, eDI_reg }
 339 #define Yv { OP_ESreg, eDI_reg }
 340 #define DSBX { OP_DSreg, eBX_reg }
 341
 342 #define es { OP_REG, es_reg }
 343 #define ss { OP_REG, ss_reg }
 344 #define cs { OP_REG, cs_reg }
 345 #define ds { OP_REG, ds_reg }
 346 #define fs { OP_REG, fs_reg }
 347 #define gs { OP_REG, gs_reg }
 348
 349 #define MX { OP_MMX, 0 }
 350 #define XM { OP_XMM, 0 }
 351 #define XMScalar { OP_XMM, scalar_mode }
 352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 353 #define XMM { OP_XMM, xmm_mode }
 354 #define XMxmmq { OP_XMM, xmmq_mode }
 355 #define EM { OP_EM, v_mode }
 356 #define EMS { OP_EM, v_swap_mode }
 357 #define EMd { OP_EM, d_mode }
 358 #define EMx { OP_EM, x_mode }
 359 #define EXw { OP_EX, w_mode }
 360 #define EXd { OP_EX, d_mode }
 361 #define EXdScalar { OP_EX, d_scalar_mode }
 362 #define EXdS { OP_EX, d_swap_mode }
 363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 364 #define EXq { OP_EX, q_mode }
 365 #define EXqScalar { OP_EX, q_scalar_mode }
 366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 367 #define EXqS { OP_EX, q_swap_mode }
 368 #define EXx { OP_EX, x_mode }
 369 #define EXxS { OP_EX, x_swap_mode }
 370 #define EXxmm { OP_EX, xmm_mode }
 371 #define EXymm { OP_EX, ymm_mode }
 372 #define EXxmmq { OP_EX, xmmq_mode }
 373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 376 #define EXxmm_md { OP_EX, xmm_md_mode }
 377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 379 #define EXxmmdw { OP_EX, xmmdw_mode }
 380 #define EXxmmqd { OP_EX, xmmqd_mode }
 381 #define EXymmq { OP_EX, ymmq_mode }
 382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 386 #define MS { OP_MS, v_mode }
 387 #define XS { OP_XS, v_mode }
 388 #define EMCq { OP_EMC, q_mode }
 389 #define MXC { OP_MXC, 0 }
 390 #define OPSUF { OP_3DNowSuffix, 0 }
 391 #define CMP { CMP_Fixup, 0 }
 392 #define XMM0 { XMM_Fixup, 0 }
 393 #define FXSAVE { FXSAVE_Fixup, 0 }
 394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexScalar { OP_VEX, vex_scalar_mode }
 399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 400 #define Vex128 { OP_VEX, vex128_mode }
 401 #define Vex256 { OP_VEX, vex256_mode }
 402 #define VexGdq { OP_VEX, dq_mode }
 403 #define VexI4 { VEXI4_Fixup, 0}
 404 #define EXdVex { OP_EX_Vex, d_mode }
 405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 407 #define EXqVex { OP_EX_Vex, q_mode }
 408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 410 #define EXVexW { OP_EX_VexW, x_mode }
 411 #define EXdVexW { OP_EX_VexW, d_mode }
 412 #define EXqVexW { OP_EX_VexW, q_mode }
 413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 414 #define XMVex { OP_XMM_Vex, 0 }
 415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 416 #define XMVexW { OP_XMM_VexW, 0 }
 417 #define XMVexI4 { OP_REG_VexI4, x_mode }
 418 #define PCLMUL { PCLMUL_Fixup, 0 }
 419 #define VZERO { VZERO_Fixup, 0 }
 420 #define VCMP { VCMP_Fixup, 0 }
 421 #define VPCMP { VPCMP_Fixup, 0 }
 422
 423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 425
 426 #define XMask { OP_Mask, mask_mode }
 427 #define MaskG { OP_G, mask_mode }
 428 #define MaskE { OP_E, mask_mode }
 429 #define MaskBDE { OP_E, mask_bd_mode }
 430 #define MaskR { OP_R, mask_mode }
 431 #define MaskVex { OP_VEX, mask_mode }
 432
 433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 437
 438 /* Used handle "rep" prefix for string instructions.  */
 439 #define Xbr { REP_Fixup, eSI_reg }
 440 #define Xvr { REP_Fixup, eSI_reg }
 441 #define Ybr { REP_Fixup, eDI_reg }
 442 #define Yvr { REP_Fixup, eDI_reg }
 443 #define Yzr { REP_Fixup, eDI_reg }
 444 #define indirDXr { REP_Fixup, indir_dx_reg }
 445 #define ALr { REP_Fixup, al_reg }
 446 #define eAXr { REP_Fixup, eAX_reg }
 447
 448 /* Used handle HLE prefix for lockable instructions.  */
 449 #define Ebh1 { HLE_Fixup1, b_mode }
 450 #define Evh1 { HLE_Fixup1, v_mode }
 451 #define Ebh2 { HLE_Fixup2, b_mode }
 452 #define Evh2 { HLE_Fixup2, v_mode }
 453 #define Ebh3 { HLE_Fixup3, b_mode }
 454 #define Evh3 { HLE_Fixup3, v_mode }
 455
 456 #define BND { BND_Fixup, 0 }
 457
 458 #define cond_jump_flag { NULL, cond_jump_mode }
 459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 460
 461 /* bits in sizeflag */
 462 #define SUFFIX_ALWAYS 4
 463 #define AFLAG 2
 464 #define DFLAG 1
 465
 466 enum
 467 {
 468   /* byte operand */
 469   b_mode = 1,
 470   /* byte operand with operand swapped */
 471   b_swap_mode,
 472   /* byte operand, sign extend like 'T' suffix */
 473   b_T_mode,
 474   /* operand size depends on prefixes */
 475   v_mode,
 476   /* operand size depends on prefixes with operand swapped */
 477   v_swap_mode,
 478   /* word operand */
 479   w_mode,
 480   /* double word operand  */
 481   d_mode,
 482   /* double word operand with operand swapped */
 483   d_swap_mode,
 484   /* quad word operand */
 485   q_mode,
 486   /* quad word operand with operand swapped */
 487   q_swap_mode,
 488   /* ten-byte operand */
 489   t_mode,
 490   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 491      broadcast enabled.  */
 492   x_mode,
 493   /* Similar to x_mode, but with different EVEX mem shifts.  */
 494   evex_x_gscat_mode,
 495   /* Similar to x_mode, but with disabled broadcast.  */
 496   evex_x_nobcst_mode,
 497   /* Similar to x_mode, but with operands swapped and disabled broadcast
 498      in EVEX.  */
 499   x_swap_mode,
 500   /* 16-byte XMM operand */
 501   xmm_mode,
 502   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 503      memory operand (depending on vector length).  Broadcast isn't
 504      allowed.  */
 505   xmmq_mode,
 506   /* Same as xmmq_mode, but broadcast is allowed.  */
 507   evex_half_bcst_xmmq_mode,
 508   /* XMM register or byte memory operand */
 509   xmm_mb_mode,
 510   /* XMM register or word memory operand */
 511   xmm_mw_mode,
 512   /* XMM register or double word memory operand */
 513   xmm_md_mode,
 514   /* XMM register or quad word memory operand */
 515   xmm_mq_mode,
 516   /* XMM register or double/quad word memory operand, depending on
 517      VEX.W.  */
 518   xmm_mdq_mode,
 519   /* 16-byte XMM, word, double word or quad word operand.  */
 520   xmmdw_mode,
 521   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 522   xmmqd_mode,
 523   /* 32-byte YMM operand */
 524   ymm_mode,
 525   /* quad word, ymmword or zmmword memory operand.  */
 526   ymmq_mode,
 527   /* 32-byte YMM or 16-byte word operand */
 528   ymmxmm_mode,
 529   /* d_mode in 32bit, q_mode in 64bit mode.  */
 530   m_mode,
 531   /* pair of v_mode operands */
 532   a_mode,
 533   cond_jump_mode,
 534   loop_jcxz_mode,
 535   v_bnd_mode,
 536   /* operand size depends on REX prefixes.  */
 537   dq_mode,
 538   /* registers like dq_mode, memory like w_mode.  */
 539   dqw_mode,
 540   dqw_swap_mode,
 541   bnd_mode,
 542   /* 4- or 6-byte pointer operand */
 543   f_mode,
 544   const_1_mode,
 545   /* v_mode for stack-related opcodes.  */
 546   stack_v_mode,
 547   /* non-quad operand size depends on prefixes */
 548   z_mode,
 549   /* 16-byte operand */
 550   o_mode,
 551   /* registers like dq_mode, memory like b_mode.  */
 552   dqb_mode,
 553   /* registers like d_mode, memory like b_mode.  */
 554   db_mode,
 555   /* registers like d_mode, memory like w_mode.  */
 556   dw_mode,
 557   /* registers like dq_mode, memory like d_mode.  */
 558   dqd_mode,
 559   /* normal vex mode */
 560   vex_mode,
 561   /* 128bit vex mode */
 562   vex128_mode,
 563   /* 256bit vex mode */
 564   vex256_mode,
 565   /* operand size depends on the VEX.W bit.  */
 566   vex_w_dq_mode,
 567
 568   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 569   vex_vsib_d_w_dq_mode,
 570   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 571   vex_vsib_d_w_d_mode,
 572   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 573   vex_vsib_q_w_dq_mode,
 574   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 575   vex_vsib_q_w_d_mode,
 576
 577   /* scalar, ignore vector length.  */
 578   scalar_mode,
 579   /* like d_mode, ignore vector length.  */
 580   d_scalar_mode,
 581   /* like d_swap_mode, ignore vector length.  */
 582   d_scalar_swap_mode,
 583   /* like q_mode, ignore vector length.  */
 584   q_scalar_mode,
 585   /* like q_swap_mode, ignore vector length.  */
 586   q_scalar_swap_mode,
 587   /* like vex_mode, ignore vector length.  */
 588   vex_scalar_mode,
 589   /* like vex_w_dq_mode, ignore vector length.  */
 590   vex_scalar_w_dq_mode,
 591
 592   /* Static rounding.  */
 593   evex_rounding_mode,
 594   /* Supress all exceptions.  */
 595   evex_sae_mode,
 596
 597   /* Mask register operand.  */
 598   mask_mode,
 599   /* Mask register operand.  */
 600   mask_bd_mode,
 601
 602   es_reg,
 603   cs_reg,
 604   ss_reg,
 605   ds_reg,
 606   fs_reg,
 607   gs_reg,
 608
 609   eAX_reg,
 610   eCX_reg,
 611   eDX_reg,
 612   eBX_reg,
 613   eSP_reg,
 614   eBP_reg,
 615   eSI_reg,
 616   eDI_reg,
 617
 618   al_reg,
 619   cl_reg,
 620   dl_reg,
 621   bl_reg,
 622   ah_reg,
 623   ch_reg,
 624   dh_reg,
 625   bh_reg,
 626
 627   ax_reg,
 628   cx_reg,
 629   dx_reg,
 630   bx_reg,
 631   sp_reg,
 632   bp_reg,
 633   si_reg,
 634   di_reg,
 635
 636   rAX_reg,
 637   rCX_reg,
 638   rDX_reg,
 639   rBX_reg,
 640   rSP_reg,
 641   rBP_reg,
 642   rSI_reg,
 643   rDI_reg,
 644
 645   z_mode_ax_reg,
 646   indir_dx_reg
 647 };
 648
 649 enum
 650 {
 651   FLOATCODE = 1,
 652   USE_REG_TABLE,
 653   USE_MOD_TABLE,
 654   USE_RM_TABLE,
 655   USE_PREFIX_TABLE,
 656   USE_X86_64_TABLE,
 657   USE_3BYTE_TABLE,
 658   USE_XOP_8F_TABLE,
 659   USE_VEX_C4_TABLE,
 660   USE_VEX_C5_TABLE,
 661   USE_VEX_LEN_TABLE,
 662   USE_VEX_W_TABLE,
 663   USE_EVEX_TABLE
 664 };
 665
 666 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 667
 668 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 669 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 670 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 671 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 672 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 673 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 674 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 675 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 676 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 677 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 678 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 679 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 680 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 681
 682 enum
 683 {
 684   REG_80 = 0,
 685   REG_81,
 686   REG_82,
 687   REG_8F,
 688   REG_C0,
 689   REG_C1,
 690   REG_C6,
 691   REG_C7,
 692   REG_D0,
 693   REG_D1,
 694   REG_D2,
 695   REG_D3,
 696   REG_F6,
 697   REG_F7,
 698   REG_FE,
 699   REG_FF,
 700   REG_0F00,
 701   REG_0F01,
 702   REG_0F0D,
 703   REG_0F18,
 704   REG_0F71,
 705   REG_0F72,
 706   REG_0F73,
 707   REG_0FA6,
 708   REG_0FA7,
 709   REG_0FAE,
 710   REG_0FBA,
 711   REG_0FC7,
 712   REG_VEX_0F71,
 713   REG_VEX_0F72,
 714   REG_VEX_0F73,
 715   REG_VEX_0FAE,
 716   REG_VEX_0F38F3,
 717   REG_XOP_LWPCB,
 718   REG_XOP_LWP,
 719   REG_XOP_TBM_01,
 720   REG_XOP_TBM_02,
 721
 722   REG_EVEX_0F71,
 723   REG_EVEX_0F72,
 724   REG_EVEX_0F73,
 725   REG_EVEX_0F38C6,
 726   REG_EVEX_0F38C7
 727 };
 728
 729 enum
 730 {
 731   MOD_8D = 0,
 732   MOD_C6_REG_7,
 733   MOD_C7_REG_7,
 734   MOD_FF_REG_3,
 735   MOD_FF_REG_5,
 736   MOD_0F01_REG_0,
 737   MOD_0F01_REG_1,
 738   MOD_0F01_REG_2,
 739   MOD_0F01_REG_3,
 740   MOD_0F01_REG_7,
 741   MOD_0F12_PREFIX_0,
 742   MOD_0F13,
 743   MOD_0F16_PREFIX_0,
 744   MOD_0F17,
 745   MOD_0F18_REG_0,
 746   MOD_0F18_REG_1,
 747   MOD_0F18_REG_2,
 748   MOD_0F18_REG_3,
 749   MOD_0F18_REG_4,
 750   MOD_0F18_REG_5,
 751   MOD_0F18_REG_6,
 752   MOD_0F18_REG_7,
 753   MOD_0F1A_PREFIX_0,
 754   MOD_0F1B_PREFIX_0,
 755   MOD_0F1B_PREFIX_1,
 756   MOD_0F24,
 757   MOD_0F26,
 758   MOD_0F2B_PREFIX_0,
 759   MOD_0F2B_PREFIX_1,
 760   MOD_0F2B_PREFIX_2,
 761   MOD_0F2B_PREFIX_3,
 762   MOD_0F51,
 763   MOD_0F71_REG_2,
 764   MOD_0F71_REG_4,
 765   MOD_0F71_REG_6,
 766   MOD_0F72_REG_2,
 767   MOD_0F72_REG_4,
 768   MOD_0F72_REG_6,
 769   MOD_0F73_REG_2,
 770   MOD_0F73_REG_3,
 771   MOD_0F73_REG_6,
 772   MOD_0F73_REG_7,
 773   MOD_0FAE_REG_0,
 774   MOD_0FAE_REG_1,
 775   MOD_0FAE_REG_2,
 776   MOD_0FAE_REG_3,
 777   MOD_0FAE_REG_4,
 778   MOD_0FAE_REG_5,
 779   MOD_0FAE_REG_6,
 780   MOD_0FAE_REG_7,
 781   MOD_0FB2,
 782   MOD_0FB4,
 783   MOD_0FB5,
 784   MOD_0FC7_REG_3,
 785   MOD_0FC7_REG_4,
 786   MOD_0FC7_REG_5,
 787   MOD_0FC7_REG_6,
 788   MOD_0FC7_REG_7,
 789   MOD_0FD7,
 790   MOD_0FE7_PREFIX_2,
 791   MOD_0FF0_PREFIX_3,
 792   MOD_0F382A_PREFIX_2,
 793   MOD_62_32BIT,
 794   MOD_C4_32BIT,
 795   MOD_C5_32BIT,
 796   MOD_VEX_0F12_PREFIX_0,
 797   MOD_VEX_0F13,
 798   MOD_VEX_0F16_PREFIX_0,
 799   MOD_VEX_0F17,
 800   MOD_VEX_0F2B,
 801   MOD_VEX_0F50,
 802   MOD_VEX_0F71_REG_2,
 803   MOD_VEX_0F71_REG_4,
 804   MOD_VEX_0F71_REG_6,
 805   MOD_VEX_0F72_REG_2,
 806   MOD_VEX_0F72_REG_4,
 807   MOD_VEX_0F72_REG_6,
 808   MOD_VEX_0F73_REG_2,
 809   MOD_VEX_0F73_REG_3,
 810   MOD_VEX_0F73_REG_6,
 811   MOD_VEX_0F73_REG_7,
 812   MOD_VEX_0FAE_REG_2,
 813   MOD_VEX_0FAE_REG_3,
 814   MOD_VEX_0FD7_PREFIX_2,
 815   MOD_VEX_0FE7_PREFIX_2,
 816   MOD_VEX_0FF0_PREFIX_3,
 817   MOD_VEX_0F381A_PREFIX_2,
 818   MOD_VEX_0F382A_PREFIX_2,
 819   MOD_VEX_0F382C_PREFIX_2,
 820   MOD_VEX_0F382D_PREFIX_2,
 821   MOD_VEX_0F382E_PREFIX_2,
 822   MOD_VEX_0F382F_PREFIX_2,
 823   MOD_VEX_0F385A_PREFIX_2,
 824   MOD_VEX_0F388C_PREFIX_2,
 825   MOD_VEX_0F388E_PREFIX_2,
 826
 827   MOD_EVEX_0F10_PREFIX_1,
 828   MOD_EVEX_0F10_PREFIX_3,
 829   MOD_EVEX_0F11_PREFIX_1,
 830   MOD_EVEX_0F11_PREFIX_3,
 831   MOD_EVEX_0F12_PREFIX_0,
 832   MOD_EVEX_0F16_PREFIX_0,
 833   MOD_EVEX_0F38C6_REG_1,
 834   MOD_EVEX_0F38C6_REG_2,
 835   MOD_EVEX_0F38C6_REG_5,
 836   MOD_EVEX_0F38C6_REG_6,
 837   MOD_EVEX_0F38C7_REG_1,
 838   MOD_EVEX_0F38C7_REG_2,
 839   MOD_EVEX_0F38C7_REG_5,
 840   MOD_EVEX_0F38C7_REG_6
 841 };
 842
 843 enum
 844 {
 845   RM_C6_REG_7 = 0,
 846   RM_C7_REG_7,
 847   RM_0F01_REG_0,
 848   RM_0F01_REG_1,
 849   RM_0F01_REG_2,
 850   RM_0F01_REG_3,
 851   RM_0F01_REG_7,
 852   RM_0FAE_REG_5,
 853   RM_0FAE_REG_6,
 854   RM_0FAE_REG_7
 855 };
 856
 857 enum
 858 {
 859   PREFIX_90 = 0,
 860   PREFIX_0F10,
 861   PREFIX_0F11,
 862   PREFIX_0F12,
 863   PREFIX_0F16,
 864   PREFIX_0F1A,
 865   PREFIX_0F1B,
 866   PREFIX_0F2A,
 867   PREFIX_0F2B,
 868   PREFIX_0F2C,
 869   PREFIX_0F2D,
 870   PREFIX_0F2E,
 871   PREFIX_0F2F,
 872   PREFIX_0F51,
 873   PREFIX_0F52,
 874   PREFIX_0F53,
 875   PREFIX_0F58,
 876   PREFIX_0F59,
 877   PREFIX_0F5A,
 878   PREFIX_0F5B,
 879   PREFIX_0F5C,
 880   PREFIX_0F5D,
 881   PREFIX_0F5E,
 882   PREFIX_0F5F,
 883   PREFIX_0F60,
 884   PREFIX_0F61,
 885   PREFIX_0F62,
 886   PREFIX_0F6C,
 887   PREFIX_0F6D,
 888   PREFIX_0F6F,
 889   PREFIX_0F70,
 890   PREFIX_0F73_REG_3,
 891   PREFIX_0F73_REG_7,
 892   PREFIX_0F78,
 893   PREFIX_0F79,
 894   PREFIX_0F7C,
 895   PREFIX_0F7D,
 896   PREFIX_0F7E,
 897   PREFIX_0F7F,
 898   PREFIX_0FAE_REG_0,
 899   PREFIX_0FAE_REG_1,
 900   PREFIX_0FAE_REG_2,
 901   PREFIX_0FAE_REG_3,
 902   PREFIX_0FAE_REG_6,
 903   PREFIX_0FAE_REG_7,
 904   PREFIX_0FB8,
 905   PREFIX_0FBC,
 906   PREFIX_0FBD,
 907   PREFIX_0FC2,
 908   PREFIX_0FC3,
 909   PREFIX_0FC7_REG_6,
 910   PREFIX_0FD0,
 911   PREFIX_0FD6,
 912   PREFIX_0FE6,
 913   PREFIX_0FE7,
 914   PREFIX_0FF0,
 915   PREFIX_0FF7,
 916   PREFIX_0F3810,
 917   PREFIX_0F3814,
 918   PREFIX_0F3815,
 919   PREFIX_0F3817,
 920   PREFIX_0F3820,
 921   PREFIX_0F3821,
 922   PREFIX_0F3822,
 923   PREFIX_0F3823,
 924   PREFIX_0F3824,
 925   PREFIX_0F3825,
 926   PREFIX_0F3828,
 927   PREFIX_0F3829,
 928   PREFIX_0F382A,
 929   PREFIX_0F382B,
 930   PREFIX_0F3830,
 931   PREFIX_0F3831,
 932   PREFIX_0F3832,
 933   PREFIX_0F3833,
 934   PREFIX_0F3834,
 935   PREFIX_0F3835,
 936   PREFIX_0F3837,
 937   PREFIX_0F3838,
 938   PREFIX_0F3839,
 939   PREFIX_0F383A,
 940   PREFIX_0F383B,
 941   PREFIX_0F383C,
 942   PREFIX_0F383D,
 943   PREFIX_0F383E,
 944   PREFIX_0F383F,
 945   PREFIX_0F3840,
 946   PREFIX_0F3841,
 947   PREFIX_0F3880,
 948   PREFIX_0F3881,
 949   PREFIX_0F3882,
 950   PREFIX_0F38C8,
 951   PREFIX_0F38C9,
 952   PREFIX_0F38CA,
 953   PREFIX_0F38CB,
 954   PREFIX_0F38CC,
 955   PREFIX_0F38CD,
 956   PREFIX_0F38DB,
 957   PREFIX_0F38DC,
 958   PREFIX_0F38DD,
 959   PREFIX_0F38DE,
 960   PREFIX_0F38DF,
 961   PREFIX_0F38F0,
 962   PREFIX_0F38F1,
 963   PREFIX_0F38F6,
 964   PREFIX_0F3A08,
 965   PREFIX_0F3A09,
 966   PREFIX_0F3A0A,
 967   PREFIX_0F3A0B,
 968   PREFIX_0F3A0C,
 969   PREFIX_0F3A0D,
 970   PREFIX_0F3A0E,
 971   PREFIX_0F3A14,
 972   PREFIX_0F3A15,
 973   PREFIX_0F3A16,
 974   PREFIX_0F3A17,
 975   PREFIX_0F3A20,
 976   PREFIX_0F3A21,
 977   PREFIX_0F3A22,
 978   PREFIX_0F3A40,
 979   PREFIX_0F3A41,
 980   PREFIX_0F3A42,
 981   PREFIX_0F3A44,
 982   PREFIX_0F3A60,
 983   PREFIX_0F3A61,
 984   PREFIX_0F3A62,
 985   PREFIX_0F3A63,
 986   PREFIX_0F3ACC,
 987   PREFIX_0F3ADF,
 988   PREFIX_VEX_0F10,
 989   PREFIX_VEX_0F11,
 990   PREFIX_VEX_0F12,
 991   PREFIX_VEX_0F16,
 992   PREFIX_VEX_0F2A,
 993   PREFIX_VEX_0F2C,
 994   PREFIX_VEX_0F2D,
 995   PREFIX_VEX_0F2E,
 996   PREFIX_VEX_0F2F,
 997   PREFIX_VEX_0F41,
 998   PREFIX_VEX_0F42,
 999   PREFIX_VEX_0F44,
1000   PREFIX_VEX_0F45,
1001   PREFIX_VEX_0F46,
1002   PREFIX_VEX_0F47,
1003   PREFIX_VEX_0F4A,
1004   PREFIX_VEX_0F4B,
1005   PREFIX_VEX_0F51,
1006   PREFIX_VEX_0F52,
1007   PREFIX_VEX_0F53,
1008   PREFIX_VEX_0F58,
1009   PREFIX_VEX_0F59,
1010   PREFIX_VEX_0F5A,
1011   PREFIX_VEX_0F5B,
1012   PREFIX_VEX_0F5C,
1013   PREFIX_VEX_0F5D,
1014   PREFIX_VEX_0F5E,
1015   PREFIX_VEX_0F5F,
1016   PREFIX_VEX_0F60,
1017   PREFIX_VEX_0F61,
1018   PREFIX_VEX_0F62,
1019   PREFIX_VEX_0F63,
1020   PREFIX_VEX_0F64,
1021   PREFIX_VEX_0F65,
1022   PREFIX_VEX_0F66,
1023   PREFIX_VEX_0F67,
1024   PREFIX_VEX_0F68,
1025   PREFIX_VEX_0F69,
1026   PREFIX_VEX_0F6A,
1027   PREFIX_VEX_0F6B,
1028   PREFIX_VEX_0F6C,
1029   PREFIX_VEX_0F6D,
1030   PREFIX_VEX_0F6E,
1031   PREFIX_VEX_0F6F,
1032   PREFIX_VEX_0F70,
1033   PREFIX_VEX_0F71_REG_2,
1034   PREFIX_VEX_0F71_REG_4,
1035   PREFIX_VEX_0F71_REG_6,
1036   PREFIX_VEX_0F72_REG_2,
1037   PREFIX_VEX_0F72_REG_4,
1038   PREFIX_VEX_0F72_REG_6,
1039   PREFIX_VEX_0F73_REG_2,
1040   PREFIX_VEX_0F73_REG_3,
1041   PREFIX_VEX_0F73_REG_6,
1042   PREFIX_VEX_0F73_REG_7,
1043   PREFIX_VEX_0F74,
1044   PREFIX_VEX_0F75,
1045   PREFIX_VEX_0F76,
1046   PREFIX_VEX_0F77,
1047   PREFIX_VEX_0F7C,
1048   PREFIX_VEX_0F7D,
1049   PREFIX_VEX_0F7E,
1050   PREFIX_VEX_0F7F,
1051   PREFIX_VEX_0F90,
1052   PREFIX_VEX_0F91,
1053   PREFIX_VEX_0F92,
1054   PREFIX_VEX_0F93,
1055   PREFIX_VEX_0F98,
1056   PREFIX_VEX_0F99,
1057   PREFIX_VEX_0FC2,
1058   PREFIX_VEX_0FC4,
1059   PREFIX_VEX_0FC5,
1060   PREFIX_VEX_0FD0,
1061   PREFIX_VEX_0FD1,
1062   PREFIX_VEX_0FD2,
1063   PREFIX_VEX_0FD3,
1064   PREFIX_VEX_0FD4,
1065   PREFIX_VEX_0FD5,
1066   PREFIX_VEX_0FD6,
1067   PREFIX_VEX_0FD7,
1068   PREFIX_VEX_0FD8,
1069   PREFIX_VEX_0FD9,
1070   PREFIX_VEX_0FDA,
1071   PREFIX_VEX_0FDB,
1072   PREFIX_VEX_0FDC,
1073   PREFIX_VEX_0FDD,
1074   PREFIX_VEX_0FDE,
1075   PREFIX_VEX_0FDF,
1076   PREFIX_VEX_0FE0,
1077   PREFIX_VEX_0FE1,
1078   PREFIX_VEX_0FE2,
1079   PREFIX_VEX_0FE3,
1080   PREFIX_VEX_0FE4,
1081   PREFIX_VEX_0FE5,
1082   PREFIX_VEX_0FE6,
1083   PREFIX_VEX_0FE7,
1084   PREFIX_VEX_0FE8,
1085   PREFIX_VEX_0FE9,
1086   PREFIX_VEX_0FEA,
1087   PREFIX_VEX_0FEB,
1088   PREFIX_VEX_0FEC,
1089   PREFIX_VEX_0FED,
1090   PREFIX_VEX_0FEE,
1091   PREFIX_VEX_0FEF,
1092   PREFIX_VEX_0FF0,
1093   PREFIX_VEX_0FF1,
1094   PREFIX_VEX_0FF2,
1095   PREFIX_VEX_0FF3,
1096   PREFIX_VEX_0FF4,
1097   PREFIX_VEX_0FF5,
1098   PREFIX_VEX_0FF6,
1099   PREFIX_VEX_0FF7,
1100   PREFIX_VEX_0FF8,
1101   PREFIX_VEX_0FF9,
1102   PREFIX_VEX_0FFA,
1103   PREFIX_VEX_0FFB,
1104   PREFIX_VEX_0FFC,
1105   PREFIX_VEX_0FFD,
1106   PREFIX_VEX_0FFE,
1107   PREFIX_VEX_0F3800,
1108   PREFIX_VEX_0F3801,
1109   PREFIX_VEX_0F3802,
1110   PREFIX_VEX_0F3803,
1111   PREFIX_VEX_0F3804,
1112   PREFIX_VEX_0F3805,
1113   PREFIX_VEX_0F3806,
1114   PREFIX_VEX_0F3807,
1115   PREFIX_VEX_0F3808,
1116   PREFIX_VEX_0F3809,
1117   PREFIX_VEX_0F380A,
1118   PREFIX_VEX_0F380B,
1119   PREFIX_VEX_0F380C,
1120   PREFIX_VEX_0F380D,
1121   PREFIX_VEX_0F380E,
1122   PREFIX_VEX_0F380F,
1123   PREFIX_VEX_0F3813,
1124   PREFIX_VEX_0F3816,
1125   PREFIX_VEX_0F3817,
1126   PREFIX_VEX_0F3818,
1127   PREFIX_VEX_0F3819,
1128   PREFIX_VEX_0F381A,
1129   PREFIX_VEX_0F381C,
1130   PREFIX_VEX_0F381D,
1131   PREFIX_VEX_0F381E,
1132   PREFIX_VEX_0F3820,
1133   PREFIX_VEX_0F3821,
1134   PREFIX_VEX_0F3822,
1135   PREFIX_VEX_0F3823,
1136   PREFIX_VEX_0F3824,
1137   PREFIX_VEX_0F3825,
1138   PREFIX_VEX_0F3828,
1139   PREFIX_VEX_0F3829,
1140   PREFIX_VEX_0F382A,
1141   PREFIX_VEX_0F382B,
1142   PREFIX_VEX_0F382C,
1143   PREFIX_VEX_0F382D,
1144   PREFIX_VEX_0F382E,
1145   PREFIX_VEX_0F382F,
1146   PREFIX_VEX_0F3830,
1147   PREFIX_VEX_0F3831,
1148   PREFIX_VEX_0F3832,
1149   PREFIX_VEX_0F3833,
1150   PREFIX_VEX_0F3834,
1151   PREFIX_VEX_0F3835,
1152   PREFIX_VEX_0F3836,
1153   PREFIX_VEX_0F3837,
1154   PREFIX_VEX_0F3838,
1155   PREFIX_VEX_0F3839,
1156   PREFIX_VEX_0F383A,
1157   PREFIX_VEX_0F383B,
1158   PREFIX_VEX_0F383C,
1159   PREFIX_VEX_0F383D,
1160   PREFIX_VEX_0F383E,
1161   PREFIX_VEX_0F383F,
1162   PREFIX_VEX_0F3840,
1163   PREFIX_VEX_0F3841,
1164   PREFIX_VEX_0F3845,
1165   PREFIX_VEX_0F3846,
1166   PREFIX_VEX_0F3847,
1167   PREFIX_VEX_0F3858,
1168   PREFIX_VEX_0F3859,
1169   PREFIX_VEX_0F385A,
1170   PREFIX_VEX_0F3878,
1171   PREFIX_VEX_0F3879,
1172   PREFIX_VEX_0F388C,
1173   PREFIX_VEX_0F388E,
1174   PREFIX_VEX_0F3890,
1175   PREFIX_VEX_0F3891,
1176   PREFIX_VEX_0F3892,
1177   PREFIX_VEX_0F3893,
1178   PREFIX_VEX_0F3896,
1179   PREFIX_VEX_0F3897,
1180   PREFIX_VEX_0F3898,
1181   PREFIX_VEX_0F3899,
1182   PREFIX_VEX_0F389A,
1183   PREFIX_VEX_0F389B,
1184   PREFIX_VEX_0F389C,
1185   PREFIX_VEX_0F389D,
1186   PREFIX_VEX_0F389E,
1187   PREFIX_VEX_0F389F,
1188   PREFIX_VEX_0F38A6,
1189   PREFIX_VEX_0F38A7,
1190   PREFIX_VEX_0F38A8,
1191   PREFIX_VEX_0F38A9,
1192   PREFIX_VEX_0F38AA,
1193   PREFIX_VEX_0F38AB,
1194   PREFIX_VEX_0F38AC,
1195   PREFIX_VEX_0F38AD,
1196   PREFIX_VEX_0F38AE,
1197   PREFIX_VEX_0F38AF,
1198   PREFIX_VEX_0F38B6,
1199   PREFIX_VEX_0F38B7,
1200   PREFIX_VEX_0F38B8,
1201   PREFIX_VEX_0F38B9,
1202   PREFIX_VEX_0F38BA,
1203   PREFIX_VEX_0F38BB,
1204   PREFIX_VEX_0F38BC,
1205   PREFIX_VEX_0F38BD,
1206   PREFIX_VEX_0F38BE,
1207   PREFIX_VEX_0F38BF,
1208   PREFIX_VEX_0F38DB,
1209   PREFIX_VEX_0F38DC,
1210   PREFIX_VEX_0F38DD,
1211   PREFIX_VEX_0F38DE,
1212   PREFIX_VEX_0F38DF,
1213   PREFIX_VEX_0F38F2,
1214   PREFIX_VEX_0F38F3_REG_1,
1215   PREFIX_VEX_0F38F3_REG_2,
1216   PREFIX_VEX_0F38F3_REG_3,
1217   PREFIX_VEX_0F38F5,
1218   PREFIX_VEX_0F38F6,
1219   PREFIX_VEX_0F38F7,
1220   PREFIX_VEX_0F3A00,
1221   PREFIX_VEX_0F3A01,
1222   PREFIX_VEX_0F3A02,
1223   PREFIX_VEX_0F3A04,
1224   PREFIX_VEX_0F3A05,
1225   PREFIX_VEX_0F3A06,
1226   PREFIX_VEX_0F3A08,
1227   PREFIX_VEX_0F3A09,
1228   PREFIX_VEX_0F3A0A,
1229   PREFIX_VEX_0F3A0B,
1230   PREFIX_VEX_0F3A0C,
1231   PREFIX_VEX_0F3A0D,
1232   PREFIX_VEX_0F3A0E,
1233   PREFIX_VEX_0F3A0F,
1234   PREFIX_VEX_0F3A14,
1235   PREFIX_VEX_0F3A15,
1236   PREFIX_VEX_0F3A16,
1237   PREFIX_VEX_0F3A17,
1238   PREFIX_VEX_0F3A18,
1239   PREFIX_VEX_0F3A19,
1240   PREFIX_VEX_0F3A1D,
1241   PREFIX_VEX_0F3A20,
1242   PREFIX_VEX_0F3A21,
1243   PREFIX_VEX_0F3A22,
1244   PREFIX_VEX_0F3A30,
1245   PREFIX_VEX_0F3A31,
1246   PREFIX_VEX_0F3A32,
1247   PREFIX_VEX_0F3A33,
1248   PREFIX_VEX_0F3A38,
1249   PREFIX_VEX_0F3A39,
1250   PREFIX_VEX_0F3A40,
1251   PREFIX_VEX_0F3A41,
1252   PREFIX_VEX_0F3A42,
1253   PREFIX_VEX_0F3A44,
1254   PREFIX_VEX_0F3A46,
1255   PREFIX_VEX_0F3A48,
1256   PREFIX_VEX_0F3A49,
1257   PREFIX_VEX_0F3A4A,
1258   PREFIX_VEX_0F3A4B,
1259   PREFIX_VEX_0F3A4C,
1260   PREFIX_VEX_0F3A5C,
1261   PREFIX_VEX_0F3A5D,
1262   PREFIX_VEX_0F3A5E,
1263   PREFIX_VEX_0F3A5F,
1264   PREFIX_VEX_0F3A60,
1265   PREFIX_VEX_0F3A61,
1266   PREFIX_VEX_0F3A62,
1267   PREFIX_VEX_0F3A63,
1268   PREFIX_VEX_0F3A68,
1269   PREFIX_VEX_0F3A69,
1270   PREFIX_VEX_0F3A6A,
1271   PREFIX_VEX_0F3A6B,
1272   PREFIX_VEX_0F3A6C,
1273   PREFIX_VEX_0F3A6D,
1274   PREFIX_VEX_0F3A6E,
1275   PREFIX_VEX_0F3A6F,
1276   PREFIX_VEX_0F3A78,
1277   PREFIX_VEX_0F3A79,
1278   PREFIX_VEX_0F3A7A,
1279   PREFIX_VEX_0F3A7B,
1280   PREFIX_VEX_0F3A7C,
1281   PREFIX_VEX_0F3A7D,
1282   PREFIX_VEX_0F3A7E,
1283   PREFIX_VEX_0F3A7F,
1284   PREFIX_VEX_0F3ADF,
1285   PREFIX_VEX_0F3AF0,
1286
1287   PREFIX_EVEX_0F10,
1288   PREFIX_EVEX_0F11,
1289   PREFIX_EVEX_0F12,
1290   PREFIX_EVEX_0F13,
1291   PREFIX_EVEX_0F14,
1292   PREFIX_EVEX_0F15,
1293   PREFIX_EVEX_0F16,
1294   PREFIX_EVEX_0F17,
1295   PREFIX_EVEX_0F28,
1296   PREFIX_EVEX_0F29,
1297   PREFIX_EVEX_0F2A,
1298   PREFIX_EVEX_0F2B,
1299   PREFIX_EVEX_0F2C,
1300   PREFIX_EVEX_0F2D,
1301   PREFIX_EVEX_0F2E,
1302   PREFIX_EVEX_0F2F,
1303   PREFIX_EVEX_0F51,
1304   PREFIX_EVEX_0F54,
1305   PREFIX_EVEX_0F55,
1306   PREFIX_EVEX_0F56,
1307   PREFIX_EVEX_0F57,
1308   PREFIX_EVEX_0F58,
1309   PREFIX_EVEX_0F59,
1310   PREFIX_EVEX_0F5A,
1311   PREFIX_EVEX_0F5B,
1312   PREFIX_EVEX_0F5C,
1313   PREFIX_EVEX_0F5D,
1314   PREFIX_EVEX_0F5E,
1315   PREFIX_EVEX_0F5F,
1316   PREFIX_EVEX_0F60,
1317   PREFIX_EVEX_0F61,
1318   PREFIX_EVEX_0F62,
1319   PREFIX_EVEX_0F63,
1320   PREFIX_EVEX_0F64,
1321   PREFIX_EVEX_0F65,
1322   PREFIX_EVEX_0F66,
1323   PREFIX_EVEX_0F67,
1324   PREFIX_EVEX_0F68,
1325   PREFIX_EVEX_0F69,
1326   PREFIX_EVEX_0F6A,
1327   PREFIX_EVEX_0F6B,
1328   PREFIX_EVEX_0F6C,
1329   PREFIX_EVEX_0F6D,
1330   PREFIX_EVEX_0F6E,
1331   PREFIX_EVEX_0F6F,
1332   PREFIX_EVEX_0F70,
1333   PREFIX_EVEX_0F71_REG_2,
1334   PREFIX_EVEX_0F71_REG_4,
1335   PREFIX_EVEX_0F71_REG_6,
1336   PREFIX_EVEX_0F72_REG_0,
1337   PREFIX_EVEX_0F72_REG_1,
1338   PREFIX_EVEX_0F72_REG_2,
1339   PREFIX_EVEX_0F72_REG_4,
1340   PREFIX_EVEX_0F72_REG_6,
1341   PREFIX_EVEX_0F73_REG_2,
1342   PREFIX_EVEX_0F73_REG_3,
1343   PREFIX_EVEX_0F73_REG_6,
1344   PREFIX_EVEX_0F73_REG_7,
1345   PREFIX_EVEX_0F74,
1346   PREFIX_EVEX_0F75,
1347   PREFIX_EVEX_0F76,
1348   PREFIX_EVEX_0F78,
1349   PREFIX_EVEX_0F79,
1350   PREFIX_EVEX_0F7A,
1351   PREFIX_EVEX_0F7B,
1352   PREFIX_EVEX_0F7E,
1353   PREFIX_EVEX_0F7F,
1354   PREFIX_EVEX_0FC2,
1355   PREFIX_EVEX_0FC4,
1356   PREFIX_EVEX_0FC5,
1357   PREFIX_EVEX_0FC6,
1358   PREFIX_EVEX_0FD1,
1359   PREFIX_EVEX_0FD2,
1360   PREFIX_EVEX_0FD3,
1361   PREFIX_EVEX_0FD4,
1362   PREFIX_EVEX_0FD5,
1363   PREFIX_EVEX_0FD6,
1364   PREFIX_EVEX_0FD8,
1365   PREFIX_EVEX_0FD9,
1366   PREFIX_EVEX_0FDA,
1367   PREFIX_EVEX_0FDB,
1368   PREFIX_EVEX_0FDC,
1369   PREFIX_EVEX_0FDD,
1370   PREFIX_EVEX_0FDE,
1371   PREFIX_EVEX_0FDF,
1372   PREFIX_EVEX_0FE0,
1373   PREFIX_EVEX_0FE1,
1374   PREFIX_EVEX_0FE2,
1375   PREFIX_EVEX_0FE3,
1376   PREFIX_EVEX_0FE4,
1377   PREFIX_EVEX_0FE5,
1378   PREFIX_EVEX_0FE6,
1379   PREFIX_EVEX_0FE7,
1380   PREFIX_EVEX_0FE8,
1381   PREFIX_EVEX_0FE9,
1382   PREFIX_EVEX_0FEA,
1383   PREFIX_EVEX_0FEB,
1384   PREFIX_EVEX_0FEC,
1385   PREFIX_EVEX_0FED,
1386   PREFIX_EVEX_0FEE,
1387   PREFIX_EVEX_0FEF,
1388   PREFIX_EVEX_0FF1,
1389   PREFIX_EVEX_0FF2,
1390   PREFIX_EVEX_0FF3,
1391   PREFIX_EVEX_0FF4,
1392   PREFIX_EVEX_0FF5,
1393   PREFIX_EVEX_0FF6,
1394   PREFIX_EVEX_0FF8,
1395   PREFIX_EVEX_0FF9,
1396   PREFIX_EVEX_0FFA,
1397   PREFIX_EVEX_0FFB,
1398   PREFIX_EVEX_0FFC,
1399   PREFIX_EVEX_0FFD,
1400   PREFIX_EVEX_0FFE,
1401   PREFIX_EVEX_0F3800,
1402   PREFIX_EVEX_0F3804,
1403   PREFIX_EVEX_0F380B,
1404   PREFIX_EVEX_0F380C,
1405   PREFIX_EVEX_0F380D,
1406   PREFIX_EVEX_0F3810,
1407   PREFIX_EVEX_0F3811,
1408   PREFIX_EVEX_0F3812,
1409   PREFIX_EVEX_0F3813,
1410   PREFIX_EVEX_0F3814,
1411   PREFIX_EVEX_0F3815,
1412   PREFIX_EVEX_0F3816,
1413   PREFIX_EVEX_0F3818,
1414   PREFIX_EVEX_0F3819,
1415   PREFIX_EVEX_0F381A,
1416   PREFIX_EVEX_0F381B,
1417   PREFIX_EVEX_0F381C,
1418   PREFIX_EVEX_0F381D,
1419   PREFIX_EVEX_0F381E,
1420   PREFIX_EVEX_0F381F,
1421   PREFIX_EVEX_0F3820,
1422   PREFIX_EVEX_0F3821,
1423   PREFIX_EVEX_0F3822,
1424   PREFIX_EVEX_0F3823,
1425   PREFIX_EVEX_0F3824,
1426   PREFIX_EVEX_0F3825,
1427   PREFIX_EVEX_0F3826,
1428   PREFIX_EVEX_0F3827,
1429   PREFIX_EVEX_0F3828,
1430   PREFIX_EVEX_0F3829,
1431   PREFIX_EVEX_0F382A,
1432   PREFIX_EVEX_0F382B,
1433   PREFIX_EVEX_0F382C,
1434   PREFIX_EVEX_0F382D,
1435   PREFIX_EVEX_0F3830,
1436   PREFIX_EVEX_0F3831,
1437   PREFIX_EVEX_0F3832,
1438   PREFIX_EVEX_0F3833,
1439   PREFIX_EVEX_0F3834,
1440   PREFIX_EVEX_0F3835,
1441   PREFIX_EVEX_0F3836,
1442   PREFIX_EVEX_0F3837,
1443   PREFIX_EVEX_0F3838,
1444   PREFIX_EVEX_0F3839,
1445   PREFIX_EVEX_0F383A,
1446   PREFIX_EVEX_0F383B,
1447   PREFIX_EVEX_0F383C,
1448   PREFIX_EVEX_0F383D,
1449   PREFIX_EVEX_0F383E,
1450   PREFIX_EVEX_0F383F,
1451   PREFIX_EVEX_0F3840,
1452   PREFIX_EVEX_0F3842,
1453   PREFIX_EVEX_0F3843,
1454   PREFIX_EVEX_0F3844,
1455   PREFIX_EVEX_0F3845,
1456   PREFIX_EVEX_0F3846,
1457   PREFIX_EVEX_0F3847,
1458   PREFIX_EVEX_0F384C,
1459   PREFIX_EVEX_0F384D,
1460   PREFIX_EVEX_0F384E,
1461   PREFIX_EVEX_0F384F,
1462   PREFIX_EVEX_0F3858,
1463   PREFIX_EVEX_0F3859,
1464   PREFIX_EVEX_0F385A,
1465   PREFIX_EVEX_0F385B,
1466   PREFIX_EVEX_0F3864,
1467   PREFIX_EVEX_0F3865,
1468   PREFIX_EVEX_0F3866,
1469   PREFIX_EVEX_0F3875,
1470   PREFIX_EVEX_0F3876,
1471   PREFIX_EVEX_0F3877,
1472   PREFIX_EVEX_0F3878,
1473   PREFIX_EVEX_0F3879,
1474   PREFIX_EVEX_0F387A,
1475   PREFIX_EVEX_0F387B,
1476   PREFIX_EVEX_0F387C,
1477   PREFIX_EVEX_0F387D,
1478   PREFIX_EVEX_0F387E,
1479   PREFIX_EVEX_0F387F,
1480   PREFIX_EVEX_0F3888,
1481   PREFIX_EVEX_0F3889,
1482   PREFIX_EVEX_0F388A,
1483   PREFIX_EVEX_0F388B,
1484   PREFIX_EVEX_0F388D,
1485   PREFIX_EVEX_0F3890,
1486   PREFIX_EVEX_0F3891,
1487   PREFIX_EVEX_0F3892,
1488   PREFIX_EVEX_0F3893,
1489   PREFIX_EVEX_0F3896,
1490   PREFIX_EVEX_0F3897,
1491   PREFIX_EVEX_0F3898,
1492   PREFIX_EVEX_0F3899,
1493   PREFIX_EVEX_0F389A,
1494   PREFIX_EVEX_0F389B,
1495   PREFIX_EVEX_0F389C,
1496   PREFIX_EVEX_0F389D,
1497   PREFIX_EVEX_0F389E,
1498   PREFIX_EVEX_0F389F,
1499   PREFIX_EVEX_0F38A0,
1500   PREFIX_EVEX_0F38A1,
1501   PREFIX_EVEX_0F38A2,
1502   PREFIX_EVEX_0F38A3,
1503   PREFIX_EVEX_0F38A6,
1504   PREFIX_EVEX_0F38A7,
1505   PREFIX_EVEX_0F38A8,
1506   PREFIX_EVEX_0F38A9,
1507   PREFIX_EVEX_0F38AA,
1508   PREFIX_EVEX_0F38AB,
1509   PREFIX_EVEX_0F38AC,
1510   PREFIX_EVEX_0F38AD,
1511   PREFIX_EVEX_0F38AE,
1512   PREFIX_EVEX_0F38AF,
1513   PREFIX_EVEX_0F38B6,
1514   PREFIX_EVEX_0F38B7,
1515   PREFIX_EVEX_0F38B8,
1516   PREFIX_EVEX_0F38B9,
1517   PREFIX_EVEX_0F38BA,
1518   PREFIX_EVEX_0F38BB,
1519   PREFIX_EVEX_0F38BC,
1520   PREFIX_EVEX_0F38BD,
1521   PREFIX_EVEX_0F38BE,
1522   PREFIX_EVEX_0F38BF,
1523   PREFIX_EVEX_0F38C4,
1524   PREFIX_EVEX_0F38C6_REG_1,
1525   PREFIX_EVEX_0F38C6_REG_2,
1526   PREFIX_EVEX_0F38C6_REG_5,
1527   PREFIX_EVEX_0F38C6_REG_6,
1528   PREFIX_EVEX_0F38C7_REG_1,
1529   PREFIX_EVEX_0F38C7_REG_2,
1530   PREFIX_EVEX_0F38C7_REG_5,
1531   PREFIX_EVEX_0F38C7_REG_6,
1532   PREFIX_EVEX_0F38C8,
1533   PREFIX_EVEX_0F38CA,
1534   PREFIX_EVEX_0F38CB,
1535   PREFIX_EVEX_0F38CC,
1536   PREFIX_EVEX_0F38CD,
1537
1538   PREFIX_EVEX_0F3A00,
1539   PREFIX_EVEX_0F3A01,
1540   PREFIX_EVEX_0F3A03,
1541   PREFIX_EVEX_0F3A04,
1542   PREFIX_EVEX_0F3A05,
1543   PREFIX_EVEX_0F3A08,
1544   PREFIX_EVEX_0F3A09,
1545   PREFIX_EVEX_0F3A0A,
1546   PREFIX_EVEX_0F3A0B,
1547   PREFIX_EVEX_0F3A0F,
1548   PREFIX_EVEX_0F3A14,
1549   PREFIX_EVEX_0F3A15,
1550   PREFIX_EVEX_0F3A16,
1551   PREFIX_EVEX_0F3A17,
1552   PREFIX_EVEX_0F3A18,
1553   PREFIX_EVEX_0F3A19,
1554   PREFIX_EVEX_0F3A1A,
1555   PREFIX_EVEX_0F3A1B,
1556   PREFIX_EVEX_0F3A1D,
1557   PREFIX_EVEX_0F3A1E,
1558   PREFIX_EVEX_0F3A1F,
1559   PREFIX_EVEX_0F3A20,
1560   PREFIX_EVEX_0F3A21,
1561   PREFIX_EVEX_0F3A22,
1562   PREFIX_EVEX_0F3A23,
1563   PREFIX_EVEX_0F3A25,
1564   PREFIX_EVEX_0F3A26,
1565   PREFIX_EVEX_0F3A27,
1566   PREFIX_EVEX_0F3A38,
1567   PREFIX_EVEX_0F3A39,
1568   PREFIX_EVEX_0F3A3A,
1569   PREFIX_EVEX_0F3A3B,
1570   PREFIX_EVEX_0F3A3E,
1571   PREFIX_EVEX_0F3A3F,
1572   PREFIX_EVEX_0F3A42,
1573   PREFIX_EVEX_0F3A43,
1574   PREFIX_EVEX_0F3A50,
1575   PREFIX_EVEX_0F3A51,
1576   PREFIX_EVEX_0F3A54,
1577   PREFIX_EVEX_0F3A55,
1578   PREFIX_EVEX_0F3A56,
1579   PREFIX_EVEX_0F3A57,
1580   PREFIX_EVEX_0F3A66,
1581   PREFIX_EVEX_0F3A67
1582 };
1583
1584 enum
1585 {
1586   X86_64_06 = 0,
1587   X86_64_07,
1588   X86_64_0D,
1589   X86_64_16,
1590   X86_64_17,
1591   X86_64_1E,
1592   X86_64_1F,
1593   X86_64_27,
1594   X86_64_2F,
1595   X86_64_37,
1596   X86_64_3F,
1597   X86_64_60,
1598   X86_64_61,
1599   X86_64_62,
1600   X86_64_63,
1601   X86_64_6D,
1602   X86_64_6F,
1603   X86_64_9A,
1604   X86_64_C4,
1605   X86_64_C5,
1606   X86_64_CE,
1607   X86_64_D4,
1608   X86_64_D5,
1609   X86_64_EA,
1610   X86_64_0F01_REG_0,
1611   X86_64_0F01_REG_1,
1612   X86_64_0F01_REG_2,
1613   X86_64_0F01_REG_3
1614 };
1615
1616 enum
1617 {
1618   THREE_BYTE_0F38 = 0,
1619   THREE_BYTE_0F3A,
1620   THREE_BYTE_0F7A
1621 };
1622
1623 enum
1624 {
1625   XOP_08 = 0,
1626   XOP_09,
1627   XOP_0A
1628 };
1629
1630 enum
1631 {
1632   VEX_0F = 0,
1633   VEX_0F38,
1634   VEX_0F3A
1635 };
1636
1637 enum
1638 {
1639   EVEX_0F = 0,
1640   EVEX_0F38,
1641   EVEX_0F3A
1642 };
1643
1644 enum
1645 {
1646   VEX_LEN_0F10_P_1 = 0,
1647   VEX_LEN_0F10_P_3,
1648   VEX_LEN_0F11_P_1,
1649   VEX_LEN_0F11_P_3,
1650   VEX_LEN_0F12_P_0_M_0,
1651   VEX_LEN_0F12_P_0_M_1,
1652   VEX_LEN_0F12_P_2,
1653   VEX_LEN_0F13_M_0,
1654   VEX_LEN_0F16_P_0_M_0,
1655   VEX_LEN_0F16_P_0_M_1,
1656   VEX_LEN_0F16_P_2,
1657   VEX_LEN_0F17_M_0,
1658   VEX_LEN_0F2A_P_1,
1659   VEX_LEN_0F2A_P_3,
1660   VEX_LEN_0F2C_P_1,
1661   VEX_LEN_0F2C_P_3,
1662   VEX_LEN_0F2D_P_1,
1663   VEX_LEN_0F2D_P_3,
1664   VEX_LEN_0F2E_P_0,
1665   VEX_LEN_0F2E_P_2,
1666   VEX_LEN_0F2F_P_0,
1667   VEX_LEN_0F2F_P_2,
1668   VEX_LEN_0F41_P_0,
1669   VEX_LEN_0F41_P_2,
1670   VEX_LEN_0F42_P_0,
1671   VEX_LEN_0F42_P_2,
1672   VEX_LEN_0F44_P_0,
1673   VEX_LEN_0F44_P_2,
1674   VEX_LEN_0F45_P_0,
1675   VEX_LEN_0F45_P_2,
1676   VEX_LEN_0F46_P_0,
1677   VEX_LEN_0F46_P_2,
1678   VEX_LEN_0F47_P_0,
1679   VEX_LEN_0F47_P_2,
1680   VEX_LEN_0F4A_P_0,
1681   VEX_LEN_0F4A_P_2,
1682   VEX_LEN_0F4B_P_0,
1683   VEX_LEN_0F4B_P_2,
1684   VEX_LEN_0F51_P_1,
1685   VEX_LEN_0F51_P_3,
1686   VEX_LEN_0F52_P_1,
1687   VEX_LEN_0F53_P_1,
1688   VEX_LEN_0F58_P_1,
1689   VEX_LEN_0F58_P_3,
1690   VEX_LEN_0F59_P_1,
1691   VEX_LEN_0F59_P_3,
1692   VEX_LEN_0F5A_P_1,
1693   VEX_LEN_0F5A_P_3,
1694   VEX_LEN_0F5C_P_1,
1695   VEX_LEN_0F5C_P_3,
1696   VEX_LEN_0F5D_P_1,
1697   VEX_LEN_0F5D_P_3,
1698   VEX_LEN_0F5E_P_1,
1699   VEX_LEN_0F5E_P_3,
1700   VEX_LEN_0F5F_P_1,
1701   VEX_LEN_0F5F_P_3,
1702   VEX_LEN_0F6E_P_2,
1703   VEX_LEN_0F7E_P_1,
1704   VEX_LEN_0F7E_P_2,
1705   VEX_LEN_0F90_P_0,
1706   VEX_LEN_0F90_P_2,
1707   VEX_LEN_0F91_P_0,
1708   VEX_LEN_0F91_P_2,
1709   VEX_LEN_0F92_P_0,
1710   VEX_LEN_0F92_P_2,
1711   VEX_LEN_0F92_P_3,
1712   VEX_LEN_0F93_P_0,
1713   VEX_LEN_0F93_P_2,
1714   VEX_LEN_0F93_P_3,
1715   VEX_LEN_0F98_P_0,
1716   VEX_LEN_0F98_P_2,
1717   VEX_LEN_0F99_P_0,
1718   VEX_LEN_0F99_P_2,
1719   VEX_LEN_0FAE_R_2_M_0,
1720   VEX_LEN_0FAE_R_3_M_0,
1721   VEX_LEN_0FC2_P_1,
1722   VEX_LEN_0FC2_P_3,
1723   VEX_LEN_0FC4_P_2,
1724   VEX_LEN_0FC5_P_2,
1725   VEX_LEN_0FD6_P_2,
1726   VEX_LEN_0FF7_P_2,
1727   VEX_LEN_0F3816_P_2,
1728   VEX_LEN_0F3819_P_2,
1729   VEX_LEN_0F381A_P_2_M_0,
1730   VEX_LEN_0F3836_P_2,
1731   VEX_LEN_0F3841_P_2,
1732   VEX_LEN_0F385A_P_2_M_0,
1733   VEX_LEN_0F38DB_P_2,
1734   VEX_LEN_0F38DC_P_2,
1735   VEX_LEN_0F38DD_P_2,
1736   VEX_LEN_0F38DE_P_2,
1737   VEX_LEN_0F38DF_P_2,
1738   VEX_LEN_0F38F2_P_0,
1739   VEX_LEN_0F38F3_R_1_P_0,
1740   VEX_LEN_0F38F3_R_2_P_0,
1741   VEX_LEN_0F38F3_R_3_P_0,
1742   VEX_LEN_0F38F5_P_0,
1743   VEX_LEN_0F38F5_P_1,
1744   VEX_LEN_0F38F5_P_3,
1745   VEX_LEN_0F38F6_P_3,
1746   VEX_LEN_0F38F7_P_0,
1747   VEX_LEN_0F38F7_P_1,
1748   VEX_LEN_0F38F7_P_2,
1749   VEX_LEN_0F38F7_P_3,
1750   VEX_LEN_0F3A00_P_2,
1751   VEX_LEN_0F3A01_P_2,
1752   VEX_LEN_0F3A06_P_2,
1753   VEX_LEN_0F3A0A_P_2,
1754   VEX_LEN_0F3A0B_P_2,
1755   VEX_LEN_0F3A14_P_2,
1756   VEX_LEN_0F3A15_P_2,
1757   VEX_LEN_0F3A16_P_2,
1758   VEX_LEN_0F3A17_P_2,
1759   VEX_LEN_0F3A18_P_2,
1760   VEX_LEN_0F3A19_P_2,
1761   VEX_LEN_0F3A20_P_2,
1762   VEX_LEN_0F3A21_P_2,
1763   VEX_LEN_0F3A22_P_2,
1764   VEX_LEN_0F3A30_P_2,
1765   VEX_LEN_0F3A31_P_2,
1766   VEX_LEN_0F3A32_P_2,
1767   VEX_LEN_0F3A33_P_2,
1768   VEX_LEN_0F3A38_P_2,
1769   VEX_LEN_0F3A39_P_2,
1770   VEX_LEN_0F3A41_P_2,
1771   VEX_LEN_0F3A44_P_2,
1772   VEX_LEN_0F3A46_P_2,
1773   VEX_LEN_0F3A60_P_2,
1774   VEX_LEN_0F3A61_P_2,
1775   VEX_LEN_0F3A62_P_2,
1776   VEX_LEN_0F3A63_P_2,
1777   VEX_LEN_0F3A6A_P_2,
1778   VEX_LEN_0F3A6B_P_2,
1779   VEX_LEN_0F3A6E_P_2,
1780   VEX_LEN_0F3A6F_P_2,
1781   VEX_LEN_0F3A7A_P_2,
1782   VEX_LEN_0F3A7B_P_2,
1783   VEX_LEN_0F3A7E_P_2,
1784   VEX_LEN_0F3A7F_P_2,
1785   VEX_LEN_0F3ADF_P_2,
1786   VEX_LEN_0F3AF0_P_3,
1787   VEX_LEN_0FXOP_08_CC,
1788   VEX_LEN_0FXOP_08_CD,
1789   VEX_LEN_0FXOP_08_CE,
1790   VEX_LEN_0FXOP_08_CF,
1791   VEX_LEN_0FXOP_08_EC,
1792   VEX_LEN_0FXOP_08_ED,
1793   VEX_LEN_0FXOP_08_EE,
1794   VEX_LEN_0FXOP_08_EF,
1795   VEX_LEN_0FXOP_09_80,
1796   VEX_LEN_0FXOP_09_81
1797 };
1798
1799 enum
1800 {
1801   VEX_W_0F10_P_0 = 0,
1802   VEX_W_0F10_P_1,
1803   VEX_W_0F10_P_2,
1804   VEX_W_0F10_P_3,
1805   VEX_W_0F11_P_0,
1806   VEX_W_0F11_P_1,
1807   VEX_W_0F11_P_2,
1808   VEX_W_0F11_P_3,
1809   VEX_W_0F12_P_0_M_0,
1810   VEX_W_0F12_P_0_M_1,
1811   VEX_W_0F12_P_1,
1812   VEX_W_0F12_P_2,
1813   VEX_W_0F12_P_3,
1814   VEX_W_0F13_M_0,
1815   VEX_W_0F14,
1816   VEX_W_0F15,
1817   VEX_W_0F16_P_0_M_0,
1818   VEX_W_0F16_P_0_M_1,
1819   VEX_W_0F16_P_1,
1820   VEX_W_0F16_P_2,
1821   VEX_W_0F17_M_0,
1822   VEX_W_0F28,
1823   VEX_W_0F29,
1824   VEX_W_0F2B_M_0,
1825   VEX_W_0F2E_P_0,
1826   VEX_W_0F2E_P_2,
1827   VEX_W_0F2F_P_0,
1828   VEX_W_0F2F_P_2,
1829   VEX_W_0F41_P_0_LEN_1,
1830   VEX_W_0F41_P_2_LEN_1,
1831   VEX_W_0F42_P_0_LEN_1,
1832   VEX_W_0F42_P_2_LEN_1,
1833   VEX_W_0F44_P_0_LEN_0,
1834   VEX_W_0F44_P_2_LEN_0,
1835   VEX_W_0F45_P_0_LEN_1,
1836   VEX_W_0F45_P_2_LEN_1,
1837   VEX_W_0F46_P_0_LEN_1,
1838   VEX_W_0F46_P_2_LEN_1,
1839   VEX_W_0F47_P_0_LEN_1,
1840   VEX_W_0F47_P_2_LEN_1,
1841   VEX_W_0F4A_P_0_LEN_1,
1842   VEX_W_0F4A_P_2_LEN_1,
1843   VEX_W_0F4B_P_0_LEN_1,
1844   VEX_W_0F4B_P_2_LEN_1,
1845   VEX_W_0F50_M_0,
1846   VEX_W_0F51_P_0,
1847   VEX_W_0F51_P_1,
1848   VEX_W_0F51_P_2,
1849   VEX_W_0F51_P_3,
1850   VEX_W_0F52_P_0,
1851   VEX_W_0F52_P_1,
1852   VEX_W_0F53_P_0,
1853   VEX_W_0F53_P_1,
1854   VEX_W_0F58_P_0,
1855   VEX_W_0F58_P_1,
1856   VEX_W_0F58_P_2,
1857   VEX_W_0F58_P_3,
1858   VEX_W_0F59_P_0,
1859   VEX_W_0F59_P_1,
1860   VEX_W_0F59_P_2,
1861   VEX_W_0F59_P_3,
1862   VEX_W_0F5A_P_0,
1863   VEX_W_0F5A_P_1,
1864   VEX_W_0F5A_P_3,
1865   VEX_W_0F5B_P_0,
1866   VEX_W_0F5B_P_1,
1867   VEX_W_0F5B_P_2,
1868   VEX_W_0F5C_P_0,
1869   VEX_W_0F5C_P_1,
1870   VEX_W_0F5C_P_2,
1871   VEX_W_0F5C_P_3,
1872   VEX_W_0F5D_P_0,
1873   VEX_W_0F5D_P_1,
1874   VEX_W_0F5D_P_2,
1875   VEX_W_0F5D_P_3,
1876   VEX_W_0F5E_P_0,
1877   VEX_W_0F5E_P_1,
1878   VEX_W_0F5E_P_2,
1879   VEX_W_0F5E_P_3,
1880   VEX_W_0F5F_P_0,
1881   VEX_W_0F5F_P_1,
1882   VEX_W_0F5F_P_2,
1883   VEX_W_0F5F_P_3,
1884   VEX_W_0F60_P_2,
1885   VEX_W_0F61_P_2,
1886   VEX_W_0F62_P_2,
1887   VEX_W_0F63_P_2,
1888   VEX_W_0F64_P_2,
1889   VEX_W_0F65_P_2,
1890   VEX_W_0F66_P_2,
1891   VEX_W_0F67_P_2,
1892   VEX_W_0F68_P_2,
1893   VEX_W_0F69_P_2,
1894   VEX_W_0F6A_P_2,
1895   VEX_W_0F6B_P_2,
1896   VEX_W_0F6C_P_2,
1897   VEX_W_0F6D_P_2,
1898   VEX_W_0F6F_P_1,
1899   VEX_W_0F6F_P_2,
1900   VEX_W_0F70_P_1,
1901   VEX_W_0F70_P_2,
1902   VEX_W_0F70_P_3,
1903   VEX_W_0F71_R_2_P_2,
1904   VEX_W_0F71_R_4_P_2,
1905   VEX_W_0F71_R_6_P_2,
1906   VEX_W_0F72_R_2_P_2,
1907   VEX_W_0F72_R_4_P_2,
1908   VEX_W_0F72_R_6_P_2,
1909   VEX_W_0F73_R_2_P_2,
1910   VEX_W_0F73_R_3_P_2,
1911   VEX_W_0F73_R_6_P_2,
1912   VEX_W_0F73_R_7_P_2,
1913   VEX_W_0F74_P_2,
1914   VEX_W_0F75_P_2,
1915   VEX_W_0F76_P_2,
1916   VEX_W_0F77_P_0,
1917   VEX_W_0F7C_P_2,
1918   VEX_W_0F7C_P_3,
1919   VEX_W_0F7D_P_2,
1920   VEX_W_0F7D_P_3,
1921   VEX_W_0F7E_P_1,
1922   VEX_W_0F7F_P_1,
1923   VEX_W_0F7F_P_2,
1924   VEX_W_0F90_P_0_LEN_0,
1925   VEX_W_0F90_P_2_LEN_0,
1926   VEX_W_0F91_P_0_LEN_0,
1927   VEX_W_0F91_P_2_LEN_0,
1928   VEX_W_0F92_P_0_LEN_0,
1929   VEX_W_0F92_P_2_LEN_0,
1930   VEX_W_0F92_P_3_LEN_0,
1931   VEX_W_0F93_P_0_LEN_0,
1932   VEX_W_0F93_P_2_LEN_0,
1933   VEX_W_0F93_P_3_LEN_0,
1934   VEX_W_0F98_P_0_LEN_0,
1935   VEX_W_0F98_P_2_LEN_0,
1936   VEX_W_0F99_P_0_LEN_0,
1937   VEX_W_0F99_P_2_LEN_0,
1938   VEX_W_0FAE_R_2_M_0,
1939   VEX_W_0FAE_R_3_M_0,
1940   VEX_W_0FC2_P_0,
1941   VEX_W_0FC2_P_1,
1942   VEX_W_0FC2_P_2,
1943   VEX_W_0FC2_P_3,
1944   VEX_W_0FC4_P_2,
1945   VEX_W_0FC5_P_2,
1946   VEX_W_0FD0_P_2,
1947   VEX_W_0FD0_P_3,
1948   VEX_W_0FD1_P_2,
1949   VEX_W_0FD2_P_2,
1950   VEX_W_0FD3_P_2,
1951   VEX_W_0FD4_P_2,
1952   VEX_W_0FD5_P_2,
1953   VEX_W_0FD6_P_2,
1954   VEX_W_0FD7_P_2_M_1,
1955   VEX_W_0FD8_P_2,
1956   VEX_W_0FD9_P_2,
1957   VEX_W_0FDA_P_2,
1958   VEX_W_0FDB_P_2,
1959   VEX_W_0FDC_P_2,
1960   VEX_W_0FDD_P_2,
1961   VEX_W_0FDE_P_2,
1962   VEX_W_0FDF_P_2,
1963   VEX_W_0FE0_P_2,
1964   VEX_W_0FE1_P_2,
1965   VEX_W_0FE2_P_2,
1966   VEX_W_0FE3_P_2,
1967   VEX_W_0FE4_P_2,
1968   VEX_W_0FE5_P_2,
1969   VEX_W_0FE6_P_1,
1970   VEX_W_0FE6_P_2,
1971   VEX_W_0FE6_P_3,
1972   VEX_W_0FE7_P_2_M_0,
1973   VEX_W_0FE8_P_2,
1974   VEX_W_0FE9_P_2,
1975   VEX_W_0FEA_P_2,
1976   VEX_W_0FEB_P_2,
1977   VEX_W_0FEC_P_2,
1978   VEX_W_0FED_P_2,
1979   VEX_W_0FEE_P_2,
1980   VEX_W_0FEF_P_2,
1981   VEX_W_0FF0_P_3_M_0,
1982   VEX_W_0FF1_P_2,
1983   VEX_W_0FF2_P_2,
1984   VEX_W_0FF3_P_2,
1985   VEX_W_0FF4_P_2,
1986   VEX_W_0FF5_P_2,
1987   VEX_W_0FF6_P_2,
1988   VEX_W_0FF7_P_2,
1989   VEX_W_0FF8_P_2,
1990   VEX_W_0FF9_P_2,
1991   VEX_W_0FFA_P_2,
1992   VEX_W_0FFB_P_2,
1993   VEX_W_0FFC_P_2,
1994   VEX_W_0FFD_P_2,
1995   VEX_W_0FFE_P_2,
1996   VEX_W_0F3800_P_2,
1997   VEX_W_0F3801_P_2,
1998   VEX_W_0F3802_P_2,
1999   VEX_W_0F3803_P_2,
2000   VEX_W_0F3804_P_2,
2001   VEX_W_0F3805_P_2,
2002   VEX_W_0F3806_P_2,
2003   VEX_W_0F3807_P_2,
2004   VEX_W_0F3808_P_2,
2005   VEX_W_0F3809_P_2,
2006   VEX_W_0F380A_P_2,
2007   VEX_W_0F380B_P_2,
2008   VEX_W_0F380C_P_2,
2009   VEX_W_0F380D_P_2,
2010   VEX_W_0F380E_P_2,
2011   VEX_W_0F380F_P_2,
2012   VEX_W_0F3816_P_2,
2013   VEX_W_0F3817_P_2,
2014   VEX_W_0F3818_P_2,
2015   VEX_W_0F3819_P_2,
2016   VEX_W_0F381A_P_2_M_0,
2017   VEX_W_0F381C_P_2,
2018   VEX_W_0F381D_P_2,
2019   VEX_W_0F381E_P_2,
2020   VEX_W_0F3820_P_2,
2021   VEX_W_0F3821_P_2,
2022   VEX_W_0F3822_P_2,
2023   VEX_W_0F3823_P_2,
2024   VEX_W_0F3824_P_2,
2025   VEX_W_0F3825_P_2,
2026   VEX_W_0F3828_P_2,
2027   VEX_W_0F3829_P_2,
2028   VEX_W_0F382A_P_2_M_0,
2029   VEX_W_0F382B_P_2,
2030   VEX_W_0F382C_P_2_M_0,
2031   VEX_W_0F382D_P_2_M_0,
2032   VEX_W_0F382E_P_2_M_0,
2033   VEX_W_0F382F_P_2_M_0,
2034   VEX_W_0F3830_P_2,
2035   VEX_W_0F3831_P_2,
2036   VEX_W_0F3832_P_2,
2037   VEX_W_0F3833_P_2,
2038   VEX_W_0F3834_P_2,
2039   VEX_W_0F3835_P_2,
2040   VEX_W_0F3836_P_2,
2041   VEX_W_0F3837_P_2,
2042   VEX_W_0F3838_P_2,
2043   VEX_W_0F3839_P_2,
2044   VEX_W_0F383A_P_2,
2045   VEX_W_0F383B_P_2,
2046   VEX_W_0F383C_P_2,
2047   VEX_W_0F383D_P_2,
2048   VEX_W_0F383E_P_2,
2049   VEX_W_0F383F_P_2,
2050   VEX_W_0F3840_P_2,
2051   VEX_W_0F3841_P_2,
2052   VEX_W_0F3846_P_2,
2053   VEX_W_0F3858_P_2,
2054   VEX_W_0F3859_P_2,
2055   VEX_W_0F385A_P_2_M_0,
2056   VEX_W_0F3878_P_2,
2057   VEX_W_0F3879_P_2,
2058   VEX_W_0F38DB_P_2,
2059   VEX_W_0F38DC_P_2,
2060   VEX_W_0F38DD_P_2,
2061   VEX_W_0F38DE_P_2,
2062   VEX_W_0F38DF_P_2,
2063   VEX_W_0F3A00_P_2,
2064   VEX_W_0F3A01_P_2,
2065   VEX_W_0F3A02_P_2,
2066   VEX_W_0F3A04_P_2,
2067   VEX_W_0F3A05_P_2,
2068   VEX_W_0F3A06_P_2,
2069   VEX_W_0F3A08_P_2,
2070   VEX_W_0F3A09_P_2,
2071   VEX_W_0F3A0A_P_2,
2072   VEX_W_0F3A0B_P_2,
2073   VEX_W_0F3A0C_P_2,
2074   VEX_W_0F3A0D_P_2,
2075   VEX_W_0F3A0E_P_2,
2076   VEX_W_0F3A0F_P_2,
2077   VEX_W_0F3A14_P_2,
2078   VEX_W_0F3A15_P_2,
2079   VEX_W_0F3A18_P_2,
2080   VEX_W_0F3A19_P_2,
2081   VEX_W_0F3A20_P_2,
2082   VEX_W_0F3A21_P_2,
2083   VEX_W_0F3A30_P_2_LEN_0,
2084   VEX_W_0F3A31_P_2_LEN_0,
2085   VEX_W_0F3A32_P_2_LEN_0,
2086   VEX_W_0F3A33_P_2_LEN_0,
2087   VEX_W_0F3A38_P_2,
2088   VEX_W_0F3A39_P_2,
2089   VEX_W_0F3A40_P_2,
2090   VEX_W_0F3A41_P_2,
2091   VEX_W_0F3A42_P_2,
2092   VEX_W_0F3A44_P_2,
2093   VEX_W_0F3A46_P_2,
2094   VEX_W_0F3A48_P_2,
2095   VEX_W_0F3A49_P_2,
2096   VEX_W_0F3A4A_P_2,
2097   VEX_W_0F3A4B_P_2,
2098   VEX_W_0F3A4C_P_2,
2099   VEX_W_0F3A60_P_2,
2100   VEX_W_0F3A61_P_2,
2101   VEX_W_0F3A62_P_2,
2102   VEX_W_0F3A63_P_2,
2103   VEX_W_0F3ADF_P_2,
2104
2105   EVEX_W_0F10_P_0,
2106   EVEX_W_0F10_P_1_M_0,
2107   EVEX_W_0F10_P_1_M_1,
2108   EVEX_W_0F10_P_2,
2109   EVEX_W_0F10_P_3_M_0,
2110   EVEX_W_0F10_P_3_M_1,
2111   EVEX_W_0F11_P_0,
2112   EVEX_W_0F11_P_1_M_0,
2113   EVEX_W_0F11_P_1_M_1,
2114   EVEX_W_0F11_P_2,
2115   EVEX_W_0F11_P_3_M_0,
2116   EVEX_W_0F11_P_3_M_1,
2117   EVEX_W_0F12_P_0_M_0,
2118   EVEX_W_0F12_P_0_M_1,
2119   EVEX_W_0F12_P_1,
2120   EVEX_W_0F12_P_2,
2121   EVEX_W_0F12_P_3,
2122   EVEX_W_0F13_P_0,
2123   EVEX_W_0F13_P_2,
2124   EVEX_W_0F14_P_0,
2125   EVEX_W_0F14_P_2,
2126   EVEX_W_0F15_P_0,
2127   EVEX_W_0F15_P_2,
2128   EVEX_W_0F16_P_0_M_0,
2129   EVEX_W_0F16_P_0_M_1,
2130   EVEX_W_0F16_P_1,
2131   EVEX_W_0F16_P_2,
2132   EVEX_W_0F17_P_0,
2133   EVEX_W_0F17_P_2,
2134   EVEX_W_0F28_P_0,
2135   EVEX_W_0F28_P_2,
2136   EVEX_W_0F29_P_0,
2137   EVEX_W_0F29_P_2,
2138   EVEX_W_0F2A_P_1,
2139   EVEX_W_0F2A_P_3,
2140   EVEX_W_0F2B_P_0,
2141   EVEX_W_0F2B_P_2,
2142   EVEX_W_0F2E_P_0,
2143   EVEX_W_0F2E_P_2,
2144   EVEX_W_0F2F_P_0,
2145   EVEX_W_0F2F_P_2,
2146   EVEX_W_0F51_P_0,
2147   EVEX_W_0F51_P_1,
2148   EVEX_W_0F51_P_2,
2149   EVEX_W_0F51_P_3,
2150   EVEX_W_0F54_P_0,
2151   EVEX_W_0F54_P_2,
2152   EVEX_W_0F55_P_0,
2153   EVEX_W_0F55_P_2,
2154   EVEX_W_0F56_P_0,
2155   EVEX_W_0F56_P_2,
2156   EVEX_W_0F57_P_0,
2157   EVEX_W_0F57_P_2,
2158   EVEX_W_0F58_P_0,
2159   EVEX_W_0F58_P_1,
2160   EVEX_W_0F58_P_2,
2161   EVEX_W_0F58_P_3,
2162   EVEX_W_0F59_P_0,
2163   EVEX_W_0F59_P_1,
2164   EVEX_W_0F59_P_2,
2165   EVEX_W_0F59_P_3,
2166   EVEX_W_0F5A_P_0,
2167   EVEX_W_0F5A_P_1,
2168   EVEX_W_0F5A_P_2,
2169   EVEX_W_0F5A_P_3,
2170   EVEX_W_0F5B_P_0,
2171   EVEX_W_0F5B_P_1,
2172   EVEX_W_0F5B_P_2,
2173   EVEX_W_0F5C_P_0,
2174   EVEX_W_0F5C_P_1,
2175   EVEX_W_0F5C_P_2,
2176   EVEX_W_0F5C_P_3,
2177   EVEX_W_0F5D_P_0,
2178   EVEX_W_0F5D_P_1,
2179   EVEX_W_0F5D_P_2,
2180   EVEX_W_0F5D_P_3,
2181   EVEX_W_0F5E_P_0,
2182   EVEX_W_0F5E_P_1,
2183   EVEX_W_0F5E_P_2,
2184   EVEX_W_0F5E_P_3,
2185   EVEX_W_0F5F_P_0,
2186   EVEX_W_0F5F_P_1,
2187   EVEX_W_0F5F_P_2,
2188   EVEX_W_0F5F_P_3,
2189   EVEX_W_0F62_P_2,
2190   EVEX_W_0F66_P_2,
2191   EVEX_W_0F6A_P_2,
2192   EVEX_W_0F6B_P_2,
2193   EVEX_W_0F6C_P_2,
2194   EVEX_W_0F6D_P_2,
2195   EVEX_W_0F6E_P_2,
2196   EVEX_W_0F6F_P_1,
2197   EVEX_W_0F6F_P_2,
2198   EVEX_W_0F6F_P_3,
2199   EVEX_W_0F70_P_2,
2200   EVEX_W_0F72_R_2_P_2,
2201   EVEX_W_0F72_R_6_P_2,
2202   EVEX_W_0F73_R_2_P_2,
2203   EVEX_W_0F73_R_6_P_2,
2204   EVEX_W_0F76_P_2,
2205   EVEX_W_0F78_P_0,
2206   EVEX_W_0F78_P_2,
2207   EVEX_W_0F79_P_0,
2208   EVEX_W_0F79_P_2,
2209   EVEX_W_0F7A_P_1,
2210   EVEX_W_0F7A_P_2,
2211   EVEX_W_0F7A_P_3,
2212   EVEX_W_0F7B_P_1,
2213   EVEX_W_0F7B_P_2,
2214   EVEX_W_0F7B_P_3,
2215   EVEX_W_0F7E_P_1,
2216   EVEX_W_0F7E_P_2,
2217   EVEX_W_0F7F_P_1,
2218   EVEX_W_0F7F_P_2,
2219   EVEX_W_0F7F_P_3,
2220   EVEX_W_0FC2_P_0,
2221   EVEX_W_0FC2_P_1,
2222   EVEX_W_0FC2_P_2,
2223   EVEX_W_0FC2_P_3,
2224   EVEX_W_0FC6_P_0,
2225   EVEX_W_0FC6_P_2,
2226   EVEX_W_0FD2_P_2,
2227   EVEX_W_0FD3_P_2,
2228   EVEX_W_0FD4_P_2,
2229   EVEX_W_0FD6_P_2,
2230   EVEX_W_0FE6_P_1,
2231   EVEX_W_0FE6_P_2,
2232   EVEX_W_0FE6_P_3,
2233   EVEX_W_0FE7_P_2,
2234   EVEX_W_0FF2_P_2,
2235   EVEX_W_0FF3_P_2,
2236   EVEX_W_0FF4_P_2,
2237   EVEX_W_0FFA_P_2,
2238   EVEX_W_0FFB_P_2,
2239   EVEX_W_0FFE_P_2,
2240   EVEX_W_0F380C_P_2,
2241   EVEX_W_0F380D_P_2,
2242   EVEX_W_0F3810_P_1,
2243   EVEX_W_0F3810_P_2,
2244   EVEX_W_0F3811_P_1,
2245   EVEX_W_0F3811_P_2,
2246   EVEX_W_0F3812_P_1,
2247   EVEX_W_0F3812_P_2,
2248   EVEX_W_0F3813_P_1,
2249   EVEX_W_0F3813_P_2,
2250   EVEX_W_0F3814_P_1,
2251   EVEX_W_0F3815_P_1,
2252   EVEX_W_0F3818_P_2,
2253   EVEX_W_0F3819_P_2,
2254   EVEX_W_0F381A_P_2,
2255   EVEX_W_0F381B_P_2,
2256   EVEX_W_0F381E_P_2,
2257   EVEX_W_0F381F_P_2,
2258   EVEX_W_0F3820_P_1,
2259   EVEX_W_0F3821_P_1,
2260   EVEX_W_0F3822_P_1,
2261   EVEX_W_0F3823_P_1,
2262   EVEX_W_0F3824_P_1,
2263   EVEX_W_0F3825_P_1,
2264   EVEX_W_0F3825_P_2,
2265   EVEX_W_0F3826_P_1,
2266   EVEX_W_0F3826_P_2,
2267   EVEX_W_0F3828_P_1,
2268   EVEX_W_0F3828_P_2,
2269   EVEX_W_0F3829_P_1,
2270   EVEX_W_0F3829_P_2,
2271   EVEX_W_0F382A_P_1,
2272   EVEX_W_0F382A_P_2,
2273   EVEX_W_0F382B_P_2,
2274   EVEX_W_0F3830_P_1,
2275   EVEX_W_0F3831_P_1,
2276   EVEX_W_0F3832_P_1,
2277   EVEX_W_0F3833_P_1,
2278   EVEX_W_0F3834_P_1,
2279   EVEX_W_0F3835_P_1,
2280   EVEX_W_0F3835_P_2,
2281   EVEX_W_0F3837_P_2,
2282   EVEX_W_0F3838_P_1,
2283   EVEX_W_0F3839_P_1,
2284   EVEX_W_0F383A_P_1,
2285   EVEX_W_0F3840_P_2,
2286   EVEX_W_0F3858_P_2,
2287   EVEX_W_0F3859_P_2,
2288   EVEX_W_0F385A_P_2,
2289   EVEX_W_0F385B_P_2,
2290   EVEX_W_0F3866_P_2,
2291   EVEX_W_0F3875_P_2,
2292   EVEX_W_0F3878_P_2,
2293   EVEX_W_0F3879_P_2,
2294   EVEX_W_0F387A_P_2,
2295   EVEX_W_0F387B_P_2,
2296   EVEX_W_0F387D_P_2,
2297   EVEX_W_0F388D_P_2,
2298   EVEX_W_0F3891_P_2,
2299   EVEX_W_0F3893_P_2,
2300   EVEX_W_0F38A1_P_2,
2301   EVEX_W_0F38A3_P_2,
2302   EVEX_W_0F38C7_R_1_P_2,
2303   EVEX_W_0F38C7_R_2_P_2,
2304   EVEX_W_0F38C7_R_5_P_2,
2305   EVEX_W_0F38C7_R_6_P_2,
2306
2307   EVEX_W_0F3A00_P_2,
2308   EVEX_W_0F3A01_P_2,
2309   EVEX_W_0F3A04_P_2,
2310   EVEX_W_0F3A05_P_2,
2311   EVEX_W_0F3A08_P_2,
2312   EVEX_W_0F3A09_P_2,
2313   EVEX_W_0F3A0A_P_2,
2314   EVEX_W_0F3A0B_P_2,
2315   EVEX_W_0F3A16_P_2,
2316   EVEX_W_0F3A18_P_2,
2317   EVEX_W_0F3A19_P_2,
2318   EVEX_W_0F3A1A_P_2,
2319   EVEX_W_0F3A1B_P_2,
2320   EVEX_W_0F3A1D_P_2,
2321   EVEX_W_0F3A21_P_2,
2322   EVEX_W_0F3A22_P_2,
2323   EVEX_W_0F3A23_P_2,
2324   EVEX_W_0F3A38_P_2,
2325   EVEX_W_0F3A39_P_2,
2326   EVEX_W_0F3A3A_P_2,
2327   EVEX_W_0F3A3B_P_2,
2328   EVEX_W_0F3A3E_P_2,
2329   EVEX_W_0F3A3F_P_2,
2330   EVEX_W_0F3A42_P_2,
2331   EVEX_W_0F3A43_P_2,
2332   EVEX_W_0F3A50_P_2,
2333   EVEX_W_0F3A51_P_2,
2334   EVEX_W_0F3A56_P_2,
2335   EVEX_W_0F3A57_P_2,
2336   EVEX_W_0F3A66_P_2,
2337   EVEX_W_0F3A67_P_2
2338 };
2339
2340 typedef void (*op_rtn) (int bytemode, int sizeflag);
2341
2342 struct dis386 {
2343   const char *name;
2344   struct
2345     {
2346       op_rtn rtn;
2347       int bytemode;
2348     } op[MAX_OPERANDS];
2349 };
2350
2351 /* Upper case letters in the instruction names here are macros.
2352    'A' => print 'b' if no register operands or suffix_always is true
2353    'B' => print 'b' if suffix_always is true
2354    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2355           size prefix
2356    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2357           suffix_always is true
2358    'E' => print 'e' if 32-bit form of jcxz
2359    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2360    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2361    'H' => print ",pt" or ",pn" branch hint
2362    'I' => honor following macro letter even in Intel mode (implemented only
2363           for some of the macro letters)
2364    'J' => print 'l'
2365    'K' => print 'd' or 'q' if rex prefix is present.
2366    'L' => print 'l' if suffix_always is true
2367    'M' => print 'r' if intel_mnemonic is false.
2368    'N' => print 'n' if instruction has no wait "prefix"
2369    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2370    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2371           or suffix_always is true.  print 'q' if rex prefix is present.
2372    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2373           is true
2374    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2375    'S' => print 'w', 'l' or 'q' if suffix_always is true
2376    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2377    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2378    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2379    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2380    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2381    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2382           suffix_always is true.
2383    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2384    '!' => change condition from true to false or from false to true.
2385    '%' => add 1 upper case letter to the macro.
2386
2387    2 upper case letter macros:
2388    "XY" => print 'x' or 'y' if no register operands or suffix_always
2389            is true.
2390    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2391    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2392            or suffix_always is true
2393    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2394    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2395    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2396    "LW" => print 'd', 'q' depending on the VEX.W bit
2397    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2398            an operand size prefix, or suffix_always is true.  print
2399            'q' if rex prefix is present.
2400
2401    Many of the above letters print nothing in Intel mode.  See "putop"
2402    for the details.
2403
2404    Braces '{' and '}', and vertical bars '|', indicate alternative
2405    mnemonic strings for AT&T and Intel.  */
2406
2407 static const struct dis386 dis386[] = {
2408   /* 00 */
2409   { "addB",             { Ebh1, Gb } },
2410   { "addS",             { Evh1, Gv } },
2411   { "addB",             { Gb, EbS } },
2412   { "addS",             { Gv, EvS } },
2413   { "addB",             { AL, Ib } },
2414   { "addS",             { eAX, Iv } },
2415   { X86_64_TABLE (X86_64_06) },
2416   { X86_64_TABLE (X86_64_07) },
2417   /* 08 */
2418   { "orB",              { Ebh1, Gb } },
2419   { "orS",              { Evh1, Gv } },
2420   { "orB",              { Gb, EbS } },
2421   { "orS",              { Gv, EvS } },
2422   { "orB",              { AL, Ib } },
2423   { "orS",              { eAX, Iv } },
2424   { X86_64_TABLE (X86_64_0D) },
2425   { Bad_Opcode },       /* 0x0f extended opcode escape */
2426   /* 10 */
2427   { "adcB",             { Ebh1, Gb } },
2428   { "adcS",             { Evh1, Gv } },
2429   { "adcB",             { Gb, EbS } },
2430   { "adcS",             { Gv, EvS } },
2431   { "adcB",             { AL, Ib } },
2432   { "adcS",             { eAX, Iv } },
2433   { X86_64_TABLE (X86_64_16) },
2434   { X86_64_TABLE (X86_64_17) },
2435   /* 18 */
2436   { "sbbB",             { Ebh1, Gb } },
2437   { "sbbS",             { Evh1, Gv } },
2438   { "sbbB",             { Gb, EbS } },
2439   { "sbbS",             { Gv, EvS } },
2440   { "sbbB",             { AL, Ib } },
2441   { "sbbS",             { eAX, Iv } },
2442   { X86_64_TABLE (X86_64_1E) },
2443   { X86_64_TABLE (X86_64_1F) },
2444   /* 20 */
2445   { "andB",             { Ebh1, Gb } },
2446   { "andS",             { Evh1, Gv } },
2447   { "andB",             { Gb, EbS } },
2448   { "andS",             { Gv, EvS } },
2449   { "andB",             { AL, Ib } },
2450   { "andS",             { eAX, Iv } },
2451   { Bad_Opcode },       /* SEG ES prefix */
2452   { X86_64_TABLE (X86_64_27) },
2453   /* 28 */
2454   { "subB",             { Ebh1, Gb } },
2455   { "subS",             { Evh1, Gv } },
2456   { "subB",             { Gb, EbS } },
2457   { "subS",             { Gv, EvS } },
2458   { "subB",             { AL, Ib } },
2459   { "subS",             { eAX, Iv } },
2460   { Bad_Opcode },       /* SEG CS prefix */
2461   { X86_64_TABLE (X86_64_2F) },
2462   /* 30 */
2463   { "xorB",             { Ebh1, Gb } },
2464   { "xorS",             { Evh1, Gv } },
2465   { "xorB",             { Gb, EbS } },
2466   { "xorS",             { Gv, EvS } },
2467   { "xorB",             { AL, Ib } },
2468   { "xorS",             { eAX, Iv } },
2469   { Bad_Opcode },       /* SEG SS prefix */
2470   { X86_64_TABLE (X86_64_37) },
2471   /* 38 */
2472   { "cmpB",             { Eb, Gb } },
2473   { "cmpS",             { Ev, Gv } },
2474   { "cmpB",             { Gb, EbS } },
2475   { "cmpS",             { Gv, EvS } },
2476   { "cmpB",             { AL, Ib } },
2477   { "cmpS",             { eAX, Iv } },
2478   { Bad_Opcode },       /* SEG DS prefix */
2479   { X86_64_TABLE (X86_64_3F) },
2480   /* 40 */
2481   { "inc{S|}",          { RMeAX } },
2482   { "inc{S|}",          { RMeCX } },
2483   { "inc{S|}",          { RMeDX } },
2484   { "inc{S|}",          { RMeBX } },
2485   { "inc{S|}",          { RMeSP } },
2486   { "inc{S|}",          { RMeBP } },
2487   { "inc{S|}",          { RMeSI } },
2488   { "inc{S|}",          { RMeDI } },
2489   /* 48 */
2490   { "dec{S|}",          { RMeAX } },
2491   { "dec{S|}",          { RMeCX } },
2492   { "dec{S|}",          { RMeDX } },
2493   { "dec{S|}",          { RMeBX } },
2494   { "dec{S|}",          { RMeSP } },
2495   { "dec{S|}",          { RMeBP } },
2496   { "dec{S|}",          { RMeSI } },
2497   { "dec{S|}",          { RMeDI } },
2498   /* 50 */
2499   { "pushV",            { RMrAX } },
2500   { "pushV",            { RMrCX } },
2501   { "pushV",            { RMrDX } },
2502   { "pushV",            { RMrBX } },
2503   { "pushV",            { RMrSP } },
2504   { "pushV",            { RMrBP } },
2505   { "pushV",            { RMrSI } },
2506   { "pushV",            { RMrDI } },
2507   /* 58 */
2508   { "popV",             { RMrAX } },
2509   { "popV",             { RMrCX } },
2510   { "popV",             { RMrDX } },
2511   { "popV",             { RMrBX } },
2512   { "popV",             { RMrSP } },
2513   { "popV",             { RMrBP } },
2514   { "popV",             { RMrSI } },
2515   { "popV",             { RMrDI } },
2516   /* 60 */
2517   { X86_64_TABLE (X86_64_60) },
2518   { X86_64_TABLE (X86_64_61) },
2519   { X86_64_TABLE (X86_64_62) },
2520   { X86_64_TABLE (X86_64_63) },
2521   { Bad_Opcode },       /* seg fs */
2522   { Bad_Opcode },       /* seg gs */
2523   { Bad_Opcode },       /* op size prefix */
2524   { Bad_Opcode },       /* adr size prefix */
2525   /* 68 */
2526   { "pushT",            { sIv } },
2527   { "imulS",            { Gv, Ev, Iv } },
2528   { "pushT",            { sIbT } },
2529   { "imulS",            { Gv, Ev, sIb } },
2530   { "ins{b|}",          { Ybr, indirDX } },
2531   { X86_64_TABLE (X86_64_6D) },
2532   { "outs{b|}",         { indirDXr, Xb } },
2533   { X86_64_TABLE (X86_64_6F) },
2534   /* 70 */
2535   { "joH",              { Jb, BND, cond_jump_flag } },
2536   { "jnoH",             { Jb, BND, cond_jump_flag } },
2537   { "jbH",              { Jb, BND, cond_jump_flag } },
2538   { "jaeH",             { Jb, BND, cond_jump_flag } },
2539   { "jeH",              { Jb, BND, cond_jump_flag } },
2540   { "jneH",             { Jb, BND, cond_jump_flag } },
2541   { "jbeH",             { Jb, BND, cond_jump_flag } },
2542   { "jaH",              { Jb, BND, cond_jump_flag } },
2543   /* 78 */
2544   { "jsH",              { Jb, BND, cond_jump_flag } },
2545   { "jnsH",             { Jb, BND, cond_jump_flag } },
2546   { "jpH",              { Jb, BND, cond_jump_flag } },
2547   { "jnpH",             { Jb, BND, cond_jump_flag } },
2548   { "jlH",              { Jb, BND, cond_jump_flag } },
2549   { "jgeH",             { Jb, BND, cond_jump_flag } },
2550   { "jleH",             { Jb, BND, cond_jump_flag } },
2551   { "jgH",              { Jb, BND, cond_jump_flag } },
2552   /* 80 */
2553   { REG_TABLE (REG_80) },
2554   { REG_TABLE (REG_81) },
2555   { Bad_Opcode },
2556   { REG_TABLE (REG_82) },
2557   { "testB",            { Eb, Gb } },
2558   { "testS",            { Ev, Gv } },
2559   { "xchgB",            { Ebh2, Gb } },
2560   { "xchgS",            { Evh2, Gv } },
2561   /* 88 */
2562   { "movB",             { Ebh3, Gb } },
2563   { "movS",             { Evh3, Gv } },
2564   { "movB",             { Gb, EbS } },
2565   { "movS",             { Gv, EvS } },
2566   { "movD",             { Sv, Sw } },
2567   { MOD_TABLE (MOD_8D) },
2568   { "movD",             { Sw, Sv } },
2569   { REG_TABLE (REG_8F) },
2570   /* 90 */
2571   { PREFIX_TABLE (PREFIX_90) },
2572   { "xchgS",            { RMeCX, eAX } },
2573   { "xchgS",            { RMeDX, eAX } },
2574   { "xchgS",            { RMeBX, eAX } },
2575   { "xchgS",            { RMeSP, eAX } },
2576   { "xchgS",            { RMeBP, eAX } },
2577   { "xchgS",            { RMeSI, eAX } },
2578   { "xchgS",            { RMeDI, eAX } },
2579   /* 98 */
2580   { "cW{t|}R",          { XX } },
2581   { "cR{t|}O",          { XX } },
2582   { X86_64_TABLE (X86_64_9A) },
2583   { Bad_Opcode },       /* fwait */
2584   { "pushfT",           { XX } },
2585   { "popfT",            { XX } },
2586   { "sahf",             { XX } },
2587   { "lahf",             { XX } },
2588   /* a0 */
2589   { "mov%LB",           { AL, Ob } },
2590   { "mov%LS",           { eAX, Ov } },
2591   { "mov%LB",           { Ob, AL } },
2592   { "mov%LS",           { Ov, eAX } },
2593   { "movs{b|}",         { Ybr, Xb } },
2594   { "movs{R|}",         { Yvr, Xv } },
2595   { "cmps{b|}",         { Xb, Yb } },
2596   { "cmps{R|}",         { Xv, Yv } },
2597   /* a8 */
2598   { "testB",            { AL, Ib } },
2599   { "testS",            { eAX, Iv } },
2600   { "stosB",            { Ybr, AL } },
2601   { "stosS",            { Yvr, eAX } },
2602   { "lodsB",            { ALr, Xb } },
2603   { "lodsS",            { eAXr, Xv } },
2604   { "scasB",            { AL, Yb } },
2605   { "scasS",            { eAX, Yv } },
2606   /* b0 */
2607   { "movB",             { RMAL, Ib } },
2608   { "movB",             { RMCL, Ib } },
2609   { "movB",             { RMDL, Ib } },
2610   { "movB",             { RMBL, Ib } },
2611   { "movB",             { RMAH, Ib } },
2612   { "movB",             { RMCH, Ib } },
2613   { "movB",             { RMDH, Ib } },
2614   { "movB",             { RMBH, Ib } },
2615   /* b8 */
2616   { "mov%LV",           { RMeAX, Iv64 } },
2617   { "mov%LV",           { RMeCX, Iv64 } },
2618   { "mov%LV",           { RMeDX, Iv64 } },
2619   { "mov%LV",           { RMeBX, Iv64 } },
2620   { "mov%LV",           { RMeSP, Iv64 } },
2621   { "mov%LV",           { RMeBP, Iv64 } },
2622   { "mov%LV",           { RMeSI, Iv64 } },
2623   { "mov%LV",           { RMeDI, Iv64 } },
2624   /* c0 */
2625   { REG_TABLE (REG_C0) },
2626   { REG_TABLE (REG_C1) },
2627   { "retT",             { Iw, BND } },
2628   { "retT",             { BND } },
2629   { X86_64_TABLE (X86_64_C4) },
2630   { X86_64_TABLE (X86_64_C5) },
2631   { REG_TABLE (REG_C6) },
2632   { REG_TABLE (REG_C7) },
2633   /* c8 */
2634   { "enterT",           { Iw, Ib } },
2635   { "leaveT",           { XX } },
2636   { "Jret{|f}P",        { Iw } },
2637   { "Jret{|f}P",        { XX } },
2638   { "int3",             { XX } },
2639   { "int",              { Ib } },
2640   { X86_64_TABLE (X86_64_CE) },
2641   { "iret%LP",          { XX } },
2642   /* d0 */
2643   { REG_TABLE (REG_D0) },
2644   { REG_TABLE (REG_D1) },
2645   { REG_TABLE (REG_D2) },
2646   { REG_TABLE (REG_D3) },
2647   { X86_64_TABLE (X86_64_D4) },
2648   { X86_64_TABLE (X86_64_D5) },
2649   { Bad_Opcode },
2650   { "xlat",             { DSBX } },
2651   /* d8 */
2652   { FLOAT },
2653   { FLOAT },
2654   { FLOAT },
2655   { FLOAT },
2656   { FLOAT },
2657   { FLOAT },
2658   { FLOAT },
2659   { FLOAT },
2660   /* e0 */
2661   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
2662   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
2663   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
2664   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
2665   { "inB",              { AL, Ib } },
2666   { "inG",              { zAX, Ib } },
2667   { "outB",             { Ib, AL } },
2668   { "outG",             { Ib, zAX } },
2669   /* e8 */
2670   { "callT",            { Jv, BND } },
2671   { "jmpT",             { Jv, BND } },
2672   { X86_64_TABLE (X86_64_EA) },
2673   { "jmp",              { Jb, BND } },
2674   { "inB",              { AL, indirDX } },
2675   { "inG",              { zAX, indirDX } },
2676   { "outB",             { indirDX, AL } },
2677   { "outG",             { indirDX, zAX } },
2678   /* f0 */
2679   { Bad_Opcode },       /* lock prefix */
2680   { "icebp",            { XX } },
2681   { Bad_Opcode },       /* repne */
2682   { Bad_Opcode },       /* repz */
2683   { "hlt",              { XX } },
2684   { "cmc",              { XX } },
2685   { REG_TABLE (REG_F6) },
2686   { REG_TABLE (REG_F7) },
2687   /* f8 */
2688   { "clc",              { XX } },
2689   { "stc",              { XX } },
2690   { "cli",              { XX } },
2691   { "sti",              { XX } },
2692   { "cld",              { XX } },
2693   { "std",              { XX } },
2694   { REG_TABLE (REG_FE) },
2695   { REG_TABLE (REG_FF) },
2696 };
2697
2698 static const struct dis386 dis386_twobyte[] = {
2699   /* 00 */
2700   { REG_TABLE (REG_0F00 ) },
2701   { REG_TABLE (REG_0F01 ) },
2702   { "larS",             { Gv, Ew } },
2703   { "lslS",             { Gv, Ew } },
2704   { Bad_Opcode },
2705   { "syscall",          { XX } },
2706   { "clts",             { XX } },
2707   { "sysret%LP",                { XX } },
2708   /* 08 */
2709   { "invd",             { XX } },
2710   { "wbinvd",           { XX } },
2711   { Bad_Opcode },
2712   { "ud2",              { XX } },
2713   { Bad_Opcode },
2714   { REG_TABLE (REG_0F0D) },
2715   { "femms",            { XX } },
2716   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2717   /* 10 */
2718   { PREFIX_TABLE (PREFIX_0F10) },
2719   { PREFIX_TABLE (PREFIX_0F11) },
2720   { PREFIX_TABLE (PREFIX_0F12) },
2721   { MOD_TABLE (MOD_0F13) },
2722   { "unpcklpX",         { XM, EXx } },
2723   { "unpckhpX",         { XM, EXx } },
2724   { PREFIX_TABLE (PREFIX_0F16) },
2725   { MOD_TABLE (MOD_0F17) },
2726   /* 18 */
2727   { REG_TABLE (REG_0F18) },
2728   { "nopQ",             { Ev } },
2729   { PREFIX_TABLE (PREFIX_0F1A) },
2730   { PREFIX_TABLE (PREFIX_0F1B) },
2731   { "nopQ",             { Ev } },
2732   { "nopQ",             { Ev } },
2733   { "nopQ",             { Ev } },
2734   { "nopQ",             { Ev } },
2735   /* 20 */
2736   { "movZ",             { Rm, Cm } },
2737   { "movZ",             { Rm, Dm } },
2738   { "movZ",             { Cm, Rm } },
2739   { "movZ",             { Dm, Rm } },
2740   { MOD_TABLE (MOD_0F24) },
2741   { Bad_Opcode },
2742   { MOD_TABLE (MOD_0F26) },
2743   { Bad_Opcode },
2744   /* 28 */
2745   { "movapX",           { XM, EXx } },
2746   { "movapX",           { EXxS, XM } },
2747   { PREFIX_TABLE (PREFIX_0F2A) },
2748   { PREFIX_TABLE (PREFIX_0F2B) },
2749   { PREFIX_TABLE (PREFIX_0F2C) },
2750   { PREFIX_TABLE (PREFIX_0F2D) },
2751   { PREFIX_TABLE (PREFIX_0F2E) },
2752   { PREFIX_TABLE (PREFIX_0F2F) },
2753   /* 30 */
2754   { "wrmsr",            { XX } },
2755   { "rdtsc",            { XX } },
2756   { "rdmsr",            { XX } },
2757   { "rdpmc",            { XX } },
2758   { "sysenter",         { XX } },
2759   { "sysexit",          { XX } },
2760   { Bad_Opcode },
2761   { "getsec",           { XX } },
2762   /* 38 */
2763   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2764   { Bad_Opcode },
2765   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2766   { Bad_Opcode },
2767   { Bad_Opcode },
2768   { Bad_Opcode },
2769   { Bad_Opcode },
2770   { Bad_Opcode },
2771   /* 40 */
2772   { "cmovoS",           { Gv, Ev } },
2773   { "cmovnoS",          { Gv, Ev } },
2774   { "cmovbS",           { Gv, Ev } },
2775   { "cmovaeS",          { Gv, Ev } },
2776   { "cmoveS",           { Gv, Ev } },
2777   { "cmovneS",          { Gv, Ev } },
2778   { "cmovbeS",          { Gv, Ev } },
2779   { "cmovaS",           { Gv, Ev } },
2780   /* 48 */
2781   { "cmovsS",           { Gv, Ev } },
2782   { "cmovnsS",          { Gv, Ev } },
2783   { "cmovpS",           { Gv, Ev } },
2784   { "cmovnpS",          { Gv, Ev } },
2785   { "cmovlS",           { Gv, Ev } },
2786   { "cmovgeS",          { Gv, Ev } },
2787   { "cmovleS",          { Gv, Ev } },
2788   { "cmovgS",           { Gv, Ev } },
2789   /* 50 */
2790   { MOD_TABLE (MOD_0F51) },
2791   { PREFIX_TABLE (PREFIX_0F51) },
2792   { PREFIX_TABLE (PREFIX_0F52) },
2793   { PREFIX_TABLE (PREFIX_0F53) },
2794   { "andpX",            { XM, EXx } },
2795   { "andnpX",           { XM, EXx } },
2796   { "orpX",             { XM, EXx } },
2797   { "xorpX",            { XM, EXx } },
2798   /* 58 */
2799   { PREFIX_TABLE (PREFIX_0F58) },
2800   { PREFIX_TABLE (PREFIX_0F59) },
2801   { PREFIX_TABLE (PREFIX_0F5A) },
2802   { PREFIX_TABLE (PREFIX_0F5B) },
2803   { PREFIX_TABLE (PREFIX_0F5C) },
2804   { PREFIX_TABLE (PREFIX_0F5D) },
2805   { PREFIX_TABLE (PREFIX_0F5E) },
2806   { PREFIX_TABLE (PREFIX_0F5F) },
2807   /* 60 */
2808   { PREFIX_TABLE (PREFIX_0F60) },
2809   { PREFIX_TABLE (PREFIX_0F61) },
2810   { PREFIX_TABLE (PREFIX_0F62) },
2811   { "packsswb",         { MX, EM } },
2812   { "pcmpgtb",          { MX, EM } },
2813   { "pcmpgtw",          { MX, EM } },
2814   { "pcmpgtd",          { MX, EM } },
2815   { "packuswb",         { MX, EM } },
2816   /* 68 */
2817   { "punpckhbw",        { MX, EM } },
2818   { "punpckhwd",        { MX, EM } },
2819   { "punpckhdq",        { MX, EM } },
2820   { "packssdw",         { MX, EM } },
2821   { PREFIX_TABLE (PREFIX_0F6C) },
2822   { PREFIX_TABLE (PREFIX_0F6D) },
2823   { "movK",             { MX, Edq } },
2824   { PREFIX_TABLE (PREFIX_0F6F) },
2825   /* 70 */
2826   { PREFIX_TABLE (PREFIX_0F70) },
2827   { REG_TABLE (REG_0F71) },
2828   { REG_TABLE (REG_0F72) },
2829   { REG_TABLE (REG_0F73) },
2830   { "pcmpeqb",          { MX, EM } },
2831   { "pcmpeqw",          { MX, EM } },
2832   { "pcmpeqd",          { MX, EM } },
2833   { "emms",             { XX } },
2834   /* 78 */
2835   { PREFIX_TABLE (PREFIX_0F78) },
2836   { PREFIX_TABLE (PREFIX_0F79) },
2837   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2838   { Bad_Opcode },
2839   { PREFIX_TABLE (PREFIX_0F7C) },
2840   { PREFIX_TABLE (PREFIX_0F7D) },
2841   { PREFIX_TABLE (PREFIX_0F7E) },
2842   { PREFIX_TABLE (PREFIX_0F7F) },
2843   /* 80 */
2844   { "joH",              { Jv, BND, cond_jump_flag } },
2845   { "jnoH",             { Jv, BND, cond_jump_flag } },
2846   { "jbH",              { Jv, BND, cond_jump_flag } },
2847   { "jaeH",             { Jv, BND, cond_jump_flag } },
2848   { "jeH",              { Jv, BND, cond_jump_flag } },
2849   { "jneH",             { Jv, BND, cond_jump_flag } },
2850   { "jbeH",             { Jv, BND, cond_jump_flag } },
2851   { "jaH",              { Jv, BND, cond_jump_flag } },
2852   /* 88 */
2853   { "jsH",              { Jv, BND, cond_jump_flag } },
2854   { "jnsH",             { Jv, BND, cond_jump_flag } },
2855   { "jpH",              { Jv, BND, cond_jump_flag } },
2856   { "jnpH",             { Jv, BND, cond_jump_flag } },
2857   { "jlH",              { Jv, BND, cond_jump_flag } },
2858   { "jgeH",             { Jv, BND, cond_jump_flag } },
2859   { "jleH",             { Jv, BND, cond_jump_flag } },
2860   { "jgH",              { Jv, BND, cond_jump_flag } },
2861   /* 90 */
2862   { "seto",             { Eb } },
2863   { "setno",            { Eb } },
2864   { "setb",             { Eb } },
2865   { "setae",            { Eb } },
2866   { "sete",             { Eb } },
2867   { "setne",            { Eb } },
2868   { "setbe",            { Eb } },
2869   { "seta",             { Eb } },
2870   /* 98 */
2871   { "sets",             { Eb } },
2872   { "setns",            { Eb } },
2873   { "setp",             { Eb } },
2874   { "setnp",            { Eb } },
2875   { "setl",             { Eb } },
2876   { "setge",            { Eb } },
2877   { "setle",            { Eb } },
2878   { "setg",             { Eb } },
2879   /* a0 */
2880   { "pushT",            { fs } },
2881   { "popT",             { fs } },
2882   { "cpuid",            { XX } },
2883   { "btS",              { Ev, Gv } },
2884   { "shldS",            { Ev, Gv, Ib } },
2885   { "shldS",            { Ev, Gv, CL } },
2886   { REG_TABLE (REG_0FA6) },
2887   { REG_TABLE (REG_0FA7) },
2888   /* a8 */
2889   { "pushT",            { gs } },
2890   { "popT",             { gs } },
2891   { "rsm",              { XX } },
2892   { "btsS",             { Evh1, Gv } },
2893   { "shrdS",            { Ev, Gv, Ib } },
2894   { "shrdS",            { Ev, Gv, CL } },
2895   { REG_TABLE (REG_0FAE) },
2896   { "imulS",            { Gv, Ev } },
2897   /* b0 */
2898   { "cmpxchgB",         { Ebh1, Gb } },
2899   { "cmpxchgS",         { Evh1, Gv } },
2900   { MOD_TABLE (MOD_0FB2) },
2901   { "btrS",             { Evh1, Gv } },
2902   { MOD_TABLE (MOD_0FB4) },
2903   { MOD_TABLE (MOD_0FB5) },
2904   { "movz{bR|x}",       { Gv, Eb } },
2905   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2906   /* b8 */
2907   { PREFIX_TABLE (PREFIX_0FB8) },
2908   { "ud1",              { XX } },
2909   { REG_TABLE (REG_0FBA) },
2910   { "btcS",             { Evh1, Gv } },
2911   { PREFIX_TABLE (PREFIX_0FBC) },
2912   { PREFIX_TABLE (PREFIX_0FBD) },
2913   { "movs{bR|x}",       { Gv, Eb } },
2914   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2915   /* c0 */
2916   { "xaddB",            { Ebh1, Gb } },
2917   { "xaddS",            { Evh1, Gv } },
2918   { PREFIX_TABLE (PREFIX_0FC2) },
2919   { PREFIX_TABLE (PREFIX_0FC3) },
2920   { "pinsrw",           { MX, Edqw, Ib } },
2921   { "pextrw",           { Gdq, MS, Ib } },
2922   { "shufpX",           { XM, EXx, Ib } },
2923   { REG_TABLE (REG_0FC7) },
2924   /* c8 */
2925   { "bswap",            { RMeAX } },
2926   { "bswap",            { RMeCX } },
2927   { "bswap",            { RMeDX } },
2928   { "bswap",            { RMeBX } },
2929   { "bswap",            { RMeSP } },
2930   { "bswap",            { RMeBP } },
2931   { "bswap",            { RMeSI } },
2932   { "bswap",            { RMeDI } },
2933   /* d0 */
2934   { PREFIX_TABLE (PREFIX_0FD0) },
2935   { "psrlw",            { MX, EM } },
2936   { "psrld",            { MX, EM } },
2937   { "psrlq",            { MX, EM } },
2938   { "paddq",            { MX, EM } },
2939   { "pmullw",           { MX, EM } },
2940   { PREFIX_TABLE (PREFIX_0FD6) },
2941   { MOD_TABLE (MOD_0FD7) },
2942   /* d8 */
2943   { "psubusb",          { MX, EM } },
2944   { "psubusw",          { MX, EM } },
2945   { "pminub",           { MX, EM } },
2946   { "pand",             { MX, EM } },
2947   { "paddusb",          { MX, EM } },
2948   { "paddusw",          { MX, EM } },
2949   { "pmaxub",           { MX, EM } },
2950   { "pandn",            { MX, EM } },
2951   /* e0 */
2952   { "pavgb",            { MX, EM } },
2953   { "psraw",            { MX, EM } },
2954   { "psrad",            { MX, EM } },
2955   { "pavgw",            { MX, EM } },
2956   { "pmulhuw",          { MX, EM } },
2957   { "pmulhw",           { MX, EM } },
2958   { PREFIX_TABLE (PREFIX_0FE6) },
2959   { PREFIX_TABLE (PREFIX_0FE7) },
2960   /* e8 */
2961   { "psubsb",           { MX, EM } },
2962   { "psubsw",           { MX, EM } },
2963   { "pminsw",           { MX, EM } },
2964   { "por",              { MX, EM } },
2965   { "paddsb",           { MX, EM } },
2966   { "paddsw",           { MX, EM } },
2967   { "pmaxsw",           { MX, EM } },
2968   { "pxor",             { MX, EM } },
2969   /* f0 */
2970   { PREFIX_TABLE (PREFIX_0FF0) },
2971   { "psllw",            { MX, EM } },
2972   { "pslld",            { MX, EM } },
2973   { "psllq",            { MX, EM } },
2974   { "pmuludq",          { MX, EM } },
2975   { "pmaddwd",          { MX, EM } },
2976   { "psadbw",           { MX, EM } },
2977   { PREFIX_TABLE (PREFIX_0FF7) },
2978   /* f8 */
2979   { "psubb",            { MX, EM } },
2980   { "psubw",            { MX, EM } },
2981   { "psubd",            { MX, EM } },
2982   { "psubq",            { MX, EM } },
2983   { "paddb",            { MX, EM } },
2984   { "paddw",            { MX, EM } },
2985   { "paddd",            { MX, EM } },
2986   { Bad_Opcode },
2987 };
2988
2989 static const unsigned char onebyte_has_modrm[256] = {
2990   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2991   /*       -------------------------------        */
2992   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2993   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2994   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2995   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2996   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2997   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2998   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2999   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3000   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3001   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3002   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3003   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3004   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3005   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3006   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3007   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3008   /*       -------------------------------        */
3009   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3010 };
3011
3012 static const unsigned char twobyte_has_modrm[256] = {
3013   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3014   /*       -------------------------------        */
3015   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3016   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3017   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3018   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3019   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3020   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3021   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3022   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3023   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3024   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3025   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3026   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3027   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3028   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3029   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3030   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3031   /*       -------------------------------        */
3032   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3033 };
3034
3035 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3036   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3037   /*       -------------------------------        */
3038   /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3039   /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3040   /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3041   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3042   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3043   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3044   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3045   /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3046   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3047   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3048   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3049   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3050   /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3051   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3052   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3053   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3054   /*       -------------------------------        */
3055   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3056 };
3057
3058 static char obuf[100];
3059 static char *obufp;
3060 static char *mnemonicendp;
3061 static char scratchbuf[100];
3062 static unsigned char *start_codep;
3063 static unsigned char *insn_codep;
3064 static unsigned char *codep;
3065 static unsigned char *end_codep;
3066 static int last_lock_prefix;
3067 static int last_repz_prefix;
3068 static int last_repnz_prefix;
3069 static int last_data_prefix;
3070 static int last_addr_prefix;
3071 static int last_rex_prefix;
3072 static int last_seg_prefix;
3073 static int fwait_prefix;
3074 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3075 static int mandatory_prefix;
3076 /* The active segment register prefix.  */
3077 static int active_seg_prefix;
3078 #define MAX_CODE_LENGTH 15
3079 /* We can up to 14 prefixes since the maximum instruction length is
3080    15bytes.  */
3081 static int all_prefixes[MAX_CODE_LENGTH - 1];
3082 static disassemble_info *the_info;
3083 static struct
3084   {
3085     int mod;
3086     int reg;
3087     int rm;
3088   }
3089 modrm;
3090 static unsigned char need_modrm;
3091 static struct
3092   {
3093     int scale;
3094     int index;
3095     int base;
3096   }
3097 sib;
3098 static struct
3099   {
3100     int register_specifier;
3101     int length;
3102     int prefix;
3103     int w;
3104     int evex;
3105     int r;
3106     int v;
3107     int mask_register_specifier;
3108     int zeroing;
3109     int ll;
3110     int b;
3111   }
3112 vex;
3113 static unsigned char need_vex;
3114 static unsigned char need_vex_reg;
3115 static unsigned char vex_w_done;
3116
3117 struct op
3118   {
3119     const char *name;
3120     unsigned int len;
3121   };
3122
3123 /* If we are accessing mod/rm/reg without need_modrm set, then the
3124    values are stale.  Hitting this abort likely indicates that you
3125    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3126 #define MODRM_CHECK  if (!need_modrm) abort ()
3127
3128 static const char **names64;
3129 static const char **names32;
3130 static const char **names16;
3131 static const char **names8;
3132 static const char **names8rex;
3133 static const char **names_seg;
3134 static const char *index64;
3135 static const char *index32;
3136 static const char **index16;
3137 static const char **names_bnd;
3138
3139 static const char *intel_names64[] = {
3140   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3141   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3142 };
3143 static const char *intel_names32[] = {
3144   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3145   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3146 };
3147 static const char *intel_names16[] = {
3148   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3149   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3150 };
3151 static const char *intel_names8[] = {
3152   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3153 };
3154 static const char *intel_names8rex[] = {
3155   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3156   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3157 };
3158 static const char *intel_names_seg[] = {
3159   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3160 };
3161 static const char *intel_index64 = "riz";
3162 static const char *intel_index32 = "eiz";
3163 static const char *intel_index16[] = {
3164   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3165 };
3166
3167 static const char *att_names64[] = {
3168   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3169   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3170 };
3171 static const char *att_names32[] = {
3172   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3173   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3174 };
3175 static const char *att_names16[] = {
3176   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3177   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3178 };
3179 static const char *att_names8[] = {
3180   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3181 };
3182 static const char *att_names8rex[] = {
3183   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3184   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3185 };
3186 static const char *att_names_seg[] = {
3187   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3188 };
3189 static const char *att_index64 = "%riz";
3190 static const char *att_index32 = "%eiz";
3191 static const char *att_index16[] = {
3192   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3193 };
3194
3195 static const char **names_mm;
3196 static const char *intel_names_mm[] = {
3197   "mm0", "mm1", "mm2", "mm3",
3198   "mm4", "mm5", "mm6", "mm7"
3199 };
3200 static const char *att_names_mm[] = {
3201   "%mm0", "%mm1", "%mm2", "%mm3",
3202   "%mm4", "%mm5", "%mm6", "%mm7"
3203 };
3204
3205 static const char *intel_names_bnd[] = {
3206   "bnd0", "bnd1", "bnd2", "bnd3"
3207 };
3208
3209 static const char *att_names_bnd[] = {
3210   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3211 };
3212
3213 static const char **names_xmm;
3214 static const char *intel_names_xmm[] = {
3215   "xmm0", "xmm1", "xmm2", "xmm3",
3216   "xmm4", "xmm5", "xmm6", "xmm7",
3217   "xmm8", "xmm9", "xmm10", "xmm11",
3218   "xmm12", "xmm13", "xmm14", "xmm15",
3219   "xmm16", "xmm17", "xmm18", "xmm19",
3220   "xmm20", "xmm21", "xmm22", "xmm23",
3221   "xmm24", "xmm25", "xmm26", "xmm27",
3222   "xmm28", "xmm29", "xmm30", "xmm31"
3223 };
3224 static const char *att_names_xmm[] = {
3225   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3226   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3227   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3228   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3229   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3230   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3231   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3232   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3233 };
3234
3235 static const char **names_ymm;
3236 static const char *intel_names_ymm[] = {
3237   "ymm0", "ymm1", "ymm2", "ymm3",
3238   "ymm4", "ymm5", "ymm6", "ymm7",
3239   "ymm8", "ymm9", "ymm10", "ymm11",
3240   "ymm12", "ymm13", "ymm14", "ymm15",
3241   "ymm16", "ymm17", "ymm18", "ymm19",
3242   "ymm20", "ymm21", "ymm22", "ymm23",
3243   "ymm24", "ymm25", "ymm26", "ymm27",
3244   "ymm28", "ymm29", "ymm30", "ymm31"
3245 };
3246 static const char *att_names_ymm[] = {
3247   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3248   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3249   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3250   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3251   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3252   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3253   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3254   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3255 };
3256
3257 static const char **names_zmm;
3258 static const char *intel_names_zmm[] = {
3259   "zmm0", "zmm1", "zmm2", "zmm3",
3260   "zmm4", "zmm5", "zmm6", "zmm7",
3261   "zmm8", "zmm9", "zmm10", "zmm11",
3262   "zmm12", "zmm13", "zmm14", "zmm15",
3263   "zmm16", "zmm17", "zmm18", "zmm19",
3264   "zmm20", "zmm21", "zmm22", "zmm23",
3265   "zmm24", "zmm25", "zmm26", "zmm27",
3266   "zmm28", "zmm29", "zmm30", "zmm31"
3267 };
3268 static const char *att_names_zmm[] = {
3269   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3270   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3271   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3272   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3273   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3274   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3275   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3276   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3277 };
3278
3279 static const char **names_mask;
3280 static const char *intel_names_mask[] = {
3281   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3282 };
3283 static const char *att_names_mask[] = {
3284   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3285 };
3286
3287 static const char *names_rounding[] =
3288 {
3289   "{rn-sae}",
3290   "{rd-sae}",
3291   "{ru-sae}",
3292   "{rz-sae}"
3293 };
3294
3295 static const struct dis386 reg_table[][8] = {
3296   /* REG_80 */
3297   {
3298     { "addA",   { Ebh1, Ib } },
3299     { "orA",    { Ebh1, Ib } },
3300     { "adcA",   { Ebh1, Ib } },
3301     { "sbbA",   { Ebh1, Ib } },
3302     { "andA",   { Ebh1, Ib } },
3303     { "subA",   { Ebh1, Ib } },
3304     { "xorA",   { Ebh1, Ib } },
3305     { "cmpA",   { Eb, Ib } },
3306   },
3307   /* REG_81 */
3308   {
3309     { "addQ",   { Evh1, Iv } },
3310     { "orQ",    { Evh1, Iv } },
3311     { "adcQ",   { Evh1, Iv } },
3312     { "sbbQ",   { Evh1, Iv } },
3313     { "andQ",   { Evh1, Iv } },
3314     { "subQ",   { Evh1, Iv } },
3315     { "xorQ",   { Evh1, Iv } },
3316     { "cmpQ",   { Ev, Iv } },
3317   },
3318   /* REG_82 */
3319   {
3320     { "addQ",   { Evh1, sIb } },
3321     { "orQ",    { Evh1, sIb } },
3322     { "adcQ",   { Evh1, sIb } },
3323     { "sbbQ",   { Evh1, sIb } },
3324     { "andQ",   { Evh1, sIb } },
3325     { "subQ",   { Evh1, sIb } },
3326     { "xorQ",   { Evh1, sIb } },
3327     { "cmpQ",   { Ev, sIb } },
3328   },
3329   /* REG_8F */
3330   {
3331     { "popU",   { stackEv } },
3332     { XOP_8F_TABLE (XOP_09) },
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { Bad_Opcode },
3336     { XOP_8F_TABLE (XOP_09) },
3337   },
3338   /* REG_C0 */
3339   {
3340     { "rolA",   { Eb, Ib } },
3341     { "rorA",   { Eb, Ib } },
3342     { "rclA",   { Eb, Ib } },
3343     { "rcrA",   { Eb, Ib } },
3344     { "shlA",   { Eb, Ib } },
3345     { "shrA",   { Eb, Ib } },
3346     { Bad_Opcode },
3347     { "sarA",   { Eb, Ib } },
3348   },
3349   /* REG_C1 */
3350   {
3351     { "rolQ",   { Ev, Ib } },
3352     { "rorQ",   { Ev, Ib } },
3353     { "rclQ",   { Ev, Ib } },
3354     { "rcrQ",   { Ev, Ib } },
3355     { "shlQ",   { Ev, Ib } },
3356     { "shrQ",   { Ev, Ib } },
3357     { Bad_Opcode },
3358     { "sarQ",   { Ev, Ib } },
3359   },
3360   /* REG_C6 */
3361   {
3362     { "movA",   { Ebh3, Ib } },
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { Bad_Opcode },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { MOD_TABLE (MOD_C6_REG_7) },
3370   },
3371   /* REG_C7 */
3372   {
3373     { "movQ",   { Evh3, Iv } },
3374     { Bad_Opcode },
3375     { Bad_Opcode },
3376     { Bad_Opcode },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { MOD_TABLE (MOD_C7_REG_7) },
3381   },
3382   /* REG_D0 */
3383   {
3384     { "rolA",   { Eb, I1 } },
3385     { "rorA",   { Eb, I1 } },
3386     { "rclA",   { Eb, I1 } },
3387     { "rcrA",   { Eb, I1 } },
3388     { "shlA",   { Eb, I1 } },
3389     { "shrA",   { Eb, I1 } },
3390     { Bad_Opcode },
3391     { "sarA",   { Eb, I1 } },
3392   },
3393   /* REG_D1 */
3394   {
3395     { "rolQ",   { Ev, I1 } },
3396     { "rorQ",   { Ev, I1 } },
3397     { "rclQ",   { Ev, I1 } },
3398     { "rcrQ",   { Ev, I1 } },
3399     { "shlQ",   { Ev, I1 } },
3400     { "shrQ",   { Ev, I1 } },
3401     { Bad_Opcode },
3402     { "sarQ",   { Ev, I1 } },
3403   },
3404   /* REG_D2 */
3405   {
3406     { "rolA",   { Eb, CL } },
3407     { "rorA",   { Eb, CL } },
3408     { "rclA",   { Eb, CL } },
3409     { "rcrA",   { Eb, CL } },
3410     { "shlA",   { Eb, CL } },
3411     { "shrA",   { Eb, CL } },
3412     { Bad_Opcode },
3413     { "sarA",   { Eb, CL } },
3414   },
3415   /* REG_D3 */
3416   {
3417     { "rolQ",   { Ev, CL } },
3418     { "rorQ",   { Ev, CL } },
3419     { "rclQ",   { Ev, CL } },
3420     { "rcrQ",   { Ev, CL } },
3421     { "shlQ",   { Ev, CL } },
3422     { "shrQ",   { Ev, CL } },
3423     { Bad_Opcode },
3424     { "sarQ",   { Ev, CL } },
3425   },
3426   /* REG_F6 */
3427   {
3428     { "testA",  { Eb, Ib } },
3429     { Bad_Opcode },
3430     { "notA",   { Ebh1 } },
3431     { "negA",   { Ebh1 } },
3432     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
3433     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
3434     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
3435     { "idivA",  { Eb } },       /* and idiv for consistency.               */
3436   },
3437   /* REG_F7 */
3438   {
3439     { "testQ",  { Ev, Iv } },
3440     { Bad_Opcode },
3441     { "notQ",   { Evh1 } },
3442     { "negQ",   { Evh1 } },
3443     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
3444     { "imulQ",  { Ev } },
3445     { "divQ",   { Ev } },
3446     { "idivQ",  { Ev } },
3447   },
3448   /* REG_FE */
3449   {
3450     { "incA",   { Ebh1 } },
3451     { "decA",   { Ebh1 } },
3452   },
3453   /* REG_FF */
3454   {
3455     { "incQ",   { Evh1 } },
3456     { "decQ",   { Evh1 } },
3457     { "call{T|}", { indirEv, BND } },
3458     { MOD_TABLE (MOD_FF_REG_3) },
3459     { "jmp{T|}", { indirEv, BND } },
3460     { MOD_TABLE (MOD_FF_REG_5) },
3461     { "pushU",  { stackEv } },
3462     { Bad_Opcode },
3463   },
3464   /* REG_0F00 */
3465   {
3466     { "sldtD",  { Sv } },
3467     { "strD",   { Sv } },
3468     { "lldt",   { Ew } },
3469     { "ltr",    { Ew } },
3470     { "verr",   { Ew } },
3471     { "verw",   { Ew } },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474   },
3475   /* REG_0F01 */
3476   {
3477     { MOD_TABLE (MOD_0F01_REG_0) },
3478     { MOD_TABLE (MOD_0F01_REG_1) },
3479     { MOD_TABLE (MOD_0F01_REG_2) },
3480     { MOD_TABLE (MOD_0F01_REG_3) },
3481     { "smswD",  { Sv } },
3482     { Bad_Opcode },
3483     { "lmsw",   { Ew } },
3484     { MOD_TABLE (MOD_0F01_REG_7) },
3485   },
3486   /* REG_0F0D */
3487   {
3488     { "prefetch",       { Mb } },
3489     { "prefetchw",      { Mb } },
3490     { "prefetchwt1",    { Mb } },
3491     { "prefetch",       { Mb } },
3492     { "prefetch",       { Mb } },
3493     { "prefetch",       { Mb } },
3494     { "prefetch",       { Mb } },
3495     { "prefetch",       { Mb } },
3496   },
3497   /* REG_0F18 */
3498   {
3499     { MOD_TABLE (MOD_0F18_REG_0) },
3500     { MOD_TABLE (MOD_0F18_REG_1) },
3501     { MOD_TABLE (MOD_0F18_REG_2) },
3502     { MOD_TABLE (MOD_0F18_REG_3) },
3503     { MOD_TABLE (MOD_0F18_REG_4) },
3504     { MOD_TABLE (MOD_0F18_REG_5) },
3505     { MOD_TABLE (MOD_0F18_REG_6) },
3506     { MOD_TABLE (MOD_0F18_REG_7) },
3507   },
3508   /* REG_0F71 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_0F71_REG_2) },
3513     { Bad_Opcode },
3514     { MOD_TABLE (MOD_0F71_REG_4) },
3515     { Bad_Opcode },
3516     { MOD_TABLE (MOD_0F71_REG_6) },
3517   },
3518   /* REG_0F72 */
3519   {
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { MOD_TABLE (MOD_0F72_REG_2) },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_0F72_REG_4) },
3525     { Bad_Opcode },
3526     { MOD_TABLE (MOD_0F72_REG_6) },
3527   },
3528   /* REG_0F73 */
3529   {
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { MOD_TABLE (MOD_0F73_REG_2) },
3533     { MOD_TABLE (MOD_0F73_REG_3) },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_0F73_REG_6) },
3537     { MOD_TABLE (MOD_0F73_REG_7) },
3538   },
3539   /* REG_0FA6 */
3540   {
3541     { "montmul",        { { OP_0f07, 0 } } },
3542     { "xsha1",          { { OP_0f07, 0 } } },
3543     { "xsha256",        { { OP_0f07, 0 } } },
3544   },
3545   /* REG_0FA7 */
3546   {
3547     { "xstore-rng",     { { OP_0f07, 0 } } },
3548     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
3549     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
3550     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
3551     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
3552     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
3553   },
3554   /* REG_0FAE */
3555   {
3556     { MOD_TABLE (MOD_0FAE_REG_0) },
3557     { MOD_TABLE (MOD_0FAE_REG_1) },
3558     { MOD_TABLE (MOD_0FAE_REG_2) },
3559     { MOD_TABLE (MOD_0FAE_REG_3) },
3560     { MOD_TABLE (MOD_0FAE_REG_4) },
3561     { MOD_TABLE (MOD_0FAE_REG_5) },
3562     { MOD_TABLE (MOD_0FAE_REG_6) },
3563     { MOD_TABLE (MOD_0FAE_REG_7) },
3564   },
3565   /* REG_0FBA */
3566   {
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { Bad_Opcode },
3570     { Bad_Opcode },
3571     { "btQ",    { Ev, Ib } },
3572     { "btsQ",   { Evh1, Ib } },
3573     { "btrQ",   { Evh1, Ib } },
3574     { "btcQ",   { Evh1, Ib } },
3575   },
3576   /* REG_0FC7 */
3577   {
3578     { Bad_Opcode },
3579     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3580     { Bad_Opcode },
3581     { MOD_TABLE (MOD_0FC7_REG_3) },
3582     { MOD_TABLE (MOD_0FC7_REG_4) },
3583     { MOD_TABLE (MOD_0FC7_REG_5) },
3584     { MOD_TABLE (MOD_0FC7_REG_6) },
3585     { MOD_TABLE (MOD_0FC7_REG_7) },
3586   },
3587   /* REG_VEX_0F71 */
3588   {
3589     { Bad_Opcode },
3590     { Bad_Opcode },
3591     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3592     { Bad_Opcode },
3593     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3594     { Bad_Opcode },
3595     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3596   },
3597   /* REG_VEX_0F72 */
3598   {
3599     { Bad_Opcode },
3600     { Bad_Opcode },
3601     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3602     { Bad_Opcode },
3603     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3604     { Bad_Opcode },
3605     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3606   },
3607   /* REG_VEX_0F73 */
3608   {
3609     { Bad_Opcode },
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3612     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3616     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3617   },
3618   /* REG_VEX_0FAE */
3619   {
3620     { Bad_Opcode },
3621     { Bad_Opcode },
3622     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3623     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3624   },
3625   /* REG_VEX_0F38F3 */
3626   {
3627     { Bad_Opcode },
3628     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3629     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3630     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3631   },
3632   /* REG_XOP_LWPCB */
3633   {
3634     { "llwpcb", { { OP_LWPCB_E, 0 } } },
3635     { "slwpcb", { { OP_LWPCB_E, 0 } } },
3636   },
3637   /* REG_XOP_LWP */
3638   {
3639     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3640     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3641   },
3642   /* REG_XOP_TBM_01 */
3643   {
3644     { Bad_Opcode },
3645     { "blcfill",        { { OP_LWP_E, 0 }, Ev } },
3646     { "blsfill",        { { OP_LWP_E, 0 }, Ev } },
3647     { "blcs",   { { OP_LWP_E, 0 }, Ev } },
3648     { "tzmsk",  { { OP_LWP_E, 0 }, Ev } },
3649     { "blcic",  { { OP_LWP_E, 0 }, Ev } },
3650     { "blsic",  { { OP_LWP_E, 0 }, Ev } },
3651     { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3652   },
3653   /* REG_XOP_TBM_02 */
3654   {
3655     { Bad_Opcode },
3656     { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3657     { Bad_Opcode },
3658     { Bad_Opcode },
3659     { Bad_Opcode },
3660     { Bad_Opcode },
3661     { "blci",   { { OP_LWP_E, 0 }, Ev } },
3662   },
3663 #define NEED_REG_TABLE
3664 #include "i386-dis-evex.h"
3665 #undef NEED_REG_TABLE
3666 };
3667
3668 static const struct dis386 prefix_table[][4] = {
3669   /* PREFIX_90 */
3670   {
3671     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3672     { "pause", { XX } },
3673     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3674   },
3675
3676   /* PREFIX_0F10 */
3677   {
3678     { "movups", { XM, EXx } },
3679     { "movss",  { XM, EXd } },
3680     { "movupd", { XM, EXx } },
3681     { "movsd",  { XM, EXq } },
3682   },
3683
3684   /* PREFIX_0F11 */
3685   {
3686     { "movups", { EXxS, XM } },
3687     { "movss",  { EXdS, XM } },
3688     { "movupd", { EXxS, XM } },
3689     { "movsd",  { EXqS, XM } },
3690   },
3691
3692   /* PREFIX_0F12 */
3693   {
3694     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3695     { "movsldup", { XM, EXx } },
3696     { "movlpd", { XM, EXq } },
3697     { "movddup", { XM, EXq } },
3698   },
3699
3700   /* PREFIX_0F16 */
3701   {
3702     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3703     { "movshdup", { XM, EXx } },
3704     { "movhpd", { XM, EXq } },
3705   },
3706
3707   /* PREFIX_0F1A */
3708   {
3709     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3710     { "bndcl",  { Gbnd, Ev_bnd } },
3711     { "bndmov", { Gbnd, Ebnd } },
3712     { "bndcu",  { Gbnd, Ev_bnd } },
3713   },
3714
3715   /* PREFIX_0F1B */
3716   {
3717     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3718     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3719     { "bndmov", { Ebnd, Gbnd } },
3720     { "bndcn",  { Gbnd, Ev_bnd } },
3721   },
3722
3723   /* PREFIX_0F2A */
3724   {
3725     { "cvtpi2ps", { XM, EMCq } },
3726     { "cvtsi2ss%LQ", { XM, Ev } },
3727     { "cvtpi2pd", { XM, EMCq } },
3728     { "cvtsi2sd%LQ", { XM, Ev } },
3729   },
3730
3731   /* PREFIX_0F2B */
3732   {
3733     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3734     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3735     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3736     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3737   },
3738
3739   /* PREFIX_0F2C */
3740   {
3741     { "cvttps2pi", { MXC, EXq } },
3742     { "cvttss2siY", { Gv, EXd } },
3743     { "cvttpd2pi", { MXC, EXx } },
3744     { "cvttsd2siY", { Gv, EXq } },
3745   },
3746
3747   /* PREFIX_0F2D */
3748   {
3749     { "cvtps2pi", { MXC, EXq } },
3750     { "cvtss2siY", { Gv, EXd } },
3751     { "cvtpd2pi", { MXC, EXx } },
3752     { "cvtsd2siY", { Gv, EXq } },
3753   },
3754
3755   /* PREFIX_0F2E */
3756   {
3757     { "ucomiss",{ XM, EXd } },
3758     { Bad_Opcode },
3759     { "ucomisd",{ XM, EXq } },
3760   },
3761
3762   /* PREFIX_0F2F */
3763   {
3764     { "comiss", { XM, EXd } },
3765     { Bad_Opcode },
3766     { "comisd", { XM, EXq } },
3767   },
3768
3769   /* PREFIX_0F51 */
3770   {
3771     { "sqrtps", { XM, EXx } },
3772     { "sqrtss", { XM, EXd } },
3773     { "sqrtpd", { XM, EXx } },
3774     { "sqrtsd", { XM, EXq } },
3775   },
3776
3777   /* PREFIX_0F52 */
3778   {
3779     { "rsqrtps",{ XM, EXx } },
3780     { "rsqrtss",{ XM, EXd } },
3781   },
3782
3783   /* PREFIX_0F53 */
3784   {
3785     { "rcpps",  { XM, EXx } },
3786     { "rcpss",  { XM, EXd } },
3787   },
3788
3789   /* PREFIX_0F58 */
3790   {
3791     { "addps", { XM, EXx } },
3792     { "addss", { XM, EXd } },
3793     { "addpd", { XM, EXx } },
3794     { "addsd", { XM, EXq } },
3795   },
3796
3797   /* PREFIX_0F59 */
3798   {
3799     { "mulps",  { XM, EXx } },
3800     { "mulss",  { XM, EXd } },
3801     { "mulpd",  { XM, EXx } },
3802     { "mulsd",  { XM, EXq } },
3803   },
3804
3805   /* PREFIX_0F5A */
3806   {
3807     { "cvtps2pd", { XM, EXq } },
3808     { "cvtss2sd", { XM, EXd } },
3809     { "cvtpd2ps", { XM, EXx } },
3810     { "cvtsd2ss", { XM, EXq } },
3811   },
3812
3813   /* PREFIX_0F5B */
3814   {
3815     { "cvtdq2ps", { XM, EXx } },
3816     { "cvttps2dq", { XM, EXx } },
3817     { "cvtps2dq", { XM, EXx } },
3818   },
3819
3820   /* PREFIX_0F5C */
3821   {
3822     { "subps",  { XM, EXx } },
3823     { "subss",  { XM, EXd } },
3824     { "subpd",  { XM, EXx } },
3825     { "subsd",  { XM, EXq } },
3826   },
3827
3828   /* PREFIX_0F5D */
3829   {
3830     { "minps",  { XM, EXx } },
3831     { "minss",  { XM, EXd } },
3832     { "minpd",  { XM, EXx } },
3833     { "minsd",  { XM, EXq } },
3834   },
3835
3836   /* PREFIX_0F5E */
3837   {
3838     { "divps",  { XM, EXx } },
3839     { "divss",  { XM, EXd } },
3840     { "divpd",  { XM, EXx } },
3841     { "divsd",  { XM, EXq } },
3842   },
3843
3844   /* PREFIX_0F5F */
3845   {
3846     { "maxps",  { XM, EXx } },
3847     { "maxss",  { XM, EXd } },
3848     { "maxpd",  { XM, EXx } },
3849     { "maxsd",  { XM, EXq } },
3850   },
3851
3852   /* PREFIX_0F60 */
3853   {
3854     { "punpcklbw",{ MX, EMd } },
3855     { Bad_Opcode },
3856     { "punpcklbw",{ MX, EMx } },
3857   },
3858
3859   /* PREFIX_0F61 */
3860   {
3861     { "punpcklwd",{ MX, EMd } },
3862     { Bad_Opcode },
3863     { "punpcklwd",{ MX, EMx } },
3864   },
3865
3866   /* PREFIX_0F62 */
3867   {
3868     { "punpckldq",{ MX, EMd } },
3869     { Bad_Opcode },
3870     { "punpckldq",{ MX, EMx } },
3871   },
3872
3873   /* PREFIX_0F6C */
3874   {
3875     { Bad_Opcode },
3876     { Bad_Opcode },
3877     { "punpcklqdq", { XM, EXx } },
3878   },
3879
3880   /* PREFIX_0F6D */
3881   {
3882     { Bad_Opcode },
3883     { Bad_Opcode },
3884     { "punpckhqdq", { XM, EXx } },
3885   },
3886
3887   /* PREFIX_0F6F */
3888   {
3889     { "movq",   { MX, EM } },
3890     { "movdqu", { XM, EXx } },
3891     { "movdqa", { XM, EXx } },
3892   },
3893
3894   /* PREFIX_0F70 */
3895   {
3896     { "pshufw", { MX, EM, Ib } },
3897     { "pshufhw",{ XM, EXx, Ib } },
3898     { "pshufd", { XM, EXx, Ib } },
3899     { "pshuflw",{ XM, EXx, Ib } },
3900   },
3901
3902   /* PREFIX_0F73_REG_3 */
3903   {
3904     { Bad_Opcode },
3905     { Bad_Opcode },
3906     { "psrldq", { XS, Ib } },
3907   },
3908
3909   /* PREFIX_0F73_REG_7 */
3910   {
3911     { Bad_Opcode },
3912     { Bad_Opcode },
3913     { "pslldq", { XS, Ib } },
3914   },
3915
3916   /* PREFIX_0F78 */
3917   {
3918     {"vmread",  { Em, Gm } },
3919     { Bad_Opcode },
3920     {"extrq",   { XS, Ib, Ib } },
3921     {"insertq", { XM, XS, Ib, Ib } },
3922   },
3923
3924   /* PREFIX_0F79 */
3925   {
3926     {"vmwrite", { Gm, Em } },
3927     { Bad_Opcode },
3928     {"extrq",   { XM, XS } },
3929     {"insertq", { XM, XS } },
3930   },
3931
3932   /* PREFIX_0F7C */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { "haddpd", { XM, EXx } },
3937     { "haddps", { XM, EXx } },
3938   },
3939
3940   /* PREFIX_0F7D */
3941   {
3942     { Bad_Opcode },
3943     { Bad_Opcode },
3944     { "hsubpd", { XM, EXx } },
3945     { "hsubps", { XM, EXx } },
3946   },
3947
3948   /* PREFIX_0F7E */
3949   {
3950     { "movK",   { Edq, MX } },
3951     { "movq",   { XM, EXq } },
3952     { "movK",   { Edq, XM } },
3953   },
3954
3955   /* PREFIX_0F7F */
3956   {
3957     { "movq",   { EMS, MX } },
3958     { "movdqu", { EXxS, XM } },
3959     { "movdqa", { EXxS, XM } },
3960   },
3961
3962   /* PREFIX_0FAE_REG_0 */
3963   {
3964     { Bad_Opcode },
3965     { "rdfsbase", { Ev } },
3966   },
3967
3968   /* PREFIX_0FAE_REG_1 */
3969   {
3970     { Bad_Opcode },
3971     { "rdgsbase", { Ev } },
3972   },
3973
3974   /* PREFIX_0FAE_REG_2 */
3975   {
3976     { Bad_Opcode },
3977     { "wrfsbase", { Ev } },
3978   },
3979
3980   /* PREFIX_0FAE_REG_3 */
3981   {
3982     { Bad_Opcode },
3983     { "wrgsbase", { Ev } },
3984   },
3985
3986   /* PREFIX_0FAE_REG_6 */
3987   {
3988     { "xsaveopt",      { FXSAVE } },
3989     { Bad_Opcode },
3990     { "clwb",   { Mb } },
3991   },
3992
3993   /* PREFIX_0FAE_REG_7 */
3994   {
3995     { "clflush",        { Mb } },
3996     { Bad_Opcode },
3997     { "clflushopt",     { Mb } },
3998   },
3999
4000   /* PREFIX_0FB8 */
4001   {
4002     { Bad_Opcode },
4003     { "popcntS", { Gv, Ev } },
4004   },
4005
4006   /* PREFIX_0FBC */
4007   {
4008     { "bsfS",   { Gv, Ev } },
4009     { "tzcntS", { Gv, Ev } },
4010     { "bsfS",   { Gv, Ev } },
4011   },
4012
4013   /* PREFIX_0FBD */
4014   {
4015     { "bsrS",   { Gv, Ev } },
4016     { "lzcntS", { Gv, Ev } },
4017     { "bsrS",   { Gv, Ev } },
4018   },
4019
4020   /* PREFIX_0FC2 */
4021   {
4022     { "cmpps",  { XM, EXx, CMP } },
4023     { "cmpss",  { XM, EXd, CMP } },
4024     { "cmppd",  { XM, EXx, CMP } },
4025     { "cmpsd",  { XM, EXq, CMP } },
4026   },
4027
4028   /* PREFIX_0FC3 */
4029   {
4030     { "movntiS", { Ma, Gv } },
4031   },
4032
4033   /* PREFIX_0FC7_REG_6 */
4034   {
4035     { "vmptrld",{ Mq } },
4036     { "vmxon",  { Mq } },
4037     { "vmclear",{ Mq } },
4038   },
4039
4040   /* PREFIX_0FD0 */
4041   {
4042     { Bad_Opcode },
4043     { Bad_Opcode },
4044     { "addsubpd", { XM, EXx } },
4045     { "addsubps", { XM, EXx } },
4046   },
4047
4048   /* PREFIX_0FD6 */
4049   {
4050     { Bad_Opcode },
4051     { "movq2dq",{ XM, MS } },
4052     { "movq",   { EXqS, XM } },
4053     { "movdq2q",{ MX, XS } },
4054   },
4055
4056   /* PREFIX_0FE6 */
4057   {
4058     { Bad_Opcode },
4059     { "cvtdq2pd", { XM, EXq } },
4060     { "cvttpd2dq", { XM, EXx } },
4061     { "cvtpd2dq", { XM, EXx } },
4062   },
4063
4064   /* PREFIX_0FE7 */
4065   {
4066     { "movntq", { Mq, MX } },
4067     { Bad_Opcode },
4068     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4069   },
4070
4071   /* PREFIX_0FF0 */
4072   {
4073     { Bad_Opcode },
4074     { Bad_Opcode },
4075     { Bad_Opcode },
4076     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4077   },
4078
4079   /* PREFIX_0FF7 */
4080   {
4081     { "maskmovq", { MX, MS } },
4082     { Bad_Opcode },
4083     { "maskmovdqu", { XM, XS } },
4084   },
4085
4086   /* PREFIX_0F3810 */
4087   {
4088     { Bad_Opcode },
4089     { Bad_Opcode },
4090     { "pblendvb", { XM, EXx, XMM0 } },
4091   },
4092
4093   /* PREFIX_0F3814 */
4094   {
4095     { Bad_Opcode },
4096     { Bad_Opcode },
4097     { "blendvps", { XM, EXx, XMM0 } },
4098   },
4099
4100   /* PREFIX_0F3815 */
4101   {
4102     { Bad_Opcode },
4103     { Bad_Opcode },
4104     { "blendvpd", { XM, EXx, XMM0 } },
4105   },
4106
4107   /* PREFIX_0F3817 */
4108   {
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "ptest",  { XM, EXx } },
4112   },
4113
4114   /* PREFIX_0F3820 */
4115   {
4116     { Bad_Opcode },
4117     { Bad_Opcode },
4118     { "pmovsxbw", { XM, EXq } },
4119   },
4120
4121   /* PREFIX_0F3821 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "pmovsxbd", { XM, EXd } },
4126   },
4127
4128   /* PREFIX_0F3822 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pmovsxbq", { XM, EXw } },
4133   },
4134
4135   /* PREFIX_0F3823 */
4136   {
4137     { Bad_Opcode },
4138     { Bad_Opcode },
4139     { "pmovsxwd", { XM, EXq } },
4140   },
4141
4142   /* PREFIX_0F3824 */
4143   {
4144     { Bad_Opcode },
4145     { Bad_Opcode },
4146     { "pmovsxwq", { XM, EXd } },
4147   },
4148
4149   /* PREFIX_0F3825 */
4150   {
4151     { Bad_Opcode },
4152     { Bad_Opcode },
4153     { "pmovsxdq", { XM, EXq } },
4154   },
4155
4156   /* PREFIX_0F3828 */
4157   {
4158     { Bad_Opcode },
4159     { Bad_Opcode },
4160     { "pmuldq", { XM, EXx } },
4161   },
4162
4163   /* PREFIX_0F3829 */
4164   {
4165     { Bad_Opcode },
4166     { Bad_Opcode },
4167     { "pcmpeqq", { XM, EXx } },
4168   },
4169
4170   /* PREFIX_0F382A */
4171   {
4172     { Bad_Opcode },
4173     { Bad_Opcode },
4174     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4175   },
4176
4177   /* PREFIX_0F382B */
4178   {
4179     { Bad_Opcode },
4180     { Bad_Opcode },
4181     { "packusdw", { XM, EXx } },
4182   },
4183
4184   /* PREFIX_0F3830 */
4185   {
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { "pmovzxbw", { XM, EXq } },
4189   },
4190
4191   /* PREFIX_0F3831 */
4192   {
4193     { Bad_Opcode },
4194     { Bad_Opcode },
4195     { "pmovzxbd", { XM, EXd } },
4196   },
4197
4198   /* PREFIX_0F3832 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pmovzxbq", { XM, EXw } },
4203   },
4204
4205   /* PREFIX_0F3833 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "pmovzxwd", { XM, EXq } },
4210   },
4211
4212   /* PREFIX_0F3834 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "pmovzxwq", { XM, EXd } },
4217   },
4218
4219   /* PREFIX_0F3835 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "pmovzxdq", { XM, EXq } },
4224   },
4225
4226   /* PREFIX_0F3837 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pcmpgtq", { XM, EXx } },
4231   },
4232
4233   /* PREFIX_0F3838 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pminsb", { XM, EXx } },
4238   },
4239
4240   /* PREFIX_0F3839 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pminsd", { XM, EXx } },
4245   },
4246
4247   /* PREFIX_0F383A */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pminuw", { XM, EXx } },
4252   },
4253
4254   /* PREFIX_0F383B */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pminud", { XM, EXx } },
4259   },
4260
4261   /* PREFIX_0F383C */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmaxsb", { XM, EXx } },
4266   },
4267
4268   /* PREFIX_0F383D */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmaxsd", { XM, EXx } },
4273   },
4274
4275   /* PREFIX_0F383E */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pmaxuw", { XM, EXx } },
4280   },
4281
4282   /* PREFIX_0F383F */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { "pmaxud", { XM, EXx } },
4287   },
4288
4289   /* PREFIX_0F3840 */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "pmulld", { XM, EXx } },
4294   },
4295
4296   /* PREFIX_0F3841 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "phminposuw", { XM, EXx } },
4301   },
4302
4303   /* PREFIX_0F3880 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "invept", { Gm, Mo } },
4308   },
4309
4310   /* PREFIX_0F3881 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "invvpid", { Gm, Mo } },
4315   },
4316
4317   /* PREFIX_0F3882 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "invpcid", { Gm, M } },
4322   },
4323
4324   /* PREFIX_0F38C8 */
4325   {
4326     { "sha1nexte", { XM, EXxmm } },
4327   },
4328
4329   /* PREFIX_0F38C9 */
4330   {
4331     { "sha1msg1", { XM, EXxmm } },
4332   },
4333
4334   /* PREFIX_0F38CA */
4335   {
4336     { "sha1msg2", { XM, EXxmm } },
4337   },
4338
4339   /* PREFIX_0F38CB */
4340   {
4341     { "sha256rnds2", { XM, EXxmm, XMM0 } },
4342   },
4343
4344   /* PREFIX_0F38CC */
4345   {
4346     { "sha256msg1", { XM, EXxmm } },
4347   },
4348
4349   /* PREFIX_0F38CD */
4350   {
4351     { "sha256msg2", { XM, EXxmm } },
4352   },
4353
4354   /* PREFIX_0F38DB */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "aesimc", { XM, EXx } },
4359   },
4360
4361   /* PREFIX_0F38DC */
4362   {
4363     { Bad_Opcode },
4364     { Bad_Opcode },
4365     { "aesenc", { XM, EXx } },
4366   },
4367
4368   /* PREFIX_0F38DD */
4369   {
4370     { Bad_Opcode },
4371     { Bad_Opcode },
4372     { "aesenclast", { XM, EXx } },
4373   },
4374
4375   /* PREFIX_0F38DE */
4376   {
4377     { Bad_Opcode },
4378     { Bad_Opcode },
4379     { "aesdec", { XM, EXx } },
4380   },
4381
4382   /* PREFIX_0F38DF */
4383   {
4384     { Bad_Opcode },
4385     { Bad_Opcode },
4386     { "aesdeclast", { XM, EXx } },
4387   },
4388
4389   /* PREFIX_0F38F0 */
4390   {
4391     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4392     { Bad_Opcode },
4393     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4394     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
4395   },
4396
4397   /* PREFIX_0F38F1 */
4398   {
4399     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4400     { Bad_Opcode },
4401     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4402     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
4403   },
4404
4405   /* PREFIX_0F38F6 */
4406   {
4407     { Bad_Opcode },
4408     { "adoxS",  { Gdq, Edq} },
4409     { "adcxS",  { Gdq, Edq} },
4410     { Bad_Opcode },
4411   },
4412
4413   /* PREFIX_0F3A08 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "roundps", { XM, EXx, Ib } },
4418   },
4419
4420   /* PREFIX_0F3A09 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "roundpd", { XM, EXx, Ib } },
4425   },
4426
4427   /* PREFIX_0F3A0A */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "roundss", { XM, EXd, Ib } },
4432   },
4433
4434   /* PREFIX_0F3A0B */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "roundsd", { XM, EXq, Ib } },
4439   },
4440
4441   /* PREFIX_0F3A0C */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "blendps", { XM, EXx, Ib } },
4446   },
4447
4448   /* PREFIX_0F3A0D */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "blendpd", { XM, EXx, Ib } },
4453   },
4454
4455   /* PREFIX_0F3A0E */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pblendw", { XM, EXx, Ib } },
4460   },
4461
4462   /* PREFIX_0F3A14 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pextrb", { Edqb, XM, Ib } },
4467   },
4468
4469   /* PREFIX_0F3A15 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pextrw", { Edqw, XM, Ib } },
4474   },
4475
4476   /* PREFIX_0F3A16 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pextrK", { Edq, XM, Ib } },
4481   },
4482
4483   /* PREFIX_0F3A17 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "extractps", { Edqd, XM, Ib } },
4488   },
4489
4490   /* PREFIX_0F3A20 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pinsrb", { XM, Edqb, Ib } },
4495   },
4496
4497   /* PREFIX_0F3A21 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "insertps", { XM, EXd, Ib } },
4502   },
4503
4504   /* PREFIX_0F3A22 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pinsrK", { XM, Edq, Ib } },
4509   },
4510
4511   /* PREFIX_0F3A40 */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "dpps",   { XM, EXx, Ib } },
4516   },
4517
4518   /* PREFIX_0F3A41 */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "dppd",   { XM, EXx, Ib } },
4523   },
4524
4525   /* PREFIX_0F3A42 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "mpsadbw", { XM, EXx, Ib } },
4530   },
4531
4532   /* PREFIX_0F3A44 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pclmulqdq", { XM, EXx, PCLMUL } },
4537   },
4538
4539   /* PREFIX_0F3A60 */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pcmpestrm", { XM, EXx, Ib } },
4544   },
4545
4546   /* PREFIX_0F3A61 */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pcmpestri", { XM, EXx, Ib } },
4551   },
4552
4553   /* PREFIX_0F3A62 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pcmpistrm", { XM, EXx, Ib } },
4558   },
4559
4560   /* PREFIX_0F3A63 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "pcmpistri", { XM, EXx, Ib } },
4565   },
4566
4567   /* PREFIX_0F3ACC */
4568   {
4569     { "sha1rnds4", { XM, EXxmm, Ib } },
4570   },
4571
4572   /* PREFIX_0F3ADF */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "aeskeygenassist", { XM, EXx, Ib } },
4577   },
4578
4579   /* PREFIX_VEX_0F10 */
4580   {
4581     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4582     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4583     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4584     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4585   },
4586
4587   /* PREFIX_VEX_0F11 */
4588   {
4589     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4590     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4591     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4592     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4593   },
4594
4595   /* PREFIX_VEX_0F12 */
4596   {
4597     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4598     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4599     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4600     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4601   },
4602
4603   /* PREFIX_VEX_0F16 */
4604   {
4605     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4606     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4607     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4608   },
4609
4610   /* PREFIX_VEX_0F2A */
4611   {
4612     { Bad_Opcode },
4613     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4616   },
4617
4618   /* PREFIX_VEX_0F2C */
4619   {
4620     { Bad_Opcode },
4621     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4622     { Bad_Opcode },
4623     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4624   },
4625
4626   /* PREFIX_VEX_0F2D */
4627   {
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4630     { Bad_Opcode },
4631     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4632   },
4633
4634   /* PREFIX_VEX_0F2E */
4635   {
4636     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4639   },
4640
4641   /* PREFIX_VEX_0F2F */
4642   {
4643     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4644     { Bad_Opcode },
4645     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4646   },
4647
4648   /* PREFIX_VEX_0F41 */
4649   {
4650     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4651     { Bad_Opcode },
4652     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4653   },
4654
4655   /* PREFIX_VEX_0F42 */
4656   {
4657     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4658     { Bad_Opcode },
4659     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4660   },
4661
4662   /* PREFIX_VEX_0F44 */
4663   {
4664     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4665     { Bad_Opcode },
4666     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4667   },
4668
4669   /* PREFIX_VEX_0F45 */
4670   {
4671     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4672     { Bad_Opcode },
4673     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4674   },
4675
4676   /* PREFIX_VEX_0F46 */
4677   {
4678     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4679     { Bad_Opcode },
4680     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4681   },
4682
4683   /* PREFIX_VEX_0F47 */
4684   {
4685     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4686     { Bad_Opcode },
4687     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4688   },
4689
4690   /* PREFIX_VEX_0F4A */
4691   {
4692     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4693     { Bad_Opcode },
4694     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4695   },
4696
4697   /* PREFIX_VEX_0F4B */
4698   {
4699     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4700     { Bad_Opcode },
4701     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4702   },
4703
4704   /* PREFIX_VEX_0F51 */
4705   {
4706     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4707     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4708     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4709     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4710   },
4711
4712   /* PREFIX_VEX_0F52 */
4713   {
4714     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4715     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4716   },
4717
4718   /* PREFIX_VEX_0F53 */
4719   {
4720     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4721     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4722   },
4723
4724   /* PREFIX_VEX_0F58 */
4725   {
4726     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4727     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4728     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4729     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4730   },
4731
4732   /* PREFIX_VEX_0F59 */
4733   {
4734     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4735     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4736     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4737     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4738   },
4739
4740   /* PREFIX_VEX_0F5A */
4741   {
4742     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4743     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4744     { "vcvtpd2ps%XY", { XMM, EXx } },
4745     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4746   },
4747
4748   /* PREFIX_VEX_0F5B */
4749   {
4750     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4751     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4752     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4753   },
4754
4755   /* PREFIX_VEX_0F5C */
4756   {
4757     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4758     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4759     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4760     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4761   },
4762
4763   /* PREFIX_VEX_0F5D */
4764   {
4765     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4766     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4767     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4769   },
4770
4771   /* PREFIX_VEX_0F5E */
4772   {
4773     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4774     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4775     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4776     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4777   },
4778
4779   /* PREFIX_VEX_0F5F */
4780   {
4781     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4782     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4783     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4784     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4785   },
4786
4787   /* PREFIX_VEX_0F60 */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4792   },
4793
4794   /* PREFIX_VEX_0F61 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4799   },
4800
4801   /* PREFIX_VEX_0F62 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4806   },
4807
4808   /* PREFIX_VEX_0F63 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4813   },
4814
4815   /* PREFIX_VEX_0F64 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4820   },
4821
4822   /* PREFIX_VEX_0F65 */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4827   },
4828
4829   /* PREFIX_VEX_0F66 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4834   },
4835
4836   /* PREFIX_VEX_0F67 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4841   },
4842
4843   /* PREFIX_VEX_0F68 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4848   },
4849
4850   /* PREFIX_VEX_0F69 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4855   },
4856
4857   /* PREFIX_VEX_0F6A */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4862   },
4863
4864   /* PREFIX_VEX_0F6B */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_0F6C */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4876   },
4877
4878   /* PREFIX_VEX_0F6D */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_0F6E */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_0F6F */
4893   {
4894     { Bad_Opcode },
4895     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4896     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_0F70 */
4900   {
4901     { Bad_Opcode },
4902     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4903     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4904     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4905   },
4906
4907   /* PREFIX_VEX_0F71_REG_2 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F71_REG_4 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4919   },
4920
4921   /* PREFIX_VEX_0F71_REG_6 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4926   },
4927
4928   /* PREFIX_VEX_0F72_REG_2 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F72_REG_4 */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4940   },
4941
4942   /* PREFIX_VEX_0F72_REG_6 */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4947   },
4948
4949   /* PREFIX_VEX_0F73_REG_2 */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4954   },
4955
4956   /* PREFIX_VEX_0F73_REG_3 */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4961   },
4962
4963   /* PREFIX_VEX_0F73_REG_6 */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F73_REG_7 */
4971   {
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4975   },
4976
4977   /* PREFIX_VEX_0F74 */
4978   {
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { VEX_W_TABLE (VEX_W_0F74_P_2) },
4982   },
4983
4984   /* PREFIX_VEX_0F75 */
4985   {
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { VEX_W_TABLE (VEX_W_0F75_P_2) },
4989   },
4990
4991   /* PREFIX_VEX_0F76 */
4992   {
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { VEX_W_TABLE (VEX_W_0F76_P_2) },
4996   },
4997
4998   /* PREFIX_VEX_0F77 */
4999   {
5000     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5001   },
5002
5003   /* PREFIX_VEX_0F7C */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5008     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5009   },
5010
5011   /* PREFIX_VEX_0F7D */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5016     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F7E */
5020   {
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5023     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_0F7F */
5027   {
5028     { Bad_Opcode },
5029     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5030     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_0F90 */
5034   {
5035     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5036     { Bad_Opcode },
5037     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5038   },
5039
5040   /* PREFIX_VEX_0F91 */
5041   {
5042     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5043     { Bad_Opcode },
5044     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5045   },
5046
5047   /* PREFIX_VEX_0F92 */
5048   {
5049     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5050     { Bad_Opcode },
5051     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5052     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5053   },
5054
5055   /* PREFIX_VEX_0F93 */
5056   {
5057     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5058     { Bad_Opcode },
5059     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5060     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5061   },
5062
5063   /* PREFIX_VEX_0F98 */
5064   {
5065     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5066     { Bad_Opcode },
5067     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5068   },
5069
5070   /* PREFIX_VEX_0F99 */
5071   {
5072     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5073     { Bad_Opcode },
5074     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5075   },
5076
5077   /* PREFIX_VEX_0FC2 */
5078   {
5079     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5080     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5081     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5082     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5083   },
5084
5085   /* PREFIX_VEX_0FC4 */
5086   {
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5090   },
5091
5092   /* PREFIX_VEX_0FC5 */
5093   {
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5097   },
5098
5099   /* PREFIX_VEX_0FD0 */
5100   {
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5104     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5105   },
5106
5107   /* PREFIX_VEX_0FD1 */
5108   {
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5112   },
5113
5114   /* PREFIX_VEX_0FD2 */
5115   {
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0FD3 */
5122   {
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5126   },
5127
5128   /* PREFIX_VEX_0FD4 */
5129   {
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0FD5 */
5136   {
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0FD6 */
5143   {
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5147   },
5148
5149   /* PREFIX_VEX_0FD7 */
5150   {
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5154   },
5155
5156   /* PREFIX_VEX_0FD8 */
5157   {
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5161   },
5162
5163   /* PREFIX_VEX_0FD9 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0FDA */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0FDB */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5182   },
5183
5184   /* PREFIX_VEX_0FDC */
5185   {
5186     { Bad_Opcode },
5187     { Bad_Opcode },
5188     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5189   },
5190
5191   /* PREFIX_VEX_0FDD */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5196   },
5197
5198   /* PREFIX_VEX_0FDE */
5199   {
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5203   },
5204
5205   /* PREFIX_VEX_0FDF */
5206   {
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5210   },
5211
5212   /* PREFIX_VEX_0FE0 */
5213   {
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5217   },
5218
5219   /* PREFIX_VEX_0FE1 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0FE2 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0FE3 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0FE4 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FE5 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0FE6 */
5255   {
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5258     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5259     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5260   },
5261
5262   /* PREFIX_VEX_0FE7 */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5267   },
5268
5269   /* PREFIX_VEX_0FE8 */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5274   },
5275
5276   /* PREFIX_VEX_0FE9 */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5281   },
5282
5283   /* PREFIX_VEX_0FEA */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5288   },
5289
5290   /* PREFIX_VEX_0FEB */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5295   },
5296
5297   /* PREFIX_VEX_0FEC */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5302   },
5303
5304   /* PREFIX_VEX_0FED */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5309   },
5310
5311   /* PREFIX_VEX_0FEE */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5316   },
5317
5318   /* PREFIX_VEX_0FEF */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5323   },
5324
5325   /* PREFIX_VEX_0FF0 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5331   },
5332
5333   /* PREFIX_VEX_0FF1 */
5334   {
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5338   },
5339
5340   /* PREFIX_VEX_0FF2 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5345   },
5346
5347   /* PREFIX_VEX_0FF3 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5352   },
5353
5354   /* PREFIX_VEX_0FF4 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5359   },
5360
5361   /* PREFIX_VEX_0FF5 */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5366   },
5367
5368   /* PREFIX_VEX_0FF6 */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5373   },
5374
5375   /* PREFIX_VEX_0FF7 */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5380   },
5381
5382   /* PREFIX_VEX_0FF8 */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5387   },
5388
5389   /* PREFIX_VEX_0FF9 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FFA */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FFB */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5408   },
5409
5410   /* PREFIX_VEX_0FFC */
5411   {
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5415   },
5416
5417   /* PREFIX_VEX_0FFD */
5418   {
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5422   },
5423
5424   /* PREFIX_VEX_0FFE */
5425   {
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5429   },
5430
5431   /* PREFIX_VEX_0F3800 */
5432   {
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5436   },
5437
5438   /* PREFIX_VEX_0F3801 */
5439   {
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5443   },
5444
5445   /* PREFIX_VEX_0F3802 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0F3803 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0F3804 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0F3805 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0F3806 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0F3807 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0F3808 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0F3809 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0F380A */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0F380B */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0F380C */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0F380D */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0F380E */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5534   },
5535
5536   /* PREFIX_VEX_0F380F */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5541   },
5542
5543   /* PREFIX_VEX_0F3813 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { "vcvtph2ps", { XM, EXxmmq } },
5548   },
5549
5550   /* PREFIX_VEX_0F3816 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5555   },
5556
5557   /* PREFIX_VEX_0F3817 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0F3818 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0F3819 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F381A */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F381C */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F381D */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F381E */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F3820 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F3821 */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F3822 */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F3823 */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F3824 */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F3825 */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F3828 */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F3829 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5660   },
5661
5662   /* PREFIX_VEX_0F382A */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F382B */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F382C */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5681   },
5682
5683   /* PREFIX_VEX_0F382D */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5688   },
5689
5690   /* PREFIX_VEX_0F382E */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5695   },
5696
5697   /* PREFIX_VEX_0F382F */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5702   },
5703
5704   /* PREFIX_VEX_0F3830 */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5709   },
5710
5711   /* PREFIX_VEX_0F3831 */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5716   },
5717
5718   /* PREFIX_VEX_0F3832 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F3833 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F3834 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F3835 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F3836 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F3837 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F3838 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F3839 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F383A */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F383B */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F383C */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F383D */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F383E */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F383F */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F3840 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3841 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5828   },
5829
5830   /* PREFIX_VEX_0F3845 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { "vpsrlv%LW", { XM, Vex, EXx } },
5835   },
5836
5837   /* PREFIX_VEX_0F3846 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F3847 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { "vpsllv%LW", { XM, Vex, EXx } },
5849   },
5850
5851   /* PREFIX_VEX_0F3858 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5856   },
5857
5858   /* PREFIX_VEX_0F3859 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5863   },
5864
5865   /* PREFIX_VEX_0F385A */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5870   },
5871
5872   /* PREFIX_VEX_0F3878 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F3879 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F388C */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F388E */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F3890 */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5905   },
5906
5907   /* PREFIX_VEX_0F3891 */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5912   },
5913
5914   /* PREFIX_VEX_0F3892 */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5919   },
5920
5921   /* PREFIX_VEX_0F3893 */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5926   },
5927
5928   /* PREFIX_VEX_0F3896 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5933   },
5934
5935   /* PREFIX_VEX_0F3897 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5940   },
5941
5942   /* PREFIX_VEX_0F3898 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { "vfmadd132p%XW", { XM, Vex, EXx } },
5947   },
5948
5949   /* PREFIX_VEX_0F3899 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5954   },
5955
5956   /* PREFIX_VEX_0F389A */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vfmsub132p%XW", { XM, Vex, EXx } },
5961   },
5962
5963   /* PREFIX_VEX_0F389B */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5968   },
5969
5970   /* PREFIX_VEX_0F389C */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { "vfnmadd132p%XW", { XM, Vex, EXx } },
5975   },
5976
5977   /* PREFIX_VEX_0F389D */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5982   },
5983
5984   /* PREFIX_VEX_0F389E */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { "vfnmsub132p%XW", { XM, Vex, EXx } },
5989   },
5990
5991   /* PREFIX_VEX_0F389F */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5996   },
5997
5998   /* PREFIX_VEX_0F38A6 */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6003     { Bad_Opcode },
6004   },
6005
6006   /* PREFIX_VEX_0F38A7 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6011   },
6012
6013   /* PREFIX_VEX_0F38A8 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmadd213p%XW", { XM, Vex, EXx } },
6018   },
6019
6020   /* PREFIX_VEX_0F38A9 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6025   },
6026
6027   /* PREFIX_VEX_0F38AA */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmsub213p%XW", { XM, Vex, EXx } },
6032   },
6033
6034   /* PREFIX_VEX_0F38AB */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6039   },
6040
6041   /* PREFIX_VEX_0F38AC */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfnmadd213p%XW", { XM, Vex, EXx } },
6046   },
6047
6048   /* PREFIX_VEX_0F38AD */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6053   },
6054
6055   /* PREFIX_VEX_0F38AE */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfnmsub213p%XW", { XM, Vex, EXx } },
6060   },
6061
6062   /* PREFIX_VEX_0F38AF */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6067   },
6068
6069   /* PREFIX_VEX_0F38B6 */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6074   },
6075
6076   /* PREFIX_VEX_0F38B7 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6081   },
6082
6083   /* PREFIX_VEX_0F38B8 */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfmadd231p%XW", { XM, Vex, EXx } },
6088   },
6089
6090   /* PREFIX_VEX_0F38B9 */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6095   },
6096
6097   /* PREFIX_VEX_0F38BA */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmsub231p%XW", { XM, Vex, EXx } },
6102   },
6103
6104   /* PREFIX_VEX_0F38BB */
6105   {
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6109   },
6110
6111   /* PREFIX_VEX_0F38BC */
6112   {
6113     { Bad_Opcode },
6114     { Bad_Opcode },
6115     { "vfnmadd231p%XW", { XM, Vex, EXx } },
6116   },
6117
6118   /* PREFIX_VEX_0F38BD */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6123   },
6124
6125   /* PREFIX_VEX_0F38BE */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfnmsub231p%XW", { XM, Vex, EXx } },
6130   },
6131
6132   /* PREFIX_VEX_0F38BF */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6137   },
6138
6139   /* PREFIX_VEX_0F38DB */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6144   },
6145
6146   /* PREFIX_VEX_0F38DC */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6151   },
6152
6153   /* PREFIX_VEX_0F38DD */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6158   },
6159
6160   /* PREFIX_VEX_0F38DE */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6165   },
6166
6167   /* PREFIX_VEX_0F38DF */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6172   },
6173
6174   /* PREFIX_VEX_0F38F2 */
6175   {
6176     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6177   },
6178
6179   /* PREFIX_VEX_0F38F3_REG_1 */
6180   {
6181     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6182   },
6183
6184   /* PREFIX_VEX_0F38F3_REG_2 */
6185   {
6186     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6187   },
6188
6189   /* PREFIX_VEX_0F38F3_REG_3 */
6190   {
6191     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6192   },
6193
6194   /* PREFIX_VEX_0F38F5 */
6195   {
6196     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6197     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6198     { Bad_Opcode },
6199     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6200   },
6201
6202   /* PREFIX_VEX_0F38F6 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6208   },
6209
6210   /* PREFIX_VEX_0F38F7 */
6211   {
6212     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6213     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6214     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6215     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6216   },
6217
6218   /* PREFIX_VEX_0F3A00 */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6223   },
6224
6225   /* PREFIX_VEX_0F3A01 */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6230   },
6231
6232   /* PREFIX_VEX_0F3A02 */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6237   },
6238
6239   /* PREFIX_VEX_0F3A04 */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6244   },
6245
6246   /* PREFIX_VEX_0F3A05 */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6251   },
6252
6253   /* PREFIX_VEX_0F3A06 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6258   },
6259
6260   /* PREFIX_VEX_0F3A08 */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6265   },
6266
6267   /* PREFIX_VEX_0F3A09 */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6272   },
6273
6274   /* PREFIX_VEX_0F3A0A */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6279   },
6280
6281   /* PREFIX_VEX_0F3A0B */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6286   },
6287
6288   /* PREFIX_VEX_0F3A0C */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6293   },
6294
6295   /* PREFIX_VEX_0F3A0D */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6300   },
6301
6302   /* PREFIX_VEX_0F3A0E */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6307   },
6308
6309   /* PREFIX_VEX_0F3A0F */
6310   {
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6314   },
6315
6316   /* PREFIX_VEX_0F3A14 */
6317   {
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6321   },
6322
6323   /* PREFIX_VEX_0F3A15 */
6324   {
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A16 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A17 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A18 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A19 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A1D */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { "vcvtps2ph", { EXxmmq, XM, Ib } },
6363   },
6364
6365   /* PREFIX_VEX_0F3A20 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F3A21 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F3A22 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A30 */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A31 */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A32 */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A33 */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A38 */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A39 */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A40 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A41 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A42 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A44 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A46 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A48 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A49 */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6475   },
6476
6477   /* PREFIX_VEX_0F3A4A */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A4B */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A4C */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A5C */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6503   },
6504
6505   /* PREFIX_VEX_0F3A5D */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6510   },
6511
6512   /* PREFIX_VEX_0F3A5E */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6517   },
6518
6519   /* PREFIX_VEX_0F3A5F */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524   },
6525
6526   /* PREFIX_VEX_0F3A60 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6531     { Bad_Opcode },
6532   },
6533
6534   /* PREFIX_VEX_0F3A61 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6539   },
6540
6541   /* PREFIX_VEX_0F3A62 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A63 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A68 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6560   },
6561
6562   /* PREFIX_VEX_0F3A69 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6567   },
6568
6569   /* PREFIX_VEX_0F3A6A */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A6B */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A6C */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6588   },
6589
6590   /* PREFIX_VEX_0F3A6D */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6595   },
6596
6597   /* PREFIX_VEX_0F3A6E */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A6F */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6609   },
6610
6611   /* PREFIX_VEX_0F3A78 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6616   },
6617
6618   /* PREFIX_VEX_0F3A79 */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6623   },
6624
6625   /* PREFIX_VEX_0F3A7A */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6630   },
6631
6632   /* PREFIX_VEX_0F3A7B */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6637   },
6638
6639   /* PREFIX_VEX_0F3A7C */
6640   {
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6644     { Bad_Opcode },
6645   },
6646
6647   /* PREFIX_VEX_0F3A7D */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6652   },
6653
6654   /* PREFIX_VEX_0F3A7E */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A7F */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3ADF */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6673   },
6674
6675   /* PREFIX_VEX_0F3AF0 */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6681   },
6682
6683 #define NEED_PREFIX_TABLE
6684 #include "i386-dis-evex.h"
6685 #undef NEED_PREFIX_TABLE
6686 };
6687
6688 static const struct dis386 x86_64_table[][2] = {
6689   /* X86_64_06 */
6690   {
6691     { "pushP", { es } },
6692   },
6693
6694   /* X86_64_07 */
6695   {
6696     { "popP", { es } },
6697   },
6698
6699   /* X86_64_0D */
6700   {
6701     { "pushP", { cs } },
6702   },
6703
6704   /* X86_64_16 */
6705   {
6706     { "pushP", { ss } },
6707   },
6708
6709   /* X86_64_17 */
6710   {
6711     { "popP", { ss } },
6712   },
6713
6714   /* X86_64_1E */
6715   {
6716     { "pushP", { ds } },
6717   },
6718
6719   /* X86_64_1F */
6720   {
6721     { "popP", { ds } },
6722   },
6723
6724   /* X86_64_27 */
6725   {
6726     { "daa", { XX } },
6727   },
6728
6729   /* X86_64_2F */
6730   {
6731     { "das", { XX } },
6732   },
6733
6734   /* X86_64_37 */
6735   {
6736     { "aaa", { XX } },
6737   },
6738
6739   /* X86_64_3F */
6740   {
6741     { "aas", { XX } },
6742   },
6743
6744   /* X86_64_60 */
6745   {
6746     { "pushaP", { XX } },
6747   },
6748
6749   /* X86_64_61 */
6750   {
6751     { "popaP", { XX } },
6752   },
6753
6754   /* X86_64_62 */
6755   {
6756     { MOD_TABLE (MOD_62_32BIT) },
6757     { EVEX_TABLE (EVEX_0F) },
6758   },
6759
6760   /* X86_64_63 */
6761   {
6762     { "arpl", { Ew, Gw } },
6763     { "movs{lq|xd}", { Gv, Ed } },
6764   },
6765
6766   /* X86_64_6D */
6767   {
6768     { "ins{R|}", { Yzr, indirDX } },
6769     { "ins{G|}", { Yzr, indirDX } },
6770   },
6771
6772   /* X86_64_6F */
6773   {
6774     { "outs{R|}", { indirDXr, Xz } },
6775     { "outs{G|}", { indirDXr, Xz } },
6776   },
6777
6778   /* X86_64_9A */
6779   {
6780     { "Jcall{T|}", { Ap } },
6781   },
6782
6783   /* X86_64_C4 */
6784   {
6785     { MOD_TABLE (MOD_C4_32BIT) },
6786     { VEX_C4_TABLE (VEX_0F) },
6787   },
6788
6789   /* X86_64_C5 */
6790   {
6791     { MOD_TABLE (MOD_C5_32BIT) },
6792     { VEX_C5_TABLE (VEX_0F) },
6793   },
6794
6795   /* X86_64_CE */
6796   {
6797     { "into", { XX } },
6798   },
6799
6800   /* X86_64_D4 */
6801   {
6802     { "aam", { Ib } },
6803   },
6804
6805   /* X86_64_D5 */
6806   {
6807     { "aad", { Ib } },
6808   },
6809
6810   /* X86_64_EA */
6811   {
6812     { "Jjmp{T|}", { Ap } },
6813   },
6814
6815   /* X86_64_0F01_REG_0 */
6816   {
6817     { "sgdt{Q|IQ}", { M } },
6818     { "sgdt", { M } },
6819   },
6820
6821   /* X86_64_0F01_REG_1 */
6822   {
6823     { "sidt{Q|IQ}", { M } },
6824     { "sidt", { M } },
6825   },
6826
6827   /* X86_64_0F01_REG_2 */
6828   {
6829     { "lgdt{Q|Q}", { M } },
6830     { "lgdt", { M } },
6831   },
6832
6833   /* X86_64_0F01_REG_3 */
6834   {
6835     { "lidt{Q|Q}", { M } },
6836     { "lidt", { M } },
6837   },
6838 };
6839
6840 static const struct dis386 three_byte_table[][256] = {
6841
6842   /* THREE_BYTE_0F38 */
6843   {
6844     /* 00 */
6845     { "pshufb",         { MX, EM } },
6846     { "phaddw",         { MX, EM } },
6847     { "phaddd",         { MX, EM } },
6848     { "phaddsw",        { MX, EM } },
6849     { "pmaddubsw",      { MX, EM } },
6850     { "phsubw",         { MX, EM } },
6851     { "phsubd",         { MX, EM } },
6852     { "phsubsw",        { MX, EM } },
6853     /* 08 */
6854     { "psignb",         { MX, EM } },
6855     { "psignw",         { MX, EM } },
6856     { "psignd",         { MX, EM } },
6857     { "pmulhrsw",       { MX, EM } },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     /* 10 */
6863     { PREFIX_TABLE (PREFIX_0F3810) },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { PREFIX_TABLE (PREFIX_0F3814) },
6868     { PREFIX_TABLE (PREFIX_0F3815) },
6869     { Bad_Opcode },
6870     { PREFIX_TABLE (PREFIX_0F3817) },
6871     /* 18 */
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { "pabsb",          { MX, EM } },
6877     { "pabsw",          { MX, EM } },
6878     { "pabsd",          { MX, EM } },
6879     { Bad_Opcode },
6880     /* 20 */
6881     { PREFIX_TABLE (PREFIX_0F3820) },
6882     { PREFIX_TABLE (PREFIX_0F3821) },
6883     { PREFIX_TABLE (PREFIX_0F3822) },
6884     { PREFIX_TABLE (PREFIX_0F3823) },
6885     { PREFIX_TABLE (PREFIX_0F3824) },
6886     { PREFIX_TABLE (PREFIX_0F3825) },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 28 */
6890     { PREFIX_TABLE (PREFIX_0F3828) },
6891     { PREFIX_TABLE (PREFIX_0F3829) },
6892     { PREFIX_TABLE (PREFIX_0F382A) },
6893     { PREFIX_TABLE (PREFIX_0F382B) },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 30 */
6899     { PREFIX_TABLE (PREFIX_0F3830) },
6900     { PREFIX_TABLE (PREFIX_0F3831) },
6901     { PREFIX_TABLE (PREFIX_0F3832) },
6902     { PREFIX_TABLE (PREFIX_0F3833) },
6903     { PREFIX_TABLE (PREFIX_0F3834) },
6904     { PREFIX_TABLE (PREFIX_0F3835) },
6905     { Bad_Opcode },
6906     { PREFIX_TABLE (PREFIX_0F3837) },
6907     /* 38 */
6908     { PREFIX_TABLE (PREFIX_0F3838) },
6909     { PREFIX_TABLE (PREFIX_0F3839) },
6910     { PREFIX_TABLE (PREFIX_0F383A) },
6911     { PREFIX_TABLE (PREFIX_0F383B) },
6912     { PREFIX_TABLE (PREFIX_0F383C) },
6913     { PREFIX_TABLE (PREFIX_0F383D) },
6914     { PREFIX_TABLE (PREFIX_0F383E) },
6915     { PREFIX_TABLE (PREFIX_0F383F) },
6916     /* 40 */
6917     { PREFIX_TABLE (PREFIX_0F3840) },
6918     { PREFIX_TABLE (PREFIX_0F3841) },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 48 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 50 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 58 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 60 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 68 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 70 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 78 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 80 */
6989     { PREFIX_TABLE (PREFIX_0F3880) },
6990     { PREFIX_TABLE (PREFIX_0F3881) },
6991     { PREFIX_TABLE (PREFIX_0F3882) },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 88 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 90 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 98 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* a0 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* a8 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* b0 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* b8 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* c0 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* c8 */
7070     { PREFIX_TABLE (PREFIX_0F38C8) },
7071     { PREFIX_TABLE (PREFIX_0F38C9) },
7072     { PREFIX_TABLE (PREFIX_0F38CA) },
7073     { PREFIX_TABLE (PREFIX_0F38CB) },
7074     { PREFIX_TABLE (PREFIX_0F38CC) },
7075     { PREFIX_TABLE (PREFIX_0F38CD) },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* d0 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* d8 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { PREFIX_TABLE (PREFIX_0F38DB) },
7092     { PREFIX_TABLE (PREFIX_0F38DC) },
7093     { PREFIX_TABLE (PREFIX_0F38DD) },
7094     { PREFIX_TABLE (PREFIX_0F38DE) },
7095     { PREFIX_TABLE (PREFIX_0F38DF) },
7096     /* e0 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* e8 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* f0 */
7115     { PREFIX_TABLE (PREFIX_0F38F0) },
7116     { PREFIX_TABLE (PREFIX_0F38F1) },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { PREFIX_TABLE (PREFIX_0F38F6) },
7122     { Bad_Opcode },
7123     /* f8 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132   },
7133   /* THREE_BYTE_0F3A */
7134   {
7135     /* 00 */
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     /* 08 */
7145     { PREFIX_TABLE (PREFIX_0F3A08) },
7146     { PREFIX_TABLE (PREFIX_0F3A09) },
7147     { PREFIX_TABLE (PREFIX_0F3A0A) },
7148     { PREFIX_TABLE (PREFIX_0F3A0B) },
7149     { PREFIX_TABLE (PREFIX_0F3A0C) },
7150     { PREFIX_TABLE (PREFIX_0F3A0D) },
7151     { PREFIX_TABLE (PREFIX_0F3A0E) },
7152     { "palignr",        { MX, EM, Ib } },
7153     /* 10 */
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { PREFIX_TABLE (PREFIX_0F3A14) },
7159     { PREFIX_TABLE (PREFIX_0F3A15) },
7160     { PREFIX_TABLE (PREFIX_0F3A16) },
7161     { PREFIX_TABLE (PREFIX_0F3A17) },
7162     /* 18 */
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     /* 20 */
7172     { PREFIX_TABLE (PREFIX_0F3A20) },
7173     { PREFIX_TABLE (PREFIX_0F3A21) },
7174     { PREFIX_TABLE (PREFIX_0F3A22) },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     /* 28 */
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     /* 30 */
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     /* 38 */
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     /* 40 */
7208     { PREFIX_TABLE (PREFIX_0F3A40) },
7209     { PREFIX_TABLE (PREFIX_0F3A41) },
7210     { PREFIX_TABLE (PREFIX_0F3A42) },
7211     { Bad_Opcode },
7212     { PREFIX_TABLE (PREFIX_0F3A44) },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     /* 48 */
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     /* 50 */
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     /* 58 */
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     /* 60 */
7244     { PREFIX_TABLE (PREFIX_0F3A60) },
7245     { PREFIX_TABLE (PREFIX_0F3A61) },
7246     { PREFIX_TABLE (PREFIX_0F3A62) },
7247     { PREFIX_TABLE (PREFIX_0F3A63) },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     /* 68 */
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     /* 70 */
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     /* 78 */
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     /* 80 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 88 */
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     /* 90 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     /* 98 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* a0 */
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* a8 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* b0 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* b8 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* c0 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* c8 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { PREFIX_TABLE (PREFIX_0F3ACC) },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* d0 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* d8 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { PREFIX_TABLE (PREFIX_0F3ADF) },
7387     /* e0 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* e8 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* f0 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* f8 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423   },
7424
7425   /* THREE_BYTE_0F7A */
7426   {
7427     /* 00 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 08 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* 10 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* 18 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* 20 */
7464     { "ptest",          { XX } },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* 28 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* 30 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* 38 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* 40 */
7500     { Bad_Opcode },
7501     { "phaddbw",        { XM, EXq } },
7502     { "phaddbd",        { XM, EXq } },
7503     { "phaddbq",        { XM, EXq } },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { "phaddwd",        { XM, EXq } },
7507     { "phaddwq",        { XM, EXq } },
7508     /* 48 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { "phadddq",        { XM, EXq } },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     /* 50 */
7518     { Bad_Opcode },
7519     { "phaddubw",       { XM, EXq } },
7520     { "phaddubd",       { XM, EXq } },
7521     { "phaddubq",       { XM, EXq } },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { "phadduwd",       { XM, EXq } },
7525     { "phadduwq",       { XM, EXq } },
7526     /* 58 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { "phaddudq",       { XM, EXq } },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* 60 */
7536     { Bad_Opcode },
7537     { "phsubbw",        { XM, EXq } },
7538     { "phsubbd",        { XM, EXq } },
7539     { "phsubbq",        { XM, EXq } },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* 68 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 70 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 78 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 80 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 88 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 90 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 98 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* a0 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* a8 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* b0 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* b8 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* c0 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* c8 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* d0 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* d8 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* e0 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* e8 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     /* f0 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     /* f8 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715   },
7716 };
7717
7718 static const struct dis386 xop_table[][256] = {
7719   /* XOP_08 */
7720   {
7721     /* 00 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     /* 08 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* 10 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* 18 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* 20 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     /* 28 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* 30 */
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* 38 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     /* 40 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* 48 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* 50 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* 58 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     /* 60 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* 68 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     /* 70 */
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     /* 78 */
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     /* 80 */
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7872     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7873     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7874     /* 88 */
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7882     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7883     /* 90 */
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7890     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7891     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7892     /* 98 */
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7900     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7901     /* a0 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7905     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7909     { Bad_Opcode },
7910     /* a8 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* b0 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7927     { Bad_Opcode },
7928     /* b8 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* c0 */
7938     { "vprotb",         { XM, Vex_2src_1, Ib } },
7939     { "vprotw",         { XM, Vex_2src_1, Ib } },
7940     { "vprotd",         { XM, Vex_2src_1, Ib } },
7941     { "vprotq",         { XM, Vex_2src_1, Ib } },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* c8 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7952     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7953     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7954     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7955     /* d0 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* d8 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* e0 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* e8 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7988     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7989     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7990     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7991     /* f0 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* f8 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009   },
8010   /* XOP_09 */
8011   {
8012     /* 00 */
8013     { Bad_Opcode },
8014     { REG_TABLE (REG_XOP_TBM_01) },
8015     { REG_TABLE (REG_XOP_TBM_02) },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     /* 08 */
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* 10 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { REG_TABLE (REG_XOP_LWPCB) },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* 18 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* 20 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* 28 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* 30 */
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     /* 38 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* 40 */
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     /* 48 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* 50 */
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* 58 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* 60 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* 68 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     /* 70 */
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     /* 78 */
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     /* 80 */
8157     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8158     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8159     { "vfrczss",        { XM, EXd } },
8160     { "vfrczsd",        { XM, EXq } },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     /* 88 */
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     /* 90 */
8175     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
8176     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
8177     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
8178     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
8179     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
8180     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
8181     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
8182     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
8183     /* 98 */
8184     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
8185     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
8186     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
8187     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* a0 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* a8 */
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* b0 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* b8 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* c0 */
8229     { Bad_Opcode },
8230     { "vphaddbw",       { XM, EXxmm } },
8231     { "vphaddbd",       { XM, EXxmm } },
8232     { "vphaddbq",       { XM, EXxmm } },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { "vphaddwd",       { XM, EXxmm } },
8236     { "vphaddwq",       { XM, EXxmm } },
8237     /* c8 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { "vphadddq",       { XM, EXxmm } },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* d0 */
8247     { Bad_Opcode },
8248     { "vphaddubw",      { XM, EXxmm } },
8249     { "vphaddubd",      { XM, EXxmm } },
8250     { "vphaddubq",      { XM, EXxmm } },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { "vphadduwd",      { XM, EXxmm } },
8254     { "vphadduwq",      { XM, EXxmm } },
8255     /* d8 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { "vphaddudq",      { XM, EXxmm } },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* e0 */
8265     { Bad_Opcode },
8266     { "vphsubbw",       { XM, EXxmm } },
8267     { "vphsubwd",       { XM, EXxmm } },
8268     { "vphsubdq",       { XM, EXxmm } },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* e8 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* f0 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* f8 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300   },
8301   /* XOP_0A */
8302   {
8303     /* 00 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* 08 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* 10 */
8322     { "bextr",  { Gv, Ev, Iq } },
8323     { Bad_Opcode },
8324     { REG_TABLE (REG_XOP_LWP) },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* 18 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* 20 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* 28 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* 30 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* 38 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* 40 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* 48 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* 50 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* 58 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* 60 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* 68 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 70 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 78 */
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     /* 80 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 88 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 90 */
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     /* 98 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* a0 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* a8 */
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     /* b0 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* b8 */
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     /* c0 */
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     /* c8 */
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     /* d0 */
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     /* d8 */
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     /* e0 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     /* e8 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* f0 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* f8 */
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591   },
8592 };
8593
8594 static const struct dis386 vex_table[][256] = {
8595   /* VEX_0F */
8596   {
8597     /* 00 */
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     /* 08 */
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* 10 */
8616     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8619     { MOD_TABLE (MOD_VEX_0F13) },
8620     { VEX_W_TABLE (VEX_W_0F14) },
8621     { VEX_W_TABLE (VEX_W_0F15) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8623     { MOD_TABLE (MOD_VEX_0F17) },
8624     /* 18 */
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     /* 20 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     /* 28 */
8643     { VEX_W_TABLE (VEX_W_0F28) },
8644     { VEX_W_TABLE (VEX_W_0F29) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8646     { MOD_TABLE (MOD_VEX_0F2B) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8648     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8649     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8651     /* 30 */
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     /* 38 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* 40 */
8670     { Bad_Opcode },
8671     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8673     { Bad_Opcode },
8674     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8677     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8678     /* 48 */
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8682     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     /* 50 */
8688     { MOD_TABLE (MOD_VEX_0F50) },
8689     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8690     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8691     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8692     { "vandpX",         { XM, Vex, EXx } },
8693     { "vandnpX",        { XM, Vex, EXx } },
8694     { "vorpX",          { XM, Vex, EXx } },
8695     { "vxorpX",         { XM, Vex, EXx } },
8696     /* 58 */
8697     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8703     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8704     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8705     /* 60 */
8706     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8708     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8709     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8710     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8711     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8712     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8714     /* 68 */
8715     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8720     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8721     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8723     /* 70 */
8724     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8725     { REG_TABLE (REG_VEX_0F71) },
8726     { REG_TABLE (REG_VEX_0F72) },
8727     { REG_TABLE (REG_VEX_0F73) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8732     /* 78 */
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8741     /* 80 */
8742     { Bad_Opcode },
8743     { Bad_Opcode },
8744     { Bad_Opcode },
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { Bad_Opcode },
8749     { Bad_Opcode },
8750     /* 88 */
8751     { Bad_Opcode },
8752     { Bad_Opcode },
8753     { Bad_Opcode },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     { Bad_Opcode },
8757     { Bad_Opcode },
8758     { Bad_Opcode },
8759     /* 90 */
8760     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8764     { Bad_Opcode },
8765     { Bad_Opcode },
8766     { Bad_Opcode },
8767     { Bad_Opcode },
8768     /* 98 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     { Bad_Opcode },
8776     { Bad_Opcode },
8777     /* a0 */
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     /* a8 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { REG_TABLE (REG_VEX_0FAE) },
8794     { Bad_Opcode },
8795     /* b0 */
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     /* b8 */
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* c0 */
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8817     { Bad_Opcode },
8818     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8819     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8820     { "vshufpX",        { XM, Vex, EXx, Ib } },
8821     { Bad_Opcode },
8822     /* c8 */
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     /* d0 */
8832     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8833     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8834     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8835     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8836     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8837     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8838     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8839     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8840     /* d8 */
8841     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8842     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8843     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8845     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8846     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8847     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8848     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8849     /* e0 */
8850     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8851     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8852     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8853     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8854     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8855     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8856     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8857     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8858     /* e8 */
8859     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8865     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8866     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8867     /* f0 */
8868     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8874     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8875     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8876     /* f8 */
8877     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8883     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8884     { Bad_Opcode },
8885   },
8886   /* VEX_0F38 */
8887   {
8888     /* 00 */
8889     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8893     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8894     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8897     /* 08 */
8898     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8906     /* 10 */
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8915     /* 18 */
8916     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8919     { Bad_Opcode },
8920     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8923     { Bad_Opcode },
8924     /* 20 */
8925     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     /* 28 */
8934     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8942     /* 30 */
8943     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8948     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8951     /* 38 */
8952     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8957     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8960     /* 40 */
8961     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8969     /* 48 */
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     /* 50 */
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* 58 */
8988     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     /* 60 */
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     /* 68 */
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     /* 70 */
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     /* 78 */
9024     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     /* 80 */
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     /* 88 */
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9047     { Bad_Opcode },
9048     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9049     { Bad_Opcode },
9050     /* 90 */
9051     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9052     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9053     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9059     /* 98 */
9060     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9063     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9064     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9068     /* a0 */
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9077     /* a8 */
9078     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9080     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9081     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9086     /* b0 */
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9094     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9095     /* b8 */
9096     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9104     /* c0 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* c8 */
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     /* d0 */
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* d8 */
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9140     /* e0 */
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* e8 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* f0 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9162     { REG_TABLE (REG_VEX_0F38F3) },
9163     { Bad_Opcode },
9164     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9167     /* f8 */
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176   },
9177   /* VEX_0F3A */
9178   {
9179     /* 00 */
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9183     { Bad_Opcode },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9185     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9186     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9187     { Bad_Opcode },
9188     /* 08 */
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9193     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9197     /* 10 */
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9206     /* 18 */
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     /* 20 */
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     /* 28 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* 30 */
9234     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* 38 */
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* 40 */
9252     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9255     { Bad_Opcode },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9257     { Bad_Opcode },
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9259     { Bad_Opcode },
9260     /* 48 */
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9264     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9265     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     /* 50 */
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* 58 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9284     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9287     /* 60 */
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9291     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* 68 */
9297     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9298     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9299     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9300     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9301     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9302     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9305     /* 70 */
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { Bad_Opcode },
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     /* 78 */
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9317     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9318     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9319     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9320     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9321     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9323     /* 80 */
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     /* 88 */
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     /* 90 */
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     /* 98 */
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     /* a0 */
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     /* a8 */
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     /* b0 */
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     /* b8 */
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     /* c0 */
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     /* c8 */
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     /* d0 */
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     /* d8 */
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     { Bad_Opcode },
9430     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9431     /* e0 */
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     /* e8 */
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     /* f0 */
9450     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { Bad_Opcode },
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     /* f8 */
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467   },
9468 };
9469
9470 #define NEED_OPCODE_TABLE
9471 #include "i386-dis-evex.h"
9472 #undef NEED_OPCODE_TABLE
9473 static const struct dis386 vex_len_table[][2] = {
9474   /* VEX_LEN_0F10_P_1 */
9475   {
9476     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9477     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9478   },
9479
9480   /* VEX_LEN_0F10_P_3 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9483     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9484   },
9485
9486   /* VEX_LEN_0F11_P_1 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9489     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9490   },
9491
9492   /* VEX_LEN_0F11_P_3 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9495     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9496   },
9497
9498   /* VEX_LEN_0F12_P_0_M_0 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9501   },
9502
9503   /* VEX_LEN_0F12_P_0_M_1 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9506   },
9507
9508   /* VEX_LEN_0F12_P_2 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9511   },
9512
9513   /* VEX_LEN_0F13_M_0 */
9514   {
9515     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9516   },
9517
9518   /* VEX_LEN_0F16_P_0_M_0 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9521   },
9522
9523   /* VEX_LEN_0F16_P_0_M_1 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9526   },
9527
9528   /* VEX_LEN_0F16_P_2 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9531   },
9532
9533   /* VEX_LEN_0F17_M_0 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9536   },
9537
9538   /* VEX_LEN_0F2A_P_1 */
9539   {
9540     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9541     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev } },
9542   },
9543
9544   /* VEX_LEN_0F2A_P_3 */
9545   {
9546     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9547     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev } },
9548   },
9549
9550   /* VEX_LEN_0F2C_P_1 */
9551   {
9552     { "vcvttss2siY",    { Gv, EXdScalar } },
9553     { "vcvttss2siY",    { Gv, EXdScalar } },
9554   },
9555
9556   /* VEX_LEN_0F2C_P_3 */
9557   {
9558     { "vcvttsd2siY",    { Gv, EXqScalar } },
9559     { "vcvttsd2siY",    { Gv, EXqScalar } },
9560   },
9561
9562   /* VEX_LEN_0F2D_P_1 */
9563   {
9564     { "vcvtss2siY",     { Gv, EXdScalar } },
9565     { "vcvtss2siY",     { Gv, EXdScalar } },
9566   },
9567
9568   /* VEX_LEN_0F2D_P_3 */
9569   {
9570     { "vcvtsd2siY",     { Gv, EXqScalar } },
9571     { "vcvtsd2siY",     { Gv, EXqScalar } },
9572   },
9573
9574   /* VEX_LEN_0F2E_P_0 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9577     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9578   },
9579
9580   /* VEX_LEN_0F2E_P_2 */
9581   {
9582     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9583     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9584   },
9585
9586   /* VEX_LEN_0F2F_P_0 */
9587   {
9588     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9589     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9590   },
9591
9592   /* VEX_LEN_0F2F_P_2 */
9593   {
9594     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9595     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9596   },
9597
9598   /* VEX_LEN_0F41_P_0 */
9599   {
9600     { Bad_Opcode },
9601     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9602   },
9603   /* VEX_LEN_0F41_P_2 */
9604   {
9605     { Bad_Opcode },
9606     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9607   },
9608   /* VEX_LEN_0F42_P_0 */
9609   {
9610     { Bad_Opcode },
9611     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9612   },
9613   /* VEX_LEN_0F42_P_2 */
9614   {
9615     { Bad_Opcode },
9616     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9617   },
9618   /* VEX_LEN_0F44_P_0 */
9619   {
9620     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9621   },
9622   /* VEX_LEN_0F44_P_2 */
9623   {
9624     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9625   },
9626   /* VEX_LEN_0F45_P_0 */
9627   {
9628     { Bad_Opcode },
9629     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9630   },
9631   /* VEX_LEN_0F45_P_2 */
9632   {
9633     { Bad_Opcode },
9634     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9635   },
9636   /* VEX_LEN_0F46_P_0 */
9637   {
9638     { Bad_Opcode },
9639     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9640   },
9641   /* VEX_LEN_0F46_P_2 */
9642   {
9643     { Bad_Opcode },
9644     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9645   },
9646   /* VEX_LEN_0F47_P_0 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9650   },
9651   /* VEX_LEN_0F47_P_2 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9655   },
9656   /* VEX_LEN_0F4A_P_0 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9660   },
9661   /* VEX_LEN_0F4A_P_2 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9665   },
9666   /* VEX_LEN_0F4B_P_0 */
9667   {
9668     { Bad_Opcode },
9669     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9670   },
9671   /* VEX_LEN_0F4B_P_2 */
9672   {
9673     { Bad_Opcode },
9674     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9675   },
9676
9677   /* VEX_LEN_0F51_P_1 */
9678   {
9679     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9680     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9681   },
9682
9683   /* VEX_LEN_0F51_P_3 */
9684   {
9685     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9686     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9687   },
9688
9689   /* VEX_LEN_0F52_P_1 */
9690   {
9691     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9692     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9693   },
9694
9695   /* VEX_LEN_0F53_P_1 */
9696   {
9697     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9698     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9699   },
9700
9701   /* VEX_LEN_0F58_P_1 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9704     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9705   },
9706
9707   /* VEX_LEN_0F58_P_3 */
9708   {
9709     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9710     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9711   },
9712
9713   /* VEX_LEN_0F59_P_1 */
9714   {
9715     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9716     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9717   },
9718
9719   /* VEX_LEN_0F59_P_3 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9722     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9723   },
9724
9725   /* VEX_LEN_0F5A_P_1 */
9726   {
9727     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9728     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9729   },
9730
9731   /* VEX_LEN_0F5A_P_3 */
9732   {
9733     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9734     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9735   },
9736
9737   /* VEX_LEN_0F5C_P_1 */
9738   {
9739     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9740     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9741   },
9742
9743   /* VEX_LEN_0F5C_P_3 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9746     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9747   },
9748
9749   /* VEX_LEN_0F5D_P_1 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9752     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9753   },
9754
9755   /* VEX_LEN_0F5D_P_3 */
9756   {
9757     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9758     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9759   },
9760
9761   /* VEX_LEN_0F5E_P_1 */
9762   {
9763     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9764     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9765   },
9766
9767   /* VEX_LEN_0F5E_P_3 */
9768   {
9769     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9770     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9771   },
9772
9773   /* VEX_LEN_0F5F_P_1 */
9774   {
9775     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9776     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9777   },
9778
9779   /* VEX_LEN_0F5F_P_3 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9782     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9783   },
9784
9785   /* VEX_LEN_0F6E_P_2 */
9786   {
9787     { "vmovK",          { XMScalar, Edq } },
9788     { "vmovK",          { XMScalar, Edq } },
9789   },
9790
9791   /* VEX_LEN_0F7E_P_1 */
9792   {
9793     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9794     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9795   },
9796
9797   /* VEX_LEN_0F7E_P_2 */
9798   {
9799     { "vmovK",          { Edq, XMScalar } },
9800     { "vmovK",          { Edq, XMScalar } },
9801   },
9802
9803   /* VEX_LEN_0F90_P_0 */
9804   {
9805     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9806   },
9807
9808   /* VEX_LEN_0F90_P_2 */
9809   {
9810     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9811   },
9812
9813   /* VEX_LEN_0F91_P_0 */
9814   {
9815     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9816   },
9817
9818   /* VEX_LEN_0F91_P_2 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9821   },
9822
9823   /* VEX_LEN_0F92_P_0 */
9824   {
9825     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9826   },
9827
9828   /* VEX_LEN_0F92_P_2 */
9829   {
9830     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9831   },
9832
9833   /* VEX_LEN_0F92_P_3 */
9834   {
9835     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9836   },
9837
9838   /* VEX_LEN_0F93_P_0 */
9839   {
9840     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9841   },
9842
9843   /* VEX_LEN_0F93_P_2 */
9844   {
9845     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9846   },
9847
9848   /* VEX_LEN_0F93_P_3 */
9849   {
9850     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9851   },
9852
9853   /* VEX_LEN_0F98_P_0 */
9854   {
9855     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9856   },
9857
9858   /* VEX_LEN_0F98_P_2 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9861   },
9862
9863   /* VEX_LEN_0F99_P_0 */
9864   {
9865     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9866   },
9867
9868   /* VEX_LEN_0F99_P_2 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9871   },
9872
9873   /* VEX_LEN_0FAE_R_2_M_0 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9876   },
9877
9878   /* VEX_LEN_0FAE_R_3_M_0 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9881   },
9882
9883   /* VEX_LEN_0FC2_P_1 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9886     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9887   },
9888
9889   /* VEX_LEN_0FC2_P_3 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9892     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9893   },
9894
9895   /* VEX_LEN_0FC4_P_2 */
9896   {
9897     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9898   },
9899
9900   /* VEX_LEN_0FC5_P_2 */
9901   {
9902     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9903   },
9904
9905   /* VEX_LEN_0FD6_P_2 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9908     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9909   },
9910
9911   /* VEX_LEN_0FF7_P_2 */
9912   {
9913     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9914   },
9915
9916   /* VEX_LEN_0F3816_P_2 */
9917   {
9918     { Bad_Opcode },
9919     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9920   },
9921
9922   /* VEX_LEN_0F3819_P_2 */
9923   {
9924     { Bad_Opcode },
9925     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9926   },
9927
9928   /* VEX_LEN_0F381A_P_2_M_0 */
9929   {
9930     { Bad_Opcode },
9931     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9932   },
9933
9934   /* VEX_LEN_0F3836_P_2 */
9935   {
9936     { Bad_Opcode },
9937     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9938   },
9939
9940   /* VEX_LEN_0F3841_P_2 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9943   },
9944
9945   /* VEX_LEN_0F385A_P_2_M_0 */
9946   {
9947     { Bad_Opcode },
9948     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9949   },
9950
9951   /* VEX_LEN_0F38DB_P_2 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9954   },
9955
9956   /* VEX_LEN_0F38DC_P_2 */
9957   {
9958     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9959   },
9960
9961   /* VEX_LEN_0F38DD_P_2 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9964   },
9965
9966   /* VEX_LEN_0F38DE_P_2 */
9967   {
9968     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9969   },
9970
9971   /* VEX_LEN_0F38DF_P_2 */
9972   {
9973     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9974   },
9975
9976   /* VEX_LEN_0F38F2_P_0 */
9977   {
9978     { "andnS",          { Gdq, VexGdq, Edq } },
9979   },
9980
9981   /* VEX_LEN_0F38F3_R_1_P_0 */
9982   {
9983     { "blsrS",          { VexGdq, Edq } },
9984   },
9985
9986   /* VEX_LEN_0F38F3_R_2_P_0 */
9987   {
9988     { "blsmskS",        { VexGdq, Edq } },
9989   },
9990
9991   /* VEX_LEN_0F38F3_R_3_P_0 */
9992   {
9993     { "blsiS",          { VexGdq, Edq } },
9994   },
9995
9996   /* VEX_LEN_0F38F5_P_0 */
9997   {
9998     { "bzhiS",          { Gdq, Edq, VexGdq } },
9999   },
10000
10001   /* VEX_LEN_0F38F5_P_1 */
10002   {
10003     { "pextS",          { Gdq, VexGdq, Edq } },
10004   },
10005
10006   /* VEX_LEN_0F38F5_P_3 */
10007   {
10008     { "pdepS",          { Gdq, VexGdq, Edq } },
10009   },
10010
10011   /* VEX_LEN_0F38F6_P_3 */
10012   {
10013     { "mulxS",          { Gdq, VexGdq, Edq } },
10014   },
10015
10016   /* VEX_LEN_0F38F7_P_0 */
10017   {
10018     { "bextrS",         { Gdq, Edq, VexGdq } },
10019   },
10020
10021   /* VEX_LEN_0F38F7_P_1 */
10022   {
10023     { "sarxS",          { Gdq, Edq, VexGdq } },
10024   },
10025
10026   /* VEX_LEN_0F38F7_P_2 */
10027   {
10028     { "shlxS",          { Gdq, Edq, VexGdq } },
10029   },
10030
10031   /* VEX_LEN_0F38F7_P_3 */
10032   {
10033     { "shrxS",          { Gdq, Edq, VexGdq } },
10034   },
10035
10036   /* VEX_LEN_0F3A00_P_2 */
10037   {
10038     { Bad_Opcode },
10039     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10040   },
10041
10042   /* VEX_LEN_0F3A01_P_2 */
10043   {
10044     { Bad_Opcode },
10045     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10046   },
10047
10048   /* VEX_LEN_0F3A06_P_2 */
10049   {
10050     { Bad_Opcode },
10051     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10052   },
10053
10054   /* VEX_LEN_0F3A0A_P_2 */
10055   {
10056     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10057     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10058   },
10059
10060   /* VEX_LEN_0F3A0B_P_2 */
10061   {
10062     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10063     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10064   },
10065
10066   /* VEX_LEN_0F3A14_P_2 */
10067   {
10068     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10069   },
10070
10071   /* VEX_LEN_0F3A15_P_2 */
10072   {
10073     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10074   },
10075
10076   /* VEX_LEN_0F3A16_P_2  */
10077   {
10078     { "vpextrK",        { Edq, XM, Ib } },
10079   },
10080
10081   /* VEX_LEN_0F3A17_P_2 */
10082   {
10083     { "vextractps",     { Edqd, XM, Ib } },
10084   },
10085
10086   /* VEX_LEN_0F3A18_P_2 */
10087   {
10088     { Bad_Opcode },
10089     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10090   },
10091
10092   /* VEX_LEN_0F3A19_P_2 */
10093   {
10094     { Bad_Opcode },
10095     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10096   },
10097
10098   /* VEX_LEN_0F3A20_P_2 */
10099   {
10100     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10101   },
10102
10103   /* VEX_LEN_0F3A21_P_2 */
10104   {
10105     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10106   },
10107
10108   /* VEX_LEN_0F3A22_P_2 */
10109   {
10110     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
10111   },
10112
10113   /* VEX_LEN_0F3A30_P_2 */
10114   {
10115     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10116   },
10117
10118   /* VEX_LEN_0F3A31_P_2 */
10119   {
10120     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10121   },
10122
10123   /* VEX_LEN_0F3A32_P_2 */
10124   {
10125     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10126   },
10127
10128   /* VEX_LEN_0F3A33_P_2 */
10129   {
10130     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10131   },
10132
10133   /* VEX_LEN_0F3A38_P_2 */
10134   {
10135     { Bad_Opcode },
10136     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10137   },
10138
10139   /* VEX_LEN_0F3A39_P_2 */
10140   {
10141     { Bad_Opcode },
10142     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10143   },
10144
10145   /* VEX_LEN_0F3A41_P_2 */
10146   {
10147     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10148   },
10149
10150   /* VEX_LEN_0F3A44_P_2 */
10151   {
10152     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10153   },
10154
10155   /* VEX_LEN_0F3A46_P_2 */
10156   {
10157     { Bad_Opcode },
10158     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10159   },
10160
10161   /* VEX_LEN_0F3A60_P_2 */
10162   {
10163     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10164   },
10165
10166   /* VEX_LEN_0F3A61_P_2 */
10167   {
10168     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10169   },
10170
10171   /* VEX_LEN_0F3A62_P_2 */
10172   {
10173     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A63_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10179   },
10180
10181   /* VEX_LEN_0F3A6A_P_2 */
10182   {
10183     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10184   },
10185
10186   /* VEX_LEN_0F3A6B_P_2 */
10187   {
10188     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10189   },
10190
10191   /* VEX_LEN_0F3A6E_P_2 */
10192   {
10193     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10194   },
10195
10196   /* VEX_LEN_0F3A6F_P_2 */
10197   {
10198     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10199   },
10200
10201   /* VEX_LEN_0F3A7A_P_2 */
10202   {
10203     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10204   },
10205
10206   /* VEX_LEN_0F3A7B_P_2 */
10207   {
10208     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10209   },
10210
10211   /* VEX_LEN_0F3A7E_P_2 */
10212   {
10213     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10214   },
10215
10216   /* VEX_LEN_0F3A7F_P_2 */
10217   {
10218     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10219   },
10220
10221   /* VEX_LEN_0F3ADF_P_2 */
10222   {
10223     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10224   },
10225
10226   /* VEX_LEN_0F3AF0_P_3 */
10227   {
10228     { "rorxS",          { Gdq, Edq, Ib } },
10229   },
10230
10231   /* VEX_LEN_0FXOP_08_CC */
10232   {
10233      { "vpcomb",        { XM, Vex128, EXx, Ib } },
10234   },
10235
10236   /* VEX_LEN_0FXOP_08_CD */
10237   {
10238      { "vpcomw",        { XM, Vex128, EXx, Ib } },
10239   },
10240
10241   /* VEX_LEN_0FXOP_08_CE */
10242   {
10243      { "vpcomd",        { XM, Vex128, EXx, Ib } },
10244   },
10245
10246   /* VEX_LEN_0FXOP_08_CF */
10247   {
10248      { "vpcomq",        { XM, Vex128, EXx, Ib } },
10249   },
10250
10251   /* VEX_LEN_0FXOP_08_EC */
10252   {
10253      { "vpcomub",       { XM, Vex128, EXx, Ib } },
10254   },
10255
10256   /* VEX_LEN_0FXOP_08_ED */
10257   {
10258      { "vpcomuw",       { XM, Vex128, EXx, Ib } },
10259   },
10260
10261   /* VEX_LEN_0FXOP_08_EE */
10262   {
10263      { "vpcomud",       { XM, Vex128, EXx, Ib } },
10264   },
10265
10266   /* VEX_LEN_0FXOP_08_EF */
10267   {
10268      { "vpcomuq",       { XM, Vex128, EXx, Ib } },
10269   },
10270
10271   /* VEX_LEN_0FXOP_09_80 */
10272   {
10273     { "vfrczps",        { XM, EXxmm } },
10274     { "vfrczps",        { XM, EXymmq } },
10275   },
10276
10277   /* VEX_LEN_0FXOP_09_81 */
10278   {
10279     { "vfrczpd",        { XM, EXxmm } },
10280     { "vfrczpd",        { XM, EXymmq } },
10281   },
10282 };
10283
10284 static const struct dis386 vex_w_table[][2] = {
10285   {
10286     /* VEX_W_0F10_P_0 */
10287     { "vmovups",        { XM, EXx } },
10288   },
10289   {
10290     /* VEX_W_0F10_P_1 */
10291     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar } },
10292   },
10293   {
10294     /* VEX_W_0F10_P_2 */
10295     { "vmovupd",        { XM, EXx } },
10296   },
10297   {
10298     /* VEX_W_0F10_P_3 */
10299     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar } },
10300   },
10301   {
10302     /* VEX_W_0F11_P_0 */
10303     { "vmovups",        { EXxS, XM } },
10304   },
10305   {
10306     /* VEX_W_0F11_P_1 */
10307     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar } },
10308   },
10309   {
10310     /* VEX_W_0F11_P_2 */
10311     { "vmovupd",        { EXxS, XM } },
10312   },
10313   {
10314     /* VEX_W_0F11_P_3 */
10315     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar } },
10316   },
10317   {
10318     /* VEX_W_0F12_P_0_M_0 */
10319     { "vmovlps",        { XM, Vex128, EXq } },
10320   },
10321   {
10322     /* VEX_W_0F12_P_0_M_1 */
10323     { "vmovhlps",       { XM, Vex128, EXq } },
10324   },
10325   {
10326     /* VEX_W_0F12_P_1 */
10327     { "vmovsldup",      { XM, EXx } },
10328   },
10329   {
10330     /* VEX_W_0F12_P_2 */
10331     { "vmovlpd",        { XM, Vex128, EXq } },
10332   },
10333   {
10334     /* VEX_W_0F12_P_3 */
10335     { "vmovddup",       { XM, EXymmq } },
10336   },
10337   {
10338     /* VEX_W_0F13_M_0 */
10339     { "vmovlpX",        { EXq, XM } },
10340   },
10341   {
10342     /* VEX_W_0F14 */
10343     { "vunpcklpX",      { XM, Vex, EXx } },
10344   },
10345   {
10346     /* VEX_W_0F15 */
10347     { "vunpckhpX",      { XM, Vex, EXx } },
10348   },
10349   {
10350     /* VEX_W_0F16_P_0_M_0 */
10351     { "vmovhps",        { XM, Vex128, EXq } },
10352   },
10353   {
10354     /* VEX_W_0F16_P_0_M_1 */
10355     { "vmovlhps",       { XM, Vex128, EXq } },
10356   },
10357   {
10358     /* VEX_W_0F16_P_1 */
10359     { "vmovshdup",      { XM, EXx } },
10360   },
10361   {
10362     /* VEX_W_0F16_P_2 */
10363     { "vmovhpd",        { XM, Vex128, EXq } },
10364   },
10365   {
10366     /* VEX_W_0F17_M_0 */
10367     { "vmovhpX",        { EXq, XM } },
10368   },
10369   {
10370     /* VEX_W_0F28 */
10371     { "vmovapX",        { XM, EXx } },
10372   },
10373   {
10374     /* VEX_W_0F29 */
10375     { "vmovapX",        { EXxS, XM } },
10376   },
10377   {
10378     /* VEX_W_0F2B_M_0 */
10379     { "vmovntpX",       { Mx, XM } },
10380   },
10381   {
10382     /* VEX_W_0F2E_P_0 */
10383     { "vucomiss",       { XMScalar, EXdScalar } },
10384   },
10385   {
10386     /* VEX_W_0F2E_P_2 */
10387     { "vucomisd",       { XMScalar, EXqScalar } },
10388   },
10389   {
10390     /* VEX_W_0F2F_P_0 */
10391     { "vcomiss",        { XMScalar, EXdScalar } },
10392   },
10393   {
10394     /* VEX_W_0F2F_P_2 */
10395     { "vcomisd",        { XMScalar, EXqScalar } },
10396   },
10397   {
10398     /* VEX_W_0F41_P_0_LEN_1 */
10399     { "kandw",          { MaskG, MaskVex, MaskR } },
10400     { "kandq",          { MaskG, MaskVex, MaskR } },
10401   },
10402   {
10403     /* VEX_W_0F41_P_2_LEN_1 */
10404     { "kandb",          { MaskG, MaskVex, MaskR } },
10405     { "kandd",          { MaskG, MaskVex, MaskR } },
10406   },
10407   {
10408     /* VEX_W_0F42_P_0_LEN_1 */
10409     { "kandnw",         { MaskG, MaskVex, MaskR } },
10410     { "kandnq",         { MaskG, MaskVex, MaskR } },
10411   },
10412   {
10413     /* VEX_W_0F42_P_2_LEN_1 */
10414     { "kandnb",         { MaskG, MaskVex, MaskR } },
10415     { "kandnd",         { MaskG, MaskVex, MaskR } },
10416   },
10417   {
10418     /* VEX_W_0F44_P_0_LEN_0 */
10419     { "knotw",          { MaskG, MaskR } },
10420     { "knotq",          { MaskG, MaskR } },
10421   },
10422   {
10423     /* VEX_W_0F44_P_2_LEN_0 */
10424     { "knotb",          { MaskG, MaskR } },
10425     { "knotd",          { MaskG, MaskR } },
10426   },
10427   {
10428     /* VEX_W_0F45_P_0_LEN_1 */
10429     { "korw",           { MaskG, MaskVex, MaskR } },
10430     { "korq",           { MaskG, MaskVex, MaskR } },
10431   },
10432   {
10433     /* VEX_W_0F45_P_2_LEN_1 */
10434     { "korb",           { MaskG, MaskVex, MaskR } },
10435     { "kord",           { MaskG, MaskVex, MaskR } },
10436   },
10437   {
10438     /* VEX_W_0F46_P_0_LEN_1 */
10439     { "kxnorw",         { MaskG, MaskVex, MaskR } },
10440     { "kxnorq",         { MaskG, MaskVex, MaskR } },
10441   },
10442   {
10443     /* VEX_W_0F46_P_2_LEN_1 */
10444     { "kxnorb",         { MaskG, MaskVex, MaskR } },
10445     { "kxnord",         { MaskG, MaskVex, MaskR } },
10446   },
10447   {
10448     /* VEX_W_0F47_P_0_LEN_1 */
10449     { "kxorw",          { MaskG, MaskVex, MaskR } },
10450     { "kxorq",          { MaskG, MaskVex, MaskR } },
10451   },
10452   {
10453     /* VEX_W_0F47_P_2_LEN_1 */
10454     { "kxorb",          { MaskG, MaskVex, MaskR } },
10455     { "kxord",          { MaskG, MaskVex, MaskR } },
10456   },
10457   {
10458     /* VEX_W_0F4A_P_0_LEN_1 */
10459     { "kaddw",          { MaskG, MaskVex, MaskR } },
10460     { "kaddq",          { MaskG, MaskVex, MaskR } },
10461   },
10462   {
10463     /* VEX_W_0F4A_P_2_LEN_1 */
10464     { "kaddb",          { MaskG, MaskVex, MaskR } },
10465     { "kaddd",          { MaskG, MaskVex, MaskR } },
10466   },
10467   {
10468     /* VEX_W_0F4B_P_0_LEN_1 */
10469     { "kunpckwd",       { MaskG, MaskVex, MaskR } },
10470     { "kunpckdq",       { MaskG, MaskVex, MaskR } },
10471   },
10472   {
10473     /* VEX_W_0F4B_P_2_LEN_1 */
10474     { "kunpckbw",       { MaskG, MaskVex, MaskR } },
10475   },
10476   {
10477     /* VEX_W_0F50_M_0 */
10478     { "vmovmskpX",      { Gdq, XS } },
10479   },
10480   {
10481     /* VEX_W_0F51_P_0 */
10482     { "vsqrtps",        { XM, EXx } },
10483   },
10484   {
10485     /* VEX_W_0F51_P_1 */
10486     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar } },
10487   },
10488   {
10489     /* VEX_W_0F51_P_2  */
10490     { "vsqrtpd",        { XM, EXx } },
10491   },
10492   {
10493     /* VEX_W_0F51_P_3 */
10494     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar } },
10495   },
10496   {
10497     /* VEX_W_0F52_P_0 */
10498     { "vrsqrtps",       { XM, EXx } },
10499   },
10500   {
10501     /* VEX_W_0F52_P_1 */
10502     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar } },
10503   },
10504   {
10505     /* VEX_W_0F53_P_0  */
10506     { "vrcpps",         { XM, EXx } },
10507   },
10508   {
10509     /* VEX_W_0F53_P_1  */
10510     { "vrcpss",         { XMScalar, VexScalar, EXdScalar } },
10511   },
10512   {
10513     /* VEX_W_0F58_P_0  */
10514     { "vaddps",         { XM, Vex, EXx } },
10515   },
10516   {
10517     /* VEX_W_0F58_P_1  */
10518     { "vaddss",         { XMScalar, VexScalar, EXdScalar } },
10519   },
10520   {
10521     /* VEX_W_0F58_P_2  */
10522     { "vaddpd",         { XM, Vex, EXx } },
10523   },
10524   {
10525     /* VEX_W_0F58_P_3  */
10526     { "vaddsd",         { XMScalar, VexScalar, EXqScalar } },
10527   },
10528   {
10529     /* VEX_W_0F59_P_0  */
10530     { "vmulps",         { XM, Vex, EXx } },
10531   },
10532   {
10533     /* VEX_W_0F59_P_1  */
10534     { "vmulss",         { XMScalar, VexScalar, EXdScalar } },
10535   },
10536   {
10537     /* VEX_W_0F59_P_2  */
10538     { "vmulpd",         { XM, Vex, EXx } },
10539   },
10540   {
10541     /* VEX_W_0F59_P_3  */
10542     { "vmulsd",         { XMScalar, VexScalar, EXqScalar } },
10543   },
10544   {
10545     /* VEX_W_0F5A_P_0  */
10546     { "vcvtps2pd",      { XM, EXxmmq } },
10547   },
10548   {
10549     /* VEX_W_0F5A_P_1  */
10550     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar } },
10551   },
10552   {
10553     /* VEX_W_0F5A_P_3  */
10554     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar } },
10555   },
10556   {
10557     /* VEX_W_0F5B_P_0  */
10558     { "vcvtdq2ps",      { XM, EXx } },
10559   },
10560   {
10561     /* VEX_W_0F5B_P_1  */
10562     { "vcvttps2dq",     { XM, EXx } },
10563   },
10564   {
10565     /* VEX_W_0F5B_P_2  */
10566     { "vcvtps2dq",      { XM, EXx } },
10567   },
10568   {
10569     /* VEX_W_0F5C_P_0  */
10570     { "vsubps",         { XM, Vex, EXx } },
10571   },
10572   {
10573     /* VEX_W_0F5C_P_1  */
10574     { "vsubss",         { XMScalar, VexScalar, EXdScalar } },
10575   },
10576   {
10577     /* VEX_W_0F5C_P_2  */
10578     { "vsubpd",         { XM, Vex, EXx } },
10579   },
10580   {
10581     /* VEX_W_0F5C_P_3  */
10582     { "vsubsd",         { XMScalar, VexScalar, EXqScalar } },
10583   },
10584   {
10585     /* VEX_W_0F5D_P_0  */
10586     { "vminps",         { XM, Vex, EXx } },
10587   },
10588   {
10589     /* VEX_W_0F5D_P_1  */
10590     { "vminss",         { XMScalar, VexScalar, EXdScalar } },
10591   },
10592   {
10593     /* VEX_W_0F5D_P_2  */
10594     { "vminpd",         { XM, Vex, EXx } },
10595   },
10596   {
10597     /* VEX_W_0F5D_P_3  */
10598     { "vminsd",         { XMScalar, VexScalar, EXqScalar } },
10599   },
10600   {
10601     /* VEX_W_0F5E_P_0  */
10602     { "vdivps",         { XM, Vex, EXx } },
10603   },
10604   {
10605     /* VEX_W_0F5E_P_1  */
10606     { "vdivss",         { XMScalar, VexScalar, EXdScalar } },
10607   },
10608   {
10609     /* VEX_W_0F5E_P_2  */
10610     { "vdivpd",         { XM, Vex, EXx } },
10611   },
10612   {
10613     /* VEX_W_0F5E_P_3  */
10614     { "vdivsd",         { XMScalar, VexScalar, EXqScalar } },
10615   },
10616   {
10617     /* VEX_W_0F5F_P_0  */
10618     { "vmaxps",         { XM, Vex, EXx } },
10619   },
10620   {
10621     /* VEX_W_0F5F_P_1  */
10622     { "vmaxss",         { XMScalar, VexScalar, EXdScalar } },
10623   },
10624   {
10625     /* VEX_W_0F5F_P_2  */
10626     { "vmaxpd",         { XM, Vex, EXx } },
10627   },
10628   {
10629     /* VEX_W_0F5F_P_3  */
10630     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar } },
10631   },
10632   {
10633     /* VEX_W_0F60_P_2  */
10634     { "vpunpcklbw",     { XM, Vex, EXx } },
10635   },
10636   {
10637     /* VEX_W_0F61_P_2  */
10638     { "vpunpcklwd",     { XM, Vex, EXx } },
10639   },
10640   {
10641     /* VEX_W_0F62_P_2  */
10642     { "vpunpckldq",     { XM, Vex, EXx } },
10643   },
10644   {
10645     /* VEX_W_0F63_P_2  */
10646     { "vpacksswb",      { XM, Vex, EXx } },
10647   },
10648   {
10649     /* VEX_W_0F64_P_2  */
10650     { "vpcmpgtb",       { XM, Vex, EXx } },
10651   },
10652   {
10653     /* VEX_W_0F65_P_2  */
10654     { "vpcmpgtw",       { XM, Vex, EXx } },
10655   },
10656   {
10657     /* VEX_W_0F66_P_2  */
10658     { "vpcmpgtd",       { XM, Vex, EXx } },
10659   },
10660   {
10661     /* VEX_W_0F67_P_2  */
10662     { "vpackuswb",      { XM, Vex, EXx } },
10663   },
10664   {
10665     /* VEX_W_0F68_P_2  */
10666     { "vpunpckhbw",     { XM, Vex, EXx } },
10667   },
10668   {
10669     /* VEX_W_0F69_P_2  */
10670     { "vpunpckhwd",     { XM, Vex, EXx } },
10671   },
10672   {
10673     /* VEX_W_0F6A_P_2  */
10674     { "vpunpckhdq",     { XM, Vex, EXx } },
10675   },
10676   {
10677     /* VEX_W_0F6B_P_2  */
10678     { "vpackssdw",      { XM, Vex, EXx } },
10679   },
10680   {
10681     /* VEX_W_0F6C_P_2  */
10682     { "vpunpcklqdq",    { XM, Vex, EXx } },
10683   },
10684   {
10685     /* VEX_W_0F6D_P_2  */
10686     { "vpunpckhqdq",    { XM, Vex, EXx } },
10687   },
10688   {
10689     /* VEX_W_0F6F_P_1  */
10690     { "vmovdqu",        { XM, EXx } },
10691   },
10692   {
10693     /* VEX_W_0F6F_P_2  */
10694     { "vmovdqa",        { XM, EXx } },
10695   },
10696   {
10697     /* VEX_W_0F70_P_1 */
10698     { "vpshufhw",       { XM, EXx, Ib } },
10699   },
10700   {
10701     /* VEX_W_0F70_P_2 */
10702     { "vpshufd",        { XM, EXx, Ib } },
10703   },
10704   {
10705     /* VEX_W_0F70_P_3 */
10706     { "vpshuflw",       { XM, EXx, Ib } },
10707   },
10708   {
10709     /* VEX_W_0F71_R_2_P_2  */
10710     { "vpsrlw",         { Vex, XS, Ib } },
10711   },
10712   {
10713     /* VEX_W_0F71_R_4_P_2  */
10714     { "vpsraw",         { Vex, XS, Ib } },
10715   },
10716   {
10717     /* VEX_W_0F71_R_6_P_2  */
10718     { "vpsllw",         { Vex, XS, Ib } },
10719   },
10720   {
10721     /* VEX_W_0F72_R_2_P_2  */
10722     { "vpsrld",         { Vex, XS, Ib } },
10723   },
10724   {
10725     /* VEX_W_0F72_R_4_P_2  */
10726     { "vpsrad",         { Vex, XS, Ib } },
10727   },
10728   {
10729     /* VEX_W_0F72_R_6_P_2  */
10730     { "vpslld",         { Vex, XS, Ib } },
10731   },
10732   {
10733     /* VEX_W_0F73_R_2_P_2  */
10734     { "vpsrlq",         { Vex, XS, Ib } },
10735   },
10736   {
10737     /* VEX_W_0F73_R_3_P_2  */
10738     { "vpsrldq",        { Vex, XS, Ib } },
10739   },
10740   {
10741     /* VEX_W_0F73_R_6_P_2  */
10742     { "vpsllq",         { Vex, XS, Ib } },
10743   },
10744   {
10745     /* VEX_W_0F73_R_7_P_2  */
10746     { "vpslldq",        { Vex, XS, Ib } },
10747   },
10748   {
10749     /* VEX_W_0F74_P_2 */
10750     { "vpcmpeqb",       { XM, Vex, EXx } },
10751   },
10752   {
10753     /* VEX_W_0F75_P_2 */
10754     { "vpcmpeqw",       { XM, Vex, EXx } },
10755   },
10756   {
10757     /* VEX_W_0F76_P_2 */
10758     { "vpcmpeqd",       { XM, Vex, EXx } },
10759   },
10760   {
10761     /* VEX_W_0F77_P_0 */
10762     { "",               { VZERO } },
10763   },
10764   {
10765     /* VEX_W_0F7C_P_2 */
10766     { "vhaddpd",        { XM, Vex, EXx } },
10767   },
10768   {
10769     /* VEX_W_0F7C_P_3 */
10770     { "vhaddps",        { XM, Vex, EXx } },
10771   },
10772   {
10773     /* VEX_W_0F7D_P_2 */
10774     { "vhsubpd",        { XM, Vex, EXx } },
10775   },
10776   {
10777     /* VEX_W_0F7D_P_3 */
10778     { "vhsubps",        { XM, Vex, EXx } },
10779   },
10780   {
10781     /* VEX_W_0F7E_P_1 */
10782     { "vmovq",          { XMScalar, EXqScalar } },
10783   },
10784   {
10785     /* VEX_W_0F7F_P_1 */
10786     { "vmovdqu",        { EXxS, XM } },
10787   },
10788   {
10789     /* VEX_W_0F7F_P_2 */
10790     { "vmovdqa",        { EXxS, XM } },
10791   },
10792   {
10793     /* VEX_W_0F90_P_0_LEN_0 */
10794     { "kmovw",          { MaskG, MaskE } },
10795     { "kmovq",          { MaskG, MaskE } },
10796   },
10797   {
10798     /* VEX_W_0F90_P_2_LEN_0 */
10799     { "kmovb",          { MaskG, MaskBDE } },
10800     { "kmovd",          { MaskG, MaskBDE } },
10801   },
10802   {
10803     /* VEX_W_0F91_P_0_LEN_0 */
10804     { "kmovw",          { Ew, MaskG } },
10805     { "kmovq",          { Eq, MaskG } },
10806   },
10807   {
10808     /* VEX_W_0F91_P_2_LEN_0 */
10809     { "kmovb",          { Eb, MaskG } },
10810     { "kmovd",          { Ed, MaskG } },
10811   },
10812   {
10813     /* VEX_W_0F92_P_0_LEN_0 */
10814     { "kmovw",          { MaskG, Rdq } },
10815   },
10816   {
10817     /* VEX_W_0F92_P_2_LEN_0 */
10818     { "kmovb",          { MaskG, Rdq } },
10819   },
10820   {
10821     /* VEX_W_0F92_P_3_LEN_0 */
10822     { "kmovd",          { MaskG, Rdq } },
10823     { "kmovq",          { MaskG, Rdq } },
10824   },
10825   {
10826     /* VEX_W_0F93_P_0_LEN_0 */
10827     { "kmovw",          { Gdq, MaskR } },
10828   },
10829   {
10830     /* VEX_W_0F93_P_2_LEN_0 */
10831     { "kmovb",          { Gdq, MaskR } },
10832   },
10833   {
10834     /* VEX_W_0F93_P_3_LEN_0 */
10835     { "kmovd",          { Gdq, MaskR } },
10836     { "kmovq",          { Gdq, MaskR } },
10837   },
10838   {
10839     /* VEX_W_0F98_P_0_LEN_0 */
10840     { "kortestw",       { MaskG, MaskR } },
10841     { "kortestq",       { MaskG, MaskR } },
10842   },
10843   {
10844     /* VEX_W_0F98_P_2_LEN_0 */
10845     { "kortestb",       { MaskG, MaskR } },
10846     { "kortestd",       { MaskG, MaskR } },
10847   },
10848   {
10849     /* VEX_W_0F99_P_0_LEN_0 */
10850     { "ktestw", { MaskG, MaskR } },
10851     { "ktestq", { MaskG, MaskR } },
10852   },
10853   {
10854     /* VEX_W_0F99_P_2_LEN_0 */
10855     { "ktestb", { MaskG, MaskR } },
10856     { "ktestd", { MaskG, MaskR } },
10857   },
10858   {
10859     /* VEX_W_0FAE_R_2_M_0 */
10860     { "vldmxcsr",       { Md } },
10861   },
10862   {
10863     /* VEX_W_0FAE_R_3_M_0 */
10864     { "vstmxcsr",       { Md } },
10865   },
10866   {
10867     /* VEX_W_0FC2_P_0 */
10868     { "vcmpps",         { XM, Vex, EXx, VCMP } },
10869   },
10870   {
10871     /* VEX_W_0FC2_P_1 */
10872     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP } },
10873   },
10874   {
10875     /* VEX_W_0FC2_P_2 */
10876     { "vcmppd",         { XM, Vex, EXx, VCMP } },
10877   },
10878   {
10879     /* VEX_W_0FC2_P_3 */
10880     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP } },
10881   },
10882   {
10883     /* VEX_W_0FC4_P_2 */
10884     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
10885   },
10886   {
10887     /* VEX_W_0FC5_P_2 */
10888     { "vpextrw",        { Gdq, XS, Ib } },
10889   },
10890   {
10891     /* VEX_W_0FD0_P_2 */
10892     { "vaddsubpd",      { XM, Vex, EXx } },
10893   },
10894   {
10895     /* VEX_W_0FD0_P_3 */
10896     { "vaddsubps",      { XM, Vex, EXx } },
10897   },
10898   {
10899     /* VEX_W_0FD1_P_2 */
10900     { "vpsrlw",         { XM, Vex, EXxmm } },
10901   },
10902   {
10903     /* VEX_W_0FD2_P_2 */
10904     { "vpsrld",         { XM, Vex, EXxmm } },
10905   },
10906   {
10907     /* VEX_W_0FD3_P_2 */
10908     { "vpsrlq",         { XM, Vex, EXxmm } },
10909   },
10910   {
10911     /* VEX_W_0FD4_P_2 */
10912     { "vpaddq",         { XM, Vex, EXx } },
10913   },
10914   {
10915     /* VEX_W_0FD5_P_2 */
10916     { "vpmullw",        { XM, Vex, EXx } },
10917   },
10918   {
10919     /* VEX_W_0FD6_P_2 */
10920     { "vmovq",          { EXqScalarS, XMScalar } },
10921   },
10922   {
10923     /* VEX_W_0FD7_P_2_M_1 */
10924     { "vpmovmskb",      { Gdq, XS } },
10925   },
10926   {
10927     /* VEX_W_0FD8_P_2 */
10928     { "vpsubusb",       { XM, Vex, EXx } },
10929   },
10930   {
10931     /* VEX_W_0FD9_P_2 */
10932     { "vpsubusw",       { XM, Vex, EXx } },
10933   },
10934   {
10935     /* VEX_W_0FDA_P_2 */
10936     { "vpminub",        { XM, Vex, EXx } },
10937   },
10938   {
10939     /* VEX_W_0FDB_P_2 */
10940     { "vpand",          { XM, Vex, EXx } },
10941   },
10942   {
10943     /* VEX_W_0FDC_P_2 */
10944     { "vpaddusb",       { XM, Vex, EXx } },
10945   },
10946   {
10947     /* VEX_W_0FDD_P_2 */
10948     { "vpaddusw",       { XM, Vex, EXx } },
10949   },
10950   {
10951     /* VEX_W_0FDE_P_2 */
10952     { "vpmaxub",        { XM, Vex, EXx } },
10953   },
10954   {
10955     /* VEX_W_0FDF_P_2 */
10956     { "vpandn",         { XM, Vex, EXx } },
10957   },
10958   {
10959     /* VEX_W_0FE0_P_2  */
10960     { "vpavgb",         { XM, Vex, EXx } },
10961   },
10962   {
10963     /* VEX_W_0FE1_P_2  */
10964     { "vpsraw",         { XM, Vex, EXxmm } },
10965   },
10966   {
10967     /* VEX_W_0FE2_P_2  */
10968     { "vpsrad",         { XM, Vex, EXxmm } },
10969   },
10970   {
10971     /* VEX_W_0FE3_P_2  */
10972     { "vpavgw",         { XM, Vex, EXx } },
10973   },
10974   {
10975     /* VEX_W_0FE4_P_2  */
10976     { "vpmulhuw",       { XM, Vex, EXx } },
10977   },
10978   {
10979     /* VEX_W_0FE5_P_2  */
10980     { "vpmulhw",        { XM, Vex, EXx } },
10981   },
10982   {
10983     /* VEX_W_0FE6_P_1  */
10984     { "vcvtdq2pd",      { XM, EXxmmq } },
10985   },
10986   {
10987     /* VEX_W_0FE6_P_2  */
10988     { "vcvttpd2dq%XY",  { XMM, EXx } },
10989   },
10990   {
10991     /* VEX_W_0FE6_P_3  */
10992     { "vcvtpd2dq%XY",   { XMM, EXx } },
10993   },
10994   {
10995     /* VEX_W_0FE7_P_2_M_0 */
10996     { "vmovntdq",       { Mx, XM } },
10997   },
10998   {
10999     /* VEX_W_0FE8_P_2  */
11000     { "vpsubsb",        { XM, Vex, EXx } },
11001   },
11002   {
11003     /* VEX_W_0FE9_P_2  */
11004     { "vpsubsw",        { XM, Vex, EXx } },
11005   },
11006   {
11007     /* VEX_W_0FEA_P_2  */
11008     { "vpminsw",        { XM, Vex, EXx } },
11009   },
11010   {
11011     /* VEX_W_0FEB_P_2  */
11012     { "vpor",           { XM, Vex, EXx } },
11013   },
11014   {
11015     /* VEX_W_0FEC_P_2  */
11016     { "vpaddsb",        { XM, Vex, EXx } },
11017   },
11018   {
11019     /* VEX_W_0FED_P_2  */
11020     { "vpaddsw",        { XM, Vex, EXx } },
11021   },
11022   {
11023     /* VEX_W_0FEE_P_2  */
11024     { "vpmaxsw",        { XM, Vex, EXx } },
11025   },
11026   {
11027     /* VEX_W_0FEF_P_2  */
11028     { "vpxor",          { XM, Vex, EXx } },
11029   },
11030   {
11031     /* VEX_W_0FF0_P_3_M_0 */
11032     { "vlddqu",         { XM, M } },
11033   },
11034   {
11035     /* VEX_W_0FF1_P_2 */
11036     { "vpsllw",         { XM, Vex, EXxmm } },
11037   },
11038   {
11039     /* VEX_W_0FF2_P_2 */
11040     { "vpslld",         { XM, Vex, EXxmm } },
11041   },
11042   {
11043     /* VEX_W_0FF3_P_2 */
11044     { "vpsllq",         { XM, Vex, EXxmm } },
11045   },
11046   {
11047     /* VEX_W_0FF4_P_2 */
11048     { "vpmuludq",       { XM, Vex, EXx } },
11049   },
11050   {
11051     /* VEX_W_0FF5_P_2 */
11052     { "vpmaddwd",       { XM, Vex, EXx } },
11053   },
11054   {
11055     /* VEX_W_0FF6_P_2 */
11056     { "vpsadbw",        { XM, Vex, EXx } },
11057   },
11058   {
11059     /* VEX_W_0FF7_P_2 */
11060     { "vmaskmovdqu",    { XM, XS } },
11061   },
11062   {
11063     /* VEX_W_0FF8_P_2 */
11064     { "vpsubb",         { XM, Vex, EXx } },
11065   },
11066   {
11067     /* VEX_W_0FF9_P_2 */
11068     { "vpsubw",         { XM, Vex, EXx } },
11069   },
11070   {
11071     /* VEX_W_0FFA_P_2 */
11072     { "vpsubd",         { XM, Vex, EXx } },
11073   },
11074   {
11075     /* VEX_W_0FFB_P_2 */
11076     { "vpsubq",         { XM, Vex, EXx } },
11077   },
11078   {
11079     /* VEX_W_0FFC_P_2 */
11080     { "vpaddb",         { XM, Vex, EXx } },
11081   },
11082   {
11083     /* VEX_W_0FFD_P_2 */
11084     { "vpaddw",         { XM, Vex, EXx } },
11085   },
11086   {
11087     /* VEX_W_0FFE_P_2 */
11088     { "vpaddd",         { XM, Vex, EXx } },
11089   },
11090   {
11091     /* VEX_W_0F3800_P_2  */
11092     { "vpshufb",        { XM, Vex, EXx } },
11093   },
11094   {
11095     /* VEX_W_0F3801_P_2  */
11096     { "vphaddw",        { XM, Vex, EXx } },
11097   },
11098   {
11099     /* VEX_W_0F3802_P_2  */
11100     { "vphaddd",        { XM, Vex, EXx } },
11101   },
11102   {
11103     /* VEX_W_0F3803_P_2  */
11104     { "vphaddsw",       { XM, Vex, EXx } },
11105   },
11106   {
11107     /* VEX_W_0F3804_P_2  */
11108     { "vpmaddubsw",     { XM, Vex, EXx } },
11109   },
11110   {
11111     /* VEX_W_0F3805_P_2  */
11112     { "vphsubw",        { XM, Vex, EXx } },
11113   },
11114   {
11115     /* VEX_W_0F3806_P_2  */
11116     { "vphsubd",        { XM, Vex, EXx } },
11117   },
11118   {
11119     /* VEX_W_0F3807_P_2  */
11120     { "vphsubsw",       { XM, Vex, EXx } },
11121   },
11122   {
11123     /* VEX_W_0F3808_P_2  */
11124     { "vpsignb",        { XM, Vex, EXx } },
11125   },
11126   {
11127     /* VEX_W_0F3809_P_2  */
11128     { "vpsignw",        { XM, Vex, EXx } },
11129   },
11130   {
11131     /* VEX_W_0F380A_P_2  */
11132     { "vpsignd",        { XM, Vex, EXx } },
11133   },
11134   {
11135     /* VEX_W_0F380B_P_2  */
11136     { "vpmulhrsw",      { XM, Vex, EXx } },
11137   },
11138   {
11139     /* VEX_W_0F380C_P_2  */
11140     { "vpermilps",      { XM, Vex, EXx } },
11141   },
11142   {
11143     /* VEX_W_0F380D_P_2  */
11144     { "vpermilpd",      { XM, Vex, EXx } },
11145   },
11146   {
11147     /* VEX_W_0F380E_P_2  */
11148     { "vtestps",        { XM, EXx } },
11149   },
11150   {
11151     /* VEX_W_0F380F_P_2  */
11152     { "vtestpd",        { XM, EXx } },
11153   },
11154   {
11155     /* VEX_W_0F3816_P_2  */
11156     { "vpermps",        { XM, Vex, EXx } },
11157   },
11158   {
11159     /* VEX_W_0F3817_P_2 */
11160     { "vptest",         { XM, EXx } },
11161   },
11162   {
11163     /* VEX_W_0F3818_P_2 */
11164     { "vbroadcastss",   { XM, EXxmm_md } },
11165   },
11166   {
11167     /* VEX_W_0F3819_P_2 */
11168     { "vbroadcastsd",   { XM, EXxmm_mq } },
11169   },
11170   {
11171     /* VEX_W_0F381A_P_2_M_0 */
11172     { "vbroadcastf128", { XM, Mxmm } },
11173   },
11174   {
11175     /* VEX_W_0F381C_P_2 */
11176     { "vpabsb",         { XM, EXx } },
11177   },
11178   {
11179     /* VEX_W_0F381D_P_2 */
11180     { "vpabsw",         { XM, EXx } },
11181   },
11182   {
11183     /* VEX_W_0F381E_P_2 */
11184     { "vpabsd",         { XM, EXx } },
11185   },
11186   {
11187     /* VEX_W_0F3820_P_2 */
11188     { "vpmovsxbw",      { XM, EXxmmq } },
11189   },
11190   {
11191     /* VEX_W_0F3821_P_2 */
11192     { "vpmovsxbd",      { XM, EXxmmqd } },
11193   },
11194   {
11195     /* VEX_W_0F3822_P_2 */
11196     { "vpmovsxbq",      { XM, EXxmmdw } },
11197   },
11198   {
11199     /* VEX_W_0F3823_P_2 */
11200     { "vpmovsxwd",      { XM, EXxmmq } },
11201   },
11202   {
11203     /* VEX_W_0F3824_P_2 */
11204     { "vpmovsxwq",      { XM, EXxmmqd } },
11205   },
11206   {
11207     /* VEX_W_0F3825_P_2 */
11208     { "vpmovsxdq",      { XM, EXxmmq } },
11209   },
11210   {
11211     /* VEX_W_0F3828_P_2 */
11212     { "vpmuldq",        { XM, Vex, EXx } },
11213   },
11214   {
11215     /* VEX_W_0F3829_P_2 */
11216     { "vpcmpeqq",       { XM, Vex, EXx } },
11217   },
11218   {
11219     /* VEX_W_0F382A_P_2_M_0 */
11220     { "vmovntdqa",      { XM, Mx } },
11221   },
11222   {
11223     /* VEX_W_0F382B_P_2 */
11224     { "vpackusdw",      { XM, Vex, EXx } },
11225   },
11226   {
11227     /* VEX_W_0F382C_P_2_M_0 */
11228     { "vmaskmovps",     { XM, Vex, Mx } },
11229   },
11230   {
11231     /* VEX_W_0F382D_P_2_M_0 */
11232     { "vmaskmovpd",     { XM, Vex, Mx } },
11233   },
11234   {
11235     /* VEX_W_0F382E_P_2_M_0 */
11236     { "vmaskmovps",     { Mx, Vex, XM } },
11237   },
11238   {
11239     /* VEX_W_0F382F_P_2_M_0 */
11240     { "vmaskmovpd",     { Mx, Vex, XM } },
11241   },
11242   {
11243     /* VEX_W_0F3830_P_2 */
11244     { "vpmovzxbw",      { XM, EXxmmq } },
11245   },
11246   {
11247     /* VEX_W_0F3831_P_2 */
11248     { "vpmovzxbd",      { XM, EXxmmqd } },
11249   },
11250   {
11251     /* VEX_W_0F3832_P_2 */
11252     { "vpmovzxbq",      { XM, EXxmmdw } },
11253   },
11254   {
11255     /* VEX_W_0F3833_P_2 */
11256     { "vpmovzxwd",      { XM, EXxmmq } },
11257   },
11258   {
11259     /* VEX_W_0F3834_P_2 */
11260     { "vpmovzxwq",      { XM, EXxmmqd } },
11261   },
11262   {
11263     /* VEX_W_0F3835_P_2 */
11264     { "vpmovzxdq",      { XM, EXxmmq } },
11265   },
11266   {
11267     /* VEX_W_0F3836_P_2  */
11268     { "vpermd",         { XM, Vex, EXx } },
11269   },
11270   {
11271     /* VEX_W_0F3837_P_2 */
11272     { "vpcmpgtq",       { XM, Vex, EXx } },
11273   },
11274   {
11275     /* VEX_W_0F3838_P_2 */
11276     { "vpminsb",        { XM, Vex, EXx } },
11277   },
11278   {
11279     /* VEX_W_0F3839_P_2 */
11280     { "vpminsd",        { XM, Vex, EXx } },
11281   },
11282   {
11283     /* VEX_W_0F383A_P_2 */
11284     { "vpminuw",        { XM, Vex, EXx } },
11285   },
11286   {
11287     /* VEX_W_0F383B_P_2 */
11288     { "vpminud",        { XM, Vex, EXx } },
11289   },
11290   {
11291     /* VEX_W_0F383C_P_2 */
11292     { "vpmaxsb",        { XM, Vex, EXx } },
11293   },
11294   {
11295     /* VEX_W_0F383D_P_2 */
11296     { "vpmaxsd",        { XM, Vex, EXx } },
11297   },
11298   {
11299     /* VEX_W_0F383E_P_2 */
11300     { "vpmaxuw",        { XM, Vex, EXx } },
11301   },
11302   {
11303     /* VEX_W_0F383F_P_2 */
11304     { "vpmaxud",        { XM, Vex, EXx } },
11305   },
11306   {
11307     /* VEX_W_0F3840_P_2 */
11308     { "vpmulld",        { XM, Vex, EXx } },
11309   },
11310   {
11311     /* VEX_W_0F3841_P_2 */
11312     { "vphminposuw",    { XM, EXx } },
11313   },
11314   {
11315     /* VEX_W_0F3846_P_2 */
11316     { "vpsravd",        { XM, Vex, EXx } },
11317   },
11318   {
11319     /* VEX_W_0F3858_P_2 */
11320     { "vpbroadcastd", { XM, EXxmm_md } },
11321   },
11322   {
11323     /* VEX_W_0F3859_P_2 */
11324     { "vpbroadcastq",   { XM, EXxmm_mq } },
11325   },
11326   {
11327     /* VEX_W_0F385A_P_2_M_0 */
11328     { "vbroadcasti128", { XM, Mxmm } },
11329   },
11330   {
11331     /* VEX_W_0F3878_P_2 */
11332     { "vpbroadcastb",   { XM, EXxmm_mb } },
11333   },
11334   {
11335     /* VEX_W_0F3879_P_2 */
11336     { "vpbroadcastw",   { XM, EXxmm_mw } },
11337   },
11338   {
11339     /* VEX_W_0F38DB_P_2 */
11340     { "vaesimc",        { XM, EXx } },
11341   },
11342   {
11343     /* VEX_W_0F38DC_P_2 */
11344     { "vaesenc",        { XM, Vex128, EXx } },
11345   },
11346   {
11347     /* VEX_W_0F38DD_P_2 */
11348     { "vaesenclast",    { XM, Vex128, EXx } },
11349   },
11350   {
11351     /* VEX_W_0F38DE_P_2 */
11352     { "vaesdec",        { XM, Vex128, EXx } },
11353   },
11354   {
11355     /* VEX_W_0F38DF_P_2 */
11356     { "vaesdeclast",    { XM, Vex128, EXx } },
11357   },
11358   {
11359     /* VEX_W_0F3A00_P_2 */
11360     { Bad_Opcode },
11361     { "vpermq",         { XM, EXx, Ib } },
11362   },
11363   {
11364     /* VEX_W_0F3A01_P_2 */
11365     { Bad_Opcode },
11366     { "vpermpd",        { XM, EXx, Ib } },
11367   },
11368   {
11369     /* VEX_W_0F3A02_P_2 */
11370     { "vpblendd",       { XM, Vex, EXx, Ib } },
11371   },
11372   {
11373     /* VEX_W_0F3A04_P_2 */
11374     { "vpermilps",      { XM, EXx, Ib } },
11375   },
11376   {
11377     /* VEX_W_0F3A05_P_2 */
11378     { "vpermilpd",      { XM, EXx, Ib } },
11379   },
11380   {
11381     /* VEX_W_0F3A06_P_2 */
11382     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
11383   },
11384   {
11385     /* VEX_W_0F3A08_P_2 */
11386     { "vroundps",       { XM, EXx, Ib } },
11387   },
11388   {
11389     /* VEX_W_0F3A09_P_2 */
11390     { "vroundpd",       { XM, EXx, Ib } },
11391   },
11392   {
11393     /* VEX_W_0F3A0A_P_2 */
11394     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib } },
11395   },
11396   {
11397     /* VEX_W_0F3A0B_P_2 */
11398     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib } },
11399   },
11400   {
11401     /* VEX_W_0F3A0C_P_2 */
11402     { "vblendps",       { XM, Vex, EXx, Ib } },
11403   },
11404   {
11405     /* VEX_W_0F3A0D_P_2 */
11406     { "vblendpd",       { XM, Vex, EXx, Ib } },
11407   },
11408   {
11409     /* VEX_W_0F3A0E_P_2 */
11410     { "vpblendw",       { XM, Vex, EXx, Ib } },
11411   },
11412   {
11413     /* VEX_W_0F3A0F_P_2 */
11414     { "vpalignr",       { XM, Vex, EXx, Ib } },
11415   },
11416   {
11417     /* VEX_W_0F3A14_P_2 */
11418     { "vpextrb",        { Edqb, XM, Ib } },
11419   },
11420   {
11421     /* VEX_W_0F3A15_P_2 */
11422     { "vpextrw",        { Edqw, XM, Ib } },
11423   },
11424   {
11425     /* VEX_W_0F3A18_P_2 */
11426     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
11427   },
11428   {
11429     /* VEX_W_0F3A19_P_2 */
11430     { "vextractf128",   { EXxmm, XM, Ib } },
11431   },
11432   {
11433     /* VEX_W_0F3A20_P_2 */
11434     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
11435   },
11436   {
11437     /* VEX_W_0F3A21_P_2 */
11438     { "vinsertps",      { XM, Vex128, EXd, Ib } },
11439   },
11440   {
11441     /* VEX_W_0F3A30_P_2_LEN_0 */
11442     { "kshiftrb",       { MaskG, MaskR, Ib } },
11443     { "kshiftrw",       { MaskG, MaskR, Ib } },
11444   },
11445   {
11446     /* VEX_W_0F3A31_P_2_LEN_0 */
11447     { "kshiftrd",       { MaskG, MaskR, Ib } },
11448     { "kshiftrq",       { MaskG, MaskR, Ib } },
11449   },
11450   {
11451     /* VEX_W_0F3A32_P_2_LEN_0 */
11452     { "kshiftlb",       { MaskG, MaskR, Ib } },
11453     { "kshiftlw",       { MaskG, MaskR, Ib } },
11454   },
11455   {
11456     /* VEX_W_0F3A33_P_2_LEN_0 */
11457     { "kshiftld",       { MaskG, MaskR, Ib } },
11458     { "kshiftlq",       { MaskG, MaskR, Ib } },
11459   },
11460   {
11461     /* VEX_W_0F3A38_P_2 */
11462     { "vinserti128",    { XM, Vex256, EXxmm, Ib } },
11463   },
11464   {
11465     /* VEX_W_0F3A39_P_2 */
11466     { "vextracti128",   { EXxmm, XM, Ib } },
11467   },
11468   {
11469     /* VEX_W_0F3A40_P_2 */
11470     { "vdpps",          { XM, Vex, EXx, Ib } },
11471   },
11472   {
11473     /* VEX_W_0F3A41_P_2 */
11474     { "vdppd",          { XM, Vex128, EXx, Ib } },
11475   },
11476   {
11477     /* VEX_W_0F3A42_P_2 */
11478     { "vmpsadbw",       { XM, Vex, EXx, Ib } },
11479   },
11480   {
11481     /* VEX_W_0F3A44_P_2 */
11482     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
11483   },
11484   {
11485     /* VEX_W_0F3A46_P_2 */
11486     { "vperm2i128",     { XM, Vex256, EXx, Ib } },
11487   },
11488   {
11489     /* VEX_W_0F3A48_P_2 */
11490     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11491     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11492   },
11493   {
11494     /* VEX_W_0F3A49_P_2 */
11495     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11496     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11497   },
11498   {
11499     /* VEX_W_0F3A4A_P_2 */
11500     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
11501   },
11502   {
11503     /* VEX_W_0F3A4B_P_2 */
11504     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
11505   },
11506   {
11507     /* VEX_W_0F3A4C_P_2 */
11508     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 } },
11509   },
11510   {
11511     /* VEX_W_0F3A60_P_2 */
11512     { "vpcmpestrm",     { XM, EXx, Ib } },
11513   },
11514   {
11515     /* VEX_W_0F3A61_P_2 */
11516     { "vpcmpestri",     { XM, EXx, Ib } },
11517   },
11518   {
11519     /* VEX_W_0F3A62_P_2 */
11520     { "vpcmpistrm",     { XM, EXx, Ib } },
11521   },
11522   {
11523     /* VEX_W_0F3A63_P_2 */
11524     { "vpcmpistri",     { XM, EXx, Ib } },
11525   },
11526   {
11527     /* VEX_W_0F3ADF_P_2 */
11528     { "vaeskeygenassist", { XM, EXx, Ib } },
11529   },
11530 #define NEED_VEX_W_TABLE
11531 #include "i386-dis-evex.h"
11532 #undef NEED_VEX_W_TABLE
11533 };
11534
11535 static const struct dis386 mod_table[][2] = {
11536   {
11537     /* MOD_8D */
11538     { "leaS",           { Gv, M } },
11539   },
11540   {
11541     /* MOD_C6_REG_7 */
11542     { Bad_Opcode },
11543     { RM_TABLE (RM_C6_REG_7) },
11544   },
11545   {
11546     /* MOD_C7_REG_7 */
11547     { Bad_Opcode },
11548     { RM_TABLE (RM_C7_REG_7) },
11549   },
11550   {
11551     /* MOD_FF_REG_3 */
11552     { "Jcall{T|}", { indirEp } },
11553   },
11554   {
11555     /* MOD_FF_REG_5 */
11556     { "Jjmp{T|}", { indirEp } },
11557   },
11558   {
11559     /* MOD_0F01_REG_0 */
11560     { X86_64_TABLE (X86_64_0F01_REG_0) },
11561     { RM_TABLE (RM_0F01_REG_0) },
11562   },
11563   {
11564     /* MOD_0F01_REG_1 */
11565     { X86_64_TABLE (X86_64_0F01_REG_1) },
11566     { RM_TABLE (RM_0F01_REG_1) },
11567   },
11568   {
11569     /* MOD_0F01_REG_2 */
11570     { X86_64_TABLE (X86_64_0F01_REG_2) },
11571     { RM_TABLE (RM_0F01_REG_2) },
11572   },
11573   {
11574     /* MOD_0F01_REG_3 */
11575     { X86_64_TABLE (X86_64_0F01_REG_3) },
11576     { RM_TABLE (RM_0F01_REG_3) },
11577   },
11578   {
11579     /* MOD_0F01_REG_7 */
11580     { "invlpg",         { Mb } },
11581     { RM_TABLE (RM_0F01_REG_7) },
11582   },
11583   {
11584     /* MOD_0F12_PREFIX_0 */
11585     { "movlps",         { XM, EXq } },
11586     { "movhlps",        { XM, EXq } },
11587   },
11588   {
11589     /* MOD_0F13 */
11590     { "movlpX",         { EXq, XM } },
11591   },
11592   {
11593     /* MOD_0F16_PREFIX_0 */
11594     { "movhps",         { XM, EXq } },
11595     { "movlhps",        { XM, EXq } },
11596   },
11597   {
11598     /* MOD_0F17 */
11599     { "movhpX",         { EXq, XM } },
11600   },
11601   {
11602     /* MOD_0F18_REG_0 */
11603     { "prefetchnta",    { Mb } },
11604   },
11605   {
11606     /* MOD_0F18_REG_1 */
11607     { "prefetcht0",     { Mb } },
11608   },
11609   {
11610     /* MOD_0F18_REG_2 */
11611     { "prefetcht1",     { Mb } },
11612   },
11613   {
11614     /* MOD_0F18_REG_3 */
11615     { "prefetcht2",     { Mb } },
11616   },
11617   {
11618     /* MOD_0F18_REG_4 */
11619     { "nop/reserved",   { Mb } },
11620   },
11621   {
11622     /* MOD_0F18_REG_5 */
11623     { "nop/reserved",   { Mb } },
11624   },
11625   {
11626     /* MOD_0F18_REG_6 */
11627     { "nop/reserved",   { Mb } },
11628   },
11629   {
11630     /* MOD_0F18_REG_7 */
11631     { "nop/reserved",   { Mb } },
11632   },
11633   {
11634     /* MOD_0F1A_PREFIX_0 */
11635     { "bndldx",         { Gbnd, Ev_bnd } },
11636     { "nopQ",           { Ev } },
11637   },
11638   {
11639     /* MOD_0F1B_PREFIX_0 */
11640     { "bndstx",         { Ev_bnd, Gbnd } },
11641     { "nopQ",           { Ev } },
11642   },
11643   {
11644     /* MOD_0F1B_PREFIX_1 */
11645     { "bndmk",          { Gbnd, Ev_bnd } },
11646     { "nopQ",           { Ev } },
11647   },
11648   {
11649     /* MOD_0F24 */
11650     { Bad_Opcode },
11651     { "movL",           { Rd, Td } },
11652   },
11653   {
11654     /* MOD_0F26 */
11655     { Bad_Opcode },
11656     { "movL",           { Td, Rd } },
11657   },
11658   {
11659     /* MOD_0F2B_PREFIX_0 */
11660     {"movntps",         { Mx, XM } },
11661   },
11662   {
11663     /* MOD_0F2B_PREFIX_1 */
11664     {"movntss",         { Md, XM } },
11665   },
11666   {
11667     /* MOD_0F2B_PREFIX_2 */
11668     {"movntpd",         { Mx, XM } },
11669   },
11670   {
11671     /* MOD_0F2B_PREFIX_3 */
11672     {"movntsd",         { Mq, XM } },
11673   },
11674   {
11675     /* MOD_0F51 */
11676     { Bad_Opcode },
11677     { "movmskpX",       { Gdq, XS } },
11678   },
11679   {
11680     /* MOD_0F71_REG_2 */
11681     { Bad_Opcode },
11682     { "psrlw",          { MS, Ib } },
11683   },
11684   {
11685     /* MOD_0F71_REG_4 */
11686     { Bad_Opcode },
11687     { "psraw",          { MS, Ib } },
11688   },
11689   {
11690     /* MOD_0F71_REG_6 */
11691     { Bad_Opcode },
11692     { "psllw",          { MS, Ib } },
11693   },
11694   {
11695     /* MOD_0F72_REG_2 */
11696     { Bad_Opcode },
11697     { "psrld",          { MS, Ib } },
11698   },
11699   {
11700     /* MOD_0F72_REG_4 */
11701     { Bad_Opcode },
11702     { "psrad",          { MS, Ib } },
11703   },
11704   {
11705     /* MOD_0F72_REG_6 */
11706     { Bad_Opcode },
11707     { "pslld",          { MS, Ib } },
11708   },
11709   {
11710     /* MOD_0F73_REG_2 */
11711     { Bad_Opcode },
11712     { "psrlq",          { MS, Ib } },
11713   },
11714   {
11715     /* MOD_0F73_REG_3 */
11716     { Bad_Opcode },
11717     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11718   },
11719   {
11720     /* MOD_0F73_REG_6 */
11721     { Bad_Opcode },
11722     { "psllq",          { MS, Ib } },
11723   },
11724   {
11725     /* MOD_0F73_REG_7 */
11726     { Bad_Opcode },
11727     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11728   },
11729   {
11730     /* MOD_0FAE_REG_0 */
11731     { "fxsave",         { FXSAVE } },
11732     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11733   },
11734   {
11735     /* MOD_0FAE_REG_1 */
11736     { "fxrstor",        { FXSAVE } },
11737     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11738   },
11739   {
11740     /* MOD_0FAE_REG_2 */
11741     { "ldmxcsr",        { Md } },
11742     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11743   },
11744   {
11745     /* MOD_0FAE_REG_3 */
11746     { "stmxcsr",        { Md } },
11747     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11748   },
11749   {
11750     /* MOD_0FAE_REG_4 */
11751     { "xsave",          { FXSAVE } },
11752   },
11753   {
11754     /* MOD_0FAE_REG_5 */
11755     { "xrstor",         { FXSAVE } },
11756     { RM_TABLE (RM_0FAE_REG_5) },
11757   },
11758   {
11759     /* MOD_0FAE_REG_6 */
11760     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11761     { RM_TABLE (RM_0FAE_REG_6) },
11762   },
11763   {
11764     /* MOD_0FAE_REG_7 */
11765     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11766     { RM_TABLE (RM_0FAE_REG_7) },
11767   },
11768   {
11769     /* MOD_0FB2 */
11770     { "lssS",           { Gv, Mp } },
11771   },
11772   {
11773     /* MOD_0FB4 */
11774     { "lfsS",           { Gv, Mp } },
11775   },
11776   {
11777     /* MOD_0FB5 */
11778     { "lgsS",           { Gv, Mp } },
11779   },
11780   {
11781     /* MOD_0FC7_REG_3 */
11782     { "xrstors",                { FXSAVE } },
11783   },
11784   {
11785     /* MOD_0FC7_REG_4 */
11786     { "xsavec",         { FXSAVE } },
11787   },
11788   {
11789     /* MOD_0FC7_REG_5 */
11790     { "xsaves",         { FXSAVE } },
11791   },
11792   {
11793     /* MOD_0FC7_REG_6 */
11794     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11795     { "rdrand",         { Ev } },
11796   },
11797   {
11798     /* MOD_0FC7_REG_7 */
11799     { "vmptrst",        { Mq } },
11800     { "rdseed",         { Ev } },
11801   },
11802   {
11803     /* MOD_0FD7 */
11804     { Bad_Opcode },
11805     { "pmovmskb",       { Gdq, MS } },
11806   },
11807   {
11808     /* MOD_0FE7_PREFIX_2 */
11809     { "movntdq",        { Mx, XM } },
11810   },
11811   {
11812     /* MOD_0FF0_PREFIX_3 */
11813     { "lddqu",          { XM, M } },
11814   },
11815   {
11816     /* MOD_0F382A_PREFIX_2 */
11817     { "movntdqa",       { XM, Mx } },
11818   },
11819   {
11820     /* MOD_62_32BIT */
11821     { "bound{S|}",      { Gv, Ma } },
11822     { EVEX_TABLE (EVEX_0F) },
11823   },
11824   {
11825     /* MOD_C4_32BIT */
11826     { "lesS",           { Gv, Mp } },
11827     { VEX_C4_TABLE (VEX_0F) },
11828   },
11829   {
11830     /* MOD_C5_32BIT */
11831     { "ldsS",           { Gv, Mp } },
11832     { VEX_C5_TABLE (VEX_0F) },
11833   },
11834   {
11835     /* MOD_VEX_0F12_PREFIX_0 */
11836     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11837     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11838   },
11839   {
11840     /* MOD_VEX_0F13 */
11841     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11842   },
11843   {
11844     /* MOD_VEX_0F16_PREFIX_0 */
11845     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11846     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11847   },
11848   {
11849     /* MOD_VEX_0F17 */
11850     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11851   },
11852   {
11853     /* MOD_VEX_0F2B */
11854     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11855   },
11856   {
11857     /* MOD_VEX_0F50 */
11858     { Bad_Opcode },
11859     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11860   },
11861   {
11862     /* MOD_VEX_0F71_REG_2 */
11863     { Bad_Opcode },
11864     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11865   },
11866   {
11867     /* MOD_VEX_0F71_REG_4 */
11868     { Bad_Opcode },
11869     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11870   },
11871   {
11872     /* MOD_VEX_0F71_REG_6 */
11873     { Bad_Opcode },
11874     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11875   },
11876   {
11877     /* MOD_VEX_0F72_REG_2 */
11878     { Bad_Opcode },
11879     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11880   },
11881   {
11882     /* MOD_VEX_0F72_REG_4 */
11883     { Bad_Opcode },
11884     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11885   },
11886   {
11887     /* MOD_VEX_0F72_REG_6 */
11888     { Bad_Opcode },
11889     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11890   },
11891   {
11892     /* MOD_VEX_0F73_REG_2 */
11893     { Bad_Opcode },
11894     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11895   },
11896   {
11897     /* MOD_VEX_0F73_REG_3 */
11898     { Bad_Opcode },
11899     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11900   },
11901   {
11902     /* MOD_VEX_0F73_REG_6 */
11903     { Bad_Opcode },
11904     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11905   },
11906   {
11907     /* MOD_VEX_0F73_REG_7 */
11908     { Bad_Opcode },
11909     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11910   },
11911   {
11912     /* MOD_VEX_0FAE_REG_2 */
11913     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11914   },
11915   {
11916     /* MOD_VEX_0FAE_REG_3 */
11917     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11918   },
11919   {
11920     /* MOD_VEX_0FD7_PREFIX_2 */
11921     { Bad_Opcode },
11922     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11923   },
11924   {
11925     /* MOD_VEX_0FE7_PREFIX_2 */
11926     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11927   },
11928   {
11929     /* MOD_VEX_0FF0_PREFIX_3 */
11930     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11931   },
11932   {
11933     /* MOD_VEX_0F381A_PREFIX_2 */
11934     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11935   },
11936   {
11937     /* MOD_VEX_0F382A_PREFIX_2 */
11938     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11939   },
11940   {
11941     /* MOD_VEX_0F382C_PREFIX_2 */
11942     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11943   },
11944   {
11945     /* MOD_VEX_0F382D_PREFIX_2 */
11946     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11947   },
11948   {
11949     /* MOD_VEX_0F382E_PREFIX_2 */
11950     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11951   },
11952   {
11953     /* MOD_VEX_0F382F_PREFIX_2 */
11954     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11955   },
11956   {
11957     /* MOD_VEX_0F385A_PREFIX_2 */
11958     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11959   },
11960   {
11961     /* MOD_VEX_0F388C_PREFIX_2 */
11962     { "vpmaskmov%LW",   { XM, Vex, Mx } },
11963   },
11964   {
11965     /* MOD_VEX_0F388E_PREFIX_2 */
11966     { "vpmaskmov%LW",   { Mx, Vex, XM } },
11967   },
11968 #define NEED_MOD_TABLE
11969 #include "i386-dis-evex.h"
11970 #undef NEED_MOD_TABLE
11971 };
11972
11973 static const struct dis386 rm_table[][8] = {
11974   {
11975     /* RM_C6_REG_7 */
11976     { "xabort",         { Skip_MODRM, Ib } },
11977   },
11978   {
11979     /* RM_C7_REG_7 */
11980     { "xbeginT",        { Skip_MODRM, Jv } },
11981   },
11982   {
11983     /* RM_0F01_REG_0 */
11984     { Bad_Opcode },
11985     { "vmcall",         { Skip_MODRM } },
11986     { "vmlaunch",       { Skip_MODRM } },
11987     { "vmresume",       { Skip_MODRM } },
11988     { "vmxoff",         { Skip_MODRM } },
11989   },
11990   {
11991     /* RM_0F01_REG_1 */
11992     { "monitor",        { { OP_Monitor, 0 } } },
11993     { "mwait",          { { OP_Mwait, 0 } } },
11994     { "clac",           { Skip_MODRM } },
11995     { "stac",           { Skip_MODRM } },
11996     { Bad_Opcode },
11997     { Bad_Opcode },
11998     { Bad_Opcode },
11999     { "encls",          { Skip_MODRM } },
12000   },
12001   {
12002     /* RM_0F01_REG_2 */
12003     { "xgetbv",         { Skip_MODRM } },
12004     { "xsetbv",         { Skip_MODRM } },
12005     { Bad_Opcode },
12006     { Bad_Opcode },
12007     { "vmfunc",         { Skip_MODRM } },
12008     { "xend",           { Skip_MODRM } },
12009     { "xtest",          { Skip_MODRM } },
12010     { "enclu",          { Skip_MODRM } },
12011   },
12012   {
12013     /* RM_0F01_REG_3 */
12014     { "vmrun",          { Skip_MODRM } },
12015     { "vmmcall",        { Skip_MODRM } },
12016     { "vmload",         { Skip_MODRM } },
12017     { "vmsave",         { Skip_MODRM } },
12018     { "stgi",           { Skip_MODRM } },
12019     { "clgi",           { Skip_MODRM } },
12020     { "skinit",         { Skip_MODRM } },
12021     { "invlpga",        { Skip_MODRM } },
12022   },
12023   {
12024     /* RM_0F01_REG_7 */
12025     { "swapgs",         { Skip_MODRM } },
12026     { "rdtscp",         { Skip_MODRM } },
12027   },
12028   {
12029     /* RM_0FAE_REG_5 */
12030     { "lfence",         { Skip_MODRM } },
12031   },
12032   {
12033     /* RM_0FAE_REG_6 */
12034     { "mfence",         { Skip_MODRM } },
12035   },
12036   {
12037     /* RM_0FAE_REG_7 */
12038     { "sfence",         { Skip_MODRM } },
12039   },
12040 };
12041
12042 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12043
12044 /* We use the high bit to indicate different name for the same
12045    prefix.  */
12046 #define REP_PREFIX      (0xf3 | 0x100)
12047 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12048 #define XRELEASE_PREFIX (0xf3 | 0x400)
12049 #define BND_PREFIX      (0xf2 | 0x400)
12050
12051 static int
12052 ckprefix (void)
12053 {
12054   int newrex, i, length;
12055   rex = 0;
12056   rex_ignored = 0;
12057   prefixes = 0;
12058   used_prefixes = 0;
12059   rex_used = 0;
12060   last_lock_prefix = -1;
12061   last_repz_prefix = -1;
12062   last_repnz_prefix = -1;
12063   last_data_prefix = -1;
12064   last_addr_prefix = -1;
12065   last_rex_prefix = -1;
12066   last_seg_prefix = -1;
12067   fwait_prefix = -1;
12068   active_seg_prefix = 0;
12069   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12070     all_prefixes[i] = 0;
12071   i = 0;
12072   length = 0;
12073   /* The maximum instruction length is 15bytes.  */
12074   while (length < MAX_CODE_LENGTH - 1)
12075     {
12076       FETCH_DATA (the_info, codep + 1);
12077       newrex = 0;
12078       switch (*codep)
12079         {
12080         /* REX prefixes family.  */
12081         case 0x40:
12082         case 0x41:
12083         case 0x42:
12084         case 0x43:
12085         case 0x44:
12086         case 0x45:
12087         case 0x46:
12088         case 0x47:
12089         case 0x48:
12090         case 0x49:
12091         case 0x4a:
12092         case 0x4b:
12093         case 0x4c:
12094         case 0x4d:
12095         case 0x4e:
12096         case 0x4f:
12097           if (address_mode == mode_64bit)
12098             newrex = *codep;
12099           else
12100             return 1;
12101           last_rex_prefix = i;
12102           break;
12103         case 0xf3:
12104           prefixes |= PREFIX_REPZ;
12105           last_repz_prefix = i;
12106           break;
12107         case 0xf2:
12108           prefixes |= PREFIX_REPNZ;
12109           last_repnz_prefix = i;
12110           break;
12111         case 0xf0:
12112           prefixes |= PREFIX_LOCK;
12113           last_lock_prefix = i;
12114           break;
12115         case 0x2e:
12116           prefixes |= PREFIX_CS;
12117           last_seg_prefix = i;
12118           active_seg_prefix = PREFIX_CS;
12119           break;
12120         case 0x36:
12121           prefixes |= PREFIX_SS;
12122           last_seg_prefix = i;
12123           active_seg_prefix = PREFIX_SS;
12124           break;
12125         case 0x3e:
12126           prefixes |= PREFIX_DS;
12127           last_seg_prefix = i;
12128           active_seg_prefix = PREFIX_DS;
12129           break;
12130         case 0x26:
12131           prefixes |= PREFIX_ES;
12132           last_seg_prefix = i;
12133           active_seg_prefix = PREFIX_ES;
12134           break;
12135         case 0x64:
12136           prefixes |= PREFIX_FS;
12137           last_seg_prefix = i;
12138           active_seg_prefix = PREFIX_FS;
12139           break;
12140         case 0x65:
12141           prefixes |= PREFIX_GS;
12142           last_seg_prefix = i;
12143           active_seg_prefix = PREFIX_GS;
12144           break;
12145         case 0x66:
12146           prefixes |= PREFIX_DATA;
12147           last_data_prefix = i;
12148           break;
12149         case 0x67:
12150           prefixes |= PREFIX_ADDR;
12151           last_addr_prefix = i;
12152           break;
12153         case FWAIT_OPCODE:
12154           /* fwait is really an instruction.  If there are prefixes
12155              before the fwait, they belong to the fwait, *not* to the
12156              following instruction.  */
12157           fwait_prefix = i;
12158           if (prefixes || rex)
12159             {
12160               prefixes |= PREFIX_FWAIT;
12161               codep++;
12162               /* This ensures that the previous REX prefixes are noticed
12163                  as unused prefixes, as in the return case below.  */
12164               rex_used = rex;
12165               return 1;
12166             }
12167           prefixes = PREFIX_FWAIT;
12168           break;
12169         default:
12170           return 1;
12171         }
12172       /* Rex is ignored when followed by another prefix.  */
12173       if (rex)
12174         {
12175           rex_used = rex;
12176           return 1;
12177         }
12178       if (*codep != FWAIT_OPCODE)
12179         all_prefixes[i++] = *codep;
12180       rex = newrex;
12181       codep++;
12182       length++;
12183     }
12184   return 0;
12185 }
12186
12187 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12188    prefix byte.  */
12189
12190 static const char *
12191 prefix_name (int pref, int sizeflag)
12192 {
12193   static const char *rexes [16] =
12194     {
12195       "rex",            /* 0x40 */
12196       "rex.B",          /* 0x41 */
12197       "rex.X",          /* 0x42 */
12198       "rex.XB",         /* 0x43 */
12199       "rex.R",          /* 0x44 */
12200       "rex.RB",         /* 0x45 */
12201       "rex.RX",         /* 0x46 */
12202       "rex.RXB",        /* 0x47 */
12203       "rex.W",          /* 0x48 */
12204       "rex.WB",         /* 0x49 */
12205       "rex.WX",         /* 0x4a */
12206       "rex.WXB",        /* 0x4b */
12207       "rex.WR",         /* 0x4c */
12208       "rex.WRB",        /* 0x4d */
12209       "rex.WRX",        /* 0x4e */
12210       "rex.WRXB",       /* 0x4f */
12211     };
12212
12213   switch (pref)
12214     {
12215     /* REX prefixes family.  */
12216     case 0x40:
12217     case 0x41:
12218     case 0x42:
12219     case 0x43:
12220     case 0x44:
12221     case 0x45:
12222     case 0x46:
12223     case 0x47:
12224     case 0x48:
12225     case 0x49:
12226     case 0x4a:
12227     case 0x4b:
12228     case 0x4c:
12229     case 0x4d:
12230     case 0x4e:
12231     case 0x4f:
12232       return rexes [pref - 0x40];
12233     case 0xf3:
12234       return "repz";
12235     case 0xf2:
12236       return "repnz";
12237     case 0xf0:
12238       return "lock";
12239     case 0x2e:
12240       return "cs";
12241     case 0x36:
12242       return "ss";
12243     case 0x3e:
12244       return "ds";
12245     case 0x26:
12246       return "es";
12247     case 0x64:
12248       return "fs";
12249     case 0x65:
12250       return "gs";
12251     case 0x66:
12252       return (sizeflag & DFLAG) ? "data16" : "data32";
12253     case 0x67:
12254       if (address_mode == mode_64bit)
12255         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12256       else
12257         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12258     case FWAIT_OPCODE:
12259       return "fwait";
12260     case REP_PREFIX:
12261       return "rep";
12262     case XACQUIRE_PREFIX:
12263       return "xacquire";
12264     case XRELEASE_PREFIX:
12265       return "xrelease";
12266     case BND_PREFIX:
12267       return "bnd";
12268     default:
12269       return NULL;
12270     }
12271 }
12272
12273 static char op_out[MAX_OPERANDS][100];
12274 static int op_ad, op_index[MAX_OPERANDS];
12275 static int two_source_ops;
12276 static bfd_vma op_address[MAX_OPERANDS];
12277 static bfd_vma op_riprel[MAX_OPERANDS];
12278 static bfd_vma start_pc;
12279
12280 /*
12281  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12282  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12283  *   section of the "Virtual 8086 Mode" chapter.)
12284  * 'pc' should be the address of this instruction, it will
12285  *   be used to print the target address if this is a relative jump or call
12286  * The function returns the length of this instruction in bytes.
12287  */
12288
12289 static char intel_syntax;
12290 static char intel_mnemonic = !SYSV386_COMPAT;
12291 static char open_char;
12292 static char close_char;
12293 static char separator_char;
12294 static char scale_char;
12295
12296 /* Here for backwards compatibility.  When gdb stops using
12297    print_insn_i386_att and print_insn_i386_intel these functions can
12298    disappear, and print_insn_i386 be merged into print_insn.  */
12299 int
12300 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12301 {
12302   intel_syntax = 0;
12303
12304   return print_insn (pc, info);
12305 }
12306
12307 int
12308 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12309 {
12310   intel_syntax = 1;
12311
12312   return print_insn (pc, info);
12313 }
12314
12315 int
12316 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12317 {
12318   intel_syntax = -1;
12319
12320   return print_insn (pc, info);
12321 }
12322
12323 void
12324 print_i386_disassembler_options (FILE *stream)
12325 {
12326   fprintf (stream, _("\n\
12327 The following i386/x86-64 specific disassembler options are supported for use\n\
12328 with the -M switch (multiple options should be separated by commas):\n"));
12329
12330   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12331   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12332   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12333   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12334   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12335   fprintf (stream, _("  att-mnemonic\n"
12336                      "              Display instruction in AT&T mnemonic\n"));
12337   fprintf (stream, _("  intel-mnemonic\n"
12338                      "              Display instruction in Intel mnemonic\n"));
12339   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12340   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12341   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12342   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12343   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12344   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12345 }
12346
12347 /* Bad opcode.  */
12348 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12349
12350 /* Get a pointer to struct dis386 with a valid name.  */
12351
12352 static const struct dis386 *
12353 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12354 {
12355   int vindex, vex_table_index;
12356
12357   if (dp->name != NULL)
12358     return dp;
12359
12360   switch (dp->op[0].bytemode)
12361     {
12362     case USE_REG_TABLE:
12363       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12364       break;
12365
12366     case USE_MOD_TABLE:
12367       vindex = modrm.mod == 0x3 ? 1 : 0;
12368       dp = &mod_table[dp->op[1].bytemode][vindex];
12369       break;
12370
12371     case USE_RM_TABLE:
12372       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12373       break;
12374
12375     case USE_PREFIX_TABLE:
12376       if (need_vex)
12377         {
12378           /* The prefix in VEX is implicit.  */
12379           switch (vex.prefix)
12380             {
12381             case 0:
12382               vindex = 0;
12383               break;
12384             case REPE_PREFIX_OPCODE:
12385               vindex = 1;
12386               break;
12387             case DATA_PREFIX_OPCODE:
12388               vindex = 2;
12389               break;
12390             case REPNE_PREFIX_OPCODE:
12391               vindex = 3;
12392               break;
12393             default:
12394               abort ();
12395               break;
12396             }
12397         }
12398       else
12399         {
12400           int last_prefix = -1;
12401           int prefix = 0;
12402           vindex = 0;
12403           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12404              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12405              last one wins.  */
12406           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12407             {
12408               if (last_repz_prefix > last_repnz_prefix)
12409                 {
12410                   vindex = 1;
12411                   prefix = PREFIX_REPZ;
12412                   last_prefix = last_repz_prefix;
12413                 }
12414               else
12415                 {
12416                   vindex = 3;
12417                   prefix = PREFIX_REPNZ;
12418                   last_prefix = last_repnz_prefix;
12419                 }
12420
12421               /* Ignore the invalid index if it isn't mandatory.  */
12422               if (!mandatory_prefix
12423                   && (prefix_table[dp->op[1].bytemode][vindex].name
12424                       == NULL)
12425                   && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12426                       == 0))
12427                 vindex = 0;
12428             }
12429
12430           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12431             {
12432               vindex = 2;
12433               prefix = PREFIX_DATA;
12434               last_prefix = last_data_prefix;
12435             }
12436
12437           if (vindex != 0)
12438             {
12439               used_prefixes |= prefix;
12440               all_prefixes[last_prefix] = 0;
12441             }
12442         }
12443       dp = &prefix_table[dp->op[1].bytemode][vindex];
12444       break;
12445
12446     case USE_X86_64_TABLE:
12447       vindex = address_mode == mode_64bit ? 1 : 0;
12448       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12449       break;
12450
12451     case USE_3BYTE_TABLE:
12452       FETCH_DATA (info, codep + 2);
12453       vindex = *codep++;
12454       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12455       end_codep = codep;
12456       modrm.mod = (*codep >> 6) & 3;
12457       modrm.reg = (*codep >> 3) & 7;
12458       modrm.rm = *codep & 7;
12459       break;
12460
12461     case USE_VEX_LEN_TABLE:
12462       if (!need_vex)
12463         abort ();
12464
12465       switch (vex.length)
12466         {
12467         case 128:
12468           vindex = 0;
12469           break;
12470         case 256:
12471           vindex = 1;
12472           break;
12473         default:
12474           abort ();
12475           break;
12476         }
12477
12478       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12479       break;
12480
12481     case USE_XOP_8F_TABLE:
12482       FETCH_DATA (info, codep + 3);
12483       /* All bits in the REX prefix are ignored.  */
12484       rex_ignored = rex;
12485       rex = ~(*codep >> 5) & 0x7;
12486
12487       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12488       switch ((*codep & 0x1f))
12489         {
12490         default:
12491           dp = &bad_opcode;
12492           return dp;
12493         case 0x8:
12494           vex_table_index = XOP_08;
12495           break;
12496         case 0x9:
12497           vex_table_index = XOP_09;
12498           break;
12499         case 0xa:
12500           vex_table_index = XOP_0A;
12501           break;
12502         }
12503       codep++;
12504       vex.w = *codep & 0x80;
12505       if (vex.w && address_mode == mode_64bit)
12506         rex |= REX_W;
12507
12508       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12509       if (address_mode != mode_64bit
12510           && vex.register_specifier > 0x7)
12511         {
12512           dp = &bad_opcode;
12513           return dp;
12514         }
12515
12516       vex.length = (*codep & 0x4) ? 256 : 128;
12517       switch ((*codep & 0x3))
12518         {
12519         case 0:
12520           vex.prefix = 0;
12521           break;
12522         case 1:
12523           vex.prefix = DATA_PREFIX_OPCODE;
12524           break;
12525         case 2:
12526           vex.prefix = REPE_PREFIX_OPCODE;
12527           break;
12528         case 3:
12529           vex.prefix = REPNE_PREFIX_OPCODE;
12530           break;
12531         }
12532       need_vex = 1;
12533       need_vex_reg = 1;
12534       codep++;
12535       vindex = *codep++;
12536       dp = &xop_table[vex_table_index][vindex];
12537
12538       end_codep = codep;
12539       FETCH_DATA (info, codep + 1);
12540       modrm.mod = (*codep >> 6) & 3;
12541       modrm.reg = (*codep >> 3) & 7;
12542       modrm.rm = *codep & 7;
12543       break;
12544
12545     case USE_VEX_C4_TABLE:
12546       /* VEX prefix.  */
12547       FETCH_DATA (info, codep + 3);
12548       /* All bits in the REX prefix are ignored.  */
12549       rex_ignored = rex;
12550       rex = ~(*codep >> 5) & 0x7;
12551       switch ((*codep & 0x1f))
12552         {
12553         default:
12554           dp = &bad_opcode;
12555           return dp;
12556         case 0x1:
12557           vex_table_index = VEX_0F;
12558           break;
12559         case 0x2:
12560           vex_table_index = VEX_0F38;
12561           break;
12562         case 0x3:
12563           vex_table_index = VEX_0F3A;
12564           break;
12565         }
12566       codep++;
12567       vex.w = *codep & 0x80;
12568       if (vex.w && address_mode == mode_64bit)
12569         rex |= REX_W;
12570
12571       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12572       if (address_mode != mode_64bit
12573           && vex.register_specifier > 0x7)
12574         {
12575           dp = &bad_opcode;
12576           return dp;
12577         }
12578
12579       vex.length = (*codep & 0x4) ? 256 : 128;
12580       switch ((*codep & 0x3))
12581         {
12582         case 0:
12583           vex.prefix = 0;
12584           break;
12585         case 1:
12586           vex.prefix = DATA_PREFIX_OPCODE;
12587           break;
12588         case 2:
12589           vex.prefix = REPE_PREFIX_OPCODE;
12590           break;
12591         case 3:
12592           vex.prefix = REPNE_PREFIX_OPCODE;
12593           break;
12594         }
12595       need_vex = 1;
12596       need_vex_reg = 1;
12597       codep++;
12598       vindex = *codep++;
12599       dp = &vex_table[vex_table_index][vindex];
12600       end_codep = codep;
12601       /* There is no MODRM byte for VEX [82|77].  */
12602       if (vindex != 0x77 && vindex != 0x82)
12603         {
12604           FETCH_DATA (info, codep + 1);
12605           modrm.mod = (*codep >> 6) & 3;
12606           modrm.reg = (*codep >> 3) & 7;
12607           modrm.rm = *codep & 7;
12608         }
12609       break;
12610
12611     case USE_VEX_C5_TABLE:
12612       /* VEX prefix.  */
12613       FETCH_DATA (info, codep + 2);
12614       /* All bits in the REX prefix are ignored.  */
12615       rex_ignored = rex;
12616       rex = (*codep & 0x80) ? 0 : REX_R;
12617
12618       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12619       if (address_mode != mode_64bit
12620           && vex.register_specifier > 0x7)
12621         {
12622           dp = &bad_opcode;
12623           return dp;
12624         }
12625
12626       vex.w = 0;
12627
12628       vex.length = (*codep & 0x4) ? 256 : 128;
12629       switch ((*codep & 0x3))
12630         {
12631         case 0:
12632           vex.prefix = 0;
12633           break;
12634         case 1:
12635           vex.prefix = DATA_PREFIX_OPCODE;
12636           break;
12637         case 2:
12638           vex.prefix = REPE_PREFIX_OPCODE;
12639           break;
12640         case 3:
12641           vex.prefix = REPNE_PREFIX_OPCODE;
12642           break;
12643         }
12644       need_vex = 1;
12645       need_vex_reg = 1;
12646       codep++;
12647       vindex = *codep++;
12648       dp = &vex_table[dp->op[1].bytemode][vindex];
12649       end_codep = codep;
12650       /* There is no MODRM byte for VEX [82|77].  */
12651       if (vindex != 0x77 && vindex != 0x82)
12652         {
12653           FETCH_DATA (info, codep + 1);
12654           modrm.mod = (*codep >> 6) & 3;
12655           modrm.reg = (*codep >> 3) & 7;
12656           modrm.rm = *codep & 7;
12657         }
12658       break;
12659
12660     case USE_VEX_W_TABLE:
12661       if (!need_vex)
12662         abort ();
12663
12664       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12665       break;
12666
12667     case USE_EVEX_TABLE:
12668       two_source_ops = 0;
12669       /* EVEX prefix.  */
12670       vex.evex = 1;
12671       FETCH_DATA (info, codep + 4);
12672       /* All bits in the REX prefix are ignored.  */
12673       rex_ignored = rex;
12674       /* The first byte after 0x62.  */
12675       rex = ~(*codep >> 5) & 0x7;
12676       vex.r = *codep & 0x10;
12677       switch ((*codep & 0xf))
12678         {
12679         default:
12680           return &bad_opcode;
12681         case 0x1:
12682           vex_table_index = EVEX_0F;
12683           break;
12684         case 0x2:
12685           vex_table_index = EVEX_0F38;
12686           break;
12687         case 0x3:
12688           vex_table_index = EVEX_0F3A;
12689           break;
12690         }
12691
12692       /* The second byte after 0x62.  */
12693       codep++;
12694       vex.w = *codep & 0x80;
12695       if (vex.w && address_mode == mode_64bit)
12696         rex |= REX_W;
12697
12698       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12699       if (address_mode != mode_64bit)
12700         {
12701           /* In 16/32-bit mode silently ignore following bits.  */
12702           rex &= ~REX_B;
12703           vex.r = 1;
12704           vex.v = 1;
12705           vex.register_specifier &= 0x7;
12706         }
12707
12708       /* The U bit.  */
12709       if (!(*codep & 0x4))
12710         return &bad_opcode;
12711
12712       switch ((*codep & 0x3))
12713         {
12714         case 0:
12715           vex.prefix = 0;
12716           break;
12717         case 1:
12718           vex.prefix = DATA_PREFIX_OPCODE;
12719           break;
12720         case 2:
12721           vex.prefix = REPE_PREFIX_OPCODE;
12722           break;
12723         case 3:
12724           vex.prefix = REPNE_PREFIX_OPCODE;
12725           break;
12726         }
12727
12728       /* The third byte after 0x62.  */
12729       codep++;
12730
12731       /* Remember the static rounding bits.  */
12732       vex.ll = (*codep >> 5) & 3;
12733       vex.b = (*codep & 0x10) != 0;
12734
12735       vex.v = *codep & 0x8;
12736       vex.mask_register_specifier = *codep & 0x7;
12737       vex.zeroing = *codep & 0x80;
12738
12739       need_vex = 1;
12740       need_vex_reg = 1;
12741       codep++;
12742       vindex = *codep++;
12743       dp = &evex_table[vex_table_index][vindex];
12744       end_codep = codep;
12745       FETCH_DATA (info, codep + 1);
12746       modrm.mod = (*codep >> 6) & 3;
12747       modrm.reg = (*codep >> 3) & 7;
12748       modrm.rm = *codep & 7;
12749
12750       /* Set vector length.  */
12751       if (modrm.mod == 3 && vex.b)
12752         vex.length = 512;
12753       else
12754         {
12755           switch (vex.ll)
12756             {
12757             case 0x0:
12758               vex.length = 128;
12759               break;
12760             case 0x1:
12761               vex.length = 256;
12762               break;
12763             case 0x2:
12764               vex.length = 512;
12765               break;
12766             default:
12767               return &bad_opcode;
12768             }
12769         }
12770       break;
12771
12772     case 0:
12773       dp = &bad_opcode;
12774       break;
12775
12776     default:
12777       abort ();
12778     }
12779
12780   if (dp->name != NULL)
12781     return dp;
12782   else
12783     return get_valid_dis386 (dp, info);
12784 }
12785
12786 static void
12787 get_sib (disassemble_info *info, int sizeflag)
12788 {
12789   /* If modrm.mod == 3, operand must be register.  */
12790   if (need_modrm
12791       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12792       && modrm.mod != 3
12793       && modrm.rm == 4)
12794     {
12795       FETCH_DATA (info, codep + 2);
12796       sib.index = (codep [1] >> 3) & 7;
12797       sib.scale = (codep [1] >> 6) & 3;
12798       sib.base = codep [1] & 7;
12799     }
12800 }
12801
12802 static int
12803 print_insn (bfd_vma pc, disassemble_info *info)
12804 {
12805   const struct dis386 *dp;
12806   int i;
12807   char *op_txt[MAX_OPERANDS];
12808   int needcomma;
12809   int sizeflag, orig_sizeflag;
12810   const char *p;
12811   struct dis_private priv;
12812   int prefix_length;
12813
12814   priv.orig_sizeflag = AFLAG | DFLAG;
12815   if ((info->mach & bfd_mach_i386_i386) != 0)
12816     address_mode = mode_32bit;
12817   else if (info->mach == bfd_mach_i386_i8086)
12818     {
12819       address_mode = mode_16bit;
12820       priv.orig_sizeflag = 0;
12821     }
12822   else
12823     address_mode = mode_64bit;
12824
12825   if (intel_syntax == (char) -1)
12826     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12827
12828   for (p = info->disassembler_options; p != NULL; )
12829     {
12830       if (CONST_STRNEQ (p, "x86-64"))
12831         {
12832           address_mode = mode_64bit;
12833           priv.orig_sizeflag = AFLAG | DFLAG;
12834         }
12835       else if (CONST_STRNEQ (p, "i386"))
12836         {
12837           address_mode = mode_32bit;
12838           priv.orig_sizeflag = AFLAG | DFLAG;
12839         }
12840       else if (CONST_STRNEQ (p, "i8086"))
12841         {
12842           address_mode = mode_16bit;
12843           priv.orig_sizeflag = 0;
12844         }
12845       else if (CONST_STRNEQ (p, "intel"))
12846         {
12847           intel_syntax = 1;
12848           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12849             intel_mnemonic = 1;
12850         }
12851       else if (CONST_STRNEQ (p, "att"))
12852         {
12853           intel_syntax = 0;
12854           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12855             intel_mnemonic = 0;
12856         }
12857       else if (CONST_STRNEQ (p, "addr"))
12858         {
12859           if (address_mode == mode_64bit)
12860             {
12861               if (p[4] == '3' && p[5] == '2')
12862                 priv.orig_sizeflag &= ~AFLAG;
12863               else if (p[4] == '6' && p[5] == '4')
12864                 priv.orig_sizeflag |= AFLAG;
12865             }
12866           else
12867             {
12868               if (p[4] == '1' && p[5] == '6')
12869                 priv.orig_sizeflag &= ~AFLAG;
12870               else if (p[4] == '3' && p[5] == '2')
12871                 priv.orig_sizeflag |= AFLAG;
12872             }
12873         }
12874       else if (CONST_STRNEQ (p, "data"))
12875         {
12876           if (p[4] == '1' && p[5] == '6')
12877             priv.orig_sizeflag &= ~DFLAG;
12878           else if (p[4] == '3' && p[5] == '2')
12879             priv.orig_sizeflag |= DFLAG;
12880         }
12881       else if (CONST_STRNEQ (p, "suffix"))
12882         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12883
12884       p = strchr (p, ',');
12885       if (p != NULL)
12886         p++;
12887     }
12888
12889   if (intel_syntax)
12890     {
12891       names64 = intel_names64;
12892       names32 = intel_names32;
12893       names16 = intel_names16;
12894       names8 = intel_names8;
12895       names8rex = intel_names8rex;
12896       names_seg = intel_names_seg;
12897       names_mm = intel_names_mm;
12898       names_bnd = intel_names_bnd;
12899       names_xmm = intel_names_xmm;
12900       names_ymm = intel_names_ymm;
12901       names_zmm = intel_names_zmm;
12902       index64 = intel_index64;
12903       index32 = intel_index32;
12904       names_mask = intel_names_mask;
12905       index16 = intel_index16;
12906       open_char = '[';
12907       close_char = ']';
12908       separator_char = '+';
12909       scale_char = '*';
12910     }
12911   else
12912     {
12913       names64 = att_names64;
12914       names32 = att_names32;
12915       names16 = att_names16;
12916       names8 = att_names8;
12917       names8rex = att_names8rex;
12918       names_seg = att_names_seg;
12919       names_mm = att_names_mm;
12920       names_bnd = att_names_bnd;
12921       names_xmm = att_names_xmm;
12922       names_ymm = att_names_ymm;
12923       names_zmm = att_names_zmm;
12924       index64 = att_index64;
12925       index32 = att_index32;
12926       names_mask = att_names_mask;
12927       index16 = att_index16;
12928       open_char = '(';
12929       close_char =  ')';
12930       separator_char = ',';
12931       scale_char = ',';
12932     }
12933
12934   /* The output looks better if we put 7 bytes on a line, since that
12935      puts most long word instructions on a single line.  Use 8 bytes
12936      for Intel L1OM.  */
12937   if ((info->mach & bfd_mach_l1om) != 0)
12938     info->bytes_per_line = 8;
12939   else
12940     info->bytes_per_line = 7;
12941
12942   info->private_data = &priv;
12943   priv.max_fetched = priv.the_buffer;
12944   priv.insn_start = pc;
12945
12946   obuf[0] = 0;
12947   for (i = 0; i < MAX_OPERANDS; ++i)
12948     {
12949       op_out[i][0] = 0;
12950       op_index[i] = -1;
12951     }
12952
12953   the_info = info;
12954   start_pc = pc;
12955   start_codep = priv.the_buffer;
12956   codep = priv.the_buffer;
12957
12958   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12959     {
12960       const char *name;
12961
12962       /* Getting here means we tried for data but didn't get it.  That
12963          means we have an incomplete instruction of some sort.  Just
12964          print the first byte as a prefix or a .byte pseudo-op.  */
12965       if (codep > priv.the_buffer)
12966         {
12967           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12968           if (name != NULL)
12969             (*info->fprintf_func) (info->stream, "%s", name);
12970           else
12971             {
12972               /* Just print the first byte as a .byte instruction.  */
12973               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12974                                      (unsigned int) priv.the_buffer[0]);
12975             }
12976
12977           return 1;
12978         }
12979
12980       return -1;
12981     }
12982
12983   obufp = obuf;
12984   sizeflag = priv.orig_sizeflag;
12985
12986   if (!ckprefix () || rex_used)
12987     {
12988       /* Too many prefixes or unused REX prefixes.  */
12989       for (i = 0;
12990            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12991            i++)
12992         (*info->fprintf_func) (info->stream, "%s%s",
12993                                i == 0 ? "" : " ",
12994                                prefix_name (all_prefixes[i], sizeflag));
12995       return i;
12996     }
12997
12998   insn_codep = codep;
12999
13000   FETCH_DATA (info, codep + 1);
13001   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13002
13003   if (((prefixes & PREFIX_FWAIT)
13004        && ((*codep < 0xd8) || (*codep > 0xdf))))
13005     {
13006       /* Handle prefixes before fwait.  */
13007       for (i = 0; i < fwait_prefix && all_prefixes[i];
13008            i++)
13009         (*info->fprintf_func) (info->stream, "%s ",
13010                                prefix_name (all_prefixes[i], sizeflag));
13011       (*info->fprintf_func) (info->stream, "fwait");
13012       return i + 1;
13013     }
13014
13015   if (*codep == 0x0f)
13016     {
13017       unsigned char threebyte;
13018       FETCH_DATA (info, codep + 2);
13019       threebyte = *++codep;
13020       dp = &dis386_twobyte[threebyte];
13021       need_modrm = twobyte_has_modrm[*codep];
13022       mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13023       codep++;
13024     }
13025   else
13026     {
13027       dp = &dis386[*codep];
13028       need_modrm = onebyte_has_modrm[*codep];
13029       mandatory_prefix = 0;
13030       codep++;
13031     }
13032
13033   /* Save sizeflag for printing the extra prefixes later before updating
13034      it for mnemonic and operand processing.  The prefix names depend
13035      only on the address mode.  */
13036   orig_sizeflag = sizeflag;
13037   if (prefixes & PREFIX_ADDR)
13038     sizeflag ^= AFLAG;
13039   if ((prefixes & PREFIX_DATA))
13040     sizeflag ^= DFLAG;
13041
13042   end_codep = codep;
13043   if (need_modrm)
13044     {
13045       FETCH_DATA (info, codep + 1);
13046       modrm.mod = (*codep >> 6) & 3;
13047       modrm.reg = (*codep >> 3) & 7;
13048       modrm.rm = *codep & 7;
13049     }
13050
13051   need_vex = 0;
13052   need_vex_reg = 0;
13053   vex_w_done = 0;
13054   vex.evex = 0;
13055
13056   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13057     {
13058       get_sib (info, sizeflag);
13059       dofloat (sizeflag);
13060     }
13061   else
13062     {
13063       dp = get_valid_dis386 (dp, info);
13064       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13065         {
13066           get_sib (info, sizeflag);
13067           for (i = 0; i < MAX_OPERANDS; ++i)
13068             {
13069               obufp = op_out[i];
13070               op_ad = MAX_OPERANDS - 1 - i;
13071               if (dp->op[i].rtn)
13072                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13073               /* For EVEX instruction after the last operand masking
13074                  should be printed.  */
13075               if (i == 0 && vex.evex)
13076                 {
13077                   /* Don't print {%k0}.  */
13078                   if (vex.mask_register_specifier)
13079                     {
13080                       oappend ("{");
13081                       oappend (names_mask[vex.mask_register_specifier]);
13082                       oappend ("}");
13083                     }
13084                   if (vex.zeroing)
13085                     oappend ("{z}");
13086                 }
13087             }
13088         }
13089     }
13090
13091   /* Check if the REX prefix is used.  */
13092   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13093     all_prefixes[last_rex_prefix] = 0;
13094
13095   /* Check if the SEG prefix is used.  */
13096   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13097                    | PREFIX_FS | PREFIX_GS)) != 0
13098       && (used_prefixes & active_seg_prefix) != 0)
13099     all_prefixes[last_seg_prefix] = 0;
13100
13101   /* Check if the ADDR prefix is used.  */
13102   if ((prefixes & PREFIX_ADDR) != 0
13103       && (used_prefixes & PREFIX_ADDR) != 0)
13104     all_prefixes[last_addr_prefix] = 0;
13105
13106   /* Check if the DATA prefix is used.  */
13107   if ((prefixes & PREFIX_DATA) != 0
13108       && (used_prefixes & PREFIX_DATA) != 0)
13109     all_prefixes[last_data_prefix] = 0;
13110
13111   /* Print the extra prefixes.  */
13112   prefix_length = 0;
13113   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13114     if (all_prefixes[i])
13115       {
13116         const char *name;
13117         name = prefix_name (all_prefixes[i], orig_sizeflag);
13118         if (name == NULL)
13119           abort ();
13120         prefix_length += strlen (name) + 1;
13121         (*info->fprintf_func) (info->stream, "%s ", name);
13122       }
13123
13124   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13125      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13126      used by putop and MMX/SSE operand and may be overriden by the
13127      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13128      separately.  */
13129   if (mandatory_prefix
13130       && dp != &bad_opcode
13131       && (((prefixes
13132             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13133            && (used_prefixes
13134                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13135           || ((((prefixes
13136                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13137                 == PREFIX_DATA)
13138                && (used_prefixes & PREFIX_DATA) == 0))))
13139     {
13140       (*info->fprintf_func) (info->stream, "(bad)");
13141       return end_codep - priv.the_buffer;
13142     }
13143
13144   /* Check maximum code length.  */
13145   if ((codep - start_codep) > MAX_CODE_LENGTH)
13146     {
13147       (*info->fprintf_func) (info->stream, "(bad)");
13148       return MAX_CODE_LENGTH;
13149     }
13150
13151   obufp = mnemonicendp;
13152   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13153     oappend (" ");
13154   oappend (" ");
13155   (*info->fprintf_func) (info->stream, "%s", obuf);
13156
13157   /* The enter and bound instructions are printed with operands in the same
13158      order as the intel book; everything else is printed in reverse order.  */
13159   if (intel_syntax || two_source_ops)
13160     {
13161       bfd_vma riprel;
13162
13163       for (i = 0; i < MAX_OPERANDS; ++i)
13164         op_txt[i] = op_out[i];
13165
13166       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13167         {
13168           op_ad = op_index[i];
13169           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13170           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13171           riprel = op_riprel[i];
13172           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13173           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13174         }
13175     }
13176   else
13177     {
13178       for (i = 0; i < MAX_OPERANDS; ++i)
13179         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13180     }
13181
13182   needcomma = 0;
13183   for (i = 0; i < MAX_OPERANDS; ++i)
13184     if (*op_txt[i])
13185       {
13186         if (needcomma)
13187           (*info->fprintf_func) (info->stream, ",");
13188         if (op_index[i] != -1 && !op_riprel[i])
13189           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13190         else
13191           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13192         needcomma = 1;
13193       }
13194
13195   for (i = 0; i < MAX_OPERANDS; i++)
13196     if (op_index[i] != -1 && op_riprel[i])
13197       {
13198         (*info->fprintf_func) (info->stream, "        # ");
13199         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13200                                                 + op_address[op_index[i]]), info);
13201         break;
13202       }
13203   return codep - priv.the_buffer;
13204 }
13205
13206 static const char *float_mem[] = {
13207   /* d8 */
13208   "fadd{s|}",
13209   "fmul{s|}",
13210   "fcom{s|}",
13211   "fcomp{s|}",
13212   "fsub{s|}",
13213   "fsubr{s|}",
13214   "fdiv{s|}",
13215   "fdivr{s|}",
13216   /* d9 */
13217   "fld{s|}",
13218   "(bad)",
13219   "fst{s|}",
13220   "fstp{s|}",
13221   "fldenvIC",
13222   "fldcw",
13223   "fNstenvIC",
13224   "fNstcw",
13225   /* da */
13226   "fiadd{l|}",
13227   "fimul{l|}",
13228   "ficom{l|}",
13229   "ficomp{l|}",
13230   "fisub{l|}",
13231   "fisubr{l|}",
13232   "fidiv{l|}",
13233   "fidivr{l|}",
13234   /* db */
13235   "fild{l|}",
13236   "fisttp{l|}",
13237   "fist{l|}",
13238   "fistp{l|}",
13239   "(bad)",
13240   "fld{t||t|}",
13241   "(bad)",
13242   "fstp{t||t|}",
13243   /* dc */
13244   "fadd{l|}",
13245   "fmul{l|}",
13246   "fcom{l|}",
13247   "fcomp{l|}",
13248   "fsub{l|}",
13249   "fsubr{l|}",
13250   "fdiv{l|}",
13251   "fdivr{l|}",
13252   /* dd */
13253   "fld{l|}",
13254   "fisttp{ll|}",
13255   "fst{l||}",
13256   "fstp{l|}",
13257   "frstorIC",
13258   "(bad)",
13259   "fNsaveIC",
13260   "fNstsw",
13261   /* de */
13262   "fiadd",
13263   "fimul",
13264   "ficom",
13265   "ficomp",
13266   "fisub",
13267   "fisubr",
13268   "fidiv",
13269   "fidivr",
13270   /* df */
13271   "fild",
13272   "fisttp",
13273   "fist",
13274   "fistp",
13275   "fbld",
13276   "fild{ll|}",
13277   "fbstp",
13278   "fistp{ll|}",
13279 };
13280
13281 static const unsigned char float_mem_mode[] = {
13282   /* d8 */
13283   d_mode,
13284   d_mode,
13285   d_mode,
13286   d_mode,
13287   d_mode,
13288   d_mode,
13289   d_mode,
13290   d_mode,
13291   /* d9 */
13292   d_mode,
13293   0,
13294   d_mode,
13295   d_mode,
13296   0,
13297   w_mode,
13298   0,
13299   w_mode,
13300   /* da */
13301   d_mode,
13302   d_mode,
13303   d_mode,
13304   d_mode,
13305   d_mode,
13306   d_mode,
13307   d_mode,
13308   d_mode,
13309   /* db */
13310   d_mode,
13311   d_mode,
13312   d_mode,
13313   d_mode,
13314   0,
13315   t_mode,
13316   0,
13317   t_mode,
13318   /* dc */
13319   q_mode,
13320   q_mode,
13321   q_mode,
13322   q_mode,
13323   q_mode,
13324   q_mode,
13325   q_mode,
13326   q_mode,
13327   /* dd */
13328   q_mode,
13329   q_mode,
13330   q_mode,
13331   q_mode,
13332   0,
13333   0,
13334   0,
13335   w_mode,
13336   /* de */
13337   w_mode,
13338   w_mode,
13339   w_mode,
13340   w_mode,
13341   w_mode,
13342   w_mode,
13343   w_mode,
13344   w_mode,
13345   /* df */
13346   w_mode,
13347   w_mode,
13348   w_mode,
13349   w_mode,
13350   t_mode,
13351   q_mode,
13352   t_mode,
13353   q_mode
13354 };
13355
13356 #define ST { OP_ST, 0 }
13357 #define STi { OP_STi, 0 }
13358
13359 #define FGRPd9_2 NULL, { { NULL, 0 } }
13360 #define FGRPd9_4 NULL, { { NULL, 1 } }
13361 #define FGRPd9_5 NULL, { { NULL, 2 } }
13362 #define FGRPd9_6 NULL, { { NULL, 3 } }
13363 #define FGRPd9_7 NULL, { { NULL, 4 } }
13364 #define FGRPda_5 NULL, { { NULL, 5 } }
13365 #define FGRPdb_4 NULL, { { NULL, 6 } }
13366 #define FGRPde_3 NULL, { { NULL, 7 } }
13367 #define FGRPdf_4 NULL, { { NULL, 8 } }
13368
13369 static const struct dis386 float_reg[][8] = {
13370   /* d8 */
13371   {
13372     { "fadd",   { ST, STi } },
13373     { "fmul",   { ST, STi } },
13374     { "fcom",   { STi } },
13375     { "fcomp",  { STi } },
13376     { "fsub",   { ST, STi } },
13377     { "fsubr",  { ST, STi } },
13378     { "fdiv",   { ST, STi } },
13379     { "fdivr",  { ST, STi } },
13380   },
13381   /* d9 */
13382   {
13383     { "fld",    { STi } },
13384     { "fxch",   { STi } },
13385     { FGRPd9_2 },
13386     { Bad_Opcode },
13387     { FGRPd9_4 },
13388     { FGRPd9_5 },
13389     { FGRPd9_6 },
13390     { FGRPd9_7 },
13391   },
13392   /* da */
13393   {
13394     { "fcmovb", { ST, STi } },
13395     { "fcmove", { ST, STi } },
13396     { "fcmovbe",{ ST, STi } },
13397     { "fcmovu", { ST, STi } },
13398     { Bad_Opcode },
13399     { FGRPda_5 },
13400     { Bad_Opcode },
13401     { Bad_Opcode },
13402   },
13403   /* db */
13404   {
13405     { "fcmovnb",{ ST, STi } },
13406     { "fcmovne",{ ST, STi } },
13407     { "fcmovnbe",{ ST, STi } },
13408     { "fcmovnu",{ ST, STi } },
13409     { FGRPdb_4 },
13410     { "fucomi", { ST, STi } },
13411     { "fcomi",  { ST, STi } },
13412     { Bad_Opcode },
13413   },
13414   /* dc */
13415   {
13416     { "fadd",   { STi, ST } },
13417     { "fmul",   { STi, ST } },
13418     { Bad_Opcode },
13419     { Bad_Opcode },
13420     { "fsub!M", { STi, ST } },
13421     { "fsubM",  { STi, ST } },
13422     { "fdiv!M", { STi, ST } },
13423     { "fdivM",  { STi, ST } },
13424   },
13425   /* dd */
13426   {
13427     { "ffree",  { STi } },
13428     { Bad_Opcode },
13429     { "fst",    { STi } },
13430     { "fstp",   { STi } },
13431     { "fucom",  { STi } },
13432     { "fucomp", { STi } },
13433     { Bad_Opcode },
13434     { Bad_Opcode },
13435   },
13436   /* de */
13437   {
13438     { "faddp",  { STi, ST } },
13439     { "fmulp",  { STi, ST } },
13440     { Bad_Opcode },
13441     { FGRPde_3 },
13442     { "fsub!Mp", { STi, ST } },
13443     { "fsubMp", { STi, ST } },
13444     { "fdiv!Mp", { STi, ST } },
13445     { "fdivMp", { STi, ST } },
13446   },
13447   /* df */
13448   {
13449     { "ffreep", { STi } },
13450     { Bad_Opcode },
13451     { Bad_Opcode },
13452     { Bad_Opcode },
13453     { FGRPdf_4 },
13454     { "fucomip", { ST, STi } },
13455     { "fcomip", { ST, STi } },
13456     { Bad_Opcode },
13457   },
13458 };
13459
13460 static char *fgrps[][8] = {
13461   /* d9_2  0 */
13462   {
13463     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13464   },
13465
13466   /* d9_4  1 */
13467   {
13468     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13469   },
13470
13471   /* d9_5  2 */
13472   {
13473     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13474   },
13475
13476   /* d9_6  3 */
13477   {
13478     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13479   },
13480
13481   /* d9_7  4 */
13482   {
13483     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13484   },
13485
13486   /* da_5  5 */
13487   {
13488     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13489   },
13490
13491   /* db_4  6 */
13492   {
13493     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13494     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13495   },
13496
13497   /* de_3  7 */
13498   {
13499     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13500   },
13501
13502   /* df_4  8 */
13503   {
13504     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13505   },
13506 };
13507
13508 static void
13509 swap_operand (void)
13510 {
13511   mnemonicendp[0] = '.';
13512   mnemonicendp[1] = 's';
13513   mnemonicendp += 2;
13514 }
13515
13516 static void
13517 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13518                int sizeflag ATTRIBUTE_UNUSED)
13519 {
13520   /* Skip mod/rm byte.  */
13521   MODRM_CHECK;
13522   codep++;
13523 }
13524
13525 static void
13526 dofloat (int sizeflag)
13527 {
13528   const struct dis386 *dp;
13529   unsigned char floatop;
13530
13531   floatop = codep[-1];
13532
13533   if (modrm.mod != 3)
13534     {
13535       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13536
13537       putop (float_mem[fp_indx], sizeflag);
13538       obufp = op_out[0];
13539       op_ad = 2;
13540       OP_E (float_mem_mode[fp_indx], sizeflag);
13541       return;
13542     }
13543   /* Skip mod/rm byte.  */
13544   MODRM_CHECK;
13545   codep++;
13546
13547   dp = &float_reg[floatop - 0xd8][modrm.reg];
13548   if (dp->name == NULL)
13549     {
13550       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13551
13552       /* Instruction fnstsw is only one with strange arg.  */
13553       if (floatop == 0xdf && codep[-1] == 0xe0)
13554         strcpy (op_out[0], names16[0]);
13555     }
13556   else
13557     {
13558       putop (dp->name, sizeflag);
13559
13560       obufp = op_out[0];
13561       op_ad = 2;
13562       if (dp->op[0].rtn)
13563         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13564
13565       obufp = op_out[1];
13566       op_ad = 1;
13567       if (dp->op[1].rtn)
13568         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13569     }
13570 }
13571
13572 /* Like oappend (below), but S is a string starting with '%'.
13573    In Intel syntax, the '%' is elided.  */
13574 static void
13575 oappend_maybe_intel (const char *s)
13576 {
13577   oappend (s + intel_syntax);
13578 }
13579
13580 static void
13581 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13582 {
13583   oappend_maybe_intel ("%st");
13584 }
13585
13586 static void
13587 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13588 {
13589   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13590   oappend_maybe_intel (scratchbuf);
13591 }
13592
13593 /* Capital letters in template are macros.  */
13594 static int
13595 putop (const char *in_template, int sizeflag)
13596 {
13597   const char *p;
13598   int alt = 0;
13599   int cond = 1;
13600   unsigned int l = 0, len = 1;
13601   char last[4];
13602
13603 #define SAVE_LAST(c)                    \
13604   if (l < len && l < sizeof (last))     \
13605     last[l++] = c;                      \
13606   else                                  \
13607     abort ();
13608
13609   for (p = in_template; *p; p++)
13610     {
13611       switch (*p)
13612         {
13613         default:
13614           *obufp++ = *p;
13615           break;
13616         case '%':
13617           len++;
13618           break;
13619         case '!':
13620           cond = 0;
13621           break;
13622         case '{':
13623           alt = 0;
13624           if (intel_syntax)
13625             {
13626               while (*++p != '|')
13627                 if (*p == '}' || *p == '\0')
13628                   abort ();
13629             }
13630           /* Fall through.  */
13631         case 'I':
13632           alt = 1;
13633           continue;
13634         case '|':
13635           while (*++p != '}')
13636             {
13637               if (*p == '\0')
13638                 abort ();
13639             }
13640           break;
13641         case '}':
13642           break;
13643         case 'A':
13644           if (intel_syntax)
13645             break;
13646           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13647             *obufp++ = 'b';
13648           break;
13649         case 'B':
13650           if (l == 0 && len == 1)
13651             {
13652 case_B:
13653               if (intel_syntax)
13654                 break;
13655               if (sizeflag & SUFFIX_ALWAYS)
13656                 *obufp++ = 'b';
13657             }
13658           else
13659             {
13660               if (l != 1
13661                   || len != 2
13662                   || last[0] != 'L')
13663                 {
13664                   SAVE_LAST (*p);
13665                   break;
13666                 }
13667
13668               if (address_mode == mode_64bit
13669                   && !(prefixes & PREFIX_ADDR))
13670                 {
13671                   *obufp++ = 'a';
13672                   *obufp++ = 'b';
13673                   *obufp++ = 's';
13674                 }
13675
13676               goto case_B;
13677             }
13678           break;
13679         case 'C':
13680           if (intel_syntax && !alt)
13681             break;
13682           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13683             {
13684               if (sizeflag & DFLAG)
13685                 *obufp++ = intel_syntax ? 'd' : 'l';
13686               else
13687                 *obufp++ = intel_syntax ? 'w' : 's';
13688               used_prefixes |= (prefixes & PREFIX_DATA);
13689             }
13690           break;
13691         case 'D':
13692           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13693             break;
13694           USED_REX (REX_W);
13695           if (modrm.mod == 3)
13696             {
13697               if (rex & REX_W)
13698                 *obufp++ = 'q';
13699               else
13700                 {
13701                   if (sizeflag & DFLAG)
13702                     *obufp++ = intel_syntax ? 'd' : 'l';
13703                   else
13704                     *obufp++ = 'w';
13705                   used_prefixes |= (prefixes & PREFIX_DATA);
13706                 }
13707             }
13708           else
13709             *obufp++ = 'w';
13710           break;
13711         case 'E':               /* For jcxz/jecxz */
13712           if (address_mode == mode_64bit)
13713             {
13714               if (sizeflag & AFLAG)
13715                 *obufp++ = 'r';
13716               else
13717                 *obufp++ = 'e';
13718             }
13719           else
13720             if (sizeflag & AFLAG)
13721               *obufp++ = 'e';
13722           used_prefixes |= (prefixes & PREFIX_ADDR);
13723           break;
13724         case 'F':
13725           if (intel_syntax)
13726             break;
13727           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13728             {
13729               if (sizeflag & AFLAG)
13730                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13731               else
13732                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13733               used_prefixes |= (prefixes & PREFIX_ADDR);
13734             }
13735           break;
13736         case 'G':
13737           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13738             break;
13739           if ((rex & REX_W) || (sizeflag & DFLAG))
13740             *obufp++ = 'l';
13741           else
13742             *obufp++ = 'w';
13743           if (!(rex & REX_W))
13744             used_prefixes |= (prefixes & PREFIX_DATA);
13745           break;
13746         case 'H':
13747           if (intel_syntax)
13748             break;
13749           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13750               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13751             {
13752               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13753               *obufp++ = ',';
13754               *obufp++ = 'p';
13755               if (prefixes & PREFIX_DS)
13756                 *obufp++ = 't';
13757               else
13758                 *obufp++ = 'n';
13759             }
13760           break;
13761         case 'J':
13762           if (intel_syntax)
13763             break;
13764           *obufp++ = 'l';
13765           break;
13766         case 'K':
13767           USED_REX (REX_W);
13768           if (rex & REX_W)
13769             *obufp++ = 'q';
13770           else
13771             *obufp++ = 'd';
13772           break;
13773         case 'Z':
13774           if (intel_syntax)
13775             break;
13776           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13777             {
13778               *obufp++ = 'q';
13779               break;
13780             }
13781           /* Fall through.  */
13782           goto case_L;
13783         case 'L':
13784           if (l != 0 || len != 1)
13785             {
13786               SAVE_LAST (*p);
13787               break;
13788             }
13789 case_L:
13790           if (intel_syntax)
13791             break;
13792           if (sizeflag & SUFFIX_ALWAYS)
13793             *obufp++ = 'l';
13794           break;
13795         case 'M':
13796           if (intel_mnemonic != cond)
13797             *obufp++ = 'r';
13798           break;
13799         case 'N':
13800           if ((prefixes & PREFIX_FWAIT) == 0)
13801             *obufp++ = 'n';
13802           else
13803             used_prefixes |= PREFIX_FWAIT;
13804           break;
13805         case 'O':
13806           USED_REX (REX_W);
13807           if (rex & REX_W)
13808             *obufp++ = 'o';
13809           else if (intel_syntax && (sizeflag & DFLAG))
13810             *obufp++ = 'q';
13811           else
13812             *obufp++ = 'd';
13813           if (!(rex & REX_W))
13814             used_prefixes |= (prefixes & PREFIX_DATA);
13815           break;
13816         case 'T':
13817           if (!intel_syntax
13818               && address_mode == mode_64bit
13819               && ((sizeflag & DFLAG) || (rex & REX_W)))
13820             {
13821               *obufp++ = 'q';
13822               break;
13823             }
13824           /* Fall through.  */
13825           goto case_P;
13826         case 'P':
13827           if (l == 0 && len == 1)
13828             {
13829 case_P:
13830               if (intel_syntax)
13831                 {
13832                   if ((rex & REX_W) == 0
13833                       && (prefixes & PREFIX_DATA))
13834                     {
13835                       if ((sizeflag & DFLAG) == 0)
13836                         *obufp++ = 'w';
13837                       used_prefixes |= (prefixes & PREFIX_DATA);
13838                     }
13839                   break;
13840                 }
13841               if ((prefixes & PREFIX_DATA)
13842                   || (rex & REX_W)
13843                   || (sizeflag & SUFFIX_ALWAYS))
13844                 {
13845                   USED_REX (REX_W);
13846                   if (rex & REX_W)
13847                     *obufp++ = 'q';
13848                   else
13849                     {
13850                       if (sizeflag & DFLAG)
13851                         *obufp++ = 'l';
13852                       else
13853                         *obufp++ = 'w';
13854                       used_prefixes |= (prefixes & PREFIX_DATA);
13855                     }
13856                 }
13857             }
13858           else
13859             {
13860               if (l != 1 || len != 2 || last[0] != 'L')
13861                 {
13862                   SAVE_LAST (*p);
13863                   break;
13864                 }
13865
13866               if ((prefixes & PREFIX_DATA)
13867                   || (rex & REX_W)
13868                   || (sizeflag & SUFFIX_ALWAYS))
13869                 {
13870                   USED_REX (REX_W);
13871                   if (rex & REX_W)
13872                     *obufp++ = 'q';
13873                   else
13874                     {
13875                       if (sizeflag & DFLAG)
13876                         *obufp++ = intel_syntax ? 'd' : 'l';
13877                       else
13878                         *obufp++ = 'w';
13879                       used_prefixes |= (prefixes & PREFIX_DATA);
13880                     }
13881                 }
13882             }
13883           break;
13884         case 'U':
13885           if (intel_syntax)
13886             break;
13887           if (address_mode == mode_64bit
13888               && ((sizeflag & DFLAG) || (rex & REX_W)))
13889             {
13890               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13891                 *obufp++ = 'q';
13892               break;
13893             }
13894           /* Fall through.  */
13895           goto case_Q;
13896         case 'Q':
13897           if (l == 0 && len == 1)
13898             {
13899 case_Q:
13900               if (intel_syntax && !alt)
13901                 break;
13902               USED_REX (REX_W);
13903               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13904                 {
13905                   if (rex & REX_W)
13906                     *obufp++ = 'q';
13907                   else
13908                     {
13909                       if (sizeflag & DFLAG)
13910                         *obufp++ = intel_syntax ? 'd' : 'l';
13911                       else
13912                         *obufp++ = 'w';
13913                       used_prefixes |= (prefixes & PREFIX_DATA);
13914                     }
13915                 }
13916             }
13917           else
13918             {
13919               if (l != 1 || len != 2 || last[0] != 'L')
13920                 {
13921                   SAVE_LAST (*p);
13922                   break;
13923                 }
13924               if (intel_syntax
13925                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13926                 break;
13927               if ((rex & REX_W))
13928                 {
13929                   USED_REX (REX_W);
13930                   *obufp++ = 'q';
13931                 }
13932               else
13933                 *obufp++ = 'l';
13934             }
13935           break;
13936         case 'R':
13937           USED_REX (REX_W);
13938           if (rex & REX_W)
13939             *obufp++ = 'q';
13940           else if (sizeflag & DFLAG)
13941             {
13942               if (intel_syntax)
13943                   *obufp++ = 'd';
13944               else
13945                   *obufp++ = 'l';
13946             }
13947           else
13948             *obufp++ = 'w';
13949           if (intel_syntax && !p[1]
13950               && ((rex & REX_W) || (sizeflag & DFLAG)))
13951             *obufp++ = 'e';
13952           if (!(rex & REX_W))
13953             used_prefixes |= (prefixes & PREFIX_DATA);
13954           break;
13955         case 'V':
13956           if (l == 0 && len == 1)
13957             {
13958               if (intel_syntax)
13959                 break;
13960               if (address_mode == mode_64bit
13961                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13962                 {
13963                   if (sizeflag & SUFFIX_ALWAYS)
13964                     *obufp++ = 'q';
13965                   break;
13966                 }
13967             }
13968           else
13969             {
13970               if (l != 1
13971                   || len != 2
13972                   || last[0] != 'L')
13973                 {
13974                   SAVE_LAST (*p);
13975                   break;
13976                 }
13977
13978               if (rex & REX_W)
13979                 {
13980                   *obufp++ = 'a';
13981                   *obufp++ = 'b';
13982                   *obufp++ = 's';
13983                 }
13984             }
13985           /* Fall through.  */
13986           goto case_S;
13987         case 'S':
13988           if (l == 0 && len == 1)
13989             {
13990 case_S:
13991               if (intel_syntax)
13992                 break;
13993               if (sizeflag & SUFFIX_ALWAYS)
13994                 {
13995                   if (rex & REX_W)
13996                     *obufp++ = 'q';
13997                   else
13998                     {
13999                       if (sizeflag & DFLAG)
14000                         *obufp++ = 'l';
14001                       else
14002                         *obufp++ = 'w';
14003                       used_prefixes |= (prefixes & PREFIX_DATA);
14004                     }
14005                 }
14006             }
14007           else
14008             {
14009               if (l != 1
14010                   || len != 2
14011                   || last[0] != 'L')
14012                 {
14013                   SAVE_LAST (*p);
14014                   break;
14015                 }
14016
14017               if (address_mode == mode_64bit
14018                   && !(prefixes & PREFIX_ADDR))
14019                 {
14020                   *obufp++ = 'a';
14021                   *obufp++ = 'b';
14022                   *obufp++ = 's';
14023                 }
14024
14025               goto case_S;
14026             }
14027           break;
14028         case 'X':
14029           if (l != 0 || len != 1)
14030             {
14031               SAVE_LAST (*p);
14032               break;
14033             }
14034           if (need_vex && vex.prefix)
14035             {
14036               if (vex.prefix == DATA_PREFIX_OPCODE)
14037                 *obufp++ = 'd';
14038               else
14039                 *obufp++ = 's';
14040             }
14041           else
14042             {
14043               if (prefixes & PREFIX_DATA)
14044                 *obufp++ = 'd';
14045               else
14046                 *obufp++ = 's';
14047               used_prefixes |= (prefixes & PREFIX_DATA);
14048             }
14049           break;
14050         case 'Y':
14051           if (l == 0 && len == 1)
14052             {
14053               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14054                 break;
14055               if (rex & REX_W)
14056                 {
14057                   USED_REX (REX_W);
14058                   *obufp++ = 'q';
14059                 }
14060               break;
14061             }
14062           else
14063             {
14064               if (l != 1 || len != 2 || last[0] != 'X')
14065                 {
14066                   SAVE_LAST (*p);
14067                   break;
14068                 }
14069               if (!need_vex)
14070                 abort ();
14071               if (intel_syntax
14072                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14073                 break;
14074               switch (vex.length)
14075                 {
14076                 case 128:
14077                   *obufp++ = 'x';
14078                   break;
14079                 case 256:
14080                   *obufp++ = 'y';
14081                   break;
14082                 default:
14083                   abort ();
14084                 }
14085             }
14086           break;
14087         case 'W':
14088           if (l == 0 && len == 1)
14089             {
14090               /* operand size flag for cwtl, cbtw */
14091               USED_REX (REX_W);
14092               if (rex & REX_W)
14093                 {
14094                   if (intel_syntax)
14095                     *obufp++ = 'd';
14096                   else
14097                     *obufp++ = 'l';
14098                 }
14099               else if (sizeflag & DFLAG)
14100                 *obufp++ = 'w';
14101               else
14102                 *obufp++ = 'b';
14103               if (!(rex & REX_W))
14104                 used_prefixes |= (prefixes & PREFIX_DATA);
14105             }
14106           else
14107             {
14108               if (l != 1
14109                   || len != 2
14110                   || (last[0] != 'X'
14111                       && last[0] != 'L'))
14112                 {
14113                   SAVE_LAST (*p);
14114                   break;
14115                 }
14116               if (!need_vex)
14117                 abort ();
14118               if (last[0] == 'X')
14119                 *obufp++ = vex.w ? 'd': 's';
14120               else
14121                 *obufp++ = vex.w ? 'q': 'd';
14122             }
14123           break;
14124         }
14125       alt = 0;
14126     }
14127   *obufp = 0;
14128   mnemonicendp = obufp;
14129   return 0;
14130 }
14131
14132 static void
14133 oappend (const char *s)
14134 {
14135   obufp = stpcpy (obufp, s);
14136 }
14137
14138 static void
14139 append_seg (void)
14140 {
14141   /* Only print the active segment register.  */
14142   if (!active_seg_prefix)
14143     return;
14144
14145   used_prefixes |= active_seg_prefix;
14146   switch (active_seg_prefix)
14147     {
14148     case PREFIX_CS:
14149       oappend_maybe_intel ("%cs:");
14150       break;
14151     case PREFIX_DS:
14152       oappend_maybe_intel ("%ds:");
14153       break;
14154     case PREFIX_SS:
14155       oappend_maybe_intel ("%ss:");
14156       break;
14157     case PREFIX_ES:
14158       oappend_maybe_intel ("%es:");
14159       break;
14160     case PREFIX_FS:
14161       oappend_maybe_intel ("%fs:");
14162       break;
14163     case PREFIX_GS:
14164       oappend_maybe_intel ("%gs:");
14165       break;
14166     default:
14167       break;
14168     }
14169 }
14170
14171 static void
14172 OP_indirE (int bytemode, int sizeflag)
14173 {
14174   if (!intel_syntax)
14175     oappend ("*");
14176   OP_E (bytemode, sizeflag);
14177 }
14178
14179 static void
14180 print_operand_value (char *buf, int hex, bfd_vma disp)
14181 {
14182   if (address_mode == mode_64bit)
14183     {
14184       if (hex)
14185         {
14186           char tmp[30];
14187           int i;
14188           buf[0] = '0';
14189           buf[1] = 'x';
14190           sprintf_vma (tmp, disp);
14191           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14192           strcpy (buf + 2, tmp + i);
14193         }
14194       else
14195         {
14196           bfd_signed_vma v = disp;
14197           char tmp[30];
14198           int i;
14199           if (v < 0)
14200             {
14201               *(buf++) = '-';
14202               v = -disp;
14203               /* Check for possible overflow on 0x8000000000000000.  */
14204               if (v < 0)
14205                 {
14206                   strcpy (buf, "9223372036854775808");
14207                   return;
14208                 }
14209             }
14210           if (!v)
14211             {
14212               strcpy (buf, "0");
14213               return;
14214             }
14215
14216           i = 0;
14217           tmp[29] = 0;
14218           while (v)
14219             {
14220               tmp[28 - i] = (v % 10) + '0';
14221               v /= 10;
14222               i++;
14223             }
14224           strcpy (buf, tmp + 29 - i);
14225         }
14226     }
14227   else
14228     {
14229       if (hex)
14230         sprintf (buf, "0x%x", (unsigned int) disp);
14231       else
14232         sprintf (buf, "%d", (int) disp);
14233     }
14234 }
14235
14236 /* Put DISP in BUF as signed hex number.  */
14237
14238 static void
14239 print_displacement (char *buf, bfd_vma disp)
14240 {
14241   bfd_signed_vma val = disp;
14242   char tmp[30];
14243   int i, j = 0;
14244
14245   if (val < 0)
14246     {
14247       buf[j++] = '-';
14248       val = -disp;
14249
14250       /* Check for possible overflow.  */
14251       if (val < 0)
14252         {
14253           switch (address_mode)
14254             {
14255             case mode_64bit:
14256               strcpy (buf + j, "0x8000000000000000");
14257               break;
14258             case mode_32bit:
14259               strcpy (buf + j, "0x80000000");
14260               break;
14261             case mode_16bit:
14262               strcpy (buf + j, "0x8000");
14263               break;
14264             }
14265           return;
14266         }
14267     }
14268
14269   buf[j++] = '0';
14270   buf[j++] = 'x';
14271
14272   sprintf_vma (tmp, (bfd_vma) val);
14273   for (i = 0; tmp[i] == '0'; i++)
14274     continue;
14275   if (tmp[i] == '\0')
14276     i--;
14277   strcpy (buf + j, tmp + i);
14278 }
14279
14280 static void
14281 intel_operand_size (int bytemode, int sizeflag)
14282 {
14283   if (vex.evex
14284       && vex.b
14285       && (bytemode == x_mode
14286           || bytemode == evex_half_bcst_xmmq_mode))
14287     {
14288       if (vex.w)
14289         oappend ("QWORD PTR ");
14290       else
14291         oappend ("DWORD PTR ");
14292       return;
14293     }
14294   switch (bytemode)
14295     {
14296     case b_mode:
14297     case b_swap_mode:
14298     case dqb_mode:
14299     case db_mode:
14300       oappend ("BYTE PTR ");
14301       break;
14302     case w_mode:
14303     case dw_mode:
14304     case dqw_mode:
14305     case dqw_swap_mode:
14306       oappend ("WORD PTR ");
14307       break;
14308     case stack_v_mode:
14309       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14310         {
14311           oappend ("QWORD PTR ");
14312           break;
14313         }
14314       /* FALLTHRU */
14315     case v_mode:
14316     case v_swap_mode:
14317     case dq_mode:
14318       USED_REX (REX_W);
14319       if (rex & REX_W)
14320         oappend ("QWORD PTR ");
14321       else
14322         {
14323           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14324             oappend ("DWORD PTR ");
14325           else
14326             oappend ("WORD PTR ");
14327           used_prefixes |= (prefixes & PREFIX_DATA);
14328         }
14329       break;
14330     case z_mode:
14331       if ((rex & REX_W) || (sizeflag & DFLAG))
14332         *obufp++ = 'D';
14333       oappend ("WORD PTR ");
14334       if (!(rex & REX_W))
14335         used_prefixes |= (prefixes & PREFIX_DATA);
14336       break;
14337     case a_mode:
14338       if (sizeflag & DFLAG)
14339         oappend ("QWORD PTR ");
14340       else
14341         oappend ("DWORD PTR ");
14342       used_prefixes |= (prefixes & PREFIX_DATA);
14343       break;
14344     case d_mode:
14345     case d_scalar_mode:
14346     case d_scalar_swap_mode:
14347     case d_swap_mode:
14348     case dqd_mode:
14349       oappend ("DWORD PTR ");
14350       break;
14351     case q_mode:
14352     case q_scalar_mode:
14353     case q_scalar_swap_mode:
14354     case q_swap_mode:
14355       oappend ("QWORD PTR ");
14356       break;
14357     case m_mode:
14358       if (address_mode == mode_64bit)
14359         oappend ("QWORD PTR ");
14360       else
14361         oappend ("DWORD PTR ");
14362       break;
14363     case f_mode:
14364       if (sizeflag & DFLAG)
14365         oappend ("FWORD PTR ");
14366       else
14367         oappend ("DWORD PTR ");
14368       used_prefixes |= (prefixes & PREFIX_DATA);
14369       break;
14370     case t_mode:
14371       oappend ("TBYTE PTR ");
14372       break;
14373     case x_mode:
14374     case x_swap_mode:
14375     case evex_x_gscat_mode:
14376     case evex_x_nobcst_mode:
14377       if (need_vex)
14378         {
14379           switch (vex.length)
14380             {
14381             case 128:
14382               oappend ("XMMWORD PTR ");
14383               break;
14384             case 256:
14385               oappend ("YMMWORD PTR ");
14386               break;
14387             case 512:
14388               oappend ("ZMMWORD PTR ");
14389               break;
14390             default:
14391               abort ();
14392             }
14393         }
14394       else
14395         oappend ("XMMWORD PTR ");
14396       break;
14397     case xmm_mode:
14398       oappend ("XMMWORD PTR ");
14399       break;
14400     case ymm_mode:
14401       oappend ("YMMWORD PTR ");
14402       break;
14403     case xmmq_mode:
14404     case evex_half_bcst_xmmq_mode:
14405       if (!need_vex)
14406         abort ();
14407
14408       switch (vex.length)
14409         {
14410         case 128:
14411           oappend ("QWORD PTR ");
14412           break;
14413         case 256:
14414           oappend ("XMMWORD PTR ");
14415           break;
14416         case 512:
14417           oappend ("YMMWORD PTR ");
14418           break;
14419         default:
14420           abort ();
14421         }
14422       break;
14423     case xmm_mb_mode:
14424       if (!need_vex)
14425         abort ();
14426
14427       switch (vex.length)
14428         {
14429         case 128:
14430         case 256:
14431         case 512:
14432           oappend ("BYTE PTR ");
14433           break;
14434         default:
14435           abort ();
14436         }
14437       break;
14438     case xmm_mw_mode:
14439       if (!need_vex)
14440         abort ();
14441
14442       switch (vex.length)
14443         {
14444         case 128:
14445         case 256:
14446         case 512:
14447           oappend ("WORD PTR ");
14448           break;
14449         default:
14450           abort ();
14451         }
14452       break;
14453     case xmm_md_mode:
14454       if (!need_vex)
14455         abort ();
14456
14457       switch (vex.length)
14458         {
14459         case 128:
14460         case 256:
14461         case 512:
14462           oappend ("DWORD PTR ");
14463           break;
14464         default:
14465           abort ();
14466         }
14467       break;
14468     case xmm_mq_mode:
14469       if (!need_vex)
14470         abort ();
14471
14472       switch (vex.length)
14473         {
14474         case 128:
14475         case 256:
14476         case 512:
14477           oappend ("QWORD PTR ");
14478           break;
14479         default:
14480           abort ();
14481         }
14482       break;
14483     case xmmdw_mode:
14484       if (!need_vex)
14485         abort ();
14486
14487       switch (vex.length)
14488         {
14489         case 128:
14490           oappend ("WORD PTR ");
14491           break;
14492         case 256:
14493           oappend ("DWORD PTR ");
14494           break;
14495         case 512:
14496           oappend ("QWORD PTR ");
14497           break;
14498         default:
14499           abort ();
14500         }
14501       break;
14502     case xmmqd_mode:
14503       if (!need_vex)
14504         abort ();
14505
14506       switch (vex.length)
14507         {
14508         case 128:
14509           oappend ("DWORD PTR ");
14510           break;
14511         case 256:
14512           oappend ("QWORD PTR ");
14513           break;
14514         case 512:
14515           oappend ("XMMWORD PTR ");
14516           break;
14517         default:
14518           abort ();
14519         }
14520       break;
14521     case ymmq_mode:
14522       if (!need_vex)
14523         abort ();
14524
14525       switch (vex.length)
14526         {
14527         case 128:
14528           oappend ("QWORD PTR ");
14529           break;
14530         case 256:
14531           oappend ("YMMWORD PTR ");
14532           break;
14533         case 512:
14534           oappend ("ZMMWORD PTR ");
14535           break;
14536         default:
14537           abort ();
14538         }
14539       break;
14540     case ymmxmm_mode:
14541       if (!need_vex)
14542         abort ();
14543
14544       switch (vex.length)
14545         {
14546         case 128:
14547         case 256:
14548           oappend ("XMMWORD PTR ");
14549           break;
14550         default:
14551           abort ();
14552         }
14553       break;
14554     case o_mode:
14555       oappend ("OWORD PTR ");
14556       break;
14557     case xmm_mdq_mode:
14558     case vex_w_dq_mode:
14559     case vex_scalar_w_dq_mode:
14560       if (!need_vex)
14561         abort ();
14562
14563       if (vex.w)
14564         oappend ("QWORD PTR ");
14565       else
14566         oappend ("DWORD PTR ");
14567       break;
14568     case vex_vsib_d_w_dq_mode:
14569     case vex_vsib_q_w_dq_mode:
14570       if (!need_vex)
14571         abort ();
14572
14573       if (!vex.evex)
14574         {
14575           if (vex.w)
14576             oappend ("QWORD PTR ");
14577           else
14578             oappend ("DWORD PTR ");
14579         }
14580       else
14581         {
14582           switch (vex.length)
14583             {
14584             case 128:
14585               oappend ("XMMWORD PTR ");
14586               break;
14587             case 256:
14588               oappend ("YMMWORD PTR ");
14589               break;
14590             case 512:
14591               oappend ("ZMMWORD PTR ");
14592               break;
14593             default:
14594               abort ();
14595             }
14596         }
14597       break;
14598     case vex_vsib_q_w_d_mode:
14599     case vex_vsib_d_w_d_mode:
14600       if (!need_vex || !vex.evex)
14601         abort ();
14602
14603       switch (vex.length)
14604         {
14605         case 128:
14606           oappend ("QWORD PTR ");
14607           break;
14608         case 256:
14609           oappend ("XMMWORD PTR ");
14610           break;
14611         case 512:
14612           oappend ("YMMWORD PTR ");
14613           break;
14614         default:
14615           abort ();
14616         }
14617
14618       break;
14619     case mask_bd_mode:
14620       if (!need_vex || vex.length != 128)
14621         abort ();
14622       if (vex.w)
14623         oappend ("DWORD PTR ");
14624       else
14625         oappend ("BYTE PTR ");
14626       break;
14627     case mask_mode:
14628       if (!need_vex)
14629         abort ();
14630       if (vex.w)
14631         oappend ("QWORD PTR ");
14632       else
14633         oappend ("WORD PTR ");
14634       break;
14635     case v_bnd_mode:
14636     default:
14637       break;
14638     }
14639 }
14640
14641 static void
14642 OP_E_register (int bytemode, int sizeflag)
14643 {
14644   int reg = modrm.rm;
14645   const char **names;
14646
14647   USED_REX (REX_B);
14648   if ((rex & REX_B))
14649     reg += 8;
14650
14651   if ((sizeflag & SUFFIX_ALWAYS)
14652       && (bytemode == b_swap_mode
14653           || bytemode == v_swap_mode
14654           || bytemode == dqw_swap_mode))
14655     swap_operand ();
14656
14657   switch (bytemode)
14658     {
14659     case b_mode:
14660     case b_swap_mode:
14661       USED_REX (0);
14662       if (rex)
14663         names = names8rex;
14664       else
14665         names = names8;
14666       break;
14667     case w_mode:
14668       names = names16;
14669       break;
14670     case d_mode:
14671     case dw_mode:
14672     case db_mode:
14673       names = names32;
14674       break;
14675     case q_mode:
14676       names = names64;
14677       break;
14678     case m_mode:
14679     case v_bnd_mode:
14680       names = address_mode == mode_64bit ? names64 : names32;
14681       break;
14682     case bnd_mode:
14683       names = names_bnd;
14684       break;
14685     case stack_v_mode:
14686       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14687         {
14688           names = names64;
14689           break;
14690         }
14691       bytemode = v_mode;
14692       /* FALLTHRU */
14693     case v_mode:
14694     case v_swap_mode:
14695     case dq_mode:
14696     case dqb_mode:
14697     case dqd_mode:
14698     case dqw_mode:
14699     case dqw_swap_mode:
14700       USED_REX (REX_W);
14701       if (rex & REX_W)
14702         names = names64;
14703       else
14704         {
14705           if ((sizeflag & DFLAG)
14706               || (bytemode != v_mode
14707                   && bytemode != v_swap_mode))
14708             names = names32;
14709           else
14710             names = names16;
14711           used_prefixes |= (prefixes & PREFIX_DATA);
14712         }
14713       break;
14714     case mask_bd_mode:
14715     case mask_mode:
14716       names = names_mask;
14717       break;
14718     case 0:
14719       return;
14720     default:
14721       oappend (INTERNAL_DISASSEMBLER_ERROR);
14722       return;
14723     }
14724   oappend (names[reg]);
14725 }
14726
14727 static void
14728 OP_E_memory (int bytemode, int sizeflag)
14729 {
14730   bfd_vma disp = 0;
14731   int add = (rex & REX_B) ? 8 : 0;
14732   int riprel = 0;
14733   int shift;
14734
14735   if (vex.evex)
14736     {
14737       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14738       if (vex.b
14739           && bytemode != x_mode
14740           && bytemode != xmmq_mode
14741           && bytemode != evex_half_bcst_xmmq_mode)
14742         {
14743           BadOp ();
14744           return;
14745         }
14746       switch (bytemode)
14747         {
14748         case dqw_mode:
14749         case dw_mode:
14750         case dqw_swap_mode:
14751           shift = 1;
14752           break;
14753         case dqb_mode:
14754         case db_mode:
14755           shift = 0;
14756           break;
14757         case vex_vsib_d_w_dq_mode:
14758         case vex_vsib_d_w_d_mode:
14759         case vex_vsib_q_w_dq_mode:
14760         case vex_vsib_q_w_d_mode:
14761         case evex_x_gscat_mode:
14762         case xmm_mdq_mode:
14763           shift = vex.w ? 3 : 2;
14764           break;
14765         case x_mode:
14766         case evex_half_bcst_xmmq_mode:
14767         case xmmq_mode:
14768           if (vex.b)
14769             {
14770               shift = vex.w ? 3 : 2;
14771               break;
14772             }
14773           /* Fall through if vex.b == 0.  */
14774         case xmmqd_mode:
14775         case xmmdw_mode:
14776         case ymmq_mode:
14777         case evex_x_nobcst_mode:
14778         case x_swap_mode:
14779           switch (vex.length)
14780             {
14781             case 128:
14782               shift = 4;
14783               break;
14784             case 256:
14785               shift = 5;
14786               break;
14787             case 512:
14788               shift = 6;
14789               break;
14790             default:
14791               abort ();
14792             }
14793           break;
14794         case ymm_mode:
14795           shift = 5;
14796           break;
14797         case xmm_mode:
14798           shift = 4;
14799           break;
14800         case xmm_mq_mode:
14801         case q_mode:
14802         case q_scalar_mode:
14803         case q_swap_mode:
14804         case q_scalar_swap_mode:
14805           shift = 3;
14806           break;
14807         case dqd_mode:
14808         case xmm_md_mode:
14809         case d_mode:
14810         case d_scalar_mode:
14811         case d_swap_mode:
14812         case d_scalar_swap_mode:
14813           shift = 2;
14814           break;
14815         case xmm_mw_mode:
14816           shift = 1;
14817           break;
14818         case xmm_mb_mode:
14819           shift = 0;
14820           break;
14821         default:
14822           abort ();
14823         }
14824       /* Make necessary corrections to shift for modes that need it.
14825          For these modes we currently have shift 4, 5 or 6 depending on
14826          vex.length (it corresponds to xmmword, ymmword or zmmword
14827          operand).  We might want to make it 3, 4 or 5 (e.g. for
14828          xmmq_mode).  In case of broadcast enabled the corrections
14829          aren't needed, as element size is always 32 or 64 bits.  */
14830       if (!vex.b
14831           && (bytemode == xmmq_mode
14832               || bytemode == evex_half_bcst_xmmq_mode))
14833         shift -= 1;
14834       else if (bytemode == xmmqd_mode)
14835         shift -= 2;
14836       else if (bytemode == xmmdw_mode)
14837         shift -= 3;
14838       else if (bytemode == ymmq_mode && vex.length == 128)
14839         shift -= 1;
14840     }
14841   else
14842     shift = 0;
14843
14844   USED_REX (REX_B);
14845   if (intel_syntax)
14846     intel_operand_size (bytemode, sizeflag);
14847   append_seg ();
14848
14849   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14850     {
14851       /* 32/64 bit address mode */
14852       int havedisp;
14853       int havesib;
14854       int havebase;
14855       int haveindex;
14856       int needindex;
14857       int base, rbase;
14858       int vindex = 0;
14859       int scale = 0;
14860       int addr32flag = !((sizeflag & AFLAG)
14861                          || bytemode == v_bnd_mode
14862                          || bytemode == bnd_mode);
14863       const char **indexes64 = names64;
14864       const char **indexes32 = names32;
14865
14866       havesib = 0;
14867       havebase = 1;
14868       haveindex = 0;
14869       base = modrm.rm;
14870
14871       if (base == 4)
14872         {
14873           havesib = 1;
14874           vindex = sib.index;
14875           USED_REX (REX_X);
14876           if (rex & REX_X)
14877             vindex += 8;
14878           switch (bytemode)
14879             {
14880             case vex_vsib_d_w_dq_mode:
14881             case vex_vsib_d_w_d_mode:
14882             case vex_vsib_q_w_dq_mode:
14883             case vex_vsib_q_w_d_mode:
14884               if (!need_vex)
14885                 abort ();
14886               if (vex.evex)
14887                 {
14888                   if (!vex.v)
14889                     vindex += 16;
14890                 }
14891
14892               haveindex = 1;
14893               switch (vex.length)
14894                 {
14895                 case 128:
14896                   indexes64 = indexes32 = names_xmm;
14897                   break;
14898                 case 256:
14899                   if (!vex.w
14900                       || bytemode == vex_vsib_q_w_dq_mode
14901                       || bytemode == vex_vsib_q_w_d_mode)
14902                     indexes64 = indexes32 = names_ymm;
14903                   else
14904                     indexes64 = indexes32 = names_xmm;
14905                   break;
14906                 case 512:
14907                   if (!vex.w
14908                       || bytemode == vex_vsib_q_w_dq_mode
14909                       || bytemode == vex_vsib_q_w_d_mode)
14910                     indexes64 = indexes32 = names_zmm;
14911                   else
14912                     indexes64 = indexes32 = names_ymm;
14913                   break;
14914                 default:
14915                   abort ();
14916                 }
14917               break;
14918             default:
14919               haveindex = vindex != 4;
14920               break;
14921             }
14922           scale = sib.scale;
14923           base = sib.base;
14924           codep++;
14925         }
14926       rbase = base + add;
14927
14928       switch (modrm.mod)
14929         {
14930         case 0:
14931           if (base == 5)
14932             {
14933               havebase = 0;
14934               if (address_mode == mode_64bit && !havesib)
14935                 riprel = 1;
14936               disp = get32s ();
14937             }
14938           break;
14939         case 1:
14940           FETCH_DATA (the_info, codep + 1);
14941           disp = *codep++;
14942           if ((disp & 0x80) != 0)
14943             disp -= 0x100;
14944           if (vex.evex && shift > 0)
14945             disp <<= shift;
14946           break;
14947         case 2:
14948           disp = get32s ();
14949           break;
14950         }
14951
14952       /* In 32bit mode, we need index register to tell [offset] from
14953          [eiz*1 + offset].  */
14954       needindex = (havesib
14955                    && !havebase
14956                    && !haveindex
14957                    && address_mode == mode_32bit);
14958       havedisp = (havebase
14959                   || needindex
14960                   || (havesib && (haveindex || scale != 0)));
14961
14962       if (!intel_syntax)
14963         if (modrm.mod != 0 || base == 5)
14964           {
14965             if (havedisp || riprel)
14966               print_displacement (scratchbuf, disp);
14967             else
14968               print_operand_value (scratchbuf, 1, disp);
14969             oappend (scratchbuf);
14970             if (riprel)
14971               {
14972                 set_op (disp, 1);
14973                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14974               }
14975           }
14976
14977       if ((havebase || haveindex || riprel)
14978           && (bytemode != v_bnd_mode)
14979           && (bytemode != bnd_mode))
14980         used_prefixes |= PREFIX_ADDR;
14981
14982       if (havedisp || (intel_syntax && riprel))
14983         {
14984           *obufp++ = open_char;
14985           if (intel_syntax && riprel)
14986             {
14987               set_op (disp, 1);
14988               oappend (sizeflag & AFLAG ? "rip" : "eip");
14989             }
14990           *obufp = '\0';
14991           if (havebase)
14992             oappend (address_mode == mode_64bit && !addr32flag
14993                      ? names64[rbase] : names32[rbase]);
14994           if (havesib)
14995             {
14996               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14997                  print index to tell base + index from base.  */
14998               if (scale != 0
14999                   || needindex
15000                   || haveindex
15001                   || (havebase && base != ESP_REG_NUM))
15002                 {
15003                   if (!intel_syntax || havebase)
15004                     {
15005                       *obufp++ = separator_char;
15006                       *obufp = '\0';
15007                     }
15008                   if (haveindex)
15009                     oappend (address_mode == mode_64bit && !addr32flag
15010                              ? indexes64[vindex] : indexes32[vindex]);
15011                   else
15012                     oappend (address_mode == mode_64bit && !addr32flag
15013                              ? index64 : index32);
15014
15015                   *obufp++ = scale_char;
15016                   *obufp = '\0';
15017                   sprintf (scratchbuf, "%d", 1 << scale);
15018                   oappend (scratchbuf);
15019                 }
15020             }
15021           if (intel_syntax
15022               && (disp || modrm.mod != 0 || base == 5))
15023             {
15024               if (!havedisp || (bfd_signed_vma) disp >= 0)
15025                 {
15026                   *obufp++ = '+';
15027                   *obufp = '\0';
15028                 }
15029               else if (modrm.mod != 1 && disp != -disp)
15030                 {
15031                   *obufp++ = '-';
15032                   *obufp = '\0';
15033                   disp = - (bfd_signed_vma) disp;
15034                 }
15035
15036               if (havedisp)
15037                 print_displacement (scratchbuf, disp);
15038               else
15039                 print_operand_value (scratchbuf, 1, disp);
15040               oappend (scratchbuf);
15041             }
15042
15043           *obufp++ = close_char;
15044           *obufp = '\0';
15045         }
15046       else if (intel_syntax)
15047         {
15048           if (modrm.mod != 0 || base == 5)
15049             {
15050               if (!active_seg_prefix)
15051                 {
15052                   oappend (names_seg[ds_reg - es_reg]);
15053                   oappend (":");
15054                 }
15055               print_operand_value (scratchbuf, 1, disp);
15056               oappend (scratchbuf);
15057             }
15058         }
15059     }
15060   else
15061     {
15062       /* 16 bit address mode */
15063       used_prefixes |= prefixes & PREFIX_ADDR;
15064       switch (modrm.mod)
15065         {
15066         case 0:
15067           if (modrm.rm == 6)
15068             {
15069               disp = get16 ();
15070               if ((disp & 0x8000) != 0)
15071                 disp -= 0x10000;
15072             }
15073           break;
15074         case 1:
15075           FETCH_DATA (the_info, codep + 1);
15076           disp = *codep++;
15077           if ((disp & 0x80) != 0)
15078             disp -= 0x100;
15079           break;
15080         case 2:
15081           disp = get16 ();
15082           if ((disp & 0x8000) != 0)
15083             disp -= 0x10000;
15084           break;
15085         }
15086
15087       if (!intel_syntax)
15088         if (modrm.mod != 0 || modrm.rm == 6)
15089           {
15090             print_displacement (scratchbuf, disp);
15091             oappend (scratchbuf);
15092           }
15093
15094       if (modrm.mod != 0 || modrm.rm != 6)
15095         {
15096           *obufp++ = open_char;
15097           *obufp = '\0';
15098           oappend (index16[modrm.rm]);
15099           if (intel_syntax
15100               && (disp || modrm.mod != 0 || modrm.rm == 6))
15101             {
15102               if ((bfd_signed_vma) disp >= 0)
15103                 {
15104                   *obufp++ = '+';
15105                   *obufp = '\0';
15106                 }
15107               else if (modrm.mod != 1)
15108                 {
15109                   *obufp++ = '-';
15110                   *obufp = '\0';
15111                   disp = - (bfd_signed_vma) disp;
15112                 }
15113
15114               print_displacement (scratchbuf, disp);
15115               oappend (scratchbuf);
15116             }
15117
15118           *obufp++ = close_char;
15119           *obufp = '\0';
15120         }
15121       else if (intel_syntax)
15122         {
15123           if (!active_seg_prefix)
15124             {
15125               oappend (names_seg[ds_reg - es_reg]);
15126               oappend (":");
15127             }
15128           print_operand_value (scratchbuf, 1, disp & 0xffff);
15129           oappend (scratchbuf);
15130         }
15131     }
15132   if (vex.evex && vex.b
15133       && (bytemode == x_mode
15134           || bytemode == xmmq_mode
15135           || bytemode == evex_half_bcst_xmmq_mode))
15136     {
15137       if (vex.w
15138           || bytemode == xmmq_mode
15139           || bytemode == evex_half_bcst_xmmq_mode)
15140         {
15141           switch (vex.length)
15142             {
15143             case 128:
15144               oappend ("{1to2}");
15145               break;
15146             case 256:
15147               oappend ("{1to4}");
15148               break;
15149             case 512:
15150               oappend ("{1to8}");
15151               break;
15152             default:
15153               abort ();
15154             }
15155         }
15156       else
15157         {
15158           switch (vex.length)
15159             {
15160             case 128:
15161               oappend ("{1to4}");
15162               break;
15163             case 256:
15164               oappend ("{1to8}");
15165               break;
15166             case 512:
15167               oappend ("{1to16}");
15168               break;
15169             default:
15170               abort ();
15171             }
15172         }
15173     }
15174 }
15175
15176 static void
15177 OP_E (int bytemode, int sizeflag)
15178 {
15179   /* Skip mod/rm byte.  */
15180   MODRM_CHECK;
15181   codep++;
15182
15183   if (modrm.mod == 3)
15184     OP_E_register (bytemode, sizeflag);
15185   else
15186     OP_E_memory (bytemode, sizeflag);
15187 }
15188
15189 static void
15190 OP_G (int bytemode, int sizeflag)
15191 {
15192   int add = 0;
15193   USED_REX (REX_R);
15194   if (rex & REX_R)
15195     add += 8;
15196   switch (bytemode)
15197     {
15198     case b_mode:
15199       USED_REX (0);
15200       if (rex)
15201         oappend (names8rex[modrm.reg + add]);
15202       else
15203         oappend (names8[modrm.reg + add]);
15204       break;
15205     case w_mode:
15206       oappend (names16[modrm.reg + add]);
15207       break;
15208     case d_mode:
15209     case db_mode:
15210     case dw_mode:
15211       oappend (names32[modrm.reg + add]);
15212       break;
15213     case q_mode:
15214       oappend (names64[modrm.reg + add]);
15215       break;
15216     case bnd_mode:
15217       oappend (names_bnd[modrm.reg]);
15218       break;
15219     case v_mode:
15220     case dq_mode:
15221     case dqb_mode:
15222     case dqd_mode:
15223     case dqw_mode:
15224     case dqw_swap_mode:
15225       USED_REX (REX_W);
15226       if (rex & REX_W)
15227         oappend (names64[modrm.reg + add]);
15228       else
15229         {
15230           if ((sizeflag & DFLAG) || bytemode != v_mode)
15231             oappend (names32[modrm.reg + add]);
15232           else
15233             oappend (names16[modrm.reg + add]);
15234           used_prefixes |= (prefixes & PREFIX_DATA);
15235         }
15236       break;
15237     case m_mode:
15238       if (address_mode == mode_64bit)
15239         oappend (names64[modrm.reg + add]);
15240       else
15241         oappend (names32[modrm.reg + add]);
15242       break;
15243     case mask_bd_mode:
15244     case mask_mode:
15245       oappend (names_mask[modrm.reg + add]);
15246       break;
15247     default:
15248       oappend (INTERNAL_DISASSEMBLER_ERROR);
15249       break;
15250     }
15251 }
15252
15253 static bfd_vma
15254 get64 (void)
15255 {
15256   bfd_vma x;
15257 #ifdef BFD64
15258   unsigned int a;
15259   unsigned int b;
15260
15261   FETCH_DATA (the_info, codep + 8);
15262   a = *codep++ & 0xff;
15263   a |= (*codep++ & 0xff) << 8;
15264   a |= (*codep++ & 0xff) << 16;
15265   a |= (*codep++ & 0xff) << 24;
15266   b = *codep++ & 0xff;
15267   b |= (*codep++ & 0xff) << 8;
15268   b |= (*codep++ & 0xff) << 16;
15269   b |= (*codep++ & 0xff) << 24;
15270   x = a + ((bfd_vma) b << 32);
15271 #else
15272   abort ();
15273   x = 0;
15274 #endif
15275   return x;
15276 }
15277
15278 static bfd_signed_vma
15279 get32 (void)
15280 {
15281   bfd_signed_vma x = 0;
15282
15283   FETCH_DATA (the_info, codep + 4);
15284   x = *codep++ & (bfd_signed_vma) 0xff;
15285   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15286   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15287   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15288   return x;
15289 }
15290
15291 static bfd_signed_vma
15292 get32s (void)
15293 {
15294   bfd_signed_vma x = 0;
15295
15296   FETCH_DATA (the_info, codep + 4);
15297   x = *codep++ & (bfd_signed_vma) 0xff;
15298   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15299   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15300   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15301
15302   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15303
15304   return x;
15305 }
15306
15307 static int
15308 get16 (void)
15309 {
15310   int x = 0;
15311
15312   FETCH_DATA (the_info, codep + 2);
15313   x = *codep++ & 0xff;
15314   x |= (*codep++ & 0xff) << 8;
15315   return x;
15316 }
15317
15318 static void
15319 set_op (bfd_vma op, int riprel)
15320 {
15321   op_index[op_ad] = op_ad;
15322   if (address_mode == mode_64bit)
15323     {
15324       op_address[op_ad] = op;
15325       op_riprel[op_ad] = riprel;
15326     }
15327   else
15328     {
15329       /* Mask to get a 32-bit address.  */
15330       op_address[op_ad] = op & 0xffffffff;
15331       op_riprel[op_ad] = riprel & 0xffffffff;
15332     }
15333 }
15334
15335 static void
15336 OP_REG (int code, int sizeflag)
15337 {
15338   const char *s;
15339   int add;
15340
15341   switch (code)
15342     {
15343     case es_reg: case ss_reg: case cs_reg:
15344     case ds_reg: case fs_reg: case gs_reg:
15345       oappend (names_seg[code - es_reg]);
15346       return;
15347     }
15348
15349   USED_REX (REX_B);
15350   if (rex & REX_B)
15351     add = 8;
15352   else
15353     add = 0;
15354
15355   switch (code)
15356     {
15357     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15358     case sp_reg: case bp_reg: case si_reg: case di_reg:
15359       s = names16[code - ax_reg + add];
15360       break;
15361     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15362     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15363       USED_REX (0);
15364       if (rex)
15365         s = names8rex[code - al_reg + add];
15366       else
15367         s = names8[code - al_reg];
15368       break;
15369     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15370     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15371       if (address_mode == mode_64bit
15372           && ((sizeflag & DFLAG) || (rex & REX_W)))
15373         {
15374           s = names64[code - rAX_reg + add];
15375           break;
15376         }
15377       code += eAX_reg - rAX_reg;
15378       /* Fall through.  */
15379     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15380     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15381       USED_REX (REX_W);
15382       if (rex & REX_W)
15383         s = names64[code - eAX_reg + add];
15384       else
15385         {
15386           if (sizeflag & DFLAG)
15387             s = names32[code - eAX_reg + add];
15388           else
15389             s = names16[code - eAX_reg + add];
15390           used_prefixes |= (prefixes & PREFIX_DATA);
15391         }
15392       break;
15393     default:
15394       s = INTERNAL_DISASSEMBLER_ERROR;
15395       break;
15396     }
15397   oappend (s);
15398 }
15399
15400 static void
15401 OP_IMREG (int code, int sizeflag)
15402 {
15403   const char *s;
15404
15405   switch (code)
15406     {
15407     case indir_dx_reg:
15408       if (intel_syntax)
15409         s = "dx";
15410       else
15411         s = "(%dx)";
15412       break;
15413     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15414     case sp_reg: case bp_reg: case si_reg: case di_reg:
15415       s = names16[code - ax_reg];
15416       break;
15417     case es_reg: case ss_reg: case cs_reg:
15418     case ds_reg: case fs_reg: case gs_reg:
15419       s = names_seg[code - es_reg];
15420       break;
15421     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15422     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15423       USED_REX (0);
15424       if (rex)
15425         s = names8rex[code - al_reg];
15426       else
15427         s = names8[code - al_reg];
15428       break;
15429     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15430     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15431       USED_REX (REX_W);
15432       if (rex & REX_W)
15433         s = names64[code - eAX_reg];
15434       else
15435         {
15436           if (sizeflag & DFLAG)
15437             s = names32[code - eAX_reg];
15438           else
15439             s = names16[code - eAX_reg];
15440           used_prefixes |= (prefixes & PREFIX_DATA);
15441         }
15442       break;
15443     case z_mode_ax_reg:
15444       if ((rex & REX_W) || (sizeflag & DFLAG))
15445         s = *names32;
15446       else
15447         s = *names16;
15448       if (!(rex & REX_W))
15449         used_prefixes |= (prefixes & PREFIX_DATA);
15450       break;
15451     default:
15452       s = INTERNAL_DISASSEMBLER_ERROR;
15453       break;
15454     }
15455   oappend (s);
15456 }
15457
15458 static void
15459 OP_I (int bytemode, int sizeflag)
15460 {
15461   bfd_signed_vma op;
15462   bfd_signed_vma mask = -1;
15463
15464   switch (bytemode)
15465     {
15466     case b_mode:
15467       FETCH_DATA (the_info, codep + 1);
15468       op = *codep++;
15469       mask = 0xff;
15470       break;
15471     case q_mode:
15472       if (address_mode == mode_64bit)
15473         {
15474           op = get32s ();
15475           break;
15476         }
15477       /* Fall through.  */
15478     case v_mode:
15479       USED_REX (REX_W);
15480       if (rex & REX_W)
15481         op = get32s ();
15482       else
15483         {
15484           if (sizeflag & DFLAG)
15485             {
15486               op = get32 ();
15487               mask = 0xffffffff;
15488             }
15489           else
15490             {
15491               op = get16 ();
15492               mask = 0xfffff;
15493             }
15494           used_prefixes |= (prefixes & PREFIX_DATA);
15495         }
15496       break;
15497     case w_mode:
15498       mask = 0xfffff;
15499       op = get16 ();
15500       break;
15501     case const_1_mode:
15502       if (intel_syntax)
15503         oappend ("1");
15504       return;
15505     default:
15506       oappend (INTERNAL_DISASSEMBLER_ERROR);
15507       return;
15508     }
15509
15510   op &= mask;
15511   scratchbuf[0] = '$';
15512   print_operand_value (scratchbuf + 1, 1, op);
15513   oappend_maybe_intel (scratchbuf);
15514   scratchbuf[0] = '\0';
15515 }
15516
15517 static void
15518 OP_I64 (int bytemode, int sizeflag)
15519 {
15520   bfd_signed_vma op;
15521   bfd_signed_vma mask = -1;
15522
15523   if (address_mode != mode_64bit)
15524     {
15525       OP_I (bytemode, sizeflag);
15526       return;
15527     }
15528
15529   switch (bytemode)
15530     {
15531     case b_mode:
15532       FETCH_DATA (the_info, codep + 1);
15533       op = *codep++;
15534       mask = 0xff;
15535       break;
15536     case v_mode:
15537       USED_REX (REX_W);
15538       if (rex & REX_W)
15539         op = get64 ();
15540       else
15541         {
15542           if (sizeflag & DFLAG)
15543             {
15544               op = get32 ();
15545               mask = 0xffffffff;
15546             }
15547           else
15548             {
15549               op = get16 ();
15550               mask = 0xfffff;
15551             }
15552           used_prefixes |= (prefixes & PREFIX_DATA);
15553         }
15554       break;
15555     case w_mode:
15556       mask = 0xfffff;
15557       op = get16 ();
15558       break;
15559     default:
15560       oappend (INTERNAL_DISASSEMBLER_ERROR);
15561       return;
15562     }
15563
15564   op &= mask;
15565   scratchbuf[0] = '$';
15566   print_operand_value (scratchbuf + 1, 1, op);
15567   oappend_maybe_intel (scratchbuf);
15568   scratchbuf[0] = '\0';
15569 }
15570
15571 static void
15572 OP_sI (int bytemode, int sizeflag)
15573 {
15574   bfd_signed_vma op;
15575
15576   switch (bytemode)
15577     {
15578     case b_mode:
15579     case b_T_mode:
15580       FETCH_DATA (the_info, codep + 1);
15581       op = *codep++;
15582       if ((op & 0x80) != 0)
15583         op -= 0x100;
15584       if (bytemode == b_T_mode)
15585         {
15586           if (address_mode != mode_64bit
15587               || !((sizeflag & DFLAG) || (rex & REX_W)))
15588             {
15589               /* The operand-size prefix is overridden by a REX prefix.  */
15590               if ((sizeflag & DFLAG) || (rex & REX_W))
15591                 op &= 0xffffffff;
15592               else
15593                 op &= 0xffff;
15594           }
15595         }
15596       else
15597         {
15598           if (!(rex & REX_W))
15599             {
15600               if (sizeflag & DFLAG)
15601                 op &= 0xffffffff;
15602               else
15603                 op &= 0xffff;
15604             }
15605         }
15606       break;
15607     case v_mode:
15608       /* The operand-size prefix is overridden by a REX prefix.  */
15609       if ((sizeflag & DFLAG) || (rex & REX_W))
15610         op = get32s ();
15611       else
15612         op = get16 ();
15613       break;
15614     default:
15615       oappend (INTERNAL_DISASSEMBLER_ERROR);
15616       return;
15617     }
15618
15619   scratchbuf[0] = '$';
15620   print_operand_value (scratchbuf + 1, 1, op);
15621   oappend_maybe_intel (scratchbuf);
15622 }
15623
15624 static void
15625 OP_J (int bytemode, int sizeflag)
15626 {
15627   bfd_vma disp;
15628   bfd_vma mask = -1;
15629   bfd_vma segment = 0;
15630
15631   switch (bytemode)
15632     {
15633     case b_mode:
15634       FETCH_DATA (the_info, codep + 1);
15635       disp = *codep++;
15636       if ((disp & 0x80) != 0)
15637         disp -= 0x100;
15638       break;
15639     case v_mode:
15640       USED_REX (REX_W);
15641       if ((sizeflag & DFLAG) || (rex & REX_W))
15642         disp = get32s ();
15643       else
15644         {
15645           disp = get16 ();
15646           if ((disp & 0x8000) != 0)
15647             disp -= 0x10000;
15648           /* In 16bit mode, address is wrapped around at 64k within
15649              the same segment.  Otherwise, a data16 prefix on a jump
15650              instruction means that the pc is masked to 16 bits after
15651              the displacement is added!  */
15652           mask = 0xffff;
15653           if ((prefixes & PREFIX_DATA) == 0)
15654             segment = ((start_pc + codep - start_codep)
15655                        & ~((bfd_vma) 0xffff));
15656         }
15657       if (!(rex & REX_W))
15658         used_prefixes |= (prefixes & PREFIX_DATA);
15659       break;
15660     default:
15661       oappend (INTERNAL_DISASSEMBLER_ERROR);
15662       return;
15663     }
15664   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15665   set_op (disp, 0);
15666   print_operand_value (scratchbuf, 1, disp);
15667   oappend (scratchbuf);
15668 }
15669
15670 static void
15671 OP_SEG (int bytemode, int sizeflag)
15672 {
15673   if (bytemode == w_mode)
15674     oappend (names_seg[modrm.reg]);
15675   else
15676     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15677 }
15678
15679 static void
15680 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15681 {
15682   int seg, offset;
15683
15684   if (sizeflag & DFLAG)
15685     {
15686       offset = get32 ();
15687       seg = get16 ();
15688     }
15689   else
15690     {
15691       offset = get16 ();
15692       seg = get16 ();
15693     }
15694   used_prefixes |= (prefixes & PREFIX_DATA);
15695   if (intel_syntax)
15696     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15697   else
15698     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15699   oappend (scratchbuf);
15700 }
15701
15702 static void
15703 OP_OFF (int bytemode, int sizeflag)
15704 {
15705   bfd_vma off;
15706
15707   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15708     intel_operand_size (bytemode, sizeflag);
15709   append_seg ();
15710
15711   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15712     off = get32 ();
15713   else
15714     off = get16 ();
15715
15716   if (intel_syntax)
15717     {
15718       if (!active_seg_prefix)
15719         {
15720           oappend (names_seg[ds_reg - es_reg]);
15721           oappend (":");
15722         }
15723     }
15724   print_operand_value (scratchbuf, 1, off);
15725   oappend (scratchbuf);
15726 }
15727
15728 static void
15729 OP_OFF64 (int bytemode, int sizeflag)
15730 {
15731   bfd_vma off;
15732
15733   if (address_mode != mode_64bit
15734       || (prefixes & PREFIX_ADDR))
15735     {
15736       OP_OFF (bytemode, sizeflag);
15737       return;
15738     }
15739
15740   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15741     intel_operand_size (bytemode, sizeflag);
15742   append_seg ();
15743
15744   off = get64 ();
15745
15746   if (intel_syntax)
15747     {
15748       if (!active_seg_prefix)
15749         {
15750           oappend (names_seg[ds_reg - es_reg]);
15751           oappend (":");
15752         }
15753     }
15754   print_operand_value (scratchbuf, 1, off);
15755   oappend (scratchbuf);
15756 }
15757
15758 static void
15759 ptr_reg (int code, int sizeflag)
15760 {
15761   const char *s;
15762
15763   *obufp++ = open_char;
15764   used_prefixes |= (prefixes & PREFIX_ADDR);
15765   if (address_mode == mode_64bit)
15766     {
15767       if (!(sizeflag & AFLAG))
15768         s = names32[code - eAX_reg];
15769       else
15770         s = names64[code - eAX_reg];
15771     }
15772   else if (sizeflag & AFLAG)
15773     s = names32[code - eAX_reg];
15774   else
15775     s = names16[code - eAX_reg];
15776   oappend (s);
15777   *obufp++ = close_char;
15778   *obufp = 0;
15779 }
15780
15781 static void
15782 OP_ESreg (int code, int sizeflag)
15783 {
15784   if (intel_syntax)
15785     {
15786       switch (codep[-1])
15787         {
15788         case 0x6d:      /* insw/insl */
15789           intel_operand_size (z_mode, sizeflag);
15790           break;
15791         case 0xa5:      /* movsw/movsl/movsq */
15792         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15793         case 0xab:      /* stosw/stosl */
15794         case 0xaf:      /* scasw/scasl */
15795           intel_operand_size (v_mode, sizeflag);
15796           break;
15797         default:
15798           intel_operand_size (b_mode, sizeflag);
15799         }
15800     }
15801   oappend_maybe_intel ("%es:");
15802   ptr_reg (code, sizeflag);
15803 }
15804
15805 static void
15806 OP_DSreg (int code, int sizeflag)
15807 {
15808   if (intel_syntax)
15809     {
15810       switch (codep[-1])
15811         {
15812         case 0x6f:      /* outsw/outsl */
15813           intel_operand_size (z_mode, sizeflag);
15814           break;
15815         case 0xa5:      /* movsw/movsl/movsq */
15816         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15817         case 0xad:      /* lodsw/lodsl/lodsq */
15818           intel_operand_size (v_mode, sizeflag);
15819           break;
15820         default:
15821           intel_operand_size (b_mode, sizeflag);
15822         }
15823     }
15824   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15825      default segment register DS is printed.  */
15826   if (!active_seg_prefix)
15827     active_seg_prefix = PREFIX_DS;
15828   append_seg ();
15829   ptr_reg (code, sizeflag);
15830 }
15831
15832 static void
15833 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15834 {
15835   int add;
15836   if (rex & REX_R)
15837     {
15838       USED_REX (REX_R);
15839       add = 8;
15840     }
15841   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15842     {
15843       all_prefixes[last_lock_prefix] = 0;
15844       used_prefixes |= PREFIX_LOCK;
15845       add = 8;
15846     }
15847   else
15848     add = 0;
15849   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15850   oappend_maybe_intel (scratchbuf);
15851 }
15852
15853 static void
15854 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15855 {
15856   int add;
15857   USED_REX (REX_R);
15858   if (rex & REX_R)
15859     add = 8;
15860   else
15861     add = 0;
15862   if (intel_syntax)
15863     sprintf (scratchbuf, "db%d", modrm.reg + add);
15864   else
15865     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15866   oappend (scratchbuf);
15867 }
15868
15869 static void
15870 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15871 {
15872   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15873   oappend_maybe_intel (scratchbuf);
15874 }
15875
15876 static void
15877 OP_R (int bytemode, int sizeflag)
15878 {
15879   /* Skip mod/rm byte.  */
15880   MODRM_CHECK;
15881   codep++;
15882   OP_E_register (bytemode, sizeflag);
15883 }
15884
15885 static void
15886 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15887 {
15888   int reg = modrm.reg;
15889   const char **names;
15890
15891   used_prefixes |= (prefixes & PREFIX_DATA);
15892   if (prefixes & PREFIX_DATA)
15893     {
15894       names = names_xmm;
15895       USED_REX (REX_R);
15896       if (rex & REX_R)
15897         reg += 8;
15898     }
15899   else
15900     names = names_mm;
15901   oappend (names[reg]);
15902 }
15903
15904 static void
15905 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15906 {
15907   int reg = modrm.reg;
15908   const char **names;
15909
15910   USED_REX (REX_R);
15911   if (rex & REX_R)
15912     reg += 8;
15913   if (vex.evex)
15914     {
15915       if (!vex.r)
15916         reg += 16;
15917     }
15918
15919   if (need_vex
15920       && bytemode != xmm_mode
15921       && bytemode != xmmq_mode
15922       && bytemode != evex_half_bcst_xmmq_mode
15923       && bytemode != ymm_mode
15924       && bytemode != scalar_mode)
15925     {
15926       switch (vex.length)
15927         {
15928         case 128:
15929           names = names_xmm;
15930           break;
15931         case 256:
15932           if (vex.w
15933               || (bytemode != vex_vsib_q_w_dq_mode
15934                   && bytemode != vex_vsib_q_w_d_mode))
15935             names = names_ymm;
15936           else
15937             names = names_xmm;
15938           break;
15939         case 512:
15940           names = names_zmm;
15941           break;
15942         default:
15943           abort ();
15944         }
15945     }
15946   else if (bytemode == xmmq_mode
15947            || bytemode == evex_half_bcst_xmmq_mode)
15948     {
15949       switch (vex.length)
15950         {
15951         case 128:
15952         case 256:
15953           names = names_xmm;
15954           break;
15955         case 512:
15956           names = names_ymm;
15957           break;
15958         default:
15959           abort ();
15960         }
15961     }
15962   else if (bytemode == ymm_mode)
15963     names = names_ymm;
15964   else
15965     names = names_xmm;
15966   oappend (names[reg]);
15967 }
15968
15969 static void
15970 OP_EM (int bytemode, int sizeflag)
15971 {
15972   int reg;
15973   const char **names;
15974
15975   if (modrm.mod != 3)
15976     {
15977       if (intel_syntax
15978           && (bytemode == v_mode || bytemode == v_swap_mode))
15979         {
15980           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15981           used_prefixes |= (prefixes & PREFIX_DATA);
15982         }
15983       OP_E (bytemode, sizeflag);
15984       return;
15985     }
15986
15987   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15988     swap_operand ();
15989
15990   /* Skip mod/rm byte.  */
15991   MODRM_CHECK;
15992   codep++;
15993   used_prefixes |= (prefixes & PREFIX_DATA);
15994   reg = modrm.rm;
15995   if (prefixes & PREFIX_DATA)
15996     {
15997       names = names_xmm;
15998       USED_REX (REX_B);
15999       if (rex & REX_B)
16000         reg += 8;
16001     }
16002   else
16003     names = names_mm;
16004   oappend (names[reg]);
16005 }
16006
16007 /* cvt* are the only instructions in sse2 which have
16008    both SSE and MMX operands and also have 0x66 prefix
16009    in their opcode. 0x66 was originally used to differentiate
16010    between SSE and MMX instruction(operands). So we have to handle the
16011    cvt* separately using OP_EMC and OP_MXC */
16012 static void
16013 OP_EMC (int bytemode, int sizeflag)
16014 {
16015   if (modrm.mod != 3)
16016     {
16017       if (intel_syntax && bytemode == v_mode)
16018         {
16019           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16020           used_prefixes |= (prefixes & PREFIX_DATA);
16021         }
16022       OP_E (bytemode, sizeflag);
16023       return;
16024     }
16025
16026   /* Skip mod/rm byte.  */
16027   MODRM_CHECK;
16028   codep++;
16029   used_prefixes |= (prefixes & PREFIX_DATA);
16030   oappend (names_mm[modrm.rm]);
16031 }
16032
16033 static void
16034 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16035 {
16036   used_prefixes |= (prefixes & PREFIX_DATA);
16037   oappend (names_mm[modrm.reg]);
16038 }
16039
16040 static void
16041 OP_EX (int bytemode, int sizeflag)
16042 {
16043   int reg;
16044   const char **names;
16045
16046   /* Skip mod/rm byte.  */
16047   MODRM_CHECK;
16048   codep++;
16049
16050   if (modrm.mod != 3)
16051     {
16052       OP_E_memory (bytemode, sizeflag);
16053       return;
16054     }
16055
16056   reg = modrm.rm;
16057   USED_REX (REX_B);
16058   if (rex & REX_B)
16059     reg += 8;
16060   if (vex.evex)
16061     {
16062       USED_REX (REX_X);
16063       if ((rex & REX_X))
16064         reg += 16;
16065     }
16066
16067   if ((sizeflag & SUFFIX_ALWAYS)
16068       && (bytemode == x_swap_mode
16069           || bytemode == d_swap_mode
16070           || bytemode == dqw_swap_mode
16071           || bytemode == d_scalar_swap_mode
16072           || bytemode == q_swap_mode
16073           || bytemode == q_scalar_swap_mode))
16074     swap_operand ();
16075
16076   if (need_vex
16077       && bytemode != xmm_mode
16078       && bytemode != xmmdw_mode
16079       && bytemode != xmmqd_mode
16080       && bytemode != xmm_mb_mode
16081       && bytemode != xmm_mw_mode
16082       && bytemode != xmm_md_mode
16083       && bytemode != xmm_mq_mode
16084       && bytemode != xmm_mdq_mode
16085       && bytemode != xmmq_mode
16086       && bytemode != evex_half_bcst_xmmq_mode
16087       && bytemode != ymm_mode
16088       && bytemode != d_scalar_mode
16089       && bytemode != d_scalar_swap_mode
16090       && bytemode != q_scalar_mode
16091       && bytemode != q_scalar_swap_mode
16092       && bytemode != vex_scalar_w_dq_mode)
16093     {
16094       switch (vex.length)
16095         {
16096         case 128:
16097           names = names_xmm;
16098           break;
16099         case 256:
16100           names = names_ymm;
16101           break;
16102         case 512:
16103           names = names_zmm;
16104           break;
16105         default:
16106           abort ();
16107         }
16108     }
16109   else if (bytemode == xmmq_mode
16110            || bytemode == evex_half_bcst_xmmq_mode)
16111     {
16112       switch (vex.length)
16113         {
16114         case 128:
16115         case 256:
16116           names = names_xmm;
16117           break;
16118         case 512:
16119           names = names_ymm;
16120           break;
16121         default:
16122           abort ();
16123         }
16124     }
16125   else if (bytemode == ymm_mode)
16126     names = names_ymm;
16127   else
16128     names = names_xmm;
16129   oappend (names[reg]);
16130 }
16131
16132 static void
16133 OP_MS (int bytemode, int sizeflag)
16134 {
16135   if (modrm.mod == 3)
16136     OP_EM (bytemode, sizeflag);
16137   else
16138     BadOp ();
16139 }
16140
16141 static void
16142 OP_XS (int bytemode, int sizeflag)
16143 {
16144   if (modrm.mod == 3)
16145     OP_EX (bytemode, sizeflag);
16146   else
16147     BadOp ();
16148 }
16149
16150 static void
16151 OP_M (int bytemode, int sizeflag)
16152 {
16153   if (modrm.mod == 3)
16154     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16155     BadOp ();
16156   else
16157     OP_E (bytemode, sizeflag);
16158 }
16159
16160 static void
16161 OP_0f07 (int bytemode, int sizeflag)
16162 {
16163   if (modrm.mod != 3 || modrm.rm != 0)
16164     BadOp ();
16165   else
16166     OP_E (bytemode, sizeflag);
16167 }
16168
16169 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16170    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16171
16172 static void
16173 NOP_Fixup1 (int bytemode, int sizeflag)
16174 {
16175   if ((prefixes & PREFIX_DATA) != 0
16176       || (rex != 0
16177           && rex != 0x48
16178           && address_mode == mode_64bit))
16179     OP_REG (bytemode, sizeflag);
16180   else
16181     strcpy (obuf, "nop");
16182 }
16183
16184 static void
16185 NOP_Fixup2 (int bytemode, int sizeflag)
16186 {
16187   if ((prefixes & PREFIX_DATA) != 0
16188       || (rex != 0
16189           && rex != 0x48
16190           && address_mode == mode_64bit))
16191     OP_IMREG (bytemode, sizeflag);
16192 }
16193
16194 static const char *const Suffix3DNow[] = {
16195 /* 00 */        NULL,           NULL,           NULL,           NULL,
16196 /* 04 */        NULL,           NULL,           NULL,           NULL,
16197 /* 08 */        NULL,           NULL,           NULL,           NULL,
16198 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16199 /* 10 */        NULL,           NULL,           NULL,           NULL,
16200 /* 14 */        NULL,           NULL,           NULL,           NULL,
16201 /* 18 */        NULL,           NULL,           NULL,           NULL,
16202 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16203 /* 20 */        NULL,           NULL,           NULL,           NULL,
16204 /* 24 */        NULL,           NULL,           NULL,           NULL,
16205 /* 28 */        NULL,           NULL,           NULL,           NULL,
16206 /* 2C */        NULL,           NULL,           NULL,           NULL,
16207 /* 30 */        NULL,           NULL,           NULL,           NULL,
16208 /* 34 */        NULL,           NULL,           NULL,           NULL,
16209 /* 38 */        NULL,           NULL,           NULL,           NULL,
16210 /* 3C */        NULL,           NULL,           NULL,           NULL,
16211 /* 40 */        NULL,           NULL,           NULL,           NULL,
16212 /* 44 */        NULL,           NULL,           NULL,           NULL,
16213 /* 48 */        NULL,           NULL,           NULL,           NULL,
16214 /* 4C */        NULL,           NULL,           NULL,           NULL,
16215 /* 50 */        NULL,           NULL,           NULL,           NULL,
16216 /* 54 */        NULL,           NULL,           NULL,           NULL,
16217 /* 58 */        NULL,           NULL,           NULL,           NULL,
16218 /* 5C */        NULL,           NULL,           NULL,           NULL,
16219 /* 60 */        NULL,           NULL,           NULL,           NULL,
16220 /* 64 */        NULL,           NULL,           NULL,           NULL,
16221 /* 68 */        NULL,           NULL,           NULL,           NULL,
16222 /* 6C */        NULL,           NULL,           NULL,           NULL,
16223 /* 70 */        NULL,           NULL,           NULL,           NULL,
16224 /* 74 */        NULL,           NULL,           NULL,           NULL,
16225 /* 78 */        NULL,           NULL,           NULL,           NULL,
16226 /* 7C */        NULL,           NULL,           NULL,           NULL,
16227 /* 80 */        NULL,           NULL,           NULL,           NULL,
16228 /* 84 */        NULL,           NULL,           NULL,           NULL,
16229 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16230 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16231 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16232 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16233 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16234 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16235 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16236 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16237 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16238 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16239 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16240 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16241 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16242 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16243 /* C0 */        NULL,           NULL,           NULL,           NULL,
16244 /* C4 */        NULL,           NULL,           NULL,           NULL,
16245 /* C8 */        NULL,           NULL,           NULL,           NULL,
16246 /* CC */        NULL,           NULL,           NULL,           NULL,
16247 /* D0 */        NULL,           NULL,           NULL,           NULL,
16248 /* D4 */        NULL,           NULL,           NULL,           NULL,
16249 /* D8 */        NULL,           NULL,           NULL,           NULL,
16250 /* DC */        NULL,           NULL,           NULL,           NULL,
16251 /* E0 */        NULL,           NULL,           NULL,           NULL,
16252 /* E4 */        NULL,           NULL,           NULL,           NULL,
16253 /* E8 */        NULL,           NULL,           NULL,           NULL,
16254 /* EC */        NULL,           NULL,           NULL,           NULL,
16255 /* F0 */        NULL,           NULL,           NULL,           NULL,
16256 /* F4 */        NULL,           NULL,           NULL,           NULL,
16257 /* F8 */        NULL,           NULL,           NULL,           NULL,
16258 /* FC */        NULL,           NULL,           NULL,           NULL,
16259 };
16260
16261 static void
16262 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16263 {
16264   const char *mnemonic;
16265
16266   FETCH_DATA (the_info, codep + 1);
16267   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16268      place where an 8-bit immediate would normally go.  ie. the last
16269      byte of the instruction.  */
16270   obufp = mnemonicendp;
16271   mnemonic = Suffix3DNow[*codep++ & 0xff];
16272   if (mnemonic)
16273     oappend (mnemonic);
16274   else
16275     {
16276       /* Since a variable sized modrm/sib chunk is between the start
16277          of the opcode (0x0f0f) and the opcode suffix, we need to do
16278          all the modrm processing first, and don't know until now that
16279          we have a bad opcode.  This necessitates some cleaning up.  */
16280       op_out[0][0] = '\0';
16281       op_out[1][0] = '\0';
16282       BadOp ();
16283     }
16284   mnemonicendp = obufp;
16285 }
16286
16287 static struct op simd_cmp_op[] =
16288 {
16289   { STRING_COMMA_LEN ("eq") },
16290   { STRING_COMMA_LEN ("lt") },
16291   { STRING_COMMA_LEN ("le") },
16292   { STRING_COMMA_LEN ("unord") },
16293   { STRING_COMMA_LEN ("neq") },
16294   { STRING_COMMA_LEN ("nlt") },
16295   { STRING_COMMA_LEN ("nle") },
16296   { STRING_COMMA_LEN ("ord") }
16297 };
16298
16299 static void
16300 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16301 {
16302   unsigned int cmp_type;
16303
16304   FETCH_DATA (the_info, codep + 1);
16305   cmp_type = *codep++ & 0xff;
16306   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16307     {
16308       char suffix [3];
16309       char *p = mnemonicendp - 2;
16310       suffix[0] = p[0];
16311       suffix[1] = p[1];
16312       suffix[2] = '\0';
16313       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16314       mnemonicendp += simd_cmp_op[cmp_type].len;
16315     }
16316   else
16317     {
16318       /* We have a reserved extension byte.  Output it directly.  */
16319       scratchbuf[0] = '$';
16320       print_operand_value (scratchbuf + 1, 1, cmp_type);
16321       oappend_maybe_intel (scratchbuf);
16322       scratchbuf[0] = '\0';
16323     }
16324 }
16325
16326 static void
16327 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16328           int sizeflag ATTRIBUTE_UNUSED)
16329 {
16330   /* mwait %eax,%ecx  */
16331   if (!intel_syntax)
16332     {
16333       const char **names = (address_mode == mode_64bit
16334                             ? names64 : names32);
16335       strcpy (op_out[0], names[0]);
16336       strcpy (op_out[1], names[1]);
16337       two_source_ops = 1;
16338     }
16339   /* Skip mod/rm byte.  */
16340   MODRM_CHECK;
16341   codep++;
16342 }
16343
16344 static void
16345 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16346             int sizeflag ATTRIBUTE_UNUSED)
16347 {
16348   /* monitor %eax,%ecx,%edx"  */
16349   if (!intel_syntax)
16350     {
16351       const char **op1_names;
16352       const char **names = (address_mode == mode_64bit
16353                             ? names64 : names32);
16354
16355       if (!(prefixes & PREFIX_ADDR))
16356         op1_names = (address_mode == mode_16bit
16357                      ? names16 : names);
16358       else
16359         {
16360           /* Remove "addr16/addr32".  */
16361           all_prefixes[last_addr_prefix] = 0;
16362           op1_names = (address_mode != mode_32bit
16363                        ? names32 : names16);
16364           used_prefixes |= PREFIX_ADDR;
16365         }
16366       strcpy (op_out[0], op1_names[0]);
16367       strcpy (op_out[1], names[1]);
16368       strcpy (op_out[2], names[2]);
16369       two_source_ops = 1;
16370     }
16371   /* Skip mod/rm byte.  */
16372   MODRM_CHECK;
16373   codep++;
16374 }
16375
16376 static void
16377 BadOp (void)
16378 {
16379   /* Throw away prefixes and 1st. opcode byte.  */
16380   codep = insn_codep + 1;
16381   oappend ("(bad)");
16382 }
16383
16384 static void
16385 REP_Fixup (int bytemode, int sizeflag)
16386 {
16387   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16388      lods and stos.  */
16389   if (prefixes & PREFIX_REPZ)
16390     all_prefixes[last_repz_prefix] = REP_PREFIX;
16391
16392   switch (bytemode)
16393     {
16394     case al_reg:
16395     case eAX_reg:
16396     case indir_dx_reg:
16397       OP_IMREG (bytemode, sizeflag);
16398       break;
16399     case eDI_reg:
16400       OP_ESreg (bytemode, sizeflag);
16401       break;
16402     case eSI_reg:
16403       OP_DSreg (bytemode, sizeflag);
16404       break;
16405     default:
16406       abort ();
16407       break;
16408     }
16409 }
16410
16411 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16412    "bnd".  */
16413
16414 static void
16415 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16416 {
16417   if (prefixes & PREFIX_REPNZ)
16418     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16419 }
16420
16421 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16422    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16423  */
16424
16425 static void
16426 HLE_Fixup1 (int bytemode, int sizeflag)
16427 {
16428   if (modrm.mod != 3
16429       && (prefixes & PREFIX_LOCK) != 0)
16430     {
16431       if (prefixes & PREFIX_REPZ)
16432         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16433       if (prefixes & PREFIX_REPNZ)
16434         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16435     }
16436
16437   OP_E (bytemode, sizeflag);
16438 }
16439
16440 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16441    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16442  */
16443
16444 static void
16445 HLE_Fixup2 (int bytemode, int sizeflag)
16446 {
16447   if (modrm.mod != 3)
16448     {
16449       if (prefixes & PREFIX_REPZ)
16450         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16451       if (prefixes & PREFIX_REPNZ)
16452         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16453     }
16454
16455   OP_E (bytemode, sizeflag);
16456 }
16457
16458 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16459    "xrelease" for memory operand.  No check for LOCK prefix.   */
16460
16461 static void
16462 HLE_Fixup3 (int bytemode, int sizeflag)
16463 {
16464   if (modrm.mod != 3
16465       && last_repz_prefix > last_repnz_prefix
16466       && (prefixes & PREFIX_REPZ) != 0)
16467     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16468
16469   OP_E (bytemode, sizeflag);
16470 }
16471
16472 static void
16473 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16474 {
16475   USED_REX (REX_W);
16476   if (rex & REX_W)
16477     {
16478       /* Change cmpxchg8b to cmpxchg16b.  */
16479       char *p = mnemonicendp - 2;
16480       mnemonicendp = stpcpy (p, "16b");
16481       bytemode = o_mode;
16482     }
16483   else if ((prefixes & PREFIX_LOCK) != 0)
16484     {
16485       if (prefixes & PREFIX_REPZ)
16486         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16487       if (prefixes & PREFIX_REPNZ)
16488         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16489     }
16490
16491   OP_M (bytemode, sizeflag);
16492 }
16493
16494 static void
16495 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16496 {
16497   const char **names;
16498
16499   if (need_vex)
16500     {
16501       switch (vex.length)
16502         {
16503         case 128:
16504           names = names_xmm;
16505           break;
16506         case 256:
16507           names = names_ymm;
16508           break;
16509         default:
16510           abort ();
16511         }
16512     }
16513   else
16514     names = names_xmm;
16515   oappend (names[reg]);
16516 }
16517
16518 static void
16519 CRC32_Fixup (int bytemode, int sizeflag)
16520 {
16521   /* Add proper suffix to "crc32".  */
16522   char *p = mnemonicendp;
16523
16524   switch (bytemode)
16525     {
16526     case b_mode:
16527       if (intel_syntax)
16528         goto skip;
16529
16530       *p++ = 'b';
16531       break;
16532     case v_mode:
16533       if (intel_syntax)
16534         goto skip;
16535
16536       USED_REX (REX_W);
16537       if (rex & REX_W)
16538         *p++ = 'q';
16539       else
16540         {
16541           if (sizeflag & DFLAG)
16542             *p++ = 'l';
16543           else
16544             *p++ = 'w';
16545           used_prefixes |= (prefixes & PREFIX_DATA);
16546         }
16547       break;
16548     default:
16549       oappend (INTERNAL_DISASSEMBLER_ERROR);
16550       break;
16551     }
16552   mnemonicendp = p;
16553   *p = '\0';
16554
16555 skip:
16556   if (modrm.mod == 3)
16557     {
16558       int add;
16559
16560       /* Skip mod/rm byte.  */
16561       MODRM_CHECK;
16562       codep++;
16563
16564       USED_REX (REX_B);
16565       add = (rex & REX_B) ? 8 : 0;
16566       if (bytemode == b_mode)
16567         {
16568           USED_REX (0);
16569           if (rex)
16570             oappend (names8rex[modrm.rm + add]);
16571           else
16572             oappend (names8[modrm.rm + add]);
16573         }
16574       else
16575         {
16576           USED_REX (REX_W);
16577           if (rex & REX_W)
16578             oappend (names64[modrm.rm + add]);
16579           else if ((prefixes & PREFIX_DATA))
16580             oappend (names16[modrm.rm + add]);
16581           else
16582             oappend (names32[modrm.rm + add]);
16583         }
16584     }
16585   else
16586     OP_E (bytemode, sizeflag);
16587 }
16588
16589 static void
16590 FXSAVE_Fixup (int bytemode, int sizeflag)
16591 {
16592   /* Add proper suffix to "fxsave" and "fxrstor".  */
16593   USED_REX (REX_W);
16594   if (rex & REX_W)
16595     {
16596       char *p = mnemonicendp;
16597       *p++ = '6';
16598       *p++ = '4';
16599       *p = '\0';
16600       mnemonicendp = p;
16601     }
16602   OP_M (bytemode, sizeflag);
16603 }
16604
16605 /* Display the destination register operand for instructions with
16606    VEX. */
16607
16608 static void
16609 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16610 {
16611   int reg;
16612   const char **names;
16613
16614   if (!need_vex)
16615     abort ();
16616
16617   if (!need_vex_reg)
16618     return;
16619
16620   reg = vex.register_specifier;
16621   if (vex.evex)
16622     {
16623       if (!vex.v)
16624         reg += 16;
16625     }
16626
16627   if (bytemode == vex_scalar_mode)
16628     {
16629       oappend (names_xmm[reg]);
16630       return;
16631     }
16632
16633   switch (vex.length)
16634     {
16635     case 128:
16636       switch (bytemode)
16637         {
16638         case vex_mode:
16639         case vex128_mode:
16640         case vex_vsib_q_w_dq_mode:
16641         case vex_vsib_q_w_d_mode:
16642           names = names_xmm;
16643           break;
16644         case dq_mode:
16645           if (vex.w)
16646             names = names64;
16647           else
16648             names = names32;
16649           break;
16650         case mask_bd_mode:
16651         case mask_mode:
16652           names = names_mask;
16653           break;
16654         default:
16655           abort ();
16656           return;
16657         }
16658       break;
16659     case 256:
16660       switch (bytemode)
16661         {
16662         case vex_mode:
16663         case vex256_mode:
16664           names = names_ymm;
16665           break;
16666         case vex_vsib_q_w_dq_mode:
16667         case vex_vsib_q_w_d_mode:
16668           names = vex.w ? names_ymm : names_xmm;
16669           break;
16670         case mask_bd_mode:
16671         case mask_mode:
16672           names = names_mask;
16673           break;
16674         default:
16675           abort ();
16676           return;
16677         }
16678       break;
16679     case 512:
16680       names = names_zmm;
16681       break;
16682     default:
16683       abort ();
16684       break;
16685     }
16686   oappend (names[reg]);
16687 }
16688
16689 /* Get the VEX immediate byte without moving codep.  */
16690
16691 static unsigned char
16692 get_vex_imm8 (int sizeflag, int opnum)
16693 {
16694   int bytes_before_imm = 0;
16695
16696   if (modrm.mod != 3)
16697     {
16698       /* There are SIB/displacement bytes.  */
16699       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16700         {
16701           /* 32/64 bit address mode */
16702           int base = modrm.rm;
16703
16704           /* Check SIB byte.  */
16705           if (base == 4)
16706             {
16707               FETCH_DATA (the_info, codep + 1);
16708               base = *codep & 7;
16709               /* When decoding the third source, don't increase
16710                  bytes_before_imm as this has already been incremented
16711                  by one in OP_E_memory while decoding the second
16712                  source operand.  */
16713               if (opnum == 0)
16714                 bytes_before_imm++;
16715             }
16716
16717           /* Don't increase bytes_before_imm when decoding the third source,
16718              it has already been incremented by OP_E_memory while decoding
16719              the second source operand.  */
16720           if (opnum == 0)
16721             {
16722               switch (modrm.mod)
16723                 {
16724                   case 0:
16725                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16726                        SIB == 5, there is a 4 byte displacement.  */
16727                     if (base != 5)
16728                       /* No displacement. */
16729                       break;
16730                   case 2:
16731                     /* 4 byte displacement.  */
16732                     bytes_before_imm += 4;
16733                     break;
16734                   case 1:
16735                     /* 1 byte displacement.  */
16736                     bytes_before_imm++;
16737                     break;
16738                 }
16739             }
16740         }
16741       else
16742         {
16743           /* 16 bit address mode */
16744           /* Don't increase bytes_before_imm when decoding the third source,
16745              it has already been incremented by OP_E_memory while decoding
16746              the second source operand.  */
16747           if (opnum == 0)
16748             {
16749               switch (modrm.mod)
16750                 {
16751                 case 0:
16752                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16753                   if (modrm.rm != 6)
16754                     /* No displacement. */
16755                     break;
16756                 case 2:
16757                   /* 2 byte displacement.  */
16758                   bytes_before_imm += 2;
16759                   break;
16760                 case 1:
16761                   /* 1 byte displacement: when decoding the third source,
16762                      don't increase bytes_before_imm as this has already
16763                      been incremented by one in OP_E_memory while decoding
16764                      the second source operand.  */
16765                   if (opnum == 0)
16766                     bytes_before_imm++;
16767
16768                   break;
16769                 }
16770             }
16771         }
16772     }
16773
16774   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16775   return codep [bytes_before_imm];
16776 }
16777
16778 static void
16779 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16780 {
16781   const char **names;
16782
16783   if (reg == -1 && modrm.mod != 3)
16784     {
16785       OP_E_memory (bytemode, sizeflag);
16786       return;
16787     }
16788   else
16789     {
16790       if (reg == -1)
16791         {
16792           reg = modrm.rm;
16793           USED_REX (REX_B);
16794           if (rex & REX_B)
16795             reg += 8;
16796         }
16797       else if (reg > 7 && address_mode != mode_64bit)
16798         BadOp ();
16799     }
16800
16801   switch (vex.length)
16802     {
16803     case 128:
16804       names = names_xmm;
16805       break;
16806     case 256:
16807       names = names_ymm;
16808       break;
16809     default:
16810       abort ();
16811     }
16812   oappend (names[reg]);
16813 }
16814
16815 static void
16816 OP_EX_VexImmW (int bytemode, int sizeflag)
16817 {
16818   int reg = -1;
16819   static unsigned char vex_imm8;
16820
16821   if (vex_w_done == 0)
16822     {
16823       vex_w_done = 1;
16824
16825       /* Skip mod/rm byte.  */
16826       MODRM_CHECK;
16827       codep++;
16828
16829       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16830
16831       if (vex.w)
16832           reg = vex_imm8 >> 4;
16833
16834       OP_EX_VexReg (bytemode, sizeflag, reg);
16835     }
16836   else if (vex_w_done == 1)
16837     {
16838       vex_w_done = 2;
16839
16840       if (!vex.w)
16841           reg = vex_imm8 >> 4;
16842
16843       OP_EX_VexReg (bytemode, sizeflag, reg);
16844     }
16845   else
16846     {
16847       /* Output the imm8 directly.  */
16848       scratchbuf[0] = '$';
16849       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16850       oappend_maybe_intel (scratchbuf);
16851       scratchbuf[0] = '\0';
16852       codep++;
16853     }
16854 }
16855
16856 static void
16857 OP_Vex_2src (int bytemode, int sizeflag)
16858 {
16859   if (modrm.mod == 3)
16860     {
16861       int reg = modrm.rm;
16862       USED_REX (REX_B);
16863       if (rex & REX_B)
16864         reg += 8;
16865       oappend (names_xmm[reg]);
16866     }
16867   else
16868     {
16869       if (intel_syntax
16870           && (bytemode == v_mode || bytemode == v_swap_mode))
16871         {
16872           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16873           used_prefixes |= (prefixes & PREFIX_DATA);
16874         }
16875       OP_E (bytemode, sizeflag);
16876     }
16877 }
16878
16879 static void
16880 OP_Vex_2src_1 (int bytemode, int sizeflag)
16881 {
16882   if (modrm.mod == 3)
16883     {
16884       /* Skip mod/rm byte.   */
16885       MODRM_CHECK;
16886       codep++;
16887     }
16888
16889   if (vex.w)
16890     oappend (names_xmm[vex.register_specifier]);
16891   else
16892     OP_Vex_2src (bytemode, sizeflag);
16893 }
16894
16895 static void
16896 OP_Vex_2src_2 (int bytemode, int sizeflag)
16897 {
16898   if (vex.w)
16899     OP_Vex_2src (bytemode, sizeflag);
16900   else
16901     oappend (names_xmm[vex.register_specifier]);
16902 }
16903
16904 static void
16905 OP_EX_VexW (int bytemode, int sizeflag)
16906 {
16907   int reg = -1;
16908
16909   if (!vex_w_done)
16910     {
16911       vex_w_done = 1;
16912
16913       /* Skip mod/rm byte.  */
16914       MODRM_CHECK;
16915       codep++;
16916
16917       if (vex.w)
16918         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16919     }
16920   else
16921     {
16922       if (!vex.w)
16923         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16924     }
16925
16926   OP_EX_VexReg (bytemode, sizeflag, reg);
16927 }
16928
16929 static void
16930 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16931              int sizeflag ATTRIBUTE_UNUSED)
16932 {
16933   /* Skip the immediate byte and check for invalid bits.  */
16934   FETCH_DATA (the_info, codep + 1);
16935   if (*codep++ & 0xf)
16936     BadOp ();
16937 }
16938
16939 static void
16940 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16941 {
16942   int reg;
16943   const char **names;
16944
16945   FETCH_DATA (the_info, codep + 1);
16946   reg = *codep++;
16947
16948   if (bytemode != x_mode)
16949     abort ();
16950
16951   if (reg & 0xf)
16952       BadOp ();
16953
16954   reg >>= 4;
16955   if (reg > 7 && address_mode != mode_64bit)
16956     BadOp ();
16957
16958   switch (vex.length)
16959     {
16960     case 128:
16961       names = names_xmm;
16962       break;
16963     case 256:
16964       names = names_ymm;
16965       break;
16966     default:
16967       abort ();
16968     }
16969   oappend (names[reg]);
16970 }
16971
16972 static void
16973 OP_XMM_VexW (int bytemode, int sizeflag)
16974 {
16975   /* Turn off the REX.W bit since it is used for swapping operands
16976      now.  */
16977   rex &= ~REX_W;
16978   OP_XMM (bytemode, sizeflag);
16979 }
16980
16981 static void
16982 OP_EX_Vex (int bytemode, int sizeflag)
16983 {
16984   if (modrm.mod != 3)
16985     {
16986       if (vex.register_specifier != 0)
16987         BadOp ();
16988       need_vex_reg = 0;
16989     }
16990   OP_EX (bytemode, sizeflag);
16991 }
16992
16993 static void
16994 OP_XMM_Vex (int bytemode, int sizeflag)
16995 {
16996   if (modrm.mod != 3)
16997     {
16998       if (vex.register_specifier != 0)
16999         BadOp ();
17000       need_vex_reg = 0;
17001     }
17002   OP_XMM (bytemode, sizeflag);
17003 }
17004
17005 static void
17006 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17007 {
17008   switch (vex.length)
17009     {
17010     case 128:
17011       mnemonicendp = stpcpy (obuf, "vzeroupper");
17012       break;
17013     case 256:
17014       mnemonicendp = stpcpy (obuf, "vzeroall");
17015       break;
17016     default:
17017       abort ();
17018     }
17019 }
17020
17021 static struct op vex_cmp_op[] =
17022 {
17023   { STRING_COMMA_LEN ("eq") },
17024   { STRING_COMMA_LEN ("lt") },
17025   { STRING_COMMA_LEN ("le") },
17026   { STRING_COMMA_LEN ("unord") },
17027   { STRING_COMMA_LEN ("neq") },
17028   { STRING_COMMA_LEN ("nlt") },
17029   { STRING_COMMA_LEN ("nle") },
17030   { STRING_COMMA_LEN ("ord") },
17031   { STRING_COMMA_LEN ("eq_uq") },
17032   { STRING_COMMA_LEN ("nge") },
17033   { STRING_COMMA_LEN ("ngt") },
17034   { STRING_COMMA_LEN ("false") },
17035   { STRING_COMMA_LEN ("neq_oq") },
17036   { STRING_COMMA_LEN ("ge") },
17037   { STRING_COMMA_LEN ("gt") },
17038   { STRING_COMMA_LEN ("true") },
17039   { STRING_COMMA_LEN ("eq_os") },
17040   { STRING_COMMA_LEN ("lt_oq") },
17041   { STRING_COMMA_LEN ("le_oq") },
17042   { STRING_COMMA_LEN ("unord_s") },
17043   { STRING_COMMA_LEN ("neq_us") },
17044   { STRING_COMMA_LEN ("nlt_uq") },
17045   { STRING_COMMA_LEN ("nle_uq") },
17046   { STRING_COMMA_LEN ("ord_s") },
17047   { STRING_COMMA_LEN ("eq_us") },
17048   { STRING_COMMA_LEN ("nge_uq") },
17049   { STRING_COMMA_LEN ("ngt_uq") },
17050   { STRING_COMMA_LEN ("false_os") },
17051   { STRING_COMMA_LEN ("neq_os") },
17052   { STRING_COMMA_LEN ("ge_oq") },
17053   { STRING_COMMA_LEN ("gt_oq") },
17054   { STRING_COMMA_LEN ("true_us") },
17055 };
17056
17057 static void
17058 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17059 {
17060   unsigned int cmp_type;
17061
17062   FETCH_DATA (the_info, codep + 1);
17063   cmp_type = *codep++ & 0xff;
17064   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17065     {
17066       char suffix [3];
17067       char *p = mnemonicendp - 2;
17068       suffix[0] = p[0];
17069       suffix[1] = p[1];
17070       suffix[2] = '\0';
17071       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17072       mnemonicendp += vex_cmp_op[cmp_type].len;
17073     }
17074   else
17075     {
17076       /* We have a reserved extension byte.  Output it directly.  */
17077       scratchbuf[0] = '$';
17078       print_operand_value (scratchbuf + 1, 1, cmp_type);
17079       oappend_maybe_intel (scratchbuf);
17080       scratchbuf[0] = '\0';
17081     }
17082 }
17083
17084 static void
17085 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17086              int sizeflag ATTRIBUTE_UNUSED)
17087 {
17088   unsigned int cmp_type;
17089
17090   if (!vex.evex)
17091     abort ();
17092
17093   FETCH_DATA (the_info, codep + 1);
17094   cmp_type = *codep++ & 0xff;
17095   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17096      If it's the case, print suffix, otherwise - print the immediate.  */
17097   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17098       && cmp_type != 3
17099       && cmp_type != 7)
17100     {
17101       char suffix [3];
17102       char *p = mnemonicendp - 2;
17103
17104       /* vpcmp* can have both one- and two-lettered suffix.  */
17105       if (p[0] == 'p')
17106         {
17107           p++;
17108           suffix[0] = p[0];
17109           suffix[1] = '\0';
17110         }
17111       else
17112         {
17113           suffix[0] = p[0];
17114           suffix[1] = p[1];
17115           suffix[2] = '\0';
17116         }
17117
17118       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17119       mnemonicendp += simd_cmp_op[cmp_type].len;
17120     }
17121   else
17122     {
17123       /* We have a reserved extension byte.  Output it directly.  */
17124       scratchbuf[0] = '$';
17125       print_operand_value (scratchbuf + 1, 1, cmp_type);
17126       oappend_maybe_intel (scratchbuf);
17127       scratchbuf[0] = '\0';
17128     }
17129 }
17130
17131 static const struct op pclmul_op[] =
17132 {
17133   { STRING_COMMA_LEN ("lql") },
17134   { STRING_COMMA_LEN ("hql") },
17135   { STRING_COMMA_LEN ("lqh") },
17136   { STRING_COMMA_LEN ("hqh") }
17137 };
17138
17139 static void
17140 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17141               int sizeflag ATTRIBUTE_UNUSED)
17142 {
17143   unsigned int pclmul_type;
17144
17145   FETCH_DATA (the_info, codep + 1);
17146   pclmul_type = *codep++ & 0xff;
17147   switch (pclmul_type)
17148     {
17149     case 0x10:
17150       pclmul_type = 2;
17151       break;
17152     case 0x11:
17153       pclmul_type = 3;
17154       break;
17155     default:
17156       break;
17157     }
17158   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17159     {
17160       char suffix [4];
17161       char *p = mnemonicendp - 3;
17162       suffix[0] = p[0];
17163       suffix[1] = p[1];
17164       suffix[2] = p[2];
17165       suffix[3] = '\0';
17166       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17167       mnemonicendp += pclmul_op[pclmul_type].len;
17168     }
17169   else
17170     {
17171       /* We have a reserved extension byte.  Output it directly.  */
17172       scratchbuf[0] = '$';
17173       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17174       oappend_maybe_intel (scratchbuf);
17175       scratchbuf[0] = '\0';
17176     }
17177 }
17178
17179 static void
17180 MOVBE_Fixup (int bytemode, int sizeflag)
17181 {
17182   /* Add proper suffix to "movbe".  */
17183   char *p = mnemonicendp;
17184
17185   switch (bytemode)
17186     {
17187     case v_mode:
17188       if (intel_syntax)
17189         goto skip;
17190
17191       USED_REX (REX_W);
17192       if (sizeflag & SUFFIX_ALWAYS)
17193         {
17194           if (rex & REX_W)
17195             *p++ = 'q';
17196           else
17197             {
17198               if (sizeflag & DFLAG)
17199                 *p++ = 'l';
17200               else
17201                 *p++ = 'w';
17202               used_prefixes |= (prefixes & PREFIX_DATA);
17203             }
17204         }
17205       break;
17206     default:
17207       oappend (INTERNAL_DISASSEMBLER_ERROR);
17208       break;
17209     }
17210   mnemonicendp = p;
17211   *p = '\0';
17212
17213 skip:
17214   OP_M (bytemode, sizeflag);
17215 }
17216
17217 static void
17218 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17219 {
17220   int reg;
17221   const char **names;
17222
17223   /* Skip mod/rm byte.  */
17224   MODRM_CHECK;
17225   codep++;
17226
17227   if (vex.w)
17228     names = names64;
17229   else
17230     names = names32;
17231
17232   reg = modrm.rm;
17233   USED_REX (REX_B);
17234   if (rex & REX_B)
17235     reg += 8;
17236
17237   oappend (names[reg]);
17238 }
17239
17240 static void
17241 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17242 {
17243   const char **names;
17244
17245   if (vex.w)
17246     names = names64;
17247   else
17248     names = names32;
17249
17250   oappend (names[vex.register_specifier]);
17251 }
17252
17253 static void
17254 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17255 {
17256   if (!vex.evex
17257       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17258     abort ();
17259
17260   USED_REX (REX_R);
17261   if ((rex & REX_R) != 0 || !vex.r)
17262     {
17263       BadOp ();
17264       return;
17265     }
17266
17267   oappend (names_mask [modrm.reg]);
17268 }
17269
17270 static void
17271 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17272 {
17273   if (!vex.evex
17274       || (bytemode != evex_rounding_mode
17275           && bytemode != evex_sae_mode))
17276     abort ();
17277   if (modrm.mod == 3 && vex.b)
17278     switch (bytemode)
17279       {
17280       case evex_rounding_mode:
17281         oappend (names_rounding[vex.ll]);
17282         break;
17283       case evex_sae_mode:
17284         oappend ("{sae}");
17285         break;
17286       default:
17287         break;
17288       }
17289 }