opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2021 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_VexR (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_Rounding (int, int);
  93 static void OP_REG_VexI4 (int, int);
  94 static void OP_VexI4 (int, int);
  95 static void PCLMUL_Fixup (int, int);
  96 static void VPCMP_Fixup (int, int);
  97 static void VPCOM_Fixup (int, int);
  98 static void OP_0f07 (int, int);
  99 static void OP_Monitor (int, int);
 100 static void OP_Mwait (int, int);
 101 static void NOP_Fixup1 (int, int);
 102 static void NOP_Fixup2 (int, int);
 103 static void OP_3DNowSuffix (int, int);
 104 static void CMP_Fixup (int, int);
 105 static void BadOp (void);
 106 static void REP_Fixup (int, int);
 107 static void SEP_Fixup (int, int);
 108 static void BND_Fixup (int, int);
 109 static void NOTRACK_Fixup (int, int);
 110 static void HLE_Fixup1 (int, int);
 111 static void HLE_Fixup2 (int, int);
 112 static void HLE_Fixup3 (int, int);
 113 static void CMPXCHG8B_Fixup (int, int);
 114 static void XMM_Fixup (int, int);
 115 static void FXSAVE_Fixup (int, int);
 116
 117 static void MOVSXD_Fixup (int, int);
 118
 119 static void OP_Mask (int, int);
 120
 121 struct dis_private {
 122   /* Points to first byte not fetched.  */
 123   bfd_byte *max_fetched;
 124   bfd_byte the_buffer[MAX_MNEM_SIZE];
 125   bfd_vma insn_start;
 126   int orig_sizeflag;
 127   OPCODES_SIGJMP_BUF bailout;
 128 };
 129
 130 enum address_mode
 131 {
 132   mode_16bit,
 133   mode_32bit,
 134   mode_64bit
 135 };
 136
 137 enum address_mode address_mode;
 138
 139 /* Flags for the prefixes for the current instruction.  See below.  */
 140 static int prefixes;
 141
 142 /* REX prefix the current instruction.  See below.  */
 143 static int rex;
 144 /* Bits of REX we've already used.  */
 145 static int rex_used;
 146 /* Mark parts used in the REX prefix.  When we are testing for
 147    empty prefix (for 8bit register REX extension), just mask it
 148    out.  Otherwise test for REX bit is excuse for existence of REX
 149    only in case value is nonzero.  */
 150 #define USED_REX(value)                                 \
 151   {                                                     \
 152     if (value)                                          \
 153       {                                                 \
 154         if ((rex & value))                              \
 155           rex_used |= (value) | REX_OPCODE;             \
 156       }                                                 \
 157     else                                                \
 158       rex_used |= REX_OPCODE;                           \
 159   }
 160
 161 /* Flags for prefixes which we somehow handled when printing the
 162    current instruction.  */
 163 static int used_prefixes;
 164
 165 /* Flags stored in PREFIXES.  */
 166 #define PREFIX_REPZ 1
 167 #define PREFIX_REPNZ 2
 168 #define PREFIX_LOCK 4
 169 #define PREFIX_CS 8
 170 #define PREFIX_SS 0x10
 171 #define PREFIX_DS 0x20
 172 #define PREFIX_ES 0x40
 173 #define PREFIX_FS 0x80
 174 #define PREFIX_GS 0x100
 175 #define PREFIX_DATA 0x200
 176 #define PREFIX_ADDR 0x400
 177 #define PREFIX_FWAIT 0x800
 178
 179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 180    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 181    on error.  */
 182 #define FETCH_DATA(info, addr) \
 183   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 184    ? 1 : fetch_data ((info), (addr)))
 185
 186 static int
 187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 188 {
 189   int status;
 190   struct dis_private *priv = (struct dis_private *) info->private_data;
 191   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 192
 193   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 194     status = (*info->read_memory_func) (start,
 195                                         priv->max_fetched,
 196                                         addr - priv->max_fetched,
 197                                         info);
 198   else
 199     status = -1;
 200   if (status != 0)
 201     {
 202       /* If we did manage to read at least one byte, then
 203          print_insn_i386 will do something sensible.  Otherwise, print
 204          an error.  We do that here because this is where we know
 205          STATUS.  */
 206       if (priv->max_fetched == priv->the_buffer)
 207         (*info->memory_error_func) (status, start, info);
 208       OPCODES_SIGLONGJMP (priv->bailout, 1);
 209     }
 210   else
 211     priv->max_fetched = addr;
 212   return 1;
 213 }
 214
 215 /* Possible values for prefix requirement.  */
 216 #define PREFIX_IGNORED_SHIFT    16
 217 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 218 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 219 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 220 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 221 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 222
 223 /* Opcode prefixes.  */
 224 #define PREFIX_OPCODE           (PREFIX_REPZ \
 225                                  | PREFIX_REPNZ \
 226                                  | PREFIX_DATA)
 227
 228 /* Prefixes ignored.  */
 229 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 230                                  | PREFIX_IGNORED_REPNZ \
 231                                  | PREFIX_IGNORED_DATA)
 232
 233 #define XX { NULL, 0 }
 234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 235
 236 #define Eb { OP_E, b_mode }
 237 #define Ebnd { OP_E, bnd_mode }
 238 #define EbS { OP_E, b_swap_mode }
 239 #define EbndS { OP_E, bnd_swap_mode }
 240 #define Ev { OP_E, v_mode }
 241 #define Eva { OP_E, va_mode }
 242 #define Ev_bnd { OP_E, v_bnd_mode }
 243 #define EvS { OP_E, v_swap_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edb { OP_E, db_mode }
 249 #define Edw { OP_E, dw_mode }
 250 #define Edqd { OP_E, dqd_mode }
 251 #define Eq { OP_E, q_mode }
 252 #define indirEv { OP_indirE, indir_v_mode }
 253 #define indirEp { OP_indirE, f_mode }
 254 #define stackEv { OP_E, stack_v_mode }
 255 #define Em { OP_E, m_mode }
 256 #define Ew { OP_E, w_mode }
 257 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 258 #define Ma { OP_M, a_mode }
 259 #define Mb { OP_M, b_mode }
 260 #define Md { OP_M, d_mode }
 261 #define Mo { OP_M, o_mode }
 262 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 263 #define Mq { OP_M, q_mode }
 264 #define Mv { OP_M, v_mode }
 265 #define Mv_bnd { OP_M, v_bndmk_mode }
 266 #define Mx { OP_M, x_mode }
 267 #define Mxmm { OP_M, xmm_mode }
 268 #define Gb { OP_G, b_mode }
 269 #define Gbnd { OP_G, bnd_mode }
 270 #define Gv { OP_G, v_mode }
 271 #define Gd { OP_G, d_mode }
 272 #define Gdq { OP_G, dq_mode }
 273 #define Gm { OP_G, m_mode }
 274 #define Gva { OP_G, va_mode }
 275 #define Gw { OP_G, w_mode }
 276 #define Ib { OP_I, b_mode }
 277 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 279 #define Iv { OP_I, v_mode }
 280 #define sIv { OP_sI, v_mode }
 281 #define Iv64 { OP_I64, v_mode }
 282 #define Id { OP_I, d_mode }
 283 #define Iw { OP_I, w_mode }
 284 #define I1 { OP_I, const_1_mode }
 285 #define Jb { OP_J, b_mode }
 286 #define Jv { OP_J, v_mode }
 287 #define Jdqw { OP_J, dqw_mode }
 288 #define Cm { OP_C, m_mode }
 289 #define Dm { OP_D, m_mode }
 290 #define Td { OP_T, d_mode }
 291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 292
 293 #define RMeAX { OP_REG, eAX_reg }
 294 #define RMeBX { OP_REG, eBX_reg }
 295 #define RMeCX { OP_REG, eCX_reg }
 296 #define RMeDX { OP_REG, eDX_reg }
 297 #define RMeSP { OP_REG, eSP_reg }
 298 #define RMeBP { OP_REG, eBP_reg }
 299 #define RMeSI { OP_REG, eSI_reg }
 300 #define RMeDI { OP_REG, eDI_reg }
 301 #define RMrAX { OP_REG, rAX_reg }
 302 #define RMrBX { OP_REG, rBX_reg }
 303 #define RMrCX { OP_REG, rCX_reg }
 304 #define RMrDX { OP_REG, rDX_reg }
 305 #define RMrSP { OP_REG, rSP_reg }
 306 #define RMrBP { OP_REG, rBP_reg }
 307 #define RMrSI { OP_REG, rSI_reg }
 308 #define RMrDI { OP_REG, rDI_reg }
 309 #define RMAL { OP_REG, al_reg }
 310 #define RMCL { OP_REG, cl_reg }
 311 #define RMDL { OP_REG, dl_reg }
 312 #define RMBL { OP_REG, bl_reg }
 313 #define RMAH { OP_REG, ah_reg }
 314 #define RMCH { OP_REG, ch_reg }
 315 #define RMDH { OP_REG, dh_reg }
 316 #define RMBH { OP_REG, bh_reg }
 317 #define RMAX { OP_REG, ax_reg }
 318 #define RMDX { OP_REG, dx_reg }
 319
 320 #define eAX { OP_IMREG, eAX_reg }
 321 #define AL { OP_IMREG, al_reg }
 322 #define CL { OP_IMREG, cl_reg }
 323 #define zAX { OP_IMREG, z_mode_ax_reg }
 324 #define indirDX { OP_IMREG, indir_dx_reg }
 325
 326 #define Sw { OP_SEG, w_mode }
 327 #define Sv { OP_SEG, v_mode }
 328 #define Ap { OP_DIR, 0 }
 329 #define Ob { OP_OFF64, b_mode }
 330 #define Ov { OP_OFF64, v_mode }
 331 #define Xb { OP_DSreg, eSI_reg }
 332 #define Xv { OP_DSreg, eSI_reg }
 333 #define Xz { OP_DSreg, eSI_reg }
 334 #define Yb { OP_ESreg, eDI_reg }
 335 #define Yv { OP_ESreg, eDI_reg }
 336 #define DSBX { OP_DSreg, eBX_reg }
 337
 338 #define es { OP_REG, es_reg }
 339 #define ss { OP_REG, ss_reg }
 340 #define cs { OP_REG, cs_reg }
 341 #define ds { OP_REG, ds_reg }
 342 #define fs { OP_REG, fs_reg }
 343 #define gs { OP_REG, gs_reg }
 344
 345 #define MX { OP_MMX, 0 }
 346 #define XM { OP_XMM, 0 }
 347 #define XMScalar { OP_XMM, scalar_mode }
 348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 349 #define XMM { OP_XMM, xmm_mode }
 350 #define TMM { OP_XMM, tmm_mode }
 351 #define XMxmmq { OP_XMM, xmmq_mode }
 352 #define EM { OP_EM, v_mode }
 353 #define EMS { OP_EM, v_swap_mode }
 354 #define EMd { OP_EM, d_mode }
 355 #define EMx { OP_EM, x_mode }
 356 #define EXbwUnit { OP_EX, bw_unit_mode }
 357 #define EXw { OP_EX, w_mode }
 358 #define EXd { OP_EX, d_mode }
 359 #define EXdS { OP_EX, d_swap_mode }
 360 #define EXq { OP_EX, q_mode }
 361 #define EXqS { OP_EX, q_swap_mode }
 362 #define EXx { OP_EX, x_mode }
 363 #define EXxS { OP_EX, x_swap_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXymm { OP_EX, ymm_mode }
 366 #define EXtmm { OP_EX, tmm_mode }
 367 #define EXxmmq { OP_EX, xmmq_mode }
 368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 371 #define EXxmm_md { OP_EX, xmm_md_mode }
 372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 373 #define EXxmmdw { OP_EX, xmmdw_mode }
 374 #define EXxmmqd { OP_EX, xmmqd_mode }
 375 #define EXymmq { OP_EX, ymmq_mode }
 376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 379 #define MS { OP_MS, v_mode }
 380 #define XS { OP_XS, v_mode }
 381 #define EMCq { OP_EMC, q_mode }
 382 #define MXC { OP_MXC, 0 }
 383 #define OPSUF { OP_3DNowSuffix, 0 }
 384 #define SEP { SEP_Fixup, 0 }
 385 #define CMP { CMP_Fixup, 0 }
 386 #define XMM0 { XMM_Fixup, 0 }
 387 #define FXSAVE { FXSAVE_Fixup, 0 }
 388
 389 #define Vex { OP_VEX, vex_mode }
 390 #define VexW { OP_VexW, vex_mode }
 391 #define VexScalar { OP_VEX, vex_scalar_mode }
 392 #define VexScalarR { OP_VexR, vex_scalar_mode }
 393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 394 #define VexGdq { OP_VEX, dq_mode }
 395 #define VexTmm { OP_VEX, tmm_mode }
 396 #define XMVexI4 { OP_REG_VexI4, x_mode }
 397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 398 #define VexI4 { OP_VexI4, 0 }
 399 #define PCLMUL { PCLMUL_Fixup, 0 }
 400 #define VPCMP { VPCMP_Fixup, 0 }
 401 #define VPCOM { VPCOM_Fixup, 0 }
 402
 403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 406
 407 #define XMask { OP_Mask, mask_mode }
 408 #define MaskG { OP_G, mask_mode }
 409 #define MaskE { OP_E, mask_mode }
 410 #define MaskBDE { OP_E, mask_bd_mode }
 411 #define MaskVex { OP_VEX, mask_mode }
 412
 413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 417
 418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 419
 420 /* Used handle "rep" prefix for string instructions.  */
 421 #define Xbr { REP_Fixup, eSI_reg }
 422 #define Xvr { REP_Fixup, eSI_reg }
 423 #define Ybr { REP_Fixup, eDI_reg }
 424 #define Yvr { REP_Fixup, eDI_reg }
 425 #define Yzr { REP_Fixup, eDI_reg }
 426 #define indirDXr { REP_Fixup, indir_dx_reg }
 427 #define ALr { REP_Fixup, al_reg }
 428 #define eAXr { REP_Fixup, eAX_reg }
 429
 430 /* Used handle HLE prefix for lockable instructions.  */
 431 #define Ebh1 { HLE_Fixup1, b_mode }
 432 #define Evh1 { HLE_Fixup1, v_mode }
 433 #define Ebh2 { HLE_Fixup2, b_mode }
 434 #define Evh2 { HLE_Fixup2, v_mode }
 435 #define Ebh3 { HLE_Fixup3, b_mode }
 436 #define Evh3 { HLE_Fixup3, v_mode }
 437
 438 #define BND { BND_Fixup, 0 }
 439 #define NOTRACK { NOTRACK_Fixup, 0 }
 440
 441 #define cond_jump_flag { NULL, cond_jump_mode }
 442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 443
 444 /* bits in sizeflag */
 445 #define SUFFIX_ALWAYS 4
 446 #define AFLAG 2
 447 #define DFLAG 1
 448
 449 enum
 450 {
 451   /* byte operand */
 452   b_mode = 1,
 453   /* byte operand with operand swapped */
 454   b_swap_mode,
 455   /* byte operand, sign extend like 'T' suffix */
 456   b_T_mode,
 457   /* operand size depends on prefixes */
 458   v_mode,
 459   /* operand size depends on prefixes with operand swapped */
 460   v_swap_mode,
 461   /* operand size depends on address prefix */
 462   va_mode,
 463   /* word operand */
 464   w_mode,
 465   /* double word operand  */
 466   d_mode,
 467   /* double word operand with operand swapped */
 468   d_swap_mode,
 469   /* quad word operand */
 470   q_mode,
 471   /* quad word operand with operand swapped */
 472   q_swap_mode,
 473   /* ten-byte operand */
 474   t_mode,
 475   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 476      broadcast enabled.  */
 477   x_mode,
 478   /* Similar to x_mode, but with different EVEX mem shifts.  */
 479   evex_x_gscat_mode,
 480   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 481   bw_unit_mode,
 482   /* Similar to x_mode, but with disabled broadcast.  */
 483   evex_x_nobcst_mode,
 484   /* Similar to x_mode, but with operands swapped and disabled broadcast
 485      in EVEX.  */
 486   x_swap_mode,
 487   /* 16-byte XMM operand */
 488   xmm_mode,
 489   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 490      memory operand (depending on vector length).  Broadcast isn't
 491      allowed.  */
 492   xmmq_mode,
 493   /* Same as xmmq_mode, but broadcast is allowed.  */
 494   evex_half_bcst_xmmq_mode,
 495   /* XMM register or byte memory operand */
 496   xmm_mb_mode,
 497   /* XMM register or word memory operand */
 498   xmm_mw_mode,
 499   /* XMM register or double word memory operand */
 500   xmm_md_mode,
 501   /* XMM register or quad word memory operand */
 502   xmm_mq_mode,
 503   /* 16-byte XMM, word, double word or quad word operand.  */
 504   xmmdw_mode,
 505   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 506   xmmqd_mode,
 507   /* 32-byte YMM operand */
 508   ymm_mode,
 509   /* quad word, ymmword or zmmword memory operand.  */
 510   ymmq_mode,
 511   /* 32-byte YMM or 16-byte word operand */
 512   ymmxmm_mode,
 513   /* TMM operand */
 514   tmm_mode,
 515   /* d_mode in 32bit, q_mode in 64bit mode.  */
 516   m_mode,
 517   /* pair of v_mode operands */
 518   a_mode,
 519   cond_jump_mode,
 520   loop_jcxz_mode,
 521   movsxd_mode,
 522   v_bnd_mode,
 523   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 524   v_bndmk_mode,
 525   /* operand size depends on REX prefixes.  */
 526   dq_mode,
 527   /* registers like dq_mode, memory like w_mode, displacements like
 528      v_mode without considering Intel64 ISA.  */
 529   dqw_mode,
 530   /* bounds operand */
 531   bnd_mode,
 532   /* bounds operand with operand swapped */
 533   bnd_swap_mode,
 534   /* 4- or 6-byte pointer operand */
 535   f_mode,
 536   const_1_mode,
 537   /* v_mode for indirect branch opcodes.  */
 538   indir_v_mode,
 539   /* v_mode for stack-related opcodes.  */
 540   stack_v_mode,
 541   /* non-quad operand size depends on prefixes */
 542   z_mode,
 543   /* 16-byte operand */
 544   o_mode,
 545   /* registers like dq_mode, memory like b_mode.  */
 546   dqb_mode,
 547   /* registers like d_mode, memory like b_mode.  */
 548   db_mode,
 549   /* registers like d_mode, memory like w_mode.  */
 550   dw_mode,
 551   /* registers like dq_mode, memory like d_mode.  */
 552   dqd_mode,
 553   /* normal vex mode */
 554   vex_mode,
 555
 556   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 557   vex_vsib_d_w_dq_mode,
 558   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 559   vex_vsib_d_w_d_mode,
 560   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 561   vex_vsib_q_w_dq_mode,
 562   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 563   vex_vsib_q_w_d_mode,
 564   /* mandatory non-vector SIB.  */
 565   vex_sibmem_mode,
 566
 567   /* scalar, ignore vector length.  */
 568   scalar_mode,
 569   /* like vex_mode, ignore vector length.  */
 570   vex_scalar_mode,
 571   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 572   vex_scalar_w_dq_mode,
 573
 574   /* Static rounding.  */
 575   evex_rounding_mode,
 576   /* Static rounding, 64-bit mode only.  */
 577   evex_rounding_64_mode,
 578   /* Supress all exceptions.  */
 579   evex_sae_mode,
 580
 581   /* Mask register operand.  */
 582   mask_mode,
 583   /* Mask register operand.  */
 584   mask_bd_mode,
 585
 586   es_reg,
 587   cs_reg,
 588   ss_reg,
 589   ds_reg,
 590   fs_reg,
 591   gs_reg,
 592
 593   eAX_reg,
 594   eCX_reg,
 595   eDX_reg,
 596   eBX_reg,
 597   eSP_reg,
 598   eBP_reg,
 599   eSI_reg,
 600   eDI_reg,
 601
 602   al_reg,
 603   cl_reg,
 604   dl_reg,
 605   bl_reg,
 606   ah_reg,
 607   ch_reg,
 608   dh_reg,
 609   bh_reg,
 610
 611   ax_reg,
 612   cx_reg,
 613   dx_reg,
 614   bx_reg,
 615   sp_reg,
 616   bp_reg,
 617   si_reg,
 618   di_reg,
 619
 620   rAX_reg,
 621   rCX_reg,
 622   rDX_reg,
 623   rBX_reg,
 624   rSP_reg,
 625   rBP_reg,
 626   rSI_reg,
 627   rDI_reg,
 628
 629   z_mode_ax_reg,
 630   indir_dx_reg
 631 };
 632
 633 enum
 634 {
 635   FLOATCODE = 1,
 636   USE_REG_TABLE,
 637   USE_MOD_TABLE,
 638   USE_RM_TABLE,
 639   USE_PREFIX_TABLE,
 640   USE_X86_64_TABLE,
 641   USE_3BYTE_TABLE,
 642   USE_XOP_8F_TABLE,
 643   USE_VEX_C4_TABLE,
 644   USE_VEX_C5_TABLE,
 645   USE_VEX_LEN_TABLE,
 646   USE_VEX_W_TABLE,
 647   USE_EVEX_TABLE,
 648   USE_EVEX_LEN_TABLE
 649 };
 650
 651 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 652
 653 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 654 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 655 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 656 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 657 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 658 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 659 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 660 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 661 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 662 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 663 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 664 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 665 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 666 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 667 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 668 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 669
 670 enum
 671 {
 672   REG_80 = 0,
 673   REG_81,
 674   REG_83,
 675   REG_8F,
 676   REG_C0,
 677   REG_C1,
 678   REG_C6,
 679   REG_C7,
 680   REG_D0,
 681   REG_D1,
 682   REG_D2,
 683   REG_D3,
 684   REG_F6,
 685   REG_F7,
 686   REG_FE,
 687   REG_FF,
 688   REG_0F00,
 689   REG_0F01,
 690   REG_0F0D,
 691   REG_0F18,
 692   REG_0F1C_P_0_MOD_0,
 693   REG_0F1E_P_1_MOD_3,
 694   REG_0F38D8_PREFIX_1,
 695   REG_0F3A0F_PREFIX_1_MOD_3,
 696   REG_0F71_MOD_0,
 697   REG_0F72_MOD_0,
 698   REG_0F73_MOD_0,
 699   REG_0FA6,
 700   REG_0FA7,
 701   REG_0FAE,
 702   REG_0FBA,
 703   REG_0FC7,
 704   REG_VEX_0F71_M_0,
 705   REG_VEX_0F72_M_0,
 706   REG_VEX_0F73_M_0,
 707   REG_VEX_0FAE,
 708   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 709   REG_VEX_0F38F3_L_0,
 710
 711   REG_0FXOP_09_01_L_0,
 712   REG_0FXOP_09_02_L_0,
 713   REG_0FXOP_09_12_M_1_L_0,
 714   REG_0FXOP_0A_12_L_0,
 715
 716   REG_EVEX_0F71,
 717   REG_EVEX_0F72,
 718   REG_EVEX_0F73,
 719   REG_EVEX_0F38C6_M_0_L_2,
 720   REG_EVEX_0F38C7_M_0_L_2_W_0,
 721   REG_EVEX_0F38C7_M_0_L_2_W_1
 722 };
 723
 724 enum
 725 {
 726   MOD_8D = 0,
 727   MOD_C6_REG_7,
 728   MOD_C7_REG_7,
 729   MOD_FF_REG_3,
 730   MOD_FF_REG_5,
 731   MOD_0F01_REG_0,
 732   MOD_0F01_REG_1,
 733   MOD_0F01_REG_2,
 734   MOD_0F01_REG_3,
 735   MOD_0F01_REG_5,
 736   MOD_0F01_REG_7,
 737   MOD_0F12_PREFIX_0,
 738   MOD_0F12_PREFIX_2,
 739   MOD_0F13,
 740   MOD_0F16_PREFIX_0,
 741   MOD_0F16_PREFIX_2,
 742   MOD_0F17,
 743   MOD_0F18_REG_0,
 744   MOD_0F18_REG_1,
 745   MOD_0F18_REG_2,
 746   MOD_0F18_REG_3,
 747   MOD_0F1A_PREFIX_0,
 748   MOD_0F1B_PREFIX_0,
 749   MOD_0F1B_PREFIX_1,
 750   MOD_0F1C_PREFIX_0,
 751   MOD_0F1E_PREFIX_1,
 752   MOD_0F2B_PREFIX_0,
 753   MOD_0F2B_PREFIX_1,
 754   MOD_0F2B_PREFIX_2,
 755   MOD_0F2B_PREFIX_3,
 756   MOD_0F50,
 757   MOD_0F71,
 758   MOD_0F72,
 759   MOD_0F73,
 760   MOD_0FAE_REG_0,
 761   MOD_0FAE_REG_1,
 762   MOD_0FAE_REG_2,
 763   MOD_0FAE_REG_3,
 764   MOD_0FAE_REG_4,
 765   MOD_0FAE_REG_5,
 766   MOD_0FAE_REG_6,
 767   MOD_0FAE_REG_7,
 768   MOD_0FB2,
 769   MOD_0FB4,
 770   MOD_0FB5,
 771   MOD_0FC3,
 772   MOD_0FC7_REG_3,
 773   MOD_0FC7_REG_4,
 774   MOD_0FC7_REG_5,
 775   MOD_0FC7_REG_6,
 776   MOD_0FC7_REG_7,
 777   MOD_0FD7,
 778   MOD_0FE7_PREFIX_2,
 779   MOD_0FF0_PREFIX_3,
 780   MOD_0F382A,
 781   MOD_0F38DC_PREFIX_1,
 782   MOD_0F38DD_PREFIX_1,
 783   MOD_0F38DE_PREFIX_1,
 784   MOD_0F38DF_PREFIX_1,
 785   MOD_0F38F5,
 786   MOD_0F38F6_PREFIX_0,
 787   MOD_0F38F8_PREFIX_1,
 788   MOD_0F38F8_PREFIX_2,
 789   MOD_0F38F8_PREFIX_3,
 790   MOD_0F38F9,
 791   MOD_0F38FA_PREFIX_1,
 792   MOD_0F38FB_PREFIX_1,
 793   MOD_0F3A0F_PREFIX_1,
 794   MOD_62_32BIT,
 795   MOD_C4_32BIT,
 796   MOD_C5_32BIT,
 797   MOD_VEX_0F12_PREFIX_0,
 798   MOD_VEX_0F12_PREFIX_2,
 799   MOD_VEX_0F13,
 800   MOD_VEX_0F16_PREFIX_0,
 801   MOD_VEX_0F16_PREFIX_2,
 802   MOD_VEX_0F17,
 803   MOD_VEX_0F2B,
 804   MOD_VEX_0F41_L_1,
 805   MOD_VEX_0F42_L_1,
 806   MOD_VEX_0F44_L_0,
 807   MOD_VEX_0F45_L_1,
 808   MOD_VEX_0F46_L_1,
 809   MOD_VEX_0F47_L_1,
 810   MOD_VEX_0F4A_L_1,
 811   MOD_VEX_0F4B_L_1,
 812   MOD_VEX_0F50,
 813   MOD_VEX_0F71,
 814   MOD_VEX_0F72,
 815   MOD_VEX_0F73,
 816   MOD_VEX_0F91_L_0,
 817   MOD_VEX_0F92_L_0,
 818   MOD_VEX_0F93_L_0,
 819   MOD_VEX_0F98_L_0,
 820   MOD_VEX_0F99_L_0,
 821   MOD_VEX_0FAE_REG_2,
 822   MOD_VEX_0FAE_REG_3,
 823   MOD_VEX_0FD7,
 824   MOD_VEX_0FE7,
 825   MOD_VEX_0FF0_PREFIX_3,
 826   MOD_VEX_0F381A,
 827   MOD_VEX_0F382A,
 828   MOD_VEX_0F382C,
 829   MOD_VEX_0F382D,
 830   MOD_VEX_0F382E,
 831   MOD_VEX_0F382F,
 832   MOD_VEX_0F3849_X86_64_P_0_W_0,
 833   MOD_VEX_0F3849_X86_64_P_2_W_0,
 834   MOD_VEX_0F3849_X86_64_P_3_W_0,
 835   MOD_VEX_0F384B_X86_64_P_1_W_0,
 836   MOD_VEX_0F384B_X86_64_P_2_W_0,
 837   MOD_VEX_0F384B_X86_64_P_3_W_0,
 838   MOD_VEX_0F385A,
 839   MOD_VEX_0F385C_X86_64_P_1_W_0,
 840   MOD_VEX_0F385E_X86_64_P_0_W_0,
 841   MOD_VEX_0F385E_X86_64_P_1_W_0,
 842   MOD_VEX_0F385E_X86_64_P_2_W_0,
 843   MOD_VEX_0F385E_X86_64_P_3_W_0,
 844   MOD_VEX_0F388C,
 845   MOD_VEX_0F388E,
 846   MOD_VEX_0F3A30_L_0,
 847   MOD_VEX_0F3A31_L_0,
 848   MOD_VEX_0F3A32_L_0,
 849   MOD_VEX_0F3A33_L_0,
 850
 851   MOD_VEX_0FXOP_09_12,
 852
 853   MOD_EVEX_0F12_PREFIX_0,
 854   MOD_EVEX_0F12_PREFIX_2,
 855   MOD_EVEX_0F13,
 856   MOD_EVEX_0F16_PREFIX_0,
 857   MOD_EVEX_0F16_PREFIX_2,
 858   MOD_EVEX_0F17,
 859   MOD_EVEX_0F2B,
 860   MOD_EVEX_0F381A,
 861   MOD_EVEX_0F381B,
 862   MOD_EVEX_0F3828_P_1,
 863   MOD_EVEX_0F382A_P_1_W_1,
 864   MOD_EVEX_0F3838_P_1,
 865   MOD_EVEX_0F383A_P_1_W_0,
 866   MOD_EVEX_0F385A,
 867   MOD_EVEX_0F385B,
 868   MOD_EVEX_0F387A_W_0,
 869   MOD_EVEX_0F387B_W_0,
 870   MOD_EVEX_0F387C,
 871   MOD_EVEX_0F38C6,
 872   MOD_EVEX_0F38C7
 873 };
 874
 875 enum
 876 {
 877   RM_C6_REG_7 = 0,
 878   RM_C7_REG_7,
 879   RM_0F01_REG_0,
 880   RM_0F01_REG_1,
 881   RM_0F01_REG_2,
 882   RM_0F01_REG_3,
 883   RM_0F01_REG_5_MOD_3,
 884   RM_0F01_REG_7_MOD_3,
 885   RM_0F1E_P_1_MOD_3_REG_7,
 886   RM_0F3A0F_P_1_MOD_3_REG_0,
 887   RM_0FAE_REG_6_MOD_3_P_0,
 888   RM_0FAE_REG_7_MOD_3,
 889   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 890 };
 891
 892 enum
 893 {
 894   PREFIX_90 = 0,
 895   PREFIX_0F01_REG_1_RM_4,
 896   PREFIX_0F01_REG_1_RM_5,
 897   PREFIX_0F01_REG_1_RM_6,
 898   PREFIX_0F01_REG_1_RM_7,
 899   PREFIX_0F01_REG_3_RM_1,
 900   PREFIX_0F01_REG_5_MOD_0,
 901   PREFIX_0F01_REG_5_MOD_3_RM_0,
 902   PREFIX_0F01_REG_5_MOD_3_RM_1,
 903   PREFIX_0F01_REG_5_MOD_3_RM_2,
 904   PREFIX_0F01_REG_5_MOD_3_RM_4,
 905   PREFIX_0F01_REG_5_MOD_3_RM_5,
 906   PREFIX_0F01_REG_5_MOD_3_RM_6,
 907   PREFIX_0F01_REG_5_MOD_3_RM_7,
 908   PREFIX_0F01_REG_7_MOD_3_RM_2,
 909   PREFIX_0F01_REG_7_MOD_3_RM_6,
 910   PREFIX_0F01_REG_7_MOD_3_RM_7,
 911   PREFIX_0F09,
 912   PREFIX_0F10,
 913   PREFIX_0F11,
 914   PREFIX_0F12,
 915   PREFIX_0F16,
 916   PREFIX_0F1A,
 917   PREFIX_0F1B,
 918   PREFIX_0F1C,
 919   PREFIX_0F1E,
 920   PREFIX_0F2A,
 921   PREFIX_0F2B,
 922   PREFIX_0F2C,
 923   PREFIX_0F2D,
 924   PREFIX_0F2E,
 925   PREFIX_0F2F,
 926   PREFIX_0F51,
 927   PREFIX_0F52,
 928   PREFIX_0F53,
 929   PREFIX_0F58,
 930   PREFIX_0F59,
 931   PREFIX_0F5A,
 932   PREFIX_0F5B,
 933   PREFIX_0F5C,
 934   PREFIX_0F5D,
 935   PREFIX_0F5E,
 936   PREFIX_0F5F,
 937   PREFIX_0F60,
 938   PREFIX_0F61,
 939   PREFIX_0F62,
 940   PREFIX_0F6F,
 941   PREFIX_0F70,
 942   PREFIX_0F78,
 943   PREFIX_0F79,
 944   PREFIX_0F7C,
 945   PREFIX_0F7D,
 946   PREFIX_0F7E,
 947   PREFIX_0F7F,
 948   PREFIX_0FAE_REG_0_MOD_3,
 949   PREFIX_0FAE_REG_1_MOD_3,
 950   PREFIX_0FAE_REG_2_MOD_3,
 951   PREFIX_0FAE_REG_3_MOD_3,
 952   PREFIX_0FAE_REG_4_MOD_0,
 953   PREFIX_0FAE_REG_4_MOD_3,
 954   PREFIX_0FAE_REG_5_MOD_3,
 955   PREFIX_0FAE_REG_6_MOD_0,
 956   PREFIX_0FAE_REG_6_MOD_3,
 957   PREFIX_0FAE_REG_7_MOD_0,
 958   PREFIX_0FB8,
 959   PREFIX_0FBC,
 960   PREFIX_0FBD,
 961   PREFIX_0FC2,
 962   PREFIX_0FC7_REG_6_MOD_0,
 963   PREFIX_0FC7_REG_6_MOD_3,
 964   PREFIX_0FC7_REG_7_MOD_3,
 965   PREFIX_0FD0,
 966   PREFIX_0FD6,
 967   PREFIX_0FE6,
 968   PREFIX_0FE7,
 969   PREFIX_0FF0,
 970   PREFIX_0FF7,
 971   PREFIX_0F38D8,
 972   PREFIX_0F38DC,
 973   PREFIX_0F38DD,
 974   PREFIX_0F38DE,
 975   PREFIX_0F38DF,
 976   PREFIX_0F38F0,
 977   PREFIX_0F38F1,
 978   PREFIX_0F38F6,
 979   PREFIX_0F38F8,
 980   PREFIX_0F38FA,
 981   PREFIX_0F38FB,
 982   PREFIX_0F3A0F,
 983   PREFIX_VEX_0F10,
 984   PREFIX_VEX_0F11,
 985   PREFIX_VEX_0F12,
 986   PREFIX_VEX_0F16,
 987   PREFIX_VEX_0F2A,
 988   PREFIX_VEX_0F2C,
 989   PREFIX_VEX_0F2D,
 990   PREFIX_VEX_0F2E,
 991   PREFIX_VEX_0F2F,
 992   PREFIX_VEX_0F41_L_1_M_1_W_0,
 993   PREFIX_VEX_0F41_L_1_M_1_W_1,
 994   PREFIX_VEX_0F42_L_1_M_1_W_0,
 995   PREFIX_VEX_0F42_L_1_M_1_W_1,
 996   PREFIX_VEX_0F44_L_0_M_1_W_0,
 997   PREFIX_VEX_0F44_L_0_M_1_W_1,
 998   PREFIX_VEX_0F45_L_1_M_1_W_0,
 999   PREFIX_VEX_0F45_L_1_M_1_W_1,
1000   PREFIX_VEX_0F46_L_1_M_1_W_0,
1001   PREFIX_VEX_0F46_L_1_M_1_W_1,
1002   PREFIX_VEX_0F47_L_1_M_1_W_0,
1003   PREFIX_VEX_0F47_L_1_M_1_W_1,
1004   PREFIX_VEX_0F4A_L_1_M_1_W_0,
1005   PREFIX_VEX_0F4A_L_1_M_1_W_1,
1006   PREFIX_VEX_0F4B_L_1_M_1_W_0,
1007   PREFIX_VEX_0F4B_L_1_M_1_W_1,
1008   PREFIX_VEX_0F51,
1009   PREFIX_VEX_0F52,
1010   PREFIX_VEX_0F53,
1011   PREFIX_VEX_0F58,
1012   PREFIX_VEX_0F59,
1013   PREFIX_VEX_0F5A,
1014   PREFIX_VEX_0F5B,
1015   PREFIX_VEX_0F5C,
1016   PREFIX_VEX_0F5D,
1017   PREFIX_VEX_0F5E,
1018   PREFIX_VEX_0F5F,
1019   PREFIX_VEX_0F6F,
1020   PREFIX_VEX_0F70,
1021   PREFIX_VEX_0F7C,
1022   PREFIX_VEX_0F7D,
1023   PREFIX_VEX_0F7E,
1024   PREFIX_VEX_0F7F,
1025   PREFIX_VEX_0F90_L_0_W_0,
1026   PREFIX_VEX_0F90_L_0_W_1,
1027   PREFIX_VEX_0F91_L_0_M_0_W_0,
1028   PREFIX_VEX_0F91_L_0_M_0_W_1,
1029   PREFIX_VEX_0F92_L_0_M_1_W_0,
1030   PREFIX_VEX_0F92_L_0_M_1_W_1,
1031   PREFIX_VEX_0F93_L_0_M_1_W_0,
1032   PREFIX_VEX_0F93_L_0_M_1_W_1,
1033   PREFIX_VEX_0F98_L_0_M_1_W_0,
1034   PREFIX_VEX_0F98_L_0_M_1_W_1,
1035   PREFIX_VEX_0F99_L_0_M_1_W_0,
1036   PREFIX_VEX_0F99_L_0_M_1_W_1,
1037   PREFIX_VEX_0FC2,
1038   PREFIX_VEX_0FD0,
1039   PREFIX_VEX_0FE6,
1040   PREFIX_VEX_0FF0,
1041   PREFIX_VEX_0F3849_X86_64,
1042   PREFIX_VEX_0F384B_X86_64,
1043   PREFIX_VEX_0F385C_X86_64,
1044   PREFIX_VEX_0F385E_X86_64,
1045   PREFIX_VEX_0F38F5_L_0,
1046   PREFIX_VEX_0F38F6_L_0,
1047   PREFIX_VEX_0F38F7_L_0,
1048   PREFIX_VEX_0F3AF0_L_0,
1049
1050   PREFIX_EVEX_0F10,
1051   PREFIX_EVEX_0F11,
1052   PREFIX_EVEX_0F12,
1053   PREFIX_EVEX_0F16,
1054   PREFIX_EVEX_0F2A,
1055   PREFIX_EVEX_0F51,
1056   PREFIX_EVEX_0F58,
1057   PREFIX_EVEX_0F59,
1058   PREFIX_EVEX_0F5A,
1059   PREFIX_EVEX_0F5B,
1060   PREFIX_EVEX_0F5C,
1061   PREFIX_EVEX_0F5D,
1062   PREFIX_EVEX_0F5E,
1063   PREFIX_EVEX_0F5F,
1064   PREFIX_EVEX_0F6F,
1065   PREFIX_EVEX_0F70,
1066   PREFIX_EVEX_0F78,
1067   PREFIX_EVEX_0F79,
1068   PREFIX_EVEX_0F7A,
1069   PREFIX_EVEX_0F7B,
1070   PREFIX_EVEX_0F7E,
1071   PREFIX_EVEX_0F7F,
1072   PREFIX_EVEX_0FC2,
1073   PREFIX_EVEX_0FE6,
1074   PREFIX_EVEX_0F3810,
1075   PREFIX_EVEX_0F3811,
1076   PREFIX_EVEX_0F3812,
1077   PREFIX_EVEX_0F3813,
1078   PREFIX_EVEX_0F3814,
1079   PREFIX_EVEX_0F3815,
1080   PREFIX_EVEX_0F3820,
1081   PREFIX_EVEX_0F3821,
1082   PREFIX_EVEX_0F3822,
1083   PREFIX_EVEX_0F3823,
1084   PREFIX_EVEX_0F3824,
1085   PREFIX_EVEX_0F3825,
1086   PREFIX_EVEX_0F3826,
1087   PREFIX_EVEX_0F3827,
1088   PREFIX_EVEX_0F3828,
1089   PREFIX_EVEX_0F3829,
1090   PREFIX_EVEX_0F382A,
1091   PREFIX_EVEX_0F3830,
1092   PREFIX_EVEX_0F3831,
1093   PREFIX_EVEX_0F3832,
1094   PREFIX_EVEX_0F3833,
1095   PREFIX_EVEX_0F3834,
1096   PREFIX_EVEX_0F3835,
1097   PREFIX_EVEX_0F3838,
1098   PREFIX_EVEX_0F3839,
1099   PREFIX_EVEX_0F383A,
1100   PREFIX_EVEX_0F3852,
1101   PREFIX_EVEX_0F3853,
1102   PREFIX_EVEX_0F3868,
1103   PREFIX_EVEX_0F3872,
1104   PREFIX_EVEX_0F389A,
1105   PREFIX_EVEX_0F389B,
1106   PREFIX_EVEX_0F38AA,
1107   PREFIX_EVEX_0F38AB,
1108 };
1109
1110 enum
1111 {
1112   X86_64_06 = 0,
1113   X86_64_07,
1114   X86_64_0E,
1115   X86_64_16,
1116   X86_64_17,
1117   X86_64_1E,
1118   X86_64_1F,
1119   X86_64_27,
1120   X86_64_2F,
1121   X86_64_37,
1122   X86_64_3F,
1123   X86_64_60,
1124   X86_64_61,
1125   X86_64_62,
1126   X86_64_63,
1127   X86_64_6D,
1128   X86_64_6F,
1129   X86_64_82,
1130   X86_64_9A,
1131   X86_64_C2,
1132   X86_64_C3,
1133   X86_64_C4,
1134   X86_64_C5,
1135   X86_64_CE,
1136   X86_64_D4,
1137   X86_64_D5,
1138   X86_64_E8,
1139   X86_64_E9,
1140   X86_64_EA,
1141   X86_64_0F01_REG_0,
1142   X86_64_0F01_REG_1,
1143   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1144   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1145   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1146   X86_64_0F01_REG_2,
1147   X86_64_0F01_REG_3,
1148   X86_64_0F24,
1149   X86_64_0F26,
1150   X86_64_VEX_0F3849,
1151   X86_64_VEX_0F384B,
1152   X86_64_VEX_0F385C,
1153   X86_64_VEX_0F385E,
1154   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1155   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1156   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1157   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1158   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1159   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1160   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1161   X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1162 };
1163
1164 enum
1165 {
1166   THREE_BYTE_0F38 = 0,
1167   THREE_BYTE_0F3A
1168 };
1169
1170 enum
1171 {
1172   XOP_08 = 0,
1173   XOP_09,
1174   XOP_0A
1175 };
1176
1177 enum
1178 {
1179   VEX_0F = 0,
1180   VEX_0F38,
1181   VEX_0F3A
1182 };
1183
1184 enum
1185 {
1186   EVEX_0F = 0,
1187   EVEX_0F38,
1188   EVEX_0F3A
1189 };
1190
1191 enum
1192 {
1193   VEX_LEN_0F12_P_0_M_0 = 0,
1194   VEX_LEN_0F12_P_0_M_1,
1195 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1196   VEX_LEN_0F13_M_0,
1197   VEX_LEN_0F16_P_0_M_0,
1198   VEX_LEN_0F16_P_0_M_1,
1199 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1200   VEX_LEN_0F17_M_0,
1201   VEX_LEN_0F41,
1202   VEX_LEN_0F42,
1203   VEX_LEN_0F44,
1204   VEX_LEN_0F45,
1205   VEX_LEN_0F46,
1206   VEX_LEN_0F47,
1207   VEX_LEN_0F4A,
1208   VEX_LEN_0F4B,
1209   VEX_LEN_0F6E,
1210   VEX_LEN_0F77,
1211   VEX_LEN_0F7E_P_1,
1212   VEX_LEN_0F7E_P_2,
1213   VEX_LEN_0F90,
1214   VEX_LEN_0F91,
1215   VEX_LEN_0F92,
1216   VEX_LEN_0F93,
1217   VEX_LEN_0F98,
1218   VEX_LEN_0F99,
1219   VEX_LEN_0FAE_R_2_M_0,
1220   VEX_LEN_0FAE_R_3_M_0,
1221   VEX_LEN_0FC4,
1222   VEX_LEN_0FC5,
1223   VEX_LEN_0FD6,
1224   VEX_LEN_0FF7,
1225   VEX_LEN_0F3816,
1226   VEX_LEN_0F3819,
1227   VEX_LEN_0F381A_M_0,
1228   VEX_LEN_0F3836,
1229   VEX_LEN_0F3841,
1230   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1231   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1232   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1233   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1234   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1235   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1236   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1237   VEX_LEN_0F385A_M_0,
1238   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1239   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1240   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1241   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1242   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1243   VEX_LEN_0F38DB,
1244   VEX_LEN_0F38F2,
1245   VEX_LEN_0F38F3,
1246   VEX_LEN_0F38F5,
1247   VEX_LEN_0F38F6,
1248   VEX_LEN_0F38F7,
1249   VEX_LEN_0F3A00,
1250   VEX_LEN_0F3A01,
1251   VEX_LEN_0F3A06,
1252   VEX_LEN_0F3A14,
1253   VEX_LEN_0F3A15,
1254   VEX_LEN_0F3A16,
1255   VEX_LEN_0F3A17,
1256   VEX_LEN_0F3A18,
1257   VEX_LEN_0F3A19,
1258   VEX_LEN_0F3A20,
1259   VEX_LEN_0F3A21,
1260   VEX_LEN_0F3A22,
1261   VEX_LEN_0F3A30,
1262   VEX_LEN_0F3A31,
1263   VEX_LEN_0F3A32,
1264   VEX_LEN_0F3A33,
1265   VEX_LEN_0F3A38,
1266   VEX_LEN_0F3A39,
1267   VEX_LEN_0F3A41,
1268   VEX_LEN_0F3A46,
1269   VEX_LEN_0F3A60,
1270   VEX_LEN_0F3A61,
1271   VEX_LEN_0F3A62,
1272   VEX_LEN_0F3A63,
1273   VEX_LEN_0F3ADF,
1274   VEX_LEN_0F3AF0,
1275   VEX_LEN_0FXOP_08_85,
1276   VEX_LEN_0FXOP_08_86,
1277   VEX_LEN_0FXOP_08_87,
1278   VEX_LEN_0FXOP_08_8E,
1279   VEX_LEN_0FXOP_08_8F,
1280   VEX_LEN_0FXOP_08_95,
1281   VEX_LEN_0FXOP_08_96,
1282   VEX_LEN_0FXOP_08_97,
1283   VEX_LEN_0FXOP_08_9E,
1284   VEX_LEN_0FXOP_08_9F,
1285   VEX_LEN_0FXOP_08_A3,
1286   VEX_LEN_0FXOP_08_A6,
1287   VEX_LEN_0FXOP_08_B6,
1288   VEX_LEN_0FXOP_08_C0,
1289   VEX_LEN_0FXOP_08_C1,
1290   VEX_LEN_0FXOP_08_C2,
1291   VEX_LEN_0FXOP_08_C3,
1292   VEX_LEN_0FXOP_08_CC,
1293   VEX_LEN_0FXOP_08_CD,
1294   VEX_LEN_0FXOP_08_CE,
1295   VEX_LEN_0FXOP_08_CF,
1296   VEX_LEN_0FXOP_08_EC,
1297   VEX_LEN_0FXOP_08_ED,
1298   VEX_LEN_0FXOP_08_EE,
1299   VEX_LEN_0FXOP_08_EF,
1300   VEX_LEN_0FXOP_09_01,
1301   VEX_LEN_0FXOP_09_02,
1302   VEX_LEN_0FXOP_09_12_M_1,
1303   VEX_LEN_0FXOP_09_82_W_0,
1304   VEX_LEN_0FXOP_09_83_W_0,
1305   VEX_LEN_0FXOP_09_90,
1306   VEX_LEN_0FXOP_09_91,
1307   VEX_LEN_0FXOP_09_92,
1308   VEX_LEN_0FXOP_09_93,
1309   VEX_LEN_0FXOP_09_94,
1310   VEX_LEN_0FXOP_09_95,
1311   VEX_LEN_0FXOP_09_96,
1312   VEX_LEN_0FXOP_09_97,
1313   VEX_LEN_0FXOP_09_98,
1314   VEX_LEN_0FXOP_09_99,
1315   VEX_LEN_0FXOP_09_9A,
1316   VEX_LEN_0FXOP_09_9B,
1317   VEX_LEN_0FXOP_09_C1,
1318   VEX_LEN_0FXOP_09_C2,
1319   VEX_LEN_0FXOP_09_C3,
1320   VEX_LEN_0FXOP_09_C6,
1321   VEX_LEN_0FXOP_09_C7,
1322   VEX_LEN_0FXOP_09_CB,
1323   VEX_LEN_0FXOP_09_D1,
1324   VEX_LEN_0FXOP_09_D2,
1325   VEX_LEN_0FXOP_09_D3,
1326   VEX_LEN_0FXOP_09_D6,
1327   VEX_LEN_0FXOP_09_D7,
1328   VEX_LEN_0FXOP_09_DB,
1329   VEX_LEN_0FXOP_09_E1,
1330   VEX_LEN_0FXOP_09_E2,
1331   VEX_LEN_0FXOP_09_E3,
1332   VEX_LEN_0FXOP_0A_12,
1333 };
1334
1335 enum
1336 {
1337   EVEX_LEN_0F6E = 0,
1338   EVEX_LEN_0F7E_P_1,
1339   EVEX_LEN_0F7E_P_2,
1340   EVEX_LEN_0FC4,
1341   EVEX_LEN_0FC5,
1342   EVEX_LEN_0FD6,
1343   EVEX_LEN_0F3816,
1344   EVEX_LEN_0F3819,
1345   EVEX_LEN_0F381A_M_0,
1346   EVEX_LEN_0F381B_M_0,
1347   EVEX_LEN_0F3836,
1348   EVEX_LEN_0F385A_M_0,
1349   EVEX_LEN_0F385B_M_0,
1350   EVEX_LEN_0F38C6_M_0,
1351   EVEX_LEN_0F38C7_M_0,
1352   EVEX_LEN_0F3A00,
1353   EVEX_LEN_0F3A01,
1354   EVEX_LEN_0F3A14,
1355   EVEX_LEN_0F3A15,
1356   EVEX_LEN_0F3A16,
1357   EVEX_LEN_0F3A17,
1358   EVEX_LEN_0F3A18,
1359   EVEX_LEN_0F3A19,
1360   EVEX_LEN_0F3A1A,
1361   EVEX_LEN_0F3A1B,
1362   EVEX_LEN_0F3A20,
1363   EVEX_LEN_0F3A21_W_0,
1364   EVEX_LEN_0F3A22,
1365   EVEX_LEN_0F3A23,
1366   EVEX_LEN_0F3A38,
1367   EVEX_LEN_0F3A39,
1368   EVEX_LEN_0F3A3A,
1369   EVEX_LEN_0F3A3B,
1370   EVEX_LEN_0F3A43
1371 };
1372
1373 enum
1374 {
1375   VEX_W_0F41_L_1_M_1 = 0,
1376   VEX_W_0F42_L_1_M_1,
1377   VEX_W_0F44_L_0_M_1,
1378   VEX_W_0F45_L_1_M_1,
1379   VEX_W_0F46_L_1_M_1,
1380   VEX_W_0F47_L_1_M_1,
1381   VEX_W_0F4A_L_1_M_1,
1382   VEX_W_0F4B_L_1_M_1,
1383   VEX_W_0F90_L_0,
1384   VEX_W_0F91_L_0_M_0,
1385   VEX_W_0F92_L_0_M_1,
1386   VEX_W_0F93_L_0_M_1,
1387   VEX_W_0F98_L_0_M_1,
1388   VEX_W_0F99_L_0_M_1,
1389   VEX_W_0F380C,
1390   VEX_W_0F380D,
1391   VEX_W_0F380E,
1392   VEX_W_0F380F,
1393   VEX_W_0F3813,
1394   VEX_W_0F3816_L_1,
1395   VEX_W_0F3818,
1396   VEX_W_0F3819_L_1,
1397   VEX_W_0F381A_M_0_L_1,
1398   VEX_W_0F382C_M_0,
1399   VEX_W_0F382D_M_0,
1400   VEX_W_0F382E_M_0,
1401   VEX_W_0F382F_M_0,
1402   VEX_W_0F3836,
1403   VEX_W_0F3846,
1404   VEX_W_0F3849_X86_64_P_0,
1405   VEX_W_0F3849_X86_64_P_2,
1406   VEX_W_0F3849_X86_64_P_3,
1407   VEX_W_0F384B_X86_64_P_1,
1408   VEX_W_0F384B_X86_64_P_2,
1409   VEX_W_0F384B_X86_64_P_3,
1410   VEX_W_0F3850,
1411   VEX_W_0F3851,
1412   VEX_W_0F3852,
1413   VEX_W_0F3853,
1414   VEX_W_0F3858,
1415   VEX_W_0F3859,
1416   VEX_W_0F385A_M_0_L_0,
1417   VEX_W_0F385C_X86_64_P_1,
1418   VEX_W_0F385E_X86_64_P_0,
1419   VEX_W_0F385E_X86_64_P_1,
1420   VEX_W_0F385E_X86_64_P_2,
1421   VEX_W_0F385E_X86_64_P_3,
1422   VEX_W_0F3878,
1423   VEX_W_0F3879,
1424   VEX_W_0F38CF,
1425   VEX_W_0F3A00_L_1,
1426   VEX_W_0F3A01_L_1,
1427   VEX_W_0F3A02,
1428   VEX_W_0F3A04,
1429   VEX_W_0F3A05,
1430   VEX_W_0F3A06_L_1,
1431   VEX_W_0F3A18_L_1,
1432   VEX_W_0F3A19_L_1,
1433   VEX_W_0F3A1D,
1434   VEX_W_0F3A38_L_1,
1435   VEX_W_0F3A39_L_1,
1436   VEX_W_0F3A46_L_1,
1437   VEX_W_0F3A4A,
1438   VEX_W_0F3A4B,
1439   VEX_W_0F3A4C,
1440   VEX_W_0F3ACE,
1441   VEX_W_0F3ACF,
1442
1443   VEX_W_0FXOP_08_85_L_0,
1444   VEX_W_0FXOP_08_86_L_0,
1445   VEX_W_0FXOP_08_87_L_0,
1446   VEX_W_0FXOP_08_8E_L_0,
1447   VEX_W_0FXOP_08_8F_L_0,
1448   VEX_W_0FXOP_08_95_L_0,
1449   VEX_W_0FXOP_08_96_L_0,
1450   VEX_W_0FXOP_08_97_L_0,
1451   VEX_W_0FXOP_08_9E_L_0,
1452   VEX_W_0FXOP_08_9F_L_0,
1453   VEX_W_0FXOP_08_A6_L_0,
1454   VEX_W_0FXOP_08_B6_L_0,
1455   VEX_W_0FXOP_08_C0_L_0,
1456   VEX_W_0FXOP_08_C1_L_0,
1457   VEX_W_0FXOP_08_C2_L_0,
1458   VEX_W_0FXOP_08_C3_L_0,
1459   VEX_W_0FXOP_08_CC_L_0,
1460   VEX_W_0FXOP_08_CD_L_0,
1461   VEX_W_0FXOP_08_CE_L_0,
1462   VEX_W_0FXOP_08_CF_L_0,
1463   VEX_W_0FXOP_08_EC_L_0,
1464   VEX_W_0FXOP_08_ED_L_0,
1465   VEX_W_0FXOP_08_EE_L_0,
1466   VEX_W_0FXOP_08_EF_L_0,
1467
1468   VEX_W_0FXOP_09_80,
1469   VEX_W_0FXOP_09_81,
1470   VEX_W_0FXOP_09_82,
1471   VEX_W_0FXOP_09_83,
1472   VEX_W_0FXOP_09_C1_L_0,
1473   VEX_W_0FXOP_09_C2_L_0,
1474   VEX_W_0FXOP_09_C3_L_0,
1475   VEX_W_0FXOP_09_C6_L_0,
1476   VEX_W_0FXOP_09_C7_L_0,
1477   VEX_W_0FXOP_09_CB_L_0,
1478   VEX_W_0FXOP_09_D1_L_0,
1479   VEX_W_0FXOP_09_D2_L_0,
1480   VEX_W_0FXOP_09_D3_L_0,
1481   VEX_W_0FXOP_09_D6_L_0,
1482   VEX_W_0FXOP_09_D7_L_0,
1483   VEX_W_0FXOP_09_DB_L_0,
1484   VEX_W_0FXOP_09_E1_L_0,
1485   VEX_W_0FXOP_09_E2_L_0,
1486   VEX_W_0FXOP_09_E3_L_0,
1487
1488   EVEX_W_0F10_P_1,
1489   EVEX_W_0F10_P_3,
1490   EVEX_W_0F11_P_1,
1491   EVEX_W_0F11_P_3,
1492   EVEX_W_0F12_P_0_M_1,
1493   EVEX_W_0F12_P_1,
1494   EVEX_W_0F12_P_3,
1495   EVEX_W_0F16_P_0_M_1,
1496   EVEX_W_0F16_P_1,
1497   EVEX_W_0F2A_P_3,
1498   EVEX_W_0F51_P_1,
1499   EVEX_W_0F51_P_3,
1500   EVEX_W_0F58_P_1,
1501   EVEX_W_0F58_P_3,
1502   EVEX_W_0F59_P_1,
1503   EVEX_W_0F59_P_3,
1504   EVEX_W_0F5A_P_0,
1505   EVEX_W_0F5A_P_1,
1506   EVEX_W_0F5A_P_2,
1507   EVEX_W_0F5A_P_3,
1508   EVEX_W_0F5B_P_0,
1509   EVEX_W_0F5B_P_1,
1510   EVEX_W_0F5B_P_2,
1511   EVEX_W_0F5C_P_1,
1512   EVEX_W_0F5C_P_3,
1513   EVEX_W_0F5D_P_1,
1514   EVEX_W_0F5D_P_3,
1515   EVEX_W_0F5E_P_1,
1516   EVEX_W_0F5E_P_3,
1517   EVEX_W_0F5F_P_1,
1518   EVEX_W_0F5F_P_3,
1519   EVEX_W_0F62,
1520   EVEX_W_0F66,
1521   EVEX_W_0F6A,
1522   EVEX_W_0F6B,
1523   EVEX_W_0F6C,
1524   EVEX_W_0F6D,
1525   EVEX_W_0F6F_P_1,
1526   EVEX_W_0F6F_P_2,
1527   EVEX_W_0F6F_P_3,
1528   EVEX_W_0F70_P_2,
1529   EVEX_W_0F72_R_2,
1530   EVEX_W_0F72_R_6,
1531   EVEX_W_0F73_R_2,
1532   EVEX_W_0F73_R_6,
1533   EVEX_W_0F76,
1534   EVEX_W_0F78_P_0,
1535   EVEX_W_0F78_P_2,
1536   EVEX_W_0F79_P_0,
1537   EVEX_W_0F79_P_2,
1538   EVEX_W_0F7A_P_1,
1539   EVEX_W_0F7A_P_2,
1540   EVEX_W_0F7A_P_3,
1541   EVEX_W_0F7B_P_2,
1542   EVEX_W_0F7B_P_3,
1543   EVEX_W_0F7E_P_1,
1544   EVEX_W_0F7F_P_1,
1545   EVEX_W_0F7F_P_2,
1546   EVEX_W_0F7F_P_3,
1547   EVEX_W_0FC2_P_1,
1548   EVEX_W_0FC2_P_3,
1549   EVEX_W_0FD2,
1550   EVEX_W_0FD3,
1551   EVEX_W_0FD4,
1552   EVEX_W_0FD6_L_0,
1553   EVEX_W_0FE6_P_1,
1554   EVEX_W_0FE6_P_2,
1555   EVEX_W_0FE6_P_3,
1556   EVEX_W_0FE7,
1557   EVEX_W_0FF2,
1558   EVEX_W_0FF3,
1559   EVEX_W_0FF4,
1560   EVEX_W_0FFA,
1561   EVEX_W_0FFB,
1562   EVEX_W_0FFE,
1563   EVEX_W_0F380D,
1564   EVEX_W_0F3810_P_1,
1565   EVEX_W_0F3810_P_2,
1566   EVEX_W_0F3811_P_1,
1567   EVEX_W_0F3811_P_2,
1568   EVEX_W_0F3812_P_1,
1569   EVEX_W_0F3812_P_2,
1570   EVEX_W_0F3813_P_1,
1571   EVEX_W_0F3813_P_2,
1572   EVEX_W_0F3814_P_1,
1573   EVEX_W_0F3815_P_1,
1574   EVEX_W_0F3819_L_n,
1575   EVEX_W_0F381A_M_0_L_n,
1576   EVEX_W_0F381B_M_0_L_2,
1577   EVEX_W_0F381E,
1578   EVEX_W_0F381F,
1579   EVEX_W_0F3820_P_1,
1580   EVEX_W_0F3821_P_1,
1581   EVEX_W_0F3822_P_1,
1582   EVEX_W_0F3823_P_1,
1583   EVEX_W_0F3824_P_1,
1584   EVEX_W_0F3825_P_1,
1585   EVEX_W_0F3825_P_2,
1586   EVEX_W_0F3828_P_2,
1587   EVEX_W_0F3829_P_2,
1588   EVEX_W_0F382A_P_1,
1589   EVEX_W_0F382A_P_2,
1590   EVEX_W_0F382B,
1591   EVEX_W_0F3830_P_1,
1592   EVEX_W_0F3831_P_1,
1593   EVEX_W_0F3832_P_1,
1594   EVEX_W_0F3833_P_1,
1595   EVEX_W_0F3834_P_1,
1596   EVEX_W_0F3835_P_1,
1597   EVEX_W_0F3835_P_2,
1598   EVEX_W_0F3837,
1599   EVEX_W_0F383A_P_1,
1600   EVEX_W_0F3852_P_1,
1601   EVEX_W_0F3859,
1602   EVEX_W_0F385A_M_0_L_n,
1603   EVEX_W_0F385B_M_0_L_2,
1604   EVEX_W_0F3870,
1605   EVEX_W_0F3872_P_1,
1606   EVEX_W_0F3872_P_2,
1607   EVEX_W_0F3872_P_3,
1608   EVEX_W_0F387A,
1609   EVEX_W_0F387B,
1610   EVEX_W_0F3883,
1611   EVEX_W_0F3891,
1612   EVEX_W_0F3893,
1613   EVEX_W_0F38A1,
1614   EVEX_W_0F38A3,
1615   EVEX_W_0F38C7_M_0_L_2,
1616
1617   EVEX_W_0F3A05,
1618   EVEX_W_0F3A08,
1619   EVEX_W_0F3A09,
1620   EVEX_W_0F3A0A,
1621   EVEX_W_0F3A0B,
1622   EVEX_W_0F3A18_L_n,
1623   EVEX_W_0F3A19_L_n,
1624   EVEX_W_0F3A1A_L_2,
1625   EVEX_W_0F3A1B_L_2,
1626   EVEX_W_0F3A21,
1627   EVEX_W_0F3A23_L_n,
1628   EVEX_W_0F3A38_L_n,
1629   EVEX_W_0F3A39_L_n,
1630   EVEX_W_0F3A3A_L_2,
1631   EVEX_W_0F3A3B_L_2,
1632   EVEX_W_0F3A42,
1633   EVEX_W_0F3A43_L_n,
1634   EVEX_W_0F3A70,
1635   EVEX_W_0F3A72,
1636 };
1637
1638 typedef void (*op_rtn) (int bytemode, int sizeflag);
1639
1640 struct dis386 {
1641   const char *name;
1642   struct
1643     {
1644       op_rtn rtn;
1645       int bytemode;
1646     } op[MAX_OPERANDS];
1647   unsigned int prefix_requirement;
1648 };
1649
1650 /* Upper case letters in the instruction names here are macros.
1651    'A' => print 'b' if no register operands or suffix_always is true
1652    'B' => print 'b' if suffix_always is true
1653    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1654           size prefix
1655    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1656           suffix_always is true
1657    'E' => print 'e' if 32-bit form of jcxz
1658    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1659    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1660    'H' => print ",pt" or ",pn" branch hint
1661    'I' unused.
1662    'J' unused.
1663    'K' => print 'd' or 'q' if rex prefix is present.
1664    'L' unused.
1665    'M' => print 'r' if intel_mnemonic is false.
1666    'N' => print 'n' if instruction has no wait "prefix"
1667    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1668    'P' => behave as 'T' except with register operand outside of suffix_always
1669           mode
1670    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1671           is true
1672    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1673    'S' => print 'w', 'l' or 'q' if suffix_always is true
1674    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1675           prefix or if suffix_always is true.
1676    'U' unused.
1677    'V' unused.
1678    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1679    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1680    'Y' unused.
1681    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1682    '!' => change condition from true to false or from false to true.
1683    '%' => add 1 upper case letter to the macro.
1684    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1685           prefix or suffix_always is true (lcall/ljmp).
1686    '@' => in 64bit mode for Intel64 ISA or if instruction
1687           has no operand sizing prefix, print 'q' if suffix_always is true or
1688           nothing otherwise; behave as 'P' in all other cases
1689
1690    2 upper case letter macros:
1691    "XY" => print 'x' or 'y' if suffix_always is true or no register
1692            operands and no broadcast.
1693    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1694            register operands and no broadcast.
1695    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1696    "XV" => print "{vex3}" pseudo prefix
1697    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1698            being false, or no operand at all in 64bit mode, or if suffix_always
1699            is true.
1700    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1701    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1702    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1703    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1704    "BW" => print 'b' or 'w' depending on the VEX.W bit
1705    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1706            an operand size prefix, or suffix_always is true.  print
1707            'q' if rex prefix is present.
1708
1709    Many of the above letters print nothing in Intel mode.  See "putop"
1710    for the details.
1711
1712    Braces '{' and '}', and vertical bars '|', indicate alternative
1713    mnemonic strings for AT&T and Intel.  */
1714
1715 static const struct dis386 dis386[] = {
1716   /* 00 */
1717   { "addB",             { Ebh1, Gb }, 0 },
1718   { "addS",             { Evh1, Gv }, 0 },
1719   { "addB",             { Gb, EbS }, 0 },
1720   { "addS",             { Gv, EvS }, 0 },
1721   { "addB",             { AL, Ib }, 0 },
1722   { "addS",             { eAX, Iv }, 0 },
1723   { X86_64_TABLE (X86_64_06) },
1724   { X86_64_TABLE (X86_64_07) },
1725   /* 08 */
1726   { "orB",              { Ebh1, Gb }, 0 },
1727   { "orS",              { Evh1, Gv }, 0 },
1728   { "orB",              { Gb, EbS }, 0 },
1729   { "orS",              { Gv, EvS }, 0 },
1730   { "orB",              { AL, Ib }, 0 },
1731   { "orS",              { eAX, Iv }, 0 },
1732   { X86_64_TABLE (X86_64_0E) },
1733   { Bad_Opcode },       /* 0x0f extended opcode escape */
1734   /* 10 */
1735   { "adcB",             { Ebh1, Gb }, 0 },
1736   { "adcS",             { Evh1, Gv }, 0 },
1737   { "adcB",             { Gb, EbS }, 0 },
1738   { "adcS",             { Gv, EvS }, 0 },
1739   { "adcB",             { AL, Ib }, 0 },
1740   { "adcS",             { eAX, Iv }, 0 },
1741   { X86_64_TABLE (X86_64_16) },
1742   { X86_64_TABLE (X86_64_17) },
1743   /* 18 */
1744   { "sbbB",             { Ebh1, Gb }, 0 },
1745   { "sbbS",             { Evh1, Gv }, 0 },
1746   { "sbbB",             { Gb, EbS }, 0 },
1747   { "sbbS",             { Gv, EvS }, 0 },
1748   { "sbbB",             { AL, Ib }, 0 },
1749   { "sbbS",             { eAX, Iv }, 0 },
1750   { X86_64_TABLE (X86_64_1E) },
1751   { X86_64_TABLE (X86_64_1F) },
1752   /* 20 */
1753   { "andB",             { Ebh1, Gb }, 0 },
1754   { "andS",             { Evh1, Gv }, 0 },
1755   { "andB",             { Gb, EbS }, 0 },
1756   { "andS",             { Gv, EvS }, 0 },
1757   { "andB",             { AL, Ib }, 0 },
1758   { "andS",             { eAX, Iv }, 0 },
1759   { Bad_Opcode },       /* SEG ES prefix */
1760   { X86_64_TABLE (X86_64_27) },
1761   /* 28 */
1762   { "subB",             { Ebh1, Gb }, 0 },
1763   { "subS",             { Evh1, Gv }, 0 },
1764   { "subB",             { Gb, EbS }, 0 },
1765   { "subS",             { Gv, EvS }, 0 },
1766   { "subB",             { AL, Ib }, 0 },
1767   { "subS",             { eAX, Iv }, 0 },
1768   { Bad_Opcode },       /* SEG CS prefix */
1769   { X86_64_TABLE (X86_64_2F) },
1770   /* 30 */
1771   { "xorB",             { Ebh1, Gb }, 0 },
1772   { "xorS",             { Evh1, Gv }, 0 },
1773   { "xorB",             { Gb, EbS }, 0 },
1774   { "xorS",             { Gv, EvS }, 0 },
1775   { "xorB",             { AL, Ib }, 0 },
1776   { "xorS",             { eAX, Iv }, 0 },
1777   { Bad_Opcode },       /* SEG SS prefix */
1778   { X86_64_TABLE (X86_64_37) },
1779   /* 38 */
1780   { "cmpB",             { Eb, Gb }, 0 },
1781   { "cmpS",             { Ev, Gv }, 0 },
1782   { "cmpB",             { Gb, EbS }, 0 },
1783   { "cmpS",             { Gv, EvS }, 0 },
1784   { "cmpB",             { AL, Ib }, 0 },
1785   { "cmpS",             { eAX, Iv }, 0 },
1786   { Bad_Opcode },       /* SEG DS prefix */
1787   { X86_64_TABLE (X86_64_3F) },
1788   /* 40 */
1789   { "inc{S|}",          { RMeAX }, 0 },
1790   { "inc{S|}",          { RMeCX }, 0 },
1791   { "inc{S|}",          { RMeDX }, 0 },
1792   { "inc{S|}",          { RMeBX }, 0 },
1793   { "inc{S|}",          { RMeSP }, 0 },
1794   { "inc{S|}",          { RMeBP }, 0 },
1795   { "inc{S|}",          { RMeSI }, 0 },
1796   { "inc{S|}",          { RMeDI }, 0 },
1797   /* 48 */
1798   { "dec{S|}",          { RMeAX }, 0 },
1799   { "dec{S|}",          { RMeCX }, 0 },
1800   { "dec{S|}",          { RMeDX }, 0 },
1801   { "dec{S|}",          { RMeBX }, 0 },
1802   { "dec{S|}",          { RMeSP }, 0 },
1803   { "dec{S|}",          { RMeBP }, 0 },
1804   { "dec{S|}",          { RMeSI }, 0 },
1805   { "dec{S|}",          { RMeDI }, 0 },
1806   /* 50 */
1807   { "push{!P|}",                { RMrAX }, 0 },
1808   { "push{!P|}",                { RMrCX }, 0 },
1809   { "push{!P|}",                { RMrDX }, 0 },
1810   { "push{!P|}",                { RMrBX }, 0 },
1811   { "push{!P|}",                { RMrSP }, 0 },
1812   { "push{!P|}",                { RMrBP }, 0 },
1813   { "push{!P|}",                { RMrSI }, 0 },
1814   { "push{!P|}",                { RMrDI }, 0 },
1815   /* 58 */
1816   { "pop{!P|}",         { RMrAX }, 0 },
1817   { "pop{!P|}",         { RMrCX }, 0 },
1818   { "pop{!P|}",         { RMrDX }, 0 },
1819   { "pop{!P|}",         { RMrBX }, 0 },
1820   { "pop{!P|}",         { RMrSP }, 0 },
1821   { "pop{!P|}",         { RMrBP }, 0 },
1822   { "pop{!P|}",         { RMrSI }, 0 },
1823   { "pop{!P|}",         { RMrDI }, 0 },
1824   /* 60 */
1825   { X86_64_TABLE (X86_64_60) },
1826   { X86_64_TABLE (X86_64_61) },
1827   { X86_64_TABLE (X86_64_62) },
1828   { X86_64_TABLE (X86_64_63) },
1829   { Bad_Opcode },       /* seg fs */
1830   { Bad_Opcode },       /* seg gs */
1831   { Bad_Opcode },       /* op size prefix */
1832   { Bad_Opcode },       /* adr size prefix */
1833   /* 68 */
1834   { "pushP",            { sIv }, 0 },
1835   { "imulS",            { Gv, Ev, Iv }, 0 },
1836   { "pushP",            { sIbT }, 0 },
1837   { "imulS",            { Gv, Ev, sIb }, 0 },
1838   { "ins{b|}",          { Ybr, indirDX }, 0 },
1839   { X86_64_TABLE (X86_64_6D) },
1840   { "outs{b|}",         { indirDXr, Xb }, 0 },
1841   { X86_64_TABLE (X86_64_6F) },
1842   /* 70 */
1843   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
1844   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
1845   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
1846   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
1847   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
1848   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
1849   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
1850   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
1851   /* 78 */
1852   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
1853   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
1854   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
1855   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
1856   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
1857   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
1858   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
1859   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
1860   /* 80 */
1861   { REG_TABLE (REG_80) },
1862   { REG_TABLE (REG_81) },
1863   { X86_64_TABLE (X86_64_82) },
1864   { REG_TABLE (REG_83) },
1865   { "testB",            { Eb, Gb }, 0 },
1866   { "testS",            { Ev, Gv }, 0 },
1867   { "xchgB",            { Ebh2, Gb }, 0 },
1868   { "xchgS",            { Evh2, Gv }, 0 },
1869   /* 88 */
1870   { "movB",             { Ebh3, Gb }, 0 },
1871   { "movS",             { Evh3, Gv }, 0 },
1872   { "movB",             { Gb, EbS }, 0 },
1873   { "movS",             { Gv, EvS }, 0 },
1874   { "movD",             { Sv, Sw }, 0 },
1875   { MOD_TABLE (MOD_8D) },
1876   { "movD",             { Sw, Sv }, 0 },
1877   { REG_TABLE (REG_8F) },
1878   /* 90 */
1879   { PREFIX_TABLE (PREFIX_90) },
1880   { "xchgS",            { RMeCX, eAX }, 0 },
1881   { "xchgS",            { RMeDX, eAX }, 0 },
1882   { "xchgS",            { RMeBX, eAX }, 0 },
1883   { "xchgS",            { RMeSP, eAX }, 0 },
1884   { "xchgS",            { RMeBP, eAX }, 0 },
1885   { "xchgS",            { RMeSI, eAX }, 0 },
1886   { "xchgS",            { RMeDI, eAX }, 0 },
1887   /* 98 */
1888   { "cW{t|}R",          { XX }, 0 },
1889   { "cR{t|}O",          { XX }, 0 },
1890   { X86_64_TABLE (X86_64_9A) },
1891   { Bad_Opcode },       /* fwait */
1892   { "pushfP",           { XX }, 0 },
1893   { "popfP",            { XX }, 0 },
1894   { "sahf",             { XX }, 0 },
1895   { "lahf",             { XX }, 0 },
1896   /* a0 */
1897   { "mov%LB",           { AL, Ob }, 0 },
1898   { "mov%LS",           { eAX, Ov }, 0 },
1899   { "mov%LB",           { Ob, AL }, 0 },
1900   { "mov%LS",           { Ov, eAX }, 0 },
1901   { "movs{b|}",         { Ybr, Xb }, 0 },
1902   { "movs{R|}",         { Yvr, Xv }, 0 },
1903   { "cmps{b|}",         { Xb, Yb }, 0 },
1904   { "cmps{R|}",         { Xv, Yv }, 0 },
1905   /* a8 */
1906   { "testB",            { AL, Ib }, 0 },
1907   { "testS",            { eAX, Iv }, 0 },
1908   { "stosB",            { Ybr, AL }, 0 },
1909   { "stosS",            { Yvr, eAX }, 0 },
1910   { "lodsB",            { ALr, Xb }, 0 },
1911   { "lodsS",            { eAXr, Xv }, 0 },
1912   { "scasB",            { AL, Yb }, 0 },
1913   { "scasS",            { eAX, Yv }, 0 },
1914   /* b0 */
1915   { "movB",             { RMAL, Ib }, 0 },
1916   { "movB",             { RMCL, Ib }, 0 },
1917   { "movB",             { RMDL, Ib }, 0 },
1918   { "movB",             { RMBL, Ib }, 0 },
1919   { "movB",             { RMAH, Ib }, 0 },
1920   { "movB",             { RMCH, Ib }, 0 },
1921   { "movB",             { RMDH, Ib }, 0 },
1922   { "movB",             { RMBH, Ib }, 0 },
1923   /* b8 */
1924   { "mov%LV",           { RMeAX, Iv64 }, 0 },
1925   { "mov%LV",           { RMeCX, Iv64 }, 0 },
1926   { "mov%LV",           { RMeDX, Iv64 }, 0 },
1927   { "mov%LV",           { RMeBX, Iv64 }, 0 },
1928   { "mov%LV",           { RMeSP, Iv64 }, 0 },
1929   { "mov%LV",           { RMeBP, Iv64 }, 0 },
1930   { "mov%LV",           { RMeSI, Iv64 }, 0 },
1931   { "mov%LV",           { RMeDI, Iv64 }, 0 },
1932   /* c0 */
1933   { REG_TABLE (REG_C0) },
1934   { REG_TABLE (REG_C1) },
1935   { X86_64_TABLE (X86_64_C2) },
1936   { X86_64_TABLE (X86_64_C3) },
1937   { X86_64_TABLE (X86_64_C4) },
1938   { X86_64_TABLE (X86_64_C5) },
1939   { REG_TABLE (REG_C6) },
1940   { REG_TABLE (REG_C7) },
1941   /* c8 */
1942   { "enterP",           { Iw, Ib }, 0 },
1943   { "leaveP",           { XX }, 0 },
1944   { "{l|}ret{|f}%LP",   { Iw }, 0 },
1945   { "{l|}ret{|f}%LP",   { XX }, 0 },
1946   { "int3",             { XX }, 0 },
1947   { "int",              { Ib }, 0 },
1948   { X86_64_TABLE (X86_64_CE) },
1949   { "iret%LP",          { XX }, 0 },
1950   /* d0 */
1951   { REG_TABLE (REG_D0) },
1952   { REG_TABLE (REG_D1) },
1953   { REG_TABLE (REG_D2) },
1954   { REG_TABLE (REG_D3) },
1955   { X86_64_TABLE (X86_64_D4) },
1956   { X86_64_TABLE (X86_64_D5) },
1957   { Bad_Opcode },
1958   { "xlat",             { DSBX }, 0 },
1959   /* d8 */
1960   { FLOAT },
1961   { FLOAT },
1962   { FLOAT },
1963   { FLOAT },
1964   { FLOAT },
1965   { FLOAT },
1966   { FLOAT },
1967   { FLOAT },
1968   /* e0 */
1969   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
1970   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
1971   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
1972   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
1973   { "inB",              { AL, Ib }, 0 },
1974   { "inG",              { zAX, Ib }, 0 },
1975   { "outB",             { Ib, AL }, 0 },
1976   { "outG",             { Ib, zAX }, 0 },
1977   /* e8 */
1978   { X86_64_TABLE (X86_64_E8) },
1979   { X86_64_TABLE (X86_64_E9) },
1980   { X86_64_TABLE (X86_64_EA) },
1981   { "jmp",              { Jb, BND }, 0 },
1982   { "inB",              { AL, indirDX }, 0 },
1983   { "inG",              { zAX, indirDX }, 0 },
1984   { "outB",             { indirDX, AL }, 0 },
1985   { "outG",             { indirDX, zAX }, 0 },
1986   /* f0 */
1987   { Bad_Opcode },       /* lock prefix */
1988   { "icebp",            { XX }, 0 },
1989   { Bad_Opcode },       /* repne */
1990   { Bad_Opcode },       /* repz */
1991   { "hlt",              { XX }, 0 },
1992   { "cmc",              { XX }, 0 },
1993   { REG_TABLE (REG_F6) },
1994   { REG_TABLE (REG_F7) },
1995   /* f8 */
1996   { "clc",              { XX }, 0 },
1997   { "stc",              { XX }, 0 },
1998   { "cli",              { XX }, 0 },
1999   { "sti",              { XX }, 0 },
2000   { "cld",              { XX }, 0 },
2001   { "std",              { XX }, 0 },
2002   { REG_TABLE (REG_FE) },
2003   { REG_TABLE (REG_FF) },
2004 };
2005
2006 static const struct dis386 dis386_twobyte[] = {
2007   /* 00 */
2008   { REG_TABLE (REG_0F00 ) },
2009   { REG_TABLE (REG_0F01 ) },
2010   { "larS",             { Gv, Ew }, 0 },
2011   { "lslS",             { Gv, Ew }, 0 },
2012   { Bad_Opcode },
2013   { "syscall",          { XX }, 0 },
2014   { "clts",             { XX }, 0 },
2015   { "sysret%LQ",                { XX }, 0 },
2016   /* 08 */
2017   { "invd",             { XX }, 0 },
2018   { PREFIX_TABLE (PREFIX_0F09) },
2019   { Bad_Opcode },
2020   { "ud2",              { XX }, 0 },
2021   { Bad_Opcode },
2022   { REG_TABLE (REG_0F0D) },
2023   { "femms",            { XX }, 0 },
2024   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2025   /* 10 */
2026   { PREFIX_TABLE (PREFIX_0F10) },
2027   { PREFIX_TABLE (PREFIX_0F11) },
2028   { PREFIX_TABLE (PREFIX_0F12) },
2029   { MOD_TABLE (MOD_0F13) },
2030   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2031   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2032   { PREFIX_TABLE (PREFIX_0F16) },
2033   { MOD_TABLE (MOD_0F17) },
2034   /* 18 */
2035   { REG_TABLE (REG_0F18) },
2036   { "nopQ",             { Ev }, 0 },
2037   { PREFIX_TABLE (PREFIX_0F1A) },
2038   { PREFIX_TABLE (PREFIX_0F1B) },
2039   { PREFIX_TABLE (PREFIX_0F1C) },
2040   { "nopQ",             { Ev }, 0 },
2041   { PREFIX_TABLE (PREFIX_0F1E) },
2042   { "nopQ",             { Ev }, 0 },
2043   /* 20 */
2044   { "movZ",             { Em, Cm }, 0 },
2045   { "movZ",             { Em, Dm }, 0 },
2046   { "movZ",             { Cm, Em }, 0 },
2047   { "movZ",             { Dm, Em }, 0 },
2048   { X86_64_TABLE (X86_64_0F24) },
2049   { Bad_Opcode },
2050   { X86_64_TABLE (X86_64_0F26) },
2051   { Bad_Opcode },
2052   /* 28 */
2053   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2054   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2055   { PREFIX_TABLE (PREFIX_0F2A) },
2056   { PREFIX_TABLE (PREFIX_0F2B) },
2057   { PREFIX_TABLE (PREFIX_0F2C) },
2058   { PREFIX_TABLE (PREFIX_0F2D) },
2059   { PREFIX_TABLE (PREFIX_0F2E) },
2060   { PREFIX_TABLE (PREFIX_0F2F) },
2061   /* 30 */
2062   { "wrmsr",            { XX }, 0 },
2063   { "rdtsc",            { XX }, 0 },
2064   { "rdmsr",            { XX }, 0 },
2065   { "rdpmc",            { XX }, 0 },
2066   { "sysenter",         { SEP }, 0 },
2067   { "sysexit%LQ",       { SEP }, 0 },
2068   { Bad_Opcode },
2069   { "getsec",           { XX }, 0 },
2070   /* 38 */
2071   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2072   { Bad_Opcode },
2073   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2074   { Bad_Opcode },
2075   { Bad_Opcode },
2076   { Bad_Opcode },
2077   { Bad_Opcode },
2078   { Bad_Opcode },
2079   /* 40 */
2080   { "cmovoS",           { Gv, Ev }, 0 },
2081   { "cmovnoS",          { Gv, Ev }, 0 },
2082   { "cmovbS",           { Gv, Ev }, 0 },
2083   { "cmovaeS",          { Gv, Ev }, 0 },
2084   { "cmoveS",           { Gv, Ev }, 0 },
2085   { "cmovneS",          { Gv, Ev }, 0 },
2086   { "cmovbeS",          { Gv, Ev }, 0 },
2087   { "cmovaS",           { Gv, Ev }, 0 },
2088   /* 48 */
2089   { "cmovsS",           { Gv, Ev }, 0 },
2090   { "cmovnsS",          { Gv, Ev }, 0 },
2091   { "cmovpS",           { Gv, Ev }, 0 },
2092   { "cmovnpS",          { Gv, Ev }, 0 },
2093   { "cmovlS",           { Gv, Ev }, 0 },
2094   { "cmovgeS",          { Gv, Ev }, 0 },
2095   { "cmovleS",          { Gv, Ev }, 0 },
2096   { "cmovgS",           { Gv, Ev }, 0 },
2097   /* 50 */
2098   { MOD_TABLE (MOD_0F50) },
2099   { PREFIX_TABLE (PREFIX_0F51) },
2100   { PREFIX_TABLE (PREFIX_0F52) },
2101   { PREFIX_TABLE (PREFIX_0F53) },
2102   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2103   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2104   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2105   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2106   /* 58 */
2107   { PREFIX_TABLE (PREFIX_0F58) },
2108   { PREFIX_TABLE (PREFIX_0F59) },
2109   { PREFIX_TABLE (PREFIX_0F5A) },
2110   { PREFIX_TABLE (PREFIX_0F5B) },
2111   { PREFIX_TABLE (PREFIX_0F5C) },
2112   { PREFIX_TABLE (PREFIX_0F5D) },
2113   { PREFIX_TABLE (PREFIX_0F5E) },
2114   { PREFIX_TABLE (PREFIX_0F5F) },
2115   /* 60 */
2116   { PREFIX_TABLE (PREFIX_0F60) },
2117   { PREFIX_TABLE (PREFIX_0F61) },
2118   { PREFIX_TABLE (PREFIX_0F62) },
2119   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2120   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2121   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2122   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2123   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2124   /* 68 */
2125   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2126   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2127   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2128   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2129   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2130   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2131   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2132   { PREFIX_TABLE (PREFIX_0F6F) },
2133   /* 70 */
2134   { PREFIX_TABLE (PREFIX_0F70) },
2135   { MOD_TABLE (MOD_0F71) },
2136   { MOD_TABLE (MOD_0F72) },
2137   { MOD_TABLE (MOD_0F73) },
2138   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2139   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2140   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2141   { "emms",             { XX }, PREFIX_OPCODE },
2142   /* 78 */
2143   { PREFIX_TABLE (PREFIX_0F78) },
2144   { PREFIX_TABLE (PREFIX_0F79) },
2145   { Bad_Opcode },
2146   { Bad_Opcode },
2147   { PREFIX_TABLE (PREFIX_0F7C) },
2148   { PREFIX_TABLE (PREFIX_0F7D) },
2149   { PREFIX_TABLE (PREFIX_0F7E) },
2150   { PREFIX_TABLE (PREFIX_0F7F) },
2151   /* 80 */
2152   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2153   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2154   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2155   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2156   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2157   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2158   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2159   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2160   /* 88 */
2161   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2162   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2163   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2164   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2165   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2166   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2167   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2168   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2169   /* 90 */
2170   { "seto",             { Eb }, 0 },
2171   { "setno",            { Eb }, 0 },
2172   { "setb",             { Eb }, 0 },
2173   { "setae",            { Eb }, 0 },
2174   { "sete",             { Eb }, 0 },
2175   { "setne",            { Eb }, 0 },
2176   { "setbe",            { Eb }, 0 },
2177   { "seta",             { Eb }, 0 },
2178   /* 98 */
2179   { "sets",             { Eb }, 0 },
2180   { "setns",            { Eb }, 0 },
2181   { "setp",             { Eb }, 0 },
2182   { "setnp",            { Eb }, 0 },
2183   { "setl",             { Eb }, 0 },
2184   { "setge",            { Eb }, 0 },
2185   { "setle",            { Eb }, 0 },
2186   { "setg",             { Eb }, 0 },
2187   /* a0 */
2188   { "pushP",            { fs }, 0 },
2189   { "popP",             { fs }, 0 },
2190   { "cpuid",            { XX }, 0 },
2191   { "btS",              { Ev, Gv }, 0 },
2192   { "shldS",            { Ev, Gv, Ib }, 0 },
2193   { "shldS",            { Ev, Gv, CL }, 0 },
2194   { REG_TABLE (REG_0FA6) },
2195   { REG_TABLE (REG_0FA7) },
2196   /* a8 */
2197   { "pushP",            { gs }, 0 },
2198   { "popP",             { gs }, 0 },
2199   { "rsm",              { XX }, 0 },
2200   { "btsS",             { Evh1, Gv }, 0 },
2201   { "shrdS",            { Ev, Gv, Ib }, 0 },
2202   { "shrdS",            { Ev, Gv, CL }, 0 },
2203   { REG_TABLE (REG_0FAE) },
2204   { "imulS",            { Gv, Ev }, 0 },
2205   /* b0 */
2206   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2207   { "cmpxchgS",         { Evh1, Gv }, 0 },
2208   { MOD_TABLE (MOD_0FB2) },
2209   { "btrS",             { Evh1, Gv }, 0 },
2210   { MOD_TABLE (MOD_0FB4) },
2211   { MOD_TABLE (MOD_0FB5) },
2212   { "movz{bR|x}",       { Gv, Eb }, 0 },
2213   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2214   /* b8 */
2215   { PREFIX_TABLE (PREFIX_0FB8) },
2216   { "ud1S",             { Gv, Ev }, 0 },
2217   { REG_TABLE (REG_0FBA) },
2218   { "btcS",             { Evh1, Gv }, 0 },
2219   { PREFIX_TABLE (PREFIX_0FBC) },
2220   { PREFIX_TABLE (PREFIX_0FBD) },
2221   { "movs{bR|x}",       { Gv, Eb }, 0 },
2222   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2223   /* c0 */
2224   { "xaddB",            { Ebh1, Gb }, 0 },
2225   { "xaddS",            { Evh1, Gv }, 0 },
2226   { PREFIX_TABLE (PREFIX_0FC2) },
2227   { MOD_TABLE (MOD_0FC3) },
2228   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2229   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2230   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2231   { REG_TABLE (REG_0FC7) },
2232   /* c8 */
2233   { "bswap",            { RMeAX }, 0 },
2234   { "bswap",            { RMeCX }, 0 },
2235   { "bswap",            { RMeDX }, 0 },
2236   { "bswap",            { RMeBX }, 0 },
2237   { "bswap",            { RMeSP }, 0 },
2238   { "bswap",            { RMeBP }, 0 },
2239   { "bswap",            { RMeSI }, 0 },
2240   { "bswap",            { RMeDI }, 0 },
2241   /* d0 */
2242   { PREFIX_TABLE (PREFIX_0FD0) },
2243   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2244   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2245   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2246   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2247   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2248   { PREFIX_TABLE (PREFIX_0FD6) },
2249   { MOD_TABLE (MOD_0FD7) },
2250   /* d8 */
2251   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2252   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2253   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2254   { "pand",             { MX, EM }, PREFIX_OPCODE },
2255   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2256   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2257   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2258   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2259   /* e0 */
2260   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2261   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2262   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2263   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2264   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2265   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2266   { PREFIX_TABLE (PREFIX_0FE6) },
2267   { PREFIX_TABLE (PREFIX_0FE7) },
2268   /* e8 */
2269   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2270   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2271   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2272   { "por",              { MX, EM }, PREFIX_OPCODE },
2273   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2274   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2275   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2276   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2277   /* f0 */
2278   { PREFIX_TABLE (PREFIX_0FF0) },
2279   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2280   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2281   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2282   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2283   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2284   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2285   { PREFIX_TABLE (PREFIX_0FF7) },
2286   /* f8 */
2287   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2288   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2289   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2290   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2291   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2292   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2293   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2294   { "ud0S",             { Gv, Ev }, 0 },
2295 };
2296
2297 static const unsigned char onebyte_has_modrm[256] = {
2298   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2299   /*       -------------------------------        */
2300   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2301   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2302   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2303   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2304   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2305   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2306   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2307   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2308   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2309   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2310   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2311   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2312   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2313   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2314   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2315   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2316   /*       -------------------------------        */
2317   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2318 };
2319
2320 static const unsigned char twobyte_has_modrm[256] = {
2321   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2322   /*       -------------------------------        */
2323   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2324   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2325   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2326   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2327   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2328   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2329   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2330   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2331   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2332   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2333   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2334   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2335   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2336   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2337   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2338   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2339   /*       -------------------------------        */
2340   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2341 };
2342
2343 static char obuf[100];
2344 static char *obufp;
2345 static char *mnemonicendp;
2346 static char scratchbuf[100];
2347 static unsigned char *start_codep;
2348 static unsigned char *insn_codep;
2349 static unsigned char *codep;
2350 static unsigned char *end_codep;
2351 static int last_lock_prefix;
2352 static int last_repz_prefix;
2353 static int last_repnz_prefix;
2354 static int last_data_prefix;
2355 static int last_addr_prefix;
2356 static int last_rex_prefix;
2357 static int last_seg_prefix;
2358 static int fwait_prefix;
2359 /* The active segment register prefix.  */
2360 static int active_seg_prefix;
2361 #define MAX_CODE_LENGTH 15
2362 /* We can up to 14 prefixes since the maximum instruction length is
2363    15bytes.  */
2364 static int all_prefixes[MAX_CODE_LENGTH - 1];
2365 static disassemble_info *the_info;
2366 static struct
2367   {
2368     int mod;
2369     int reg;
2370     int rm;
2371   }
2372 modrm;
2373 static unsigned char need_modrm;
2374 static struct
2375   {
2376     int scale;
2377     int index;
2378     int base;
2379   }
2380 sib;
2381 static struct
2382   {
2383     int register_specifier;
2384     int length;
2385     int prefix;
2386     int w;
2387     int evex;
2388     int r;
2389     int v;
2390     int mask_register_specifier;
2391     int zeroing;
2392     int ll;
2393     int b;
2394   }
2395 vex;
2396 static unsigned char need_vex;
2397
2398 struct op
2399   {
2400     const char *name;
2401     unsigned int len;
2402   };
2403
2404 /* If we are accessing mod/rm/reg without need_modrm set, then the
2405    values are stale.  Hitting this abort likely indicates that you
2406    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2407 #define MODRM_CHECK  if (!need_modrm) abort ()
2408
2409 static const char **names64;
2410 static const char **names32;
2411 static const char **names16;
2412 static const char **names8;
2413 static const char **names8rex;
2414 static const char **names_seg;
2415 static const char *index64;
2416 static const char *index32;
2417 static const char **index16;
2418 static const char **names_bnd;
2419
2420 static const char *intel_names64[] = {
2421   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2422   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2423 };
2424 static const char *intel_names32[] = {
2425   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2426   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2427 };
2428 static const char *intel_names16[] = {
2429   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2430   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2431 };
2432 static const char *intel_names8[] = {
2433   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2434 };
2435 static const char *intel_names8rex[] = {
2436   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2437   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2438 };
2439 static const char *intel_names_seg[] = {
2440   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2441 };
2442 static const char *intel_index64 = "riz";
2443 static const char *intel_index32 = "eiz";
2444 static const char *intel_index16[] = {
2445   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2446 };
2447
2448 static const char *att_names64[] = {
2449   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2450   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2451 };
2452 static const char *att_names32[] = {
2453   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2454   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2455 };
2456 static const char *att_names16[] = {
2457   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2458   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2459 };
2460 static const char *att_names8[] = {
2461   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2462 };
2463 static const char *att_names8rex[] = {
2464   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2465   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2466 };
2467 static const char *att_names_seg[] = {
2468   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2469 };
2470 static const char *att_index64 = "%riz";
2471 static const char *att_index32 = "%eiz";
2472 static const char *att_index16[] = {
2473   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2474 };
2475
2476 static const char **names_mm;
2477 static const char *intel_names_mm[] = {
2478   "mm0", "mm1", "mm2", "mm3",
2479   "mm4", "mm5", "mm6", "mm7"
2480 };
2481 static const char *att_names_mm[] = {
2482   "%mm0", "%mm1", "%mm2", "%mm3",
2483   "%mm4", "%mm5", "%mm6", "%mm7"
2484 };
2485
2486 static const char *intel_names_bnd[] = {
2487   "bnd0", "bnd1", "bnd2", "bnd3"
2488 };
2489
2490 static const char *att_names_bnd[] = {
2491   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2492 };
2493
2494 static const char **names_xmm;
2495 static const char *intel_names_xmm[] = {
2496   "xmm0", "xmm1", "xmm2", "xmm3",
2497   "xmm4", "xmm5", "xmm6", "xmm7",
2498   "xmm8", "xmm9", "xmm10", "xmm11",
2499   "xmm12", "xmm13", "xmm14", "xmm15",
2500   "xmm16", "xmm17", "xmm18", "xmm19",
2501   "xmm20", "xmm21", "xmm22", "xmm23",
2502   "xmm24", "xmm25", "xmm26", "xmm27",
2503   "xmm28", "xmm29", "xmm30", "xmm31"
2504 };
2505 static const char *att_names_xmm[] = {
2506   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2507   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2508   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2509   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2510   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2511   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2512   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2513   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2514 };
2515
2516 static const char **names_ymm;
2517 static const char *intel_names_ymm[] = {
2518   "ymm0", "ymm1", "ymm2", "ymm3",
2519   "ymm4", "ymm5", "ymm6", "ymm7",
2520   "ymm8", "ymm9", "ymm10", "ymm11",
2521   "ymm12", "ymm13", "ymm14", "ymm15",
2522   "ymm16", "ymm17", "ymm18", "ymm19",
2523   "ymm20", "ymm21", "ymm22", "ymm23",
2524   "ymm24", "ymm25", "ymm26", "ymm27",
2525   "ymm28", "ymm29", "ymm30", "ymm31"
2526 };
2527 static const char *att_names_ymm[] = {
2528   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2529   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2530   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2531   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2532   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2533   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2534   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2535   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2536 };
2537
2538 static const char **names_zmm;
2539 static const char *intel_names_zmm[] = {
2540   "zmm0", "zmm1", "zmm2", "zmm3",
2541   "zmm4", "zmm5", "zmm6", "zmm7",
2542   "zmm8", "zmm9", "zmm10", "zmm11",
2543   "zmm12", "zmm13", "zmm14", "zmm15",
2544   "zmm16", "zmm17", "zmm18", "zmm19",
2545   "zmm20", "zmm21", "zmm22", "zmm23",
2546   "zmm24", "zmm25", "zmm26", "zmm27",
2547   "zmm28", "zmm29", "zmm30", "zmm31"
2548 };
2549 static const char *att_names_zmm[] = {
2550   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2551   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2552   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2553   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2554   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2555   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2556   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2557   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2558 };
2559
2560 static const char **names_tmm;
2561 static const char *intel_names_tmm[] = {
2562   "tmm0", "tmm1", "tmm2", "tmm3",
2563   "tmm4", "tmm5", "tmm6", "tmm7"
2564 };
2565 static const char *att_names_tmm[] = {
2566   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2567   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2568 };
2569
2570 static const char **names_mask;
2571 static const char *intel_names_mask[] = {
2572   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2573 };
2574 static const char *att_names_mask[] = {
2575   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2576 };
2577
2578 static const char *names_rounding[] =
2579 {
2580   "{rn-sae}",
2581   "{rd-sae}",
2582   "{ru-sae}",
2583   "{rz-sae}"
2584 };
2585
2586 static const struct dis386 reg_table[][8] = {
2587   /* REG_80 */
2588   {
2589     { "addA",   { Ebh1, Ib }, 0 },
2590     { "orA",    { Ebh1, Ib }, 0 },
2591     { "adcA",   { Ebh1, Ib }, 0 },
2592     { "sbbA",   { Ebh1, Ib }, 0 },
2593     { "andA",   { Ebh1, Ib }, 0 },
2594     { "subA",   { Ebh1, Ib }, 0 },
2595     { "xorA",   { Ebh1, Ib }, 0 },
2596     { "cmpA",   { Eb, Ib }, 0 },
2597   },
2598   /* REG_81 */
2599   {
2600     { "addQ",   { Evh1, Iv }, 0 },
2601     { "orQ",    { Evh1, Iv }, 0 },
2602     { "adcQ",   { Evh1, Iv }, 0 },
2603     { "sbbQ",   { Evh1, Iv }, 0 },
2604     { "andQ",   { Evh1, Iv }, 0 },
2605     { "subQ",   { Evh1, Iv }, 0 },
2606     { "xorQ",   { Evh1, Iv }, 0 },
2607     { "cmpQ",   { Ev, Iv }, 0 },
2608   },
2609   /* REG_83 */
2610   {
2611     { "addQ",   { Evh1, sIb }, 0 },
2612     { "orQ",    { Evh1, sIb }, 0 },
2613     { "adcQ",   { Evh1, sIb }, 0 },
2614     { "sbbQ",   { Evh1, sIb }, 0 },
2615     { "andQ",   { Evh1, sIb }, 0 },
2616     { "subQ",   { Evh1, sIb }, 0 },
2617     { "xorQ",   { Evh1, sIb }, 0 },
2618     { "cmpQ",   { Ev, sIb }, 0 },
2619   },
2620   /* REG_8F */
2621   {
2622     { "pop{P|}", { stackEv }, 0 },
2623     { XOP_8F_TABLE (XOP_09) },
2624     { Bad_Opcode },
2625     { Bad_Opcode },
2626     { Bad_Opcode },
2627     { XOP_8F_TABLE (XOP_09) },
2628   },
2629   /* REG_C0 */
2630   {
2631     { "rolA",   { Eb, Ib }, 0 },
2632     { "rorA",   { Eb, Ib }, 0 },
2633     { "rclA",   { Eb, Ib }, 0 },
2634     { "rcrA",   { Eb, Ib }, 0 },
2635     { "shlA",   { Eb, Ib }, 0 },
2636     { "shrA",   { Eb, Ib }, 0 },
2637     { "shlA",   { Eb, Ib }, 0 },
2638     { "sarA",   { Eb, Ib }, 0 },
2639   },
2640   /* REG_C1 */
2641   {
2642     { "rolQ",   { Ev, Ib }, 0 },
2643     { "rorQ",   { Ev, Ib }, 0 },
2644     { "rclQ",   { Ev, Ib }, 0 },
2645     { "rcrQ",   { Ev, Ib }, 0 },
2646     { "shlQ",   { Ev, Ib }, 0 },
2647     { "shrQ",   { Ev, Ib }, 0 },
2648     { "shlQ",   { Ev, Ib }, 0 },
2649     { "sarQ",   { Ev, Ib }, 0 },
2650   },
2651   /* REG_C6 */
2652   {
2653     { "movA",   { Ebh3, Ib }, 0 },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { Bad_Opcode },
2657     { Bad_Opcode },
2658     { Bad_Opcode },
2659     { Bad_Opcode },
2660     { MOD_TABLE (MOD_C6_REG_7) },
2661   },
2662   /* REG_C7 */
2663   {
2664     { "movQ",   { Evh3, Iv }, 0 },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { Bad_Opcode },
2670     { Bad_Opcode },
2671     { MOD_TABLE (MOD_C7_REG_7) },
2672   },
2673   /* REG_D0 */
2674   {
2675     { "rolA",   { Eb, I1 }, 0 },
2676     { "rorA",   { Eb, I1 }, 0 },
2677     { "rclA",   { Eb, I1 }, 0 },
2678     { "rcrA",   { Eb, I1 }, 0 },
2679     { "shlA",   { Eb, I1 }, 0 },
2680     { "shrA",   { Eb, I1 }, 0 },
2681     { "shlA",   { Eb, I1 }, 0 },
2682     { "sarA",   { Eb, I1 }, 0 },
2683   },
2684   /* REG_D1 */
2685   {
2686     { "rolQ",   { Ev, I1 }, 0 },
2687     { "rorQ",   { Ev, I1 }, 0 },
2688     { "rclQ",   { Ev, I1 }, 0 },
2689     { "rcrQ",   { Ev, I1 }, 0 },
2690     { "shlQ",   { Ev, I1 }, 0 },
2691     { "shrQ",   { Ev, I1 }, 0 },
2692     { "shlQ",   { Ev, I1 }, 0 },
2693     { "sarQ",   { Ev, I1 }, 0 },
2694   },
2695   /* REG_D2 */
2696   {
2697     { "rolA",   { Eb, CL }, 0 },
2698     { "rorA",   { Eb, CL }, 0 },
2699     { "rclA",   { Eb, CL }, 0 },
2700     { "rcrA",   { Eb, CL }, 0 },
2701     { "shlA",   { Eb, CL }, 0 },
2702     { "shrA",   { Eb, CL }, 0 },
2703     { "shlA",   { Eb, CL }, 0 },
2704     { "sarA",   { Eb, CL }, 0 },
2705   },
2706   /* REG_D3 */
2707   {
2708     { "rolQ",   { Ev, CL }, 0 },
2709     { "rorQ",   { Ev, CL }, 0 },
2710     { "rclQ",   { Ev, CL }, 0 },
2711     { "rcrQ",   { Ev, CL }, 0 },
2712     { "shlQ",   { Ev, CL }, 0 },
2713     { "shrQ",   { Ev, CL }, 0 },
2714     { "shlQ",   { Ev, CL }, 0 },
2715     { "sarQ",   { Ev, CL }, 0 },
2716   },
2717   /* REG_F6 */
2718   {
2719     { "testA",  { Eb, Ib }, 0 },
2720     { "testA",  { Eb, Ib }, 0 },
2721     { "notA",   { Ebh1 }, 0 },
2722     { "negA",   { Ebh1 }, 0 },
2723     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2724     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2725     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2726     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2727   },
2728   /* REG_F7 */
2729   {
2730     { "testQ",  { Ev, Iv }, 0 },
2731     { "testQ",  { Ev, Iv }, 0 },
2732     { "notQ",   { Evh1 }, 0 },
2733     { "negQ",   { Evh1 }, 0 },
2734     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2735     { "imulQ",  { Ev }, 0 },
2736     { "divQ",   { Ev }, 0 },
2737     { "idivQ",  { Ev }, 0 },
2738   },
2739   /* REG_FE */
2740   {
2741     { "incA",   { Ebh1 }, 0 },
2742     { "decA",   { Ebh1 }, 0 },
2743   },
2744   /* REG_FF */
2745   {
2746     { "incQ",   { Evh1 }, 0 },
2747     { "decQ",   { Evh1 }, 0 },
2748     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2749     { MOD_TABLE (MOD_FF_REG_3) },
2750     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2751     { MOD_TABLE (MOD_FF_REG_5) },
2752     { "push{P|}", { stackEv }, 0 },
2753     { Bad_Opcode },
2754   },
2755   /* REG_0F00 */
2756   {
2757     { "sldtD",  { Sv }, 0 },
2758     { "strD",   { Sv }, 0 },
2759     { "lldt",   { Ew }, 0 },
2760     { "ltr",    { Ew }, 0 },
2761     { "verr",   { Ew }, 0 },
2762     { "verw",   { Ew }, 0 },
2763     { Bad_Opcode },
2764     { Bad_Opcode },
2765   },
2766   /* REG_0F01 */
2767   {
2768     { MOD_TABLE (MOD_0F01_REG_0) },
2769     { MOD_TABLE (MOD_0F01_REG_1) },
2770     { MOD_TABLE (MOD_0F01_REG_2) },
2771     { MOD_TABLE (MOD_0F01_REG_3) },
2772     { "smswD",  { Sv }, 0 },
2773     { MOD_TABLE (MOD_0F01_REG_5) },
2774     { "lmsw",   { Ew }, 0 },
2775     { MOD_TABLE (MOD_0F01_REG_7) },
2776   },
2777   /* REG_0F0D */
2778   {
2779     { "prefetch",       { Mb }, 0 },
2780     { "prefetchw",      { Mb }, 0 },
2781     { "prefetchwt1",    { Mb }, 0 },
2782     { "prefetch",       { Mb }, 0 },
2783     { "prefetch",       { Mb }, 0 },
2784     { "prefetch",       { Mb }, 0 },
2785     { "prefetch",       { Mb }, 0 },
2786     { "prefetch",       { Mb }, 0 },
2787   },
2788   /* REG_0F18 */
2789   {
2790     { MOD_TABLE (MOD_0F18_REG_0) },
2791     { MOD_TABLE (MOD_0F18_REG_1) },
2792     { MOD_TABLE (MOD_0F18_REG_2) },
2793     { MOD_TABLE (MOD_0F18_REG_3) },
2794     { "nopQ",           { Ev }, 0 },
2795     { "nopQ",           { Ev }, 0 },
2796     { "nopQ",           { Ev }, 0 },
2797     { "nopQ",           { Ev }, 0 },
2798   },
2799   /* REG_0F1C_P_0_MOD_0 */
2800   {
2801     { "cldemote",       { Mb }, 0 },
2802     { "nopQ",           { Ev }, 0 },
2803     { "nopQ",           { Ev }, 0 },
2804     { "nopQ",           { Ev }, 0 },
2805     { "nopQ",           { Ev }, 0 },
2806     { "nopQ",           { Ev }, 0 },
2807     { "nopQ",           { Ev }, 0 },
2808     { "nopQ",           { Ev }, 0 },
2809   },
2810   /* REG_0F1E_P_1_MOD_3 */
2811   {
2812     { "nopQ",           { Ev }, PREFIX_IGNORED },
2813     { "rdsspK",         { Edq }, 0 },
2814     { "nopQ",           { Ev }, PREFIX_IGNORED },
2815     { "nopQ",           { Ev }, PREFIX_IGNORED },
2816     { "nopQ",           { Ev }, PREFIX_IGNORED },
2817     { "nopQ",           { Ev }, PREFIX_IGNORED },
2818     { "nopQ",           { Ev }, PREFIX_IGNORED },
2819     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2820   },
2821   /* REG_0F38D8_PREFIX_1 */
2822   {
2823     { "aesencwide128kl",        { M }, 0 },
2824     { "aesdecwide128kl",        { M }, 0 },
2825     { "aesencwide256kl",        { M }, 0 },
2826     { "aesdecwide256kl",        { M }, 0 },
2827   },
2828   /* REG_0F3A0F_PREFIX_1_MOD_3 */
2829   {
2830     { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2831   },
2832   /* REG_0F71_MOD_0 */
2833   {
2834     { Bad_Opcode },
2835     { Bad_Opcode },
2836     { "psrlw",          { MS, Ib }, PREFIX_OPCODE },
2837     { Bad_Opcode },
2838     { "psraw",          { MS, Ib }, PREFIX_OPCODE },
2839     { Bad_Opcode },
2840     { "psllw",          { MS, Ib }, PREFIX_OPCODE },
2841   },
2842   /* REG_0F72_MOD_0 */
2843   {
2844     { Bad_Opcode },
2845     { Bad_Opcode },
2846     { "psrld",          { MS, Ib }, PREFIX_OPCODE },
2847     { Bad_Opcode },
2848     { "psrad",          { MS, Ib }, PREFIX_OPCODE },
2849     { Bad_Opcode },
2850     { "pslld",          { MS, Ib }, PREFIX_OPCODE },
2851   },
2852   /* REG_0F73_MOD_0 */
2853   {
2854     { Bad_Opcode },
2855     { Bad_Opcode },
2856     { "psrlq",          { MS, Ib }, PREFIX_OPCODE },
2857     { "psrldq",         { XS, Ib }, PREFIX_DATA },
2858     { Bad_Opcode },
2859     { Bad_Opcode },
2860     { "psllq",          { MS, Ib }, PREFIX_OPCODE },
2861     { "pslldq",         { XS, Ib }, PREFIX_DATA },
2862   },
2863   /* REG_0FA6 */
2864   {
2865     { "montmul",        { { OP_0f07, 0 } }, 0 },
2866     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2867     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2868   },
2869   /* REG_0FA7 */
2870   {
2871     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2872     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2873     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2874     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2875     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2876     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2877   },
2878   /* REG_0FAE */
2879   {
2880     { MOD_TABLE (MOD_0FAE_REG_0) },
2881     { MOD_TABLE (MOD_0FAE_REG_1) },
2882     { MOD_TABLE (MOD_0FAE_REG_2) },
2883     { MOD_TABLE (MOD_0FAE_REG_3) },
2884     { MOD_TABLE (MOD_0FAE_REG_4) },
2885     { MOD_TABLE (MOD_0FAE_REG_5) },
2886     { MOD_TABLE (MOD_0FAE_REG_6) },
2887     { MOD_TABLE (MOD_0FAE_REG_7) },
2888   },
2889   /* REG_0FBA */
2890   {
2891     { Bad_Opcode },
2892     { Bad_Opcode },
2893     { Bad_Opcode },
2894     { Bad_Opcode },
2895     { "btQ",    { Ev, Ib }, 0 },
2896     { "btsQ",   { Evh1, Ib }, 0 },
2897     { "btrQ",   { Evh1, Ib }, 0 },
2898     { "btcQ",   { Evh1, Ib }, 0 },
2899   },
2900   /* REG_0FC7 */
2901   {
2902     { Bad_Opcode },
2903     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2904     { Bad_Opcode },
2905     { MOD_TABLE (MOD_0FC7_REG_3) },
2906     { MOD_TABLE (MOD_0FC7_REG_4) },
2907     { MOD_TABLE (MOD_0FC7_REG_5) },
2908     { MOD_TABLE (MOD_0FC7_REG_6) },
2909     { MOD_TABLE (MOD_0FC7_REG_7) },
2910   },
2911   /* REG_VEX_0F71_M_0 */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "vpsrlw",         { Vex, XS, Ib }, PREFIX_DATA },
2916     { Bad_Opcode },
2917     { "vpsraw",         { Vex, XS, Ib }, PREFIX_DATA },
2918     { Bad_Opcode },
2919     { "vpsllw",         { Vex, XS, Ib }, PREFIX_DATA },
2920   },
2921   /* REG_VEX_0F72_M_0 */
2922   {
2923     { Bad_Opcode },
2924     { Bad_Opcode },
2925     { "vpsrld",         { Vex, XS, Ib }, PREFIX_DATA },
2926     { Bad_Opcode },
2927     { "vpsrad",         { Vex, XS, Ib }, PREFIX_DATA },
2928     { Bad_Opcode },
2929     { "vpslld",         { Vex, XS, Ib }, PREFIX_DATA },
2930   },
2931   /* REG_VEX_0F73_M_0 */
2932   {
2933     { Bad_Opcode },
2934     { Bad_Opcode },
2935     { "vpsrlq",         { Vex, XS, Ib }, PREFIX_DATA },
2936     { "vpsrldq",        { Vex, XS, Ib }, PREFIX_DATA },
2937     { Bad_Opcode },
2938     { Bad_Opcode },
2939     { "vpsllq",         { Vex, XS, Ib }, PREFIX_DATA },
2940     { "vpslldq",        { Vex, XS, Ib }, PREFIX_DATA },
2941   },
2942   /* REG_VEX_0FAE */
2943   {
2944     { Bad_Opcode },
2945     { Bad_Opcode },
2946     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2947     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2948   },
2949   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2950   {
2951     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2952   },
2953   /* REG_VEX_0F38F3_L_0 */
2954   {
2955     { Bad_Opcode },
2956     { "blsrS",          { VexGdq, Edq }, PREFIX_OPCODE },
2957     { "blsmskS",        { VexGdq, Edq }, PREFIX_OPCODE },
2958     { "blsiS",          { VexGdq, Edq }, PREFIX_OPCODE },
2959   },
2960   /* REG_0FXOP_09_01_L_0 */
2961   {
2962     { Bad_Opcode },
2963     { "blcfill",        { VexGdq, Edq }, 0 },
2964     { "blsfill",        { VexGdq, Edq }, 0 },
2965     { "blcs",   { VexGdq, Edq }, 0 },
2966     { "tzmsk",  { VexGdq, Edq }, 0 },
2967     { "blcic",  { VexGdq, Edq }, 0 },
2968     { "blsic",  { VexGdq, Edq }, 0 },
2969     { "t1mskc", { VexGdq, Edq }, 0 },
2970   },
2971   /* REG_0FXOP_09_02_L_0 */
2972   {
2973     { Bad_Opcode },
2974     { "blcmsk", { VexGdq, Edq }, 0 },
2975     { Bad_Opcode },
2976     { Bad_Opcode },
2977     { Bad_Opcode },
2978     { Bad_Opcode },
2979     { "blci",   { VexGdq, Edq }, 0 },
2980   },
2981   /* REG_0FXOP_09_12_M_1_L_0 */
2982   {
2983     { "llwpcb", { Edq }, 0 },
2984     { "slwpcb", { Edq }, 0 },
2985   },
2986   /* REG_0FXOP_0A_12_L_0 */
2987   {
2988     { "lwpins", { VexGdq, Ed, Id }, 0 },
2989     { "lwpval", { VexGdq, Ed, Id }, 0 },
2990   },
2991
2992 #include "i386-dis-evex-reg.h"
2993 };
2994
2995 static const struct dis386 prefix_table[][4] = {
2996   /* PREFIX_90 */
2997   {
2998     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
2999     { "pause", { XX }, 0 },
3000     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3001     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3002   },
3003
3004   /* PREFIX_0F01_REG_1_RM_4 */
3005   {
3006     { Bad_Opcode },
3007     { Bad_Opcode },
3008     { "tdcall",         { Skip_MODRM }, 0 },
3009     { Bad_Opcode },
3010   },
3011
3012   /* PREFIX_0F01_REG_1_RM_5 */
3013   {
3014     { Bad_Opcode },
3015     { Bad_Opcode },
3016     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3017     { Bad_Opcode },
3018   },
3019
3020   /* PREFIX_0F01_REG_1_RM_6 */
3021   {
3022     { Bad_Opcode },
3023     { Bad_Opcode },
3024     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3025     { Bad_Opcode },
3026   },
3027
3028   /* PREFIX_0F01_REG_1_RM_7 */
3029   {
3030     { "encls",          { Skip_MODRM }, 0 },
3031     { Bad_Opcode },
3032     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3033     { Bad_Opcode },
3034   },
3035
3036   /* PREFIX_0F01_REG_3_RM_1 */
3037   {
3038     { "vmmcall",        { Skip_MODRM }, 0 },
3039     { "vmgexit",        { Skip_MODRM }, 0 },
3040     { Bad_Opcode },
3041     { "vmgexit",        { Skip_MODRM }, 0 },
3042   },
3043
3044   /* PREFIX_0F01_REG_5_MOD_0 */
3045   {
3046     { Bad_Opcode },
3047     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3048   },
3049
3050   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3051   {
3052     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3053     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3054     { Bad_Opcode },
3055     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3056   },
3057
3058   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3059   {
3060     { Bad_Opcode },
3061     { Bad_Opcode },
3062     { Bad_Opcode },
3063     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3064   },
3065
3066   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3067   {
3068     { Bad_Opcode },
3069     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3070   },
3071
3072   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3073   {
3074     { Bad_Opcode },
3075     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3076   },
3077
3078   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3079   {
3080     { Bad_Opcode },
3081     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3082   },
3083
3084   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3085   {
3086     { "rdpkru", { Skip_MODRM }, 0 },
3087     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3088   },
3089
3090   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3091   {
3092     { "wrpkru", { Skip_MODRM }, 0 },
3093     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3094   },
3095
3096   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3097   {
3098     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3099     { "mcommit",        { Skip_MODRM }, 0 },
3100   },
3101
3102   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3103   {
3104     { "invlpgb",        { Skip_MODRM }, 0 },
3105     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3106     { Bad_Opcode },
3107     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3108   },
3109
3110   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3111   {
3112     { "tlbsync",        { Skip_MODRM }, 0 },
3113     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3114     { Bad_Opcode },
3115     { "pvalidate",      { Skip_MODRM }, 0 },
3116   },
3117
3118   /* PREFIX_0F09 */
3119   {
3120     { "wbinvd",   { XX }, 0 },
3121     { "wbnoinvd", { XX }, 0 },
3122   },
3123
3124   /* PREFIX_0F10 */
3125   {
3126     { "movups", { XM, EXx }, PREFIX_OPCODE },
3127     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3128     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3129     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3130   },
3131
3132   /* PREFIX_0F11 */
3133   {
3134     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3135     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3136     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3137     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3138   },
3139
3140   /* PREFIX_0F12 */
3141   {
3142     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3143     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3144     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3145     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3146   },
3147
3148   /* PREFIX_0F16 */
3149   {
3150     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3151     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3152     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3153   },
3154
3155   /* PREFIX_0F1A */
3156   {
3157     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3158     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3159     { "bndmov", { Gbnd, Ebnd }, 0 },
3160     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3161   },
3162
3163   /* PREFIX_0F1B */
3164   {
3165     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3166     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3167     { "bndmov", { EbndS, Gbnd }, 0 },
3168     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3169   },
3170
3171   /* PREFIX_0F1C */
3172   {
3173     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3174     { "nopQ",   { Ev }, PREFIX_IGNORED },
3175     { "nopQ",   { Ev }, 0 },
3176     { "nopQ",   { Ev }, PREFIX_IGNORED },
3177   },
3178
3179   /* PREFIX_0F1E */
3180   {
3181     { "nopQ",   { Ev }, 0 },
3182     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3183     { "nopQ",   { Ev }, 0 },
3184     { NULL,     { XX }, PREFIX_IGNORED },
3185   },
3186
3187   /* PREFIX_0F2A */
3188   {
3189     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3190     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3191     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3192     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3193   },
3194
3195   /* PREFIX_0F2B */
3196   {
3197     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3198     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3199     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3200     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3201   },
3202
3203   /* PREFIX_0F2C */
3204   {
3205     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3206     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3207     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3208     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3209   },
3210
3211   /* PREFIX_0F2D */
3212   {
3213     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3214     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3215     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3216     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3217   },
3218
3219   /* PREFIX_0F2E */
3220   {
3221     { "ucomiss",{ XM, EXd }, 0 },
3222     { Bad_Opcode },
3223     { "ucomisd",{ XM, EXq }, 0 },
3224   },
3225
3226   /* PREFIX_0F2F */
3227   {
3228     { "comiss", { XM, EXd }, 0 },
3229     { Bad_Opcode },
3230     { "comisd", { XM, EXq }, 0 },
3231   },
3232
3233   /* PREFIX_0F51 */
3234   {
3235     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3236     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3237     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3238     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3239   },
3240
3241   /* PREFIX_0F52 */
3242   {
3243     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3244     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3245   },
3246
3247   /* PREFIX_0F53 */
3248   {
3249     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3250     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3251   },
3252
3253   /* PREFIX_0F58 */
3254   {
3255     { "addps", { XM, EXx }, PREFIX_OPCODE },
3256     { "addss", { XM, EXd }, PREFIX_OPCODE },
3257     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3258     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3259   },
3260
3261   /* PREFIX_0F59 */
3262   {
3263     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3264     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3265     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3266     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3267   },
3268
3269   /* PREFIX_0F5A */
3270   {
3271     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3272     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3273     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3274     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3275   },
3276
3277   /* PREFIX_0F5B */
3278   {
3279     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3280     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3281     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3282   },
3283
3284   /* PREFIX_0F5C */
3285   {
3286     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3287     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3288     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3289     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3290   },
3291
3292   /* PREFIX_0F5D */
3293   {
3294     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3295     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3296     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3297     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3298   },
3299
3300   /* PREFIX_0F5E */
3301   {
3302     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3303     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3304     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3305     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3306   },
3307
3308   /* PREFIX_0F5F */
3309   {
3310     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3311     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3312     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3313     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3314   },
3315
3316   /* PREFIX_0F60 */
3317   {
3318     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3319     { Bad_Opcode },
3320     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3321   },
3322
3323   /* PREFIX_0F61 */
3324   {
3325     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3326     { Bad_Opcode },
3327     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3328   },
3329
3330   /* PREFIX_0F62 */
3331   {
3332     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3333     { Bad_Opcode },
3334     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3335   },
3336
3337   /* PREFIX_0F6F */
3338   {
3339     { "movq",   { MX, EM }, PREFIX_OPCODE },
3340     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3341     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3342   },
3343
3344   /* PREFIX_0F70 */
3345   {
3346     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3347     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3348     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3349     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3350   },
3351
3352   /* PREFIX_0F78 */
3353   {
3354     {"vmread",  { Em, Gm }, 0 },
3355     { Bad_Opcode },
3356     {"extrq",   { XS, Ib, Ib }, 0 },
3357     {"insertq", { XM, XS, Ib, Ib }, 0 },
3358   },
3359
3360   /* PREFIX_0F79 */
3361   {
3362     {"vmwrite", { Gm, Em }, 0 },
3363     { Bad_Opcode },
3364     {"extrq",   { XM, XS }, 0 },
3365     {"insertq", { XM, XS }, 0 },
3366   },
3367
3368   /* PREFIX_0F7C */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3373     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3374   },
3375
3376   /* PREFIX_0F7D */
3377   {
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3381     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3382   },
3383
3384   /* PREFIX_0F7E */
3385   {
3386     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3387     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3388     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3389   },
3390
3391   /* PREFIX_0F7F */
3392   {
3393     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3394     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3395     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0FAE_REG_0_MOD_3 */
3399   {
3400     { Bad_Opcode },
3401     { "rdfsbase", { Ev }, 0 },
3402   },
3403
3404   /* PREFIX_0FAE_REG_1_MOD_3 */
3405   {
3406     { Bad_Opcode },
3407     { "rdgsbase", { Ev }, 0 },
3408   },
3409
3410   /* PREFIX_0FAE_REG_2_MOD_3 */
3411   {
3412     { Bad_Opcode },
3413     { "wrfsbase", { Ev }, 0 },
3414   },
3415
3416   /* PREFIX_0FAE_REG_3_MOD_3 */
3417   {
3418     { Bad_Opcode },
3419     { "wrgsbase", { Ev }, 0 },
3420   },
3421
3422   /* PREFIX_0FAE_REG_4_MOD_0 */
3423   {
3424     { "xsave",  { FXSAVE }, 0 },
3425     { "ptwrite{%LQ|}", { Edq }, 0 },
3426   },
3427
3428   /* PREFIX_0FAE_REG_4_MOD_3 */
3429   {
3430     { Bad_Opcode },
3431     { "ptwrite{%LQ|}", { Edq }, 0 },
3432   },
3433
3434   /* PREFIX_0FAE_REG_5_MOD_3 */
3435   {
3436     { "lfence",         { Skip_MODRM }, 0 },
3437     { "incsspK",        { Edq }, PREFIX_OPCODE },
3438   },
3439
3440   /* PREFIX_0FAE_REG_6_MOD_0 */
3441   {
3442     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3443     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3444     { "clwb",   { Mb }, PREFIX_OPCODE },
3445   },
3446
3447   /* PREFIX_0FAE_REG_6_MOD_3 */
3448   {
3449     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3450     { "umonitor",       { Eva }, PREFIX_OPCODE },
3451     { "tpause", { Edq }, PREFIX_OPCODE },
3452     { "umwait", { Edq }, PREFIX_OPCODE },
3453   },
3454
3455   /* PREFIX_0FAE_REG_7_MOD_0 */
3456   {
3457     { "clflush",        { Mb }, 0 },
3458     { Bad_Opcode },
3459     { "clflushopt",     { Mb }, 0 },
3460   },
3461
3462   /* PREFIX_0FB8 */
3463   {
3464     { Bad_Opcode },
3465     { "popcntS", { Gv, Ev }, 0 },
3466   },
3467
3468   /* PREFIX_0FBC */
3469   {
3470     { "bsfS",   { Gv, Ev }, 0 },
3471     { "tzcntS", { Gv, Ev }, 0 },
3472     { "bsfS",   { Gv, Ev }, 0 },
3473   },
3474
3475   /* PREFIX_0FBD */
3476   {
3477     { "bsrS",   { Gv, Ev }, 0 },
3478     { "lzcntS", { Gv, Ev }, 0 },
3479     { "bsrS",   { Gv, Ev }, 0 },
3480   },
3481
3482   /* PREFIX_0FC2 */
3483   {
3484     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
3485     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
3486     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
3487     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
3488   },
3489
3490   /* PREFIX_0FC7_REG_6_MOD_0 */
3491   {
3492     { "vmptrld",{ Mq }, 0 },
3493     { "vmxon",  { Mq }, 0 },
3494     { "vmclear",{ Mq }, 0 },
3495   },
3496
3497   /* PREFIX_0FC7_REG_6_MOD_3 */
3498   {
3499     { "rdrand", { Ev }, 0 },
3500     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3501     { "rdrand", { Ev }, 0 }
3502   },
3503
3504   /* PREFIX_0FC7_REG_7_MOD_3 */
3505   {
3506     { "rdseed", { Ev }, 0 },
3507     { "rdpid",  { Em }, 0 },
3508     { "rdseed", { Ev }, 0 },
3509   },
3510
3511   /* PREFIX_0FD0 */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { "addsubpd", { XM, EXx }, 0 },
3516     { "addsubps", { XM, EXx }, 0 },
3517   },
3518
3519   /* PREFIX_0FD6 */
3520   {
3521     { Bad_Opcode },
3522     { "movq2dq",{ XM, MS }, 0 },
3523     { "movq",   { EXqS, XM }, 0 },
3524     { "movdq2q",{ MX, XS }, 0 },
3525   },
3526
3527   /* PREFIX_0FE6 */
3528   {
3529     { Bad_Opcode },
3530     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3531     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3532     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3533   },
3534
3535   /* PREFIX_0FE7 */
3536   {
3537     { "movntq", { Mq, MX }, PREFIX_OPCODE },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3540   },
3541
3542   /* PREFIX_0FF0 */
3543   {
3544     { Bad_Opcode },
3545     { Bad_Opcode },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3548   },
3549
3550   /* PREFIX_0FF7 */
3551   {
3552     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3553     { Bad_Opcode },
3554     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3555   },
3556
3557   /* PREFIX_0F38D8 */
3558   {
3559     { Bad_Opcode },
3560     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3561   },
3562
3563   /* PREFIX_0F38DC */
3564   {
3565     { Bad_Opcode },
3566     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3567     { "aesenc", { XM, EXx }, 0 },
3568   },
3569
3570   /* PREFIX_0F38DD */
3571   {
3572     { Bad_Opcode },
3573     { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3574     { "aesenclast", { XM, EXx }, 0 },
3575   },
3576
3577   /* PREFIX_0F38DE */
3578   {
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3581     { "aesdec", { XM, EXx }, 0 },
3582   },
3583
3584   /* PREFIX_0F38DF */
3585   {
3586     { Bad_Opcode },
3587     { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3588     { "aesdeclast", { XM, EXx }, 0 },
3589   },
3590
3591   /* PREFIX_0F38F0 */
3592   {
3593     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3594     { Bad_Opcode },
3595     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3596     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3597   },
3598
3599   /* PREFIX_0F38F1 */
3600   {
3601     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3602     { Bad_Opcode },
3603     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3604     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3605   },
3606
3607   /* PREFIX_0F38F6 */
3608   {
3609     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3610     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
3611     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
3612     { Bad_Opcode },
3613   },
3614
3615   /* PREFIX_0F38F8 */
3616   {
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3619     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3620     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3621   },
3622   /* PREFIX_0F38FA */
3623   {
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3626   },
3627
3628   /* PREFIX_0F38FB */
3629   {
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3632   },
3633
3634   /* PREFIX_0F3A0F */
3635   {
3636     { Bad_Opcode },
3637     { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3638   },
3639
3640   /* PREFIX_VEX_0F10 */
3641   {
3642     { "vmovups",        { XM, EXx }, 0 },
3643     { "vmovss",         { XMScalar, VexScalarR, EXxmm_md }, 0 },
3644     { "vmovupd",        { XM, EXx }, 0 },
3645     { "vmovsd",         { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3646   },
3647
3648   /* PREFIX_VEX_0F11 */
3649   {
3650     { "vmovups",        { EXxS, XM }, 0 },
3651     { "vmovss",         { EXdS, VexScalarR, XMScalar }, 0 },
3652     { "vmovupd",        { EXxS, XM }, 0 },
3653     { "vmovsd",         { EXqS, VexScalarR, XMScalar }, 0 },
3654   },
3655
3656   /* PREFIX_VEX_0F12 */
3657   {
3658     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3659     { "vmovsldup",      { XM, EXx }, 0 },
3660     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3661     { "vmovddup",       { XM, EXymmq }, 0 },
3662   },
3663
3664   /* PREFIX_VEX_0F16 */
3665   {
3666     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3667     { "vmovshdup",      { XM, EXx }, 0 },
3668     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3669   },
3670
3671   /* PREFIX_VEX_0F2A */
3672   {
3673     { Bad_Opcode },
3674     { "vcvtsi2ss{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3675     { Bad_Opcode },
3676     { "vcvtsi2sd{%LQ|}",        { XMScalar, VexScalar, Edq }, 0 },
3677   },
3678
3679   /* PREFIX_VEX_0F2C */
3680   {
3681     { Bad_Opcode },
3682     { "vcvttss2si",     { Gdq, EXxmm_md, EXxEVexS }, 0 },
3683     { Bad_Opcode },
3684     { "vcvttsd2si",     { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3685   },
3686
3687   /* PREFIX_VEX_0F2D */
3688   {
3689     { Bad_Opcode },
3690     { "vcvtss2si",      { Gdq, EXxmm_md, EXxEVexR }, 0 },
3691     { Bad_Opcode },
3692     { "vcvtsd2si",      { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3693   },
3694
3695   /* PREFIX_VEX_0F2E */
3696   {
3697     { "vucomisX",       { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3698     { Bad_Opcode },
3699     { "vucomisX",       { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3700   },
3701
3702   /* PREFIX_VEX_0F2F */
3703   {
3704     { "vcomisX",        { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3705     { Bad_Opcode },
3706     { "vcomisX",        { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3707   },
3708
3709   /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3710   {
3711     { "kandw",          { MaskG, MaskVex, MaskE }, 0 },
3712     { Bad_Opcode },
3713     { "kandb",          { MaskG, MaskVex, MaskE }, 0 },
3714   },
3715
3716   /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3717   {
3718     { "kandq",          { MaskG, MaskVex, MaskE }, 0 },
3719     { Bad_Opcode },
3720     { "kandd",          { MaskG, MaskVex, MaskE }, 0 },
3721   },
3722
3723   /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3724   {
3725     { "kandnw",         { MaskG, MaskVex, MaskE }, 0 },
3726     { Bad_Opcode },
3727     { "kandnb",         { MaskG, MaskVex, MaskE }, 0 },
3728   },
3729
3730   /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3731   {
3732     { "kandnq",         { MaskG, MaskVex, MaskE }, 0 },
3733     { Bad_Opcode },
3734     { "kandnd",         { MaskG, MaskVex, MaskE }, 0 },
3735   },
3736
3737   /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3738   {
3739     { "knotw",          { MaskG, MaskE }, 0 },
3740     { Bad_Opcode },
3741     { "knotb",          { MaskG, MaskE }, 0 },
3742   },
3743
3744   /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3745   {
3746     { "knotq",          { MaskG, MaskE }, 0 },
3747     { Bad_Opcode },
3748     { "knotd",          { MaskG, MaskE }, 0 },
3749   },
3750
3751   /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3752   {
3753     { "korw",       { MaskG, MaskVex, MaskE }, 0 },
3754     { Bad_Opcode },
3755     { "korb",       { MaskG, MaskVex, MaskE }, 0 },
3756   },
3757
3758   /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3759   {
3760     { "korq",       { MaskG, MaskVex, MaskE }, 0 },
3761     { Bad_Opcode },
3762     { "kord",       { MaskG, MaskVex, MaskE }, 0 },
3763   },
3764
3765   /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3766   {
3767     { "kxnorw",     { MaskG, MaskVex, MaskE }, 0 },
3768     { Bad_Opcode },
3769     { "kxnorb",     { MaskG, MaskVex, MaskE }, 0 },
3770   },
3771
3772   /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3773   {
3774     { "kxnorq",     { MaskG, MaskVex, MaskE }, 0 },
3775     { Bad_Opcode },
3776     { "kxnord",     { MaskG, MaskVex, MaskE }, 0 },
3777   },
3778
3779   /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3780   {
3781     { "kxorw",      { MaskG, MaskVex, MaskE }, 0 },
3782     { Bad_Opcode },
3783     { "kxorb",      { MaskG, MaskVex, MaskE }, 0 },
3784   },
3785
3786   /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3787   {
3788     { "kxorq",      { MaskG, MaskVex, MaskE }, 0 },
3789     { Bad_Opcode },
3790     { "kxord",      { MaskG, MaskVex, MaskE }, 0 },
3791   },
3792
3793   /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3794   {
3795     { "kaddw",          { MaskG, MaskVex, MaskE }, 0 },
3796     { Bad_Opcode },
3797     { "kaddb",          { MaskG, MaskVex, MaskE }, 0 },
3798   },
3799
3800   /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3801   {
3802     { "kaddq",          { MaskG, MaskVex, MaskE }, 0 },
3803     { Bad_Opcode },
3804     { "kaddd",          { MaskG, MaskVex, MaskE }, 0 },
3805   },
3806
3807   /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3808   {
3809     { "kunpckwd",   { MaskG, MaskVex, MaskE }, 0 },
3810     { Bad_Opcode },
3811     { "kunpckbw",   { MaskG, MaskVex, MaskE }, 0 },
3812   },
3813
3814   /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3815   {
3816     { "kunpckdq",   { MaskG, MaskVex, MaskE }, 0 },
3817   },
3818
3819   /* PREFIX_VEX_0F51 */
3820   {
3821     { "vsqrtps",        { XM, EXx }, 0 },
3822     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
3823     { "vsqrtpd",        { XM, EXx }, 0 },
3824     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
3825   },
3826
3827   /* PREFIX_VEX_0F52 */
3828   {
3829     { "vrsqrtps",       { XM, EXx }, 0 },
3830     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
3831   },
3832
3833   /* PREFIX_VEX_0F53 */
3834   {
3835     { "vrcpps",         { XM, EXx }, 0 },
3836     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3837   },
3838
3839   /* PREFIX_VEX_0F58 */
3840   {
3841     { "vaddps",         { XM, Vex, EXx }, 0 },
3842     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3843     { "vaddpd",         { XM, Vex, EXx }, 0 },
3844     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3845   },
3846
3847   /* PREFIX_VEX_0F59 */
3848   {
3849     { "vmulps",         { XM, Vex, EXx }, 0 },
3850     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3851     { "vmulpd",         { XM, Vex, EXx }, 0 },
3852     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3853   },
3854
3855   /* PREFIX_VEX_0F5A */
3856   {
3857     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
3858     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
3859     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3860     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
3861   },
3862
3863   /* PREFIX_VEX_0F5B */
3864   {
3865     { "vcvtdq2ps",      { XM, EXx }, 0 },
3866     { "vcvttps2dq",     { XM, EXx }, 0 },
3867     { "vcvtps2dq",      { XM, EXx }, 0 },
3868   },
3869
3870   /* PREFIX_VEX_0F5C */
3871   {
3872     { "vsubps",         { XM, Vex, EXx }, 0 },
3873     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3874     { "vsubpd",         { XM, Vex, EXx }, 0 },
3875     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3876   },
3877
3878   /* PREFIX_VEX_0F5D */
3879   {
3880     { "vminps",         { XM, Vex, EXx }, 0 },
3881     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3882     { "vminpd",         { XM, Vex, EXx }, 0 },
3883     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3884   },
3885
3886   /* PREFIX_VEX_0F5E */
3887   {
3888     { "vdivps",         { XM, Vex, EXx }, 0 },
3889     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3890     { "vdivpd",         { XM, Vex, EXx }, 0 },
3891     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3892   },
3893
3894   /* PREFIX_VEX_0F5F */
3895   {
3896     { "vmaxps",         { XM, Vex, EXx }, 0 },
3897     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
3898     { "vmaxpd",         { XM, Vex, EXx }, 0 },
3899     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
3900   },
3901
3902   /* PREFIX_VEX_0F6F */
3903   {
3904     { Bad_Opcode },
3905     { "vmovdqu",        { XM, EXx }, 0 },
3906     { "vmovdqa",        { XM, EXx }, 0 },
3907   },
3908
3909   /* PREFIX_VEX_0F70 */
3910   {
3911     { Bad_Opcode },
3912     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3913     { "vpshufd",        { XM, EXx, Ib }, 0 },
3914     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3915   },
3916
3917   /* PREFIX_VEX_0F7C */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { "vhaddpd",        { XM, Vex, EXx }, 0 },
3922     { "vhaddps",        { XM, Vex, EXx }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F7D */
3926   {
3927     { Bad_Opcode },
3928     { Bad_Opcode },
3929     { "vhsubpd",        { XM, Vex, EXx }, 0 },
3930     { "vhsubps",        { XM, Vex, EXx }, 0 },
3931   },
3932
3933   /* PREFIX_VEX_0F7E */
3934   {
3935     { Bad_Opcode },
3936     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3937     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3938   },
3939
3940   /* PREFIX_VEX_0F7F */
3941   {
3942     { Bad_Opcode },
3943     { "vmovdqu",        { EXxS, XM }, 0 },
3944     { "vmovdqa",        { EXxS, XM }, 0 },
3945   },
3946
3947   /* PREFIX_VEX_0F90_L_0_W_0 */
3948   {
3949     { "kmovw",          { MaskG, MaskE }, 0 },
3950     { Bad_Opcode },
3951     { "kmovb",          { MaskG, MaskBDE }, 0 },
3952   },
3953
3954   /* PREFIX_VEX_0F90_L_0_W_1 */
3955   {
3956     { "kmovq",          { MaskG, MaskE }, 0 },
3957     { Bad_Opcode },
3958     { "kmovd",          { MaskG, MaskBDE }, 0 },
3959   },
3960
3961   /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
3962   {
3963     { "kmovw",          { Ew, MaskG }, 0 },
3964     { Bad_Opcode },
3965     { "kmovb",          { Eb, MaskG }, 0 },
3966   },
3967
3968   /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
3969   {
3970     { "kmovq",          { Eq, MaskG }, 0 },
3971     { Bad_Opcode },
3972     { "kmovd",          { Ed, MaskG }, 0 },
3973   },
3974
3975   /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
3976   {
3977     { "kmovw",          { MaskG, Edq }, 0 },
3978     { Bad_Opcode },
3979     { "kmovb",          { MaskG, Edq }, 0 },
3980     { "kmovd",          { MaskG, Edq }, 0 },
3981   },
3982
3983   /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
3984   {
3985     { Bad_Opcode },
3986     { Bad_Opcode },
3987     { Bad_Opcode },
3988     { "kmovK",          { MaskG, Edq }, 0 },
3989   },
3990
3991   /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
3992   {
3993     { "kmovw",          { Gdq, MaskE }, 0 },
3994     { Bad_Opcode },
3995     { "kmovb",          { Gdq, MaskE }, 0 },
3996     { "kmovd",          { Gdq, MaskE }, 0 },
3997   },
3998
3999   /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { Bad_Opcode },
4004     { "kmovK",          { Gdq, MaskE }, 0 },
4005   },
4006
4007   /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4008   {
4009     { "kortestw", { MaskG, MaskE }, 0 },
4010     { Bad_Opcode },
4011     { "kortestb", { MaskG, MaskE }, 0 },
4012   },
4013
4014   /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4015   {
4016     { "kortestq", { MaskG, MaskE }, 0 },
4017     { Bad_Opcode },
4018     { "kortestd", { MaskG, MaskE }, 0 },
4019   },
4020
4021   /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4022   {
4023     { "ktestw", { MaskG, MaskE }, 0 },
4024     { Bad_Opcode },
4025     { "ktestb", { MaskG, MaskE }, 0 },
4026   },
4027
4028   /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4029   {
4030     { "ktestq", { MaskG, MaskE }, 0 },
4031     { Bad_Opcode },
4032     { "ktestd", { MaskG, MaskE }, 0 },
4033   },
4034
4035   /* PREFIX_VEX_0FC2 */
4036   {
4037     { "vcmpps",         { XM, Vex, EXx, CMP }, 0 },
4038     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4039     { "vcmppd",         { XM, Vex, EXx, CMP }, 0 },
4040     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4041   },
4042
4043   /* PREFIX_VEX_0FD0 */
4044   {
4045     { Bad_Opcode },
4046     { Bad_Opcode },
4047     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
4048     { "vaddsubps",      { XM, Vex, EXx }, 0 },
4049   },
4050
4051   /* PREFIX_VEX_0FE6 */
4052   {
4053     { Bad_Opcode },
4054     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
4055     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
4056     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
4057   },
4058
4059   /* PREFIX_VEX_0FF0 */
4060   {
4061     { Bad_Opcode },
4062     { Bad_Opcode },
4063     { Bad_Opcode },
4064     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4065   },
4066
4067   /* PREFIX_VEX_0F3849_X86_64 */
4068   {
4069     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4070     { Bad_Opcode },
4071     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4072     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4073   },
4074
4075   /* PREFIX_VEX_0F384B_X86_64 */
4076   {
4077     { Bad_Opcode },
4078     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4079     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4080     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4081   },
4082
4083   /* PREFIX_VEX_0F385C_X86_64 */
4084   {
4085     { Bad_Opcode },
4086     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4087     { Bad_Opcode },
4088   },
4089
4090   /* PREFIX_VEX_0F385E_X86_64 */
4091   {
4092     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4093     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4094     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4095     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4096   },
4097
4098   /* PREFIX_VEX_0F38F5_L_0 */
4099   {
4100     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4101     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4102     { Bad_Opcode },
4103     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4104   },
4105
4106   /* PREFIX_VEX_0F38F6_L_0 */
4107   {
4108     { Bad_Opcode },
4109     { Bad_Opcode },
4110     { Bad_Opcode },
4111     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4112   },
4113
4114   /* PREFIX_VEX_0F38F7_L_0 */
4115   {
4116     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4117     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4118     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4119     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4120   },
4121
4122   /* PREFIX_VEX_0F3AF0_L_0 */
4123   {
4124     { Bad_Opcode },
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4128   },
4129
4130 #include "i386-dis-evex-prefix.h"
4131 };
4132
4133 static const struct dis386 x86_64_table[][2] = {
4134   /* X86_64_06 */
4135   {
4136     { "pushP", { es }, 0 },
4137   },
4138
4139   /* X86_64_07 */
4140   {
4141     { "popP", { es }, 0 },
4142   },
4143
4144   /* X86_64_0E */
4145   {
4146     { "pushP", { cs }, 0 },
4147   },
4148
4149   /* X86_64_16 */
4150   {
4151     { "pushP", { ss }, 0 },
4152   },
4153
4154   /* X86_64_17 */
4155   {
4156     { "popP", { ss }, 0 },
4157   },
4158
4159   /* X86_64_1E */
4160   {
4161     { "pushP", { ds }, 0 },
4162   },
4163
4164   /* X86_64_1F */
4165   {
4166     { "popP", { ds }, 0 },
4167   },
4168
4169   /* X86_64_27 */
4170   {
4171     { "daa", { XX }, 0 },
4172   },
4173
4174   /* X86_64_2F */
4175   {
4176     { "das", { XX }, 0 },
4177   },
4178
4179   /* X86_64_37 */
4180   {
4181     { "aaa", { XX }, 0 },
4182   },
4183
4184   /* X86_64_3F */
4185   {
4186     { "aas", { XX }, 0 },
4187   },
4188
4189   /* X86_64_60 */
4190   {
4191     { "pushaP", { XX }, 0 },
4192   },
4193
4194   /* X86_64_61 */
4195   {
4196     { "popaP", { XX }, 0 },
4197   },
4198
4199   /* X86_64_62 */
4200   {
4201     { MOD_TABLE (MOD_62_32BIT) },
4202     { EVEX_TABLE (EVEX_0F) },
4203   },
4204
4205   /* X86_64_63 */
4206   {
4207     { "arpl", { Ew, Gw }, 0 },
4208     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4209   },
4210
4211   /* X86_64_6D */
4212   {
4213     { "ins{R|}", { Yzr, indirDX }, 0 },
4214     { "ins{G|}", { Yzr, indirDX }, 0 },
4215   },
4216
4217   /* X86_64_6F */
4218   {
4219     { "outs{R|}", { indirDXr, Xz }, 0 },
4220     { "outs{G|}", { indirDXr, Xz }, 0 },
4221   },
4222
4223   /* X86_64_82 */
4224   {
4225     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4226     { REG_TABLE (REG_80) },
4227   },
4228
4229   /* X86_64_9A */
4230   {
4231     { "{l|}call{P|}", { Ap }, 0 },
4232   },
4233
4234   /* X86_64_C2 */
4235   {
4236     { "retP",           { Iw, BND }, 0 },
4237     { "ret@",           { Iw, BND }, 0 },
4238   },
4239
4240   /* X86_64_C3 */
4241   {
4242     { "retP",           { BND }, 0 },
4243     { "ret@",           { BND }, 0 },
4244   },
4245
4246   /* X86_64_C4 */
4247   {
4248     { MOD_TABLE (MOD_C4_32BIT) },
4249     { VEX_C4_TABLE (VEX_0F) },
4250   },
4251
4252   /* X86_64_C5 */
4253   {
4254     { MOD_TABLE (MOD_C5_32BIT) },
4255     { VEX_C5_TABLE (VEX_0F) },
4256   },
4257
4258   /* X86_64_CE */
4259   {
4260     { "into", { XX }, 0 },
4261   },
4262
4263   /* X86_64_D4 */
4264   {
4265     { "aam", { Ib }, 0 },
4266   },
4267
4268   /* X86_64_D5 */
4269   {
4270     { "aad", { Ib }, 0 },
4271   },
4272
4273   /* X86_64_E8 */
4274   {
4275     { "callP",          { Jv, BND }, 0 },
4276     { "call@",          { Jv, BND }, 0 }
4277   },
4278
4279   /* X86_64_E9 */
4280   {
4281     { "jmpP",           { Jv, BND }, 0 },
4282     { "jmp@",           { Jv, BND }, 0 }
4283   },
4284
4285   /* X86_64_EA */
4286   {
4287     { "{l|}jmp{P|}", { Ap }, 0 },
4288   },
4289
4290   /* X86_64_0F01_REG_0 */
4291   {
4292     { "sgdt{Q|Q}", { M }, 0 },
4293     { "sgdt", { M }, 0 },
4294   },
4295
4296   /* X86_64_0F01_REG_1 */
4297   {
4298     { "sidt{Q|Q}", { M }, 0 },
4299     { "sidt", { M }, 0 },
4300   },
4301
4302   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4303   {
4304     { Bad_Opcode },
4305     { "seamret",        { Skip_MODRM }, 0 },
4306   },
4307
4308   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4309   {
4310     { Bad_Opcode },
4311     { "seamops",        { Skip_MODRM }, 0 },
4312   },
4313
4314   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4315   {
4316     { Bad_Opcode },
4317     { "seamcall",       { Skip_MODRM }, 0 },
4318   },
4319
4320   /* X86_64_0F01_REG_2 */
4321   {
4322     { "lgdt{Q|Q}", { M }, 0 },
4323     { "lgdt", { M }, 0 },
4324   },
4325
4326   /* X86_64_0F01_REG_3 */
4327   {
4328     { "lidt{Q|Q}", { M }, 0 },
4329     { "lidt", { M }, 0 },
4330   },
4331
4332   {
4333     /* X86_64_0F24 */
4334     { "movZ",           { Em, Td }, 0 },
4335   },
4336
4337   {
4338     /* X86_64_0F26 */
4339     { "movZ",           { Td, Em }, 0 },
4340   },
4341
4342   /* X86_64_VEX_0F3849 */
4343   {
4344     { Bad_Opcode },
4345     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4346   },
4347
4348   /* X86_64_VEX_0F384B */
4349   {
4350     { Bad_Opcode },
4351     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4352   },
4353
4354   /* X86_64_VEX_0F385C */
4355   {
4356     { Bad_Opcode },
4357     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4358   },
4359
4360   /* X86_64_VEX_0F385E */
4361   {
4362     { Bad_Opcode },
4363     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4364   },
4365
4366   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4367   {
4368     { Bad_Opcode },
4369     { "uiret",  { Skip_MODRM }, 0 },
4370   },
4371
4372   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4373   {
4374     { Bad_Opcode },
4375     { "testui", { Skip_MODRM }, 0 },
4376   },
4377
4378   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4379   {
4380     { Bad_Opcode },
4381     { "clui",   { Skip_MODRM }, 0 },
4382   },
4383
4384   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4385   {
4386     { Bad_Opcode },
4387     { "stui",   { Skip_MODRM }, 0 },
4388   },
4389
4390   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4391   {
4392     { Bad_Opcode },
4393     { "rmpadjust",      { Skip_MODRM }, 0 },
4394   },
4395
4396   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4397   {
4398     { Bad_Opcode },
4399     { "rmpupdate",      { Skip_MODRM }, 0 },
4400   },
4401
4402   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4403   {
4404     { Bad_Opcode },
4405     { "psmash", { Skip_MODRM }, 0 },
4406   },
4407
4408   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4409   {
4410     { Bad_Opcode },
4411     { "senduipi",       { Eq }, 0 },
4412   },
4413 };
4414
4415 static const struct dis386 three_byte_table[][256] = {
4416
4417   /* THREE_BYTE_0F38 */
4418   {
4419     /* 00 */
4420     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4421     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4422     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4423     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4424     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4425     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4426     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4427     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4428     /* 08 */
4429     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4430     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4431     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4432     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4433     { Bad_Opcode },
4434     { Bad_Opcode },
4435     { Bad_Opcode },
4436     { Bad_Opcode },
4437     /* 10 */
4438     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4439     { Bad_Opcode },
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4443     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4444     { Bad_Opcode },
4445     { "ptest",  { XM, EXx }, PREFIX_DATA },
4446     /* 18 */
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { Bad_Opcode },
4450     { Bad_Opcode },
4451     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4452     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4453     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4454     { Bad_Opcode },
4455     /* 20 */
4456     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4457     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4458     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4459     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4460     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4461     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4462     { Bad_Opcode },
4463     { Bad_Opcode },
4464     /* 28 */
4465     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4466     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4467     { MOD_TABLE (MOD_0F382A) },
4468     { "packusdw", { XM, EXx }, PREFIX_DATA },
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     /* 30 */
4474     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4475     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4476     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4477     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4478     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4479     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4480     { Bad_Opcode },
4481     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4482     /* 38 */
4483     { "pminsb", { XM, EXx }, PREFIX_DATA },
4484     { "pminsd", { XM, EXx }, PREFIX_DATA },
4485     { "pminuw", { XM, EXx }, PREFIX_DATA },
4486     { "pminud", { XM, EXx }, PREFIX_DATA },
4487     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4488     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4489     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4490     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4491     /* 40 */
4492     { "pmulld", { XM, EXx }, PREFIX_DATA },
4493     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { Bad_Opcode },
4500     /* 48 */
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     /* 50 */
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517     { Bad_Opcode },
4518     /* 58 */
4519     { Bad_Opcode },
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     /* 60 */
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     /* 68 */
4537     { Bad_Opcode },
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     /* 70 */
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     /* 78 */
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { Bad_Opcode },
4563     /* 80 */
4564     { "invept", { Gm, Mo }, PREFIX_DATA },
4565     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4566     { "invpcid", { Gm, M }, PREFIX_DATA },
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     /* 88 */
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { Bad_Opcode },
4581     /* 90 */
4582     { Bad_Opcode },
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     /* 98 */
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     /* a0 */
4600     { Bad_Opcode },
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     /* a8 */
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     /* b0 */
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     /* b8 */
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     /* c0 */
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     /* c8 */
4645     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4646     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4647     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4648     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4649     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4650     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4651     { Bad_Opcode },
4652     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4653     /* d0 */
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     /* d8 */
4663     { PREFIX_TABLE (PREFIX_0F38D8) },
4664     { Bad_Opcode },
4665     { Bad_Opcode },
4666     { "aesimc", { XM, EXx }, PREFIX_DATA },
4667     { PREFIX_TABLE (PREFIX_0F38DC) },
4668     { PREFIX_TABLE (PREFIX_0F38DD) },
4669     { PREFIX_TABLE (PREFIX_0F38DE) },
4670     { PREFIX_TABLE (PREFIX_0F38DF) },
4671     /* e0 */
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     /* e8 */
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     /* f0 */
4690     { PREFIX_TABLE (PREFIX_0F38F0) },
4691     { PREFIX_TABLE (PREFIX_0F38F1) },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { MOD_TABLE (MOD_0F38F5) },
4696     { PREFIX_TABLE (PREFIX_0F38F6) },
4697     { Bad_Opcode },
4698     /* f8 */
4699     { PREFIX_TABLE (PREFIX_0F38F8) },
4700     { MOD_TABLE (MOD_0F38F9) },
4701     { PREFIX_TABLE (PREFIX_0F38FA) },
4702     { PREFIX_TABLE (PREFIX_0F38FB) },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707   },
4708   /* THREE_BYTE_0F3A */
4709   {
4710     /* 00 */
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     /* 08 */
4720     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4721     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4722     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4723     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4724     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4725     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4726     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4727     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4728     /* 10 */
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4734     { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4735     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4736     { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4737     /* 18 */
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     /* 20 */
4747     { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4748     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4749     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4750     { Bad_Opcode },
4751     { Bad_Opcode },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     /* 28 */
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     /* 30 */
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     /* 38 */
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     /* 40 */
4783     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4784     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4785     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4786     { Bad_Opcode },
4787     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     /* 48 */
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     /* 50 */
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     /* 58 */
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     /* 60 */
4819     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4820     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4821     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4822     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     /* 68 */
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { Bad_Opcode },
4834     { Bad_Opcode },
4835     { Bad_Opcode },
4836     /* 70 */
4837     { Bad_Opcode },
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     /* 78 */
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { Bad_Opcode },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     /* 80 */
4855     { Bad_Opcode },
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     /* 88 */
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     /* 90 */
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { Bad_Opcode },
4881     /* 98 */
4882     { Bad_Opcode },
4883     { Bad_Opcode },
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     /* a0 */
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     /* a8 */
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     /* b0 */
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { Bad_Opcode },
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     /* b8 */
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     /* c0 */
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     /* c8 */
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4941     { Bad_Opcode },
4942     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4943     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4944     /* d0 */
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     /* d8 */
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
4962     /* e0 */
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     /* e8 */
4972     { Bad_Opcode },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     /* f0 */
4981     { PREFIX_TABLE (PREFIX_0F3A0F) },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     /* f8 */
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998   },
4999 };
5000
5001 static const struct dis386 xop_table[][256] = {
5002   /* XOP_08 */
5003   {
5004     /* 00 */
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     /* 08 */
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     /* 10 */
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     /* 18 */
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     /* 20 */
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     /* 28 */
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     /* 30 */
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     /* 38 */
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     /* 40 */
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     /* 48 */
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     /* 50 */
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     /* 58 */
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     /* 60 */
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     /* 68 */
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     /* 70 */
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     /* 78 */
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     /* 80 */
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5155     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5156     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5157     /* 88 */
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5165     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5166     /* 90 */
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5173     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5174     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5175     /* 98 */
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5183     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5184     /* a0 */
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5188     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5192     { Bad_Opcode },
5193     /* a8 */
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     /* b0 */
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5210     { Bad_Opcode },
5211     /* b8 */
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     /* c0 */
5221     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5222     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5223     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5224     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     /* c8 */
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5235     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5236     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5237     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5238     /* d0 */
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     /* d8 */
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     /* e0 */
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     /* e8 */
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5271     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5272     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5273     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5274     /* f0 */
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     /* f8 */
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292   },
5293   /* XOP_09 */
5294   {
5295     /* 00 */
5296     { Bad_Opcode },
5297     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5298     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     /* 08 */
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     /* 10 */
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     /* 18 */
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     /* 20 */
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     /* 28 */
5341     { Bad_Opcode },
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     /* 30 */
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     /* 38 */
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     /* 40 */
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { Bad_Opcode },
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     /* 48 */
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     /* 50 */
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     /* 58 */
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     /* 60 */
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     /* 68 */
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     /* 70 */
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     /* 78 */
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     /* 80 */
5440     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5441     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5442     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5443     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     /* 88 */
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     /* 90 */
5458     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5459     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5460     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5461     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5462     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5463     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5464     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5465     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5466     /* 98 */
5467     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5468     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5469     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5470     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* a0 */
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     /* a8 */
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     /* b0 */
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* b8 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     /* c0 */
5512     { Bad_Opcode },
5513     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5514     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5515     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5519     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5520     /* c8 */
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     /* d0 */
5530     { Bad_Opcode },
5531     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5532     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5533     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5537     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5538     /* d8 */
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     /* e0 */
5548     { Bad_Opcode },
5549     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5550     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5551     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     /* e8 */
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     /* f0 */
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     /* f8 */
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583   },
5584   /* XOP_0A */
5585   {
5586     /* 00 */
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     /* 08 */
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     /* 10 */
5605     { "bextrS", { Gdq, Edq, Id }, 0 },
5606     { Bad_Opcode },
5607     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     /* 18 */
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     /* 20 */
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     /* 28 */
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     /* 30 */
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     /* 38 */
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     /* 40 */
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     /* 48 */
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     /* 50 */
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     /* 58 */
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     /* 60 */
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     /* 68 */
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     /* 70 */
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     /* 78 */
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     /* 80 */
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     /* 88 */
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     /* 90 */
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     /* 98 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* a0 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* a8 */
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* b0 */
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* b8 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     /* c0 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* c8 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* d0 */
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     /* d8 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* e0 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* e8 */
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     /* f0 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* f8 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874   },
5875 };
5876
5877 static const struct dis386 vex_table[][256] = {
5878   /* VEX_0F */
5879   {
5880     /* 00 */
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     /* 08 */
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     /* 10 */
5899     { PREFIX_TABLE (PREFIX_VEX_0F10) },
5900     { PREFIX_TABLE (PREFIX_VEX_0F11) },
5901     { PREFIX_TABLE (PREFIX_VEX_0F12) },
5902     { MOD_TABLE (MOD_VEX_0F13) },
5903     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5904     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
5905     { PREFIX_TABLE (PREFIX_VEX_0F16) },
5906     { MOD_TABLE (MOD_VEX_0F17) },
5907     /* 18 */
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     /* 20 */
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     /* 28 */
5926     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
5927     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
5928     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5929     { MOD_TABLE (MOD_VEX_0F2B) },
5930     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5931     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5932     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5933     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5934     /* 30 */
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     /* 38 */
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     /* 40 */
5953     { Bad_Opcode },
5954     { VEX_LEN_TABLE (VEX_LEN_0F41) },
5955     { VEX_LEN_TABLE (VEX_LEN_0F42) },
5956     { Bad_Opcode },
5957     { VEX_LEN_TABLE (VEX_LEN_0F44) },
5958     { VEX_LEN_TABLE (VEX_LEN_0F45) },
5959     { VEX_LEN_TABLE (VEX_LEN_0F46) },
5960     { VEX_LEN_TABLE (VEX_LEN_0F47) },
5961     /* 48 */
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
5965     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     /* 50 */
5971     { MOD_TABLE (MOD_VEX_0F50) },
5972     { PREFIX_TABLE (PREFIX_VEX_0F51) },
5973     { PREFIX_TABLE (PREFIX_VEX_0F52) },
5974     { PREFIX_TABLE (PREFIX_VEX_0F53) },
5975     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5976     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
5977     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
5978     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
5979     /* 58 */
5980     { PREFIX_TABLE (PREFIX_VEX_0F58) },
5981     { PREFIX_TABLE (PREFIX_VEX_0F59) },
5982     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
5983     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
5984     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
5985     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
5986     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
5987     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
5988     /* 60 */
5989     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
5990     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
5991     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
5992     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
5993     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
5994     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
5995     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
5996     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
5997     /* 68 */
5998     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
5999     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6000     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6001     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6002     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6003     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6004     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6005     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6006     /* 70 */
6007     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6008     { MOD_TABLE (MOD_VEX_0F71) },
6009     { MOD_TABLE (MOD_VEX_0F72) },
6010     { MOD_TABLE (MOD_VEX_0F73) },
6011     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6012     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6013     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6014     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6015     /* 78 */
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6021     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6022     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6023     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6024     /* 80 */
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     /* 88 */
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     /* 90 */
6043     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6044     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6045     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6046     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     /* 98 */
6052     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6053     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     /* a0 */
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     /* a8 */
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { REG_TABLE (REG_VEX_0FAE) },
6077     { Bad_Opcode },
6078     /* b0 */
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     /* b8 */
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     /* c0 */
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6100     { Bad_Opcode },
6101     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6102     { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6103     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6104     { Bad_Opcode },
6105     /* c8 */
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     /* d0 */
6115     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6116     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6117     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6118     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6119     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6120     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6121     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6122     { MOD_TABLE (MOD_VEX_0FD7) },
6123     /* d8 */
6124     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6125     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6126     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6127     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6128     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6129     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6130     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6131     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6132     /* e0 */
6133     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6134     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6135     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6136     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6137     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6138     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6139     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6140     { MOD_TABLE (MOD_VEX_0FE7) },
6141     /* e8 */
6142     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6143     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6144     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6145     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6146     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6147     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6148     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6149     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6150     /* f0 */
6151     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6152     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6153     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6154     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6155     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6156     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6157     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6158     { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6159     /* f8 */
6160     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6161     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6162     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6163     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6164     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6165     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6166     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6167     { Bad_Opcode },
6168   },
6169   /* VEX_0F38 */
6170   {
6171     /* 00 */
6172     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6173     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6174     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6175     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6176     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6177     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6179     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6180     /* 08 */
6181     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6182     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6183     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6185     { VEX_W_TABLE (VEX_W_0F380C) },
6186     { VEX_W_TABLE (VEX_W_0F380D) },
6187     { VEX_W_TABLE (VEX_W_0F380E) },
6188     { VEX_W_TABLE (VEX_W_0F380F) },
6189     /* 10 */
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { VEX_W_TABLE (VEX_W_0F3813) },
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6197     { "vptest",         { XM, EXx }, PREFIX_DATA },
6198     /* 18 */
6199     { VEX_W_TABLE (VEX_W_0F3818) },
6200     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6201     { MOD_TABLE (MOD_VEX_0F381A) },
6202     { Bad_Opcode },
6203     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6204     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6205     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6206     { Bad_Opcode },
6207     /* 20 */
6208     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6209     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6210     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6211     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6212     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6213     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     /* 28 */
6217     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6218     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6219     { MOD_TABLE (MOD_VEX_0F382A) },
6220     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6221     { MOD_TABLE (MOD_VEX_0F382C) },
6222     { MOD_TABLE (MOD_VEX_0F382D) },
6223     { MOD_TABLE (MOD_VEX_0F382E) },
6224     { MOD_TABLE (MOD_VEX_0F382F) },
6225     /* 30 */
6226     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6227     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6228     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6229     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6230     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6231     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6232     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6233     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6234     /* 38 */
6235     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6236     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6237     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6238     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6239     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6240     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6241     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6242     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6243     /* 40 */
6244     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6245     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6250     { VEX_W_TABLE (VEX_W_0F3846) },
6251     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6252     /* 48 */
6253     { Bad_Opcode },
6254     { X86_64_TABLE (X86_64_VEX_0F3849) },
6255     { Bad_Opcode },
6256     { X86_64_TABLE (X86_64_VEX_0F384B) },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     /* 50 */
6262     { VEX_W_TABLE (VEX_W_0F3850) },
6263     { VEX_W_TABLE (VEX_W_0F3851) },
6264     { VEX_W_TABLE (VEX_W_0F3852) },
6265     { VEX_W_TABLE (VEX_W_0F3853) },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     /* 58 */
6271     { VEX_W_TABLE (VEX_W_0F3858) },
6272     { VEX_W_TABLE (VEX_W_0F3859) },
6273     { MOD_TABLE (MOD_VEX_0F385A) },
6274     { Bad_Opcode },
6275     { X86_64_TABLE (X86_64_VEX_0F385C) },
6276     { Bad_Opcode },
6277     { X86_64_TABLE (X86_64_VEX_0F385E) },
6278     { Bad_Opcode },
6279     /* 60 */
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     /* 68 */
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     /* 70 */
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     /* 78 */
6307     { VEX_W_TABLE (VEX_W_0F3878) },
6308     { VEX_W_TABLE (VEX_W_0F3879) },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     /* 80 */
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     /* 88 */
6325     { Bad_Opcode },
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { MOD_TABLE (MOD_VEX_0F388C) },
6330     { Bad_Opcode },
6331     { MOD_TABLE (MOD_VEX_0F388E) },
6332     { Bad_Opcode },
6333     /* 90 */
6334     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6335     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6336     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6337     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6341     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6342     /* 98 */
6343     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6345     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6347     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6349     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6351     /* a0 */
6352     { Bad_Opcode },
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6359     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6360     /* a8 */
6361     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6363     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6365     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6366     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6367     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6368     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6369     /* b0 */
6370     { Bad_Opcode },
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6377     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6378     /* b8 */
6379     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6381     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6382     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6383     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6384     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6385     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6386     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6387     /* c0 */
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     /* c8 */
6397     { Bad_Opcode },
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_W_TABLE (VEX_W_0F38CF) },
6405     /* d0 */
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     /* d8 */
6415     { Bad_Opcode },
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6419     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6420     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6421     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6422     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6423     /* e0 */
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     /* e8 */
6433     { Bad_Opcode },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     /* f0 */
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6445     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6448     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6449     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6450     /* f8 */
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { Bad_Opcode },
6459   },
6460   /* VEX_0F3A */
6461   {
6462     /* 00 */
6463     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6465     { VEX_W_TABLE (VEX_W_0F3A02) },
6466     { Bad_Opcode },
6467     { VEX_W_TABLE (VEX_W_0F3A04) },
6468     { VEX_W_TABLE (VEX_W_0F3A05) },
6469     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6470     { Bad_Opcode },
6471     /* 08 */
6472     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6473     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6474     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6475     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6476     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6477     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6478     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6479     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6480     /* 10 */
6481     { Bad_Opcode },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6486     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6487     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6489     /* 18 */
6490     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6491     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_W_TABLE (VEX_W_0F3A1D) },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     /* 20 */
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6501     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     /* 28 */
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     /* 30 */
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6518     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6519     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     /* 38 */
6526     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     /* 40 */
6535     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6536     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6537     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6538     { Bad_Opcode },
6539     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6540     { Bad_Opcode },
6541     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6542     { Bad_Opcode },
6543     /* 48 */
6544     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6545     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6546     { VEX_W_TABLE (VEX_W_0F3A4A) },
6547     { VEX_W_TABLE (VEX_W_0F3A4B) },
6548     { VEX_W_TABLE (VEX_W_0F3A4C) },
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     /* 50 */
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     /* 58 */
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6567     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6568     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6569     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6570     /* 60 */
6571     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6573     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6574     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     /* 68 */
6580     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6581     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6582     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6583     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6584     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6585     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6586     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6587     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6588     /* 70 */
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     /* 78 */
6598     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6599     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6600     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6601     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6602     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6603     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6604     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6605     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6606     /* 80 */
6607     { Bad_Opcode },
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     /* 88 */
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     /* 90 */
6625     { Bad_Opcode },
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     /* 98 */
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     /* a0 */
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     /* a8 */
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     /* b0 */
6661     { Bad_Opcode },
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     /* b8 */
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     /* c0 */
6679     { Bad_Opcode },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     /* c8 */
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { VEX_W_TABLE (VEX_W_0F3ACE) },
6695     { VEX_W_TABLE (VEX_W_0F3ACF) },
6696     /* d0 */
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     /* d8 */
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6714     /* e0 */
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     /* e8 */
6724     { Bad_Opcode },
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     /* f0 */
6733     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     /* f8 */
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750   },
6751 };
6752
6753 #include "i386-dis-evex.h"
6754
6755 static const struct dis386 vex_len_table[][2] = {
6756   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6757   {
6758     { "vmovlpX",        { XM, Vex, EXq }, 0 },
6759   },
6760
6761   /* VEX_LEN_0F12_P_0_M_1 */
6762   {
6763     { "vmovhlps",       { XM, Vex, EXq }, 0 },
6764   },
6765
6766   /* VEX_LEN_0F13_M_0 */
6767   {
6768     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
6769   },
6770
6771   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6772   {
6773     { "vmovhpX",        { XM, Vex, EXq }, 0 },
6774   },
6775
6776   /* VEX_LEN_0F16_P_0_M_1 */
6777   {
6778     { "vmovlhps",       { XM, Vex, EXq }, 0 },
6779   },
6780
6781   /* VEX_LEN_0F17_M_0 */
6782   {
6783     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
6784   },
6785
6786   /* VEX_LEN_0F41 */
6787   {
6788     { Bad_Opcode },
6789     { MOD_TABLE (MOD_VEX_0F41_L_1) },
6790   },
6791
6792   /* VEX_LEN_0F42 */
6793   {
6794     { Bad_Opcode },
6795     { MOD_TABLE (MOD_VEX_0F42_L_1) },
6796   },
6797
6798   /* VEX_LEN_0F44 */
6799   {
6800     { MOD_TABLE (MOD_VEX_0F44_L_0) },
6801   },
6802
6803   /* VEX_LEN_0F45 */
6804   {
6805     { Bad_Opcode },
6806     { MOD_TABLE (MOD_VEX_0F45_L_1) },
6807   },
6808
6809   /* VEX_LEN_0F46 */
6810   {
6811     { Bad_Opcode },
6812     { MOD_TABLE (MOD_VEX_0F46_L_1) },
6813   },
6814
6815   /* VEX_LEN_0F47 */
6816   {
6817     { Bad_Opcode },
6818     { MOD_TABLE (MOD_VEX_0F47_L_1) },
6819   },
6820
6821   /* VEX_LEN_0F4A */
6822   {
6823     { Bad_Opcode },
6824     { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6825   },
6826
6827   /* VEX_LEN_0F4B */
6828   {
6829     { Bad_Opcode },
6830     { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6831   },
6832
6833   /* VEX_LEN_0F6E */
6834   {
6835     { "vmovK",          { XMScalar, Edq }, PREFIX_DATA },
6836   },
6837
6838   /* VEX_LEN_0F77 */
6839   {
6840     { "vzeroupper",     { XX }, 0 },
6841     { "vzeroall",       { XX }, 0 },
6842   },
6843
6844   /* VEX_LEN_0F7E_P_1 */
6845   {
6846     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
6847   },
6848
6849   /* VEX_LEN_0F7E_P_2 */
6850   {
6851     { "vmovK",          { Edq, XMScalar }, 0 },
6852   },
6853
6854   /* VEX_LEN_0F90 */
6855   {
6856     { VEX_W_TABLE (VEX_W_0F90_L_0) },
6857   },
6858
6859   /* VEX_LEN_0F91 */
6860   {
6861     { MOD_TABLE (MOD_VEX_0F91_L_0) },
6862   },
6863
6864   /* VEX_LEN_0F92 */
6865   {
6866     { MOD_TABLE (MOD_VEX_0F92_L_0) },
6867   },
6868
6869   /* VEX_LEN_0F93 */
6870   {
6871     { MOD_TABLE (MOD_VEX_0F93_L_0) },
6872   },
6873
6874   /* VEX_LEN_0F98 */
6875   {
6876     { MOD_TABLE (MOD_VEX_0F98_L_0) },
6877   },
6878
6879   /* VEX_LEN_0F99 */
6880   {
6881     { MOD_TABLE (MOD_VEX_0F99_L_0) },
6882   },
6883
6884   /* VEX_LEN_0FAE_R_2_M_0 */
6885   {
6886     { "vldmxcsr",       { Md }, 0 },
6887   },
6888
6889   /* VEX_LEN_0FAE_R_3_M_0 */
6890   {
6891     { "vstmxcsr",       { Md }, 0 },
6892   },
6893
6894   /* VEX_LEN_0FC4 */
6895   {
6896     { "vpinsrw",        { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6897   },
6898
6899   /* VEX_LEN_0FC5 */
6900   {
6901     { "vpextrw",        { Gdq, XS, Ib }, PREFIX_DATA },
6902   },
6903
6904   /* VEX_LEN_0FD6 */
6905   {
6906     { "vmovq",          { EXqS, XMScalar }, PREFIX_DATA },
6907   },
6908
6909   /* VEX_LEN_0FF7 */
6910   {
6911     { "vmaskmovdqu",    { XM, XS }, PREFIX_DATA },
6912   },
6913
6914   /* VEX_LEN_0F3816 */
6915   {
6916     { Bad_Opcode },
6917     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6918   },
6919
6920   /* VEX_LEN_0F3819 */
6921   {
6922     { Bad_Opcode },
6923     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6924   },
6925
6926   /* VEX_LEN_0F381A_M_0 */
6927   {
6928     { Bad_Opcode },
6929     { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6930   },
6931
6932   /* VEX_LEN_0F3836 */
6933   {
6934     { Bad_Opcode },
6935     { VEX_W_TABLE (VEX_W_0F3836) },
6936   },
6937
6938   /* VEX_LEN_0F3841 */
6939   {
6940     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
6941   },
6942
6943    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6944   {
6945     { "ldtilecfg", { M }, 0 },
6946   },
6947
6948   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6949   {
6950     { "tilerelease", { Skip_MODRM }, 0 },
6951   },
6952
6953   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6954   {
6955     { "sttilecfg", { M }, 0 },
6956   },
6957
6958   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6959   {
6960     { "tilezero", { TMM, Skip_MODRM }, 0 },
6961   },
6962
6963   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
6964   {
6965     { "tilestored", { MVexSIBMEM, TMM }, 0 },
6966   },
6967   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
6968   {
6969     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
6970   },
6971
6972   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
6973   {
6974     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
6975   },
6976
6977   /* VEX_LEN_0F385A_M_0 */
6978   {
6979     { Bad_Opcode },
6980     { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
6981   },
6982
6983   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
6984   {
6985     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
6986   },
6987
6988   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
6989   {
6990     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
6991   },
6992
6993   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
6994   {
6995     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
6996   },
6997
6998   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
6999   {
7000     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7001   },
7002
7003   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7004   {
7005     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7006   },
7007
7008   /* VEX_LEN_0F38DB */
7009   {
7010     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7011   },
7012
7013   /* VEX_LEN_0F38F2 */
7014   {
7015     { "andnS",          { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7016   },
7017
7018   /* VEX_LEN_0F38F3 */
7019   {
7020     { REG_TABLE(REG_VEX_0F38F3_L_0) },
7021   },
7022
7023   /* VEX_LEN_0F38F5 */
7024   {
7025     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7026   },
7027
7028   /* VEX_LEN_0F38F6 */
7029   {
7030     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7031   },
7032
7033   /* VEX_LEN_0F38F7 */
7034   {
7035     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7036   },
7037
7038   /* VEX_LEN_0F3A00 */
7039   {
7040     { Bad_Opcode },
7041     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7042   },
7043
7044   /* VEX_LEN_0F3A01 */
7045   {
7046     { Bad_Opcode },
7047     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7048   },
7049
7050   /* VEX_LEN_0F3A06 */
7051   {
7052     { Bad_Opcode },
7053     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7054   },
7055
7056   /* VEX_LEN_0F3A14 */
7057   {
7058     { "vpextrb",        { Edqb, XM, Ib }, PREFIX_DATA },
7059   },
7060
7061   /* VEX_LEN_0F3A15 */
7062   {
7063     { "vpextrw",        { Edqw, XM, Ib }, PREFIX_DATA },
7064   },
7065
7066   /* VEX_LEN_0F3A16  */
7067   {
7068     { "vpextrK",        { Edq, XM, Ib }, PREFIX_DATA },
7069   },
7070
7071   /* VEX_LEN_0F3A17 */
7072   {
7073     { "vextractps",     { Edqd, XM, Ib }, PREFIX_DATA },
7074   },
7075
7076   /* VEX_LEN_0F3A18 */
7077   {
7078     { Bad_Opcode },
7079     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7080   },
7081
7082   /* VEX_LEN_0F3A19 */
7083   {
7084     { Bad_Opcode },
7085     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7086   },
7087
7088   /* VEX_LEN_0F3A20 */
7089   {
7090     { "vpinsrb",        { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7091   },
7092
7093   /* VEX_LEN_0F3A21 */
7094   {
7095     { "vinsertps",      { XM, Vex, EXd, Ib }, PREFIX_DATA },
7096   },
7097
7098   /* VEX_LEN_0F3A22 */
7099   {
7100     { "vpinsrK",        { XM, Vex, Edq, Ib }, PREFIX_DATA },
7101   },
7102
7103   /* VEX_LEN_0F3A30 */
7104   {
7105     { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7106   },
7107
7108   /* VEX_LEN_0F3A31 */
7109   {
7110     { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7111   },
7112
7113   /* VEX_LEN_0F3A32 */
7114   {
7115     { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7116   },
7117
7118   /* VEX_LEN_0F3A33 */
7119   {
7120     { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7121   },
7122
7123   /* VEX_LEN_0F3A38 */
7124   {
7125     { Bad_Opcode },
7126     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7127   },
7128
7129   /* VEX_LEN_0F3A39 */
7130   {
7131     { Bad_Opcode },
7132     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7133   },
7134
7135   /* VEX_LEN_0F3A41 */
7136   {
7137     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7138   },
7139
7140   /* VEX_LEN_0F3A46 */
7141   {
7142     { Bad_Opcode },
7143     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7144   },
7145
7146   /* VEX_LEN_0F3A60 */
7147   {
7148     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7149   },
7150
7151   /* VEX_LEN_0F3A61 */
7152   {
7153     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7154   },
7155
7156   /* VEX_LEN_0F3A62 */
7157   {
7158     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7159   },
7160
7161   /* VEX_LEN_0F3A63 */
7162   {
7163     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7164   },
7165
7166   /* VEX_LEN_0F3ADF */
7167   {
7168     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7169   },
7170
7171   /* VEX_LEN_0F3AF0 */
7172   {
7173     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7174   },
7175
7176   /* VEX_LEN_0FXOP_08_85 */
7177   {
7178     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7179   },
7180
7181   /* VEX_LEN_0FXOP_08_86 */
7182   {
7183     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7184   },
7185
7186   /* VEX_LEN_0FXOP_08_87 */
7187   {
7188     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7189   },
7190
7191   /* VEX_LEN_0FXOP_08_8E */
7192   {
7193     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7194   },
7195
7196   /* VEX_LEN_0FXOP_08_8F */
7197   {
7198     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7199   },
7200
7201   /* VEX_LEN_0FXOP_08_95 */
7202   {
7203     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7204   },
7205
7206   /* VEX_LEN_0FXOP_08_96 */
7207   {
7208     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7209   },
7210
7211   /* VEX_LEN_0FXOP_08_97 */
7212   {
7213     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7214   },
7215
7216   /* VEX_LEN_0FXOP_08_9E */
7217   {
7218     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7219   },
7220
7221   /* VEX_LEN_0FXOP_08_9F */
7222   {
7223     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7224   },
7225
7226   /* VEX_LEN_0FXOP_08_A3 */
7227   {
7228     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7229   },
7230
7231   /* VEX_LEN_0FXOP_08_A6 */
7232   {
7233     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7234   },
7235
7236   /* VEX_LEN_0FXOP_08_B6 */
7237   {
7238     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7239   },
7240
7241   /* VEX_LEN_0FXOP_08_C0 */
7242   {
7243     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7244   },
7245
7246   /* VEX_LEN_0FXOP_08_C1 */
7247   {
7248     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7249   },
7250
7251   /* VEX_LEN_0FXOP_08_C2 */
7252   {
7253     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7254   },
7255
7256   /* VEX_LEN_0FXOP_08_C3 */
7257   {
7258     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7259   },
7260
7261   /* VEX_LEN_0FXOP_08_CC */
7262   {
7263     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7264   },
7265
7266   /* VEX_LEN_0FXOP_08_CD */
7267   {
7268     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7269   },
7270
7271   /* VEX_LEN_0FXOP_08_CE */
7272   {
7273     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7274   },
7275
7276   /* VEX_LEN_0FXOP_08_CF */
7277   {
7278     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7279   },
7280
7281   /* VEX_LEN_0FXOP_08_EC */
7282   {
7283     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7284   },
7285
7286   /* VEX_LEN_0FXOP_08_ED */
7287   {
7288     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7289   },
7290
7291   /* VEX_LEN_0FXOP_08_EE */
7292   {
7293     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7294   },
7295
7296   /* VEX_LEN_0FXOP_08_EF */
7297   {
7298     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7299   },
7300
7301   /* VEX_LEN_0FXOP_09_01 */
7302   {
7303     { REG_TABLE (REG_0FXOP_09_01_L_0) },
7304   },
7305
7306   /* VEX_LEN_0FXOP_09_02 */
7307   {
7308     { REG_TABLE (REG_0FXOP_09_02_L_0) },
7309   },
7310
7311   /* VEX_LEN_0FXOP_09_12_M_1 */
7312   {
7313     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7314   },
7315
7316   /* VEX_LEN_0FXOP_09_82_W_0 */
7317   {
7318     { "vfrczss",        { XM, EXd }, 0 },
7319   },
7320
7321   /* VEX_LEN_0FXOP_09_83_W_0 */
7322   {
7323     { "vfrczsd",        { XM, EXq }, 0 },
7324   },
7325
7326   /* VEX_LEN_0FXOP_09_90 */
7327   {
7328     { "vprotb",         { XM, EXx, VexW }, 0 },
7329   },
7330
7331   /* VEX_LEN_0FXOP_09_91 */
7332   {
7333     { "vprotw",         { XM, EXx, VexW }, 0 },
7334   },
7335
7336   /* VEX_LEN_0FXOP_09_92 */
7337   {
7338     { "vprotd",         { XM, EXx, VexW }, 0 },
7339   },
7340
7341   /* VEX_LEN_0FXOP_09_93 */
7342   {
7343     { "vprotq",         { XM, EXx, VexW }, 0 },
7344   },
7345
7346   /* VEX_LEN_0FXOP_09_94 */
7347   {
7348     { "vpshlb",         { XM, EXx, VexW }, 0 },
7349   },
7350
7351   /* VEX_LEN_0FXOP_09_95 */
7352   {
7353     { "vpshlw",         { XM, EXx, VexW }, 0 },
7354   },
7355
7356   /* VEX_LEN_0FXOP_09_96 */
7357   {
7358     { "vpshld",         { XM, EXx, VexW }, 0 },
7359   },
7360
7361   /* VEX_LEN_0FXOP_09_97 */
7362   {
7363     { "vpshlq",         { XM, EXx, VexW }, 0 },
7364   },
7365
7366   /* VEX_LEN_0FXOP_09_98 */
7367   {
7368     { "vpshab",         { XM, EXx, VexW }, 0 },
7369   },
7370
7371   /* VEX_LEN_0FXOP_09_99 */
7372   {
7373     { "vpshaw",         { XM, EXx, VexW }, 0 },
7374   },
7375
7376   /* VEX_LEN_0FXOP_09_9A */
7377   {
7378     { "vpshad",         { XM, EXx, VexW }, 0 },
7379   },
7380
7381   /* VEX_LEN_0FXOP_09_9B */
7382   {
7383     { "vpshaq",         { XM, EXx, VexW }, 0 },
7384   },
7385
7386   /* VEX_LEN_0FXOP_09_C1 */
7387   {
7388     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7389   },
7390
7391   /* VEX_LEN_0FXOP_09_C2 */
7392   {
7393     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7394   },
7395
7396   /* VEX_LEN_0FXOP_09_C3 */
7397   {
7398     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7399   },
7400
7401   /* VEX_LEN_0FXOP_09_C6 */
7402   {
7403     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7404   },
7405
7406   /* VEX_LEN_0FXOP_09_C7 */
7407   {
7408     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7409   },
7410
7411   /* VEX_LEN_0FXOP_09_CB */
7412   {
7413     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7414   },
7415
7416   /* VEX_LEN_0FXOP_09_D1 */
7417   {
7418     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7419   },
7420
7421   /* VEX_LEN_0FXOP_09_D2 */
7422   {
7423     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7424   },
7425
7426   /* VEX_LEN_0FXOP_09_D3 */
7427   {
7428     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7429   },
7430
7431   /* VEX_LEN_0FXOP_09_D6 */
7432   {
7433     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7434   },
7435
7436   /* VEX_LEN_0FXOP_09_D7 */
7437   {
7438     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7439   },
7440
7441   /* VEX_LEN_0FXOP_09_DB */
7442   {
7443     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7444   },
7445
7446   /* VEX_LEN_0FXOP_09_E1 */
7447   {
7448     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7449   },
7450
7451   /* VEX_LEN_0FXOP_09_E2 */
7452   {
7453     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7454   },
7455
7456   /* VEX_LEN_0FXOP_09_E3 */
7457   {
7458     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7459   },
7460
7461   /* VEX_LEN_0FXOP_0A_12 */
7462   {
7463     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7464   },
7465 };
7466
7467 #include "i386-dis-evex-len.h"
7468
7469 static const struct dis386 vex_w_table[][2] = {
7470   {
7471     /* VEX_W_0F41_L_1_M_1 */
7472     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7473     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7474   },
7475   {
7476     /* VEX_W_0F42_L_1_M_1 */
7477     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7478     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7479   },
7480   {
7481     /* VEX_W_0F44_L_0_M_1 */
7482     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7483     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7484   },
7485   {
7486     /* VEX_W_0F45_L_1_M_1 */
7487     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7488     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7489   },
7490   {
7491     /* VEX_W_0F46_L_1_M_1 */
7492     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7493     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7494   },
7495   {
7496     /* VEX_W_0F47_L_1_M_1 */
7497     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7498     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7499   },
7500   {
7501     /* VEX_W_0F4A_L_1_M_1 */
7502     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7503     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7504   },
7505   {
7506     /* VEX_W_0F4B_L_1_M_1 */
7507     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7508     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7509   },
7510   {
7511     /* VEX_W_0F90_L_0 */
7512     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7513     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7514   },
7515   {
7516     /* VEX_W_0F91_L_0_M_0 */
7517     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7518     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7519   },
7520   {
7521     /* VEX_W_0F92_L_0_M_1 */
7522     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7523     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7524   },
7525   {
7526     /* VEX_W_0F93_L_0_M_1 */
7527     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7528     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7529   },
7530   {
7531     /* VEX_W_0F98_L_0_M_1 */
7532     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7533     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7534   },
7535   {
7536     /* VEX_W_0F99_L_0_M_1 */
7537     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7538     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7539   },
7540   {
7541     /* VEX_W_0F380C  */
7542     { "vpermilps",      { XM, Vex, EXx }, PREFIX_DATA },
7543   },
7544   {
7545     /* VEX_W_0F380D  */
7546     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7547   },
7548   {
7549     /* VEX_W_0F380E  */
7550     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7551   },
7552   {
7553     /* VEX_W_0F380F  */
7554     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7555   },
7556   {
7557     /* VEX_W_0F3813 */
7558     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7559   },
7560   {
7561     /* VEX_W_0F3816_L_1  */
7562     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7563   },
7564   {
7565     /* VEX_W_0F3818 */
7566     { "vbroadcastss",   { XM, EXxmm_md }, PREFIX_DATA },
7567   },
7568   {
7569     /* VEX_W_0F3819_L_1 */
7570     { "vbroadcastsd",   { XM, EXxmm_mq }, PREFIX_DATA },
7571   },
7572   {
7573     /* VEX_W_0F381A_M_0_L_1 */
7574     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7575   },
7576   {
7577     /* VEX_W_0F382C_M_0 */
7578     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7579   },
7580   {
7581     /* VEX_W_0F382D_M_0 */
7582     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7583   },
7584   {
7585     /* VEX_W_0F382E_M_0 */
7586     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7587   },
7588   {
7589     /* VEX_W_0F382F_M_0 */
7590     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7591   },
7592   {
7593     /* VEX_W_0F3836  */
7594     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7595   },
7596   {
7597     /* VEX_W_0F3846 */
7598     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7599   },
7600   {
7601     /* VEX_W_0F3849_X86_64_P_0 */
7602     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7603   },
7604   {
7605     /* VEX_W_0F3849_X86_64_P_2 */
7606     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7607   },
7608   {
7609     /* VEX_W_0F3849_X86_64_P_3 */
7610     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7611   },
7612   {
7613     /* VEX_W_0F384B_X86_64_P_1 */
7614     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7615   },
7616   {
7617     /* VEX_W_0F384B_X86_64_P_2 */
7618     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7619   },
7620   {
7621     /* VEX_W_0F384B_X86_64_P_3 */
7622     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7623   },
7624   {
7625     /* VEX_W_0F3850 */
7626     { "%XV vpdpbusd",   { XM, Vex, EXx }, 0 },
7627   },
7628   {
7629     /* VEX_W_0F3851 */
7630     { "%XV vpdpbusds",  { XM, Vex, EXx }, 0 },
7631   },
7632   {
7633     /* VEX_W_0F3852 */
7634     { "%XV vpdpwssd",   { XM, Vex, EXx }, 0 },
7635   },
7636   {
7637     /* VEX_W_0F3853 */
7638     { "%XV vpdpwssds",  { XM, Vex, EXx }, 0 },
7639   },
7640   {
7641     /* VEX_W_0F3858 */
7642     { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7643   },
7644   {
7645     /* VEX_W_0F3859 */
7646     { "vpbroadcastq",   { XM, EXxmm_mq }, PREFIX_DATA },
7647   },
7648   {
7649     /* VEX_W_0F385A_M_0_L_0 */
7650     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7651   },
7652   {
7653     /* VEX_W_0F385C_X86_64_P_1 */
7654     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7655   },
7656   {
7657     /* VEX_W_0F385E_X86_64_P_0 */
7658     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7659   },
7660   {
7661     /* VEX_W_0F385E_X86_64_P_1 */
7662     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7663   },
7664   {
7665     /* VEX_W_0F385E_X86_64_P_2 */
7666     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7667   },
7668   {
7669     /* VEX_W_0F385E_X86_64_P_3 */
7670     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7671   },
7672   {
7673     /* VEX_W_0F3878 */
7674     { "vpbroadcastb",   { XM, EXxmm_mb }, PREFIX_DATA },
7675   },
7676   {
7677     /* VEX_W_0F3879 */
7678     { "vpbroadcastw",   { XM, EXxmm_mw }, PREFIX_DATA },
7679   },
7680   {
7681     /* VEX_W_0F38CF */
7682     { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7683   },
7684   {
7685     /* VEX_W_0F3A00_L_1 */
7686     { Bad_Opcode },
7687     { "vpermq",         { XM, EXx, Ib }, PREFIX_DATA },
7688   },
7689   {
7690     /* VEX_W_0F3A01_L_1 */
7691     { Bad_Opcode },
7692     { "vpermpd",        { XM, EXx, Ib }, PREFIX_DATA },
7693   },
7694   {
7695     /* VEX_W_0F3A02 */
7696     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7697   },
7698   {
7699     /* VEX_W_0F3A04 */
7700     { "vpermilps",      { XM, EXx, Ib }, PREFIX_DATA },
7701   },
7702   {
7703     /* VEX_W_0F3A05 */
7704     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7705   },
7706   {
7707     /* VEX_W_0F3A06_L_1 */
7708     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7709   },
7710   {
7711     /* VEX_W_0F3A18_L_1 */
7712     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7713   },
7714   {
7715     /* VEX_W_0F3A19_L_1 */
7716     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7717   },
7718   {
7719     /* VEX_W_0F3A1D */
7720     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7721   },
7722   {
7723     /* VEX_W_0F3A38_L_1 */
7724     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F3A39_L_1 */
7728     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F3A46_L_1 */
7732     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F3A4A */
7736     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3A4B */
7740     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3A4C */
7744     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7745   },
7746   {
7747     /* VEX_W_0F3ACE */
7748     { Bad_Opcode },
7749     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F3ACF */
7753     { Bad_Opcode },
7754     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7755   },
7756   /* VEX_W_0FXOP_08_85_L_0 */
7757   {
7758     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7759   },
7760   /* VEX_W_0FXOP_08_86_L_0 */
7761   {
7762     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7763   },
7764   /* VEX_W_0FXOP_08_87_L_0 */
7765   {
7766     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7767   },
7768   /* VEX_W_0FXOP_08_8E_L_0 */
7769   {
7770     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7771   },
7772   /* VEX_W_0FXOP_08_8F_L_0 */
7773   {
7774     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7775   },
7776   /* VEX_W_0FXOP_08_95_L_0 */
7777   {
7778     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7779   },
7780   /* VEX_W_0FXOP_08_96_L_0 */
7781   {
7782     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7783   },
7784   /* VEX_W_0FXOP_08_97_L_0 */
7785   {
7786     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7787   },
7788   /* VEX_W_0FXOP_08_9E_L_0 */
7789   {
7790     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7791   },
7792   /* VEX_W_0FXOP_08_9F_L_0 */
7793   {
7794     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
7795   },
7796   /* VEX_W_0FXOP_08_A6_L_0 */
7797   {
7798     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
7799   },
7800   /* VEX_W_0FXOP_08_B6_L_0 */
7801   {
7802     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7803   },
7804   /* VEX_W_0FXOP_08_C0_L_0 */
7805   {
7806     { "vprotb",         { XM, EXx, Ib }, 0 },
7807   },
7808   /* VEX_W_0FXOP_08_C1_L_0 */
7809   {
7810     { "vprotw",         { XM, EXx, Ib }, 0 },
7811   },
7812   /* VEX_W_0FXOP_08_C2_L_0 */
7813   {
7814     { "vprotd",         { XM, EXx, Ib }, 0 },
7815   },
7816   /* VEX_W_0FXOP_08_C3_L_0 */
7817   {
7818     { "vprotq",         { XM, EXx, Ib }, 0 },
7819   },
7820   /* VEX_W_0FXOP_08_CC_L_0 */
7821   {
7822      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
7823   },
7824   /* VEX_W_0FXOP_08_CD_L_0 */
7825   {
7826      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
7827   },
7828   /* VEX_W_0FXOP_08_CE_L_0 */
7829   {
7830      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
7831   },
7832   /* VEX_W_0FXOP_08_CF_L_0 */
7833   {
7834      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
7835   },
7836   /* VEX_W_0FXOP_08_EC_L_0 */
7837   {
7838      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
7839   },
7840   /* VEX_W_0FXOP_08_ED_L_0 */
7841   {
7842      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
7843   },
7844   /* VEX_W_0FXOP_08_EE_L_0 */
7845   {
7846      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
7847   },
7848   /* VEX_W_0FXOP_08_EF_L_0 */
7849   {
7850      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
7851   },
7852   /* VEX_W_0FXOP_09_80 */
7853   {
7854     { "vfrczps",        { XM, EXx }, 0 },
7855   },
7856   /* VEX_W_0FXOP_09_81 */
7857   {
7858     { "vfrczpd",        { XM, EXx }, 0 },
7859   },
7860   /* VEX_W_0FXOP_09_82 */
7861   {
7862     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7863   },
7864   /* VEX_W_0FXOP_09_83 */
7865   {
7866     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7867   },
7868   /* VEX_W_0FXOP_09_C1_L_0 */
7869   {
7870     { "vphaddbw",       { XM, EXxmm }, 0 },
7871   },
7872   /* VEX_W_0FXOP_09_C2_L_0 */
7873   {
7874     { "vphaddbd",       { XM, EXxmm }, 0 },
7875   },
7876   /* VEX_W_0FXOP_09_C3_L_0 */
7877   {
7878     { "vphaddbq",       { XM, EXxmm }, 0 },
7879   },
7880   /* VEX_W_0FXOP_09_C6_L_0 */
7881   {
7882     { "vphaddwd",       { XM, EXxmm }, 0 },
7883   },
7884   /* VEX_W_0FXOP_09_C7_L_0 */
7885   {
7886     { "vphaddwq",       { XM, EXxmm }, 0 },
7887   },
7888   /* VEX_W_0FXOP_09_CB_L_0 */
7889   {
7890     { "vphadddq",       { XM, EXxmm }, 0 },
7891   },
7892   /* VEX_W_0FXOP_09_D1_L_0 */
7893   {
7894     { "vphaddubw",      { XM, EXxmm }, 0 },
7895   },
7896   /* VEX_W_0FXOP_09_D2_L_0 */
7897   {
7898     { "vphaddubd",      { XM, EXxmm }, 0 },
7899   },
7900   /* VEX_W_0FXOP_09_D3_L_0 */
7901   {
7902     { "vphaddubq",      { XM, EXxmm }, 0 },
7903   },
7904   /* VEX_W_0FXOP_09_D6_L_0 */
7905   {
7906     { "vphadduwd",      { XM, EXxmm }, 0 },
7907   },
7908   /* VEX_W_0FXOP_09_D7_L_0 */
7909   {
7910     { "vphadduwq",      { XM, EXxmm }, 0 },
7911   },
7912   /* VEX_W_0FXOP_09_DB_L_0 */
7913   {
7914     { "vphaddudq",      { XM, EXxmm }, 0 },
7915   },
7916   /* VEX_W_0FXOP_09_E1_L_0 */
7917   {
7918     { "vphsubbw",       { XM, EXxmm }, 0 },
7919   },
7920   /* VEX_W_0FXOP_09_E2_L_0 */
7921   {
7922     { "vphsubwd",       { XM, EXxmm }, 0 },
7923   },
7924   /* VEX_W_0FXOP_09_E3_L_0 */
7925   {
7926     { "vphsubdq",       { XM, EXxmm }, 0 },
7927   },
7928
7929 #include "i386-dis-evex-w.h"
7930 };
7931
7932 static const struct dis386 mod_table[][2] = {
7933   {
7934     /* MOD_8D */
7935     { "leaS",           { Gv, M }, 0 },
7936   },
7937   {
7938     /* MOD_C6_REG_7 */
7939     { Bad_Opcode },
7940     { RM_TABLE (RM_C6_REG_7) },
7941   },
7942   {
7943     /* MOD_C7_REG_7 */
7944     { Bad_Opcode },
7945     { RM_TABLE (RM_C7_REG_7) },
7946   },
7947   {
7948     /* MOD_FF_REG_3 */
7949     { "{l|}call^", { indirEp }, 0 },
7950   },
7951   {
7952     /* MOD_FF_REG_5 */
7953     { "{l|}jmp^", { indirEp }, 0 },
7954   },
7955   {
7956     /* MOD_0F01_REG_0 */
7957     { X86_64_TABLE (X86_64_0F01_REG_0) },
7958     { RM_TABLE (RM_0F01_REG_0) },
7959   },
7960   {
7961     /* MOD_0F01_REG_1 */
7962     { X86_64_TABLE (X86_64_0F01_REG_1) },
7963     { RM_TABLE (RM_0F01_REG_1) },
7964   },
7965   {
7966     /* MOD_0F01_REG_2 */
7967     { X86_64_TABLE (X86_64_0F01_REG_2) },
7968     { RM_TABLE (RM_0F01_REG_2) },
7969   },
7970   {
7971     /* MOD_0F01_REG_3 */
7972     { X86_64_TABLE (X86_64_0F01_REG_3) },
7973     { RM_TABLE (RM_0F01_REG_3) },
7974   },
7975   {
7976     /* MOD_0F01_REG_5 */
7977     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
7978     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
7979   },
7980   {
7981     /* MOD_0F01_REG_7 */
7982     { "invlpg",         { Mb }, 0 },
7983     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
7984   },
7985   {
7986     /* MOD_0F12_PREFIX_0 */
7987     { "movlpX",         { XM, EXq }, 0 },
7988     { "movhlps",        { XM, EXq }, 0 },
7989   },
7990   {
7991     /* MOD_0F12_PREFIX_2 */
7992     { "movlpX", { XM, EXq }, 0 },
7993   },
7994   {
7995     /* MOD_0F13 */
7996     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
7997   },
7998   {
7999     /* MOD_0F16_PREFIX_0 */
8000     { "movhpX",         { XM, EXq }, 0 },
8001     { "movlhps",        { XM, EXq }, 0 },
8002   },
8003   {
8004     /* MOD_0F16_PREFIX_2 */
8005     { "movhpX", { XM, EXq }, 0 },
8006   },
8007   {
8008     /* MOD_0F17 */
8009     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
8010   },
8011   {
8012     /* MOD_0F18_REG_0 */
8013     { "prefetchnta",    { Mb }, 0 },
8014     { "nopQ",           { Ev }, 0 },
8015   },
8016   {
8017     /* MOD_0F18_REG_1 */
8018     { "prefetcht0",     { Mb }, 0 },
8019     { "nopQ",           { Ev }, 0 },
8020   },
8021   {
8022     /* MOD_0F18_REG_2 */
8023     { "prefetcht1",     { Mb }, 0 },
8024     { "nopQ",           { Ev }, 0 },
8025   },
8026   {
8027     /* MOD_0F18_REG_3 */
8028     { "prefetcht2",     { Mb }, 0 },
8029     { "nopQ",           { Ev }, 0 },
8030   },
8031   {
8032     /* MOD_0F1A_PREFIX_0 */
8033     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8034     { "nopQ",           { Ev }, 0 },
8035   },
8036   {
8037     /* MOD_0F1B_PREFIX_0 */
8038     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8039     { "nopQ",           { Ev }, 0 },
8040   },
8041   {
8042     /* MOD_0F1B_PREFIX_1 */
8043     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8044     { "nopQ",           { Ev }, PREFIX_IGNORED },
8045   },
8046   {
8047     /* MOD_0F1C_PREFIX_0 */
8048     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8049     { "nopQ",           { Ev }, 0 },
8050   },
8051   {
8052     /* MOD_0F1E_PREFIX_1 */
8053     { "nopQ",           { Ev }, PREFIX_IGNORED },
8054     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8055   },
8056   {
8057     /* MOD_0F2B_PREFIX_0 */
8058     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
8059   },
8060   {
8061     /* MOD_0F2B_PREFIX_1 */
8062     {"movntss",         { Md, XM }, PREFIX_OPCODE },
8063   },
8064   {
8065     /* MOD_0F2B_PREFIX_2 */
8066     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
8067   },
8068   {
8069     /* MOD_0F2B_PREFIX_3 */
8070     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
8071   },
8072   {
8073     /* MOD_0F50 */
8074     { Bad_Opcode },
8075     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
8076   },
8077   {
8078     /* MOD_0F71 */
8079     { Bad_Opcode },
8080     { REG_TABLE (REG_0F71_MOD_0) },
8081   },
8082   {
8083     /* MOD_0F72 */
8084     { Bad_Opcode },
8085     { REG_TABLE (REG_0F72_MOD_0) },
8086   },
8087   {
8088     /* MOD_0F73 */
8089     { Bad_Opcode },
8090     { REG_TABLE (REG_0F73_MOD_0) },
8091   },
8092   {
8093     /* MOD_0FAE_REG_0 */
8094     { "fxsave",         { FXSAVE }, 0 },
8095     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8096   },
8097   {
8098     /* MOD_0FAE_REG_1 */
8099     { "fxrstor",        { FXSAVE }, 0 },
8100     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8101   },
8102   {
8103     /* MOD_0FAE_REG_2 */
8104     { "ldmxcsr",        { Md }, 0 },
8105     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8106   },
8107   {
8108     /* MOD_0FAE_REG_3 */
8109     { "stmxcsr",        { Md }, 0 },
8110     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8111   },
8112   {
8113     /* MOD_0FAE_REG_4 */
8114     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8115     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8116   },
8117   {
8118     /* MOD_0FAE_REG_5 */
8119     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
8120     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8121   },
8122   {
8123     /* MOD_0FAE_REG_6 */
8124     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8125     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8126   },
8127   {
8128     /* MOD_0FAE_REG_7 */
8129     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8130     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8131   },
8132   {
8133     /* MOD_0FB2 */
8134     { "lssS",           { Gv, Mp }, 0 },
8135   },
8136   {
8137     /* MOD_0FB4 */
8138     { "lfsS",           { Gv, Mp }, 0 },
8139   },
8140   {
8141     /* MOD_0FB5 */
8142     { "lgsS",           { Gv, Mp }, 0 },
8143   },
8144   {
8145     /* MOD_0FC3 */
8146     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8147   },
8148   {
8149     /* MOD_0FC7_REG_3 */
8150     { "xrstors",        { FXSAVE }, 0 },
8151   },
8152   {
8153     /* MOD_0FC7_REG_4 */
8154     { "xsavec",         { FXSAVE }, 0 },
8155   },
8156   {
8157     /* MOD_0FC7_REG_5 */
8158     { "xsaves",         { FXSAVE }, 0 },
8159   },
8160   {
8161     /* MOD_0FC7_REG_6 */
8162     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8163     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8164   },
8165   {
8166     /* MOD_0FC7_REG_7 */
8167     { "vmptrst",        { Mq }, 0 },
8168     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8169   },
8170   {
8171     /* MOD_0FD7 */
8172     { Bad_Opcode },
8173     { "pmovmskb",       { Gdq, MS }, 0 },
8174   },
8175   {
8176     /* MOD_0FE7_PREFIX_2 */
8177     { "movntdq",        { Mx, XM }, 0 },
8178   },
8179   {
8180     /* MOD_0FF0_PREFIX_3 */
8181     { "lddqu",          { XM, M }, 0 },
8182   },
8183   {
8184     /* MOD_0F382A */
8185     { "movntdqa",       { XM, Mx }, PREFIX_DATA },
8186   },
8187   {
8188     /* MOD_0F38DC_PREFIX_1 */
8189     { "aesenc128kl",    { XM, M }, 0 },
8190     { "loadiwkey",      { XM, EXx }, 0 },
8191   },
8192   {
8193     /* MOD_0F38DD_PREFIX_1 */
8194     { "aesdec128kl",    { XM, M }, 0 },
8195   },
8196   {
8197     /* MOD_0F38DE_PREFIX_1 */
8198     { "aesenc256kl",    { XM, M }, 0 },
8199   },
8200   {
8201     /* MOD_0F38DF_PREFIX_1 */
8202     { "aesdec256kl",    { XM, M }, 0 },
8203   },
8204   {
8205     /* MOD_0F38F5 */
8206     { "wrussK",         { M, Gdq }, PREFIX_DATA },
8207   },
8208   {
8209     /* MOD_0F38F6_PREFIX_0 */
8210     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
8211   },
8212   {
8213     /* MOD_0F38F8_PREFIX_1 */
8214     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
8215   },
8216   {
8217     /* MOD_0F38F8_PREFIX_2 */
8218     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
8219   },
8220   {
8221     /* MOD_0F38F8_PREFIX_3 */
8222     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
8223   },
8224   {
8225     /* MOD_0F38F9 */
8226     { "movdiri",        { Edq, Gdq }, PREFIX_OPCODE },
8227   },
8228   {
8229     /* MOD_0F38FA_PREFIX_1 */
8230     { Bad_Opcode },
8231     { "encodekey128", { Gd, Ed }, 0 },
8232   },
8233   {
8234     /* MOD_0F38FB_PREFIX_1 */
8235     { Bad_Opcode },
8236     { "encodekey256", { Gd, Ed }, 0 },
8237   },
8238   {
8239     /* MOD_0F3A0F_PREFIX_1 */
8240     { Bad_Opcode },
8241     { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8242   },
8243   {
8244     /* MOD_62_32BIT */
8245     { "bound{S|}",      { Gv, Ma }, 0 },
8246     { EVEX_TABLE (EVEX_0F) },
8247   },
8248   {
8249     /* MOD_C4_32BIT */
8250     { "lesS",           { Gv, Mp }, 0 },
8251     { VEX_C4_TABLE (VEX_0F) },
8252   },
8253   {
8254     /* MOD_C5_32BIT */
8255     { "ldsS",           { Gv, Mp }, 0 },
8256     { VEX_C5_TABLE (VEX_0F) },
8257   },
8258   {
8259     /* MOD_VEX_0F12_PREFIX_0 */
8260     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8261     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8262   },
8263   {
8264     /* MOD_VEX_0F12_PREFIX_2 */
8265     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8266   },
8267   {
8268     /* MOD_VEX_0F13 */
8269     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8270   },
8271   {
8272     /* MOD_VEX_0F16_PREFIX_0 */
8273     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8274     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8275   },
8276   {
8277     /* MOD_VEX_0F16_PREFIX_2 */
8278     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8279   },
8280   {
8281     /* MOD_VEX_0F17 */
8282     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8283   },
8284   {
8285     /* MOD_VEX_0F2B */
8286     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
8287   },
8288   {
8289     /* MOD_VEX_0F41_L_1 */
8290     { Bad_Opcode },
8291     { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8292   },
8293   {
8294     /* MOD_VEX_0F42_L_1 */
8295     { Bad_Opcode },
8296     { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8297   },
8298   {
8299     /* MOD_VEX_0F44_L_0 */
8300     { Bad_Opcode },
8301     { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8302   },
8303   {
8304     /* MOD_VEX_0F45_L_1 */
8305     { Bad_Opcode },
8306     { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8307   },
8308   {
8309     /* MOD_VEX_0F46_L_1 */
8310     { Bad_Opcode },
8311     { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8312   },
8313   {
8314     /* MOD_VEX_0F47_L_1 */
8315     { Bad_Opcode },
8316     { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8317   },
8318   {
8319     /* MOD_VEX_0F4A_L_1 */
8320     { Bad_Opcode },
8321     { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8322   },
8323   {
8324     /* MOD_VEX_0F4B_L_1 */
8325     { Bad_Opcode },
8326     { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8327   },
8328   {
8329     /* MOD_VEX_0F50 */
8330     { Bad_Opcode },
8331     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
8332   },
8333   {
8334     /* MOD_VEX_0F71 */
8335     { Bad_Opcode },
8336     { REG_TABLE (REG_VEX_0F71_M_0) },
8337   },
8338   {
8339     /* MOD_VEX_0F72 */
8340     { Bad_Opcode },
8341     { REG_TABLE (REG_VEX_0F72_M_0) },
8342   },
8343   {
8344     /* MOD_VEX_0F73 */
8345     { Bad_Opcode },
8346     { REG_TABLE (REG_VEX_0F73_M_0) },
8347   },
8348   {
8349     /* MOD_VEX_0F91_L_0 */
8350     { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8351   },
8352   {
8353     /* MOD_VEX_0F92_L_0 */
8354     { Bad_Opcode },
8355     { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8356   },
8357   {
8358     /* MOD_VEX_0F93_L_0 */
8359     { Bad_Opcode },
8360     { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8361   },
8362   {
8363     /* MOD_VEX_0F98_L_0 */
8364     { Bad_Opcode },
8365     { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8366   },
8367   {
8368     /* MOD_VEX_0F99_L_0 */
8369     { Bad_Opcode },
8370     { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8371   },
8372   {
8373     /* MOD_VEX_0FAE_REG_2 */
8374     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8375   },
8376   {
8377     /* MOD_VEX_0FAE_REG_3 */
8378     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8379   },
8380   {
8381     /* MOD_VEX_0FD7 */
8382     { Bad_Opcode },
8383     { "vpmovmskb",      { Gdq, XS }, PREFIX_DATA },
8384   },
8385   {
8386     /* MOD_VEX_0FE7 */
8387     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
8388   },
8389   {
8390     /* MOD_VEX_0FF0_PREFIX_3 */
8391     { "vlddqu",         { XM, M }, 0 },
8392   },
8393   {
8394     /* MOD_VEX_0F381A */
8395     { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8396   },
8397   {
8398     /* MOD_VEX_0F382A */
8399     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
8400   },
8401   {
8402     /* MOD_VEX_0F382C */
8403     { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8404   },
8405   {
8406     /* MOD_VEX_0F382D */
8407     { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8408   },
8409   {
8410     /* MOD_VEX_0F382E */
8411     { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8412   },
8413   {
8414     /* MOD_VEX_0F382F */
8415     { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8416   },
8417   {
8418     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8419     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8420     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8421   },
8422   {
8423     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8424     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8425   },
8426   {
8427     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8428     { Bad_Opcode },
8429     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8430   },
8431   {
8432     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8433     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8434   },
8435   {
8436     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8437     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8438   },
8439   {
8440     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8441     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8442   },
8443   {
8444     /* MOD_VEX_0F385A */
8445     { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8446   },
8447   {
8448     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8449     { Bad_Opcode },
8450     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8451   },
8452   {
8453     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8454     { Bad_Opcode },
8455     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8456   },
8457   {
8458     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8459     { Bad_Opcode },
8460     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8461   },
8462   {
8463     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8464     { Bad_Opcode },
8465     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8466   },
8467   {
8468     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8469     { Bad_Opcode },
8470     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8471   },
8472   {
8473     /* MOD_VEX_0F388C */
8474     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
8475   },
8476   {
8477     /* MOD_VEX_0F388E */
8478     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
8479   },
8480   {
8481     /* MOD_VEX_0F3A30_L_0 */
8482     { Bad_Opcode },
8483     { "kshiftr%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8484   },
8485   {
8486     /* MOD_VEX_0F3A31_L_0 */
8487     { Bad_Opcode },
8488     { "kshiftr%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8489   },
8490   {
8491     /* MOD_VEX_0F3A32_L_0 */
8492     { Bad_Opcode },
8493     { "kshiftl%BW",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8494   },
8495   {
8496     /* MOD_VEX_0F3A33_L_0 */
8497     { Bad_Opcode },
8498     { "kshiftl%DQ",     { MaskG, MaskE, Ib }, PREFIX_DATA },
8499   },
8500   {
8501     /* MOD_VEX_0FXOP_09_12 */
8502     { Bad_Opcode },
8503     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8504   },
8505
8506 #include "i386-dis-evex-mod.h"
8507 };
8508
8509 static const struct dis386 rm_table[][8] = {
8510   {
8511     /* RM_C6_REG_7 */
8512     { "xabort",         { Skip_MODRM, Ib }, 0 },
8513   },
8514   {
8515     /* RM_C7_REG_7 */
8516     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8517   },
8518   {
8519     /* RM_0F01_REG_0 */
8520     { "enclv",          { Skip_MODRM }, 0 },
8521     { "vmcall",         { Skip_MODRM }, 0 },
8522     { "vmlaunch",       { Skip_MODRM }, 0 },
8523     { "vmresume",       { Skip_MODRM }, 0 },
8524     { "vmxoff",         { Skip_MODRM }, 0 },
8525     { "pconfig",        { Skip_MODRM }, 0 },
8526   },
8527   {
8528     /* RM_0F01_REG_1 */
8529     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8530     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8531     { "clac",           { Skip_MODRM }, 0 },
8532     { "stac",           { Skip_MODRM }, 0 },
8533     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8534     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8535     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8536     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8537   },
8538   {
8539     /* RM_0F01_REG_2 */
8540     { "xgetbv",         { Skip_MODRM }, 0 },
8541     { "xsetbv",         { Skip_MODRM }, 0 },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { "vmfunc",         { Skip_MODRM }, 0 },
8545     { "xend",           { Skip_MODRM }, 0 },
8546     { "xtest",          { Skip_MODRM }, 0 },
8547     { "enclu",          { Skip_MODRM }, 0 },
8548   },
8549   {
8550     /* RM_0F01_REG_3 */
8551     { "vmrun",          { Skip_MODRM }, 0 },
8552     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8553     { "vmload",         { Skip_MODRM }, 0 },
8554     { "vmsave",         { Skip_MODRM }, 0 },
8555     { "stgi",           { Skip_MODRM }, 0 },
8556     { "clgi",           { Skip_MODRM }, 0 },
8557     { "skinit",         { Skip_MODRM }, 0 },
8558     { "invlpga",        { Skip_MODRM }, 0 },
8559   },
8560   {
8561     /* RM_0F01_REG_5_MOD_3 */
8562     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8563     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8564     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8565     { Bad_Opcode },
8566     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8567     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8568     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8569     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8570   },
8571   {
8572     /* RM_0F01_REG_7_MOD_3 */
8573     { "swapgs",         { Skip_MODRM }, 0  },
8574     { "rdtscp",         { Skip_MODRM }, 0  },
8575     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8576     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8577     { "clzero",         { Skip_MODRM }, 0  },
8578     { "rdpru",          { Skip_MODRM }, 0  },
8579     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8580     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8581   },
8582   {
8583     /* RM_0F1E_P_1_MOD_3_REG_7 */
8584     { "nopQ",           { Ev }, PREFIX_IGNORED },
8585     { "nopQ",           { Ev }, PREFIX_IGNORED },
8586     { "endbr64",        { Skip_MODRM }, 0 },
8587     { "endbr32",        { Skip_MODRM }, 0 },
8588     { "nopQ",           { Ev }, PREFIX_IGNORED },
8589     { "nopQ",           { Ev }, PREFIX_IGNORED },
8590     { "nopQ",           { Ev }, PREFIX_IGNORED },
8591     { "nopQ",           { Ev }, PREFIX_IGNORED },
8592   },
8593   {
8594     /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8595     { "hreset",         { Skip_MODRM, Ib }, 0 },
8596   },
8597   {
8598     /* RM_0FAE_REG_6_MOD_3 */
8599     { "mfence",         { Skip_MODRM }, 0 },
8600   },
8601   {
8602     /* RM_0FAE_REG_7_MOD_3 */
8603     { "sfence",         { Skip_MODRM }, 0 },
8604
8605   },
8606   {
8607     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8608     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8609   },
8610 };
8611
8612 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8613
8614 /* We use the high bit to indicate different name for the same
8615    prefix.  */
8616 #define REP_PREFIX      (0xf3 | 0x100)
8617 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8618 #define XRELEASE_PREFIX (0xf3 | 0x400)
8619 #define BND_PREFIX      (0xf2 | 0x400)
8620 #define NOTRACK_PREFIX  (0x3e | 0x100)
8621
8622 /* Remember if the current op is a jump instruction.  */
8623 static bfd_boolean op_is_jump = FALSE;
8624
8625 static int
8626 ckprefix (void)
8627 {
8628   int newrex, i, length;
8629   rex = 0;
8630   prefixes = 0;
8631   used_prefixes = 0;
8632   rex_used = 0;
8633   last_lock_prefix = -1;
8634   last_repz_prefix = -1;
8635   last_repnz_prefix = -1;
8636   last_data_prefix = -1;
8637   last_addr_prefix = -1;
8638   last_rex_prefix = -1;
8639   last_seg_prefix = -1;
8640   fwait_prefix = -1;
8641   active_seg_prefix = 0;
8642   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8643     all_prefixes[i] = 0;
8644   i = 0;
8645   length = 0;
8646   /* The maximum instruction length is 15bytes.  */
8647   while (length < MAX_CODE_LENGTH - 1)
8648     {
8649       FETCH_DATA (the_info, codep + 1);
8650       newrex = 0;
8651       switch (*codep)
8652         {
8653         /* REX prefixes family.  */
8654         case 0x40:
8655         case 0x41:
8656         case 0x42:
8657         case 0x43:
8658         case 0x44:
8659         case 0x45:
8660         case 0x46:
8661         case 0x47:
8662         case 0x48:
8663         case 0x49:
8664         case 0x4a:
8665         case 0x4b:
8666         case 0x4c:
8667         case 0x4d:
8668         case 0x4e:
8669         case 0x4f:
8670           if (address_mode == mode_64bit)
8671             newrex = *codep;
8672           else
8673             return 1;
8674           last_rex_prefix = i;
8675           break;
8676         case 0xf3:
8677           prefixes |= PREFIX_REPZ;
8678           last_repz_prefix = i;
8679           break;
8680         case 0xf2:
8681           prefixes |= PREFIX_REPNZ;
8682           last_repnz_prefix = i;
8683           break;
8684         case 0xf0:
8685           prefixes |= PREFIX_LOCK;
8686           last_lock_prefix = i;
8687           break;
8688         case 0x2e:
8689           prefixes |= PREFIX_CS;
8690           last_seg_prefix = i;
8691
8692           if (address_mode != mode_64bit)
8693             active_seg_prefix = PREFIX_CS;
8694
8695           break;
8696         case 0x36:
8697           prefixes |= PREFIX_SS;
8698           last_seg_prefix = i;
8699
8700           if (address_mode != mode_64bit)
8701             active_seg_prefix = PREFIX_SS;
8702
8703           break;
8704         case 0x3e:
8705           prefixes |= PREFIX_DS;
8706           last_seg_prefix = i;
8707
8708           if (address_mode != mode_64bit)
8709             active_seg_prefix = PREFIX_DS;
8710
8711           break;
8712         case 0x26:
8713           prefixes |= PREFIX_ES;
8714           last_seg_prefix = i;
8715
8716           if (address_mode != mode_64bit)
8717             active_seg_prefix = PREFIX_ES;
8718
8719           break;
8720         case 0x64:
8721           prefixes |= PREFIX_FS;
8722           last_seg_prefix = i;
8723           active_seg_prefix = PREFIX_FS;
8724           break;
8725         case 0x65:
8726           prefixes |= PREFIX_GS;
8727           last_seg_prefix = i;
8728           active_seg_prefix = PREFIX_GS;
8729           break;
8730         case 0x66:
8731           prefixes |= PREFIX_DATA;
8732           last_data_prefix = i;
8733           break;
8734         case 0x67:
8735           prefixes |= PREFIX_ADDR;
8736           last_addr_prefix = i;
8737           break;
8738         case FWAIT_OPCODE:
8739           /* fwait is really an instruction.  If there are prefixes
8740              before the fwait, they belong to the fwait, *not* to the
8741              following instruction.  */
8742           fwait_prefix = i;
8743           if (prefixes || rex)
8744             {
8745               prefixes |= PREFIX_FWAIT;
8746               codep++;
8747               /* This ensures that the previous REX prefixes are noticed
8748                  as unused prefixes, as in the return case below.  */
8749               rex_used = rex;
8750               return 1;
8751             }
8752           prefixes = PREFIX_FWAIT;
8753           break;
8754         default:
8755           return 1;
8756         }
8757       /* Rex is ignored when followed by another prefix.  */
8758       if (rex)
8759         {
8760           rex_used = rex;
8761           return 1;
8762         }
8763       if (*codep != FWAIT_OPCODE)
8764         all_prefixes[i++] = *codep;
8765       rex = newrex;
8766       codep++;
8767       length++;
8768     }
8769   return 0;
8770 }
8771
8772 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8773    prefix byte.  */
8774
8775 static const char *
8776 prefix_name (int pref, int sizeflag)
8777 {
8778   static const char *rexes [16] =
8779     {
8780       "rex",            /* 0x40 */
8781       "rex.B",          /* 0x41 */
8782       "rex.X",          /* 0x42 */
8783       "rex.XB",         /* 0x43 */
8784       "rex.R",          /* 0x44 */
8785       "rex.RB",         /* 0x45 */
8786       "rex.RX",         /* 0x46 */
8787       "rex.RXB",        /* 0x47 */
8788       "rex.W",          /* 0x48 */
8789       "rex.WB",         /* 0x49 */
8790       "rex.WX",         /* 0x4a */
8791       "rex.WXB",        /* 0x4b */
8792       "rex.WR",         /* 0x4c */
8793       "rex.WRB",        /* 0x4d */
8794       "rex.WRX",        /* 0x4e */
8795       "rex.WRXB",       /* 0x4f */
8796     };
8797
8798   switch (pref)
8799     {
8800     /* REX prefixes family.  */
8801     case 0x40:
8802     case 0x41:
8803     case 0x42:
8804     case 0x43:
8805     case 0x44:
8806     case 0x45:
8807     case 0x46:
8808     case 0x47:
8809     case 0x48:
8810     case 0x49:
8811     case 0x4a:
8812     case 0x4b:
8813     case 0x4c:
8814     case 0x4d:
8815     case 0x4e:
8816     case 0x4f:
8817       return rexes [pref - 0x40];
8818     case 0xf3:
8819       return "repz";
8820     case 0xf2:
8821       return "repnz";
8822     case 0xf0:
8823       return "lock";
8824     case 0x2e:
8825       return "cs";
8826     case 0x36:
8827       return "ss";
8828     case 0x3e:
8829       return "ds";
8830     case 0x26:
8831       return "es";
8832     case 0x64:
8833       return "fs";
8834     case 0x65:
8835       return "gs";
8836     case 0x66:
8837       return (sizeflag & DFLAG) ? "data16" : "data32";
8838     case 0x67:
8839       if (address_mode == mode_64bit)
8840         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8841       else
8842         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8843     case FWAIT_OPCODE:
8844       return "fwait";
8845     case REP_PREFIX:
8846       return "rep";
8847     case XACQUIRE_PREFIX:
8848       return "xacquire";
8849     case XRELEASE_PREFIX:
8850       return "xrelease";
8851     case BND_PREFIX:
8852       return "bnd";
8853     case NOTRACK_PREFIX:
8854       return "notrack";
8855     default:
8856       return NULL;
8857     }
8858 }
8859
8860 static char op_out[MAX_OPERANDS][100];
8861 static int op_ad, op_index[MAX_OPERANDS];
8862 static int two_source_ops;
8863 static bfd_vma op_address[MAX_OPERANDS];
8864 static bfd_vma op_riprel[MAX_OPERANDS];
8865 static bfd_vma start_pc;
8866
8867 /*
8868  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8869  *   (see topic "Redundant prefixes" in the "Differences from 8086"
8870  *   section of the "Virtual 8086 Mode" chapter.)
8871  * 'pc' should be the address of this instruction, it will
8872  *   be used to print the target address if this is a relative jump or call
8873  * The function returns the length of this instruction in bytes.
8874  */
8875
8876 static char intel_syntax;
8877 static char intel_mnemonic = !SYSV386_COMPAT;
8878 static char open_char;
8879 static char close_char;
8880 static char separator_char;
8881 static char scale_char;
8882
8883 enum x86_64_isa
8884 {
8885   amd64 = 1,
8886   intel64
8887 };
8888
8889 static enum x86_64_isa isa64;
8890
8891 /* Here for backwards compatibility.  When gdb stops using
8892    print_insn_i386_att and print_insn_i386_intel these functions can
8893    disappear, and print_insn_i386 be merged into print_insn.  */
8894 int
8895 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8896 {
8897   intel_syntax = 0;
8898
8899   return print_insn (pc, info);
8900 }
8901
8902 int
8903 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8904 {
8905   intel_syntax = 1;
8906
8907   return print_insn (pc, info);
8908 }
8909
8910 int
8911 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8912 {
8913   intel_syntax = -1;
8914
8915   return print_insn (pc, info);
8916 }
8917
8918 void
8919 print_i386_disassembler_options (FILE *stream)
8920 {
8921   fprintf (stream, _("\n\
8922 The following i386/x86-64 specific disassembler options are supported for use\n\
8923 with the -M switch (multiple options should be separated by commas):\n"));
8924
8925   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8926   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8927   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8928   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8929   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8930   fprintf (stream, _("  att-mnemonic\n"
8931                      "              Display instruction in AT&T mnemonic\n"));
8932   fprintf (stream, _("  intel-mnemonic\n"
8933                      "              Display instruction in Intel mnemonic\n"));
8934   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8935   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8936   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8937   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8938   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8939   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8940   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8941   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8942 }
8943
8944 /* Bad opcode.  */
8945 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8946
8947 /* Get a pointer to struct dis386 with a valid name.  */
8948
8949 static const struct dis386 *
8950 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8951 {
8952   int vindex, vex_table_index;
8953
8954   if (dp->name != NULL)
8955     return dp;
8956
8957   switch (dp->op[0].bytemode)
8958     {
8959     case USE_REG_TABLE:
8960       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
8961       break;
8962
8963     case USE_MOD_TABLE:
8964       vindex = modrm.mod == 0x3 ? 1 : 0;
8965       dp = &mod_table[dp->op[1].bytemode][vindex];
8966       break;
8967
8968     case USE_RM_TABLE:
8969       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
8970       break;
8971
8972     case USE_PREFIX_TABLE:
8973       if (need_vex)
8974         {
8975           /* The prefix in VEX is implicit.  */
8976           switch (vex.prefix)
8977             {
8978             case 0:
8979               vindex = 0;
8980               break;
8981             case REPE_PREFIX_OPCODE:
8982               vindex = 1;
8983               break;
8984             case DATA_PREFIX_OPCODE:
8985               vindex = 2;
8986               break;
8987             case REPNE_PREFIX_OPCODE:
8988               vindex = 3;
8989               break;
8990             default:
8991               abort ();
8992               break;
8993             }
8994         }
8995       else
8996         {
8997           int last_prefix = -1;
8998           int prefix = 0;
8999           vindex = 0;
9000           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9001              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9002              last one wins.  */
9003           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9004             {
9005               if (last_repz_prefix > last_repnz_prefix)
9006                 {
9007                   vindex = 1;
9008                   prefix = PREFIX_REPZ;
9009                   last_prefix = last_repz_prefix;
9010                 }
9011               else
9012                 {
9013                   vindex = 3;
9014                   prefix = PREFIX_REPNZ;
9015                   last_prefix = last_repnz_prefix;
9016                 }
9017
9018               /* Check if prefix should be ignored.  */
9019               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9020                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9021                    & prefix) != 0
9022                   && !prefix_table[dp->op[1].bytemode][vindex].name)
9023                 vindex = 0;
9024             }
9025
9026           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9027             {
9028               vindex = 2;
9029               prefix = PREFIX_DATA;
9030               last_prefix = last_data_prefix;
9031             }
9032
9033           if (vindex != 0)
9034             {
9035               used_prefixes |= prefix;
9036               all_prefixes[last_prefix] = 0;
9037             }
9038         }
9039       dp = &prefix_table[dp->op[1].bytemode][vindex];
9040       break;
9041
9042     case USE_X86_64_TABLE:
9043       vindex = address_mode == mode_64bit ? 1 : 0;
9044       dp = &x86_64_table[dp->op[1].bytemode][vindex];
9045       break;
9046
9047     case USE_3BYTE_TABLE:
9048       FETCH_DATA (info, codep + 2);
9049       vindex = *codep++;
9050       dp = &three_byte_table[dp->op[1].bytemode][vindex];
9051       end_codep = codep;
9052       modrm.mod = (*codep >> 6) & 3;
9053       modrm.reg = (*codep >> 3) & 7;
9054       modrm.rm = *codep & 7;
9055       break;
9056
9057     case USE_VEX_LEN_TABLE:
9058       if (!need_vex)
9059         abort ();
9060
9061       switch (vex.length)
9062         {
9063         case 128:
9064           vindex = 0;
9065           break;
9066         case 256:
9067           vindex = 1;
9068           break;
9069         default:
9070           abort ();
9071           break;
9072         }
9073
9074       dp = &vex_len_table[dp->op[1].bytemode][vindex];
9075       break;
9076
9077     case USE_EVEX_LEN_TABLE:
9078       if (!vex.evex)
9079         abort ();
9080
9081       switch (vex.length)
9082         {
9083         case 128:
9084           vindex = 0;
9085           break;
9086         case 256:
9087           vindex = 1;
9088           break;
9089         case 512:
9090           vindex = 2;
9091           break;
9092         default:
9093           abort ();
9094           break;
9095         }
9096
9097       dp = &evex_len_table[dp->op[1].bytemode][vindex];
9098       break;
9099
9100     case USE_XOP_8F_TABLE:
9101       FETCH_DATA (info, codep + 3);
9102       rex = ~(*codep >> 5) & 0x7;
9103
9104       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
9105       switch ((*codep & 0x1f))
9106         {
9107         default:
9108           dp = &bad_opcode;
9109           return dp;
9110         case 0x8:
9111           vex_table_index = XOP_08;
9112           break;
9113         case 0x9:
9114           vex_table_index = XOP_09;
9115           break;
9116         case 0xa:
9117           vex_table_index = XOP_0A;
9118           break;
9119         }
9120       codep++;
9121       vex.w = *codep & 0x80;
9122       if (vex.w && address_mode == mode_64bit)
9123         rex |= REX_W;
9124
9125       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9126       if (address_mode != mode_64bit)
9127         {
9128           /* In 16/32-bit mode REX_B is silently ignored.  */
9129           rex &= ~REX_B;
9130         }
9131
9132       vex.length = (*codep & 0x4) ? 256 : 128;
9133       switch ((*codep & 0x3))
9134         {
9135         case 0:
9136           break;
9137         case 1:
9138           vex.prefix = DATA_PREFIX_OPCODE;
9139           break;
9140         case 2:
9141           vex.prefix = REPE_PREFIX_OPCODE;
9142           break;
9143         case 3:
9144           vex.prefix = REPNE_PREFIX_OPCODE;
9145           break;
9146         }
9147       need_vex = 1;
9148       codep++;
9149       vindex = *codep++;
9150       dp = &xop_table[vex_table_index][vindex];
9151
9152       end_codep = codep;
9153       FETCH_DATA (info, codep + 1);
9154       modrm.mod = (*codep >> 6) & 3;
9155       modrm.reg = (*codep >> 3) & 7;
9156       modrm.rm = *codep & 7;
9157
9158       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9159          having to decode the bits for every otherwise valid encoding.  */
9160       if (vex.prefix)
9161         return &bad_opcode;
9162       break;
9163
9164     case USE_VEX_C4_TABLE:
9165       /* VEX prefix.  */
9166       FETCH_DATA (info, codep + 3);
9167       rex = ~(*codep >> 5) & 0x7;
9168       switch ((*codep & 0x1f))
9169         {
9170         default:
9171           dp = &bad_opcode;
9172           return dp;
9173         case 0x1:
9174           vex_table_index = VEX_0F;
9175           break;
9176         case 0x2:
9177           vex_table_index = VEX_0F38;
9178           break;
9179         case 0x3:
9180           vex_table_index = VEX_0F3A;
9181           break;
9182         }
9183       codep++;
9184       vex.w = *codep & 0x80;
9185       if (address_mode == mode_64bit)
9186         {
9187           if (vex.w)
9188             rex |= REX_W;
9189         }
9190       else
9191         {
9192           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9193              is ignored, other REX bits are 0 and the highest bit in
9194              VEX.vvvv is also ignored (but we mustn't clear it here).  */
9195           rex = 0;
9196         }
9197       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9198       vex.length = (*codep & 0x4) ? 256 : 128;
9199       switch ((*codep & 0x3))
9200         {
9201         case 0:
9202           break;
9203         case 1:
9204           vex.prefix = DATA_PREFIX_OPCODE;
9205           break;
9206         case 2:
9207           vex.prefix = REPE_PREFIX_OPCODE;
9208           break;
9209         case 3:
9210           vex.prefix = REPNE_PREFIX_OPCODE;
9211           break;
9212         }
9213       need_vex = 1;
9214       codep++;
9215       vindex = *codep++;
9216       dp = &vex_table[vex_table_index][vindex];
9217       end_codep = codep;
9218       /* There is no MODRM byte for VEX0F 77.  */
9219       if (vex_table_index != VEX_0F || vindex != 0x77)
9220         {
9221           FETCH_DATA (info, codep + 1);
9222           modrm.mod = (*codep >> 6) & 3;
9223           modrm.reg = (*codep >> 3) & 7;
9224           modrm.rm = *codep & 7;
9225         }
9226       break;
9227
9228     case USE_VEX_C5_TABLE:
9229       /* VEX prefix.  */
9230       FETCH_DATA (info, codep + 2);
9231       rex = (*codep & 0x80) ? 0 : REX_R;
9232
9233       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9234          VEX.vvvv is 1.  */
9235       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9236       vex.length = (*codep & 0x4) ? 256 : 128;
9237       switch ((*codep & 0x3))
9238         {
9239         case 0:
9240           break;
9241         case 1:
9242           vex.prefix = DATA_PREFIX_OPCODE;
9243           break;
9244         case 2:
9245           vex.prefix = REPE_PREFIX_OPCODE;
9246           break;
9247         case 3:
9248           vex.prefix = REPNE_PREFIX_OPCODE;
9249           break;
9250         }
9251       need_vex = 1;
9252       codep++;
9253       vindex = *codep++;
9254       dp = &vex_table[dp->op[1].bytemode][vindex];
9255       end_codep = codep;
9256       /* There is no MODRM byte for VEX 77.  */
9257       if (vindex != 0x77)
9258         {
9259           FETCH_DATA (info, codep + 1);
9260           modrm.mod = (*codep >> 6) & 3;
9261           modrm.reg = (*codep >> 3) & 7;
9262           modrm.rm = *codep & 7;
9263         }
9264       break;
9265
9266     case USE_VEX_W_TABLE:
9267       if (!need_vex)
9268         abort ();
9269
9270       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9271       break;
9272
9273     case USE_EVEX_TABLE:
9274       two_source_ops = 0;
9275       /* EVEX prefix.  */
9276       vex.evex = 1;
9277       FETCH_DATA (info, codep + 4);
9278       /* The first byte after 0x62.  */
9279       rex = ~(*codep >> 5) & 0x7;
9280       vex.r = *codep & 0x10;
9281       switch ((*codep & 0xf))
9282         {
9283         default:
9284           return &bad_opcode;
9285         case 0x1:
9286           vex_table_index = EVEX_0F;
9287           break;
9288         case 0x2:
9289           vex_table_index = EVEX_0F38;
9290           break;
9291         case 0x3:
9292           vex_table_index = EVEX_0F3A;
9293           break;
9294         }
9295
9296       /* The second byte after 0x62.  */
9297       codep++;
9298       vex.w = *codep & 0x80;
9299       if (vex.w && address_mode == mode_64bit)
9300         rex |= REX_W;
9301
9302       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9303
9304       /* The U bit.  */
9305       if (!(*codep & 0x4))
9306         return &bad_opcode;
9307
9308       switch ((*codep & 0x3))
9309         {
9310         case 0:
9311           break;
9312         case 1:
9313           vex.prefix = DATA_PREFIX_OPCODE;
9314           break;
9315         case 2:
9316           vex.prefix = REPE_PREFIX_OPCODE;
9317           break;
9318         case 3:
9319           vex.prefix = REPNE_PREFIX_OPCODE;
9320           break;
9321         }
9322
9323       /* The third byte after 0x62.  */
9324       codep++;
9325
9326       /* Remember the static rounding bits.  */
9327       vex.ll = (*codep >> 5) & 3;
9328       vex.b = (*codep & 0x10) != 0;
9329
9330       vex.v = *codep & 0x8;
9331       vex.mask_register_specifier = *codep & 0x7;
9332       vex.zeroing = *codep & 0x80;
9333
9334       if (address_mode != mode_64bit)
9335         {
9336           /* In 16/32-bit mode silently ignore following bits.  */
9337           rex &= ~REX_B;
9338           vex.r = 1;
9339           vex.v = 1;
9340         }
9341
9342       need_vex = 1;
9343       codep++;
9344       vindex = *codep++;
9345       dp = &evex_table[vex_table_index][vindex];
9346       end_codep = codep;
9347       FETCH_DATA (info, codep + 1);
9348       modrm.mod = (*codep >> 6) & 3;
9349       modrm.reg = (*codep >> 3) & 7;
9350       modrm.rm = *codep & 7;
9351
9352       /* Set vector length.  */
9353       if (modrm.mod == 3 && vex.b)
9354         vex.length = 512;
9355       else
9356         {
9357           switch (vex.ll)
9358             {
9359             case 0x0:
9360               vex.length = 128;
9361               break;
9362             case 0x1:
9363               vex.length = 256;
9364               break;
9365             case 0x2:
9366               vex.length = 512;
9367               break;
9368             default:
9369               return &bad_opcode;
9370             }
9371         }
9372       break;
9373
9374     case 0:
9375       dp = &bad_opcode;
9376       break;
9377
9378     default:
9379       abort ();
9380     }
9381
9382   if (dp->name != NULL)
9383     return dp;
9384   else
9385     return get_valid_dis386 (dp, info);
9386 }
9387
9388 static void
9389 get_sib (disassemble_info *info, int sizeflag)
9390 {
9391   /* If modrm.mod == 3, operand must be register.  */
9392   if (need_modrm
9393       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9394       && modrm.mod != 3
9395       && modrm.rm == 4)
9396     {
9397       FETCH_DATA (info, codep + 2);
9398       sib.index = (codep [1] >> 3) & 7;
9399       sib.scale = (codep [1] >> 6) & 3;
9400       sib.base = codep [1] & 7;
9401     }
9402 }
9403
9404 static int
9405 print_insn (bfd_vma pc, disassemble_info *info)
9406 {
9407   const struct dis386 *dp;
9408   int i;
9409   char *op_txt[MAX_OPERANDS];
9410   int needcomma;
9411   int sizeflag, orig_sizeflag;
9412   const char *p;
9413   struct dis_private priv;
9414   int prefix_length;
9415
9416   priv.orig_sizeflag = AFLAG | DFLAG;
9417   if ((info->mach & bfd_mach_i386_i386) != 0)
9418     address_mode = mode_32bit;
9419   else if (info->mach == bfd_mach_i386_i8086)
9420     {
9421       address_mode = mode_16bit;
9422       priv.orig_sizeflag = 0;
9423     }
9424   else
9425     address_mode = mode_64bit;
9426
9427   if (intel_syntax == (char) -1)
9428     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9429
9430   for (p = info->disassembler_options; p != NULL; )
9431     {
9432       if (CONST_STRNEQ (p, "amd64"))
9433         isa64 = amd64;
9434       else if (CONST_STRNEQ (p, "intel64"))
9435         isa64 = intel64;
9436       else if (CONST_STRNEQ (p, "x86-64"))
9437         {
9438           address_mode = mode_64bit;
9439           priv.orig_sizeflag |= AFLAG | DFLAG;
9440         }
9441       else if (CONST_STRNEQ (p, "i386"))
9442         {
9443           address_mode = mode_32bit;
9444           priv.orig_sizeflag |= AFLAG | DFLAG;
9445         }
9446       else if (CONST_STRNEQ (p, "i8086"))
9447         {
9448           address_mode = mode_16bit;
9449           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9450         }
9451       else if (CONST_STRNEQ (p, "intel"))
9452         {
9453           intel_syntax = 1;
9454           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9455             intel_mnemonic = 1;
9456         }
9457       else if (CONST_STRNEQ (p, "att"))
9458         {
9459           intel_syntax = 0;
9460           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9461             intel_mnemonic = 0;
9462         }
9463       else if (CONST_STRNEQ (p, "addr"))
9464         {
9465           if (address_mode == mode_64bit)
9466             {
9467               if (p[4] == '3' && p[5] == '2')
9468                 priv.orig_sizeflag &= ~AFLAG;
9469               else if (p[4] == '6' && p[5] == '4')
9470                 priv.orig_sizeflag |= AFLAG;
9471             }
9472           else
9473             {
9474               if (p[4] == '1' && p[5] == '6')
9475                 priv.orig_sizeflag &= ~AFLAG;
9476               else if (p[4] == '3' && p[5] == '2')
9477                 priv.orig_sizeflag |= AFLAG;
9478             }
9479         }
9480       else if (CONST_STRNEQ (p, "data"))
9481         {
9482           if (p[4] == '1' && p[5] == '6')
9483             priv.orig_sizeflag &= ~DFLAG;
9484           else if (p[4] == '3' && p[5] == '2')
9485             priv.orig_sizeflag |= DFLAG;
9486         }
9487       else if (CONST_STRNEQ (p, "suffix"))
9488         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9489
9490       p = strchr (p, ',');
9491       if (p != NULL)
9492         p++;
9493     }
9494
9495   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9496     {
9497       (*info->fprintf_func) (info->stream,
9498                              _("64-bit address is disabled"));
9499       return -1;
9500     }
9501
9502   if (intel_syntax)
9503     {
9504       names64 = intel_names64;
9505       names32 = intel_names32;
9506       names16 = intel_names16;
9507       names8 = intel_names8;
9508       names8rex = intel_names8rex;
9509       names_seg = intel_names_seg;
9510       names_mm = intel_names_mm;
9511       names_bnd = intel_names_bnd;
9512       names_xmm = intel_names_xmm;
9513       names_ymm = intel_names_ymm;
9514       names_zmm = intel_names_zmm;
9515       names_tmm = intel_names_tmm;
9516       index64 = intel_index64;
9517       index32 = intel_index32;
9518       names_mask = intel_names_mask;
9519       index16 = intel_index16;
9520       open_char = '[';
9521       close_char = ']';
9522       separator_char = '+';
9523       scale_char = '*';
9524     }
9525   else
9526     {
9527       names64 = att_names64;
9528       names32 = att_names32;
9529       names16 = att_names16;
9530       names8 = att_names8;
9531       names8rex = att_names8rex;
9532       names_seg = att_names_seg;
9533       names_mm = att_names_mm;
9534       names_bnd = att_names_bnd;
9535       names_xmm = att_names_xmm;
9536       names_ymm = att_names_ymm;
9537       names_zmm = att_names_zmm;
9538       names_tmm = att_names_tmm;
9539       index64 = att_index64;
9540       index32 = att_index32;
9541       names_mask = att_names_mask;
9542       index16 = att_index16;
9543       open_char = '(';
9544       close_char =  ')';
9545       separator_char = ',';
9546       scale_char = ',';
9547     }
9548
9549   /* The output looks better if we put 7 bytes on a line, since that
9550      puts most long word instructions on a single line.  Use 8 bytes
9551      for Intel L1OM.  */
9552   if ((info->mach & bfd_mach_l1om) != 0)
9553     info->bytes_per_line = 8;
9554   else
9555     info->bytes_per_line = 7;
9556
9557   info->private_data = &priv;
9558   priv.max_fetched = priv.the_buffer;
9559   priv.insn_start = pc;
9560
9561   obuf[0] = 0;
9562   for (i = 0; i < MAX_OPERANDS; ++i)
9563     {
9564       op_out[i][0] = 0;
9565       op_index[i] = -1;
9566     }
9567
9568   the_info = info;
9569   start_pc = pc;
9570   start_codep = priv.the_buffer;
9571   codep = priv.the_buffer;
9572
9573   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9574     {
9575       const char *name;
9576
9577       /* Getting here means we tried for data but didn't get it.  That
9578          means we have an incomplete instruction of some sort.  Just
9579          print the first byte as a prefix or a .byte pseudo-op.  */
9580       if (codep > priv.the_buffer)
9581         {
9582           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9583           if (name != NULL)
9584             (*info->fprintf_func) (info->stream, "%s", name);
9585           else
9586             {
9587               /* Just print the first byte as a .byte instruction.  */
9588               (*info->fprintf_func) (info->stream, ".byte 0x%x",
9589                                      (unsigned int) priv.the_buffer[0]);
9590             }
9591
9592           return 1;
9593         }
9594
9595       return -1;
9596     }
9597
9598   obufp = obuf;
9599   sizeflag = priv.orig_sizeflag;
9600
9601   if (!ckprefix () || rex_used)
9602     {
9603       /* Too many prefixes or unused REX prefixes.  */
9604       for (i = 0;
9605            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9606            i++)
9607         (*info->fprintf_func) (info->stream, "%s%s",
9608                                i == 0 ? "" : " ",
9609                                prefix_name (all_prefixes[i], sizeflag));
9610       return i;
9611     }
9612
9613   insn_codep = codep;
9614
9615   FETCH_DATA (info, codep + 1);
9616   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9617
9618   if (((prefixes & PREFIX_FWAIT)
9619        && ((*codep < 0xd8) || (*codep > 0xdf))))
9620     {
9621       /* Handle prefixes before fwait.  */
9622       for (i = 0; i < fwait_prefix && all_prefixes[i];
9623            i++)
9624         (*info->fprintf_func) (info->stream, "%s ",
9625                                prefix_name (all_prefixes[i], sizeflag));
9626       (*info->fprintf_func) (info->stream, "fwait");
9627       return i + 1;
9628     }
9629
9630   if (*codep == 0x0f)
9631     {
9632       unsigned char threebyte;
9633
9634       codep++;
9635       FETCH_DATA (info, codep + 1);
9636       threebyte = *codep;
9637       dp = &dis386_twobyte[threebyte];
9638       need_modrm = twobyte_has_modrm[threebyte];
9639       codep++;
9640     }
9641   else
9642     {
9643       dp = &dis386[*codep];
9644       need_modrm = onebyte_has_modrm[*codep];
9645       codep++;
9646     }
9647
9648   /* Save sizeflag for printing the extra prefixes later before updating
9649      it for mnemonic and operand processing.  The prefix names depend
9650      only on the address mode.  */
9651   orig_sizeflag = sizeflag;
9652   if (prefixes & PREFIX_ADDR)
9653     sizeflag ^= AFLAG;
9654   if ((prefixes & PREFIX_DATA))
9655     sizeflag ^= DFLAG;
9656
9657   end_codep = codep;
9658   if (need_modrm)
9659     {
9660       FETCH_DATA (info, codep + 1);
9661       modrm.mod = (*codep >> 6) & 3;
9662       modrm.reg = (*codep >> 3) & 7;
9663       modrm.rm = *codep & 7;
9664     }
9665   else
9666     memset (&modrm, 0, sizeof (modrm));
9667
9668   need_vex = 0;
9669   memset (&vex, 0, sizeof (vex));
9670
9671   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9672     {
9673       get_sib (info, sizeflag);
9674       dofloat (sizeflag);
9675     }
9676   else
9677     {
9678       dp = get_valid_dis386 (dp, info);
9679       if (dp != NULL && putop (dp->name, sizeflag) == 0)
9680         {
9681           get_sib (info, sizeflag);
9682           for (i = 0; i < MAX_OPERANDS; ++i)
9683             {
9684               obufp = op_out[i];
9685               op_ad = MAX_OPERANDS - 1 - i;
9686               if (dp->op[i].rtn)
9687                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9688               /* For EVEX instruction after the last operand masking
9689                  should be printed.  */
9690               if (i == 0 && vex.evex)
9691                 {
9692                   /* Don't print {%k0}.  */
9693                   if (vex.mask_register_specifier)
9694                     {
9695                       oappend ("{");
9696                       oappend (names_mask[vex.mask_register_specifier]);
9697                       oappend ("}");
9698                     }
9699                   if (vex.zeroing)
9700                     oappend ("{z}");
9701                 }
9702             }
9703         }
9704     }
9705
9706   /* Clear instruction information.  */
9707   if (the_info)
9708     {
9709       the_info->insn_info_valid = 0;
9710       the_info->branch_delay_insns = 0;
9711       the_info->data_size = 0;
9712       the_info->insn_type = dis_noninsn;
9713       the_info->target = 0;
9714       the_info->target2 = 0;
9715     }
9716
9717   /* Reset jump operation indicator.  */
9718   op_is_jump = FALSE;
9719
9720   {
9721     int jump_detection = 0;
9722
9723     /* Extract flags.  */
9724     for (i = 0; i < MAX_OPERANDS; ++i)
9725       {
9726         if ((dp->op[i].rtn == OP_J)
9727             || (dp->op[i].rtn == OP_indirE))
9728           jump_detection |= 1;
9729         else if ((dp->op[i].rtn == BND_Fixup)
9730                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9731           jump_detection |= 2;
9732         else if ((dp->op[i].bytemode == cond_jump_mode)
9733                  || (dp->op[i].bytemode == loop_jcxz_mode))
9734           jump_detection |= 4;
9735       }
9736
9737     /* Determine if this is a jump or branch.  */
9738     if ((jump_detection & 0x3) == 0x3)
9739       {
9740         op_is_jump = TRUE;
9741         if (jump_detection & 0x4)
9742           the_info->insn_type = dis_condbranch;
9743         else
9744           the_info->insn_type =
9745             (dp->name && !strncmp(dp->name, "call", 4))
9746             ? dis_jsr : dis_branch;
9747       }
9748   }
9749
9750   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9751      are all 0s in inverted form.  */
9752   if (need_vex && vex.register_specifier != 0)
9753     {
9754       (*info->fprintf_func) (info->stream, "(bad)");
9755       return end_codep - priv.the_buffer;
9756     }
9757
9758   switch (dp->prefix_requirement)
9759     {
9760     case PREFIX_DATA:
9761       /* If only the data prefix is marked as mandatory, its absence renders
9762          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9763       if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9764         {
9765           (*info->fprintf_func) (info->stream, "(bad)");
9766           return end_codep - priv.the_buffer;
9767         }
9768       used_prefixes |= PREFIX_DATA;
9769       /* Fall through.  */
9770     case PREFIX_OPCODE:
9771       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9772          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9773          used by putop and MMX/SSE operand and may be overridden by the
9774          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9775          separately.  */
9776       if (((need_vex
9777             ? vex.prefix == REPE_PREFIX_OPCODE
9778               || vex.prefix == REPNE_PREFIX_OPCODE
9779             : (prefixes
9780                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9781            && (used_prefixes
9782                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9783           || (((need_vex
9784                 ? vex.prefix == DATA_PREFIX_OPCODE
9785                 : ((prefixes
9786                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9787                    == PREFIX_DATA))
9788                && (used_prefixes & PREFIX_DATA) == 0))
9789           || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9790               && !vex.w != !(used_prefixes & PREFIX_DATA)))
9791         {
9792           (*info->fprintf_func) (info->stream, "(bad)");
9793           return end_codep - priv.the_buffer;
9794         }
9795       break;
9796
9797     case PREFIX_IGNORED:
9798       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9799          origins in all_prefixes.  */
9800       used_prefixes &= ~PREFIX_OPCODE;
9801       if (last_data_prefix >= 0)
9802         all_prefixes[last_repz_prefix] = 0x66;
9803       if (last_repz_prefix >= 0)
9804         all_prefixes[last_repz_prefix] = 0xf3;
9805       if (last_repnz_prefix >= 0)
9806         all_prefixes[last_repnz_prefix] = 0xf2;
9807       break;
9808     }
9809
9810   /* Check if the REX prefix is used.  */
9811   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9812     all_prefixes[last_rex_prefix] = 0;
9813
9814   /* Check if the SEG prefix is used.  */
9815   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9816                    | PREFIX_FS | PREFIX_GS)) != 0
9817       && (used_prefixes & active_seg_prefix) != 0)
9818     all_prefixes[last_seg_prefix] = 0;
9819
9820   /* Check if the ADDR prefix is used.  */
9821   if ((prefixes & PREFIX_ADDR) != 0
9822       && (used_prefixes & PREFIX_ADDR) != 0)
9823     all_prefixes[last_addr_prefix] = 0;
9824
9825   /* Check if the DATA prefix is used.  */
9826   if ((prefixes & PREFIX_DATA) != 0
9827       && (used_prefixes & PREFIX_DATA) != 0
9828       && !need_vex)
9829     all_prefixes[last_data_prefix] = 0;
9830
9831   /* Print the extra prefixes.  */
9832   prefix_length = 0;
9833   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9834     if (all_prefixes[i])
9835       {
9836         const char *name;
9837         name = prefix_name (all_prefixes[i], orig_sizeflag);
9838         if (name == NULL)
9839           abort ();
9840         prefix_length += strlen (name) + 1;
9841         (*info->fprintf_func) (info->stream, "%s ", name);
9842       }
9843
9844   /* Check maximum code length.  */
9845   if ((codep - start_codep) > MAX_CODE_LENGTH)
9846     {
9847       (*info->fprintf_func) (info->stream, "(bad)");
9848       return MAX_CODE_LENGTH;
9849     }
9850
9851   obufp = mnemonicendp;
9852   for (i = strlen (obuf) + prefix_length; i < 6; i++)
9853     oappend (" ");
9854   oappend (" ");
9855   (*info->fprintf_func) (info->stream, "%s", obuf);
9856
9857   /* The enter and bound instructions are printed with operands in the same
9858      order as the intel book; everything else is printed in reverse order.  */
9859   if (intel_syntax || two_source_ops)
9860     {
9861       bfd_vma riprel;
9862
9863       for (i = 0; i < MAX_OPERANDS; ++i)
9864         op_txt[i] = op_out[i];
9865
9866       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9867           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9868         {
9869           op_txt[2] = op_out[3];
9870           op_txt[3] = op_out[2];
9871         }
9872
9873       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9874         {
9875           op_ad = op_index[i];
9876           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9877           op_index[MAX_OPERANDS - 1 - i] = op_ad;
9878           riprel = op_riprel[i];
9879           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9880           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9881         }
9882     }
9883   else
9884     {
9885       for (i = 0; i < MAX_OPERANDS; ++i)
9886         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9887     }
9888
9889   needcomma = 0;
9890   for (i = 0; i < MAX_OPERANDS; ++i)
9891     if (*op_txt[i])
9892       {
9893         if (needcomma)
9894           (*info->fprintf_func) (info->stream, ",");
9895         if (op_index[i] != -1 && !op_riprel[i])
9896           {
9897             bfd_vma target = (bfd_vma) op_address[op_index[i]];
9898
9899             if (the_info && op_is_jump)
9900               {
9901                 the_info->insn_info_valid = 1;
9902                 the_info->branch_delay_insns = 0;
9903                 the_info->data_size = 0;
9904                 the_info->target = target;
9905                 the_info->target2 = 0;
9906               }
9907             (*info->print_address_func) (target, info);
9908           }
9909         else
9910           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9911         needcomma = 1;
9912       }
9913
9914   for (i = 0; i < MAX_OPERANDS; i++)
9915     if (op_index[i] != -1 && op_riprel[i])
9916       {
9917         (*info->fprintf_func) (info->stream, "        # ");
9918         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9919                                                 + op_address[op_index[i]]), info);
9920         break;
9921       }
9922   return codep - priv.the_buffer;
9923 }
9924
9925 static const char *float_mem[] = {
9926   /* d8 */
9927   "fadd{s|}",
9928   "fmul{s|}",
9929   "fcom{s|}",
9930   "fcomp{s|}",
9931   "fsub{s|}",
9932   "fsubr{s|}",
9933   "fdiv{s|}",
9934   "fdivr{s|}",
9935   /* d9 */
9936   "fld{s|}",
9937   "(bad)",
9938   "fst{s|}",
9939   "fstp{s|}",
9940   "fldenv{C|C}",
9941   "fldcw",
9942   "fNstenv{C|C}",
9943   "fNstcw",
9944   /* da */
9945   "fiadd{l|}",
9946   "fimul{l|}",
9947   "ficom{l|}",
9948   "ficomp{l|}",
9949   "fisub{l|}",
9950   "fisubr{l|}",
9951   "fidiv{l|}",
9952   "fidivr{l|}",
9953   /* db */
9954   "fild{l|}",
9955   "fisttp{l|}",
9956   "fist{l|}",
9957   "fistp{l|}",
9958   "(bad)",
9959   "fld{t|}",
9960   "(bad)",
9961   "fstp{t|}",
9962   /* dc */
9963   "fadd{l|}",
9964   "fmul{l|}",
9965   "fcom{l|}",
9966   "fcomp{l|}",
9967   "fsub{l|}",
9968   "fsubr{l|}",
9969   "fdiv{l|}",
9970   "fdivr{l|}",
9971   /* dd */
9972   "fld{l|}",
9973   "fisttp{ll|}",
9974   "fst{l||}",
9975   "fstp{l|}",
9976   "frstor{C|C}",
9977   "(bad)",
9978   "fNsave{C|C}",
9979   "fNstsw",
9980   /* de */
9981   "fiadd{s|}",
9982   "fimul{s|}",
9983   "ficom{s|}",
9984   "ficomp{s|}",
9985   "fisub{s|}",
9986   "fisubr{s|}",
9987   "fidiv{s|}",
9988   "fidivr{s|}",
9989   /* df */
9990   "fild{s|}",
9991   "fisttp{s|}",
9992   "fist{s|}",
9993   "fistp{s|}",
9994   "fbld",
9995   "fild{ll|}",
9996   "fbstp",
9997   "fistp{ll|}",
9998 };
9999
10000 static const unsigned char float_mem_mode[] = {
10001   /* d8 */
10002   d_mode,
10003   d_mode,
10004   d_mode,
10005   d_mode,
10006   d_mode,
10007   d_mode,
10008   d_mode,
10009   d_mode,
10010   /* d9 */
10011   d_mode,
10012   0,
10013   d_mode,
10014   d_mode,
10015   0,
10016   w_mode,
10017   0,
10018   w_mode,
10019   /* da */
10020   d_mode,
10021   d_mode,
10022   d_mode,
10023   d_mode,
10024   d_mode,
10025   d_mode,
10026   d_mode,
10027   d_mode,
10028   /* db */
10029   d_mode,
10030   d_mode,
10031   d_mode,
10032   d_mode,
10033   0,
10034   t_mode,
10035   0,
10036   t_mode,
10037   /* dc */
10038   q_mode,
10039   q_mode,
10040   q_mode,
10041   q_mode,
10042   q_mode,
10043   q_mode,
10044   q_mode,
10045   q_mode,
10046   /* dd */
10047   q_mode,
10048   q_mode,
10049   q_mode,
10050   q_mode,
10051   0,
10052   0,
10053   0,
10054   w_mode,
10055   /* de */
10056   w_mode,
10057   w_mode,
10058   w_mode,
10059   w_mode,
10060   w_mode,
10061   w_mode,
10062   w_mode,
10063   w_mode,
10064   /* df */
10065   w_mode,
10066   w_mode,
10067   w_mode,
10068   w_mode,
10069   t_mode,
10070   q_mode,
10071   t_mode,
10072   q_mode
10073 };
10074
10075 #define ST { OP_ST, 0 }
10076 #define STi { OP_STi, 0 }
10077
10078 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10079 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10080 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10081 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10082 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10083 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10084 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10085 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10086 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10087
10088 static const struct dis386 float_reg[][8] = {
10089   /* d8 */
10090   {
10091     { "fadd",   { ST, STi }, 0 },
10092     { "fmul",   { ST, STi }, 0 },
10093     { "fcom",   { STi }, 0 },
10094     { "fcomp",  { STi }, 0 },
10095     { "fsub",   { ST, STi }, 0 },
10096     { "fsubr",  { ST, STi }, 0 },
10097     { "fdiv",   { ST, STi }, 0 },
10098     { "fdivr",  { ST, STi }, 0 },
10099   },
10100   /* d9 */
10101   {
10102     { "fld",    { STi }, 0 },
10103     { "fxch",   { STi }, 0 },
10104     { FGRPd9_2 },
10105     { Bad_Opcode },
10106     { FGRPd9_4 },
10107     { FGRPd9_5 },
10108     { FGRPd9_6 },
10109     { FGRPd9_7 },
10110   },
10111   /* da */
10112   {
10113     { "fcmovb", { ST, STi }, 0 },
10114     { "fcmove", { ST, STi }, 0 },
10115     { "fcmovbe",{ ST, STi }, 0 },
10116     { "fcmovu", { ST, STi }, 0 },
10117     { Bad_Opcode },
10118     { FGRPda_5 },
10119     { Bad_Opcode },
10120     { Bad_Opcode },
10121   },
10122   /* db */
10123   {
10124     { "fcmovnb",{ ST, STi }, 0 },
10125     { "fcmovne",{ ST, STi }, 0 },
10126     { "fcmovnbe",{ ST, STi }, 0 },
10127     { "fcmovnu",{ ST, STi }, 0 },
10128     { FGRPdb_4 },
10129     { "fucomi", { ST, STi }, 0 },
10130     { "fcomi",  { ST, STi }, 0 },
10131     { Bad_Opcode },
10132   },
10133   /* dc */
10134   {
10135     { "fadd",   { STi, ST }, 0 },
10136     { "fmul",   { STi, ST }, 0 },
10137     { Bad_Opcode },
10138     { Bad_Opcode },
10139     { "fsub{!M|r}",     { STi, ST }, 0 },
10140     { "fsub{M|}",       { STi, ST }, 0 },
10141     { "fdiv{!M|r}",     { STi, ST }, 0 },
10142     { "fdiv{M|}",       { STi, ST }, 0 },
10143   },
10144   /* dd */
10145   {
10146     { "ffree",  { STi }, 0 },
10147     { Bad_Opcode },
10148     { "fst",    { STi }, 0 },
10149     { "fstp",   { STi }, 0 },
10150     { "fucom",  { STi }, 0 },
10151     { "fucomp", { STi }, 0 },
10152     { Bad_Opcode },
10153     { Bad_Opcode },
10154   },
10155   /* de */
10156   {
10157     { "faddp",  { STi, ST }, 0 },
10158     { "fmulp",  { STi, ST }, 0 },
10159     { Bad_Opcode },
10160     { FGRPde_3 },
10161     { "fsub{!M|r}p",    { STi, ST }, 0 },
10162     { "fsub{M|}p",      { STi, ST }, 0 },
10163     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10164     { "fdiv{M|}p",      { STi, ST }, 0 },
10165   },
10166   /* df */
10167   {
10168     { "ffreep", { STi }, 0 },
10169     { Bad_Opcode },
10170     { Bad_Opcode },
10171     { Bad_Opcode },
10172     { FGRPdf_4 },
10173     { "fucomip", { ST, STi }, 0 },
10174     { "fcomip", { ST, STi }, 0 },
10175     { Bad_Opcode },
10176   },
10177 };
10178
10179 static char *fgrps[][8] = {
10180   /* Bad opcode 0 */
10181   {
10182     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10183   },
10184
10185   /* d9_2  1 */
10186   {
10187     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10188   },
10189
10190   /* d9_4  2 */
10191   {
10192     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10193   },
10194
10195   /* d9_5  3 */
10196   {
10197     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10198   },
10199
10200   /* d9_6  4 */
10201   {
10202     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10203   },
10204
10205   /* d9_7  5 */
10206   {
10207     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10208   },
10209
10210   /* da_5  6 */
10211   {
10212     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10213   },
10214
10215   /* db_4  7 */
10216   {
10217     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10218     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10219   },
10220
10221   /* de_3  8 */
10222   {
10223     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10224   },
10225
10226   /* df_4  9 */
10227   {
10228     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10229   },
10230 };
10231
10232 static void
10233 swap_operand (void)
10234 {
10235   mnemonicendp[0] = '.';
10236   mnemonicendp[1] = 's';
10237   mnemonicendp += 2;
10238 }
10239
10240 static void
10241 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10242                int sizeflag ATTRIBUTE_UNUSED)
10243 {
10244   /* Skip mod/rm byte.  */
10245   MODRM_CHECK;
10246   codep++;
10247 }
10248
10249 static void
10250 dofloat (int sizeflag)
10251 {
10252   const struct dis386 *dp;
10253   unsigned char floatop;
10254
10255   floatop = codep[-1];
10256
10257   if (modrm.mod != 3)
10258     {
10259       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10260
10261       putop (float_mem[fp_indx], sizeflag);
10262       obufp = op_out[0];
10263       op_ad = 2;
10264       OP_E (float_mem_mode[fp_indx], sizeflag);
10265       return;
10266     }
10267   /* Skip mod/rm byte.  */
10268   MODRM_CHECK;
10269   codep++;
10270
10271   dp = &float_reg[floatop - 0xd8][modrm.reg];
10272   if (dp->name == NULL)
10273     {
10274       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10275
10276       /* Instruction fnstsw is only one with strange arg.  */
10277       if (floatop == 0xdf && codep[-1] == 0xe0)
10278         strcpy (op_out[0], names16[0]);
10279     }
10280   else
10281     {
10282       putop (dp->name, sizeflag);
10283
10284       obufp = op_out[0];
10285       op_ad = 2;
10286       if (dp->op[0].rtn)
10287         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10288
10289       obufp = op_out[1];
10290       op_ad = 1;
10291       if (dp->op[1].rtn)
10292         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10293     }
10294 }
10295
10296 /* Like oappend (below), but S is a string starting with '%'.
10297    In Intel syntax, the '%' is elided.  */
10298 static void
10299 oappend_maybe_intel (const char *s)
10300 {
10301   oappend (s + intel_syntax);
10302 }
10303
10304 static void
10305 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10306 {
10307   oappend_maybe_intel ("%st");
10308 }
10309
10310 static void
10311 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10312 {
10313   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10314   oappend_maybe_intel (scratchbuf);
10315 }
10316
10317 /* Capital letters in template are macros.  */
10318 static int
10319 putop (const char *in_template, int sizeflag)
10320 {
10321   const char *p;
10322   int alt = 0;
10323   int cond = 1;
10324   unsigned int l = 0, len = 0;
10325   char last[4];
10326
10327   for (p = in_template; *p; p++)
10328     {
10329       if (len > l)
10330         {
10331           if (l >= sizeof (last) || !ISUPPER (*p))
10332             abort ();
10333           last[l++] = *p;
10334           continue;
10335         }
10336       switch (*p)
10337         {
10338         default:
10339           *obufp++ = *p;
10340           break;
10341         case '%':
10342           len++;
10343           break;
10344         case '!':
10345           cond = 0;
10346           break;
10347         case '{':
10348           if (intel_syntax)
10349             {
10350               while (*++p != '|')
10351                 if (*p == '}' || *p == '\0')
10352                   abort ();
10353               alt = 1;
10354             }
10355           break;
10356         case '|':
10357           while (*++p != '}')
10358             {
10359               if (*p == '\0')
10360                 abort ();
10361             }
10362           break;
10363         case '}':
10364           alt = 0;
10365           break;
10366         case 'A':
10367           if (intel_syntax)
10368             break;
10369           if ((need_modrm && modrm.mod != 3)
10370               || (sizeflag & SUFFIX_ALWAYS))
10371             *obufp++ = 'b';
10372           break;
10373         case 'B':
10374           if (l == 0)
10375             {
10376             case_B:
10377               if (intel_syntax)
10378                 break;
10379               if (sizeflag & SUFFIX_ALWAYS)
10380                 *obufp++ = 'b';
10381             }
10382           else if (l == 1 && last[0] == 'L')
10383             {
10384               if (address_mode == mode_64bit
10385                   && !(prefixes & PREFIX_ADDR))
10386                 {
10387                   *obufp++ = 'a';
10388                   *obufp++ = 'b';
10389                   *obufp++ = 's';
10390                 }
10391
10392               goto case_B;
10393             }
10394           else
10395             abort ();
10396           break;
10397         case 'C':
10398           if (intel_syntax && !alt)
10399             break;
10400           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10401             {
10402               if (sizeflag & DFLAG)
10403                 *obufp++ = intel_syntax ? 'd' : 'l';
10404               else
10405                 *obufp++ = intel_syntax ? 'w' : 's';
10406               used_prefixes |= (prefixes & PREFIX_DATA);
10407             }
10408           break;
10409         case 'D':
10410           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10411             break;
10412           USED_REX (REX_W);
10413           if (modrm.mod == 3)
10414             {
10415               if (rex & REX_W)
10416                 *obufp++ = 'q';
10417               else
10418                 {
10419                   if (sizeflag & DFLAG)
10420                     *obufp++ = intel_syntax ? 'd' : 'l';
10421                   else
10422                     *obufp++ = 'w';
10423                   used_prefixes |= (prefixes & PREFIX_DATA);
10424                 }
10425             }
10426           else
10427             *obufp++ = 'w';
10428           break;
10429         case 'E':               /* For jcxz/jecxz */
10430           if (address_mode == mode_64bit)
10431             {
10432               if (sizeflag & AFLAG)
10433                 *obufp++ = 'r';
10434               else
10435                 *obufp++ = 'e';
10436             }
10437           else
10438             if (sizeflag & AFLAG)
10439               *obufp++ = 'e';
10440           used_prefixes |= (prefixes & PREFIX_ADDR);
10441           break;
10442         case 'F':
10443           if (intel_syntax)
10444             break;
10445           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10446             {
10447               if (sizeflag & AFLAG)
10448                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10449               else
10450                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10451               used_prefixes |= (prefixes & PREFIX_ADDR);
10452             }
10453           break;
10454         case 'G':
10455           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10456             break;
10457           if ((rex & REX_W) || (sizeflag & DFLAG))
10458             *obufp++ = 'l';
10459           else
10460             *obufp++ = 'w';
10461           if (!(rex & REX_W))
10462             used_prefixes |= (prefixes & PREFIX_DATA);
10463           break;
10464         case 'H':
10465           if (intel_syntax)
10466             break;
10467           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10468               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10469             {
10470               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10471               *obufp++ = ',';
10472               *obufp++ = 'p';
10473
10474               /* Set active_seg_prefix even if not set in 64-bit mode
10475                  because here it is a valid branch hint. */
10476               if (prefixes & PREFIX_DS)
10477                 {
10478                   active_seg_prefix = PREFIX_DS;
10479                   *obufp++ = 't';
10480                 }
10481               else
10482                 {
10483                   active_seg_prefix = PREFIX_CS;
10484                   *obufp++ = 'n';
10485                 }
10486             }
10487           break;
10488         case 'K':
10489           USED_REX (REX_W);
10490           if (rex & REX_W)
10491             *obufp++ = 'q';
10492           else
10493             *obufp++ = 'd';
10494           break;
10495         case 'L':
10496           abort ();
10497         case 'M':
10498           if (intel_mnemonic != cond)
10499             *obufp++ = 'r';
10500           break;
10501         case 'N':
10502           if ((prefixes & PREFIX_FWAIT) == 0)
10503             *obufp++ = 'n';
10504           else
10505             used_prefixes |= PREFIX_FWAIT;
10506           break;
10507         case 'O':
10508           USED_REX (REX_W);
10509           if (rex & REX_W)
10510             *obufp++ = 'o';
10511           else if (intel_syntax && (sizeflag & DFLAG))
10512             *obufp++ = 'q';
10513           else
10514             *obufp++ = 'd';
10515           if (!(rex & REX_W))
10516             used_prefixes |= (prefixes & PREFIX_DATA);
10517           break;
10518         case '@':
10519           if (address_mode == mode_64bit
10520               && (isa64 == intel64 || (rex & REX_W)
10521                   || !(prefixes & PREFIX_DATA)))
10522             {
10523               if (sizeflag & SUFFIX_ALWAYS)
10524                 *obufp++ = 'q';
10525               break;
10526             }
10527           /* Fall through.  */
10528         case 'P':
10529           if (l == 0)
10530             {
10531               if ((modrm.mod == 3 || !cond)
10532                   && !(sizeflag & SUFFIX_ALWAYS))
10533                 break;
10534           /* Fall through.  */
10535         case 'T':
10536               if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10537                   || ((sizeflag & SUFFIX_ALWAYS)
10538                       && address_mode != mode_64bit))
10539                 {
10540                   *obufp++ = (sizeflag & DFLAG) ?
10541                              intel_syntax ? 'd' : 'l' : 'w';
10542                   used_prefixes |= (prefixes & PREFIX_DATA);
10543                 }
10544               else if (sizeflag & SUFFIX_ALWAYS)
10545                 *obufp++ = 'q';
10546             }
10547           else if (l == 1 && last[0] == 'L')
10548             {
10549               if ((prefixes & PREFIX_DATA)
10550                   || (rex & REX_W)
10551                   || (sizeflag & SUFFIX_ALWAYS))
10552                 {
10553                   USED_REX (REX_W);
10554                   if (rex & REX_W)
10555                     *obufp++ = 'q';
10556                   else
10557                     {
10558                       if (sizeflag & DFLAG)
10559                         *obufp++ = intel_syntax ? 'd' : 'l';
10560                       else
10561                         *obufp++ = 'w';
10562                       used_prefixes |= (prefixes & PREFIX_DATA);
10563                     }
10564                 }
10565             }
10566           else
10567             abort ();
10568           break;
10569         case 'Q':
10570           if (l == 0)
10571             {
10572               if (intel_syntax && !alt)
10573                 break;
10574               USED_REX (REX_W);
10575               if ((need_modrm && modrm.mod != 3)
10576                   || (sizeflag & SUFFIX_ALWAYS))
10577                 {
10578                   if (rex & REX_W)
10579                     *obufp++ = 'q';
10580                   else
10581                     {
10582                       if (sizeflag & DFLAG)
10583                         *obufp++ = intel_syntax ? 'd' : 'l';
10584                       else
10585                         *obufp++ = 'w';
10586                       used_prefixes |= (prefixes & PREFIX_DATA);
10587                     }
10588                 }
10589             }
10590           else if (l == 1 && last[0] == 'D')
10591             *obufp++ = vex.w ? 'q' : 'd';
10592           else if (l == 1 && last[0] == 'L')
10593             {
10594               if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10595                        : address_mode != mode_64bit)
10596                 break;
10597               if ((rex & REX_W))
10598                 {
10599                   USED_REX (REX_W);
10600                   *obufp++ = 'q';
10601                 }
10602               else if((address_mode == mode_64bit && cond)
10603                       || (sizeflag & SUFFIX_ALWAYS))
10604                 *obufp++ = intel_syntax? 'd' : 'l';
10605             }
10606           else
10607             abort ();
10608           break;
10609         case 'R':
10610           USED_REX (REX_W);
10611           if (rex & REX_W)
10612             *obufp++ = 'q';
10613           else if (sizeflag & DFLAG)
10614             {
10615               if (intel_syntax)
10616                   *obufp++ = 'd';
10617               else
10618                   *obufp++ = 'l';
10619             }
10620           else
10621             *obufp++ = 'w';
10622           if (intel_syntax && !p[1]
10623               && ((rex & REX_W) || (sizeflag & DFLAG)))
10624             *obufp++ = 'e';
10625           if (!(rex & REX_W))
10626             used_prefixes |= (prefixes & PREFIX_DATA);
10627           break;
10628         case 'S':
10629           if (l == 0)
10630             {
10631             case_S:
10632               if (intel_syntax)
10633                 break;
10634               if (sizeflag & SUFFIX_ALWAYS)
10635                 {
10636                   if (rex & REX_W)
10637                     *obufp++ = 'q';
10638                   else
10639                     {
10640                       if (sizeflag & DFLAG)
10641                         *obufp++ = 'l';
10642                       else
10643                         *obufp++ = 'w';
10644                       used_prefixes |= (prefixes & PREFIX_DATA);
10645                     }
10646                 }
10647             }
10648           else if (l == 1 && last[0] == 'L')
10649             {
10650               if (address_mode == mode_64bit
10651                   && !(prefixes & PREFIX_ADDR))
10652                 {
10653                   *obufp++ = 'a';
10654                   *obufp++ = 'b';
10655                   *obufp++ = 's';
10656                 }
10657
10658               goto case_S;
10659             }
10660           else
10661             abort ();
10662           break;
10663         case 'V':
10664           if (l == 0)
10665             abort ();
10666           else if (l == 1
10667                    && (last[0] == 'L' || last[0] == 'X'))
10668             {
10669               if (last[0] == 'X')
10670                 {
10671                   *obufp++ = '{';
10672                   *obufp++ = 'v';
10673                   *obufp++ = 'e';
10674                   *obufp++ = 'x';
10675                   *obufp++ = '}';
10676                 }
10677               else if (rex & REX_W)
10678                 {
10679                   *obufp++ = 'a';
10680                   *obufp++ = 'b';
10681                   *obufp++ = 's';
10682                 }
10683             }
10684           else
10685             abort ();
10686           goto case_S;
10687         case 'W':
10688           if (l == 0)
10689             {
10690               /* operand size flag for cwtl, cbtw */
10691               USED_REX (REX_W);
10692               if (rex & REX_W)
10693                 {
10694                   if (intel_syntax)
10695                     *obufp++ = 'd';
10696                   else
10697                     *obufp++ = 'l';
10698                 }
10699               else if (sizeflag & DFLAG)
10700                 *obufp++ = 'w';
10701               else
10702                 *obufp++ = 'b';
10703               if (!(rex & REX_W))
10704                 used_prefixes |= (prefixes & PREFIX_DATA);
10705             }
10706           else if (l == 1)
10707             {
10708               if (!need_vex)
10709                 abort ();
10710               if (last[0] == 'X')
10711                 *obufp++ = vex.w ? 'd': 's';
10712               else if (last[0] == 'B')
10713                 *obufp++ = vex.w ? 'w': 'b';
10714               else
10715                 abort ();
10716             }
10717           else
10718             abort ();
10719           break;
10720         case 'X':
10721           if (l != 0)
10722             abort ();
10723           if (need_vex
10724               ? vex.prefix == DATA_PREFIX_OPCODE
10725               : prefixes & PREFIX_DATA)
10726             {
10727               *obufp++ = 'd';
10728               used_prefixes |= PREFIX_DATA;
10729             }
10730           else
10731             *obufp++ = 's';
10732           break;
10733         case 'Y':
10734           if (l == 1 && last[0] == 'X')
10735             {
10736               if (!need_vex)
10737                 abort ();
10738               if (intel_syntax
10739                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10740                 break;
10741               switch (vex.length)
10742                 {
10743                 case 128:
10744                   *obufp++ = 'x';
10745                   break;
10746                 case 256:
10747                   *obufp++ = 'y';
10748                   break;
10749                 case 512:
10750                   if (!vex.evex)
10751                 default:
10752                     abort ();
10753                 }
10754             }
10755           else
10756             abort ();
10757           break;
10758         case 'Z':
10759           if (l == 0)
10760             {
10761               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10762               modrm.mod = 3;
10763               if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10764                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10765             }
10766           else if (l == 1 && last[0] == 'X')
10767             {
10768               if (!need_vex || !vex.evex)
10769                 abort ();
10770               if (intel_syntax
10771                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10772                 break;
10773               switch (vex.length)
10774                 {
10775                 case 128:
10776                   *obufp++ = 'x';
10777                   break;
10778                 case 256:
10779                   *obufp++ = 'y';
10780                   break;
10781                 case 512:
10782                   *obufp++ = 'z';
10783                   break;
10784                 default:
10785                   abort ();
10786                 }
10787             }
10788           else
10789             abort ();
10790           break;
10791         case '^':
10792           if (intel_syntax)
10793             break;
10794           if (isa64 == intel64 && (rex & REX_W))
10795             {
10796               USED_REX (REX_W);
10797               *obufp++ = 'q';
10798               break;
10799             }
10800           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10801             {
10802               if (sizeflag & DFLAG)
10803                 *obufp++ = 'l';
10804               else
10805                 *obufp++ = 'w';
10806               used_prefixes |= (prefixes & PREFIX_DATA);
10807             }
10808           break;
10809         }
10810
10811       if (len == l)
10812         len = l = 0;
10813     }
10814   *obufp = 0;
10815   mnemonicendp = obufp;
10816   return 0;
10817 }
10818
10819 static void
10820 oappend (const char *s)
10821 {
10822   obufp = stpcpy (obufp, s);
10823 }
10824
10825 static void
10826 append_seg (void)
10827 {
10828   /* Only print the active segment register.  */
10829   if (!active_seg_prefix)
10830     return;
10831
10832   used_prefixes |= active_seg_prefix;
10833   switch (active_seg_prefix)
10834     {
10835     case PREFIX_CS:
10836       oappend_maybe_intel ("%cs:");
10837       break;
10838     case PREFIX_DS:
10839       oappend_maybe_intel ("%ds:");
10840       break;
10841     case PREFIX_SS:
10842       oappend_maybe_intel ("%ss:");
10843       break;
10844     case PREFIX_ES:
10845       oappend_maybe_intel ("%es:");
10846       break;
10847     case PREFIX_FS:
10848       oappend_maybe_intel ("%fs:");
10849       break;
10850     case PREFIX_GS:
10851       oappend_maybe_intel ("%gs:");
10852       break;
10853     default:
10854       break;
10855     }
10856 }
10857
10858 static void
10859 OP_indirE (int bytemode, int sizeflag)
10860 {
10861   if (!intel_syntax)
10862     oappend ("*");
10863   OP_E (bytemode, sizeflag);
10864 }
10865
10866 static void
10867 print_operand_value (char *buf, int hex, bfd_vma disp)
10868 {
10869   if (address_mode == mode_64bit)
10870     {
10871       if (hex)
10872         {
10873           char tmp[30];
10874           int i;
10875           buf[0] = '0';
10876           buf[1] = 'x';
10877           sprintf_vma (tmp, disp);
10878           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10879           strcpy (buf + 2, tmp + i);
10880         }
10881       else
10882         {
10883           bfd_signed_vma v = disp;
10884           char tmp[30];
10885           int i;
10886           if (v < 0)
10887             {
10888               *(buf++) = '-';
10889               v = -disp;
10890               /* Check for possible overflow on 0x8000000000000000.  */
10891               if (v < 0)
10892                 {
10893                   strcpy (buf, "9223372036854775808");
10894                   return;
10895                 }
10896             }
10897           if (!v)
10898             {
10899               strcpy (buf, "0");
10900               return;
10901             }
10902
10903           i = 0;
10904           tmp[29] = 0;
10905           while (v)
10906             {
10907               tmp[28 - i] = (v % 10) + '0';
10908               v /= 10;
10909               i++;
10910             }
10911           strcpy (buf, tmp + 29 - i);
10912         }
10913     }
10914   else
10915     {
10916       if (hex)
10917         sprintf (buf, "0x%x", (unsigned int) disp);
10918       else
10919         sprintf (buf, "%d", (int) disp);
10920     }
10921 }
10922
10923 /* Put DISP in BUF as signed hex number.  */
10924
10925 static void
10926 print_displacement (char *buf, bfd_vma disp)
10927 {
10928   bfd_signed_vma val = disp;
10929   char tmp[30];
10930   int i, j = 0;
10931
10932   if (val < 0)
10933     {
10934       buf[j++] = '-';
10935       val = -disp;
10936
10937       /* Check for possible overflow.  */
10938       if (val < 0)
10939         {
10940           switch (address_mode)
10941             {
10942             case mode_64bit:
10943               strcpy (buf + j, "0x8000000000000000");
10944               break;
10945             case mode_32bit:
10946               strcpy (buf + j, "0x80000000");
10947               break;
10948             case mode_16bit:
10949               strcpy (buf + j, "0x8000");
10950               break;
10951             }
10952           return;
10953         }
10954     }
10955
10956   buf[j++] = '0';
10957   buf[j++] = 'x';
10958
10959   sprintf_vma (tmp, (bfd_vma) val);
10960   for (i = 0; tmp[i] == '0'; i++)
10961     continue;
10962   if (tmp[i] == '\0')
10963     i--;
10964   strcpy (buf + j, tmp + i);
10965 }
10966
10967 static void
10968 intel_operand_size (int bytemode, int sizeflag)
10969 {
10970   if (vex.evex
10971       && vex.b
10972       && (bytemode == x_mode
10973           || bytemode == evex_half_bcst_xmmq_mode))
10974     {
10975       if (vex.w)
10976         oappend ("QWORD PTR ");
10977       else
10978         oappend ("DWORD PTR ");
10979       return;
10980     }
10981   switch (bytemode)
10982     {
10983     case b_mode:
10984     case b_swap_mode:
10985     case dqb_mode:
10986     case db_mode:
10987       oappend ("BYTE PTR ");
10988       break;
10989     case w_mode:
10990     case dw_mode:
10991     case dqw_mode:
10992       oappend ("WORD PTR ");
10993       break;
10994     case indir_v_mode:
10995       if (address_mode == mode_64bit && isa64 == intel64)
10996         {
10997           oappend ("QWORD PTR ");
10998           break;
10999         }
11000       /* Fall through.  */
11001     case stack_v_mode:
11002       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11003         {
11004           oappend ("QWORD PTR ");
11005           break;
11006         }
11007       /* Fall through.  */
11008     case v_mode:
11009     case v_swap_mode:
11010     case dq_mode:
11011       USED_REX (REX_W);
11012       if (rex & REX_W)
11013         oappend ("QWORD PTR ");
11014       else if (bytemode == dq_mode)
11015         oappend ("DWORD PTR ");
11016       else
11017         {
11018           if (sizeflag & DFLAG)
11019             oappend ("DWORD PTR ");
11020           else
11021             oappend ("WORD PTR ");
11022           used_prefixes |= (prefixes & PREFIX_DATA);
11023         }
11024       break;
11025     case z_mode:
11026       if ((rex & REX_W) || (sizeflag & DFLAG))
11027         *obufp++ = 'D';
11028       oappend ("WORD PTR ");
11029       if (!(rex & REX_W))
11030         used_prefixes |= (prefixes & PREFIX_DATA);
11031       break;
11032     case a_mode:
11033       if (sizeflag & DFLAG)
11034         oappend ("QWORD PTR ");
11035       else
11036         oappend ("DWORD PTR ");
11037       used_prefixes |= (prefixes & PREFIX_DATA);
11038       break;
11039     case movsxd_mode:
11040       if (!(sizeflag & DFLAG) && isa64 == intel64)
11041         oappend ("WORD PTR ");
11042       else
11043         oappend ("DWORD PTR ");
11044       used_prefixes |= (prefixes & PREFIX_DATA);
11045       break;
11046     case d_mode:
11047     case d_swap_mode:
11048     case dqd_mode:
11049       oappend ("DWORD PTR ");
11050       break;
11051     case q_mode:
11052     case q_swap_mode:
11053       oappend ("QWORD PTR ");
11054       break;
11055     case m_mode:
11056       if (address_mode == mode_64bit)
11057         oappend ("QWORD PTR ");
11058       else
11059         oappend ("DWORD PTR ");
11060       break;
11061     case f_mode:
11062       if (sizeflag & DFLAG)
11063         oappend ("FWORD PTR ");
11064       else
11065         oappend ("DWORD PTR ");
11066       used_prefixes |= (prefixes & PREFIX_DATA);
11067       break;
11068     case t_mode:
11069       oappend ("TBYTE PTR ");
11070       break;
11071     case x_mode:
11072     case x_swap_mode:
11073     case evex_x_gscat_mode:
11074     case evex_x_nobcst_mode:
11075     case bw_unit_mode:
11076       if (need_vex)
11077         {
11078           switch (vex.length)
11079             {
11080             case 128:
11081               oappend ("XMMWORD PTR ");
11082               break;
11083             case 256:
11084               oappend ("YMMWORD PTR ");
11085               break;
11086             case 512:
11087               oappend ("ZMMWORD PTR ");
11088               break;
11089             default:
11090               abort ();
11091             }
11092         }
11093       else
11094         oappend ("XMMWORD PTR ");
11095       break;
11096     case xmm_mode:
11097       oappend ("XMMWORD PTR ");
11098       break;
11099     case ymm_mode:
11100       oappend ("YMMWORD PTR ");
11101       break;
11102     case xmmq_mode:
11103     case evex_half_bcst_xmmq_mode:
11104       if (!need_vex)
11105         abort ();
11106
11107       switch (vex.length)
11108         {
11109         case 128:
11110           oappend ("QWORD PTR ");
11111           break;
11112         case 256:
11113           oappend ("XMMWORD PTR ");
11114           break;
11115         case 512:
11116           oappend ("YMMWORD PTR ");
11117           break;
11118         default:
11119           abort ();
11120         }
11121       break;
11122     case xmm_mb_mode:
11123       if (!need_vex)
11124         abort ();
11125
11126       switch (vex.length)
11127         {
11128         case 128:
11129         case 256:
11130         case 512:
11131           oappend ("BYTE PTR ");
11132           break;
11133         default:
11134           abort ();
11135         }
11136       break;
11137     case xmm_mw_mode:
11138       if (!need_vex)
11139         abort ();
11140
11141       switch (vex.length)
11142         {
11143         case 128:
11144         case 256:
11145         case 512:
11146           oappend ("WORD PTR ");
11147           break;
11148         default:
11149           abort ();
11150         }
11151       break;
11152     case xmm_md_mode:
11153       if (!need_vex)
11154         abort ();
11155
11156       switch (vex.length)
11157         {
11158         case 128:
11159         case 256:
11160         case 512:
11161           oappend ("DWORD PTR ");
11162           break;
11163         default:
11164           abort ();
11165         }
11166       break;
11167     case xmm_mq_mode:
11168       if (!need_vex)
11169         abort ();
11170
11171       switch (vex.length)
11172         {
11173         case 128:
11174         case 256:
11175         case 512:
11176           oappend ("QWORD PTR ");
11177           break;
11178         default:
11179           abort ();
11180         }
11181       break;
11182     case xmmdw_mode:
11183       if (!need_vex)
11184         abort ();
11185
11186       switch (vex.length)
11187         {
11188         case 128:
11189           oappend ("WORD PTR ");
11190           break;
11191         case 256:
11192           oappend ("DWORD PTR ");
11193           break;
11194         case 512:
11195           oappend ("QWORD PTR ");
11196           break;
11197         default:
11198           abort ();
11199         }
11200       break;
11201     case xmmqd_mode:
11202       if (!need_vex)
11203         abort ();
11204
11205       switch (vex.length)
11206         {
11207         case 128:
11208           oappend ("DWORD PTR ");
11209           break;
11210         case 256:
11211           oappend ("QWORD PTR ");
11212           break;
11213         case 512:
11214           oappend ("XMMWORD PTR ");
11215           break;
11216         default:
11217           abort ();
11218         }
11219       break;
11220     case ymmq_mode:
11221       if (!need_vex)
11222         abort ();
11223
11224       switch (vex.length)
11225         {
11226         case 128:
11227           oappend ("QWORD PTR ");
11228           break;
11229         case 256:
11230           oappend ("YMMWORD PTR ");
11231           break;
11232         case 512:
11233           oappend ("ZMMWORD PTR ");
11234           break;
11235         default:
11236           abort ();
11237         }
11238       break;
11239     case ymmxmm_mode:
11240       if (!need_vex)
11241         abort ();
11242
11243       switch (vex.length)
11244         {
11245         case 128:
11246         case 256:
11247           oappend ("XMMWORD PTR ");
11248           break;
11249         default:
11250           abort ();
11251         }
11252       break;
11253     case o_mode:
11254       oappend ("OWORD PTR ");
11255       break;
11256     case vex_scalar_w_dq_mode:
11257       if (!need_vex)
11258         abort ();
11259
11260       if (vex.w)
11261         oappend ("QWORD PTR ");
11262       else
11263         oappend ("DWORD PTR ");
11264       break;
11265     case vex_vsib_d_w_dq_mode:
11266     case vex_vsib_q_w_dq_mode:
11267       if (!need_vex)
11268         abort ();
11269
11270       if (!vex.evex)
11271         {
11272           if (vex.w)
11273             oappend ("QWORD PTR ");
11274           else
11275             oappend ("DWORD PTR ");
11276         }
11277       else
11278         {
11279           switch (vex.length)
11280             {
11281             case 128:
11282               oappend ("XMMWORD PTR ");
11283               break;
11284             case 256:
11285               oappend ("YMMWORD PTR ");
11286               break;
11287             case 512:
11288               oappend ("ZMMWORD PTR ");
11289               break;
11290             default:
11291               abort ();
11292             }
11293         }
11294       break;
11295     case vex_vsib_q_w_d_mode:
11296     case vex_vsib_d_w_d_mode:
11297       if (!need_vex || !vex.evex)
11298         abort ();
11299
11300       switch (vex.length)
11301         {
11302         case 128:
11303           oappend ("QWORD PTR ");
11304           break;
11305         case 256:
11306           oappend ("XMMWORD PTR ");
11307           break;
11308         case 512:
11309           oappend ("YMMWORD PTR ");
11310           break;
11311         default:
11312           abort ();
11313         }
11314
11315       break;
11316     case mask_bd_mode:
11317       if (!need_vex || vex.length != 128)
11318         abort ();
11319       if (vex.w)
11320         oappend ("DWORD PTR ");
11321       else
11322         oappend ("BYTE PTR ");
11323       break;
11324     case mask_mode:
11325       if (!need_vex)
11326         abort ();
11327       if (vex.w)
11328         oappend ("QWORD PTR ");
11329       else
11330         oappend ("WORD PTR ");
11331       break;
11332     case v_bnd_mode:
11333     case v_bndmk_mode:
11334     default:
11335       break;
11336     }
11337 }
11338
11339 static void
11340 OP_E_register (int bytemode, int sizeflag)
11341 {
11342   int reg = modrm.rm;
11343   const char **names;
11344
11345   USED_REX (REX_B);
11346   if ((rex & REX_B))
11347     reg += 8;
11348
11349   if ((sizeflag & SUFFIX_ALWAYS)
11350       && (bytemode == b_swap_mode
11351           || bytemode == bnd_swap_mode
11352           || bytemode == v_swap_mode))
11353     swap_operand ();
11354
11355   switch (bytemode)
11356     {
11357     case b_mode:
11358     case b_swap_mode:
11359       if (reg & 4)
11360         USED_REX (0);
11361       if (rex)
11362         names = names8rex;
11363       else
11364         names = names8;
11365       break;
11366     case w_mode:
11367       names = names16;
11368       break;
11369     case d_mode:
11370     case dw_mode:
11371     case db_mode:
11372       names = names32;
11373       break;
11374     case q_mode:
11375       names = names64;
11376       break;
11377     case m_mode:
11378     case v_bnd_mode:
11379       names = address_mode == mode_64bit ? names64 : names32;
11380       break;
11381     case bnd_mode:
11382     case bnd_swap_mode:
11383       if (reg > 0x3)
11384         {
11385           oappend ("(bad)");
11386           return;
11387         }
11388       names = names_bnd;
11389       break;
11390     case indir_v_mode:
11391       if (address_mode == mode_64bit && isa64 == intel64)
11392         {
11393           names = names64;
11394           break;
11395         }
11396       /* Fall through.  */
11397     case stack_v_mode:
11398       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11399         {
11400           names = names64;
11401           break;
11402         }
11403       bytemode = v_mode;
11404       /* Fall through.  */
11405     case v_mode:
11406     case v_swap_mode:
11407     case dq_mode:
11408     case dqb_mode:
11409     case dqd_mode:
11410     case dqw_mode:
11411       USED_REX (REX_W);
11412       if (rex & REX_W)
11413         names = names64;
11414       else if (bytemode != v_mode && bytemode != v_swap_mode)
11415         names = names32;
11416       else
11417         {
11418           if (sizeflag & DFLAG)
11419             names = names32;
11420           else
11421             names = names16;
11422           used_prefixes |= (prefixes & PREFIX_DATA);
11423         }
11424       break;
11425     case movsxd_mode:
11426       if (!(sizeflag & DFLAG) && isa64 == intel64)
11427         names = names16;
11428       else
11429         names = names32;
11430       used_prefixes |= (prefixes & PREFIX_DATA);
11431       break;
11432     case va_mode:
11433       names = (address_mode == mode_64bit
11434                ? names64 : names32);
11435       if (!(prefixes & PREFIX_ADDR))
11436         names = (address_mode == mode_16bit
11437                      ? names16 : names);
11438       else
11439         {
11440           /* Remove "addr16/addr32".  */
11441           all_prefixes[last_addr_prefix] = 0;
11442           names = (address_mode != mode_32bit
11443                        ? names32 : names16);
11444           used_prefixes |= PREFIX_ADDR;
11445         }
11446       break;
11447     case mask_bd_mode:
11448     case mask_mode:
11449       if (reg > 0x7)
11450         {
11451           oappend ("(bad)");
11452           return;
11453         }
11454       names = names_mask;
11455       break;
11456     case 0:
11457       return;
11458     default:
11459       oappend (INTERNAL_DISASSEMBLER_ERROR);
11460       return;
11461     }
11462   oappend (names[reg]);
11463 }
11464
11465 static void
11466 OP_E_memory (int bytemode, int sizeflag)
11467 {
11468   bfd_vma disp = 0;
11469   int add = (rex & REX_B) ? 8 : 0;
11470   int riprel = 0;
11471   int shift;
11472
11473   if (vex.evex)
11474     {
11475       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
11476       if (vex.b
11477           && bytemode != x_mode
11478           && bytemode != xmmq_mode
11479           && bytemode != evex_half_bcst_xmmq_mode)
11480         {
11481           BadOp ();
11482           return;
11483         }
11484       switch (bytemode)
11485         {
11486         case dqw_mode:
11487         case dw_mode:
11488         case xmm_mw_mode:
11489           shift = 1;
11490           break;
11491         case dqb_mode:
11492         case db_mode:
11493         case xmm_mb_mode:
11494           shift = 0;
11495           break;
11496         case dq_mode:
11497           if (address_mode != mode_64bit)
11498             {
11499         case dqd_mode:
11500         case xmm_md_mode:
11501         case d_mode:
11502         case d_swap_mode:
11503               shift = 2;
11504               break;
11505             }
11506             /* fall through */
11507         case vex_scalar_w_dq_mode:
11508         case vex_vsib_d_w_dq_mode:
11509         case vex_vsib_d_w_d_mode:
11510         case vex_vsib_q_w_dq_mode:
11511         case vex_vsib_q_w_d_mode:
11512         case evex_x_gscat_mode:
11513           shift = vex.w ? 3 : 2;
11514           break;
11515         case x_mode:
11516         case evex_half_bcst_xmmq_mode:
11517         case xmmq_mode:
11518           if (vex.b)
11519             {
11520               shift = vex.w ? 3 : 2;
11521               break;
11522             }
11523           /* Fall through.  */
11524         case xmmqd_mode:
11525         case xmmdw_mode:
11526         case ymmq_mode:
11527         case evex_x_nobcst_mode:
11528         case x_swap_mode:
11529           switch (vex.length)
11530             {
11531             case 128:
11532               shift = 4;
11533               break;
11534             case 256:
11535               shift = 5;
11536               break;
11537             case 512:
11538               shift = 6;
11539               break;
11540             default:
11541               abort ();
11542             }
11543           /* Make necessary corrections to shift for modes that need it.  */
11544           if (bytemode == xmmq_mode
11545               || bytemode == evex_half_bcst_xmmq_mode
11546               || (bytemode == ymmq_mode && vex.length == 128))
11547             shift -= 1;
11548           else if (bytemode == xmmqd_mode)
11549             shift -= 2;
11550           else if (bytemode == xmmdw_mode)
11551             shift -= 3;
11552           break;
11553         case ymm_mode:
11554           shift = 5;
11555           break;
11556         case xmm_mode:
11557           shift = 4;
11558           break;
11559         case xmm_mq_mode:
11560         case q_mode:
11561         case q_swap_mode:
11562           shift = 3;
11563           break;
11564         case bw_unit_mode:
11565           shift = vex.w ? 1 : 0;
11566           break;
11567         default:
11568           abort ();
11569         }
11570     }
11571   else
11572     shift = 0;
11573
11574   USED_REX (REX_B);
11575   if (intel_syntax)
11576     intel_operand_size (bytemode, sizeflag);
11577   append_seg ();
11578
11579   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11580     {
11581       /* 32/64 bit address mode */
11582       int havedisp;
11583       int havesib;
11584       int havebase;
11585       int haveindex;
11586       int needindex;
11587       int needaddr32;
11588       int base, rbase;
11589       int vindex = 0;
11590       int scale = 0;
11591       int addr32flag = !((sizeflag & AFLAG)
11592                          || bytemode == v_bnd_mode
11593                          || bytemode == v_bndmk_mode
11594                          || bytemode == bnd_mode
11595                          || bytemode == bnd_swap_mode);
11596       const char **indexes64 = names64;
11597       const char **indexes32 = names32;
11598
11599       havesib = 0;
11600       havebase = 1;
11601       haveindex = 0;
11602       base = modrm.rm;
11603
11604       if (base == 4)
11605         {
11606           havesib = 1;
11607           vindex = sib.index;
11608           USED_REX (REX_X);
11609           if (rex & REX_X)
11610             vindex += 8;
11611           switch (bytemode)
11612             {
11613             case vex_vsib_d_w_dq_mode:
11614             case vex_vsib_d_w_d_mode:
11615             case vex_vsib_q_w_dq_mode:
11616             case vex_vsib_q_w_d_mode:
11617               if (!need_vex)
11618                 abort ();
11619               if (vex.evex)
11620                 {
11621                   if (!vex.v)
11622                     vindex += 16;
11623                 }
11624
11625               haveindex = 1;
11626               switch (vex.length)
11627                 {
11628                 case 128:
11629                   indexes64 = indexes32 = names_xmm;
11630                   break;
11631                 case 256:
11632                   if (!vex.w
11633                       || bytemode == vex_vsib_q_w_dq_mode
11634                       || bytemode == vex_vsib_q_w_d_mode)
11635                     indexes64 = indexes32 = names_ymm;
11636                   else
11637                     indexes64 = indexes32 = names_xmm;
11638                   break;
11639                 case 512:
11640                   if (!vex.w
11641                       || bytemode == vex_vsib_q_w_dq_mode
11642                       || bytemode == vex_vsib_q_w_d_mode)
11643                     indexes64 = indexes32 = names_zmm;
11644                   else
11645                     indexes64 = indexes32 = names_ymm;
11646                   break;
11647                 default:
11648                   abort ();
11649                 }
11650               break;
11651             default:
11652               haveindex = vindex != 4;
11653               break;
11654             }
11655           scale = sib.scale;
11656           base = sib.base;
11657           codep++;
11658         }
11659       else
11660         {
11661           /* mandatory non-vector SIB must have sib */
11662           if (bytemode == vex_sibmem_mode)
11663             {
11664               oappend ("(bad)");
11665               return;
11666             }
11667         }
11668       rbase = base + add;
11669
11670       switch (modrm.mod)
11671         {
11672         case 0:
11673           if (base == 5)
11674             {
11675               havebase = 0;
11676               if (address_mode == mode_64bit && !havesib)
11677                 riprel = 1;
11678               disp = get32s ();
11679               if (riprel && bytemode == v_bndmk_mode)
11680                 {
11681                   oappend ("(bad)");
11682                   return;
11683                 }
11684             }
11685           break;
11686         case 1:
11687           FETCH_DATA (the_info, codep + 1);
11688           disp = *codep++;
11689           if ((disp & 0x80) != 0)
11690             disp -= 0x100;
11691           if (vex.evex && shift > 0)
11692             disp <<= shift;
11693           break;
11694         case 2:
11695           disp = get32s ();
11696           break;
11697         }
11698
11699       needindex = 0;
11700       needaddr32 = 0;
11701       if (havesib
11702           && !havebase
11703           && !haveindex
11704           && address_mode != mode_16bit)
11705         {
11706           if (address_mode == mode_64bit)
11707             {
11708               if (addr32flag)
11709                 {
11710                   /* Without base nor index registers, zero-extend the
11711                      lower 32-bit displacement to 64 bits.  */
11712                   disp = (unsigned int) disp;
11713                   needindex = 1;
11714                 }
11715               needaddr32 = 1;
11716             }
11717           else
11718             {
11719               /* In 32-bit mode, we need index register to tell [offset]
11720                  from [eiz*1 + offset].  */
11721               needindex = 1;
11722             }
11723         }
11724
11725       havedisp = (havebase
11726                   || needindex
11727                   || (havesib && (haveindex || scale != 0)));
11728
11729       if (!intel_syntax)
11730         if (modrm.mod != 0 || base == 5)
11731           {
11732             if (havedisp || riprel)
11733               print_displacement (scratchbuf, disp);
11734             else
11735               print_operand_value (scratchbuf, 1, disp);
11736             oappend (scratchbuf);
11737             if (riprel)
11738               {
11739                 set_op (disp, 1);
11740                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11741               }
11742           }
11743
11744       if ((havebase || haveindex || needindex || needaddr32 || riprel)
11745           && (address_mode != mode_64bit
11746               || ((bytemode != v_bnd_mode)
11747                   && (bytemode != v_bndmk_mode)
11748                   && (bytemode != bnd_mode)
11749                   && (bytemode != bnd_swap_mode))))
11750         used_prefixes |= PREFIX_ADDR;
11751
11752       if (havedisp || (intel_syntax && riprel))
11753         {
11754           *obufp++ = open_char;
11755           if (intel_syntax && riprel)
11756             {
11757               set_op (disp, 1);
11758               oappend (!addr32flag ? "rip" : "eip");
11759             }
11760           *obufp = '\0';
11761           if (havebase)
11762             oappend (address_mode == mode_64bit && !addr32flag
11763                      ? names64[rbase] : names32[rbase]);
11764           if (havesib)
11765             {
11766               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11767                  print index to tell base + index from base.  */
11768               if (scale != 0
11769                   || needindex
11770                   || haveindex
11771                   || (havebase && base != ESP_REG_NUM))
11772                 {
11773                   if (!intel_syntax || havebase)
11774                     {
11775                       *obufp++ = separator_char;
11776                       *obufp = '\0';
11777                     }
11778                   if (haveindex)
11779                     oappend (address_mode == mode_64bit && !addr32flag
11780                              ? indexes64[vindex] : indexes32[vindex]);
11781                   else
11782                     oappend (address_mode == mode_64bit && !addr32flag
11783                              ? index64 : index32);
11784
11785                   *obufp++ = scale_char;
11786                   *obufp = '\0';
11787                   sprintf (scratchbuf, "%d", 1 << scale);
11788                   oappend (scratchbuf);
11789                 }
11790             }
11791           if (intel_syntax
11792               && (disp || modrm.mod != 0 || base == 5))
11793             {
11794               if (!havedisp || (bfd_signed_vma) disp >= 0)
11795                 {
11796                   *obufp++ = '+';
11797                   *obufp = '\0';
11798                 }
11799               else if (modrm.mod != 1 && disp != -disp)
11800                 {
11801                   *obufp++ = '-';
11802                   *obufp = '\0';
11803                   disp = -disp;
11804                 }
11805
11806               if (havedisp)
11807                 print_displacement (scratchbuf, disp);
11808               else
11809                 print_operand_value (scratchbuf, 1, disp);
11810               oappend (scratchbuf);
11811             }
11812
11813           *obufp++ = close_char;
11814           *obufp = '\0';
11815         }
11816       else if (intel_syntax)
11817         {
11818           if (modrm.mod != 0 || base == 5)
11819             {
11820               if (!active_seg_prefix)
11821                 {
11822                   oappend (names_seg[ds_reg - es_reg]);
11823                   oappend (":");
11824                 }
11825               print_operand_value (scratchbuf, 1, disp);
11826               oappend (scratchbuf);
11827             }
11828         }
11829     }
11830   else if (bytemode == v_bnd_mode
11831            || bytemode == v_bndmk_mode
11832            || bytemode == bnd_mode
11833            || bytemode == bnd_swap_mode)
11834     {
11835       oappend ("(bad)");
11836       return;
11837     }
11838   else
11839     {
11840       /* 16 bit address mode */
11841       used_prefixes |= prefixes & PREFIX_ADDR;
11842       switch (modrm.mod)
11843         {
11844         case 0:
11845           if (modrm.rm == 6)
11846             {
11847               disp = get16 ();
11848               if ((disp & 0x8000) != 0)
11849                 disp -= 0x10000;
11850             }
11851           break;
11852         case 1:
11853           FETCH_DATA (the_info, codep + 1);
11854           disp = *codep++;
11855           if ((disp & 0x80) != 0)
11856             disp -= 0x100;
11857           if (vex.evex && shift > 0)
11858             disp <<= shift;
11859           break;
11860         case 2:
11861           disp = get16 ();
11862           if ((disp & 0x8000) != 0)
11863             disp -= 0x10000;
11864           break;
11865         }
11866
11867       if (!intel_syntax)
11868         if (modrm.mod != 0 || modrm.rm == 6)
11869           {
11870             print_displacement (scratchbuf, disp);
11871             oappend (scratchbuf);
11872           }
11873
11874       if (modrm.mod != 0 || modrm.rm != 6)
11875         {
11876           *obufp++ = open_char;
11877           *obufp = '\0';
11878           oappend (index16[modrm.rm]);
11879           if (intel_syntax
11880               && (disp || modrm.mod != 0 || modrm.rm == 6))
11881             {
11882               if ((bfd_signed_vma) disp >= 0)
11883                 {
11884                   *obufp++ = '+';
11885                   *obufp = '\0';
11886                 }
11887               else if (modrm.mod != 1)
11888                 {
11889                   *obufp++ = '-';
11890                   *obufp = '\0';
11891                   disp = -disp;
11892                 }
11893
11894               print_displacement (scratchbuf, disp);
11895               oappend (scratchbuf);
11896             }
11897
11898           *obufp++ = close_char;
11899           *obufp = '\0';
11900         }
11901       else if (intel_syntax)
11902         {
11903           if (!active_seg_prefix)
11904             {
11905               oappend (names_seg[ds_reg - es_reg]);
11906               oappend (":");
11907             }
11908           print_operand_value (scratchbuf, 1, disp & 0xffff);
11909           oappend (scratchbuf);
11910         }
11911     }
11912   if (vex.evex && vex.b
11913       && (bytemode == x_mode
11914           || bytemode == xmmq_mode
11915           || bytemode == evex_half_bcst_xmmq_mode))
11916     {
11917       if (vex.w
11918           || bytemode == xmmq_mode
11919           || bytemode == evex_half_bcst_xmmq_mode)
11920         {
11921           switch (vex.length)
11922             {
11923             case 128:
11924               oappend ("{1to2}");
11925               break;
11926             case 256:
11927               oappend ("{1to4}");
11928               break;
11929             case 512:
11930               oappend ("{1to8}");
11931               break;
11932             default:
11933               abort ();
11934             }
11935         }
11936       else
11937         {
11938           switch (vex.length)
11939             {
11940             case 128:
11941               oappend ("{1to4}");
11942               break;
11943             case 256:
11944               oappend ("{1to8}");
11945               break;
11946             case 512:
11947               oappend ("{1to16}");
11948               break;
11949             default:
11950               abort ();
11951             }
11952         }
11953     }
11954 }
11955
11956 static void
11957 OP_E (int bytemode, int sizeflag)
11958 {
11959   /* Skip mod/rm byte.  */
11960   MODRM_CHECK;
11961   codep++;
11962
11963   if (modrm.mod == 3)
11964     OP_E_register (bytemode, sizeflag);
11965   else
11966     OP_E_memory (bytemode, sizeflag);
11967 }
11968
11969 static void
11970 OP_G (int bytemode, int sizeflag)
11971 {
11972   int add = 0;
11973   const char **names;
11974   USED_REX (REX_R);
11975   if (rex & REX_R)
11976     add += 8;
11977   switch (bytemode)
11978     {
11979     case b_mode:
11980       if (modrm.reg & 4)
11981         USED_REX (0);
11982       if (rex)
11983         oappend (names8rex[modrm.reg + add]);
11984       else
11985         oappend (names8[modrm.reg + add]);
11986       break;
11987     case w_mode:
11988       oappend (names16[modrm.reg + add]);
11989       break;
11990     case d_mode:
11991     case db_mode:
11992     case dw_mode:
11993       oappend (names32[modrm.reg + add]);
11994       break;
11995     case q_mode:
11996       oappend (names64[modrm.reg + add]);
11997       break;
11998     case bnd_mode:
11999       if (modrm.reg > 0x3)
12000         {
12001           oappend ("(bad)");
12002           return;
12003         }
12004       oappend (names_bnd[modrm.reg]);
12005       break;
12006     case v_mode:
12007     case dq_mode:
12008     case dqb_mode:
12009     case dqd_mode:
12010     case dqw_mode:
12011     case movsxd_mode:
12012       USED_REX (REX_W);
12013       if (rex & REX_W)
12014         oappend (names64[modrm.reg + add]);
12015       else if (bytemode != v_mode && bytemode != movsxd_mode)
12016         oappend (names32[modrm.reg + add]);
12017       else
12018         {
12019           if (sizeflag & DFLAG)
12020             oappend (names32[modrm.reg + add]);
12021           else
12022             oappend (names16[modrm.reg + add]);
12023           used_prefixes |= (prefixes & PREFIX_DATA);
12024         }
12025       break;
12026     case va_mode:
12027       names = (address_mode == mode_64bit
12028                ? names64 : names32);
12029       if (!(prefixes & PREFIX_ADDR))
12030         {
12031           if (address_mode == mode_16bit)
12032             names = names16;
12033         }
12034       else
12035         {
12036           /* Remove "addr16/addr32".  */
12037           all_prefixes[last_addr_prefix] = 0;
12038           names = (address_mode != mode_32bit
12039                        ? names32 : names16);
12040           used_prefixes |= PREFIX_ADDR;
12041         }
12042       oappend (names[modrm.reg + add]);
12043       break;
12044     case m_mode:
12045       if (address_mode == mode_64bit)
12046         oappend (names64[modrm.reg + add]);
12047       else
12048         oappend (names32[modrm.reg + add]);
12049       break;
12050     case mask_bd_mode:
12051     case mask_mode:
12052       if ((modrm.reg + add) > 0x7)
12053         {
12054           oappend ("(bad)");
12055           return;
12056         }
12057       oappend (names_mask[modrm.reg + add]);
12058       break;
12059     default:
12060       oappend (INTERNAL_DISASSEMBLER_ERROR);
12061       break;
12062     }
12063 }
12064
12065 static bfd_vma
12066 get64 (void)
12067 {
12068   bfd_vma x;
12069 #ifdef BFD64
12070   unsigned int a;
12071   unsigned int b;
12072
12073   FETCH_DATA (the_info, codep + 8);
12074   a = *codep++ & 0xff;
12075   a |= (*codep++ & 0xff) << 8;
12076   a |= (*codep++ & 0xff) << 16;
12077   a |= (*codep++ & 0xffu) << 24;
12078   b = *codep++ & 0xff;
12079   b |= (*codep++ & 0xff) << 8;
12080   b |= (*codep++ & 0xff) << 16;
12081   b |= (*codep++ & 0xffu) << 24;
12082   x = a + ((bfd_vma) b << 32);
12083 #else
12084   abort ();
12085   x = 0;
12086 #endif
12087   return x;
12088 }
12089
12090 static bfd_signed_vma
12091 get32 (void)
12092 {
12093   bfd_vma x = 0;
12094
12095   FETCH_DATA (the_info, codep + 4);
12096   x = *codep++ & (bfd_vma) 0xff;
12097   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12098   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12099   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12100   return x;
12101 }
12102
12103 static bfd_signed_vma
12104 get32s (void)
12105 {
12106   bfd_vma x = 0;
12107
12108   FETCH_DATA (the_info, codep + 4);
12109   x = *codep++ & (bfd_vma) 0xff;
12110   x |= (*codep++ & (bfd_vma) 0xff) << 8;
12111   x |= (*codep++ & (bfd_vma) 0xff) << 16;
12112   x |= (*codep++ & (bfd_vma) 0xff) << 24;
12113
12114   x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12115
12116   return x;
12117 }
12118
12119 static int
12120 get16 (void)
12121 {
12122   int x = 0;
12123
12124   FETCH_DATA (the_info, codep + 2);
12125   x = *codep++ & 0xff;
12126   x |= (*codep++ & 0xff) << 8;
12127   return x;
12128 }
12129
12130 static void
12131 set_op (bfd_vma op, int riprel)
12132 {
12133   op_index[op_ad] = op_ad;
12134   if (address_mode == mode_64bit)
12135     {
12136       op_address[op_ad] = op;
12137       op_riprel[op_ad] = riprel;
12138     }
12139   else
12140     {
12141       /* Mask to get a 32-bit address.  */
12142       op_address[op_ad] = op & 0xffffffff;
12143       op_riprel[op_ad] = riprel & 0xffffffff;
12144     }
12145 }
12146
12147 static void
12148 OP_REG (int code, int sizeflag)
12149 {
12150   const char *s;
12151   int add;
12152
12153   switch (code)
12154     {
12155     case es_reg: case ss_reg: case cs_reg:
12156     case ds_reg: case fs_reg: case gs_reg:
12157       oappend (names_seg[code - es_reg]);
12158       return;
12159     }
12160
12161   USED_REX (REX_B);
12162   if (rex & REX_B)
12163     add = 8;
12164   else
12165     add = 0;
12166
12167   switch (code)
12168     {
12169     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12170     case sp_reg: case bp_reg: case si_reg: case di_reg:
12171       s = names16[code - ax_reg + add];
12172       break;
12173     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12174       USED_REX (0);
12175       /* Fall through.  */
12176     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12177       if (rex)
12178         s = names8rex[code - al_reg + add];
12179       else
12180         s = names8[code - al_reg];
12181       break;
12182     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12183     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12184       if (address_mode == mode_64bit
12185           && ((sizeflag & DFLAG) || (rex & REX_W)))
12186         {
12187           s = names64[code - rAX_reg + add];
12188           break;
12189         }
12190       code += eAX_reg - rAX_reg;
12191       /* Fall through.  */
12192     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12193     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12194       USED_REX (REX_W);
12195       if (rex & REX_W)
12196         s = names64[code - eAX_reg + add];
12197       else
12198         {
12199           if (sizeflag & DFLAG)
12200             s = names32[code - eAX_reg + add];
12201           else
12202             s = names16[code - eAX_reg + add];
12203           used_prefixes |= (prefixes & PREFIX_DATA);
12204         }
12205       break;
12206     default:
12207       s = INTERNAL_DISASSEMBLER_ERROR;
12208       break;
12209     }
12210   oappend (s);
12211 }
12212
12213 static void
12214 OP_IMREG (int code, int sizeflag)
12215 {
12216   const char *s;
12217
12218   switch (code)
12219     {
12220     case indir_dx_reg:
12221       if (intel_syntax)
12222         s = "dx";
12223       else
12224         s = "(%dx)";
12225       break;
12226     case al_reg: case cl_reg:
12227       s = names8[code - al_reg];
12228       break;
12229     case eAX_reg:
12230       USED_REX (REX_W);
12231       if (rex & REX_W)
12232         {
12233           s = *names64;
12234           break;
12235         }
12236       /* Fall through.  */
12237     case z_mode_ax_reg:
12238       if ((rex & REX_W) || (sizeflag & DFLAG))
12239         s = *names32;
12240       else
12241         s = *names16;
12242       if (!(rex & REX_W))
12243         used_prefixes |= (prefixes & PREFIX_DATA);
12244       break;
12245     default:
12246       s = INTERNAL_DISASSEMBLER_ERROR;
12247       break;
12248     }
12249   oappend (s);
12250 }
12251
12252 static void
12253 OP_I (int bytemode, int sizeflag)
12254 {
12255   bfd_signed_vma op;
12256   bfd_signed_vma mask = -1;
12257
12258   switch (bytemode)
12259     {
12260     case b_mode:
12261       FETCH_DATA (the_info, codep + 1);
12262       op = *codep++;
12263       mask = 0xff;
12264       break;
12265     case v_mode:
12266       USED_REX (REX_W);
12267       if (rex & REX_W)
12268         op = get32s ();
12269       else
12270         {
12271           if (sizeflag & DFLAG)
12272             {
12273               op = get32 ();
12274               mask = 0xffffffff;
12275             }
12276           else
12277             {
12278               op = get16 ();
12279               mask = 0xfffff;
12280             }
12281           used_prefixes |= (prefixes & PREFIX_DATA);
12282         }
12283       break;
12284     case d_mode:
12285       mask = 0xffffffff;
12286       op = get32 ();
12287       break;
12288     case w_mode:
12289       mask = 0xfffff;
12290       op = get16 ();
12291       break;
12292     case const_1_mode:
12293       if (intel_syntax)
12294         oappend ("1");
12295       return;
12296     default:
12297       oappend (INTERNAL_DISASSEMBLER_ERROR);
12298       return;
12299     }
12300
12301   op &= mask;
12302   scratchbuf[0] = '$';
12303   print_operand_value (scratchbuf + 1, 1, op);
12304   oappend_maybe_intel (scratchbuf);
12305   scratchbuf[0] = '\0';
12306 }
12307
12308 static void
12309 OP_I64 (int bytemode, int sizeflag)
12310 {
12311   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12312     {
12313       OP_I (bytemode, sizeflag);
12314       return;
12315     }
12316
12317   USED_REX (REX_W);
12318
12319   scratchbuf[0] = '$';
12320   print_operand_value (scratchbuf + 1, 1, get64 ());
12321   oappend_maybe_intel (scratchbuf);
12322   scratchbuf[0] = '\0';
12323 }
12324
12325 static void
12326 OP_sI (int bytemode, int sizeflag)
12327 {
12328   bfd_signed_vma op;
12329
12330   switch (bytemode)
12331     {
12332     case b_mode:
12333     case b_T_mode:
12334       FETCH_DATA (the_info, codep + 1);
12335       op = *codep++;
12336       if ((op & 0x80) != 0)
12337         op -= 0x100;
12338       if (bytemode == b_T_mode)
12339         {
12340           if (address_mode != mode_64bit
12341               || !((sizeflag & DFLAG) || (rex & REX_W)))
12342             {
12343               /* The operand-size prefix is overridden by a REX prefix.  */
12344               if ((sizeflag & DFLAG) || (rex & REX_W))
12345                 op &= 0xffffffff;
12346               else
12347                 op &= 0xffff;
12348           }
12349         }
12350       else
12351         {
12352           if (!(rex & REX_W))
12353             {
12354               if (sizeflag & DFLAG)
12355                 op &= 0xffffffff;
12356               else
12357                 op &= 0xffff;
12358             }
12359         }
12360       break;
12361     case v_mode:
12362       /* The operand-size prefix is overridden by a REX prefix.  */
12363       if ((sizeflag & DFLAG) || (rex & REX_W))
12364         op = get32s ();
12365       else
12366         op = get16 ();
12367       break;
12368     default:
12369       oappend (INTERNAL_DISASSEMBLER_ERROR);
12370       return;
12371     }
12372
12373   scratchbuf[0] = '$';
12374   print_operand_value (scratchbuf + 1, 1, op);
12375   oappend_maybe_intel (scratchbuf);
12376 }
12377
12378 static void
12379 OP_J (int bytemode, int sizeflag)
12380 {
12381   bfd_vma disp;
12382   bfd_vma mask = -1;
12383   bfd_vma segment = 0;
12384
12385   switch (bytemode)
12386     {
12387     case b_mode:
12388       FETCH_DATA (the_info, codep + 1);
12389       disp = *codep++;
12390       if ((disp & 0x80) != 0)
12391         disp -= 0x100;
12392       break;
12393     case v_mode:
12394     case dqw_mode:
12395       if ((sizeflag & DFLAG)
12396           || (address_mode == mode_64bit
12397               && ((isa64 == intel64 && bytemode != dqw_mode)
12398                   || (rex & REX_W))))
12399         disp = get32s ();
12400       else
12401         {
12402           disp = get16 ();
12403           if ((disp & 0x8000) != 0)
12404             disp -= 0x10000;
12405           /* In 16bit mode, address is wrapped around at 64k within
12406              the same segment.  Otherwise, a data16 prefix on a jump
12407              instruction means that the pc is masked to 16 bits after
12408              the displacement is added!  */
12409           mask = 0xffff;
12410           if ((prefixes & PREFIX_DATA) == 0)
12411             segment = ((start_pc + (codep - start_codep))
12412                        & ~((bfd_vma) 0xffff));
12413         }
12414       if (address_mode != mode_64bit
12415           || (isa64 != intel64 && !(rex & REX_W)))
12416         used_prefixes |= (prefixes & PREFIX_DATA);
12417       break;
12418     default:
12419       oappend (INTERNAL_DISASSEMBLER_ERROR);
12420       return;
12421     }
12422   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12423   set_op (disp, 0);
12424   print_operand_value (scratchbuf, 1, disp);
12425   oappend (scratchbuf);
12426 }
12427
12428 static void
12429 OP_SEG (int bytemode, int sizeflag)
12430 {
12431   if (bytemode == w_mode)
12432     oappend (names_seg[modrm.reg]);
12433   else
12434     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12435 }
12436
12437 static void
12438 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12439 {
12440   int seg, offset;
12441
12442   if (sizeflag & DFLAG)
12443     {
12444       offset = get32 ();
12445       seg = get16 ();
12446     }
12447   else
12448     {
12449       offset = get16 ();
12450       seg = get16 ();
12451     }
12452   used_prefixes |= (prefixes & PREFIX_DATA);
12453   if (intel_syntax)
12454     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12455   else
12456     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12457   oappend (scratchbuf);
12458 }
12459
12460 static void
12461 OP_OFF (int bytemode, int sizeflag)
12462 {
12463   bfd_vma off;
12464
12465   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12466     intel_operand_size (bytemode, sizeflag);
12467   append_seg ();
12468
12469   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12470     off = get32 ();
12471   else
12472     off = get16 ();
12473
12474   if (intel_syntax)
12475     {
12476       if (!active_seg_prefix)
12477         {
12478           oappend (names_seg[ds_reg - es_reg]);
12479           oappend (":");
12480         }
12481     }
12482   print_operand_value (scratchbuf, 1, off);
12483   oappend (scratchbuf);
12484 }
12485
12486 static void
12487 OP_OFF64 (int bytemode, int sizeflag)
12488 {
12489   bfd_vma off;
12490
12491   if (address_mode != mode_64bit
12492       || (prefixes & PREFIX_ADDR))
12493     {
12494       OP_OFF (bytemode, sizeflag);
12495       return;
12496     }
12497
12498   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12499     intel_operand_size (bytemode, sizeflag);
12500   append_seg ();
12501
12502   off = get64 ();
12503
12504   if (intel_syntax)
12505     {
12506       if (!active_seg_prefix)
12507         {
12508           oappend (names_seg[ds_reg - es_reg]);
12509           oappend (":");
12510         }
12511     }
12512   print_operand_value (scratchbuf, 1, off);
12513   oappend (scratchbuf);
12514 }
12515
12516 static void
12517 ptr_reg (int code, int sizeflag)
12518 {
12519   const char *s;
12520
12521   *obufp++ = open_char;
12522   used_prefixes |= (prefixes & PREFIX_ADDR);
12523   if (address_mode == mode_64bit)
12524     {
12525       if (!(sizeflag & AFLAG))
12526         s = names32[code - eAX_reg];
12527       else
12528         s = names64[code - eAX_reg];
12529     }
12530   else if (sizeflag & AFLAG)
12531     s = names32[code - eAX_reg];
12532   else
12533     s = names16[code - eAX_reg];
12534   oappend (s);
12535   *obufp++ = close_char;
12536   *obufp = 0;
12537 }
12538
12539 static void
12540 OP_ESreg (int code, int sizeflag)
12541 {
12542   if (intel_syntax)
12543     {
12544       switch (codep[-1])
12545         {
12546         case 0x6d:      /* insw/insl */
12547           intel_operand_size (z_mode, sizeflag);
12548           break;
12549         case 0xa5:      /* movsw/movsl/movsq */
12550         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12551         case 0xab:      /* stosw/stosl */
12552         case 0xaf:      /* scasw/scasl */
12553           intel_operand_size (v_mode, sizeflag);
12554           break;
12555         default:
12556           intel_operand_size (b_mode, sizeflag);
12557         }
12558     }
12559   oappend_maybe_intel ("%es:");
12560   ptr_reg (code, sizeflag);
12561 }
12562
12563 static void
12564 OP_DSreg (int code, int sizeflag)
12565 {
12566   if (intel_syntax)
12567     {
12568       switch (codep[-1])
12569         {
12570         case 0x6f:      /* outsw/outsl */
12571           intel_operand_size (z_mode, sizeflag);
12572           break;
12573         case 0xa5:      /* movsw/movsl/movsq */
12574         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12575         case 0xad:      /* lodsw/lodsl/lodsq */
12576           intel_operand_size (v_mode, sizeflag);
12577           break;
12578         default:
12579           intel_operand_size (b_mode, sizeflag);
12580         }
12581     }
12582   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12583      default segment register DS is printed.  */
12584   if (!active_seg_prefix)
12585     active_seg_prefix = PREFIX_DS;
12586   append_seg ();
12587   ptr_reg (code, sizeflag);
12588 }
12589
12590 static void
12591 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12592 {
12593   int add;
12594   if (rex & REX_R)
12595     {
12596       USED_REX (REX_R);
12597       add = 8;
12598     }
12599   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12600     {
12601       all_prefixes[last_lock_prefix] = 0;
12602       used_prefixes |= PREFIX_LOCK;
12603       add = 8;
12604     }
12605   else
12606     add = 0;
12607   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12608   oappend_maybe_intel (scratchbuf);
12609 }
12610
12611 static void
12612 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12613 {
12614   int add;
12615   USED_REX (REX_R);
12616   if (rex & REX_R)
12617     add = 8;
12618   else
12619     add = 0;
12620   if (intel_syntax)
12621     sprintf (scratchbuf, "dr%d", modrm.reg + add);
12622   else
12623     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12624   oappend (scratchbuf);
12625 }
12626
12627 static void
12628 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12629 {
12630   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12631   oappend_maybe_intel (scratchbuf);
12632 }
12633
12634 static void
12635 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12636 {
12637   int reg = modrm.reg;
12638   const char **names;
12639
12640   used_prefixes |= (prefixes & PREFIX_DATA);
12641   if (prefixes & PREFIX_DATA)
12642     {
12643       names = names_xmm;
12644       USED_REX (REX_R);
12645       if (rex & REX_R)
12646         reg += 8;
12647     }
12648   else
12649     names = names_mm;
12650   oappend (names[reg]);
12651 }
12652
12653 static void
12654 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12655 {
12656   int reg = modrm.reg;
12657   const char **names;
12658
12659   USED_REX (REX_R);
12660   if (rex & REX_R)
12661     reg += 8;
12662   if (vex.evex)
12663     {
12664       if (!vex.r)
12665         reg += 16;
12666     }
12667
12668   if (need_vex
12669       && bytemode != xmm_mode
12670       && bytemode != xmmq_mode
12671       && bytemode != evex_half_bcst_xmmq_mode
12672       && bytemode != ymm_mode
12673       && bytemode != tmm_mode
12674       && bytemode != scalar_mode)
12675     {
12676       switch (vex.length)
12677         {
12678         case 128:
12679           names = names_xmm;
12680           break;
12681         case 256:
12682           if (vex.w
12683               || (bytemode != vex_vsib_q_w_dq_mode
12684                   && bytemode != vex_vsib_q_w_d_mode))
12685             names = names_ymm;
12686           else
12687             names = names_xmm;
12688           break;
12689         case 512:
12690           names = names_zmm;
12691           break;
12692         default:
12693           abort ();
12694         }
12695     }
12696   else if (bytemode == xmmq_mode
12697            || bytemode == evex_half_bcst_xmmq_mode)
12698     {
12699       switch (vex.length)
12700         {
12701         case 128:
12702         case 256:
12703           names = names_xmm;
12704           break;
12705         case 512:
12706           names = names_ymm;
12707           break;
12708         default:
12709           abort ();
12710         }
12711     }
12712   else if (bytemode == tmm_mode)
12713     {
12714       modrm.reg = reg;
12715       if (reg >= 8)
12716         {
12717           oappend ("(bad)");
12718           return;
12719         }
12720       names = names_tmm;
12721     }
12722   else if (bytemode == ymm_mode)
12723     names = names_ymm;
12724   else
12725     names = names_xmm;
12726   oappend (names[reg]);
12727 }
12728
12729 static void
12730 OP_EM (int bytemode, int sizeflag)
12731 {
12732   int reg;
12733   const char **names;
12734
12735   if (modrm.mod != 3)
12736     {
12737       if (intel_syntax
12738           && (bytemode == v_mode || bytemode == v_swap_mode))
12739         {
12740           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12741           used_prefixes |= (prefixes & PREFIX_DATA);
12742         }
12743       OP_E (bytemode, sizeflag);
12744       return;
12745     }
12746
12747   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12748     swap_operand ();
12749
12750   /* Skip mod/rm byte.  */
12751   MODRM_CHECK;
12752   codep++;
12753   used_prefixes |= (prefixes & PREFIX_DATA);
12754   reg = modrm.rm;
12755   if (prefixes & PREFIX_DATA)
12756     {
12757       names = names_xmm;
12758       USED_REX (REX_B);
12759       if (rex & REX_B)
12760         reg += 8;
12761     }
12762   else
12763     names = names_mm;
12764   oappend (names[reg]);
12765 }
12766
12767 /* cvt* are the only instructions in sse2 which have
12768    both SSE and MMX operands and also have 0x66 prefix
12769    in their opcode. 0x66 was originally used to differentiate
12770    between SSE and MMX instruction(operands). So we have to handle the
12771    cvt* separately using OP_EMC and OP_MXC */
12772 static void
12773 OP_EMC (int bytemode, int sizeflag)
12774 {
12775   if (modrm.mod != 3)
12776     {
12777       if (intel_syntax && bytemode == v_mode)
12778         {
12779           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12780           used_prefixes |= (prefixes & PREFIX_DATA);
12781         }
12782       OP_E (bytemode, sizeflag);
12783       return;
12784     }
12785
12786   /* Skip mod/rm byte.  */
12787   MODRM_CHECK;
12788   codep++;
12789   used_prefixes |= (prefixes & PREFIX_DATA);
12790   oappend (names_mm[modrm.rm]);
12791 }
12792
12793 static void
12794 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12795 {
12796   used_prefixes |= (prefixes & PREFIX_DATA);
12797   oappend (names_mm[modrm.reg]);
12798 }
12799
12800 static void
12801 OP_EX (int bytemode, int sizeflag)
12802 {
12803   int reg;
12804   const char **names;
12805
12806   /* Skip mod/rm byte.  */
12807   MODRM_CHECK;
12808   codep++;
12809
12810   if (modrm.mod != 3)
12811     {
12812       OP_E_memory (bytemode, sizeflag);
12813       return;
12814     }
12815
12816   reg = modrm.rm;
12817   USED_REX (REX_B);
12818   if (rex & REX_B)
12819     reg += 8;
12820   if (vex.evex)
12821     {
12822       USED_REX (REX_X);
12823       if ((rex & REX_X))
12824         reg += 16;
12825     }
12826
12827   if ((sizeflag & SUFFIX_ALWAYS)
12828       && (bytemode == x_swap_mode
12829           || bytemode == d_swap_mode
12830           || bytemode == q_swap_mode))
12831     swap_operand ();
12832
12833   if (need_vex
12834       && bytemode != xmm_mode
12835       && bytemode != xmmdw_mode
12836       && bytemode != xmmqd_mode
12837       && bytemode != xmm_mb_mode
12838       && bytemode != xmm_mw_mode
12839       && bytemode != xmm_md_mode
12840       && bytemode != xmm_mq_mode
12841       && bytemode != xmmq_mode
12842       && bytemode != evex_half_bcst_xmmq_mode
12843       && bytemode != ymm_mode
12844       && bytemode != tmm_mode
12845       && bytemode != vex_scalar_w_dq_mode)
12846     {
12847       switch (vex.length)
12848         {
12849         case 128:
12850           names = names_xmm;
12851           break;
12852         case 256:
12853           names = names_ymm;
12854           break;
12855         case 512:
12856           names = names_zmm;
12857           break;
12858         default:
12859           abort ();
12860         }
12861     }
12862   else if (bytemode == xmmq_mode
12863            || bytemode == evex_half_bcst_xmmq_mode)
12864     {
12865       switch (vex.length)
12866         {
12867         case 128:
12868         case 256:
12869           names = names_xmm;
12870           break;
12871         case 512:
12872           names = names_ymm;
12873           break;
12874         default:
12875           abort ();
12876         }
12877     }
12878   else if (bytemode == tmm_mode)
12879     {
12880       modrm.rm = reg;
12881       if (reg >= 8)
12882         {
12883           oappend ("(bad)");
12884           return;
12885         }
12886       names = names_tmm;
12887     }
12888   else if (bytemode == ymm_mode)
12889     names = names_ymm;
12890   else
12891     names = names_xmm;
12892   oappend (names[reg]);
12893 }
12894
12895 static void
12896 OP_MS (int bytemode, int sizeflag)
12897 {
12898   if (modrm.mod == 3)
12899     OP_EM (bytemode, sizeflag);
12900   else
12901     BadOp ();
12902 }
12903
12904 static void
12905 OP_XS (int bytemode, int sizeflag)
12906 {
12907   if (modrm.mod == 3)
12908     OP_EX (bytemode, sizeflag);
12909   else
12910     BadOp ();
12911 }
12912
12913 static void
12914 OP_M (int bytemode, int sizeflag)
12915 {
12916   if (modrm.mod == 3)
12917     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12918     BadOp ();
12919   else
12920     OP_E (bytemode, sizeflag);
12921 }
12922
12923 static void
12924 OP_0f07 (int bytemode, int sizeflag)
12925 {
12926   if (modrm.mod != 3 || modrm.rm != 0)
12927     BadOp ();
12928   else
12929     OP_E (bytemode, sizeflag);
12930 }
12931
12932 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12933    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12934
12935 static void
12936 NOP_Fixup1 (int bytemode, int sizeflag)
12937 {
12938   if ((prefixes & PREFIX_DATA) != 0
12939       || (rex != 0
12940           && rex != 0x48
12941           && address_mode == mode_64bit))
12942     OP_REG (bytemode, sizeflag);
12943   else
12944     strcpy (obuf, "nop");
12945 }
12946
12947 static void
12948 NOP_Fixup2 (int bytemode, int sizeflag)
12949 {
12950   if ((prefixes & PREFIX_DATA) != 0
12951       || (rex != 0
12952           && rex != 0x48
12953           && address_mode == mode_64bit))
12954     OP_IMREG (bytemode, sizeflag);
12955 }
12956
12957 static const char *const Suffix3DNow[] = {
12958 /* 00 */        NULL,           NULL,           NULL,           NULL,
12959 /* 04 */        NULL,           NULL,           NULL,           NULL,
12960 /* 08 */        NULL,           NULL,           NULL,           NULL,
12961 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12962 /* 10 */        NULL,           NULL,           NULL,           NULL,
12963 /* 14 */        NULL,           NULL,           NULL,           NULL,
12964 /* 18 */        NULL,           NULL,           NULL,           NULL,
12965 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12966 /* 20 */        NULL,           NULL,           NULL,           NULL,
12967 /* 24 */        NULL,           NULL,           NULL,           NULL,
12968 /* 28 */        NULL,           NULL,           NULL,           NULL,
12969 /* 2C */        NULL,           NULL,           NULL,           NULL,
12970 /* 30 */        NULL,           NULL,           NULL,           NULL,
12971 /* 34 */        NULL,           NULL,           NULL,           NULL,
12972 /* 38 */        NULL,           NULL,           NULL,           NULL,
12973 /* 3C */        NULL,           NULL,           NULL,           NULL,
12974 /* 40 */        NULL,           NULL,           NULL,           NULL,
12975 /* 44 */        NULL,           NULL,           NULL,           NULL,
12976 /* 48 */        NULL,           NULL,           NULL,           NULL,
12977 /* 4C */        NULL,           NULL,           NULL,           NULL,
12978 /* 50 */        NULL,           NULL,           NULL,           NULL,
12979 /* 54 */        NULL,           NULL,           NULL,           NULL,
12980 /* 58 */        NULL,           NULL,           NULL,           NULL,
12981 /* 5C */        NULL,           NULL,           NULL,           NULL,
12982 /* 60 */        NULL,           NULL,           NULL,           NULL,
12983 /* 64 */        NULL,           NULL,           NULL,           NULL,
12984 /* 68 */        NULL,           NULL,           NULL,           NULL,
12985 /* 6C */        NULL,           NULL,           NULL,           NULL,
12986 /* 70 */        NULL,           NULL,           NULL,           NULL,
12987 /* 74 */        NULL,           NULL,           NULL,           NULL,
12988 /* 78 */        NULL,           NULL,           NULL,           NULL,
12989 /* 7C */        NULL,           NULL,           NULL,           NULL,
12990 /* 80 */        NULL,           NULL,           NULL,           NULL,
12991 /* 84 */        NULL,           NULL,           NULL,           NULL,
12992 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12993 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12994 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12995 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12996 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12997 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12998 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12999 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13000 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13001 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13002 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13003 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13004 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13005 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13006 /* C0 */        NULL,           NULL,           NULL,           NULL,
13007 /* C4 */        NULL,           NULL,           NULL,           NULL,
13008 /* C8 */        NULL,           NULL,           NULL,           NULL,
13009 /* CC */        NULL,           NULL,           NULL,           NULL,
13010 /* D0 */        NULL,           NULL,           NULL,           NULL,
13011 /* D4 */        NULL,           NULL,           NULL,           NULL,
13012 /* D8 */        NULL,           NULL,           NULL,           NULL,
13013 /* DC */        NULL,           NULL,           NULL,           NULL,
13014 /* E0 */        NULL,           NULL,           NULL,           NULL,
13015 /* E4 */        NULL,           NULL,           NULL,           NULL,
13016 /* E8 */        NULL,           NULL,           NULL,           NULL,
13017 /* EC */        NULL,           NULL,           NULL,           NULL,
13018 /* F0 */        NULL,           NULL,           NULL,           NULL,
13019 /* F4 */        NULL,           NULL,           NULL,           NULL,
13020 /* F8 */        NULL,           NULL,           NULL,           NULL,
13021 /* FC */        NULL,           NULL,           NULL,           NULL,
13022 };
13023
13024 static void
13025 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13026 {
13027   const char *mnemonic;
13028
13029   FETCH_DATA (the_info, codep + 1);
13030   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13031      place where an 8-bit immediate would normally go.  ie. the last
13032      byte of the instruction.  */
13033   obufp = mnemonicendp;
13034   mnemonic = Suffix3DNow[*codep++ & 0xff];
13035   if (mnemonic)
13036     oappend (mnemonic);
13037   else
13038     {
13039       /* Since a variable sized modrm/sib chunk is between the start
13040          of the opcode (0x0f0f) and the opcode suffix, we need to do
13041          all the modrm processing first, and don't know until now that
13042          we have a bad opcode.  This necessitates some cleaning up.  */
13043       op_out[0][0] = '\0';
13044       op_out[1][0] = '\0';
13045       BadOp ();
13046     }
13047   mnemonicendp = obufp;
13048 }
13049
13050 static const struct op simd_cmp_op[] =
13051 {
13052   { STRING_COMMA_LEN ("eq") },
13053   { STRING_COMMA_LEN ("lt") },
13054   { STRING_COMMA_LEN ("le") },
13055   { STRING_COMMA_LEN ("unord") },
13056   { STRING_COMMA_LEN ("neq") },
13057   { STRING_COMMA_LEN ("nlt") },
13058   { STRING_COMMA_LEN ("nle") },
13059   { STRING_COMMA_LEN ("ord") }
13060 };
13061
13062 static const struct op vex_cmp_op[] =
13063 {
13064   { STRING_COMMA_LEN ("eq_uq") },
13065   { STRING_COMMA_LEN ("nge") },
13066   { STRING_COMMA_LEN ("ngt") },
13067   { STRING_COMMA_LEN ("false") },
13068   { STRING_COMMA_LEN ("neq_oq") },
13069   { STRING_COMMA_LEN ("ge") },
13070   { STRING_COMMA_LEN ("gt") },
13071   { STRING_COMMA_LEN ("true") },
13072   { STRING_COMMA_LEN ("eq_os") },
13073   { STRING_COMMA_LEN ("lt_oq") },
13074   { STRING_COMMA_LEN ("le_oq") },
13075   { STRING_COMMA_LEN ("unord_s") },
13076   { STRING_COMMA_LEN ("neq_us") },
13077   { STRING_COMMA_LEN ("nlt_uq") },
13078   { STRING_COMMA_LEN ("nle_uq") },
13079   { STRING_COMMA_LEN ("ord_s") },
13080   { STRING_COMMA_LEN ("eq_us") },
13081   { STRING_COMMA_LEN ("nge_uq") },
13082   { STRING_COMMA_LEN ("ngt_uq") },
13083   { STRING_COMMA_LEN ("false_os") },
13084   { STRING_COMMA_LEN ("neq_os") },
13085   { STRING_COMMA_LEN ("ge_oq") },
13086   { STRING_COMMA_LEN ("gt_oq") },
13087   { STRING_COMMA_LEN ("true_us") },
13088 };
13089
13090 static void
13091 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13092 {
13093   unsigned int cmp_type;
13094
13095   FETCH_DATA (the_info, codep + 1);
13096   cmp_type = *codep++ & 0xff;
13097   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13098     {
13099       char suffix [3];
13100       char *p = mnemonicendp - 2;
13101       suffix[0] = p[0];
13102       suffix[1] = p[1];
13103       suffix[2] = '\0';
13104       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13105       mnemonicendp += simd_cmp_op[cmp_type].len;
13106     }
13107   else if (need_vex
13108            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13109     {
13110       char suffix [3];
13111       char *p = mnemonicendp - 2;
13112       suffix[0] = p[0];
13113       suffix[1] = p[1];
13114       suffix[2] = '\0';
13115       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13116       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13117       mnemonicendp += vex_cmp_op[cmp_type].len;
13118     }
13119   else
13120     {
13121       /* We have a reserved extension byte.  Output it directly.  */
13122       scratchbuf[0] = '$';
13123       print_operand_value (scratchbuf + 1, 1, cmp_type);
13124       oappend_maybe_intel (scratchbuf);
13125       scratchbuf[0] = '\0';
13126     }
13127 }
13128
13129 static void
13130 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13131 {
13132   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13133   if (!intel_syntax)
13134     {
13135       strcpy (op_out[0], names32[0]);
13136       strcpy (op_out[1], names32[1]);
13137       if (bytemode == eBX_reg)
13138         strcpy (op_out[2], names32[3]);
13139       two_source_ops = 1;
13140     }
13141   /* Skip mod/rm byte.  */
13142   MODRM_CHECK;
13143   codep++;
13144 }
13145
13146 static void
13147 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13148             int sizeflag ATTRIBUTE_UNUSED)
13149 {
13150   /* monitor %{e,r,}ax,%ecx,%edx"  */
13151   if (!intel_syntax)
13152     {
13153       const char **names = (address_mode == mode_64bit
13154                             ? names64 : names32);
13155
13156       if (prefixes & PREFIX_ADDR)
13157         {
13158           /* Remove "addr16/addr32".  */
13159           all_prefixes[last_addr_prefix] = 0;
13160           names = (address_mode != mode_32bit
13161                    ? names32 : names16);
13162           used_prefixes |= PREFIX_ADDR;
13163         }
13164       else if (address_mode == mode_16bit)
13165         names = names16;
13166       strcpy (op_out[0], names[0]);
13167       strcpy (op_out[1], names32[1]);
13168       strcpy (op_out[2], names32[2]);
13169       two_source_ops = 1;
13170     }
13171   /* Skip mod/rm byte.  */
13172   MODRM_CHECK;
13173   codep++;
13174 }
13175
13176 static void
13177 BadOp (void)
13178 {
13179   /* Throw away prefixes and 1st. opcode byte.  */
13180   codep = insn_codep + 1;
13181   oappend ("(bad)");
13182 }
13183
13184 static void
13185 REP_Fixup (int bytemode, int sizeflag)
13186 {
13187   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13188      lods and stos.  */
13189   if (prefixes & PREFIX_REPZ)
13190     all_prefixes[last_repz_prefix] = REP_PREFIX;
13191
13192   switch (bytemode)
13193     {
13194     case al_reg:
13195     case eAX_reg:
13196     case indir_dx_reg:
13197       OP_IMREG (bytemode, sizeflag);
13198       break;
13199     case eDI_reg:
13200       OP_ESreg (bytemode, sizeflag);
13201       break;
13202     case eSI_reg:
13203       OP_DSreg (bytemode, sizeflag);
13204       break;
13205     default:
13206       abort ();
13207       break;
13208     }
13209 }
13210
13211 static void
13212 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13213 {
13214   if ( isa64 != amd64 )
13215     return;
13216
13217   obufp = obuf;
13218   BadOp ();
13219   mnemonicendp = obufp;
13220   ++codep;
13221 }
13222
13223 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13224    "bnd".  */
13225
13226 static void
13227 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13228 {
13229   if (prefixes & PREFIX_REPNZ)
13230     all_prefixes[last_repnz_prefix] = BND_PREFIX;
13231 }
13232
13233 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13234    "notrack".  */
13235
13236 static void
13237 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13238                int sizeflag ATTRIBUTE_UNUSED)
13239 {
13240
13241   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13242      we've seen a PREFIX_DS.  */
13243   if ((prefixes & PREFIX_DS) != 0
13244       && (address_mode != mode_64bit || last_data_prefix < 0))
13245     {
13246       /* NOTRACK prefix is only valid on indirect branch instructions.
13247          NB: DATA prefix is unsupported for Intel64.  */
13248       active_seg_prefix = 0;
13249       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13250     }
13251 }
13252
13253 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13254    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13255  */
13256
13257 static void
13258 HLE_Fixup1 (int bytemode, int sizeflag)
13259 {
13260   if (modrm.mod != 3
13261       && (prefixes & PREFIX_LOCK) != 0)
13262     {
13263       if (prefixes & PREFIX_REPZ)
13264         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13265       if (prefixes & PREFIX_REPNZ)
13266         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13267     }
13268
13269   OP_E (bytemode, sizeflag);
13270 }
13271
13272 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
13273    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13274  */
13275
13276 static void
13277 HLE_Fixup2 (int bytemode, int sizeflag)
13278 {
13279   if (modrm.mod != 3)
13280     {
13281       if (prefixes & PREFIX_REPZ)
13282         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13283       if (prefixes & PREFIX_REPNZ)
13284         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13285     }
13286
13287   OP_E (bytemode, sizeflag);
13288 }
13289
13290 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13291    "xrelease" for memory operand.  No check for LOCK prefix.   */
13292
13293 static void
13294 HLE_Fixup3 (int bytemode, int sizeflag)
13295 {
13296   if (modrm.mod != 3
13297       && last_repz_prefix > last_repnz_prefix
13298       && (prefixes & PREFIX_REPZ) != 0)
13299     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13300
13301   OP_E (bytemode, sizeflag);
13302 }
13303
13304 static void
13305 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13306 {
13307   USED_REX (REX_W);
13308   if (rex & REX_W)
13309     {
13310       /* Change cmpxchg8b to cmpxchg16b.  */
13311       char *p = mnemonicendp - 2;
13312       mnemonicendp = stpcpy (p, "16b");
13313       bytemode = o_mode;
13314     }
13315   else if ((prefixes & PREFIX_LOCK) != 0)
13316     {
13317       if (prefixes & PREFIX_REPZ)
13318         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13319       if (prefixes & PREFIX_REPNZ)
13320         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13321     }
13322
13323   OP_M (bytemode, sizeflag);
13324 }
13325
13326 static void
13327 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13328 {
13329   const char **names;
13330
13331   if (need_vex)
13332     {
13333       switch (vex.length)
13334         {
13335         case 128:
13336           names = names_xmm;
13337           break;
13338         case 256:
13339           names = names_ymm;
13340           break;
13341         default:
13342           abort ();
13343         }
13344     }
13345   else
13346     names = names_xmm;
13347   oappend (names[reg]);
13348 }
13349
13350 static void
13351 FXSAVE_Fixup (int bytemode, int sizeflag)
13352 {
13353   /* Add proper suffix to "fxsave" and "fxrstor".  */
13354   USED_REX (REX_W);
13355   if (rex & REX_W)
13356     {
13357       char *p = mnemonicendp;
13358       *p++ = '6';
13359       *p++ = '4';
13360       *p = '\0';
13361       mnemonicendp = p;
13362     }
13363   OP_M (bytemode, sizeflag);
13364 }
13365
13366 /* Display the destination register operand for instructions with
13367    VEX. */
13368
13369 static void
13370 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13371 {
13372   int reg;
13373   const char **names;
13374
13375   if (!need_vex)
13376     abort ();
13377
13378   reg = vex.register_specifier;
13379   vex.register_specifier = 0;
13380   if (address_mode != mode_64bit)
13381     reg &= 7;
13382   else if (vex.evex && !vex.v)
13383     reg += 16;
13384
13385   if (bytemode == vex_scalar_mode)
13386     {
13387       oappend (names_xmm[reg]);
13388       return;
13389     }
13390
13391   if (bytemode == tmm_mode)
13392     {
13393       /* All 3 TMM registers must be distinct.  */
13394       if (reg >= 8)
13395         oappend ("(bad)");
13396       else
13397         {
13398           /* This must be the 3rd operand.  */
13399           if (obufp != op_out[2])
13400             abort ();
13401           oappend (names_tmm[reg]);
13402           if (reg == modrm.reg || reg == modrm.rm)
13403             strcpy (obufp, "/(bad)");
13404         }
13405
13406       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13407         {
13408           if (modrm.reg <= 8
13409               && (modrm.reg == modrm.rm || modrm.reg == reg))
13410             strcat (op_out[0], "/(bad)");
13411           if (modrm.rm <= 8
13412               && (modrm.rm == modrm.reg || modrm.rm == reg))
13413             strcat (op_out[1], "/(bad)");
13414         }
13415
13416       return;
13417     }
13418
13419   switch (vex.length)
13420     {
13421     case 128:
13422       switch (bytemode)
13423         {
13424         case vex_mode:
13425         case vex_vsib_q_w_dq_mode:
13426         case vex_vsib_q_w_d_mode:
13427           names = names_xmm;
13428           break;
13429         case dq_mode:
13430           if (rex & REX_W)
13431             names = names64;
13432           else
13433             names = names32;
13434           break;
13435         case mask_bd_mode:
13436         case mask_mode:
13437           if (reg > 0x7)
13438             {
13439               oappend ("(bad)");
13440               return;
13441             }
13442           names = names_mask;
13443           break;
13444         default:
13445           abort ();
13446           return;
13447         }
13448       break;
13449     case 256:
13450       switch (bytemode)
13451         {
13452         case vex_mode:
13453           names = names_ymm;
13454           break;
13455         case vex_vsib_q_w_dq_mode:
13456         case vex_vsib_q_w_d_mode:
13457           names = vex.w ? names_ymm : names_xmm;
13458           break;
13459         case mask_bd_mode:
13460         case mask_mode:
13461           if (reg > 0x7)
13462             {
13463               oappend ("(bad)");
13464               return;
13465             }
13466           names = names_mask;
13467           break;
13468         default:
13469           /* See PR binutils/20893 for a reproducer.  */
13470           oappend ("(bad)");
13471           return;
13472         }
13473       break;
13474     case 512:
13475       names = names_zmm;
13476       break;
13477     default:
13478       abort ();
13479       break;
13480     }
13481   oappend (names[reg]);
13482 }
13483
13484 static void
13485 OP_VexR (int bytemode, int sizeflag)
13486 {
13487   if (modrm.mod == 3)
13488     OP_VEX (bytemode, sizeflag);
13489 }
13490
13491 static void
13492 OP_VexW (int bytemode, int sizeflag)
13493 {
13494   OP_VEX (bytemode, sizeflag);
13495
13496   if (vex.w)
13497     {
13498       /* Swap 2nd and 3rd operands.  */
13499       strcpy (scratchbuf, op_out[2]);
13500       strcpy (op_out[2], op_out[1]);
13501       strcpy (op_out[1], scratchbuf);
13502     }
13503 }
13504
13505 static void
13506 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13507 {
13508   int reg;
13509   const char **names = names_xmm;
13510
13511   FETCH_DATA (the_info, codep + 1);
13512   reg = *codep++;
13513
13514   if (bytemode != x_mode && bytemode != scalar_mode)
13515     abort ();
13516
13517   reg >>= 4;
13518   if (address_mode != mode_64bit)
13519     reg &= 7;
13520
13521   if (bytemode == x_mode && vex.length == 256)
13522     names = names_ymm;
13523
13524   oappend (names[reg]);
13525
13526   if (vex.w)
13527     {
13528       /* Swap 3rd and 4th operands.  */
13529       strcpy (scratchbuf, op_out[3]);
13530       strcpy (op_out[3], op_out[2]);
13531       strcpy (op_out[2], scratchbuf);
13532     }
13533 }
13534
13535 static void
13536 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13537           int sizeflag ATTRIBUTE_UNUSED)
13538 {
13539   scratchbuf[0] = '$';
13540   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13541   oappend_maybe_intel (scratchbuf);
13542 }
13543
13544 static void
13545 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13546              int sizeflag ATTRIBUTE_UNUSED)
13547 {
13548   unsigned int cmp_type;
13549
13550   if (!vex.evex)
13551     abort ();
13552
13553   FETCH_DATA (the_info, codep + 1);
13554   cmp_type = *codep++ & 0xff;
13555   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13556      If it's the case, print suffix, otherwise - print the immediate.  */
13557   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13558       && cmp_type != 3
13559       && cmp_type != 7)
13560     {
13561       char suffix [3];
13562       char *p = mnemonicendp - 2;
13563
13564       /* vpcmp* can have both one- and two-lettered suffix.  */
13565       if (p[0] == 'p')
13566         {
13567           p++;
13568           suffix[0] = p[0];
13569           suffix[1] = '\0';
13570         }
13571       else
13572         {
13573           suffix[0] = p[0];
13574           suffix[1] = p[1];
13575           suffix[2] = '\0';
13576         }
13577
13578       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13579       mnemonicendp += simd_cmp_op[cmp_type].len;
13580     }
13581   else
13582     {
13583       /* We have a reserved extension byte.  Output it directly.  */
13584       scratchbuf[0] = '$';
13585       print_operand_value (scratchbuf + 1, 1, cmp_type);
13586       oappend_maybe_intel (scratchbuf);
13587       scratchbuf[0] = '\0';
13588     }
13589 }
13590
13591 static const struct op xop_cmp_op[] =
13592 {
13593   { STRING_COMMA_LEN ("lt") },
13594   { STRING_COMMA_LEN ("le") },
13595   { STRING_COMMA_LEN ("gt") },
13596   { STRING_COMMA_LEN ("ge") },
13597   { STRING_COMMA_LEN ("eq") },
13598   { STRING_COMMA_LEN ("neq") },
13599   { STRING_COMMA_LEN ("false") },
13600   { STRING_COMMA_LEN ("true") }
13601 };
13602
13603 static void
13604 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13605              int sizeflag ATTRIBUTE_UNUSED)
13606 {
13607   unsigned int cmp_type;
13608
13609   FETCH_DATA (the_info, codep + 1);
13610   cmp_type = *codep++ & 0xff;
13611   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13612     {
13613       char suffix[3];
13614       char *p = mnemonicendp - 2;
13615
13616       /* vpcom* can have both one- and two-lettered suffix.  */
13617       if (p[0] == 'm')
13618         {
13619           p++;
13620           suffix[0] = p[0];
13621           suffix[1] = '\0';
13622         }
13623       else
13624         {
13625           suffix[0] = p[0];
13626           suffix[1] = p[1];
13627           suffix[2] = '\0';
13628         }
13629
13630       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13631       mnemonicendp += xop_cmp_op[cmp_type].len;
13632     }
13633   else
13634     {
13635       /* We have a reserved extension byte.  Output it directly.  */
13636       scratchbuf[0] = '$';
13637       print_operand_value (scratchbuf + 1, 1, cmp_type);
13638       oappend_maybe_intel (scratchbuf);
13639       scratchbuf[0] = '\0';
13640     }
13641 }
13642
13643 static const struct op pclmul_op[] =
13644 {
13645   { STRING_COMMA_LEN ("lql") },
13646   { STRING_COMMA_LEN ("hql") },
13647   { STRING_COMMA_LEN ("lqh") },
13648   { STRING_COMMA_LEN ("hqh") }
13649 };
13650
13651 static void
13652 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13653               int sizeflag ATTRIBUTE_UNUSED)
13654 {
13655   unsigned int pclmul_type;
13656
13657   FETCH_DATA (the_info, codep + 1);
13658   pclmul_type = *codep++ & 0xff;
13659   switch (pclmul_type)
13660     {
13661     case 0x10:
13662       pclmul_type = 2;
13663       break;
13664     case 0x11:
13665       pclmul_type = 3;
13666       break;
13667     default:
13668       break;
13669     }
13670   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13671     {
13672       char suffix [4];
13673       char *p = mnemonicendp - 3;
13674       suffix[0] = p[0];
13675       suffix[1] = p[1];
13676       suffix[2] = p[2];
13677       suffix[3] = '\0';
13678       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13679       mnemonicendp += pclmul_op[pclmul_type].len;
13680     }
13681   else
13682     {
13683       /* We have a reserved extension byte.  Output it directly.  */
13684       scratchbuf[0] = '$';
13685       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13686       oappend_maybe_intel (scratchbuf);
13687       scratchbuf[0] = '\0';
13688     }
13689 }
13690
13691 static void
13692 MOVSXD_Fixup (int bytemode, int sizeflag)
13693 {
13694   /* Add proper suffix to "movsxd".  */
13695   char *p = mnemonicendp;
13696
13697   switch (bytemode)
13698     {
13699     case movsxd_mode:
13700       if (intel_syntax)
13701         {
13702           *p++ = 'x';
13703           *p++ = 'd';
13704           goto skip;
13705         }
13706
13707       USED_REX (REX_W);
13708       if (rex & REX_W)
13709         {
13710           *p++ = 'l';
13711           *p++ = 'q';
13712         }
13713       else
13714         {
13715           *p++ = 'x';
13716           *p++ = 'd';
13717         }
13718       break;
13719     default:
13720       oappend (INTERNAL_DISASSEMBLER_ERROR);
13721       break;
13722     }
13723
13724  skip:
13725   mnemonicendp = p;
13726   *p = '\0';
13727   OP_E (bytemode, sizeflag);
13728 }
13729
13730 static void
13731 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13732 {
13733   if (!vex.evex
13734       || (bytemode != mask_mode && bytemode != mask_bd_mode))
13735     abort ();
13736
13737   USED_REX (REX_R);
13738   if ((rex & REX_R) != 0 || !vex.r)
13739     {
13740       BadOp ();
13741       return;
13742     }
13743
13744   oappend (names_mask [modrm.reg]);
13745 }
13746
13747 static void
13748 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13749 {
13750   if (modrm.mod == 3 && vex.b)
13751     switch (bytemode)
13752       {
13753       case evex_rounding_64_mode:
13754         if (address_mode != mode_64bit)
13755           {
13756             oappend ("(bad)");
13757             break;
13758           }
13759         /* Fall through.  */
13760       case evex_rounding_mode:
13761         oappend (names_rounding[vex.ll]);
13762         break;
13763       case evex_sae_mode:
13764         oappend ("{sae}");
13765         break;
13766       default:
13767         abort ();
13768         break;
13769       }
13770 }