opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void HLE_Fixup1 (int, int);
 113 static void HLE_Fixup2 (int, int);
 114 static void HLE_Fixup3 (int, int);
 115 static void CMPXCHG8B_Fixup (int, int);
 116 static void XMM_Fixup (int, int);
 117 static void CRC32_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void OP_LWPCB_E (int, int);
 120 static void OP_LWP_E (int, int);
 121 static void OP_Vex_2src_1 (int, int);
 122 static void OP_Vex_2src_2 (int, int);
 123
 124 static void MOVBE_Fixup (int, int);
 125
 126 static void OP_Mask (int, int);
 127
 128 struct dis_private {
 129   /* Points to first byte not fetched.  */
 130   bfd_byte *max_fetched;
 131   bfd_byte the_buffer[MAX_MNEM_SIZE];
 132   bfd_vma insn_start;
 133   int orig_sizeflag;
 134   OPCODES_SIGJMP_BUF bailout;
 135 };
 136
 137 enum address_mode
 138 {
 139   mode_16bit,
 140   mode_32bit,
 141   mode_64bit
 142 };
 143
 144 enum address_mode address_mode;
 145
 146 /* Flags for the prefixes for the current instruction.  See below.  */
 147 static int prefixes;
 148
 149 /* REX prefix the current instruction.  See below.  */
 150 static int rex;
 151 /* Bits of REX we've already used.  */
 152 static int rex_used;
 153 /* REX bits in original REX prefix ignored.  */
 154 static int rex_ignored;
 155 /* Mark parts used in the REX prefix.  When we are testing for
 156    empty prefix (for 8bit register REX extension), just mask it
 157    out.  Otherwise test for REX bit is excuse for existence of REX
 158    only in case value is nonzero.  */
 159 #define USED_REX(value)                                 \
 160   {                                                     \
 161     if (value)                                          \
 162       {                                                 \
 163         if ((rex & value))                              \
 164           rex_used |= (value) | REX_OPCODE;             \
 165       }                                                 \
 166     else                                                \
 167       rex_used |= REX_OPCODE;                           \
 168   }
 169
 170 /* Flags for prefixes which we somehow handled when printing the
 171    current instruction.  */
 172 static int used_prefixes;
 173
 174 /* Flags stored in PREFIXES.  */
 175 #define PREFIX_REPZ 1
 176 #define PREFIX_REPNZ 2
 177 #define PREFIX_LOCK 4
 178 #define PREFIX_CS 8
 179 #define PREFIX_SS 0x10
 180 #define PREFIX_DS 0x20
 181 #define PREFIX_ES 0x40
 182 #define PREFIX_FS 0x80
 183 #define PREFIX_GS 0x100
 184 #define PREFIX_DATA 0x200
 185 #define PREFIX_ADDR 0x400
 186 #define PREFIX_FWAIT 0x800
 187
 188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 189    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 190    on error.  */
 191 #define FETCH_DATA(info, addr) \
 192   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 193    ? 1 : fetch_data ((info), (addr)))
 194
 195 static int
 196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 197 {
 198   int status;
 199   struct dis_private *priv = (struct dis_private *) info->private_data;
 200   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 201
 202   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 203     status = (*info->read_memory_func) (start,
 204                                         priv->max_fetched,
 205                                         addr - priv->max_fetched,
 206                                         info);
 207   else
 208     status = -1;
 209   if (status != 0)
 210     {
 211       /* If we did manage to read at least one byte, then
 212          print_insn_i386 will do something sensible.  Otherwise, print
 213          an error.  We do that here because this is where we know
 214          STATUS.  */
 215       if (priv->max_fetched == priv->the_buffer)
 216         (*info->memory_error_func) (status, start, info);
 217       OPCODES_SIGLONGJMP (priv->bailout, 1);
 218     }
 219   else
 220     priv->max_fetched = addr;
 221   return 1;
 222 }
 223
 224 /* Possible values for prefix requirement.  */
 225 #define PREFIX_IGNORED_SHIFT    16
 226 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 227 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 231
 232 /* Opcode prefixes.  */
 233 #define PREFIX_OPCODE           (PREFIX_REPZ \
 234                                  | PREFIX_REPNZ \
 235                                  | PREFIX_DATA)
 236
 237 /* Prefixes ignored.  */
 238 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 239                                  | PREFIX_IGNORED_REPNZ \
 240                                  | PREFIX_IGNORED_DATA)
 241
 242 #define XX { NULL, 0 }
 243 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 244
 245 #define Eb { OP_E, b_mode }
 246 #define Ebnd { OP_E, bnd_mode }
 247 #define EbS { OP_E, b_swap_mode }
 248 #define Ev { OP_E, v_mode }
 249 #define Ev_bnd { OP_E, v_bnd_mode }
 250 #define EvS { OP_E, v_swap_mode }
 251 #define Ed { OP_E, d_mode }
 252 #define Edq { OP_E, dq_mode }
 253 #define Edqw { OP_E, dqw_mode }
 254 #define EdqwS { OP_E, dqw_swap_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, stack_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   dqw_swap_mode,
 559   bnd_mode,
 560   /* 4- or 6-byte pointer operand */
 561   f_mode,
 562   const_1_mode,
 563   /* v_mode for stack-related opcodes.  */
 564   stack_v_mode,
 565   /* non-quad operand size depends on prefixes */
 566   z_mode,
 567   /* 16-byte operand */
 568   o_mode,
 569   /* registers like dq_mode, memory like b_mode.  */
 570   dqb_mode,
 571   /* registers like d_mode, memory like b_mode.  */
 572   db_mode,
 573   /* registers like d_mode, memory like w_mode.  */
 574   dw_mode,
 575   /* registers like dq_mode, memory like d_mode.  */
 576   dqd_mode,
 577   /* normal vex mode */
 578   vex_mode,
 579   /* 128bit vex mode */
 580   vex128_mode,
 581   /* 256bit vex mode */
 582   vex256_mode,
 583   /* operand size depends on the VEX.W bit.  */
 584   vex_w_dq_mode,
 585
 586   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 587   vex_vsib_d_w_dq_mode,
 588   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 589   vex_vsib_d_w_d_mode,
 590   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 591   vex_vsib_q_w_dq_mode,
 592   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 593   vex_vsib_q_w_d_mode,
 594
 595   /* scalar, ignore vector length.  */
 596   scalar_mode,
 597   /* like d_mode, ignore vector length.  */
 598   d_scalar_mode,
 599   /* like d_swap_mode, ignore vector length.  */
 600   d_scalar_swap_mode,
 601   /* like q_mode, ignore vector length.  */
 602   q_scalar_mode,
 603   /* like q_swap_mode, ignore vector length.  */
 604   q_scalar_swap_mode,
 605   /* like vex_mode, ignore vector length.  */
 606   vex_scalar_mode,
 607   /* like vex_w_dq_mode, ignore vector length.  */
 608   vex_scalar_w_dq_mode,
 609
 610   /* Static rounding.  */
 611   evex_rounding_mode,
 612   /* Supress all exceptions.  */
 613   evex_sae_mode,
 614
 615   /* Mask register operand.  */
 616   mask_mode,
 617   /* Mask register operand.  */
 618   mask_bd_mode,
 619
 620   es_reg,
 621   cs_reg,
 622   ss_reg,
 623   ds_reg,
 624   fs_reg,
 625   gs_reg,
 626
 627   eAX_reg,
 628   eCX_reg,
 629   eDX_reg,
 630   eBX_reg,
 631   eSP_reg,
 632   eBP_reg,
 633   eSI_reg,
 634   eDI_reg,
 635
 636   al_reg,
 637   cl_reg,
 638   dl_reg,
 639   bl_reg,
 640   ah_reg,
 641   ch_reg,
 642   dh_reg,
 643   bh_reg,
 644
 645   ax_reg,
 646   cx_reg,
 647   dx_reg,
 648   bx_reg,
 649   sp_reg,
 650   bp_reg,
 651   si_reg,
 652   di_reg,
 653
 654   rAX_reg,
 655   rCX_reg,
 656   rDX_reg,
 657   rBX_reg,
 658   rSP_reg,
 659   rBP_reg,
 660   rSI_reg,
 661   rDI_reg,
 662
 663   z_mode_ax_reg,
 664   indir_dx_reg
 665 };
 666
 667 enum
 668 {
 669   FLOATCODE = 1,
 670   USE_REG_TABLE,
 671   USE_MOD_TABLE,
 672   USE_RM_TABLE,
 673   USE_PREFIX_TABLE,
 674   USE_X86_64_TABLE,
 675   USE_3BYTE_TABLE,
 676   USE_XOP_8F_TABLE,
 677   USE_VEX_C4_TABLE,
 678   USE_VEX_C5_TABLE,
 679   USE_VEX_LEN_TABLE,
 680   USE_VEX_W_TABLE,
 681   USE_EVEX_TABLE
 682 };
 683
 684 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 685
 686 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 687 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 688 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 689 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 690 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 691 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 692 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 693 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 694 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 695 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 696 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 697 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 698 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 699 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 700 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 701
 702 enum
 703 {
 704   REG_80 = 0,
 705   REG_81,
 706   REG_82,
 707   REG_8F,
 708   REG_C0,
 709   REG_C1,
 710   REG_C6,
 711   REG_C7,
 712   REG_D0,
 713   REG_D1,
 714   REG_D2,
 715   REG_D3,
 716   REG_F6,
 717   REG_F7,
 718   REG_FE,
 719   REG_FF,
 720   REG_0F00,
 721   REG_0F01,
 722   REG_0F0D,
 723   REG_0F18,
 724   REG_0F71,
 725   REG_0F72,
 726   REG_0F73,
 727   REG_0FA6,
 728   REG_0FA7,
 729   REG_0FAE,
 730   REG_0FBA,
 731   REG_0FC7,
 732   REG_VEX_0F71,
 733   REG_VEX_0F72,
 734   REG_VEX_0F73,
 735   REG_VEX_0FAE,
 736   REG_VEX_0F38F3,
 737   REG_XOP_LWPCB,
 738   REG_XOP_LWP,
 739   REG_XOP_TBM_01,
 740   REG_XOP_TBM_02,
 741
 742   REG_EVEX_0F71,
 743   REG_EVEX_0F72,
 744   REG_EVEX_0F73,
 745   REG_EVEX_0F38C6,
 746   REG_EVEX_0F38C7
 747 };
 748
 749 enum
 750 {
 751   MOD_8D = 0,
 752   MOD_C6_REG_7,
 753   MOD_C7_REG_7,
 754   MOD_FF_REG_3,
 755   MOD_FF_REG_5,
 756   MOD_0F01_REG_0,
 757   MOD_0F01_REG_1,
 758   MOD_0F01_REG_2,
 759   MOD_0F01_REG_3,
 760   MOD_0F01_REG_7,
 761   MOD_0F12_PREFIX_0,
 762   MOD_0F13,
 763   MOD_0F16_PREFIX_0,
 764   MOD_0F17,
 765   MOD_0F18_REG_0,
 766   MOD_0F18_REG_1,
 767   MOD_0F18_REG_2,
 768   MOD_0F18_REG_3,
 769   MOD_0F18_REG_4,
 770   MOD_0F18_REG_5,
 771   MOD_0F18_REG_6,
 772   MOD_0F18_REG_7,
 773   MOD_0F1A_PREFIX_0,
 774   MOD_0F1B_PREFIX_0,
 775   MOD_0F1B_PREFIX_1,
 776   MOD_0F24,
 777   MOD_0F26,
 778   MOD_0F2B_PREFIX_0,
 779   MOD_0F2B_PREFIX_1,
 780   MOD_0F2B_PREFIX_2,
 781   MOD_0F2B_PREFIX_3,
 782   MOD_0F51,
 783   MOD_0F71_REG_2,
 784   MOD_0F71_REG_4,
 785   MOD_0F71_REG_6,
 786   MOD_0F72_REG_2,
 787   MOD_0F72_REG_4,
 788   MOD_0F72_REG_6,
 789   MOD_0F73_REG_2,
 790   MOD_0F73_REG_3,
 791   MOD_0F73_REG_6,
 792   MOD_0F73_REG_7,
 793   MOD_0FAE_REG_0,
 794   MOD_0FAE_REG_1,
 795   MOD_0FAE_REG_2,
 796   MOD_0FAE_REG_3,
 797   MOD_0FAE_REG_4,
 798   MOD_0FAE_REG_5,
 799   MOD_0FAE_REG_6,
 800   MOD_0FAE_REG_7,
 801   MOD_0FB2,
 802   MOD_0FB4,
 803   MOD_0FB5,
 804   MOD_0FC7_REG_3,
 805   MOD_0FC7_REG_4,
 806   MOD_0FC7_REG_5,
 807   MOD_0FC7_REG_6,
 808   MOD_0FC7_REG_7,
 809   MOD_0FD7,
 810   MOD_0FE7_PREFIX_2,
 811   MOD_0FF0_PREFIX_3,
 812   MOD_0F382A_PREFIX_2,
 813   MOD_62_32BIT,
 814   MOD_C4_32BIT,
 815   MOD_C5_32BIT,
 816   MOD_VEX_0F12_PREFIX_0,
 817   MOD_VEX_0F13,
 818   MOD_VEX_0F16_PREFIX_0,
 819   MOD_VEX_0F17,
 820   MOD_VEX_0F2B,
 821   MOD_VEX_0F50,
 822   MOD_VEX_0F71_REG_2,
 823   MOD_VEX_0F71_REG_4,
 824   MOD_VEX_0F71_REG_6,
 825   MOD_VEX_0F72_REG_2,
 826   MOD_VEX_0F72_REG_4,
 827   MOD_VEX_0F72_REG_6,
 828   MOD_VEX_0F73_REG_2,
 829   MOD_VEX_0F73_REG_3,
 830   MOD_VEX_0F73_REG_6,
 831   MOD_VEX_0F73_REG_7,
 832   MOD_VEX_0FAE_REG_2,
 833   MOD_VEX_0FAE_REG_3,
 834   MOD_VEX_0FD7_PREFIX_2,
 835   MOD_VEX_0FE7_PREFIX_2,
 836   MOD_VEX_0FF0_PREFIX_3,
 837   MOD_VEX_0F381A_PREFIX_2,
 838   MOD_VEX_0F382A_PREFIX_2,
 839   MOD_VEX_0F382C_PREFIX_2,
 840   MOD_VEX_0F382D_PREFIX_2,
 841   MOD_VEX_0F382E_PREFIX_2,
 842   MOD_VEX_0F382F_PREFIX_2,
 843   MOD_VEX_0F385A_PREFIX_2,
 844   MOD_VEX_0F388C_PREFIX_2,
 845   MOD_VEX_0F388E_PREFIX_2,
 846
 847   MOD_EVEX_0F10_PREFIX_1,
 848   MOD_EVEX_0F10_PREFIX_3,
 849   MOD_EVEX_0F11_PREFIX_1,
 850   MOD_EVEX_0F11_PREFIX_3,
 851   MOD_EVEX_0F12_PREFIX_0,
 852   MOD_EVEX_0F16_PREFIX_0,
 853   MOD_EVEX_0F38C6_REG_1,
 854   MOD_EVEX_0F38C6_REG_2,
 855   MOD_EVEX_0F38C6_REG_5,
 856   MOD_EVEX_0F38C6_REG_6,
 857   MOD_EVEX_0F38C7_REG_1,
 858   MOD_EVEX_0F38C7_REG_2,
 859   MOD_EVEX_0F38C7_REG_5,
 860   MOD_EVEX_0F38C7_REG_6
 861 };
 862
 863 enum
 864 {
 865   RM_C6_REG_7 = 0,
 866   RM_C7_REG_7,
 867   RM_0F01_REG_0,
 868   RM_0F01_REG_1,
 869   RM_0F01_REG_2,
 870   RM_0F01_REG_3,
 871   RM_0F01_REG_7,
 872   RM_0FAE_REG_5,
 873   RM_0FAE_REG_6,
 874   RM_0FAE_REG_7
 875 };
 876
 877 enum
 878 {
 879   PREFIX_90 = 0,
 880   PREFIX_0F10,
 881   PREFIX_0F11,
 882   PREFIX_0F12,
 883   PREFIX_0F16,
 884   PREFIX_0F1A,
 885   PREFIX_0F1B,
 886   PREFIX_0F2A,
 887   PREFIX_0F2B,
 888   PREFIX_0F2C,
 889   PREFIX_0F2D,
 890   PREFIX_0F2E,
 891   PREFIX_0F2F,
 892   PREFIX_0F51,
 893   PREFIX_0F52,
 894   PREFIX_0F53,
 895   PREFIX_0F58,
 896   PREFIX_0F59,
 897   PREFIX_0F5A,
 898   PREFIX_0F5B,
 899   PREFIX_0F5C,
 900   PREFIX_0F5D,
 901   PREFIX_0F5E,
 902   PREFIX_0F5F,
 903   PREFIX_0F60,
 904   PREFIX_0F61,
 905   PREFIX_0F62,
 906   PREFIX_0F6C,
 907   PREFIX_0F6D,
 908   PREFIX_0F6F,
 909   PREFIX_0F70,
 910   PREFIX_0F73_REG_3,
 911   PREFIX_0F73_REG_7,
 912   PREFIX_0F78,
 913   PREFIX_0F79,
 914   PREFIX_0F7C,
 915   PREFIX_0F7D,
 916   PREFIX_0F7E,
 917   PREFIX_0F7F,
 918   PREFIX_0FAE_REG_0,
 919   PREFIX_0FAE_REG_1,
 920   PREFIX_0FAE_REG_2,
 921   PREFIX_0FAE_REG_3,
 922   PREFIX_0FAE_REG_6,
 923   PREFIX_0FAE_REG_7,
 924   PREFIX_RM_0_0FAE_REG_7,
 925   PREFIX_0FB8,
 926   PREFIX_0FBC,
 927   PREFIX_0FBD,
 928   PREFIX_0FC2,
 929   PREFIX_0FC3,
 930   PREFIX_MOD_0_0FC7_REG_6,
 931   PREFIX_MOD_3_0FC7_REG_6,
 932   PREFIX_MOD_3_0FC7_REG_7,
 933   PREFIX_0FD0,
 934   PREFIX_0FD6,
 935   PREFIX_0FE6,
 936   PREFIX_0FE7,
 937   PREFIX_0FF0,
 938   PREFIX_0FF7,
 939   PREFIX_0F3810,
 940   PREFIX_0F3814,
 941   PREFIX_0F3815,
 942   PREFIX_0F3817,
 943   PREFIX_0F3820,
 944   PREFIX_0F3821,
 945   PREFIX_0F3822,
 946   PREFIX_0F3823,
 947   PREFIX_0F3824,
 948   PREFIX_0F3825,
 949   PREFIX_0F3828,
 950   PREFIX_0F3829,
 951   PREFIX_0F382A,
 952   PREFIX_0F382B,
 953   PREFIX_0F3830,
 954   PREFIX_0F3831,
 955   PREFIX_0F3832,
 956   PREFIX_0F3833,
 957   PREFIX_0F3834,
 958   PREFIX_0F3835,
 959   PREFIX_0F3837,
 960   PREFIX_0F3838,
 961   PREFIX_0F3839,
 962   PREFIX_0F383A,
 963   PREFIX_0F383B,
 964   PREFIX_0F383C,
 965   PREFIX_0F383D,
 966   PREFIX_0F383E,
 967   PREFIX_0F383F,
 968   PREFIX_0F3840,
 969   PREFIX_0F3841,
 970   PREFIX_0F3880,
 971   PREFIX_0F3881,
 972   PREFIX_0F3882,
 973   PREFIX_0F38C8,
 974   PREFIX_0F38C9,
 975   PREFIX_0F38CA,
 976   PREFIX_0F38CB,
 977   PREFIX_0F38CC,
 978   PREFIX_0F38CD,
 979   PREFIX_0F38DB,
 980   PREFIX_0F38DC,
 981   PREFIX_0F38DD,
 982   PREFIX_0F38DE,
 983   PREFIX_0F38DF,
 984   PREFIX_0F38F0,
 985   PREFIX_0F38F1,
 986   PREFIX_0F38F6,
 987   PREFIX_0F3A08,
 988   PREFIX_0F3A09,
 989   PREFIX_0F3A0A,
 990   PREFIX_0F3A0B,
 991   PREFIX_0F3A0C,
 992   PREFIX_0F3A0D,
 993   PREFIX_0F3A0E,
 994   PREFIX_0F3A14,
 995   PREFIX_0F3A15,
 996   PREFIX_0F3A16,
 997   PREFIX_0F3A17,
 998   PREFIX_0F3A20,
 999   PREFIX_0F3A21,
1000   PREFIX_0F3A22,
1001   PREFIX_0F3A40,
1002   PREFIX_0F3A41,
1003   PREFIX_0F3A42,
1004   PREFIX_0F3A44,
1005   PREFIX_0F3A60,
1006   PREFIX_0F3A61,
1007   PREFIX_0F3A62,
1008   PREFIX_0F3A63,
1009   PREFIX_0F3ACC,
1010   PREFIX_0F3ADF,
1011   PREFIX_VEX_0F10,
1012   PREFIX_VEX_0F11,
1013   PREFIX_VEX_0F12,
1014   PREFIX_VEX_0F16,
1015   PREFIX_VEX_0F2A,
1016   PREFIX_VEX_0F2C,
1017   PREFIX_VEX_0F2D,
1018   PREFIX_VEX_0F2E,
1019   PREFIX_VEX_0F2F,
1020   PREFIX_VEX_0F41,
1021   PREFIX_VEX_0F42,
1022   PREFIX_VEX_0F44,
1023   PREFIX_VEX_0F45,
1024   PREFIX_VEX_0F46,
1025   PREFIX_VEX_0F47,
1026   PREFIX_VEX_0F4A,
1027   PREFIX_VEX_0F4B,
1028   PREFIX_VEX_0F51,
1029   PREFIX_VEX_0F52,
1030   PREFIX_VEX_0F53,
1031   PREFIX_VEX_0F58,
1032   PREFIX_VEX_0F59,
1033   PREFIX_VEX_0F5A,
1034   PREFIX_VEX_0F5B,
1035   PREFIX_VEX_0F5C,
1036   PREFIX_VEX_0F5D,
1037   PREFIX_VEX_0F5E,
1038   PREFIX_VEX_0F5F,
1039   PREFIX_VEX_0F60,
1040   PREFIX_VEX_0F61,
1041   PREFIX_VEX_0F62,
1042   PREFIX_VEX_0F63,
1043   PREFIX_VEX_0F64,
1044   PREFIX_VEX_0F65,
1045   PREFIX_VEX_0F66,
1046   PREFIX_VEX_0F67,
1047   PREFIX_VEX_0F68,
1048   PREFIX_VEX_0F69,
1049   PREFIX_VEX_0F6A,
1050   PREFIX_VEX_0F6B,
1051   PREFIX_VEX_0F6C,
1052   PREFIX_VEX_0F6D,
1053   PREFIX_VEX_0F6E,
1054   PREFIX_VEX_0F6F,
1055   PREFIX_VEX_0F70,
1056   PREFIX_VEX_0F71_REG_2,
1057   PREFIX_VEX_0F71_REG_4,
1058   PREFIX_VEX_0F71_REG_6,
1059   PREFIX_VEX_0F72_REG_2,
1060   PREFIX_VEX_0F72_REG_4,
1061   PREFIX_VEX_0F72_REG_6,
1062   PREFIX_VEX_0F73_REG_2,
1063   PREFIX_VEX_0F73_REG_3,
1064   PREFIX_VEX_0F73_REG_6,
1065   PREFIX_VEX_0F73_REG_7,
1066   PREFIX_VEX_0F74,
1067   PREFIX_VEX_0F75,
1068   PREFIX_VEX_0F76,
1069   PREFIX_VEX_0F77,
1070   PREFIX_VEX_0F7C,
1071   PREFIX_VEX_0F7D,
1072   PREFIX_VEX_0F7E,
1073   PREFIX_VEX_0F7F,
1074   PREFIX_VEX_0F90,
1075   PREFIX_VEX_0F91,
1076   PREFIX_VEX_0F92,
1077   PREFIX_VEX_0F93,
1078   PREFIX_VEX_0F98,
1079   PREFIX_VEX_0F99,
1080   PREFIX_VEX_0FC2,
1081   PREFIX_VEX_0FC4,
1082   PREFIX_VEX_0FC5,
1083   PREFIX_VEX_0FD0,
1084   PREFIX_VEX_0FD1,
1085   PREFIX_VEX_0FD2,
1086   PREFIX_VEX_0FD3,
1087   PREFIX_VEX_0FD4,
1088   PREFIX_VEX_0FD5,
1089   PREFIX_VEX_0FD6,
1090   PREFIX_VEX_0FD7,
1091   PREFIX_VEX_0FD8,
1092   PREFIX_VEX_0FD9,
1093   PREFIX_VEX_0FDA,
1094   PREFIX_VEX_0FDB,
1095   PREFIX_VEX_0FDC,
1096   PREFIX_VEX_0FDD,
1097   PREFIX_VEX_0FDE,
1098   PREFIX_VEX_0FDF,
1099   PREFIX_VEX_0FE0,
1100   PREFIX_VEX_0FE1,
1101   PREFIX_VEX_0FE2,
1102   PREFIX_VEX_0FE3,
1103   PREFIX_VEX_0FE4,
1104   PREFIX_VEX_0FE5,
1105   PREFIX_VEX_0FE6,
1106   PREFIX_VEX_0FE7,
1107   PREFIX_VEX_0FE8,
1108   PREFIX_VEX_0FE9,
1109   PREFIX_VEX_0FEA,
1110   PREFIX_VEX_0FEB,
1111   PREFIX_VEX_0FEC,
1112   PREFIX_VEX_0FED,
1113   PREFIX_VEX_0FEE,
1114   PREFIX_VEX_0FEF,
1115   PREFIX_VEX_0FF0,
1116   PREFIX_VEX_0FF1,
1117   PREFIX_VEX_0FF2,
1118   PREFIX_VEX_0FF3,
1119   PREFIX_VEX_0FF4,
1120   PREFIX_VEX_0FF5,
1121   PREFIX_VEX_0FF6,
1122   PREFIX_VEX_0FF7,
1123   PREFIX_VEX_0FF8,
1124   PREFIX_VEX_0FF9,
1125   PREFIX_VEX_0FFA,
1126   PREFIX_VEX_0FFB,
1127   PREFIX_VEX_0FFC,
1128   PREFIX_VEX_0FFD,
1129   PREFIX_VEX_0FFE,
1130   PREFIX_VEX_0F3800,
1131   PREFIX_VEX_0F3801,
1132   PREFIX_VEX_0F3802,
1133   PREFIX_VEX_0F3803,
1134   PREFIX_VEX_0F3804,
1135   PREFIX_VEX_0F3805,
1136   PREFIX_VEX_0F3806,
1137   PREFIX_VEX_0F3807,
1138   PREFIX_VEX_0F3808,
1139   PREFIX_VEX_0F3809,
1140   PREFIX_VEX_0F380A,
1141   PREFIX_VEX_0F380B,
1142   PREFIX_VEX_0F380C,
1143   PREFIX_VEX_0F380D,
1144   PREFIX_VEX_0F380E,
1145   PREFIX_VEX_0F380F,
1146   PREFIX_VEX_0F3813,
1147   PREFIX_VEX_0F3816,
1148   PREFIX_VEX_0F3817,
1149   PREFIX_VEX_0F3818,
1150   PREFIX_VEX_0F3819,
1151   PREFIX_VEX_0F381A,
1152   PREFIX_VEX_0F381C,
1153   PREFIX_VEX_0F381D,
1154   PREFIX_VEX_0F381E,
1155   PREFIX_VEX_0F3820,
1156   PREFIX_VEX_0F3821,
1157   PREFIX_VEX_0F3822,
1158   PREFIX_VEX_0F3823,
1159   PREFIX_VEX_0F3824,
1160   PREFIX_VEX_0F3825,
1161   PREFIX_VEX_0F3828,
1162   PREFIX_VEX_0F3829,
1163   PREFIX_VEX_0F382A,
1164   PREFIX_VEX_0F382B,
1165   PREFIX_VEX_0F382C,
1166   PREFIX_VEX_0F382D,
1167   PREFIX_VEX_0F382E,
1168   PREFIX_VEX_0F382F,
1169   PREFIX_VEX_0F3830,
1170   PREFIX_VEX_0F3831,
1171   PREFIX_VEX_0F3832,
1172   PREFIX_VEX_0F3833,
1173   PREFIX_VEX_0F3834,
1174   PREFIX_VEX_0F3835,
1175   PREFIX_VEX_0F3836,
1176   PREFIX_VEX_0F3837,
1177   PREFIX_VEX_0F3838,
1178   PREFIX_VEX_0F3839,
1179   PREFIX_VEX_0F383A,
1180   PREFIX_VEX_0F383B,
1181   PREFIX_VEX_0F383C,
1182   PREFIX_VEX_0F383D,
1183   PREFIX_VEX_0F383E,
1184   PREFIX_VEX_0F383F,
1185   PREFIX_VEX_0F3840,
1186   PREFIX_VEX_0F3841,
1187   PREFIX_VEX_0F3845,
1188   PREFIX_VEX_0F3846,
1189   PREFIX_VEX_0F3847,
1190   PREFIX_VEX_0F3858,
1191   PREFIX_VEX_0F3859,
1192   PREFIX_VEX_0F385A,
1193   PREFIX_VEX_0F3878,
1194   PREFIX_VEX_0F3879,
1195   PREFIX_VEX_0F388C,
1196   PREFIX_VEX_0F388E,
1197   PREFIX_VEX_0F3890,
1198   PREFIX_VEX_0F3891,
1199   PREFIX_VEX_0F3892,
1200   PREFIX_VEX_0F3893,
1201   PREFIX_VEX_0F3896,
1202   PREFIX_VEX_0F3897,
1203   PREFIX_VEX_0F3898,
1204   PREFIX_VEX_0F3899,
1205   PREFIX_VEX_0F389A,
1206   PREFIX_VEX_0F389B,
1207   PREFIX_VEX_0F389C,
1208   PREFIX_VEX_0F389D,
1209   PREFIX_VEX_0F389E,
1210   PREFIX_VEX_0F389F,
1211   PREFIX_VEX_0F38A6,
1212   PREFIX_VEX_0F38A7,
1213   PREFIX_VEX_0F38A8,
1214   PREFIX_VEX_0F38A9,
1215   PREFIX_VEX_0F38AA,
1216   PREFIX_VEX_0F38AB,
1217   PREFIX_VEX_0F38AC,
1218   PREFIX_VEX_0F38AD,
1219   PREFIX_VEX_0F38AE,
1220   PREFIX_VEX_0F38AF,
1221   PREFIX_VEX_0F38B6,
1222   PREFIX_VEX_0F38B7,
1223   PREFIX_VEX_0F38B8,
1224   PREFIX_VEX_0F38B9,
1225   PREFIX_VEX_0F38BA,
1226   PREFIX_VEX_0F38BB,
1227   PREFIX_VEX_0F38BC,
1228   PREFIX_VEX_0F38BD,
1229   PREFIX_VEX_0F38BE,
1230   PREFIX_VEX_0F38BF,
1231   PREFIX_VEX_0F38DB,
1232   PREFIX_VEX_0F38DC,
1233   PREFIX_VEX_0F38DD,
1234   PREFIX_VEX_0F38DE,
1235   PREFIX_VEX_0F38DF,
1236   PREFIX_VEX_0F38F2,
1237   PREFIX_VEX_0F38F3_REG_1,
1238   PREFIX_VEX_0F38F3_REG_2,
1239   PREFIX_VEX_0F38F3_REG_3,
1240   PREFIX_VEX_0F38F5,
1241   PREFIX_VEX_0F38F6,
1242   PREFIX_VEX_0F38F7,
1243   PREFIX_VEX_0F3A00,
1244   PREFIX_VEX_0F3A01,
1245   PREFIX_VEX_0F3A02,
1246   PREFIX_VEX_0F3A04,
1247   PREFIX_VEX_0F3A05,
1248   PREFIX_VEX_0F3A06,
1249   PREFIX_VEX_0F3A08,
1250   PREFIX_VEX_0F3A09,
1251   PREFIX_VEX_0F3A0A,
1252   PREFIX_VEX_0F3A0B,
1253   PREFIX_VEX_0F3A0C,
1254   PREFIX_VEX_0F3A0D,
1255   PREFIX_VEX_0F3A0E,
1256   PREFIX_VEX_0F3A0F,
1257   PREFIX_VEX_0F3A14,
1258   PREFIX_VEX_0F3A15,
1259   PREFIX_VEX_0F3A16,
1260   PREFIX_VEX_0F3A17,
1261   PREFIX_VEX_0F3A18,
1262   PREFIX_VEX_0F3A19,
1263   PREFIX_VEX_0F3A1D,
1264   PREFIX_VEX_0F3A20,
1265   PREFIX_VEX_0F3A21,
1266   PREFIX_VEX_0F3A22,
1267   PREFIX_VEX_0F3A30,
1268   PREFIX_VEX_0F3A31,
1269   PREFIX_VEX_0F3A32,
1270   PREFIX_VEX_0F3A33,
1271   PREFIX_VEX_0F3A38,
1272   PREFIX_VEX_0F3A39,
1273   PREFIX_VEX_0F3A40,
1274   PREFIX_VEX_0F3A41,
1275   PREFIX_VEX_0F3A42,
1276   PREFIX_VEX_0F3A44,
1277   PREFIX_VEX_0F3A46,
1278   PREFIX_VEX_0F3A48,
1279   PREFIX_VEX_0F3A49,
1280   PREFIX_VEX_0F3A4A,
1281   PREFIX_VEX_0F3A4B,
1282   PREFIX_VEX_0F3A4C,
1283   PREFIX_VEX_0F3A5C,
1284   PREFIX_VEX_0F3A5D,
1285   PREFIX_VEX_0F3A5E,
1286   PREFIX_VEX_0F3A5F,
1287   PREFIX_VEX_0F3A60,
1288   PREFIX_VEX_0F3A61,
1289   PREFIX_VEX_0F3A62,
1290   PREFIX_VEX_0F3A63,
1291   PREFIX_VEX_0F3A68,
1292   PREFIX_VEX_0F3A69,
1293   PREFIX_VEX_0F3A6A,
1294   PREFIX_VEX_0F3A6B,
1295   PREFIX_VEX_0F3A6C,
1296   PREFIX_VEX_0F3A6D,
1297   PREFIX_VEX_0F3A6E,
1298   PREFIX_VEX_0F3A6F,
1299   PREFIX_VEX_0F3A78,
1300   PREFIX_VEX_0F3A79,
1301   PREFIX_VEX_0F3A7A,
1302   PREFIX_VEX_0F3A7B,
1303   PREFIX_VEX_0F3A7C,
1304   PREFIX_VEX_0F3A7D,
1305   PREFIX_VEX_0F3A7E,
1306   PREFIX_VEX_0F3A7F,
1307   PREFIX_VEX_0F3ADF,
1308   PREFIX_VEX_0F3AF0,
1309
1310   PREFIX_EVEX_0F10,
1311   PREFIX_EVEX_0F11,
1312   PREFIX_EVEX_0F12,
1313   PREFIX_EVEX_0F13,
1314   PREFIX_EVEX_0F14,
1315   PREFIX_EVEX_0F15,
1316   PREFIX_EVEX_0F16,
1317   PREFIX_EVEX_0F17,
1318   PREFIX_EVEX_0F28,
1319   PREFIX_EVEX_0F29,
1320   PREFIX_EVEX_0F2A,
1321   PREFIX_EVEX_0F2B,
1322   PREFIX_EVEX_0F2C,
1323   PREFIX_EVEX_0F2D,
1324   PREFIX_EVEX_0F2E,
1325   PREFIX_EVEX_0F2F,
1326   PREFIX_EVEX_0F51,
1327   PREFIX_EVEX_0F54,
1328   PREFIX_EVEX_0F55,
1329   PREFIX_EVEX_0F56,
1330   PREFIX_EVEX_0F57,
1331   PREFIX_EVEX_0F58,
1332   PREFIX_EVEX_0F59,
1333   PREFIX_EVEX_0F5A,
1334   PREFIX_EVEX_0F5B,
1335   PREFIX_EVEX_0F5C,
1336   PREFIX_EVEX_0F5D,
1337   PREFIX_EVEX_0F5E,
1338   PREFIX_EVEX_0F5F,
1339   PREFIX_EVEX_0F60,
1340   PREFIX_EVEX_0F61,
1341   PREFIX_EVEX_0F62,
1342   PREFIX_EVEX_0F63,
1343   PREFIX_EVEX_0F64,
1344   PREFIX_EVEX_0F65,
1345   PREFIX_EVEX_0F66,
1346   PREFIX_EVEX_0F67,
1347   PREFIX_EVEX_0F68,
1348   PREFIX_EVEX_0F69,
1349   PREFIX_EVEX_0F6A,
1350   PREFIX_EVEX_0F6B,
1351   PREFIX_EVEX_0F6C,
1352   PREFIX_EVEX_0F6D,
1353   PREFIX_EVEX_0F6E,
1354   PREFIX_EVEX_0F6F,
1355   PREFIX_EVEX_0F70,
1356   PREFIX_EVEX_0F71_REG_2,
1357   PREFIX_EVEX_0F71_REG_4,
1358   PREFIX_EVEX_0F71_REG_6,
1359   PREFIX_EVEX_0F72_REG_0,
1360   PREFIX_EVEX_0F72_REG_1,
1361   PREFIX_EVEX_0F72_REG_2,
1362   PREFIX_EVEX_0F72_REG_4,
1363   PREFIX_EVEX_0F72_REG_6,
1364   PREFIX_EVEX_0F73_REG_2,
1365   PREFIX_EVEX_0F73_REG_3,
1366   PREFIX_EVEX_0F73_REG_6,
1367   PREFIX_EVEX_0F73_REG_7,
1368   PREFIX_EVEX_0F74,
1369   PREFIX_EVEX_0F75,
1370   PREFIX_EVEX_0F76,
1371   PREFIX_EVEX_0F78,
1372   PREFIX_EVEX_0F79,
1373   PREFIX_EVEX_0F7A,
1374   PREFIX_EVEX_0F7B,
1375   PREFIX_EVEX_0F7E,
1376   PREFIX_EVEX_0F7F,
1377   PREFIX_EVEX_0FC2,
1378   PREFIX_EVEX_0FC4,
1379   PREFIX_EVEX_0FC5,
1380   PREFIX_EVEX_0FC6,
1381   PREFIX_EVEX_0FD1,
1382   PREFIX_EVEX_0FD2,
1383   PREFIX_EVEX_0FD3,
1384   PREFIX_EVEX_0FD4,
1385   PREFIX_EVEX_0FD5,
1386   PREFIX_EVEX_0FD6,
1387   PREFIX_EVEX_0FD8,
1388   PREFIX_EVEX_0FD9,
1389   PREFIX_EVEX_0FDA,
1390   PREFIX_EVEX_0FDB,
1391   PREFIX_EVEX_0FDC,
1392   PREFIX_EVEX_0FDD,
1393   PREFIX_EVEX_0FDE,
1394   PREFIX_EVEX_0FDF,
1395   PREFIX_EVEX_0FE0,
1396   PREFIX_EVEX_0FE1,
1397   PREFIX_EVEX_0FE2,
1398   PREFIX_EVEX_0FE3,
1399   PREFIX_EVEX_0FE4,
1400   PREFIX_EVEX_0FE5,
1401   PREFIX_EVEX_0FE6,
1402   PREFIX_EVEX_0FE7,
1403   PREFIX_EVEX_0FE8,
1404   PREFIX_EVEX_0FE9,
1405   PREFIX_EVEX_0FEA,
1406   PREFIX_EVEX_0FEB,
1407   PREFIX_EVEX_0FEC,
1408   PREFIX_EVEX_0FED,
1409   PREFIX_EVEX_0FEE,
1410   PREFIX_EVEX_0FEF,
1411   PREFIX_EVEX_0FF1,
1412   PREFIX_EVEX_0FF2,
1413   PREFIX_EVEX_0FF3,
1414   PREFIX_EVEX_0FF4,
1415   PREFIX_EVEX_0FF5,
1416   PREFIX_EVEX_0FF6,
1417   PREFIX_EVEX_0FF8,
1418   PREFIX_EVEX_0FF9,
1419   PREFIX_EVEX_0FFA,
1420   PREFIX_EVEX_0FFB,
1421   PREFIX_EVEX_0FFC,
1422   PREFIX_EVEX_0FFD,
1423   PREFIX_EVEX_0FFE,
1424   PREFIX_EVEX_0F3800,
1425   PREFIX_EVEX_0F3804,
1426   PREFIX_EVEX_0F380B,
1427   PREFIX_EVEX_0F380C,
1428   PREFIX_EVEX_0F380D,
1429   PREFIX_EVEX_0F3810,
1430   PREFIX_EVEX_0F3811,
1431   PREFIX_EVEX_0F3812,
1432   PREFIX_EVEX_0F3813,
1433   PREFIX_EVEX_0F3814,
1434   PREFIX_EVEX_0F3815,
1435   PREFIX_EVEX_0F3816,
1436   PREFIX_EVEX_0F3818,
1437   PREFIX_EVEX_0F3819,
1438   PREFIX_EVEX_0F381A,
1439   PREFIX_EVEX_0F381B,
1440   PREFIX_EVEX_0F381C,
1441   PREFIX_EVEX_0F381D,
1442   PREFIX_EVEX_0F381E,
1443   PREFIX_EVEX_0F381F,
1444   PREFIX_EVEX_0F3820,
1445   PREFIX_EVEX_0F3821,
1446   PREFIX_EVEX_0F3822,
1447   PREFIX_EVEX_0F3823,
1448   PREFIX_EVEX_0F3824,
1449   PREFIX_EVEX_0F3825,
1450   PREFIX_EVEX_0F3826,
1451   PREFIX_EVEX_0F3827,
1452   PREFIX_EVEX_0F3828,
1453   PREFIX_EVEX_0F3829,
1454   PREFIX_EVEX_0F382A,
1455   PREFIX_EVEX_0F382B,
1456   PREFIX_EVEX_0F382C,
1457   PREFIX_EVEX_0F382D,
1458   PREFIX_EVEX_0F3830,
1459   PREFIX_EVEX_0F3831,
1460   PREFIX_EVEX_0F3832,
1461   PREFIX_EVEX_0F3833,
1462   PREFIX_EVEX_0F3834,
1463   PREFIX_EVEX_0F3835,
1464   PREFIX_EVEX_0F3836,
1465   PREFIX_EVEX_0F3837,
1466   PREFIX_EVEX_0F3838,
1467   PREFIX_EVEX_0F3839,
1468   PREFIX_EVEX_0F383A,
1469   PREFIX_EVEX_0F383B,
1470   PREFIX_EVEX_0F383C,
1471   PREFIX_EVEX_0F383D,
1472   PREFIX_EVEX_0F383E,
1473   PREFIX_EVEX_0F383F,
1474   PREFIX_EVEX_0F3840,
1475   PREFIX_EVEX_0F3842,
1476   PREFIX_EVEX_0F3843,
1477   PREFIX_EVEX_0F3844,
1478   PREFIX_EVEX_0F3845,
1479   PREFIX_EVEX_0F3846,
1480   PREFIX_EVEX_0F3847,
1481   PREFIX_EVEX_0F384C,
1482   PREFIX_EVEX_0F384D,
1483   PREFIX_EVEX_0F384E,
1484   PREFIX_EVEX_0F384F,
1485   PREFIX_EVEX_0F3858,
1486   PREFIX_EVEX_0F3859,
1487   PREFIX_EVEX_0F385A,
1488   PREFIX_EVEX_0F385B,
1489   PREFIX_EVEX_0F3864,
1490   PREFIX_EVEX_0F3865,
1491   PREFIX_EVEX_0F3866,
1492   PREFIX_EVEX_0F3875,
1493   PREFIX_EVEX_0F3876,
1494   PREFIX_EVEX_0F3877,
1495   PREFIX_EVEX_0F3878,
1496   PREFIX_EVEX_0F3879,
1497   PREFIX_EVEX_0F387A,
1498   PREFIX_EVEX_0F387B,
1499   PREFIX_EVEX_0F387C,
1500   PREFIX_EVEX_0F387D,
1501   PREFIX_EVEX_0F387E,
1502   PREFIX_EVEX_0F387F,
1503   PREFIX_EVEX_0F3883,
1504   PREFIX_EVEX_0F3888,
1505   PREFIX_EVEX_0F3889,
1506   PREFIX_EVEX_0F388A,
1507   PREFIX_EVEX_0F388B,
1508   PREFIX_EVEX_0F388D,
1509   PREFIX_EVEX_0F3890,
1510   PREFIX_EVEX_0F3891,
1511   PREFIX_EVEX_0F3892,
1512   PREFIX_EVEX_0F3893,
1513   PREFIX_EVEX_0F3896,
1514   PREFIX_EVEX_0F3897,
1515   PREFIX_EVEX_0F3898,
1516   PREFIX_EVEX_0F3899,
1517   PREFIX_EVEX_0F389A,
1518   PREFIX_EVEX_0F389B,
1519   PREFIX_EVEX_0F389C,
1520   PREFIX_EVEX_0F389D,
1521   PREFIX_EVEX_0F389E,
1522   PREFIX_EVEX_0F389F,
1523   PREFIX_EVEX_0F38A0,
1524   PREFIX_EVEX_0F38A1,
1525   PREFIX_EVEX_0F38A2,
1526   PREFIX_EVEX_0F38A3,
1527   PREFIX_EVEX_0F38A6,
1528   PREFIX_EVEX_0F38A7,
1529   PREFIX_EVEX_0F38A8,
1530   PREFIX_EVEX_0F38A9,
1531   PREFIX_EVEX_0F38AA,
1532   PREFIX_EVEX_0F38AB,
1533   PREFIX_EVEX_0F38AC,
1534   PREFIX_EVEX_0F38AD,
1535   PREFIX_EVEX_0F38AE,
1536   PREFIX_EVEX_0F38AF,
1537   PREFIX_EVEX_0F38B4,
1538   PREFIX_EVEX_0F38B5,
1539   PREFIX_EVEX_0F38B6,
1540   PREFIX_EVEX_0F38B7,
1541   PREFIX_EVEX_0F38B8,
1542   PREFIX_EVEX_0F38B9,
1543   PREFIX_EVEX_0F38BA,
1544   PREFIX_EVEX_0F38BB,
1545   PREFIX_EVEX_0F38BC,
1546   PREFIX_EVEX_0F38BD,
1547   PREFIX_EVEX_0F38BE,
1548   PREFIX_EVEX_0F38BF,
1549   PREFIX_EVEX_0F38C4,
1550   PREFIX_EVEX_0F38C6_REG_1,
1551   PREFIX_EVEX_0F38C6_REG_2,
1552   PREFIX_EVEX_0F38C6_REG_5,
1553   PREFIX_EVEX_0F38C6_REG_6,
1554   PREFIX_EVEX_0F38C7_REG_1,
1555   PREFIX_EVEX_0F38C7_REG_2,
1556   PREFIX_EVEX_0F38C7_REG_5,
1557   PREFIX_EVEX_0F38C7_REG_6,
1558   PREFIX_EVEX_0F38C8,
1559   PREFIX_EVEX_0F38CA,
1560   PREFIX_EVEX_0F38CB,
1561   PREFIX_EVEX_0F38CC,
1562   PREFIX_EVEX_0F38CD,
1563
1564   PREFIX_EVEX_0F3A00,
1565   PREFIX_EVEX_0F3A01,
1566   PREFIX_EVEX_0F3A03,
1567   PREFIX_EVEX_0F3A04,
1568   PREFIX_EVEX_0F3A05,
1569   PREFIX_EVEX_0F3A08,
1570   PREFIX_EVEX_0F3A09,
1571   PREFIX_EVEX_0F3A0A,
1572   PREFIX_EVEX_0F3A0B,
1573   PREFIX_EVEX_0F3A0F,
1574   PREFIX_EVEX_0F3A14,
1575   PREFIX_EVEX_0F3A15,
1576   PREFIX_EVEX_0F3A16,
1577   PREFIX_EVEX_0F3A17,
1578   PREFIX_EVEX_0F3A18,
1579   PREFIX_EVEX_0F3A19,
1580   PREFIX_EVEX_0F3A1A,
1581   PREFIX_EVEX_0F3A1B,
1582   PREFIX_EVEX_0F3A1D,
1583   PREFIX_EVEX_0F3A1E,
1584   PREFIX_EVEX_0F3A1F,
1585   PREFIX_EVEX_0F3A20,
1586   PREFIX_EVEX_0F3A21,
1587   PREFIX_EVEX_0F3A22,
1588   PREFIX_EVEX_0F3A23,
1589   PREFIX_EVEX_0F3A25,
1590   PREFIX_EVEX_0F3A26,
1591   PREFIX_EVEX_0F3A27,
1592   PREFIX_EVEX_0F3A38,
1593   PREFIX_EVEX_0F3A39,
1594   PREFIX_EVEX_0F3A3A,
1595   PREFIX_EVEX_0F3A3B,
1596   PREFIX_EVEX_0F3A3E,
1597   PREFIX_EVEX_0F3A3F,
1598   PREFIX_EVEX_0F3A42,
1599   PREFIX_EVEX_0F3A43,
1600   PREFIX_EVEX_0F3A50,
1601   PREFIX_EVEX_0F3A51,
1602   PREFIX_EVEX_0F3A54,
1603   PREFIX_EVEX_0F3A55,
1604   PREFIX_EVEX_0F3A56,
1605   PREFIX_EVEX_0F3A57,
1606   PREFIX_EVEX_0F3A66,
1607   PREFIX_EVEX_0F3A67
1608 };
1609
1610 enum
1611 {
1612   X86_64_06 = 0,
1613   X86_64_07,
1614   X86_64_0D,
1615   X86_64_16,
1616   X86_64_17,
1617   X86_64_1E,
1618   X86_64_1F,
1619   X86_64_27,
1620   X86_64_2F,
1621   X86_64_37,
1622   X86_64_3F,
1623   X86_64_60,
1624   X86_64_61,
1625   X86_64_62,
1626   X86_64_63,
1627   X86_64_6D,
1628   X86_64_6F,
1629   X86_64_9A,
1630   X86_64_C4,
1631   X86_64_C5,
1632   X86_64_CE,
1633   X86_64_D4,
1634   X86_64_D5,
1635   X86_64_EA,
1636   X86_64_0F01_REG_0,
1637   X86_64_0F01_REG_1,
1638   X86_64_0F01_REG_2,
1639   X86_64_0F01_REG_3
1640 };
1641
1642 enum
1643 {
1644   THREE_BYTE_0F38 = 0,
1645   THREE_BYTE_0F3A,
1646   THREE_BYTE_0F7A
1647 };
1648
1649 enum
1650 {
1651   XOP_08 = 0,
1652   XOP_09,
1653   XOP_0A
1654 };
1655
1656 enum
1657 {
1658   VEX_0F = 0,
1659   VEX_0F38,
1660   VEX_0F3A
1661 };
1662
1663 enum
1664 {
1665   EVEX_0F = 0,
1666   EVEX_0F38,
1667   EVEX_0F3A
1668 };
1669
1670 enum
1671 {
1672   VEX_LEN_0F10_P_1 = 0,
1673   VEX_LEN_0F10_P_3,
1674   VEX_LEN_0F11_P_1,
1675   VEX_LEN_0F11_P_3,
1676   VEX_LEN_0F12_P_0_M_0,
1677   VEX_LEN_0F12_P_0_M_1,
1678   VEX_LEN_0F12_P_2,
1679   VEX_LEN_0F13_M_0,
1680   VEX_LEN_0F16_P_0_M_0,
1681   VEX_LEN_0F16_P_0_M_1,
1682   VEX_LEN_0F16_P_2,
1683   VEX_LEN_0F17_M_0,
1684   VEX_LEN_0F2A_P_1,
1685   VEX_LEN_0F2A_P_3,
1686   VEX_LEN_0F2C_P_1,
1687   VEX_LEN_0F2C_P_3,
1688   VEX_LEN_0F2D_P_1,
1689   VEX_LEN_0F2D_P_3,
1690   VEX_LEN_0F2E_P_0,
1691   VEX_LEN_0F2E_P_2,
1692   VEX_LEN_0F2F_P_0,
1693   VEX_LEN_0F2F_P_2,
1694   VEX_LEN_0F41_P_0,
1695   VEX_LEN_0F41_P_2,
1696   VEX_LEN_0F42_P_0,
1697   VEX_LEN_0F42_P_2,
1698   VEX_LEN_0F44_P_0,
1699   VEX_LEN_0F44_P_2,
1700   VEX_LEN_0F45_P_0,
1701   VEX_LEN_0F45_P_2,
1702   VEX_LEN_0F46_P_0,
1703   VEX_LEN_0F46_P_2,
1704   VEX_LEN_0F47_P_0,
1705   VEX_LEN_0F47_P_2,
1706   VEX_LEN_0F4A_P_0,
1707   VEX_LEN_0F4A_P_2,
1708   VEX_LEN_0F4B_P_0,
1709   VEX_LEN_0F4B_P_2,
1710   VEX_LEN_0F51_P_1,
1711   VEX_LEN_0F51_P_3,
1712   VEX_LEN_0F52_P_1,
1713   VEX_LEN_0F53_P_1,
1714   VEX_LEN_0F58_P_1,
1715   VEX_LEN_0F58_P_3,
1716   VEX_LEN_0F59_P_1,
1717   VEX_LEN_0F59_P_3,
1718   VEX_LEN_0F5A_P_1,
1719   VEX_LEN_0F5A_P_3,
1720   VEX_LEN_0F5C_P_1,
1721   VEX_LEN_0F5C_P_3,
1722   VEX_LEN_0F5D_P_1,
1723   VEX_LEN_0F5D_P_3,
1724   VEX_LEN_0F5E_P_1,
1725   VEX_LEN_0F5E_P_3,
1726   VEX_LEN_0F5F_P_1,
1727   VEX_LEN_0F5F_P_3,
1728   VEX_LEN_0F6E_P_2,
1729   VEX_LEN_0F7E_P_1,
1730   VEX_LEN_0F7E_P_2,
1731   VEX_LEN_0F90_P_0,
1732   VEX_LEN_0F90_P_2,
1733   VEX_LEN_0F91_P_0,
1734   VEX_LEN_0F91_P_2,
1735   VEX_LEN_0F92_P_0,
1736   VEX_LEN_0F92_P_2,
1737   VEX_LEN_0F92_P_3,
1738   VEX_LEN_0F93_P_0,
1739   VEX_LEN_0F93_P_2,
1740   VEX_LEN_0F93_P_3,
1741   VEX_LEN_0F98_P_0,
1742   VEX_LEN_0F98_P_2,
1743   VEX_LEN_0F99_P_0,
1744   VEX_LEN_0F99_P_2,
1745   VEX_LEN_0FAE_R_2_M_0,
1746   VEX_LEN_0FAE_R_3_M_0,
1747   VEX_LEN_0FC2_P_1,
1748   VEX_LEN_0FC2_P_3,
1749   VEX_LEN_0FC4_P_2,
1750   VEX_LEN_0FC5_P_2,
1751   VEX_LEN_0FD6_P_2,
1752   VEX_LEN_0FF7_P_2,
1753   VEX_LEN_0F3816_P_2,
1754   VEX_LEN_0F3819_P_2,
1755   VEX_LEN_0F381A_P_2_M_0,
1756   VEX_LEN_0F3836_P_2,
1757   VEX_LEN_0F3841_P_2,
1758   VEX_LEN_0F385A_P_2_M_0,
1759   VEX_LEN_0F38DB_P_2,
1760   VEX_LEN_0F38DC_P_2,
1761   VEX_LEN_0F38DD_P_2,
1762   VEX_LEN_0F38DE_P_2,
1763   VEX_LEN_0F38DF_P_2,
1764   VEX_LEN_0F38F2_P_0,
1765   VEX_LEN_0F38F3_R_1_P_0,
1766   VEX_LEN_0F38F3_R_2_P_0,
1767   VEX_LEN_0F38F3_R_3_P_0,
1768   VEX_LEN_0F38F5_P_0,
1769   VEX_LEN_0F38F5_P_1,
1770   VEX_LEN_0F38F5_P_3,
1771   VEX_LEN_0F38F6_P_3,
1772   VEX_LEN_0F38F7_P_0,
1773   VEX_LEN_0F38F7_P_1,
1774   VEX_LEN_0F38F7_P_2,
1775   VEX_LEN_0F38F7_P_3,
1776   VEX_LEN_0F3A00_P_2,
1777   VEX_LEN_0F3A01_P_2,
1778   VEX_LEN_0F3A06_P_2,
1779   VEX_LEN_0F3A0A_P_2,
1780   VEX_LEN_0F3A0B_P_2,
1781   VEX_LEN_0F3A14_P_2,
1782   VEX_LEN_0F3A15_P_2,
1783   VEX_LEN_0F3A16_P_2,
1784   VEX_LEN_0F3A17_P_2,
1785   VEX_LEN_0F3A18_P_2,
1786   VEX_LEN_0F3A19_P_2,
1787   VEX_LEN_0F3A20_P_2,
1788   VEX_LEN_0F3A21_P_2,
1789   VEX_LEN_0F3A22_P_2,
1790   VEX_LEN_0F3A30_P_2,
1791   VEX_LEN_0F3A31_P_2,
1792   VEX_LEN_0F3A32_P_2,
1793   VEX_LEN_0F3A33_P_2,
1794   VEX_LEN_0F3A38_P_2,
1795   VEX_LEN_0F3A39_P_2,
1796   VEX_LEN_0F3A41_P_2,
1797   VEX_LEN_0F3A44_P_2,
1798   VEX_LEN_0F3A46_P_2,
1799   VEX_LEN_0F3A60_P_2,
1800   VEX_LEN_0F3A61_P_2,
1801   VEX_LEN_0F3A62_P_2,
1802   VEX_LEN_0F3A63_P_2,
1803   VEX_LEN_0F3A6A_P_2,
1804   VEX_LEN_0F3A6B_P_2,
1805   VEX_LEN_0F3A6E_P_2,
1806   VEX_LEN_0F3A6F_P_2,
1807   VEX_LEN_0F3A7A_P_2,
1808   VEX_LEN_0F3A7B_P_2,
1809   VEX_LEN_0F3A7E_P_2,
1810   VEX_LEN_0F3A7F_P_2,
1811   VEX_LEN_0F3ADF_P_2,
1812   VEX_LEN_0F3AF0_P_3,
1813   VEX_LEN_0FXOP_08_CC,
1814   VEX_LEN_0FXOP_08_CD,
1815   VEX_LEN_0FXOP_08_CE,
1816   VEX_LEN_0FXOP_08_CF,
1817   VEX_LEN_0FXOP_08_EC,
1818   VEX_LEN_0FXOP_08_ED,
1819   VEX_LEN_0FXOP_08_EE,
1820   VEX_LEN_0FXOP_08_EF,
1821   VEX_LEN_0FXOP_09_80,
1822   VEX_LEN_0FXOP_09_81
1823 };
1824
1825 enum
1826 {
1827   VEX_W_0F10_P_0 = 0,
1828   VEX_W_0F10_P_1,
1829   VEX_W_0F10_P_2,
1830   VEX_W_0F10_P_3,
1831   VEX_W_0F11_P_0,
1832   VEX_W_0F11_P_1,
1833   VEX_W_0F11_P_2,
1834   VEX_W_0F11_P_3,
1835   VEX_W_0F12_P_0_M_0,
1836   VEX_W_0F12_P_0_M_1,
1837   VEX_W_0F12_P_1,
1838   VEX_W_0F12_P_2,
1839   VEX_W_0F12_P_3,
1840   VEX_W_0F13_M_0,
1841   VEX_W_0F14,
1842   VEX_W_0F15,
1843   VEX_W_0F16_P_0_M_0,
1844   VEX_W_0F16_P_0_M_1,
1845   VEX_W_0F16_P_1,
1846   VEX_W_0F16_P_2,
1847   VEX_W_0F17_M_0,
1848   VEX_W_0F28,
1849   VEX_W_0F29,
1850   VEX_W_0F2B_M_0,
1851   VEX_W_0F2E_P_0,
1852   VEX_W_0F2E_P_2,
1853   VEX_W_0F2F_P_0,
1854   VEX_W_0F2F_P_2,
1855   VEX_W_0F41_P_0_LEN_1,
1856   VEX_W_0F41_P_2_LEN_1,
1857   VEX_W_0F42_P_0_LEN_1,
1858   VEX_W_0F42_P_2_LEN_1,
1859   VEX_W_0F44_P_0_LEN_0,
1860   VEX_W_0F44_P_2_LEN_0,
1861   VEX_W_0F45_P_0_LEN_1,
1862   VEX_W_0F45_P_2_LEN_1,
1863   VEX_W_0F46_P_0_LEN_1,
1864   VEX_W_0F46_P_2_LEN_1,
1865   VEX_W_0F47_P_0_LEN_1,
1866   VEX_W_0F47_P_2_LEN_1,
1867   VEX_W_0F4A_P_0_LEN_1,
1868   VEX_W_0F4A_P_2_LEN_1,
1869   VEX_W_0F4B_P_0_LEN_1,
1870   VEX_W_0F4B_P_2_LEN_1,
1871   VEX_W_0F50_M_0,
1872   VEX_W_0F51_P_0,
1873   VEX_W_0F51_P_1,
1874   VEX_W_0F51_P_2,
1875   VEX_W_0F51_P_3,
1876   VEX_W_0F52_P_0,
1877   VEX_W_0F52_P_1,
1878   VEX_W_0F53_P_0,
1879   VEX_W_0F53_P_1,
1880   VEX_W_0F58_P_0,
1881   VEX_W_0F58_P_1,
1882   VEX_W_0F58_P_2,
1883   VEX_W_0F58_P_3,
1884   VEX_W_0F59_P_0,
1885   VEX_W_0F59_P_1,
1886   VEX_W_0F59_P_2,
1887   VEX_W_0F59_P_3,
1888   VEX_W_0F5A_P_0,
1889   VEX_W_0F5A_P_1,
1890   VEX_W_0F5A_P_3,
1891   VEX_W_0F5B_P_0,
1892   VEX_W_0F5B_P_1,
1893   VEX_W_0F5B_P_2,
1894   VEX_W_0F5C_P_0,
1895   VEX_W_0F5C_P_1,
1896   VEX_W_0F5C_P_2,
1897   VEX_W_0F5C_P_3,
1898   VEX_W_0F5D_P_0,
1899   VEX_W_0F5D_P_1,
1900   VEX_W_0F5D_P_2,
1901   VEX_W_0F5D_P_3,
1902   VEX_W_0F5E_P_0,
1903   VEX_W_0F5E_P_1,
1904   VEX_W_0F5E_P_2,
1905   VEX_W_0F5E_P_3,
1906   VEX_W_0F5F_P_0,
1907   VEX_W_0F5F_P_1,
1908   VEX_W_0F5F_P_2,
1909   VEX_W_0F5F_P_3,
1910   VEX_W_0F60_P_2,
1911   VEX_W_0F61_P_2,
1912   VEX_W_0F62_P_2,
1913   VEX_W_0F63_P_2,
1914   VEX_W_0F64_P_2,
1915   VEX_W_0F65_P_2,
1916   VEX_W_0F66_P_2,
1917   VEX_W_0F67_P_2,
1918   VEX_W_0F68_P_2,
1919   VEX_W_0F69_P_2,
1920   VEX_W_0F6A_P_2,
1921   VEX_W_0F6B_P_2,
1922   VEX_W_0F6C_P_2,
1923   VEX_W_0F6D_P_2,
1924   VEX_W_0F6F_P_1,
1925   VEX_W_0F6F_P_2,
1926   VEX_W_0F70_P_1,
1927   VEX_W_0F70_P_2,
1928   VEX_W_0F70_P_3,
1929   VEX_W_0F71_R_2_P_2,
1930   VEX_W_0F71_R_4_P_2,
1931   VEX_W_0F71_R_6_P_2,
1932   VEX_W_0F72_R_2_P_2,
1933   VEX_W_0F72_R_4_P_2,
1934   VEX_W_0F72_R_6_P_2,
1935   VEX_W_0F73_R_2_P_2,
1936   VEX_W_0F73_R_3_P_2,
1937   VEX_W_0F73_R_6_P_2,
1938   VEX_W_0F73_R_7_P_2,
1939   VEX_W_0F74_P_2,
1940   VEX_W_0F75_P_2,
1941   VEX_W_0F76_P_2,
1942   VEX_W_0F77_P_0,
1943   VEX_W_0F7C_P_2,
1944   VEX_W_0F7C_P_3,
1945   VEX_W_0F7D_P_2,
1946   VEX_W_0F7D_P_3,
1947   VEX_W_0F7E_P_1,
1948   VEX_W_0F7F_P_1,
1949   VEX_W_0F7F_P_2,
1950   VEX_W_0F90_P_0_LEN_0,
1951   VEX_W_0F90_P_2_LEN_0,
1952   VEX_W_0F91_P_0_LEN_0,
1953   VEX_W_0F91_P_2_LEN_0,
1954   VEX_W_0F92_P_0_LEN_0,
1955   VEX_W_0F92_P_2_LEN_0,
1956   VEX_W_0F92_P_3_LEN_0,
1957   VEX_W_0F93_P_0_LEN_0,
1958   VEX_W_0F93_P_2_LEN_0,
1959   VEX_W_0F93_P_3_LEN_0,
1960   VEX_W_0F98_P_0_LEN_0,
1961   VEX_W_0F98_P_2_LEN_0,
1962   VEX_W_0F99_P_0_LEN_0,
1963   VEX_W_0F99_P_2_LEN_0,
1964   VEX_W_0FAE_R_2_M_0,
1965   VEX_W_0FAE_R_3_M_0,
1966   VEX_W_0FC2_P_0,
1967   VEX_W_0FC2_P_1,
1968   VEX_W_0FC2_P_2,
1969   VEX_W_0FC2_P_3,
1970   VEX_W_0FC4_P_2,
1971   VEX_W_0FC5_P_2,
1972   VEX_W_0FD0_P_2,
1973   VEX_W_0FD0_P_3,
1974   VEX_W_0FD1_P_2,
1975   VEX_W_0FD2_P_2,
1976   VEX_W_0FD3_P_2,
1977   VEX_W_0FD4_P_2,
1978   VEX_W_0FD5_P_2,
1979   VEX_W_0FD6_P_2,
1980   VEX_W_0FD7_P_2_M_1,
1981   VEX_W_0FD8_P_2,
1982   VEX_W_0FD9_P_2,
1983   VEX_W_0FDA_P_2,
1984   VEX_W_0FDB_P_2,
1985   VEX_W_0FDC_P_2,
1986   VEX_W_0FDD_P_2,
1987   VEX_W_0FDE_P_2,
1988   VEX_W_0FDF_P_2,
1989   VEX_W_0FE0_P_2,
1990   VEX_W_0FE1_P_2,
1991   VEX_W_0FE2_P_2,
1992   VEX_W_0FE3_P_2,
1993   VEX_W_0FE4_P_2,
1994   VEX_W_0FE5_P_2,
1995   VEX_W_0FE6_P_1,
1996   VEX_W_0FE6_P_2,
1997   VEX_W_0FE6_P_3,
1998   VEX_W_0FE7_P_2_M_0,
1999   VEX_W_0FE8_P_2,
2000   VEX_W_0FE9_P_2,
2001   VEX_W_0FEA_P_2,
2002   VEX_W_0FEB_P_2,
2003   VEX_W_0FEC_P_2,
2004   VEX_W_0FED_P_2,
2005   VEX_W_0FEE_P_2,
2006   VEX_W_0FEF_P_2,
2007   VEX_W_0FF0_P_3_M_0,
2008   VEX_W_0FF1_P_2,
2009   VEX_W_0FF2_P_2,
2010   VEX_W_0FF3_P_2,
2011   VEX_W_0FF4_P_2,
2012   VEX_W_0FF5_P_2,
2013   VEX_W_0FF6_P_2,
2014   VEX_W_0FF7_P_2,
2015   VEX_W_0FF8_P_2,
2016   VEX_W_0FF9_P_2,
2017   VEX_W_0FFA_P_2,
2018   VEX_W_0FFB_P_2,
2019   VEX_W_0FFC_P_2,
2020   VEX_W_0FFD_P_2,
2021   VEX_W_0FFE_P_2,
2022   VEX_W_0F3800_P_2,
2023   VEX_W_0F3801_P_2,
2024   VEX_W_0F3802_P_2,
2025   VEX_W_0F3803_P_2,
2026   VEX_W_0F3804_P_2,
2027   VEX_W_0F3805_P_2,
2028   VEX_W_0F3806_P_2,
2029   VEX_W_0F3807_P_2,
2030   VEX_W_0F3808_P_2,
2031   VEX_W_0F3809_P_2,
2032   VEX_W_0F380A_P_2,
2033   VEX_W_0F380B_P_2,
2034   VEX_W_0F380C_P_2,
2035   VEX_W_0F380D_P_2,
2036   VEX_W_0F380E_P_2,
2037   VEX_W_0F380F_P_2,
2038   VEX_W_0F3816_P_2,
2039   VEX_W_0F3817_P_2,
2040   VEX_W_0F3818_P_2,
2041   VEX_W_0F3819_P_2,
2042   VEX_W_0F381A_P_2_M_0,
2043   VEX_W_0F381C_P_2,
2044   VEX_W_0F381D_P_2,
2045   VEX_W_0F381E_P_2,
2046   VEX_W_0F3820_P_2,
2047   VEX_W_0F3821_P_2,
2048   VEX_W_0F3822_P_2,
2049   VEX_W_0F3823_P_2,
2050   VEX_W_0F3824_P_2,
2051   VEX_W_0F3825_P_2,
2052   VEX_W_0F3828_P_2,
2053   VEX_W_0F3829_P_2,
2054   VEX_W_0F382A_P_2_M_0,
2055   VEX_W_0F382B_P_2,
2056   VEX_W_0F382C_P_2_M_0,
2057   VEX_W_0F382D_P_2_M_0,
2058   VEX_W_0F382E_P_2_M_0,
2059   VEX_W_0F382F_P_2_M_0,
2060   VEX_W_0F3830_P_2,
2061   VEX_W_0F3831_P_2,
2062   VEX_W_0F3832_P_2,
2063   VEX_W_0F3833_P_2,
2064   VEX_W_0F3834_P_2,
2065   VEX_W_0F3835_P_2,
2066   VEX_W_0F3836_P_2,
2067   VEX_W_0F3837_P_2,
2068   VEX_W_0F3838_P_2,
2069   VEX_W_0F3839_P_2,
2070   VEX_W_0F383A_P_2,
2071   VEX_W_0F383B_P_2,
2072   VEX_W_0F383C_P_2,
2073   VEX_W_0F383D_P_2,
2074   VEX_W_0F383E_P_2,
2075   VEX_W_0F383F_P_2,
2076   VEX_W_0F3840_P_2,
2077   VEX_W_0F3841_P_2,
2078   VEX_W_0F3846_P_2,
2079   VEX_W_0F3858_P_2,
2080   VEX_W_0F3859_P_2,
2081   VEX_W_0F385A_P_2_M_0,
2082   VEX_W_0F3878_P_2,
2083   VEX_W_0F3879_P_2,
2084   VEX_W_0F38DB_P_2,
2085   VEX_W_0F38DC_P_2,
2086   VEX_W_0F38DD_P_2,
2087   VEX_W_0F38DE_P_2,
2088   VEX_W_0F38DF_P_2,
2089   VEX_W_0F3A00_P_2,
2090   VEX_W_0F3A01_P_2,
2091   VEX_W_0F3A02_P_2,
2092   VEX_W_0F3A04_P_2,
2093   VEX_W_0F3A05_P_2,
2094   VEX_W_0F3A06_P_2,
2095   VEX_W_0F3A08_P_2,
2096   VEX_W_0F3A09_P_2,
2097   VEX_W_0F3A0A_P_2,
2098   VEX_W_0F3A0B_P_2,
2099   VEX_W_0F3A0C_P_2,
2100   VEX_W_0F3A0D_P_2,
2101   VEX_W_0F3A0E_P_2,
2102   VEX_W_0F3A0F_P_2,
2103   VEX_W_0F3A14_P_2,
2104   VEX_W_0F3A15_P_2,
2105   VEX_W_0F3A18_P_2,
2106   VEX_W_0F3A19_P_2,
2107   VEX_W_0F3A20_P_2,
2108   VEX_W_0F3A21_P_2,
2109   VEX_W_0F3A30_P_2_LEN_0,
2110   VEX_W_0F3A31_P_2_LEN_0,
2111   VEX_W_0F3A32_P_2_LEN_0,
2112   VEX_W_0F3A33_P_2_LEN_0,
2113   VEX_W_0F3A38_P_2,
2114   VEX_W_0F3A39_P_2,
2115   VEX_W_0F3A40_P_2,
2116   VEX_W_0F3A41_P_2,
2117   VEX_W_0F3A42_P_2,
2118   VEX_W_0F3A44_P_2,
2119   VEX_W_0F3A46_P_2,
2120   VEX_W_0F3A48_P_2,
2121   VEX_W_0F3A49_P_2,
2122   VEX_W_0F3A4A_P_2,
2123   VEX_W_0F3A4B_P_2,
2124   VEX_W_0F3A4C_P_2,
2125   VEX_W_0F3A60_P_2,
2126   VEX_W_0F3A61_P_2,
2127   VEX_W_0F3A62_P_2,
2128   VEX_W_0F3A63_P_2,
2129   VEX_W_0F3ADF_P_2,
2130
2131   EVEX_W_0F10_P_0,
2132   EVEX_W_0F10_P_1_M_0,
2133   EVEX_W_0F10_P_1_M_1,
2134   EVEX_W_0F10_P_2,
2135   EVEX_W_0F10_P_3_M_0,
2136   EVEX_W_0F10_P_3_M_1,
2137   EVEX_W_0F11_P_0,
2138   EVEX_W_0F11_P_1_M_0,
2139   EVEX_W_0F11_P_1_M_1,
2140   EVEX_W_0F11_P_2,
2141   EVEX_W_0F11_P_3_M_0,
2142   EVEX_W_0F11_P_3_M_1,
2143   EVEX_W_0F12_P_0_M_0,
2144   EVEX_W_0F12_P_0_M_1,
2145   EVEX_W_0F12_P_1,
2146   EVEX_W_0F12_P_2,
2147   EVEX_W_0F12_P_3,
2148   EVEX_W_0F13_P_0,
2149   EVEX_W_0F13_P_2,
2150   EVEX_W_0F14_P_0,
2151   EVEX_W_0F14_P_2,
2152   EVEX_W_0F15_P_0,
2153   EVEX_W_0F15_P_2,
2154   EVEX_W_0F16_P_0_M_0,
2155   EVEX_W_0F16_P_0_M_1,
2156   EVEX_W_0F16_P_1,
2157   EVEX_W_0F16_P_2,
2158   EVEX_W_0F17_P_0,
2159   EVEX_W_0F17_P_2,
2160   EVEX_W_0F28_P_0,
2161   EVEX_W_0F28_P_2,
2162   EVEX_W_0F29_P_0,
2163   EVEX_W_0F29_P_2,
2164   EVEX_W_0F2A_P_1,
2165   EVEX_W_0F2A_P_3,
2166   EVEX_W_0F2B_P_0,
2167   EVEX_W_0F2B_P_2,
2168   EVEX_W_0F2E_P_0,
2169   EVEX_W_0F2E_P_2,
2170   EVEX_W_0F2F_P_0,
2171   EVEX_W_0F2F_P_2,
2172   EVEX_W_0F51_P_0,
2173   EVEX_W_0F51_P_1,
2174   EVEX_W_0F51_P_2,
2175   EVEX_W_0F51_P_3,
2176   EVEX_W_0F54_P_0,
2177   EVEX_W_0F54_P_2,
2178   EVEX_W_0F55_P_0,
2179   EVEX_W_0F55_P_2,
2180   EVEX_W_0F56_P_0,
2181   EVEX_W_0F56_P_2,
2182   EVEX_W_0F57_P_0,
2183   EVEX_W_0F57_P_2,
2184   EVEX_W_0F58_P_0,
2185   EVEX_W_0F58_P_1,
2186   EVEX_W_0F58_P_2,
2187   EVEX_W_0F58_P_3,
2188   EVEX_W_0F59_P_0,
2189   EVEX_W_0F59_P_1,
2190   EVEX_W_0F59_P_2,
2191   EVEX_W_0F59_P_3,
2192   EVEX_W_0F5A_P_0,
2193   EVEX_W_0F5A_P_1,
2194   EVEX_W_0F5A_P_2,
2195   EVEX_W_0F5A_P_3,
2196   EVEX_W_0F5B_P_0,
2197   EVEX_W_0F5B_P_1,
2198   EVEX_W_0F5B_P_2,
2199   EVEX_W_0F5C_P_0,
2200   EVEX_W_0F5C_P_1,
2201   EVEX_W_0F5C_P_2,
2202   EVEX_W_0F5C_P_3,
2203   EVEX_W_0F5D_P_0,
2204   EVEX_W_0F5D_P_1,
2205   EVEX_W_0F5D_P_2,
2206   EVEX_W_0F5D_P_3,
2207   EVEX_W_0F5E_P_0,
2208   EVEX_W_0F5E_P_1,
2209   EVEX_W_0F5E_P_2,
2210   EVEX_W_0F5E_P_3,
2211   EVEX_W_0F5F_P_0,
2212   EVEX_W_0F5F_P_1,
2213   EVEX_W_0F5F_P_2,
2214   EVEX_W_0F5F_P_3,
2215   EVEX_W_0F62_P_2,
2216   EVEX_W_0F66_P_2,
2217   EVEX_W_0F6A_P_2,
2218   EVEX_W_0F6B_P_2,
2219   EVEX_W_0F6C_P_2,
2220   EVEX_W_0F6D_P_2,
2221   EVEX_W_0F6E_P_2,
2222   EVEX_W_0F6F_P_1,
2223   EVEX_W_0F6F_P_2,
2224   EVEX_W_0F6F_P_3,
2225   EVEX_W_0F70_P_2,
2226   EVEX_W_0F72_R_2_P_2,
2227   EVEX_W_0F72_R_6_P_2,
2228   EVEX_W_0F73_R_2_P_2,
2229   EVEX_W_0F73_R_6_P_2,
2230   EVEX_W_0F76_P_2,
2231   EVEX_W_0F78_P_0,
2232   EVEX_W_0F78_P_2,
2233   EVEX_W_0F79_P_0,
2234   EVEX_W_0F79_P_2,
2235   EVEX_W_0F7A_P_1,
2236   EVEX_W_0F7A_P_2,
2237   EVEX_W_0F7A_P_3,
2238   EVEX_W_0F7B_P_1,
2239   EVEX_W_0F7B_P_2,
2240   EVEX_W_0F7B_P_3,
2241   EVEX_W_0F7E_P_1,
2242   EVEX_W_0F7E_P_2,
2243   EVEX_W_0F7F_P_1,
2244   EVEX_W_0F7F_P_2,
2245   EVEX_W_0F7F_P_3,
2246   EVEX_W_0FC2_P_0,
2247   EVEX_W_0FC2_P_1,
2248   EVEX_W_0FC2_P_2,
2249   EVEX_W_0FC2_P_3,
2250   EVEX_W_0FC6_P_0,
2251   EVEX_W_0FC6_P_2,
2252   EVEX_W_0FD2_P_2,
2253   EVEX_W_0FD3_P_2,
2254   EVEX_W_0FD4_P_2,
2255   EVEX_W_0FD6_P_2,
2256   EVEX_W_0FE6_P_1,
2257   EVEX_W_0FE6_P_2,
2258   EVEX_W_0FE6_P_3,
2259   EVEX_W_0FE7_P_2,
2260   EVEX_W_0FF2_P_2,
2261   EVEX_W_0FF3_P_2,
2262   EVEX_W_0FF4_P_2,
2263   EVEX_W_0FFA_P_2,
2264   EVEX_W_0FFB_P_2,
2265   EVEX_W_0FFE_P_2,
2266   EVEX_W_0F380C_P_2,
2267   EVEX_W_0F380D_P_2,
2268   EVEX_W_0F3810_P_1,
2269   EVEX_W_0F3810_P_2,
2270   EVEX_W_0F3811_P_1,
2271   EVEX_W_0F3811_P_2,
2272   EVEX_W_0F3812_P_1,
2273   EVEX_W_0F3812_P_2,
2274   EVEX_W_0F3813_P_1,
2275   EVEX_W_0F3813_P_2,
2276   EVEX_W_0F3814_P_1,
2277   EVEX_W_0F3815_P_1,
2278   EVEX_W_0F3818_P_2,
2279   EVEX_W_0F3819_P_2,
2280   EVEX_W_0F381A_P_2,
2281   EVEX_W_0F381B_P_2,
2282   EVEX_W_0F381E_P_2,
2283   EVEX_W_0F381F_P_2,
2284   EVEX_W_0F3820_P_1,
2285   EVEX_W_0F3821_P_1,
2286   EVEX_W_0F3822_P_1,
2287   EVEX_W_0F3823_P_1,
2288   EVEX_W_0F3824_P_1,
2289   EVEX_W_0F3825_P_1,
2290   EVEX_W_0F3825_P_2,
2291   EVEX_W_0F3826_P_1,
2292   EVEX_W_0F3826_P_2,
2293   EVEX_W_0F3828_P_1,
2294   EVEX_W_0F3828_P_2,
2295   EVEX_W_0F3829_P_1,
2296   EVEX_W_0F3829_P_2,
2297   EVEX_W_0F382A_P_1,
2298   EVEX_W_0F382A_P_2,
2299   EVEX_W_0F382B_P_2,
2300   EVEX_W_0F3830_P_1,
2301   EVEX_W_0F3831_P_1,
2302   EVEX_W_0F3832_P_1,
2303   EVEX_W_0F3833_P_1,
2304   EVEX_W_0F3834_P_1,
2305   EVEX_W_0F3835_P_1,
2306   EVEX_W_0F3835_P_2,
2307   EVEX_W_0F3837_P_2,
2308   EVEX_W_0F3838_P_1,
2309   EVEX_W_0F3839_P_1,
2310   EVEX_W_0F383A_P_1,
2311   EVEX_W_0F3840_P_2,
2312   EVEX_W_0F3858_P_2,
2313   EVEX_W_0F3859_P_2,
2314   EVEX_W_0F385A_P_2,
2315   EVEX_W_0F385B_P_2,
2316   EVEX_W_0F3866_P_2,
2317   EVEX_W_0F3875_P_2,
2318   EVEX_W_0F3878_P_2,
2319   EVEX_W_0F3879_P_2,
2320   EVEX_W_0F387A_P_2,
2321   EVEX_W_0F387B_P_2,
2322   EVEX_W_0F387D_P_2,
2323   EVEX_W_0F3883_P_2,
2324   EVEX_W_0F388D_P_2,
2325   EVEX_W_0F3891_P_2,
2326   EVEX_W_0F3893_P_2,
2327   EVEX_W_0F38A1_P_2,
2328   EVEX_W_0F38A3_P_2,
2329   EVEX_W_0F38C7_R_1_P_2,
2330   EVEX_W_0F38C7_R_2_P_2,
2331   EVEX_W_0F38C7_R_5_P_2,
2332   EVEX_W_0F38C7_R_6_P_2,
2333
2334   EVEX_W_0F3A00_P_2,
2335   EVEX_W_0F3A01_P_2,
2336   EVEX_W_0F3A04_P_2,
2337   EVEX_W_0F3A05_P_2,
2338   EVEX_W_0F3A08_P_2,
2339   EVEX_W_0F3A09_P_2,
2340   EVEX_W_0F3A0A_P_2,
2341   EVEX_W_0F3A0B_P_2,
2342   EVEX_W_0F3A16_P_2,
2343   EVEX_W_0F3A18_P_2,
2344   EVEX_W_0F3A19_P_2,
2345   EVEX_W_0F3A1A_P_2,
2346   EVEX_W_0F3A1B_P_2,
2347   EVEX_W_0F3A1D_P_2,
2348   EVEX_W_0F3A21_P_2,
2349   EVEX_W_0F3A22_P_2,
2350   EVEX_W_0F3A23_P_2,
2351   EVEX_W_0F3A38_P_2,
2352   EVEX_W_0F3A39_P_2,
2353   EVEX_W_0F3A3A_P_2,
2354   EVEX_W_0F3A3B_P_2,
2355   EVEX_W_0F3A3E_P_2,
2356   EVEX_W_0F3A3F_P_2,
2357   EVEX_W_0F3A42_P_2,
2358   EVEX_W_0F3A43_P_2,
2359   EVEX_W_0F3A50_P_2,
2360   EVEX_W_0F3A51_P_2,
2361   EVEX_W_0F3A56_P_2,
2362   EVEX_W_0F3A57_P_2,
2363   EVEX_W_0F3A66_P_2,
2364   EVEX_W_0F3A67_P_2
2365 };
2366
2367 typedef void (*op_rtn) (int bytemode, int sizeflag);
2368
2369 struct dis386 {
2370   const char *name;
2371   struct
2372     {
2373       op_rtn rtn;
2374       int bytemode;
2375     } op[MAX_OPERANDS];
2376   unsigned int prefix_requirement;
2377 };
2378
2379 /* Upper case letters in the instruction names here are macros.
2380    'A' => print 'b' if no register operands or suffix_always is true
2381    'B' => print 'b' if suffix_always is true
2382    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2383           size prefix
2384    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2385           suffix_always is true
2386    'E' => print 'e' if 32-bit form of jcxz
2387    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2388    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2389    'H' => print ",pt" or ",pn" branch hint
2390    'I' => honor following macro letter even in Intel mode (implemented only
2391           for some of the macro letters)
2392    'J' => print 'l'
2393    'K' => print 'd' or 'q' if rex prefix is present.
2394    'L' => print 'l' if suffix_always is true
2395    'M' => print 'r' if intel_mnemonic is false.
2396    'N' => print 'n' if instruction has no wait "prefix"
2397    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2398    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2399           or suffix_always is true.  print 'q' if rex prefix is present.
2400    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2401           is true
2402    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2403    'S' => print 'w', 'l' or 'q' if suffix_always is true
2404    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2405    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2406    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2407    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2408    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2409    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2410           suffix_always is true.
2411    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2412    '!' => change condition from true to false or from false to true.
2413    '%' => add 1 upper case letter to the macro.
2414
2415    2 upper case letter macros:
2416    "XY" => print 'x' or 'y' if no register operands or suffix_always
2417            is true.
2418    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2419    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2420            or suffix_always is true
2421    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2422    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2423    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2424    "LW" => print 'd', 'q' depending on the VEX.W bit
2425    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2426            an operand size prefix, or suffix_always is true.  print
2427            'q' if rex prefix is present.
2428
2429    Many of the above letters print nothing in Intel mode.  See "putop"
2430    for the details.
2431
2432    Braces '{' and '}', and vertical bars '|', indicate alternative
2433    mnemonic strings for AT&T and Intel.  */
2434
2435 static const struct dis386 dis386[] = {
2436   /* 00 */
2437   { "addB",             { Ebh1, Gb }, 0 },
2438   { "addS",             { Evh1, Gv }, 0 },
2439   { "addB",             { Gb, EbS }, 0 },
2440   { "addS",             { Gv, EvS }, 0 },
2441   { "addB",             { AL, Ib }, 0 },
2442   { "addS",             { eAX, Iv }, 0 },
2443   { X86_64_TABLE (X86_64_06) },
2444   { X86_64_TABLE (X86_64_07) },
2445   /* 08 */
2446   { "orB",              { Ebh1, Gb }, 0 },
2447   { "orS",              { Evh1, Gv }, 0 },
2448   { "orB",              { Gb, EbS }, 0 },
2449   { "orS",              { Gv, EvS }, 0 },
2450   { "orB",              { AL, Ib }, 0 },
2451   { "orS",              { eAX, Iv }, 0 },
2452   { X86_64_TABLE (X86_64_0D) },
2453   { Bad_Opcode },       /* 0x0f extended opcode escape */
2454   /* 10 */
2455   { "adcB",             { Ebh1, Gb }, 0 },
2456   { "adcS",             { Evh1, Gv }, 0 },
2457   { "adcB",             { Gb, EbS }, 0 },
2458   { "adcS",             { Gv, EvS }, 0 },
2459   { "adcB",             { AL, Ib }, 0 },
2460   { "adcS",             { eAX, Iv }, 0 },
2461   { X86_64_TABLE (X86_64_16) },
2462   { X86_64_TABLE (X86_64_17) },
2463   /* 18 */
2464   { "sbbB",             { Ebh1, Gb }, 0 },
2465   { "sbbS",             { Evh1, Gv }, 0 },
2466   { "sbbB",             { Gb, EbS }, 0 },
2467   { "sbbS",             { Gv, EvS }, 0 },
2468   { "sbbB",             { AL, Ib }, 0 },
2469   { "sbbS",             { eAX, Iv }, 0 },
2470   { X86_64_TABLE (X86_64_1E) },
2471   { X86_64_TABLE (X86_64_1F) },
2472   /* 20 */
2473   { "andB",             { Ebh1, Gb }, 0 },
2474   { "andS",             { Evh1, Gv }, 0 },
2475   { "andB",             { Gb, EbS }, 0 },
2476   { "andS",             { Gv, EvS }, 0 },
2477   { "andB",             { AL, Ib }, 0 },
2478   { "andS",             { eAX, Iv }, 0 },
2479   { Bad_Opcode },       /* SEG ES prefix */
2480   { X86_64_TABLE (X86_64_27) },
2481   /* 28 */
2482   { "subB",             { Ebh1, Gb }, 0 },
2483   { "subS",             { Evh1, Gv }, 0 },
2484   { "subB",             { Gb, EbS }, 0 },
2485   { "subS",             { Gv, EvS }, 0 },
2486   { "subB",             { AL, Ib }, 0 },
2487   { "subS",             { eAX, Iv }, 0 },
2488   { Bad_Opcode },       /* SEG CS prefix */
2489   { X86_64_TABLE (X86_64_2F) },
2490   /* 30 */
2491   { "xorB",             { Ebh1, Gb }, 0 },
2492   { "xorS",             { Evh1, Gv }, 0 },
2493   { "xorB",             { Gb, EbS }, 0 },
2494   { "xorS",             { Gv, EvS }, 0 },
2495   { "xorB",             { AL, Ib }, 0 },
2496   { "xorS",             { eAX, Iv }, 0 },
2497   { Bad_Opcode },       /* SEG SS prefix */
2498   { X86_64_TABLE (X86_64_37) },
2499   /* 38 */
2500   { "cmpB",             { Eb, Gb }, 0 },
2501   { "cmpS",             { Ev, Gv }, 0 },
2502   { "cmpB",             { Gb, EbS }, 0 },
2503   { "cmpS",             { Gv, EvS }, 0 },
2504   { "cmpB",             { AL, Ib }, 0 },
2505   { "cmpS",             { eAX, Iv }, 0 },
2506   { Bad_Opcode },       /* SEG DS prefix */
2507   { X86_64_TABLE (X86_64_3F) },
2508   /* 40 */
2509   { "inc{S|}",          { RMeAX }, 0 },
2510   { "inc{S|}",          { RMeCX }, 0 },
2511   { "inc{S|}",          { RMeDX }, 0 },
2512   { "inc{S|}",          { RMeBX }, 0 },
2513   { "inc{S|}",          { RMeSP }, 0 },
2514   { "inc{S|}",          { RMeBP }, 0 },
2515   { "inc{S|}",          { RMeSI }, 0 },
2516   { "inc{S|}",          { RMeDI }, 0 },
2517   /* 48 */
2518   { "dec{S|}",          { RMeAX }, 0 },
2519   { "dec{S|}",          { RMeCX }, 0 },
2520   { "dec{S|}",          { RMeDX }, 0 },
2521   { "dec{S|}",          { RMeBX }, 0 },
2522   { "dec{S|}",          { RMeSP }, 0 },
2523   { "dec{S|}",          { RMeBP }, 0 },
2524   { "dec{S|}",          { RMeSI }, 0 },
2525   { "dec{S|}",          { RMeDI }, 0 },
2526   /* 50 */
2527   { "pushV",            { RMrAX }, 0 },
2528   { "pushV",            { RMrCX }, 0 },
2529   { "pushV",            { RMrDX }, 0 },
2530   { "pushV",            { RMrBX }, 0 },
2531   { "pushV",            { RMrSP }, 0 },
2532   { "pushV",            { RMrBP }, 0 },
2533   { "pushV",            { RMrSI }, 0 },
2534   { "pushV",            { RMrDI }, 0 },
2535   /* 58 */
2536   { "popV",             { RMrAX }, 0 },
2537   { "popV",             { RMrCX }, 0 },
2538   { "popV",             { RMrDX }, 0 },
2539   { "popV",             { RMrBX }, 0 },
2540   { "popV",             { RMrSP }, 0 },
2541   { "popV",             { RMrBP }, 0 },
2542   { "popV",             { RMrSI }, 0 },
2543   { "popV",             { RMrDI }, 0 },
2544   /* 60 */
2545   { X86_64_TABLE (X86_64_60) },
2546   { X86_64_TABLE (X86_64_61) },
2547   { X86_64_TABLE (X86_64_62) },
2548   { X86_64_TABLE (X86_64_63) },
2549   { Bad_Opcode },       /* seg fs */
2550   { Bad_Opcode },       /* seg gs */
2551   { Bad_Opcode },       /* op size prefix */
2552   { Bad_Opcode },       /* adr size prefix */
2553   /* 68 */
2554   { "pushT",            { sIv }, 0 },
2555   { "imulS",            { Gv, Ev, Iv }, 0 },
2556   { "pushT",            { sIbT }, 0 },
2557   { "imulS",            { Gv, Ev, sIb }, 0 },
2558   { "ins{b|}",          { Ybr, indirDX }, 0 },
2559   { X86_64_TABLE (X86_64_6D) },
2560   { "outs{b|}",         { indirDXr, Xb }, 0 },
2561   { X86_64_TABLE (X86_64_6F) },
2562   /* 70 */
2563   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2564   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2565   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2566   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2567   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2568   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2569   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2570   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2571   /* 78 */
2572   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2573   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2574   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2575   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2576   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2577   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2578   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2579   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2580   /* 80 */
2581   { REG_TABLE (REG_80) },
2582   { REG_TABLE (REG_81) },
2583   { Bad_Opcode },
2584   { REG_TABLE (REG_82) },
2585   { "testB",            { Eb, Gb }, 0 },
2586   { "testS",            { Ev, Gv }, 0 },
2587   { "xchgB",            { Ebh2, Gb }, 0 },
2588   { "xchgS",            { Evh2, Gv }, 0 },
2589   /* 88 */
2590   { "movB",             { Ebh3, Gb }, 0 },
2591   { "movS",             { Evh3, Gv }, 0 },
2592   { "movB",             { Gb, EbS }, 0 },
2593   { "movS",             { Gv, EvS }, 0 },
2594   { "movD",             { Sv, Sw }, 0 },
2595   { MOD_TABLE (MOD_8D) },
2596   { "movD",             { Sw, Sv }, 0 },
2597   { REG_TABLE (REG_8F) },
2598   /* 90 */
2599   { PREFIX_TABLE (PREFIX_90) },
2600   { "xchgS",            { RMeCX, eAX }, 0 },
2601   { "xchgS",            { RMeDX, eAX }, 0 },
2602   { "xchgS",            { RMeBX, eAX }, 0 },
2603   { "xchgS",            { RMeSP, eAX }, 0 },
2604   { "xchgS",            { RMeBP, eAX }, 0 },
2605   { "xchgS",            { RMeSI, eAX }, 0 },
2606   { "xchgS",            { RMeDI, eAX }, 0 },
2607   /* 98 */
2608   { "cW{t|}R",          { XX }, 0 },
2609   { "cR{t|}O",          { XX }, 0 },
2610   { X86_64_TABLE (X86_64_9A) },
2611   { Bad_Opcode },       /* fwait */
2612   { "pushfT",           { XX }, 0 },
2613   { "popfT",            { XX }, 0 },
2614   { "sahf",             { XX }, 0 },
2615   { "lahf",             { XX }, 0 },
2616   /* a0 */
2617   { "mov%LB",           { AL, Ob }, 0 },
2618   { "mov%LS",           { eAX, Ov }, 0 },
2619   { "mov%LB",           { Ob, AL }, 0 },
2620   { "mov%LS",           { Ov, eAX }, 0 },
2621   { "movs{b|}",         { Ybr, Xb }, 0 },
2622   { "movs{R|}",         { Yvr, Xv }, 0 },
2623   { "cmps{b|}",         { Xb, Yb }, 0 },
2624   { "cmps{R|}",         { Xv, Yv }, 0 },
2625   /* a8 */
2626   { "testB",            { AL, Ib }, 0 },
2627   { "testS",            { eAX, Iv }, 0 },
2628   { "stosB",            { Ybr, AL }, 0 },
2629   { "stosS",            { Yvr, eAX }, 0 },
2630   { "lodsB",            { ALr, Xb }, 0 },
2631   { "lodsS",            { eAXr, Xv }, 0 },
2632   { "scasB",            { AL, Yb }, 0 },
2633   { "scasS",            { eAX, Yv }, 0 },
2634   /* b0 */
2635   { "movB",             { RMAL, Ib }, 0 },
2636   { "movB",             { RMCL, Ib }, 0 },
2637   { "movB",             { RMDL, Ib }, 0 },
2638   { "movB",             { RMBL, Ib }, 0 },
2639   { "movB",             { RMAH, Ib }, 0 },
2640   { "movB",             { RMCH, Ib }, 0 },
2641   { "movB",             { RMDH, Ib }, 0 },
2642   { "movB",             { RMBH, Ib }, 0 },
2643   /* b8 */
2644   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2645   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2646   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2647   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2648   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2649   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2650   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2651   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2652   /* c0 */
2653   { REG_TABLE (REG_C0) },
2654   { REG_TABLE (REG_C1) },
2655   { "retT",             { Iw, BND }, 0 },
2656   { "retT",             { BND }, 0 },
2657   { X86_64_TABLE (X86_64_C4) },
2658   { X86_64_TABLE (X86_64_C5) },
2659   { REG_TABLE (REG_C6) },
2660   { REG_TABLE (REG_C7) },
2661   /* c8 */
2662   { "enterT",           { Iw, Ib }, 0 },
2663   { "leaveT",           { XX }, 0 },
2664   { "Jret{|f}P",        { Iw }, 0 },
2665   { "Jret{|f}P",        { XX }, 0 },
2666   { "int3",             { XX }, 0 },
2667   { "int",              { Ib }, 0 },
2668   { X86_64_TABLE (X86_64_CE) },
2669   { "iret%LP",          { XX }, 0 },
2670   /* d0 */
2671   { REG_TABLE (REG_D0) },
2672   { REG_TABLE (REG_D1) },
2673   { REG_TABLE (REG_D2) },
2674   { REG_TABLE (REG_D3) },
2675   { X86_64_TABLE (X86_64_D4) },
2676   { X86_64_TABLE (X86_64_D5) },
2677   { Bad_Opcode },
2678   { "xlat",             { DSBX }, 0 },
2679   /* d8 */
2680   { FLOAT },
2681   { FLOAT },
2682   { FLOAT },
2683   { FLOAT },
2684   { FLOAT },
2685   { FLOAT },
2686   { FLOAT },
2687   { FLOAT },
2688   /* e0 */
2689   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2690   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2691   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2692   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2693   { "inB",              { AL, Ib }, 0 },
2694   { "inG",              { zAX, Ib }, 0 },
2695   { "outB",             { Ib, AL }, 0 },
2696   { "outG",             { Ib, zAX }, 0 },
2697   /* e8 */
2698   { "callT",            { Jv, BND }, 0 },
2699   { "jmpT",             { Jv, BND }, 0 },
2700   { X86_64_TABLE (X86_64_EA) },
2701   { "jmp",              { Jb, BND }, 0 },
2702   { "inB",              { AL, indirDX }, 0 },
2703   { "inG",              { zAX, indirDX }, 0 },
2704   { "outB",             { indirDX, AL }, 0 },
2705   { "outG",             { indirDX, zAX }, 0 },
2706   /* f0 */
2707   { Bad_Opcode },       /* lock prefix */
2708   { "icebp",            { XX }, 0 },
2709   { Bad_Opcode },       /* repne */
2710   { Bad_Opcode },       /* repz */
2711   { "hlt",              { XX }, 0 },
2712   { "cmc",              { XX }, 0 },
2713   { REG_TABLE (REG_F6) },
2714   { REG_TABLE (REG_F7) },
2715   /* f8 */
2716   { "clc",              { XX }, 0 },
2717   { "stc",              { XX }, 0 },
2718   { "cli",              { XX }, 0 },
2719   { "sti",              { XX }, 0 },
2720   { "cld",              { XX }, 0 },
2721   { "std",              { XX }, 0 },
2722   { REG_TABLE (REG_FE) },
2723   { REG_TABLE (REG_FF) },
2724 };
2725
2726 static const struct dis386 dis386_twobyte[] = {
2727   /* 00 */
2728   { REG_TABLE (REG_0F00 ) },
2729   { REG_TABLE (REG_0F01 ) },
2730   { "larS",             { Gv, Ew }, 0 },
2731   { "lslS",             { Gv, Ew }, 0 },
2732   { Bad_Opcode },
2733   { "syscall",          { XX }, 0 },
2734   { "clts",             { XX }, 0 },
2735   { "sysret%LP",                { XX }, 0 },
2736   /* 08 */
2737   { "invd",             { XX }, 0 },
2738   { "wbinvd",           { XX }, 0 },
2739   { Bad_Opcode },
2740   { "ud2",              { XX }, 0 },
2741   { Bad_Opcode },
2742   { REG_TABLE (REG_0F0D) },
2743   { "femms",            { XX }, 0 },
2744   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2745   /* 10 */
2746   { PREFIX_TABLE (PREFIX_0F10) },
2747   { PREFIX_TABLE (PREFIX_0F11) },
2748   { PREFIX_TABLE (PREFIX_0F12) },
2749   { MOD_TABLE (MOD_0F13) },
2750   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2751   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2752   { PREFIX_TABLE (PREFIX_0F16) },
2753   { MOD_TABLE (MOD_0F17) },
2754   /* 18 */
2755   { REG_TABLE (REG_0F18) },
2756   { "nopQ",             { Ev }, 0 },
2757   { PREFIX_TABLE (PREFIX_0F1A) },
2758   { PREFIX_TABLE (PREFIX_0F1B) },
2759   { "nopQ",             { Ev }, 0 },
2760   { "nopQ",             { Ev }, 0 },
2761   { "nopQ",             { Ev }, 0 },
2762   { "nopQ",             { Ev }, 0 },
2763   /* 20 */
2764   { "movZ",             { Rm, Cm }, 0 },
2765   { "movZ",             { Rm, Dm }, 0 },
2766   { "movZ",             { Cm, Rm }, 0 },
2767   { "movZ",             { Dm, Rm }, 0 },
2768   { MOD_TABLE (MOD_0F24) },
2769   { Bad_Opcode },
2770   { MOD_TABLE (MOD_0F26) },
2771   { Bad_Opcode },
2772   /* 28 */
2773   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2774   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2775   { PREFIX_TABLE (PREFIX_0F2A) },
2776   { PREFIX_TABLE (PREFIX_0F2B) },
2777   { PREFIX_TABLE (PREFIX_0F2C) },
2778   { PREFIX_TABLE (PREFIX_0F2D) },
2779   { PREFIX_TABLE (PREFIX_0F2E) },
2780   { PREFIX_TABLE (PREFIX_0F2F) },
2781   /* 30 */
2782   { "wrmsr",            { XX }, 0 },
2783   { "rdtsc",            { XX }, 0 },
2784   { "rdmsr",            { XX }, 0 },
2785   { "rdpmc",            { XX }, 0 },
2786   { "sysenter",         { XX }, 0 },
2787   { "sysexit",          { XX }, 0 },
2788   { Bad_Opcode },
2789   { "getsec",           { XX }, 0 },
2790   /* 38 */
2791   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2792   { Bad_Opcode },
2793   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2794   { Bad_Opcode },
2795   { Bad_Opcode },
2796   { Bad_Opcode },
2797   { Bad_Opcode },
2798   { Bad_Opcode },
2799   /* 40 */
2800   { "cmovoS",           { Gv, Ev }, 0 },
2801   { "cmovnoS",          { Gv, Ev }, 0 },
2802   { "cmovbS",           { Gv, Ev }, 0 },
2803   { "cmovaeS",          { Gv, Ev }, 0 },
2804   { "cmoveS",           { Gv, Ev }, 0 },
2805   { "cmovneS",          { Gv, Ev }, 0 },
2806   { "cmovbeS",          { Gv, Ev }, 0 },
2807   { "cmovaS",           { Gv, Ev }, 0 },
2808   /* 48 */
2809   { "cmovsS",           { Gv, Ev }, 0 },
2810   { "cmovnsS",          { Gv, Ev }, 0 },
2811   { "cmovpS",           { Gv, Ev }, 0 },
2812   { "cmovnpS",          { Gv, Ev }, 0 },
2813   { "cmovlS",           { Gv, Ev }, 0 },
2814   { "cmovgeS",          { Gv, Ev }, 0 },
2815   { "cmovleS",          { Gv, Ev }, 0 },
2816   { "cmovgS",           { Gv, Ev }, 0 },
2817   /* 50 */
2818   { MOD_TABLE (MOD_0F51) },
2819   { PREFIX_TABLE (PREFIX_0F51) },
2820   { PREFIX_TABLE (PREFIX_0F52) },
2821   { PREFIX_TABLE (PREFIX_0F53) },
2822   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2823   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2824   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2825   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2826   /* 58 */
2827   { PREFIX_TABLE (PREFIX_0F58) },
2828   { PREFIX_TABLE (PREFIX_0F59) },
2829   { PREFIX_TABLE (PREFIX_0F5A) },
2830   { PREFIX_TABLE (PREFIX_0F5B) },
2831   { PREFIX_TABLE (PREFIX_0F5C) },
2832   { PREFIX_TABLE (PREFIX_0F5D) },
2833   { PREFIX_TABLE (PREFIX_0F5E) },
2834   { PREFIX_TABLE (PREFIX_0F5F) },
2835   /* 60 */
2836   { PREFIX_TABLE (PREFIX_0F60) },
2837   { PREFIX_TABLE (PREFIX_0F61) },
2838   { PREFIX_TABLE (PREFIX_0F62) },
2839   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2840   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2841   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2842   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2843   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2844   /* 68 */
2845   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2846   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2847   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2848   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2849   { PREFIX_TABLE (PREFIX_0F6C) },
2850   { PREFIX_TABLE (PREFIX_0F6D) },
2851   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2852   { PREFIX_TABLE (PREFIX_0F6F) },
2853   /* 70 */
2854   { PREFIX_TABLE (PREFIX_0F70) },
2855   { REG_TABLE (REG_0F71) },
2856   { REG_TABLE (REG_0F72) },
2857   { REG_TABLE (REG_0F73) },
2858   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2859   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2860   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2861   { "emms",             { XX }, PREFIX_OPCODE },
2862   /* 78 */
2863   { PREFIX_TABLE (PREFIX_0F78) },
2864   { PREFIX_TABLE (PREFIX_0F79) },
2865   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2866   { Bad_Opcode },
2867   { PREFIX_TABLE (PREFIX_0F7C) },
2868   { PREFIX_TABLE (PREFIX_0F7D) },
2869   { PREFIX_TABLE (PREFIX_0F7E) },
2870   { PREFIX_TABLE (PREFIX_0F7F) },
2871   /* 80 */
2872   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2873   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2874   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2875   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2876   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2877   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2878   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2879   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2880   /* 88 */
2881   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2882   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2883   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2884   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2885   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2886   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2887   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2888   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2889   /* 90 */
2890   { "seto",             { Eb }, 0 },
2891   { "setno",            { Eb }, 0 },
2892   { "setb",             { Eb }, 0 },
2893   { "setae",            { Eb }, 0 },
2894   { "sete",             { Eb }, 0 },
2895   { "setne",            { Eb }, 0 },
2896   { "setbe",            { Eb }, 0 },
2897   { "seta",             { Eb }, 0 },
2898   /* 98 */
2899   { "sets",             { Eb }, 0 },
2900   { "setns",            { Eb }, 0 },
2901   { "setp",             { Eb }, 0 },
2902   { "setnp",            { Eb }, 0 },
2903   { "setl",             { Eb }, 0 },
2904   { "setge",            { Eb }, 0 },
2905   { "setle",            { Eb }, 0 },
2906   { "setg",             { Eb }, 0 },
2907   /* a0 */
2908   { "pushT",            { fs }, 0 },
2909   { "popT",             { fs }, 0 },
2910   { "cpuid",            { XX }, 0 },
2911   { "btS",              { Ev, Gv }, 0 },
2912   { "shldS",            { Ev, Gv, Ib }, 0 },
2913   { "shldS",            { Ev, Gv, CL }, 0 },
2914   { REG_TABLE (REG_0FA6) },
2915   { REG_TABLE (REG_0FA7) },
2916   /* a8 */
2917   { "pushT",            { gs }, 0 },
2918   { "popT",             { gs }, 0 },
2919   { "rsm",              { XX }, 0 },
2920   { "btsS",             { Evh1, Gv }, 0 },
2921   { "shrdS",            { Ev, Gv, Ib }, 0 },
2922   { "shrdS",            { Ev, Gv, CL }, 0 },
2923   { REG_TABLE (REG_0FAE) },
2924   { "imulS",            { Gv, Ev }, 0 },
2925   /* b0 */
2926   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2927   { "cmpxchgS",         { Evh1, Gv }, 0 },
2928   { MOD_TABLE (MOD_0FB2) },
2929   { "btrS",             { Evh1, Gv }, 0 },
2930   { MOD_TABLE (MOD_0FB4) },
2931   { MOD_TABLE (MOD_0FB5) },
2932   { "movz{bR|x}",       { Gv, Eb }, 0 },
2933   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2934   /* b8 */
2935   { PREFIX_TABLE (PREFIX_0FB8) },
2936   { "ud1",              { XX }, 0 },
2937   { REG_TABLE (REG_0FBA) },
2938   { "btcS",             { Evh1, Gv }, 0 },
2939   { PREFIX_TABLE (PREFIX_0FBC) },
2940   { PREFIX_TABLE (PREFIX_0FBD) },
2941   { "movs{bR|x}",       { Gv, Eb }, 0 },
2942   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2943   /* c0 */
2944   { "xaddB",            { Ebh1, Gb }, 0 },
2945   { "xaddS",            { Evh1, Gv }, 0 },
2946   { PREFIX_TABLE (PREFIX_0FC2) },
2947   { PREFIX_TABLE (PREFIX_0FC3) },
2948   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2949   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2950   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2951   { REG_TABLE (REG_0FC7) },
2952   /* c8 */
2953   { "bswap",            { RMeAX }, 0 },
2954   { "bswap",            { RMeCX }, 0 },
2955   { "bswap",            { RMeDX }, 0 },
2956   { "bswap",            { RMeBX }, 0 },
2957   { "bswap",            { RMeSP }, 0 },
2958   { "bswap",            { RMeBP }, 0 },
2959   { "bswap",            { RMeSI }, 0 },
2960   { "bswap",            { RMeDI }, 0 },
2961   /* d0 */
2962   { PREFIX_TABLE (PREFIX_0FD0) },
2963   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2964   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2965   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2966   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2967   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2968   { PREFIX_TABLE (PREFIX_0FD6) },
2969   { MOD_TABLE (MOD_0FD7) },
2970   /* d8 */
2971   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2972   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2973   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2974   { "pand",             { MX, EM }, PREFIX_OPCODE },
2975   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2976   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2977   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2978   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2979   /* e0 */
2980   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2981   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2982   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2983   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2984   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2985   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2986   { PREFIX_TABLE (PREFIX_0FE6) },
2987   { PREFIX_TABLE (PREFIX_0FE7) },
2988   /* e8 */
2989   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2990   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2991   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2992   { "por",              { MX, EM }, PREFIX_OPCODE },
2993   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2994   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2995   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2996   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2997   /* f0 */
2998   { PREFIX_TABLE (PREFIX_0FF0) },
2999   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3000   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3001   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3002   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3003   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3004   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3005   { PREFIX_TABLE (PREFIX_0FF7) },
3006   /* f8 */
3007   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3008   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3009   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3010   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3011   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3012   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3013   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3014   { Bad_Opcode },
3015 };
3016
3017 static const unsigned char onebyte_has_modrm[256] = {
3018   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3019   /*       -------------------------------        */
3020   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3021   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3022   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3023   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3024   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3025   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3026   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3027   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3028   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3029   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3030   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3031   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3032   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3033   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3034   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3035   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3036   /*       -------------------------------        */
3037   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3038 };
3039
3040 static const unsigned char twobyte_has_modrm[256] = {
3041   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3042   /*       -------------------------------        */
3043   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3044   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3045   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3046   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3047   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3048   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3049   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3050   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3051   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3052   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3053   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3054   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3055   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3056   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3057   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3058   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3059   /*       -------------------------------        */
3060   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3061 };
3062
3063 static char obuf[100];
3064 static char *obufp;
3065 static char *mnemonicendp;
3066 static char scratchbuf[100];
3067 static unsigned char *start_codep;
3068 static unsigned char *insn_codep;
3069 static unsigned char *codep;
3070 static unsigned char *end_codep;
3071 static int last_lock_prefix;
3072 static int last_repz_prefix;
3073 static int last_repnz_prefix;
3074 static int last_data_prefix;
3075 static int last_addr_prefix;
3076 static int last_rex_prefix;
3077 static int last_seg_prefix;
3078 static int fwait_prefix;
3079 /* The active segment register prefix.  */
3080 static int active_seg_prefix;
3081 #define MAX_CODE_LENGTH 15
3082 /* We can up to 14 prefixes since the maximum instruction length is
3083    15bytes.  */
3084 static int all_prefixes[MAX_CODE_LENGTH - 1];
3085 static disassemble_info *the_info;
3086 static struct
3087   {
3088     int mod;
3089     int reg;
3090     int rm;
3091   }
3092 modrm;
3093 static unsigned char need_modrm;
3094 static struct
3095   {
3096     int scale;
3097     int index;
3098     int base;
3099   }
3100 sib;
3101 static struct
3102   {
3103     int register_specifier;
3104     int length;
3105     int prefix;
3106     int w;
3107     int evex;
3108     int r;
3109     int v;
3110     int mask_register_specifier;
3111     int zeroing;
3112     int ll;
3113     int b;
3114   }
3115 vex;
3116 static unsigned char need_vex;
3117 static unsigned char need_vex_reg;
3118 static unsigned char vex_w_done;
3119
3120 struct op
3121   {
3122     const char *name;
3123     unsigned int len;
3124   };
3125
3126 /* If we are accessing mod/rm/reg without need_modrm set, then the
3127    values are stale.  Hitting this abort likely indicates that you
3128    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3129 #define MODRM_CHECK  if (!need_modrm) abort ()
3130
3131 static const char **names64;
3132 static const char **names32;
3133 static const char **names16;
3134 static const char **names8;
3135 static const char **names8rex;
3136 static const char **names_seg;
3137 static const char *index64;
3138 static const char *index32;
3139 static const char **index16;
3140 static const char **names_bnd;
3141
3142 static const char *intel_names64[] = {
3143   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3144   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3145 };
3146 static const char *intel_names32[] = {
3147   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3148   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3149 };
3150 static const char *intel_names16[] = {
3151   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3152   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3153 };
3154 static const char *intel_names8[] = {
3155   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3156 };
3157 static const char *intel_names8rex[] = {
3158   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3159   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3160 };
3161 static const char *intel_names_seg[] = {
3162   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3163 };
3164 static const char *intel_index64 = "riz";
3165 static const char *intel_index32 = "eiz";
3166 static const char *intel_index16[] = {
3167   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3168 };
3169
3170 static const char *att_names64[] = {
3171   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3172   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3173 };
3174 static const char *att_names32[] = {
3175   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3176   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3177 };
3178 static const char *att_names16[] = {
3179   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3180   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3181 };
3182 static const char *att_names8[] = {
3183   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3184 };
3185 static const char *att_names8rex[] = {
3186   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3187   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3188 };
3189 static const char *att_names_seg[] = {
3190   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3191 };
3192 static const char *att_index64 = "%riz";
3193 static const char *att_index32 = "%eiz";
3194 static const char *att_index16[] = {
3195   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3196 };
3197
3198 static const char **names_mm;
3199 static const char *intel_names_mm[] = {
3200   "mm0", "mm1", "mm2", "mm3",
3201   "mm4", "mm5", "mm6", "mm7"
3202 };
3203 static const char *att_names_mm[] = {
3204   "%mm0", "%mm1", "%mm2", "%mm3",
3205   "%mm4", "%mm5", "%mm6", "%mm7"
3206 };
3207
3208 static const char *intel_names_bnd[] = {
3209   "bnd0", "bnd1", "bnd2", "bnd3"
3210 };
3211
3212 static const char *att_names_bnd[] = {
3213   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3214 };
3215
3216 static const char **names_xmm;
3217 static const char *intel_names_xmm[] = {
3218   "xmm0", "xmm1", "xmm2", "xmm3",
3219   "xmm4", "xmm5", "xmm6", "xmm7",
3220   "xmm8", "xmm9", "xmm10", "xmm11",
3221   "xmm12", "xmm13", "xmm14", "xmm15",
3222   "xmm16", "xmm17", "xmm18", "xmm19",
3223   "xmm20", "xmm21", "xmm22", "xmm23",
3224   "xmm24", "xmm25", "xmm26", "xmm27",
3225   "xmm28", "xmm29", "xmm30", "xmm31"
3226 };
3227 static const char *att_names_xmm[] = {
3228   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3229   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3230   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3231   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3232   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3233   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3234   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3235   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3236 };
3237
3238 static const char **names_ymm;
3239 static const char *intel_names_ymm[] = {
3240   "ymm0", "ymm1", "ymm2", "ymm3",
3241   "ymm4", "ymm5", "ymm6", "ymm7",
3242   "ymm8", "ymm9", "ymm10", "ymm11",
3243   "ymm12", "ymm13", "ymm14", "ymm15",
3244   "ymm16", "ymm17", "ymm18", "ymm19",
3245   "ymm20", "ymm21", "ymm22", "ymm23",
3246   "ymm24", "ymm25", "ymm26", "ymm27",
3247   "ymm28", "ymm29", "ymm30", "ymm31"
3248 };
3249 static const char *att_names_ymm[] = {
3250   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3251   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3252   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3253   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3254   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3255   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3256   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3257   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3258 };
3259
3260 static const char **names_zmm;
3261 static const char *intel_names_zmm[] = {
3262   "zmm0", "zmm1", "zmm2", "zmm3",
3263   "zmm4", "zmm5", "zmm6", "zmm7",
3264   "zmm8", "zmm9", "zmm10", "zmm11",
3265   "zmm12", "zmm13", "zmm14", "zmm15",
3266   "zmm16", "zmm17", "zmm18", "zmm19",
3267   "zmm20", "zmm21", "zmm22", "zmm23",
3268   "zmm24", "zmm25", "zmm26", "zmm27",
3269   "zmm28", "zmm29", "zmm30", "zmm31"
3270 };
3271 static const char *att_names_zmm[] = {
3272   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3273   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3274   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3275   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3276   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3277   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3278   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3279   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3280 };
3281
3282 static const char **names_mask;
3283 static const char *intel_names_mask[] = {
3284   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3285 };
3286 static const char *att_names_mask[] = {
3287   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3288 };
3289
3290 static const char *names_rounding[] =
3291 {
3292   "{rn-sae}",
3293   "{rd-sae}",
3294   "{ru-sae}",
3295   "{rz-sae}"
3296 };
3297
3298 static const struct dis386 reg_table[][8] = {
3299   /* REG_80 */
3300   {
3301     { "addA",   { Ebh1, Ib }, 0 },
3302     { "orA",    { Ebh1, Ib }, 0 },
3303     { "adcA",   { Ebh1, Ib }, 0 },
3304     { "sbbA",   { Ebh1, Ib }, 0 },
3305     { "andA",   { Ebh1, Ib }, 0 },
3306     { "subA",   { Ebh1, Ib }, 0 },
3307     { "xorA",   { Ebh1, Ib }, 0 },
3308     { "cmpA",   { Eb, Ib }, 0 },
3309   },
3310   /* REG_81 */
3311   {
3312     { "addQ",   { Evh1, Iv }, 0 },
3313     { "orQ",    { Evh1, Iv }, 0 },
3314     { "adcQ",   { Evh1, Iv }, 0 },
3315     { "sbbQ",   { Evh1, Iv }, 0 },
3316     { "andQ",   { Evh1, Iv }, 0 },
3317     { "subQ",   { Evh1, Iv }, 0 },
3318     { "xorQ",   { Evh1, Iv }, 0 },
3319     { "cmpQ",   { Ev, Iv }, 0 },
3320   },
3321   /* REG_82 */
3322   {
3323     { "addQ",   { Evh1, sIb }, 0 },
3324     { "orQ",    { Evh1, sIb }, 0 },
3325     { "adcQ",   { Evh1, sIb }, 0 },
3326     { "sbbQ",   { Evh1, sIb }, 0 },
3327     { "andQ",   { Evh1, sIb }, 0 },
3328     { "subQ",   { Evh1, sIb }, 0 },
3329     { "xorQ",   { Evh1, sIb }, 0 },
3330     { "cmpQ",   { Ev, sIb }, 0 },
3331   },
3332   /* REG_8F */
3333   {
3334     { "popU",   { stackEv }, 0 },
3335     { XOP_8F_TABLE (XOP_09) },
3336     { Bad_Opcode },
3337     { Bad_Opcode },
3338     { Bad_Opcode },
3339     { XOP_8F_TABLE (XOP_09) },
3340   },
3341   /* REG_C0 */
3342   {
3343     { "rolA",   { Eb, Ib }, 0 },
3344     { "rorA",   { Eb, Ib }, 0 },
3345     { "rclA",   { Eb, Ib }, 0 },
3346     { "rcrA",   { Eb, Ib }, 0 },
3347     { "shlA",   { Eb, Ib }, 0 },
3348     { "shrA",   { Eb, Ib }, 0 },
3349     { Bad_Opcode },
3350     { "sarA",   { Eb, Ib }, 0 },
3351   },
3352   /* REG_C1 */
3353   {
3354     { "rolQ",   { Ev, Ib }, 0 },
3355     { "rorQ",   { Ev, Ib }, 0 },
3356     { "rclQ",   { Ev, Ib }, 0 },
3357     { "rcrQ",   { Ev, Ib }, 0 },
3358     { "shlQ",   { Ev, Ib }, 0 },
3359     { "shrQ",   { Ev, Ib }, 0 },
3360     { Bad_Opcode },
3361     { "sarQ",   { Ev, Ib }, 0 },
3362   },
3363   /* REG_C6 */
3364   {
3365     { "movA",   { Ebh3, Ib }, 0 },
3366     { Bad_Opcode },
3367     { Bad_Opcode },
3368     { Bad_Opcode },
3369     { Bad_Opcode },
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { MOD_TABLE (MOD_C6_REG_7) },
3373   },
3374   /* REG_C7 */
3375   {
3376     { "movQ",   { Evh3, Iv }, 0 },
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { Bad_Opcode },
3380     { Bad_Opcode },
3381     { Bad_Opcode },
3382     { Bad_Opcode },
3383     { MOD_TABLE (MOD_C7_REG_7) },
3384   },
3385   /* REG_D0 */
3386   {
3387     { "rolA",   { Eb, I1 }, 0 },
3388     { "rorA",   { Eb, I1 }, 0 },
3389     { "rclA",   { Eb, I1 }, 0 },
3390     { "rcrA",   { Eb, I1 }, 0 },
3391     { "shlA",   { Eb, I1 }, 0 },
3392     { "shrA",   { Eb, I1 }, 0 },
3393     { Bad_Opcode },
3394     { "sarA",   { Eb, I1 }, 0 },
3395   },
3396   /* REG_D1 */
3397   {
3398     { "rolQ",   { Ev, I1 }, 0 },
3399     { "rorQ",   { Ev, I1 }, 0 },
3400     { "rclQ",   { Ev, I1 }, 0 },
3401     { "rcrQ",   { Ev, I1 }, 0 },
3402     { "shlQ",   { Ev, I1 }, 0 },
3403     { "shrQ",   { Ev, I1 }, 0 },
3404     { Bad_Opcode },
3405     { "sarQ",   { Ev, I1 }, 0 },
3406   },
3407   /* REG_D2 */
3408   {
3409     { "rolA",   { Eb, CL }, 0 },
3410     { "rorA",   { Eb, CL }, 0 },
3411     { "rclA",   { Eb, CL }, 0 },
3412     { "rcrA",   { Eb, CL }, 0 },
3413     { "shlA",   { Eb, CL }, 0 },
3414     { "shrA",   { Eb, CL }, 0 },
3415     { Bad_Opcode },
3416     { "sarA",   { Eb, CL }, 0 },
3417   },
3418   /* REG_D3 */
3419   {
3420     { "rolQ",   { Ev, CL }, 0 },
3421     { "rorQ",   { Ev, CL }, 0 },
3422     { "rclQ",   { Ev, CL }, 0 },
3423     { "rcrQ",   { Ev, CL }, 0 },
3424     { "shlQ",   { Ev, CL }, 0 },
3425     { "shrQ",   { Ev, CL }, 0 },
3426     { Bad_Opcode },
3427     { "sarQ",   { Ev, CL }, 0 },
3428   },
3429   /* REG_F6 */
3430   {
3431     { "testA",  { Eb, Ib }, 0 },
3432     { Bad_Opcode },
3433     { "notA",   { Ebh1 }, 0 },
3434     { "negA",   { Ebh1 }, 0 },
3435     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3436     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3437     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3438     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3439   },
3440   /* REG_F7 */
3441   {
3442     { "testQ",  { Ev, Iv }, 0 },
3443     { Bad_Opcode },
3444     { "notQ",   { Evh1 }, 0 },
3445     { "negQ",   { Evh1 }, 0 },
3446     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3447     { "imulQ",  { Ev }, 0 },
3448     { "divQ",   { Ev }, 0 },
3449     { "idivQ",  { Ev }, 0 },
3450   },
3451   /* REG_FE */
3452   {
3453     { "incA",   { Ebh1 }, 0 },
3454     { "decA",   { Ebh1 }, 0 },
3455   },
3456   /* REG_FF */
3457   {
3458     { "incQ",   { Evh1 }, 0 },
3459     { "decQ",   { Evh1 }, 0 },
3460     { "call{T|}", { indirEv, BND }, 0 },
3461     { MOD_TABLE (MOD_FF_REG_3) },
3462     { "jmp{T|}", { indirEv, BND }, 0 },
3463     { MOD_TABLE (MOD_FF_REG_5) },
3464     { "pushU",  { stackEv }, 0 },
3465     { Bad_Opcode },
3466   },
3467   /* REG_0F00 */
3468   {
3469     { "sldtD",  { Sv }, 0 },
3470     { "strD",   { Sv }, 0 },
3471     { "lldt",   { Ew }, 0 },
3472     { "ltr",    { Ew }, 0 },
3473     { "verr",   { Ew }, 0 },
3474     { "verw",   { Ew }, 0 },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477   },
3478   /* REG_0F01 */
3479   {
3480     { MOD_TABLE (MOD_0F01_REG_0) },
3481     { MOD_TABLE (MOD_0F01_REG_1) },
3482     { MOD_TABLE (MOD_0F01_REG_2) },
3483     { MOD_TABLE (MOD_0F01_REG_3) },
3484     { "smswD",  { Sv }, 0 },
3485     { Bad_Opcode },
3486     { "lmsw",   { Ew }, 0 },
3487     { MOD_TABLE (MOD_0F01_REG_7) },
3488   },
3489   /* REG_0F0D */
3490   {
3491     { "prefetch",       { Mb }, 0 },
3492     { "prefetchw",      { Mb }, 0 },
3493     { "prefetchwt1",    { Mb }, 0 },
3494     { "prefetch",       { Mb }, 0 },
3495     { "prefetch",       { Mb }, 0 },
3496     { "prefetch",       { Mb }, 0 },
3497     { "prefetch",       { Mb }, 0 },
3498     { "prefetch",       { Mb }, 0 },
3499   },
3500   /* REG_0F18 */
3501   {
3502     { MOD_TABLE (MOD_0F18_REG_0) },
3503     { MOD_TABLE (MOD_0F18_REG_1) },
3504     { MOD_TABLE (MOD_0F18_REG_2) },
3505     { MOD_TABLE (MOD_0F18_REG_3) },
3506     { MOD_TABLE (MOD_0F18_REG_4) },
3507     { MOD_TABLE (MOD_0F18_REG_5) },
3508     { MOD_TABLE (MOD_0F18_REG_6) },
3509     { MOD_TABLE (MOD_0F18_REG_7) },
3510   },
3511   /* REG_0F71 */
3512   {
3513     { Bad_Opcode },
3514     { Bad_Opcode },
3515     { MOD_TABLE (MOD_0F71_REG_2) },
3516     { Bad_Opcode },
3517     { MOD_TABLE (MOD_0F71_REG_4) },
3518     { Bad_Opcode },
3519     { MOD_TABLE (MOD_0F71_REG_6) },
3520   },
3521   /* REG_0F72 */
3522   {
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_0F72_REG_2) },
3526     { Bad_Opcode },
3527     { MOD_TABLE (MOD_0F72_REG_4) },
3528     { Bad_Opcode },
3529     { MOD_TABLE (MOD_0F72_REG_6) },
3530   },
3531   /* REG_0F73 */
3532   {
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { MOD_TABLE (MOD_0F73_REG_2) },
3536     { MOD_TABLE (MOD_0F73_REG_3) },
3537     { Bad_Opcode },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0F73_REG_6) },
3540     { MOD_TABLE (MOD_0F73_REG_7) },
3541   },
3542   /* REG_0FA6 */
3543   {
3544     { "montmul",        { { OP_0f07, 0 } }, 0 },
3545     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3546     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3547   },
3548   /* REG_0FA7 */
3549   {
3550     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3551     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3552     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3553     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3554     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3555     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3556   },
3557   /* REG_0FAE */
3558   {
3559     { MOD_TABLE (MOD_0FAE_REG_0) },
3560     { MOD_TABLE (MOD_0FAE_REG_1) },
3561     { MOD_TABLE (MOD_0FAE_REG_2) },
3562     { MOD_TABLE (MOD_0FAE_REG_3) },
3563     { MOD_TABLE (MOD_0FAE_REG_4) },
3564     { MOD_TABLE (MOD_0FAE_REG_5) },
3565     { MOD_TABLE (MOD_0FAE_REG_6) },
3566     { MOD_TABLE (MOD_0FAE_REG_7) },
3567   },
3568   /* REG_0FBA */
3569   {
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572     { Bad_Opcode },
3573     { Bad_Opcode },
3574     { "btQ",    { Ev, Ib }, 0 },
3575     { "btsQ",   { Evh1, Ib }, 0 },
3576     { "btrQ",   { Evh1, Ib }, 0 },
3577     { "btcQ",   { Evh1, Ib }, 0 },
3578   },
3579   /* REG_0FC7 */
3580   {
3581     { Bad_Opcode },
3582     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3583     { Bad_Opcode },
3584     { MOD_TABLE (MOD_0FC7_REG_3) },
3585     { MOD_TABLE (MOD_0FC7_REG_4) },
3586     { MOD_TABLE (MOD_0FC7_REG_5) },
3587     { MOD_TABLE (MOD_0FC7_REG_6) },
3588     { MOD_TABLE (MOD_0FC7_REG_7) },
3589   },
3590   /* REG_VEX_0F71 */
3591   {
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3595     { Bad_Opcode },
3596     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3597     { Bad_Opcode },
3598     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3599   },
3600   /* REG_VEX_0F72 */
3601   {
3602     { Bad_Opcode },
3603     { Bad_Opcode },
3604     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3605     { Bad_Opcode },
3606     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3607     { Bad_Opcode },
3608     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3609   },
3610   /* REG_VEX_0F73 */
3611   {
3612     { Bad_Opcode },
3613     { Bad_Opcode },
3614     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3615     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3619     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3620   },
3621   /* REG_VEX_0FAE */
3622   {
3623     { Bad_Opcode },
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3626     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3627   },
3628   /* REG_VEX_0F38F3 */
3629   {
3630     { Bad_Opcode },
3631     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3632     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3633     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3634   },
3635   /* REG_XOP_LWPCB */
3636   {
3637     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3638     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3639   },
3640   /* REG_XOP_LWP */
3641   {
3642     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3643     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3644   },
3645   /* REG_XOP_TBM_01 */
3646   {
3647     { Bad_Opcode },
3648     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3649     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3650     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3651     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3652     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3653     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3654     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3655   },
3656   /* REG_XOP_TBM_02 */
3657   {
3658     { Bad_Opcode },
3659     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3660     { Bad_Opcode },
3661     { Bad_Opcode },
3662     { Bad_Opcode },
3663     { Bad_Opcode },
3664     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3665   },
3666 #define NEED_REG_TABLE
3667 #include "i386-dis-evex.h"
3668 #undef NEED_REG_TABLE
3669 };
3670
3671 static const struct dis386 prefix_table[][4] = {
3672   /* PREFIX_90 */
3673   {
3674     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3675     { "pause", { XX }, 0 },
3676     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3677     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3678   },
3679
3680   /* PREFIX_0F10 */
3681   {
3682     { "movups", { XM, EXx }, PREFIX_OPCODE },
3683     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3684     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3685     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3686   },
3687
3688   /* PREFIX_0F11 */
3689   {
3690     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3691     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3692     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3693     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3694   },
3695
3696   /* PREFIX_0F12 */
3697   {
3698     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3699     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3700     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3701     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3702   },
3703
3704   /* PREFIX_0F16 */
3705   {
3706     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3707     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3708     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3709   },
3710
3711   /* PREFIX_0F1A */
3712   {
3713     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3714     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3715     { "bndmov", { Gbnd, Ebnd }, 0 },
3716     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3717   },
3718
3719   /* PREFIX_0F1B */
3720   {
3721     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3722     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3723     { "bndmov", { Ebnd, Gbnd }, 0 },
3724     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3725   },
3726
3727   /* PREFIX_0F2A */
3728   {
3729     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3730     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3731     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3732     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3733   },
3734
3735   /* PREFIX_0F2B */
3736   {
3737     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3738     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3739     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3740     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3741   },
3742
3743   /* PREFIX_0F2C */
3744   {
3745     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3746     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3747     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3748     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3749   },
3750
3751   /* PREFIX_0F2D */
3752   {
3753     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3754     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3755     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3756     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F2E */
3760   {
3761     { "ucomiss",{ XM, EXd }, 0 },
3762     { Bad_Opcode },
3763     { "ucomisd",{ XM, EXq }, 0 },
3764   },
3765
3766   /* PREFIX_0F2F */
3767   {
3768     { "comiss", { XM, EXd }, 0 },
3769     { Bad_Opcode },
3770     { "comisd", { XM, EXq }, 0 },
3771   },
3772
3773   /* PREFIX_0F51 */
3774   {
3775     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3776     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3777     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3778     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F52 */
3782   {
3783     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3784     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F53 */
3788   {
3789     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3790     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3791   },
3792
3793   /* PREFIX_0F58 */
3794   {
3795     { "addps", { XM, EXx }, PREFIX_OPCODE },
3796     { "addss", { XM, EXd }, PREFIX_OPCODE },
3797     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3798     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3799   },
3800
3801   /* PREFIX_0F59 */
3802   {
3803     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3804     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3805     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3806     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3807   },
3808
3809   /* PREFIX_0F5A */
3810   {
3811     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3812     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3813     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3814     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3815   },
3816
3817   /* PREFIX_0F5B */
3818   {
3819     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3820     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3821     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3822   },
3823
3824   /* PREFIX_0F5C */
3825   {
3826     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3827     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3828     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3829     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3830   },
3831
3832   /* PREFIX_0F5D */
3833   {
3834     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3835     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3836     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3837     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3838   },
3839
3840   /* PREFIX_0F5E */
3841   {
3842     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3843     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3844     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3845     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F5F */
3849   {
3850     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3851     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3852     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3853     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3854   },
3855
3856   /* PREFIX_0F60 */
3857   {
3858     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3859     { Bad_Opcode },
3860     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F61 */
3864   {
3865     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3866     { Bad_Opcode },
3867     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3868   },
3869
3870   /* PREFIX_0F62 */
3871   {
3872     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3873     { Bad_Opcode },
3874     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3875   },
3876
3877   /* PREFIX_0F6C */
3878   {
3879     { Bad_Opcode },
3880     { Bad_Opcode },
3881     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F6D */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F6F */
3892   {
3893     { "movq",   { MX, EM }, PREFIX_OPCODE },
3894     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3895     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3896   },
3897
3898   /* PREFIX_0F70 */
3899   {
3900     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3901     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3902     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3903     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F73_REG_3 */
3907   {
3908     { Bad_Opcode },
3909     { Bad_Opcode },
3910     { "psrldq", { XS, Ib }, 0 },
3911   },
3912
3913   /* PREFIX_0F73_REG_7 */
3914   {
3915     { Bad_Opcode },
3916     { Bad_Opcode },
3917     { "pslldq", { XS, Ib }, 0 },
3918   },
3919
3920   /* PREFIX_0F78 */
3921   {
3922     {"vmread",  { Em, Gm }, 0 },
3923     { Bad_Opcode },
3924     {"extrq",   { XS, Ib, Ib }, 0 },
3925     {"insertq", { XM, XS, Ib, Ib }, 0 },
3926   },
3927
3928   /* PREFIX_0F79 */
3929   {
3930     {"vmwrite", { Gm, Em }, 0 },
3931     { Bad_Opcode },
3932     {"extrq",   { XM, XS }, 0 },
3933     {"insertq", { XM, XS }, 0 },
3934   },
3935
3936   /* PREFIX_0F7C */
3937   {
3938     { Bad_Opcode },
3939     { Bad_Opcode },
3940     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3941     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0F7D */
3945   {
3946     { Bad_Opcode },
3947     { Bad_Opcode },
3948     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3949     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F7E */
3953   {
3954     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3955     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3956     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F7F */
3960   {
3961     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3962     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3963     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0FAE_REG_0 */
3967   {
3968     { Bad_Opcode },
3969     { "rdfsbase", { Ev }, 0 },
3970   },
3971
3972   /* PREFIX_0FAE_REG_1 */
3973   {
3974     { Bad_Opcode },
3975     { "rdgsbase", { Ev }, 0 },
3976   },
3977
3978   /* PREFIX_0FAE_REG_2 */
3979   {
3980     { Bad_Opcode },
3981     { "wrfsbase", { Ev }, 0 },
3982   },
3983
3984   /* PREFIX_0FAE_REG_3 */
3985   {
3986     { Bad_Opcode },
3987     { "wrgsbase", { Ev }, 0 },
3988   },
3989
3990   /* PREFIX_0FAE_REG_6 */
3991   {
3992     { "xsaveopt",      { FXSAVE }, 0 },
3993     { Bad_Opcode },
3994     { "clwb",   { Mb }, 0 },
3995   },
3996
3997   /* PREFIX_0FAE_REG_7 */
3998   {
3999     { "clflush",        { Mb }, 0 },
4000     { Bad_Opcode },
4001     { "clflushopt",     { Mb }, 0 },
4002   },
4003
4004   /* PREFIX_RM_0_0FAE_REG_7 */
4005   {
4006     { "sfence",         { Skip_MODRM }, 0 },
4007     { Bad_Opcode },
4008     { "pcommit",                { Skip_MODRM }, 0 },
4009   },
4010
4011   /* PREFIX_0FB8 */
4012   {
4013     { Bad_Opcode },
4014     { "popcntS", { Gv, Ev }, 0 },
4015   },
4016
4017   /* PREFIX_0FBC */
4018   {
4019     { "bsfS",   { Gv, Ev }, 0 },
4020     { "tzcntS", { Gv, Ev }, 0 },
4021     { "bsfS",   { Gv, Ev }, 0 },
4022   },
4023
4024   /* PREFIX_0FBD */
4025   {
4026     { "bsrS",   { Gv, Ev }, 0 },
4027     { "lzcntS", { Gv, Ev }, 0 },
4028     { "bsrS",   { Gv, Ev }, 0 },
4029   },
4030
4031   /* PREFIX_0FC2 */
4032   {
4033     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4034     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4035     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4036     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0FC3 */
4040   {
4041     { "movntiS", { Ma, Gv }, PREFIX_OPCODE },
4042   },
4043
4044   /* PREFIX_MOD_0_0FC7_REG_6 */
4045   {
4046     { "vmptrld",{ Mq }, 0 },
4047     { "vmxon",  { Mq }, 0 },
4048     { "vmclear",{ Mq }, 0 },
4049   },
4050
4051   /* PREFIX_MOD_3_0FC7_REG_6 */
4052   {
4053     { "rdrand", { Ev }, 0 },
4054     { Bad_Opcode },
4055     { "rdrand", { Ev }, 0 }
4056   },
4057
4058   /* PREFIX_MOD_3_0FC7_REG_7 */
4059   {
4060     { "rdseed", { Ev }, 0 },
4061     { Bad_Opcode },
4062     { "rdseed", { Ev }, 0 },
4063   },
4064
4065   /* PREFIX_0FD0 */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { "addsubpd", { XM, EXx }, 0 },
4070     { "addsubps", { XM, EXx }, 0 },
4071   },
4072
4073   /* PREFIX_0FD6 */
4074   {
4075     { Bad_Opcode },
4076     { "movq2dq",{ XM, MS }, 0 },
4077     { "movq",   { EXqS, XM }, 0 },
4078     { "movdq2q",{ MX, XS }, 0 },
4079   },
4080
4081   /* PREFIX_0FE6 */
4082   {
4083     { Bad_Opcode },
4084     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4085     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4086     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4087   },
4088
4089   /* PREFIX_0FE7 */
4090   {
4091     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4092     { Bad_Opcode },
4093     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4094   },
4095
4096   /* PREFIX_0FF0 */
4097   {
4098     { Bad_Opcode },
4099     { Bad_Opcode },
4100     { Bad_Opcode },
4101     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4102   },
4103
4104   /* PREFIX_0FF7 */
4105   {
4106     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4107     { Bad_Opcode },
4108     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4109   },
4110
4111   /* PREFIX_0F3810 */
4112   {
4113     { Bad_Opcode },
4114     { Bad_Opcode },
4115     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4116   },
4117
4118   /* PREFIX_0F3814 */
4119   {
4120     { Bad_Opcode },
4121     { Bad_Opcode },
4122     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4123   },
4124
4125   /* PREFIX_0F3815 */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4130   },
4131
4132   /* PREFIX_0F3817 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_0F3820 */
4140   {
4141     { Bad_Opcode },
4142     { Bad_Opcode },
4143     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4144   },
4145
4146   /* PREFIX_0F3821 */
4147   {
4148     { Bad_Opcode },
4149     { Bad_Opcode },
4150     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4151   },
4152
4153   /* PREFIX_0F3822 */
4154   {
4155     { Bad_Opcode },
4156     { Bad_Opcode },
4157     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4158   },
4159
4160   /* PREFIX_0F3823 */
4161   {
4162     { Bad_Opcode },
4163     { Bad_Opcode },
4164     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F3824 */
4168   {
4169     { Bad_Opcode },
4170     { Bad_Opcode },
4171     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F3825 */
4175   {
4176     { Bad_Opcode },
4177     { Bad_Opcode },
4178     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0F3828 */
4182   {
4183     { Bad_Opcode },
4184     { Bad_Opcode },
4185     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4186   },
4187
4188   /* PREFIX_0F3829 */
4189   {
4190     { Bad_Opcode },
4191     { Bad_Opcode },
4192     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4193   },
4194
4195   /* PREFIX_0F382A */
4196   {
4197     { Bad_Opcode },
4198     { Bad_Opcode },
4199     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4200   },
4201
4202   /* PREFIX_0F382B */
4203   {
4204     { Bad_Opcode },
4205     { Bad_Opcode },
4206     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4207   },
4208
4209   /* PREFIX_0F3830 */
4210   {
4211     { Bad_Opcode },
4212     { Bad_Opcode },
4213     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4214   },
4215
4216   /* PREFIX_0F3831 */
4217   {
4218     { Bad_Opcode },
4219     { Bad_Opcode },
4220     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4221   },
4222
4223   /* PREFIX_0F3832 */
4224   {
4225     { Bad_Opcode },
4226     { Bad_Opcode },
4227     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4228   },
4229
4230   /* PREFIX_0F3833 */
4231   {
4232     { Bad_Opcode },
4233     { Bad_Opcode },
4234     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0F3834 */
4238   {
4239     { Bad_Opcode },
4240     { Bad_Opcode },
4241     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4242   },
4243
4244   /* PREFIX_0F3835 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4249   },
4250
4251   /* PREFIX_0F3837 */
4252   {
4253     { Bad_Opcode },
4254     { Bad_Opcode },
4255     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4256   },
4257
4258   /* PREFIX_0F3838 */
4259   {
4260     { Bad_Opcode },
4261     { Bad_Opcode },
4262     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4263   },
4264
4265   /* PREFIX_0F3839 */
4266   {
4267     { Bad_Opcode },
4268     { Bad_Opcode },
4269     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4270   },
4271
4272   /* PREFIX_0F383A */
4273   {
4274     { Bad_Opcode },
4275     { Bad_Opcode },
4276     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4277   },
4278
4279   /* PREFIX_0F383B */
4280   {
4281     { Bad_Opcode },
4282     { Bad_Opcode },
4283     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4284   },
4285
4286   /* PREFIX_0F383C */
4287   {
4288     { Bad_Opcode },
4289     { Bad_Opcode },
4290     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4291   },
4292
4293   /* PREFIX_0F383D */
4294   {
4295     { Bad_Opcode },
4296     { Bad_Opcode },
4297     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4298   },
4299
4300   /* PREFIX_0F383E */
4301   {
4302     { Bad_Opcode },
4303     { Bad_Opcode },
4304     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4305   },
4306
4307   /* PREFIX_0F383F */
4308   {
4309     { Bad_Opcode },
4310     { Bad_Opcode },
4311     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4312   },
4313
4314   /* PREFIX_0F3840 */
4315   {
4316     { Bad_Opcode },
4317     { Bad_Opcode },
4318     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4319   },
4320
4321   /* PREFIX_0F3841 */
4322   {
4323     { Bad_Opcode },
4324     { Bad_Opcode },
4325     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0F3880 */
4329   {
4330     { Bad_Opcode },
4331     { Bad_Opcode },
4332     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4333   },
4334
4335   /* PREFIX_0F3881 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4340   },
4341
4342   /* PREFIX_0F3882 */
4343   {
4344     { Bad_Opcode },
4345     { Bad_Opcode },
4346     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4347   },
4348
4349   /* PREFIX_0F38C8 */
4350   {
4351     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F38C9 */
4355   {
4356     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F38CA */
4360   {
4361     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F38CB */
4365   {
4366     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4367   },
4368
4369   /* PREFIX_0F38CC */
4370   {
4371     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4372   },
4373
4374   /* PREFIX_0F38CD */
4375   {
4376     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4377   },
4378
4379   /* PREFIX_0F38DB */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F38DC */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38DD */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4398   },
4399
4400   /* PREFIX_0F38DE */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4405   },
4406
4407   /* PREFIX_0F38DF */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4412   },
4413
4414   /* PREFIX_0F38F0 */
4415   {
4416     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4417     { Bad_Opcode },
4418     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4419     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F38F1 */
4423   {
4424     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4425     { Bad_Opcode },
4426     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4427     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4428   },
4429
4430   /* PREFIX_0F38F6 */
4431   {
4432     { Bad_Opcode },
4433     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4434     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4435     { Bad_Opcode },
4436   },
4437
4438   /* PREFIX_0F3A08 */
4439   {
4440     { Bad_Opcode },
4441     { Bad_Opcode },
4442     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4443   },
4444
4445   /* PREFIX_0F3A09 */
4446   {
4447     { Bad_Opcode },
4448     { Bad_Opcode },
4449     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4450   },
4451
4452   /* PREFIX_0F3A0A */
4453   {
4454     { Bad_Opcode },
4455     { Bad_Opcode },
4456     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4457   },
4458
4459   /* PREFIX_0F3A0B */
4460   {
4461     { Bad_Opcode },
4462     { Bad_Opcode },
4463     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F3A0C */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F3A0D */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F3A0E */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F3A14 */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F3A15 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A16 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A17 */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A20 */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A21 */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A22 */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A40 */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A41 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A42 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A44 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A60 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A61 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A62 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A63 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3ACC */
4593   {
4594     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4595   },
4596
4597   /* PREFIX_0F3ADF */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4602   },
4603
4604   /* PREFIX_VEX_0F10 */
4605   {
4606     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4607     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4608     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4609     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4610   },
4611
4612   /* PREFIX_VEX_0F11 */
4613   {
4614     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4615     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4616     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4617     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4618   },
4619
4620   /* PREFIX_VEX_0F12 */
4621   {
4622     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4623     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4624     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4625     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4626   },
4627
4628   /* PREFIX_VEX_0F16 */
4629   {
4630     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4631     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4632     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4633   },
4634
4635   /* PREFIX_VEX_0F2A */
4636   {
4637     { Bad_Opcode },
4638     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4639     { Bad_Opcode },
4640     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4641   },
4642
4643   /* PREFIX_VEX_0F2C */
4644   {
4645     { Bad_Opcode },
4646     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4647     { Bad_Opcode },
4648     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4649   },
4650
4651   /* PREFIX_VEX_0F2D */
4652   {
4653     { Bad_Opcode },
4654     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4655     { Bad_Opcode },
4656     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4657   },
4658
4659   /* PREFIX_VEX_0F2E */
4660   {
4661     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4662     { Bad_Opcode },
4663     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4664   },
4665
4666   /* PREFIX_VEX_0F2F */
4667   {
4668     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4669     { Bad_Opcode },
4670     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4671   },
4672
4673   /* PREFIX_VEX_0F41 */
4674   {
4675     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4676     { Bad_Opcode },
4677     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4678   },
4679
4680   /* PREFIX_VEX_0F42 */
4681   {
4682     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4683     { Bad_Opcode },
4684     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4685   },
4686
4687   /* PREFIX_VEX_0F44 */
4688   {
4689     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4690     { Bad_Opcode },
4691     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4692   },
4693
4694   /* PREFIX_VEX_0F45 */
4695   {
4696     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4697     { Bad_Opcode },
4698     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4699   },
4700
4701   /* PREFIX_VEX_0F46 */
4702   {
4703     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4704     { Bad_Opcode },
4705     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4706   },
4707
4708   /* PREFIX_VEX_0F47 */
4709   {
4710     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4711     { Bad_Opcode },
4712     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4713   },
4714
4715   /* PREFIX_VEX_0F4A */
4716   {
4717     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4718     { Bad_Opcode },
4719     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F4B */
4723   {
4724     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4725     { Bad_Opcode },
4726     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4727   },
4728
4729   /* PREFIX_VEX_0F51 */
4730   {
4731     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4732     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4733     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4734     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4735   },
4736
4737   /* PREFIX_VEX_0F52 */
4738   {
4739     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4740     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4741   },
4742
4743   /* PREFIX_VEX_0F53 */
4744   {
4745     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4746     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4747   },
4748
4749   /* PREFIX_VEX_0F58 */
4750   {
4751     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4752     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4753     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4754     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4755   },
4756
4757   /* PREFIX_VEX_0F59 */
4758   {
4759     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4760     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4761     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4762     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4763   },
4764
4765   /* PREFIX_VEX_0F5A */
4766   {
4767     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4768     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4769     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4770     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4771   },
4772
4773   /* PREFIX_VEX_0F5B */
4774   {
4775     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4776     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4777     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4778   },
4779
4780   /* PREFIX_VEX_0F5C */
4781   {
4782     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4783     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4784     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4785     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4786   },
4787
4788   /* PREFIX_VEX_0F5D */
4789   {
4790     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4791     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4792     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4793     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4794   },
4795
4796   /* PREFIX_VEX_0F5E */
4797   {
4798     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4799     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4800     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4801     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4802   },
4803
4804   /* PREFIX_VEX_0F5F */
4805   {
4806     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4807     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4808     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4809     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4810   },
4811
4812   /* PREFIX_VEX_0F60 */
4813   {
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4817   },
4818
4819   /* PREFIX_VEX_0F61 */
4820   {
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4824   },
4825
4826   /* PREFIX_VEX_0F62 */
4827   {
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4831   },
4832
4833   /* PREFIX_VEX_0F63 */
4834   {
4835     { Bad_Opcode },
4836     { Bad_Opcode },
4837     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4838   },
4839
4840   /* PREFIX_VEX_0F64 */
4841   {
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4845   },
4846
4847   /* PREFIX_VEX_0F65 */
4848   {
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4852   },
4853
4854   /* PREFIX_VEX_0F66 */
4855   {
4856     { Bad_Opcode },
4857     { Bad_Opcode },
4858     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4859   },
4860
4861   /* PREFIX_VEX_0F67 */
4862   {
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4866   },
4867
4868   /* PREFIX_VEX_0F68 */
4869   {
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4873   },
4874
4875   /* PREFIX_VEX_0F69 */
4876   {
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4880   },
4881
4882   /* PREFIX_VEX_0F6A */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4887   },
4888
4889   /* PREFIX_VEX_0F6B */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4894   },
4895
4896   /* PREFIX_VEX_0F6C */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4901   },
4902
4903   /* PREFIX_VEX_0F6D */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4908   },
4909
4910   /* PREFIX_VEX_0F6E */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4915   },
4916
4917   /* PREFIX_VEX_0F6F */
4918   {
4919     { Bad_Opcode },
4920     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4921     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4922   },
4923
4924   /* PREFIX_VEX_0F70 */
4925   {
4926     { Bad_Opcode },
4927     { VEX_W_TABLE (VEX_W_0F70_P_1) },
4928     { VEX_W_TABLE (VEX_W_0F70_P_2) },
4929     { VEX_W_TABLE (VEX_W_0F70_P_3) },
4930   },
4931
4932   /* PREFIX_VEX_0F71_REG_2 */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4937   },
4938
4939   /* PREFIX_VEX_0F71_REG_4 */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4944   },
4945
4946   /* PREFIX_VEX_0F71_REG_6 */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4951   },
4952
4953   /* PREFIX_VEX_0F72_REG_2 */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F72_REG_4 */
4961   {
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4965   },
4966
4967   /* PREFIX_VEX_0F72_REG_6 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4972   },
4973
4974   /* PREFIX_VEX_0F73_REG_2 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F73_REG_3 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F73_REG_6 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F73_REG_7 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F74 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0F75 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5014   },
5015
5016   /* PREFIX_VEX_0F76 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5021   },
5022
5023   /* PREFIX_VEX_0F77 */
5024   {
5025     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5026   },
5027
5028   /* PREFIX_VEX_0F7C */
5029   {
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5033     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5034   },
5035
5036   /* PREFIX_VEX_0F7D */
5037   {
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5041     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5042   },
5043
5044   /* PREFIX_VEX_0F7E */
5045   {
5046     { Bad_Opcode },
5047     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5048     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0F7F */
5052   {
5053     { Bad_Opcode },
5054     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5055     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0F90 */
5059   {
5060     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5061     { Bad_Opcode },
5062     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F91 */
5066   {
5067     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F92 */
5073   {
5074     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5075     { Bad_Opcode },
5076     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5077     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5078   },
5079
5080   /* PREFIX_VEX_0F93 */
5081   {
5082     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5083     { Bad_Opcode },
5084     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5085     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5086   },
5087
5088   /* PREFIX_VEX_0F98 */
5089   {
5090     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5091     { Bad_Opcode },
5092     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5093   },
5094
5095   /* PREFIX_VEX_0F99 */
5096   {
5097     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5098     { Bad_Opcode },
5099     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5100   },
5101
5102   /* PREFIX_VEX_0FC2 */
5103   {
5104     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5105     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5106     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5107     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5108   },
5109
5110   /* PREFIX_VEX_0FC4 */
5111   {
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5115   },
5116
5117   /* PREFIX_VEX_0FC5 */
5118   {
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5122   },
5123
5124   /* PREFIX_VEX_0FD0 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5129     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5130   },
5131
5132   /* PREFIX_VEX_0FD1 */
5133   {
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5137   },
5138
5139   /* PREFIX_VEX_0FD2 */
5140   {
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5144   },
5145
5146   /* PREFIX_VEX_0FD3 */
5147   {
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5151   },
5152
5153   /* PREFIX_VEX_0FD4 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0FD5 */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0FD6 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5172   },
5173
5174   /* PREFIX_VEX_0FD7 */
5175   {
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5179   },
5180
5181   /* PREFIX_VEX_0FD8 */
5182   {
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5186   },
5187
5188   /* PREFIX_VEX_0FD9 */
5189   {
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5193   },
5194
5195   /* PREFIX_VEX_0FDA */
5196   {
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5200   },
5201
5202   /* PREFIX_VEX_0FDB */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5207   },
5208
5209   /* PREFIX_VEX_0FDC */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5214   },
5215
5216   /* PREFIX_VEX_0FDD */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5221   },
5222
5223   /* PREFIX_VEX_0FDE */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5228   },
5229
5230   /* PREFIX_VEX_0FDF */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5235   },
5236
5237   /* PREFIX_VEX_0FE0 */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5242   },
5243
5244   /* PREFIX_VEX_0FE1 */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5249   },
5250
5251   /* PREFIX_VEX_0FE2 */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5256   },
5257
5258   /* PREFIX_VEX_0FE3 */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5263   },
5264
5265   /* PREFIX_VEX_0FE4 */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5270   },
5271
5272   /* PREFIX_VEX_0FE5 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5277   },
5278
5279   /* PREFIX_VEX_0FE6 */
5280   {
5281     { Bad_Opcode },
5282     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5283     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5284     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5285   },
5286
5287   /* PREFIX_VEX_0FE7 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5292   },
5293
5294   /* PREFIX_VEX_0FE8 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_0FE9 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5306   },
5307
5308   /* PREFIX_VEX_0FEA */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5313   },
5314
5315   /* PREFIX_VEX_0FEB */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5320   },
5321
5322   /* PREFIX_VEX_0FEC */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FED */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5334   },
5335
5336   /* PREFIX_VEX_0FEE */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0FEF */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FF0 */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5356   },
5357
5358   /* PREFIX_VEX_0FF1 */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5363   },
5364
5365   /* PREFIX_VEX_0FF2 */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5370   },
5371
5372   /* PREFIX_VEX_0FF3 */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5377   },
5378
5379   /* PREFIX_VEX_0FF4 */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5384   },
5385
5386   /* PREFIX_VEX_0FF5 */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5391   },
5392
5393   /* PREFIX_VEX_0FF6 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5398   },
5399
5400   /* PREFIX_VEX_0FF7 */
5401   {
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5405   },
5406
5407   /* PREFIX_VEX_0FF8 */
5408   {
5409     { Bad_Opcode },
5410     { Bad_Opcode },
5411     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5412   },
5413
5414   /* PREFIX_VEX_0FF9 */
5415   {
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5419   },
5420
5421   /* PREFIX_VEX_0FFA */
5422   {
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5426   },
5427
5428   /* PREFIX_VEX_0FFB */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5433   },
5434
5435   /* PREFIX_VEX_0FFC */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5440   },
5441
5442   /* PREFIX_VEX_0FFD */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5447   },
5448
5449   /* PREFIX_VEX_0FFE */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0F3800 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0F3801 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0F3802 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0F3803 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0F3804 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0F3805 */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0F3806 */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0F3807 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5510   },
5511
5512   /* PREFIX_VEX_0F3808 */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5517   },
5518
5519   /* PREFIX_VEX_0F3809 */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5524   },
5525
5526   /* PREFIX_VEX_0F380A */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5531   },
5532
5533   /* PREFIX_VEX_0F380B */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5538   },
5539
5540   /* PREFIX_VEX_0F380C */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5545   },
5546
5547   /* PREFIX_VEX_0F380D */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5552   },
5553
5554   /* PREFIX_VEX_0F380E */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5559   },
5560
5561   /* PREFIX_VEX_0F380F */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5566   },
5567
5568   /* PREFIX_VEX_0F3813 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F3816 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5580   },
5581
5582   /* PREFIX_VEX_0F3817 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5587   },
5588
5589   /* PREFIX_VEX_0F3818 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5594   },
5595
5596   /* PREFIX_VEX_0F3819 */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5601   },
5602
5603   /* PREFIX_VEX_0F381A */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5608   },
5609
5610   /* PREFIX_VEX_0F381C */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F381D */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F381E */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F3820 */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F3821 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5643   },
5644
5645   /* PREFIX_VEX_0F3822 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F3823 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5657   },
5658
5659   /* PREFIX_VEX_0F3824 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F3825 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F3828 */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F3829 */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5685   },
5686
5687   /* PREFIX_VEX_0F382A */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5692   },
5693
5694   /* PREFIX_VEX_0F382B */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5699   },
5700
5701   /* PREFIX_VEX_0F382C */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5706   },
5707
5708   /* PREFIX_VEX_0F382D */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5713   },
5714
5715   /* PREFIX_VEX_0F382E */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5720   },
5721
5722   /* PREFIX_VEX_0F382F */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5727   },
5728
5729   /* PREFIX_VEX_0F3830 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5734   },
5735
5736   /* PREFIX_VEX_0F3831 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5741   },
5742
5743   /* PREFIX_VEX_0F3832 */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5748   },
5749
5750   /* PREFIX_VEX_0F3833 */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5755   },
5756
5757   /* PREFIX_VEX_0F3834 */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F3835 */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5769   },
5770
5771   /* PREFIX_VEX_0F3836 */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F3837 */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F3838 */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5790   },
5791
5792   /* PREFIX_VEX_0F3839 */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F383A */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5804   },
5805
5806   /* PREFIX_VEX_0F383B */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5811   },
5812
5813   /* PREFIX_VEX_0F383C */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5818   },
5819
5820   /* PREFIX_VEX_0F383D */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5825   },
5826
5827   /* PREFIX_VEX_0F383E */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5832   },
5833
5834   /* PREFIX_VEX_0F383F */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5839   },
5840
5841   /* PREFIX_VEX_0F3840 */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F3841 */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5853   },
5854
5855   /* PREFIX_VEX_0F3845 */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F3846 */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5867   },
5868
5869   /* PREFIX_VEX_0F3847 */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F3858 */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5881   },
5882
5883   /* PREFIX_VEX_0F3859 */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5888   },
5889
5890   /* PREFIX_VEX_0F385A */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5895   },
5896
5897   /* PREFIX_VEX_0F3878 */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5902   },
5903
5904   /* PREFIX_VEX_0F3879 */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5909   },
5910
5911   /* PREFIX_VEX_0F388C */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5916   },
5917
5918   /* PREFIX_VEX_0F388E */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3890 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5930   },
5931
5932   /* PREFIX_VEX_0F3891 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5937   },
5938
5939   /* PREFIX_VEX_0F3892 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5944   },
5945
5946   /* PREFIX_VEX_0F3893 */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5951   },
5952
5953   /* PREFIX_VEX_0F3896 */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
5958   },
5959
5960   /* PREFIX_VEX_0F3897 */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
5965   },
5966
5967   /* PREFIX_VEX_0F3898 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
5972   },
5973
5974   /* PREFIX_VEX_0F3899 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5979   },
5980
5981   /* PREFIX_VEX_0F389A */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
5986   },
5987
5988   /* PREFIX_VEX_0F389B */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
5993   },
5994
5995   /* PREFIX_VEX_0F389C */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6000   },
6001
6002   /* PREFIX_VEX_0F389D */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6007   },
6008
6009   /* PREFIX_VEX_0F389E */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6014   },
6015
6016   /* PREFIX_VEX_0F389F */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6021   },
6022
6023   /* PREFIX_VEX_0F38A6 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6028     { Bad_Opcode },
6029   },
6030
6031   /* PREFIX_VEX_0F38A7 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6036   },
6037
6038   /* PREFIX_VEX_0F38A8 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6043   },
6044
6045   /* PREFIX_VEX_0F38A9 */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6050   },
6051
6052   /* PREFIX_VEX_0F38AA */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6057   },
6058
6059   /* PREFIX_VEX_0F38AB */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6064   },
6065
6066   /* PREFIX_VEX_0F38AC */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6071   },
6072
6073   /* PREFIX_VEX_0F38AD */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6078   },
6079
6080   /* PREFIX_VEX_0F38AE */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F38AF */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F38B6 */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F38B7 */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38B8 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6113   },
6114
6115   /* PREFIX_VEX_0F38B9 */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6120   },
6121
6122   /* PREFIX_VEX_0F38BA */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F38BB */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F38BC */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F38BD */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F38BE */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F38BF */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F38DB */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6169   },
6170
6171   /* PREFIX_VEX_0F38DC */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6176   },
6177
6178   /* PREFIX_VEX_0F38DD */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6183   },
6184
6185   /* PREFIX_VEX_0F38DE */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6190   },
6191
6192   /* PREFIX_VEX_0F38DF */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6197   },
6198
6199   /* PREFIX_VEX_0F38F2 */
6200   {
6201     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6202   },
6203
6204   /* PREFIX_VEX_0F38F3_REG_1 */
6205   {
6206     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6207   },
6208
6209   /* PREFIX_VEX_0F38F3_REG_2 */
6210   {
6211     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6212   },
6213
6214   /* PREFIX_VEX_0F38F3_REG_3 */
6215   {
6216     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6217   },
6218
6219   /* PREFIX_VEX_0F38F5 */
6220   {
6221     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6222     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6223     { Bad_Opcode },
6224     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6225   },
6226
6227   /* PREFIX_VEX_0F38F6 */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6233   },
6234
6235   /* PREFIX_VEX_0F38F7 */
6236   {
6237     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6238     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6239     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6240     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6241   },
6242
6243   /* PREFIX_VEX_0F3A00 */
6244   {
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6248   },
6249
6250   /* PREFIX_VEX_0F3A01 */
6251   {
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6255   },
6256
6257   /* PREFIX_VEX_0F3A02 */
6258   {
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6262   },
6263
6264   /* PREFIX_VEX_0F3A04 */
6265   {
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6269   },
6270
6271   /* PREFIX_VEX_0F3A05 */
6272   {
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6276   },
6277
6278   /* PREFIX_VEX_0F3A06 */
6279   {
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6283   },
6284
6285   /* PREFIX_VEX_0F3A08 */
6286   {
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6290   },
6291
6292   /* PREFIX_VEX_0F3A09 */
6293   {
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6297   },
6298
6299   /* PREFIX_VEX_0F3A0A */
6300   {
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6304   },
6305
6306   /* PREFIX_VEX_0F3A0B */
6307   {
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6311   },
6312
6313   /* PREFIX_VEX_0F3A0C */
6314   {
6315     { Bad_Opcode },
6316     { Bad_Opcode },
6317     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6318   },
6319
6320   /* PREFIX_VEX_0F3A0D */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A0E */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6332   },
6333
6334   /* PREFIX_VEX_0F3A0F */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6339   },
6340
6341   /* PREFIX_VEX_0F3A14 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6346   },
6347
6348   /* PREFIX_VEX_0F3A15 */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6353   },
6354
6355   /* PREFIX_VEX_0F3A16 */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6360   },
6361
6362   /* PREFIX_VEX_0F3A17 */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6367   },
6368
6369   /* PREFIX_VEX_0F3A18 */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6374   },
6375
6376   /* PREFIX_VEX_0F3A19 */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6381   },
6382
6383   /* PREFIX_VEX_0F3A1D */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6388   },
6389
6390   /* PREFIX_VEX_0F3A20 */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6395   },
6396
6397   /* PREFIX_VEX_0F3A21 */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6402   },
6403
6404   /* PREFIX_VEX_0F3A22 */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6409   },
6410
6411   /* PREFIX_VEX_0F3A30 */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6416   },
6417
6418   /* PREFIX_VEX_0F3A31 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A32 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A33 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A38 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A39 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A40 */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A41 */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6465   },
6466
6467   /* PREFIX_VEX_0F3A42 */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A44 */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A46 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A48 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A49 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A4A */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A4B */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A4C */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A5C */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6528   },
6529
6530   /* PREFIX_VEX_0F3A5D */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6535   },
6536
6537   /* PREFIX_VEX_0F3A5E */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6542   },
6543
6544   /* PREFIX_VEX_0F3A5F */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6549   },
6550
6551   /* PREFIX_VEX_0F3A60 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6556     { Bad_Opcode },
6557   },
6558
6559   /* PREFIX_VEX_0F3A61 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A62 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A63 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A68 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6585   },
6586
6587   /* PREFIX_VEX_0F3A69 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6592   },
6593
6594   /* PREFIX_VEX_0F3A6A */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A6B */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A6C */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6613   },
6614
6615   /* PREFIX_VEX_0F3A6D */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6620   },
6621
6622   /* PREFIX_VEX_0F3A6E */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6627   },
6628
6629   /* PREFIX_VEX_0F3A6F */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6634   },
6635
6636   /* PREFIX_VEX_0F3A78 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6641   },
6642
6643   /* PREFIX_VEX_0F3A79 */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6648   },
6649
6650   /* PREFIX_VEX_0F3A7A */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A7B */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6662   },
6663
6664   /* PREFIX_VEX_0F3A7C */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6669     { Bad_Opcode },
6670   },
6671
6672   /* PREFIX_VEX_0F3A7D */
6673   {
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6677   },
6678
6679   /* PREFIX_VEX_0F3A7E */
6680   {
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6684   },
6685
6686   /* PREFIX_VEX_0F3A7F */
6687   {
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6691   },
6692
6693   /* PREFIX_VEX_0F3ADF */
6694   {
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6698   },
6699
6700   /* PREFIX_VEX_0F3AF0 */
6701   {
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6706   },
6707
6708 #define NEED_PREFIX_TABLE
6709 #include "i386-dis-evex.h"
6710 #undef NEED_PREFIX_TABLE
6711 };
6712
6713 static const struct dis386 x86_64_table[][2] = {
6714   /* X86_64_06 */
6715   {
6716     { "pushP", { es }, 0 },
6717   },
6718
6719   /* X86_64_07 */
6720   {
6721     { "popP", { es }, 0 },
6722   },
6723
6724   /* X86_64_0D */
6725   {
6726     { "pushP", { cs }, 0 },
6727   },
6728
6729   /* X86_64_16 */
6730   {
6731     { "pushP", { ss }, 0 },
6732   },
6733
6734   /* X86_64_17 */
6735   {
6736     { "popP", { ss }, 0 },
6737   },
6738
6739   /* X86_64_1E */
6740   {
6741     { "pushP", { ds }, 0 },
6742   },
6743
6744   /* X86_64_1F */
6745   {
6746     { "popP", { ds }, 0 },
6747   },
6748
6749   /* X86_64_27 */
6750   {
6751     { "daa", { XX }, 0 },
6752   },
6753
6754   /* X86_64_2F */
6755   {
6756     { "das", { XX }, 0 },
6757   },
6758
6759   /* X86_64_37 */
6760   {
6761     { "aaa", { XX }, 0 },
6762   },
6763
6764   /* X86_64_3F */
6765   {
6766     { "aas", { XX }, 0 },
6767   },
6768
6769   /* X86_64_60 */
6770   {
6771     { "pushaP", { XX }, 0 },
6772   },
6773
6774   /* X86_64_61 */
6775   {
6776     { "popaP", { XX }, 0 },
6777   },
6778
6779   /* X86_64_62 */
6780   {
6781     { MOD_TABLE (MOD_62_32BIT) },
6782     { EVEX_TABLE (EVEX_0F) },
6783   },
6784
6785   /* X86_64_63 */
6786   {
6787     { "arpl", { Ew, Gw }, 0 },
6788     { "movs{lq|xd}", { Gv, Ed }, 0 },
6789   },
6790
6791   /* X86_64_6D */
6792   {
6793     { "ins{R|}", { Yzr, indirDX }, 0 },
6794     { "ins{G|}", { Yzr, indirDX }, 0 },
6795   },
6796
6797   /* X86_64_6F */
6798   {
6799     { "outs{R|}", { indirDXr, Xz }, 0 },
6800     { "outs{G|}", { indirDXr, Xz }, 0 },
6801   },
6802
6803   /* X86_64_9A */
6804   {
6805     { "Jcall{T|}", { Ap }, 0 },
6806   },
6807
6808   /* X86_64_C4 */
6809   {
6810     { MOD_TABLE (MOD_C4_32BIT) },
6811     { VEX_C4_TABLE (VEX_0F) },
6812   },
6813
6814   /* X86_64_C5 */
6815   {
6816     { MOD_TABLE (MOD_C5_32BIT) },
6817     { VEX_C5_TABLE (VEX_0F) },
6818   },
6819
6820   /* X86_64_CE */
6821   {
6822     { "into", { XX }, 0 },
6823   },
6824
6825   /* X86_64_D4 */
6826   {
6827     { "aam", { Ib }, 0 },
6828   },
6829
6830   /* X86_64_D5 */
6831   {
6832     { "aad", { Ib }, 0 },
6833   },
6834
6835   /* X86_64_EA */
6836   {
6837     { "Jjmp{T|}", { Ap }, 0 },
6838   },
6839
6840   /* X86_64_0F01_REG_0 */
6841   {
6842     { "sgdt{Q|IQ}", { M }, 0 },
6843     { "sgdt", { M }, 0 },
6844   },
6845
6846   /* X86_64_0F01_REG_1 */
6847   {
6848     { "sidt{Q|IQ}", { M }, 0 },
6849     { "sidt", { M }, 0 },
6850   },
6851
6852   /* X86_64_0F01_REG_2 */
6853   {
6854     { "lgdt{Q|Q}", { M }, 0 },
6855     { "lgdt", { M }, 0 },
6856   },
6857
6858   /* X86_64_0F01_REG_3 */
6859   {
6860     { "lidt{Q|Q}", { M }, 0 },
6861     { "lidt", { M }, 0 },
6862   },
6863 };
6864
6865 static const struct dis386 three_byte_table[][256] = {
6866
6867   /* THREE_BYTE_0F38 */
6868   {
6869     /* 00 */
6870     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6871     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6872     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6873     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6874     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6875     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6876     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6877     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6878     /* 08 */
6879     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6880     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6881     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6882     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     /* 10 */
6888     { PREFIX_TABLE (PREFIX_0F3810) },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { PREFIX_TABLE (PREFIX_0F3814) },
6893     { PREFIX_TABLE (PREFIX_0F3815) },
6894     { Bad_Opcode },
6895     { PREFIX_TABLE (PREFIX_0F3817) },
6896     /* 18 */
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6902     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6903     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6904     { Bad_Opcode },
6905     /* 20 */
6906     { PREFIX_TABLE (PREFIX_0F3820) },
6907     { PREFIX_TABLE (PREFIX_0F3821) },
6908     { PREFIX_TABLE (PREFIX_0F3822) },
6909     { PREFIX_TABLE (PREFIX_0F3823) },
6910     { PREFIX_TABLE (PREFIX_0F3824) },
6911     { PREFIX_TABLE (PREFIX_0F3825) },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     /* 28 */
6915     { PREFIX_TABLE (PREFIX_0F3828) },
6916     { PREFIX_TABLE (PREFIX_0F3829) },
6917     { PREFIX_TABLE (PREFIX_0F382A) },
6918     { PREFIX_TABLE (PREFIX_0F382B) },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     /* 30 */
6924     { PREFIX_TABLE (PREFIX_0F3830) },
6925     { PREFIX_TABLE (PREFIX_0F3831) },
6926     { PREFIX_TABLE (PREFIX_0F3832) },
6927     { PREFIX_TABLE (PREFIX_0F3833) },
6928     { PREFIX_TABLE (PREFIX_0F3834) },
6929     { PREFIX_TABLE (PREFIX_0F3835) },
6930     { Bad_Opcode },
6931     { PREFIX_TABLE (PREFIX_0F3837) },
6932     /* 38 */
6933     { PREFIX_TABLE (PREFIX_0F3838) },
6934     { PREFIX_TABLE (PREFIX_0F3839) },
6935     { PREFIX_TABLE (PREFIX_0F383A) },
6936     { PREFIX_TABLE (PREFIX_0F383B) },
6937     { PREFIX_TABLE (PREFIX_0F383C) },
6938     { PREFIX_TABLE (PREFIX_0F383D) },
6939     { PREFIX_TABLE (PREFIX_0F383E) },
6940     { PREFIX_TABLE (PREFIX_0F383F) },
6941     /* 40 */
6942     { PREFIX_TABLE (PREFIX_0F3840) },
6943     { PREFIX_TABLE (PREFIX_0F3841) },
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     /* 48 */
6951     { Bad_Opcode },
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     /* 50 */
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     /* 58 */
6969     { Bad_Opcode },
6970     { Bad_Opcode },
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     /* 60 */
6978     { Bad_Opcode },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     /* 68 */
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     /* 70 */
6996     { Bad_Opcode },
6997     { Bad_Opcode },
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* 78 */
7005     { Bad_Opcode },
7006     { Bad_Opcode },
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* 80 */
7014     { PREFIX_TABLE (PREFIX_0F3880) },
7015     { PREFIX_TABLE (PREFIX_0F3881) },
7016     { PREFIX_TABLE (PREFIX_0F3882) },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     /* 88 */
7023     { Bad_Opcode },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     /* 90 */
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* 98 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* a0 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* a8 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* b0 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* b8 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* c0 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* c8 */
7095     { PREFIX_TABLE (PREFIX_0F38C8) },
7096     { PREFIX_TABLE (PREFIX_0F38C9) },
7097     { PREFIX_TABLE (PREFIX_0F38CA) },
7098     { PREFIX_TABLE (PREFIX_0F38CB) },
7099     { PREFIX_TABLE (PREFIX_0F38CC) },
7100     { PREFIX_TABLE (PREFIX_0F38CD) },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* d0 */
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* d8 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { PREFIX_TABLE (PREFIX_0F38DB) },
7117     { PREFIX_TABLE (PREFIX_0F38DC) },
7118     { PREFIX_TABLE (PREFIX_0F38DD) },
7119     { PREFIX_TABLE (PREFIX_0F38DE) },
7120     { PREFIX_TABLE (PREFIX_0F38DF) },
7121     /* e0 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* e8 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* f0 */
7140     { PREFIX_TABLE (PREFIX_0F38F0) },
7141     { PREFIX_TABLE (PREFIX_0F38F1) },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { PREFIX_TABLE (PREFIX_0F38F6) },
7147     { Bad_Opcode },
7148     /* f8 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157   },
7158   /* THREE_BYTE_0F3A */
7159   {
7160     /* 00 */
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* 08 */
7170     { PREFIX_TABLE (PREFIX_0F3A08) },
7171     { PREFIX_TABLE (PREFIX_0F3A09) },
7172     { PREFIX_TABLE (PREFIX_0F3A0A) },
7173     { PREFIX_TABLE (PREFIX_0F3A0B) },
7174     { PREFIX_TABLE (PREFIX_0F3A0C) },
7175     { PREFIX_TABLE (PREFIX_0F3A0D) },
7176     { PREFIX_TABLE (PREFIX_0F3A0E) },
7177     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7178     /* 10 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { PREFIX_TABLE (PREFIX_0F3A14) },
7184     { PREFIX_TABLE (PREFIX_0F3A15) },
7185     { PREFIX_TABLE (PREFIX_0F3A16) },
7186     { PREFIX_TABLE (PREFIX_0F3A17) },
7187     /* 18 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* 20 */
7197     { PREFIX_TABLE (PREFIX_0F3A20) },
7198     { PREFIX_TABLE (PREFIX_0F3A21) },
7199     { PREFIX_TABLE (PREFIX_0F3A22) },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     /* 28 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* 30 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* 38 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* 40 */
7233     { PREFIX_TABLE (PREFIX_0F3A40) },
7234     { PREFIX_TABLE (PREFIX_0F3A41) },
7235     { PREFIX_TABLE (PREFIX_0F3A42) },
7236     { Bad_Opcode },
7237     { PREFIX_TABLE (PREFIX_0F3A44) },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* 48 */
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     /* 50 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* 58 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 60 */
7269     { PREFIX_TABLE (PREFIX_0F3A60) },
7270     { PREFIX_TABLE (PREFIX_0F3A61) },
7271     { PREFIX_TABLE (PREFIX_0F3A62) },
7272     { PREFIX_TABLE (PREFIX_0F3A63) },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 68 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 70 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 78 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 80 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 88 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 90 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 98 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* a0 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* a8 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* b0 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* b8 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* c0 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* c8 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { PREFIX_TABLE (PREFIX_0F3ACC) },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* d0 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* d8 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { PREFIX_TABLE (PREFIX_0F3ADF) },
7412     /* e0 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* e8 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* f0 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* f8 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448   },
7449
7450   /* THREE_BYTE_0F7A */
7451   {
7452     /* 00 */
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     /* 08 */
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     /* 10 */
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     /* 18 */
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     /* 20 */
7489     { "ptest",          { XX }, PREFIX_OPCODE },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     /* 28 */
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     /* 30 */
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     /* 38 */
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     /* 40 */
7525     { Bad_Opcode },
7526     { "phaddbw",        { XM, EXq }, PREFIX_OPCODE },
7527     { "phaddbd",        { XM, EXq }, PREFIX_OPCODE },
7528     { "phaddbq",        { XM, EXq }, PREFIX_OPCODE },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { "phaddwd",        { XM, EXq }, PREFIX_OPCODE },
7532     { "phaddwq",        { XM, EXq }, PREFIX_OPCODE },
7533     /* 48 */
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { "phadddq",        { XM, EXq }, PREFIX_OPCODE },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     /* 50 */
7543     { Bad_Opcode },
7544     { "phaddubw",       { XM, EXq }, PREFIX_OPCODE },
7545     { "phaddubd",       { XM, EXq }, PREFIX_OPCODE },
7546     { "phaddubq",       { XM, EXq }, PREFIX_OPCODE },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { "phadduwd",       { XM, EXq }, PREFIX_OPCODE },
7550     { "phadduwq",       { XM, EXq }, PREFIX_OPCODE },
7551     /* 58 */
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { "phaddudq",       { XM, EXq }, PREFIX_OPCODE },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     /* 60 */
7561     { Bad_Opcode },
7562     { "phsubbw",        { XM, EXq }, PREFIX_OPCODE },
7563     { "phsubbd",        { XM, EXq }, PREFIX_OPCODE },
7564     { "phsubbq",        { XM, EXq }, PREFIX_OPCODE },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     /* 68 */
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     /* 70 */
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     /* 78 */
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     /* 80 */
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     /* 88 */
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     /* 90 */
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     /* 98 */
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     /* a0 */
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     /* a8 */
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     /* b0 */
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     /* b8 */
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     /* c0 */
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     /* c8 */
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     /* d0 */
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     /* d8 */
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     /* e0 */
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     /* e8 */
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     /* f0 */
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     /* f8 */
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740   },
7741 };
7742
7743 static const struct dis386 xop_table[][256] = {
7744   /* XOP_08 */
7745   {
7746     /* 00 */
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     /* 08 */
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     /* 10 */
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     /* 18 */
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     /* 20 */
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     /* 28 */
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     /* 30 */
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     /* 38 */
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     /* 40 */
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     /* 48 */
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     /* 50 */
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     /* 58 */
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     /* 60 */
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     /* 68 */
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     /* 70 */
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     /* 78 */
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     /* 80 */
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7897     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7898     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7899     /* 88 */
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7907     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7908     /* 90 */
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7915     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7916     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7917     /* 98 */
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7925     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7926     /* a0 */
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7930     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7934     { Bad_Opcode },
7935     /* a8 */
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     /* b0 */
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7952     { Bad_Opcode },
7953     /* b8 */
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     /* c0 */
7963     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7964     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7965     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7966     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     /* c8 */
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7977     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7978     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7979     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7980     /* d0 */
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     /* d8 */
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     /* e0 */
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     /* e8 */
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8013     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8014     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8015     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8016     /* f0 */
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     /* f8 */
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034   },
8035   /* XOP_09 */
8036   {
8037     /* 00 */
8038     { Bad_Opcode },
8039     { REG_TABLE (REG_XOP_TBM_01) },
8040     { REG_TABLE (REG_XOP_TBM_02) },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     /* 08 */
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     /* 10 */
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { REG_TABLE (REG_XOP_LWPCB) },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     /* 18 */
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     /* 20 */
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     /* 28 */
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     /* 30 */
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     /* 38 */
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     /* 40 */
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     /* 48 */
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     /* 50 */
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     /* 58 */
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     /* 60 */
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     /* 68 */
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     /* 70 */
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     /* 78 */
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     /* 80 */
8182     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8183     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8184     { "vfrczss",        { XM, EXd }, 0 },
8185     { "vfrczsd",        { XM, EXq }, 0 },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     /* 88 */
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     /* 90 */
8200     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8201     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8202     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8203     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8204     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8205     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8206     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8207     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8208     /* 98 */
8209     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8210     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8211     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     /* a0 */
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     /* a8 */
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     /* b0 */
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     /* b8 */
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     /* c0 */
8254     { Bad_Opcode },
8255     { "vphaddbw",       { XM, EXxmm }, 0 },
8256     { "vphaddbd",       { XM, EXxmm }, 0 },
8257     { "vphaddbq",       { XM, EXxmm }, 0 },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { "vphaddwd",       { XM, EXxmm }, 0 },
8261     { "vphaddwq",       { XM, EXxmm }, 0 },
8262     /* c8 */
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { "vphadddq",       { XM, EXxmm }, 0 },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     /* d0 */
8272     { Bad_Opcode },
8273     { "vphaddubw",      { XM, EXxmm }, 0 },
8274     { "vphaddubd",      { XM, EXxmm }, 0 },
8275     { "vphaddubq",      { XM, EXxmm }, 0 },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { "vphadduwd",      { XM, EXxmm }, 0 },
8279     { "vphadduwq",      { XM, EXxmm }, 0 },
8280     /* d8 */
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { "vphaddudq",      { XM, EXxmm }, 0 },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     /* e0 */
8290     { Bad_Opcode },
8291     { "vphsubbw",       { XM, EXxmm }, 0 },
8292     { "vphsubwd",       { XM, EXxmm }, 0 },
8293     { "vphsubdq",       { XM, EXxmm }, 0 },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     /* e8 */
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     /* f0 */
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     /* f8 */
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325   },
8326   /* XOP_0A */
8327   {
8328     /* 00 */
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     /* 08 */
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     /* 10 */
8347     { "bextr",  { Gv, Ev, Iq }, 0 },
8348     { Bad_Opcode },
8349     { REG_TABLE (REG_XOP_LWP) },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     /* 18 */
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     /* 20 */
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     /* 28 */
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     /* 30 */
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     /* 38 */
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     /* 40 */
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     /* 48 */
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     /* 50 */
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     /* 58 */
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     /* 60 */
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     { Bad_Opcode },
8445     /* 68 */
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     /* 70 */
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     /* 78 */
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     { Bad_Opcode },
8472     /* 80 */
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     /* 88 */
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     /* 90 */
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     { Bad_Opcode },
8499     /* 98 */
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     /* a0 */
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     /* a8 */
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     { Bad_Opcode },
8526     /* b0 */
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     /* b8 */
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     /* c0 */
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     { Bad_Opcode },
8553     /* c8 */
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     /* d0 */
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     /* d8 */
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     /* e0 */
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     /* e8 */
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     /* f0 */
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     /* f8 */
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616   },
8617 };
8618
8619 static const struct dis386 vex_table[][256] = {
8620   /* VEX_0F */
8621   {
8622     /* 00 */
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     /* 08 */
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     /* 10 */
8641     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8644     { MOD_TABLE (MOD_VEX_0F13) },
8645     { VEX_W_TABLE (VEX_W_0F14) },
8646     { VEX_W_TABLE (VEX_W_0F15) },
8647     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8648     { MOD_TABLE (MOD_VEX_0F17) },
8649     /* 18 */
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     { Bad_Opcode },
8658     /* 20 */
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     /* 28 */
8668     { VEX_W_TABLE (VEX_W_0F28) },
8669     { VEX_W_TABLE (VEX_W_0F29) },
8670     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8671     { MOD_TABLE (MOD_VEX_0F2B) },
8672     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8674     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8675     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8676     /* 30 */
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     { Bad_Opcode },
8685     /* 38 */
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     { Bad_Opcode },
8694     /* 40 */
8695     { Bad_Opcode },
8696     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8697     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8698     { Bad_Opcode },
8699     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8702     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8703     /* 48 */
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8707     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     { Bad_Opcode },
8712     /* 50 */
8713     { MOD_TABLE (MOD_VEX_0F50) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8717     { "vandpX",         { XM, Vex, EXx }, 0 },
8718     { "vandnpX",        { XM, Vex, EXx }, 0 },
8719     { "vorpX",          { XM, Vex, EXx }, 0 },
8720     { "vxorpX",         { XM, Vex, EXx }, 0 },
8721     /* 58 */
8722     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8730     /* 60 */
8731     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8735     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8736     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8739     /* 68 */
8740     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8748     /* 70 */
8749     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8750     { REG_TABLE (REG_VEX_0F71) },
8751     { REG_TABLE (REG_VEX_0F72) },
8752     { REG_TABLE (REG_VEX_0F73) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8757     /* 78 */
8758     { Bad_Opcode },
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8766     /* 80 */
8767     { Bad_Opcode },
8768     { Bad_Opcode },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     { Bad_Opcode },
8772     { Bad_Opcode },
8773     { Bad_Opcode },
8774     { Bad_Opcode },
8775     /* 88 */
8776     { Bad_Opcode },
8777     { Bad_Opcode },
8778     { Bad_Opcode },
8779     { Bad_Opcode },
8780     { Bad_Opcode },
8781     { Bad_Opcode },
8782     { Bad_Opcode },
8783     { Bad_Opcode },
8784     /* 90 */
8785     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8789     { Bad_Opcode },
8790     { Bad_Opcode },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     /* 98 */
8794     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     { Bad_Opcode },
8802     /* a0 */
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     /* a8 */
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { REG_TABLE (REG_VEX_0FAE) },
8819     { Bad_Opcode },
8820     /* b0 */
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     /* b8 */
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     /* c0 */
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8842     { Bad_Opcode },
8843     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8844     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8845     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8846     { Bad_Opcode },
8847     /* c8 */
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     /* d0 */
8857     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8858     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8859     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8860     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8861     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8862     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8863     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8864     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8865     /* d8 */
8866     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8867     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8868     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8869     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8871     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8872     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8873     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8874     /* e0 */
8875     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8876     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8877     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8878     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8879     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8880     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8881     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8882     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8883     /* e8 */
8884     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8891     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8892     /* f0 */
8893     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8900     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8901     /* f8 */
8902     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8909     { Bad_Opcode },
8910   },
8911   /* VEX_0F38 */
8912   {
8913     /* 00 */
8914     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8922     /* 08 */
8923     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8927     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8929     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8930     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8931     /* 10 */
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8940     /* 18 */
8941     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8944     { Bad_Opcode },
8945     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8948     { Bad_Opcode },
8949     /* 20 */
8950     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     /* 28 */
8959     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8966     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8967     /* 30 */
8968     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8976     /* 38 */
8977     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8984     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8985     /* 40 */
8986     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8993     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8994     /* 48 */
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { Bad_Opcode },
9002     { Bad_Opcode },
9003     /* 50 */
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     /* 58 */
9013     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     { Bad_Opcode },
9020     { Bad_Opcode },
9021     /* 60 */
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     { Bad_Opcode },
9030     /* 68 */
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     /* 70 */
9040     { Bad_Opcode },
9041     { Bad_Opcode },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     { Bad_Opcode },
9048     /* 78 */
9049     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     { Bad_Opcode },
9057     /* 80 */
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     /* 88 */
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9072     { Bad_Opcode },
9073     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9074     { Bad_Opcode },
9075     /* 90 */
9076     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9078     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9084     /* 98 */
9085     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9090     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9093     /* a0 */
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9102     /* a8 */
9103     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9111     /* b0 */
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9119     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9120     /* b8 */
9121     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9129     /* c0 */
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     /* c8 */
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     /* d0 */
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     /* d8 */
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9161     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9162     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9163     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9165     /* e0 */
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     /* e8 */
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     /* f0 */
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9187     { REG_TABLE (REG_VEX_0F38F3) },
9188     { Bad_Opcode },
9189     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9192     /* f8 */
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201   },
9202   /* VEX_0F3A */
9203   {
9204     /* 00 */
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9208     { Bad_Opcode },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9211     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9212     { Bad_Opcode },
9213     /* 08 */
9214     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9215     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9218     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9219     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9220     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9222     /* 10 */
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9229     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9230     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9231     /* 18 */
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     /* 20 */
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     /* 28 */
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     /* 30 */
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9260     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9261     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9262     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     /* 38 */
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     /* 40 */
9277     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9278     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9279     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9280     { Bad_Opcode },
9281     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9282     { Bad_Opcode },
9283     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9284     { Bad_Opcode },
9285     /* 48 */
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9289     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9290     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     /* 50 */
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     /* 58 */
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9311     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9312     /* 60 */
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     { Bad_Opcode },
9321     /* 68 */
9322     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9323     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9324     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9325     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9326     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9327     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9328     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9329     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9330     /* 70 */
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     { Bad_Opcode },
9339     /* 78 */
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9341     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9343     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9344     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9345     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9346     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9347     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9348     /* 80 */
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     { Bad_Opcode },
9356     { Bad_Opcode },
9357     /* 88 */
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     { Bad_Opcode },
9366     /* 90 */
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373     { Bad_Opcode },
9374     { Bad_Opcode },
9375     /* 98 */
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     { Bad_Opcode },
9384     /* a0 */
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     { Bad_Opcode },
9393     /* a8 */
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     { Bad_Opcode },
9402     /* b0 */
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     { Bad_Opcode },
9411     /* b8 */
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     { Bad_Opcode },
9420     /* c0 */
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     { Bad_Opcode },
9429     /* c8 */
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     { Bad_Opcode },
9438     /* d0 */
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     { Bad_Opcode },
9447     /* d8 */
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9456     /* e0 */
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { Bad_Opcode },
9463     { Bad_Opcode },
9464     { Bad_Opcode },
9465     /* e8 */
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     { Bad_Opcode },
9474     /* f0 */
9475     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { Bad_Opcode },
9482     { Bad_Opcode },
9483     /* f8 */
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     { Bad_Opcode },
9492   },
9493 };
9494
9495 #define NEED_OPCODE_TABLE
9496 #include "i386-dis-evex.h"
9497 #undef NEED_OPCODE_TABLE
9498 static const struct dis386 vex_len_table[][2] = {
9499   /* VEX_LEN_0F10_P_1 */
9500   {
9501     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9502     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9503   },
9504
9505   /* VEX_LEN_0F10_P_3 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9508     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9509   },
9510
9511   /* VEX_LEN_0F11_P_1 */
9512   {
9513     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9514     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9515   },
9516
9517   /* VEX_LEN_0F11_P_3 */
9518   {
9519     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9520     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9521   },
9522
9523   /* VEX_LEN_0F12_P_0_M_0 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9526   },
9527
9528   /* VEX_LEN_0F12_P_0_M_1 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9531   },
9532
9533   /* VEX_LEN_0F12_P_2 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9536   },
9537
9538   /* VEX_LEN_0F13_M_0 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9541   },
9542
9543   /* VEX_LEN_0F16_P_0_M_0 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9546   },
9547
9548   /* VEX_LEN_0F16_P_0_M_1 */
9549   {
9550     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9551   },
9552
9553   /* VEX_LEN_0F16_P_2 */
9554   {
9555     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9556   },
9557
9558   /* VEX_LEN_0F17_M_0 */
9559   {
9560     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9561   },
9562
9563   /* VEX_LEN_0F2A_P_1 */
9564   {
9565     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9566     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9567   },
9568
9569   /* VEX_LEN_0F2A_P_3 */
9570   {
9571     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9572     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9573   },
9574
9575   /* VEX_LEN_0F2C_P_1 */
9576   {
9577     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9578     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F2C_P_3 */
9582   {
9583     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9584     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9585   },
9586
9587   /* VEX_LEN_0F2D_P_1 */
9588   {
9589     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9590     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9591   },
9592
9593   /* VEX_LEN_0F2D_P_3 */
9594   {
9595     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9596     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9597   },
9598
9599   /* VEX_LEN_0F2E_P_0 */
9600   {
9601     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9602     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9603   },
9604
9605   /* VEX_LEN_0F2E_P_2 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9608     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9609   },
9610
9611   /* VEX_LEN_0F2F_P_0 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9614     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9615   },
9616
9617   /* VEX_LEN_0F2F_P_2 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9620     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9621   },
9622
9623   /* VEX_LEN_0F41_P_0 */
9624   {
9625     { Bad_Opcode },
9626     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9627   },
9628   /* VEX_LEN_0F41_P_2 */
9629   {
9630     { Bad_Opcode },
9631     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9632   },
9633   /* VEX_LEN_0F42_P_0 */
9634   {
9635     { Bad_Opcode },
9636     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9637   },
9638   /* VEX_LEN_0F42_P_2 */
9639   {
9640     { Bad_Opcode },
9641     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9642   },
9643   /* VEX_LEN_0F44_P_0 */
9644   {
9645     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9646   },
9647   /* VEX_LEN_0F44_P_2 */
9648   {
9649     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9650   },
9651   /* VEX_LEN_0F45_P_0 */
9652   {
9653     { Bad_Opcode },
9654     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9655   },
9656   /* VEX_LEN_0F45_P_2 */
9657   {
9658     { Bad_Opcode },
9659     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9660   },
9661   /* VEX_LEN_0F46_P_0 */
9662   {
9663     { Bad_Opcode },
9664     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9665   },
9666   /* VEX_LEN_0F46_P_2 */
9667   {
9668     { Bad_Opcode },
9669     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9670   },
9671   /* VEX_LEN_0F47_P_0 */
9672   {
9673     { Bad_Opcode },
9674     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9675   },
9676   /* VEX_LEN_0F47_P_2 */
9677   {
9678     { Bad_Opcode },
9679     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9680   },
9681   /* VEX_LEN_0F4A_P_0 */
9682   {
9683     { Bad_Opcode },
9684     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9685   },
9686   /* VEX_LEN_0F4A_P_2 */
9687   {
9688     { Bad_Opcode },
9689     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9690   },
9691   /* VEX_LEN_0F4B_P_0 */
9692   {
9693     { Bad_Opcode },
9694     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9695   },
9696   /* VEX_LEN_0F4B_P_2 */
9697   {
9698     { Bad_Opcode },
9699     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9700   },
9701
9702   /* VEX_LEN_0F51_P_1 */
9703   {
9704     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9705     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9706   },
9707
9708   /* VEX_LEN_0F51_P_3 */
9709   {
9710     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9711     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9712   },
9713
9714   /* VEX_LEN_0F52_P_1 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9717     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9718   },
9719
9720   /* VEX_LEN_0F53_P_1 */
9721   {
9722     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9723     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9724   },
9725
9726   /* VEX_LEN_0F58_P_1 */
9727   {
9728     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9729     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9730   },
9731
9732   /* VEX_LEN_0F58_P_3 */
9733   {
9734     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9735     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9736   },
9737
9738   /* VEX_LEN_0F59_P_1 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9741     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9742   },
9743
9744   /* VEX_LEN_0F59_P_3 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9747     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9748   },
9749
9750   /* VEX_LEN_0F5A_P_1 */
9751   {
9752     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9753     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9754   },
9755
9756   /* VEX_LEN_0F5A_P_3 */
9757   {
9758     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9759     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9760   },
9761
9762   /* VEX_LEN_0F5C_P_1 */
9763   {
9764     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9765     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9766   },
9767
9768   /* VEX_LEN_0F5C_P_3 */
9769   {
9770     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9771     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9772   },
9773
9774   /* VEX_LEN_0F5D_P_1 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9777     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9778   },
9779
9780   /* VEX_LEN_0F5D_P_3 */
9781   {
9782     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9783     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9784   },
9785
9786   /* VEX_LEN_0F5E_P_1 */
9787   {
9788     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9789     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9790   },
9791
9792   /* VEX_LEN_0F5E_P_3 */
9793   {
9794     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9795     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9796   },
9797
9798   /* VEX_LEN_0F5F_P_1 */
9799   {
9800     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9801     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9802   },
9803
9804   /* VEX_LEN_0F5F_P_3 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9807     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9808   },
9809
9810   /* VEX_LEN_0F6E_P_2 */
9811   {
9812     { "vmovK",          { XMScalar, Edq }, 0 },
9813     { "vmovK",          { XMScalar, Edq }, 0 },
9814   },
9815
9816   /* VEX_LEN_0F7E_P_1 */
9817   {
9818     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9819     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9820   },
9821
9822   /* VEX_LEN_0F7E_P_2 */
9823   {
9824     { "vmovK",          { Edq, XMScalar }, 0 },
9825     { "vmovK",          { Edq, XMScalar }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F90_P_0 */
9829   {
9830     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9831   },
9832
9833   /* VEX_LEN_0F90_P_2 */
9834   {
9835     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9836   },
9837
9838   /* VEX_LEN_0F91_P_0 */
9839   {
9840     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9841   },
9842
9843   /* VEX_LEN_0F91_P_2 */
9844   {
9845     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9846   },
9847
9848   /* VEX_LEN_0F92_P_0 */
9849   {
9850     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9851   },
9852
9853   /* VEX_LEN_0F92_P_2 */
9854   {
9855     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9856   },
9857
9858   /* VEX_LEN_0F92_P_3 */
9859   {
9860     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9861   },
9862
9863   /* VEX_LEN_0F93_P_0 */
9864   {
9865     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9866   },
9867
9868   /* VEX_LEN_0F93_P_2 */
9869   {
9870     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9871   },
9872
9873   /* VEX_LEN_0F93_P_3 */
9874   {
9875     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9876   },
9877
9878   /* VEX_LEN_0F98_P_0 */
9879   {
9880     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9881   },
9882
9883   /* VEX_LEN_0F98_P_2 */
9884   {
9885     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9886   },
9887
9888   /* VEX_LEN_0F99_P_0 */
9889   {
9890     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9891   },
9892
9893   /* VEX_LEN_0F99_P_2 */
9894   {
9895     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9896   },
9897
9898   /* VEX_LEN_0FAE_R_2_M_0 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9901   },
9902
9903   /* VEX_LEN_0FAE_R_3_M_0 */
9904   {
9905     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9906   },
9907
9908   /* VEX_LEN_0FC2_P_1 */
9909   {
9910     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9911     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9912   },
9913
9914   /* VEX_LEN_0FC2_P_3 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9917     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9918   },
9919
9920   /* VEX_LEN_0FC4_P_2 */
9921   {
9922     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9923   },
9924
9925   /* VEX_LEN_0FC5_P_2 */
9926   {
9927     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9928   },
9929
9930   /* VEX_LEN_0FD6_P_2 */
9931   {
9932     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9933     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9934   },
9935
9936   /* VEX_LEN_0FF7_P_2 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9939   },
9940
9941   /* VEX_LEN_0F3816_P_2 */
9942   {
9943     { Bad_Opcode },
9944     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9945   },
9946
9947   /* VEX_LEN_0F3819_P_2 */
9948   {
9949     { Bad_Opcode },
9950     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9951   },
9952
9953   /* VEX_LEN_0F381A_P_2_M_0 */
9954   {
9955     { Bad_Opcode },
9956     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9957   },
9958
9959   /* VEX_LEN_0F3836_P_2 */
9960   {
9961     { Bad_Opcode },
9962     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9963   },
9964
9965   /* VEX_LEN_0F3841_P_2 */
9966   {
9967     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9968   },
9969
9970   /* VEX_LEN_0F385A_P_2_M_0 */
9971   {
9972     { Bad_Opcode },
9973     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9974   },
9975
9976   /* VEX_LEN_0F38DB_P_2 */
9977   {
9978     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9979   },
9980
9981   /* VEX_LEN_0F38DC_P_2 */
9982   {
9983     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9984   },
9985
9986   /* VEX_LEN_0F38DD_P_2 */
9987   {
9988     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9989   },
9990
9991   /* VEX_LEN_0F38DE_P_2 */
9992   {
9993     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9994   },
9995
9996   /* VEX_LEN_0F38DF_P_2 */
9997   {
9998     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9999   },
10000
10001   /* VEX_LEN_0F38F2_P_0 */
10002   {
10003     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10004   },
10005
10006   /* VEX_LEN_0F38F3_R_1_P_0 */
10007   {
10008     { "blsrS",          { VexGdq, Edq }, 0 },
10009   },
10010
10011   /* VEX_LEN_0F38F3_R_2_P_0 */
10012   {
10013     { "blsmskS",        { VexGdq, Edq }, 0 },
10014   },
10015
10016   /* VEX_LEN_0F38F3_R_3_P_0 */
10017   {
10018     { "blsiS",          { VexGdq, Edq }, 0 },
10019   },
10020
10021   /* VEX_LEN_0F38F5_P_0 */
10022   {
10023     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10024   },
10025
10026   /* VEX_LEN_0F38F5_P_1 */
10027   {
10028     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10029   },
10030
10031   /* VEX_LEN_0F38F5_P_3 */
10032   {
10033     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10034   },
10035
10036   /* VEX_LEN_0F38F6_P_3 */
10037   {
10038     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10039   },
10040
10041   /* VEX_LEN_0F38F7_P_0 */
10042   {
10043     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10044   },
10045
10046   /* VEX_LEN_0F38F7_P_1 */
10047   {
10048     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10049   },
10050
10051   /* VEX_LEN_0F38F7_P_2 */
10052   {
10053     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10054   },
10055
10056   /* VEX_LEN_0F38F7_P_3 */
10057   {
10058     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10059   },
10060
10061   /* VEX_LEN_0F3A00_P_2 */
10062   {
10063     { Bad_Opcode },
10064     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10065   },
10066
10067   /* VEX_LEN_0F3A01_P_2 */
10068   {
10069     { Bad_Opcode },
10070     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10071   },
10072
10073   /* VEX_LEN_0F3A06_P_2 */
10074   {
10075     { Bad_Opcode },
10076     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A0A_P_2 */
10080   {
10081     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10082     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A0B_P_2 */
10086   {
10087     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10088     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F3A14_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10094   },
10095
10096   /* VEX_LEN_0F3A15_P_2 */
10097   {
10098     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10099   },
10100
10101   /* VEX_LEN_0F3A16_P_2  */
10102   {
10103     { "vpextrK",        { Edq, XM, Ib }, 0 },
10104   },
10105
10106   /* VEX_LEN_0F3A17_P_2 */
10107   {
10108     { "vextractps",     { Edqd, XM, Ib }, 0 },
10109   },
10110
10111   /* VEX_LEN_0F3A18_P_2 */
10112   {
10113     { Bad_Opcode },
10114     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10115   },
10116
10117   /* VEX_LEN_0F3A19_P_2 */
10118   {
10119     { Bad_Opcode },
10120     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10121   },
10122
10123   /* VEX_LEN_0F3A20_P_2 */
10124   {
10125     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10126   },
10127
10128   /* VEX_LEN_0F3A21_P_2 */
10129   {
10130     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10131   },
10132
10133   /* VEX_LEN_0F3A22_P_2 */
10134   {
10135     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10136   },
10137
10138   /* VEX_LEN_0F3A30_P_2 */
10139   {
10140     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10141   },
10142
10143   /* VEX_LEN_0F3A31_P_2 */
10144   {
10145     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10146   },
10147
10148   /* VEX_LEN_0F3A32_P_2 */
10149   {
10150     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10151   },
10152
10153   /* VEX_LEN_0F3A33_P_2 */
10154   {
10155     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10156   },
10157
10158   /* VEX_LEN_0F3A38_P_2 */
10159   {
10160     { Bad_Opcode },
10161     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10162   },
10163
10164   /* VEX_LEN_0F3A39_P_2 */
10165   {
10166     { Bad_Opcode },
10167     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10168   },
10169
10170   /* VEX_LEN_0F3A41_P_2 */
10171   {
10172     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10173   },
10174
10175   /* VEX_LEN_0F3A44_P_2 */
10176   {
10177     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10178   },
10179
10180   /* VEX_LEN_0F3A46_P_2 */
10181   {
10182     { Bad_Opcode },
10183     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10184   },
10185
10186   /* VEX_LEN_0F3A60_P_2 */
10187   {
10188     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10189   },
10190
10191   /* VEX_LEN_0F3A61_P_2 */
10192   {
10193     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10194   },
10195
10196   /* VEX_LEN_0F3A62_P_2 */
10197   {
10198     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10199   },
10200
10201   /* VEX_LEN_0F3A63_P_2 */
10202   {
10203     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10204   },
10205
10206   /* VEX_LEN_0F3A6A_P_2 */
10207   {
10208     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10209   },
10210
10211   /* VEX_LEN_0F3A6B_P_2 */
10212   {
10213     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10214   },
10215
10216   /* VEX_LEN_0F3A6E_P_2 */
10217   {
10218     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10219   },
10220
10221   /* VEX_LEN_0F3A6F_P_2 */
10222   {
10223     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10224   },
10225
10226   /* VEX_LEN_0F3A7A_P_2 */
10227   {
10228     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10229   },
10230
10231   /* VEX_LEN_0F3A7B_P_2 */
10232   {
10233     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10234   },
10235
10236   /* VEX_LEN_0F3A7E_P_2 */
10237   {
10238     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10239   },
10240
10241   /* VEX_LEN_0F3A7F_P_2 */
10242   {
10243     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10244   },
10245
10246   /* VEX_LEN_0F3ADF_P_2 */
10247   {
10248     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10249   },
10250
10251   /* VEX_LEN_0F3AF0_P_3 */
10252   {
10253     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10254   },
10255
10256   /* VEX_LEN_0FXOP_08_CC */
10257   {
10258      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10259   },
10260
10261   /* VEX_LEN_0FXOP_08_CD */
10262   {
10263      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10264   },
10265
10266   /* VEX_LEN_0FXOP_08_CE */
10267   {
10268      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10269   },
10270
10271   /* VEX_LEN_0FXOP_08_CF */
10272   {
10273      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10274   },
10275
10276   /* VEX_LEN_0FXOP_08_EC */
10277   {
10278      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10279   },
10280
10281   /* VEX_LEN_0FXOP_08_ED */
10282   {
10283      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10284   },
10285
10286   /* VEX_LEN_0FXOP_08_EE */
10287   {
10288      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10289   },
10290
10291   /* VEX_LEN_0FXOP_08_EF */
10292   {
10293      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10294   },
10295
10296   /* VEX_LEN_0FXOP_09_80 */
10297   {
10298     { "vfrczps",        { XM, EXxmm }, 0 },
10299     { "vfrczps",        { XM, EXymmq }, 0 },
10300   },
10301
10302   /* VEX_LEN_0FXOP_09_81 */
10303   {
10304     { "vfrczpd",        { XM, EXxmm }, 0 },
10305     { "vfrczpd",        { XM, EXymmq }, 0 },
10306   },
10307 };
10308
10309 static const struct dis386 vex_w_table[][2] = {
10310   {
10311     /* VEX_W_0F10_P_0 */
10312     { "vmovups",        { XM, EXx }, 0 },
10313   },
10314   {
10315     /* VEX_W_0F10_P_1 */
10316     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F10_P_2 */
10320     { "vmovupd",        { XM, EXx }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F10_P_3 */
10324     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F11_P_0 */
10328     { "vmovups",        { EXxS, XM }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F11_P_1 */
10332     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F11_P_2 */
10336     { "vmovupd",        { EXxS, XM }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F11_P_3 */
10340     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F12_P_0_M_0 */
10344     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F12_P_0_M_1 */
10348     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F12_P_1 */
10352     { "vmovsldup",      { XM, EXx }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F12_P_2 */
10356     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F12_P_3 */
10360     { "vmovddup",       { XM, EXymmq }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F13_M_0 */
10364     { "vmovlpX",        { EXq, XM }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F14 */
10368     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F15 */
10372     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10373   },
10374   {
10375     /* VEX_W_0F16_P_0_M_0 */
10376     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F16_P_0_M_1 */
10380     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F16_P_1 */
10384     { "vmovshdup",      { XM, EXx }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F16_P_2 */
10388     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F17_M_0 */
10392     { "vmovhpX",        { EXq, XM }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F28 */
10396     { "vmovapX",        { XM, EXx }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F29 */
10400     { "vmovapX",        { EXxS, XM }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F2B_M_0 */
10404     { "vmovntpX",       { Mx, XM }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F2E_P_0 */
10408     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F2E_P_2 */
10412     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F2F_P_0 */
10416     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F2F_P_2 */
10420     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F41_P_0_LEN_1 */
10424     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10425     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10426   },
10427   {
10428     /* VEX_W_0F41_P_2_LEN_1 */
10429     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10430     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10431   },
10432   {
10433     /* VEX_W_0F42_P_0_LEN_1 */
10434     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10435     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F42_P_2_LEN_1 */
10439     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10440     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F44_P_0_LEN_0 */
10444     { "knotw",          { MaskG, MaskR }, 0 },
10445     { "knotq",          { MaskG, MaskR }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F44_P_2_LEN_0 */
10449     { "knotb",          { MaskG, MaskR }, 0 },
10450     { "knotd",          { MaskG, MaskR }, 0 },
10451   },
10452   {
10453     /* VEX_W_0F45_P_0_LEN_1 */
10454     { "korw",           { MaskG, MaskVex, MaskR }, 0 },
10455     { "korq",           { MaskG, MaskVex, MaskR }, 0 },
10456   },
10457   {
10458     /* VEX_W_0F45_P_2_LEN_1 */
10459     { "korb",           { MaskG, MaskVex, MaskR }, 0 },
10460     { "kord",           { MaskG, MaskVex, MaskR }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F46_P_0_LEN_1 */
10464     { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
10465     { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F46_P_2_LEN_1 */
10469     { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
10470     { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
10471   },
10472   {
10473     /* VEX_W_0F47_P_0_LEN_1 */
10474     { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
10475     { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
10476   },
10477   {
10478     /* VEX_W_0F47_P_2_LEN_1 */
10479     { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
10480     { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F4A_P_0_LEN_1 */
10484     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10485     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10486   },
10487   {
10488     /* VEX_W_0F4A_P_2_LEN_1 */
10489     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10490     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10491   },
10492   {
10493     /* VEX_W_0F4B_P_0_LEN_1 */
10494     { "kunpckwd",       { MaskG, MaskVex, MaskR }, 0 },
10495     { "kunpckdq",       { MaskG, MaskVex, MaskR }, 0 },
10496   },
10497   {
10498     /* VEX_W_0F4B_P_2_LEN_1 */
10499     { "kunpckbw",       { MaskG, MaskVex, MaskR }, 0 },
10500   },
10501   {
10502     /* VEX_W_0F50_M_0 */
10503     { "vmovmskpX",      { Gdq, XS }, 0 },
10504   },
10505   {
10506     /* VEX_W_0F51_P_0 */
10507     { "vsqrtps",        { XM, EXx }, 0 },
10508   },
10509   {
10510     /* VEX_W_0F51_P_1 */
10511     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10512   },
10513   {
10514     /* VEX_W_0F51_P_2  */
10515     { "vsqrtpd",        { XM, EXx }, 0 },
10516   },
10517   {
10518     /* VEX_W_0F51_P_3 */
10519     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10520   },
10521   {
10522     /* VEX_W_0F52_P_0 */
10523     { "vrsqrtps",       { XM, EXx }, 0 },
10524   },
10525   {
10526     /* VEX_W_0F52_P_1 */
10527     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10528   },
10529   {
10530     /* VEX_W_0F53_P_0  */
10531     { "vrcpps",         { XM, EXx }, 0 },
10532   },
10533   {
10534     /* VEX_W_0F53_P_1  */
10535     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10536   },
10537   {
10538     /* VEX_W_0F58_P_0  */
10539     { "vaddps",         { XM, Vex, EXx }, 0 },
10540   },
10541   {
10542     /* VEX_W_0F58_P_1  */
10543     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10544   },
10545   {
10546     /* VEX_W_0F58_P_2  */
10547     { "vaddpd",         { XM, Vex, EXx }, 0 },
10548   },
10549   {
10550     /* VEX_W_0F58_P_3  */
10551     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10552   },
10553   {
10554     /* VEX_W_0F59_P_0  */
10555     { "vmulps",         { XM, Vex, EXx }, 0 },
10556   },
10557   {
10558     /* VEX_W_0F59_P_1  */
10559     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10560   },
10561   {
10562     /* VEX_W_0F59_P_2  */
10563     { "vmulpd",         { XM, Vex, EXx }, 0 },
10564   },
10565   {
10566     /* VEX_W_0F59_P_3  */
10567     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10568   },
10569   {
10570     /* VEX_W_0F5A_P_0  */
10571     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10572   },
10573   {
10574     /* VEX_W_0F5A_P_1  */
10575     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10576   },
10577   {
10578     /* VEX_W_0F5A_P_3  */
10579     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10580   },
10581   {
10582     /* VEX_W_0F5B_P_0  */
10583     { "vcvtdq2ps",      { XM, EXx }, 0 },
10584   },
10585   {
10586     /* VEX_W_0F5B_P_1  */
10587     { "vcvttps2dq",     { XM, EXx }, 0 },
10588   },
10589   {
10590     /* VEX_W_0F5B_P_2  */
10591     { "vcvtps2dq",      { XM, EXx }, 0 },
10592   },
10593   {
10594     /* VEX_W_0F5C_P_0  */
10595     { "vsubps",         { XM, Vex, EXx }, 0 },
10596   },
10597   {
10598     /* VEX_W_0F5C_P_1  */
10599     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10600   },
10601   {
10602     /* VEX_W_0F5C_P_2  */
10603     { "vsubpd",         { XM, Vex, EXx }, 0 },
10604   },
10605   {
10606     /* VEX_W_0F5C_P_3  */
10607     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10608   },
10609   {
10610     /* VEX_W_0F5D_P_0  */
10611     { "vminps",         { XM, Vex, EXx }, 0 },
10612   },
10613   {
10614     /* VEX_W_0F5D_P_1  */
10615     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10616   },
10617   {
10618     /* VEX_W_0F5D_P_2  */
10619     { "vminpd",         { XM, Vex, EXx }, 0 },
10620   },
10621   {
10622     /* VEX_W_0F5D_P_3  */
10623     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10624   },
10625   {
10626     /* VEX_W_0F5E_P_0  */
10627     { "vdivps",         { XM, Vex, EXx }, 0 },
10628   },
10629   {
10630     /* VEX_W_0F5E_P_1  */
10631     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10632   },
10633   {
10634     /* VEX_W_0F5E_P_2  */
10635     { "vdivpd",         { XM, Vex, EXx }, 0 },
10636   },
10637   {
10638     /* VEX_W_0F5E_P_3  */
10639     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10640   },
10641   {
10642     /* VEX_W_0F5F_P_0  */
10643     { "vmaxps",         { XM, Vex, EXx }, 0 },
10644   },
10645   {
10646     /* VEX_W_0F5F_P_1  */
10647     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10648   },
10649   {
10650     /* VEX_W_0F5F_P_2  */
10651     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10652   },
10653   {
10654     /* VEX_W_0F5F_P_3  */
10655     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10656   },
10657   {
10658     /* VEX_W_0F60_P_2  */
10659     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10660   },
10661   {
10662     /* VEX_W_0F61_P_2  */
10663     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10664   },
10665   {
10666     /* VEX_W_0F62_P_2  */
10667     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10668   },
10669   {
10670     /* VEX_W_0F63_P_2  */
10671     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10672   },
10673   {
10674     /* VEX_W_0F64_P_2  */
10675     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10676   },
10677   {
10678     /* VEX_W_0F65_P_2  */
10679     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10680   },
10681   {
10682     /* VEX_W_0F66_P_2  */
10683     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10684   },
10685   {
10686     /* VEX_W_0F67_P_2  */
10687     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10688   },
10689   {
10690     /* VEX_W_0F68_P_2  */
10691     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10692   },
10693   {
10694     /* VEX_W_0F69_P_2  */
10695     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10696   },
10697   {
10698     /* VEX_W_0F6A_P_2  */
10699     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10700   },
10701   {
10702     /* VEX_W_0F6B_P_2  */
10703     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10704   },
10705   {
10706     /* VEX_W_0F6C_P_2  */
10707     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10708   },
10709   {
10710     /* VEX_W_0F6D_P_2  */
10711     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10712   },
10713   {
10714     /* VEX_W_0F6F_P_1  */
10715     { "vmovdqu",        { XM, EXx }, 0 },
10716   },
10717   {
10718     /* VEX_W_0F6F_P_2  */
10719     { "vmovdqa",        { XM, EXx }, 0 },
10720   },
10721   {
10722     /* VEX_W_0F70_P_1 */
10723     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10724   },
10725   {
10726     /* VEX_W_0F70_P_2 */
10727     { "vpshufd",        { XM, EXx, Ib }, 0 },
10728   },
10729   {
10730     /* VEX_W_0F70_P_3 */
10731     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10732   },
10733   {
10734     /* VEX_W_0F71_R_2_P_2  */
10735     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10736   },
10737   {
10738     /* VEX_W_0F71_R_4_P_2  */
10739     { "vpsraw",         { Vex, XS, Ib }, 0 },
10740   },
10741   {
10742     /* VEX_W_0F71_R_6_P_2  */
10743     { "vpsllw",         { Vex, XS, Ib }, 0 },
10744   },
10745   {
10746     /* VEX_W_0F72_R_2_P_2  */
10747     { "vpsrld",         { Vex, XS, Ib }, 0 },
10748   },
10749   {
10750     /* VEX_W_0F72_R_4_P_2  */
10751     { "vpsrad",         { Vex, XS, Ib }, 0 },
10752   },
10753   {
10754     /* VEX_W_0F72_R_6_P_2  */
10755     { "vpslld",         { Vex, XS, Ib }, 0 },
10756   },
10757   {
10758     /* VEX_W_0F73_R_2_P_2  */
10759     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10760   },
10761   {
10762     /* VEX_W_0F73_R_3_P_2  */
10763     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10764   },
10765   {
10766     /* VEX_W_0F73_R_6_P_2  */
10767     { "vpsllq",         { Vex, XS, Ib }, 0 },
10768   },
10769   {
10770     /* VEX_W_0F73_R_7_P_2  */
10771     { "vpslldq",        { Vex, XS, Ib }, 0 },
10772   },
10773   {
10774     /* VEX_W_0F74_P_2 */
10775     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10776   },
10777   {
10778     /* VEX_W_0F75_P_2 */
10779     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10780   },
10781   {
10782     /* VEX_W_0F76_P_2 */
10783     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10784   },
10785   {
10786     /* VEX_W_0F77_P_0 */
10787     { "",               { VZERO }, 0 },
10788   },
10789   {
10790     /* VEX_W_0F7C_P_2 */
10791     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10792   },
10793   {
10794     /* VEX_W_0F7C_P_3 */
10795     { "vhaddps",        { XM, Vex, EXx }, 0 },
10796   },
10797   {
10798     /* VEX_W_0F7D_P_2 */
10799     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10800   },
10801   {
10802     /* VEX_W_0F7D_P_3 */
10803     { "vhsubps",        { XM, Vex, EXx }, 0 },
10804   },
10805   {
10806     /* VEX_W_0F7E_P_1 */
10807     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10808   },
10809   {
10810     /* VEX_W_0F7F_P_1 */
10811     { "vmovdqu",        { EXxS, XM }, 0 },
10812   },
10813   {
10814     /* VEX_W_0F7F_P_2 */
10815     { "vmovdqa",        { EXxS, XM }, 0 },
10816   },
10817   {
10818     /* VEX_W_0F90_P_0_LEN_0 */
10819     { "kmovw",          { MaskG, MaskE }, 0 },
10820     { "kmovq",          { MaskG, MaskE }, 0 },
10821   },
10822   {
10823     /* VEX_W_0F90_P_2_LEN_0 */
10824     { "kmovb",          { MaskG, MaskBDE }, 0 },
10825     { "kmovd",          { MaskG, MaskBDE }, 0 },
10826   },
10827   {
10828     /* VEX_W_0F91_P_0_LEN_0 */
10829     { "kmovw",          { Ew, MaskG }, 0 },
10830     { "kmovq",          { Eq, MaskG }, 0 },
10831   },
10832   {
10833     /* VEX_W_0F91_P_2_LEN_0 */
10834     { "kmovb",          { Eb, MaskG }, 0 },
10835     { "kmovd",          { Ed, MaskG }, 0 },
10836   },
10837   {
10838     /* VEX_W_0F92_P_0_LEN_0 */
10839     { "kmovw",          { MaskG, Rdq }, 0 },
10840   },
10841   {
10842     /* VEX_W_0F92_P_2_LEN_0 */
10843     { "kmovb",          { MaskG, Rdq }, 0 },
10844   },
10845   {
10846     /* VEX_W_0F92_P_3_LEN_0 */
10847     { "kmovd",          { MaskG, Rdq }, 0 },
10848     { "kmovq",          { MaskG, Rdq }, 0 },
10849   },
10850   {
10851     /* VEX_W_0F93_P_0_LEN_0 */
10852     { "kmovw",          { Gdq, MaskR }, 0 },
10853   },
10854   {
10855     /* VEX_W_0F93_P_2_LEN_0 */
10856     { "kmovb",          { Gdq, MaskR }, 0 },
10857   },
10858   {
10859     /* VEX_W_0F93_P_3_LEN_0 */
10860     { "kmovd",          { Gdq, MaskR }, 0 },
10861     { "kmovq",          { Gdq, MaskR }, 0 },
10862   },
10863   {
10864     /* VEX_W_0F98_P_0_LEN_0 */
10865     { "kortestw",       { MaskG, MaskR }, 0 },
10866     { "kortestq",       { MaskG, MaskR }, 0 },
10867   },
10868   {
10869     /* VEX_W_0F98_P_2_LEN_0 */
10870     { "kortestb",       { MaskG, MaskR }, 0 },
10871     { "kortestd",       { MaskG, MaskR }, 0 },
10872   },
10873   {
10874     /* VEX_W_0F99_P_0_LEN_0 */
10875     { "ktestw", { MaskG, MaskR }, 0 },
10876     { "ktestq", { MaskG, MaskR }, 0 },
10877   },
10878   {
10879     /* VEX_W_0F99_P_2_LEN_0 */
10880     { "ktestb", { MaskG, MaskR }, 0 },
10881     { "ktestd", { MaskG, MaskR }, 0 },
10882   },
10883   {
10884     /* VEX_W_0FAE_R_2_M_0 */
10885     { "vldmxcsr",       { Md }, 0 },
10886   },
10887   {
10888     /* VEX_W_0FAE_R_3_M_0 */
10889     { "vstmxcsr",       { Md }, 0 },
10890   },
10891   {
10892     /* VEX_W_0FC2_P_0 */
10893     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10894   },
10895   {
10896     /* VEX_W_0FC2_P_1 */
10897     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10898   },
10899   {
10900     /* VEX_W_0FC2_P_2 */
10901     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10902   },
10903   {
10904     /* VEX_W_0FC2_P_3 */
10905     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10906   },
10907   {
10908     /* VEX_W_0FC4_P_2 */
10909     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10910   },
10911   {
10912     /* VEX_W_0FC5_P_2 */
10913     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10914   },
10915   {
10916     /* VEX_W_0FD0_P_2 */
10917     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10918   },
10919   {
10920     /* VEX_W_0FD0_P_3 */
10921     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10922   },
10923   {
10924     /* VEX_W_0FD1_P_2 */
10925     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10926   },
10927   {
10928     /* VEX_W_0FD2_P_2 */
10929     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10930   },
10931   {
10932     /* VEX_W_0FD3_P_2 */
10933     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10934   },
10935   {
10936     /* VEX_W_0FD4_P_2 */
10937     { "vpaddq",         { XM, Vex, EXx }, 0 },
10938   },
10939   {
10940     /* VEX_W_0FD5_P_2 */
10941     { "vpmullw",        { XM, Vex, EXx }, 0 },
10942   },
10943   {
10944     /* VEX_W_0FD6_P_2 */
10945     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10946   },
10947   {
10948     /* VEX_W_0FD7_P_2_M_1 */
10949     { "vpmovmskb",      { Gdq, XS }, 0 },
10950   },
10951   {
10952     /* VEX_W_0FD8_P_2 */
10953     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10954   },
10955   {
10956     /* VEX_W_0FD9_P_2 */
10957     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10958   },
10959   {
10960     /* VEX_W_0FDA_P_2 */
10961     { "vpminub",        { XM, Vex, EXx }, 0 },
10962   },
10963   {
10964     /* VEX_W_0FDB_P_2 */
10965     { "vpand",          { XM, Vex, EXx }, 0 },
10966   },
10967   {
10968     /* VEX_W_0FDC_P_2 */
10969     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10970   },
10971   {
10972     /* VEX_W_0FDD_P_2 */
10973     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10974   },
10975   {
10976     /* VEX_W_0FDE_P_2 */
10977     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10978   },
10979   {
10980     /* VEX_W_0FDF_P_2 */
10981     { "vpandn",         { XM, Vex, EXx }, 0 },
10982   },
10983   {
10984     /* VEX_W_0FE0_P_2  */
10985     { "vpavgb",         { XM, Vex, EXx }, 0 },
10986   },
10987   {
10988     /* VEX_W_0FE1_P_2  */
10989     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10990   },
10991   {
10992     /* VEX_W_0FE2_P_2  */
10993     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10994   },
10995   {
10996     /* VEX_W_0FE3_P_2  */
10997     { "vpavgw",         { XM, Vex, EXx }, 0 },
10998   },
10999   {
11000     /* VEX_W_0FE4_P_2  */
11001     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11002   },
11003   {
11004     /* VEX_W_0FE5_P_2  */
11005     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11006   },
11007   {
11008     /* VEX_W_0FE6_P_1  */
11009     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11010   },
11011   {
11012     /* VEX_W_0FE6_P_2  */
11013     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11014   },
11015   {
11016     /* VEX_W_0FE6_P_3  */
11017     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11018   },
11019   {
11020     /* VEX_W_0FE7_P_2_M_0 */
11021     { "vmovntdq",       { Mx, XM }, 0 },
11022   },
11023   {
11024     /* VEX_W_0FE8_P_2  */
11025     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11026   },
11027   {
11028     /* VEX_W_0FE9_P_2  */
11029     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11030   },
11031   {
11032     /* VEX_W_0FEA_P_2  */
11033     { "vpminsw",        { XM, Vex, EXx }, 0 },
11034   },
11035   {
11036     /* VEX_W_0FEB_P_2  */
11037     { "vpor",           { XM, Vex, EXx }, 0 },
11038   },
11039   {
11040     /* VEX_W_0FEC_P_2  */
11041     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11042   },
11043   {
11044     /* VEX_W_0FED_P_2  */
11045     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11046   },
11047   {
11048     /* VEX_W_0FEE_P_2  */
11049     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11050   },
11051   {
11052     /* VEX_W_0FEF_P_2  */
11053     { "vpxor",          { XM, Vex, EXx }, 0 },
11054   },
11055   {
11056     /* VEX_W_0FF0_P_3_M_0 */
11057     { "vlddqu",         { XM, M }, 0 },
11058   },
11059   {
11060     /* VEX_W_0FF1_P_2 */
11061     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11062   },
11063   {
11064     /* VEX_W_0FF2_P_2 */
11065     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11066   },
11067   {
11068     /* VEX_W_0FF3_P_2 */
11069     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11070   },
11071   {
11072     /* VEX_W_0FF4_P_2 */
11073     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11074   },
11075   {
11076     /* VEX_W_0FF5_P_2 */
11077     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11078   },
11079   {
11080     /* VEX_W_0FF6_P_2 */
11081     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11082   },
11083   {
11084     /* VEX_W_0FF7_P_2 */
11085     { "vmaskmovdqu",    { XM, XS }, 0 },
11086   },
11087   {
11088     /* VEX_W_0FF8_P_2 */
11089     { "vpsubb",         { XM, Vex, EXx }, 0 },
11090   },
11091   {
11092     /* VEX_W_0FF9_P_2 */
11093     { "vpsubw",         { XM, Vex, EXx }, 0 },
11094   },
11095   {
11096     /* VEX_W_0FFA_P_2 */
11097     { "vpsubd",         { XM, Vex, EXx }, 0 },
11098   },
11099   {
11100     /* VEX_W_0FFB_P_2 */
11101     { "vpsubq",         { XM, Vex, EXx }, 0 },
11102   },
11103   {
11104     /* VEX_W_0FFC_P_2 */
11105     { "vpaddb",         { XM, Vex, EXx }, 0 },
11106   },
11107   {
11108     /* VEX_W_0FFD_P_2 */
11109     { "vpaddw",         { XM, Vex, EXx }, 0 },
11110   },
11111   {
11112     /* VEX_W_0FFE_P_2 */
11113     { "vpaddd",         { XM, Vex, EXx }, 0 },
11114   },
11115   {
11116     /* VEX_W_0F3800_P_2  */
11117     { "vpshufb",        { XM, Vex, EXx }, 0 },
11118   },
11119   {
11120     /* VEX_W_0F3801_P_2  */
11121     { "vphaddw",        { XM, Vex, EXx }, 0 },
11122   },
11123   {
11124     /* VEX_W_0F3802_P_2  */
11125     { "vphaddd",        { XM, Vex, EXx }, 0 },
11126   },
11127   {
11128     /* VEX_W_0F3803_P_2  */
11129     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11130   },
11131   {
11132     /* VEX_W_0F3804_P_2  */
11133     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11134   },
11135   {
11136     /* VEX_W_0F3805_P_2  */
11137     { "vphsubw",        { XM, Vex, EXx }, 0 },
11138   },
11139   {
11140     /* VEX_W_0F3806_P_2  */
11141     { "vphsubd",        { XM, Vex, EXx }, 0 },
11142   },
11143   {
11144     /* VEX_W_0F3807_P_2  */
11145     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11146   },
11147   {
11148     /* VEX_W_0F3808_P_2  */
11149     { "vpsignb",        { XM, Vex, EXx }, 0 },
11150   },
11151   {
11152     /* VEX_W_0F3809_P_2  */
11153     { "vpsignw",        { XM, Vex, EXx }, 0 },
11154   },
11155   {
11156     /* VEX_W_0F380A_P_2  */
11157     { "vpsignd",        { XM, Vex, EXx }, 0 },
11158   },
11159   {
11160     /* VEX_W_0F380B_P_2  */
11161     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11162   },
11163   {
11164     /* VEX_W_0F380C_P_2  */
11165     { "vpermilps",      { XM, Vex, EXx }, 0 },
11166   },
11167   {
11168     /* VEX_W_0F380D_P_2  */
11169     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11170   },
11171   {
11172     /* VEX_W_0F380E_P_2  */
11173     { "vtestps",        { XM, EXx }, 0 },
11174   },
11175   {
11176     /* VEX_W_0F380F_P_2  */
11177     { "vtestpd",        { XM, EXx }, 0 },
11178   },
11179   {
11180     /* VEX_W_0F3816_P_2  */
11181     { "vpermps",        { XM, Vex, EXx }, 0 },
11182   },
11183   {
11184     /* VEX_W_0F3817_P_2 */
11185     { "vptest",         { XM, EXx }, 0 },
11186   },
11187   {
11188     /* VEX_W_0F3818_P_2 */
11189     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11190   },
11191   {
11192     /* VEX_W_0F3819_P_2 */
11193     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11194   },
11195   {
11196     /* VEX_W_0F381A_P_2_M_0 */
11197     { "vbroadcastf128", { XM, Mxmm }, 0 },
11198   },
11199   {
11200     /* VEX_W_0F381C_P_2 */
11201     { "vpabsb",         { XM, EXx }, 0 },
11202   },
11203   {
11204     /* VEX_W_0F381D_P_2 */
11205     { "vpabsw",         { XM, EXx }, 0 },
11206   },
11207   {
11208     /* VEX_W_0F381E_P_2 */
11209     { "vpabsd",         { XM, EXx }, 0 },
11210   },
11211   {
11212     /* VEX_W_0F3820_P_2 */
11213     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11214   },
11215   {
11216     /* VEX_W_0F3821_P_2 */
11217     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11218   },
11219   {
11220     /* VEX_W_0F3822_P_2 */
11221     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11222   },
11223   {
11224     /* VEX_W_0F3823_P_2 */
11225     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11226   },
11227   {
11228     /* VEX_W_0F3824_P_2 */
11229     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11230   },
11231   {
11232     /* VEX_W_0F3825_P_2 */
11233     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11234   },
11235   {
11236     /* VEX_W_0F3828_P_2 */
11237     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11238   },
11239   {
11240     /* VEX_W_0F3829_P_2 */
11241     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11242   },
11243   {
11244     /* VEX_W_0F382A_P_2_M_0 */
11245     { "vmovntdqa",      { XM, Mx }, 0 },
11246   },
11247   {
11248     /* VEX_W_0F382B_P_2 */
11249     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11250   },
11251   {
11252     /* VEX_W_0F382C_P_2_M_0 */
11253     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11254   },
11255   {
11256     /* VEX_W_0F382D_P_2_M_0 */
11257     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11258   },
11259   {
11260     /* VEX_W_0F382E_P_2_M_0 */
11261     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11262   },
11263   {
11264     /* VEX_W_0F382F_P_2_M_0 */
11265     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11266   },
11267   {
11268     /* VEX_W_0F3830_P_2 */
11269     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11270   },
11271   {
11272     /* VEX_W_0F3831_P_2 */
11273     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11274   },
11275   {
11276     /* VEX_W_0F3832_P_2 */
11277     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11278   },
11279   {
11280     /* VEX_W_0F3833_P_2 */
11281     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11282   },
11283   {
11284     /* VEX_W_0F3834_P_2 */
11285     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11286   },
11287   {
11288     /* VEX_W_0F3835_P_2 */
11289     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11290   },
11291   {
11292     /* VEX_W_0F3836_P_2  */
11293     { "vpermd",         { XM, Vex, EXx }, 0 },
11294   },
11295   {
11296     /* VEX_W_0F3837_P_2 */
11297     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11298   },
11299   {
11300     /* VEX_W_0F3838_P_2 */
11301     { "vpminsb",        { XM, Vex, EXx }, 0 },
11302   },
11303   {
11304     /* VEX_W_0F3839_P_2 */
11305     { "vpminsd",        { XM, Vex, EXx }, 0 },
11306   },
11307   {
11308     /* VEX_W_0F383A_P_2 */
11309     { "vpminuw",        { XM, Vex, EXx }, 0 },
11310   },
11311   {
11312     /* VEX_W_0F383B_P_2 */
11313     { "vpminud",        { XM, Vex, EXx }, 0 },
11314   },
11315   {
11316     /* VEX_W_0F383C_P_2 */
11317     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11318   },
11319   {
11320     /* VEX_W_0F383D_P_2 */
11321     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11322   },
11323   {
11324     /* VEX_W_0F383E_P_2 */
11325     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11326   },
11327   {
11328     /* VEX_W_0F383F_P_2 */
11329     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F3840_P_2 */
11333     { "vpmulld",        { XM, Vex, EXx }, 0 },
11334   },
11335   {
11336     /* VEX_W_0F3841_P_2 */
11337     { "vphminposuw",    { XM, EXx }, 0 },
11338   },
11339   {
11340     /* VEX_W_0F3846_P_2 */
11341     { "vpsravd",        { XM, Vex, EXx }, 0 },
11342   },
11343   {
11344     /* VEX_W_0F3858_P_2 */
11345     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11346   },
11347   {
11348     /* VEX_W_0F3859_P_2 */
11349     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11350   },
11351   {
11352     /* VEX_W_0F385A_P_2_M_0 */
11353     { "vbroadcasti128", { XM, Mxmm }, 0 },
11354   },
11355   {
11356     /* VEX_W_0F3878_P_2 */
11357     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11358   },
11359   {
11360     /* VEX_W_0F3879_P_2 */
11361     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11362   },
11363   {
11364     /* VEX_W_0F38DB_P_2 */
11365     { "vaesimc",        { XM, EXx }, 0 },
11366   },
11367   {
11368     /* VEX_W_0F38DC_P_2 */
11369     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11370   },
11371   {
11372     /* VEX_W_0F38DD_P_2 */
11373     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11374   },
11375   {
11376     /* VEX_W_0F38DE_P_2 */
11377     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11378   },
11379   {
11380     /* VEX_W_0F38DF_P_2 */
11381     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11382   },
11383   {
11384     /* VEX_W_0F3A00_P_2 */
11385     { Bad_Opcode },
11386     { "vpermq",         { XM, EXx, Ib }, 0 },
11387   },
11388   {
11389     /* VEX_W_0F3A01_P_2 */
11390     { Bad_Opcode },
11391     { "vpermpd",        { XM, EXx, Ib }, 0 },
11392   },
11393   {
11394     /* VEX_W_0F3A02_P_2 */
11395     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11396   },
11397   {
11398     /* VEX_W_0F3A04_P_2 */
11399     { "vpermilps",      { XM, EXx, Ib }, 0 },
11400   },
11401   {
11402     /* VEX_W_0F3A05_P_2 */
11403     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11404   },
11405   {
11406     /* VEX_W_0F3A06_P_2 */
11407     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11408   },
11409   {
11410     /* VEX_W_0F3A08_P_2 */
11411     { "vroundps",       { XM, EXx, Ib }, 0 },
11412   },
11413   {
11414     /* VEX_W_0F3A09_P_2 */
11415     { "vroundpd",       { XM, EXx, Ib }, 0 },
11416   },
11417   {
11418     /* VEX_W_0F3A0A_P_2 */
11419     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11420   },
11421   {
11422     /* VEX_W_0F3A0B_P_2 */
11423     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11424   },
11425   {
11426     /* VEX_W_0F3A0C_P_2 */
11427     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11428   },
11429   {
11430     /* VEX_W_0F3A0D_P_2 */
11431     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11432   },
11433   {
11434     /* VEX_W_0F3A0E_P_2 */
11435     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11436   },
11437   {
11438     /* VEX_W_0F3A0F_P_2 */
11439     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11440   },
11441   {
11442     /* VEX_W_0F3A14_P_2 */
11443     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11444   },
11445   {
11446     /* VEX_W_0F3A15_P_2 */
11447     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11448   },
11449   {
11450     /* VEX_W_0F3A18_P_2 */
11451     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11452   },
11453   {
11454     /* VEX_W_0F3A19_P_2 */
11455     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11456   },
11457   {
11458     /* VEX_W_0F3A20_P_2 */
11459     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11460   },
11461   {
11462     /* VEX_W_0F3A21_P_2 */
11463     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11464   },
11465   {
11466     /* VEX_W_0F3A30_P_2_LEN_0 */
11467     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11468     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11469   },
11470   {
11471     /* VEX_W_0F3A31_P_2_LEN_0 */
11472     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11473     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11474   },
11475   {
11476     /* VEX_W_0F3A32_P_2_LEN_0 */
11477     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11478     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11479   },
11480   {
11481     /* VEX_W_0F3A33_P_2_LEN_0 */
11482     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11483     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11484   },
11485   {
11486     /* VEX_W_0F3A38_P_2 */
11487     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11488   },
11489   {
11490     /* VEX_W_0F3A39_P_2 */
11491     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11492   },
11493   {
11494     /* VEX_W_0F3A40_P_2 */
11495     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11496   },
11497   {
11498     /* VEX_W_0F3A41_P_2 */
11499     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11500   },
11501   {
11502     /* VEX_W_0F3A42_P_2 */
11503     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11504   },
11505   {
11506     /* VEX_W_0F3A44_P_2 */
11507     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11508   },
11509   {
11510     /* VEX_W_0F3A46_P_2 */
11511     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11512   },
11513   {
11514     /* VEX_W_0F3A48_P_2 */
11515     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11516     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11517   },
11518   {
11519     /* VEX_W_0F3A49_P_2 */
11520     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11521     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11522   },
11523   {
11524     /* VEX_W_0F3A4A_P_2 */
11525     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11526   },
11527   {
11528     /* VEX_W_0F3A4B_P_2 */
11529     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11530   },
11531   {
11532     /* VEX_W_0F3A4C_P_2 */
11533     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11534   },
11535   {
11536     /* VEX_W_0F3A60_P_2 */
11537     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11538   },
11539   {
11540     /* VEX_W_0F3A61_P_2 */
11541     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11542   },
11543   {
11544     /* VEX_W_0F3A62_P_2 */
11545     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11546   },
11547   {
11548     /* VEX_W_0F3A63_P_2 */
11549     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11550   },
11551   {
11552     /* VEX_W_0F3ADF_P_2 */
11553     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11554   },
11555 #define NEED_VEX_W_TABLE
11556 #include "i386-dis-evex.h"
11557 #undef NEED_VEX_W_TABLE
11558 };
11559
11560 static const struct dis386 mod_table[][2] = {
11561   {
11562     /* MOD_8D */
11563     { "leaS",           { Gv, M }, 0 },
11564   },
11565   {
11566     /* MOD_C6_REG_7 */
11567     { Bad_Opcode },
11568     { RM_TABLE (RM_C6_REG_7) },
11569   },
11570   {
11571     /* MOD_C7_REG_7 */
11572     { Bad_Opcode },
11573     { RM_TABLE (RM_C7_REG_7) },
11574   },
11575   {
11576     /* MOD_FF_REG_3 */
11577     { "Jcall{T|}", { indirEp }, 0 },
11578   },
11579   {
11580     /* MOD_FF_REG_5 */
11581     { "Jjmp{T|}", { indirEp }, 0 },
11582   },
11583   {
11584     /* MOD_0F01_REG_0 */
11585     { X86_64_TABLE (X86_64_0F01_REG_0) },
11586     { RM_TABLE (RM_0F01_REG_0) },
11587   },
11588   {
11589     /* MOD_0F01_REG_1 */
11590     { X86_64_TABLE (X86_64_0F01_REG_1) },
11591     { RM_TABLE (RM_0F01_REG_1) },
11592   },
11593   {
11594     /* MOD_0F01_REG_2 */
11595     { X86_64_TABLE (X86_64_0F01_REG_2) },
11596     { RM_TABLE (RM_0F01_REG_2) },
11597   },
11598   {
11599     /* MOD_0F01_REG_3 */
11600     { X86_64_TABLE (X86_64_0F01_REG_3) },
11601     { RM_TABLE (RM_0F01_REG_3) },
11602   },
11603   {
11604     /* MOD_0F01_REG_7 */
11605     { "invlpg",         { Mb }, 0 },
11606     { RM_TABLE (RM_0F01_REG_7) },
11607   },
11608   {
11609     /* MOD_0F12_PREFIX_0 */
11610     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11611     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11612   },
11613   {
11614     /* MOD_0F13 */
11615     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11616   },
11617   {
11618     /* MOD_0F16_PREFIX_0 */
11619     { "movhps",         { XM, EXq }, 0 },
11620     { "movlhps",        { XM, EXq }, 0 },
11621   },
11622   {
11623     /* MOD_0F17 */
11624     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11625   },
11626   {
11627     /* MOD_0F18_REG_0 */
11628     { "prefetchnta",    { Mb }, 0 },
11629   },
11630   {
11631     /* MOD_0F18_REG_1 */
11632     { "prefetcht0",     { Mb }, 0 },
11633   },
11634   {
11635     /* MOD_0F18_REG_2 */
11636     { "prefetcht1",     { Mb }, 0 },
11637   },
11638   {
11639     /* MOD_0F18_REG_3 */
11640     { "prefetcht2",     { Mb }, 0 },
11641   },
11642   {
11643     /* MOD_0F18_REG_4 */
11644     { "nop/reserved",   { Mb }, 0 },
11645   },
11646   {
11647     /* MOD_0F18_REG_5 */
11648     { "nop/reserved",   { Mb }, 0 },
11649   },
11650   {
11651     /* MOD_0F18_REG_6 */
11652     { "nop/reserved",   { Mb }, 0 },
11653   },
11654   {
11655     /* MOD_0F18_REG_7 */
11656     { "nop/reserved",   { Mb }, 0 },
11657   },
11658   {
11659     /* MOD_0F1A_PREFIX_0 */
11660     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11661     { "nopQ",           { Ev }, 0 },
11662   },
11663   {
11664     /* MOD_0F1B_PREFIX_0 */
11665     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11666     { "nopQ",           { Ev }, 0 },
11667   },
11668   {
11669     /* MOD_0F1B_PREFIX_1 */
11670     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11671     { "nopQ",           { Ev }, 0 },
11672   },
11673   {
11674     /* MOD_0F24 */
11675     { Bad_Opcode },
11676     { "movL",           { Rd, Td }, 0 },
11677   },
11678   {
11679     /* MOD_0F26 */
11680     { Bad_Opcode },
11681     { "movL",           { Td, Rd }, 0 },
11682   },
11683   {
11684     /* MOD_0F2B_PREFIX_0 */
11685     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11686   },
11687   {
11688     /* MOD_0F2B_PREFIX_1 */
11689     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11690   },
11691   {
11692     /* MOD_0F2B_PREFIX_2 */
11693     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11694   },
11695   {
11696     /* MOD_0F2B_PREFIX_3 */
11697     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11698   },
11699   {
11700     /* MOD_0F51 */
11701     { Bad_Opcode },
11702     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11703   },
11704   {
11705     /* MOD_0F71_REG_2 */
11706     { Bad_Opcode },
11707     { "psrlw",          { MS, Ib }, 0 },
11708   },
11709   {
11710     /* MOD_0F71_REG_4 */
11711     { Bad_Opcode },
11712     { "psraw",          { MS, Ib }, 0 },
11713   },
11714   {
11715     /* MOD_0F71_REG_6 */
11716     { Bad_Opcode },
11717     { "psllw",          { MS, Ib }, 0 },
11718   },
11719   {
11720     /* MOD_0F72_REG_2 */
11721     { Bad_Opcode },
11722     { "psrld",          { MS, Ib }, 0 },
11723   },
11724   {
11725     /* MOD_0F72_REG_4 */
11726     { Bad_Opcode },
11727     { "psrad",          { MS, Ib }, 0 },
11728   },
11729   {
11730     /* MOD_0F72_REG_6 */
11731     { Bad_Opcode },
11732     { "pslld",          { MS, Ib }, 0 },
11733   },
11734   {
11735     /* MOD_0F73_REG_2 */
11736     { Bad_Opcode },
11737     { "psrlq",          { MS, Ib }, 0 },
11738   },
11739   {
11740     /* MOD_0F73_REG_3 */
11741     { Bad_Opcode },
11742     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11743   },
11744   {
11745     /* MOD_0F73_REG_6 */
11746     { Bad_Opcode },
11747     { "psllq",          { MS, Ib }, 0 },
11748   },
11749   {
11750     /* MOD_0F73_REG_7 */
11751     { Bad_Opcode },
11752     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11753   },
11754   {
11755     /* MOD_0FAE_REG_0 */
11756     { "fxsave",         { FXSAVE }, 0 },
11757     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11758   },
11759   {
11760     /* MOD_0FAE_REG_1 */
11761     { "fxrstor",        { FXSAVE }, 0 },
11762     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11763   },
11764   {
11765     /* MOD_0FAE_REG_2 */
11766     { "ldmxcsr",        { Md }, 0 },
11767     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11768   },
11769   {
11770     /* MOD_0FAE_REG_3 */
11771     { "stmxcsr",        { Md }, 0 },
11772     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11773   },
11774   {
11775     /* MOD_0FAE_REG_4 */
11776     { "xsave",          { FXSAVE }, 0 },
11777   },
11778   {
11779     /* MOD_0FAE_REG_5 */
11780     { "xrstor",         { FXSAVE }, 0 },
11781     { RM_TABLE (RM_0FAE_REG_5) },
11782   },
11783   {
11784     /* MOD_0FAE_REG_6 */
11785     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11786     { RM_TABLE (RM_0FAE_REG_6) },
11787   },
11788   {
11789     /* MOD_0FAE_REG_7 */
11790     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11791     { RM_TABLE (RM_0FAE_REG_7) },
11792   },
11793   {
11794     /* MOD_0FB2 */
11795     { "lssS",           { Gv, Mp }, 0 },
11796   },
11797   {
11798     /* MOD_0FB4 */
11799     { "lfsS",           { Gv, Mp }, 0 },
11800   },
11801   {
11802     /* MOD_0FB5 */
11803     { "lgsS",           { Gv, Mp }, 0 },
11804   },
11805   {
11806     /* MOD_0FC7_REG_3 */
11807     { "xrstors",                { FXSAVE }, 0 },
11808   },
11809   {
11810     /* MOD_0FC7_REG_4 */
11811     { "xsavec",         { FXSAVE }, 0 },
11812   },
11813   {
11814     /* MOD_0FC7_REG_5 */
11815     { "xsaves",         { FXSAVE }, 0 },
11816   },
11817   {
11818     /* MOD_0FC7_REG_6 */
11819     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11820     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11821   },
11822   {
11823     /* MOD_0FC7_REG_7 */
11824     { "vmptrst",        { Mq }, 0 },
11825     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11826   },
11827   {
11828     /* MOD_0FD7 */
11829     { Bad_Opcode },
11830     { "pmovmskb",       { Gdq, MS }, 0 },
11831   },
11832   {
11833     /* MOD_0FE7_PREFIX_2 */
11834     { "movntdq",        { Mx, XM }, 0 },
11835   },
11836   {
11837     /* MOD_0FF0_PREFIX_3 */
11838     { "lddqu",          { XM, M }, 0 },
11839   },
11840   {
11841     /* MOD_0F382A_PREFIX_2 */
11842     { "movntdqa",       { XM, Mx }, 0 },
11843   },
11844   {
11845     /* MOD_62_32BIT */
11846     { "bound{S|}",      { Gv, Ma }, 0 },
11847     { EVEX_TABLE (EVEX_0F) },
11848   },
11849   {
11850     /* MOD_C4_32BIT */
11851     { "lesS",           { Gv, Mp }, 0 },
11852     { VEX_C4_TABLE (VEX_0F) },
11853   },
11854   {
11855     /* MOD_C5_32BIT */
11856     { "ldsS",           { Gv, Mp }, 0 },
11857     { VEX_C5_TABLE (VEX_0F) },
11858   },
11859   {
11860     /* MOD_VEX_0F12_PREFIX_0 */
11861     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11862     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11863   },
11864   {
11865     /* MOD_VEX_0F13 */
11866     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11867   },
11868   {
11869     /* MOD_VEX_0F16_PREFIX_0 */
11870     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11871     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11872   },
11873   {
11874     /* MOD_VEX_0F17 */
11875     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11876   },
11877   {
11878     /* MOD_VEX_0F2B */
11879     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11880   },
11881   {
11882     /* MOD_VEX_0F50 */
11883     { Bad_Opcode },
11884     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11885   },
11886   {
11887     /* MOD_VEX_0F71_REG_2 */
11888     { Bad_Opcode },
11889     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11890   },
11891   {
11892     /* MOD_VEX_0F71_REG_4 */
11893     { Bad_Opcode },
11894     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11895   },
11896   {
11897     /* MOD_VEX_0F71_REG_6 */
11898     { Bad_Opcode },
11899     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11900   },
11901   {
11902     /* MOD_VEX_0F72_REG_2 */
11903     { Bad_Opcode },
11904     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11905   },
11906   {
11907     /* MOD_VEX_0F72_REG_4 */
11908     { Bad_Opcode },
11909     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11910   },
11911   {
11912     /* MOD_VEX_0F72_REG_6 */
11913     { Bad_Opcode },
11914     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11915   },
11916   {
11917     /* MOD_VEX_0F73_REG_2 */
11918     { Bad_Opcode },
11919     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11920   },
11921   {
11922     /* MOD_VEX_0F73_REG_3 */
11923     { Bad_Opcode },
11924     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11925   },
11926   {
11927     /* MOD_VEX_0F73_REG_6 */
11928     { Bad_Opcode },
11929     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11930   },
11931   {
11932     /* MOD_VEX_0F73_REG_7 */
11933     { Bad_Opcode },
11934     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11935   },
11936   {
11937     /* MOD_VEX_0FAE_REG_2 */
11938     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11939   },
11940   {
11941     /* MOD_VEX_0FAE_REG_3 */
11942     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11943   },
11944   {
11945     /* MOD_VEX_0FD7_PREFIX_2 */
11946     { Bad_Opcode },
11947     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11948   },
11949   {
11950     /* MOD_VEX_0FE7_PREFIX_2 */
11951     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11952   },
11953   {
11954     /* MOD_VEX_0FF0_PREFIX_3 */
11955     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11956   },
11957   {
11958     /* MOD_VEX_0F381A_PREFIX_2 */
11959     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11960   },
11961   {
11962     /* MOD_VEX_0F382A_PREFIX_2 */
11963     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11964   },
11965   {
11966     /* MOD_VEX_0F382C_PREFIX_2 */
11967     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11968   },
11969   {
11970     /* MOD_VEX_0F382D_PREFIX_2 */
11971     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11972   },
11973   {
11974     /* MOD_VEX_0F382E_PREFIX_2 */
11975     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11976   },
11977   {
11978     /* MOD_VEX_0F382F_PREFIX_2 */
11979     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11980   },
11981   {
11982     /* MOD_VEX_0F385A_PREFIX_2 */
11983     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11984   },
11985   {
11986     /* MOD_VEX_0F388C_PREFIX_2 */
11987     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_0F388E_PREFIX_2 */
11991     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11992   },
11993 #define NEED_MOD_TABLE
11994 #include "i386-dis-evex.h"
11995 #undef NEED_MOD_TABLE
11996 };
11997
11998 static const struct dis386 rm_table[][8] = {
11999   {
12000     /* RM_C6_REG_7 */
12001     { "xabort",         { Skip_MODRM, Ib }, 0 },
12002   },
12003   {
12004     /* RM_C7_REG_7 */
12005     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12006   },
12007   {
12008     /* RM_0F01_REG_0 */
12009     { Bad_Opcode },
12010     { "vmcall",         { Skip_MODRM }, 0 },
12011     { "vmlaunch",       { Skip_MODRM }, 0 },
12012     { "vmresume",       { Skip_MODRM }, 0 },
12013     { "vmxoff",         { Skip_MODRM }, 0 },
12014   },
12015   {
12016     /* RM_0F01_REG_1 */
12017     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12018     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12019     { "clac",           { Skip_MODRM }, 0 },
12020     { "stac",           { Skip_MODRM }, 0 },
12021     { Bad_Opcode },
12022     { Bad_Opcode },
12023     { Bad_Opcode },
12024     { "encls",          { Skip_MODRM }, 0 },
12025   },
12026   {
12027     /* RM_0F01_REG_2 */
12028     { "xgetbv",         { Skip_MODRM }, 0 },
12029     { "xsetbv",         { Skip_MODRM }, 0 },
12030     { Bad_Opcode },
12031     { Bad_Opcode },
12032     { "vmfunc",         { Skip_MODRM }, 0 },
12033     { "xend",           { Skip_MODRM }, 0 },
12034     { "xtest",          { Skip_MODRM }, 0 },
12035     { "enclu",          { Skip_MODRM }, 0 },
12036   },
12037   {
12038     /* RM_0F01_REG_3 */
12039     { "vmrun",          { Skip_MODRM }, 0 },
12040     { "vmmcall",        { Skip_MODRM }, 0 },
12041     { "vmload",         { Skip_MODRM }, 0 },
12042     { "vmsave",         { Skip_MODRM }, 0 },
12043     { "stgi",           { Skip_MODRM }, 0 },
12044     { "clgi",           { Skip_MODRM }, 0 },
12045     { "skinit",         { Skip_MODRM }, 0 },
12046     { "invlpga",        { Skip_MODRM }, 0 },
12047   },
12048   {
12049     /* RM_0F01_REG_7 */
12050     { "swapgs",         { Skip_MODRM }, 0  },
12051     { "rdtscp",         { Skip_MODRM }, 0  },
12052     { Bad_Opcode },
12053     { Bad_Opcode },
12054     { "clzero",         { Skip_MODRM }, 0  },
12055   },
12056   {
12057     /* RM_0FAE_REG_5 */
12058     { "lfence",         { Skip_MODRM }, 0 },
12059   },
12060   {
12061     /* RM_0FAE_REG_6 */
12062     { "mfence",         { Skip_MODRM }, 0 },
12063   },
12064   {
12065     /* RM_0FAE_REG_7 */
12066     { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12067   },
12068 };
12069
12070 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12071
12072 /* We use the high bit to indicate different name for the same
12073    prefix.  */
12074 #define REP_PREFIX      (0xf3 | 0x100)
12075 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12076 #define XRELEASE_PREFIX (0xf3 | 0x400)
12077 #define BND_PREFIX      (0xf2 | 0x400)
12078
12079 static int
12080 ckprefix (void)
12081 {
12082   int newrex, i, length;
12083   rex = 0;
12084   rex_ignored = 0;
12085   prefixes = 0;
12086   used_prefixes = 0;
12087   rex_used = 0;
12088   last_lock_prefix = -1;
12089   last_repz_prefix = -1;
12090   last_repnz_prefix = -1;
12091   last_data_prefix = -1;
12092   last_addr_prefix = -1;
12093   last_rex_prefix = -1;
12094   last_seg_prefix = -1;
12095   fwait_prefix = -1;
12096   active_seg_prefix = 0;
12097   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12098     all_prefixes[i] = 0;
12099   i = 0;
12100   length = 0;
12101   /* The maximum instruction length is 15bytes.  */
12102   while (length < MAX_CODE_LENGTH - 1)
12103     {
12104       FETCH_DATA (the_info, codep + 1);
12105       newrex = 0;
12106       switch (*codep)
12107         {
12108         /* REX prefixes family.  */
12109         case 0x40:
12110         case 0x41:
12111         case 0x42:
12112         case 0x43:
12113         case 0x44:
12114         case 0x45:
12115         case 0x46:
12116         case 0x47:
12117         case 0x48:
12118         case 0x49:
12119         case 0x4a:
12120         case 0x4b:
12121         case 0x4c:
12122         case 0x4d:
12123         case 0x4e:
12124         case 0x4f:
12125           if (address_mode == mode_64bit)
12126             newrex = *codep;
12127           else
12128             return 1;
12129           last_rex_prefix = i;
12130           break;
12131         case 0xf3:
12132           prefixes |= PREFIX_REPZ;
12133           last_repz_prefix = i;
12134           break;
12135         case 0xf2:
12136           prefixes |= PREFIX_REPNZ;
12137           last_repnz_prefix = i;
12138           break;
12139         case 0xf0:
12140           prefixes |= PREFIX_LOCK;
12141           last_lock_prefix = i;
12142           break;
12143         case 0x2e:
12144           prefixes |= PREFIX_CS;
12145           last_seg_prefix = i;
12146           active_seg_prefix = PREFIX_CS;
12147           break;
12148         case 0x36:
12149           prefixes |= PREFIX_SS;
12150           last_seg_prefix = i;
12151           active_seg_prefix = PREFIX_SS;
12152           break;
12153         case 0x3e:
12154           prefixes |= PREFIX_DS;
12155           last_seg_prefix = i;
12156           active_seg_prefix = PREFIX_DS;
12157           break;
12158         case 0x26:
12159           prefixes |= PREFIX_ES;
12160           last_seg_prefix = i;
12161           active_seg_prefix = PREFIX_ES;
12162           break;
12163         case 0x64:
12164           prefixes |= PREFIX_FS;
12165           last_seg_prefix = i;
12166           active_seg_prefix = PREFIX_FS;
12167           break;
12168         case 0x65:
12169           prefixes |= PREFIX_GS;
12170           last_seg_prefix = i;
12171           active_seg_prefix = PREFIX_GS;
12172           break;
12173         case 0x66:
12174           prefixes |= PREFIX_DATA;
12175           last_data_prefix = i;
12176           break;
12177         case 0x67:
12178           prefixes |= PREFIX_ADDR;
12179           last_addr_prefix = i;
12180           break;
12181         case FWAIT_OPCODE:
12182           /* fwait is really an instruction.  If there are prefixes
12183              before the fwait, they belong to the fwait, *not* to the
12184              following instruction.  */
12185           fwait_prefix = i;
12186           if (prefixes || rex)
12187             {
12188               prefixes |= PREFIX_FWAIT;
12189               codep++;
12190               /* This ensures that the previous REX prefixes are noticed
12191                  as unused prefixes, as in the return case below.  */
12192               rex_used = rex;
12193               return 1;
12194             }
12195           prefixes = PREFIX_FWAIT;
12196           break;
12197         default:
12198           return 1;
12199         }
12200       /* Rex is ignored when followed by another prefix.  */
12201       if (rex)
12202         {
12203           rex_used = rex;
12204           return 1;
12205         }
12206       if (*codep != FWAIT_OPCODE)
12207         all_prefixes[i++] = *codep;
12208       rex = newrex;
12209       codep++;
12210       length++;
12211     }
12212   return 0;
12213 }
12214
12215 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12216    prefix byte.  */
12217
12218 static const char *
12219 prefix_name (int pref, int sizeflag)
12220 {
12221   static const char *rexes [16] =
12222     {
12223       "rex",            /* 0x40 */
12224       "rex.B",          /* 0x41 */
12225       "rex.X",          /* 0x42 */
12226       "rex.XB",         /* 0x43 */
12227       "rex.R",          /* 0x44 */
12228       "rex.RB",         /* 0x45 */
12229       "rex.RX",         /* 0x46 */
12230       "rex.RXB",        /* 0x47 */
12231       "rex.W",          /* 0x48 */
12232       "rex.WB",         /* 0x49 */
12233       "rex.WX",         /* 0x4a */
12234       "rex.WXB",        /* 0x4b */
12235       "rex.WR",         /* 0x4c */
12236       "rex.WRB",        /* 0x4d */
12237       "rex.WRX",        /* 0x4e */
12238       "rex.WRXB",       /* 0x4f */
12239     };
12240
12241   switch (pref)
12242     {
12243     /* REX prefixes family.  */
12244     case 0x40:
12245     case 0x41:
12246     case 0x42:
12247     case 0x43:
12248     case 0x44:
12249     case 0x45:
12250     case 0x46:
12251     case 0x47:
12252     case 0x48:
12253     case 0x49:
12254     case 0x4a:
12255     case 0x4b:
12256     case 0x4c:
12257     case 0x4d:
12258     case 0x4e:
12259     case 0x4f:
12260       return rexes [pref - 0x40];
12261     case 0xf3:
12262       return "repz";
12263     case 0xf2:
12264       return "repnz";
12265     case 0xf0:
12266       return "lock";
12267     case 0x2e:
12268       return "cs";
12269     case 0x36:
12270       return "ss";
12271     case 0x3e:
12272       return "ds";
12273     case 0x26:
12274       return "es";
12275     case 0x64:
12276       return "fs";
12277     case 0x65:
12278       return "gs";
12279     case 0x66:
12280       return (sizeflag & DFLAG) ? "data16" : "data32";
12281     case 0x67:
12282       if (address_mode == mode_64bit)
12283         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12284       else
12285         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12286     case FWAIT_OPCODE:
12287       return "fwait";
12288     case REP_PREFIX:
12289       return "rep";
12290     case XACQUIRE_PREFIX:
12291       return "xacquire";
12292     case XRELEASE_PREFIX:
12293       return "xrelease";
12294     case BND_PREFIX:
12295       return "bnd";
12296     default:
12297       return NULL;
12298     }
12299 }
12300
12301 static char op_out[MAX_OPERANDS][100];
12302 static int op_ad, op_index[MAX_OPERANDS];
12303 static int two_source_ops;
12304 static bfd_vma op_address[MAX_OPERANDS];
12305 static bfd_vma op_riprel[MAX_OPERANDS];
12306 static bfd_vma start_pc;
12307
12308 /*
12309  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12310  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12311  *   section of the "Virtual 8086 Mode" chapter.)
12312  * 'pc' should be the address of this instruction, it will
12313  *   be used to print the target address if this is a relative jump or call
12314  * The function returns the length of this instruction in bytes.
12315  */
12316
12317 static char intel_syntax;
12318 static char intel_mnemonic = !SYSV386_COMPAT;
12319 static char open_char;
12320 static char close_char;
12321 static char separator_char;
12322 static char scale_char;
12323
12324 /* Here for backwards compatibility.  When gdb stops using
12325    print_insn_i386_att and print_insn_i386_intel these functions can
12326    disappear, and print_insn_i386 be merged into print_insn.  */
12327 int
12328 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12329 {
12330   intel_syntax = 0;
12331
12332   return print_insn (pc, info);
12333 }
12334
12335 int
12336 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12337 {
12338   intel_syntax = 1;
12339
12340   return print_insn (pc, info);
12341 }
12342
12343 int
12344 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12345 {
12346   intel_syntax = -1;
12347
12348   return print_insn (pc, info);
12349 }
12350
12351 void
12352 print_i386_disassembler_options (FILE *stream)
12353 {
12354   fprintf (stream, _("\n\
12355 The following i386/x86-64 specific disassembler options are supported for use\n\
12356 with the -M switch (multiple options should be separated by commas):\n"));
12357
12358   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12359   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12360   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12361   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12362   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12363   fprintf (stream, _("  att-mnemonic\n"
12364                      "              Display instruction in AT&T mnemonic\n"));
12365   fprintf (stream, _("  intel-mnemonic\n"
12366                      "              Display instruction in Intel mnemonic\n"));
12367   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12368   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12369   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12370   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12371   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12372   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12373 }
12374
12375 /* Bad opcode.  */
12376 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12377
12378 /* Get a pointer to struct dis386 with a valid name.  */
12379
12380 static const struct dis386 *
12381 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12382 {
12383   int vindex, vex_table_index;
12384
12385   if (dp->name != NULL)
12386     return dp;
12387
12388   switch (dp->op[0].bytemode)
12389     {
12390     case USE_REG_TABLE:
12391       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12392       break;
12393
12394     case USE_MOD_TABLE:
12395       vindex = modrm.mod == 0x3 ? 1 : 0;
12396       dp = &mod_table[dp->op[1].bytemode][vindex];
12397       break;
12398
12399     case USE_RM_TABLE:
12400       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12401       break;
12402
12403     case USE_PREFIX_TABLE:
12404       if (need_vex)
12405         {
12406           /* The prefix in VEX is implicit.  */
12407           switch (vex.prefix)
12408             {
12409             case 0:
12410               vindex = 0;
12411               break;
12412             case REPE_PREFIX_OPCODE:
12413               vindex = 1;
12414               break;
12415             case DATA_PREFIX_OPCODE:
12416               vindex = 2;
12417               break;
12418             case REPNE_PREFIX_OPCODE:
12419               vindex = 3;
12420               break;
12421             default:
12422               abort ();
12423               break;
12424             }
12425         }
12426       else
12427         {
12428           int last_prefix = -1;
12429           int prefix = 0;
12430           vindex = 0;
12431           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12432              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12433              last one wins.  */
12434           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12435             {
12436               if (last_repz_prefix > last_repnz_prefix)
12437                 {
12438                   vindex = 1;
12439                   prefix = PREFIX_REPZ;
12440                   last_prefix = last_repz_prefix;
12441                 }
12442               else
12443                 {
12444                   vindex = 3;
12445                   prefix = PREFIX_REPNZ;
12446                   last_prefix = last_repnz_prefix;
12447                 }
12448
12449               /* Check if prefix should be ignored.  */
12450               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12451                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12452                    & prefix) != 0)
12453                 vindex = 0;
12454             }
12455
12456           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12457             {
12458               vindex = 2;
12459               prefix = PREFIX_DATA;
12460               last_prefix = last_data_prefix;
12461             }
12462
12463           if (vindex != 0)
12464             {
12465               used_prefixes |= prefix;
12466               all_prefixes[last_prefix] = 0;
12467             }
12468         }
12469       dp = &prefix_table[dp->op[1].bytemode][vindex];
12470       break;
12471
12472     case USE_X86_64_TABLE:
12473       vindex = address_mode == mode_64bit ? 1 : 0;
12474       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12475       break;
12476
12477     case USE_3BYTE_TABLE:
12478       FETCH_DATA (info, codep + 2);
12479       vindex = *codep++;
12480       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12481       end_codep = codep;
12482       modrm.mod = (*codep >> 6) & 3;
12483       modrm.reg = (*codep >> 3) & 7;
12484       modrm.rm = *codep & 7;
12485       break;
12486
12487     case USE_VEX_LEN_TABLE:
12488       if (!need_vex)
12489         abort ();
12490
12491       switch (vex.length)
12492         {
12493         case 128:
12494           vindex = 0;
12495           break;
12496         case 256:
12497           vindex = 1;
12498           break;
12499         default:
12500           abort ();
12501           break;
12502         }
12503
12504       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12505       break;
12506
12507     case USE_XOP_8F_TABLE:
12508       FETCH_DATA (info, codep + 3);
12509       /* All bits in the REX prefix are ignored.  */
12510       rex_ignored = rex;
12511       rex = ~(*codep >> 5) & 0x7;
12512
12513       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12514       switch ((*codep & 0x1f))
12515         {
12516         default:
12517           dp = &bad_opcode;
12518           return dp;
12519         case 0x8:
12520           vex_table_index = XOP_08;
12521           break;
12522         case 0x9:
12523           vex_table_index = XOP_09;
12524           break;
12525         case 0xa:
12526           vex_table_index = XOP_0A;
12527           break;
12528         }
12529       codep++;
12530       vex.w = *codep & 0x80;
12531       if (vex.w && address_mode == mode_64bit)
12532         rex |= REX_W;
12533
12534       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12535       if (address_mode != mode_64bit
12536           && vex.register_specifier > 0x7)
12537         {
12538           dp = &bad_opcode;
12539           return dp;
12540         }
12541
12542       vex.length = (*codep & 0x4) ? 256 : 128;
12543       switch ((*codep & 0x3))
12544         {
12545         case 0:
12546           vex.prefix = 0;
12547           break;
12548         case 1:
12549           vex.prefix = DATA_PREFIX_OPCODE;
12550           break;
12551         case 2:
12552           vex.prefix = REPE_PREFIX_OPCODE;
12553           break;
12554         case 3:
12555           vex.prefix = REPNE_PREFIX_OPCODE;
12556           break;
12557         }
12558       need_vex = 1;
12559       need_vex_reg = 1;
12560       codep++;
12561       vindex = *codep++;
12562       dp = &xop_table[vex_table_index][vindex];
12563
12564       end_codep = codep;
12565       FETCH_DATA (info, codep + 1);
12566       modrm.mod = (*codep >> 6) & 3;
12567       modrm.reg = (*codep >> 3) & 7;
12568       modrm.rm = *codep & 7;
12569       break;
12570
12571     case USE_VEX_C4_TABLE:
12572       /* VEX prefix.  */
12573       FETCH_DATA (info, codep + 3);
12574       /* All bits in the REX prefix are ignored.  */
12575       rex_ignored = rex;
12576       rex = ~(*codep >> 5) & 0x7;
12577       switch ((*codep & 0x1f))
12578         {
12579         default:
12580           dp = &bad_opcode;
12581           return dp;
12582         case 0x1:
12583           vex_table_index = VEX_0F;
12584           break;
12585         case 0x2:
12586           vex_table_index = VEX_0F38;
12587           break;
12588         case 0x3:
12589           vex_table_index = VEX_0F3A;
12590           break;
12591         }
12592       codep++;
12593       vex.w = *codep & 0x80;
12594       if (vex.w && address_mode == mode_64bit)
12595         rex |= REX_W;
12596
12597       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12598       if (address_mode != mode_64bit
12599           && vex.register_specifier > 0x7)
12600         {
12601           dp = &bad_opcode;
12602           return dp;
12603         }
12604
12605       vex.length = (*codep & 0x4) ? 256 : 128;
12606       switch ((*codep & 0x3))
12607         {
12608         case 0:
12609           vex.prefix = 0;
12610           break;
12611         case 1:
12612           vex.prefix = DATA_PREFIX_OPCODE;
12613           break;
12614         case 2:
12615           vex.prefix = REPE_PREFIX_OPCODE;
12616           break;
12617         case 3:
12618           vex.prefix = REPNE_PREFIX_OPCODE;
12619           break;
12620         }
12621       need_vex = 1;
12622       need_vex_reg = 1;
12623       codep++;
12624       vindex = *codep++;
12625       dp = &vex_table[vex_table_index][vindex];
12626       end_codep = codep;
12627       /* There is no MODRM byte for VEX [82|77].  */
12628       if (vindex != 0x77 && vindex != 0x82)
12629         {
12630           FETCH_DATA (info, codep + 1);
12631           modrm.mod = (*codep >> 6) & 3;
12632           modrm.reg = (*codep >> 3) & 7;
12633           modrm.rm = *codep & 7;
12634         }
12635       break;
12636
12637     case USE_VEX_C5_TABLE:
12638       /* VEX prefix.  */
12639       FETCH_DATA (info, codep + 2);
12640       /* All bits in the REX prefix are ignored.  */
12641       rex_ignored = rex;
12642       rex = (*codep & 0x80) ? 0 : REX_R;
12643
12644       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12645       if (address_mode != mode_64bit
12646           && vex.register_specifier > 0x7)
12647         {
12648           dp = &bad_opcode;
12649           return dp;
12650         }
12651
12652       vex.w = 0;
12653
12654       vex.length = (*codep & 0x4) ? 256 : 128;
12655       switch ((*codep & 0x3))
12656         {
12657         case 0:
12658           vex.prefix = 0;
12659           break;
12660         case 1:
12661           vex.prefix = DATA_PREFIX_OPCODE;
12662           break;
12663         case 2:
12664           vex.prefix = REPE_PREFIX_OPCODE;
12665           break;
12666         case 3:
12667           vex.prefix = REPNE_PREFIX_OPCODE;
12668           break;
12669         }
12670       need_vex = 1;
12671       need_vex_reg = 1;
12672       codep++;
12673       vindex = *codep++;
12674       dp = &vex_table[dp->op[1].bytemode][vindex];
12675       end_codep = codep;
12676       /* There is no MODRM byte for VEX [82|77].  */
12677       if (vindex != 0x77 && vindex != 0x82)
12678         {
12679           FETCH_DATA (info, codep + 1);
12680           modrm.mod = (*codep >> 6) & 3;
12681           modrm.reg = (*codep >> 3) & 7;
12682           modrm.rm = *codep & 7;
12683         }
12684       break;
12685
12686     case USE_VEX_W_TABLE:
12687       if (!need_vex)
12688         abort ();
12689
12690       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12691       break;
12692
12693     case USE_EVEX_TABLE:
12694       two_source_ops = 0;
12695       /* EVEX prefix.  */
12696       vex.evex = 1;
12697       FETCH_DATA (info, codep + 4);
12698       /* All bits in the REX prefix are ignored.  */
12699       rex_ignored = rex;
12700       /* The first byte after 0x62.  */
12701       rex = ~(*codep >> 5) & 0x7;
12702       vex.r = *codep & 0x10;
12703       switch ((*codep & 0xf))
12704         {
12705         default:
12706           return &bad_opcode;
12707         case 0x1:
12708           vex_table_index = EVEX_0F;
12709           break;
12710         case 0x2:
12711           vex_table_index = EVEX_0F38;
12712           break;
12713         case 0x3:
12714           vex_table_index = EVEX_0F3A;
12715           break;
12716         }
12717
12718       /* The second byte after 0x62.  */
12719       codep++;
12720       vex.w = *codep & 0x80;
12721       if (vex.w && address_mode == mode_64bit)
12722         rex |= REX_W;
12723
12724       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12725       if (address_mode != mode_64bit)
12726         {
12727           /* In 16/32-bit mode silently ignore following bits.  */
12728           rex &= ~REX_B;
12729           vex.r = 1;
12730           vex.v = 1;
12731           vex.register_specifier &= 0x7;
12732         }
12733
12734       /* The U bit.  */
12735       if (!(*codep & 0x4))
12736         return &bad_opcode;
12737
12738       switch ((*codep & 0x3))
12739         {
12740         case 0:
12741           vex.prefix = 0;
12742           break;
12743         case 1:
12744           vex.prefix = DATA_PREFIX_OPCODE;
12745           break;
12746         case 2:
12747           vex.prefix = REPE_PREFIX_OPCODE;
12748           break;
12749         case 3:
12750           vex.prefix = REPNE_PREFIX_OPCODE;
12751           break;
12752         }
12753
12754       /* The third byte after 0x62.  */
12755       codep++;
12756
12757       /* Remember the static rounding bits.  */
12758       vex.ll = (*codep >> 5) & 3;
12759       vex.b = (*codep & 0x10) != 0;
12760
12761       vex.v = *codep & 0x8;
12762       vex.mask_register_specifier = *codep & 0x7;
12763       vex.zeroing = *codep & 0x80;
12764
12765       need_vex = 1;
12766       need_vex_reg = 1;
12767       codep++;
12768       vindex = *codep++;
12769       dp = &evex_table[vex_table_index][vindex];
12770       end_codep = codep;
12771       FETCH_DATA (info, codep + 1);
12772       modrm.mod = (*codep >> 6) & 3;
12773       modrm.reg = (*codep >> 3) & 7;
12774       modrm.rm = *codep & 7;
12775
12776       /* Set vector length.  */
12777       if (modrm.mod == 3 && vex.b)
12778         vex.length = 512;
12779       else
12780         {
12781           switch (vex.ll)
12782             {
12783             case 0x0:
12784               vex.length = 128;
12785               break;
12786             case 0x1:
12787               vex.length = 256;
12788               break;
12789             case 0x2:
12790               vex.length = 512;
12791               break;
12792             default:
12793               return &bad_opcode;
12794             }
12795         }
12796       break;
12797
12798     case 0:
12799       dp = &bad_opcode;
12800       break;
12801
12802     default:
12803       abort ();
12804     }
12805
12806   if (dp->name != NULL)
12807     return dp;
12808   else
12809     return get_valid_dis386 (dp, info);
12810 }
12811
12812 static void
12813 get_sib (disassemble_info *info, int sizeflag)
12814 {
12815   /* If modrm.mod == 3, operand must be register.  */
12816   if (need_modrm
12817       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12818       && modrm.mod != 3
12819       && modrm.rm == 4)
12820     {
12821       FETCH_DATA (info, codep + 2);
12822       sib.index = (codep [1] >> 3) & 7;
12823       sib.scale = (codep [1] >> 6) & 3;
12824       sib.base = codep [1] & 7;
12825     }
12826 }
12827
12828 static int
12829 print_insn (bfd_vma pc, disassemble_info *info)
12830 {
12831   const struct dis386 *dp;
12832   int i;
12833   char *op_txt[MAX_OPERANDS];
12834   int needcomma;
12835   int sizeflag, orig_sizeflag;
12836   const char *p;
12837   struct dis_private priv;
12838   int prefix_length;
12839
12840   priv.orig_sizeflag = AFLAG | DFLAG;
12841   if ((info->mach & bfd_mach_i386_i386) != 0)
12842     address_mode = mode_32bit;
12843   else if (info->mach == bfd_mach_i386_i8086)
12844     {
12845       address_mode = mode_16bit;
12846       priv.orig_sizeflag = 0;
12847     }
12848   else
12849     address_mode = mode_64bit;
12850
12851   if (intel_syntax == (char) -1)
12852     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12853
12854   for (p = info->disassembler_options; p != NULL; )
12855     {
12856       if (CONST_STRNEQ (p, "x86-64"))
12857         {
12858           address_mode = mode_64bit;
12859           priv.orig_sizeflag = AFLAG | DFLAG;
12860         }
12861       else if (CONST_STRNEQ (p, "i386"))
12862         {
12863           address_mode = mode_32bit;
12864           priv.orig_sizeflag = AFLAG | DFLAG;
12865         }
12866       else if (CONST_STRNEQ (p, "i8086"))
12867         {
12868           address_mode = mode_16bit;
12869           priv.orig_sizeflag = 0;
12870         }
12871       else if (CONST_STRNEQ (p, "intel"))
12872         {
12873           intel_syntax = 1;
12874           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12875             intel_mnemonic = 1;
12876         }
12877       else if (CONST_STRNEQ (p, "att"))
12878         {
12879           intel_syntax = 0;
12880           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12881             intel_mnemonic = 0;
12882         }
12883       else if (CONST_STRNEQ (p, "addr"))
12884         {
12885           if (address_mode == mode_64bit)
12886             {
12887               if (p[4] == '3' && p[5] == '2')
12888                 priv.orig_sizeflag &= ~AFLAG;
12889               else if (p[4] == '6' && p[5] == '4')
12890                 priv.orig_sizeflag |= AFLAG;
12891             }
12892           else
12893             {
12894               if (p[4] == '1' && p[5] == '6')
12895                 priv.orig_sizeflag &= ~AFLAG;
12896               else if (p[4] == '3' && p[5] == '2')
12897                 priv.orig_sizeflag |= AFLAG;
12898             }
12899         }
12900       else if (CONST_STRNEQ (p, "data"))
12901         {
12902           if (p[4] == '1' && p[5] == '6')
12903             priv.orig_sizeflag &= ~DFLAG;
12904           else if (p[4] == '3' && p[5] == '2')
12905             priv.orig_sizeflag |= DFLAG;
12906         }
12907       else if (CONST_STRNEQ (p, "suffix"))
12908         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12909
12910       p = strchr (p, ',');
12911       if (p != NULL)
12912         p++;
12913     }
12914
12915   if (intel_syntax)
12916     {
12917       names64 = intel_names64;
12918       names32 = intel_names32;
12919       names16 = intel_names16;
12920       names8 = intel_names8;
12921       names8rex = intel_names8rex;
12922       names_seg = intel_names_seg;
12923       names_mm = intel_names_mm;
12924       names_bnd = intel_names_bnd;
12925       names_xmm = intel_names_xmm;
12926       names_ymm = intel_names_ymm;
12927       names_zmm = intel_names_zmm;
12928       index64 = intel_index64;
12929       index32 = intel_index32;
12930       names_mask = intel_names_mask;
12931       index16 = intel_index16;
12932       open_char = '[';
12933       close_char = ']';
12934       separator_char = '+';
12935       scale_char = '*';
12936     }
12937   else
12938     {
12939       names64 = att_names64;
12940       names32 = att_names32;
12941       names16 = att_names16;
12942       names8 = att_names8;
12943       names8rex = att_names8rex;
12944       names_seg = att_names_seg;
12945       names_mm = att_names_mm;
12946       names_bnd = att_names_bnd;
12947       names_xmm = att_names_xmm;
12948       names_ymm = att_names_ymm;
12949       names_zmm = att_names_zmm;
12950       index64 = att_index64;
12951       index32 = att_index32;
12952       names_mask = att_names_mask;
12953       index16 = att_index16;
12954       open_char = '(';
12955       close_char =  ')';
12956       separator_char = ',';
12957       scale_char = ',';
12958     }
12959
12960   /* The output looks better if we put 7 bytes on a line, since that
12961      puts most long word instructions on a single line.  Use 8 bytes
12962      for Intel L1OM.  */
12963   if ((info->mach & bfd_mach_l1om) != 0)
12964     info->bytes_per_line = 8;
12965   else
12966     info->bytes_per_line = 7;
12967
12968   info->private_data = &priv;
12969   priv.max_fetched = priv.the_buffer;
12970   priv.insn_start = pc;
12971
12972   obuf[0] = 0;
12973   for (i = 0; i < MAX_OPERANDS; ++i)
12974     {
12975       op_out[i][0] = 0;
12976       op_index[i] = -1;
12977     }
12978
12979   the_info = info;
12980   start_pc = pc;
12981   start_codep = priv.the_buffer;
12982   codep = priv.the_buffer;
12983
12984   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12985     {
12986       const char *name;
12987
12988       /* Getting here means we tried for data but didn't get it.  That
12989          means we have an incomplete instruction of some sort.  Just
12990          print the first byte as a prefix or a .byte pseudo-op.  */
12991       if (codep > priv.the_buffer)
12992         {
12993           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12994           if (name != NULL)
12995             (*info->fprintf_func) (info->stream, "%s", name);
12996           else
12997             {
12998               /* Just print the first byte as a .byte instruction.  */
12999               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13000                                      (unsigned int) priv.the_buffer[0]);
13001             }
13002
13003           return 1;
13004         }
13005
13006       return -1;
13007     }
13008
13009   obufp = obuf;
13010   sizeflag = priv.orig_sizeflag;
13011
13012   if (!ckprefix () || rex_used)
13013     {
13014       /* Too many prefixes or unused REX prefixes.  */
13015       for (i = 0;
13016            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13017            i++)
13018         (*info->fprintf_func) (info->stream, "%s%s",
13019                                i == 0 ? "" : " ",
13020                                prefix_name (all_prefixes[i], sizeflag));
13021       return i;
13022     }
13023
13024   insn_codep = codep;
13025
13026   FETCH_DATA (info, codep + 1);
13027   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13028
13029   if (((prefixes & PREFIX_FWAIT)
13030        && ((*codep < 0xd8) || (*codep > 0xdf))))
13031     {
13032       /* Handle prefixes before fwait.  */
13033       for (i = 0; i < fwait_prefix && all_prefixes[i];
13034            i++)
13035         (*info->fprintf_func) (info->stream, "%s ",
13036                                prefix_name (all_prefixes[i], sizeflag));
13037       (*info->fprintf_func) (info->stream, "fwait");
13038       return i + 1;
13039     }
13040
13041   if (*codep == 0x0f)
13042     {
13043       unsigned char threebyte;
13044       FETCH_DATA (info, codep + 2);
13045       threebyte = *++codep;
13046       dp = &dis386_twobyte[threebyte];
13047       need_modrm = twobyte_has_modrm[*codep];
13048       codep++;
13049     }
13050   else
13051     {
13052       dp = &dis386[*codep];
13053       need_modrm = onebyte_has_modrm[*codep];
13054       codep++;
13055     }
13056
13057   /* Save sizeflag for printing the extra prefixes later before updating
13058      it for mnemonic and operand processing.  The prefix names depend
13059      only on the address mode.  */
13060   orig_sizeflag = sizeflag;
13061   if (prefixes & PREFIX_ADDR)
13062     sizeflag ^= AFLAG;
13063   if ((prefixes & PREFIX_DATA))
13064     sizeflag ^= DFLAG;
13065
13066   end_codep = codep;
13067   if (need_modrm)
13068     {
13069       FETCH_DATA (info, codep + 1);
13070       modrm.mod = (*codep >> 6) & 3;
13071       modrm.reg = (*codep >> 3) & 7;
13072       modrm.rm = *codep & 7;
13073     }
13074
13075   need_vex = 0;
13076   need_vex_reg = 0;
13077   vex_w_done = 0;
13078   vex.evex = 0;
13079
13080   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13081     {
13082       get_sib (info, sizeflag);
13083       dofloat (sizeflag);
13084     }
13085   else
13086     {
13087       dp = get_valid_dis386 (dp, info);
13088       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13089         {
13090           get_sib (info, sizeflag);
13091           for (i = 0; i < MAX_OPERANDS; ++i)
13092             {
13093               obufp = op_out[i];
13094               op_ad = MAX_OPERANDS - 1 - i;
13095               if (dp->op[i].rtn)
13096                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13097               /* For EVEX instruction after the last operand masking
13098                  should be printed.  */
13099               if (i == 0 && vex.evex)
13100                 {
13101                   /* Don't print {%k0}.  */
13102                   if (vex.mask_register_specifier)
13103                     {
13104                       oappend ("{");
13105                       oappend (names_mask[vex.mask_register_specifier]);
13106                       oappend ("}");
13107                     }
13108                   if (vex.zeroing)
13109                     oappend ("{z}");
13110                 }
13111             }
13112         }
13113     }
13114
13115   /* Check if the REX prefix is used.  */
13116   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13117     all_prefixes[last_rex_prefix] = 0;
13118
13119   /* Check if the SEG prefix is used.  */
13120   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13121                    | PREFIX_FS | PREFIX_GS)) != 0
13122       && (used_prefixes & active_seg_prefix) != 0)
13123     all_prefixes[last_seg_prefix] = 0;
13124
13125   /* Check if the ADDR prefix is used.  */
13126   if ((prefixes & PREFIX_ADDR) != 0
13127       && (used_prefixes & PREFIX_ADDR) != 0)
13128     all_prefixes[last_addr_prefix] = 0;
13129
13130   /* Check if the DATA prefix is used.  */
13131   if ((prefixes & PREFIX_DATA) != 0
13132       && (used_prefixes & PREFIX_DATA) != 0)
13133     all_prefixes[last_data_prefix] = 0;
13134
13135   /* Print the extra prefixes.  */
13136   prefix_length = 0;
13137   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13138     if (all_prefixes[i])
13139       {
13140         const char *name;
13141         name = prefix_name (all_prefixes[i], orig_sizeflag);
13142         if (name == NULL)
13143           abort ();
13144         prefix_length += strlen (name) + 1;
13145         (*info->fprintf_func) (info->stream, "%s ", name);
13146       }
13147
13148   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13149      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13150      used by putop and MMX/SSE operand and may be overriden by the
13151      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13152      separately.  */
13153   if (dp->prefix_requirement == PREFIX_OPCODE
13154       && dp != &bad_opcode
13155       && (((prefixes
13156             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13157            && (used_prefixes
13158                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13159           || ((((prefixes
13160                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13161                 == PREFIX_DATA)
13162                && (used_prefixes & PREFIX_DATA) == 0))))
13163     {
13164       (*info->fprintf_func) (info->stream, "(bad)");
13165       return end_codep - priv.the_buffer;
13166     }
13167
13168   /* Check maximum code length.  */
13169   if ((codep - start_codep) > MAX_CODE_LENGTH)
13170     {
13171       (*info->fprintf_func) (info->stream, "(bad)");
13172       return MAX_CODE_LENGTH;
13173     }
13174
13175   obufp = mnemonicendp;
13176   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13177     oappend (" ");
13178   oappend (" ");
13179   (*info->fprintf_func) (info->stream, "%s", obuf);
13180
13181   /* The enter and bound instructions are printed with operands in the same
13182      order as the intel book; everything else is printed in reverse order.  */
13183   if (intel_syntax || two_source_ops)
13184     {
13185       bfd_vma riprel;
13186
13187       for (i = 0; i < MAX_OPERANDS; ++i)
13188         op_txt[i] = op_out[i];
13189
13190       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13191         {
13192           op_ad = op_index[i];
13193           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13194           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13195           riprel = op_riprel[i];
13196           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13197           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13198         }
13199     }
13200   else
13201     {
13202       for (i = 0; i < MAX_OPERANDS; ++i)
13203         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13204     }
13205
13206   needcomma = 0;
13207   for (i = 0; i < MAX_OPERANDS; ++i)
13208     if (*op_txt[i])
13209       {
13210         if (needcomma)
13211           (*info->fprintf_func) (info->stream, ",");
13212         if (op_index[i] != -1 && !op_riprel[i])
13213           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13214         else
13215           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13216         needcomma = 1;
13217       }
13218
13219   for (i = 0; i < MAX_OPERANDS; i++)
13220     if (op_index[i] != -1 && op_riprel[i])
13221       {
13222         (*info->fprintf_func) (info->stream, "        # ");
13223         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13224                                                 + op_address[op_index[i]]), info);
13225         break;
13226       }
13227   return codep - priv.the_buffer;
13228 }
13229
13230 static const char *float_mem[] = {
13231   /* d8 */
13232   "fadd{s|}",
13233   "fmul{s|}",
13234   "fcom{s|}",
13235   "fcomp{s|}",
13236   "fsub{s|}",
13237   "fsubr{s|}",
13238   "fdiv{s|}",
13239   "fdivr{s|}",
13240   /* d9 */
13241   "fld{s|}",
13242   "(bad)",
13243   "fst{s|}",
13244   "fstp{s|}",
13245   "fldenvIC",
13246   "fldcw",
13247   "fNstenvIC",
13248   "fNstcw",
13249   /* da */
13250   "fiadd{l|}",
13251   "fimul{l|}",
13252   "ficom{l|}",
13253   "ficomp{l|}",
13254   "fisub{l|}",
13255   "fisubr{l|}",
13256   "fidiv{l|}",
13257   "fidivr{l|}",
13258   /* db */
13259   "fild{l|}",
13260   "fisttp{l|}",
13261   "fist{l|}",
13262   "fistp{l|}",
13263   "(bad)",
13264   "fld{t||t|}",
13265   "(bad)",
13266   "fstp{t||t|}",
13267   /* dc */
13268   "fadd{l|}",
13269   "fmul{l|}",
13270   "fcom{l|}",
13271   "fcomp{l|}",
13272   "fsub{l|}",
13273   "fsubr{l|}",
13274   "fdiv{l|}",
13275   "fdivr{l|}",
13276   /* dd */
13277   "fld{l|}",
13278   "fisttp{ll|}",
13279   "fst{l||}",
13280   "fstp{l|}",
13281   "frstorIC",
13282   "(bad)",
13283   "fNsaveIC",
13284   "fNstsw",
13285   /* de */
13286   "fiadd",
13287   "fimul",
13288   "ficom",
13289   "ficomp",
13290   "fisub",
13291   "fisubr",
13292   "fidiv",
13293   "fidivr",
13294   /* df */
13295   "fild",
13296   "fisttp",
13297   "fist",
13298   "fistp",
13299   "fbld",
13300   "fild{ll|}",
13301   "fbstp",
13302   "fistp{ll|}",
13303 };
13304
13305 static const unsigned char float_mem_mode[] = {
13306   /* d8 */
13307   d_mode,
13308   d_mode,
13309   d_mode,
13310   d_mode,
13311   d_mode,
13312   d_mode,
13313   d_mode,
13314   d_mode,
13315   /* d9 */
13316   d_mode,
13317   0,
13318   d_mode,
13319   d_mode,
13320   0,
13321   w_mode,
13322   0,
13323   w_mode,
13324   /* da */
13325   d_mode,
13326   d_mode,
13327   d_mode,
13328   d_mode,
13329   d_mode,
13330   d_mode,
13331   d_mode,
13332   d_mode,
13333   /* db */
13334   d_mode,
13335   d_mode,
13336   d_mode,
13337   d_mode,
13338   0,
13339   t_mode,
13340   0,
13341   t_mode,
13342   /* dc */
13343   q_mode,
13344   q_mode,
13345   q_mode,
13346   q_mode,
13347   q_mode,
13348   q_mode,
13349   q_mode,
13350   q_mode,
13351   /* dd */
13352   q_mode,
13353   q_mode,
13354   q_mode,
13355   q_mode,
13356   0,
13357   0,
13358   0,
13359   w_mode,
13360   /* de */
13361   w_mode,
13362   w_mode,
13363   w_mode,
13364   w_mode,
13365   w_mode,
13366   w_mode,
13367   w_mode,
13368   w_mode,
13369   /* df */
13370   w_mode,
13371   w_mode,
13372   w_mode,
13373   w_mode,
13374   t_mode,
13375   q_mode,
13376   t_mode,
13377   q_mode
13378 };
13379
13380 #define ST { OP_ST, 0 }
13381 #define STi { OP_STi, 0 }
13382
13383 #define FGRPd9_2 NULL, { { NULL, 0 } }, 0
13384 #define FGRPd9_4 NULL, { { NULL, 1 } }, 0
13385 #define FGRPd9_5 NULL, { { NULL, 2 } }, 0
13386 #define FGRPd9_6 NULL, { { NULL, 3 } }, 0
13387 #define FGRPd9_7 NULL, { { NULL, 4 } }, 0
13388 #define FGRPda_5 NULL, { { NULL, 5 } }, 0
13389 #define FGRPdb_4 NULL, { { NULL, 6 } }, 0
13390 #define FGRPde_3 NULL, { { NULL, 7 } }, 0
13391 #define FGRPdf_4 NULL, { { NULL, 8 } }, 0
13392
13393 static const struct dis386 float_reg[][8] = {
13394   /* d8 */
13395   {
13396     { "fadd",   { ST, STi }, 0 },
13397     { "fmul",   { ST, STi }, 0 },
13398     { "fcom",   { STi }, 0 },
13399     { "fcomp",  { STi }, 0 },
13400     { "fsub",   { ST, STi }, 0 },
13401     { "fsubr",  { ST, STi }, 0 },
13402     { "fdiv",   { ST, STi }, 0 },
13403     { "fdivr",  { ST, STi }, 0 },
13404   },
13405   /* d9 */
13406   {
13407     { "fld",    { STi }, 0 },
13408     { "fxch",   { STi }, 0 },
13409     { FGRPd9_2 },
13410     { Bad_Opcode },
13411     { FGRPd9_4 },
13412     { FGRPd9_5 },
13413     { FGRPd9_6 },
13414     { FGRPd9_7 },
13415   },
13416   /* da */
13417   {
13418     { "fcmovb", { ST, STi }, 0 },
13419     { "fcmove", { ST, STi }, 0 },
13420     { "fcmovbe",{ ST, STi }, 0 },
13421     { "fcmovu", { ST, STi }, 0 },
13422     { Bad_Opcode },
13423     { FGRPda_5 },
13424     { Bad_Opcode },
13425     { Bad_Opcode },
13426   },
13427   /* db */
13428   {
13429     { "fcmovnb",{ ST, STi }, 0 },
13430     { "fcmovne",{ ST, STi }, 0 },
13431     { "fcmovnbe",{ ST, STi }, 0 },
13432     { "fcmovnu",{ ST, STi }, 0 },
13433     { FGRPdb_4 },
13434     { "fucomi", { ST, STi }, 0 },
13435     { "fcomi",  { ST, STi }, 0 },
13436     { Bad_Opcode },
13437   },
13438   /* dc */
13439   {
13440     { "fadd",   { STi, ST }, 0 },
13441     { "fmul",   { STi, ST }, 0 },
13442     { Bad_Opcode },
13443     { Bad_Opcode },
13444     { "fsub!M", { STi, ST }, 0 },
13445     { "fsubM",  { STi, ST }, 0 },
13446     { "fdiv!M", { STi, ST }, 0 },
13447     { "fdivM",  { STi, ST }, 0 },
13448   },
13449   /* dd */
13450   {
13451     { "ffree",  { STi }, 0 },
13452     { Bad_Opcode },
13453     { "fst",    { STi }, 0 },
13454     { "fstp",   { STi }, 0 },
13455     { "fucom",  { STi }, 0 },
13456     { "fucomp", { STi }, 0 },
13457     { Bad_Opcode },
13458     { Bad_Opcode },
13459   },
13460   /* de */
13461   {
13462     { "faddp",  { STi, ST }, 0 },
13463     { "fmulp",  { STi, ST }, 0 },
13464     { Bad_Opcode },
13465     { FGRPde_3 },
13466     { "fsub!Mp", { STi, ST }, 0 },
13467     { "fsubMp", { STi, ST }, 0 },
13468     { "fdiv!Mp", { STi, ST }, 0 },
13469     { "fdivMp", { STi, ST }, 0 },
13470   },
13471   /* df */
13472   {
13473     { "ffreep", { STi }, 0 },
13474     { Bad_Opcode },
13475     { Bad_Opcode },
13476     { Bad_Opcode },
13477     { FGRPdf_4 },
13478     { "fucomip", { ST, STi }, 0 },
13479     { "fcomip", { ST, STi }, 0 },
13480     { Bad_Opcode },
13481   },
13482 };
13483
13484 static char *fgrps[][8] = {
13485   /* d9_2  0 */
13486   {
13487     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13488   },
13489
13490   /* d9_4  1 */
13491   {
13492     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13493   },
13494
13495   /* d9_5  2 */
13496   {
13497     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13498   },
13499
13500   /* d9_6  3 */
13501   {
13502     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13503   },
13504
13505   /* d9_7  4 */
13506   {
13507     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13508   },
13509
13510   /* da_5  5 */
13511   {
13512     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13513   },
13514
13515   /* db_4  6 */
13516   {
13517     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13518     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13519   },
13520
13521   /* de_3  7 */
13522   {
13523     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13524   },
13525
13526   /* df_4  8 */
13527   {
13528     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13529   },
13530 };
13531
13532 static void
13533 swap_operand (void)
13534 {
13535   mnemonicendp[0] = '.';
13536   mnemonicendp[1] = 's';
13537   mnemonicendp += 2;
13538 }
13539
13540 static void
13541 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13542                int sizeflag ATTRIBUTE_UNUSED)
13543 {
13544   /* Skip mod/rm byte.  */
13545   MODRM_CHECK;
13546   codep++;
13547 }
13548
13549 static void
13550 dofloat (int sizeflag)
13551 {
13552   const struct dis386 *dp;
13553   unsigned char floatop;
13554
13555   floatop = codep[-1];
13556
13557   if (modrm.mod != 3)
13558     {
13559       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13560
13561       putop (float_mem[fp_indx], sizeflag);
13562       obufp = op_out[0];
13563       op_ad = 2;
13564       OP_E (float_mem_mode[fp_indx], sizeflag);
13565       return;
13566     }
13567   /* Skip mod/rm byte.  */
13568   MODRM_CHECK;
13569   codep++;
13570
13571   dp = &float_reg[floatop - 0xd8][modrm.reg];
13572   if (dp->name == NULL)
13573     {
13574       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13575
13576       /* Instruction fnstsw is only one with strange arg.  */
13577       if (floatop == 0xdf && codep[-1] == 0xe0)
13578         strcpy (op_out[0], names16[0]);
13579     }
13580   else
13581     {
13582       putop (dp->name, sizeflag);
13583
13584       obufp = op_out[0];
13585       op_ad = 2;
13586       if (dp->op[0].rtn)
13587         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13588
13589       obufp = op_out[1];
13590       op_ad = 1;
13591       if (dp->op[1].rtn)
13592         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13593     }
13594 }
13595
13596 /* Like oappend (below), but S is a string starting with '%'.
13597    In Intel syntax, the '%' is elided.  */
13598 static void
13599 oappend_maybe_intel (const char *s)
13600 {
13601   oappend (s + intel_syntax);
13602 }
13603
13604 static void
13605 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13606 {
13607   oappend_maybe_intel ("%st");
13608 }
13609
13610 static void
13611 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13612 {
13613   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13614   oappend_maybe_intel (scratchbuf);
13615 }
13616
13617 /* Capital letters in template are macros.  */
13618 static int
13619 putop (const char *in_template, int sizeflag)
13620 {
13621   const char *p;
13622   int alt = 0;
13623   int cond = 1;
13624   unsigned int l = 0, len = 1;
13625   char last[4];
13626
13627 #define SAVE_LAST(c)                    \
13628   if (l < len && l < sizeof (last))     \
13629     last[l++] = c;                      \
13630   else                                  \
13631     abort ();
13632
13633   for (p = in_template; *p; p++)
13634     {
13635       switch (*p)
13636         {
13637         default:
13638           *obufp++ = *p;
13639           break;
13640         case '%':
13641           len++;
13642           break;
13643         case '!':
13644           cond = 0;
13645           break;
13646         case '{':
13647           alt = 0;
13648           if (intel_syntax)
13649             {
13650               while (*++p != '|')
13651                 if (*p == '}' || *p == '\0')
13652                   abort ();
13653             }
13654           /* Fall through.  */
13655         case 'I':
13656           alt = 1;
13657           continue;
13658         case '|':
13659           while (*++p != '}')
13660             {
13661               if (*p == '\0')
13662                 abort ();
13663             }
13664           break;
13665         case '}':
13666           break;
13667         case 'A':
13668           if (intel_syntax)
13669             break;
13670           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13671             *obufp++ = 'b';
13672           break;
13673         case 'B':
13674           if (l == 0 && len == 1)
13675             {
13676 case_B:
13677               if (intel_syntax)
13678                 break;
13679               if (sizeflag & SUFFIX_ALWAYS)
13680                 *obufp++ = 'b';
13681             }
13682           else
13683             {
13684               if (l != 1
13685                   || len != 2
13686                   || last[0] != 'L')
13687                 {
13688                   SAVE_LAST (*p);
13689                   break;
13690                 }
13691
13692               if (address_mode == mode_64bit
13693                   && !(prefixes & PREFIX_ADDR))
13694                 {
13695                   *obufp++ = 'a';
13696                   *obufp++ = 'b';
13697                   *obufp++ = 's';
13698                 }
13699
13700               goto case_B;
13701             }
13702           break;
13703         case 'C':
13704           if (intel_syntax && !alt)
13705             break;
13706           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13707             {
13708               if (sizeflag & DFLAG)
13709                 *obufp++ = intel_syntax ? 'd' : 'l';
13710               else
13711                 *obufp++ = intel_syntax ? 'w' : 's';
13712               used_prefixes |= (prefixes & PREFIX_DATA);
13713             }
13714           break;
13715         case 'D':
13716           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13717             break;
13718           USED_REX (REX_W);
13719           if (modrm.mod == 3)
13720             {
13721               if (rex & REX_W)
13722                 *obufp++ = 'q';
13723               else
13724                 {
13725                   if (sizeflag & DFLAG)
13726                     *obufp++ = intel_syntax ? 'd' : 'l';
13727                   else
13728                     *obufp++ = 'w';
13729                   used_prefixes |= (prefixes & PREFIX_DATA);
13730                 }
13731             }
13732           else
13733             *obufp++ = 'w';
13734           break;
13735         case 'E':               /* For jcxz/jecxz */
13736           if (address_mode == mode_64bit)
13737             {
13738               if (sizeflag & AFLAG)
13739                 *obufp++ = 'r';
13740               else
13741                 *obufp++ = 'e';
13742             }
13743           else
13744             if (sizeflag & AFLAG)
13745               *obufp++ = 'e';
13746           used_prefixes |= (prefixes & PREFIX_ADDR);
13747           break;
13748         case 'F':
13749           if (intel_syntax)
13750             break;
13751           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13752             {
13753               if (sizeflag & AFLAG)
13754                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13755               else
13756                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13757               used_prefixes |= (prefixes & PREFIX_ADDR);
13758             }
13759           break;
13760         case 'G':
13761           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13762             break;
13763           if ((rex & REX_W) || (sizeflag & DFLAG))
13764             *obufp++ = 'l';
13765           else
13766             *obufp++ = 'w';
13767           if (!(rex & REX_W))
13768             used_prefixes |= (prefixes & PREFIX_DATA);
13769           break;
13770         case 'H':
13771           if (intel_syntax)
13772             break;
13773           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13774               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13775             {
13776               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13777               *obufp++ = ',';
13778               *obufp++ = 'p';
13779               if (prefixes & PREFIX_DS)
13780                 *obufp++ = 't';
13781               else
13782                 *obufp++ = 'n';
13783             }
13784           break;
13785         case 'J':
13786           if (intel_syntax)
13787             break;
13788           *obufp++ = 'l';
13789           break;
13790         case 'K':
13791           USED_REX (REX_W);
13792           if (rex & REX_W)
13793             *obufp++ = 'q';
13794           else
13795             *obufp++ = 'd';
13796           break;
13797         case 'Z':
13798           if (intel_syntax)
13799             break;
13800           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13801             {
13802               *obufp++ = 'q';
13803               break;
13804             }
13805           /* Fall through.  */
13806           goto case_L;
13807         case 'L':
13808           if (l != 0 || len != 1)
13809             {
13810               SAVE_LAST (*p);
13811               break;
13812             }
13813 case_L:
13814           if (intel_syntax)
13815             break;
13816           if (sizeflag & SUFFIX_ALWAYS)
13817             *obufp++ = 'l';
13818           break;
13819         case 'M':
13820           if (intel_mnemonic != cond)
13821             *obufp++ = 'r';
13822           break;
13823         case 'N':
13824           if ((prefixes & PREFIX_FWAIT) == 0)
13825             *obufp++ = 'n';
13826           else
13827             used_prefixes |= PREFIX_FWAIT;
13828           break;
13829         case 'O':
13830           USED_REX (REX_W);
13831           if (rex & REX_W)
13832             *obufp++ = 'o';
13833           else if (intel_syntax && (sizeflag & DFLAG))
13834             *obufp++ = 'q';
13835           else
13836             *obufp++ = 'd';
13837           if (!(rex & REX_W))
13838             used_prefixes |= (prefixes & PREFIX_DATA);
13839           break;
13840         case 'T':
13841           if (!intel_syntax
13842               && address_mode == mode_64bit
13843               && ((sizeflag & DFLAG) || (rex & REX_W)))
13844             {
13845               *obufp++ = 'q';
13846               break;
13847             }
13848           /* Fall through.  */
13849           goto case_P;
13850         case 'P':
13851           if (l == 0 && len == 1)
13852             {
13853 case_P:
13854               if (intel_syntax)
13855                 {
13856                   if ((rex & REX_W) == 0
13857                       && (prefixes & PREFIX_DATA))
13858                     {
13859                       if ((sizeflag & DFLAG) == 0)
13860                         *obufp++ = 'w';
13861                       used_prefixes |= (prefixes & PREFIX_DATA);
13862                     }
13863                   break;
13864                 }
13865               if ((prefixes & PREFIX_DATA)
13866                   || (rex & REX_W)
13867                   || (sizeflag & SUFFIX_ALWAYS))
13868                 {
13869                   USED_REX (REX_W);
13870                   if (rex & REX_W)
13871                     *obufp++ = 'q';
13872                   else
13873                     {
13874                       if (sizeflag & DFLAG)
13875                         *obufp++ = 'l';
13876                       else
13877                         *obufp++ = 'w';
13878                       used_prefixes |= (prefixes & PREFIX_DATA);
13879                     }
13880                 }
13881             }
13882           else
13883             {
13884               if (l != 1 || len != 2 || last[0] != 'L')
13885                 {
13886                   SAVE_LAST (*p);
13887                   break;
13888                 }
13889
13890               if ((prefixes & PREFIX_DATA)
13891                   || (rex & REX_W)
13892                   || (sizeflag & SUFFIX_ALWAYS))
13893                 {
13894                   USED_REX (REX_W);
13895                   if (rex & REX_W)
13896                     *obufp++ = 'q';
13897                   else
13898                     {
13899                       if (sizeflag & DFLAG)
13900                         *obufp++ = intel_syntax ? 'd' : 'l';
13901                       else
13902                         *obufp++ = 'w';
13903                       used_prefixes |= (prefixes & PREFIX_DATA);
13904                     }
13905                 }
13906             }
13907           break;
13908         case 'U':
13909           if (intel_syntax)
13910             break;
13911           if (address_mode == mode_64bit
13912               && ((sizeflag & DFLAG) || (rex & REX_W)))
13913             {
13914               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13915                 *obufp++ = 'q';
13916               break;
13917             }
13918           /* Fall through.  */
13919           goto case_Q;
13920         case 'Q':
13921           if (l == 0 && len == 1)
13922             {
13923 case_Q:
13924               if (intel_syntax && !alt)
13925                 break;
13926               USED_REX (REX_W);
13927               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13928                 {
13929                   if (rex & REX_W)
13930                     *obufp++ = 'q';
13931                   else
13932                     {
13933                       if (sizeflag & DFLAG)
13934                         *obufp++ = intel_syntax ? 'd' : 'l';
13935                       else
13936                         *obufp++ = 'w';
13937                       used_prefixes |= (prefixes & PREFIX_DATA);
13938                     }
13939                 }
13940             }
13941           else
13942             {
13943               if (l != 1 || len != 2 || last[0] != 'L')
13944                 {
13945                   SAVE_LAST (*p);
13946                   break;
13947                 }
13948               if (intel_syntax
13949                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13950                 break;
13951               if ((rex & REX_W))
13952                 {
13953                   USED_REX (REX_W);
13954                   *obufp++ = 'q';
13955                 }
13956               else
13957                 *obufp++ = 'l';
13958             }
13959           break;
13960         case 'R':
13961           USED_REX (REX_W);
13962           if (rex & REX_W)
13963             *obufp++ = 'q';
13964           else if (sizeflag & DFLAG)
13965             {
13966               if (intel_syntax)
13967                   *obufp++ = 'd';
13968               else
13969                   *obufp++ = 'l';
13970             }
13971           else
13972             *obufp++ = 'w';
13973           if (intel_syntax && !p[1]
13974               && ((rex & REX_W) || (sizeflag & DFLAG)))
13975             *obufp++ = 'e';
13976           if (!(rex & REX_W))
13977             used_prefixes |= (prefixes & PREFIX_DATA);
13978           break;
13979         case 'V':
13980           if (l == 0 && len == 1)
13981             {
13982               if (intel_syntax)
13983                 break;
13984               if (address_mode == mode_64bit
13985                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13986                 {
13987                   if (sizeflag & SUFFIX_ALWAYS)
13988                     *obufp++ = 'q';
13989                   break;
13990                 }
13991             }
13992           else
13993             {
13994               if (l != 1
13995                   || len != 2
13996                   || last[0] != 'L')
13997                 {
13998                   SAVE_LAST (*p);
13999                   break;
14000                 }
14001
14002               if (rex & REX_W)
14003                 {
14004                   *obufp++ = 'a';
14005                   *obufp++ = 'b';
14006                   *obufp++ = 's';
14007                 }
14008             }
14009           /* Fall through.  */
14010           goto case_S;
14011         case 'S':
14012           if (l == 0 && len == 1)
14013             {
14014 case_S:
14015               if (intel_syntax)
14016                 break;
14017               if (sizeflag & SUFFIX_ALWAYS)
14018                 {
14019                   if (rex & REX_W)
14020                     *obufp++ = 'q';
14021                   else
14022                     {
14023                       if (sizeflag & DFLAG)
14024                         *obufp++ = 'l';
14025                       else
14026                         *obufp++ = 'w';
14027                       used_prefixes |= (prefixes & PREFIX_DATA);
14028                     }
14029                 }
14030             }
14031           else
14032             {
14033               if (l != 1
14034                   || len != 2
14035                   || last[0] != 'L')
14036                 {
14037                   SAVE_LAST (*p);
14038                   break;
14039                 }
14040
14041               if (address_mode == mode_64bit
14042                   && !(prefixes & PREFIX_ADDR))
14043                 {
14044                   *obufp++ = 'a';
14045                   *obufp++ = 'b';
14046                   *obufp++ = 's';
14047                 }
14048
14049               goto case_S;
14050             }
14051           break;
14052         case 'X':
14053           if (l != 0 || len != 1)
14054             {
14055               SAVE_LAST (*p);
14056               break;
14057             }
14058           if (need_vex && vex.prefix)
14059             {
14060               if (vex.prefix == DATA_PREFIX_OPCODE)
14061                 *obufp++ = 'd';
14062               else
14063                 *obufp++ = 's';
14064             }
14065           else
14066             {
14067               if (prefixes & PREFIX_DATA)
14068                 *obufp++ = 'd';
14069               else
14070                 *obufp++ = 's';
14071               used_prefixes |= (prefixes & PREFIX_DATA);
14072             }
14073           break;
14074         case 'Y':
14075           if (l == 0 && len == 1)
14076             {
14077               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14078                 break;
14079               if (rex & REX_W)
14080                 {
14081                   USED_REX (REX_W);
14082                   *obufp++ = 'q';
14083                 }
14084               break;
14085             }
14086           else
14087             {
14088               if (l != 1 || len != 2 || last[0] != 'X')
14089                 {
14090                   SAVE_LAST (*p);
14091                   break;
14092                 }
14093               if (!need_vex)
14094                 abort ();
14095               if (intel_syntax
14096                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14097                 break;
14098               switch (vex.length)
14099                 {
14100                 case 128:
14101                   *obufp++ = 'x';
14102                   break;
14103                 case 256:
14104                   *obufp++ = 'y';
14105                   break;
14106                 default:
14107                   abort ();
14108                 }
14109             }
14110           break;
14111         case 'W':
14112           if (l == 0 && len == 1)
14113             {
14114               /* operand size flag for cwtl, cbtw */
14115               USED_REX (REX_W);
14116               if (rex & REX_W)
14117                 {
14118                   if (intel_syntax)
14119                     *obufp++ = 'd';
14120                   else
14121                     *obufp++ = 'l';
14122                 }
14123               else if (sizeflag & DFLAG)
14124                 *obufp++ = 'w';
14125               else
14126                 *obufp++ = 'b';
14127               if (!(rex & REX_W))
14128                 used_prefixes |= (prefixes & PREFIX_DATA);
14129             }
14130           else
14131             {
14132               if (l != 1
14133                   || len != 2
14134                   || (last[0] != 'X'
14135                       && last[0] != 'L'))
14136                 {
14137                   SAVE_LAST (*p);
14138                   break;
14139                 }
14140               if (!need_vex)
14141                 abort ();
14142               if (last[0] == 'X')
14143                 *obufp++ = vex.w ? 'd': 's';
14144               else
14145                 *obufp++ = vex.w ? 'q': 'd';
14146             }
14147           break;
14148         }
14149       alt = 0;
14150     }
14151   *obufp = 0;
14152   mnemonicendp = obufp;
14153   return 0;
14154 }
14155
14156 static void
14157 oappend (const char *s)
14158 {
14159   obufp = stpcpy (obufp, s);
14160 }
14161
14162 static void
14163 append_seg (void)
14164 {
14165   /* Only print the active segment register.  */
14166   if (!active_seg_prefix)
14167     return;
14168
14169   used_prefixes |= active_seg_prefix;
14170   switch (active_seg_prefix)
14171     {
14172     case PREFIX_CS:
14173       oappend_maybe_intel ("%cs:");
14174       break;
14175     case PREFIX_DS:
14176       oappend_maybe_intel ("%ds:");
14177       break;
14178     case PREFIX_SS:
14179       oappend_maybe_intel ("%ss:");
14180       break;
14181     case PREFIX_ES:
14182       oappend_maybe_intel ("%es:");
14183       break;
14184     case PREFIX_FS:
14185       oappend_maybe_intel ("%fs:");
14186       break;
14187     case PREFIX_GS:
14188       oappend_maybe_intel ("%gs:");
14189       break;
14190     default:
14191       break;
14192     }
14193 }
14194
14195 static void
14196 OP_indirE (int bytemode, int sizeflag)
14197 {
14198   if (!intel_syntax)
14199     oappend ("*");
14200   OP_E (bytemode, sizeflag);
14201 }
14202
14203 static void
14204 print_operand_value (char *buf, int hex, bfd_vma disp)
14205 {
14206   if (address_mode == mode_64bit)
14207     {
14208       if (hex)
14209         {
14210           char tmp[30];
14211           int i;
14212           buf[0] = '0';
14213           buf[1] = 'x';
14214           sprintf_vma (tmp, disp);
14215           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14216           strcpy (buf + 2, tmp + i);
14217         }
14218       else
14219         {
14220           bfd_signed_vma v = disp;
14221           char tmp[30];
14222           int i;
14223           if (v < 0)
14224             {
14225               *(buf++) = '-';
14226               v = -disp;
14227               /* Check for possible overflow on 0x8000000000000000.  */
14228               if (v < 0)
14229                 {
14230                   strcpy (buf, "9223372036854775808");
14231                   return;
14232                 }
14233             }
14234           if (!v)
14235             {
14236               strcpy (buf, "0");
14237               return;
14238             }
14239
14240           i = 0;
14241           tmp[29] = 0;
14242           while (v)
14243             {
14244               tmp[28 - i] = (v % 10) + '0';
14245               v /= 10;
14246               i++;
14247             }
14248           strcpy (buf, tmp + 29 - i);
14249         }
14250     }
14251   else
14252     {
14253       if (hex)
14254         sprintf (buf, "0x%x", (unsigned int) disp);
14255       else
14256         sprintf (buf, "%d", (int) disp);
14257     }
14258 }
14259
14260 /* Put DISP in BUF as signed hex number.  */
14261
14262 static void
14263 print_displacement (char *buf, bfd_vma disp)
14264 {
14265   bfd_signed_vma val = disp;
14266   char tmp[30];
14267   int i, j = 0;
14268
14269   if (val < 0)
14270     {
14271       buf[j++] = '-';
14272       val = -disp;
14273
14274       /* Check for possible overflow.  */
14275       if (val < 0)
14276         {
14277           switch (address_mode)
14278             {
14279             case mode_64bit:
14280               strcpy (buf + j, "0x8000000000000000");
14281               break;
14282             case mode_32bit:
14283               strcpy (buf + j, "0x80000000");
14284               break;
14285             case mode_16bit:
14286               strcpy (buf + j, "0x8000");
14287               break;
14288             }
14289           return;
14290         }
14291     }
14292
14293   buf[j++] = '0';
14294   buf[j++] = 'x';
14295
14296   sprintf_vma (tmp, (bfd_vma) val);
14297   for (i = 0; tmp[i] == '0'; i++)
14298     continue;
14299   if (tmp[i] == '\0')
14300     i--;
14301   strcpy (buf + j, tmp + i);
14302 }
14303
14304 static void
14305 intel_operand_size (int bytemode, int sizeflag)
14306 {
14307   if (vex.evex
14308       && vex.b
14309       && (bytemode == x_mode
14310           || bytemode == evex_half_bcst_xmmq_mode))
14311     {
14312       if (vex.w)
14313         oappend ("QWORD PTR ");
14314       else
14315         oappend ("DWORD PTR ");
14316       return;
14317     }
14318   switch (bytemode)
14319     {
14320     case b_mode:
14321     case b_swap_mode:
14322     case dqb_mode:
14323     case db_mode:
14324       oappend ("BYTE PTR ");
14325       break;
14326     case w_mode:
14327     case dw_mode:
14328     case dqw_mode:
14329     case dqw_swap_mode:
14330       oappend ("WORD PTR ");
14331       break;
14332     case stack_v_mode:
14333       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14334         {
14335           oappend ("QWORD PTR ");
14336           break;
14337         }
14338       /* FALLTHRU */
14339     case v_mode:
14340     case v_swap_mode:
14341     case dq_mode:
14342       USED_REX (REX_W);
14343       if (rex & REX_W)
14344         oappend ("QWORD PTR ");
14345       else
14346         {
14347           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14348             oappend ("DWORD PTR ");
14349           else
14350             oappend ("WORD PTR ");
14351           used_prefixes |= (prefixes & PREFIX_DATA);
14352         }
14353       break;
14354     case z_mode:
14355       if ((rex & REX_W) || (sizeflag & DFLAG))
14356         *obufp++ = 'D';
14357       oappend ("WORD PTR ");
14358       if (!(rex & REX_W))
14359         used_prefixes |= (prefixes & PREFIX_DATA);
14360       break;
14361     case a_mode:
14362       if (sizeflag & DFLAG)
14363         oappend ("QWORD PTR ");
14364       else
14365         oappend ("DWORD PTR ");
14366       used_prefixes |= (prefixes & PREFIX_DATA);
14367       break;
14368     case d_mode:
14369     case d_scalar_mode:
14370     case d_scalar_swap_mode:
14371     case d_swap_mode:
14372     case dqd_mode:
14373       oappend ("DWORD PTR ");
14374       break;
14375     case q_mode:
14376     case q_scalar_mode:
14377     case q_scalar_swap_mode:
14378     case q_swap_mode:
14379       oappend ("QWORD PTR ");
14380       break;
14381     case m_mode:
14382       if (address_mode == mode_64bit)
14383         oappend ("QWORD PTR ");
14384       else
14385         oappend ("DWORD PTR ");
14386       break;
14387     case f_mode:
14388       if (sizeflag & DFLAG)
14389         oappend ("FWORD PTR ");
14390       else
14391         oappend ("DWORD PTR ");
14392       used_prefixes |= (prefixes & PREFIX_DATA);
14393       break;
14394     case t_mode:
14395       oappend ("TBYTE PTR ");
14396       break;
14397     case x_mode:
14398     case x_swap_mode:
14399     case evex_x_gscat_mode:
14400     case evex_x_nobcst_mode:
14401       if (need_vex)
14402         {
14403           switch (vex.length)
14404             {
14405             case 128:
14406               oappend ("XMMWORD PTR ");
14407               break;
14408             case 256:
14409               oappend ("YMMWORD PTR ");
14410               break;
14411             case 512:
14412               oappend ("ZMMWORD PTR ");
14413               break;
14414             default:
14415               abort ();
14416             }
14417         }
14418       else
14419         oappend ("XMMWORD PTR ");
14420       break;
14421     case xmm_mode:
14422       oappend ("XMMWORD PTR ");
14423       break;
14424     case ymm_mode:
14425       oappend ("YMMWORD PTR ");
14426       break;
14427     case xmmq_mode:
14428     case evex_half_bcst_xmmq_mode:
14429       if (!need_vex)
14430         abort ();
14431
14432       switch (vex.length)
14433         {
14434         case 128:
14435           oappend ("QWORD PTR ");
14436           break;
14437         case 256:
14438           oappend ("XMMWORD PTR ");
14439           break;
14440         case 512:
14441           oappend ("YMMWORD PTR ");
14442           break;
14443         default:
14444           abort ();
14445         }
14446       break;
14447     case xmm_mb_mode:
14448       if (!need_vex)
14449         abort ();
14450
14451       switch (vex.length)
14452         {
14453         case 128:
14454         case 256:
14455         case 512:
14456           oappend ("BYTE PTR ");
14457           break;
14458         default:
14459           abort ();
14460         }
14461       break;
14462     case xmm_mw_mode:
14463       if (!need_vex)
14464         abort ();
14465
14466       switch (vex.length)
14467         {
14468         case 128:
14469         case 256:
14470         case 512:
14471           oappend ("WORD PTR ");
14472           break;
14473         default:
14474           abort ();
14475         }
14476       break;
14477     case xmm_md_mode:
14478       if (!need_vex)
14479         abort ();
14480
14481       switch (vex.length)
14482         {
14483         case 128:
14484         case 256:
14485         case 512:
14486           oappend ("DWORD PTR ");
14487           break;
14488         default:
14489           abort ();
14490         }
14491       break;
14492     case xmm_mq_mode:
14493       if (!need_vex)
14494         abort ();
14495
14496       switch (vex.length)
14497         {
14498         case 128:
14499         case 256:
14500         case 512:
14501           oappend ("QWORD PTR ");
14502           break;
14503         default:
14504           abort ();
14505         }
14506       break;
14507     case xmmdw_mode:
14508       if (!need_vex)
14509         abort ();
14510
14511       switch (vex.length)
14512         {
14513         case 128:
14514           oappend ("WORD PTR ");
14515           break;
14516         case 256:
14517           oappend ("DWORD PTR ");
14518           break;
14519         case 512:
14520           oappend ("QWORD PTR ");
14521           break;
14522         default:
14523           abort ();
14524         }
14525       break;
14526     case xmmqd_mode:
14527       if (!need_vex)
14528         abort ();
14529
14530       switch (vex.length)
14531         {
14532         case 128:
14533           oappend ("DWORD PTR ");
14534           break;
14535         case 256:
14536           oappend ("QWORD PTR ");
14537           break;
14538         case 512:
14539           oappend ("XMMWORD PTR ");
14540           break;
14541         default:
14542           abort ();
14543         }
14544       break;
14545     case ymmq_mode:
14546       if (!need_vex)
14547         abort ();
14548
14549       switch (vex.length)
14550         {
14551         case 128:
14552           oappend ("QWORD PTR ");
14553           break;
14554         case 256:
14555           oappend ("YMMWORD PTR ");
14556           break;
14557         case 512:
14558           oappend ("ZMMWORD PTR ");
14559           break;
14560         default:
14561           abort ();
14562         }
14563       break;
14564     case ymmxmm_mode:
14565       if (!need_vex)
14566         abort ();
14567
14568       switch (vex.length)
14569         {
14570         case 128:
14571         case 256:
14572           oappend ("XMMWORD PTR ");
14573           break;
14574         default:
14575           abort ();
14576         }
14577       break;
14578     case o_mode:
14579       oappend ("OWORD PTR ");
14580       break;
14581     case xmm_mdq_mode:
14582     case vex_w_dq_mode:
14583     case vex_scalar_w_dq_mode:
14584       if (!need_vex)
14585         abort ();
14586
14587       if (vex.w)
14588         oappend ("QWORD PTR ");
14589       else
14590         oappend ("DWORD PTR ");
14591       break;
14592     case vex_vsib_d_w_dq_mode:
14593     case vex_vsib_q_w_dq_mode:
14594       if (!need_vex)
14595         abort ();
14596
14597       if (!vex.evex)
14598         {
14599           if (vex.w)
14600             oappend ("QWORD PTR ");
14601           else
14602             oappend ("DWORD PTR ");
14603         }
14604       else
14605         {
14606           switch (vex.length)
14607             {
14608             case 128:
14609               oappend ("XMMWORD PTR ");
14610               break;
14611             case 256:
14612               oappend ("YMMWORD PTR ");
14613               break;
14614             case 512:
14615               oappend ("ZMMWORD PTR ");
14616               break;
14617             default:
14618               abort ();
14619             }
14620         }
14621       break;
14622     case vex_vsib_q_w_d_mode:
14623     case vex_vsib_d_w_d_mode:
14624       if (!need_vex || !vex.evex)
14625         abort ();
14626
14627       switch (vex.length)
14628         {
14629         case 128:
14630           oappend ("QWORD PTR ");
14631           break;
14632         case 256:
14633           oappend ("XMMWORD PTR ");
14634           break;
14635         case 512:
14636           oappend ("YMMWORD PTR ");
14637           break;
14638         default:
14639           abort ();
14640         }
14641
14642       break;
14643     case mask_bd_mode:
14644       if (!need_vex || vex.length != 128)
14645         abort ();
14646       if (vex.w)
14647         oappend ("DWORD PTR ");
14648       else
14649         oappend ("BYTE PTR ");
14650       break;
14651     case mask_mode:
14652       if (!need_vex)
14653         abort ();
14654       if (vex.w)
14655         oappend ("QWORD PTR ");
14656       else
14657         oappend ("WORD PTR ");
14658       break;
14659     case v_bnd_mode:
14660     default:
14661       break;
14662     }
14663 }
14664
14665 static void
14666 OP_E_register (int bytemode, int sizeflag)
14667 {
14668   int reg = modrm.rm;
14669   const char **names;
14670
14671   USED_REX (REX_B);
14672   if ((rex & REX_B))
14673     reg += 8;
14674
14675   if ((sizeflag & SUFFIX_ALWAYS)
14676       && (bytemode == b_swap_mode
14677           || bytemode == v_swap_mode
14678           || bytemode == dqw_swap_mode))
14679     swap_operand ();
14680
14681   switch (bytemode)
14682     {
14683     case b_mode:
14684     case b_swap_mode:
14685       USED_REX (0);
14686       if (rex)
14687         names = names8rex;
14688       else
14689         names = names8;
14690       break;
14691     case w_mode:
14692       names = names16;
14693       break;
14694     case d_mode:
14695     case dw_mode:
14696     case db_mode:
14697       names = names32;
14698       break;
14699     case q_mode:
14700       names = names64;
14701       break;
14702     case m_mode:
14703     case v_bnd_mode:
14704       names = address_mode == mode_64bit ? names64 : names32;
14705       break;
14706     case bnd_mode:
14707       names = names_bnd;
14708       break;
14709     case stack_v_mode:
14710       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14711         {
14712           names = names64;
14713           break;
14714         }
14715       bytemode = v_mode;
14716       /* FALLTHRU */
14717     case v_mode:
14718     case v_swap_mode:
14719     case dq_mode:
14720     case dqb_mode:
14721     case dqd_mode:
14722     case dqw_mode:
14723     case dqw_swap_mode:
14724       USED_REX (REX_W);
14725       if (rex & REX_W)
14726         names = names64;
14727       else
14728         {
14729           if ((sizeflag & DFLAG)
14730               || (bytemode != v_mode
14731                   && bytemode != v_swap_mode))
14732             names = names32;
14733           else
14734             names = names16;
14735           used_prefixes |= (prefixes & PREFIX_DATA);
14736         }
14737       break;
14738     case mask_bd_mode:
14739     case mask_mode:
14740       names = names_mask;
14741       break;
14742     case 0:
14743       return;
14744     default:
14745       oappend (INTERNAL_DISASSEMBLER_ERROR);
14746       return;
14747     }
14748   oappend (names[reg]);
14749 }
14750
14751 static void
14752 OP_E_memory (int bytemode, int sizeflag)
14753 {
14754   bfd_vma disp = 0;
14755   int add = (rex & REX_B) ? 8 : 0;
14756   int riprel = 0;
14757   int shift;
14758
14759   if (vex.evex)
14760     {
14761       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14762       if (vex.b
14763           && bytemode != x_mode
14764           && bytemode != xmmq_mode
14765           && bytemode != evex_half_bcst_xmmq_mode)
14766         {
14767           BadOp ();
14768           return;
14769         }
14770       switch (bytemode)
14771         {
14772         case dqw_mode:
14773         case dw_mode:
14774         case dqw_swap_mode:
14775           shift = 1;
14776           break;
14777         case dqb_mode:
14778         case db_mode:
14779           shift = 0;
14780           break;
14781         case vex_vsib_d_w_dq_mode:
14782         case vex_vsib_d_w_d_mode:
14783         case vex_vsib_q_w_dq_mode:
14784         case vex_vsib_q_w_d_mode:
14785         case evex_x_gscat_mode:
14786         case xmm_mdq_mode:
14787           shift = vex.w ? 3 : 2;
14788           break;
14789         case x_mode:
14790         case evex_half_bcst_xmmq_mode:
14791         case xmmq_mode:
14792           if (vex.b)
14793             {
14794               shift = vex.w ? 3 : 2;
14795               break;
14796             }
14797           /* Fall through if vex.b == 0.  */
14798         case xmmqd_mode:
14799         case xmmdw_mode:
14800         case ymmq_mode:
14801         case evex_x_nobcst_mode:
14802         case x_swap_mode:
14803           switch (vex.length)
14804             {
14805             case 128:
14806               shift = 4;
14807               break;
14808             case 256:
14809               shift = 5;
14810               break;
14811             case 512:
14812               shift = 6;
14813               break;
14814             default:
14815               abort ();
14816             }
14817           break;
14818         case ymm_mode:
14819           shift = 5;
14820           break;
14821         case xmm_mode:
14822           shift = 4;
14823           break;
14824         case xmm_mq_mode:
14825         case q_mode:
14826         case q_scalar_mode:
14827         case q_swap_mode:
14828         case q_scalar_swap_mode:
14829           shift = 3;
14830           break;
14831         case dqd_mode:
14832         case xmm_md_mode:
14833         case d_mode:
14834         case d_scalar_mode:
14835         case d_swap_mode:
14836         case d_scalar_swap_mode:
14837           shift = 2;
14838           break;
14839         case xmm_mw_mode:
14840           shift = 1;
14841           break;
14842         case xmm_mb_mode:
14843           shift = 0;
14844           break;
14845         default:
14846           abort ();
14847         }
14848       /* Make necessary corrections to shift for modes that need it.
14849          For these modes we currently have shift 4, 5 or 6 depending on
14850          vex.length (it corresponds to xmmword, ymmword or zmmword
14851          operand).  We might want to make it 3, 4 or 5 (e.g. for
14852          xmmq_mode).  In case of broadcast enabled the corrections
14853          aren't needed, as element size is always 32 or 64 bits.  */
14854       if (!vex.b
14855           && (bytemode == xmmq_mode
14856               || bytemode == evex_half_bcst_xmmq_mode))
14857         shift -= 1;
14858       else if (bytemode == xmmqd_mode)
14859         shift -= 2;
14860       else if (bytemode == xmmdw_mode)
14861         shift -= 3;
14862       else if (bytemode == ymmq_mode && vex.length == 128)
14863         shift -= 1;
14864     }
14865   else
14866     shift = 0;
14867
14868   USED_REX (REX_B);
14869   if (intel_syntax)
14870     intel_operand_size (bytemode, sizeflag);
14871   append_seg ();
14872
14873   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14874     {
14875       /* 32/64 bit address mode */
14876       int havedisp;
14877       int havesib;
14878       int havebase;
14879       int haveindex;
14880       int needindex;
14881       int base, rbase;
14882       int vindex = 0;
14883       int scale = 0;
14884       int addr32flag = !((sizeflag & AFLAG)
14885                          || bytemode == v_bnd_mode
14886                          || bytemode == bnd_mode);
14887       const char **indexes64 = names64;
14888       const char **indexes32 = names32;
14889
14890       havesib = 0;
14891       havebase = 1;
14892       haveindex = 0;
14893       base = modrm.rm;
14894
14895       if (base == 4)
14896         {
14897           havesib = 1;
14898           vindex = sib.index;
14899           USED_REX (REX_X);
14900           if (rex & REX_X)
14901             vindex += 8;
14902           switch (bytemode)
14903             {
14904             case vex_vsib_d_w_dq_mode:
14905             case vex_vsib_d_w_d_mode:
14906             case vex_vsib_q_w_dq_mode:
14907             case vex_vsib_q_w_d_mode:
14908               if (!need_vex)
14909                 abort ();
14910               if (vex.evex)
14911                 {
14912                   if (!vex.v)
14913                     vindex += 16;
14914                 }
14915
14916               haveindex = 1;
14917               switch (vex.length)
14918                 {
14919                 case 128:
14920                   indexes64 = indexes32 = names_xmm;
14921                   break;
14922                 case 256:
14923                   if (!vex.w
14924                       || bytemode == vex_vsib_q_w_dq_mode
14925                       || bytemode == vex_vsib_q_w_d_mode)
14926                     indexes64 = indexes32 = names_ymm;
14927                   else
14928                     indexes64 = indexes32 = names_xmm;
14929                   break;
14930                 case 512:
14931                   if (!vex.w
14932                       || bytemode == vex_vsib_q_w_dq_mode
14933                       || bytemode == vex_vsib_q_w_d_mode)
14934                     indexes64 = indexes32 = names_zmm;
14935                   else
14936                     indexes64 = indexes32 = names_ymm;
14937                   break;
14938                 default:
14939                   abort ();
14940                 }
14941               break;
14942             default:
14943               haveindex = vindex != 4;
14944               break;
14945             }
14946           scale = sib.scale;
14947           base = sib.base;
14948           codep++;
14949         }
14950       rbase = base + add;
14951
14952       switch (modrm.mod)
14953         {
14954         case 0:
14955           if (base == 5)
14956             {
14957               havebase = 0;
14958               if (address_mode == mode_64bit && !havesib)
14959                 riprel = 1;
14960               disp = get32s ();
14961             }
14962           break;
14963         case 1:
14964           FETCH_DATA (the_info, codep + 1);
14965           disp = *codep++;
14966           if ((disp & 0x80) != 0)
14967             disp -= 0x100;
14968           if (vex.evex && shift > 0)
14969             disp <<= shift;
14970           break;
14971         case 2:
14972           disp = get32s ();
14973           break;
14974         }
14975
14976       /* In 32bit mode, we need index register to tell [offset] from
14977          [eiz*1 + offset].  */
14978       needindex = (havesib
14979                    && !havebase
14980                    && !haveindex
14981                    && address_mode == mode_32bit);
14982       havedisp = (havebase
14983                   || needindex
14984                   || (havesib && (haveindex || scale != 0)));
14985
14986       if (!intel_syntax)
14987         if (modrm.mod != 0 || base == 5)
14988           {
14989             if (havedisp || riprel)
14990               print_displacement (scratchbuf, disp);
14991             else
14992               print_operand_value (scratchbuf, 1, disp);
14993             oappend (scratchbuf);
14994             if (riprel)
14995               {
14996                 set_op (disp, 1);
14997                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14998               }
14999           }
15000
15001       if ((havebase || haveindex || riprel)
15002           && (bytemode != v_bnd_mode)
15003           && (bytemode != bnd_mode))
15004         used_prefixes |= PREFIX_ADDR;
15005
15006       if (havedisp || (intel_syntax && riprel))
15007         {
15008           *obufp++ = open_char;
15009           if (intel_syntax && riprel)
15010             {
15011               set_op (disp, 1);
15012               oappend (sizeflag & AFLAG ? "rip" : "eip");
15013             }
15014           *obufp = '\0';
15015           if (havebase)
15016             oappend (address_mode == mode_64bit && !addr32flag
15017                      ? names64[rbase] : names32[rbase]);
15018           if (havesib)
15019             {
15020               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15021                  print index to tell base + index from base.  */
15022               if (scale != 0
15023                   || needindex
15024                   || haveindex
15025                   || (havebase && base != ESP_REG_NUM))
15026                 {
15027                   if (!intel_syntax || havebase)
15028                     {
15029                       *obufp++ = separator_char;
15030                       *obufp = '\0';
15031                     }
15032                   if (haveindex)
15033                     oappend (address_mode == mode_64bit && !addr32flag
15034                              ? indexes64[vindex] : indexes32[vindex]);
15035                   else
15036                     oappend (address_mode == mode_64bit && !addr32flag
15037                              ? index64 : index32);
15038
15039                   *obufp++ = scale_char;
15040                   *obufp = '\0';
15041                   sprintf (scratchbuf, "%d", 1 << scale);
15042                   oappend (scratchbuf);
15043                 }
15044             }
15045           if (intel_syntax
15046               && (disp || modrm.mod != 0 || base == 5))
15047             {
15048               if (!havedisp || (bfd_signed_vma) disp >= 0)
15049                 {
15050                   *obufp++ = '+';
15051                   *obufp = '\0';
15052                 }
15053               else if (modrm.mod != 1 && disp != -disp)
15054                 {
15055                   *obufp++ = '-';
15056                   *obufp = '\0';
15057                   disp = - (bfd_signed_vma) disp;
15058                 }
15059
15060               if (havedisp)
15061                 print_displacement (scratchbuf, disp);
15062               else
15063                 print_operand_value (scratchbuf, 1, disp);
15064               oappend (scratchbuf);
15065             }
15066
15067           *obufp++ = close_char;
15068           *obufp = '\0';
15069         }
15070       else if (intel_syntax)
15071         {
15072           if (modrm.mod != 0 || base == 5)
15073             {
15074               if (!active_seg_prefix)
15075                 {
15076                   oappend (names_seg[ds_reg - es_reg]);
15077                   oappend (":");
15078                 }
15079               print_operand_value (scratchbuf, 1, disp);
15080               oappend (scratchbuf);
15081             }
15082         }
15083     }
15084   else
15085     {
15086       /* 16 bit address mode */
15087       used_prefixes |= prefixes & PREFIX_ADDR;
15088       switch (modrm.mod)
15089         {
15090         case 0:
15091           if (modrm.rm == 6)
15092             {
15093               disp = get16 ();
15094               if ((disp & 0x8000) != 0)
15095                 disp -= 0x10000;
15096             }
15097           break;
15098         case 1:
15099           FETCH_DATA (the_info, codep + 1);
15100           disp = *codep++;
15101           if ((disp & 0x80) != 0)
15102             disp -= 0x100;
15103           break;
15104         case 2:
15105           disp = get16 ();
15106           if ((disp & 0x8000) != 0)
15107             disp -= 0x10000;
15108           break;
15109         }
15110
15111       if (!intel_syntax)
15112         if (modrm.mod != 0 || modrm.rm == 6)
15113           {
15114             print_displacement (scratchbuf, disp);
15115             oappend (scratchbuf);
15116           }
15117
15118       if (modrm.mod != 0 || modrm.rm != 6)
15119         {
15120           *obufp++ = open_char;
15121           *obufp = '\0';
15122           oappend (index16[modrm.rm]);
15123           if (intel_syntax
15124               && (disp || modrm.mod != 0 || modrm.rm == 6))
15125             {
15126               if ((bfd_signed_vma) disp >= 0)
15127                 {
15128                   *obufp++ = '+';
15129                   *obufp = '\0';
15130                 }
15131               else if (modrm.mod != 1)
15132                 {
15133                   *obufp++ = '-';
15134                   *obufp = '\0';
15135                   disp = - (bfd_signed_vma) disp;
15136                 }
15137
15138               print_displacement (scratchbuf, disp);
15139               oappend (scratchbuf);
15140             }
15141
15142           *obufp++ = close_char;
15143           *obufp = '\0';
15144         }
15145       else if (intel_syntax)
15146         {
15147           if (!active_seg_prefix)
15148             {
15149               oappend (names_seg[ds_reg - es_reg]);
15150               oappend (":");
15151             }
15152           print_operand_value (scratchbuf, 1, disp & 0xffff);
15153           oappend (scratchbuf);
15154         }
15155     }
15156   if (vex.evex && vex.b
15157       && (bytemode == x_mode
15158           || bytemode == xmmq_mode
15159           || bytemode == evex_half_bcst_xmmq_mode))
15160     {
15161       if (vex.w
15162           || bytemode == xmmq_mode
15163           || bytemode == evex_half_bcst_xmmq_mode)
15164         {
15165           switch (vex.length)
15166             {
15167             case 128:
15168               oappend ("{1to2}");
15169               break;
15170             case 256:
15171               oappend ("{1to4}");
15172               break;
15173             case 512:
15174               oappend ("{1to8}");
15175               break;
15176             default:
15177               abort ();
15178             }
15179         }
15180       else
15181         {
15182           switch (vex.length)
15183             {
15184             case 128:
15185               oappend ("{1to4}");
15186               break;
15187             case 256:
15188               oappend ("{1to8}");
15189               break;
15190             case 512:
15191               oappend ("{1to16}");
15192               break;
15193             default:
15194               abort ();
15195             }
15196         }
15197     }
15198 }
15199
15200 static void
15201 OP_E (int bytemode, int sizeflag)
15202 {
15203   /* Skip mod/rm byte.  */
15204   MODRM_CHECK;
15205   codep++;
15206
15207   if (modrm.mod == 3)
15208     OP_E_register (bytemode, sizeflag);
15209   else
15210     OP_E_memory (bytemode, sizeflag);
15211 }
15212
15213 static void
15214 OP_G (int bytemode, int sizeflag)
15215 {
15216   int add = 0;
15217   USED_REX (REX_R);
15218   if (rex & REX_R)
15219     add += 8;
15220   switch (bytemode)
15221     {
15222     case b_mode:
15223       USED_REX (0);
15224       if (rex)
15225         oappend (names8rex[modrm.reg + add]);
15226       else
15227         oappend (names8[modrm.reg + add]);
15228       break;
15229     case w_mode:
15230       oappend (names16[modrm.reg + add]);
15231       break;
15232     case d_mode:
15233     case db_mode:
15234     case dw_mode:
15235       oappend (names32[modrm.reg + add]);
15236       break;
15237     case q_mode:
15238       oappend (names64[modrm.reg + add]);
15239       break;
15240     case bnd_mode:
15241       oappend (names_bnd[modrm.reg]);
15242       break;
15243     case v_mode:
15244     case dq_mode:
15245     case dqb_mode:
15246     case dqd_mode:
15247     case dqw_mode:
15248     case dqw_swap_mode:
15249       USED_REX (REX_W);
15250       if (rex & REX_W)
15251         oappend (names64[modrm.reg + add]);
15252       else
15253         {
15254           if ((sizeflag & DFLAG) || bytemode != v_mode)
15255             oappend (names32[modrm.reg + add]);
15256           else
15257             oappend (names16[modrm.reg + add]);
15258           used_prefixes |= (prefixes & PREFIX_DATA);
15259         }
15260       break;
15261     case m_mode:
15262       if (address_mode == mode_64bit)
15263         oappend (names64[modrm.reg + add]);
15264       else
15265         oappend (names32[modrm.reg + add]);
15266       break;
15267     case mask_bd_mode:
15268     case mask_mode:
15269       oappend (names_mask[modrm.reg + add]);
15270       break;
15271     default:
15272       oappend (INTERNAL_DISASSEMBLER_ERROR);
15273       break;
15274     }
15275 }
15276
15277 static bfd_vma
15278 get64 (void)
15279 {
15280   bfd_vma x;
15281 #ifdef BFD64
15282   unsigned int a;
15283   unsigned int b;
15284
15285   FETCH_DATA (the_info, codep + 8);
15286   a = *codep++ & 0xff;
15287   a |= (*codep++ & 0xff) << 8;
15288   a |= (*codep++ & 0xff) << 16;
15289   a |= (*codep++ & 0xff) << 24;
15290   b = *codep++ & 0xff;
15291   b |= (*codep++ & 0xff) << 8;
15292   b |= (*codep++ & 0xff) << 16;
15293   b |= (*codep++ & 0xff) << 24;
15294   x = a + ((bfd_vma) b << 32);
15295 #else
15296   abort ();
15297   x = 0;
15298 #endif
15299   return x;
15300 }
15301
15302 static bfd_signed_vma
15303 get32 (void)
15304 {
15305   bfd_signed_vma x = 0;
15306
15307   FETCH_DATA (the_info, codep + 4);
15308   x = *codep++ & (bfd_signed_vma) 0xff;
15309   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15310   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15311   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15312   return x;
15313 }
15314
15315 static bfd_signed_vma
15316 get32s (void)
15317 {
15318   bfd_signed_vma x = 0;
15319
15320   FETCH_DATA (the_info, codep + 4);
15321   x = *codep++ & (bfd_signed_vma) 0xff;
15322   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15323   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15324   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15325
15326   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15327
15328   return x;
15329 }
15330
15331 static int
15332 get16 (void)
15333 {
15334   int x = 0;
15335
15336   FETCH_DATA (the_info, codep + 2);
15337   x = *codep++ & 0xff;
15338   x |= (*codep++ & 0xff) << 8;
15339   return x;
15340 }
15341
15342 static void
15343 set_op (bfd_vma op, int riprel)
15344 {
15345   op_index[op_ad] = op_ad;
15346   if (address_mode == mode_64bit)
15347     {
15348       op_address[op_ad] = op;
15349       op_riprel[op_ad] = riprel;
15350     }
15351   else
15352     {
15353       /* Mask to get a 32-bit address.  */
15354       op_address[op_ad] = op & 0xffffffff;
15355       op_riprel[op_ad] = riprel & 0xffffffff;
15356     }
15357 }
15358
15359 static void
15360 OP_REG (int code, int sizeflag)
15361 {
15362   const char *s;
15363   int add;
15364
15365   switch (code)
15366     {
15367     case es_reg: case ss_reg: case cs_reg:
15368     case ds_reg: case fs_reg: case gs_reg:
15369       oappend (names_seg[code - es_reg]);
15370       return;
15371     }
15372
15373   USED_REX (REX_B);
15374   if (rex & REX_B)
15375     add = 8;
15376   else
15377     add = 0;
15378
15379   switch (code)
15380     {
15381     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15382     case sp_reg: case bp_reg: case si_reg: case di_reg:
15383       s = names16[code - ax_reg + add];
15384       break;
15385     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15386     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15387       USED_REX (0);
15388       if (rex)
15389         s = names8rex[code - al_reg + add];
15390       else
15391         s = names8[code - al_reg];
15392       break;
15393     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15394     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15395       if (address_mode == mode_64bit
15396           && ((sizeflag & DFLAG) || (rex & REX_W)))
15397         {
15398           s = names64[code - rAX_reg + add];
15399           break;
15400         }
15401       code += eAX_reg - rAX_reg;
15402       /* Fall through.  */
15403     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15404     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15405       USED_REX (REX_W);
15406       if (rex & REX_W)
15407         s = names64[code - eAX_reg + add];
15408       else
15409         {
15410           if (sizeflag & DFLAG)
15411             s = names32[code - eAX_reg + add];
15412           else
15413             s = names16[code - eAX_reg + add];
15414           used_prefixes |= (prefixes & PREFIX_DATA);
15415         }
15416       break;
15417     default:
15418       s = INTERNAL_DISASSEMBLER_ERROR;
15419       break;
15420     }
15421   oappend (s);
15422 }
15423
15424 static void
15425 OP_IMREG (int code, int sizeflag)
15426 {
15427   const char *s;
15428
15429   switch (code)
15430     {
15431     case indir_dx_reg:
15432       if (intel_syntax)
15433         s = "dx";
15434       else
15435         s = "(%dx)";
15436       break;
15437     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15438     case sp_reg: case bp_reg: case si_reg: case di_reg:
15439       s = names16[code - ax_reg];
15440       break;
15441     case es_reg: case ss_reg: case cs_reg:
15442     case ds_reg: case fs_reg: case gs_reg:
15443       s = names_seg[code - es_reg];
15444       break;
15445     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15446     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15447       USED_REX (0);
15448       if (rex)
15449         s = names8rex[code - al_reg];
15450       else
15451         s = names8[code - al_reg];
15452       break;
15453     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15454     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15455       USED_REX (REX_W);
15456       if (rex & REX_W)
15457         s = names64[code - eAX_reg];
15458       else
15459         {
15460           if (sizeflag & DFLAG)
15461             s = names32[code - eAX_reg];
15462           else
15463             s = names16[code - eAX_reg];
15464           used_prefixes |= (prefixes & PREFIX_DATA);
15465         }
15466       break;
15467     case z_mode_ax_reg:
15468       if ((rex & REX_W) || (sizeflag & DFLAG))
15469         s = *names32;
15470       else
15471         s = *names16;
15472       if (!(rex & REX_W))
15473         used_prefixes |= (prefixes & PREFIX_DATA);
15474       break;
15475     default:
15476       s = INTERNAL_DISASSEMBLER_ERROR;
15477       break;
15478     }
15479   oappend (s);
15480 }
15481
15482 static void
15483 OP_I (int bytemode, int sizeflag)
15484 {
15485   bfd_signed_vma op;
15486   bfd_signed_vma mask = -1;
15487
15488   switch (bytemode)
15489     {
15490     case b_mode:
15491       FETCH_DATA (the_info, codep + 1);
15492       op = *codep++;
15493       mask = 0xff;
15494       break;
15495     case q_mode:
15496       if (address_mode == mode_64bit)
15497         {
15498           op = get32s ();
15499           break;
15500         }
15501       /* Fall through.  */
15502     case v_mode:
15503       USED_REX (REX_W);
15504       if (rex & REX_W)
15505         op = get32s ();
15506       else
15507         {
15508           if (sizeflag & DFLAG)
15509             {
15510               op = get32 ();
15511               mask = 0xffffffff;
15512             }
15513           else
15514             {
15515               op = get16 ();
15516               mask = 0xfffff;
15517             }
15518           used_prefixes |= (prefixes & PREFIX_DATA);
15519         }
15520       break;
15521     case w_mode:
15522       mask = 0xfffff;
15523       op = get16 ();
15524       break;
15525     case const_1_mode:
15526       if (intel_syntax)
15527         oappend ("1");
15528       return;
15529     default:
15530       oappend (INTERNAL_DISASSEMBLER_ERROR);
15531       return;
15532     }
15533
15534   op &= mask;
15535   scratchbuf[0] = '$';
15536   print_operand_value (scratchbuf + 1, 1, op);
15537   oappend_maybe_intel (scratchbuf);
15538   scratchbuf[0] = '\0';
15539 }
15540
15541 static void
15542 OP_I64 (int bytemode, int sizeflag)
15543 {
15544   bfd_signed_vma op;
15545   bfd_signed_vma mask = -1;
15546
15547   if (address_mode != mode_64bit)
15548     {
15549       OP_I (bytemode, sizeflag);
15550       return;
15551     }
15552
15553   switch (bytemode)
15554     {
15555     case b_mode:
15556       FETCH_DATA (the_info, codep + 1);
15557       op = *codep++;
15558       mask = 0xff;
15559       break;
15560     case v_mode:
15561       USED_REX (REX_W);
15562       if (rex & REX_W)
15563         op = get64 ();
15564       else
15565         {
15566           if (sizeflag & DFLAG)
15567             {
15568               op = get32 ();
15569               mask = 0xffffffff;
15570             }
15571           else
15572             {
15573               op = get16 ();
15574               mask = 0xfffff;
15575             }
15576           used_prefixes |= (prefixes & PREFIX_DATA);
15577         }
15578       break;
15579     case w_mode:
15580       mask = 0xfffff;
15581       op = get16 ();
15582       break;
15583     default:
15584       oappend (INTERNAL_DISASSEMBLER_ERROR);
15585       return;
15586     }
15587
15588   op &= mask;
15589   scratchbuf[0] = '$';
15590   print_operand_value (scratchbuf + 1, 1, op);
15591   oappend_maybe_intel (scratchbuf);
15592   scratchbuf[0] = '\0';
15593 }
15594
15595 static void
15596 OP_sI (int bytemode, int sizeflag)
15597 {
15598   bfd_signed_vma op;
15599
15600   switch (bytemode)
15601     {
15602     case b_mode:
15603     case b_T_mode:
15604       FETCH_DATA (the_info, codep + 1);
15605       op = *codep++;
15606       if ((op & 0x80) != 0)
15607         op -= 0x100;
15608       if (bytemode == b_T_mode)
15609         {
15610           if (address_mode != mode_64bit
15611               || !((sizeflag & DFLAG) || (rex & REX_W)))
15612             {
15613               /* The operand-size prefix is overridden by a REX prefix.  */
15614               if ((sizeflag & DFLAG) || (rex & REX_W))
15615                 op &= 0xffffffff;
15616               else
15617                 op &= 0xffff;
15618           }
15619         }
15620       else
15621         {
15622           if (!(rex & REX_W))
15623             {
15624               if (sizeflag & DFLAG)
15625                 op &= 0xffffffff;
15626               else
15627                 op &= 0xffff;
15628             }
15629         }
15630       break;
15631     case v_mode:
15632       /* The operand-size prefix is overridden by a REX prefix.  */
15633       if ((sizeflag & DFLAG) || (rex & REX_W))
15634         op = get32s ();
15635       else
15636         op = get16 ();
15637       break;
15638     default:
15639       oappend (INTERNAL_DISASSEMBLER_ERROR);
15640       return;
15641     }
15642
15643   scratchbuf[0] = '$';
15644   print_operand_value (scratchbuf + 1, 1, op);
15645   oappend_maybe_intel (scratchbuf);
15646 }
15647
15648 static void
15649 OP_J (int bytemode, int sizeflag)
15650 {
15651   bfd_vma disp;
15652   bfd_vma mask = -1;
15653   bfd_vma segment = 0;
15654
15655   switch (bytemode)
15656     {
15657     case b_mode:
15658       FETCH_DATA (the_info, codep + 1);
15659       disp = *codep++;
15660       if ((disp & 0x80) != 0)
15661         disp -= 0x100;
15662       break;
15663     case v_mode:
15664       USED_REX (REX_W);
15665       if ((sizeflag & DFLAG) || (rex & REX_W))
15666         disp = get32s ();
15667       else
15668         {
15669           disp = get16 ();
15670           if ((disp & 0x8000) != 0)
15671             disp -= 0x10000;
15672           /* In 16bit mode, address is wrapped around at 64k within
15673              the same segment.  Otherwise, a data16 prefix on a jump
15674              instruction means that the pc is masked to 16 bits after
15675              the displacement is added!  */
15676           mask = 0xffff;
15677           if ((prefixes & PREFIX_DATA) == 0)
15678             segment = ((start_pc + codep - start_codep)
15679                        & ~((bfd_vma) 0xffff));
15680         }
15681       if (!(rex & REX_W))
15682         used_prefixes |= (prefixes & PREFIX_DATA);
15683       break;
15684     default:
15685       oappend (INTERNAL_DISASSEMBLER_ERROR);
15686       return;
15687     }
15688   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15689   set_op (disp, 0);
15690   print_operand_value (scratchbuf, 1, disp);
15691   oappend (scratchbuf);
15692 }
15693
15694 static void
15695 OP_SEG (int bytemode, int sizeflag)
15696 {
15697   if (bytemode == w_mode)
15698     oappend (names_seg[modrm.reg]);
15699   else
15700     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15701 }
15702
15703 static void
15704 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15705 {
15706   int seg, offset;
15707
15708   if (sizeflag & DFLAG)
15709     {
15710       offset = get32 ();
15711       seg = get16 ();
15712     }
15713   else
15714     {
15715       offset = get16 ();
15716       seg = get16 ();
15717     }
15718   used_prefixes |= (prefixes & PREFIX_DATA);
15719   if (intel_syntax)
15720     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15721   else
15722     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15723   oappend (scratchbuf);
15724 }
15725
15726 static void
15727 OP_OFF (int bytemode, int sizeflag)
15728 {
15729   bfd_vma off;
15730
15731   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15732     intel_operand_size (bytemode, sizeflag);
15733   append_seg ();
15734
15735   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15736     off = get32 ();
15737   else
15738     off = get16 ();
15739
15740   if (intel_syntax)
15741     {
15742       if (!active_seg_prefix)
15743         {
15744           oappend (names_seg[ds_reg - es_reg]);
15745           oappend (":");
15746         }
15747     }
15748   print_operand_value (scratchbuf, 1, off);
15749   oappend (scratchbuf);
15750 }
15751
15752 static void
15753 OP_OFF64 (int bytemode, int sizeflag)
15754 {
15755   bfd_vma off;
15756
15757   if (address_mode != mode_64bit
15758       || (prefixes & PREFIX_ADDR))
15759     {
15760       OP_OFF (bytemode, sizeflag);
15761       return;
15762     }
15763
15764   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15765     intel_operand_size (bytemode, sizeflag);
15766   append_seg ();
15767
15768   off = get64 ();
15769
15770   if (intel_syntax)
15771     {
15772       if (!active_seg_prefix)
15773         {
15774           oappend (names_seg[ds_reg - es_reg]);
15775           oappend (":");
15776         }
15777     }
15778   print_operand_value (scratchbuf, 1, off);
15779   oappend (scratchbuf);
15780 }
15781
15782 static void
15783 ptr_reg (int code, int sizeflag)
15784 {
15785   const char *s;
15786
15787   *obufp++ = open_char;
15788   used_prefixes |= (prefixes & PREFIX_ADDR);
15789   if (address_mode == mode_64bit)
15790     {
15791       if (!(sizeflag & AFLAG))
15792         s = names32[code - eAX_reg];
15793       else
15794         s = names64[code - eAX_reg];
15795     }
15796   else if (sizeflag & AFLAG)
15797     s = names32[code - eAX_reg];
15798   else
15799     s = names16[code - eAX_reg];
15800   oappend (s);
15801   *obufp++ = close_char;
15802   *obufp = 0;
15803 }
15804
15805 static void
15806 OP_ESreg (int code, int sizeflag)
15807 {
15808   if (intel_syntax)
15809     {
15810       switch (codep[-1])
15811         {
15812         case 0x6d:      /* insw/insl */
15813           intel_operand_size (z_mode, sizeflag);
15814           break;
15815         case 0xa5:      /* movsw/movsl/movsq */
15816         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15817         case 0xab:      /* stosw/stosl */
15818         case 0xaf:      /* scasw/scasl */
15819           intel_operand_size (v_mode, sizeflag);
15820           break;
15821         default:
15822           intel_operand_size (b_mode, sizeflag);
15823         }
15824     }
15825   oappend_maybe_intel ("%es:");
15826   ptr_reg (code, sizeflag);
15827 }
15828
15829 static void
15830 OP_DSreg (int code, int sizeflag)
15831 {
15832   if (intel_syntax)
15833     {
15834       switch (codep[-1])
15835         {
15836         case 0x6f:      /* outsw/outsl */
15837           intel_operand_size (z_mode, sizeflag);
15838           break;
15839         case 0xa5:      /* movsw/movsl/movsq */
15840         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15841         case 0xad:      /* lodsw/lodsl/lodsq */
15842           intel_operand_size (v_mode, sizeflag);
15843           break;
15844         default:
15845           intel_operand_size (b_mode, sizeflag);
15846         }
15847     }
15848   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15849      default segment register DS is printed.  */
15850   if (!active_seg_prefix)
15851     active_seg_prefix = PREFIX_DS;
15852   append_seg ();
15853   ptr_reg (code, sizeflag);
15854 }
15855
15856 static void
15857 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15858 {
15859   int add;
15860   if (rex & REX_R)
15861     {
15862       USED_REX (REX_R);
15863       add = 8;
15864     }
15865   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15866     {
15867       all_prefixes[last_lock_prefix] = 0;
15868       used_prefixes |= PREFIX_LOCK;
15869       add = 8;
15870     }
15871   else
15872     add = 0;
15873   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15874   oappend_maybe_intel (scratchbuf);
15875 }
15876
15877 static void
15878 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15879 {
15880   int add;
15881   USED_REX (REX_R);
15882   if (rex & REX_R)
15883     add = 8;
15884   else
15885     add = 0;
15886   if (intel_syntax)
15887     sprintf (scratchbuf, "db%d", modrm.reg + add);
15888   else
15889     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15890   oappend (scratchbuf);
15891 }
15892
15893 static void
15894 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15895 {
15896   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15897   oappend_maybe_intel (scratchbuf);
15898 }
15899
15900 static void
15901 OP_R (int bytemode, int sizeflag)
15902 {
15903   /* Skip mod/rm byte.  */
15904   MODRM_CHECK;
15905   codep++;
15906   OP_E_register (bytemode, sizeflag);
15907 }
15908
15909 static void
15910 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15911 {
15912   int reg = modrm.reg;
15913   const char **names;
15914
15915   used_prefixes |= (prefixes & PREFIX_DATA);
15916   if (prefixes & PREFIX_DATA)
15917     {
15918       names = names_xmm;
15919       USED_REX (REX_R);
15920       if (rex & REX_R)
15921         reg += 8;
15922     }
15923   else
15924     names = names_mm;
15925   oappend (names[reg]);
15926 }
15927
15928 static void
15929 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15930 {
15931   int reg = modrm.reg;
15932   const char **names;
15933
15934   USED_REX (REX_R);
15935   if (rex & REX_R)
15936     reg += 8;
15937   if (vex.evex)
15938     {
15939       if (!vex.r)
15940         reg += 16;
15941     }
15942
15943   if (need_vex
15944       && bytemode != xmm_mode
15945       && bytemode != xmmq_mode
15946       && bytemode != evex_half_bcst_xmmq_mode
15947       && bytemode != ymm_mode
15948       && bytemode != scalar_mode)
15949     {
15950       switch (vex.length)
15951         {
15952         case 128:
15953           names = names_xmm;
15954           break;
15955         case 256:
15956           if (vex.w
15957               || (bytemode != vex_vsib_q_w_dq_mode
15958                   && bytemode != vex_vsib_q_w_d_mode))
15959             names = names_ymm;
15960           else
15961             names = names_xmm;
15962           break;
15963         case 512:
15964           names = names_zmm;
15965           break;
15966         default:
15967           abort ();
15968         }
15969     }
15970   else if (bytemode == xmmq_mode
15971            || bytemode == evex_half_bcst_xmmq_mode)
15972     {
15973       switch (vex.length)
15974         {
15975         case 128:
15976         case 256:
15977           names = names_xmm;
15978           break;
15979         case 512:
15980           names = names_ymm;
15981           break;
15982         default:
15983           abort ();
15984         }
15985     }
15986   else if (bytemode == ymm_mode)
15987     names = names_ymm;
15988   else
15989     names = names_xmm;
15990   oappend (names[reg]);
15991 }
15992
15993 static void
15994 OP_EM (int bytemode, int sizeflag)
15995 {
15996   int reg;
15997   const char **names;
15998
15999   if (modrm.mod != 3)
16000     {
16001       if (intel_syntax
16002           && (bytemode == v_mode || bytemode == v_swap_mode))
16003         {
16004           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16005           used_prefixes |= (prefixes & PREFIX_DATA);
16006         }
16007       OP_E (bytemode, sizeflag);
16008       return;
16009     }
16010
16011   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16012     swap_operand ();
16013
16014   /* Skip mod/rm byte.  */
16015   MODRM_CHECK;
16016   codep++;
16017   used_prefixes |= (prefixes & PREFIX_DATA);
16018   reg = modrm.rm;
16019   if (prefixes & PREFIX_DATA)
16020     {
16021       names = names_xmm;
16022       USED_REX (REX_B);
16023       if (rex & REX_B)
16024         reg += 8;
16025     }
16026   else
16027     names = names_mm;
16028   oappend (names[reg]);
16029 }
16030
16031 /* cvt* are the only instructions in sse2 which have
16032    both SSE and MMX operands and also have 0x66 prefix
16033    in their opcode. 0x66 was originally used to differentiate
16034    between SSE and MMX instruction(operands). So we have to handle the
16035    cvt* separately using OP_EMC and OP_MXC */
16036 static void
16037 OP_EMC (int bytemode, int sizeflag)
16038 {
16039   if (modrm.mod != 3)
16040     {
16041       if (intel_syntax && bytemode == v_mode)
16042         {
16043           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16044           used_prefixes |= (prefixes & PREFIX_DATA);
16045         }
16046       OP_E (bytemode, sizeflag);
16047       return;
16048     }
16049
16050   /* Skip mod/rm byte.  */
16051   MODRM_CHECK;
16052   codep++;
16053   used_prefixes |= (prefixes & PREFIX_DATA);
16054   oappend (names_mm[modrm.rm]);
16055 }
16056
16057 static void
16058 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16059 {
16060   used_prefixes |= (prefixes & PREFIX_DATA);
16061   oappend (names_mm[modrm.reg]);
16062 }
16063
16064 static void
16065 OP_EX (int bytemode, int sizeflag)
16066 {
16067   int reg;
16068   const char **names;
16069
16070   /* Skip mod/rm byte.  */
16071   MODRM_CHECK;
16072   codep++;
16073
16074   if (modrm.mod != 3)
16075     {
16076       OP_E_memory (bytemode, sizeflag);
16077       return;
16078     }
16079
16080   reg = modrm.rm;
16081   USED_REX (REX_B);
16082   if (rex & REX_B)
16083     reg += 8;
16084   if (vex.evex)
16085     {
16086       USED_REX (REX_X);
16087       if ((rex & REX_X))
16088         reg += 16;
16089     }
16090
16091   if ((sizeflag & SUFFIX_ALWAYS)
16092       && (bytemode == x_swap_mode
16093           || bytemode == d_swap_mode
16094           || bytemode == dqw_swap_mode
16095           || bytemode == d_scalar_swap_mode
16096           || bytemode == q_swap_mode
16097           || bytemode == q_scalar_swap_mode))
16098     swap_operand ();
16099
16100   if (need_vex
16101       && bytemode != xmm_mode
16102       && bytemode != xmmdw_mode
16103       && bytemode != xmmqd_mode
16104       && bytemode != xmm_mb_mode
16105       && bytemode != xmm_mw_mode
16106       && bytemode != xmm_md_mode
16107       && bytemode != xmm_mq_mode
16108       && bytemode != xmm_mdq_mode
16109       && bytemode != xmmq_mode
16110       && bytemode != evex_half_bcst_xmmq_mode
16111       && bytemode != ymm_mode
16112       && bytemode != d_scalar_mode
16113       && bytemode != d_scalar_swap_mode
16114       && bytemode != q_scalar_mode
16115       && bytemode != q_scalar_swap_mode
16116       && bytemode != vex_scalar_w_dq_mode)
16117     {
16118       switch (vex.length)
16119         {
16120         case 128:
16121           names = names_xmm;
16122           break;
16123         case 256:
16124           names = names_ymm;
16125           break;
16126         case 512:
16127           names = names_zmm;
16128           break;
16129         default:
16130           abort ();
16131         }
16132     }
16133   else if (bytemode == xmmq_mode
16134            || bytemode == evex_half_bcst_xmmq_mode)
16135     {
16136       switch (vex.length)
16137         {
16138         case 128:
16139         case 256:
16140           names = names_xmm;
16141           break;
16142         case 512:
16143           names = names_ymm;
16144           break;
16145         default:
16146           abort ();
16147         }
16148     }
16149   else if (bytemode == ymm_mode)
16150     names = names_ymm;
16151   else
16152     names = names_xmm;
16153   oappend (names[reg]);
16154 }
16155
16156 static void
16157 OP_MS (int bytemode, int sizeflag)
16158 {
16159   if (modrm.mod == 3)
16160     OP_EM (bytemode, sizeflag);
16161   else
16162     BadOp ();
16163 }
16164
16165 static void
16166 OP_XS (int bytemode, int sizeflag)
16167 {
16168   if (modrm.mod == 3)
16169     OP_EX (bytemode, sizeflag);
16170   else
16171     BadOp ();
16172 }
16173
16174 static void
16175 OP_M (int bytemode, int sizeflag)
16176 {
16177   if (modrm.mod == 3)
16178     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16179     BadOp ();
16180   else
16181     OP_E (bytemode, sizeflag);
16182 }
16183
16184 static void
16185 OP_0f07 (int bytemode, int sizeflag)
16186 {
16187   if (modrm.mod != 3 || modrm.rm != 0)
16188     BadOp ();
16189   else
16190     OP_E (bytemode, sizeflag);
16191 }
16192
16193 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16194    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16195
16196 static void
16197 NOP_Fixup1 (int bytemode, int sizeflag)
16198 {
16199   if ((prefixes & PREFIX_DATA) != 0
16200       || (rex != 0
16201           && rex != 0x48
16202           && address_mode == mode_64bit))
16203     OP_REG (bytemode, sizeflag);
16204   else
16205     strcpy (obuf, "nop");
16206 }
16207
16208 static void
16209 NOP_Fixup2 (int bytemode, int sizeflag)
16210 {
16211   if ((prefixes & PREFIX_DATA) != 0
16212       || (rex != 0
16213           && rex != 0x48
16214           && address_mode == mode_64bit))
16215     OP_IMREG (bytemode, sizeflag);
16216 }
16217
16218 static const char *const Suffix3DNow[] = {
16219 /* 00 */        NULL,           NULL,           NULL,           NULL,
16220 /* 04 */        NULL,           NULL,           NULL,           NULL,
16221 /* 08 */        NULL,           NULL,           NULL,           NULL,
16222 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16223 /* 10 */        NULL,           NULL,           NULL,           NULL,
16224 /* 14 */        NULL,           NULL,           NULL,           NULL,
16225 /* 18 */        NULL,           NULL,           NULL,           NULL,
16226 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16227 /* 20 */        NULL,           NULL,           NULL,           NULL,
16228 /* 24 */        NULL,           NULL,           NULL,           NULL,
16229 /* 28 */        NULL,           NULL,           NULL,           NULL,
16230 /* 2C */        NULL,           NULL,           NULL,           NULL,
16231 /* 30 */        NULL,           NULL,           NULL,           NULL,
16232 /* 34 */        NULL,           NULL,           NULL,           NULL,
16233 /* 38 */        NULL,           NULL,           NULL,           NULL,
16234 /* 3C */        NULL,           NULL,           NULL,           NULL,
16235 /* 40 */        NULL,           NULL,           NULL,           NULL,
16236 /* 44 */        NULL,           NULL,           NULL,           NULL,
16237 /* 48 */        NULL,           NULL,           NULL,           NULL,
16238 /* 4C */        NULL,           NULL,           NULL,           NULL,
16239 /* 50 */        NULL,           NULL,           NULL,           NULL,
16240 /* 54 */        NULL,           NULL,           NULL,           NULL,
16241 /* 58 */        NULL,           NULL,           NULL,           NULL,
16242 /* 5C */        NULL,           NULL,           NULL,           NULL,
16243 /* 60 */        NULL,           NULL,           NULL,           NULL,
16244 /* 64 */        NULL,           NULL,           NULL,           NULL,
16245 /* 68 */        NULL,           NULL,           NULL,           NULL,
16246 /* 6C */        NULL,           NULL,           NULL,           NULL,
16247 /* 70 */        NULL,           NULL,           NULL,           NULL,
16248 /* 74 */        NULL,           NULL,           NULL,           NULL,
16249 /* 78 */        NULL,           NULL,           NULL,           NULL,
16250 /* 7C */        NULL,           NULL,           NULL,           NULL,
16251 /* 80 */        NULL,           NULL,           NULL,           NULL,
16252 /* 84 */        NULL,           NULL,           NULL,           NULL,
16253 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16254 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16255 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16256 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16257 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16258 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16259 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16260 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16261 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16262 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16263 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16264 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16265 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16266 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16267 /* C0 */        NULL,           NULL,           NULL,           NULL,
16268 /* C4 */        NULL,           NULL,           NULL,           NULL,
16269 /* C8 */        NULL,           NULL,           NULL,           NULL,
16270 /* CC */        NULL,           NULL,           NULL,           NULL,
16271 /* D0 */        NULL,           NULL,           NULL,           NULL,
16272 /* D4 */        NULL,           NULL,           NULL,           NULL,
16273 /* D8 */        NULL,           NULL,           NULL,           NULL,
16274 /* DC */        NULL,           NULL,           NULL,           NULL,
16275 /* E0 */        NULL,           NULL,           NULL,           NULL,
16276 /* E4 */        NULL,           NULL,           NULL,           NULL,
16277 /* E8 */        NULL,           NULL,           NULL,           NULL,
16278 /* EC */        NULL,           NULL,           NULL,           NULL,
16279 /* F0 */        NULL,           NULL,           NULL,           NULL,
16280 /* F4 */        NULL,           NULL,           NULL,           NULL,
16281 /* F8 */        NULL,           NULL,           NULL,           NULL,
16282 /* FC */        NULL,           NULL,           NULL,           NULL,
16283 };
16284
16285 static void
16286 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16287 {
16288   const char *mnemonic;
16289
16290   FETCH_DATA (the_info, codep + 1);
16291   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16292      place where an 8-bit immediate would normally go.  ie. the last
16293      byte of the instruction.  */
16294   obufp = mnemonicendp;
16295   mnemonic = Suffix3DNow[*codep++ & 0xff];
16296   if (mnemonic)
16297     oappend (mnemonic);
16298   else
16299     {
16300       /* Since a variable sized modrm/sib chunk is between the start
16301          of the opcode (0x0f0f) and the opcode suffix, we need to do
16302          all the modrm processing first, and don't know until now that
16303          we have a bad opcode.  This necessitates some cleaning up.  */
16304       op_out[0][0] = '\0';
16305       op_out[1][0] = '\0';
16306       BadOp ();
16307     }
16308   mnemonicendp = obufp;
16309 }
16310
16311 static struct op simd_cmp_op[] =
16312 {
16313   { STRING_COMMA_LEN ("eq") },
16314   { STRING_COMMA_LEN ("lt") },
16315   { STRING_COMMA_LEN ("le") },
16316   { STRING_COMMA_LEN ("unord") },
16317   { STRING_COMMA_LEN ("neq") },
16318   { STRING_COMMA_LEN ("nlt") },
16319   { STRING_COMMA_LEN ("nle") },
16320   { STRING_COMMA_LEN ("ord") }
16321 };
16322
16323 static void
16324 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16325 {
16326   unsigned int cmp_type;
16327
16328   FETCH_DATA (the_info, codep + 1);
16329   cmp_type = *codep++ & 0xff;
16330   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16331     {
16332       char suffix [3];
16333       char *p = mnemonicendp - 2;
16334       suffix[0] = p[0];
16335       suffix[1] = p[1];
16336       suffix[2] = '\0';
16337       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16338       mnemonicendp += simd_cmp_op[cmp_type].len;
16339     }
16340   else
16341     {
16342       /* We have a reserved extension byte.  Output it directly.  */
16343       scratchbuf[0] = '$';
16344       print_operand_value (scratchbuf + 1, 1, cmp_type);
16345       oappend_maybe_intel (scratchbuf);
16346       scratchbuf[0] = '\0';
16347     }
16348 }
16349
16350 static void
16351 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16352           int sizeflag ATTRIBUTE_UNUSED)
16353 {
16354   /* mwait %eax,%ecx  */
16355   if (!intel_syntax)
16356     {
16357       const char **names = (address_mode == mode_64bit
16358                             ? names64 : names32);
16359       strcpy (op_out[0], names[0]);
16360       strcpy (op_out[1], names[1]);
16361       two_source_ops = 1;
16362     }
16363   /* Skip mod/rm byte.  */
16364   MODRM_CHECK;
16365   codep++;
16366 }
16367
16368 static void
16369 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16370             int sizeflag ATTRIBUTE_UNUSED)
16371 {
16372   /* monitor %eax,%ecx,%edx"  */
16373   if (!intel_syntax)
16374     {
16375       const char **op1_names;
16376       const char **names = (address_mode == mode_64bit
16377                             ? names64 : names32);
16378
16379       if (!(prefixes & PREFIX_ADDR))
16380         op1_names = (address_mode == mode_16bit
16381                      ? names16 : names);
16382       else
16383         {
16384           /* Remove "addr16/addr32".  */
16385           all_prefixes[last_addr_prefix] = 0;
16386           op1_names = (address_mode != mode_32bit
16387                        ? names32 : names16);
16388           used_prefixes |= PREFIX_ADDR;
16389         }
16390       strcpy (op_out[0], op1_names[0]);
16391       strcpy (op_out[1], names[1]);
16392       strcpy (op_out[2], names[2]);
16393       two_source_ops = 1;
16394     }
16395   /* Skip mod/rm byte.  */
16396   MODRM_CHECK;
16397   codep++;
16398 }
16399
16400 static void
16401 BadOp (void)
16402 {
16403   /* Throw away prefixes and 1st. opcode byte.  */
16404   codep = insn_codep + 1;
16405   oappend ("(bad)");
16406 }
16407
16408 static void
16409 REP_Fixup (int bytemode, int sizeflag)
16410 {
16411   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16412      lods and stos.  */
16413   if (prefixes & PREFIX_REPZ)
16414     all_prefixes[last_repz_prefix] = REP_PREFIX;
16415
16416   switch (bytemode)
16417     {
16418     case al_reg:
16419     case eAX_reg:
16420     case indir_dx_reg:
16421       OP_IMREG (bytemode, sizeflag);
16422       break;
16423     case eDI_reg:
16424       OP_ESreg (bytemode, sizeflag);
16425       break;
16426     case eSI_reg:
16427       OP_DSreg (bytemode, sizeflag);
16428       break;
16429     default:
16430       abort ();
16431       break;
16432     }
16433 }
16434
16435 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16436    "bnd".  */
16437
16438 static void
16439 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16440 {
16441   if (prefixes & PREFIX_REPNZ)
16442     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16443 }
16444
16445 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16446    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16447  */
16448
16449 static void
16450 HLE_Fixup1 (int bytemode, int sizeflag)
16451 {
16452   if (modrm.mod != 3
16453       && (prefixes & PREFIX_LOCK) != 0)
16454     {
16455       if (prefixes & PREFIX_REPZ)
16456         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16457       if (prefixes & PREFIX_REPNZ)
16458         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16459     }
16460
16461   OP_E (bytemode, sizeflag);
16462 }
16463
16464 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16465    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16466  */
16467
16468 static void
16469 HLE_Fixup2 (int bytemode, int sizeflag)
16470 {
16471   if (modrm.mod != 3)
16472     {
16473       if (prefixes & PREFIX_REPZ)
16474         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16475       if (prefixes & PREFIX_REPNZ)
16476         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16477     }
16478
16479   OP_E (bytemode, sizeflag);
16480 }
16481
16482 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16483    "xrelease" for memory operand.  No check for LOCK prefix.   */
16484
16485 static void
16486 HLE_Fixup3 (int bytemode, int sizeflag)
16487 {
16488   if (modrm.mod != 3
16489       && last_repz_prefix > last_repnz_prefix
16490       && (prefixes & PREFIX_REPZ) != 0)
16491     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16492
16493   OP_E (bytemode, sizeflag);
16494 }
16495
16496 static void
16497 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16498 {
16499   USED_REX (REX_W);
16500   if (rex & REX_W)
16501     {
16502       /* Change cmpxchg8b to cmpxchg16b.  */
16503       char *p = mnemonicendp - 2;
16504       mnemonicendp = stpcpy (p, "16b");
16505       bytemode = o_mode;
16506     }
16507   else if ((prefixes & PREFIX_LOCK) != 0)
16508     {
16509       if (prefixes & PREFIX_REPZ)
16510         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16511       if (prefixes & PREFIX_REPNZ)
16512         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16513     }
16514
16515   OP_M (bytemode, sizeflag);
16516 }
16517
16518 static void
16519 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16520 {
16521   const char **names;
16522
16523   if (need_vex)
16524     {
16525       switch (vex.length)
16526         {
16527         case 128:
16528           names = names_xmm;
16529           break;
16530         case 256:
16531           names = names_ymm;
16532           break;
16533         default:
16534           abort ();
16535         }
16536     }
16537   else
16538     names = names_xmm;
16539   oappend (names[reg]);
16540 }
16541
16542 static void
16543 CRC32_Fixup (int bytemode, int sizeflag)
16544 {
16545   /* Add proper suffix to "crc32".  */
16546   char *p = mnemonicendp;
16547
16548   switch (bytemode)
16549     {
16550     case b_mode:
16551       if (intel_syntax)
16552         goto skip;
16553
16554       *p++ = 'b';
16555       break;
16556     case v_mode:
16557       if (intel_syntax)
16558         goto skip;
16559
16560       USED_REX (REX_W);
16561       if (rex & REX_W)
16562         *p++ = 'q';
16563       else
16564         {
16565           if (sizeflag & DFLAG)
16566             *p++ = 'l';
16567           else
16568             *p++ = 'w';
16569           used_prefixes |= (prefixes & PREFIX_DATA);
16570         }
16571       break;
16572     default:
16573       oappend (INTERNAL_DISASSEMBLER_ERROR);
16574       break;
16575     }
16576   mnemonicendp = p;
16577   *p = '\0';
16578
16579 skip:
16580   if (modrm.mod == 3)
16581     {
16582       int add;
16583
16584       /* Skip mod/rm byte.  */
16585       MODRM_CHECK;
16586       codep++;
16587
16588       USED_REX (REX_B);
16589       add = (rex & REX_B) ? 8 : 0;
16590       if (bytemode == b_mode)
16591         {
16592           USED_REX (0);
16593           if (rex)
16594             oappend (names8rex[modrm.rm + add]);
16595           else
16596             oappend (names8[modrm.rm + add]);
16597         }
16598       else
16599         {
16600           USED_REX (REX_W);
16601           if (rex & REX_W)
16602             oappend (names64[modrm.rm + add]);
16603           else if ((prefixes & PREFIX_DATA))
16604             oappend (names16[modrm.rm + add]);
16605           else
16606             oappend (names32[modrm.rm + add]);
16607         }
16608     }
16609   else
16610     OP_E (bytemode, sizeflag);
16611 }
16612
16613 static void
16614 FXSAVE_Fixup (int bytemode, int sizeflag)
16615 {
16616   /* Add proper suffix to "fxsave" and "fxrstor".  */
16617   USED_REX (REX_W);
16618   if (rex & REX_W)
16619     {
16620       char *p = mnemonicendp;
16621       *p++ = '6';
16622       *p++ = '4';
16623       *p = '\0';
16624       mnemonicendp = p;
16625     }
16626   OP_M (bytemode, sizeflag);
16627 }
16628
16629 /* Display the destination register operand for instructions with
16630    VEX. */
16631
16632 static void
16633 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16634 {
16635   int reg;
16636   const char **names;
16637
16638   if (!need_vex)
16639     abort ();
16640
16641   if (!need_vex_reg)
16642     return;
16643
16644   reg = vex.register_specifier;
16645   if (vex.evex)
16646     {
16647       if (!vex.v)
16648         reg += 16;
16649     }
16650
16651   if (bytemode == vex_scalar_mode)
16652     {
16653       oappend (names_xmm[reg]);
16654       return;
16655     }
16656
16657   switch (vex.length)
16658     {
16659     case 128:
16660       switch (bytemode)
16661         {
16662         case vex_mode:
16663         case vex128_mode:
16664         case vex_vsib_q_w_dq_mode:
16665         case vex_vsib_q_w_d_mode:
16666           names = names_xmm;
16667           break;
16668         case dq_mode:
16669           if (vex.w)
16670             names = names64;
16671           else
16672             names = names32;
16673           break;
16674         case mask_bd_mode:
16675         case mask_mode:
16676           names = names_mask;
16677           break;
16678         default:
16679           abort ();
16680           return;
16681         }
16682       break;
16683     case 256:
16684       switch (bytemode)
16685         {
16686         case vex_mode:
16687         case vex256_mode:
16688           names = names_ymm;
16689           break;
16690         case vex_vsib_q_w_dq_mode:
16691         case vex_vsib_q_w_d_mode:
16692           names = vex.w ? names_ymm : names_xmm;
16693           break;
16694         case mask_bd_mode:
16695         case mask_mode:
16696           names = names_mask;
16697           break;
16698         default:
16699           abort ();
16700           return;
16701         }
16702       break;
16703     case 512:
16704       names = names_zmm;
16705       break;
16706     default:
16707       abort ();
16708       break;
16709     }
16710   oappend (names[reg]);
16711 }
16712
16713 /* Get the VEX immediate byte without moving codep.  */
16714
16715 static unsigned char
16716 get_vex_imm8 (int sizeflag, int opnum)
16717 {
16718   int bytes_before_imm = 0;
16719
16720   if (modrm.mod != 3)
16721     {
16722       /* There are SIB/displacement bytes.  */
16723       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16724         {
16725           /* 32/64 bit address mode */
16726           int base = modrm.rm;
16727
16728           /* Check SIB byte.  */
16729           if (base == 4)
16730             {
16731               FETCH_DATA (the_info, codep + 1);
16732               base = *codep & 7;
16733               /* When decoding the third source, don't increase
16734                  bytes_before_imm as this has already been incremented
16735                  by one in OP_E_memory while decoding the second
16736                  source operand.  */
16737               if (opnum == 0)
16738                 bytes_before_imm++;
16739             }
16740
16741           /* Don't increase bytes_before_imm when decoding the third source,
16742              it has already been incremented by OP_E_memory while decoding
16743              the second source operand.  */
16744           if (opnum == 0)
16745             {
16746               switch (modrm.mod)
16747                 {
16748                   case 0:
16749                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16750                        SIB == 5, there is a 4 byte displacement.  */
16751                     if (base != 5)
16752                       /* No displacement. */
16753                       break;
16754                   case 2:
16755                     /* 4 byte displacement.  */
16756                     bytes_before_imm += 4;
16757                     break;
16758                   case 1:
16759                     /* 1 byte displacement.  */
16760                     bytes_before_imm++;
16761                     break;
16762                 }
16763             }
16764         }
16765       else
16766         {
16767           /* 16 bit address mode */
16768           /* Don't increase bytes_before_imm when decoding the third source,
16769              it has already been incremented by OP_E_memory while decoding
16770              the second source operand.  */
16771           if (opnum == 0)
16772             {
16773               switch (modrm.mod)
16774                 {
16775                 case 0:
16776                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16777                   if (modrm.rm != 6)
16778                     /* No displacement. */
16779                     break;
16780                 case 2:
16781                   /* 2 byte displacement.  */
16782                   bytes_before_imm += 2;
16783                   break;
16784                 case 1:
16785                   /* 1 byte displacement: when decoding the third source,
16786                      don't increase bytes_before_imm as this has already
16787                      been incremented by one in OP_E_memory while decoding
16788                      the second source operand.  */
16789                   if (opnum == 0)
16790                     bytes_before_imm++;
16791
16792                   break;
16793                 }
16794             }
16795         }
16796     }
16797
16798   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16799   return codep [bytes_before_imm];
16800 }
16801
16802 static void
16803 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16804 {
16805   const char **names;
16806
16807   if (reg == -1 && modrm.mod != 3)
16808     {
16809       OP_E_memory (bytemode, sizeflag);
16810       return;
16811     }
16812   else
16813     {
16814       if (reg == -1)
16815         {
16816           reg = modrm.rm;
16817           USED_REX (REX_B);
16818           if (rex & REX_B)
16819             reg += 8;
16820         }
16821       else if (reg > 7 && address_mode != mode_64bit)
16822         BadOp ();
16823     }
16824
16825   switch (vex.length)
16826     {
16827     case 128:
16828       names = names_xmm;
16829       break;
16830     case 256:
16831       names = names_ymm;
16832       break;
16833     default:
16834       abort ();
16835     }
16836   oappend (names[reg]);
16837 }
16838
16839 static void
16840 OP_EX_VexImmW (int bytemode, int sizeflag)
16841 {
16842   int reg = -1;
16843   static unsigned char vex_imm8;
16844
16845   if (vex_w_done == 0)
16846     {
16847       vex_w_done = 1;
16848
16849       /* Skip mod/rm byte.  */
16850       MODRM_CHECK;
16851       codep++;
16852
16853       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16854
16855       if (vex.w)
16856           reg = vex_imm8 >> 4;
16857
16858       OP_EX_VexReg (bytemode, sizeflag, reg);
16859     }
16860   else if (vex_w_done == 1)
16861     {
16862       vex_w_done = 2;
16863
16864       if (!vex.w)
16865           reg = vex_imm8 >> 4;
16866
16867       OP_EX_VexReg (bytemode, sizeflag, reg);
16868     }
16869   else
16870     {
16871       /* Output the imm8 directly.  */
16872       scratchbuf[0] = '$';
16873       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16874       oappend_maybe_intel (scratchbuf);
16875       scratchbuf[0] = '\0';
16876       codep++;
16877     }
16878 }
16879
16880 static void
16881 OP_Vex_2src (int bytemode, int sizeflag)
16882 {
16883   if (modrm.mod == 3)
16884     {
16885       int reg = modrm.rm;
16886       USED_REX (REX_B);
16887       if (rex & REX_B)
16888         reg += 8;
16889       oappend (names_xmm[reg]);
16890     }
16891   else
16892     {
16893       if (intel_syntax
16894           && (bytemode == v_mode || bytemode == v_swap_mode))
16895         {
16896           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16897           used_prefixes |= (prefixes & PREFIX_DATA);
16898         }
16899       OP_E (bytemode, sizeflag);
16900     }
16901 }
16902
16903 static void
16904 OP_Vex_2src_1 (int bytemode, int sizeflag)
16905 {
16906   if (modrm.mod == 3)
16907     {
16908       /* Skip mod/rm byte.   */
16909       MODRM_CHECK;
16910       codep++;
16911     }
16912
16913   if (vex.w)
16914     oappend (names_xmm[vex.register_specifier]);
16915   else
16916     OP_Vex_2src (bytemode, sizeflag);
16917 }
16918
16919 static void
16920 OP_Vex_2src_2 (int bytemode, int sizeflag)
16921 {
16922   if (vex.w)
16923     OP_Vex_2src (bytemode, sizeflag);
16924   else
16925     oappend (names_xmm[vex.register_specifier]);
16926 }
16927
16928 static void
16929 OP_EX_VexW (int bytemode, int sizeflag)
16930 {
16931   int reg = -1;
16932
16933   if (!vex_w_done)
16934     {
16935       vex_w_done = 1;
16936
16937       /* Skip mod/rm byte.  */
16938       MODRM_CHECK;
16939       codep++;
16940
16941       if (vex.w)
16942         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16943     }
16944   else
16945     {
16946       if (!vex.w)
16947         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16948     }
16949
16950   OP_EX_VexReg (bytemode, sizeflag, reg);
16951 }
16952
16953 static void
16954 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16955              int sizeflag ATTRIBUTE_UNUSED)
16956 {
16957   /* Skip the immediate byte and check for invalid bits.  */
16958   FETCH_DATA (the_info, codep + 1);
16959   if (*codep++ & 0xf)
16960     BadOp ();
16961 }
16962
16963 static void
16964 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16965 {
16966   int reg;
16967   const char **names;
16968
16969   FETCH_DATA (the_info, codep + 1);
16970   reg = *codep++;
16971
16972   if (bytemode != x_mode)
16973     abort ();
16974
16975   if (reg & 0xf)
16976       BadOp ();
16977
16978   reg >>= 4;
16979   if (reg > 7 && address_mode != mode_64bit)
16980     BadOp ();
16981
16982   switch (vex.length)
16983     {
16984     case 128:
16985       names = names_xmm;
16986       break;
16987     case 256:
16988       names = names_ymm;
16989       break;
16990     default:
16991       abort ();
16992     }
16993   oappend (names[reg]);
16994 }
16995
16996 static void
16997 OP_XMM_VexW (int bytemode, int sizeflag)
16998 {
16999   /* Turn off the REX.W bit since it is used for swapping operands
17000      now.  */
17001   rex &= ~REX_W;
17002   OP_XMM (bytemode, sizeflag);
17003 }
17004
17005 static void
17006 OP_EX_Vex (int bytemode, int sizeflag)
17007 {
17008   if (modrm.mod != 3)
17009     {
17010       if (vex.register_specifier != 0)
17011         BadOp ();
17012       need_vex_reg = 0;
17013     }
17014   OP_EX (bytemode, sizeflag);
17015 }
17016
17017 static void
17018 OP_XMM_Vex (int bytemode, int sizeflag)
17019 {
17020   if (modrm.mod != 3)
17021     {
17022       if (vex.register_specifier != 0)
17023         BadOp ();
17024       need_vex_reg = 0;
17025     }
17026   OP_XMM (bytemode, sizeflag);
17027 }
17028
17029 static void
17030 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17031 {
17032   switch (vex.length)
17033     {
17034     case 128:
17035       mnemonicendp = stpcpy (obuf, "vzeroupper");
17036       break;
17037     case 256:
17038       mnemonicendp = stpcpy (obuf, "vzeroall");
17039       break;
17040     default:
17041       abort ();
17042     }
17043 }
17044
17045 static struct op vex_cmp_op[] =
17046 {
17047   { STRING_COMMA_LEN ("eq") },
17048   { STRING_COMMA_LEN ("lt") },
17049   { STRING_COMMA_LEN ("le") },
17050   { STRING_COMMA_LEN ("unord") },
17051   { STRING_COMMA_LEN ("neq") },
17052   { STRING_COMMA_LEN ("nlt") },
17053   { STRING_COMMA_LEN ("nle") },
17054   { STRING_COMMA_LEN ("ord") },
17055   { STRING_COMMA_LEN ("eq_uq") },
17056   { STRING_COMMA_LEN ("nge") },
17057   { STRING_COMMA_LEN ("ngt") },
17058   { STRING_COMMA_LEN ("false") },
17059   { STRING_COMMA_LEN ("neq_oq") },
17060   { STRING_COMMA_LEN ("ge") },
17061   { STRING_COMMA_LEN ("gt") },
17062   { STRING_COMMA_LEN ("true") },
17063   { STRING_COMMA_LEN ("eq_os") },
17064   { STRING_COMMA_LEN ("lt_oq") },
17065   { STRING_COMMA_LEN ("le_oq") },
17066   { STRING_COMMA_LEN ("unord_s") },
17067   { STRING_COMMA_LEN ("neq_us") },
17068   { STRING_COMMA_LEN ("nlt_uq") },
17069   { STRING_COMMA_LEN ("nle_uq") },
17070   { STRING_COMMA_LEN ("ord_s") },
17071   { STRING_COMMA_LEN ("eq_us") },
17072   { STRING_COMMA_LEN ("nge_uq") },
17073   { STRING_COMMA_LEN ("ngt_uq") },
17074   { STRING_COMMA_LEN ("false_os") },
17075   { STRING_COMMA_LEN ("neq_os") },
17076   { STRING_COMMA_LEN ("ge_oq") },
17077   { STRING_COMMA_LEN ("gt_oq") },
17078   { STRING_COMMA_LEN ("true_us") },
17079 };
17080
17081 static void
17082 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17083 {
17084   unsigned int cmp_type;
17085
17086   FETCH_DATA (the_info, codep + 1);
17087   cmp_type = *codep++ & 0xff;
17088   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17089     {
17090       char suffix [3];
17091       char *p = mnemonicendp - 2;
17092       suffix[0] = p[0];
17093       suffix[1] = p[1];
17094       suffix[2] = '\0';
17095       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17096       mnemonicendp += vex_cmp_op[cmp_type].len;
17097     }
17098   else
17099     {
17100       /* We have a reserved extension byte.  Output it directly.  */
17101       scratchbuf[0] = '$';
17102       print_operand_value (scratchbuf + 1, 1, cmp_type);
17103       oappend_maybe_intel (scratchbuf);
17104       scratchbuf[0] = '\0';
17105     }
17106 }
17107
17108 static void
17109 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17110              int sizeflag ATTRIBUTE_UNUSED)
17111 {
17112   unsigned int cmp_type;
17113
17114   if (!vex.evex)
17115     abort ();
17116
17117   FETCH_DATA (the_info, codep + 1);
17118   cmp_type = *codep++ & 0xff;
17119   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17120      If it's the case, print suffix, otherwise - print the immediate.  */
17121   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17122       && cmp_type != 3
17123       && cmp_type != 7)
17124     {
17125       char suffix [3];
17126       char *p = mnemonicendp - 2;
17127
17128       /* vpcmp* can have both one- and two-lettered suffix.  */
17129       if (p[0] == 'p')
17130         {
17131           p++;
17132           suffix[0] = p[0];
17133           suffix[1] = '\0';
17134         }
17135       else
17136         {
17137           suffix[0] = p[0];
17138           suffix[1] = p[1];
17139           suffix[2] = '\0';
17140         }
17141
17142       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17143       mnemonicendp += simd_cmp_op[cmp_type].len;
17144     }
17145   else
17146     {
17147       /* We have a reserved extension byte.  Output it directly.  */
17148       scratchbuf[0] = '$';
17149       print_operand_value (scratchbuf + 1, 1, cmp_type);
17150       oappend_maybe_intel (scratchbuf);
17151       scratchbuf[0] = '\0';
17152     }
17153 }
17154
17155 static const struct op pclmul_op[] =
17156 {
17157   { STRING_COMMA_LEN ("lql") },
17158   { STRING_COMMA_LEN ("hql") },
17159   { STRING_COMMA_LEN ("lqh") },
17160   { STRING_COMMA_LEN ("hqh") }
17161 };
17162
17163 static void
17164 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17165               int sizeflag ATTRIBUTE_UNUSED)
17166 {
17167   unsigned int pclmul_type;
17168
17169   FETCH_DATA (the_info, codep + 1);
17170   pclmul_type = *codep++ & 0xff;
17171   switch (pclmul_type)
17172     {
17173     case 0x10:
17174       pclmul_type = 2;
17175       break;
17176     case 0x11:
17177       pclmul_type = 3;
17178       break;
17179     default:
17180       break;
17181     }
17182   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17183     {
17184       char suffix [4];
17185       char *p = mnemonicendp - 3;
17186       suffix[0] = p[0];
17187       suffix[1] = p[1];
17188       suffix[2] = p[2];
17189       suffix[3] = '\0';
17190       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17191       mnemonicendp += pclmul_op[pclmul_type].len;
17192     }
17193   else
17194     {
17195       /* We have a reserved extension byte.  Output it directly.  */
17196       scratchbuf[0] = '$';
17197       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17198       oappend_maybe_intel (scratchbuf);
17199       scratchbuf[0] = '\0';
17200     }
17201 }
17202
17203 static void
17204 MOVBE_Fixup (int bytemode, int sizeflag)
17205 {
17206   /* Add proper suffix to "movbe".  */
17207   char *p = mnemonicendp;
17208
17209   switch (bytemode)
17210     {
17211     case v_mode:
17212       if (intel_syntax)
17213         goto skip;
17214
17215       USED_REX (REX_W);
17216       if (sizeflag & SUFFIX_ALWAYS)
17217         {
17218           if (rex & REX_W)
17219             *p++ = 'q';
17220           else
17221             {
17222               if (sizeflag & DFLAG)
17223                 *p++ = 'l';
17224               else
17225                 *p++ = 'w';
17226               used_prefixes |= (prefixes & PREFIX_DATA);
17227             }
17228         }
17229       break;
17230     default:
17231       oappend (INTERNAL_DISASSEMBLER_ERROR);
17232       break;
17233     }
17234   mnemonicendp = p;
17235   *p = '\0';
17236
17237 skip:
17238   OP_M (bytemode, sizeflag);
17239 }
17240
17241 static void
17242 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17243 {
17244   int reg;
17245   const char **names;
17246
17247   /* Skip mod/rm byte.  */
17248   MODRM_CHECK;
17249   codep++;
17250
17251   if (vex.w)
17252     names = names64;
17253   else
17254     names = names32;
17255
17256   reg = modrm.rm;
17257   USED_REX (REX_B);
17258   if (rex & REX_B)
17259     reg += 8;
17260
17261   oappend (names[reg]);
17262 }
17263
17264 static void
17265 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17266 {
17267   const char **names;
17268
17269   if (vex.w)
17270     names = names64;
17271   else
17272     names = names32;
17273
17274   oappend (names[vex.register_specifier]);
17275 }
17276
17277 static void
17278 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17279 {
17280   if (!vex.evex
17281       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17282     abort ();
17283
17284   USED_REX (REX_R);
17285   if ((rex & REX_R) != 0 || !vex.r)
17286     {
17287       BadOp ();
17288       return;
17289     }
17290
17291   oappend (names_mask [modrm.reg]);
17292 }
17293
17294 static void
17295 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17296 {
17297   if (!vex.evex
17298       || (bytemode != evex_rounding_mode
17299           && bytemode != evex_sae_mode))
17300     abort ();
17301   if (modrm.mod == 3 && vex.b)
17302     switch (bytemode)
17303       {
17304       case evex_rounding_mode:
17305         oappend (names_rounding[vex.ll]);
17306         break;
17307       case evex_sae_mode:
17308         oappend ("{sae}");
17309         break;
17310       default:
17311         break;
17312       }
17313 }