opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int fetch_data (struct disassemble_info *, bfd_byte *);
  46 static void ckprefix (void);
  47 static const char *prefix_name (int, int);
  48 static int print_insn (bfd_vma, disassemble_info *);
  49 static void dofloat (int);
  50 static void OP_ST (int, int);
  51 static void OP_STi (int, int);
  52 static int putop (const char *, int);
  53 static void oappend (const char *);
  54 static void append_seg (void);
  55 static void OP_indirE (int, int);
  56 static void print_operand_value (char *, int, bfd_vma);
  57 static void OP_E_register (int, int);
  58 static void OP_E_memory (int, int, int);
  59 static void OP_E_extended (int, int, int);
  60 static void print_displacement (char *, bfd_vma);
  61 static void OP_E (int, int);
  62 static void OP_G (int, int);
  63 static bfd_vma get64 (void);
  64 static bfd_signed_vma get32 (void);
  65 static bfd_signed_vma get32s (void);
  66 static int get16 (void);
  67 static void set_op (bfd_vma, int);
  68 static void OP_Skip_MODRM (int, int);
  69 static void OP_REG (int, int);
  70 static void OP_IMREG (int, int);
  71 static void OP_I (int, int);
  72 static void OP_I64 (int, int);
  73 static void OP_sI (int, int);
  74 static void OP_J (int, int);
  75 static void OP_SEG (int, int);
  76 static void OP_DIR (int, int);
  77 static void OP_OFF (int, int);
  78 static void OP_OFF64 (int, int);
  79 static void ptr_reg (int, int);
  80 static void OP_ESreg (int, int);
  81 static void OP_DSreg (int, int);
  82 static void OP_C (int, int);
  83 static void OP_D (int, int);
  84 static void OP_T (int, int);
  85 static void OP_R (int, int);
  86 static void OP_MMX (int, int);
  87 static void OP_XMM (int, int);
  88 static void OP_EM (int, int);
  89 static void OP_EX (int, int);
  90 static void OP_EMC (int,int);
  91 static void OP_MXC (int,int);
  92 static void OP_MS (int, int);
  93 static void OP_XS (int, int);
  94 static void OP_M (int, int);
  95 static void OP_VEX (int, int);
  96 static void OP_VEX_FMA (int, int);
  97 static void OP_EX_Vex (int, int);
  98 static void OP_EX_VexW (int, int);
  99 static void OP_EX_VexImmW (int, int);
 100 static void OP_XMM_Vex (int, int);
 101 static void OP_XMM_VexW (int, int);
 102 static void OP_REG_VexI4 (int, int);
 103 static void PCLMUL_Fixup (int, int);
 104 static void VEXI4_Fixup (int, int);
 105 static void VZERO_Fixup (int, int);
 106 static void VCMP_Fixup (int, int);
 107 static void VPERMIL2_Fixup (int, int);
 108 static void OP_0f07 (int, int);
 109 static void OP_Monitor (int, int);
 110 static void OP_Mwait (int, int);
 111 static void NOP_Fixup1 (int, int);
 112 static void NOP_Fixup2 (int, int);
 113 static void OP_3DNowSuffix (int, int);
 114 static void CMP_Fixup (int, int);
 115 static void BadOp (void);
 116 static void REP_Fixup (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void print_drex_arg (unsigned int, int, int);
 121 static void OP_DREX4 (int, int);
 122 static void OP_DREX3 (int, int);
 123 static void OP_DREX_ICMP (int, int);
 124 static void OP_DREX_FCMP (int, int);
 125 static void MOVBE_Fixup (int, int);
 126
 127 struct dis_private {
 128   /* Points to first byte not fetched.  */
 129   bfd_byte *max_fetched;
 130   bfd_byte the_buffer[MAX_MNEM_SIZE];
 131   bfd_vma insn_start;
 132   int orig_sizeflag;
 133   jmp_buf bailout;
 134 };
 135
 136 enum address_mode
 137 {
 138   mode_16bit,
 139   mode_32bit,
 140   mode_64bit
 141 };
 142
 143 enum address_mode address_mode;
 144
 145 /* Flags for the prefixes for the current instruction.  See below.  */
 146 static int prefixes;
 147
 148 /* REX prefix the current instruction.  See below.  */
 149 static int rex;
 150 /* Bits of REX we've already used.  */
 151 static int rex_used;
 152 /* Original REX prefix.  */
 153 static int rex_original;
 154 /* REX bits in original REX prefix ignored.  It may not be the same
 155    as rex_original since some bits may not be ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Special 'registers' for DREX handling */
 173 #define DREX_REG_UNKNOWN        1000    /* not initialized */
 174 #define DREX_REG_MEMORY         1001    /* use MODRM/SIB/OFFSET memory */
 175
 176 /* The DREX byte has the following fields:
 177    Bits 7-4 -- DREX.Dest, xmm destination register
 178    Bit 3    -- DREX.OC0, operand config bit defines operand order
 179    Bit 2    -- DREX.R, equivalent to REX_R bit, to extend ModRM register
 180    Bit 1    -- DREX.X, equivalent to REX_X bit, to extend SIB index field
 181    Bit 0    -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
 182                SIB base field, or opcode reg field.  */
 183 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
 184 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
 185
 186 /* Flags for prefixes which we somehow handled when printing the
 187    current instruction.  */
 188 static int used_prefixes;
 189
 190 /* Flags stored in PREFIXES.  */
 191 #define PREFIX_REPZ 1
 192 #define PREFIX_REPNZ 2
 193 #define PREFIX_LOCK 4
 194 #define PREFIX_CS 8
 195 #define PREFIX_SS 0x10
 196 #define PREFIX_DS 0x20
 197 #define PREFIX_ES 0x40
 198 #define PREFIX_FS 0x80
 199 #define PREFIX_GS 0x100
 200 #define PREFIX_DATA 0x200
 201 #define PREFIX_ADDR 0x400
 202 #define PREFIX_FWAIT 0x800
 203
 204 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 205    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 206    on error.  */
 207 #define FETCH_DATA(info, addr) \
 208   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 209    ? 1 : fetch_data ((info), (addr)))
 210
 211 static int
 212 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 213 {
 214   int status;
 215   struct dis_private *priv = (struct dis_private *) info->private_data;
 216   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 217
 218   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 219     status = (*info->read_memory_func) (start,
 220                                         priv->max_fetched,
 221                                         addr - priv->max_fetched,
 222                                         info);
 223   else
 224     status = -1;
 225   if (status != 0)
 226     {
 227       /* If we did manage to read at least one byte, then
 228          print_insn_i386 will do something sensible.  Otherwise, print
 229          an error.  We do that here because this is where we know
 230          STATUS.  */
 231       if (priv->max_fetched == priv->the_buffer)
 232         (*info->memory_error_func) (status, start, info);
 233       longjmp (priv->bailout, 1);
 234     }
 235   else
 236     priv->max_fetched = addr;
 237   return 1;
 238 }
 239
 240 #define XX { NULL, 0 }
 241
 242 #define Eb { OP_E, b_mode }
 243 #define Ev { OP_E, v_mode }
 244 #define Ed { OP_E, d_mode }
 245 #define Edq { OP_E, dq_mode }
 246 #define Edqw { OP_E, dqw_mode }
 247 #define Edqb { OP_E, dqb_mode }
 248 #define Edqd { OP_E, dqd_mode }
 249 #define Eq { OP_E, q_mode }
 250 #define indirEv { OP_indirE, stack_v_mode }
 251 #define indirEp { OP_indirE, f_mode }
 252 #define stackEv { OP_E, stack_v_mode }
 253 #define Em { OP_E, m_mode }
 254 #define Ew { OP_E, w_mode }
 255 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 256 #define Ma { OP_M, a_mode }
 257 #define Mb { OP_M, b_mode }
 258 #define Md { OP_M, d_mode }
 259 #define Mo { OP_M, o_mode }
 260 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 261 #define Mq { OP_M, q_mode }
 262 #define Mx { OP_M, x_mode }
 263 #define Mxmm { OP_M, xmm_mode }
 264 #define Gb { OP_G, b_mode }
 265 #define Gv { OP_G, v_mode }
 266 #define Gd { OP_G, d_mode }
 267 #define Gdq { OP_G, dq_mode }
 268 #define Gm { OP_G, m_mode }
 269 #define Gw { OP_G, w_mode }
 270 #define Rd { OP_R, d_mode }
 271 #define Rm { OP_R, m_mode }
 272 #define Ib { OP_I, b_mode }
 273 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 274 #define Iv { OP_I, v_mode }
 275 #define Iq { OP_I, q_mode }
 276 #define Iv64 { OP_I64, v_mode }
 277 #define Iw { OP_I, w_mode }
 278 #define I1 { OP_I, const_1_mode }
 279 #define Jb { OP_J, b_mode }
 280 #define Jv { OP_J, v_mode }
 281 #define Cm { OP_C, m_mode }
 282 #define Dm { OP_D, m_mode }
 283 #define Td { OP_T, d_mode }
 284 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 285
 286 #define RMeAX { OP_REG, eAX_reg }
 287 #define RMeBX { OP_REG, eBX_reg }
 288 #define RMeCX { OP_REG, eCX_reg }
 289 #define RMeDX { OP_REG, eDX_reg }
 290 #define RMeSP { OP_REG, eSP_reg }
 291 #define RMeBP { OP_REG, eBP_reg }
 292 #define RMeSI { OP_REG, eSI_reg }
 293 #define RMeDI { OP_REG, eDI_reg }
 294 #define RMrAX { OP_REG, rAX_reg }
 295 #define RMrBX { OP_REG, rBX_reg }
 296 #define RMrCX { OP_REG, rCX_reg }
 297 #define RMrDX { OP_REG, rDX_reg }
 298 #define RMrSP { OP_REG, rSP_reg }
 299 #define RMrBP { OP_REG, rBP_reg }
 300 #define RMrSI { OP_REG, rSI_reg }
 301 #define RMrDI { OP_REG, rDI_reg }
 302 #define RMAL { OP_REG, al_reg }
 303 #define RMAL { OP_REG, al_reg }
 304 #define RMCL { OP_REG, cl_reg }
 305 #define RMDL { OP_REG, dl_reg }
 306 #define RMBL { OP_REG, bl_reg }
 307 #define RMAH { OP_REG, ah_reg }
 308 #define RMCH { OP_REG, ch_reg }
 309 #define RMDH { OP_REG, dh_reg }
 310 #define RMBH { OP_REG, bh_reg }
 311 #define RMAX { OP_REG, ax_reg }
 312 #define RMDX { OP_REG, dx_reg }
 313
 314 #define eAX { OP_IMREG, eAX_reg }
 315 #define eBX { OP_IMREG, eBX_reg }
 316 #define eCX { OP_IMREG, eCX_reg }
 317 #define eDX { OP_IMREG, eDX_reg }
 318 #define eSP { OP_IMREG, eSP_reg }
 319 #define eBP { OP_IMREG, eBP_reg }
 320 #define eSI { OP_IMREG, eSI_reg }
 321 #define eDI { OP_IMREG, eDI_reg }
 322 #define AL { OP_IMREG, al_reg }
 323 #define CL { OP_IMREG, cl_reg }
 324 #define DL { OP_IMREG, dl_reg }
 325 #define BL { OP_IMREG, bl_reg }
 326 #define AH { OP_IMREG, ah_reg }
 327 #define CH { OP_IMREG, ch_reg }
 328 #define DH { OP_IMREG, dh_reg }
 329 #define BH { OP_IMREG, bh_reg }
 330 #define AX { OP_IMREG, ax_reg }
 331 #define DX { OP_IMREG, dx_reg }
 332 #define zAX { OP_IMREG, z_mode_ax_reg }
 333 #define indirDX { OP_IMREG, indir_dx_reg }
 334
 335 #define Sw { OP_SEG, w_mode }
 336 #define Sv { OP_SEG, v_mode }
 337 #define Ap { OP_DIR, 0 }
 338 #define Ob { OP_OFF64, b_mode }
 339 #define Ov { OP_OFF64, v_mode }
 340 #define Xb { OP_DSreg, eSI_reg }
 341 #define Xv { OP_DSreg, eSI_reg }
 342 #define Xz { OP_DSreg, eSI_reg }
 343 #define Yb { OP_ESreg, eDI_reg }
 344 #define Yv { OP_ESreg, eDI_reg }
 345 #define DSBX { OP_DSreg, eBX_reg }
 346
 347 #define es { OP_REG, es_reg }
 348 #define ss { OP_REG, ss_reg }
 349 #define cs { OP_REG, cs_reg }
 350 #define ds { OP_REG, ds_reg }
 351 #define fs { OP_REG, fs_reg }
 352 #define gs { OP_REG, gs_reg }
 353
 354 #define MX { OP_MMX, 0 }
 355 #define XM { OP_XMM, 0 }
 356 #define XMM { OP_XMM, xmm_mode }
 357 #define EM { OP_EM, v_mode }
 358 #define EMd { OP_EM, d_mode }
 359 #define EMx { OP_EM, x_mode }
 360 #define EXw { OP_EX, w_mode }
 361 #define EXd { OP_EX, d_mode }
 362 #define EXq { OP_EX, q_mode }
 363 #define EXx { OP_EX, x_mode }
 364 #define EXxmm { OP_EX, xmm_mode }
 365 #define EXxmmq { OP_EX, xmmq_mode }
 366 #define EXymmq { OP_EX, ymmq_mode }
 367 #define MS { OP_MS, v_mode }
 368 #define XS { OP_XS, v_mode }
 369 #define EMCq { OP_EMC, q_mode }
 370 #define MXC { OP_MXC, 0 }
 371 #define OPSUF { OP_3DNowSuffix, 0 }
 372 #define CMP { CMP_Fixup, 0 }
 373 #define XMM0 { XMM_Fixup, 0 }
 374
 375 #define Vex { OP_VEX, vex_mode }
 376 #define Vex128 { OP_VEX, vex128_mode }
 377 #define Vex256 { OP_VEX, vex256_mode }
 378 #define VexI4 { VEXI4_Fixup, 0}
 379 #define VexFMA { OP_VEX_FMA, vex_mode }
 380 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
 381 #define EXdVex { OP_EX_Vex, d_mode }
 382 #define EXqVex { OP_EX_Vex, q_mode }
 383 #define EXVexW { OP_EX_VexW, x_mode }
 384 #define EXdVexW { OP_EX_VexW, d_mode }
 385 #define EXqVexW { OP_EX_VexW, q_mode }
 386 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 387 #define XMVex { OP_XMM_Vex, 0 }
 388 #define XMVexW { OP_XMM_VexW, 0 }
 389 #define XMVexI4 { OP_REG_VexI4, x_mode }
 390 #define PCLMUL { PCLMUL_Fixup, 0 }
 391 #define VZERO { VZERO_Fixup, 0 }
 392 #define VCMP { VCMP_Fixup, 0 }
 393 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
 394
 395 /* Used handle "rep" prefix for string instructions.  */
 396 #define Xbr { REP_Fixup, eSI_reg }
 397 #define Xvr { REP_Fixup, eSI_reg }
 398 #define Ybr { REP_Fixup, eDI_reg }
 399 #define Yvr { REP_Fixup, eDI_reg }
 400 #define Yzr { REP_Fixup, eDI_reg }
 401 #define indirDXr { REP_Fixup, indir_dx_reg }
 402 #define ALr { REP_Fixup, al_reg }
 403 #define eAXr { REP_Fixup, eAX_reg }
 404
 405 #define cond_jump_flag { NULL, cond_jump_mode }
 406 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 407
 408 /* bits in sizeflag */
 409 #define SUFFIX_ALWAYS 4
 410 #define AFLAG 2
 411 #define DFLAG 1
 412
 413 /* byte operand */
 414 #define b_mode                  1
 415 /* operand size depends on prefixes */
 416 #define v_mode                  (b_mode + 1)
 417 /* word operand */
 418 #define w_mode                  (v_mode + 1)
 419 /* double word operand  */
 420 #define d_mode                  (w_mode + 1)
 421 /* quad word operand */
 422 #define q_mode                  (d_mode + 1)
 423 /* ten-byte operand */
 424 #define t_mode                  (q_mode + 1)
 425 /* 16-byte XMM or 32-byte YMM operand */
 426 #define x_mode                  (t_mode + 1)
 427 /* 16-byte XMM operand */
 428 #define xmm_mode                (x_mode + 1)
 429 /* 16-byte XMM or quad word operand */
 430 #define xmmq_mode               (xmm_mode + 1)
 431 /* 32-byte YMM or quad word operand */
 432 #define ymmq_mode               (xmmq_mode + 1)
 433 /* d_mode in 32bit, q_mode in 64bit mode.  */
 434 #define m_mode                  (ymmq_mode + 1)
 435 /* pair of v_mode operands */
 436 #define a_mode                  (m_mode + 1)
 437 #define cond_jump_mode          (a_mode + 1)
 438 #define loop_jcxz_mode          (cond_jump_mode + 1)
 439 /* operand size depends on REX prefixes.  */
 440 #define dq_mode                 (loop_jcxz_mode + 1)
 441 /* registers like dq_mode, memory like w_mode.  */
 442 #define dqw_mode                (dq_mode + 1)
 443 /* 4- or 6-byte pointer operand */
 444 #define f_mode                  (dqw_mode + 1)
 445 #define const_1_mode            (f_mode + 1)
 446 /* v_mode for stack-related opcodes.  */
 447 #define stack_v_mode            (const_1_mode + 1)
 448 /* non-quad operand size depends on prefixes */
 449 #define z_mode                  (stack_v_mode + 1)
 450 /* 16-byte operand */
 451 #define o_mode                  (z_mode + 1)
 452 /* registers like dq_mode, memory like b_mode.  */
 453 #define dqb_mode                (o_mode + 1)
 454 /* registers like dq_mode, memory like d_mode.  */
 455 #define dqd_mode                (dqb_mode + 1)
 456 /* normal vex mode */
 457 #define vex_mode                (dqd_mode + 1)
 458 /* 128bit vex mode */
 459 #define vex128_mode             (vex_mode + 1)
 460 /* 256bit vex mode */
 461 #define vex256_mode             (vex128_mode + 1)
 462
 463 #define es_reg                  (vex256_mode + 1)
 464 #define cs_reg                  (es_reg + 1)
 465 #define ss_reg                  (cs_reg + 1)
 466 #define ds_reg                  (ss_reg + 1)
 467 #define fs_reg                  (ds_reg + 1)
 468 #define gs_reg                  (fs_reg + 1)
 469
 470 #define eAX_reg                 (gs_reg + 1)
 471 #define eCX_reg                 (eAX_reg + 1)
 472 #define eDX_reg                 (eCX_reg + 1)
 473 #define eBX_reg                 (eDX_reg + 1)
 474 #define eSP_reg                 (eBX_reg + 1)
 475 #define eBP_reg                 (eSP_reg + 1)
 476 #define eSI_reg                 (eBP_reg + 1)
 477 #define eDI_reg                 (eSI_reg + 1)
 478
 479 #define al_reg                  (eDI_reg + 1)
 480 #define cl_reg                  (al_reg + 1)
 481 #define dl_reg                  (cl_reg + 1)
 482 #define bl_reg                  (dl_reg + 1)
 483 #define ah_reg                  (bl_reg + 1)
 484 #define ch_reg                  (ah_reg + 1)
 485 #define dh_reg                  (ch_reg + 1)
 486 #define bh_reg                  (dh_reg + 1)
 487
 488 #define ax_reg                  (bh_reg + 1)
 489 #define cx_reg                  (ax_reg + 1)
 490 #define dx_reg                  (cx_reg + 1)
 491 #define bx_reg                  (dx_reg + 1)
 492 #define sp_reg                  (bx_reg + 1)
 493 #define bp_reg                  (sp_reg + 1)
 494 #define si_reg                  (bp_reg + 1)
 495 #define di_reg                  (si_reg + 1)
 496
 497 #define rAX_reg                 (di_reg + 1)
 498 #define rCX_reg                 (rAX_reg + 1)
 499 #define rDX_reg                 (rCX_reg + 1)
 500 #define rBX_reg                 (rDX_reg + 1)
 501 #define rSP_reg                 (rBX_reg + 1)
 502 #define rBP_reg                 (rSP_reg + 1)
 503 #define rSI_reg                 (rBP_reg + 1)
 504 #define rDI_reg                 (rSI_reg + 1)
 505
 506 #define z_mode_ax_reg           (rDI_reg + 1)
 507 #define indir_dx_reg            (z_mode_ax_reg + 1)
 508
 509 #define MAX_BYTEMODE    indir_dx_reg
 510
 511 /* Flags that are OR'ed into the bytemode field to pass extra
 512    information.  */
 513 #define DREX_OC1                0x10000 /* OC1 bit set */
 514 #define DREX_NO_OC0             0x20000 /* OC0 bit not used */
 515 #define DREX_MASK               0x40000 /* mask to delete */
 516
 517 #if MAX_BYTEMODE >= DREX_OC1
 518 #error MAX_BYTEMODE must be less than DREX_OC1
 519 #endif
 520
 521 #define FLOATCODE               1
 522 #define USE_REG_TABLE           (FLOATCODE + 1)
 523 #define USE_MOD_TABLE           (USE_REG_TABLE + 1)
 524 #define USE_RM_TABLE            (USE_MOD_TABLE + 1)
 525 #define USE_PREFIX_TABLE        (USE_RM_TABLE + 1)
 526 #define USE_X86_64_TABLE        (USE_PREFIX_TABLE + 1)
 527 #define USE_3BYTE_TABLE         (USE_X86_64_TABLE + 1)
 528 #define USE_VEX_C4_TABLE        (USE_3BYTE_TABLE + 1)
 529 #define USE_VEX_C5_TABLE        (USE_VEX_C4_TABLE + 1)
 530 #define USE_VEX_LEN_TABLE       (USE_VEX_C5_TABLE + 1)
 531
 532 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 533
 534 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 535 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 536 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 537 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 538 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 539 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 540 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 541 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 542 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 543 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 544
 545 #define REG_80                  0
 546 #define REG_81                  (REG_80 + 1)
 547 #define REG_82                  (REG_81 + 1)
 548 #define REG_8F                  (REG_82 + 1)
 549 #define REG_C0                  (REG_8F + 1)
 550 #define REG_C1                  (REG_C0 + 1)
 551 #define REG_C6                  (REG_C1 + 1)
 552 #define REG_C7                  (REG_C6 + 1)
 553 #define REG_D0                  (REG_C7 + 1)
 554 #define REG_D1                  (REG_D0 + 1)
 555 #define REG_D2                  (REG_D1 + 1)
 556 #define REG_D3                  (REG_D2 + 1)
 557 #define REG_F6                  (REG_D3 + 1)
 558 #define REG_F7                  (REG_F6 + 1)
 559 #define REG_FE                  (REG_F7 + 1)
 560 #define REG_FF                  (REG_FE + 1)
 561 #define REG_0F00                (REG_FF + 1)
 562 #define REG_0F01                (REG_0F00 + 1)
 563 #define REG_0F0D                (REG_0F01 + 1)
 564 #define REG_0F18                (REG_0F0D + 1)
 565 #define REG_0F71                (REG_0F18 + 1)
 566 #define REG_0F72                (REG_0F71 + 1)
 567 #define REG_0F73                (REG_0F72 + 1)
 568 #define REG_0FA6                (REG_0F73 + 1)
 569 #define REG_0FA7                (REG_0FA6 + 1)
 570 #define REG_0FAE                (REG_0FA7 + 1)
 571 #define REG_0FBA                (REG_0FAE + 1)
 572 #define REG_0FC7                (REG_0FBA + 1)
 573 #define REG_VEX_71              (REG_0FC7 + 1)
 574 #define REG_VEX_72              (REG_VEX_71 + 1)
 575 #define REG_VEX_73              (REG_VEX_72 + 1)
 576 #define REG_VEX_AE              (REG_VEX_73 + 1)
 577
 578 #define MOD_8D                  0
 579 #define MOD_0F01_REG_0          (MOD_8D + 1)
 580 #define MOD_0F01_REG_1          (MOD_0F01_REG_0 + 1)
 581 #define MOD_0F01_REG_2          (MOD_0F01_REG_1 + 1)
 582 #define MOD_0F01_REG_3          (MOD_0F01_REG_2 + 1)
 583 #define MOD_0F01_REG_7          (MOD_0F01_REG_3 + 1)
 584 #define MOD_0F12_PREFIX_0       (MOD_0F01_REG_7 + 1)
 585 #define MOD_0F13                (MOD_0F12_PREFIX_0 + 1)
 586 #define MOD_0F16_PREFIX_0       (MOD_0F13 + 1)
 587 #define MOD_0F17                (MOD_0F16_PREFIX_0 + 1)
 588 #define MOD_0F18_REG_0          (MOD_0F17 + 1)
 589 #define MOD_0F18_REG_1          (MOD_0F18_REG_0 + 1)
 590 #define MOD_0F18_REG_2          (MOD_0F18_REG_1 + 1)
 591 #define MOD_0F18_REG_3          (MOD_0F18_REG_2 + 1)
 592 #define MOD_0F20                (MOD_0F18_REG_3 + 1)
 593 #define MOD_0F21                (MOD_0F20 + 1)
 594 #define MOD_0F22                (MOD_0F21 + 1)
 595 #define MOD_0F23                (MOD_0F22 + 1)
 596 #define MOD_0F24                (MOD_0F23 + 1)
 597 #define MOD_0F26                (MOD_0F24 + 1)
 598 #define MOD_0F2B_PREFIX_0       (MOD_0F26 + 1)
 599 #define MOD_0F2B_PREFIX_1       (MOD_0F2B_PREFIX_0 + 1)
 600 #define MOD_0F2B_PREFIX_2       (MOD_0F2B_PREFIX_1 + 1)
 601 #define MOD_0F2B_PREFIX_3       (MOD_0F2B_PREFIX_2 + 1)
 602 #define MOD_0F51                (MOD_0F2B_PREFIX_3 + 1)
 603 #define MOD_0F71_REG_2          (MOD_0F51 + 1)
 604 #define MOD_0F71_REG_4          (MOD_0F71_REG_2 + 1)
 605 #define MOD_0F71_REG_6          (MOD_0F71_REG_4 + 1)
 606 #define MOD_0F72_REG_2          (MOD_0F71_REG_6 + 1)
 607 #define MOD_0F72_REG_4          (MOD_0F72_REG_2 + 1)
 608 #define MOD_0F72_REG_6          (MOD_0F72_REG_4 + 1)
 609 #define MOD_0F73_REG_2          (MOD_0F72_REG_6 + 1)
 610 #define MOD_0F73_REG_3          (MOD_0F73_REG_2 + 1)
 611 #define MOD_0F73_REG_6          (MOD_0F73_REG_3 + 1)
 612 #define MOD_0F73_REG_7          (MOD_0F73_REG_6 + 1)
 613 #define MOD_0FAE_REG_0          (MOD_0F73_REG_7 + 1)
 614 #define MOD_0FAE_REG_1          (MOD_0FAE_REG_0 + 1)
 615 #define MOD_0FAE_REG_2          (MOD_0FAE_REG_1 + 1)
 616 #define MOD_0FAE_REG_3          (MOD_0FAE_REG_2 + 1)
 617 #define MOD_0FAE_REG_4          (MOD_0FAE_REG_3 + 1)
 618 #define MOD_0FAE_REG_5          (MOD_0FAE_REG_4 + 1)
 619 #define MOD_0FAE_REG_6          (MOD_0FAE_REG_5 + 1)
 620 #define MOD_0FAE_REG_7          (MOD_0FAE_REG_6 + 1)
 621 #define MOD_0FB2                (MOD_0FAE_REG_7 + 1)
 622 #define MOD_0FB4                (MOD_0FB2 + 1)
 623 #define MOD_0FB5                (MOD_0FB4 + 1)
 624 #define MOD_0FC7_REG_6          (MOD_0FB5 + 1)
 625 #define MOD_0FC7_REG_7          (MOD_0FC7_REG_6 + 1)
 626 #define MOD_0FD7                (MOD_0FC7_REG_7 + 1)
 627 #define MOD_0FE7_PREFIX_2       (MOD_0FD7 + 1)
 628 #define MOD_0FF0_PREFIX_3       (MOD_0FE7_PREFIX_2 + 1)
 629 #define MOD_0F382A_PREFIX_2     (MOD_0FF0_PREFIX_3 + 1)
 630 #define MOD_62_32BIT            (MOD_0F382A_PREFIX_2 + 1)
 631 #define MOD_C4_32BIT            (MOD_62_32BIT + 1)
 632 #define MOD_C5_32BIT            (MOD_C4_32BIT + 1)
 633 #define MOD_VEX_12_PREFIX_0     (MOD_C5_32BIT + 1)
 634 #define MOD_VEX_13              (MOD_VEX_12_PREFIX_0 + 1)
 635 #define MOD_VEX_16_PREFIX_0     (MOD_VEX_13 + 1)
 636 #define MOD_VEX_17              (MOD_VEX_16_PREFIX_0 + 1)
 637 #define MOD_VEX_2B              (MOD_VEX_17 + 1)
 638 #define MOD_VEX_51              (MOD_VEX_2B + 1)
 639 #define MOD_VEX_71_REG_2        (MOD_VEX_51 + 1)
 640 #define MOD_VEX_71_REG_4        (MOD_VEX_71_REG_2 + 1)
 641 #define MOD_VEX_71_REG_6        (MOD_VEX_71_REG_4 + 1)
 642 #define MOD_VEX_72_REG_2        (MOD_VEX_71_REG_6 + 1)
 643 #define MOD_VEX_72_REG_4        (MOD_VEX_72_REG_2 + 1)
 644 #define MOD_VEX_72_REG_6        (MOD_VEX_72_REG_4 + 1)
 645 #define MOD_VEX_73_REG_2        (MOD_VEX_72_REG_6 + 1)
 646 #define MOD_VEX_73_REG_3        (MOD_VEX_73_REG_2 + 1)
 647 #define MOD_VEX_73_REG_6        (MOD_VEX_73_REG_3 + 1)
 648 #define MOD_VEX_73_REG_7        (MOD_VEX_73_REG_6 + 1)
 649 #define MOD_VEX_AE_REG_2        (MOD_VEX_73_REG_7 + 1)
 650 #define MOD_VEX_AE_REG_3        (MOD_VEX_AE_REG_2 + 1)
 651 #define MOD_VEX_D7_PREFIX_2     (MOD_VEX_AE_REG_3 + 1)
 652 #define MOD_VEX_E7_PREFIX_2     (MOD_VEX_D7_PREFIX_2 + 1)
 653 #define MOD_VEX_F0_PREFIX_3     (MOD_VEX_E7_PREFIX_2 + 1)
 654 #define MOD_VEX_3818_PREFIX_2   (MOD_VEX_F0_PREFIX_3 + 1)
 655 #define MOD_VEX_3819_PREFIX_2   (MOD_VEX_3818_PREFIX_2 + 1)
 656 #define MOD_VEX_381A_PREFIX_2   (MOD_VEX_3819_PREFIX_2 + 1)
 657 #define MOD_VEX_382A_PREFIX_2   (MOD_VEX_381A_PREFIX_2 + 1)
 658 #define MOD_VEX_382C_PREFIX_2   (MOD_VEX_382A_PREFIX_2 + 1)
 659 #define MOD_VEX_382D_PREFIX_2   (MOD_VEX_382C_PREFIX_2 + 1)
 660 #define MOD_VEX_382E_PREFIX_2   (MOD_VEX_382D_PREFIX_2 + 1)
 661 #define MOD_VEX_382F_PREFIX_2   (MOD_VEX_382E_PREFIX_2 + 1)
 662
 663 #define RM_0F01_REG_0           0
 664 #define RM_0F01_REG_1           (RM_0F01_REG_0 + 1)
 665 #define RM_0F01_REG_2           (RM_0F01_REG_1 + 1)
 666 #define RM_0F01_REG_3           (RM_0F01_REG_2 + 1)
 667 #define RM_0F01_REG_7           (RM_0F01_REG_3 + 1)
 668 #define RM_0FAE_REG_5           (RM_0F01_REG_7 + 1)
 669 #define RM_0FAE_REG_6           (RM_0FAE_REG_5 + 1)
 670 #define RM_0FAE_REG_7           (RM_0FAE_REG_6 + 1)
 671
 672 #define PREFIX_90               0
 673 #define PREFIX_0F10             (PREFIX_90 + 1)
 674 #define PREFIX_0F11             (PREFIX_0F10 + 1)
 675 #define PREFIX_0F12             (PREFIX_0F11 + 1)
 676 #define PREFIX_0F16             (PREFIX_0F12 + 1)
 677 #define PREFIX_0F2A             (PREFIX_0F16 + 1)
 678 #define PREFIX_0F2B             (PREFIX_0F2A + 1)
 679 #define PREFIX_0F2C             (PREFIX_0F2B + 1)
 680 #define PREFIX_0F2D             (PREFIX_0F2C + 1)
 681 #define PREFIX_0F2E             (PREFIX_0F2D + 1)
 682 #define PREFIX_0F2F             (PREFIX_0F2E + 1)
 683 #define PREFIX_0F51             (PREFIX_0F2F + 1)
 684 #define PREFIX_0F52             (PREFIX_0F51 + 1)
 685 #define PREFIX_0F53             (PREFIX_0F52 + 1)
 686 #define PREFIX_0F58             (PREFIX_0F53 + 1)
 687 #define PREFIX_0F59             (PREFIX_0F58 + 1)
 688 #define PREFIX_0F5A             (PREFIX_0F59 + 1)
 689 #define PREFIX_0F5B             (PREFIX_0F5A + 1)
 690 #define PREFIX_0F5C             (PREFIX_0F5B + 1)
 691 #define PREFIX_0F5D             (PREFIX_0F5C + 1)
 692 #define PREFIX_0F5E             (PREFIX_0F5D + 1)
 693 #define PREFIX_0F5F             (PREFIX_0F5E + 1)
 694 #define PREFIX_0F60             (PREFIX_0F5F + 1)
 695 #define PREFIX_0F61             (PREFIX_0F60 + 1)
 696 #define PREFIX_0F62             (PREFIX_0F61 + 1)
 697 #define PREFIX_0F6C             (PREFIX_0F62 + 1)
 698 #define PREFIX_0F6D             (PREFIX_0F6C + 1)
 699 #define PREFIX_0F6F             (PREFIX_0F6D + 1)
 700 #define PREFIX_0F70             (PREFIX_0F6F + 1)
 701 #define PREFIX_0F73_REG_3       (PREFIX_0F70 + 1)
 702 #define PREFIX_0F73_REG_7       (PREFIX_0F73_REG_3 + 1)
 703 #define PREFIX_0F78             (PREFIX_0F73_REG_7 + 1)
 704 #define PREFIX_0F79             (PREFIX_0F78 + 1)
 705 #define PREFIX_0F7C             (PREFIX_0F79 + 1)
 706 #define PREFIX_0F7D             (PREFIX_0F7C + 1)
 707 #define PREFIX_0F7E             (PREFIX_0F7D + 1)
 708 #define PREFIX_0F7F             (PREFIX_0F7E + 1)
 709 #define PREFIX_0FB8             (PREFIX_0F7F + 1)
 710 #define PREFIX_0FBD             (PREFIX_0FB8 + 1)
 711 #define PREFIX_0FC2             (PREFIX_0FBD + 1)
 712 #define PREFIX_0FC3             (PREFIX_0FC2 + 1)
 713 #define PREFIX_0FC7_REG_6       (PREFIX_0FC3 + 1)
 714 #define PREFIX_0FD0             (PREFIX_0FC7_REG_6 + 1)
 715 #define PREFIX_0FD6             (PREFIX_0FD0 + 1)
 716 #define PREFIX_0FE6             (PREFIX_0FD6 + 1)
 717 #define PREFIX_0FE7             (PREFIX_0FE6 + 1)
 718 #define PREFIX_0FF0             (PREFIX_0FE7 + 1)
 719 #define PREFIX_0FF7             (PREFIX_0FF0 + 1)
 720 #define PREFIX_0F3810           (PREFIX_0FF7 + 1)
 721 #define PREFIX_0F3814           (PREFIX_0F3810 + 1)
 722 #define PREFIX_0F3815           (PREFIX_0F3814 + 1)
 723 #define PREFIX_0F3817           (PREFIX_0F3815 + 1)
 724 #define PREFIX_0F3820           (PREFIX_0F3817 + 1)
 725 #define PREFIX_0F3821           (PREFIX_0F3820 + 1)
 726 #define PREFIX_0F3822           (PREFIX_0F3821 + 1)
 727 #define PREFIX_0F3823           (PREFIX_0F3822 + 1)
 728 #define PREFIX_0F3824           (PREFIX_0F3823 + 1)
 729 #define PREFIX_0F3825           (PREFIX_0F3824 + 1)
 730 #define PREFIX_0F3828           (PREFIX_0F3825 + 1)
 731 #define PREFIX_0F3829           (PREFIX_0F3828 + 1)
 732 #define PREFIX_0F382A           (PREFIX_0F3829 + 1)
 733 #define PREFIX_0F382B           (PREFIX_0F382A + 1)
 734 #define PREFIX_0F3830           (PREFIX_0F382B + 1)
 735 #define PREFIX_0F3831           (PREFIX_0F3830 + 1)
 736 #define PREFIX_0F3832           (PREFIX_0F3831 + 1)
 737 #define PREFIX_0F3833           (PREFIX_0F3832 + 1)
 738 #define PREFIX_0F3834           (PREFIX_0F3833 + 1)
 739 #define PREFIX_0F3835           (PREFIX_0F3834 + 1)
 740 #define PREFIX_0F3837           (PREFIX_0F3835 + 1)
 741 #define PREFIX_0F3838           (PREFIX_0F3837 + 1)
 742 #define PREFIX_0F3839           (PREFIX_0F3838 + 1)
 743 #define PREFIX_0F383A           (PREFIX_0F3839 + 1)
 744 #define PREFIX_0F383B           (PREFIX_0F383A + 1)
 745 #define PREFIX_0F383C           (PREFIX_0F383B + 1)
 746 #define PREFIX_0F383D           (PREFIX_0F383C + 1)
 747 #define PREFIX_0F383E           (PREFIX_0F383D + 1)
 748 #define PREFIX_0F383F           (PREFIX_0F383E + 1)
 749 #define PREFIX_0F3840           (PREFIX_0F383F + 1)
 750 #define PREFIX_0F3841           (PREFIX_0F3840 + 1)
 751 #define PREFIX_0F3880           (PREFIX_0F3841 + 1)
 752 #define PREFIX_0F3881           (PREFIX_0F3880 + 1)
 753 #define PREFIX_0F38DB           (PREFIX_0F3881 + 1)
 754 #define PREFIX_0F38DC           (PREFIX_0F38DB + 1)
 755 #define PREFIX_0F38DD           (PREFIX_0F38DC + 1)
 756 #define PREFIX_0F38DE           (PREFIX_0F38DD + 1)
 757 #define PREFIX_0F38DF           (PREFIX_0F38DE + 1)
 758 #define PREFIX_0F38F0           (PREFIX_0F38DF + 1)
 759 #define PREFIX_0F38F1           (PREFIX_0F38F0 + 1)
 760 #define PREFIX_0F3A08           (PREFIX_0F38F1 + 1)
 761 #define PREFIX_0F3A09           (PREFIX_0F3A08 + 1)
 762 #define PREFIX_0F3A0A           (PREFIX_0F3A09 + 1)
 763 #define PREFIX_0F3A0B           (PREFIX_0F3A0A + 1)
 764 #define PREFIX_0F3A0C           (PREFIX_0F3A0B + 1)
 765 #define PREFIX_0F3A0D           (PREFIX_0F3A0C + 1)
 766 #define PREFIX_0F3A0E           (PREFIX_0F3A0D + 1)
 767 #define PREFIX_0F3A14           (PREFIX_0F3A0E + 1)
 768 #define PREFIX_0F3A15           (PREFIX_0F3A14 + 1)
 769 #define PREFIX_0F3A16           (PREFIX_0F3A15 + 1)
 770 #define PREFIX_0F3A17           (PREFIX_0F3A16 + 1)
 771 #define PREFIX_0F3A20           (PREFIX_0F3A17 + 1)
 772 #define PREFIX_0F3A21           (PREFIX_0F3A20 + 1)
 773 #define PREFIX_0F3A22           (PREFIX_0F3A21 + 1)
 774 #define PREFIX_0F3A40           (PREFIX_0F3A22 + 1)
 775 #define PREFIX_0F3A41           (PREFIX_0F3A40 + 1)
 776 #define PREFIX_0F3A42           (PREFIX_0F3A41 + 1)
 777 #define PREFIX_0F3A44           (PREFIX_0F3A42 + 1)
 778 #define PREFIX_0F3A60           (PREFIX_0F3A44 + 1)
 779 #define PREFIX_0F3A61           (PREFIX_0F3A60 + 1)
 780 #define PREFIX_0F3A62           (PREFIX_0F3A61 + 1)
 781 #define PREFIX_0F3A63           (PREFIX_0F3A62 + 1)
 782 #define PREFIX_0F3ADF           (PREFIX_0F3A63 + 1)
 783 #define PREFIX_VEX_10           (PREFIX_0F3ADF + 1)
 784 #define PREFIX_VEX_11           (PREFIX_VEX_10 + 1)
 785 #define PREFIX_VEX_12           (PREFIX_VEX_11 + 1)
 786 #define PREFIX_VEX_16           (PREFIX_VEX_12 + 1)
 787 #define PREFIX_VEX_2A           (PREFIX_VEX_16 + 1)
 788 #define PREFIX_VEX_2C           (PREFIX_VEX_2A + 1)
 789 #define PREFIX_VEX_2D           (PREFIX_VEX_2C + 1)
 790 #define PREFIX_VEX_2E           (PREFIX_VEX_2D + 1)
 791 #define PREFIX_VEX_2F           (PREFIX_VEX_2E + 1)
 792 #define PREFIX_VEX_51           (PREFIX_VEX_2F + 1)
 793 #define PREFIX_VEX_52           (PREFIX_VEX_51 + 1)
 794 #define PREFIX_VEX_53           (PREFIX_VEX_52 + 1)
 795 #define PREFIX_VEX_58           (PREFIX_VEX_53 + 1)
 796 #define PREFIX_VEX_59           (PREFIX_VEX_58 + 1)
 797 #define PREFIX_VEX_5A           (PREFIX_VEX_59 + 1)
 798 #define PREFIX_VEX_5B           (PREFIX_VEX_5A + 1)
 799 #define PREFIX_VEX_5C           (PREFIX_VEX_5B + 1)
 800 #define PREFIX_VEX_5D           (PREFIX_VEX_5C + 1)
 801 #define PREFIX_VEX_5E           (PREFIX_VEX_5D + 1)
 802 #define PREFIX_VEX_5F           (PREFIX_VEX_5E + 1)
 803 #define PREFIX_VEX_60           (PREFIX_VEX_5F + 1)
 804 #define PREFIX_VEX_61           (PREFIX_VEX_60 + 1)
 805 #define PREFIX_VEX_62           (PREFIX_VEX_61 + 1)
 806 #define PREFIX_VEX_63           (PREFIX_VEX_62 + 1)
 807 #define PREFIX_VEX_64           (PREFIX_VEX_63 + 1)
 808 #define PREFIX_VEX_65           (PREFIX_VEX_64 + 1)
 809 #define PREFIX_VEX_66           (PREFIX_VEX_65 + 1)
 810 #define PREFIX_VEX_67           (PREFIX_VEX_66 + 1)
 811 #define PREFIX_VEX_68           (PREFIX_VEX_67 + 1)
 812 #define PREFIX_VEX_69           (PREFIX_VEX_68 + 1)
 813 #define PREFIX_VEX_6A           (PREFIX_VEX_69 + 1)
 814 #define PREFIX_VEX_6B           (PREFIX_VEX_6A + 1)
 815 #define PREFIX_VEX_6C           (PREFIX_VEX_6B + 1)
 816 #define PREFIX_VEX_6D           (PREFIX_VEX_6C + 1)
 817 #define PREFIX_VEX_6E           (PREFIX_VEX_6D + 1)
 818 #define PREFIX_VEX_6F           (PREFIX_VEX_6E + 1)
 819 #define PREFIX_VEX_70           (PREFIX_VEX_6F + 1)
 820 #define PREFIX_VEX_71_REG_2     (PREFIX_VEX_70 + 1)
 821 #define PREFIX_VEX_71_REG_4     (PREFIX_VEX_71_REG_2 + 1)
 822 #define PREFIX_VEX_71_REG_6     (PREFIX_VEX_71_REG_4 + 1)
 823 #define PREFIX_VEX_72_REG_2     (PREFIX_VEX_71_REG_6 + 1)
 824 #define PREFIX_VEX_72_REG_4     (PREFIX_VEX_72_REG_2 + 1)
 825 #define PREFIX_VEX_72_REG_6     (PREFIX_VEX_72_REG_4 + 1)
 826 #define PREFIX_VEX_73_REG_2     (PREFIX_VEX_72_REG_6 + 1)
 827 #define PREFIX_VEX_73_REG_3     (PREFIX_VEX_73_REG_2 + 1)
 828 #define PREFIX_VEX_73_REG_6     (PREFIX_VEX_73_REG_3 + 1)
 829 #define PREFIX_VEX_73_REG_7     (PREFIX_VEX_73_REG_6 + 1)
 830 #define PREFIX_VEX_74           (PREFIX_VEX_73_REG_7 + 1)
 831 #define PREFIX_VEX_75           (PREFIX_VEX_74 + 1)
 832 #define PREFIX_VEX_76           (PREFIX_VEX_75 + 1)
 833 #define PREFIX_VEX_77           (PREFIX_VEX_76 + 1)
 834 #define PREFIX_VEX_7C           (PREFIX_VEX_77 + 1)
 835 #define PREFIX_VEX_7D           (PREFIX_VEX_7C + 1)
 836 #define PREFIX_VEX_7E           (PREFIX_VEX_7D + 1)
 837 #define PREFIX_VEX_7F           (PREFIX_VEX_7E + 1)
 838 #define PREFIX_VEX_C2           (PREFIX_VEX_7F + 1)
 839 #define PREFIX_VEX_C4           (PREFIX_VEX_C2 + 1)
 840 #define PREFIX_VEX_C5           (PREFIX_VEX_C4 + 1)
 841 #define PREFIX_VEX_D0           (PREFIX_VEX_C5 + 1)
 842 #define PREFIX_VEX_D1           (PREFIX_VEX_D0 + 1)
 843 #define PREFIX_VEX_D2           (PREFIX_VEX_D1 + 1)
 844 #define PREFIX_VEX_D3           (PREFIX_VEX_D2 + 1)
 845 #define PREFIX_VEX_D4           (PREFIX_VEX_D3 + 1)
 846 #define PREFIX_VEX_D5           (PREFIX_VEX_D4 + 1)
 847 #define PREFIX_VEX_D6           (PREFIX_VEX_D5 + 1)
 848 #define PREFIX_VEX_D7           (PREFIX_VEX_D6 + 1)
 849 #define PREFIX_VEX_D8           (PREFIX_VEX_D7 + 1)
 850 #define PREFIX_VEX_D9           (PREFIX_VEX_D8 + 1)
 851 #define PREFIX_VEX_DA           (PREFIX_VEX_D9 + 1)
 852 #define PREFIX_VEX_DB           (PREFIX_VEX_DA + 1)
 853 #define PREFIX_VEX_DC           (PREFIX_VEX_DB + 1)
 854 #define PREFIX_VEX_DD           (PREFIX_VEX_DC + 1)
 855 #define PREFIX_VEX_DE           (PREFIX_VEX_DD + 1)
 856 #define PREFIX_VEX_DF           (PREFIX_VEX_DE + 1)
 857 #define PREFIX_VEX_E0           (PREFIX_VEX_DF + 1)
 858 #define PREFIX_VEX_E1           (PREFIX_VEX_E0 + 1)
 859 #define PREFIX_VEX_E2           (PREFIX_VEX_E1 + 1)
 860 #define PREFIX_VEX_E3           (PREFIX_VEX_E2 + 1)
 861 #define PREFIX_VEX_E4           (PREFIX_VEX_E3 + 1)
 862 #define PREFIX_VEX_E5           (PREFIX_VEX_E4 + 1)
 863 #define PREFIX_VEX_E6           (PREFIX_VEX_E5 + 1)
 864 #define PREFIX_VEX_E7           (PREFIX_VEX_E6 + 1)
 865 #define PREFIX_VEX_E8           (PREFIX_VEX_E7 + 1)
 866 #define PREFIX_VEX_E9           (PREFIX_VEX_E8 + 1)
 867 #define PREFIX_VEX_EA           (PREFIX_VEX_E9 + 1)
 868 #define PREFIX_VEX_EB           (PREFIX_VEX_EA + 1)
 869 #define PREFIX_VEX_EC           (PREFIX_VEX_EB + 1)
 870 #define PREFIX_VEX_ED           (PREFIX_VEX_EC + 1)
 871 #define PREFIX_VEX_EE           (PREFIX_VEX_ED + 1)
 872 #define PREFIX_VEX_EF           (PREFIX_VEX_EE + 1)
 873 #define PREFIX_VEX_F0           (PREFIX_VEX_EF + 1)
 874 #define PREFIX_VEX_F1           (PREFIX_VEX_F0 + 1)
 875 #define PREFIX_VEX_F2           (PREFIX_VEX_F1 + 1)
 876 #define PREFIX_VEX_F3           (PREFIX_VEX_F2 + 1)
 877 #define PREFIX_VEX_F4           (PREFIX_VEX_F3 + 1)
 878 #define PREFIX_VEX_F5           (PREFIX_VEX_F4 + 1)
 879 #define PREFIX_VEX_F6           (PREFIX_VEX_F5 + 1)
 880 #define PREFIX_VEX_F7           (PREFIX_VEX_F6 + 1)
 881 #define PREFIX_VEX_F8           (PREFIX_VEX_F7 + 1)
 882 #define PREFIX_VEX_F9           (PREFIX_VEX_F8 + 1)
 883 #define PREFIX_VEX_FA           (PREFIX_VEX_F9 + 1)
 884 #define PREFIX_VEX_FB           (PREFIX_VEX_FA + 1)
 885 #define PREFIX_VEX_FC           (PREFIX_VEX_FB + 1)
 886 #define PREFIX_VEX_FD           (PREFIX_VEX_FC + 1)
 887 #define PREFIX_VEX_FE           (PREFIX_VEX_FD + 1)
 888 #define PREFIX_VEX_3800         (PREFIX_VEX_FE + 1)
 889 #define PREFIX_VEX_3801         (PREFIX_VEX_3800 + 1)
 890 #define PREFIX_VEX_3802         (PREFIX_VEX_3801 + 1)
 891 #define PREFIX_VEX_3803         (PREFIX_VEX_3802 + 1)
 892 #define PREFIX_VEX_3804         (PREFIX_VEX_3803 + 1)
 893 #define PREFIX_VEX_3805         (PREFIX_VEX_3804 + 1)
 894 #define PREFIX_VEX_3806         (PREFIX_VEX_3805 + 1)
 895 #define PREFIX_VEX_3807         (PREFIX_VEX_3806 + 1)
 896 #define PREFIX_VEX_3808         (PREFIX_VEX_3807 + 1)
 897 #define PREFIX_VEX_3809         (PREFIX_VEX_3808 + 1)
 898 #define PREFIX_VEX_380A         (PREFIX_VEX_3809 + 1)
 899 #define PREFIX_VEX_380B         (PREFIX_VEX_380A + 1)
 900 #define PREFIX_VEX_380C         (PREFIX_VEX_380B + 1)
 901 #define PREFIX_VEX_380D         (PREFIX_VEX_380C + 1)
 902 #define PREFIX_VEX_380E         (PREFIX_VEX_380D + 1)
 903 #define PREFIX_VEX_380F         (PREFIX_VEX_380E + 1)
 904 #define PREFIX_VEX_3817         (PREFIX_VEX_380F + 1)
 905 #define PREFIX_VEX_3818         (PREFIX_VEX_3817 + 1)
 906 #define PREFIX_VEX_3819         (PREFIX_VEX_3818 + 1)
 907 #define PREFIX_VEX_381A         (PREFIX_VEX_3819 + 1)
 908 #define PREFIX_VEX_381C         (PREFIX_VEX_381A + 1)
 909 #define PREFIX_VEX_381D         (PREFIX_VEX_381C + 1)
 910 #define PREFIX_VEX_381E         (PREFIX_VEX_381D + 1)
 911 #define PREFIX_VEX_3820         (PREFIX_VEX_381E + 1)
 912 #define PREFIX_VEX_3821         (PREFIX_VEX_3820 + 1)
 913 #define PREFIX_VEX_3822         (PREFIX_VEX_3821 + 1)
 914 #define PREFIX_VEX_3823         (PREFIX_VEX_3822 + 1)
 915 #define PREFIX_VEX_3824         (PREFIX_VEX_3823 + 1)
 916 #define PREFIX_VEX_3825         (PREFIX_VEX_3824 + 1)
 917 #define PREFIX_VEX_3828         (PREFIX_VEX_3825 + 1)
 918 #define PREFIX_VEX_3829         (PREFIX_VEX_3828 + 1)
 919 #define PREFIX_VEX_382A         (PREFIX_VEX_3829 + 1)
 920 #define PREFIX_VEX_382B         (PREFIX_VEX_382A + 1)
 921 #define PREFIX_VEX_382C         (PREFIX_VEX_382B + 1)
 922 #define PREFIX_VEX_382D         (PREFIX_VEX_382C + 1)
 923 #define PREFIX_VEX_382E         (PREFIX_VEX_382D + 1)
 924 #define PREFIX_VEX_382F         (PREFIX_VEX_382E + 1)
 925 #define PREFIX_VEX_3830         (PREFIX_VEX_382F + 1)
 926 #define PREFIX_VEX_3831         (PREFIX_VEX_3830 + 1)
 927 #define PREFIX_VEX_3832         (PREFIX_VEX_3831 + 1)
 928 #define PREFIX_VEX_3833         (PREFIX_VEX_3832 + 1)
 929 #define PREFIX_VEX_3834         (PREFIX_VEX_3833 + 1)
 930 #define PREFIX_VEX_3835         (PREFIX_VEX_3834 + 1)
 931 #define PREFIX_VEX_3837         (PREFIX_VEX_3835 + 1)
 932 #define PREFIX_VEX_3838         (PREFIX_VEX_3837 + 1)
 933 #define PREFIX_VEX_3839         (PREFIX_VEX_3838 + 1)
 934 #define PREFIX_VEX_383A         (PREFIX_VEX_3839 + 1)
 935 #define PREFIX_VEX_383B         (PREFIX_VEX_383A + 1)
 936 #define PREFIX_VEX_383C         (PREFIX_VEX_383B + 1)
 937 #define PREFIX_VEX_383D         (PREFIX_VEX_383C + 1)
 938 #define PREFIX_VEX_383E         (PREFIX_VEX_383D + 1)
 939 #define PREFIX_VEX_383F         (PREFIX_VEX_383E + 1)
 940 #define PREFIX_VEX_3840         (PREFIX_VEX_383F + 1)
 941 #define PREFIX_VEX_3841         (PREFIX_VEX_3840 + 1)
 942 #define PREFIX_VEX_3A04         (PREFIX_VEX_3841 + 1)
 943 #define PREFIX_VEX_3A05         (PREFIX_VEX_3A04 + 1)
 944 #define PREFIX_VEX_3A06         (PREFIX_VEX_3A05 + 1)
 945 #define PREFIX_VEX_3A08         (PREFIX_VEX_3A06 + 1)
 946 #define PREFIX_VEX_3A09         (PREFIX_VEX_3A08 + 1)
 947 #define PREFIX_VEX_3A0A         (PREFIX_VEX_3A09 + 1)
 948 #define PREFIX_VEX_3A0B         (PREFIX_VEX_3A0A + 1)
 949 #define PREFIX_VEX_3A0C         (PREFIX_VEX_3A0B + 1)
 950 #define PREFIX_VEX_3A0D         (PREFIX_VEX_3A0C + 1)
 951 #define PREFIX_VEX_3A0E         (PREFIX_VEX_3A0D + 1)
 952 #define PREFIX_VEX_3A0F         (PREFIX_VEX_3A0E + 1)
 953 #define PREFIX_VEX_3A14         (PREFIX_VEX_3A0F + 1)
 954 #define PREFIX_VEX_3A15         (PREFIX_VEX_3A14 + 1)
 955 #define PREFIX_VEX_3A16         (PREFIX_VEX_3A15 + 1)
 956 #define PREFIX_VEX_3A17         (PREFIX_VEX_3A16 + 1)
 957 #define PREFIX_VEX_3A18         (PREFIX_VEX_3A17 + 1)
 958 #define PREFIX_VEX_3A19         (PREFIX_VEX_3A18 + 1)
 959 #define PREFIX_VEX_3A20         (PREFIX_VEX_3A19 + 1)
 960 #define PREFIX_VEX_3A21         (PREFIX_VEX_3A20 + 1)
 961 #define PREFIX_VEX_3A22         (PREFIX_VEX_3A21 + 1)
 962 #define PREFIX_VEX_3A40         (PREFIX_VEX_3A22 + 1)
 963 #define PREFIX_VEX_3A41         (PREFIX_VEX_3A40 + 1)
 964 #define PREFIX_VEX_3A42         (PREFIX_VEX_3A41 + 1)
 965 #define PREFIX_VEX_3A48         (PREFIX_VEX_3A42 + 1)
 966 #define PREFIX_VEX_3A49         (PREFIX_VEX_3A48 + 1)
 967 #define PREFIX_VEX_3A4A         (PREFIX_VEX_3A49 + 1)
 968 #define PREFIX_VEX_3A4B         (PREFIX_VEX_3A4A + 1)
 969 #define PREFIX_VEX_3A4C         (PREFIX_VEX_3A4B + 1)
 970 #define PREFIX_VEX_3A5C         (PREFIX_VEX_3A4C + 1)
 971 #define PREFIX_VEX_3A5D         (PREFIX_VEX_3A5C + 1)
 972 #define PREFIX_VEX_3A5E         (PREFIX_VEX_3A5D + 1)
 973 #define PREFIX_VEX_3A5F         (PREFIX_VEX_3A5E + 1)
 974 #define PREFIX_VEX_3A60         (PREFIX_VEX_3A5F + 1)
 975 #define PREFIX_VEX_3A61         (PREFIX_VEX_3A60 + 1)
 976 #define PREFIX_VEX_3A62         (PREFIX_VEX_3A61 + 1)
 977 #define PREFIX_VEX_3A63         (PREFIX_VEX_3A62 + 1)
 978 #define PREFIX_VEX_3A68         (PREFIX_VEX_3A63 + 1)
 979 #define PREFIX_VEX_3A69         (PREFIX_VEX_3A68 + 1)
 980 #define PREFIX_VEX_3A6A         (PREFIX_VEX_3A69 + 1)
 981 #define PREFIX_VEX_3A6B         (PREFIX_VEX_3A6A + 1)
 982 #define PREFIX_VEX_3A6C         (PREFIX_VEX_3A6B + 1)
 983 #define PREFIX_VEX_3A6D         (PREFIX_VEX_3A6C + 1)
 984 #define PREFIX_VEX_3A6E         (PREFIX_VEX_3A6D + 1)
 985 #define PREFIX_VEX_3A6F         (PREFIX_VEX_3A6E + 1)
 986 #define PREFIX_VEX_3A78         (PREFIX_VEX_3A6F + 1)
 987 #define PREFIX_VEX_3A79         (PREFIX_VEX_3A78 + 1)
 988 #define PREFIX_VEX_3A7A         (PREFIX_VEX_3A79 + 1)
 989 #define PREFIX_VEX_3A7B         (PREFIX_VEX_3A7A + 1)
 990 #define PREFIX_VEX_3A7C         (PREFIX_VEX_3A7B + 1)
 991 #define PREFIX_VEX_3A7D         (PREFIX_VEX_3A7C + 1)
 992 #define PREFIX_VEX_3A7E         (PREFIX_VEX_3A7D + 1)
 993 #define PREFIX_VEX_3A7F         (PREFIX_VEX_3A7E + 1)
 994
 995 #define X86_64_06               0
 996 #define X86_64_07               (X86_64_06 + 1)
 997 #define X86_64_0D               (X86_64_07 + 1)
 998 #define X86_64_16               (X86_64_0D + 1)
 999 #define X86_64_17               (X86_64_16 + 1)
1000 #define X86_64_1E               (X86_64_17 + 1)
1001 #define X86_64_1F               (X86_64_1E + 1)
1002 #define X86_64_27               (X86_64_1F + 1)
1003 #define X86_64_2F               (X86_64_27 + 1)
1004 #define X86_64_37               (X86_64_2F + 1)
1005 #define X86_64_3F               (X86_64_37 + 1)
1006 #define X86_64_60               (X86_64_3F + 1)
1007 #define X86_64_61               (X86_64_60 + 1)
1008 #define X86_64_62               (X86_64_61 + 1)
1009 #define X86_64_63               (X86_64_62 + 1)
1010 #define X86_64_6D               (X86_64_63 + 1)
1011 #define X86_64_6F               (X86_64_6D + 1)
1012 #define X86_64_9A               (X86_64_6F + 1)
1013 #define X86_64_C4               (X86_64_9A + 1)
1014 #define X86_64_C5               (X86_64_C4 + 1)
1015 #define X86_64_CE               (X86_64_C5 + 1)
1016 #define X86_64_D4               (X86_64_CE + 1)
1017 #define X86_64_D5               (X86_64_D4 + 1)
1018 #define X86_64_EA               (X86_64_D5 + 1)
1019 #define X86_64_0F01_REG_0       (X86_64_EA + 1)
1020 #define X86_64_0F01_REG_1       (X86_64_0F01_REG_0 + 1)
1021 #define X86_64_0F01_REG_2       (X86_64_0F01_REG_1 + 1)
1022 #define X86_64_0F01_REG_3       (X86_64_0F01_REG_2 + 1)
1023
1024 #define THREE_BYTE_0F24         0
1025 #define THREE_BYTE_0F25         (THREE_BYTE_0F24 + 1)
1026 #define THREE_BYTE_0F38         (THREE_BYTE_0F25 + 1)
1027 #define THREE_BYTE_0F3A         (THREE_BYTE_0F38 + 1)
1028 #define THREE_BYTE_0F7A         (THREE_BYTE_0F3A + 1)
1029 #define THREE_BYTE_0F7B         (THREE_BYTE_0F7A + 1)
1030
1031 #define VEX_0F                  0
1032 #define VEX_0F38                (VEX_0F + 1)
1033 #define VEX_0F3A                (VEX_0F38 + 1)
1034
1035 #define VEX_LEN_10_P_1  0
1036 #define VEX_LEN_10_P_3  (VEX_LEN_10_P_1 + 1)
1037 #define VEX_LEN_11_P_1  (VEX_LEN_10_P_3 + 1)
1038 #define VEX_LEN_11_P_3  (VEX_LEN_11_P_1 + 1)
1039 #define VEX_LEN_12_P_0_M_0      (VEX_LEN_11_P_3 + 1)
1040 #define VEX_LEN_12_P_0_M_1      (VEX_LEN_12_P_0_M_0 + 1)
1041 #define VEX_LEN_12_P_2  (VEX_LEN_12_P_0_M_1 + 1)
1042 #define VEX_LEN_13_M_0  (VEX_LEN_12_P_2 + 1)
1043 #define VEX_LEN_16_P_0_M_0      (VEX_LEN_13_M_0 + 1)
1044 #define VEX_LEN_16_P_0_M_1      (VEX_LEN_16_P_0_M_0 + 1)
1045 #define VEX_LEN_16_P_2  (VEX_LEN_16_P_0_M_1 + 1)
1046 #define VEX_LEN_17_M_0  (VEX_LEN_16_P_2 + 1)
1047 #define VEX_LEN_2A_P_1  (VEX_LEN_17_M_0 + 1)
1048 #define VEX_LEN_2A_P_3  (VEX_LEN_2A_P_1 + 1)
1049 #define VEX_LEN_2B_M_0  (VEX_LEN_2A_P_3 + 1)
1050 #define VEX_LEN_2C_P_1  (VEX_LEN_2B_M_0 + 1)
1051 #define VEX_LEN_2C_P_3  (VEX_LEN_2C_P_1 + 1)
1052 #define VEX_LEN_2D_P_1  (VEX_LEN_2C_P_3 + 1)
1053 #define VEX_LEN_2D_P_3  (VEX_LEN_2D_P_1 + 1)
1054 #define VEX_LEN_2E_P_0  (VEX_LEN_2D_P_3 + 1)
1055 #define VEX_LEN_2E_P_2  (VEX_LEN_2E_P_0 + 1)
1056 #define VEX_LEN_2F_P_0  (VEX_LEN_2E_P_2 + 1)
1057 #define VEX_LEN_2F_P_2  (VEX_LEN_2F_P_0 + 1)
1058 #define VEX_LEN_51_P_1  (VEX_LEN_2F_P_2 + 1)
1059 #define VEX_LEN_51_P_3  (VEX_LEN_51_P_1 + 1)
1060 #define VEX_LEN_52_P_1  (VEX_LEN_51_P_3 + 1)
1061 #define VEX_LEN_53_P_1  (VEX_LEN_52_P_1 + 1)
1062 #define VEX_LEN_58_P_1  (VEX_LEN_53_P_1 + 1)
1063 #define VEX_LEN_58_P_3  (VEX_LEN_58_P_1 + 1)
1064 #define VEX_LEN_59_P_1  (VEX_LEN_58_P_3 + 1)
1065 #define VEX_LEN_59_P_3  (VEX_LEN_59_P_1 + 1)
1066 #define VEX_LEN_5A_P_1  (VEX_LEN_59_P_3 + 1)
1067 #define VEX_LEN_5A_P_3  (VEX_LEN_5A_P_1 + 1)
1068 #define VEX_LEN_5C_P_1  (VEX_LEN_5A_P_3 + 1)
1069 #define VEX_LEN_5C_P_3  (VEX_LEN_5C_P_1 + 1)
1070 #define VEX_LEN_5D_P_1  (VEX_LEN_5C_P_3 + 1)
1071 #define VEX_LEN_5D_P_3  (VEX_LEN_5D_P_1 + 1)
1072 #define VEX_LEN_5E_P_1  (VEX_LEN_5D_P_3 + 1)
1073 #define VEX_LEN_5E_P_3  (VEX_LEN_5E_P_1 + 1)
1074 #define VEX_LEN_5F_P_1  (VEX_LEN_5E_P_3 + 1)
1075 #define VEX_LEN_5F_P_3  (VEX_LEN_5F_P_1 + 1)
1076 #define VEX_LEN_60_P_2  (VEX_LEN_5F_P_3 + 1)
1077 #define VEX_LEN_61_P_2  (VEX_LEN_60_P_2 + 1)
1078 #define VEX_LEN_62_P_2  (VEX_LEN_61_P_2 + 1)
1079 #define VEX_LEN_63_P_2  (VEX_LEN_62_P_2 + 1)
1080 #define VEX_LEN_64_P_2  (VEX_LEN_63_P_2 + 1)
1081 #define VEX_LEN_65_P_2  (VEX_LEN_64_P_2 + 1)
1082 #define VEX_LEN_66_P_2  (VEX_LEN_65_P_2 + 1)
1083 #define VEX_LEN_67_P_2  (VEX_LEN_66_P_2 + 1)
1084 #define VEX_LEN_68_P_2  (VEX_LEN_67_P_2 + 1)
1085 #define VEX_LEN_69_P_2  (VEX_LEN_68_P_2 + 1)
1086 #define VEX_LEN_6A_P_2  (VEX_LEN_69_P_2 + 1)
1087 #define VEX_LEN_6B_P_2  (VEX_LEN_6A_P_2 + 1)
1088 #define VEX_LEN_6C_P_2  (VEX_LEN_6B_P_2 + 1)
1089 #define VEX_LEN_6D_P_2  (VEX_LEN_6C_P_2 + 1)
1090 #define VEX_LEN_6E_P_2  (VEX_LEN_6D_P_2 + 1)
1091 #define VEX_LEN_70_P_1  (VEX_LEN_6E_P_2 + 1)
1092 #define VEX_LEN_70_P_2  (VEX_LEN_70_P_1 + 1)
1093 #define VEX_LEN_70_P_3  (VEX_LEN_70_P_2 + 1)
1094 #define VEX_LEN_71_R_2_P_2      (VEX_LEN_70_P_3 + 1)
1095 #define VEX_LEN_71_R_4_P_2      (VEX_LEN_71_R_2_P_2 + 1)
1096 #define VEX_LEN_71_R_6_P_2      (VEX_LEN_71_R_4_P_2 + 1)
1097 #define VEX_LEN_72_R_2_P_2      (VEX_LEN_71_R_6_P_2 + 1)
1098 #define VEX_LEN_72_R_4_P_2      (VEX_LEN_72_R_2_P_2 + 1)
1099 #define VEX_LEN_72_R_6_P_2      (VEX_LEN_72_R_4_P_2 + 1)
1100 #define VEX_LEN_73_R_2_P_2      (VEX_LEN_72_R_6_P_2 + 1)
1101 #define VEX_LEN_73_R_3_P_2      (VEX_LEN_73_R_2_P_2 + 1)
1102 #define VEX_LEN_73_R_6_P_2      (VEX_LEN_73_R_3_P_2 + 1)
1103 #define VEX_LEN_73_R_7_P_2      (VEX_LEN_73_R_6_P_2 + 1)
1104 #define VEX_LEN_74_P_2  (VEX_LEN_73_R_7_P_2 + 1)
1105 #define VEX_LEN_75_P_2  (VEX_LEN_74_P_2 + 1)
1106 #define VEX_LEN_76_P_2  (VEX_LEN_75_P_2 + 1)
1107 #define VEX_LEN_7E_P_1  (VEX_LEN_76_P_2 + 1)
1108 #define VEX_LEN_7E_P_2  (VEX_LEN_7E_P_1 + 1)
1109 #define VEX_LEN_AE_R_2_M_0      (VEX_LEN_7E_P_2 + 1)
1110 #define VEX_LEN_AE_R_3_M_0      (VEX_LEN_AE_R_2_M_0 + 1)
1111 #define VEX_LEN_C2_P_1  (VEX_LEN_AE_R_3_M_0 + 1)
1112 #define VEX_LEN_C2_P_3  (VEX_LEN_C2_P_1 + 1)
1113 #define VEX_LEN_C4_P_2  (VEX_LEN_C2_P_3 + 1)
1114 #define VEX_LEN_C5_P_2  (VEX_LEN_C4_P_2 + 1)
1115 #define VEX_LEN_D1_P_2  (VEX_LEN_C5_P_2 + 1)
1116 #define VEX_LEN_D2_P_2  (VEX_LEN_D1_P_2 + 1)
1117 #define VEX_LEN_D3_P_2  (VEX_LEN_D2_P_2 + 1)
1118 #define VEX_LEN_D4_P_2  (VEX_LEN_D3_P_2 + 1)
1119 #define VEX_LEN_D5_P_2  (VEX_LEN_D4_P_2 + 1)
1120 #define VEX_LEN_D6_P_2  (VEX_LEN_D5_P_2 + 1)
1121 #define VEX_LEN_D7_P_2_M_1      (VEX_LEN_D6_P_2 + 1)
1122 #define VEX_LEN_D8_P_2  (VEX_LEN_D7_P_2_M_1 + 1)
1123 #define VEX_LEN_D9_P_2  (VEX_LEN_D8_P_2 + 1)
1124 #define VEX_LEN_DA_P_2  (VEX_LEN_D9_P_2 + 1)
1125 #define VEX_LEN_DB_P_2  (VEX_LEN_DA_P_2 + 1)
1126 #define VEX_LEN_DC_P_2  (VEX_LEN_DB_P_2 + 1)
1127 #define VEX_LEN_DD_P_2  (VEX_LEN_DC_P_2 + 1)
1128 #define VEX_LEN_DE_P_2  (VEX_LEN_DD_P_2 + 1)
1129 #define VEX_LEN_DF_P_2  (VEX_LEN_DE_P_2 + 1)
1130 #define VEX_LEN_E0_P_2  (VEX_LEN_DF_P_2 + 1)
1131 #define VEX_LEN_E1_P_2  (VEX_LEN_E0_P_2 + 1)
1132 #define VEX_LEN_E2_P_2  (VEX_LEN_E1_P_2 + 1)
1133 #define VEX_LEN_E3_P_2  (VEX_LEN_E2_P_2 + 1)
1134 #define VEX_LEN_E4_P_2  (VEX_LEN_E3_P_2 + 1)
1135 #define VEX_LEN_E5_P_2  (VEX_LEN_E4_P_2 + 1)
1136 #define VEX_LEN_E7_P_2_M_0      (VEX_LEN_E5_P_2 + 1)
1137 #define VEX_LEN_E8_P_2  (VEX_LEN_E7_P_2_M_0 + 1)
1138 #define VEX_LEN_E9_P_2  (VEX_LEN_E8_P_2 + 1)
1139 #define VEX_LEN_EA_P_2  (VEX_LEN_E9_P_2 + 1)
1140 #define VEX_LEN_EB_P_2  (VEX_LEN_EA_P_2 + 1)
1141 #define VEX_LEN_EC_P_2  (VEX_LEN_EB_P_2 + 1)
1142 #define VEX_LEN_ED_P_2  (VEX_LEN_EC_P_2 + 1)
1143 #define VEX_LEN_EE_P_2  (VEX_LEN_ED_P_2 + 1)
1144 #define VEX_LEN_EF_P_2  (VEX_LEN_EE_P_2 + 1)
1145 #define VEX_LEN_F1_P_2  (VEX_LEN_EF_P_2 + 1)
1146 #define VEX_LEN_F2_P_2  (VEX_LEN_F1_P_2 + 1)
1147 #define VEX_LEN_F3_P_2  (VEX_LEN_F2_P_2 + 1)
1148 #define VEX_LEN_F4_P_2  (VEX_LEN_F3_P_2 + 1)
1149 #define VEX_LEN_F5_P_2  (VEX_LEN_F4_P_2 + 1)
1150 #define VEX_LEN_F6_P_2  (VEX_LEN_F5_P_2 + 1)
1151 #define VEX_LEN_F7_P_2  (VEX_LEN_F6_P_2 + 1)
1152 #define VEX_LEN_F8_P_2  (VEX_LEN_F7_P_2 + 1)
1153 #define VEX_LEN_F9_P_2  (VEX_LEN_F8_P_2 + 1)
1154 #define VEX_LEN_FA_P_2  (VEX_LEN_F9_P_2 + 1)
1155 #define VEX_LEN_FB_P_2  (VEX_LEN_FA_P_2 + 1)
1156 #define VEX_LEN_FC_P_2  (VEX_LEN_FB_P_2 + 1)
1157 #define VEX_LEN_FD_P_2  (VEX_LEN_FC_P_2 + 1)
1158 #define VEX_LEN_FE_P_2  (VEX_LEN_FD_P_2 + 1)
1159 #define VEX_LEN_3800_P_2        (VEX_LEN_FE_P_2 + 1)
1160 #define VEX_LEN_3801_P_2        (VEX_LEN_3800_P_2 + 1)
1161 #define VEX_LEN_3802_P_2        (VEX_LEN_3801_P_2 + 1)
1162 #define VEX_LEN_3803_P_2        (VEX_LEN_3802_P_2 + 1)
1163 #define VEX_LEN_3804_P_2        (VEX_LEN_3803_P_2 + 1)
1164 #define VEX_LEN_3805_P_2        (VEX_LEN_3804_P_2 + 1)
1165 #define VEX_LEN_3806_P_2        (VEX_LEN_3805_P_2 + 1)
1166 #define VEX_LEN_3807_P_2        (VEX_LEN_3806_P_2 + 1)
1167 #define VEX_LEN_3808_P_2        (VEX_LEN_3807_P_2 + 1)
1168 #define VEX_LEN_3809_P_2        (VEX_LEN_3808_P_2 + 1)
1169 #define VEX_LEN_380A_P_2        (VEX_LEN_3809_P_2 + 1)
1170 #define VEX_LEN_380B_P_2        (VEX_LEN_380A_P_2 + 1)
1171 #define VEX_LEN_3819_P_2_M_0    (VEX_LEN_380B_P_2 + 1)
1172 #define VEX_LEN_381A_P_2_M_0    (VEX_LEN_3819_P_2_M_0 + 1)
1173 #define VEX_LEN_381C_P_2        (VEX_LEN_381A_P_2_M_0 + 1)
1174 #define VEX_LEN_381D_P_2        (VEX_LEN_381C_P_2 + 1)
1175 #define VEX_LEN_381E_P_2        (VEX_LEN_381D_P_2 + 1)
1176 #define VEX_LEN_3820_P_2        (VEX_LEN_381E_P_2 + 1)
1177 #define VEX_LEN_3821_P_2        (VEX_LEN_3820_P_2 + 1)
1178 #define VEX_LEN_3822_P_2        (VEX_LEN_3821_P_2 + 1)
1179 #define VEX_LEN_3823_P_2        (VEX_LEN_3822_P_2 + 1)
1180 #define VEX_LEN_3824_P_2        (VEX_LEN_3823_P_2 + 1)
1181 #define VEX_LEN_3825_P_2        (VEX_LEN_3824_P_2 + 1)
1182 #define VEX_LEN_3828_P_2        (VEX_LEN_3825_P_2 + 1)
1183 #define VEX_LEN_3829_P_2        (VEX_LEN_3828_P_2 + 1)
1184 #define VEX_LEN_382A_P_2_M_0    (VEX_LEN_3829_P_2 + 1)
1185 #define VEX_LEN_382B_P_2        (VEX_LEN_382A_P_2_M_0 + 1)
1186 #define VEX_LEN_3830_P_2        (VEX_LEN_382B_P_2 + 1)
1187 #define VEX_LEN_3831_P_2        (VEX_LEN_3830_P_2 + 1)
1188 #define VEX_LEN_3832_P_2        (VEX_LEN_3831_P_2 + 1)
1189 #define VEX_LEN_3833_P_2        (VEX_LEN_3832_P_2 + 1)
1190 #define VEX_LEN_3834_P_2        (VEX_LEN_3833_P_2 + 1)
1191 #define VEX_LEN_3835_P_2        (VEX_LEN_3834_P_2 + 1)
1192 #define VEX_LEN_3837_P_2        (VEX_LEN_3835_P_2 + 1)
1193 #define VEX_LEN_3838_P_2        (VEX_LEN_3837_P_2 + 1)
1194 #define VEX_LEN_3839_P_2        (VEX_LEN_3838_P_2 + 1)
1195 #define VEX_LEN_383A_P_2        (VEX_LEN_3839_P_2 + 1)
1196 #define VEX_LEN_383B_P_2        (VEX_LEN_383A_P_2 + 1)
1197 #define VEX_LEN_383C_P_2        (VEX_LEN_383B_P_2 + 1)
1198 #define VEX_LEN_383D_P_2        (VEX_LEN_383C_P_2 + 1)
1199 #define VEX_LEN_383E_P_2        (VEX_LEN_383D_P_2 + 1)
1200 #define VEX_LEN_383F_P_2        (VEX_LEN_383E_P_2 + 1)
1201 #define VEX_LEN_3840_P_2        (VEX_LEN_383F_P_2 + 1)
1202 #define VEX_LEN_3841_P_2        (VEX_LEN_3840_P_2 + 1)
1203 #define VEX_LEN_3A06_P_2        (VEX_LEN_3841_P_2 + 1)
1204 #define VEX_LEN_3A0A_P_2        (VEX_LEN_3A06_P_2 + 1)
1205 #define VEX_LEN_3A0B_P_2        (VEX_LEN_3A0A_P_2 + 1)
1206 #define VEX_LEN_3A0E_P_2        (VEX_LEN_3A0B_P_2 + 1)
1207 #define VEX_LEN_3A0F_P_2        (VEX_LEN_3A0E_P_2 + 1)
1208 #define VEX_LEN_3A14_P_2        (VEX_LEN_3A0F_P_2 + 1)
1209 #define VEX_LEN_3A15_P_2        (VEX_LEN_3A14_P_2 + 1)
1210 #define VEX_LEN_3A16_P_2        (VEX_LEN_3A15_P_2 + 1)
1211 #define VEX_LEN_3A17_P_2        (VEX_LEN_3A16_P_2 + 1)
1212 #define VEX_LEN_3A18_P_2        (VEX_LEN_3A17_P_2 + 1)
1213 #define VEX_LEN_3A19_P_2        (VEX_LEN_3A18_P_2 + 1)
1214 #define VEX_LEN_3A20_P_2        (VEX_LEN_3A19_P_2 + 1)
1215 #define VEX_LEN_3A21_P_2        (VEX_LEN_3A20_P_2 + 1)
1216 #define VEX_LEN_3A22_P_2        (VEX_LEN_3A21_P_2 + 1)
1217 #define VEX_LEN_3A41_P_2        (VEX_LEN_3A22_P_2 + 1)
1218 #define VEX_LEN_3A42_P_2        (VEX_LEN_3A41_P_2 + 1)
1219 #define VEX_LEN_3A4C_P_2        (VEX_LEN_3A42_P_2 + 1)
1220 #define VEX_LEN_3A60_P_2        (VEX_LEN_3A4C_P_2 + 1)
1221 #define VEX_LEN_3A61_P_2        (VEX_LEN_3A60_P_2 + 1)
1222 #define VEX_LEN_3A62_P_2        (VEX_LEN_3A61_P_2 + 1)
1223 #define VEX_LEN_3A63_P_2        (VEX_LEN_3A62_P_2 + 1)
1224 #define VEX_LEN_3A6A_P_2        (VEX_LEN_3A63_P_2 + 1)
1225 #define VEX_LEN_3A6B_P_2        (VEX_LEN_3A6A_P_2 + 1)
1226 #define VEX_LEN_3A6E_P_2        (VEX_LEN_3A6B_P_2 + 1)
1227 #define VEX_LEN_3A6F_P_2        (VEX_LEN_3A6E_P_2 + 1)
1228 #define VEX_LEN_3A7A_P_2        (VEX_LEN_3A6F_P_2 + 1)
1229 #define VEX_LEN_3A7B_P_2        (VEX_LEN_3A7A_P_2 + 1)
1230 #define VEX_LEN_3A7E_P_2        (VEX_LEN_3A7B_P_2 + 1)
1231 #define VEX_LEN_3A7F_P_2        (VEX_LEN_3A7E_P_2 + 1)
1232
1233 typedef void (*op_rtn) (int bytemode, int sizeflag);
1234
1235 struct dis386 {
1236   const char *name;
1237   struct
1238     {
1239       op_rtn rtn;
1240       int bytemode;
1241     } op[MAX_OPERANDS];
1242 };
1243
1244 /* Upper case letters in the instruction names here are macros.
1245    'A' => print 'b' if no register operands or suffix_always is true
1246    'B' => print 'b' if suffix_always is true
1247    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1248           size prefix
1249    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1250           suffix_always is true
1251    'E' => print 'e' if 32-bit form of jcxz
1252    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1253    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1254    'H' => print ",pt" or ",pn" branch hint
1255    'I' => honor following macro letter even in Intel mode (implemented only
1256           for some of the macro letters)
1257    'J' => print 'l'
1258    'K' => print 'd' or 'q' if rex prefix is present.
1259    'L' => print 'l' if suffix_always is true
1260    'M' => print 'r' if intel_mnemonic is false.
1261    'N' => print 'n' if instruction has no wait "prefix"
1262    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1263    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1264           or suffix_always is true.  print 'q' if rex prefix is present.
1265    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1266           is true
1267    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1268    'S' => print 'w', 'l' or 'q' if suffix_always is true
1269    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1270    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1271    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1272    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1273    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1274    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1275           suffix_always is true.
1276    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1277    '!' => change condition from true to false or from false to true.
1278    '%' => add 1 upper case letter to the macro.
1279
1280    2 upper case letter macros:
1281    "XY" => print 'x' or 'y' if no register operands or suffix_always
1282            is true.
1283    'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1284            or suffix_always is true
1285
1286    Many of the above letters print nothing in Intel mode.  See "putop"
1287    for the details.
1288
1289    Braces '{' and '}', and vertical bars '|', indicate alternative
1290    mnemonic strings for AT&T and Intel.  */
1291
1292 static const struct dis386 dis386[] = {
1293   /* 00 */
1294   { "addB",             { Eb, Gb } },
1295   { "addS",             { Ev, Gv } },
1296   { "addB",             { Gb, Eb } },
1297   { "addS",             { Gv, Ev } },
1298   { "addB",             { AL, Ib } },
1299   { "addS",             { eAX, Iv } },
1300   { X86_64_TABLE (X86_64_06) },
1301   { X86_64_TABLE (X86_64_07) },
1302   /* 08 */
1303   { "orB",              { Eb, Gb } },
1304   { "orS",              { Ev, Gv } },
1305   { "orB",              { Gb, Eb } },
1306   { "orS",              { Gv, Ev } },
1307   { "orB",              { AL, Ib } },
1308   { "orS",              { eAX, Iv } },
1309   { X86_64_TABLE (X86_64_0D) },
1310   { "(bad)",            { XX } },       /* 0x0f extended opcode escape */
1311   /* 10 */
1312   { "adcB",             { Eb, Gb } },
1313   { "adcS",             { Ev, Gv } },
1314   { "adcB",             { Gb, Eb } },
1315   { "adcS",             { Gv, Ev } },
1316   { "adcB",             { AL, Ib } },
1317   { "adcS",             { eAX, Iv } },
1318   { X86_64_TABLE (X86_64_16) },
1319   { X86_64_TABLE (X86_64_17) },
1320   /* 18 */
1321   { "sbbB",             { Eb, Gb } },
1322   { "sbbS",             { Ev, Gv } },
1323   { "sbbB",             { Gb, Eb } },
1324   { "sbbS",             { Gv, Ev } },
1325   { "sbbB",             { AL, Ib } },
1326   { "sbbS",             { eAX, Iv } },
1327   { X86_64_TABLE (X86_64_1E) },
1328   { X86_64_TABLE (X86_64_1F) },
1329   /* 20 */
1330   { "andB",             { Eb, Gb } },
1331   { "andS",             { Ev, Gv } },
1332   { "andB",             { Gb, Eb } },
1333   { "andS",             { Gv, Ev } },
1334   { "andB",             { AL, Ib } },
1335   { "andS",             { eAX, Iv } },
1336   { "(bad)",            { XX } },       /* SEG ES prefix */
1337   { X86_64_TABLE (X86_64_27) },
1338   /* 28 */
1339   { "subB",             { Eb, Gb } },
1340   { "subS",             { Ev, Gv } },
1341   { "subB",             { Gb, Eb } },
1342   { "subS",             { Gv, Ev } },
1343   { "subB",             { AL, Ib } },
1344   { "subS",             { eAX, Iv } },
1345   { "(bad)",            { XX } },       /* SEG CS prefix */
1346   { X86_64_TABLE (X86_64_2F) },
1347   /* 30 */
1348   { "xorB",             { Eb, Gb } },
1349   { "xorS",             { Ev, Gv } },
1350   { "xorB",             { Gb, Eb } },
1351   { "xorS",             { Gv, Ev } },
1352   { "xorB",             { AL, Ib } },
1353   { "xorS",             { eAX, Iv } },
1354   { "(bad)",            { XX } },       /* SEG SS prefix */
1355   { X86_64_TABLE (X86_64_37) },
1356   /* 38 */
1357   { "cmpB",             { Eb, Gb } },
1358   { "cmpS",             { Ev, Gv } },
1359   { "cmpB",             { Gb, Eb } },
1360   { "cmpS",             { Gv, Ev } },
1361   { "cmpB",             { AL, Ib } },
1362   { "cmpS",             { eAX, Iv } },
1363   { "(bad)",            { XX } },       /* SEG DS prefix */
1364   { X86_64_TABLE (X86_64_3F) },
1365   /* 40 */
1366   { "inc{S|}",          { RMeAX } },
1367   { "inc{S|}",          { RMeCX } },
1368   { "inc{S|}",          { RMeDX } },
1369   { "inc{S|}",          { RMeBX } },
1370   { "inc{S|}",          { RMeSP } },
1371   { "inc{S|}",          { RMeBP } },
1372   { "inc{S|}",          { RMeSI } },
1373   { "inc{S|}",          { RMeDI } },
1374   /* 48 */
1375   { "dec{S|}",          { RMeAX } },
1376   { "dec{S|}",          { RMeCX } },
1377   { "dec{S|}",          { RMeDX } },
1378   { "dec{S|}",          { RMeBX } },
1379   { "dec{S|}",          { RMeSP } },
1380   { "dec{S|}",          { RMeBP } },
1381   { "dec{S|}",          { RMeSI } },
1382   { "dec{S|}",          { RMeDI } },
1383   /* 50 */
1384   { "pushV",            { RMrAX } },
1385   { "pushV",            { RMrCX } },
1386   { "pushV",            { RMrDX } },
1387   { "pushV",            { RMrBX } },
1388   { "pushV",            { RMrSP } },
1389   { "pushV",            { RMrBP } },
1390   { "pushV",            { RMrSI } },
1391   { "pushV",            { RMrDI } },
1392   /* 58 */
1393   { "popV",             { RMrAX } },
1394   { "popV",             { RMrCX } },
1395   { "popV",             { RMrDX } },
1396   { "popV",             { RMrBX } },
1397   { "popV",             { RMrSP } },
1398   { "popV",             { RMrBP } },
1399   { "popV",             { RMrSI } },
1400   { "popV",             { RMrDI } },
1401   /* 60 */
1402   { X86_64_TABLE (X86_64_60) },
1403   { X86_64_TABLE (X86_64_61) },
1404   { X86_64_TABLE (X86_64_62) },
1405   { X86_64_TABLE (X86_64_63) },
1406   { "(bad)",            { XX } },       /* seg fs */
1407   { "(bad)",            { XX } },       /* seg gs */
1408   { "(bad)",            { XX } },       /* op size prefix */
1409   { "(bad)",            { XX } },       /* adr size prefix */
1410   /* 68 */
1411   { "pushT",            { Iq } },
1412   { "imulS",            { Gv, Ev, Iv } },
1413   { "pushT",            { sIb } },
1414   { "imulS",            { Gv, Ev, sIb } },
1415   { "ins{b|}",          { Ybr, indirDX } },
1416   { X86_64_TABLE (X86_64_6D) },
1417   { "outs{b|}",         { indirDXr, Xb } },
1418   { X86_64_TABLE (X86_64_6F) },
1419   /* 70 */
1420   { "joH",              { Jb, XX, cond_jump_flag } },
1421   { "jnoH",             { Jb, XX, cond_jump_flag } },
1422   { "jbH",              { Jb, XX, cond_jump_flag } },
1423   { "jaeH",             { Jb, XX, cond_jump_flag } },
1424   { "jeH",              { Jb, XX, cond_jump_flag } },
1425   { "jneH",             { Jb, XX, cond_jump_flag } },
1426   { "jbeH",             { Jb, XX, cond_jump_flag } },
1427   { "jaH",              { Jb, XX, cond_jump_flag } },
1428   /* 78 */
1429   { "jsH",              { Jb, XX, cond_jump_flag } },
1430   { "jnsH",             { Jb, XX, cond_jump_flag } },
1431   { "jpH",              { Jb, XX, cond_jump_flag } },
1432   { "jnpH",             { Jb, XX, cond_jump_flag } },
1433   { "jlH",              { Jb, XX, cond_jump_flag } },
1434   { "jgeH",             { Jb, XX, cond_jump_flag } },
1435   { "jleH",             { Jb, XX, cond_jump_flag } },
1436   { "jgH",              { Jb, XX, cond_jump_flag } },
1437   /* 80 */
1438   { REG_TABLE (REG_80) },
1439   { REG_TABLE (REG_81) },
1440   { "(bad)",            { XX } },
1441   { REG_TABLE (REG_82) },
1442   { "testB",            { Eb, Gb } },
1443   { "testS",            { Ev, Gv } },
1444   { "xchgB",            { Eb, Gb } },
1445   { "xchgS",            { Ev, Gv } },
1446   /* 88 */
1447   { "movB",             { Eb, Gb } },
1448   { "movS",             { Ev, Gv } },
1449   { "movB",             { Gb, Eb } },
1450   { "movS",             { Gv, Ev } },
1451   { "movD",             { Sv, Sw } },
1452   { MOD_TABLE (MOD_8D) },
1453   { "movD",             { Sw, Sv } },
1454   { REG_TABLE (REG_8F) },
1455   /* 90 */
1456   { PREFIX_TABLE (PREFIX_90) },
1457   { "xchgS",            { RMeCX, eAX } },
1458   { "xchgS",            { RMeDX, eAX } },
1459   { "xchgS",            { RMeBX, eAX } },
1460   { "xchgS",            { RMeSP, eAX } },
1461   { "xchgS",            { RMeBP, eAX } },
1462   { "xchgS",            { RMeSI, eAX } },
1463   { "xchgS",            { RMeDI, eAX } },
1464   /* 98 */
1465   { "cW{t|}R",          { XX } },
1466   { "cR{t|}O",          { XX } },
1467   { X86_64_TABLE (X86_64_9A) },
1468   { "(bad)",            { XX } },       /* fwait */
1469   { "pushfT",           { XX } },
1470   { "popfT",            { XX } },
1471   { "sahf",             { XX } },
1472   { "lahf",             { XX } },
1473   /* a0 */
1474   { "movB",             { AL, Ob } },
1475   { "movS",             { eAX, Ov } },
1476   { "movB",             { Ob, AL } },
1477   { "movS",             { Ov, eAX } },
1478   { "movs{b|}",         { Ybr, Xb } },
1479   { "movs{R|}",         { Yvr, Xv } },
1480   { "cmps{b|}",         { Xb, Yb } },
1481   { "cmps{R|}",         { Xv, Yv } },
1482   /* a8 */
1483   { "testB",            { AL, Ib } },
1484   { "testS",            { eAX, Iv } },
1485   { "stosB",            { Ybr, AL } },
1486   { "stosS",            { Yvr, eAX } },
1487   { "lodsB",            { ALr, Xb } },
1488   { "lodsS",            { eAXr, Xv } },
1489   { "scasB",            { AL, Yb } },
1490   { "scasS",            { eAX, Yv } },
1491   /* b0 */
1492   { "movB",             { RMAL, Ib } },
1493   { "movB",             { RMCL, Ib } },
1494   { "movB",             { RMDL, Ib } },
1495   { "movB",             { RMBL, Ib } },
1496   { "movB",             { RMAH, Ib } },
1497   { "movB",             { RMCH, Ib } },
1498   { "movB",             { RMDH, Ib } },
1499   { "movB",             { RMBH, Ib } },
1500   /* b8 */
1501   { "movS",             { RMeAX, Iv64 } },
1502   { "movS",             { RMeCX, Iv64 } },
1503   { "movS",             { RMeDX, Iv64 } },
1504   { "movS",             { RMeBX, Iv64 } },
1505   { "movS",             { RMeSP, Iv64 } },
1506   { "movS",             { RMeBP, Iv64 } },
1507   { "movS",             { RMeSI, Iv64 } },
1508   { "movS",             { RMeDI, Iv64 } },
1509   /* c0 */
1510   { REG_TABLE (REG_C0) },
1511   { REG_TABLE (REG_C1) },
1512   { "retT",             { Iw } },
1513   { "retT",             { XX } },
1514   { X86_64_TABLE (X86_64_C4) },
1515   { X86_64_TABLE (X86_64_C5) },
1516   { REG_TABLE (REG_C6) },
1517   { REG_TABLE (REG_C7) },
1518   /* c8 */
1519   { "enterT",           { Iw, Ib } },
1520   { "leaveT",           { XX } },
1521   { "lretP",            { Iw } },
1522   { "lretP",            { XX } },
1523   { "int3",             { XX } },
1524   { "int",              { Ib } },
1525   { X86_64_TABLE (X86_64_CE) },
1526   { "iretP",            { XX } },
1527   /* d0 */
1528   { REG_TABLE (REG_D0) },
1529   { REG_TABLE (REG_D1) },
1530   { REG_TABLE (REG_D2) },
1531   { REG_TABLE (REG_D3) },
1532   { X86_64_TABLE (X86_64_D4) },
1533   { X86_64_TABLE (X86_64_D5) },
1534   { "(bad)",            { XX } },
1535   { "xlat",             { DSBX } },
1536   /* d8 */
1537   { FLOAT },
1538   { FLOAT },
1539   { FLOAT },
1540   { FLOAT },
1541   { FLOAT },
1542   { FLOAT },
1543   { FLOAT },
1544   { FLOAT },
1545   /* e0 */
1546   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1547   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1548   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1549   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1550   { "inB",              { AL, Ib } },
1551   { "inG",              { zAX, Ib } },
1552   { "outB",             { Ib, AL } },
1553   { "outG",             { Ib, zAX } },
1554   /* e8 */
1555   { "callT",            { Jv } },
1556   { "jmpT",             { Jv } },
1557   { X86_64_TABLE (X86_64_EA) },
1558   { "jmp",              { Jb } },
1559   { "inB",              { AL, indirDX } },
1560   { "inG",              { zAX, indirDX } },
1561   { "outB",             { indirDX, AL } },
1562   { "outG",             { indirDX, zAX } },
1563   /* f0 */
1564   { "(bad)",            { XX } },       /* lock prefix */
1565   { "icebp",            { XX } },
1566   { "(bad)",            { XX } },       /* repne */
1567   { "(bad)",            { XX } },       /* repz */
1568   { "hlt",              { XX } },
1569   { "cmc",              { XX } },
1570   { REG_TABLE (REG_F6) },
1571   { REG_TABLE (REG_F7) },
1572   /* f8 */
1573   { "clc",              { XX } },
1574   { "stc",              { XX } },
1575   { "cli",              { XX } },
1576   { "sti",              { XX } },
1577   { "cld",              { XX } },
1578   { "std",              { XX } },
1579   { REG_TABLE (REG_FE) },
1580   { REG_TABLE (REG_FF) },
1581 };
1582
1583 static const struct dis386 dis386_twobyte[] = {
1584   /* 00 */
1585   { REG_TABLE (REG_0F00 ) },
1586   { REG_TABLE (REG_0F01 ) },
1587   { "larS",             { Gv, Ew } },
1588   { "lslS",             { Gv, Ew } },
1589   { "(bad)",            { XX } },
1590   { "syscall",          { XX } },
1591   { "clts",             { XX } },
1592   { "sysretP",          { XX } },
1593   /* 08 */
1594   { "invd",             { XX } },
1595   { "wbinvd",           { XX } },
1596   { "(bad)",            { XX } },
1597   { "ud2a",             { XX } },
1598   { "(bad)",            { XX } },
1599   { REG_TABLE (REG_0F0D) },
1600   { "femms",            { XX } },
1601   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1602   /* 10 */
1603   { PREFIX_TABLE (PREFIX_0F10) },
1604   { PREFIX_TABLE (PREFIX_0F11) },
1605   { PREFIX_TABLE (PREFIX_0F12) },
1606   { MOD_TABLE (MOD_0F13) },
1607   { "unpcklpX",         { XM, EXx } },
1608   { "unpckhpX",         { XM, EXx } },
1609   { PREFIX_TABLE (PREFIX_0F16) },
1610   { MOD_TABLE (MOD_0F17) },
1611   /* 18 */
1612   { REG_TABLE (REG_0F18) },
1613   { "nopQ",             { Ev } },
1614   { "nopQ",             { Ev } },
1615   { "nopQ",             { Ev } },
1616   { "nopQ",             { Ev } },
1617   { "nopQ",             { Ev } },
1618   { "nopQ",             { Ev } },
1619   { "nopQ",             { Ev } },
1620   /* 20 */
1621   { MOD_TABLE (MOD_0F20) },
1622   { MOD_TABLE (MOD_0F21) },
1623   { MOD_TABLE (MOD_0F22) },
1624   { MOD_TABLE (MOD_0F23) },
1625   { MOD_TABLE (MOD_0F24) },
1626   { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1627   { MOD_TABLE (MOD_0F26) },
1628   { "(bad)",            { XX } },
1629   /* 28 */
1630   { "movapX",           { XM, EXx } },
1631   { "movapX",           { EXx, XM } },
1632   { PREFIX_TABLE (PREFIX_0F2A) },
1633   { PREFIX_TABLE (PREFIX_0F2B) },
1634   { PREFIX_TABLE (PREFIX_0F2C) },
1635   { PREFIX_TABLE (PREFIX_0F2D) },
1636   { PREFIX_TABLE (PREFIX_0F2E) },
1637   { PREFIX_TABLE (PREFIX_0F2F) },
1638   /* 30 */
1639   { "wrmsr",            { XX } },
1640   { "rdtsc",            { XX } },
1641   { "rdmsr",            { XX } },
1642   { "rdpmc",            { XX } },
1643   { "sysenter",         { XX } },
1644   { "sysexit",          { XX } },
1645   { "(bad)",            { XX } },
1646   { "getsec",           { XX } },
1647   /* 38 */
1648   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1649   { "(bad)",            { XX } },
1650   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1651   { "(bad)",            { XX } },
1652   { "(bad)",            { XX } },
1653   { "(bad)",            { XX } },
1654   { "(bad)",            { XX } },
1655   { "(bad)",            { XX } },
1656   /* 40 */
1657   { "cmovo",            { Gv, Ev } },
1658   { "cmovno",           { Gv, Ev } },
1659   { "cmovb",            { Gv, Ev } },
1660   { "cmovae",           { Gv, Ev } },
1661   { "cmove",            { Gv, Ev } },
1662   { "cmovne",           { Gv, Ev } },
1663   { "cmovbe",           { Gv, Ev } },
1664   { "cmova",            { Gv, Ev } },
1665   /* 48 */
1666   { "cmovs",            { Gv, Ev } },
1667   { "cmovns",           { Gv, Ev } },
1668   { "cmovp",            { Gv, Ev } },
1669   { "cmovnp",           { Gv, Ev } },
1670   { "cmovl",            { Gv, Ev } },
1671   { "cmovge",           { Gv, Ev } },
1672   { "cmovle",           { Gv, Ev } },
1673   { "cmovg",            { Gv, Ev } },
1674   /* 50 */
1675   { MOD_TABLE (MOD_0F51) },
1676   { PREFIX_TABLE (PREFIX_0F51) },
1677   { PREFIX_TABLE (PREFIX_0F52) },
1678   { PREFIX_TABLE (PREFIX_0F53) },
1679   { "andpX",            { XM, EXx } },
1680   { "andnpX",           { XM, EXx } },
1681   { "orpX",             { XM, EXx } },
1682   { "xorpX",            { XM, EXx } },
1683   /* 58 */
1684   { PREFIX_TABLE (PREFIX_0F58) },
1685   { PREFIX_TABLE (PREFIX_0F59) },
1686   { PREFIX_TABLE (PREFIX_0F5A) },
1687   { PREFIX_TABLE (PREFIX_0F5B) },
1688   { PREFIX_TABLE (PREFIX_0F5C) },
1689   { PREFIX_TABLE (PREFIX_0F5D) },
1690   { PREFIX_TABLE (PREFIX_0F5E) },
1691   { PREFIX_TABLE (PREFIX_0F5F) },
1692   /* 60 */
1693   { PREFIX_TABLE (PREFIX_0F60) },
1694   { PREFIX_TABLE (PREFIX_0F61) },
1695   { PREFIX_TABLE (PREFIX_0F62) },
1696   { "packsswb",         { MX, EM } },
1697   { "pcmpgtb",          { MX, EM } },
1698   { "pcmpgtw",          { MX, EM } },
1699   { "pcmpgtd",          { MX, EM } },
1700   { "packuswb",         { MX, EM } },
1701   /* 68 */
1702   { "punpckhbw",        { MX, EM } },
1703   { "punpckhwd",        { MX, EM } },
1704   { "punpckhdq",        { MX, EM } },
1705   { "packssdw",         { MX, EM } },
1706   { PREFIX_TABLE (PREFIX_0F6C) },
1707   { PREFIX_TABLE (PREFIX_0F6D) },
1708   { "movK",             { MX, Edq } },
1709   { PREFIX_TABLE (PREFIX_0F6F) },
1710   /* 70 */
1711   { PREFIX_TABLE (PREFIX_0F70) },
1712   { REG_TABLE (REG_0F71) },
1713   { REG_TABLE (REG_0F72) },
1714   { REG_TABLE (REG_0F73) },
1715   { "pcmpeqb",          { MX, EM } },
1716   { "pcmpeqw",          { MX, EM } },
1717   { "pcmpeqd",          { MX, EM } },
1718   { "emms",             { XX } },
1719   /* 78 */
1720   { PREFIX_TABLE (PREFIX_0F78) },
1721   { PREFIX_TABLE (PREFIX_0F79) },
1722   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1723   { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1724   { PREFIX_TABLE (PREFIX_0F7C) },
1725   { PREFIX_TABLE (PREFIX_0F7D) },
1726   { PREFIX_TABLE (PREFIX_0F7E) },
1727   { PREFIX_TABLE (PREFIX_0F7F) },
1728   /* 80 */
1729   { "joH",              { Jv, XX, cond_jump_flag } },
1730   { "jnoH",             { Jv, XX, cond_jump_flag } },
1731   { "jbH",              { Jv, XX, cond_jump_flag } },
1732   { "jaeH",             { Jv, XX, cond_jump_flag } },
1733   { "jeH",              { Jv, XX, cond_jump_flag } },
1734   { "jneH",             { Jv, XX, cond_jump_flag } },
1735   { "jbeH",             { Jv, XX, cond_jump_flag } },
1736   { "jaH",              { Jv, XX, cond_jump_flag } },
1737   /* 88 */
1738   { "jsH",              { Jv, XX, cond_jump_flag } },
1739   { "jnsH",             { Jv, XX, cond_jump_flag } },
1740   { "jpH",              { Jv, XX, cond_jump_flag } },
1741   { "jnpH",             { Jv, XX, cond_jump_flag } },
1742   { "jlH",              { Jv, XX, cond_jump_flag } },
1743   { "jgeH",             { Jv, XX, cond_jump_flag } },
1744   { "jleH",             { Jv, XX, cond_jump_flag } },
1745   { "jgH",              { Jv, XX, cond_jump_flag } },
1746   /* 90 */
1747   { "seto",             { Eb } },
1748   { "setno",            { Eb } },
1749   { "setb",             { Eb } },
1750   { "setae",            { Eb } },
1751   { "sete",             { Eb } },
1752   { "setne",            { Eb } },
1753   { "setbe",            { Eb } },
1754   { "seta",             { Eb } },
1755   /* 98 */
1756   { "sets",             { Eb } },
1757   { "setns",            { Eb } },
1758   { "setp",             { Eb } },
1759   { "setnp",            { Eb } },
1760   { "setl",             { Eb } },
1761   { "setge",            { Eb } },
1762   { "setle",            { Eb } },
1763   { "setg",             { Eb } },
1764   /* a0 */
1765   { "pushT",            { fs } },
1766   { "popT",             { fs } },
1767   { "cpuid",            { XX } },
1768   { "btS",              { Ev, Gv } },
1769   { "shldS",            { Ev, Gv, Ib } },
1770   { "shldS",            { Ev, Gv, CL } },
1771   { REG_TABLE (REG_0FA6) },
1772   { REG_TABLE (REG_0FA7) },
1773   /* a8 */
1774   { "pushT",            { gs } },
1775   { "popT",             { gs } },
1776   { "rsm",              { XX } },
1777   { "btsS",             { Ev, Gv } },
1778   { "shrdS",            { Ev, Gv, Ib } },
1779   { "shrdS",            { Ev, Gv, CL } },
1780   { REG_TABLE (REG_0FAE) },
1781   { "imulS",            { Gv, Ev } },
1782   /* b0 */
1783   { "cmpxchgB",         { Eb, Gb } },
1784   { "cmpxchgS",         { Ev, Gv } },
1785   { MOD_TABLE (MOD_0FB2) },
1786   { "btrS",             { Ev, Gv } },
1787   { MOD_TABLE (MOD_0FB4) },
1788   { MOD_TABLE (MOD_0FB5) },
1789   { "movz{bR|x}",       { Gv, Eb } },
1790   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
1791   /* b8 */
1792   { PREFIX_TABLE (PREFIX_0FB8) },
1793   { "ud2b",             { XX } },
1794   { REG_TABLE (REG_0FBA) },
1795   { "btcS",             { Ev, Gv } },
1796   { "bsfS",             { Gv, Ev } },
1797   { PREFIX_TABLE (PREFIX_0FBD) },
1798   { "movs{bR|x}",       { Gv, Eb } },
1799   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
1800   /* c0 */
1801   { "xaddB",            { Eb, Gb } },
1802   { "xaddS",            { Ev, Gv } },
1803   { PREFIX_TABLE (PREFIX_0FC2) },
1804   { PREFIX_TABLE (PREFIX_0FC3) },
1805   { "pinsrw",           { MX, Edqw, Ib } },
1806   { "pextrw",           { Gdq, MS, Ib } },
1807   { "shufpX",           { XM, EXx, Ib } },
1808   { REG_TABLE (REG_0FC7) },
1809   /* c8 */
1810   { "bswap",            { RMeAX } },
1811   { "bswap",            { RMeCX } },
1812   { "bswap",            { RMeDX } },
1813   { "bswap",            { RMeBX } },
1814   { "bswap",            { RMeSP } },
1815   { "bswap",            { RMeBP } },
1816   { "bswap",            { RMeSI } },
1817   { "bswap",            { RMeDI } },
1818   /* d0 */
1819   { PREFIX_TABLE (PREFIX_0FD0) },
1820   { "psrlw",            { MX, EM } },
1821   { "psrld",            { MX, EM } },
1822   { "psrlq",            { MX, EM } },
1823   { "paddq",            { MX, EM } },
1824   { "pmullw",           { MX, EM } },
1825   { PREFIX_TABLE (PREFIX_0FD6) },
1826   { MOD_TABLE (MOD_0FD7) },
1827   /* d8 */
1828   { "psubusb",          { MX, EM } },
1829   { "psubusw",          { MX, EM } },
1830   { "pminub",           { MX, EM } },
1831   { "pand",             { MX, EM } },
1832   { "paddusb",          { MX, EM } },
1833   { "paddusw",          { MX, EM } },
1834   { "pmaxub",           { MX, EM } },
1835   { "pandn",            { MX, EM } },
1836   /* e0 */
1837   { "pavgb",            { MX, EM } },
1838   { "psraw",            { MX, EM } },
1839   { "psrad",            { MX, EM } },
1840   { "pavgw",            { MX, EM } },
1841   { "pmulhuw",          { MX, EM } },
1842   { "pmulhw",           { MX, EM } },
1843   { PREFIX_TABLE (PREFIX_0FE6) },
1844   { PREFIX_TABLE (PREFIX_0FE7) },
1845   /* e8 */
1846   { "psubsb",           { MX, EM } },
1847   { "psubsw",           { MX, EM } },
1848   { "pminsw",           { MX, EM } },
1849   { "por",              { MX, EM } },
1850   { "paddsb",           { MX, EM } },
1851   { "paddsw",           { MX, EM } },
1852   { "pmaxsw",           { MX, EM } },
1853   { "pxor",             { MX, EM } },
1854   /* f0 */
1855   { PREFIX_TABLE (PREFIX_0FF0) },
1856   { "psllw",            { MX, EM } },
1857   { "pslld",            { MX, EM } },
1858   { "psllq",            { MX, EM } },
1859   { "pmuludq",          { MX, EM } },
1860   { "pmaddwd",          { MX, EM } },
1861   { "psadbw",           { MX, EM } },
1862   { PREFIX_TABLE (PREFIX_0FF7) },
1863   /* f8 */
1864   { "psubb",            { MX, EM } },
1865   { "psubw",            { MX, EM } },
1866   { "psubd",            { MX, EM } },
1867   { "psubq",            { MX, EM } },
1868   { "paddb",            { MX, EM } },
1869   { "paddw",            { MX, EM } },
1870   { "paddd",            { MX, EM } },
1871   { "(bad)",            { XX } },
1872 };
1873
1874 static const unsigned char onebyte_has_modrm[256] = {
1875   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1876   /*       -------------------------------        */
1877   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1878   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1879   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1880   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1881   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1882   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1883   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1884   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1885   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1886   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1887   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1888   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1889   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1890   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1891   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1892   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
1893   /*       -------------------------------        */
1894   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1895 };
1896
1897 static const unsigned char twobyte_has_modrm[256] = {
1898   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1899   /*       -------------------------------        */
1900   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1901   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1902   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1903   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1904   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1905   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1906   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1907   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1908   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1909   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1910   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1911   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1912   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1913   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1914   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1915   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
1916   /*       -------------------------------        */
1917   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
1918 };
1919
1920 static char obuf[100];
1921 static char *obufp;
1922 static char scratchbuf[100];
1923 static unsigned char *start_codep;
1924 static unsigned char *insn_codep;
1925 static unsigned char *codep;
1926 static const char *lock_prefix;
1927 static const char *data_prefix;
1928 static const char *addr_prefix;
1929 static const char *repz_prefix;
1930 static const char *repnz_prefix;
1931 static disassemble_info *the_info;
1932 static struct
1933   {
1934     int mod;
1935     int reg;
1936     int rm;
1937   }
1938 modrm;
1939 static unsigned char need_modrm;
1940 static struct
1941   {
1942     int register_specifier;
1943     int length;
1944     int prefix;
1945     int w;
1946   }
1947 vex;
1948 static unsigned char need_vex;
1949 static unsigned char need_vex_reg;
1950 static unsigned char vex_w_done;
1951
1952 /* If we are accessing mod/rm/reg without need_modrm set, then the
1953    values are stale.  Hitting this abort likely indicates that you
1954    need to update onebyte_has_modrm or twobyte_has_modrm.  */
1955 #define MODRM_CHECK  if (!need_modrm) abort ()
1956
1957 static const char **names64;
1958 static const char **names32;
1959 static const char **names16;
1960 static const char **names8;
1961 static const char **names8rex;
1962 static const char **names_seg;
1963 static const char *index64;
1964 static const char *index32;
1965 static const char **index16;
1966
1967 static const char *intel_names64[] = {
1968   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
1969   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1970 };
1971 static const char *intel_names32[] = {
1972   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
1973   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
1974 };
1975 static const char *intel_names16[] = {
1976   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
1977   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
1978 };
1979 static const char *intel_names8[] = {
1980   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
1981 };
1982 static const char *intel_names8rex[] = {
1983   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
1984   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
1985 };
1986 static const char *intel_names_seg[] = {
1987   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
1988 };
1989 static const char *intel_index64 = "riz";
1990 static const char *intel_index32 = "eiz";
1991 static const char *intel_index16[] = {
1992   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
1993 };
1994
1995 static const char *att_names64[] = {
1996   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
1997   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
1998 };
1999 static const char *att_names32[] = {
2000   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2001   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2002 };
2003 static const char *att_names16[] = {
2004   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2005   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2006 };
2007 static const char *att_names8[] = {
2008   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2009 };
2010 static const char *att_names8rex[] = {
2011   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2012   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2013 };
2014 static const char *att_names_seg[] = {
2015   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2016 };
2017 static const char *att_index64 = "%riz";
2018 static const char *att_index32 = "%eiz";
2019 static const char *att_index16[] = {
2020   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2021 };
2022
2023 static const struct dis386 reg_table[][8] = {
2024   /* REG_80 */
2025   {
2026     { "addA",   { Eb, Ib } },
2027     { "orA",    { Eb, Ib } },
2028     { "adcA",   { Eb, Ib } },
2029     { "sbbA",   { Eb, Ib } },
2030     { "andA",   { Eb, Ib } },
2031     { "subA",   { Eb, Ib } },
2032     { "xorA",   { Eb, Ib } },
2033     { "cmpA",   { Eb, Ib } },
2034   },
2035   /* REG_81 */
2036   {
2037     { "addQ",   { Ev, Iv } },
2038     { "orQ",    { Ev, Iv } },
2039     { "adcQ",   { Ev, Iv } },
2040     { "sbbQ",   { Ev, Iv } },
2041     { "andQ",   { Ev, Iv } },
2042     { "subQ",   { Ev, Iv } },
2043     { "xorQ",   { Ev, Iv } },
2044     { "cmpQ",   { Ev, Iv } },
2045   },
2046   /* REG_82 */
2047   {
2048     { "addQ",   { Ev, sIb } },
2049     { "orQ",    { Ev, sIb } },
2050     { "adcQ",   { Ev, sIb } },
2051     { "sbbQ",   { Ev, sIb } },
2052     { "andQ",   { Ev, sIb } },
2053     { "subQ",   { Ev, sIb } },
2054     { "xorQ",   { Ev, sIb } },
2055     { "cmpQ",   { Ev, sIb } },
2056   },
2057   /* REG_8F */
2058   {
2059     { "popU",   { stackEv } },
2060     { "(bad)",  { XX } },
2061     { "(bad)",  { XX } },
2062     { "(bad)",  { XX } },
2063     { "(bad)",  { XX } },
2064     { "(bad)",  { XX } },
2065     { "(bad)",  { XX } },
2066     { "(bad)",  { XX } },
2067   },
2068   /* REG_C0 */
2069   {
2070     { "rolA",   { Eb, Ib } },
2071     { "rorA",   { Eb, Ib } },
2072     { "rclA",   { Eb, Ib } },
2073     { "rcrA",   { Eb, Ib } },
2074     { "shlA",   { Eb, Ib } },
2075     { "shrA",   { Eb, Ib } },
2076     { "(bad)",  { XX } },
2077     { "sarA",   { Eb, Ib } },
2078   },
2079   /* REG_C1 */
2080   {
2081     { "rolQ",   { Ev, Ib } },
2082     { "rorQ",   { Ev, Ib } },
2083     { "rclQ",   { Ev, Ib } },
2084     { "rcrQ",   { Ev, Ib } },
2085     { "shlQ",   { Ev, Ib } },
2086     { "shrQ",   { Ev, Ib } },
2087     { "(bad)",  { XX } },
2088     { "sarQ",   { Ev, Ib } },
2089   },
2090   /* REG_C6 */
2091   {
2092     { "movA",   { Eb, Ib } },
2093     { "(bad)",  { XX } },
2094     { "(bad)",  { XX } },
2095     { "(bad)",  { XX } },
2096     { "(bad)",  { XX } },
2097     { "(bad)",  { XX } },
2098     { "(bad)",  { XX } },
2099     { "(bad)",  { XX } },
2100   },
2101   /* REG_C7 */
2102   {
2103     { "movQ",   { Ev, Iv } },
2104     { "(bad)",  { XX } },
2105     { "(bad)",  { XX } },
2106     { "(bad)",  { XX } },
2107     { "(bad)",  { XX } },
2108     { "(bad)",  { XX } },
2109     { "(bad)",  { XX } },
2110     { "(bad)",  { XX } },
2111   },
2112   /* REG_D0 */
2113   {
2114     { "rolA",   { Eb, I1 } },
2115     { "rorA",   { Eb, I1 } },
2116     { "rclA",   { Eb, I1 } },
2117     { "rcrA",   { Eb, I1 } },
2118     { "shlA",   { Eb, I1 } },
2119     { "shrA",   { Eb, I1 } },
2120     { "(bad)",  { XX } },
2121     { "sarA",   { Eb, I1 } },
2122   },
2123   /* REG_D1 */
2124   {
2125     { "rolQ",   { Ev, I1 } },
2126     { "rorQ",   { Ev, I1 } },
2127     { "rclQ",   { Ev, I1 } },
2128     { "rcrQ",   { Ev, I1 } },
2129     { "shlQ",   { Ev, I1 } },
2130     { "shrQ",   { Ev, I1 } },
2131     { "(bad)",  { XX } },
2132     { "sarQ",   { Ev, I1 } },
2133   },
2134   /* REG_D2 */
2135   {
2136     { "rolA",   { Eb, CL } },
2137     { "rorA",   { Eb, CL } },
2138     { "rclA",   { Eb, CL } },
2139     { "rcrA",   { Eb, CL } },
2140     { "shlA",   { Eb, CL } },
2141     { "shrA",   { Eb, CL } },
2142     { "(bad)",  { XX } },
2143     { "sarA",   { Eb, CL } },
2144   },
2145   /* REG_D3 */
2146   {
2147     { "rolQ",   { Ev, CL } },
2148     { "rorQ",   { Ev, CL } },
2149     { "rclQ",   { Ev, CL } },
2150     { "rcrQ",   { Ev, CL } },
2151     { "shlQ",   { Ev, CL } },
2152     { "shrQ",   { Ev, CL } },
2153     { "(bad)",  { XX } },
2154     { "sarQ",   { Ev, CL } },
2155   },
2156   /* REG_F6 */
2157   {
2158     { "testA",  { Eb, Ib } },
2159     { "(bad)",  { XX } },
2160     { "notA",   { Eb } },
2161     { "negA",   { Eb } },
2162     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2163     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2164     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2165     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2166   },
2167   /* REG_F7 */
2168   {
2169     { "testQ",  { Ev, Iv } },
2170     { "(bad)",  { XX } },
2171     { "notQ",   { Ev } },
2172     { "negQ",   { Ev } },
2173     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2174     { "imulQ",  { Ev } },
2175     { "divQ",   { Ev } },
2176     { "idivQ",  { Ev } },
2177   },
2178   /* REG_FE */
2179   {
2180     { "incA",   { Eb } },
2181     { "decA",   { Eb } },
2182     { "(bad)",  { XX } },
2183     { "(bad)",  { XX } },
2184     { "(bad)",  { XX } },
2185     { "(bad)",  { XX } },
2186     { "(bad)",  { XX } },
2187     { "(bad)",  { XX } },
2188   },
2189   /* REG_FF */
2190   {
2191     { "incQ",   { Ev } },
2192     { "decQ",   { Ev } },
2193     { "callT",  { indirEv } },
2194     { "JcallT", { indirEp } },
2195     { "jmpT",   { indirEv } },
2196     { "JjmpT",  { indirEp } },
2197     { "pushU",  { stackEv } },
2198     { "(bad)",  { XX } },
2199   },
2200   /* REG_0F00 */
2201   {
2202     { "sldtD",  { Sv } },
2203     { "strD",   { Sv } },
2204     { "lldt",   { Ew } },
2205     { "ltr",    { Ew } },
2206     { "verr",   { Ew } },
2207     { "verw",   { Ew } },
2208     { "(bad)",  { XX } },
2209     { "(bad)",  { XX } },
2210   },
2211   /* REG_0F01 */
2212   {
2213     { MOD_TABLE (MOD_0F01_REG_0) },
2214     { MOD_TABLE (MOD_0F01_REG_1) },
2215     { MOD_TABLE (MOD_0F01_REG_2) },
2216     { MOD_TABLE (MOD_0F01_REG_3) },
2217     { "smswD",  { Sv } },
2218     { "(bad)",  { XX } },
2219     { "lmsw",   { Ew } },
2220     { MOD_TABLE (MOD_0F01_REG_7) },
2221   },
2222   /* REG_0F0D */
2223   {
2224     { "prefetch",       { Eb } },
2225     { "prefetchw",      { Eb } },
2226     { "(bad)",          { XX } },
2227     { "(bad)",          { XX } },
2228     { "(bad)",          { XX } },
2229     { "(bad)",          { XX } },
2230     { "(bad)",          { XX } },
2231     { "(bad)",          { XX } },
2232   },
2233   /* REG_0F18 */
2234   {
2235     { MOD_TABLE (MOD_0F18_REG_0) },
2236     { MOD_TABLE (MOD_0F18_REG_1) },
2237     { MOD_TABLE (MOD_0F18_REG_2) },
2238     { MOD_TABLE (MOD_0F18_REG_3) },
2239     { "(bad)",  { XX } },
2240     { "(bad)",  { XX } },
2241     { "(bad)",  { XX } },
2242     { "(bad)",  { XX } },
2243   },
2244   /* REG_0F71 */
2245   {
2246     { "(bad)",  { XX } },
2247     { "(bad)",  { XX } },
2248     { MOD_TABLE (MOD_0F71_REG_2) },
2249     { "(bad)",  { XX } },
2250     { MOD_TABLE (MOD_0F71_REG_4) },
2251     { "(bad)",  { XX } },
2252     { MOD_TABLE (MOD_0F71_REG_6) },
2253     { "(bad)",  { XX } },
2254   },
2255   /* REG_0F72 */
2256   {
2257     { "(bad)",  { XX } },
2258     { "(bad)",  { XX } },
2259     { MOD_TABLE (MOD_0F72_REG_2) },
2260     { "(bad)",  { XX } },
2261     { MOD_TABLE (MOD_0F72_REG_4) },
2262     { "(bad)",  { XX } },
2263     { MOD_TABLE (MOD_0F72_REG_6) },
2264     { "(bad)",  { XX } },
2265   },
2266   /* REG_0F73 */
2267   {
2268     { "(bad)",  { XX } },
2269     { "(bad)",  { XX } },
2270     { MOD_TABLE (MOD_0F73_REG_2) },
2271     { MOD_TABLE (MOD_0F73_REG_3) },
2272     { "(bad)",  { XX } },
2273     { "(bad)",  { XX } },
2274     { MOD_TABLE (MOD_0F73_REG_6) },
2275     { MOD_TABLE (MOD_0F73_REG_7) },
2276   },
2277   /* REG_0FA6 */
2278   {
2279     { "montmul",        { { OP_0f07, 0 } } },
2280     { "xsha1",          { { OP_0f07, 0 } } },
2281     { "xsha256",        { { OP_0f07, 0 } } },
2282     { "(bad)",          { { OP_0f07, 0 } } },
2283     { "(bad)",          { { OP_0f07, 0 } } },
2284     { "(bad)",          { { OP_0f07, 0 } } },
2285     { "(bad)",          { { OP_0f07, 0 } } },
2286     { "(bad)",          { { OP_0f07, 0 } } },
2287   },
2288   /* REG_0FA7 */
2289   {
2290     { "xstore-rng",     { { OP_0f07, 0 } } },
2291     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2292     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2293     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2294     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2295     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2296     { "(bad)",          { { OP_0f07, 0 } } },
2297     { "(bad)",          { { OP_0f07, 0 } } },
2298   },
2299   /* REG_0FAE */
2300   {
2301     { MOD_TABLE (MOD_0FAE_REG_0) },
2302     { MOD_TABLE (MOD_0FAE_REG_1) },
2303     { MOD_TABLE (MOD_0FAE_REG_2) },
2304     { MOD_TABLE (MOD_0FAE_REG_3) },
2305     { MOD_TABLE (MOD_0FAE_REG_4) },
2306     { MOD_TABLE (MOD_0FAE_REG_5) },
2307     { MOD_TABLE (MOD_0FAE_REG_6) },
2308     { MOD_TABLE (MOD_0FAE_REG_7) },
2309   },
2310   /* REG_0FBA */
2311   {
2312     { "(bad)",  { XX } },
2313     { "(bad)",  { XX } },
2314     { "(bad)",  { XX } },
2315     { "(bad)",  { XX } },
2316     { "btQ",    { Ev, Ib } },
2317     { "btsQ",   { Ev, Ib } },
2318     { "btrQ",   { Ev, Ib } },
2319     { "btcQ",   { Ev, Ib } },
2320   },
2321   /* REG_0FC7 */
2322   {
2323     { "(bad)",  { XX } },
2324     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2325     { "(bad)",  { XX } },
2326     { "(bad)",  { XX } },
2327     { "(bad)",  { XX } },
2328     { "(bad)",  { XX } },
2329     { MOD_TABLE (MOD_0FC7_REG_6) },
2330     { MOD_TABLE (MOD_0FC7_REG_7) },
2331   },
2332   /* REG_VEX_71 */
2333   {
2334     { "(bad)",  { XX } },
2335     { "(bad)",  { XX } },
2336     { MOD_TABLE (MOD_VEX_71_REG_2) },
2337     { "(bad)",  { XX } },
2338     { MOD_TABLE (MOD_VEX_71_REG_4) },
2339     { "(bad)",  { XX } },
2340     { MOD_TABLE (MOD_VEX_71_REG_6) },
2341     { "(bad)",  { XX } },
2342   },
2343   /* REG_VEX_72 */
2344   {
2345     { "(bad)",  { XX } },
2346     { "(bad)",  { XX } },
2347     { MOD_TABLE (MOD_VEX_72_REG_2) },
2348     { "(bad)",  { XX } },
2349     { MOD_TABLE (MOD_VEX_72_REG_4) },
2350     { "(bad)",  { XX } },
2351     { MOD_TABLE (MOD_VEX_72_REG_6) },
2352     { "(bad)",  { XX } },
2353   },
2354   /* REG_VEX_73 */
2355   {
2356     { "(bad)",  { XX } },
2357     { "(bad)",  { XX } },
2358     { MOD_TABLE (MOD_VEX_73_REG_2) },
2359     { MOD_TABLE (MOD_VEX_73_REG_3) },
2360     { "(bad)",  { XX } },
2361     { "(bad)",  { XX } },
2362     { MOD_TABLE (MOD_VEX_73_REG_6) },
2363     { MOD_TABLE (MOD_VEX_73_REG_7) },
2364   },
2365   /* REG_VEX_AE */
2366   {
2367     { "(bad)",  { XX } },
2368     { "(bad)",  { XX } },
2369     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2370     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2371     { "(bad)",  { XX } },
2372     { "(bad)",  { XX } },
2373     { "(bad)",  { XX } },
2374     { "(bad)",  { XX } },
2375   },
2376 };
2377
2378 static const struct dis386 prefix_table[][4] = {
2379   /* PREFIX_90 */
2380   {
2381     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2382     { "pause", { XX } },
2383     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2384     { "(bad)", { XX } },
2385   },
2386
2387   /* PREFIX_0F10 */
2388   {
2389     { "movups", { XM, EXx } },
2390     { "movss",  { XM, EXd } },
2391     { "movupd", { XM, EXx } },
2392     { "movsd",  { XM, EXq } },
2393   },
2394
2395   /* PREFIX_0F11 */
2396   {
2397     { "movups", { EXx, XM } },
2398     { "movss",  { EXd, XM } },
2399     { "movupd", { EXx, XM } },
2400     { "movsd",  { EXq, XM } },
2401   },
2402
2403   /* PREFIX_0F12 */
2404   {
2405     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2406     { "movsldup", { XM, EXx } },
2407     { "movlpd", { XM, EXq } },
2408     { "movddup", { XM, EXq } },
2409   },
2410
2411   /* PREFIX_0F16 */
2412   {
2413     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2414     { "movshdup", { XM, EXx } },
2415     { "movhpd", { XM, EXq } },
2416     { "(bad)",  { XX } },
2417   },
2418
2419   /* PREFIX_0F2A */
2420   {
2421     { "cvtpi2ps", { XM, EMCq } },
2422     { "cvtsi2ss%LQ", { XM, Ev } },
2423     { "cvtpi2pd", { XM, EMCq } },
2424     { "cvtsi2sd%LQ", { XM, Ev } },
2425   },
2426
2427   /* PREFIX_0F2B */
2428   {
2429     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2430     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2431     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2432     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2433   },
2434
2435   /* PREFIX_0F2C */
2436   {
2437     { "cvttps2pi", { MXC, EXq } },
2438     { "cvttss2siY", { Gv, EXd } },
2439     { "cvttpd2pi", { MXC, EXx } },
2440     { "cvttsd2siY", { Gv, EXq } },
2441   },
2442
2443   /* PREFIX_0F2D */
2444   {
2445     { "cvtps2pi", { MXC, EXq } },
2446     { "cvtss2siY", { Gv, EXd } },
2447     { "cvtpd2pi", { MXC, EXx } },
2448     { "cvtsd2siY", { Gv, EXq } },
2449   },
2450
2451   /* PREFIX_0F2E */
2452   {
2453     { "ucomiss",{ XM, EXd } },
2454     { "(bad)",  { XX } },
2455     { "ucomisd",{ XM, EXq } },
2456     { "(bad)",  { XX } },
2457   },
2458
2459   /* PREFIX_0F2F */
2460   {
2461     { "comiss", { XM, EXd } },
2462     { "(bad)",  { XX } },
2463     { "comisd", { XM, EXq } },
2464     { "(bad)",  { XX } },
2465   },
2466
2467   /* PREFIX_0F51 */
2468   {
2469     { "sqrtps", { XM, EXx } },
2470     { "sqrtss", { XM, EXd } },
2471     { "sqrtpd", { XM, EXx } },
2472     { "sqrtsd", { XM, EXq } },
2473   },
2474
2475   /* PREFIX_0F52 */
2476   {
2477     { "rsqrtps",{ XM, EXx } },
2478     { "rsqrtss",{ XM, EXd } },
2479     { "(bad)",  { XX } },
2480     { "(bad)",  { XX } },
2481   },
2482
2483   /* PREFIX_0F53 */
2484   {
2485     { "rcpps",  { XM, EXx } },
2486     { "rcpss",  { XM, EXd } },
2487     { "(bad)",  { XX } },
2488     { "(bad)",  { XX } },
2489   },
2490
2491   /* PREFIX_0F58 */
2492   {
2493     { "addps", { XM, EXx } },
2494     { "addss", { XM, EXd } },
2495     { "addpd", { XM, EXx } },
2496     { "addsd", { XM, EXq } },
2497   },
2498
2499   /* PREFIX_0F59 */
2500   {
2501     { "mulps",  { XM, EXx } },
2502     { "mulss",  { XM, EXd } },
2503     { "mulpd",  { XM, EXx } },
2504     { "mulsd",  { XM, EXq } },
2505   },
2506
2507   /* PREFIX_0F5A */
2508   {
2509     { "cvtps2pd", { XM, EXq } },
2510     { "cvtss2sd", { XM, EXd } },
2511     { "cvtpd2ps", { XM, EXx } },
2512     { "cvtsd2ss", { XM, EXq } },
2513   },
2514
2515   /* PREFIX_0F5B */
2516   {
2517     { "cvtdq2ps", { XM, EXx } },
2518     { "cvttps2dq", { XM, EXx } },
2519     { "cvtps2dq", { XM, EXx } },
2520     { "(bad)",  { XX } },
2521   },
2522
2523   /* PREFIX_0F5C */
2524   {
2525     { "subps",  { XM, EXx } },
2526     { "subss",  { XM, EXd } },
2527     { "subpd",  { XM, EXx } },
2528     { "subsd",  { XM, EXq } },
2529   },
2530
2531   /* PREFIX_0F5D */
2532   {
2533     { "minps",  { XM, EXx } },
2534     { "minss",  { XM, EXd } },
2535     { "minpd",  { XM, EXx } },
2536     { "minsd",  { XM, EXq } },
2537   },
2538
2539   /* PREFIX_0F5E */
2540   {
2541     { "divps",  { XM, EXx } },
2542     { "divss",  { XM, EXd } },
2543     { "divpd",  { XM, EXx } },
2544     { "divsd",  { XM, EXq } },
2545   },
2546
2547   /* PREFIX_0F5F */
2548   {
2549     { "maxps",  { XM, EXx } },
2550     { "maxss",  { XM, EXd } },
2551     { "maxpd",  { XM, EXx } },
2552     { "maxsd",  { XM, EXq } },
2553   },
2554
2555   /* PREFIX_0F60 */
2556   {
2557     { "punpcklbw",{ MX, EMd } },
2558     { "(bad)",  { XX } },
2559     { "punpcklbw",{ MX, EMx } },
2560     { "(bad)",  { XX } },
2561   },
2562
2563   /* PREFIX_0F61 */
2564   {
2565     { "punpcklwd",{ MX, EMd } },
2566     { "(bad)",  { XX } },
2567     { "punpcklwd",{ MX, EMx } },
2568     { "(bad)",  { XX } },
2569   },
2570
2571   /* PREFIX_0F62 */
2572   {
2573     { "punpckldq",{ MX, EMd } },
2574     { "(bad)",  { XX } },
2575     { "punpckldq",{ MX, EMx } },
2576     { "(bad)",  { XX } },
2577   },
2578
2579   /* PREFIX_0F6C */
2580   {
2581     { "(bad)",  { XX } },
2582     { "(bad)",  { XX } },
2583     { "punpcklqdq", { XM, EXx } },
2584     { "(bad)",  { XX } },
2585   },
2586
2587   /* PREFIX_0F6D */
2588   {
2589     { "(bad)",  { XX } },
2590     { "(bad)",  { XX } },
2591     { "punpckhqdq", { XM, EXx } },
2592     { "(bad)",  { XX } },
2593   },
2594
2595   /* PREFIX_0F6F */
2596   {
2597     { "movq",   { MX, EM } },
2598     { "movdqu", { XM, EXx } },
2599     { "movdqa", { XM, EXx } },
2600     { "(bad)",  { XX } },
2601   },
2602
2603   /* PREFIX_0F70 */
2604   {
2605     { "pshufw", { MX, EM, Ib } },
2606     { "pshufhw",{ XM, EXx, Ib } },
2607     { "pshufd", { XM, EXx, Ib } },
2608     { "pshuflw",{ XM, EXx, Ib } },
2609   },
2610
2611   /* PREFIX_0F73_REG_3 */
2612   {
2613     { "(bad)",  { XX } },
2614     { "(bad)",  { XX } },
2615     { "psrldq", { XS, Ib } },
2616     { "(bad)",  { XX } },
2617   },
2618
2619   /* PREFIX_0F73_REG_7 */
2620   {
2621     { "(bad)",  { XX } },
2622     { "(bad)",  { XX } },
2623     { "pslldq", { XS, Ib } },
2624     { "(bad)",  { XX } },
2625   },
2626
2627   /* PREFIX_0F78 */
2628   {
2629     {"vmread",  { Em, Gm } },
2630     {"(bad)",   { XX } },
2631     {"extrq",   { XS, Ib, Ib } },
2632     {"insertq", { XM, XS, Ib, Ib } },
2633   },
2634
2635   /* PREFIX_0F79 */
2636   {
2637     {"vmwrite", { Gm, Em } },
2638     {"(bad)",   { XX } },
2639     {"extrq",   { XM, XS } },
2640     {"insertq", { XM, XS } },
2641   },
2642
2643   /* PREFIX_0F7C */
2644   {
2645     { "(bad)",  { XX } },
2646     { "(bad)",  { XX } },
2647     { "haddpd", { XM, EXx } },
2648     { "haddps", { XM, EXx } },
2649   },
2650
2651   /* PREFIX_0F7D */
2652   {
2653     { "(bad)",  { XX } },
2654     { "(bad)",  { XX } },
2655     { "hsubpd", { XM, EXx } },
2656     { "hsubps", { XM, EXx } },
2657   },
2658
2659   /* PREFIX_0F7E */
2660   {
2661     { "movK",   { Edq, MX } },
2662     { "movq",   { XM, EXq } },
2663     { "movK",   { Edq, XM } },
2664     { "(bad)",  { XX } },
2665   },
2666
2667   /* PREFIX_0F7F */
2668   {
2669     { "movq",   { EM, MX } },
2670     { "movdqu", { EXx, XM } },
2671     { "movdqa", { EXx, XM } },
2672     { "(bad)",  { XX } },
2673   },
2674
2675   /* PREFIX_0FB8 */
2676   {
2677     { "(bad)", { XX } },
2678     { "popcntS", { Gv, Ev } },
2679     { "(bad)", { XX } },
2680     { "(bad)", { XX } },
2681   },
2682
2683   /* PREFIX_0FBD */
2684   {
2685     { "bsrS",   { Gv, Ev } },
2686     { "lzcntS", { Gv, Ev } },
2687     { "bsrS",   { Gv, Ev } },
2688     { "(bad)",  { XX } },
2689   },
2690
2691   /* PREFIX_0FC2 */
2692   {
2693     { "cmpps",  { XM, EXx, CMP } },
2694     { "cmpss",  { XM, EXd, CMP } },
2695     { "cmppd",  { XM, EXx, CMP } },
2696     { "cmpsd",  { XM, EXq, CMP } },
2697   },
2698
2699   /* PREFIX_0FC3 */
2700   {
2701     { "movntiS", { Ma, Gv } },
2702     { "(bad)",  { XX } },
2703     { "(bad)",  { XX } },
2704     { "(bad)",  { XX } },
2705   },
2706
2707   /* PREFIX_0FC7_REG_6 */
2708   {
2709     { "vmptrld",{ Mq } },
2710     { "vmxon",  { Mq } },
2711     { "vmclear",{ Mq } },
2712     { "(bad)",  { XX } },
2713   },
2714
2715   /* PREFIX_0FD0 */
2716   {
2717     { "(bad)",  { XX } },
2718     { "(bad)",  { XX } },
2719     { "addsubpd", { XM, EXx } },
2720     { "addsubps", { XM, EXx } },
2721   },
2722
2723   /* PREFIX_0FD6 */
2724   {
2725     { "(bad)",  { XX } },
2726     { "movq2dq",{ XM, MS } },
2727     { "movq",   { EXq, XM } },
2728     { "movdq2q",{ MX, XS } },
2729   },
2730
2731   /* PREFIX_0FE6 */
2732   {
2733     { "(bad)",  { XX } },
2734     { "cvtdq2pd", { XM, EXq } },
2735     { "cvttpd2dq", { XM, EXx } },
2736     { "cvtpd2dq", { XM, EXx } },
2737   },
2738
2739   /* PREFIX_0FE7 */
2740   {
2741     { "movntq", { Mq, MX } },
2742     { "(bad)",  { XX } },
2743     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2744     { "(bad)",  { XX } },
2745   },
2746
2747   /* PREFIX_0FF0 */
2748   {
2749     { "(bad)",  { XX } },
2750     { "(bad)",  { XX } },
2751     { "(bad)",  { XX } },
2752     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2753   },
2754
2755   /* PREFIX_0FF7 */
2756   {
2757     { "maskmovq", { MX, MS } },
2758     { "(bad)",  { XX } },
2759     { "maskmovdqu", { XM, XS } },
2760     { "(bad)",  { XX } },
2761   },
2762
2763   /* PREFIX_0F3810 */
2764   {
2765     { "(bad)",  { XX } },
2766     { "(bad)",  { XX } },
2767     { "pblendvb", { XM, EXx, XMM0 } },
2768     { "(bad)",  { XX } },
2769   },
2770
2771   /* PREFIX_0F3814 */
2772   {
2773     { "(bad)",  { XX } },
2774     { "(bad)",  { XX } },
2775     { "blendvps", { XM, EXx, XMM0 } },
2776     { "(bad)",  { XX } },
2777   },
2778
2779   /* PREFIX_0F3815 */
2780   {
2781     { "(bad)",  { XX } },
2782     { "(bad)",  { XX } },
2783     { "blendvpd", { XM, EXx, XMM0 } },
2784     { "(bad)",  { XX } },
2785   },
2786
2787   /* PREFIX_0F3817 */
2788   {
2789     { "(bad)",  { XX } },
2790     { "(bad)",  { XX } },
2791     { "ptest",  { XM, EXx } },
2792     { "(bad)",  { XX } },
2793   },
2794
2795   /* PREFIX_0F3820 */
2796   {
2797     { "(bad)",  { XX } },
2798     { "(bad)",  { XX } },
2799     { "pmovsxbw", { XM, EXq } },
2800     { "(bad)",  { XX } },
2801   },
2802
2803   /* PREFIX_0F3821 */
2804   {
2805     { "(bad)",  { XX } },
2806     { "(bad)",  { XX } },
2807     { "pmovsxbd", { XM, EXd } },
2808     { "(bad)",  { XX } },
2809   },
2810
2811   /* PREFIX_0F3822 */
2812   {
2813     { "(bad)",  { XX } },
2814     { "(bad)",  { XX } },
2815     { "pmovsxbq", { XM, EXw } },
2816     { "(bad)",  { XX } },
2817   },
2818
2819   /* PREFIX_0F3823 */
2820   {
2821     { "(bad)",  { XX } },
2822     { "(bad)",  { XX } },
2823     { "pmovsxwd", { XM, EXq } },
2824     { "(bad)",  { XX } },
2825   },
2826
2827   /* PREFIX_0F3824 */
2828   {
2829     { "(bad)",  { XX } },
2830     { "(bad)",  { XX } },
2831     { "pmovsxwq", { XM, EXd } },
2832     { "(bad)",  { XX } },
2833   },
2834
2835   /* PREFIX_0F3825 */
2836   {
2837     { "(bad)",  { XX } },
2838     { "(bad)",  { XX } },
2839     { "pmovsxdq", { XM, EXq } },
2840     { "(bad)",  { XX } },
2841   },
2842
2843   /* PREFIX_0F3828 */
2844   {
2845     { "(bad)",  { XX } },
2846     { "(bad)",  { XX } },
2847     { "pmuldq", { XM, EXx } },
2848     { "(bad)",  { XX } },
2849   },
2850
2851   /* PREFIX_0F3829 */
2852   {
2853     { "(bad)",  { XX } },
2854     { "(bad)",  { XX } },
2855     { "pcmpeqq", { XM, EXx } },
2856     { "(bad)",  { XX } },
2857   },
2858
2859   /* PREFIX_0F382A */
2860   {
2861     { "(bad)",  { XX } },
2862     { "(bad)",  { XX } },
2863     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2864     { "(bad)",  { XX } },
2865   },
2866
2867   /* PREFIX_0F382B */
2868   {
2869     { "(bad)",  { XX } },
2870     { "(bad)",  { XX } },
2871     { "packusdw", { XM, EXx } },
2872     { "(bad)",  { XX } },
2873   },
2874
2875   /* PREFIX_0F3830 */
2876   {
2877     { "(bad)",  { XX } },
2878     { "(bad)",  { XX } },
2879     { "pmovzxbw", { XM, EXq } },
2880     { "(bad)",  { XX } },
2881   },
2882
2883   /* PREFIX_0F3831 */
2884   {
2885     { "(bad)",  { XX } },
2886     { "(bad)",  { XX } },
2887     { "pmovzxbd", { XM, EXd } },
2888     { "(bad)",  { XX } },
2889   },
2890
2891   /* PREFIX_0F3832 */
2892   {
2893     { "(bad)",  { XX } },
2894     { "(bad)",  { XX } },
2895     { "pmovzxbq", { XM, EXw } },
2896     { "(bad)",  { XX } },
2897   },
2898
2899   /* PREFIX_0F3833 */
2900   {
2901     { "(bad)",  { XX } },
2902     { "(bad)",  { XX } },
2903     { "pmovzxwd", { XM, EXq } },
2904     { "(bad)",  { XX } },
2905   },
2906
2907   /* PREFIX_0F3834 */
2908   {
2909     { "(bad)",  { XX } },
2910     { "(bad)",  { XX } },
2911     { "pmovzxwq", { XM, EXd } },
2912     { "(bad)",  { XX } },
2913   },
2914
2915   /* PREFIX_0F3835 */
2916   {
2917     { "(bad)",  { XX } },
2918     { "(bad)",  { XX } },
2919     { "pmovzxdq", { XM, EXq } },
2920     { "(bad)",  { XX } },
2921   },
2922
2923   /* PREFIX_0F3837 */
2924   {
2925     { "(bad)",  { XX } },
2926     { "(bad)",  { XX } },
2927     { "pcmpgtq", { XM, EXx } },
2928     { "(bad)",  { XX } },
2929   },
2930
2931   /* PREFIX_0F3838 */
2932   {
2933     { "(bad)",  { XX } },
2934     { "(bad)",  { XX } },
2935     { "pminsb", { XM, EXx } },
2936     { "(bad)",  { XX } },
2937   },
2938
2939   /* PREFIX_0F3839 */
2940   {
2941     { "(bad)",  { XX } },
2942     { "(bad)",  { XX } },
2943     { "pminsd", { XM, EXx } },
2944     { "(bad)",  { XX } },
2945   },
2946
2947   /* PREFIX_0F383A */
2948   {
2949     { "(bad)",  { XX } },
2950     { "(bad)",  { XX } },
2951     { "pminuw", { XM, EXx } },
2952     { "(bad)",  { XX } },
2953   },
2954
2955   /* PREFIX_0F383B */
2956   {
2957     { "(bad)",  { XX } },
2958     { "(bad)",  { XX } },
2959     { "pminud", { XM, EXx } },
2960     { "(bad)",  { XX } },
2961   },
2962
2963   /* PREFIX_0F383C */
2964   {
2965     { "(bad)",  { XX } },
2966     { "(bad)",  { XX } },
2967     { "pmaxsb", { XM, EXx } },
2968     { "(bad)",  { XX } },
2969   },
2970
2971   /* PREFIX_0F383D */
2972   {
2973     { "(bad)",  { XX } },
2974     { "(bad)",  { XX } },
2975     { "pmaxsd", { XM, EXx } },
2976     { "(bad)",  { XX } },
2977   },
2978
2979   /* PREFIX_0F383E */
2980   {
2981     { "(bad)",  { XX } },
2982     { "(bad)",  { XX } },
2983     { "pmaxuw", { XM, EXx } },
2984     { "(bad)",  { XX } },
2985   },
2986
2987   /* PREFIX_0F383F */
2988   {
2989     { "(bad)",  { XX } },
2990     { "(bad)",  { XX } },
2991     { "pmaxud", { XM, EXx } },
2992     { "(bad)",  { XX } },
2993   },
2994
2995   /* PREFIX_0F3840 */
2996   {
2997     { "(bad)",  { XX } },
2998     { "(bad)",  { XX } },
2999     { "pmulld", { XM, EXx } },
3000     { "(bad)",  { XX } },
3001   },
3002
3003   /* PREFIX_0F3841 */
3004   {
3005     { "(bad)",  { XX } },
3006     { "(bad)",  { XX } },
3007     { "phminposuw", { XM, EXx } },
3008     { "(bad)",  { XX } },
3009   },
3010
3011   /* PREFIX_0F3880 */
3012   {
3013     { "(bad)",  { XX } },
3014     { "(bad)",  { XX } },
3015     { "invept", { Gm, Mo } },
3016     { "(bad)",  { XX } },
3017   },
3018
3019   /* PREFIX_0F3881 */
3020   {
3021     { "(bad)",  { XX } },
3022     { "(bad)",  { XX } },
3023     { "invvpid", { Gm, Mo } },
3024     { "(bad)",  { XX } },
3025   },
3026
3027   /* PREFIX_0F38DB */
3028   {
3029     { "(bad)",  { XX } },
3030     { "(bad)",  { XX } },
3031     { "aesimc", { XM, EXx } },
3032     { "(bad)",  { XX } },
3033   },
3034
3035   /* PREFIX_0F38DC */
3036   {
3037     { "(bad)",  { XX } },
3038     { "(bad)",  { XX } },
3039     { "aesenc", { XM, EXx } },
3040     { "(bad)",  { XX } },
3041   },
3042
3043   /* PREFIX_0F38DD */
3044   {
3045     { "(bad)",  { XX } },
3046     { "(bad)",  { XX } },
3047     { "aesenclast", { XM, EXx } },
3048     { "(bad)",  { XX } },
3049   },
3050
3051   /* PREFIX_0F38DE */
3052   {
3053     { "(bad)",  { XX } },
3054     { "(bad)",  { XX } },
3055     { "aesdec", { XM, EXx } },
3056     { "(bad)",  { XX } },
3057   },
3058
3059   /* PREFIX_0F38DF */
3060   {
3061     { "(bad)",  { XX } },
3062     { "(bad)",  { XX } },
3063     { "aesdeclast", { XM, EXx } },
3064     { "(bad)",  { XX } },
3065   },
3066
3067   /* PREFIX_0F38F0 */
3068   {
3069     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3070     { "(bad)",  { XX } },
3071     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3072     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3073   },
3074
3075   /* PREFIX_0F38F1 */
3076   {
3077     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3078     { "(bad)",  { XX } },
3079     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3080     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3081   },
3082
3083   /* PREFIX_0F3A08 */
3084   {
3085     { "(bad)",  { XX } },
3086     { "(bad)",  { XX } },
3087     { "roundps", { XM, EXx, Ib } },
3088     { "(bad)",  { XX } },
3089   },
3090
3091   /* PREFIX_0F3A09 */
3092   {
3093     { "(bad)",  { XX } },
3094     { "(bad)",  { XX } },
3095     { "roundpd", { XM, EXx, Ib } },
3096     { "(bad)",  { XX } },
3097   },
3098
3099   /* PREFIX_0F3A0A */
3100   {
3101     { "(bad)",  { XX } },
3102     { "(bad)",  { XX } },
3103     { "roundss", { XM, EXd, Ib } },
3104     { "(bad)",  { XX } },
3105   },
3106
3107   /* PREFIX_0F3A0B */
3108   {
3109     { "(bad)",  { XX } },
3110     { "(bad)",  { XX } },
3111     { "roundsd", { XM, EXq, Ib } },
3112     { "(bad)",  { XX } },
3113   },
3114
3115   /* PREFIX_0F3A0C */
3116   {
3117     { "(bad)",  { XX } },
3118     { "(bad)",  { XX } },
3119     { "blendps", { XM, EXx, Ib } },
3120     { "(bad)",  { XX } },
3121   },
3122
3123   /* PREFIX_0F3A0D */
3124   {
3125     { "(bad)",  { XX } },
3126     { "(bad)",  { XX } },
3127     { "blendpd", { XM, EXx, Ib } },
3128     { "(bad)",  { XX } },
3129   },
3130
3131   /* PREFIX_0F3A0E */
3132   {
3133     { "(bad)",  { XX } },
3134     { "(bad)",  { XX } },
3135     { "pblendw", { XM, EXx, Ib } },
3136     { "(bad)",  { XX } },
3137   },
3138
3139   /* PREFIX_0F3A14 */
3140   {
3141     { "(bad)",  { XX } },
3142     { "(bad)",  { XX } },
3143     { "pextrb", { Edqb, XM, Ib } },
3144     { "(bad)",  { XX } },
3145   },
3146
3147   /* PREFIX_0F3A15 */
3148   {
3149     { "(bad)",  { XX } },
3150     { "(bad)",  { XX } },
3151     { "pextrw", { Edqw, XM, Ib } },
3152     { "(bad)",  { XX } },
3153   },
3154
3155   /* PREFIX_0F3A16 */
3156   {
3157     { "(bad)",  { XX } },
3158     { "(bad)",  { XX } },
3159     { "pextrK", { Edq, XM, Ib } },
3160     { "(bad)",  { XX } },
3161   },
3162
3163   /* PREFIX_0F3A17 */
3164   {
3165     { "(bad)",  { XX } },
3166     { "(bad)",  { XX } },
3167     { "extractps", { Edqd, XM, Ib } },
3168     { "(bad)",  { XX } },
3169   },
3170
3171   /* PREFIX_0F3A20 */
3172   {
3173     { "(bad)",  { XX } },
3174     { "(bad)",  { XX } },
3175     { "pinsrb", { XM, Edqb, Ib } },
3176     { "(bad)",  { XX } },
3177   },
3178
3179   /* PREFIX_0F3A21 */
3180   {
3181     { "(bad)",  { XX } },
3182     { "(bad)",  { XX } },
3183     { "insertps", { XM, EXd, Ib } },
3184     { "(bad)",  { XX } },
3185   },
3186
3187   /* PREFIX_0F3A22 */
3188   {
3189     { "(bad)",  { XX } },
3190     { "(bad)",  { XX } },
3191     { "pinsrK", { XM, Edq, Ib } },
3192     { "(bad)",  { XX } },
3193   },
3194
3195   /* PREFIX_0F3A40 */
3196   {
3197     { "(bad)",  { XX } },
3198     { "(bad)",  { XX } },
3199     { "dpps",   { XM, EXx, Ib } },
3200     { "(bad)",  { XX } },
3201   },
3202
3203   /* PREFIX_0F3A41 */
3204   {
3205     { "(bad)",  { XX } },
3206     { "(bad)",  { XX } },
3207     { "dppd",   { XM, EXx, Ib } },
3208     { "(bad)",  { XX } },
3209   },
3210
3211   /* PREFIX_0F3A42 */
3212   {
3213     { "(bad)",  { XX } },
3214     { "(bad)",  { XX } },
3215     { "mpsadbw", { XM, EXx, Ib } },
3216     { "(bad)",  { XX } },
3217   },
3218
3219   /* PREFIX_0F3A44 */
3220   {
3221     { "(bad)",  { XX } },
3222     { "(bad)",  { XX } },
3223     { "pclmulqdq", { XM, EXx, PCLMUL } },
3224     { "(bad)",  { XX } },
3225   },
3226
3227   /* PREFIX_0F3A60 */
3228   {
3229     { "(bad)",  { XX } },
3230     { "(bad)",  { XX } },
3231     { "pcmpestrm", { XM, EXx, Ib } },
3232     { "(bad)",  { XX } },
3233   },
3234
3235   /* PREFIX_0F3A61 */
3236   {
3237     { "(bad)",  { XX } },
3238     { "(bad)",  { XX } },
3239     { "pcmpestri", { XM, EXx, Ib } },
3240     { "(bad)",  { XX } },
3241   },
3242
3243   /* PREFIX_0F3A62 */
3244   {
3245     { "(bad)",  { XX } },
3246     { "(bad)",  { XX } },
3247     { "pcmpistrm", { XM, EXx, Ib } },
3248     { "(bad)",  { XX } },
3249   },
3250
3251   /* PREFIX_0F3A63 */
3252   {
3253     { "(bad)",  { XX } },
3254     { "(bad)",  { XX } },
3255     { "pcmpistri", { XM, EXx, Ib } },
3256     { "(bad)",  { XX } },
3257   },
3258
3259   /* PREFIX_0F3ADF */
3260   {
3261     { "(bad)",  { XX } },
3262     { "(bad)",  { XX } },
3263     { "aeskeygenassist", { XM, EXx, Ib } },
3264     { "(bad)",  { XX } },
3265   },
3266
3267   /* PREFIX_VEX_10 */
3268   {
3269     { "vmovups", { XM, EXx } },
3270     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3271     { "vmovupd", { XM, EXx } },
3272     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3273   },
3274
3275   /* PREFIX_VEX_11 */
3276   {
3277     { "vmovups", { EXx, XM } },
3278     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3279     { "vmovupd", { EXx, XM } },
3280     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3281   },
3282
3283   /* PREFIX_VEX_12 */
3284   {
3285     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3286     { "vmovsldup", { XM, EXx } },
3287     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3288     { "vmovddup", { XM, EXymmq } },
3289   },
3290
3291   /* PREFIX_VEX_16 */
3292   {
3293     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3294     { "vmovshdup", { XM, EXx } },
3295     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3296     { "(bad)",  { XX } },
3297   },
3298
3299   /* PREFIX_VEX_2A */
3300   {
3301     { "(bad)",  { XX } },
3302     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3303     { "(bad)",  { XX } },
3304     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3305   },
3306
3307   /* PREFIX_VEX_2C */
3308   {
3309     { "(bad)",  { XX } },
3310     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3311     { "(bad)",  { XX } },
3312     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3313   },
3314
3315   /* PREFIX_VEX_2D */
3316   {
3317     { "(bad)",  { XX } },
3318     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3319     { "(bad)",  { XX } },
3320     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3321   },
3322
3323   /* PREFIX_VEX_2E */
3324   {
3325     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3326     { "(bad)",  { XX } },
3327     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3328     { "(bad)",  { XX } },
3329   },
3330
3331   /* PREFIX_VEX_2F */
3332   {
3333     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3334     { "(bad)",  { XX } },
3335     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3336     { "(bad)",  { XX } },
3337   },
3338
3339   /* PREFIX_VEX_51 */
3340   {
3341     { "vsqrtps", { XM, EXx } },
3342     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3343     { "vsqrtpd", { XM, EXx } },
3344     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3345   },
3346
3347   /* PREFIX_VEX_52 */
3348   {
3349     { "vrsqrtps", { XM, EXx } },
3350     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3351     { "(bad)",  { XX } },
3352     { "(bad)",  { XX } },
3353   },
3354
3355   /* PREFIX_VEX_53 */
3356   {
3357     { "vrcpps", { XM, EXx } },
3358     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3359     { "(bad)",  { XX } },
3360     { "(bad)",  { XX } },
3361   },
3362
3363   /* PREFIX_VEX_58 */
3364   {
3365     { "vaddps", { XM, Vex, EXx } },
3366     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3367     { "vaddpd", { XM, Vex, EXx } },
3368     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3369   },
3370
3371   /* PREFIX_VEX_59 */
3372   {
3373     { "vmulps", { XM, Vex, EXx } },
3374     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3375     { "vmulpd", { XM, Vex, EXx } },
3376     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3377   },
3378
3379   /* PREFIX_VEX_5A */
3380   {
3381     { "vcvtps2pd", { XM, EXxmmq } },
3382     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3383     { "vcvtpd2ps%XY", { XMM, EXx } },
3384     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3385   },
3386
3387   /* PREFIX_VEX_5B */
3388   {
3389     { "vcvtdq2ps", { XM, EXx } },
3390     { "vcvttps2dq", { XM, EXx } },
3391     { "vcvtps2dq", { XM, EXx } },
3392     { "(bad)",  { XX } },
3393   },
3394
3395   /* PREFIX_VEX_5C */
3396   {
3397     { "vsubps", { XM, Vex, EXx } },
3398     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3399     { "vsubpd", { XM, Vex, EXx } },
3400     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3401   },
3402
3403   /* PREFIX_VEX_5D */
3404   {
3405     { "vminps", { XM, Vex, EXx } },
3406     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3407     { "vminpd", { XM, Vex, EXx } },
3408     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3409   },
3410
3411   /* PREFIX_VEX_5E */
3412   {
3413     { "vdivps", { XM, Vex, EXx } },
3414     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3415     { "vdivpd", { XM, Vex, EXx } },
3416     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3417   },
3418
3419   /* PREFIX_VEX_5F */
3420   {
3421     { "vmaxps", { XM, Vex, EXx } },
3422     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3423     { "vmaxpd", { XM, Vex, EXx } },
3424     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3425   },
3426
3427   /* PREFIX_VEX_60 */
3428   {
3429     { "(bad)",  { XX } },
3430     { "(bad)",  { XX } },
3431     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3432     { "(bad)",  { XX } },
3433   },
3434
3435   /* PREFIX_VEX_61 */
3436   {
3437     { "(bad)",  { XX } },
3438     { "(bad)",  { XX } },
3439     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3440     { "(bad)",  { XX } },
3441   },
3442
3443   /* PREFIX_VEX_62 */
3444   {
3445     { "(bad)",  { XX } },
3446     { "(bad)",  { XX } },
3447     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3448     { "(bad)",  { XX } },
3449   },
3450
3451   /* PREFIX_VEX_63 */
3452   {
3453     { "(bad)",  { XX } },
3454     { "(bad)",  { XX } },
3455     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3456     { "(bad)",  { XX } },
3457   },
3458
3459   /* PREFIX_VEX_64 */
3460   {
3461     { "(bad)",  { XX } },
3462     { "(bad)",  { XX } },
3463     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3464     { "(bad)",  { XX } },
3465   },
3466
3467   /* PREFIX_VEX_65 */
3468   {
3469     { "(bad)",  { XX } },
3470     { "(bad)",  { XX } },
3471     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3472     { "(bad)",  { XX } },
3473   },
3474
3475   /* PREFIX_VEX_66 */
3476   {
3477     { "(bad)",  { XX } },
3478     { "(bad)",  { XX } },
3479     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3480     { "(bad)",  { XX } },
3481   },
3482
3483   /* PREFIX_VEX_67 */
3484   {
3485     { "(bad)",  { XX } },
3486     { "(bad)",  { XX } },
3487     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3488     { "(bad)",  { XX } },
3489   },
3490
3491   /* PREFIX_VEX_68 */
3492   {
3493     { "(bad)",  { XX } },
3494     { "(bad)",  { XX } },
3495     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3496     { "(bad)",  { XX } },
3497   },
3498
3499   /* PREFIX_VEX_69 */
3500   {
3501     { "(bad)",  { XX } },
3502     { "(bad)",  { XX } },
3503     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3504     { "(bad)",  { XX } },
3505   },
3506
3507   /* PREFIX_VEX_6A */
3508   {
3509     { "(bad)",  { XX } },
3510     { "(bad)",  { XX } },
3511     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3512     { "(bad)",  { XX } },
3513   },
3514
3515   /* PREFIX_VEX_6B */
3516   {
3517     { "(bad)",  { XX } },
3518     { "(bad)",  { XX } },
3519     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3520     { "(bad)",  { XX } },
3521   },
3522
3523   /* PREFIX_VEX_6C */
3524   {
3525     { "(bad)",  { XX } },
3526     { "(bad)",  { XX } },
3527     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3528     { "(bad)",  { XX } },
3529   },
3530
3531   /* PREFIX_VEX_6D */
3532   {
3533     { "(bad)",  { XX } },
3534     { "(bad)",  { XX } },
3535     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3536     { "(bad)",  { XX } },
3537   },
3538
3539   /* PREFIX_VEX_6E */
3540   {
3541     { "(bad)",  { XX } },
3542     { "(bad)",  { XX } },
3543     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3544     { "(bad)",  { XX } },
3545   },
3546
3547   /* PREFIX_VEX_6F */
3548   {
3549     { "(bad)",  { XX } },
3550     { "vmovdqu", { XM, EXx } },
3551     { "vmovdqa", { XM, EXx } },
3552     { "(bad)",  { XX } },
3553   },
3554
3555   /* PREFIX_VEX_70 */
3556   {
3557     { "(bad)",  { XX } },
3558     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3559     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3560     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3561   },
3562
3563   /* PREFIX_VEX_71_REG_2 */
3564   {
3565     { "(bad)",  { XX } },
3566     { "(bad)",  { XX } },
3567     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3568     { "(bad)",  { XX } },
3569   },
3570
3571   /* PREFIX_VEX_71_REG_4 */
3572   {
3573     { "(bad)",  { XX } },
3574     { "(bad)",  { XX } },
3575     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3576     { "(bad)",  { XX } },
3577   },
3578
3579   /* PREFIX_VEX_71_REG_6 */
3580   {
3581     { "(bad)",  { XX } },
3582     { "(bad)",  { XX } },
3583     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3584     { "(bad)",  { XX } },
3585   },
3586
3587   /* PREFIX_VEX_72_REG_2 */
3588   {
3589     { "(bad)",  { XX } },
3590     { "(bad)",  { XX } },
3591     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3592     { "(bad)",  { XX } },
3593   },
3594
3595   /* PREFIX_VEX_72_REG_4 */
3596   {
3597     { "(bad)",  { XX } },
3598     { "(bad)",  { XX } },
3599     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3600     { "(bad)",  { XX } },
3601   },
3602
3603   /* PREFIX_VEX_72_REG_6 */
3604   {
3605     { "(bad)",  { XX } },
3606     { "(bad)",  { XX } },
3607     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3608     { "(bad)",  { XX } },
3609   },
3610
3611   /* PREFIX_VEX_73_REG_2 */
3612   {
3613     { "(bad)",  { XX } },
3614     { "(bad)",  { XX } },
3615     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3616     { "(bad)",  { XX } },
3617   },
3618
3619   /* PREFIX_VEX_73_REG_3 */
3620   {
3621     { "(bad)",  { XX } },
3622     { "(bad)",  { XX } },
3623     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3624     { "(bad)",  { XX } },
3625   },
3626
3627   /* PREFIX_VEX_73_REG_6 */
3628   {
3629     { "(bad)",  { XX } },
3630     { "(bad)",  { XX } },
3631     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3632     { "(bad)",  { XX } },
3633   },
3634
3635   /* PREFIX_VEX_73_REG_7 */
3636   {
3637     { "(bad)",  { XX } },
3638     { "(bad)",  { XX } },
3639     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3640     { "(bad)",  { XX } },
3641   },
3642
3643   /* PREFIX_VEX_74 */
3644   {
3645     { "(bad)",  { XX } },
3646     { "(bad)",  { XX } },
3647     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3648     { "(bad)",  { XX } },
3649   },
3650
3651   /* PREFIX_VEX_75 */
3652   {
3653     { "(bad)",  { XX } },
3654     { "(bad)",  { XX } },
3655     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3656     { "(bad)",  { XX } },
3657   },
3658
3659   /* PREFIX_VEX_76 */
3660   {
3661     { "(bad)",  { XX } },
3662     { "(bad)",  { XX } },
3663     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3664     { "(bad)",  { XX } },
3665   },
3666
3667   /* PREFIX_VEX_77 */
3668   {
3669     { "",       { VZERO } },
3670     { "(bad)",  { XX } },
3671     { "(bad)",  { XX } },
3672     { "(bad)",  { XX } },
3673   },
3674
3675   /* PREFIX_VEX_7C */
3676   {
3677     { "(bad)",  { XX } },
3678     { "(bad)",  { XX } },
3679     { "vhaddpd", { XM, Vex, EXx } },
3680     { "vhaddps", { XM, Vex, EXx } },
3681   },
3682
3683   /* PREFIX_VEX_7D */
3684   {
3685     { "(bad)",  { XX } },
3686     { "(bad)",  { XX } },
3687     { "vhsubpd", { XM, Vex, EXx } },
3688     { "vhsubps", { XM, Vex, EXx } },
3689   },
3690
3691   /* PREFIX_VEX_7E */
3692   {
3693     { "(bad)",  { XX } },
3694     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3695     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3696     { "(bad)",  { XX } },
3697   },
3698
3699   /* PREFIX_VEX_7F */
3700   {
3701     { "(bad)",  { XX } },
3702     { "vmovdqu", { EXx, XM } },
3703     { "vmovdqa", { EXx, XM } },
3704     { "(bad)",  { XX } },
3705   },
3706
3707   /* PREFIX_VEX_C2 */
3708   {
3709     { "vcmpps", { XM, Vex, EXx, VCMP } },
3710     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3711     { "vcmppd", { XM, Vex, EXx, VCMP } },
3712     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3713   },
3714
3715   /* PREFIX_VEX_C4 */
3716   {
3717     { "(bad)",  { XX } },
3718     { "(bad)",  { XX } },
3719     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3720     { "(bad)",  { XX } },
3721   },
3722
3723   /* PREFIX_VEX_C5 */
3724   {
3725     { "(bad)",  { XX } },
3726     { "(bad)",  { XX } },
3727     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3728     { "(bad)",  { XX } },
3729   },
3730
3731   /* PREFIX_VEX_D0 */
3732   {
3733     { "(bad)",  { XX } },
3734     { "(bad)",  { XX } },
3735     { "vaddsubpd", { XM, Vex, EXx } },
3736     { "vaddsubps", { XM, Vex, EXx } },
3737   },
3738
3739   /* PREFIX_VEX_D1 */
3740   {
3741     { "(bad)",  { XX } },
3742     { "(bad)",  { XX } },
3743     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3744     { "(bad)",  { XX } },
3745   },
3746
3747   /* PREFIX_VEX_D2 */
3748   {
3749     { "(bad)",  { XX } },
3750     { "(bad)",  { XX } },
3751     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3752     { "(bad)",  { XX } },
3753   },
3754
3755   /* PREFIX_VEX_D3 */
3756   {
3757     { "(bad)",  { XX } },
3758     { "(bad)",  { XX } },
3759     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3760     { "(bad)",  { XX } },
3761   },
3762
3763   /* PREFIX_VEX_D4 */
3764   {
3765     { "(bad)",  { XX } },
3766     { "(bad)",  { XX } },
3767     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3768     { "(bad)",  { XX } },
3769   },
3770
3771   /* PREFIX_VEX_D5 */
3772   {
3773     { "(bad)",  { XX } },
3774     { "(bad)",  { XX } },
3775     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3776     { "(bad)",  { XX } },
3777   },
3778
3779   /* PREFIX_VEX_D6 */
3780   {
3781     { "(bad)",  { XX } },
3782     { "(bad)",  { XX } },
3783     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3784     { "(bad)",  { XX } },
3785   },
3786
3787   /* PREFIX_VEX_D7 */
3788   {
3789     { "(bad)",  { XX } },
3790     { "(bad)",  { XX } },
3791     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3792     { "(bad)",  { XX } },
3793   },
3794
3795   /* PREFIX_VEX_D8 */
3796   {
3797     { "(bad)",  { XX } },
3798     { "(bad)",  { XX } },
3799     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3800     { "(bad)",  { XX } },
3801   },
3802
3803   /* PREFIX_VEX_D9 */
3804   {
3805     { "(bad)",  { XX } },
3806     { "(bad)",  { XX } },
3807     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3808     { "(bad)",  { XX } },
3809   },
3810
3811   /* PREFIX_VEX_DA */
3812   {
3813     { "(bad)",  { XX } },
3814     { "(bad)",  { XX } },
3815     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3816     { "(bad)",  { XX } },
3817   },
3818
3819   /* PREFIX_VEX_DB */
3820   {
3821     { "(bad)",  { XX } },
3822     { "(bad)",  { XX } },
3823     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3824     { "(bad)",  { XX } },
3825   },
3826
3827   /* PREFIX_VEX_DC */
3828   {
3829     { "(bad)",  { XX } },
3830     { "(bad)",  { XX } },
3831     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3832     { "(bad)",  { XX } },
3833   },
3834
3835   /* PREFIX_VEX_DD */
3836   {
3837     { "(bad)",  { XX } },
3838     { "(bad)",  { XX } },
3839     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3840     { "(bad)",  { XX } },
3841   },
3842
3843   /* PREFIX_VEX_DE */
3844   {
3845     { "(bad)",  { XX } },
3846     { "(bad)",  { XX } },
3847     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3848     { "(bad)",  { XX } },
3849   },
3850
3851   /* PREFIX_VEX_DF */
3852   {
3853     { "(bad)",  { XX } },
3854     { "(bad)",  { XX } },
3855     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3856     { "(bad)",  { XX } },
3857   },
3858
3859   /* PREFIX_VEX_E0 */
3860   {
3861     { "(bad)",  { XX } },
3862     { "(bad)",  { XX } },
3863     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3864     { "(bad)",  { XX } },
3865   },
3866
3867   /* PREFIX_VEX_E1 */
3868   {
3869     { "(bad)",  { XX } },
3870     { "(bad)",  { XX } },
3871     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3872     { "(bad)",  { XX } },
3873   },
3874
3875   /* PREFIX_VEX_E2 */
3876   {
3877     { "(bad)",  { XX } },
3878     { "(bad)",  { XX } },
3879     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3880     { "(bad)",  { XX } },
3881   },
3882
3883   /* PREFIX_VEX_E3 */
3884   {
3885     { "(bad)",  { XX } },
3886     { "(bad)",  { XX } },
3887     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3888     { "(bad)",  { XX } },
3889   },
3890
3891   /* PREFIX_VEX_E4 */
3892   {
3893     { "(bad)",  { XX } },
3894     { "(bad)",  { XX } },
3895     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3896     { "(bad)",  { XX } },
3897   },
3898
3899   /* PREFIX_VEX_E5 */
3900   {
3901     { "(bad)",  { XX } },
3902     { "(bad)",  { XX } },
3903     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3904     { "(bad)",  { XX } },
3905   },
3906
3907   /* PREFIX_VEX_E6 */
3908   {
3909     { "(bad)",  { XX } },
3910     { "vcvtdq2pd", { XM, EXxmmq } },
3911     { "vcvttpd2dq%XY", { XMM, EXx } },
3912     { "vcvtpd2dq%XY", { XMM, EXx } },
3913   },
3914
3915   /* PREFIX_VEX_E7 */
3916   {
3917     { "(bad)",  { XX } },
3918     { "(bad)",  { XX } },
3919     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3920     { "(bad)",  { XX } },
3921   },
3922
3923   /* PREFIX_VEX_E8 */
3924   {
3925     { "(bad)",  { XX } },
3926     { "(bad)",  { XX } },
3927     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3928     { "(bad)",  { XX } },
3929   },
3930
3931   /* PREFIX_VEX_E9 */
3932   {
3933     { "(bad)",  { XX } },
3934     { "(bad)",  { XX } },
3935     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3936     { "(bad)",  { XX } },
3937   },
3938
3939   /* PREFIX_VEX_EA */
3940   {
3941     { "(bad)",  { XX } },
3942     { "(bad)",  { XX } },
3943     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3944     { "(bad)",  { XX } },
3945   },
3946
3947   /* PREFIX_VEX_EB */
3948   {
3949     { "(bad)",  { XX } },
3950     { "(bad)",  { XX } },
3951     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3952     { "(bad)",  { XX } },
3953   },
3954
3955   /* PREFIX_VEX_EC */
3956   {
3957     { "(bad)",  { XX } },
3958     { "(bad)",  { XX } },
3959     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3960     { "(bad)",  { XX } },
3961   },
3962
3963   /* PREFIX_VEX_ED */
3964   {
3965     { "(bad)",  { XX } },
3966     { "(bad)",  { XX } },
3967     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
3968     { "(bad)",  { XX } },
3969   },
3970
3971   /* PREFIX_VEX_EE */
3972   {
3973     { "(bad)",  { XX } },
3974     { "(bad)",  { XX } },
3975     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
3976     { "(bad)",  { XX } },
3977   },
3978
3979   /* PREFIX_VEX_EF */
3980   {
3981     { "(bad)",  { XX } },
3982     { "(bad)",  { XX } },
3983     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
3984     { "(bad)",  { XX } },
3985   },
3986
3987   /* PREFIX_VEX_F0 */
3988   {
3989     { "(bad)",  { XX } },
3990     { "(bad)",  { XX } },
3991     { "(bad)",  { XX } },
3992     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
3993   },
3994
3995   /* PREFIX_VEX_F1 */
3996   {
3997     { "(bad)",  { XX } },
3998     { "(bad)",  { XX } },
3999     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4000     { "(bad)",  { XX } },
4001   },
4002
4003   /* PREFIX_VEX_F2 */
4004   {
4005     { "(bad)",  { XX } },
4006     { "(bad)",  { XX } },
4007     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4008     { "(bad)",  { XX } },
4009   },
4010
4011   /* PREFIX_VEX_F3 */
4012   {
4013     { "(bad)",  { XX } },
4014     { "(bad)",  { XX } },
4015     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4016     { "(bad)",  { XX } },
4017   },
4018
4019   /* PREFIX_VEX_F4 */
4020   {
4021     { "(bad)",  { XX } },
4022     { "(bad)",  { XX } },
4023     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4024     { "(bad)",  { XX } },
4025   },
4026
4027   /* PREFIX_VEX_F5 */
4028   {
4029     { "(bad)",  { XX } },
4030     { "(bad)",  { XX } },
4031     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4032     { "(bad)",  { XX } },
4033   },
4034
4035   /* PREFIX_VEX_F6 */
4036   {
4037     { "(bad)",  { XX } },
4038     { "(bad)",  { XX } },
4039     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4040     { "(bad)",  { XX } },
4041   },
4042
4043   /* PREFIX_VEX_F7 */
4044   {
4045     { "(bad)",  { XX } },
4046     { "(bad)",  { XX } },
4047     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4048     { "(bad)",  { XX } },
4049   },
4050
4051   /* PREFIX_VEX_F8 */
4052   {
4053     { "(bad)",  { XX } },
4054     { "(bad)",  { XX } },
4055     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4056     { "(bad)",  { XX } },
4057   },
4058
4059   /* PREFIX_VEX_F9 */
4060   {
4061     { "(bad)",  { XX } },
4062     { "(bad)",  { XX } },
4063     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4064     { "(bad)",  { XX } },
4065   },
4066
4067   /* PREFIX_VEX_FA */
4068   {
4069     { "(bad)",  { XX } },
4070     { "(bad)",  { XX } },
4071     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4072     { "(bad)",  { XX } },
4073   },
4074
4075   /* PREFIX_VEX_FB */
4076   {
4077     { "(bad)",  { XX } },
4078     { "(bad)",  { XX } },
4079     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4080     { "(bad)",  { XX } },
4081   },
4082
4083   /* PREFIX_VEX_FC */
4084   {
4085     { "(bad)",  { XX } },
4086     { "(bad)",  { XX } },
4087     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4088     { "(bad)",  { XX } },
4089   },
4090
4091   /* PREFIX_VEX_FD */
4092   {
4093     { "(bad)",  { XX } },
4094     { "(bad)",  { XX } },
4095     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4096     { "(bad)",  { XX } },
4097   },
4098
4099   /* PREFIX_VEX_FE */
4100   {
4101     { "(bad)",  { XX } },
4102     { "(bad)",  { XX } },
4103     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4104     { "(bad)",  { XX } },
4105   },
4106
4107   /* PREFIX_VEX_3800 */
4108   {
4109     { "(bad)",  { XX } },
4110     { "(bad)",  { XX } },
4111     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4112     { "(bad)",  { XX } },
4113   },
4114
4115   /* PREFIX_VEX_3801 */
4116   {
4117     { "(bad)",  { XX } },
4118     { "(bad)",  { XX } },
4119     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4120     { "(bad)",  { XX } },
4121   },
4122
4123   /* PREFIX_VEX_3802 */
4124   {
4125     { "(bad)",  { XX } },
4126     { "(bad)",  { XX } },
4127     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4128     { "(bad)",  { XX } },
4129   },
4130
4131   /* PREFIX_VEX_3803 */
4132   {
4133     { "(bad)",  { XX } },
4134     { "(bad)",  { XX } },
4135     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4136     { "(bad)",  { XX } },
4137   },
4138
4139   /* PREFIX_VEX_3804 */
4140   {
4141     { "(bad)",  { XX } },
4142     { "(bad)",  { XX } },
4143     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4144     { "(bad)",  { XX } },
4145   },
4146
4147   /* PREFIX_VEX_3805 */
4148   {
4149     { "(bad)",  { XX } },
4150     { "(bad)",  { XX } },
4151     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4152     { "(bad)",  { XX } },
4153   },
4154
4155   /* PREFIX_VEX_3806 */
4156   {
4157     { "(bad)",  { XX } },
4158     { "(bad)",  { XX } },
4159     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4160     { "(bad)",  { XX } },
4161   },
4162
4163   /* PREFIX_VEX_3807 */
4164   {
4165     { "(bad)",  { XX } },
4166     { "(bad)",  { XX } },
4167     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4168     { "(bad)",  { XX } },
4169   },
4170
4171   /* PREFIX_VEX_3808 */
4172   {
4173     { "(bad)",  { XX } },
4174     { "(bad)",  { XX } },
4175     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4176     { "(bad)",  { XX } },
4177   },
4178
4179   /* PREFIX_VEX_3809 */
4180   {
4181     { "(bad)",  { XX } },
4182     { "(bad)",  { XX } },
4183     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4184     { "(bad)",  { XX } },
4185   },
4186
4187   /* PREFIX_VEX_380A */
4188   {
4189     { "(bad)",  { XX } },
4190     { "(bad)",  { XX } },
4191     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4192     { "(bad)",  { XX } },
4193   },
4194
4195   /* PREFIX_VEX_380B */
4196   {
4197     { "(bad)",  { XX } },
4198     { "(bad)",  { XX } },
4199     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4200     { "(bad)",  { XX } },
4201   },
4202
4203   /* PREFIX_VEX_380C */
4204   {
4205     { "(bad)",  { XX } },
4206     { "(bad)",  { XX } },
4207     { "vpermilps", { XM, Vex, EXx } },
4208     { "(bad)",  { XX } },
4209   },
4210
4211   /* PREFIX_VEX_380D */
4212   {
4213     { "(bad)",  { XX } },
4214     { "(bad)",  { XX } },
4215     { "vpermilpd", { XM, Vex, EXx } },
4216     { "(bad)",  { XX } },
4217   },
4218
4219   /* PREFIX_VEX_380E */
4220   {
4221     { "(bad)",  { XX } },
4222     { "(bad)",  { XX } },
4223     { "vtestps", { XM, EXx } },
4224     { "(bad)",  { XX } },
4225   },
4226
4227   /* PREFIX_VEX_380F */
4228   {
4229     { "(bad)",  { XX } },
4230     { "(bad)",  { XX } },
4231     { "vtestpd", { XM, EXx } },
4232     { "(bad)",  { XX } },
4233   },
4234
4235   /* PREFIX_VEX_3817 */
4236   {
4237     { "(bad)",  { XX } },
4238     { "(bad)",  { XX } },
4239     { "vptest", { XM, EXx } },
4240     { "(bad)",  { XX } },
4241   },
4242
4243   /* PREFIX_VEX_3818 */
4244   {
4245     { "(bad)",  { XX } },
4246     { "(bad)",  { XX } },
4247     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4248     { "(bad)",  { XX } },
4249   },
4250
4251   /* PREFIX_VEX_3819 */
4252   {
4253     { "(bad)",  { XX } },
4254     { "(bad)",  { XX } },
4255     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4256     { "(bad)",  { XX } },
4257   },
4258
4259   /* PREFIX_VEX_381A */
4260   {
4261     { "(bad)",  { XX } },
4262     { "(bad)",  { XX } },
4263     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4264     { "(bad)",  { XX } },
4265   },
4266
4267   /* PREFIX_VEX_381C */
4268   {
4269     { "(bad)",  { XX } },
4270     { "(bad)",  { XX } },
4271     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4272     { "(bad)",  { XX } },
4273   },
4274
4275   /* PREFIX_VEX_381D */
4276   {
4277     { "(bad)",  { XX } },
4278     { "(bad)",  { XX } },
4279     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4280     { "(bad)",  { XX } },
4281   },
4282
4283   /* PREFIX_VEX_381E */
4284   {
4285     { "(bad)",  { XX } },
4286     { "(bad)",  { XX } },
4287     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4288     { "(bad)",  { XX } },
4289   },
4290
4291   /* PREFIX_VEX_3820 */
4292   {
4293     { "(bad)",  { XX } },
4294     { "(bad)",  { XX } },
4295     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4296     { "(bad)",  { XX } },
4297   },
4298
4299   /* PREFIX_VEX_3821 */
4300   {
4301     { "(bad)",  { XX } },
4302     { "(bad)",  { XX } },
4303     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4304     { "(bad)",  { XX } },
4305   },
4306
4307   /* PREFIX_VEX_3822 */
4308   {
4309     { "(bad)",  { XX } },
4310     { "(bad)",  { XX } },
4311     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4312     { "(bad)",  { XX } },
4313   },
4314
4315   /* PREFIX_VEX_3823 */
4316   {
4317     { "(bad)",  { XX } },
4318     { "(bad)",  { XX } },
4319     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4320     { "(bad)",  { XX } },
4321   },
4322
4323   /* PREFIX_VEX_3824 */
4324   {
4325     { "(bad)",  { XX } },
4326     { "(bad)",  { XX } },
4327     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4328     { "(bad)",  { XX } },
4329   },
4330
4331   /* PREFIX_VEX_3825 */
4332   {
4333     { "(bad)",  { XX } },
4334     { "(bad)",  { XX } },
4335     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4336     { "(bad)",  { XX } },
4337   },
4338
4339   /* PREFIX_VEX_3828 */
4340   {
4341     { "(bad)",  { XX } },
4342     { "(bad)",  { XX } },
4343     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4344     { "(bad)",  { XX } },
4345   },
4346
4347   /* PREFIX_VEX_3829 */
4348   {
4349     { "(bad)",  { XX } },
4350     { "(bad)",  { XX } },
4351     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4352     { "(bad)",  { XX } },
4353   },
4354
4355   /* PREFIX_VEX_382A */
4356   {
4357     { "(bad)",  { XX } },
4358     { "(bad)",  { XX } },
4359     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4360     { "(bad)",  { XX } },
4361   },
4362
4363   /* PREFIX_VEX_382B */
4364   {
4365     { "(bad)",  { XX } },
4366     { "(bad)",  { XX } },
4367     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4368     { "(bad)",  { XX } },
4369   },
4370
4371   /* PREFIX_VEX_382C */
4372   {
4373     { "(bad)",  { XX } },
4374     { "(bad)",  { XX } },
4375      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4376     { "(bad)",  { XX } },
4377   },
4378
4379   /* PREFIX_VEX_382D */
4380   {
4381     { "(bad)",  { XX } },
4382     { "(bad)",  { XX } },
4383      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4384     { "(bad)",  { XX } },
4385   },
4386
4387   /* PREFIX_VEX_382E */
4388   {
4389     { "(bad)",  { XX } },
4390     { "(bad)",  { XX } },
4391      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4392     { "(bad)",  { XX } },
4393   },
4394
4395   /* PREFIX_VEX_382F */
4396   {
4397     { "(bad)",  { XX } },
4398     { "(bad)",  { XX } },
4399      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4400     { "(bad)",  { XX } },
4401   },
4402
4403   /* PREFIX_VEX_3830 */
4404   {
4405     { "(bad)",  { XX } },
4406     { "(bad)",  { XX } },
4407     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4408     { "(bad)",  { XX } },
4409   },
4410
4411   /* PREFIX_VEX_3831 */
4412   {
4413     { "(bad)",  { XX } },
4414     { "(bad)",  { XX } },
4415     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4416     { "(bad)",  { XX } },
4417   },
4418
4419   /* PREFIX_VEX_3832 */
4420   {
4421     { "(bad)",  { XX } },
4422     { "(bad)",  { XX } },
4423     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4424     { "(bad)",  { XX } },
4425   },
4426
4427   /* PREFIX_VEX_3833 */
4428   {
4429     { "(bad)",  { XX } },
4430     { "(bad)",  { XX } },
4431     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4432     { "(bad)",  { XX } },
4433   },
4434
4435   /* PREFIX_VEX_3834 */
4436   {
4437     { "(bad)",  { XX } },
4438     { "(bad)",  { XX } },
4439     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4440     { "(bad)",  { XX } },
4441   },
4442
4443   /* PREFIX_VEX_3835 */
4444   {
4445     { "(bad)",  { XX } },
4446     { "(bad)",  { XX } },
4447     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4448     { "(bad)",  { XX } },
4449   },
4450
4451   /* PREFIX_VEX_3837 */
4452   {
4453     { "(bad)",  { XX } },
4454     { "(bad)",  { XX } },
4455     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4456     { "(bad)",  { XX } },
4457   },
4458
4459   /* PREFIX_VEX_3838 */
4460   {
4461     { "(bad)",  { XX } },
4462     { "(bad)",  { XX } },
4463     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4464     { "(bad)",  { XX } },
4465   },
4466
4467   /* PREFIX_VEX_3839 */
4468   {
4469     { "(bad)",  { XX } },
4470     { "(bad)",  { XX } },
4471     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4472     { "(bad)",  { XX } },
4473   },
4474
4475   /* PREFIX_VEX_383A */
4476   {
4477     { "(bad)",  { XX } },
4478     { "(bad)",  { XX } },
4479     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4480     { "(bad)",  { XX } },
4481   },
4482
4483   /* PREFIX_VEX_383B */
4484   {
4485     { "(bad)",  { XX } },
4486     { "(bad)",  { XX } },
4487     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4488     { "(bad)",  { XX } },
4489   },
4490
4491   /* PREFIX_VEX_383C */
4492   {
4493     { "(bad)",  { XX } },
4494     { "(bad)",  { XX } },
4495     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4496     { "(bad)",  { XX } },
4497   },
4498
4499   /* PREFIX_VEX_383D */
4500   {
4501     { "(bad)",  { XX } },
4502     { "(bad)",  { XX } },
4503     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4504     { "(bad)",  { XX } },
4505   },
4506
4507   /* PREFIX_VEX_383E */
4508   {
4509     { "(bad)",  { XX } },
4510     { "(bad)",  { XX } },
4511     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4512     { "(bad)",  { XX } },
4513   },
4514
4515   /* PREFIX_VEX_383F */
4516   {
4517     { "(bad)",  { XX } },
4518     { "(bad)",  { XX } },
4519     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4520     { "(bad)",  { XX } },
4521   },
4522
4523   /* PREFIX_VEX_3840 */
4524   {
4525     { "(bad)",  { XX } },
4526     { "(bad)",  { XX } },
4527     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4528     { "(bad)",  { XX } },
4529   },
4530
4531   /* PREFIX_VEX_3841 */
4532   {
4533     { "(bad)",  { XX } },
4534     { "(bad)",  { XX } },
4535     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4536     { "(bad)",  { XX } },
4537   },
4538
4539   /* PREFIX_VEX_3A04 */
4540   {
4541     { "(bad)",  { XX } },
4542     { "(bad)",  { XX } },
4543     { "vpermilps", { XM, EXx, Ib } },
4544     { "(bad)",  { XX } },
4545   },
4546
4547   /* PREFIX_VEX_3A05 */
4548   {
4549     { "(bad)",  { XX } },
4550     { "(bad)",  { XX } },
4551     { "vpermilpd", { XM, EXx, Ib } },
4552     { "(bad)",  { XX } },
4553   },
4554
4555   /* PREFIX_VEX_3A06 */
4556   {
4557     { "(bad)",  { XX } },
4558     { "(bad)",  { XX } },
4559     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4560     { "(bad)",  { XX } },
4561   },
4562
4563   /* PREFIX_VEX_3A08 */
4564   {
4565     { "(bad)",  { XX } },
4566     { "(bad)",  { XX } },
4567     { "vroundps", { XM, EXx, Ib } },
4568     { "(bad)",  { XX } },
4569   },
4570
4571   /* PREFIX_VEX_3A09 */
4572   {
4573     { "(bad)",  { XX } },
4574     { "(bad)",  { XX } },
4575     { "vroundpd", { XM, EXx, Ib } },
4576     { "(bad)",  { XX } },
4577   },
4578
4579   /* PREFIX_VEX_3A0A */
4580   {
4581     { "(bad)",  { XX } },
4582     { "(bad)",  { XX } },
4583     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4584     { "(bad)",  { XX } },
4585   },
4586
4587   /* PREFIX_VEX_3A0B */
4588   {
4589     { "(bad)",  { XX } },
4590     { "(bad)",  { XX } },
4591     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4592     { "(bad)",  { XX } },
4593   },
4594
4595   /* PREFIX_VEX_3A0C */
4596   {
4597     { "(bad)",  { XX } },
4598     { "(bad)",  { XX } },
4599     { "vblendps", { XM, Vex, EXx, Ib } },
4600     { "(bad)",  { XX } },
4601   },
4602
4603   /* PREFIX_VEX_3A0D */
4604   {
4605     { "(bad)",  { XX } },
4606     { "(bad)",  { XX } },
4607     { "vblendpd", { XM, Vex, EXx, Ib } },
4608     { "(bad)",  { XX } },
4609   },
4610
4611   /* PREFIX_VEX_3A0E */
4612   {
4613     { "(bad)",  { XX } },
4614     { "(bad)",  { XX } },
4615     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4616     { "(bad)",  { XX } },
4617   },
4618
4619   /* PREFIX_VEX_3A0F */
4620   {
4621     { "(bad)",  { XX } },
4622     { "(bad)",  { XX } },
4623     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4624     { "(bad)",  { XX } },
4625   },
4626
4627   /* PREFIX_VEX_3A14 */
4628   {
4629     { "(bad)",  { XX } },
4630     { "(bad)",  { XX } },
4631     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4632     { "(bad)",  { XX } },
4633   },
4634
4635   /* PREFIX_VEX_3A15 */
4636   {
4637     { "(bad)",  { XX } },
4638     { "(bad)",  { XX } },
4639     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4640     { "(bad)",  { XX } },
4641   },
4642
4643   /* PREFIX_VEX_3A16 */
4644   {
4645     { "(bad)",  { XX } },
4646     { "(bad)",  { XX } },
4647     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4648     { "(bad)",  { XX } },
4649   },
4650
4651   /* PREFIX_VEX_3A17 */
4652   {
4653     { "(bad)",  { XX } },
4654     { "(bad)",  { XX } },
4655     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4656     { "(bad)",  { XX } },
4657   },
4658
4659   /* PREFIX_VEX_3A18 */
4660   {
4661     { "(bad)",  { XX } },
4662     { "(bad)",  { XX } },
4663     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4664     { "(bad)",  { XX } },
4665   },
4666
4667   /* PREFIX_VEX_3A19 */
4668   {
4669     { "(bad)",  { XX } },
4670     { "(bad)",  { XX } },
4671     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4672     { "(bad)",  { XX } },
4673   },
4674
4675   /* PREFIX_VEX_3A20 */
4676   {
4677     { "(bad)",  { XX } },
4678     { "(bad)",  { XX } },
4679     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4680     { "(bad)",  { XX } },
4681   },
4682
4683   /* PREFIX_VEX_3A21 */
4684   {
4685     { "(bad)",  { XX } },
4686     { "(bad)",  { XX } },
4687     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4688     { "(bad)",  { XX } },
4689   },
4690
4691   /* PREFIX_VEX_3A22 */
4692   {
4693     { "(bad)",  { XX } },
4694     { "(bad)",  { XX } },
4695     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4696     { "(bad)",  { XX } },
4697   },
4698
4699   /* PREFIX_VEX_3A40 */
4700   {
4701     { "(bad)",  { XX } },
4702     { "(bad)",  { XX } },
4703     { "vdpps",  { XM, Vex, EXx, Ib } },
4704     { "(bad)",  { XX } },
4705   },
4706
4707   /* PREFIX_VEX_3A41 */
4708   {
4709     { "(bad)",  { XX } },
4710     { "(bad)",  { XX } },
4711     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4712     { "(bad)",  { XX } },
4713   },
4714
4715   /* PREFIX_VEX_3A42 */
4716   {
4717     { "(bad)",  { XX } },
4718     { "(bad)",  { XX } },
4719     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4720     { "(bad)",  { XX } },
4721   },
4722
4723   /* PREFIX_VEX_3A48 */
4724   {
4725     { "(bad)",  { XX } },
4726     { "(bad)",  { XX } },
4727     { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4728     { "(bad)",  { XX } },
4729   },
4730
4731   /* PREFIX_VEX_3A49 */
4732   {
4733     { "(bad)",  { XX } },
4734     { "(bad)",  { XX } },
4735     { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4736     { "(bad)",  { XX } },
4737   },
4738
4739   /* PREFIX_VEX_3A4A */
4740   {
4741     { "(bad)",  { XX } },
4742     { "(bad)",  { XX } },
4743     { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4744     { "(bad)",  { XX } },
4745   },
4746
4747   /* PREFIX_VEX_3A4B */
4748   {
4749     { "(bad)",  { XX } },
4750     { "(bad)",  { XX } },
4751     { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4752     { "(bad)",  { XX } },
4753   },
4754
4755   /* PREFIX_VEX_3A4C */
4756   {
4757     { "(bad)",  { XX } },
4758     { "(bad)",  { XX } },
4759     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4760     { "(bad)",  { XX } },
4761   },
4762
4763   /* PREFIX_VEX_3A5C */
4764   {
4765     { "(bad)",  { XX } },
4766     { "(bad)",  { XX } },
4767     { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4768     { "(bad)",  { XX } },
4769   },
4770
4771   /* PREFIX_VEX_3A5D */
4772   {
4773     { "(bad)",  { XX } },
4774     { "(bad)",  { XX } },
4775     { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4776     { "(bad)",  { XX } },
4777   },
4778
4779   /* PREFIX_VEX_3A5E */
4780   {
4781     { "(bad)",  { XX } },
4782     { "(bad)",  { XX } },
4783     { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4784     { "(bad)",  { XX } },
4785   },
4786
4787   /* PREFIX_VEX_3A5F */
4788   {
4789     { "(bad)",  { XX } },
4790     { "(bad)",  { XX } },
4791     { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4792     { "(bad)",  { XX } },
4793   },
4794
4795   /* PREFIX_VEX_3A60 */
4796   {
4797     { "(bad)",  { XX } },
4798     { "(bad)",  { XX } },
4799     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4800     { "(bad)",  { XX } },
4801   },
4802
4803   /* PREFIX_VEX_3A61 */
4804   {
4805     { "(bad)",  { XX } },
4806     { "(bad)",  { XX } },
4807     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4808     { "(bad)",  { XX } },
4809   },
4810
4811   /* PREFIX_VEX_3A62 */
4812   {
4813     { "(bad)",  { XX } },
4814     { "(bad)",  { XX } },
4815     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4816     { "(bad)",  { XX } },
4817   },
4818
4819   /* PREFIX_VEX_3A63 */
4820   {
4821     { "(bad)",  { XX } },
4822     { "(bad)",  { XX } },
4823     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4824     { "(bad)",  { XX } },
4825   },
4826
4827   /* PREFIX_VEX_3A68 */
4828   {
4829     { "(bad)",  { XX } },
4830     { "(bad)",  { XX } },
4831     { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4832     { "(bad)",  { XX } },
4833   },
4834
4835   /* PREFIX_VEX_3A69 */
4836   {
4837     { "(bad)",  { XX } },
4838     { "(bad)",  { XX } },
4839     { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4840     { "(bad)",  { XX } },
4841   },
4842
4843   /* PREFIX_VEX_3A6A */
4844   {
4845     { "(bad)",  { XX } },
4846     { "(bad)",  { XX } },
4847     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4848     { "(bad)",  { XX } },
4849   },
4850
4851   /* PREFIX_VEX_3A6B */
4852   {
4853     { "(bad)",  { XX } },
4854     { "(bad)",  { XX } },
4855     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4856     { "(bad)",  { XX } },
4857   },
4858
4859   /* PREFIX_VEX_3A6C */
4860   {
4861     { "(bad)",  { XX } },
4862     { "(bad)",  { XX } },
4863     { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4864     { "(bad)",  { XX } },
4865   },
4866
4867   /* PREFIX_VEX_3A6D */
4868   {
4869     { "(bad)",  { XX } },
4870     { "(bad)",  { XX } },
4871     { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4872     { "(bad)",  { XX } },
4873   },
4874
4875   /* PREFIX_VEX_3A6E */
4876   {
4877     { "(bad)",  { XX } },
4878     { "(bad)",  { XX } },
4879     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4880     { "(bad)",  { XX } },
4881   },
4882
4883   /* PREFIX_VEX_3A6F */
4884   {
4885     { "(bad)",  { XX } },
4886     { "(bad)",  { XX } },
4887     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4888     { "(bad)",  { XX } },
4889   },
4890
4891   /* PREFIX_VEX_3A78 */
4892   {
4893     { "(bad)",  { XX } },
4894     { "(bad)",  { XX } },
4895     { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4896     { "(bad)",  { XX } },
4897   },
4898
4899   /* PREFIX_VEX_3A79 */
4900   {
4901     { "(bad)",  { XX } },
4902     { "(bad)",  { XX } },
4903     { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4904     { "(bad)",  { XX } },
4905   },
4906
4907   /* PREFIX_VEX_3A7A */
4908   {
4909     { "(bad)",  { XX } },
4910     { "(bad)",  { XX } },
4911     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4912     { "(bad)",  { XX } },
4913   },
4914
4915   /* PREFIX_VEX_3A7B */
4916   {
4917     { "(bad)",  { XX } },
4918     { "(bad)",  { XX } },
4919     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4920     { "(bad)",  { XX } },
4921   },
4922
4923   /* PREFIX_VEX_3A7C */
4924   {
4925     { "(bad)",  { XX } },
4926     { "(bad)",  { XX } },
4927     { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4928     { "(bad)",  { XX } },
4929   },
4930
4931   /* PREFIX_VEX_3A7D */
4932   {
4933     { "(bad)",  { XX } },
4934     { "(bad)",  { XX } },
4935     { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4936     { "(bad)",  { XX } },
4937   },
4938
4939   /* PREFIX_VEX_3A7E */
4940   {
4941     { "(bad)",  { XX } },
4942     { "(bad)",  { XX } },
4943     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
4944     { "(bad)",  { XX } },
4945   },
4946
4947   /* PREFIX_VEX_3A7F */
4948   {
4949     { "(bad)",  { XX } },
4950     { "(bad)",  { XX } },
4951     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
4952     { "(bad)",  { XX } },
4953   },
4954 };
4955
4956 static const struct dis386 x86_64_table[][2] = {
4957   /* X86_64_06 */
4958   {
4959     { "push{T|}", { es } },
4960     { "(bad)", { XX } },
4961   },
4962
4963   /* X86_64_07 */
4964   {
4965     { "pop{T|}", { es } },
4966     { "(bad)", { XX } },
4967   },
4968
4969   /* X86_64_0D */
4970   {
4971     { "push{T|}", { cs } },
4972     { "(bad)", { XX } },
4973   },
4974
4975   /* X86_64_16 */
4976   {
4977     { "push{T|}", { ss } },
4978     { "(bad)", { XX } },
4979   },
4980
4981   /* X86_64_17 */
4982   {
4983     { "pop{T|}", { ss } },
4984     { "(bad)", { XX } },
4985   },
4986
4987   /* X86_64_1E */
4988   {
4989     { "push{T|}", { ds } },
4990     { "(bad)", { XX } },
4991   },
4992
4993   /* X86_64_1F */
4994   {
4995     { "pop{T|}", { ds } },
4996     { "(bad)", { XX } },
4997   },
4998
4999   /* X86_64_27 */
5000   {
5001     { "daa", { XX } },
5002     { "(bad)", { XX } },
5003   },
5004
5005   /* X86_64_2F */
5006   {
5007     { "das", { XX } },
5008     { "(bad)", { XX } },
5009   },
5010
5011   /* X86_64_37 */
5012   {
5013     { "aaa", { XX } },
5014     { "(bad)", { XX } },
5015   },
5016
5017   /* X86_64_3F */
5018   {
5019     { "aas", { XX } },
5020     { "(bad)", { XX } },
5021   },
5022
5023   /* X86_64_60 */
5024   {
5025     { "pusha{P|}", { XX } },
5026     { "(bad)", { XX } },
5027   },
5028
5029   /* X86_64_61 */
5030   {
5031     { "popa{P|}", { XX } },
5032     { "(bad)", { XX } },
5033   },
5034
5035   /* X86_64_62 */
5036   {
5037     { MOD_TABLE (MOD_62_32BIT) },
5038     { "(bad)", { XX } },
5039   },
5040
5041   /* X86_64_63 */
5042   {
5043     { "arpl", { Ew, Gw } },
5044     { "movs{lq|xd}", { Gv, Ed } },
5045   },
5046
5047   /* X86_64_6D */
5048   {
5049     { "ins{R|}", { Yzr, indirDX } },
5050     { "ins{G|}", { Yzr, indirDX } },
5051   },
5052
5053   /* X86_64_6F */
5054   {
5055     { "outs{R|}", { indirDXr, Xz } },
5056     { "outs{G|}", { indirDXr, Xz } },
5057   },
5058
5059   /* X86_64_9A */
5060   {
5061     { "Jcall{T|}", { Ap } },
5062     { "(bad)", { XX } },
5063   },
5064
5065   /* X86_64_C4 */
5066   {
5067     { MOD_TABLE (MOD_C4_32BIT) },
5068     { VEX_C4_TABLE (VEX_0F) },
5069   },
5070
5071   /* X86_64_C5 */
5072   {
5073     { MOD_TABLE (MOD_C5_32BIT) },
5074     { VEX_C5_TABLE (VEX_0F) },
5075   },
5076
5077   /* X86_64_CE */
5078   {
5079     { "into", { XX } },
5080     { "(bad)", { XX } },
5081   },
5082
5083   /* X86_64_D4 */
5084   {
5085     { "aam", { sIb } },
5086     { "(bad)", { XX } },
5087   },
5088
5089   /* X86_64_D5 */
5090   {
5091     { "aad", { sIb } },
5092     { "(bad)", { XX } },
5093   },
5094
5095   /* X86_64_EA */
5096   {
5097     { "Jjmp{T|}", { Ap } },
5098     { "(bad)", { XX } },
5099   },
5100
5101   /* X86_64_0F01_REG_0 */
5102   {
5103     { "sgdt{Q|IQ}", { M } },
5104     { "sgdt", { M } },
5105   },
5106
5107   /* X86_64_0F01_REG_1 */
5108   {
5109     { "sidt{Q|IQ}", { M } },
5110     { "sidt", { M } },
5111   },
5112
5113   /* X86_64_0F01_REG_2 */
5114   {
5115     { "lgdt{Q|Q}", { M } },
5116     { "lgdt", { M } },
5117   },
5118
5119   /* X86_64_0F01_REG_3 */
5120   {
5121     { "lidt{Q|Q}", { M } },
5122     { "lidt", { M } },
5123   },
5124 };
5125
5126 static const struct dis386 three_byte_table[][256] = {
5127   /* THREE_BYTE_0F24 */
5128   {
5129     /* 00 */
5130     { "fmaddps",        { { OP_DREX4, q_mode } } },
5131     { "fmaddpd",        { { OP_DREX4, q_mode } } },
5132     { "fmaddss",        { { OP_DREX4, w_mode } } },
5133     { "fmaddsd",        { { OP_DREX4, d_mode } } },
5134     { "fmaddps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5135     { "fmaddpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5136     { "fmaddss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5137     { "fmaddsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5138     /* 08 */
5139     { "fmsubps",        { { OP_DREX4, q_mode } } },
5140     { "fmsubpd",        { { OP_DREX4, q_mode } } },
5141     { "fmsubss",        { { OP_DREX4, w_mode } } },
5142     { "fmsubsd",        { { OP_DREX4, d_mode } } },
5143     { "fmsubps",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5144     { "fmsubpd",        { { OP_DREX4, DREX_OC1 + q_mode } } },
5145     { "fmsubss",        { { OP_DREX4, DREX_OC1 + w_mode } } },
5146     { "fmsubsd",        { { OP_DREX4, DREX_OC1 + d_mode } } },
5147     /* 10 */
5148     { "fnmaddps",       { { OP_DREX4, q_mode } } },
5149     { "fnmaddpd",       { { OP_DREX4, q_mode } } },
5150     { "fnmaddss",       { { OP_DREX4, w_mode } } },
5151     { "fnmaddsd",       { { OP_DREX4, d_mode } } },
5152     { "fnmaddps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5153     { "fnmaddpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5154     { "fnmaddss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5155     { "fnmaddsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5156     /* 18 */
5157     { "fnmsubps",       { { OP_DREX4, q_mode } } },
5158     { "fnmsubpd",       { { OP_DREX4, q_mode } } },
5159     { "fnmsubss",       { { OP_DREX4, w_mode } } },
5160     { "fnmsubsd",       { { OP_DREX4, d_mode } } },
5161     { "fnmsubps",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5162     { "fnmsubpd",       { { OP_DREX4, DREX_OC1 + q_mode } } },
5163     { "fnmsubss",       { { OP_DREX4, DREX_OC1 + w_mode } } },
5164     { "fnmsubsd",       { { OP_DREX4, DREX_OC1 + d_mode } } },
5165     /* 20 */
5166     { "permps",         { { OP_DREX4, q_mode } } },
5167     { "permpd",         { { OP_DREX4, q_mode } } },
5168     { "pcmov",          { { OP_DREX4, q_mode } } },
5169     { "pperm",          { { OP_DREX4, q_mode } } },
5170     { "permps",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5171     { "permpd",         { { OP_DREX4, DREX_OC1 + q_mode } } },
5172     { "pcmov",          { { OP_DREX4, DREX_OC1 + w_mode } } },
5173     { "pperm",          { { OP_DREX4, DREX_OC1 + d_mode } } },
5174     /* 28 */
5175     { "(bad)",          { XX } },
5176     { "(bad)",          { XX } },
5177     { "(bad)",          { XX } },
5178     { "(bad)",          { XX } },
5179     { "(bad)",          { XX } },
5180     { "(bad)",          { XX } },
5181     { "(bad)",          { XX } },
5182     { "(bad)",          { XX } },
5183     /* 30 */
5184     { "(bad)",          { XX } },
5185     { "(bad)",          { XX } },
5186     { "(bad)",          { XX } },
5187     { "(bad)",          { XX } },
5188     { "(bad)",          { XX } },
5189     { "(bad)",          { XX } },
5190     { "(bad)",          { XX } },
5191     { "(bad)",          { XX } },
5192     /* 38 */
5193     { "(bad)",          { XX } },
5194     { "(bad)",          { XX } },
5195     { "(bad)",          { XX } },
5196     { "(bad)",          { XX } },
5197     { "(bad)",          { XX } },
5198     { "(bad)",          { XX } },
5199     { "(bad)",          { XX } },
5200     { "(bad)",          { XX } },
5201     /* 40 */
5202     { "protb",          { { OP_DREX3, q_mode } } },
5203     { "protw",          { { OP_DREX3, q_mode } } },
5204     { "protd",          { { OP_DREX3, q_mode } } },
5205     { "protq",          { { OP_DREX3, q_mode } } },
5206     { "pshlb",          { { OP_DREX3, q_mode } } },
5207     { "pshlw",          { { OP_DREX3, q_mode } } },
5208     { "pshld",          { { OP_DREX3, q_mode } } },
5209     { "pshlq",          { { OP_DREX3, q_mode } } },
5210     /* 48 */
5211     { "pshab",          { { OP_DREX3, q_mode } } },
5212     { "pshaw",          { { OP_DREX3, q_mode } } },
5213     { "pshad",          { { OP_DREX3, q_mode } } },
5214     { "pshaq",          { { OP_DREX3, q_mode } } },
5215     { "(bad)",          { XX } },
5216     { "(bad)",          { XX } },
5217     { "(bad)",          { XX } },
5218     { "(bad)",          { XX } },
5219     /* 50 */
5220     { "(bad)",          { XX } },
5221     { "(bad)",          { XX } },
5222     { "(bad)",          { XX } },
5223     { "(bad)",          { XX } },
5224     { "(bad)",          { XX } },
5225     { "(bad)",          { XX } },
5226     { "(bad)",          { XX } },
5227     { "(bad)",          { XX } },
5228     /* 58 */
5229     { "(bad)",          { XX } },
5230     { "(bad)",          { XX } },
5231     { "(bad)",          { XX } },
5232     { "(bad)",          { XX } },
5233     { "(bad)",          { XX } },
5234     { "(bad)",          { XX } },
5235     { "(bad)",          { XX } },
5236     { "(bad)",          { XX } },
5237     /* 60 */
5238     { "(bad)",          { XX } },
5239     { "(bad)",          { XX } },
5240     { "(bad)",          { XX } },
5241     { "(bad)",          { XX } },
5242     { "(bad)",          { XX } },
5243     { "(bad)",          { XX } },
5244     { "(bad)",          { XX } },
5245     { "(bad)",          { XX } },
5246     /* 68 */
5247     { "(bad)",          { XX } },
5248     { "(bad)",          { XX } },
5249     { "(bad)",          { XX } },
5250     { "(bad)",          { XX } },
5251     { "(bad)",          { XX } },
5252     { "(bad)",          { XX } },
5253     { "(bad)",          { XX } },
5254     { "(bad)",          { XX } },
5255     /* 70 */
5256     { "(bad)",          { XX } },
5257     { "(bad)",          { XX } },
5258     { "(bad)",          { XX } },
5259     { "(bad)",          { XX } },
5260     { "(bad)",          { XX } },
5261     { "(bad)",          { XX } },
5262     { "(bad)",          { XX } },
5263     { "(bad)",          { XX } },
5264     /* 78 */
5265     { "(bad)",          { XX } },
5266     { "(bad)",          { XX } },
5267     { "(bad)",          { XX } },
5268     { "(bad)",          { XX } },
5269     { "(bad)",          { XX } },
5270     { "(bad)",          { XX } },
5271     { "(bad)",          { XX } },
5272     { "(bad)",          { XX } },
5273     /* 80 */
5274     { "(bad)",          { XX } },
5275     { "(bad)",          { XX } },
5276     { "(bad)",          { XX } },
5277     { "(bad)",          { XX } },
5278     { "(bad)",          { XX } },
5279     { "pmacssww",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5280     { "pmacsswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5281     { "pmacssdql",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5282     /* 88 */
5283     { "(bad)",          { XX } },
5284     { "(bad)",          { XX } },
5285     { "(bad)",          { XX } },
5286     { "(bad)",          { XX } },
5287     { "(bad)",          { XX } },
5288     { "(bad)",          { XX } },
5289     { "pmacssdd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5290     { "pmacssdqh",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5291     /* 90 */
5292     { "(bad)",          { XX } },
5293     { "(bad)",          { XX } },
5294     { "(bad)",          { XX } },
5295     { "(bad)",          { XX } },
5296     { "(bad)",          { XX } },
5297     { "pmacsww",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5298     { "pmacswd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5299     { "pmacsdql",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5300     /* 98 */
5301     { "(bad)",          { XX } },
5302     { "(bad)",          { XX } },
5303     { "(bad)",          { XX } },
5304     { "(bad)",          { XX } },
5305     { "(bad)",          { XX } },
5306     { "(bad)",          { XX } },
5307     { "pmacsdd",        { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5308     { "pmacsdqh",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5309     /* a0 */
5310     { "(bad)",          { XX } },
5311     { "(bad)",          { XX } },
5312     { "(bad)",          { XX } },
5313     { "(bad)",          { XX } },
5314     { "(bad)",          { XX } },
5315     { "(bad)",          { XX } },
5316     { "pmadcsswd",      { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5317     { "(bad)",          { XX } },
5318     /* a8 */
5319     { "(bad)",          { XX } },
5320     { "(bad)",          { XX } },
5321     { "(bad)",          { XX } },
5322     { "(bad)",          { XX } },
5323     { "(bad)",          { XX } },
5324     { "(bad)",          { XX } },
5325     { "(bad)",          { XX } },
5326     { "(bad)",          { XX } },
5327     /* b0 */
5328     { "(bad)",          { XX } },
5329     { "(bad)",          { XX } },
5330     { "(bad)",          { XX } },
5331     { "(bad)",          { XX } },
5332     { "(bad)",          { XX } },
5333     { "(bad)",          { XX } },
5334     { "pmadcswd",       { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5335     { "(bad)",          { XX } },
5336     /* b8 */
5337     { "(bad)",          { XX } },
5338     { "(bad)",          { XX } },
5339     { "(bad)",          { XX } },
5340     { "(bad)",          { XX } },
5341     { "(bad)",          { XX } },
5342     { "(bad)",          { XX } },
5343     { "(bad)",          { XX } },
5344     { "(bad)",          { XX } },
5345     /* c0 */
5346     { "(bad)",          { XX } },
5347     { "(bad)",          { XX } },
5348     { "(bad)",          { XX } },
5349     { "(bad)",          { XX } },
5350     { "(bad)",          { XX } },
5351     { "(bad)",          { XX } },
5352     { "(bad)",          { XX } },
5353     { "(bad)",          { XX } },
5354     /* c8 */
5355     { "(bad)",          { XX } },
5356     { "(bad)",          { XX } },
5357     { "(bad)",          { XX } },
5358     { "(bad)",          { XX } },
5359     { "(bad)",          { XX } },
5360     { "(bad)",          { XX } },
5361     { "(bad)",          { XX } },
5362     { "(bad)",          { XX } },
5363     /* d0 */
5364     { "(bad)",          { XX } },
5365     { "(bad)",          { XX } },
5366     { "(bad)",          { XX } },
5367     { "(bad)",          { XX } },
5368     { "(bad)",          { XX } },
5369     { "(bad)",          { XX } },
5370     { "(bad)",          { XX } },
5371     { "(bad)",          { XX } },
5372     /* d8 */
5373     { "(bad)",          { XX } },
5374     { "(bad)",          { XX } },
5375     { "(bad)",          { XX } },
5376     { "(bad)",          { XX } },
5377     { "(bad)",          { XX } },
5378     { "(bad)",          { XX } },
5379     { "(bad)",          { XX } },
5380     { "(bad)",          { XX } },
5381     /* e0 */
5382     { "(bad)",          { XX } },
5383     { "(bad)",          { XX } },
5384     { "(bad)",          { XX } },
5385     { "(bad)",          { XX } },
5386     { "(bad)",          { XX } },
5387     { "(bad)",          { XX } },
5388     { "(bad)",          { XX } },
5389     { "(bad)",          { XX } },
5390     /* e8 */
5391     { "(bad)",          { XX } },
5392     { "(bad)",          { XX } },
5393     { "(bad)",          { XX } },
5394     { "(bad)",          { XX } },
5395     { "(bad)",          { XX } },
5396     { "(bad)",          { XX } },
5397     { "(bad)",          { XX } },
5398     { "(bad)",          { XX } },
5399     /* f0 */
5400     { "(bad)",          { XX } },
5401     { "(bad)",          { XX } },
5402     { "(bad)",          { XX } },
5403     { "(bad)",          { XX } },
5404     { "(bad)",          { XX } },
5405     { "(bad)",          { XX } },
5406     { "(bad)",          { XX } },
5407     { "(bad)",          { XX } },
5408     /* f8 */
5409     { "(bad)",          { XX } },
5410     { "(bad)",          { XX } },
5411     { "(bad)",          { XX } },
5412     { "(bad)",          { XX } },
5413     { "(bad)",          { XX } },
5414     { "(bad)",          { XX } },
5415     { "(bad)",          { XX } },
5416     { "(bad)",          { XX } },
5417   },
5418   /* THREE_BYTE_0F25 */
5419   {
5420     /* 00 */
5421     { "(bad)",          { XX } },
5422     { "(bad)",          { XX } },
5423     { "(bad)",          { XX } },
5424     { "(bad)",          { XX } },
5425     { "(bad)",          { XX } },
5426     { "(bad)",          { XX } },
5427     { "(bad)",          { XX } },
5428     { "(bad)",          { XX } },
5429     /* 08 */
5430     { "(bad)",          { XX } },
5431     { "(bad)",          { XX } },
5432     { "(bad)",          { XX } },
5433     { "(bad)",          { XX } },
5434     { "(bad)",          { XX } },
5435     { "(bad)",          { XX } },
5436     { "(bad)",          { XX } },
5437     { "(bad)",          { XX } },
5438     /* 10 */
5439     { "(bad)",          { XX } },
5440     { "(bad)",          { XX } },
5441     { "(bad)",          { XX } },
5442     { "(bad)",          { XX } },
5443     { "(bad)",          { XX } },
5444     { "(bad)",          { XX } },
5445     { "(bad)",          { XX } },
5446     { "(bad)",          { XX } },
5447     /* 18 */
5448     { "(bad)",          { XX } },
5449     { "(bad)",          { XX } },
5450     { "(bad)",          { XX } },
5451     { "(bad)",          { XX } },
5452     { "(bad)",          { XX } },
5453     { "(bad)",          { XX } },
5454     { "(bad)",          { XX } },
5455     { "(bad)",          { XX } },
5456     /* 20 */
5457     { "(bad)",          { XX } },
5458     { "(bad)",          { XX } },
5459     { "(bad)",          { XX } },
5460     { "(bad)",          { XX } },
5461     { "(bad)",          { XX } },
5462     { "(bad)",          { XX } },
5463     { "(bad)",          { XX } },
5464     { "(bad)",          { XX } },
5465     /* 28 */
5466     { "(bad)",          { XX } },
5467     { "(bad)",          { XX } },
5468     { "(bad)",          { XX } },
5469     { "(bad)",          { XX } },
5470     { "comps",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5471     { "compd",          { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5472     { "comss",          { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5473     { "comsd",          { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5474     /* 30 */
5475     { "(bad)",          { XX } },
5476     { "(bad)",          { XX } },
5477     { "(bad)",          { XX } },
5478     { "(bad)",          { XX } },
5479     { "(bad)",          { XX } },
5480     { "(bad)",          { XX } },
5481     { "(bad)",          { XX } },
5482     { "(bad)",          { XX } },
5483     /* 38 */
5484     { "(bad)",          { XX } },
5485     { "(bad)",          { XX } },
5486     { "(bad)",          { XX } },
5487     { "(bad)",          { XX } },
5488     { "(bad)",          { XX } },
5489     { "(bad)",          { XX } },
5490     { "(bad)",          { XX } },
5491     { "(bad)",          { XX } },
5492     /* 40 */
5493     { "(bad)",          { XX } },
5494     { "(bad)",          { XX } },
5495     { "(bad)",          { XX } },
5496     { "(bad)",          { XX } },
5497     { "(bad)",          { XX } },
5498     { "(bad)",          { XX } },
5499     { "(bad)",          { XX } },
5500     { "(bad)",          { XX } },
5501     /* 48 */
5502     { "(bad)",          { XX } },
5503     { "(bad)",          { XX } },
5504     { "(bad)",          { XX } },
5505     { "(bad)",          { XX } },
5506     { "pcomb",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5507     { "pcomw",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5508     { "pcomd",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5509     { "pcomq",          { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5510     /* 50 */
5511     { "(bad)",          { XX } },
5512     { "(bad)",          { XX } },
5513     { "(bad)",          { XX } },
5514     { "(bad)",          { XX } },
5515     { "(bad)",          { XX } },
5516     { "(bad)",          { XX } },
5517     { "(bad)",          { XX } },
5518     { "(bad)",          { XX } },
5519     /* 58 */
5520     { "(bad)",          { XX } },
5521     { "(bad)",          { XX } },
5522     { "(bad)",          { XX } },
5523     { "(bad)",          { XX } },
5524     { "(bad)",          { XX } },
5525     { "(bad)",          { XX } },
5526     { "(bad)",          { XX } },
5527     { "(bad)",          { XX } },
5528     /* 60 */
5529     { "(bad)",          { XX } },
5530     { "(bad)",          { XX } },
5531     { "(bad)",          { XX } },
5532     { "(bad)",          { XX } },
5533     { "(bad)",          { XX } },
5534     { "(bad)",          { XX } },
5535     { "(bad)",          { XX } },
5536     { "(bad)",          { XX } },
5537     /* 68 */
5538     { "(bad)",          { XX } },
5539     { "(bad)",          { XX } },
5540     { "(bad)",          { XX } },
5541     { "(bad)",          { XX } },
5542     { "pcomub",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5543     { "pcomuw",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5544     { "pcomud",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5545     { "pcomuq",         { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5546     /* 70 */
5547     { "(bad)",          { XX } },
5548     { "(bad)",          { XX } },
5549     { "(bad)",          { XX } },
5550     { "(bad)",          { XX } },
5551     { "(bad)",          { XX } },
5552     { "(bad)",          { XX } },
5553     { "(bad)",          { XX } },
5554     { "(bad)",          { XX } },
5555     /* 78 */
5556     { "(bad)",          { XX } },
5557     { "(bad)",          { XX } },
5558     { "(bad)",          { XX } },
5559     { "(bad)",          { XX } },
5560     { "(bad)",          { XX } },
5561     { "(bad)",          { XX } },
5562     { "(bad)",          { XX } },
5563     { "(bad)",          { XX } },
5564     /* 80 */
5565     { "(bad)",          { XX } },
5566     { "(bad)",          { XX } },
5567     { "(bad)",          { XX } },
5568     { "(bad)",          { XX } },
5569     { "(bad)",          { XX } },
5570     { "(bad)",          { XX } },
5571     { "(bad)",          { XX } },
5572     { "(bad)",          { XX } },
5573     /* 88 */
5574     { "(bad)",          { XX } },
5575     { "(bad)",          { XX } },
5576     { "(bad)",          { XX } },
5577     { "(bad)",          { XX } },
5578     { "(bad)",          { XX } },
5579     { "(bad)",          { XX } },
5580     { "(bad)",          { XX } },
5581     { "(bad)",          { XX } },
5582     /* 90 */
5583     { "(bad)",          { XX } },
5584     { "(bad)",          { XX } },
5585     { "(bad)",          { XX } },
5586     { "(bad)",          { XX } },
5587     { "(bad)",          { XX } },
5588     { "(bad)",          { XX } },
5589     { "(bad)",          { XX } },
5590     { "(bad)",          { XX } },
5591     /* 98 */
5592     { "(bad)",          { XX } },
5593     { "(bad)",          { XX } },
5594     { "(bad)",          { XX } },
5595     { "(bad)",          { XX } },
5596     { "(bad)",          { XX } },
5597     { "(bad)",          { XX } },
5598     { "(bad)",          { XX } },
5599     { "(bad)",          { XX } },
5600     /* a0 */
5601     { "(bad)",          { XX } },
5602     { "(bad)",          { XX } },
5603     { "(bad)",          { XX } },
5604     { "(bad)",          { XX } },
5605     { "(bad)",          { XX } },
5606     { "(bad)",          { XX } },
5607     { "(bad)",          { XX } },
5608     { "(bad)",          { XX } },
5609     /* a8 */
5610     { "(bad)",          { XX } },
5611     { "(bad)",          { XX } },
5612     { "(bad)",          { XX } },
5613     { "(bad)",          { XX } },
5614     { "(bad)",          { XX } },
5615     { "(bad)",          { XX } },
5616     { "(bad)",          { XX } },
5617     { "(bad)",          { XX } },
5618     /* b0 */
5619     { "(bad)",          { XX } },
5620     { "(bad)",          { XX } },
5621     { "(bad)",          { XX } },
5622     { "(bad)",          { XX } },
5623     { "(bad)",          { XX } },
5624     { "(bad)",          { XX } },
5625     { "(bad)",          { XX } },
5626     { "(bad)",          { XX } },
5627     /* b8 */
5628     { "(bad)",          { XX } },
5629     { "(bad)",          { XX } },
5630     { "(bad)",          { XX } },
5631     { "(bad)",          { XX } },
5632     { "(bad)",          { XX } },
5633     { "(bad)",          { XX } },
5634     { "(bad)",          { XX } },
5635     { "(bad)",          { XX } },
5636     /* c0 */
5637     { "(bad)",          { XX } },
5638     { "(bad)",          { XX } },
5639     { "(bad)",          { XX } },
5640     { "(bad)",          { XX } },
5641     { "(bad)",          { XX } },
5642     { "(bad)",          { XX } },
5643     { "(bad)",          { XX } },
5644     { "(bad)",          { XX } },
5645     /* c8 */
5646     { "(bad)",          { XX } },
5647     { "(bad)",          { XX } },
5648     { "(bad)",          { XX } },
5649     { "(bad)",          { XX } },
5650     { "(bad)",          { XX } },
5651     { "(bad)",          { XX } },
5652     { "(bad)",          { XX } },
5653     { "(bad)",          { XX } },
5654     /* d0 */
5655     { "(bad)",          { XX } },
5656     { "(bad)",          { XX } },
5657     { "(bad)",          { XX } },
5658     { "(bad)",          { XX } },
5659     { "(bad)",          { XX } },
5660     { "(bad)",          { XX } },
5661     { "(bad)",          { XX } },
5662     { "(bad)",          { XX } },
5663     /* d8 */
5664     { "(bad)",          { XX } },
5665     { "(bad)",          { XX } },
5666     { "(bad)",          { XX } },
5667     { "(bad)",          { XX } },
5668     { "(bad)",          { XX } },
5669     { "(bad)",          { XX } },
5670     { "(bad)",          { XX } },
5671     { "(bad)",          { XX } },
5672     /* e0 */
5673     { "(bad)",          { XX } },
5674     { "(bad)",          { XX } },
5675     { "(bad)",          { XX } },
5676     { "(bad)",          { XX } },
5677     { "(bad)",          { XX } },
5678     { "(bad)",          { XX } },
5679     { "(bad)",          { XX } },
5680     { "(bad)",          { XX } },
5681     /* e8 */
5682     { "(bad)",          { XX } },
5683     { "(bad)",          { XX } },
5684     { "(bad)",          { XX } },
5685     { "(bad)",          { XX } },
5686     { "(bad)",          { XX } },
5687     { "(bad)",          { XX } },
5688     { "(bad)",          { XX } },
5689     { "(bad)",          { XX } },
5690     /* f0 */
5691     { "(bad)",          { XX } },
5692     { "(bad)",          { XX } },
5693     { "(bad)",          { XX } },
5694     { "(bad)",          { XX } },
5695     { "(bad)",          { XX } },
5696     { "(bad)",          { XX } },
5697     { "(bad)",          { XX } },
5698     { "(bad)",          { XX } },
5699     /* f8 */
5700     { "(bad)",          { XX } },
5701     { "(bad)",          { XX } },
5702     { "(bad)",          { XX } },
5703     { "(bad)",          { XX } },
5704     { "(bad)",          { XX } },
5705     { "(bad)",          { XX } },
5706     { "(bad)",          { XX } },
5707     { "(bad)",          { XX } },
5708   },
5709   /* THREE_BYTE_0F38 */
5710   {
5711     /* 00 */
5712     { "pshufb",         { MX, EM } },
5713     { "phaddw",         { MX, EM } },
5714     { "phaddd",         { MX, EM } },
5715     { "phaddsw",        { MX, EM } },
5716     { "pmaddubsw",      { MX, EM } },
5717     { "phsubw",         { MX, EM } },
5718     { "phsubd",         { MX, EM } },
5719     { "phsubsw",        { MX, EM } },
5720     /* 08 */
5721     { "psignb",         { MX, EM } },
5722     { "psignw",         { MX, EM } },
5723     { "psignd",         { MX, EM } },
5724     { "pmulhrsw",       { MX, EM } },
5725     { "(bad)",          { XX } },
5726     { "(bad)",          { XX } },
5727     { "(bad)",          { XX } },
5728     { "(bad)",          { XX } },
5729     /* 10 */
5730     { PREFIX_TABLE (PREFIX_0F3810) },
5731     { "(bad)",          { XX } },
5732     { "(bad)",          { XX } },
5733     { "(bad)",          { XX } },
5734     { PREFIX_TABLE (PREFIX_0F3814) },
5735     { PREFIX_TABLE (PREFIX_0F3815) },
5736     { "(bad)",          { XX } },
5737     { PREFIX_TABLE (PREFIX_0F3817) },
5738     /* 18 */
5739     { "(bad)",          { XX } },
5740     { "(bad)",          { XX } },
5741     { "(bad)",          { XX } },
5742     { "(bad)",          { XX } },
5743     { "pabsb",          { MX, EM } },
5744     { "pabsw",          { MX, EM } },
5745     { "pabsd",          { MX, EM } },
5746     { "(bad)",          { XX } },
5747     /* 20 */
5748     { PREFIX_TABLE (PREFIX_0F3820) },
5749     { PREFIX_TABLE (PREFIX_0F3821) },
5750     { PREFIX_TABLE (PREFIX_0F3822) },
5751     { PREFIX_TABLE (PREFIX_0F3823) },
5752     { PREFIX_TABLE (PREFIX_0F3824) },
5753     { PREFIX_TABLE (PREFIX_0F3825) },
5754     { "(bad)",          { XX } },
5755     { "(bad)",          { XX } },
5756     /* 28 */
5757     { PREFIX_TABLE (PREFIX_0F3828) },
5758     { PREFIX_TABLE (PREFIX_0F3829) },
5759     { PREFIX_TABLE (PREFIX_0F382A) },
5760     { PREFIX_TABLE (PREFIX_0F382B) },
5761     { "(bad)",          { XX } },
5762     { "(bad)",          { XX } },
5763     { "(bad)",          { XX } },
5764     { "(bad)",          { XX } },
5765     /* 30 */
5766     { PREFIX_TABLE (PREFIX_0F3830) },
5767     { PREFIX_TABLE (PREFIX_0F3831) },
5768     { PREFIX_TABLE (PREFIX_0F3832) },
5769     { PREFIX_TABLE (PREFIX_0F3833) },
5770     { PREFIX_TABLE (PREFIX_0F3834) },
5771     { PREFIX_TABLE (PREFIX_0F3835) },
5772     { "(bad)",          { XX } },
5773     { PREFIX_TABLE (PREFIX_0F3837) },
5774     /* 38 */
5775     { PREFIX_TABLE (PREFIX_0F3838) },
5776     { PREFIX_TABLE (PREFIX_0F3839) },
5777     { PREFIX_TABLE (PREFIX_0F383A) },
5778     { PREFIX_TABLE (PREFIX_0F383B) },
5779     { PREFIX_TABLE (PREFIX_0F383C) },
5780     { PREFIX_TABLE (PREFIX_0F383D) },
5781     { PREFIX_TABLE (PREFIX_0F383E) },
5782     { PREFIX_TABLE (PREFIX_0F383F) },
5783     /* 40 */
5784     { PREFIX_TABLE (PREFIX_0F3840) },
5785     { PREFIX_TABLE (PREFIX_0F3841) },
5786     { "(bad)",          { XX } },
5787     { "(bad)",          { XX } },
5788     { "(bad)",          { XX } },
5789     { "(bad)",          { XX } },
5790     { "(bad)",          { XX } },
5791     { "(bad)",          { XX } },
5792     /* 48 */
5793     { "(bad)",          { XX } },
5794     { "(bad)",          { XX } },
5795     { "(bad)",          { XX } },
5796     { "(bad)",          { XX } },
5797     { "(bad)",          { XX } },
5798     { "(bad)",          { XX } },
5799     { "(bad)",          { XX } },
5800     { "(bad)",          { XX } },
5801     /* 50 */
5802     { "(bad)",          { XX } },
5803     { "(bad)",          { XX } },
5804     { "(bad)",          { XX } },
5805     { "(bad)",          { XX } },
5806     { "(bad)",          { XX } },
5807     { "(bad)",          { XX } },
5808     { "(bad)",          { XX } },
5809     { "(bad)",          { XX } },
5810     /* 58 */
5811     { "(bad)",          { XX } },
5812     { "(bad)",          { XX } },
5813     { "(bad)",          { XX } },
5814     { "(bad)",          { XX } },
5815     { "(bad)",          { XX } },
5816     { "(bad)",          { XX } },
5817     { "(bad)",          { XX } },
5818     { "(bad)",          { XX } },
5819     /* 60 */
5820     { "(bad)",          { XX } },
5821     { "(bad)",          { XX } },
5822     { "(bad)",          { XX } },
5823     { "(bad)",          { XX } },
5824     { "(bad)",          { XX } },
5825     { "(bad)",          { XX } },
5826     { "(bad)",          { XX } },
5827     { "(bad)",          { XX } },
5828     /* 68 */
5829     { "(bad)",          { XX } },
5830     { "(bad)",          { XX } },
5831     { "(bad)",          { XX } },
5832     { "(bad)",          { XX } },
5833     { "(bad)",          { XX } },
5834     { "(bad)",          { XX } },
5835     { "(bad)",          { XX } },
5836     { "(bad)",          { XX } },
5837     /* 70 */
5838     { "(bad)",          { XX } },
5839     { "(bad)",          { XX } },
5840     { "(bad)",          { XX } },
5841     { "(bad)",          { XX } },
5842     { "(bad)",          { XX } },
5843     { "(bad)",          { XX } },
5844     { "(bad)",          { XX } },
5845     { "(bad)",          { XX } },
5846     /* 78 */
5847     { "(bad)",          { XX } },
5848     { "(bad)",          { XX } },
5849     { "(bad)",          { XX } },
5850     { "(bad)",          { XX } },
5851     { "(bad)",          { XX } },
5852     { "(bad)",          { XX } },
5853     { "(bad)",          { XX } },
5854     { "(bad)",          { XX } },
5855     /* 80 */
5856     { PREFIX_TABLE (PREFIX_0F3880) },
5857     { PREFIX_TABLE (PREFIX_0F3881) },
5858     { "(bad)",          { XX } },
5859     { "(bad)",          { XX } },
5860     { "(bad)",          { XX } },
5861     { "(bad)",          { XX } },
5862     { "(bad)",          { XX } },
5863     { "(bad)",          { XX } },
5864     /* 88 */
5865     { "(bad)",          { XX } },
5866     { "(bad)",          { XX } },
5867     { "(bad)",          { XX } },
5868     { "(bad)",          { XX } },
5869     { "(bad)",          { XX } },
5870     { "(bad)",          { XX } },
5871     { "(bad)",          { XX } },
5872     { "(bad)",          { XX } },
5873     /* 90 */
5874     { "(bad)",          { XX } },
5875     { "(bad)",          { XX } },
5876     { "(bad)",          { XX } },
5877     { "(bad)",          { XX } },
5878     { "(bad)",          { XX } },
5879     { "(bad)",          { XX } },
5880     { "(bad)",          { XX } },
5881     { "(bad)",          { XX } },
5882     /* 98 */
5883     { "(bad)",          { XX } },
5884     { "(bad)",          { XX } },
5885     { "(bad)",          { XX } },
5886     { "(bad)",          { XX } },
5887     { "(bad)",          { XX } },
5888     { "(bad)",          { XX } },
5889     { "(bad)",          { XX } },
5890     { "(bad)",          { XX } },
5891     /* a0 */
5892     { "(bad)",          { XX } },
5893     { "(bad)",          { XX } },
5894     { "(bad)",          { XX } },
5895     { "(bad)",          { XX } },
5896     { "(bad)",          { XX } },
5897     { "(bad)",          { XX } },
5898     { "(bad)",          { XX } },
5899     { "(bad)",          { XX } },
5900     /* a8 */
5901     { "(bad)",          { XX } },
5902     { "(bad)",          { XX } },
5903     { "(bad)",          { XX } },
5904     { "(bad)",          { XX } },
5905     { "(bad)",          { XX } },
5906     { "(bad)",          { XX } },
5907     { "(bad)",          { XX } },
5908     { "(bad)",          { XX } },
5909     /* b0 */
5910     { "(bad)",          { XX } },
5911     { "(bad)",          { XX } },
5912     { "(bad)",          { XX } },
5913     { "(bad)",          { XX } },
5914     { "(bad)",          { XX } },
5915     { "(bad)",          { XX } },
5916     { "(bad)",          { XX } },
5917     { "(bad)",          { XX } },
5918     /* b8 */
5919     { "(bad)",          { XX } },
5920     { "(bad)",          { XX } },
5921     { "(bad)",          { XX } },
5922     { "(bad)",          { XX } },
5923     { "(bad)",          { XX } },
5924     { "(bad)",          { XX } },
5925     { "(bad)",          { XX } },
5926     { "(bad)",          { XX } },
5927     /* c0 */
5928     { "(bad)",          { XX } },
5929     { "(bad)",          { XX } },
5930     { "(bad)",          { XX } },
5931     { "(bad)",          { XX } },
5932     { "(bad)",          { XX } },
5933     { "(bad)",          { XX } },
5934     { "(bad)",          { XX } },
5935     { "(bad)",          { XX } },
5936     /* c8 */
5937     { "(bad)",          { XX } },
5938     { "(bad)",          { XX } },
5939     { "(bad)",          { XX } },
5940     { "(bad)",          { XX } },
5941     { "(bad)",          { XX } },
5942     { "(bad)",          { XX } },
5943     { "(bad)",          { XX } },
5944     { "(bad)",          { XX } },
5945     /* d0 */
5946     { "(bad)",          { XX } },
5947     { "(bad)",          { XX } },
5948     { "(bad)",          { XX } },
5949     { "(bad)",          { XX } },
5950     { "(bad)",          { XX } },
5951     { "(bad)",          { XX } },
5952     { "(bad)",          { XX } },
5953     { "(bad)",          { XX } },
5954     /* d8 */
5955     { "(bad)",          { XX } },
5956     { "(bad)",          { XX } },
5957     { "(bad)",          { XX } },
5958     { PREFIX_TABLE (PREFIX_0F38DB) },
5959     { PREFIX_TABLE (PREFIX_0F38DC) },
5960     { PREFIX_TABLE (PREFIX_0F38DD) },
5961     { PREFIX_TABLE (PREFIX_0F38DE) },
5962     { PREFIX_TABLE (PREFIX_0F38DF) },
5963     /* e0 */
5964     { "(bad)",          { XX } },
5965     { "(bad)",          { XX } },
5966     { "(bad)",          { XX } },
5967     { "(bad)",          { XX } },
5968     { "(bad)",          { XX } },
5969     { "(bad)",          { XX } },
5970     { "(bad)",          { XX } },
5971     { "(bad)",          { XX } },
5972     /* e8 */
5973     { "(bad)",          { XX } },
5974     { "(bad)",          { XX } },
5975     { "(bad)",          { XX } },
5976     { "(bad)",          { XX } },
5977     { "(bad)",          { XX } },
5978     { "(bad)",          { XX } },
5979     { "(bad)",          { XX } },
5980     { "(bad)",          { XX } },
5981     /* f0 */
5982     { PREFIX_TABLE (PREFIX_0F38F0) },
5983     { PREFIX_TABLE (PREFIX_0F38F1) },
5984     { "(bad)",          { XX } },
5985     { "(bad)",          { XX } },
5986     { "(bad)",          { XX } },
5987     { "(bad)",          { XX } },
5988     { "(bad)",          { XX } },
5989     { "(bad)",          { XX } },
5990     /* f8 */
5991     { "(bad)",          { XX } },
5992     { "(bad)",          { XX } },
5993     { "(bad)",          { XX } },
5994     { "(bad)",          { XX } },
5995     { "(bad)",          { XX } },
5996     { "(bad)",          { XX } },
5997     { "(bad)",          { XX } },
5998     { "(bad)",          { XX } },
5999   },
6000   /* THREE_BYTE_0F3A */
6001   {
6002     /* 00 */
6003     { "(bad)",          { XX } },
6004     { "(bad)",          { XX } },
6005     { "(bad)",          { XX } },
6006     { "(bad)",          { XX } },
6007     { "(bad)",          { XX } },
6008     { "(bad)",          { XX } },
6009     { "(bad)",          { XX } },
6010     { "(bad)",          { XX } },
6011     /* 08 */
6012     { PREFIX_TABLE (PREFIX_0F3A08) },
6013     { PREFIX_TABLE (PREFIX_0F3A09) },
6014     { PREFIX_TABLE (PREFIX_0F3A0A) },
6015     { PREFIX_TABLE (PREFIX_0F3A0B) },
6016     { PREFIX_TABLE (PREFIX_0F3A0C) },
6017     { PREFIX_TABLE (PREFIX_0F3A0D) },
6018     { PREFIX_TABLE (PREFIX_0F3A0E) },
6019     { "palignr",        { MX, EM, Ib } },
6020     /* 10 */
6021     { "(bad)",          { XX } },
6022     { "(bad)",          { XX } },
6023     { "(bad)",          { XX } },
6024     { "(bad)",          { XX } },
6025     { PREFIX_TABLE (PREFIX_0F3A14) },
6026     { PREFIX_TABLE (PREFIX_0F3A15) },
6027     { PREFIX_TABLE (PREFIX_0F3A16) },
6028     { PREFIX_TABLE (PREFIX_0F3A17) },
6029     /* 18 */
6030     { "(bad)",          { XX } },
6031     { "(bad)",          { XX } },
6032     { "(bad)",          { XX } },
6033     { "(bad)",          { XX } },
6034     { "(bad)",          { XX } },
6035     { "(bad)",          { XX } },
6036     { "(bad)",          { XX } },
6037     { "(bad)",          { XX } },
6038     /* 20 */
6039     { PREFIX_TABLE (PREFIX_0F3A20) },
6040     { PREFIX_TABLE (PREFIX_0F3A21) },
6041     { PREFIX_TABLE (PREFIX_0F3A22) },
6042     { "(bad)",          { XX } },
6043     { "(bad)",          { XX } },
6044     { "(bad)",          { XX } },
6045     { "(bad)",          { XX } },
6046     { "(bad)",          { XX } },
6047     /* 28 */
6048     { "(bad)",          { XX } },
6049     { "(bad)",          { XX } },
6050     { "(bad)",          { XX } },
6051     { "(bad)",          { XX } },
6052     { "(bad)",          { XX } },
6053     { "(bad)",          { XX } },
6054     { "(bad)",          { XX } },
6055     { "(bad)",          { XX } },
6056     /* 30 */
6057     { "(bad)",          { XX } },
6058     { "(bad)",          { XX } },
6059     { "(bad)",          { XX } },
6060     { "(bad)",          { XX } },
6061     { "(bad)",          { XX } },
6062     { "(bad)",          { XX } },
6063     { "(bad)",          { XX } },
6064     { "(bad)",          { XX } },
6065     /* 38 */
6066     { "(bad)",          { XX } },
6067     { "(bad)",          { XX } },
6068     { "(bad)",          { XX } },
6069     { "(bad)",          { XX } },
6070     { "(bad)",          { XX } },
6071     { "(bad)",          { XX } },
6072     { "(bad)",          { XX } },
6073     { "(bad)",          { XX } },
6074     /* 40 */
6075     { PREFIX_TABLE (PREFIX_0F3A40) },
6076     { PREFIX_TABLE (PREFIX_0F3A41) },
6077     { PREFIX_TABLE (PREFIX_0F3A42) },
6078     { "(bad)",          { XX } },
6079     { PREFIX_TABLE (PREFIX_0F3A44) },
6080     { "(bad)",          { XX } },
6081     { "(bad)",          { XX } },
6082     { "(bad)",          { XX } },
6083     /* 48 */
6084     { "(bad)",          { XX } },
6085     { "(bad)",          { XX } },
6086     { "(bad)",          { XX } },
6087     { "(bad)",          { XX } },
6088     { "(bad)",          { XX } },
6089     { "(bad)",          { XX } },
6090     { "(bad)",          { XX } },
6091     { "(bad)",          { XX } },
6092     /* 50 */
6093     { "(bad)",          { XX } },
6094     { "(bad)",          { XX } },
6095     { "(bad)",          { XX } },
6096     { "(bad)",          { XX } },
6097     { "(bad)",          { XX } },
6098     { "(bad)",          { XX } },
6099     { "(bad)",          { XX } },
6100     { "(bad)",          { XX } },
6101     /* 58 */
6102     { "(bad)",          { XX } },
6103     { "(bad)",          { XX } },
6104     { "(bad)",          { XX } },
6105     { "(bad)",          { XX } },
6106     { "(bad)",          { XX } },
6107     { "(bad)",          { XX } },
6108     { "(bad)",          { XX } },
6109     { "(bad)",          { XX } },
6110     /* 60 */
6111     { PREFIX_TABLE (PREFIX_0F3A60) },
6112     { PREFIX_TABLE (PREFIX_0F3A61) },
6113     { PREFIX_TABLE (PREFIX_0F3A62) },
6114     { PREFIX_TABLE (PREFIX_0F3A63) },
6115     { "(bad)",          { XX } },
6116     { "(bad)",          { XX } },
6117     { "(bad)",          { XX } },
6118     { "(bad)",          { XX } },
6119     /* 68 */
6120     { "(bad)",          { XX } },
6121     { "(bad)",          { XX } },
6122     { "(bad)",          { XX } },
6123     { "(bad)",          { XX } },
6124     { "(bad)",          { XX } },
6125     { "(bad)",          { XX } },
6126     { "(bad)",          { XX } },
6127     { "(bad)",          { XX } },
6128     /* 70 */
6129     { "(bad)",          { XX } },
6130     { "(bad)",          { XX } },
6131     { "(bad)",          { XX } },
6132     { "(bad)",          { XX } },
6133     { "(bad)",          { XX } },
6134     { "(bad)",          { XX } },
6135     { "(bad)",          { XX } },
6136     { "(bad)",          { XX } },
6137     /* 78 */
6138     { "(bad)",          { XX } },
6139     { "(bad)",          { XX } },
6140     { "(bad)",          { XX } },
6141     { "(bad)",          { XX } },
6142     { "(bad)",          { XX } },
6143     { "(bad)",          { XX } },
6144     { "(bad)",          { XX } },
6145     { "(bad)",          { XX } },
6146     /* 80 */
6147     { "(bad)",          { XX } },
6148     { "(bad)",          { XX } },
6149     { "(bad)",          { XX } },
6150     { "(bad)",          { XX } },
6151     { "(bad)",          { XX } },
6152     { "(bad)",          { XX } },
6153     { "(bad)",          { XX } },
6154     { "(bad)",          { XX } },
6155     /* 88 */
6156     { "(bad)",          { XX } },
6157     { "(bad)",          { XX } },
6158     { "(bad)",          { XX } },
6159     { "(bad)",          { XX } },
6160     { "(bad)",          { XX } },
6161     { "(bad)",          { XX } },
6162     { "(bad)",          { XX } },
6163     { "(bad)",          { XX } },
6164     /* 90 */
6165     { "(bad)",          { XX } },
6166     { "(bad)",          { XX } },
6167     { "(bad)",          { XX } },
6168     { "(bad)",          { XX } },
6169     { "(bad)",          { XX } },
6170     { "(bad)",          { XX } },
6171     { "(bad)",          { XX } },
6172     { "(bad)",          { XX } },
6173     /* 98 */
6174     { "(bad)",          { XX } },
6175     { "(bad)",          { XX } },
6176     { "(bad)",          { XX } },
6177     { "(bad)",          { XX } },
6178     { "(bad)",          { XX } },
6179     { "(bad)",          { XX } },
6180     { "(bad)",          { XX } },
6181     { "(bad)",          { XX } },
6182     /* a0 */
6183     { "(bad)",          { XX } },
6184     { "(bad)",          { XX } },
6185     { "(bad)",          { XX } },
6186     { "(bad)",          { XX } },
6187     { "(bad)",          { XX } },
6188     { "(bad)",          { XX } },
6189     { "(bad)",          { XX } },
6190     { "(bad)",          { XX } },
6191     /* a8 */
6192     { "(bad)",          { XX } },
6193     { "(bad)",          { XX } },
6194     { "(bad)",          { XX } },
6195     { "(bad)",          { XX } },
6196     { "(bad)",          { XX } },
6197     { "(bad)",          { XX } },
6198     { "(bad)",          { XX } },
6199     { "(bad)",          { XX } },
6200     /* b0 */
6201     { "(bad)",          { XX } },
6202     { "(bad)",          { XX } },
6203     { "(bad)",          { XX } },
6204     { "(bad)",          { XX } },
6205     { "(bad)",          { XX } },
6206     { "(bad)",          { XX } },
6207     { "(bad)",          { XX } },
6208     { "(bad)",          { XX } },
6209     /* b8 */
6210     { "(bad)",          { XX } },
6211     { "(bad)",          { XX } },
6212     { "(bad)",          { XX } },
6213     { "(bad)",          { XX } },
6214     { "(bad)",          { XX } },
6215     { "(bad)",          { XX } },
6216     { "(bad)",          { XX } },
6217     { "(bad)",          { XX } },
6218     /* c0 */
6219     { "(bad)",          { XX } },
6220     { "(bad)",          { XX } },
6221     { "(bad)",          { XX } },
6222     { "(bad)",          { XX } },
6223     { "(bad)",          { XX } },
6224     { "(bad)",          { XX } },
6225     { "(bad)",          { XX } },
6226     { "(bad)",          { XX } },
6227     /* c8 */
6228     { "(bad)",          { XX } },
6229     { "(bad)",          { XX } },
6230     { "(bad)",          { XX } },
6231     { "(bad)",          { XX } },
6232     { "(bad)",          { XX } },
6233     { "(bad)",          { XX } },
6234     { "(bad)",          { XX } },
6235     { "(bad)",          { XX } },
6236     /* d0 */
6237     { "(bad)",          { XX } },
6238     { "(bad)",          { XX } },
6239     { "(bad)",          { XX } },
6240     { "(bad)",          { XX } },
6241     { "(bad)",          { XX } },
6242     { "(bad)",          { XX } },
6243     { "(bad)",          { XX } },
6244     { "(bad)",          { XX } },
6245     /* d8 */
6246     { "(bad)",          { XX } },
6247     { "(bad)",          { XX } },
6248     { "(bad)",          { XX } },
6249     { "(bad)",          { XX } },
6250     { "(bad)",          { XX } },
6251     { "(bad)",          { XX } },
6252     { "(bad)",          { XX } },
6253     { PREFIX_TABLE (PREFIX_0F3ADF) },
6254     /* e0 */
6255     { "(bad)",          { XX } },
6256     { "(bad)",          { XX } },
6257     { "(bad)",          { XX } },
6258     { "(bad)",          { XX } },
6259     { "(bad)",          { XX } },
6260     { "(bad)",          { XX } },
6261     { "(bad)",          { XX } },
6262     { "(bad)",          { XX } },
6263     /* e8 */
6264     { "(bad)",          { XX } },
6265     { "(bad)",          { XX } },
6266     { "(bad)",          { XX } },
6267     { "(bad)",          { XX } },
6268     { "(bad)",          { XX } },
6269     { "(bad)",          { XX } },
6270     { "(bad)",          { XX } },
6271     { "(bad)",          { XX } },
6272     /* f0 */
6273     { "(bad)",          { XX } },
6274     { "(bad)",          { XX } },
6275     { "(bad)",          { XX } },
6276     { "(bad)",          { XX } },
6277     { "(bad)",          { XX } },
6278     { "(bad)",          { XX } },
6279     { "(bad)",          { XX } },
6280     { "(bad)",          { XX } },
6281     /* f8 */
6282     { "(bad)",          { XX } },
6283     { "(bad)",          { XX } },
6284     { "(bad)",          { XX } },
6285     { "(bad)",          { XX } },
6286     { "(bad)",          { XX } },
6287     { "(bad)",          { XX } },
6288     { "(bad)",          { XX } },
6289     { "(bad)",          { XX } },
6290   },
6291   /* THREE_BYTE_0F7A */
6292   {
6293     /* 00 */
6294     { "(bad)",          { XX } },
6295     { "(bad)",          { XX } },
6296     { "(bad)",          { XX } },
6297     { "(bad)",          { XX } },
6298     { "(bad)",          { XX } },
6299     { "(bad)",          { XX } },
6300     { "(bad)",          { XX } },
6301     { "(bad)",          { XX } },
6302     /* 08 */
6303     { "(bad)",          { XX } },
6304     { "(bad)",          { XX } },
6305     { "(bad)",          { XX } },
6306     { "(bad)",          { XX } },
6307     { "(bad)",          { XX } },
6308     { "(bad)",          { XX } },
6309     { "(bad)",          { XX } },
6310     { "(bad)",          { XX } },
6311     /* 10 */
6312     { "frczps",         { XM, EXq } },
6313     { "frczpd",         { XM, EXq } },
6314     { "frczss",         { XM, EXq } },
6315     { "frczsd",         { XM, EXq } },
6316     { "(bad)",          { XX } },
6317     { "(bad)",          { XX } },
6318     { "(bad)",          { XX } },
6319     { "(bad)",          { XX } },
6320     /* 18 */
6321     { "(bad)",          { XX } },
6322     { "(bad)",          { XX } },
6323     { "(bad)",          { XX } },
6324     { "(bad)",          { XX } },
6325     { "(bad)",          { XX } },
6326     { "(bad)",          { XX } },
6327     { "(bad)",          { XX } },
6328     { "(bad)",          { XX } },
6329     /* 20 */
6330     { "ptest",          { XX } },
6331     { "(bad)",          { XX } },
6332     { "(bad)",          { XX } },
6333     { "(bad)",          { XX } },
6334     { "(bad)",          { XX } },
6335     { "(bad)",          { XX } },
6336     { "(bad)",          { XX } },
6337     { "(bad)",          { XX } },
6338     /* 28 */
6339     { "(bad)",          { XX } },
6340     { "(bad)",          { XX } },
6341     { "(bad)",          { XX } },
6342     { "(bad)",          { XX } },
6343     { "(bad)",          { XX } },
6344     { "(bad)",          { XX } },
6345     { "(bad)",          { XX } },
6346     { "(bad)",          { XX } },
6347     /* 30 */
6348     { "cvtph2ps",       { XM, EXd } },
6349     { "cvtps2ph",       { EXd, XM } },
6350     { "(bad)",          { XX } },
6351     { "(bad)",          { XX } },
6352     { "(bad)",          { XX } },
6353     { "(bad)",          { XX } },
6354     { "(bad)",          { XX } },
6355     { "(bad)",          { XX } },
6356     /* 38 */
6357     { "(bad)",          { XX } },
6358     { "(bad)",          { XX } },
6359     { "(bad)",          { XX } },
6360     { "(bad)",          { XX } },
6361     { "(bad)",          { XX } },
6362     { "(bad)",          { XX } },
6363     { "(bad)",          { XX } },
6364     { "(bad)",          { XX } },
6365     /* 40 */
6366     { "(bad)",          { XX } },
6367     { "phaddbw",        { XM, EXq } },
6368     { "phaddbd",        { XM, EXq } },
6369     { "phaddbq",        { XM, EXq } },
6370     { "(bad)",          { XX } },
6371     { "(bad)",          { XX } },
6372     { "phaddwd",        { XM, EXq } },
6373     { "phaddwq",        { XM, EXq } },
6374     /* 48 */
6375     { "(bad)",          { XX } },
6376     { "(bad)",          { XX } },
6377     { "(bad)",          { XX } },
6378     { "phadddq",        { XM, EXq } },
6379     { "(bad)",          { XX } },
6380     { "(bad)",          { XX } },
6381     { "(bad)",          { XX } },
6382     { "(bad)",          { XX } },
6383     /* 50 */
6384     { "(bad)",          { XX } },
6385     { "phaddubw",       { XM, EXq } },
6386     { "phaddubd",       { XM, EXq } },
6387     { "phaddubq",       { XM, EXq } },
6388     { "(bad)",          { XX } },
6389     { "(bad)",          { XX } },
6390     { "phadduwd",       { XM, EXq } },
6391     { "phadduwq",       { XM, EXq } },
6392     /* 58 */
6393     { "(bad)",          { XX } },
6394     { "(bad)",          { XX } },
6395     { "(bad)",          { XX } },
6396     { "phaddudq",       { XM, EXq } },
6397     { "(bad)",          { XX } },
6398     { "(bad)",          { XX } },
6399     { "(bad)",          { XX } },
6400     { "(bad)",          { XX } },
6401     /* 60 */
6402     { "(bad)",          { XX } },
6403     { "phsubbw",        { XM, EXq } },
6404     { "phsubbd",        { XM, EXq } },
6405     { "phsubbq",        { XM, EXq } },
6406     { "(bad)",          { XX } },
6407     { "(bad)",          { XX } },
6408     { "(bad)",          { XX } },
6409     { "(bad)",          { XX } },
6410     /* 68 */
6411     { "(bad)",          { XX } },
6412     { "(bad)",          { XX } },
6413     { "(bad)",          { XX } },
6414     { "(bad)",          { XX } },
6415     { "(bad)",          { XX } },
6416     { "(bad)",          { XX } },
6417     { "(bad)",          { XX } },
6418     { "(bad)",          { XX } },
6419     /* 70 */
6420     { "(bad)",          { XX } },
6421     { "(bad)",          { XX } },
6422     { "(bad)",          { XX } },
6423     { "(bad)",          { XX } },
6424     { "(bad)",          { XX } },
6425     { "(bad)",          { XX } },
6426     { "(bad)",          { XX } },
6427     { "(bad)",          { XX } },
6428     /* 78 */
6429     { "(bad)",          { XX } },
6430     { "(bad)",          { XX } },
6431     { "(bad)",          { XX } },
6432     { "(bad)",          { XX } },
6433     { "(bad)",          { XX } },
6434     { "(bad)",          { XX } },
6435     { "(bad)",          { XX } },
6436     { "(bad)",          { XX } },
6437     /* 80 */
6438     { "(bad)",          { XX } },
6439     { "(bad)",          { XX } },
6440     { "(bad)",          { XX } },
6441     { "(bad)",          { XX } },
6442     { "(bad)",          { XX } },
6443     { "(bad)",          { XX } },
6444     { "(bad)",          { XX } },
6445     { "(bad)",          { XX } },
6446     /* 88 */
6447     { "(bad)",          { XX } },
6448     { "(bad)",          { XX } },
6449     { "(bad)",          { XX } },
6450     { "(bad)",          { XX } },
6451     { "(bad)",          { XX } },
6452     { "(bad)",          { XX } },
6453     { "(bad)",          { XX } },
6454     { "(bad)",          { XX } },
6455     /* 90 */
6456     { "(bad)",          { XX } },
6457     { "(bad)",          { XX } },
6458     { "(bad)",          { XX } },
6459     { "(bad)",          { XX } },
6460     { "(bad)",          { XX } },
6461     { "(bad)",          { XX } },
6462     { "(bad)",          { XX } },
6463     { "(bad)",          { XX } },
6464     /* 98 */
6465     { "(bad)",          { XX } },
6466     { "(bad)",          { XX } },
6467     { "(bad)",          { XX } },
6468     { "(bad)",          { XX } },
6469     { "(bad)",          { XX } },
6470     { "(bad)",          { XX } },
6471     { "(bad)",          { XX } },
6472     { "(bad)",          { XX } },
6473     /* a0 */
6474     { "(bad)",          { XX } },
6475     { "(bad)",          { XX } },
6476     { "(bad)",          { XX } },
6477     { "(bad)",          { XX } },
6478     { "(bad)",          { XX } },
6479     { "(bad)",          { XX } },
6480     { "(bad)",          { XX } },
6481     { "(bad)",          { XX } },
6482     /* a8 */
6483     { "(bad)",          { XX } },
6484     { "(bad)",          { XX } },
6485     { "(bad)",          { XX } },
6486     { "(bad)",          { XX } },
6487     { "(bad)",          { XX } },
6488     { "(bad)",          { XX } },
6489     { "(bad)",          { XX } },
6490     { "(bad)",          { XX } },
6491     /* b0 */
6492     { "(bad)",          { XX } },
6493     { "(bad)",          { XX } },
6494     { "(bad)",          { XX } },
6495     { "(bad)",          { XX } },
6496     { "(bad)",          { XX } },
6497     { "(bad)",          { XX } },
6498     { "(bad)",          { XX } },
6499     { "(bad)",          { XX } },
6500     /* b8 */
6501     { "(bad)",          { XX } },
6502     { "(bad)",          { XX } },
6503     { "(bad)",          { XX } },
6504     { "(bad)",          { XX } },
6505     { "(bad)",          { XX } },
6506     { "(bad)",          { XX } },
6507     { "(bad)",          { XX } },
6508     { "(bad)",          { XX } },
6509     /* c0 */
6510     { "(bad)",          { XX } },
6511     { "(bad)",          { XX } },
6512     { "(bad)",          { XX } },
6513     { "(bad)",          { XX } },
6514     { "(bad)",          { XX } },
6515     { "(bad)",          { XX } },
6516     { "(bad)",          { XX } },
6517     { "(bad)",          { XX } },
6518     /* c8 */
6519     { "(bad)",          { XX } },
6520     { "(bad)",          { XX } },
6521     { "(bad)",          { XX } },
6522     { "(bad)",          { XX } },
6523     { "(bad)",          { XX } },
6524     { "(bad)",          { XX } },
6525     { "(bad)",          { XX } },
6526     { "(bad)",          { XX } },
6527     /* d0 */
6528     { "(bad)",          { XX } },
6529     { "(bad)",          { XX } },
6530     { "(bad)",          { XX } },
6531     { "(bad)",          { XX } },
6532     { "(bad)",          { XX } },
6533     { "(bad)",          { XX } },
6534     { "(bad)",          { XX } },
6535     { "(bad)",          { XX } },
6536     /* d8 */
6537     { "(bad)",          { XX } },
6538     { "(bad)",          { XX } },
6539     { "(bad)",          { XX } },
6540     { "(bad)",          { XX } },
6541     { "(bad)",          { XX } },
6542     { "(bad)",          { XX } },
6543     { "(bad)",          { XX } },
6544     { "(bad)",          { XX } },
6545     /* e0 */
6546     { "(bad)",          { XX } },
6547     { "(bad)",          { XX } },
6548     { "(bad)",          { XX } },
6549     { "(bad)",          { XX } },
6550     { "(bad)",          { XX } },
6551     { "(bad)",          { XX } },
6552     { "(bad)",          { XX } },
6553     { "(bad)",          { XX } },
6554     /* e8 */
6555     { "(bad)",          { XX } },
6556     { "(bad)",          { XX } },
6557     { "(bad)",          { XX } },
6558     { "(bad)",          { XX } },
6559     { "(bad)",          { XX } },
6560     { "(bad)",          { XX } },
6561     { "(bad)",          { XX } },
6562     { "(bad)",          { XX } },
6563     /* f0 */
6564     { "(bad)",          { XX } },
6565     { "(bad)",          { XX } },
6566     { "(bad)",          { XX } },
6567     { "(bad)",          { XX } },
6568     { "(bad)",          { XX } },
6569     { "(bad)",          { XX } },
6570     { "(bad)",          { XX } },
6571     { "(bad)",          { XX } },
6572     /* f8 */
6573     { "(bad)",          { XX } },
6574     { "(bad)",          { XX } },
6575     { "(bad)",          { XX } },
6576     { "(bad)",          { XX } },
6577     { "(bad)",          { XX } },
6578     { "(bad)",          { XX } },
6579     { "(bad)",          { XX } },
6580     { "(bad)",          { XX } },
6581   },
6582   /* THREE_BYTE_0F7B */
6583   {
6584     /* 00 */
6585     { "(bad)",          { XX } },
6586     { "(bad)",          { XX } },
6587     { "(bad)",          { XX } },
6588     { "(bad)",          { XX } },
6589     { "(bad)",          { XX } },
6590     { "(bad)",          { XX } },
6591     { "(bad)",          { XX } },
6592     { "(bad)",          { XX } },
6593     /* 08 */
6594     { "(bad)",          { XX } },
6595     { "(bad)",          { XX } },
6596     { "(bad)",          { XX } },
6597     { "(bad)",          { XX } },
6598     { "(bad)",          { XX } },
6599     { "(bad)",          { XX } },
6600     { "(bad)",          { XX } },
6601     { "(bad)",          { XX } },
6602     /* 10 */
6603     { "(bad)",          { XX } },
6604     { "(bad)",          { XX } },
6605     { "(bad)",          { XX } },
6606     { "(bad)",          { XX } },
6607     { "(bad)",          { XX } },
6608     { "(bad)",          { XX } },
6609     { "(bad)",          { XX } },
6610     { "(bad)",          { XX } },
6611     /* 18 */
6612     { "(bad)",          { XX } },
6613     { "(bad)",          { XX } },
6614     { "(bad)",          { XX } },
6615     { "(bad)",          { XX } },
6616     { "(bad)",          { XX } },
6617     { "(bad)",          { XX } },
6618     { "(bad)",          { XX } },
6619     { "(bad)",          { XX } },
6620     /* 20 */
6621     { "(bad)",          { XX } },
6622     { "(bad)",          { XX } },
6623     { "(bad)",          { XX } },
6624     { "(bad)",          { XX } },
6625     { "(bad)",          { XX } },
6626     { "(bad)",          { XX } },
6627     { "(bad)",          { XX } },
6628     { "(bad)",          { XX } },
6629     /* 28 */
6630     { "(bad)",          { XX } },
6631     { "(bad)",          { XX } },
6632     { "(bad)",          { XX } },
6633     { "(bad)",          { XX } },
6634     { "(bad)",          { XX } },
6635     { "(bad)",          { XX } },
6636     { "(bad)",          { XX } },
6637     { "(bad)",          { XX } },
6638     /* 30 */
6639     { "(bad)",          { XX } },
6640     { "(bad)",          { XX } },
6641     { "(bad)",          { XX } },
6642     { "(bad)",          { XX } },
6643     { "(bad)",          { XX } },
6644     { "(bad)",          { XX } },
6645     { "(bad)",          { XX } },
6646     { "(bad)",          { XX } },
6647     /* 38 */
6648     { "(bad)",          { XX } },
6649     { "(bad)",          { XX } },
6650     { "(bad)",          { XX } },
6651     { "(bad)",          { XX } },
6652     { "(bad)",          { XX } },
6653     { "(bad)",          { XX } },
6654     { "(bad)",          { XX } },
6655     { "(bad)",          { XX } },
6656     /* 40 */
6657     { "protb",          { XM, EXq, Ib } },
6658     { "protw",          { XM, EXq, Ib } },
6659     { "protd",          { XM, EXq, Ib } },
6660     { "protq",          { XM, EXq, Ib } },
6661     { "pshlb",          { XM, EXq, Ib } },
6662     { "pshlw",          { XM, EXq, Ib } },
6663     { "pshld",          { XM, EXq, Ib } },
6664     { "pshlq",          { XM, EXq, Ib } },
6665     /* 48 */
6666     { "pshab",          { XM, EXq, Ib } },
6667     { "pshaw",          { XM, EXq, Ib } },
6668     { "pshad",          { XM, EXq, Ib } },
6669     { "pshaq",          { XM, EXq, Ib } },
6670     { "(bad)",          { XX } },
6671     { "(bad)",          { XX } },
6672     { "(bad)",          { XX } },
6673     { "(bad)",          { XX } },
6674     /* 50 */
6675     { "(bad)",          { XX } },
6676     { "(bad)",          { XX } },
6677     { "(bad)",          { XX } },
6678     { "(bad)",          { XX } },
6679     { "(bad)",          { XX } },
6680     { "(bad)",          { XX } },
6681     { "(bad)",          { XX } },
6682     { "(bad)",          { XX } },
6683     /* 58 */
6684     { "(bad)",          { XX } },
6685     { "(bad)",          { XX } },
6686     { "(bad)",          { XX } },
6687     { "(bad)",          { XX } },
6688     { "(bad)",          { XX } },
6689     { "(bad)",          { XX } },
6690     { "(bad)",          { XX } },
6691     { "(bad)",          { XX } },
6692     /* 60 */
6693     { "(bad)",          { XX } },
6694     { "(bad)",          { XX } },
6695     { "(bad)",          { XX } },
6696     { "(bad)",          { XX } },
6697     { "(bad)",          { XX } },
6698     { "(bad)",          { XX } },
6699     { "(bad)",          { XX } },
6700     { "(bad)",          { XX } },
6701     /* 68 */
6702     { "(bad)",          { XX } },
6703     { "(bad)",          { XX } },
6704     { "(bad)",          { XX } },
6705     { "(bad)",          { XX } },
6706     { "(bad)",          { XX } },
6707     { "(bad)",          { XX } },
6708     { "(bad)",          { XX } },
6709     { "(bad)",          { XX } },
6710     /* 70 */
6711     { "(bad)",          { XX } },
6712     { "(bad)",          { XX } },
6713     { "(bad)",          { XX } },
6714     { "(bad)",          { XX } },
6715     { "(bad)",          { XX } },
6716     { "(bad)",          { XX } },
6717     { "(bad)",          { XX } },
6718     { "(bad)",          { XX } },
6719     /* 78 */
6720     { "(bad)",          { XX } },
6721     { "(bad)",          { XX } },
6722     { "(bad)",          { XX } },
6723     { "(bad)",          { XX } },
6724     { "(bad)",          { XX } },
6725     { "(bad)",          { XX } },
6726     { "(bad)",          { XX } },
6727     { "(bad)",          { XX } },
6728     /* 80 */
6729     { "(bad)",          { XX } },
6730     { "(bad)",          { XX } },
6731     { "(bad)",          { XX } },
6732     { "(bad)",          { XX } },
6733     { "(bad)",          { XX } },
6734     { "(bad)",          { XX } },
6735     { "(bad)",          { XX } },
6736     { "(bad)",          { XX } },
6737     /* 88 */
6738     { "(bad)",          { XX } },
6739     { "(bad)",          { XX } },
6740     { "(bad)",          { XX } },
6741     { "(bad)",          { XX } },
6742     { "(bad)",          { XX } },
6743     { "(bad)",          { XX } },
6744     { "(bad)",          { XX } },
6745     { "(bad)",          { XX } },
6746     /* 90 */
6747     { "(bad)",          { XX } },
6748     { "(bad)",          { XX } },
6749     { "(bad)",          { XX } },
6750     { "(bad)",          { XX } },
6751     { "(bad)",          { XX } },
6752     { "(bad)",          { XX } },
6753     { "(bad)",          { XX } },
6754     { "(bad)",          { XX } },
6755     /* 98 */
6756     { "(bad)",          { XX } },
6757     { "(bad)",          { XX } },
6758     { "(bad)",          { XX } },
6759     { "(bad)",          { XX } },
6760     { "(bad)",          { XX } },
6761     { "(bad)",          { XX } },
6762     { "(bad)",          { XX } },
6763     { "(bad)",          { XX } },
6764     /* a0 */
6765     { "(bad)",          { XX } },
6766     { "(bad)",          { XX } },
6767     { "(bad)",          { XX } },
6768     { "(bad)",          { XX } },
6769     { "(bad)",          { XX } },
6770     { "(bad)",          { XX } },
6771     { "(bad)",          { XX } },
6772     { "(bad)",          { XX } },
6773     /* a8 */
6774     { "(bad)",          { XX } },
6775     { "(bad)",          { XX } },
6776     { "(bad)",          { XX } },
6777     { "(bad)",          { XX } },
6778     { "(bad)",          { XX } },
6779     { "(bad)",          { XX } },
6780     { "(bad)",          { XX } },
6781     { "(bad)",          { XX } },
6782     /* b0 */
6783     { "(bad)",          { XX } },
6784     { "(bad)",          { XX } },
6785     { "(bad)",          { XX } },
6786     { "(bad)",          { XX } },
6787     { "(bad)",          { XX } },
6788     { "(bad)",          { XX } },
6789     { "(bad)",          { XX } },
6790     { "(bad)",          { XX } },
6791     /* b8 */
6792     { "(bad)",          { XX } },
6793     { "(bad)",          { XX } },
6794     { "(bad)",          { XX } },
6795     { "(bad)",          { XX } },
6796     { "(bad)",          { XX } },
6797     { "(bad)",          { XX } },
6798     { "(bad)",          { XX } },
6799     { "(bad)",          { XX } },
6800     /* c0 */
6801     { "(bad)",          { XX } },
6802     { "(bad)",          { XX } },
6803     { "(bad)",          { XX } },
6804     { "(bad)",          { XX } },
6805     { "(bad)",          { XX } },
6806     { "(bad)",          { XX } },
6807     { "(bad)",          { XX } },
6808     { "(bad)",          { XX } },
6809     /* c8 */
6810     { "(bad)",          { XX } },
6811     { "(bad)",          { XX } },
6812     { "(bad)",          { XX } },
6813     { "(bad)",          { XX } },
6814     { "(bad)",          { XX } },
6815     { "(bad)",          { XX } },
6816     { "(bad)",          { XX } },
6817     { "(bad)",          { XX } },
6818     /* d0 */
6819     { "(bad)",          { XX } },
6820     { "(bad)",          { XX } },
6821     { "(bad)",          { XX } },
6822     { "(bad)",          { XX } },
6823     { "(bad)",          { XX } },
6824     { "(bad)",          { XX } },
6825     { "(bad)",          { XX } },
6826     { "(bad)",          { XX } },
6827     /* d8 */
6828     { "(bad)",          { XX } },
6829     { "(bad)",          { XX } },
6830     { "(bad)",          { XX } },
6831     { "(bad)",          { XX } },
6832     { "(bad)",          { XX } },
6833     { "(bad)",          { XX } },
6834     { "(bad)",          { XX } },
6835     { "(bad)",          { XX } },
6836     /* e0 */
6837     { "(bad)",          { XX } },
6838     { "(bad)",          { XX } },
6839     { "(bad)",          { XX } },
6840     { "(bad)",          { XX } },
6841     { "(bad)",          { XX } },
6842     { "(bad)",          { XX } },
6843     { "(bad)",          { XX } },
6844     { "(bad)",          { XX } },
6845     /* e8 */
6846     { "(bad)",          { XX } },
6847     { "(bad)",          { XX } },
6848     { "(bad)",          { XX } },
6849     { "(bad)",          { XX } },
6850     { "(bad)",          { XX } },
6851     { "(bad)",          { XX } },
6852     { "(bad)",          { XX } },
6853     { "(bad)",          { XX } },
6854     /* f0 */
6855     { "(bad)",          { XX } },
6856     { "(bad)",          { XX } },
6857     { "(bad)",          { XX } },
6858     { "(bad)",          { XX } },
6859     { "(bad)",          { XX } },
6860     { "(bad)",          { XX } },
6861     { "(bad)",          { XX } },
6862     { "(bad)",          { XX } },
6863     /* f8 */
6864     { "(bad)",          { XX } },
6865     { "(bad)",          { XX } },
6866     { "(bad)",          { XX } },
6867     { "(bad)",          { XX } },
6868     { "(bad)",          { XX } },
6869     { "(bad)",          { XX } },
6870     { "(bad)",          { XX } },
6871     { "(bad)",          { XX } },
6872   },
6873 };
6874
6875 static const struct dis386 vex_table[][256] = {
6876   /* VEX_0F */
6877   {
6878     /* 00 */
6879     { "(bad)",          { XX } },
6880     { "(bad)",          { XX } },
6881     { "(bad)",          { XX } },
6882     { "(bad)",          { XX } },
6883     { "(bad)",          { XX } },
6884     { "(bad)",          { XX } },
6885     { "(bad)",          { XX } },
6886     { "(bad)",          { XX } },
6887     /* 08 */
6888     { "(bad)",          { XX } },
6889     { "(bad)",          { XX } },
6890     { "(bad)",          { XX } },
6891     { "(bad)",          { XX } },
6892     { "(bad)",          { XX } },
6893     { "(bad)",          { XX } },
6894     { "(bad)",          { XX } },
6895     { "(bad)",          { XX } },
6896     /* 10 */
6897     { PREFIX_TABLE (PREFIX_VEX_10) },
6898     { PREFIX_TABLE (PREFIX_VEX_11) },
6899     { PREFIX_TABLE (PREFIX_VEX_12) },
6900     { MOD_TABLE (MOD_VEX_13) },
6901     { "vunpcklpX",      { XM, Vex, EXx } },
6902     { "vunpckhpX",      { XM, Vex, EXx } },
6903     { PREFIX_TABLE (PREFIX_VEX_16) },
6904     { MOD_TABLE (MOD_VEX_17) },
6905     /* 18 */
6906     { "(bad)",          { XX } },
6907     { "(bad)",          { XX } },
6908     { "(bad)",          { XX } },
6909     { "(bad)",          { XX } },
6910     { "(bad)",          { XX } },
6911     { "(bad)",          { XX } },
6912     { "(bad)",          { XX } },
6913     { "(bad)",          { XX } },
6914     /* 20 */
6915     { "(bad)",          { XX } },
6916     { "(bad)",          { XX } },
6917     { "(bad)",          { XX } },
6918     { "(bad)",          { XX } },
6919     { "(bad)",          { XX } },
6920     { "(bad)",          { XX } },
6921     { "(bad)",          { XX } },
6922     { "(bad)",          { XX } },
6923     /* 28 */
6924     { "vmovapX",        { XM, EXx } },
6925     { "vmovapX",        { EXx, XM } },
6926     { PREFIX_TABLE (PREFIX_VEX_2A) },
6927     { MOD_TABLE (MOD_VEX_2B) },
6928     { PREFIX_TABLE (PREFIX_VEX_2C) },
6929     { PREFIX_TABLE (PREFIX_VEX_2D) },
6930     { PREFIX_TABLE (PREFIX_VEX_2E) },
6931     { PREFIX_TABLE (PREFIX_VEX_2F) },
6932     /* 30 */
6933     { "(bad)",          { XX } },
6934     { "(bad)",          { XX } },
6935     { "(bad)",          { XX } },
6936     { "(bad)",          { XX } },
6937     { "(bad)",          { XX } },
6938     { "(bad)",          { XX } },
6939     { "(bad)",          { XX } },
6940     { "(bad)",          { XX } },
6941     /* 38 */
6942     { "(bad)",          { XX } },
6943     { "(bad)",          { XX } },
6944     { "(bad)",          { XX } },
6945     { "(bad)",          { XX } },
6946     { "(bad)",          { XX } },
6947     { "(bad)",          { XX } },
6948     { "(bad)",          { XX } },
6949     { "(bad)",          { XX } },
6950     /* 40 */
6951     { "(bad)",          { XX } },
6952     { "(bad)",          { XX } },
6953     { "(bad)",          { XX } },
6954     { "(bad)",          { XX } },
6955     { "(bad)",          { XX } },
6956     { "(bad)",          { XX } },
6957     { "(bad)",          { XX } },
6958     { "(bad)",          { XX } },
6959     /* 48 */
6960     { "(bad)",          { XX } },
6961     { "(bad)",          { XX } },
6962     { "(bad)",          { XX } },
6963     { "(bad)",          { XX } },
6964     { "(bad)",          { XX } },
6965     { "(bad)",          { XX } },
6966     { "(bad)",          { XX } },
6967     { "(bad)",          { XX } },
6968     /* 50 */
6969     { MOD_TABLE (MOD_VEX_51) },
6970     { PREFIX_TABLE (PREFIX_VEX_51) },
6971     { PREFIX_TABLE (PREFIX_VEX_52) },
6972     { PREFIX_TABLE (PREFIX_VEX_53) },
6973     { "vandpX",         { XM, Vex, EXx } },
6974     { "vandnpX",        { XM, Vex, EXx } },
6975     { "vorpX",          { XM, Vex, EXx } },
6976     { "vxorpX",         { XM, Vex, EXx } },
6977     /* 58 */
6978     { PREFIX_TABLE (PREFIX_VEX_58) },
6979     { PREFIX_TABLE (PREFIX_VEX_59) },
6980     { PREFIX_TABLE (PREFIX_VEX_5A) },
6981     { PREFIX_TABLE (PREFIX_VEX_5B) },
6982     { PREFIX_TABLE (PREFIX_VEX_5C) },
6983     { PREFIX_TABLE (PREFIX_VEX_5D) },
6984     { PREFIX_TABLE (PREFIX_VEX_5E) },
6985     { PREFIX_TABLE (PREFIX_VEX_5F) },
6986     /* 60 */
6987     { PREFIX_TABLE (PREFIX_VEX_60) },
6988     { PREFIX_TABLE (PREFIX_VEX_61) },
6989     { PREFIX_TABLE (PREFIX_VEX_62) },
6990     { PREFIX_TABLE (PREFIX_VEX_63) },
6991     { PREFIX_TABLE (PREFIX_VEX_64) },
6992     { PREFIX_TABLE (PREFIX_VEX_65) },
6993     { PREFIX_TABLE (PREFIX_VEX_66) },
6994     { PREFIX_TABLE (PREFIX_VEX_67) },
6995     /* 68 */
6996     { PREFIX_TABLE (PREFIX_VEX_68) },
6997     { PREFIX_TABLE (PREFIX_VEX_69) },
6998     { PREFIX_TABLE (PREFIX_VEX_6A) },
6999     { PREFIX_TABLE (PREFIX_VEX_6B) },
7000     { PREFIX_TABLE (PREFIX_VEX_6C) },
7001     { PREFIX_TABLE (PREFIX_VEX_6D) },
7002     { PREFIX_TABLE (PREFIX_VEX_6E) },
7003     { PREFIX_TABLE (PREFIX_VEX_6F) },
7004     /* 70 */
7005     { PREFIX_TABLE (PREFIX_VEX_70) },
7006     { REG_TABLE (REG_VEX_71) },
7007     { REG_TABLE (REG_VEX_72) },
7008     { REG_TABLE (REG_VEX_73) },
7009     { PREFIX_TABLE (PREFIX_VEX_74) },
7010     { PREFIX_TABLE (PREFIX_VEX_75) },
7011     { PREFIX_TABLE (PREFIX_VEX_76) },
7012     { PREFIX_TABLE (PREFIX_VEX_77) },
7013     /* 78 */
7014     { "(bad)",          { XX } },
7015     { "(bad)",          { XX } },
7016     { "(bad)",          { XX } },
7017     { "(bad)",          { XX } },
7018     { PREFIX_TABLE (PREFIX_VEX_7C) },
7019     { PREFIX_TABLE (PREFIX_VEX_7D) },
7020     { PREFIX_TABLE (PREFIX_VEX_7E) },
7021     { PREFIX_TABLE (PREFIX_VEX_7F) },
7022     /* 80 */
7023     { "(bad)",          { XX } },
7024     { "(bad)",          { XX } },
7025     { "(bad)",          { XX } },
7026     { "(bad)",          { XX } },
7027     { "(bad)",          { XX } },
7028     { "(bad)",          { XX } },
7029     { "(bad)",          { XX } },
7030     { "(bad)",          { XX } },
7031     /* 88 */
7032     { "(bad)",          { XX } },
7033     { "(bad)",          { XX } },
7034     { "(bad)",          { XX } },
7035     { "(bad)",          { XX } },
7036     { "(bad)",          { XX } },
7037     { "(bad)",          { XX } },
7038     { "(bad)",          { XX } },
7039     { "(bad)",          { XX } },
7040     /* 90 */
7041     { "(bad)",          { XX } },
7042     { "(bad)",          { XX } },
7043     { "(bad)",          { XX } },
7044     { "(bad)",          { XX } },
7045     { "(bad)",          { XX } },
7046     { "(bad)",          { XX } },
7047     { "(bad)",          { XX } },
7048     { "(bad)",          { XX } },
7049     /* 98 */
7050     { "(bad)",          { XX } },
7051     { "(bad)",          { XX } },
7052     { "(bad)",          { XX } },
7053     { "(bad)",          { XX } },
7054     { "(bad)",          { XX } },
7055     { "(bad)",          { XX } },
7056     { "(bad)",          { XX } },
7057     { "(bad)",          { XX } },
7058     /* a0 */
7059     { "(bad)",          { XX } },
7060     { "(bad)",          { XX } },
7061     { "(bad)",          { XX } },
7062     { "(bad)",          { XX } },
7063     { "(bad)",          { XX } },
7064     { "(bad)",          { XX } },
7065     { "(bad)",          { XX } },
7066     { "(bad)",          { XX } },
7067     /* a8 */
7068     { "(bad)",          { XX } },
7069     { "(bad)",          { XX } },
7070     { "(bad)",          { XX } },
7071     { "(bad)",          { XX } },
7072     { "(bad)",          { XX } },
7073     { "(bad)",          { XX } },
7074     { REG_TABLE (REG_VEX_AE) },
7075     { "(bad)",          { XX } },
7076     /* b0 */
7077     { "(bad)",          { XX } },
7078     { "(bad)",          { XX } },
7079     { "(bad)",          { XX } },
7080     { "(bad)",          { XX } },
7081     { "(bad)",          { XX } },
7082     { "(bad)",          { XX } },
7083     { "(bad)",          { XX } },
7084     { "(bad)",          { XX } },
7085     /* b8 */
7086     { "(bad)",          { XX } },
7087     { "(bad)",          { XX } },
7088     { "(bad)",          { XX } },
7089     { "(bad)",          { XX } },
7090     { "(bad)",          { XX } },
7091     { "(bad)",          { XX } },
7092     { "(bad)",          { XX } },
7093     { "(bad)",          { XX } },
7094     /* c0 */
7095     { "(bad)",          { XX } },
7096     { "(bad)",          { XX } },
7097     { PREFIX_TABLE (PREFIX_VEX_C2) },
7098     { "(bad)",          { XX } },
7099     { PREFIX_TABLE (PREFIX_VEX_C4) },
7100     { PREFIX_TABLE (PREFIX_VEX_C5) },
7101     { "vshufpX",        { XM, Vex, EXx, Ib } },
7102     { "(bad)",          { XX } },
7103     /* c8 */
7104     { "(bad)",          { XX } },
7105     { "(bad)",          { XX } },
7106     { "(bad)",          { XX } },
7107     { "(bad)",          { XX } },
7108     { "(bad)",          { XX } },
7109     { "(bad)",          { XX } },
7110     { "(bad)",          { XX } },
7111     { "(bad)",          { XX } },
7112     /* d0 */
7113     { PREFIX_TABLE (PREFIX_VEX_D0) },
7114     { PREFIX_TABLE (PREFIX_VEX_D1) },
7115     { PREFIX_TABLE (PREFIX_VEX_D2) },
7116     { PREFIX_TABLE (PREFIX_VEX_D3) },
7117     { PREFIX_TABLE (PREFIX_VEX_D4) },
7118     { PREFIX_TABLE (PREFIX_VEX_D5) },
7119     { PREFIX_TABLE (PREFIX_VEX_D6) },
7120     { PREFIX_TABLE (PREFIX_VEX_D7) },
7121     /* d8 */
7122     { PREFIX_TABLE (PREFIX_VEX_D8) },
7123     { PREFIX_TABLE (PREFIX_VEX_D9) },
7124     { PREFIX_TABLE (PREFIX_VEX_DA) },
7125     { PREFIX_TABLE (PREFIX_VEX_DB) },
7126     { PREFIX_TABLE (PREFIX_VEX_DC) },
7127     { PREFIX_TABLE (PREFIX_VEX_DD) },
7128     { PREFIX_TABLE (PREFIX_VEX_DE) },
7129     { PREFIX_TABLE (PREFIX_VEX_DF) },
7130     /* e0 */
7131     { PREFIX_TABLE (PREFIX_VEX_E0) },
7132     { PREFIX_TABLE (PREFIX_VEX_E1) },
7133     { PREFIX_TABLE (PREFIX_VEX_E2) },
7134     { PREFIX_TABLE (PREFIX_VEX_E3) },
7135     { PREFIX_TABLE (PREFIX_VEX_E4) },
7136     { PREFIX_TABLE (PREFIX_VEX_E5) },
7137     { PREFIX_TABLE (PREFIX_VEX_E6) },
7138     { PREFIX_TABLE (PREFIX_VEX_E7) },
7139     /* e8 */
7140     { PREFIX_TABLE (PREFIX_VEX_E8) },
7141     { PREFIX_TABLE (PREFIX_VEX_E9) },
7142     { PREFIX_TABLE (PREFIX_VEX_EA) },
7143     { PREFIX_TABLE (PREFIX_VEX_EB) },
7144     { PREFIX_TABLE (PREFIX_VEX_EC) },
7145     { PREFIX_TABLE (PREFIX_VEX_ED) },
7146     { PREFIX_TABLE (PREFIX_VEX_EE) },
7147     { PREFIX_TABLE (PREFIX_VEX_EF) },
7148     /* f0 */
7149     { PREFIX_TABLE (PREFIX_VEX_F0) },
7150     { PREFIX_TABLE (PREFIX_VEX_F1) },
7151     { PREFIX_TABLE (PREFIX_VEX_F2) },
7152     { PREFIX_TABLE (PREFIX_VEX_F3) },
7153     { PREFIX_TABLE (PREFIX_VEX_F4) },
7154     { PREFIX_TABLE (PREFIX_VEX_F5) },
7155     { PREFIX_TABLE (PREFIX_VEX_F6) },
7156     { PREFIX_TABLE (PREFIX_VEX_F7) },
7157     /* f8 */
7158     { PREFIX_TABLE (PREFIX_VEX_F8) },
7159     { PREFIX_TABLE (PREFIX_VEX_F9) },
7160     { PREFIX_TABLE (PREFIX_VEX_FA) },
7161     { PREFIX_TABLE (PREFIX_VEX_FB) },
7162     { PREFIX_TABLE (PREFIX_VEX_FC) },
7163     { PREFIX_TABLE (PREFIX_VEX_FD) },
7164     { PREFIX_TABLE (PREFIX_VEX_FE) },
7165     { "(bad)",          { XX } },
7166   },
7167   /* VEX_0F38 */
7168   {
7169     /* 00 */
7170     { PREFIX_TABLE (PREFIX_VEX_3800) },
7171     { PREFIX_TABLE (PREFIX_VEX_3801) },
7172     { PREFIX_TABLE (PREFIX_VEX_3802) },
7173     { PREFIX_TABLE (PREFIX_VEX_3803) },
7174     { PREFIX_TABLE (PREFIX_VEX_3804) },
7175     { PREFIX_TABLE (PREFIX_VEX_3805) },
7176     { PREFIX_TABLE (PREFIX_VEX_3806) },
7177     { PREFIX_TABLE (PREFIX_VEX_3807) },
7178     /* 08 */
7179     { PREFIX_TABLE (PREFIX_VEX_3808) },
7180     { PREFIX_TABLE (PREFIX_VEX_3809) },
7181     { PREFIX_TABLE (PREFIX_VEX_380A) },
7182     { PREFIX_TABLE (PREFIX_VEX_380B) },
7183     { PREFIX_TABLE (PREFIX_VEX_380C) },
7184     { PREFIX_TABLE (PREFIX_VEX_380D) },
7185     { PREFIX_TABLE (PREFIX_VEX_380E) },
7186     { PREFIX_TABLE (PREFIX_VEX_380F) },
7187     /* 10 */
7188     { "(bad)",          { XX } },
7189     { "(bad)",          { XX } },
7190     { "(bad)",          { XX } },
7191     { "(bad)",          { XX } },
7192     { "(bad)",          { XX } },
7193     { "(bad)",          { XX } },
7194     { "(bad)",          { XX } },
7195     { PREFIX_TABLE (PREFIX_VEX_3817) },
7196     /* 18 */
7197     { PREFIX_TABLE (PREFIX_VEX_3818) },
7198     { PREFIX_TABLE (PREFIX_VEX_3819) },
7199     { PREFIX_TABLE (PREFIX_VEX_381A) },
7200     { "(bad)",          { XX } },
7201     { PREFIX_TABLE (PREFIX_VEX_381C) },
7202     { PREFIX_TABLE (PREFIX_VEX_381D) },
7203     { PREFIX_TABLE (PREFIX_VEX_381E) },
7204     { "(bad)",          { XX } },
7205     /* 20 */
7206     { PREFIX_TABLE (PREFIX_VEX_3820) },
7207     { PREFIX_TABLE (PREFIX_VEX_3821) },
7208     { PREFIX_TABLE (PREFIX_VEX_3822) },
7209     { PREFIX_TABLE (PREFIX_VEX_3823) },
7210     { PREFIX_TABLE (PREFIX_VEX_3824) },
7211     { PREFIX_TABLE (PREFIX_VEX_3825) },
7212     { "(bad)",          { XX } },
7213     { "(bad)",          { XX } },
7214     /* 28 */
7215     { PREFIX_TABLE (PREFIX_VEX_3828) },
7216     { PREFIX_TABLE (PREFIX_VEX_3829) },
7217     { PREFIX_TABLE (PREFIX_VEX_382A) },
7218     { PREFIX_TABLE (PREFIX_VEX_382B) },
7219     { PREFIX_TABLE (PREFIX_VEX_382C) },
7220     { PREFIX_TABLE (PREFIX_VEX_382D) },
7221     { PREFIX_TABLE (PREFIX_VEX_382E) },
7222     { PREFIX_TABLE (PREFIX_VEX_382F) },
7223     /* 30 */
7224     { PREFIX_TABLE (PREFIX_VEX_3830) },
7225     { PREFIX_TABLE (PREFIX_VEX_3831) },
7226     { PREFIX_TABLE (PREFIX_VEX_3832) },
7227     { PREFIX_TABLE (PREFIX_VEX_3833) },
7228     { PREFIX_TABLE (PREFIX_VEX_3834) },
7229     { PREFIX_TABLE (PREFIX_VEX_3835) },
7230     { "(bad)",          { XX } },
7231     { PREFIX_TABLE (PREFIX_VEX_3837) },
7232     /* 38 */
7233     { PREFIX_TABLE (PREFIX_VEX_3838) },
7234     { PREFIX_TABLE (PREFIX_VEX_3839) },
7235     { PREFIX_TABLE (PREFIX_VEX_383A) },
7236     { PREFIX_TABLE (PREFIX_VEX_383B) },
7237     { PREFIX_TABLE (PREFIX_VEX_383C) },
7238     { PREFIX_TABLE (PREFIX_VEX_383D) },
7239     { PREFIX_TABLE (PREFIX_VEX_383E) },
7240     { PREFIX_TABLE (PREFIX_VEX_383F) },
7241     /* 40 */
7242     { PREFIX_TABLE (PREFIX_VEX_3840) },
7243     { PREFIX_TABLE (PREFIX_VEX_3841) },
7244     { "(bad)",          { XX } },
7245     { "(bad)",          { XX } },
7246     { "(bad)",          { XX } },
7247     { "(bad)",          { XX } },
7248     { "(bad)",          { XX } },
7249     { "(bad)",          { XX } },
7250     /* 48 */
7251     { "(bad)",          { XX } },
7252     { "(bad)",          { XX } },
7253     { "(bad)",          { XX } },
7254     { "(bad)",          { XX } },
7255     { "(bad)",          { XX } },
7256     { "(bad)",          { XX } },
7257     { "(bad)",          { XX } },
7258     { "(bad)",          { XX } },
7259     /* 50 */
7260     { "(bad)",          { XX } },
7261     { "(bad)",          { XX } },
7262     { "(bad)",          { XX } },
7263     { "(bad)",          { XX } },
7264     { "(bad)",          { XX } },
7265     { "(bad)",          { XX } },
7266     { "(bad)",          { XX } },
7267     { "(bad)",          { XX } },
7268     /* 58 */
7269     { "(bad)",          { XX } },
7270     { "(bad)",          { XX } },
7271     { "(bad)",          { XX } },
7272     { "(bad)",          { XX } },
7273     { "(bad)",          { XX } },
7274     { "(bad)",          { XX } },
7275     { "(bad)",          { XX } },
7276     { "(bad)",          { XX } },
7277     /* 60 */
7278     { "(bad)",          { XX } },
7279     { "(bad)",          { XX } },
7280     { "(bad)",          { XX } },
7281     { "(bad)",          { XX } },
7282     { "(bad)",          { XX } },
7283     { "(bad)",          { XX } },
7284     { "(bad)",          { XX } },
7285     { "(bad)",          { XX } },
7286     /* 68 */
7287     { "(bad)",          { XX } },
7288     { "(bad)",          { XX } },
7289     { "(bad)",          { XX } },
7290     { "(bad)",          { XX } },
7291     { "(bad)",          { XX } },
7292     { "(bad)",          { XX } },
7293     { "(bad)",          { XX } },
7294     { "(bad)",          { XX } },
7295     /* 70 */
7296     { "(bad)",          { XX } },
7297     { "(bad)",          { XX } },
7298     { "(bad)",          { XX } },
7299     { "(bad)",          { XX } },
7300     { "(bad)",          { XX } },
7301     { "(bad)",          { XX } },
7302     { "(bad)",          { XX } },
7303     { "(bad)",          { XX } },
7304     /* 78 */
7305     { "(bad)",          { XX } },
7306     { "(bad)",          { XX } },
7307     { "(bad)",          { XX } },
7308     { "(bad)",          { XX } },
7309     { "(bad)",          { XX } },
7310     { "(bad)",          { XX } },
7311     { "(bad)",          { XX } },
7312     { "(bad)",          { XX } },
7313     /* 80 */
7314     { "(bad)",          { XX } },
7315     { "(bad)",          { XX } },
7316     { "(bad)",          { XX } },
7317     { "(bad)",          { XX } },
7318     { "(bad)",          { XX } },
7319     { "(bad)",          { XX } },
7320     { "(bad)",          { XX } },
7321     { "(bad)",          { XX } },
7322     /* 88 */
7323     { "(bad)",          { XX } },
7324     { "(bad)",          { XX } },
7325     { "(bad)",          { XX } },
7326     { "(bad)",          { XX } },
7327     { "(bad)",          { XX } },
7328     { "(bad)",          { XX } },
7329     { "(bad)",          { XX } },
7330     { "(bad)",          { XX } },
7331     /* 90 */
7332     { "(bad)",          { XX } },
7333     { "(bad)",          { XX } },
7334     { "(bad)",          { XX } },
7335     { "(bad)",          { XX } },
7336     { "(bad)",          { XX } },
7337     { "(bad)",          { XX } },
7338     { "(bad)",          { XX } },
7339     { "(bad)",          { XX } },
7340     /* 98 */
7341     { "(bad)",          { XX } },
7342     { "(bad)",          { XX } },
7343     { "(bad)",          { XX } },
7344     { "(bad)",          { XX } },
7345     { "(bad)",          { XX } },
7346     { "(bad)",          { XX } },
7347     { "(bad)",          { XX } },
7348     { "(bad)",          { XX } },
7349     /* a0 */
7350     { "(bad)",          { XX } },
7351     { "(bad)",          { XX } },
7352     { "(bad)",          { XX } },
7353     { "(bad)",          { XX } },
7354     { "(bad)",          { XX } },
7355     { "(bad)",          { XX } },
7356     { "(bad)",          { XX } },
7357     { "(bad)",          { XX } },
7358     /* a8 */
7359     { "(bad)",          { XX } },
7360     { "(bad)",          { XX } },
7361     { "(bad)",          { XX } },
7362     { "(bad)",          { XX } },
7363     { "(bad)",          { XX } },
7364     { "(bad)",          { XX } },
7365     { "(bad)",          { XX } },
7366     { "(bad)",          { XX } },
7367     /* b0 */
7368     { "(bad)",          { XX } },
7369     { "(bad)",          { XX } },
7370     { "(bad)",          { XX } },
7371     { "(bad)",          { XX } },
7372     { "(bad)",          { XX } },
7373     { "(bad)",          { XX } },
7374     { "(bad)",          { XX } },
7375     { "(bad)",          { XX } },
7376     /* b8 */
7377     { "(bad)",          { XX } },
7378     { "(bad)",          { XX } },
7379     { "(bad)",          { XX } },
7380     { "(bad)",          { XX } },
7381     { "(bad)",          { XX } },
7382     { "(bad)",          { XX } },
7383     { "(bad)",          { XX } },
7384     { "(bad)",          { XX } },
7385     /* c0 */
7386     { "(bad)",          { XX } },
7387     { "(bad)",          { XX } },
7388     { "(bad)",          { XX } },
7389     { "(bad)",          { XX } },
7390     { "(bad)",          { XX } },
7391     { "(bad)",          { XX } },
7392     { "(bad)",          { XX } },
7393     { "(bad)",          { XX } },
7394     /* c8 */
7395     { "(bad)",          { XX } },
7396     { "(bad)",          { XX } },
7397     { "(bad)",          { XX } },
7398     { "(bad)",          { XX } },
7399     { "(bad)",          { XX } },
7400     { "(bad)",          { XX } },
7401     { "(bad)",          { XX } },
7402     { "(bad)",          { XX } },
7403     /* d0 */
7404     { "(bad)",          { XX } },
7405     { "(bad)",          { XX } },
7406     { "(bad)",          { XX } },
7407     { "(bad)",          { XX } },
7408     { "(bad)",          { XX } },
7409     { "(bad)",          { XX } },
7410     { "(bad)",          { XX } },
7411     { "(bad)",          { XX } },
7412     /* d8 */
7413     { "(bad)",          { XX } },
7414     { "(bad)",          { XX } },
7415     { "(bad)",          { XX } },
7416     { "(bad)",          { XX } },
7417     { "(bad)",          { XX } },
7418     { "(bad)",          { XX } },
7419     { "(bad)",          { XX } },
7420     { "(bad)",          { XX } },
7421     /* e0 */
7422     { "(bad)",          { XX } },
7423     { "(bad)",          { XX } },
7424     { "(bad)",          { XX } },
7425     { "(bad)",          { XX } },
7426     { "(bad)",          { XX } },
7427     { "(bad)",          { XX } },
7428     { "(bad)",          { XX } },
7429     { "(bad)",          { XX } },
7430     /* e8 */
7431     { "(bad)",          { XX } },
7432     { "(bad)",          { XX } },
7433     { "(bad)",          { XX } },
7434     { "(bad)",          { XX } },
7435     { "(bad)",          { XX } },
7436     { "(bad)",          { XX } },
7437     { "(bad)",          { XX } },
7438     { "(bad)",          { XX } },
7439     /* f0 */
7440     { "(bad)",          { XX } },
7441     { "(bad)",          { XX } },
7442     { "(bad)",          { XX } },
7443     { "(bad)",          { XX } },
7444     { "(bad)",          { XX } },
7445     { "(bad)",          { XX } },
7446     { "(bad)",          { XX } },
7447     { "(bad)",          { XX } },
7448     /* f8 */
7449     { "(bad)",          { XX } },
7450     { "(bad)",          { XX } },
7451     { "(bad)",          { XX } },
7452     { "(bad)",          { XX } },
7453     { "(bad)",          { XX } },
7454     { "(bad)",          { XX } },
7455     { "(bad)",          { XX } },
7456     { "(bad)",          { XX } },
7457   },
7458   /* VEX_0F3A */
7459   {
7460     /* 00 */
7461     { "(bad)",          { XX } },
7462     { "(bad)",          { XX } },
7463     { "(bad)",          { XX } },
7464     { "(bad)",          { XX } },
7465     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7466     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7467     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7468     { "(bad)",          { XX } },
7469     /* 08 */
7470     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7471     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7472     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7473     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7474     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7475     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7476     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7477     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7478     /* 10 */
7479     { "(bad)",          { XX } },
7480     { "(bad)",          { XX } },
7481     { "(bad)",          { XX } },
7482     { "(bad)",          { XX } },
7483     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7484     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7485     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7486     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7487     /* 18 */
7488     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7489     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7490     { "(bad)",          { XX } },
7491     { "(bad)",          { XX } },
7492     { "(bad)",          { XX } },
7493     { "(bad)",          { XX } },
7494     { "(bad)",          { XX } },
7495     { "(bad)",          { XX } },
7496     /* 20 */
7497     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7498     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7499     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7500     { "(bad)",          { XX } },
7501     { "(bad)",          { XX } },
7502     { "(bad)",          { XX } },
7503     { "(bad)",          { XX } },
7504     { "(bad)",          { XX } },
7505     /* 28 */
7506     { "(bad)",          { XX } },
7507     { "(bad)",          { XX } },
7508     { "(bad)",          { XX } },
7509     { "(bad)",          { XX } },
7510     { "(bad)",          { XX } },
7511     { "(bad)",          { XX } },
7512     { "(bad)",          { XX } },
7513     { "(bad)",          { XX } },
7514     /* 30 */
7515     { "(bad)",          { XX } },
7516     { "(bad)",          { XX } },
7517     { "(bad)",          { XX } },
7518     { "(bad)",          { XX } },
7519     { "(bad)",          { XX } },
7520     { "(bad)",          { XX } },
7521     { "(bad)",          { XX } },
7522     { "(bad)",          { XX } },
7523     /* 38 */
7524     { "(bad)",          { XX } },
7525     { "(bad)",          { XX } },
7526     { "(bad)",          { XX } },
7527     { "(bad)",          { XX } },
7528     { "(bad)",          { XX } },
7529     { "(bad)",          { XX } },
7530     { "(bad)",          { XX } },
7531     { "(bad)",          { XX } },
7532     /* 40 */
7533     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7534     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7535     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7536     { "(bad)",          { XX } },
7537     { "(bad)",          { XX } },
7538     { "(bad)",          { XX } },
7539     { "(bad)",          { XX } },
7540     { "(bad)",          { XX } },
7541     /* 48 */
7542     { PREFIX_TABLE (PREFIX_VEX_3A48) },
7543     { PREFIX_TABLE (PREFIX_VEX_3A49) },
7544     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7545     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7546     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7547     { "(bad)",          { XX } },
7548     { "(bad)",          { XX } },
7549     { "(bad)",          { XX } },
7550     /* 50 */
7551     { "(bad)",          { XX } },
7552     { "(bad)",          { XX } },
7553     { "(bad)",          { XX } },
7554     { "(bad)",          { XX } },
7555     { "(bad)",          { XX } },
7556     { "(bad)",          { XX } },
7557     { "(bad)",          { XX } },
7558     { "(bad)",          { XX } },
7559     /* 58 */
7560     { "(bad)",          { XX } },
7561     { "(bad)",          { XX } },
7562     { "(bad)",          { XX } },
7563     { "(bad)",          { XX } },
7564     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7565     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7566     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7567     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7568     /* 60 */
7569     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7570     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7571     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7572     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7573     { "(bad)",          { XX } },
7574     { "(bad)",          { XX } },
7575     { "(bad)",          { XX } },
7576     { "(bad)",          { XX } },
7577     /* 68 */
7578     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7579     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7580     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7581     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7582     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7583     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7584     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7585     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7586     /* 70 */
7587     { "(bad)",          { XX } },
7588     { "(bad)",          { XX } },
7589     { "(bad)",          { XX } },
7590     { "(bad)",          { XX } },
7591     { "(bad)",          { XX } },
7592     { "(bad)",          { XX } },
7593     { "(bad)",          { XX } },
7594     { "(bad)",          { XX } },
7595     /* 78 */
7596     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7597     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7598     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7599     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7600     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7601     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7602     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7603     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7604     /* 80 */
7605     { "(bad)",          { XX } },
7606     { "(bad)",          { XX } },
7607     { "(bad)",          { XX } },
7608     { "(bad)",          { XX } },
7609     { "(bad)",          { XX } },
7610     { "(bad)",          { XX } },
7611     { "(bad)",          { XX } },
7612     { "(bad)",          { XX } },
7613     /* 88 */
7614     { "(bad)",          { XX } },
7615     { "(bad)",          { XX } },
7616     { "(bad)",          { XX } },
7617     { "(bad)",          { XX } },
7618     { "(bad)",          { XX } },
7619     { "(bad)",          { XX } },
7620     { "(bad)",          { XX } },
7621     { "(bad)",          { XX } },
7622     /* 90 */
7623     { "(bad)",          { XX } },
7624     { "(bad)",          { XX } },
7625     { "(bad)",          { XX } },
7626     { "(bad)",          { XX } },
7627     { "(bad)",          { XX } },
7628     { "(bad)",          { XX } },
7629     { "(bad)",          { XX } },
7630     { "(bad)",          { XX } },
7631     /* 98 */
7632     { "(bad)",          { XX } },
7633     { "(bad)",          { XX } },
7634     { "(bad)",          { XX } },
7635     { "(bad)",          { XX } },
7636     { "(bad)",          { XX } },
7637     { "(bad)",          { XX } },
7638     { "(bad)",          { XX } },
7639     { "(bad)",          { XX } },
7640     /* a0 */
7641     { "(bad)",          { XX } },
7642     { "(bad)",          { XX } },
7643     { "(bad)",          { XX } },
7644     { "(bad)",          { XX } },
7645     { "(bad)",          { XX } },
7646     { "(bad)",          { XX } },
7647     { "(bad)",          { XX } },
7648     { "(bad)",          { XX } },
7649     /* a8 */
7650     { "(bad)",          { XX } },
7651     { "(bad)",          { XX } },
7652     { "(bad)",          { XX } },
7653     { "(bad)",          { XX } },
7654     { "(bad)",          { XX } },
7655     { "(bad)",          { XX } },
7656     { "(bad)",          { XX } },
7657     { "(bad)",          { XX } },
7658     /* b0 */
7659     { "(bad)",          { XX } },
7660     { "(bad)",          { XX } },
7661     { "(bad)",          { XX } },
7662     { "(bad)",          { XX } },
7663     { "(bad)",          { XX } },
7664     { "(bad)",          { XX } },
7665     { "(bad)",          { XX } },
7666     { "(bad)",          { XX } },
7667     /* b8 */
7668     { "(bad)",          { XX } },
7669     { "(bad)",          { XX } },
7670     { "(bad)",          { XX } },
7671     { "(bad)",          { XX } },
7672     { "(bad)",          { XX } },
7673     { "(bad)",          { XX } },
7674     { "(bad)",          { XX } },
7675     { "(bad)",          { XX } },
7676     /* c0 */
7677     { "(bad)",          { XX } },
7678     { "(bad)",          { XX } },
7679     { "(bad)",          { XX } },
7680     { "(bad)",          { XX } },
7681     { "(bad)",          { XX } },
7682     { "(bad)",          { XX } },
7683     { "(bad)",          { XX } },
7684     { "(bad)",          { XX } },
7685     /* c8 */
7686     { "(bad)",          { XX } },
7687     { "(bad)",          { XX } },
7688     { "(bad)",          { XX } },
7689     { "(bad)",          { XX } },
7690     { "(bad)",          { XX } },
7691     { "(bad)",          { XX } },
7692     { "(bad)",          { XX } },
7693     { "(bad)",          { XX } },
7694     /* d0 */
7695     { "(bad)",          { XX } },
7696     { "(bad)",          { XX } },
7697     { "(bad)",          { XX } },
7698     { "(bad)",          { XX } },
7699     { "(bad)",          { XX } },
7700     { "(bad)",          { XX } },
7701     { "(bad)",          { XX } },
7702     { "(bad)",          { XX } },
7703     /* d8 */
7704     { "(bad)",          { XX } },
7705     { "(bad)",          { XX } },
7706     { "(bad)",          { XX } },
7707     { "(bad)",          { XX } },
7708     { "(bad)",          { XX } },
7709     { "(bad)",          { XX } },
7710     { "(bad)",          { XX } },
7711     { "(bad)",          { XX } },
7712     /* e0 */
7713     { "(bad)",          { XX } },
7714     { "(bad)",          { XX } },
7715     { "(bad)",          { XX } },
7716     { "(bad)",          { XX } },
7717     { "(bad)",          { XX } },
7718     { "(bad)",          { XX } },
7719     { "(bad)",          { XX } },
7720     { "(bad)",          { XX } },
7721     /* e8 */
7722     { "(bad)",          { XX } },
7723     { "(bad)",          { XX } },
7724     { "(bad)",          { XX } },
7725     { "(bad)",          { XX } },
7726     { "(bad)",          { XX } },
7727     { "(bad)",          { XX } },
7728     { "(bad)",          { XX } },
7729     { "(bad)",          { XX } },
7730     /* f0 */
7731     { "(bad)",          { XX } },
7732     { "(bad)",          { XX } },
7733     { "(bad)",          { XX } },
7734     { "(bad)",          { XX } },
7735     { "(bad)",          { XX } },
7736     { "(bad)",          { XX } },
7737     { "(bad)",          { XX } },
7738     { "(bad)",          { XX } },
7739     /* f8 */
7740     { "(bad)",          { XX } },
7741     { "(bad)",          { XX } },
7742     { "(bad)",          { XX } },
7743     { "(bad)",          { XX } },
7744     { "(bad)",          { XX } },
7745     { "(bad)",          { XX } },
7746     { "(bad)",          { XX } },
7747     { "(bad)",          { XX } },
7748   },
7749 };
7750
7751 static const struct dis386 vex_len_table[][2] = {
7752   /* VEX_LEN_10_P_1 */
7753   {
7754     { "vmovss",         { XMVex, Vex128, EXd } },
7755     { "(bad)",          { XX } },
7756   },
7757
7758   /* VEX_LEN_10_P_3 */
7759   {
7760     { "vmovsd",         { XMVex, Vex128, EXq } },
7761     { "(bad)",          { XX } },
7762   },
7763
7764   /* VEX_LEN_11_P_1 */
7765   {
7766     { "vmovss",         { EXdVex, Vex128, XM } },
7767     { "(bad)",          { XX } },
7768   },
7769
7770   /* VEX_LEN_11_P_3 */
7771   {
7772     { "vmovsd",         { EXqVex, Vex128, XM } },
7773     { "(bad)",          { XX } },
7774   },
7775
7776   /* VEX_LEN_12_P_0_M_0 */
7777   {
7778     { "vmovlps",        { XM, Vex128, EXq } },
7779     { "(bad)",          { XX } },
7780   },
7781
7782   /* VEX_LEN_12_P_0_M_1 */
7783   {
7784     { "vmovhlps",       { XM, Vex128, EXq } },
7785     { "(bad)",          { XX } },
7786   },
7787
7788   /* VEX_LEN_12_P_2 */
7789   {
7790     { "vmovlpd",        { XM, Vex128, EXq } },
7791     { "(bad)",          { XX } },
7792   },
7793
7794   /* VEX_LEN_13_M_0 */
7795   {
7796     { "vmovlpX",        { EXq, XM } },
7797     { "(bad)",          { XX } },
7798   },
7799
7800   /* VEX_LEN_16_P_0_M_0 */
7801   {
7802     { "vmovhps",        { XM, Vex128, EXq } },
7803     { "(bad)",          { XX } },
7804   },
7805
7806   /* VEX_LEN_16_P_0_M_1 */
7807   {
7808     { "vmovlhps",       { XM, Vex128, EXq } },
7809     { "(bad)",          { XX } },
7810   },
7811
7812   /* VEX_LEN_16_P_2 */
7813   {
7814     { "vmovhpd",        { XM, Vex128, EXq } },
7815     { "(bad)",          { XX } },
7816   },
7817
7818   /* VEX_LEN_17_M_0 */
7819   {
7820     { "vmovhpX",        { EXq, XM } },
7821     { "(bad)",          { XX } },
7822   },
7823
7824   /* VEX_LEN_2A_P_1 */
7825   {
7826     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
7827     { "(bad)",          { XX } },
7828   },
7829
7830   /* VEX_LEN_2A_P_3 */
7831   {
7832     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
7833     { "(bad)",          { XX } },
7834   },
7835
7836   /* VEX_LEN_2B_M_0 */
7837   {
7838     { "vmovntpX",       { Mx, XM } },
7839     { "(bad)",          { XX } },
7840   },
7841
7842   /* VEX_LEN_2C_P_1 */
7843   {
7844     { "vcvttss2siY",    { Gv, EXd } },
7845     { "(bad)",          { XX } },
7846   },
7847
7848   /* VEX_LEN_2C_P_3 */
7849   {
7850     { "vcvttsd2siY",    { Gv, EXq } },
7851     { "(bad)",          { XX } },
7852   },
7853
7854   /* VEX_LEN_2D_P_1 */
7855   {
7856     { "vcvtss2siY",     { Gv, EXd } },
7857     { "(bad)",          { XX } },
7858   },
7859
7860   /* VEX_LEN_2D_P_3 */
7861   {
7862     { "vcvtsd2siY",     { Gv, EXq } },
7863     { "(bad)",          { XX } },
7864   },
7865
7866   /* VEX_LEN_2E_P_0 */
7867   {
7868     { "vucomiss",       { XM, EXd } },
7869     { "(bad)",          { XX } },
7870   },
7871
7872   /* VEX_LEN_2E_P_2 */
7873   {
7874     { "vucomisd",       { XM, EXq } },
7875     { "(bad)",          { XX } },
7876   },
7877
7878   /* VEX_LEN_2F_P_0 */
7879   {
7880     { "vcomiss",        { XM, EXd } },
7881     { "(bad)",          { XX } },
7882   },
7883
7884   /* VEX_LEN_2F_P_2 */
7885   {
7886     { "vcomisd",        { XM, EXq } },
7887     { "(bad)",          { XX } },
7888   },
7889
7890   /* VEX_LEN_51_P_1 */
7891   {
7892     { "vsqrtss",        { XM, Vex128, EXd } },
7893     { "(bad)",          { XX } },
7894   },
7895
7896   /* VEX_LEN_51_P_3 */
7897   {
7898     { "vsqrtsd",        { XM, Vex128, EXq } },
7899     { "(bad)",          { XX } },
7900   },
7901
7902   /* VEX_LEN_52_P_1 */
7903   {
7904     { "vrsqrtss",       { XM, Vex128, EXd } },
7905     { "(bad)",          { XX } },
7906   },
7907
7908   /* VEX_LEN_53_P_1 */
7909   {
7910     { "vrcpss",         { XM, Vex128, EXd } },
7911     { "(bad)",          { XX } },
7912   },
7913
7914   /* VEX_LEN_58_P_1 */
7915   {
7916     { "vaddss",         { XM, Vex128, EXd } },
7917     { "(bad)",          { XX } },
7918   },
7919
7920   /* VEX_LEN_58_P_3 */
7921   {
7922     { "vaddsd",         { XM, Vex128, EXq } },
7923     { "(bad)",          { XX } },
7924   },
7925
7926   /* VEX_LEN_59_P_1 */
7927   {
7928     { "vmulss",         { XM, Vex128, EXd } },
7929     { "(bad)",          { XX } },
7930   },
7931
7932   /* VEX_LEN_59_P_3 */
7933   {
7934     { "vmulsd",         { XM, Vex128, EXq } },
7935     { "(bad)",          { XX } },
7936   },
7937
7938   /* VEX_LEN_5A_P_1 */
7939   {
7940     { "vcvtss2sd",      { XM, Vex128, EXd } },
7941     { "(bad)",          { XX } },
7942   },
7943
7944   /* VEX_LEN_5A_P_3 */
7945   {
7946     { "vcvtsd2ss",      { XM, Vex128, EXq } },
7947     { "(bad)",          { XX } },
7948   },
7949
7950   /* VEX_LEN_5C_P_1 */
7951   {
7952     { "vsubss",         { XM, Vex128, EXd } },
7953     { "(bad)",          { XX } },
7954   },
7955
7956   /* VEX_LEN_5C_P_3 */
7957   {
7958     { "vsubsd",         { XM, Vex128, EXq } },
7959     { "(bad)",          { XX } },
7960   },
7961
7962   /* VEX_LEN_5D_P_1 */
7963   {
7964     { "vminss",         { XM, Vex128, EXd } },
7965     { "(bad)",          { XX } },
7966   },
7967
7968   /* VEX_LEN_5D_P_3 */
7969   {
7970     { "vminsd",         { XM, Vex128, EXq } },
7971     { "(bad)",          { XX } },
7972   },
7973
7974   /* VEX_LEN_5E_P_1 */
7975   {
7976     { "vdivss",         { XM, Vex128, EXd } },
7977     { "(bad)",          { XX } },
7978   },
7979
7980   /* VEX_LEN_5E_P_3 */
7981   {
7982     { "vdivsd",         { XM, Vex128, EXq } },
7983     { "(bad)",          { XX } },
7984   },
7985
7986   /* VEX_LEN_5F_P_1 */
7987   {
7988     { "vmaxss",         { XM, Vex128, EXd } },
7989     { "(bad)",          { XX } },
7990   },
7991
7992   /* VEX_LEN_5F_P_3 */
7993   {
7994     { "vmaxsd",         { XM, Vex128, EXq } },
7995     { "(bad)",          { XX } },
7996   },
7997
7998   /* VEX_LEN_60_P_2 */
7999   {
8000     { "vpunpcklbw",     { XM, Vex128, EXx } },
8001     { "(bad)",          { XX } },
8002   },
8003
8004   /* VEX_LEN_61_P_2 */
8005   {
8006     { "vpunpcklwd",     { XM, Vex128, EXx } },
8007     { "(bad)",          { XX } },
8008   },
8009
8010   /* VEX_LEN_62_P_2 */
8011   {
8012     { "vpunpckldq",     { XM, Vex128, EXx } },
8013     { "(bad)",          { XX } },
8014   },
8015
8016   /* VEX_LEN_63_P_2 */
8017   {
8018     { "vpacksswb",      { XM, Vex128, EXx } },
8019     { "(bad)",          { XX } },
8020   },
8021
8022   /* VEX_LEN_64_P_2 */
8023   {
8024     { "vpcmpgtb",       { XM, Vex128, EXx } },
8025     { "(bad)",          { XX } },
8026   },
8027
8028   /* VEX_LEN_65_P_2 */
8029   {
8030     { "vpcmpgtw",       { XM, Vex128, EXx } },
8031     { "(bad)",          { XX } },
8032   },
8033
8034   /* VEX_LEN_66_P_2 */
8035   {
8036     { "vpcmpgtd",       { XM, Vex128, EXx } },
8037     { "(bad)",          { XX } },
8038   },
8039
8040   /* VEX_LEN_67_P_2 */
8041   {
8042     { "vpackuswb",      { XM, Vex128, EXx } },
8043     { "(bad)",          { XX } },
8044   },
8045
8046   /* VEX_LEN_68_P_2 */
8047   {
8048     { "vpunpckhbw",     { XM, Vex128, EXx } },
8049     { "(bad)",          { XX } },
8050   },
8051
8052   /* VEX_LEN_69_P_2 */
8053   {
8054     { "vpunpckhwd",     { XM, Vex128, EXx } },
8055     { "(bad)",          { XX } },
8056   },
8057
8058   /* VEX_LEN_6A_P_2 */
8059   {
8060     { "vpunpckhdq",     { XM, Vex128, EXx } },
8061     { "(bad)",          { XX } },
8062   },
8063
8064   /* VEX_LEN_6B_P_2 */
8065   {
8066     { "vpackssdw",      { XM, Vex128, EXx } },
8067     { "(bad)",          { XX } },
8068   },
8069
8070   /* VEX_LEN_6C_P_2 */
8071   {
8072     { "vpunpcklqdq",    { XM, Vex128, EXx } },
8073     { "(bad)",          { XX } },
8074   },
8075
8076   /* VEX_LEN_6D_P_2 */
8077   {
8078     { "vpunpckhqdq",    { XM, Vex128, EXx } },
8079     { "(bad)",          { XX } },
8080   },
8081
8082   /* VEX_LEN_6E_P_2 */
8083   {
8084     { "vmovK",          { XM, Edq } },
8085     { "(bad)",          { XX } },
8086   },
8087
8088   /* VEX_LEN_70_P_1 */
8089   {
8090     { "vpshufhw",       { XM, EXx, Ib } },
8091     { "(bad)",          { XX } },
8092   },
8093
8094   /* VEX_LEN_70_P_2 */
8095   {
8096     { "vpshufd",        { XM, EXx, Ib } },
8097     { "(bad)",          { XX } },
8098   },
8099
8100   /* VEX_LEN_70_P_3 */
8101   {
8102     { "vpshuflw",       { XM, EXx, Ib } },
8103     { "(bad)",          { XX } },
8104   },
8105
8106   /* VEX_LEN_71_R_2_P_2 */
8107   {
8108     { "vpsrlw",         { Vex128, XS, Ib } },
8109     { "(bad)",          { XX } },
8110   },
8111
8112   /* VEX_LEN_71_R_4_P_2 */
8113   {
8114     { "vpsraw",         { Vex128, XS, Ib } },
8115     { "(bad)",          { XX } },
8116   },
8117
8118   /* VEX_LEN_71_R_6_P_2 */
8119   {
8120     { "vpsllw",         { Vex128, XS, Ib } },
8121     { "(bad)",          { XX } },
8122   },
8123
8124   /* VEX_LEN_72_R_2_P_2 */
8125   {
8126     { "vpsrld",         { Vex128, XS, Ib } },
8127     { "(bad)",          { XX } },
8128   },
8129
8130   /* VEX_LEN_72_R_4_P_2 */
8131   {
8132     { "vpsrad",         { Vex128, XS, Ib } },
8133     { "(bad)",          { XX } },
8134   },
8135
8136   /* VEX_LEN_72_R_6_P_2 */
8137   {
8138     { "vpslld",         { Vex128, XS, Ib } },
8139     { "(bad)",          { XX } },
8140   },
8141
8142   /* VEX_LEN_73_R_2_P_2 */
8143   {
8144     { "vpsrlq",         { Vex128, XS, Ib } },
8145     { "(bad)",          { XX } },
8146   },
8147
8148   /* VEX_LEN_73_R_3_P_2 */
8149   {
8150     { "vpsrldq",        { Vex128, XS, Ib } },
8151     { "(bad)",          { XX } },
8152   },
8153
8154   /* VEX_LEN_73_R_6_P_2 */
8155   {
8156     { "vpsllq",         { Vex128, XS, Ib } },
8157     { "(bad)",          { XX } },
8158   },
8159
8160   /* VEX_LEN_73_R_7_P_2 */
8161   {
8162     { "vpslldq",        { Vex128, XS, Ib } },
8163     { "(bad)",          { XX } },
8164   },
8165
8166   /* VEX_LEN_74_P_2 */
8167   {
8168     { "vpcmpeqb",       { XM, Vex128, EXx } },
8169     { "(bad)",          { XX } },
8170   },
8171
8172   /* VEX_LEN_75_P_2 */
8173   {
8174     { "vpcmpeqw",       { XM, Vex128, EXx } },
8175     { "(bad)",          { XX } },
8176   },
8177
8178   /* VEX_LEN_76_P_2 */
8179   {
8180     { "vpcmpeqd",       { XM, Vex128, EXx } },
8181     { "(bad)",          { XX } },
8182   },
8183
8184   /* VEX_LEN_7E_P_1 */
8185   {
8186     { "vmovq",          { XM, EXq } },
8187     { "(bad)",          { XX } },
8188   },
8189
8190   /* VEX_LEN_7E_P_2 */
8191   {
8192     { "vmovK",          { Edq, XM } },
8193     { "(bad)",          { XX } },
8194   },
8195
8196   /* VEX_LEN_AE_R_2_M0 */
8197   {
8198     { "vldmxcsr",       { Md } },
8199     { "(bad)",          { XX } },
8200   },
8201
8202   /* VEX_LEN_AE_R_3_M0 */
8203   {
8204     { "vstmxcsr",       { Md } },
8205     { "(bad)",          { XX } },
8206   },
8207
8208   /* VEX_LEN_C2_P_1 */
8209   {
8210     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
8211     { "(bad)",          { XX } },
8212   },
8213
8214   /* VEX_LEN_C2_P_3 */
8215   {
8216     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
8217     { "(bad)",          { XX } },
8218   },
8219
8220   /* VEX_LEN_C4_P_2 */
8221   {
8222     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
8223     { "(bad)",          { XX } },
8224   },
8225
8226   /* VEX_LEN_C5_P_2 */
8227   {
8228     { "vpextrw",        { Gdq, XS, Ib } },
8229     { "(bad)",          { XX } },
8230   },
8231
8232   /* VEX_LEN_D1_P_2 */
8233   {
8234     { "vpsrlw",         { XM, Vex128, EXx } },
8235     { "(bad)",          { XX } },
8236   },
8237
8238   /* VEX_LEN_D2_P_2 */
8239   {
8240     { "vpsrld",         { XM, Vex128, EXx } },
8241     { "(bad)",          { XX } },
8242   },
8243
8244   /* VEX_LEN_D3_P_2 */
8245   {
8246     { "vpsrlq",         { XM, Vex128, EXx } },
8247     { "(bad)",          { XX } },
8248   },
8249
8250   /* VEX_LEN_D4_P_2 */
8251   {
8252     { "vpaddq",         { XM, Vex128, EXx } },
8253     { "(bad)",          { XX } },
8254   },
8255
8256   /* VEX_LEN_D5_P_2 */
8257   {
8258     { "vpmullw",        { XM, Vex128, EXx } },
8259     { "(bad)",          { XX } },
8260   },
8261
8262   /* VEX_LEN_D6_P_2 */
8263   {
8264     { "vmovq",          { EXq, XM } },
8265     { "(bad)",          { XX } },
8266   },
8267
8268   /* VEX_LEN_D7_P_2_M_1 */
8269   {
8270     { "vpmovmskb",      { Gdq, XS } },
8271     { "(bad)",          { XX } },
8272   },
8273
8274   /* VEX_LEN_D8_P_2 */
8275   {
8276     { "vpsubusb",       { XM, Vex128, EXx } },
8277     { "(bad)",          { XX } },
8278   },
8279
8280   /* VEX_LEN_D9_P_2 */
8281   {
8282     { "vpsubusw",       { XM, Vex128, EXx } },
8283     { "(bad)",          { XX } },
8284   },
8285
8286   /* VEX_LEN_DA_P_2 */
8287   {
8288     { "vpminub",        { XM, Vex128, EXx } },
8289     { "(bad)",          { XX } },
8290   },
8291
8292   /* VEX_LEN_DB_P_2 */
8293   {
8294     { "vpand",          { XM, Vex128, EXx } },
8295     { "(bad)",          { XX } },
8296   },
8297
8298   /* VEX_LEN_DC_P_2 */
8299   {
8300     { "vpaddusb",       { XM, Vex128, EXx } },
8301     { "(bad)",          { XX } },
8302   },
8303
8304   /* VEX_LEN_DD_P_2 */
8305   {
8306     { "vpaddusw",       { XM, Vex128, EXx } },
8307     { "(bad)",          { XX } },
8308   },
8309
8310   /* VEX_LEN_DE_P_2 */
8311   {
8312     { "vpmaxub",        { XM, Vex128, EXx } },
8313     { "(bad)",          { XX } },
8314   },
8315
8316   /* VEX_LEN_DF_P_2 */
8317   {
8318     { "vpandn",         { XM, Vex128, EXx } },
8319     { "(bad)",          { XX } },
8320   },
8321
8322   /* VEX_LEN_E0_P_2 */
8323   {
8324     { "vpavgb",         { XM, Vex128, EXx } },
8325     { "(bad)",          { XX } },
8326   },
8327
8328   /* VEX_LEN_E1_P_2 */
8329   {
8330     { "vpsraw",         { XM, Vex128, EXx } },
8331     { "(bad)",          { XX } },
8332   },
8333
8334   /* VEX_LEN_E2_P_2 */
8335   {
8336     { "vpsrad",         { XM, Vex128, EXx } },
8337     { "(bad)",          { XX } },
8338   },
8339
8340   /* VEX_LEN_E3_P_2 */
8341   {
8342     { "vpavgw",         { XM, Vex128, EXx } },
8343     { "(bad)",          { XX } },
8344   },
8345
8346   /* VEX_LEN_E4_P_2 */
8347   {
8348     { "vpmulhuw",       { XM, Vex128, EXx } },
8349     { "(bad)",          { XX } },
8350   },
8351
8352   /* VEX_LEN_E5_P_2 */
8353   {
8354     { "vpmulhw",        { XM, Vex128, EXx } },
8355     { "(bad)",          { XX } },
8356   },
8357
8358   /* VEX_LEN_E7_P_2_M_0 */
8359   {
8360     { "vmovntdq",       { Mx, XM } },
8361     { "(bad)",          { XX } },
8362   },
8363
8364   /* VEX_LEN_E8_P_2 */
8365   {
8366     { "vpsubsb",        { XM, Vex128, EXx } },
8367     { "(bad)",          { XX } },
8368   },
8369
8370   /* VEX_LEN_E9_P_2 */
8371   {
8372     { "vpsubsw",        { XM, Vex128, EXx } },
8373     { "(bad)",          { XX } },
8374   },
8375
8376   /* VEX_LEN_EA_P_2 */
8377   {
8378     { "vpminsw",        { XM, Vex128, EXx } },
8379     { "(bad)",          { XX } },
8380   },
8381
8382   /* VEX_LEN_EB_P_2 */
8383   {
8384     { "vpor",           { XM, Vex128, EXx } },
8385     { "(bad)",          { XX } },
8386   },
8387
8388   /* VEX_LEN_EC_P_2 */
8389   {
8390     { "vpaddsb",        { XM, Vex128, EXx } },
8391     { "(bad)",          { XX } },
8392   },
8393
8394   /* VEX_LEN_ED_P_2 */
8395   {
8396     { "vpaddsw",        { XM, Vex128, EXx } },
8397     { "(bad)",          { XX } },
8398   },
8399
8400   /* VEX_LEN_EE_P_2 */
8401   {
8402     { "vpmaxsw",        { XM, Vex128, EXx } },
8403     { "(bad)",          { XX } },
8404   },
8405
8406   /* VEX_LEN_EF_P_2 */
8407   {
8408     { "vpxor",          { XM, Vex128, EXx } },
8409     { "(bad)",          { XX } },
8410   },
8411
8412   /* VEX_LEN_F1_P_2 */
8413   {
8414     { "vpsllw",         { XM, Vex128, EXx } },
8415     { "(bad)",          { XX } },
8416   },
8417
8418   /* VEX_LEN_F2_P_2 */
8419   {
8420     { "vpslld",         { XM, Vex128, EXx } },
8421     { "(bad)",          { XX } },
8422   },
8423
8424   /* VEX_LEN_F3_P_2 */
8425   {
8426     { "vpsllq",         { XM, Vex128, EXx } },
8427     { "(bad)",          { XX } },
8428   },
8429
8430   /* VEX_LEN_F4_P_2 */
8431   {
8432     { "vpmuludq",       { XM, Vex128, EXx } },
8433     { "(bad)",          { XX } },
8434   },
8435
8436   /* VEX_LEN_F5_P_2 */
8437   {
8438     { "vpmaddwd",       { XM, Vex128, EXx } },
8439     { "(bad)",          { XX } },
8440   },
8441
8442   /* VEX_LEN_F6_P_2 */
8443   {
8444     { "vpsadbw",        { XM, Vex128, EXx } },
8445     { "(bad)",          { XX } },
8446   },
8447
8448   /* VEX_LEN_F7_P_2 */
8449   {
8450     { "vmaskmovdqu",    { XM, XS } },
8451     { "(bad)",          { XX } },
8452   },
8453
8454   /* VEX_LEN_F8_P_2 */
8455   {
8456     { "vpsubb",         { XM, Vex128, EXx } },
8457     { "(bad)",          { XX } },
8458   },
8459
8460   /* VEX_LEN_F9_P_2 */
8461   {
8462     { "vpsubw",         { XM, Vex128, EXx } },
8463     { "(bad)",          { XX } },
8464   },
8465
8466   /* VEX_LEN_FA_P_2 */
8467   {
8468     { "vpsubd",         { XM, Vex128, EXx } },
8469     { "(bad)",          { XX } },
8470   },
8471
8472   /* VEX_LEN_FB_P_2 */
8473   {
8474     { "vpsubq",         { XM, Vex128, EXx } },
8475     { "(bad)",          { XX } },
8476   },
8477
8478   /* VEX_LEN_FC_P_2 */
8479   {
8480     { "vpaddb",         { XM, Vex128, EXx } },
8481     { "(bad)",          { XX } },
8482   },
8483
8484   /* VEX_LEN_FD_P_2 */
8485   {
8486     { "vpaddw",         { XM, Vex128, EXx } },
8487     { "(bad)",          { XX } },
8488   },
8489
8490   /* VEX_LEN_FE_P_2 */
8491   {
8492     { "vpaddd",         { XM, Vex128, EXx } },
8493     { "(bad)",          { XX } },
8494   },
8495
8496   /* VEX_LEN_3800_P_2 */
8497   {
8498     { "vpshufb",        { XM, Vex128, EXx } },
8499     { "(bad)",          { XX } },
8500   },
8501
8502   /* VEX_LEN_3801_P_2 */
8503   {
8504     { "vphaddw",        { XM, Vex128, EXx } },
8505     { "(bad)",          { XX } },
8506   },
8507
8508   /* VEX_LEN_3802_P_2 */
8509   {
8510     { "vphaddd",        { XM, Vex128, EXx } },
8511     { "(bad)",          { XX } },
8512   },
8513
8514   /* VEX_LEN_3803_P_2 */
8515   {
8516     { "vphaddsw",       { XM, Vex128, EXx } },
8517     { "(bad)",          { XX } },
8518   },
8519
8520   /* VEX_LEN_3804_P_2 */
8521   {
8522     { "vpmaddubsw",     { XM, Vex128, EXx } },
8523     { "(bad)",          { XX } },
8524   },
8525
8526   /* VEX_LEN_3805_P_2 */
8527   {
8528     { "vphsubw",        { XM, Vex128, EXx } },
8529     { "(bad)",          { XX } },
8530   },
8531
8532   /* VEX_LEN_3806_P_2 */
8533   {
8534     { "vphsubd",        { XM, Vex128, EXx } },
8535     { "(bad)",          { XX } },
8536   },
8537
8538   /* VEX_LEN_3807_P_2 */
8539   {
8540     { "vphsubsw",       { XM, Vex128, EXx } },
8541     { "(bad)",          { XX } },
8542   },
8543
8544   /* VEX_LEN_3808_P_2 */
8545   {
8546     { "vpsignb",        { XM, Vex128, EXx } },
8547     { "(bad)",          { XX } },
8548   },
8549
8550   /* VEX_LEN_3809_P_2 */
8551   {
8552     { "vpsignw",        { XM, Vex128, EXx } },
8553     { "(bad)",          { XX } },
8554   },
8555
8556   /* VEX_LEN_380A_P_2 */
8557   {
8558     { "vpsignd",        { XM, Vex128, EXx } },
8559     { "(bad)",          { XX } },
8560   },
8561
8562   /* VEX_LEN_380B_P_2 */
8563   {
8564     { "vpmulhrsw",      { XM, Vex128, EXx } },
8565     { "(bad)",          { XX } },
8566   },
8567
8568   /* VEX_LEN_3819_P_2_M_0 */
8569   {
8570     { "(bad)",          { XX } },
8571     { "vbroadcastsd",   { XM, Mq } },
8572   },
8573
8574   /* VEX_LEN_381A_P_2_M_0 */
8575   {
8576     { "(bad)",          { XX } },
8577     { "vbroadcastf128", { XM, Mxmm } },
8578   },
8579
8580   /* VEX_LEN_381C_P_2 */
8581   {
8582     { "vpabsb",         { XM, EXx } },
8583     { "(bad)",          { XX } },
8584   },
8585
8586   /* VEX_LEN_381D_P_2 */
8587   {
8588     { "vpabsw",         { XM, EXx } },
8589     { "(bad)",          { XX } },
8590   },
8591
8592   /* VEX_LEN_381E_P_2 */
8593   {
8594     { "vpabsd",         { XM, EXx } },
8595     { "(bad)",          { XX } },
8596   },
8597
8598   /* VEX_LEN_3820_P_2 */
8599   {
8600     { "vpmovsxbw",      { XM, EXq } },
8601     { "(bad)",          { XX } },
8602   },
8603
8604   /* VEX_LEN_3821_P_2 */
8605   {
8606     { "vpmovsxbd",      { XM, EXd } },
8607     { "(bad)",          { XX } },
8608   },
8609
8610   /* VEX_LEN_3822_P_2 */
8611   {
8612     { "vpmovsxbq",      { XM, EXw } },
8613     { "(bad)",          { XX } },
8614   },
8615
8616   /* VEX_LEN_3823_P_2 */
8617   {
8618     { "vpmovsxwd",      { XM, EXq } },
8619     { "(bad)",          { XX } },
8620   },
8621
8622   /* VEX_LEN_3824_P_2 */
8623   {
8624     { "vpmovsxwq",      { XM, EXd } },
8625     { "(bad)",          { XX } },
8626   },
8627
8628   /* VEX_LEN_3825_P_2 */
8629   {
8630     { "vpmovsxdq",      { XM, EXq } },
8631     { "(bad)",          { XX } },
8632   },
8633
8634   /* VEX_LEN_3828_P_2 */
8635   {
8636     { "vpmuldq",        { XM, Vex128, EXx } },
8637     { "(bad)",          { XX } },
8638   },
8639
8640   /* VEX_LEN_3829_P_2 */
8641   {
8642     { "vpcmpeqq",       { XM, Vex128, EXx } },
8643     { "(bad)",          { XX } },
8644   },
8645
8646   /* VEX_LEN_382A_P_2_M_0 */
8647   {
8648     { "vmovntdqa",      { XM, Mx } },
8649     { "(bad)",          { XX } },
8650   },
8651
8652   /* VEX_LEN_382B_P_2 */
8653   {
8654     { "vpackusdw",      { XM, Vex128, EXx } },
8655     { "(bad)",          { XX } },
8656   },
8657
8658   /* VEX_LEN_3830_P_2 */
8659   {
8660     { "vpmovzxbw",      { XM, EXq } },
8661     { "(bad)",          { XX } },
8662   },
8663
8664   /* VEX_LEN_3831_P_2 */
8665   {
8666     { "vpmovzxbd",      { XM, EXd } },
8667     { "(bad)",          { XX } },
8668   },
8669
8670   /* VEX_LEN_3832_P_2 */
8671   {
8672     { "vpmovzxbq",      { XM, EXw } },
8673     { "(bad)",          { XX } },
8674   },
8675
8676   /* VEX_LEN_3833_P_2 */
8677   {
8678     { "vpmovzxwd",      { XM, EXq } },
8679     { "(bad)",          { XX } },
8680   },
8681
8682   /* VEX_LEN_3834_P_2 */
8683   {
8684     { "vpmovzxwq",      { XM, EXd } },
8685     { "(bad)",          { XX } },
8686   },
8687
8688   /* VEX_LEN_3835_P_2 */
8689   {
8690     { "vpmovzxdq",      { XM, EXq } },
8691     { "(bad)",          { XX } },
8692   },
8693
8694   /* VEX_LEN_3837_P_2 */
8695   {
8696     { "vpcmpgtq",       { XM, Vex128, EXx } },
8697     { "(bad)",          { XX } },
8698   },
8699
8700   /* VEX_LEN_3838_P_2 */
8701   {
8702     { "vpminsb",        { XM, Vex128, EXx } },
8703     { "(bad)",          { XX } },
8704   },
8705
8706   /* VEX_LEN_3839_P_2 */
8707   {
8708     { "vpminsd",        { XM, Vex128, EXx } },
8709     { "(bad)",          { XX } },
8710   },
8711
8712   /* VEX_LEN_383A_P_2 */
8713   {
8714     { "vpminuw",        { XM, Vex128, EXx } },
8715     { "(bad)",          { XX } },
8716   },
8717
8718   /* VEX_LEN_383B_P_2 */
8719   {
8720     { "vpminud",        { XM, Vex128, EXx } },
8721     { "(bad)",          { XX } },
8722   },
8723
8724   /* VEX_LEN_383C_P_2 */
8725   {
8726     { "vpmaxsb",        { XM, Vex128, EXx } },
8727     { "(bad)",          { XX } },
8728   },
8729
8730   /* VEX_LEN_383D_P_2 */
8731   {
8732     { "vpmaxsd",        { XM, Vex128, EXx } },
8733     { "(bad)",          { XX } },
8734   },
8735
8736   /* VEX_LEN_383E_P_2 */
8737   {
8738     { "vpmaxuw",        { XM, Vex128, EXx } },
8739     { "(bad)",          { XX } },
8740   },
8741
8742   /* VEX_LEN_383F_P_2 */
8743   {
8744     { "vpmaxud",        { XM, Vex128, EXx } },
8745     { "(bad)",          { XX } },
8746   },
8747
8748   /* VEX_LEN_3840_P_2 */
8749   {
8750     { "vpmulld",        { XM, Vex128, EXx } },
8751     { "(bad)",          { XX } },
8752   },
8753
8754   /* VEX_LEN_3841_P_2 */
8755   {
8756     { "vphminposuw",    { XM, EXx } },
8757     { "(bad)",          { XX } },
8758   },
8759
8760   /* VEX_LEN_3A06_P_2 */
8761   {
8762     { "(bad)",          { XX } },
8763     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
8764   },
8765
8766   /* VEX_LEN_3A0A_P_2 */
8767   {
8768     { "vroundss",       { XM, Vex128, EXd, Ib } },
8769     { "(bad)",          { XX } },
8770   },
8771
8772   /* VEX_LEN_3A0B_P_2 */
8773   {
8774     { "vroundsd",       { XM, Vex128, EXq, Ib } },
8775     { "(bad)",          { XX } },
8776   },
8777
8778   /* VEX_LEN_3A0E_P_2 */
8779   {
8780     { "vpblendw",       { XM, Vex128, EXx, Ib } },
8781     { "(bad)",          { XX } },
8782   },
8783
8784   /* VEX_LEN_3A0F_P_2 */
8785   {
8786     { "vpalignr",       { XM, Vex128, EXx, Ib } },
8787     { "(bad)",          { XX } },
8788   },
8789
8790   /* VEX_LEN_3A14_P_2 */
8791   {
8792     { "vpextrb",        { Edqb, XM, Ib } },
8793     { "(bad)",          { XX } },
8794   },
8795
8796   /* VEX_LEN_3A15_P_2 */
8797   {
8798     { "vpextrw",        { Edqw, XM, Ib } },
8799     { "(bad)",          { XX } },
8800   },
8801
8802   /* VEX_LEN_3A16_P_2  */
8803   {
8804     { "vpextrK",        { Edq, XM, Ib } },
8805     { "(bad)",          { XX } },
8806   },
8807
8808   /* VEX_LEN_3A17_P_2 */
8809   {
8810     { "vextractps",     { Edqd, XM, Ib } },
8811     { "(bad)",          { XX } },
8812   },
8813
8814   /* VEX_LEN_3A18_P_2 */
8815   {
8816     { "(bad)",          { XX } },
8817     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
8818   },
8819
8820   /* VEX_LEN_3A19_P_2 */
8821   {
8822     { "(bad)",          { XX } },
8823     { "vextractf128",   { EXxmm, XM, Ib } },
8824   },
8825
8826   /* VEX_LEN_3A20_P_2 */
8827   {
8828     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
8829     { "(bad)",          { XX } },
8830   },
8831
8832   /* VEX_LEN_3A21_P_2 */
8833   {
8834     { "vinsertps",      { XM, Vex128, EXd, Ib } },
8835     { "(bad)",          { XX } },
8836   },
8837
8838   /* VEX_LEN_3A22_P_2 */
8839   {
8840     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8841     { "(bad)",          { XX } },
8842   },
8843
8844   /* VEX_LEN_3A41_P_2 */
8845   {
8846     { "vdppd",          { XM, Vex128, EXx, Ib } },
8847     { "(bad)",          { XX } },
8848   },
8849
8850   /* VEX_LEN_3A42_P_2 */
8851   {
8852     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
8853     { "(bad)",          { XX } },
8854   },
8855
8856   /* VEX_LEN_3A4C_P_2 */
8857   {
8858     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
8859     { "(bad)",          { XX } },
8860   },
8861
8862   /* VEX_LEN_3A60_P_2 */
8863   {
8864     { "vpcmpestrm",     { XM, EXx, Ib } },
8865     { "(bad)",          { XX } },
8866   },
8867
8868   /* VEX_LEN_3A61_P_2 */
8869   {
8870     { "vpcmpestri",     { XM, EXx, Ib } },
8871     { "(bad)",          { XX } },
8872   },
8873
8874   /* VEX_LEN_3A62_P_2 */
8875   {
8876     { "vpcmpistrm",     { XM, EXx, Ib } },
8877     { "(bad)",          { XX } },
8878   },
8879
8880   /* VEX_LEN_3A63_P_2 */
8881   {
8882     { "vpcmpistri",     { XM, EXx, Ib } },
8883     { "(bad)",          { XX } },
8884   },
8885
8886   /* VEX_LEN_3A6A_P_2 */
8887   {
8888     { "vfmaddss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8889     { "(bad)",          { XX } },
8890   },
8891
8892   /* VEX_LEN_3A6B_P_2 */
8893   {
8894     { "vfmaddsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8895     { "(bad)",          { XX } },
8896   },
8897
8898   /* VEX_LEN_3A6E_P_2 */
8899   {
8900     { "vfmsubss",       { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8901     { "(bad)",          { XX } },
8902   },
8903
8904   /* VEX_LEN_3A6F_P_2 */
8905   {
8906     { "vfmsubsd",       { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8907     { "(bad)",          { XX } },
8908   },
8909
8910   /* VEX_LEN_3A7A_P_2 */
8911   {
8912     { "vfnmaddss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8913     { "(bad)",          { XX } },
8914   },
8915
8916   /* VEX_LEN_3A7B_P_2 */
8917   {
8918     { "vfnmaddsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8919     { "(bad)",          { XX } },
8920   },
8921
8922   /* VEX_LEN_3A7E_P_2 */
8923   {
8924     { "vfnmsubss",      { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
8925     { "(bad)",          { XX } },
8926   },
8927
8928   /* VEX_LEN_3A7F_P_2 */
8929   {
8930     { "vfnmsubsd",      { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
8931     { "(bad)",          { XX } },
8932   },
8933 };
8934
8935 static const struct dis386 mod_table[][2] = {
8936   {
8937     /* MOD_8D */
8938     { "leaS",           { Gv, M } },
8939     { "(bad)",          { XX } },
8940   },
8941   {
8942     /* MOD_0F01_REG_0 */
8943     { X86_64_TABLE (X86_64_0F01_REG_0) },
8944     { RM_TABLE (RM_0F01_REG_0) },
8945   },
8946   {
8947     /* MOD_0F01_REG_1 */
8948     { X86_64_TABLE (X86_64_0F01_REG_1) },
8949     { RM_TABLE (RM_0F01_REG_1) },
8950   },
8951   {
8952     /* MOD_0F01_REG_2 */
8953     { X86_64_TABLE (X86_64_0F01_REG_2) },
8954     { RM_TABLE (RM_0F01_REG_2) },
8955   },
8956   {
8957     /* MOD_0F01_REG_3 */
8958     { X86_64_TABLE (X86_64_0F01_REG_3) },
8959     { RM_TABLE (RM_0F01_REG_3) },
8960   },
8961   {
8962     /* MOD_0F01_REG_7 */
8963     { "invlpg",         { Mb } },
8964     { RM_TABLE (RM_0F01_REG_7) },
8965   },
8966   {
8967     /* MOD_0F12_PREFIX_0 */
8968     { "movlps",         { XM, EXq } },
8969     { "movhlps",        { XM, EXq } },
8970   },
8971   {
8972     /* MOD_0F13 */
8973     { "movlpX",         { EXq, XM } },
8974     { "(bad)",          { XX } },
8975   },
8976   {
8977     /* MOD_0F16_PREFIX_0 */
8978     { "movhps",         { XM, EXq } },
8979     { "movlhps",        { XM, EXq } },
8980   },
8981   {
8982     /* MOD_0F17 */
8983     { "movhpX",         { EXq, XM } },
8984     { "(bad)",          { XX } },
8985   },
8986   {
8987     /* MOD_0F18_REG_0 */
8988     { "prefetchnta",    { Mb } },
8989     { "(bad)",          { XX } },
8990   },
8991   {
8992     /* MOD_0F18_REG_1 */
8993     { "prefetcht0",     { Mb } },
8994     { "(bad)",          { XX } },
8995   },
8996   {
8997     /* MOD_0F18_REG_2 */
8998     { "prefetcht1",     { Mb } },
8999     { "(bad)",          { XX } },
9000   },
9001   {
9002     /* MOD_0F18_REG_3 */
9003     { "prefetcht2",     { Mb } },
9004     { "(bad)",          { XX } },
9005   },
9006   {
9007     /* MOD_0F20 */
9008     { "(bad)",          { XX } },
9009     { "movZ",           { Rm, Cm } },
9010   },
9011   {
9012     /* MOD_0F21 */
9013     { "(bad)",          { XX } },
9014     { "movZ",           { Rm, Dm } },
9015   },
9016   {
9017     /* MOD_0F22 */
9018     { "(bad)",          { XX } },
9019     { "movZ",           { Cm, Rm } },
9020   },
9021   {
9022     /* MOD_0F23 */
9023     { "(bad)",          { XX } },
9024     { "movZ",           { Dm, Rm } },
9025   },
9026   {
9027     /* MOD_0F24 */
9028     { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9029     { "movL",           { Rd, Td } },
9030   },
9031   {
9032     /* MOD_0F26 */
9033     { "(bad)",          { XX } },
9034     { "movL",           { Td, Rd } },
9035   },
9036   {
9037     /* MOD_0F2B_PREFIX_0 */
9038     {"movntps",         { Mx, XM } },
9039     { "(bad)",          { XX } },
9040   },
9041   {
9042     /* MOD_0F2B_PREFIX_1 */
9043     {"movntss",         { Md, XM } },
9044     { "(bad)",          { XX } },
9045   },
9046   {
9047     /* MOD_0F2B_PREFIX_2 */
9048     {"movntpd",         { Mx, XM } },
9049     { "(bad)",          { XX } },
9050   },
9051   {
9052     /* MOD_0F2B_PREFIX_3 */
9053     {"movntsd",         { Mq, XM } },
9054     { "(bad)",          { XX } },
9055   },
9056   {
9057     /* MOD_0F51 */
9058     { "(bad)",          { XX } },
9059     { "movmskpX",       { Gdq, XS } },
9060   },
9061   {
9062     /* MOD_0F71_REG_2 */
9063     { "(bad)",          { XX } },
9064     { "psrlw",          { MS, Ib } },
9065   },
9066   {
9067     /* MOD_0F71_REG_4 */
9068     { "(bad)",          { XX } },
9069     { "psraw",          { MS, Ib } },
9070   },
9071   {
9072     /* MOD_0F71_REG_6 */
9073     { "(bad)",          { XX } },
9074     { "psllw",          { MS, Ib } },
9075   },
9076   {
9077     /* MOD_0F72_REG_2 */
9078     { "(bad)",          { XX } },
9079     { "psrld",          { MS, Ib } },
9080   },
9081   {
9082     /* MOD_0F72_REG_4 */
9083     { "(bad)",          { XX } },
9084     { "psrad",          { MS, Ib } },
9085   },
9086   {
9087     /* MOD_0F72_REG_6 */
9088     { "(bad)",          { XX } },
9089     { "pslld",          { MS, Ib } },
9090   },
9091   {
9092     /* MOD_0F73_REG_2 */
9093     { "(bad)",          { XX } },
9094     { "psrlq",          { MS, Ib } },
9095   },
9096   {
9097     /* MOD_0F73_REG_3 */
9098     { "(bad)",          { XX } },
9099     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9100   },
9101   {
9102     /* MOD_0F73_REG_6 */
9103     { "(bad)",          { XX } },
9104     { "psllq",          { MS, Ib } },
9105   },
9106   {
9107     /* MOD_0F73_REG_7 */
9108     { "(bad)",          { XX } },
9109     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9110   },
9111   {
9112     /* MOD_0FAE_REG_0 */
9113     { "fxsave",         { M } },
9114     { "(bad)",          { XX } },
9115   },
9116   {
9117     /* MOD_0FAE_REG_1 */
9118     { "fxrstor",        { M } },
9119     { "(bad)",          { XX } },
9120   },
9121   {
9122     /* MOD_0FAE_REG_2 */
9123     { "ldmxcsr",        { Md } },
9124     { "(bad)",          { XX } },
9125   },
9126   {
9127     /* MOD_0FAE_REG_3 */
9128     { "stmxcsr",        { Md } },
9129     { "(bad)",          { XX } },
9130   },
9131   {
9132     /* MOD_0FAE_REG_4 */
9133     { "xsave",          { M } },
9134     { "(bad)",          { XX } },
9135   },
9136   {
9137     /* MOD_0FAE_REG_5 */
9138     { "xrstor",         { M } },
9139     { RM_TABLE (RM_0FAE_REG_5) },
9140   },
9141   {
9142     /* MOD_0FAE_REG_6 */
9143     { "xsaveopt",       { M } },
9144     { RM_TABLE (RM_0FAE_REG_6) },
9145   },
9146   {
9147     /* MOD_0FAE_REG_7 */
9148     { "clflush",        { Mb } },
9149     { RM_TABLE (RM_0FAE_REG_7) },
9150   },
9151   {
9152     /* MOD_0FB2 */
9153     { "lssS",           { Gv, Mp } },
9154     { "(bad)",          { XX } },
9155   },
9156   {
9157     /* MOD_0FB4 */
9158     { "lfsS",           { Gv, Mp } },
9159     { "(bad)",          { XX } },
9160   },
9161   {
9162     /* MOD_0FB5 */
9163     { "lgsS",           { Gv, Mp } },
9164     { "(bad)",          { XX } },
9165   },
9166   {
9167     /* MOD_0FC7_REG_6 */
9168     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9169     { "(bad)",          { XX } },
9170   },
9171   {
9172     /* MOD_0FC7_REG_7 */
9173     { "vmptrst",        { Mq } },
9174     { "(bad)",          { XX } },
9175   },
9176   {
9177     /* MOD_0FD7 */
9178     { "(bad)",          { XX } },
9179     { "pmovmskb",       { Gdq, MS } },
9180   },
9181   {
9182     /* MOD_0FE7_PREFIX_2 */
9183     { "movntdq",        { Mx, XM } },
9184     { "(bad)",          { XX } },
9185   },
9186   {
9187     /* MOD_0FF0_PREFIX_3 */
9188     { "lddqu",          { XM, M } },
9189     { "(bad)",          { XX } },
9190   },
9191   {
9192     /* MOD_0F382A_PREFIX_2 */
9193     { "movntdqa",       { XM, Mx } },
9194     { "(bad)",          { XX } },
9195   },
9196   {
9197     /* MOD_62_32BIT */
9198     { "bound{S|}",      { Gv, Ma } },
9199     { "(bad)",          { XX } },
9200   },
9201   {
9202     /* MOD_C4_32BIT */
9203     { "lesS",           { Gv, Mp } },
9204     { VEX_C4_TABLE (VEX_0F) },
9205   },
9206   {
9207     /* MOD_C5_32BIT */
9208     { "ldsS",           { Gv, Mp } },
9209     { VEX_C5_TABLE (VEX_0F) },
9210   },
9211   {
9212     /* MOD_VEX_12_PREFIX_0 */
9213     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9214     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9215   },
9216   {
9217     /* MOD_VEX_13 */
9218     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9219     { "(bad)",          { XX } },
9220   },
9221   {
9222     /* MOD_VEX_16_PREFIX_0 */
9223     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9224     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9225   },
9226   {
9227     /* MOD_VEX_17 */
9228     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9229     { "(bad)",          { XX } },
9230   },
9231   {
9232     /* MOD_VEX_2B */
9233     { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9234     { "(bad)",          { XX } },
9235   },
9236   {
9237     /* MOD_VEX_51 */
9238     { "(bad)",          { XX } },
9239     { "vmovmskpX",      { Gdq, XS } },
9240   },
9241   {
9242     /* MOD_VEX_71_REG_2 */
9243     { "(bad)",          { XX } },
9244     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9245   },
9246   {
9247     /* MOD_VEX_71_REG_4 */
9248     { "(bad)",          { XX } },
9249     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9250   },
9251   {
9252     /* MOD_VEX_71_REG_6 */
9253     { "(bad)",          { XX } },
9254     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9255   },
9256   {
9257     /* MOD_VEX_72_REG_2 */
9258     { "(bad)",          { XX } },
9259     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9260   },
9261   {
9262     /* MOD_VEX_72_REG_4 */
9263     { "(bad)",          { XX } },
9264     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9265   },
9266   {
9267     /* MOD_VEX_72_REG_6 */
9268     { "(bad)",          { XX } },
9269     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9270   },
9271   {
9272     /* MOD_VEX_73_REG_2 */
9273     { "(bad)",          { XX } },
9274     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9275   },
9276   {
9277     /* MOD_VEX_73_REG_3 */
9278     { "(bad)",          { XX } },
9279     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9280   },
9281   {
9282     /* MOD_VEX_73_REG_6 */
9283     { "(bad)",          { XX } },
9284     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9285   },
9286   {
9287     /* MOD_VEX_73_REG_7 */
9288     { "(bad)",          { XX } },
9289     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9290   },
9291   {
9292     /* MOD_VEX_AE_REG_2 */
9293     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9294     { "(bad)",          { XX } },
9295   },
9296   {
9297     /* MOD_VEX_AE_REG_3 */
9298     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9299     { "(bad)",          { XX } },
9300   },
9301   {
9302     /* MOD_VEX_D7_PREFIX_2 */
9303     { "(bad)",          { XX } },
9304     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9305   },
9306   {
9307     /* MOD_VEX_E7_PREFIX_2 */
9308     { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9309     { "(bad)",          { XX } },
9310   },
9311   {
9312     /* MOD_VEX_F0_PREFIX_3 */
9313     { "vlddqu",         { XM, M } },
9314     { "(bad)",          { XX } },
9315   },
9316   {
9317     /* MOD_VEX_3818_PREFIX_2 */
9318     { "vbroadcastss",   { XM, Md } },
9319     { "(bad)",          { XX } },
9320   },
9321   {
9322     /* MOD_VEX_3819_PREFIX_2 */
9323     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9324     { "(bad)",          { XX } },
9325   },
9326   {
9327     /* MOD_VEX_381A_PREFIX_2 */
9328     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9329     { "(bad)",          { XX } },
9330   },
9331   {
9332     /* MOD_VEX_382A_PREFIX_2 */
9333     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9334     { "(bad)",          { XX } },
9335   },
9336   {
9337     /* MOD_VEX_382C_PREFIX_2 */
9338     { "vmaskmovps",     { XM, Vex, Mx } },
9339     { "(bad)",          { XX } },
9340   },
9341   {
9342     /* MOD_VEX_382D_PREFIX_2 */
9343     { "vmaskmovpd",     { XM, Vex, Mx } },
9344     { "(bad)",          { XX } },
9345   },
9346   {
9347     /* MOD_VEX_382E_PREFIX_2 */
9348     { "vmaskmovps",     { Mx, Vex, XM } },
9349     { "(bad)",          { XX } },
9350   },
9351   {
9352     /* MOD_VEX_382F_PREFIX_2 */
9353     { "vmaskmovpd",     { Mx, Vex, XM } },
9354     { "(bad)",          { XX } },
9355   },
9356 };
9357
9358 static const struct dis386 rm_table[][8] = {
9359   {
9360     /* RM_0F01_REG_0 */
9361     { "(bad)",          { XX } },
9362     { "vmcall",         { Skip_MODRM } },
9363     { "vmlaunch",       { Skip_MODRM } },
9364     { "vmresume",       { Skip_MODRM } },
9365     { "vmxoff",         { Skip_MODRM } },
9366     { "(bad)",          { XX } },
9367     { "(bad)",          { XX } },
9368     { "(bad)",          { XX } },
9369   },
9370   {
9371     /* RM_0F01_REG_1 */
9372     { "monitor",        { { OP_Monitor, 0 } } },
9373     { "mwait",          { { OP_Mwait, 0 } } },
9374     { "(bad)",          { XX } },
9375     { "(bad)",          { XX } },
9376     { "(bad)",          { XX } },
9377     { "(bad)",          { XX } },
9378     { "(bad)",          { XX } },
9379     { "(bad)",          { XX } },
9380   },
9381   {
9382     /* RM_0F01_REG_2 */
9383     { "xgetbv",         { Skip_MODRM } },
9384     { "xsetbv",         { Skip_MODRM } },
9385     { "(bad)",          { XX } },
9386     { "(bad)",          { XX } },
9387     { "(bad)",          { XX } },
9388     { "(bad)",          { XX } },
9389     { "(bad)",          { XX } },
9390     { "(bad)",          { XX } },
9391   },
9392   {
9393     /* RM_0F01_REG_3 */
9394     { "vmrun",          { Skip_MODRM } },
9395     { "vmmcall",        { Skip_MODRM } },
9396     { "vmload",         { Skip_MODRM } },
9397     { "vmsave",         { Skip_MODRM } },
9398     { "stgi",           { Skip_MODRM } },
9399     { "clgi",           { Skip_MODRM } },
9400     { "skinit",         { Skip_MODRM } },
9401     { "invlpga",        { Skip_MODRM } },
9402   },
9403   {
9404     /* RM_0F01_REG_7 */
9405     { "swapgs",         { Skip_MODRM } },
9406     { "rdtscp",         { Skip_MODRM } },
9407     { "(bad)",          { XX } },
9408     { "(bad)",          { XX } },
9409     { "(bad)",          { XX } },
9410     { "(bad)",          { XX } },
9411     { "(bad)",          { XX } },
9412     { "(bad)",          { XX } },
9413   },
9414   {
9415     /* RM_0FAE_REG_5 */
9416     { "lfence",         { Skip_MODRM } },
9417     { "(bad)",          { XX } },
9418     { "(bad)",          { XX } },
9419     { "(bad)",          { XX } },
9420     { "(bad)",          { XX } },
9421     { "(bad)",          { XX } },
9422     { "(bad)",          { XX } },
9423     { "(bad)",          { XX } },
9424   },
9425   {
9426     /* RM_0FAE_REG_6 */
9427     { "mfence",         { Skip_MODRM } },
9428     { "(bad)",          { XX } },
9429     { "(bad)",          { XX } },
9430     { "(bad)",          { XX } },
9431     { "(bad)",          { XX } },
9432     { "(bad)",          { XX } },
9433     { "(bad)",          { XX } },
9434     { "(bad)",          { XX } },
9435   },
9436   {
9437     /* RM_0FAE_REG_7 */
9438     { "sfence",         { Skip_MODRM } },
9439     { "(bad)",          { XX } },
9440     { "(bad)",          { XX } },
9441     { "(bad)",          { XX } },
9442     { "(bad)",          { XX } },
9443     { "(bad)",          { XX } },
9444     { "(bad)",          { XX } },
9445     { "(bad)",          { XX } },
9446   },
9447 };
9448
9449 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9450
9451 static void
9452 ckprefix (void)
9453 {
9454   int newrex;
9455   rex = 0;
9456   rex_original = 0;
9457   rex_ignored = 0;
9458   prefixes = 0;
9459   used_prefixes = 0;
9460   rex_used = 0;
9461   while (1)
9462     {
9463       FETCH_DATA (the_info, codep + 1);
9464       newrex = 0;
9465       switch (*codep)
9466         {
9467         /* REX prefixes family.  */
9468         case 0x40:
9469         case 0x41:
9470         case 0x42:
9471         case 0x43:
9472         case 0x44:
9473         case 0x45:
9474         case 0x46:
9475         case 0x47:
9476         case 0x48:
9477         case 0x49:
9478         case 0x4a:
9479         case 0x4b:
9480         case 0x4c:
9481         case 0x4d:
9482         case 0x4e:
9483         case 0x4f:
9484             if (address_mode == mode_64bit)
9485               newrex = *codep;
9486             else
9487               return;
9488           break;
9489         case 0xf3:
9490           prefixes |= PREFIX_REPZ;
9491           break;
9492         case 0xf2:
9493           prefixes |= PREFIX_REPNZ;
9494           break;
9495         case 0xf0:
9496           prefixes |= PREFIX_LOCK;
9497           break;
9498         case 0x2e:
9499           prefixes |= PREFIX_CS;
9500           break;
9501         case 0x36:
9502           prefixes |= PREFIX_SS;
9503           break;
9504         case 0x3e:
9505           prefixes |= PREFIX_DS;
9506           break;
9507         case 0x26:
9508           prefixes |= PREFIX_ES;
9509           break;
9510         case 0x64:
9511           prefixes |= PREFIX_FS;
9512           break;
9513         case 0x65:
9514           prefixes |= PREFIX_GS;
9515           break;
9516         case 0x66:
9517           prefixes |= PREFIX_DATA;
9518           break;
9519         case 0x67:
9520           prefixes |= PREFIX_ADDR;
9521           break;
9522         case FWAIT_OPCODE:
9523           /* fwait is really an instruction.  If there are prefixes
9524              before the fwait, they belong to the fwait, *not* to the
9525              following instruction.  */
9526           if (prefixes || rex)
9527             {
9528               prefixes |= PREFIX_FWAIT;
9529               codep++;
9530               return;
9531             }
9532           prefixes = PREFIX_FWAIT;
9533           break;
9534         default:
9535           return;
9536         }
9537       /* Rex is ignored when followed by another prefix.  */
9538       if (rex)
9539         {
9540           rex_used = rex;
9541           return;
9542         }
9543       rex = newrex;
9544       rex_original = rex;
9545       codep++;
9546     }
9547 }
9548
9549 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9550    prefix byte.  */
9551
9552 static const char *
9553 prefix_name (int pref, int sizeflag)
9554 {
9555   static const char *rexes [16] =
9556     {
9557       "rex",            /* 0x40 */
9558       "rex.B",          /* 0x41 */
9559       "rex.X",          /* 0x42 */
9560       "rex.XB",         /* 0x43 */
9561       "rex.R",          /* 0x44 */
9562       "rex.RB",         /* 0x45 */
9563       "rex.RX",         /* 0x46 */
9564       "rex.RXB",        /* 0x47 */
9565       "rex.W",          /* 0x48 */
9566       "rex.WB",         /* 0x49 */
9567       "rex.WX",         /* 0x4a */
9568       "rex.WXB",        /* 0x4b */
9569       "rex.WR",         /* 0x4c */
9570       "rex.WRB",        /* 0x4d */
9571       "rex.WRX",        /* 0x4e */
9572       "rex.WRXB",       /* 0x4f */
9573     };
9574
9575   switch (pref)
9576     {
9577     /* REX prefixes family.  */
9578     case 0x40:
9579     case 0x41:
9580     case 0x42:
9581     case 0x43:
9582     case 0x44:
9583     case 0x45:
9584     case 0x46:
9585     case 0x47:
9586     case 0x48:
9587     case 0x49:
9588     case 0x4a:
9589     case 0x4b:
9590     case 0x4c:
9591     case 0x4d:
9592     case 0x4e:
9593     case 0x4f:
9594       return rexes [pref - 0x40];
9595     case 0xf3:
9596       return "repz";
9597     case 0xf2:
9598       return "repnz";
9599     case 0xf0:
9600       return "lock";
9601     case 0x2e:
9602       return "cs";
9603     case 0x36:
9604       return "ss";
9605     case 0x3e:
9606       return "ds";
9607     case 0x26:
9608       return "es";
9609     case 0x64:
9610       return "fs";
9611     case 0x65:
9612       return "gs";
9613     case 0x66:
9614       return (sizeflag & DFLAG) ? "data16" : "data32";
9615     case 0x67:
9616       if (address_mode == mode_64bit)
9617         return (sizeflag & AFLAG) ? "addr32" : "addr64";
9618       else
9619         return (sizeflag & AFLAG) ? "addr16" : "addr32";
9620     case FWAIT_OPCODE:
9621       return "fwait";
9622     default:
9623       return NULL;
9624     }
9625 }
9626
9627 static char op_out[MAX_OPERANDS][100];
9628 static int op_ad, op_index[MAX_OPERANDS];
9629 static int two_source_ops;
9630 static bfd_vma op_address[MAX_OPERANDS];
9631 static bfd_vma op_riprel[MAX_OPERANDS];
9632 static bfd_vma start_pc;
9633
9634 /*
9635  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9636  *   (see topic "Redundant prefixes" in the "Differences from 8086"
9637  *   section of the "Virtual 8086 Mode" chapter.)
9638  * 'pc' should be the address of this instruction, it will
9639  *   be used to print the target address if this is a relative jump or call
9640  * The function returns the length of this instruction in bytes.
9641  */
9642
9643 static char intel_syntax;
9644 static char intel_mnemonic = !SYSV386_COMPAT;
9645 static char open_char;
9646 static char close_char;
9647 static char separator_char;
9648 static char scale_char;
9649
9650 /* Here for backwards compatibility.  When gdb stops using
9651    print_insn_i386_att and print_insn_i386_intel these functions can
9652    disappear, and print_insn_i386 be merged into print_insn.  */
9653 int
9654 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9655 {
9656   intel_syntax = 0;
9657
9658   return print_insn (pc, info);
9659 }
9660
9661 int
9662 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9663 {
9664   intel_syntax = 1;
9665
9666   return print_insn (pc, info);
9667 }
9668
9669 int
9670 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9671 {
9672   intel_syntax = -1;
9673
9674   return print_insn (pc, info);
9675 }
9676
9677 void
9678 print_i386_disassembler_options (FILE *stream)
9679 {
9680   fprintf (stream, _("\n\
9681 The following i386/x86-64 specific disassembler options are supported for use\n\
9682 with the -M switch (multiple options should be separated by commas):\n"));
9683
9684   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
9685   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
9686   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
9687   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
9688   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
9689   fprintf (stream, _("  att-mnemonic\n"
9690                      "              Display instruction in AT&T mnemonic\n"));
9691   fprintf (stream, _("  intel-mnemonic\n"
9692                      "              Display instruction in Intel mnemonic\n"));
9693   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
9694   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
9695   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
9696   fprintf (stream, _("  data32      Assume 32bit data size\n"));
9697   fprintf (stream, _("  data16      Assume 16bit data size\n"));
9698   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
9699 }
9700
9701 /* Get a pointer to struct dis386 with a valid name.  */
9702
9703 static const struct dis386 *
9704 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9705 {
9706   int index, vex_table_index;
9707
9708   if (dp->name != NULL)
9709     return dp;
9710
9711   switch (dp->op[0].bytemode)
9712     {
9713     case USE_REG_TABLE:
9714       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9715       break;
9716
9717     case USE_MOD_TABLE:
9718       index = modrm.mod == 0x3 ? 1 : 0;
9719       dp = &mod_table[dp->op[1].bytemode][index];
9720       break;
9721
9722     case USE_RM_TABLE:
9723       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9724       break;
9725
9726     case USE_PREFIX_TABLE:
9727       if (need_vex)
9728         {
9729           /* The prefix in VEX is implicit.  */
9730           switch (vex.prefix)
9731             {
9732             case 0:
9733               index = 0;
9734               break;
9735             case REPE_PREFIX_OPCODE:
9736               index = 1;
9737               break;
9738             case DATA_PREFIX_OPCODE:
9739               index = 2;
9740               break;
9741             case REPNE_PREFIX_OPCODE:
9742               index = 3;
9743               break;
9744             default:
9745               abort ();
9746               break;
9747             }
9748         }
9749       else
9750         {
9751           index = 0;
9752           used_prefixes |= (prefixes & PREFIX_REPZ);
9753           if (prefixes & PREFIX_REPZ)
9754             {
9755               index = 1;
9756               repz_prefix = NULL;
9757             }
9758           else
9759             {
9760               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9761                  PREFIX_DATA.  */
9762               used_prefixes |= (prefixes & PREFIX_REPNZ);
9763               if (prefixes & PREFIX_REPNZ)
9764                 {
9765                   index = 3;
9766                   repnz_prefix = NULL;
9767                 }
9768               else
9769                 {
9770                   used_prefixes |= (prefixes & PREFIX_DATA);
9771                   if (prefixes & PREFIX_DATA)
9772                     {
9773                       index = 2;
9774                       data_prefix = NULL;
9775                     }
9776                 }
9777             }
9778         }
9779       dp = &prefix_table[dp->op[1].bytemode][index];
9780       break;
9781
9782     case USE_X86_64_TABLE:
9783       index = address_mode == mode_64bit ? 1 : 0;
9784       dp = &x86_64_table[dp->op[1].bytemode][index];
9785       break;
9786
9787     case USE_3BYTE_TABLE:
9788       FETCH_DATA (info, codep + 2);
9789       index = *codep++;
9790       dp = &three_byte_table[dp->op[1].bytemode][index];
9791       modrm.mod = (*codep >> 6) & 3;
9792       modrm.reg = (*codep >> 3) & 7;
9793       modrm.rm = *codep & 7;
9794       break;
9795
9796     case USE_VEX_LEN_TABLE:
9797       if (!need_vex)
9798         abort ();
9799
9800       switch (vex.length)
9801         {
9802         case 128:
9803           index = 0;
9804           break;
9805         case 256:
9806           index = 1;
9807           break;
9808         default:
9809           abort ();
9810           break;
9811         }
9812
9813       dp = &vex_len_table[dp->op[1].bytemode][index];
9814       break;
9815
9816     case USE_VEX_C4_TABLE:
9817       FETCH_DATA (info, codep + 3);
9818       /* All bits in the REX prefix are ignored.  */
9819       rex_ignored = rex;
9820       rex = ~(*codep >> 5) & 0x7;
9821       switch ((*codep & 0x1f))
9822         {
9823         default:
9824           BadOp ();
9825         case 0x1:
9826           vex_table_index = 0;
9827           break;
9828         case 0x2:
9829           vex_table_index = 1;
9830           break;
9831         case 0x3:
9832           vex_table_index = 2;
9833           break;
9834         }
9835       codep++;
9836       vex.w = *codep & 0x80;
9837       if (vex.w && address_mode == mode_64bit)
9838         rex |= REX_W;
9839
9840       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9841       if (address_mode != mode_64bit
9842           && vex.register_specifier > 0x7)
9843         BadOp ();
9844
9845       vex.length = (*codep & 0x4) ? 256 : 128;
9846       switch ((*codep & 0x3))
9847         {
9848         case 0:
9849           vex.prefix = 0;
9850           break;
9851         case 1:
9852           vex.prefix = DATA_PREFIX_OPCODE;
9853           break;
9854         case 2:
9855           vex.prefix = REPE_PREFIX_OPCODE;
9856           break;
9857         case 3:
9858           vex.prefix = REPNE_PREFIX_OPCODE;
9859           break;
9860         }
9861       need_vex = 1;
9862       need_vex_reg = 1;
9863       codep++;
9864       index = *codep++;
9865       dp = &vex_table[vex_table_index][index];
9866       /* There is no MODRM byte for VEX [82|77].  */
9867       if (index != 0x77 && index != 0x82)
9868         {
9869           FETCH_DATA (info, codep + 1);
9870           modrm.mod = (*codep >> 6) & 3;
9871           modrm.reg = (*codep >> 3) & 7;
9872           modrm.rm = *codep & 7;
9873         }
9874       break;
9875
9876     case USE_VEX_C5_TABLE:
9877       FETCH_DATA (info, codep + 2);
9878       /* All bits in the REX prefix are ignored.  */
9879       rex_ignored = rex;
9880       rex = (*codep & 0x80) ? 0 : REX_R;
9881
9882       vex.register_specifier = (~(*codep >> 3)) & 0xf;
9883       if (address_mode != mode_64bit
9884           && vex.register_specifier > 0x7)
9885         BadOp ();
9886
9887       vex.length = (*codep & 0x4) ? 256 : 128;
9888       switch ((*codep & 0x3))
9889         {
9890         case 0:
9891           vex.prefix = 0;
9892           break;
9893         case 1:
9894           vex.prefix = DATA_PREFIX_OPCODE;
9895           break;
9896         case 2:
9897           vex.prefix = REPE_PREFIX_OPCODE;
9898           break;
9899         case 3:
9900           vex.prefix = REPNE_PREFIX_OPCODE;
9901           break;
9902         }
9903       need_vex = 1;
9904       need_vex_reg = 1;
9905       codep++;
9906       index = *codep++;
9907       dp = &vex_table[dp->op[1].bytemode][index];
9908       /* There is no MODRM byte for VEX [82|77].  */
9909       if (index != 0x77 && index != 0x82)
9910         {
9911           FETCH_DATA (info, codep + 1);
9912           modrm.mod = (*codep >> 6) & 3;
9913           modrm.reg = (*codep >> 3) & 7;
9914           modrm.rm = *codep & 7;
9915         }
9916       break;
9917
9918     default:
9919       oappend (INTERNAL_DISASSEMBLER_ERROR);
9920       return NULL;
9921     }
9922
9923   if (dp->name != NULL)
9924     return dp;
9925   else
9926     return get_valid_dis386 (dp, info);
9927 }
9928
9929 static int
9930 print_insn (bfd_vma pc, disassemble_info *info)
9931 {
9932   const struct dis386 *dp;
9933   int i;
9934   char *op_txt[MAX_OPERANDS];
9935   int needcomma;
9936   int sizeflag;
9937   const char *p;
9938   struct dis_private priv;
9939   unsigned char op;
9940   char prefix_obuf[32];
9941   char *prefix_obufp;
9942
9943   if (info->mach == bfd_mach_x86_64_intel_syntax
9944       || info->mach == bfd_mach_x86_64)
9945     address_mode = mode_64bit;
9946   else
9947     address_mode = mode_32bit;
9948
9949   if (intel_syntax == (char) -1)
9950     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
9951                     || info->mach == bfd_mach_x86_64_intel_syntax);
9952
9953   if (info->mach == bfd_mach_i386_i386
9954       || info->mach == bfd_mach_x86_64
9955       || info->mach == bfd_mach_i386_i386_intel_syntax
9956       || info->mach == bfd_mach_x86_64_intel_syntax)
9957     priv.orig_sizeflag = AFLAG | DFLAG;
9958   else if (info->mach == bfd_mach_i386_i8086)
9959     priv.orig_sizeflag = 0;
9960   else
9961     abort ();
9962
9963   for (p = info->disassembler_options; p != NULL; )
9964     {
9965       if (CONST_STRNEQ (p, "x86-64"))
9966         {
9967           address_mode = mode_64bit;
9968           priv.orig_sizeflag = AFLAG | DFLAG;
9969         }
9970       else if (CONST_STRNEQ (p, "i386"))
9971         {
9972           address_mode = mode_32bit;
9973           priv.orig_sizeflag = AFLAG | DFLAG;
9974         }
9975       else if (CONST_STRNEQ (p, "i8086"))
9976         {
9977           address_mode = mode_16bit;
9978           priv.orig_sizeflag = 0;
9979         }
9980       else if (CONST_STRNEQ (p, "intel"))
9981         {
9982           intel_syntax = 1;
9983           if (CONST_STRNEQ (p + 5, "-mnemonic"))
9984             intel_mnemonic = 1;
9985         }
9986       else if (CONST_STRNEQ (p, "att"))
9987         {
9988           intel_syntax = 0;
9989           if (CONST_STRNEQ (p + 3, "-mnemonic"))
9990             intel_mnemonic = 0;
9991         }
9992       else if (CONST_STRNEQ (p, "addr"))
9993         {
9994           if (address_mode == mode_64bit)
9995             {
9996               if (p[4] == '3' && p[5] == '2')
9997                 priv.orig_sizeflag &= ~AFLAG;
9998               else if (p[4] == '6' && p[5] == '4')
9999                 priv.orig_sizeflag |= AFLAG;
10000             }
10001           else
10002             {
10003               if (p[4] == '1' && p[5] == '6')
10004                 priv.orig_sizeflag &= ~AFLAG;
10005               else if (p[4] == '3' && p[5] == '2')
10006                 priv.orig_sizeflag |= AFLAG;
10007             }
10008         }
10009       else if (CONST_STRNEQ (p, "data"))
10010         {
10011           if (p[4] == '1' && p[5] == '6')
10012             priv.orig_sizeflag &= ~DFLAG;
10013           else if (p[4] == '3' && p[5] == '2')
10014             priv.orig_sizeflag |= DFLAG;
10015         }
10016       else if (CONST_STRNEQ (p, "suffix"))
10017         priv.orig_sizeflag |= SUFFIX_ALWAYS;
10018
10019       p = strchr (p, ',');
10020       if (p != NULL)
10021         p++;
10022     }
10023
10024   if (intel_syntax)
10025     {
10026       names64 = intel_names64;
10027       names32 = intel_names32;
10028       names16 = intel_names16;
10029       names8 = intel_names8;
10030       names8rex = intel_names8rex;
10031       names_seg = intel_names_seg;
10032       index64 = intel_index64;
10033       index32 = intel_index32;
10034       index16 = intel_index16;
10035       open_char = '[';
10036       close_char = ']';
10037       separator_char = '+';
10038       scale_char = '*';
10039     }
10040   else
10041     {
10042       names64 = att_names64;
10043       names32 = att_names32;
10044       names16 = att_names16;
10045       names8 = att_names8;
10046       names8rex = att_names8rex;
10047       names_seg = att_names_seg;
10048       index64 = att_index64;
10049       index32 = att_index32;
10050       index16 = att_index16;
10051       open_char = '(';
10052       close_char =  ')';
10053       separator_char = ',';
10054       scale_char = ',';
10055     }
10056
10057   /* The output looks better if we put 7 bytes on a line, since that
10058      puts most long word instructions on a single line.  */
10059   info->bytes_per_line = 7;
10060
10061   info->private_data = &priv;
10062   priv.max_fetched = priv.the_buffer;
10063   priv.insn_start = pc;
10064
10065   obuf[0] = 0;
10066   for (i = 0; i < MAX_OPERANDS; ++i)
10067     {
10068       op_out[i][0] = 0;
10069       op_index[i] = -1;
10070     }
10071
10072   the_info = info;
10073   start_pc = pc;
10074   start_codep = priv.the_buffer;
10075   codep = priv.the_buffer;
10076
10077   if (setjmp (priv.bailout) != 0)
10078     {
10079       const char *name;
10080
10081       /* Getting here means we tried for data but didn't get it.  That
10082          means we have an incomplete instruction of some sort.  Just
10083          print the first byte as a prefix or a .byte pseudo-op.  */
10084       if (codep > priv.the_buffer)
10085         {
10086           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10087           if (name != NULL)
10088             (*info->fprintf_func) (info->stream, "%s", name);
10089           else
10090             {
10091               /* Just print the first byte as a .byte instruction.  */
10092               (*info->fprintf_func) (info->stream, ".byte 0x%x",
10093                                      (unsigned int) priv.the_buffer[0]);
10094             }
10095
10096           return 1;
10097         }
10098
10099       return -1;
10100     }
10101
10102   obufp = obuf;
10103   ckprefix ();
10104
10105   insn_codep = codep;
10106   sizeflag = priv.orig_sizeflag;
10107
10108   FETCH_DATA (info, codep + 1);
10109   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10110
10111   if (((prefixes & PREFIX_FWAIT)
10112        && ((*codep < 0xd8) || (*codep > 0xdf)))
10113       || (rex && rex_used))
10114     {
10115       const char *name;
10116
10117       /* fwait not followed by floating point instruction, or rex followed
10118          by other prefixes.  Print the first prefix.  */
10119       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10120       if (name == NULL)
10121         name = INTERNAL_DISASSEMBLER_ERROR;
10122       (*info->fprintf_func) (info->stream, "%s", name);
10123       return 1;
10124     }
10125
10126   op = 0;
10127   if (*codep == 0x0f)
10128     {
10129       unsigned char threebyte;
10130       FETCH_DATA (info, codep + 2);
10131       threebyte = *++codep;
10132       dp = &dis386_twobyte[threebyte];
10133       need_modrm = twobyte_has_modrm[*codep];
10134       codep++;
10135     }
10136   else
10137     {
10138       dp = &dis386[*codep];
10139       need_modrm = onebyte_has_modrm[*codep];
10140       codep++;
10141     }
10142
10143   if ((prefixes & PREFIX_REPZ))
10144     {
10145       repz_prefix = "repz ";
10146       used_prefixes |= PREFIX_REPZ;
10147     }
10148   else
10149     repz_prefix = NULL;
10150
10151   if ((prefixes & PREFIX_REPNZ))
10152     {
10153       repnz_prefix = "repnz ";
10154       used_prefixes |= PREFIX_REPNZ;
10155     }
10156   else
10157     repnz_prefix = NULL;
10158
10159   if ((prefixes & PREFIX_LOCK))
10160     {
10161       lock_prefix = "lock ";
10162       used_prefixes |= PREFIX_LOCK;
10163     }
10164   else
10165     lock_prefix = NULL;
10166
10167   addr_prefix = NULL;
10168   if (prefixes & PREFIX_ADDR)
10169     {
10170       sizeflag ^= AFLAG;
10171       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10172         {
10173           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10174             addr_prefix = "addr32 ";
10175           else
10176             addr_prefix = "addr16 ";
10177           used_prefixes |= PREFIX_ADDR;
10178         }
10179     }
10180
10181   data_prefix = NULL;
10182   if ((prefixes & PREFIX_DATA))
10183     {
10184       sizeflag ^= DFLAG;
10185       if (dp->op[2].bytemode == cond_jump_mode
10186           && dp->op[0].bytemode == v_mode
10187           && !intel_syntax)
10188         {
10189           if (sizeflag & DFLAG)
10190             data_prefix = "data32 ";
10191           else
10192             data_prefix = "data16 ";
10193           used_prefixes |= PREFIX_DATA;
10194         }
10195     }
10196
10197   if (need_modrm)
10198     {
10199       FETCH_DATA (info, codep + 1);
10200       modrm.mod = (*codep >> 6) & 3;
10201       modrm.reg = (*codep >> 3) & 7;
10202       modrm.rm = *codep & 7;
10203     }
10204
10205   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10206     {
10207       dofloat (sizeflag);
10208     }
10209   else
10210     {
10211       need_vex = 0;
10212       need_vex_reg = 0;
10213       vex_w_done = 0;
10214       dp = get_valid_dis386 (dp, info);
10215       if (dp != NULL && putop (dp->name, sizeflag) == 0)
10216         {
10217           for (i = 0; i < MAX_OPERANDS; ++i)
10218             {
10219               obufp = op_out[i];
10220               op_ad = MAX_OPERANDS - 1 - i;
10221               if (dp->op[i].rtn)
10222                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10223             }
10224         }
10225     }
10226
10227   /* See if any prefixes were not used.  If so, print the first one
10228      separately.  If we don't do this, we'll wind up printing an
10229      instruction stream which does not precisely correspond to the
10230      bytes we are disassembling.  */
10231   if ((prefixes & ~used_prefixes) != 0)
10232     {
10233       const char *name;
10234
10235       name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10236       if (name == NULL)
10237         name = INTERNAL_DISASSEMBLER_ERROR;
10238       (*info->fprintf_func) (info->stream, "%s", name);
10239       return 1;
10240     }
10241   if ((rex_original & ~rex_used) || rex_ignored)
10242     {
10243       const char *name;
10244       name = prefix_name (rex_original, priv.orig_sizeflag);
10245       if (name == NULL)
10246         name = INTERNAL_DISASSEMBLER_ERROR;
10247       (*info->fprintf_func) (info->stream, "%s ", name);
10248     }
10249
10250   prefix_obuf[0] = 0;
10251   prefix_obufp = prefix_obuf;
10252   if (lock_prefix)
10253     prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10254   if (repz_prefix)
10255     prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10256   if (repnz_prefix)
10257     prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10258   if (addr_prefix)
10259     prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10260   if (data_prefix)
10261     prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10262
10263   if (prefix_obuf[0] != 0)
10264     (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10265
10266   obufp = obuf + strlen (obuf);
10267   for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10268     oappend (" ");
10269   oappend (" ");
10270   (*info->fprintf_func) (info->stream, "%s", obuf);
10271
10272   /* The enter and bound instructions are printed with operands in the same
10273      order as the intel book; everything else is printed in reverse order.  */
10274   if (intel_syntax || two_source_ops)
10275     {
10276       bfd_vma riprel;
10277
10278       for (i = 0; i < MAX_OPERANDS; ++i)
10279         op_txt[i] = op_out[i];
10280
10281       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10282         {
10283           op_ad = op_index[i];
10284           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10285           op_index[MAX_OPERANDS - 1 - i] = op_ad;
10286           riprel = op_riprel[i];
10287           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10288           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10289         }
10290     }
10291   else
10292     {
10293       for (i = 0; i < MAX_OPERANDS; ++i)
10294         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10295     }
10296
10297   needcomma = 0;
10298   for (i = 0; i < MAX_OPERANDS; ++i)
10299     if (*op_txt[i])
10300       {
10301         if (needcomma)
10302           (*info->fprintf_func) (info->stream, ",");
10303         if (op_index[i] != -1 && !op_riprel[i])
10304           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10305         else
10306           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10307         needcomma = 1;
10308       }
10309
10310   for (i = 0; i < MAX_OPERANDS; i++)
10311     if (op_index[i] != -1 && op_riprel[i])
10312       {
10313         (*info->fprintf_func) (info->stream, "        # ");
10314         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10315                                                 + op_address[op_index[i]]), info);
10316         break;
10317       }
10318   return codep - priv.the_buffer;
10319 }
10320
10321 static const char *float_mem[] = {
10322   /* d8 */
10323   "fadd{s|}",
10324   "fmul{s|}",
10325   "fcom{s|}",
10326   "fcomp{s|}",
10327   "fsub{s|}",
10328   "fsubr{s|}",
10329   "fdiv{s|}",
10330   "fdivr{s|}",
10331   /* d9 */
10332   "fld{s|}",
10333   "(bad)",
10334   "fst{s|}",
10335   "fstp{s|}",
10336   "fldenvIC",
10337   "fldcw",
10338   "fNstenvIC",
10339   "fNstcw",
10340   /* da */
10341   "fiadd{l|}",
10342   "fimul{l|}",
10343   "ficom{l|}",
10344   "ficomp{l|}",
10345   "fisub{l|}",
10346   "fisubr{l|}",
10347   "fidiv{l|}",
10348   "fidivr{l|}",
10349   /* db */
10350   "fild{l|}",
10351   "fisttp{l|}",
10352   "fist{l|}",
10353   "fistp{l|}",
10354   "(bad)",
10355   "fld{t||t|}",
10356   "(bad)",
10357   "fstp{t||t|}",
10358   /* dc */
10359   "fadd{l|}",
10360   "fmul{l|}",
10361   "fcom{l|}",
10362   "fcomp{l|}",
10363   "fsub{l|}",
10364   "fsubr{l|}",
10365   "fdiv{l|}",
10366   "fdivr{l|}",
10367   /* dd */
10368   "fld{l|}",
10369   "fisttp{ll|}",
10370   "fst{l||}",
10371   "fstp{l|}",
10372   "frstorIC",
10373   "(bad)",
10374   "fNsaveIC",
10375   "fNstsw",
10376   /* de */
10377   "fiadd",
10378   "fimul",
10379   "ficom",
10380   "ficomp",
10381   "fisub",
10382   "fisubr",
10383   "fidiv",
10384   "fidivr",
10385   /* df */
10386   "fild",
10387   "fisttp",
10388   "fist",
10389   "fistp",
10390   "fbld",
10391   "fild{ll|}",
10392   "fbstp",
10393   "fistp{ll|}",
10394 };
10395
10396 static const unsigned char float_mem_mode[] = {
10397   /* d8 */
10398   d_mode,
10399   d_mode,
10400   d_mode,
10401   d_mode,
10402   d_mode,
10403   d_mode,
10404   d_mode,
10405   d_mode,
10406   /* d9 */
10407   d_mode,
10408   0,
10409   d_mode,
10410   d_mode,
10411   0,
10412   w_mode,
10413   0,
10414   w_mode,
10415   /* da */
10416   d_mode,
10417   d_mode,
10418   d_mode,
10419   d_mode,
10420   d_mode,
10421   d_mode,
10422   d_mode,
10423   d_mode,
10424   /* db */
10425   d_mode,
10426   d_mode,
10427   d_mode,
10428   d_mode,
10429   0,
10430   t_mode,
10431   0,
10432   t_mode,
10433   /* dc */
10434   q_mode,
10435   q_mode,
10436   q_mode,
10437   q_mode,
10438   q_mode,
10439   q_mode,
10440   q_mode,
10441   q_mode,
10442   /* dd */
10443   q_mode,
10444   q_mode,
10445   q_mode,
10446   q_mode,
10447   0,
10448   0,
10449   0,
10450   w_mode,
10451   /* de */
10452   w_mode,
10453   w_mode,
10454   w_mode,
10455   w_mode,
10456   w_mode,
10457   w_mode,
10458   w_mode,
10459   w_mode,
10460   /* df */
10461   w_mode,
10462   w_mode,
10463   w_mode,
10464   w_mode,
10465   t_mode,
10466   q_mode,
10467   t_mode,
10468   q_mode
10469 };
10470
10471 #define ST { OP_ST, 0 }
10472 #define STi { OP_STi, 0 }
10473
10474 #define FGRPd9_2 NULL, { { NULL, 0 } }
10475 #define FGRPd9_4 NULL, { { NULL, 1 } }
10476 #define FGRPd9_5 NULL, { { NULL, 2 } }
10477 #define FGRPd9_6 NULL, { { NULL, 3 } }
10478 #define FGRPd9_7 NULL, { { NULL, 4 } }
10479 #define FGRPda_5 NULL, { { NULL, 5 } }
10480 #define FGRPdb_4 NULL, { { NULL, 6 } }
10481 #define FGRPde_3 NULL, { { NULL, 7 } }
10482 #define FGRPdf_4 NULL, { { NULL, 8 } }
10483
10484 static const struct dis386 float_reg[][8] = {
10485   /* d8 */
10486   {
10487     { "fadd",   { ST, STi } },
10488     { "fmul",   { ST, STi } },
10489     { "fcom",   { STi } },
10490     { "fcomp",  { STi } },
10491     { "fsub",   { ST, STi } },
10492     { "fsubr",  { ST, STi } },
10493     { "fdiv",   { ST, STi } },
10494     { "fdivr",  { ST, STi } },
10495   },
10496   /* d9 */
10497   {
10498     { "fld",    { STi } },
10499     { "fxch",   { STi } },
10500     { FGRPd9_2 },
10501     { "(bad)",  { XX } },
10502     { FGRPd9_4 },
10503     { FGRPd9_5 },
10504     { FGRPd9_6 },
10505     { FGRPd9_7 },
10506   },
10507   /* da */
10508   {
10509     { "fcmovb", { ST, STi } },
10510     { "fcmove", { ST, STi } },
10511     { "fcmovbe",{ ST, STi } },
10512     { "fcmovu", { ST, STi } },
10513     { "(bad)",  { XX } },
10514     { FGRPda_5 },
10515     { "(bad)",  { XX } },
10516     { "(bad)",  { XX } },
10517   },
10518   /* db */
10519   {
10520     { "fcmovnb",{ ST, STi } },
10521     { "fcmovne",{ ST, STi } },
10522     { "fcmovnbe",{ ST, STi } },
10523     { "fcmovnu",{ ST, STi } },
10524     { FGRPdb_4 },
10525     { "fucomi", { ST, STi } },
10526     { "fcomi",  { ST, STi } },
10527     { "(bad)",  { XX } },
10528   },
10529   /* dc */
10530   {
10531     { "fadd",   { STi, ST } },
10532     { "fmul",   { STi, ST } },
10533     { "(bad)",  { XX } },
10534     { "(bad)",  { XX } },
10535     { "fsub!M", { STi, ST } },
10536     { "fsubM",  { STi, ST } },
10537     { "fdiv!M", { STi, ST } },
10538     { "fdivM",  { STi, ST } },
10539   },
10540   /* dd */
10541   {
10542     { "ffree",  { STi } },
10543     { "(bad)",  { XX } },
10544     { "fst",    { STi } },
10545     { "fstp",   { STi } },
10546     { "fucom",  { STi } },
10547     { "fucomp", { STi } },
10548     { "(bad)",  { XX } },
10549     { "(bad)",  { XX } },
10550   },
10551   /* de */
10552   {
10553     { "faddp",  { STi, ST } },
10554     { "fmulp",  { STi, ST } },
10555     { "(bad)",  { XX } },
10556     { FGRPde_3 },
10557     { "fsub!Mp", { STi, ST } },
10558     { "fsubMp", { STi, ST } },
10559     { "fdiv!Mp", { STi, ST } },
10560     { "fdivMp", { STi, ST } },
10561   },
10562   /* df */
10563   {
10564     { "ffreep", { STi } },
10565     { "(bad)",  { XX } },
10566     { "(bad)",  { XX } },
10567     { "(bad)",  { XX } },
10568     { FGRPdf_4 },
10569     { "fucomip", { ST, STi } },
10570     { "fcomip", { ST, STi } },
10571     { "(bad)",  { XX } },
10572   },
10573 };
10574
10575 static char *fgrps[][8] = {
10576   /* d9_2  0 */
10577   {
10578     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10579   },
10580
10581   /* d9_4  1 */
10582   {
10583     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10584   },
10585
10586   /* d9_5  2 */
10587   {
10588     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10589   },
10590
10591   /* d9_6  3 */
10592   {
10593     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10594   },
10595
10596   /* d9_7  4 */
10597   {
10598     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10599   },
10600
10601   /* da_5  5 */
10602   {
10603     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10604   },
10605
10606   /* db_4  6 */
10607   {
10608     "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10609     "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10610   },
10611
10612   /* de_3  7 */
10613   {
10614     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10615   },
10616
10617   /* df_4  8 */
10618   {
10619     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10620   },
10621 };
10622
10623 static void
10624 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10625                int sizeflag ATTRIBUTE_UNUSED)
10626 {
10627   /* Skip mod/rm byte.  */
10628   MODRM_CHECK;
10629   codep++;
10630 }
10631
10632 static void
10633 dofloat (int sizeflag)
10634 {
10635   const struct dis386 *dp;
10636   unsigned char floatop;
10637
10638   floatop = codep[-1];
10639
10640   if (modrm.mod != 3)
10641     {
10642       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10643
10644       putop (float_mem[fp_indx], sizeflag);
10645       obufp = op_out[0];
10646       op_ad = 2;
10647       OP_E (float_mem_mode[fp_indx], sizeflag);
10648       return;
10649     }
10650   /* Skip mod/rm byte.  */
10651   MODRM_CHECK;
10652   codep++;
10653
10654   dp = &float_reg[floatop - 0xd8][modrm.reg];
10655   if (dp->name == NULL)
10656     {
10657       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10658
10659       /* Instruction fnstsw is only one with strange arg.  */
10660       if (floatop == 0xdf && codep[-1] == 0xe0)
10661         strcpy (op_out[0], names16[0]);
10662     }
10663   else
10664     {
10665       putop (dp->name, sizeflag);
10666
10667       obufp = op_out[0];
10668       op_ad = 2;
10669       if (dp->op[0].rtn)
10670         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10671
10672       obufp = op_out[1];
10673       op_ad = 1;
10674       if (dp->op[1].rtn)
10675         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10676     }
10677 }
10678
10679 static void
10680 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10681 {
10682   oappend ("%st" + intel_syntax);
10683 }
10684
10685 static void
10686 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10687 {
10688   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10689   oappend (scratchbuf + intel_syntax);
10690 }
10691
10692 /* Capital letters in template are macros.  */
10693 static int
10694 putop (const char *template, int sizeflag)
10695 {
10696   const char *p;
10697   int alt = 0;
10698   int cond = 1;
10699   unsigned int l = 0, len = 1;
10700   char last[4];
10701
10702 #define SAVE_LAST(c)                    \
10703   if (l < len && l < sizeof (last))     \
10704     last[l++] = c;                      \
10705   else                                  \
10706     abort ();
10707
10708   for (p = template; *p; p++)
10709     {
10710       switch (*p)
10711         {
10712         default:
10713           *obufp++ = *p;
10714           break;
10715         case '%':
10716           len++;
10717           break;
10718         case '!':
10719           cond = 0;
10720           break;
10721         case '{':
10722           alt = 0;
10723           if (intel_syntax)
10724             {
10725               while (*++p != '|')
10726                 if (*p == '}' || *p == '\0')
10727                   abort ();
10728             }
10729           /* Fall through.  */
10730         case 'I':
10731           alt = 1;
10732           continue;
10733         case '|':
10734           while (*++p != '}')
10735             {
10736               if (*p == '\0')
10737                 abort ();
10738             }
10739           break;
10740         case '}':
10741           break;
10742         case 'A':
10743           if (intel_syntax)
10744             break;
10745           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10746             *obufp++ = 'b';
10747           break;
10748         case 'B':
10749           if (intel_syntax)
10750             break;
10751           if (sizeflag & SUFFIX_ALWAYS)
10752             *obufp++ = 'b';
10753           break;
10754         case 'C':
10755           if (intel_syntax && !alt)
10756             break;
10757           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10758             {
10759               if (sizeflag & DFLAG)
10760                 *obufp++ = intel_syntax ? 'd' : 'l';
10761               else
10762                 *obufp++ = intel_syntax ? 'w' : 's';
10763               used_prefixes |= (prefixes & PREFIX_DATA);
10764             }
10765           break;
10766         case 'D':
10767           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10768             break;
10769           USED_REX (REX_W);
10770           if (modrm.mod == 3)
10771             {
10772               if (rex & REX_W)
10773                 *obufp++ = 'q';
10774               else if (sizeflag & DFLAG)
10775                 *obufp++ = intel_syntax ? 'd' : 'l';
10776               else
10777                 *obufp++ = 'w';
10778               used_prefixes |= (prefixes & PREFIX_DATA);
10779             }
10780           else
10781             *obufp++ = 'w';
10782           break;
10783         case 'E':               /* For jcxz/jecxz */
10784           if (address_mode == mode_64bit)
10785             {
10786               if (sizeflag & AFLAG)
10787                 *obufp++ = 'r';
10788               else
10789                 *obufp++ = 'e';
10790             }
10791           else
10792             if (sizeflag & AFLAG)
10793               *obufp++ = 'e';
10794           used_prefixes |= (prefixes & PREFIX_ADDR);
10795           break;
10796         case 'F':
10797           if (intel_syntax)
10798             break;
10799           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10800             {
10801               if (sizeflag & AFLAG)
10802                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10803               else
10804                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10805               used_prefixes |= (prefixes & PREFIX_ADDR);
10806             }
10807           break;
10808         case 'G':
10809           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10810             break;
10811           if ((rex & REX_W) || (sizeflag & DFLAG))
10812             *obufp++ = 'l';
10813           else
10814             *obufp++ = 'w';
10815           if (!(rex & REX_W))
10816             used_prefixes |= (prefixes & PREFIX_DATA);
10817           break;
10818         case 'H':
10819           if (intel_syntax)
10820             break;
10821           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10822               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10823             {
10824               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10825               *obufp++ = ',';
10826               *obufp++ = 'p';
10827               if (prefixes & PREFIX_DS)
10828                 *obufp++ = 't';
10829               else
10830                 *obufp++ = 'n';
10831             }
10832           break;
10833         case 'J':
10834           if (intel_syntax)
10835             break;
10836           *obufp++ = 'l';
10837           break;
10838         case 'K':
10839           USED_REX (REX_W);
10840           if (rex & REX_W)
10841             *obufp++ = 'q';
10842           else
10843             *obufp++ = 'd';
10844           break;
10845         case 'Z':
10846           if (intel_syntax)
10847             break;
10848           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10849             {
10850               *obufp++ = 'q';
10851               break;
10852             }
10853           /* Fall through.  */
10854           goto case_L;
10855         case 'L':
10856           if (l != 0 || len != 1)
10857             {
10858               SAVE_LAST (*p);
10859               break;
10860             }
10861 case_L:
10862           if (intel_syntax)
10863             break;
10864           if (sizeflag & SUFFIX_ALWAYS)
10865             *obufp++ = 'l';
10866           break;
10867         case 'M':
10868           if (intel_mnemonic != cond)
10869             *obufp++ = 'r';
10870           break;
10871         case 'N':
10872           if ((prefixes & PREFIX_FWAIT) == 0)
10873             *obufp++ = 'n';
10874           else
10875             used_prefixes |= PREFIX_FWAIT;
10876           break;
10877         case 'O':
10878           USED_REX (REX_W);
10879           if (rex & REX_W)
10880             *obufp++ = 'o';
10881           else if (intel_syntax && (sizeflag & DFLAG))
10882             *obufp++ = 'q';
10883           else
10884             *obufp++ = 'd';
10885           if (!(rex & REX_W))
10886             used_prefixes |= (prefixes & PREFIX_DATA);
10887           break;
10888         case 'T':
10889           if (intel_syntax)
10890             break;
10891           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10892             {
10893               *obufp++ = 'q';
10894               break;
10895             }
10896           /* Fall through.  */
10897         case 'P':
10898           if (intel_syntax)
10899             break;
10900           if ((prefixes & PREFIX_DATA)
10901               || (rex & REX_W)
10902               || (sizeflag & SUFFIX_ALWAYS))
10903             {
10904               USED_REX (REX_W);
10905               if (rex & REX_W)
10906                 *obufp++ = 'q';
10907               else
10908                 {
10909                    if (sizeflag & DFLAG)
10910                       *obufp++ = 'l';
10911                    else
10912                      *obufp++ = 'w';
10913                 }
10914               used_prefixes |= (prefixes & PREFIX_DATA);
10915             }
10916           break;
10917         case 'U':
10918           if (intel_syntax)
10919             break;
10920           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10921             {
10922               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10923                 *obufp++ = 'q';
10924               break;
10925             }
10926           /* Fall through.  */
10927           goto case_Q;
10928         case 'Q':
10929           if (l == 0 && len == 1)
10930             {
10931 case_Q:
10932               if (intel_syntax && !alt)
10933                 break;
10934               USED_REX (REX_W);
10935               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10936                 {
10937                   if (rex & REX_W)
10938                     *obufp++ = 'q';
10939                   else
10940                     {
10941                       if (sizeflag & DFLAG)
10942                         *obufp++ = intel_syntax ? 'd' : 'l';
10943                       else
10944                         *obufp++ = 'w';
10945                     }
10946                   used_prefixes |= (prefixes & PREFIX_DATA);
10947                 }
10948             }
10949           else
10950             {
10951               if (l != 1 || len != 2 || last[0] != 'L')
10952                 {
10953                   SAVE_LAST (*p);
10954                   break;
10955                 }
10956               if (intel_syntax
10957                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
10958                 break;
10959               if ((rex & REX_W))
10960                 {
10961                   USED_REX (REX_W);
10962                   *obufp++ = 'q';
10963                 }
10964               else
10965                 *obufp++ = 'l';
10966             }
10967           break;
10968         case 'R':
10969           USED_REX (REX_W);
10970           if (rex & REX_W)
10971             *obufp++ = 'q';
10972           else if (sizeflag & DFLAG)
10973             {
10974               if (intel_syntax)
10975                   *obufp++ = 'd';
10976               else
10977                   *obufp++ = 'l';
10978             }
10979           else
10980             *obufp++ = 'w';
10981           if (intel_syntax && !p[1]
10982               && ((rex & REX_W) || (sizeflag & DFLAG)))
10983             *obufp++ = 'e';
10984           if (!(rex & REX_W))
10985             used_prefixes |= (prefixes & PREFIX_DATA);
10986           break;
10987         case 'V':
10988           if (intel_syntax)
10989             break;
10990           if (address_mode == mode_64bit && (sizeflag & DFLAG))
10991             {
10992               if (sizeflag & SUFFIX_ALWAYS)
10993                 *obufp++ = 'q';
10994               break;
10995             }
10996           /* Fall through.  */
10997         case 'S':
10998           if (intel_syntax)
10999             break;
11000           if (sizeflag & SUFFIX_ALWAYS)
11001             {
11002               if (rex & REX_W)
11003                 *obufp++ = 'q';
11004               else
11005                 {
11006                   if (sizeflag & DFLAG)
11007                     *obufp++ = 'l';
11008                   else
11009                     *obufp++ = 'w';
11010                   used_prefixes |= (prefixes & PREFIX_DATA);
11011                 }
11012             }
11013           break;
11014         case 'X':
11015           if (l != 0 || len != 1)
11016             {
11017               SAVE_LAST (*p);
11018               break;
11019             }
11020           if (need_vex && vex.prefix)
11021             {
11022               if (vex.prefix == DATA_PREFIX_OPCODE)
11023                 *obufp++ = 'd';
11024               else
11025                 *obufp++ = 's';
11026             }
11027           else if (prefixes & PREFIX_DATA)
11028             *obufp++ = 'd';
11029           else
11030             *obufp++ = 's';
11031           used_prefixes |= (prefixes & PREFIX_DATA);
11032           break;
11033         case 'Y':
11034           if (l == 0 && len == 1)
11035             {
11036               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11037                 break;
11038               if (rex & REX_W)
11039                 {
11040                   USED_REX (REX_W);
11041                   *obufp++ = 'q';
11042                 }
11043               break;
11044             }
11045           else
11046             {
11047               if (l != 1 || len != 2 || last[0] != 'X')
11048                 {
11049                   SAVE_LAST (*p);
11050                   break;
11051                 }
11052               if (!need_vex)
11053                 abort ();
11054               if (intel_syntax
11055                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11056                 break;
11057               switch (vex.length)
11058                 {
11059                 case 128:
11060                   *obufp++ = 'x';
11061                   break;
11062                 case 256:
11063                   *obufp++ = 'y';
11064                   break;
11065                 default:
11066                   abort ();
11067                 }
11068             }
11069           break;
11070           /* implicit operand size 'l' for i386 or 'q' for x86-64 */
11071         case 'W':
11072           /* operand size flag for cwtl, cbtw */
11073           USED_REX (REX_W);
11074           if (rex & REX_W)
11075             {
11076               if (intel_syntax)
11077                 *obufp++ = 'd';
11078               else
11079                 *obufp++ = 'l';
11080             }
11081           else if (sizeflag & DFLAG)
11082             *obufp++ = 'w';
11083           else
11084             *obufp++ = 'b';
11085           if (!(rex & REX_W))
11086             used_prefixes |= (prefixes & PREFIX_DATA);
11087           break;
11088         }
11089       alt = 0;
11090     }
11091   *obufp = 0;
11092   return 0;
11093 }
11094
11095 static void
11096 oappend (const char *s)
11097 {
11098   strcpy (obufp, s);
11099   obufp += strlen (s);
11100 }
11101
11102 static void
11103 append_seg (void)
11104 {
11105   if (prefixes & PREFIX_CS)
11106     {
11107       used_prefixes |= PREFIX_CS;
11108       oappend ("%cs:" + intel_syntax);
11109     }
11110   if (prefixes & PREFIX_DS)
11111     {
11112       used_prefixes |= PREFIX_DS;
11113       oappend ("%ds:" + intel_syntax);
11114     }
11115   if (prefixes & PREFIX_SS)
11116     {
11117       used_prefixes |= PREFIX_SS;
11118       oappend ("%ss:" + intel_syntax);
11119     }
11120   if (prefixes & PREFIX_ES)
11121     {
11122       used_prefixes |= PREFIX_ES;
11123       oappend ("%es:" + intel_syntax);
11124     }
11125   if (prefixes & PREFIX_FS)
11126     {
11127       used_prefixes |= PREFIX_FS;
11128       oappend ("%fs:" + intel_syntax);
11129     }
11130   if (prefixes & PREFIX_GS)
11131     {
11132       used_prefixes |= PREFIX_GS;
11133       oappend ("%gs:" + intel_syntax);
11134     }
11135 }
11136
11137 static void
11138 OP_indirE (int bytemode, int sizeflag)
11139 {
11140   if (!intel_syntax)
11141     oappend ("*");
11142   OP_E (bytemode, sizeflag);
11143 }
11144
11145 static void
11146 print_operand_value (char *buf, int hex, bfd_vma disp)
11147 {
11148   if (address_mode == mode_64bit)
11149     {
11150       if (hex)
11151         {
11152           char tmp[30];
11153           int i;
11154           buf[0] = '0';
11155           buf[1] = 'x';
11156           sprintf_vma (tmp, disp);
11157           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11158           strcpy (buf + 2, tmp + i);
11159         }
11160       else
11161         {
11162           bfd_signed_vma v = disp;
11163           char tmp[30];
11164           int i;
11165           if (v < 0)
11166             {
11167               *(buf++) = '-';
11168               v = -disp;
11169               /* Check for possible overflow on 0x8000000000000000.  */
11170               if (v < 0)
11171                 {
11172                   strcpy (buf, "9223372036854775808");
11173                   return;
11174                 }
11175             }
11176           if (!v)
11177             {
11178               strcpy (buf, "0");
11179               return;
11180             }
11181
11182           i = 0;
11183           tmp[29] = 0;
11184           while (v)
11185             {
11186               tmp[28 - i] = (v % 10) + '0';
11187               v /= 10;
11188               i++;
11189             }
11190           strcpy (buf, tmp + 29 - i);
11191         }
11192     }
11193   else
11194     {
11195       if (hex)
11196         sprintf (buf, "0x%x", (unsigned int) disp);
11197       else
11198         sprintf (buf, "%d", (int) disp);
11199     }
11200 }
11201
11202 /* Put DISP in BUF as signed hex number.  */
11203
11204 static void
11205 print_displacement (char *buf, bfd_vma disp)
11206 {
11207   bfd_signed_vma val = disp;
11208   char tmp[30];
11209   int i, j = 0;
11210
11211   if (val < 0)
11212     {
11213       buf[j++] = '-';
11214       val = -disp;
11215
11216       /* Check for possible overflow.  */
11217       if (val < 0)
11218         {
11219           switch (address_mode)
11220             {
11221             case mode_64bit:
11222               strcpy (buf + j, "0x8000000000000000");
11223               break;
11224             case mode_32bit:
11225               strcpy (buf + j, "0x80000000");
11226               break;
11227             case mode_16bit:
11228               strcpy (buf + j, "0x8000");
11229               break;
11230             }
11231           return;
11232         }
11233     }
11234
11235   buf[j++] = '0';
11236   buf[j++] = 'x';
11237
11238   sprintf_vma (tmp, (bfd_vma) val);
11239   for (i = 0; tmp[i] == '0'; i++)
11240     continue;
11241   if (tmp[i] == '\0')
11242     i--;
11243   strcpy (buf + j, tmp + i);
11244 }
11245
11246 static void
11247 intel_operand_size (int bytemode, int sizeflag)
11248 {
11249   switch (bytemode)
11250     {
11251     case b_mode:
11252     case dqb_mode:
11253       oappend ("BYTE PTR ");
11254       break;
11255     case w_mode:
11256     case dqw_mode:
11257       oappend ("WORD PTR ");
11258       break;
11259     case stack_v_mode:
11260       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11261         {
11262           oappend ("QWORD PTR ");
11263           used_prefixes |= (prefixes & PREFIX_DATA);
11264           break;
11265         }
11266       /* FALLTHRU */
11267     case v_mode:
11268     case dq_mode:
11269       USED_REX (REX_W);
11270       if (rex & REX_W)
11271         oappend ("QWORD PTR ");
11272       else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11273         oappend ("DWORD PTR ");
11274       else
11275         oappend ("WORD PTR ");
11276       used_prefixes |= (prefixes & PREFIX_DATA);
11277       break;
11278     case z_mode:
11279       if ((rex & REX_W) || (sizeflag & DFLAG))
11280         *obufp++ = 'D';
11281       oappend ("WORD PTR ");
11282       if (!(rex & REX_W))
11283         used_prefixes |= (prefixes & PREFIX_DATA);
11284       break;
11285     case a_mode:
11286       if (sizeflag & DFLAG)
11287         oappend ("QWORD PTR ");
11288       else
11289         oappend ("DWORD PTR ");
11290       used_prefixes |= (prefixes & PREFIX_DATA);
11291       break;
11292     case d_mode:
11293     case dqd_mode:
11294       oappend ("DWORD PTR ");
11295       break;
11296     case q_mode:
11297       oappend ("QWORD PTR ");
11298       break;
11299     case m_mode:
11300       if (address_mode == mode_64bit)
11301         oappend ("QWORD PTR ");
11302       else
11303         oappend ("DWORD PTR ");
11304       break;
11305     case f_mode:
11306       if (sizeflag & DFLAG)
11307         oappend ("FWORD PTR ");
11308       else
11309         oappend ("DWORD PTR ");
11310       used_prefixes |= (prefixes & PREFIX_DATA);
11311       break;
11312     case t_mode:
11313       oappend ("TBYTE PTR ");
11314       break;
11315     case x_mode:
11316       if (need_vex)
11317         {
11318           switch (vex.length)
11319             {
11320             case 128:
11321               oappend ("XMMWORD PTR ");
11322               break;
11323             case 256:
11324               oappend ("YMMWORD PTR ");
11325               break;
11326             default:
11327               abort ();
11328             }
11329         }
11330       else
11331         oappend ("XMMWORD PTR ");
11332       break;
11333     case xmm_mode:
11334       oappend ("XMMWORD PTR ");
11335       break;
11336     case xmmq_mode:
11337       if (!need_vex)
11338         abort ();
11339
11340       switch (vex.length)
11341         {
11342         case 128:
11343           oappend ("QWORD PTR ");
11344           break;
11345         case 256:
11346           oappend ("XMMWORD PTR ");
11347           break;
11348         default:
11349           abort ();
11350         }
11351       break;
11352     case ymmq_mode:
11353       if (!need_vex)
11354         abort ();
11355
11356       switch (vex.length)
11357         {
11358         case 128:
11359           oappend ("QWORD PTR ");
11360           break;
11361         case 256:
11362           oappend ("YMMWORD PTR ");
11363           break;
11364         default:
11365           abort ();
11366         }
11367       break;
11368     case o_mode:
11369       oappend ("OWORD PTR ");
11370       break;
11371     default:
11372       break;
11373     }
11374 }
11375
11376 static void
11377 OP_E_register (int bytemode, int sizeflag)
11378 {
11379   int reg = modrm.rm;
11380   const char **names;
11381
11382   USED_REX (REX_B);
11383   if ((rex & REX_B))
11384     reg += 8;
11385
11386   switch (bytemode)
11387     {
11388     case b_mode:
11389       USED_REX (0);
11390       if (rex)
11391         names = names8rex;
11392       else
11393         names = names8;
11394       break;
11395     case w_mode:
11396       names = names16;
11397       break;
11398     case d_mode:
11399       names = names32;
11400       break;
11401     case q_mode:
11402       names = names64;
11403       break;
11404     case m_mode:
11405       names = address_mode == mode_64bit ? names64 : names32;
11406       break;
11407     case stack_v_mode:
11408       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11409         {
11410           names = names64;
11411           used_prefixes |= (prefixes & PREFIX_DATA);
11412           break;
11413         }
11414       bytemode = v_mode;
11415       /* FALLTHRU */
11416     case v_mode:
11417     case dq_mode:
11418     case dqb_mode:
11419     case dqd_mode:
11420     case dqw_mode:
11421       USED_REX (REX_W);
11422       if (rex & REX_W)
11423         names = names64;
11424       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11425         names = names32;
11426       else
11427         names = names16;
11428       used_prefixes |= (prefixes & PREFIX_DATA);
11429       break;
11430     case 0:
11431       return;
11432     default:
11433       oappend (INTERNAL_DISASSEMBLER_ERROR);
11434       return;
11435     }
11436   oappend (names[reg]);
11437 }
11438
11439 static void
11440 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11441 {
11442   bfd_vma disp = 0;
11443   int add = (rex & REX_B) ? 8 : 0;
11444   int riprel = 0;
11445
11446   USED_REX (REX_B);
11447   if (intel_syntax)
11448     intel_operand_size (bytemode, sizeflag);
11449   append_seg ();
11450
11451   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11452     {
11453       /* 32/64 bit address mode */
11454       int havedisp;
11455       int havesib;
11456       int havebase;
11457       int haveindex;
11458       int needindex;
11459       int base, rbase;
11460       int index = 0;
11461       int scale = 0;
11462
11463       havesib = 0;
11464       havebase = 1;
11465       haveindex = 0;
11466       base = modrm.rm;
11467
11468       if (base == 4)
11469         {
11470           havesib = 1;
11471           FETCH_DATA (the_info, codep + 1);
11472           index = (*codep >> 3) & 7;
11473           scale = (*codep >> 6) & 3;
11474           base = *codep & 7;
11475           USED_REX (REX_X);
11476           if (rex & REX_X)
11477             index += 8;
11478           haveindex = index != 4;
11479           codep++;
11480         }
11481       rbase = base + add;
11482
11483       /* If we have a DREX byte, skip it now
11484          (it has already been handled) */
11485       if (has_drex)
11486         {
11487           FETCH_DATA (the_info, codep + 1);
11488           codep++;
11489         }
11490
11491       switch (modrm.mod)
11492         {
11493         case 0:
11494           if (base == 5)
11495             {
11496               havebase = 0;
11497               if (address_mode == mode_64bit && !havesib)
11498                 riprel = 1;
11499               disp = get32s ();
11500             }
11501           break;
11502         case 1:
11503           FETCH_DATA (the_info, codep + 1);
11504           disp = *codep++;
11505           if ((disp & 0x80) != 0)
11506             disp -= 0x100;
11507           break;
11508         case 2:
11509           disp = get32s ();
11510           break;
11511         }
11512
11513       /* In 32bit mode, we need index register to tell [offset] from
11514          [eiz*1 + offset].  */
11515       needindex = (havesib
11516                    && !havebase
11517                    && !haveindex
11518                    && address_mode == mode_32bit);
11519       havedisp = (havebase
11520                   || needindex
11521                   || (havesib && (haveindex || scale != 0)));
11522
11523       if (!intel_syntax)
11524         if (modrm.mod != 0 || base == 5)
11525           {
11526             if (havedisp || riprel)
11527               print_displacement (scratchbuf, disp);
11528             else
11529               print_operand_value (scratchbuf, 1, disp);
11530             oappend (scratchbuf);
11531             if (riprel)
11532               {
11533                 set_op (disp, 1);
11534                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11535               }
11536           }
11537
11538       if (havebase || haveindex || riprel)
11539         used_prefixes |= PREFIX_ADDR;
11540
11541       if (havedisp || (intel_syntax && riprel))
11542         {
11543           *obufp++ = open_char;
11544           if (intel_syntax && riprel)
11545             {
11546               set_op (disp, 1);
11547               oappend (sizeflag & AFLAG ? "rip" : "eip");
11548             }
11549           *obufp = '\0';
11550           if (havebase)
11551             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11552                      ? names64[rbase] : names32[rbase]);
11553           if (havesib)
11554             {
11555               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11556                  print index to tell base + index from base.  */
11557               if (scale != 0
11558                   || needindex
11559                   || haveindex
11560                   || (havebase && base != ESP_REG_NUM))
11561                 {
11562                   if (!intel_syntax || havebase)
11563                     {
11564                       *obufp++ = separator_char;
11565                       *obufp = '\0';
11566                     }
11567                   if (haveindex)
11568                     oappend (address_mode == mode_64bit
11569                              && (sizeflag & AFLAG)
11570                              ? names64[index] : names32[index]);
11571                   else
11572                     oappend (address_mode == mode_64bit
11573                              && (sizeflag & AFLAG)
11574                              ? index64 : index32);
11575
11576                   *obufp++ = scale_char;
11577                   *obufp = '\0';
11578                   sprintf (scratchbuf, "%d", 1 << scale);
11579                   oappend (scratchbuf);
11580                 }
11581             }
11582           if (intel_syntax
11583               && (disp || modrm.mod != 0 || base == 5))
11584             {
11585               if (!havedisp || (bfd_signed_vma) disp >= 0)
11586                 {
11587                   *obufp++ = '+';
11588                   *obufp = '\0';
11589                 }
11590               else if (modrm.mod != 1)
11591                 {
11592                   *obufp++ = '-';
11593                   *obufp = '\0';
11594                   disp = - (bfd_signed_vma) disp;
11595                 }
11596
11597               if (havedisp)
11598                 print_displacement (scratchbuf, disp);
11599               else
11600                 print_operand_value (scratchbuf, 1, disp);
11601               oappend (scratchbuf);
11602             }
11603
11604           *obufp++ = close_char;
11605           *obufp = '\0';
11606         }
11607       else if (intel_syntax)
11608         {
11609           if (modrm.mod != 0 || base == 5)
11610             {
11611               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11612                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11613                 ;
11614               else
11615                 {
11616                   oappend (names_seg[ds_reg - es_reg]);
11617                   oappend (":");
11618                 }
11619               print_operand_value (scratchbuf, 1, disp);
11620               oappend (scratchbuf);
11621             }
11622         }
11623     }
11624   else
11625     { /* 16 bit address mode */
11626       switch (modrm.mod)
11627         {
11628         case 0:
11629           if (modrm.rm == 6)
11630             {
11631               disp = get16 ();
11632               if ((disp & 0x8000) != 0)
11633                 disp -= 0x10000;
11634             }
11635           break;
11636         case 1:
11637           FETCH_DATA (the_info, codep + 1);
11638           disp = *codep++;
11639           if ((disp & 0x80) != 0)
11640             disp -= 0x100;
11641           break;
11642         case 2:
11643           disp = get16 ();
11644           if ((disp & 0x8000) != 0)
11645             disp -= 0x10000;
11646           break;
11647         }
11648
11649       if (!intel_syntax)
11650         if (modrm.mod != 0 || modrm.rm == 6)
11651           {
11652             print_displacement (scratchbuf, disp);
11653             oappend (scratchbuf);
11654           }
11655
11656       if (modrm.mod != 0 || modrm.rm != 6)
11657         {
11658           *obufp++ = open_char;
11659           *obufp = '\0';
11660           oappend (index16[modrm.rm]);
11661           if (intel_syntax
11662               && (disp || modrm.mod != 0 || modrm.rm == 6))
11663             {
11664               if ((bfd_signed_vma) disp >= 0)
11665                 {
11666                   *obufp++ = '+';
11667                   *obufp = '\0';
11668                 }
11669               else if (modrm.mod != 1)
11670                 {
11671                   *obufp++ = '-';
11672                   *obufp = '\0';
11673                   disp = - (bfd_signed_vma) disp;
11674                 }
11675
11676               print_displacement (scratchbuf, disp);
11677               oappend (scratchbuf);
11678             }
11679
11680           *obufp++ = close_char;
11681           *obufp = '\0';
11682         }
11683       else if (intel_syntax)
11684         {
11685           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11686                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11687             ;
11688           else
11689             {
11690               oappend (names_seg[ds_reg - es_reg]);
11691               oappend (":");
11692             }
11693           print_operand_value (scratchbuf, 1, disp & 0xffff);
11694           oappend (scratchbuf);
11695         }
11696     }
11697 }
11698
11699 static void
11700 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11701 {
11702   /* Skip mod/rm byte.  */
11703   MODRM_CHECK;
11704   codep++;
11705
11706   if (modrm.mod == 3)
11707     OP_E_register (bytemode, sizeflag);
11708   else
11709     OP_E_memory (bytemode, sizeflag, has_drex);
11710 }
11711
11712 static void
11713 OP_E (int bytemode, int sizeflag)
11714 {
11715   OP_E_extended (bytemode, sizeflag, 0);
11716 }
11717
11718
11719 static void
11720 OP_G (int bytemode, int sizeflag)
11721 {
11722   int add = 0;
11723   USED_REX (REX_R);
11724   if (rex & REX_R)
11725     add += 8;
11726   switch (bytemode)
11727     {
11728     case b_mode:
11729       USED_REX (0);
11730       if (rex)
11731         oappend (names8rex[modrm.reg + add]);
11732       else
11733         oappend (names8[modrm.reg + add]);
11734       break;
11735     case w_mode:
11736       oappend (names16[modrm.reg + add]);
11737       break;
11738     case d_mode:
11739       oappend (names32[modrm.reg + add]);
11740       break;
11741     case q_mode:
11742       oappend (names64[modrm.reg + add]);
11743       break;
11744     case v_mode:
11745     case dq_mode:
11746     case dqb_mode:
11747     case dqd_mode:
11748     case dqw_mode:
11749       USED_REX (REX_W);
11750       if (rex & REX_W)
11751         oappend (names64[modrm.reg + add]);
11752       else if ((sizeflag & DFLAG) || bytemode != v_mode)
11753         oappend (names32[modrm.reg + add]);
11754       else
11755         oappend (names16[modrm.reg + add]);
11756       used_prefixes |= (prefixes & PREFIX_DATA);
11757       break;
11758     case m_mode:
11759       if (address_mode == mode_64bit)
11760         oappend (names64[modrm.reg + add]);
11761       else
11762         oappend (names32[modrm.reg + add]);
11763       break;
11764     default:
11765       oappend (INTERNAL_DISASSEMBLER_ERROR);
11766       break;
11767     }
11768 }
11769
11770 static bfd_vma
11771 get64 (void)
11772 {
11773   bfd_vma x;
11774 #ifdef BFD64
11775   unsigned int a;
11776   unsigned int b;
11777
11778   FETCH_DATA (the_info, codep + 8);
11779   a = *codep++ & 0xff;
11780   a |= (*codep++ & 0xff) << 8;
11781   a |= (*codep++ & 0xff) << 16;
11782   a |= (*codep++ & 0xff) << 24;
11783   b = *codep++ & 0xff;
11784   b |= (*codep++ & 0xff) << 8;
11785   b |= (*codep++ & 0xff) << 16;
11786   b |= (*codep++ & 0xff) << 24;
11787   x = a + ((bfd_vma) b << 32);
11788 #else
11789   abort ();
11790   x = 0;
11791 #endif
11792   return x;
11793 }
11794
11795 static bfd_signed_vma
11796 get32 (void)
11797 {
11798   bfd_signed_vma x = 0;
11799
11800   FETCH_DATA (the_info, codep + 4);
11801   x = *codep++ & (bfd_signed_vma) 0xff;
11802   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11803   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11804   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11805   return x;
11806 }
11807
11808 static bfd_signed_vma
11809 get32s (void)
11810 {
11811   bfd_signed_vma x = 0;
11812
11813   FETCH_DATA (the_info, codep + 4);
11814   x = *codep++ & (bfd_signed_vma) 0xff;
11815   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11816   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11817   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11818
11819   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11820
11821   return x;
11822 }
11823
11824 static int
11825 get16 (void)
11826 {
11827   int x = 0;
11828
11829   FETCH_DATA (the_info, codep + 2);
11830   x = *codep++ & 0xff;
11831   x |= (*codep++ & 0xff) << 8;
11832   return x;
11833 }
11834
11835 static void
11836 set_op (bfd_vma op, int riprel)
11837 {
11838   op_index[op_ad] = op_ad;
11839   if (address_mode == mode_64bit)
11840     {
11841       op_address[op_ad] = op;
11842       op_riprel[op_ad] = riprel;
11843     }
11844   else
11845     {
11846       /* Mask to get a 32-bit address.  */
11847       op_address[op_ad] = op & 0xffffffff;
11848       op_riprel[op_ad] = riprel & 0xffffffff;
11849     }
11850 }
11851
11852 static void
11853 OP_REG (int code, int sizeflag)
11854 {
11855   const char *s;
11856   int add;
11857   USED_REX (REX_B);
11858   if (rex & REX_B)
11859     add = 8;
11860   else
11861     add = 0;
11862
11863   switch (code)
11864     {
11865     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11866     case sp_reg: case bp_reg: case si_reg: case di_reg:
11867       s = names16[code - ax_reg + add];
11868       break;
11869     case es_reg: case ss_reg: case cs_reg:
11870     case ds_reg: case fs_reg: case gs_reg:
11871       s = names_seg[code - es_reg + add];
11872       break;
11873     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11874     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11875       USED_REX (0);
11876       if (rex)
11877         s = names8rex[code - al_reg + add];
11878       else
11879         s = names8[code - al_reg];
11880       break;
11881     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
11882     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
11883       if (address_mode == mode_64bit && (sizeflag & DFLAG))
11884         {
11885           s = names64[code - rAX_reg + add];
11886           break;
11887         }
11888       code += eAX_reg - rAX_reg;
11889       /* Fall through.  */
11890     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11891     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11892       USED_REX (REX_W);
11893       if (rex & REX_W)
11894         s = names64[code - eAX_reg + add];
11895       else if (sizeflag & DFLAG)
11896         s = names32[code - eAX_reg + add];
11897       else
11898         s = names16[code - eAX_reg + add];
11899       used_prefixes |= (prefixes & PREFIX_DATA);
11900       break;
11901     default:
11902       s = INTERNAL_DISASSEMBLER_ERROR;
11903       break;
11904     }
11905   oappend (s);
11906 }
11907
11908 static void
11909 OP_IMREG (int code, int sizeflag)
11910 {
11911   const char *s;
11912
11913   switch (code)
11914     {
11915     case indir_dx_reg:
11916       if (intel_syntax)
11917         s = "dx";
11918       else
11919         s = "(%dx)";
11920       break;
11921     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
11922     case sp_reg: case bp_reg: case si_reg: case di_reg:
11923       s = names16[code - ax_reg];
11924       break;
11925     case es_reg: case ss_reg: case cs_reg:
11926     case ds_reg: case fs_reg: case gs_reg:
11927       s = names_seg[code - es_reg];
11928       break;
11929     case al_reg: case ah_reg: case cl_reg: case ch_reg:
11930     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
11931       USED_REX (0);
11932       if (rex)
11933         s = names8rex[code - al_reg];
11934       else
11935         s = names8[code - al_reg];
11936       break;
11937     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
11938     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
11939       USED_REX (REX_W);
11940       if (rex & REX_W)
11941         s = names64[code - eAX_reg];
11942       else if (sizeflag & DFLAG)
11943         s = names32[code - eAX_reg];
11944       else
11945         s = names16[code - eAX_reg];
11946       used_prefixes |= (prefixes & PREFIX_DATA);
11947       break;
11948     case z_mode_ax_reg:
11949       if ((rex & REX_W) || (sizeflag & DFLAG))
11950         s = *names32;
11951       else
11952         s = *names16;
11953       if (!(rex & REX_W))
11954         used_prefixes |= (prefixes & PREFIX_DATA);
11955       break;
11956     default:
11957       s = INTERNAL_DISASSEMBLER_ERROR;
11958       break;
11959     }
11960   oappend (s);
11961 }
11962
11963 static void
11964 OP_I (int bytemode, int sizeflag)
11965 {
11966   bfd_signed_vma op;
11967   bfd_signed_vma mask = -1;
11968
11969   switch (bytemode)
11970     {
11971     case b_mode:
11972       FETCH_DATA (the_info, codep + 1);
11973       op = *codep++;
11974       mask = 0xff;
11975       break;
11976     case q_mode:
11977       if (address_mode == mode_64bit)
11978         {
11979           op = get32s ();
11980           break;
11981         }
11982       /* Fall through.  */
11983     case v_mode:
11984       USED_REX (REX_W);
11985       if (rex & REX_W)
11986         op = get32s ();
11987       else if (sizeflag & DFLAG)
11988         {
11989           op = get32 ();
11990           mask = 0xffffffff;
11991         }
11992       else
11993         {
11994           op = get16 ();
11995           mask = 0xfffff;
11996         }
11997       used_prefixes |= (prefixes & PREFIX_DATA);
11998       break;
11999     case w_mode:
12000       mask = 0xfffff;
12001       op = get16 ();
12002       break;
12003     case const_1_mode:
12004       if (intel_syntax)
12005         oappend ("1");
12006       return;
12007     default:
12008       oappend (INTERNAL_DISASSEMBLER_ERROR);
12009       return;
12010     }
12011
12012   op &= mask;
12013   scratchbuf[0] = '$';
12014   print_operand_value (scratchbuf + 1, 1, op);
12015   oappend (scratchbuf + intel_syntax);
12016   scratchbuf[0] = '\0';
12017 }
12018
12019 static void
12020 OP_I64 (int bytemode, int sizeflag)
12021 {
12022   bfd_signed_vma op;
12023   bfd_signed_vma mask = -1;
12024
12025   if (address_mode != mode_64bit)
12026     {
12027       OP_I (bytemode, sizeflag);
12028       return;
12029     }
12030
12031   switch (bytemode)
12032     {
12033     case b_mode:
12034       FETCH_DATA (the_info, codep + 1);
12035       op = *codep++;
12036       mask = 0xff;
12037       break;
12038     case v_mode:
12039       USED_REX (REX_W);
12040       if (rex & REX_W)
12041         op = get64 ();
12042       else if (sizeflag & DFLAG)
12043         {
12044           op = get32 ();
12045           mask = 0xffffffff;
12046         }
12047       else
12048         {
12049           op = get16 ();
12050           mask = 0xfffff;
12051         }
12052       used_prefixes |= (prefixes & PREFIX_DATA);
12053       break;
12054     case w_mode:
12055       mask = 0xfffff;
12056       op = get16 ();
12057       break;
12058     default:
12059       oappend (INTERNAL_DISASSEMBLER_ERROR);
12060       return;
12061     }
12062
12063   op &= mask;
12064   scratchbuf[0] = '$';
12065   print_operand_value (scratchbuf + 1, 1, op);
12066   oappend (scratchbuf + intel_syntax);
12067   scratchbuf[0] = '\0';
12068 }
12069
12070 static void
12071 OP_sI (int bytemode, int sizeflag)
12072 {
12073   bfd_signed_vma op;
12074   bfd_signed_vma mask = -1;
12075
12076   switch (bytemode)
12077     {
12078     case b_mode:
12079       FETCH_DATA (the_info, codep + 1);
12080       op = *codep++;
12081       if ((op & 0x80) != 0)
12082         op -= 0x100;
12083       mask = 0xffffffff;
12084       break;
12085     case v_mode:
12086       USED_REX (REX_W);
12087       if (rex & REX_W)
12088         op = get32s ();
12089       else if (sizeflag & DFLAG)
12090         {
12091           op = get32s ();
12092           mask = 0xffffffff;
12093         }
12094       else
12095         {
12096           mask = 0xffffffff;
12097           op = get16 ();
12098           if ((op & 0x8000) != 0)
12099             op -= 0x10000;
12100         }
12101       used_prefixes |= (prefixes & PREFIX_DATA);
12102       break;
12103     case w_mode:
12104       op = get16 ();
12105       mask = 0xffffffff;
12106       if ((op & 0x8000) != 0)
12107         op -= 0x10000;
12108       break;
12109     default:
12110       oappend (INTERNAL_DISASSEMBLER_ERROR);
12111       return;
12112     }
12113
12114   scratchbuf[0] = '$';
12115   print_operand_value (scratchbuf + 1, 1, op);
12116   oappend (scratchbuf + intel_syntax);
12117 }
12118
12119 static void
12120 OP_J (int bytemode, int sizeflag)
12121 {
12122   bfd_vma disp;
12123   bfd_vma mask = -1;
12124   bfd_vma segment = 0;
12125
12126   switch (bytemode)
12127     {
12128     case b_mode:
12129       FETCH_DATA (the_info, codep + 1);
12130       disp = *codep++;
12131       if ((disp & 0x80) != 0)
12132         disp -= 0x100;
12133       break;
12134     case v_mode:
12135       if ((sizeflag & DFLAG) || (rex & REX_W))
12136         disp = get32s ();
12137       else
12138         {
12139           disp = get16 ();
12140           if ((disp & 0x8000) != 0)
12141             disp -= 0x10000;
12142           /* In 16bit mode, address is wrapped around at 64k within
12143              the same segment.  Otherwise, a data16 prefix on a jump
12144              instruction means that the pc is masked to 16 bits after
12145              the displacement is added!  */
12146           mask = 0xffff;
12147           if ((prefixes & PREFIX_DATA) == 0)
12148             segment = ((start_pc + codep - start_codep)
12149                        & ~((bfd_vma) 0xffff));
12150         }
12151       used_prefixes |= (prefixes & PREFIX_DATA);
12152       break;
12153     default:
12154       oappend (INTERNAL_DISASSEMBLER_ERROR);
12155       return;
12156     }
12157   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12158   set_op (disp, 0);
12159   print_operand_value (scratchbuf, 1, disp);
12160   oappend (scratchbuf);
12161 }
12162
12163 static void
12164 OP_SEG (int bytemode, int sizeflag)
12165 {
12166   if (bytemode == w_mode)
12167     oappend (names_seg[modrm.reg]);
12168   else
12169     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12170 }
12171
12172 static void
12173 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12174 {
12175   int seg, offset;
12176
12177   if (sizeflag & DFLAG)
12178     {
12179       offset = get32 ();
12180       seg = get16 ();
12181     }
12182   else
12183     {
12184       offset = get16 ();
12185       seg = get16 ();
12186     }
12187   used_prefixes |= (prefixes & PREFIX_DATA);
12188   if (intel_syntax)
12189     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12190   else
12191     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12192   oappend (scratchbuf);
12193 }
12194
12195 static void
12196 OP_OFF (int bytemode, int sizeflag)
12197 {
12198   bfd_vma off;
12199
12200   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12201     intel_operand_size (bytemode, sizeflag);
12202   append_seg ();
12203
12204   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12205     off = get32 ();
12206   else
12207     off = get16 ();
12208
12209   if (intel_syntax)
12210     {
12211       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12212                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12213         {
12214           oappend (names_seg[ds_reg - es_reg]);
12215           oappend (":");
12216         }
12217     }
12218   print_operand_value (scratchbuf, 1, off);
12219   oappend (scratchbuf);
12220 }
12221
12222 static void
12223 OP_OFF64 (int bytemode, int sizeflag)
12224 {
12225   bfd_vma off;
12226
12227   if (address_mode != mode_64bit
12228       || (prefixes & PREFIX_ADDR))
12229     {
12230       OP_OFF (bytemode, sizeflag);
12231       return;
12232     }
12233
12234   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12235     intel_operand_size (bytemode, sizeflag);
12236   append_seg ();
12237
12238   off = get64 ();
12239
12240   if (intel_syntax)
12241     {
12242       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12243                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12244         {
12245           oappend (names_seg[ds_reg - es_reg]);
12246           oappend (":");
12247         }
12248     }
12249   print_operand_value (scratchbuf, 1, off);
12250   oappend (scratchbuf);
12251 }
12252
12253 static void
12254 ptr_reg (int code, int sizeflag)
12255 {
12256   const char *s;
12257
12258   *obufp++ = open_char;
12259   used_prefixes |= (prefixes & PREFIX_ADDR);
12260   if (address_mode == mode_64bit)
12261     {
12262       if (!(sizeflag & AFLAG))
12263         s = names32[code - eAX_reg];
12264       else
12265         s = names64[code - eAX_reg];
12266     }
12267   else if (sizeflag & AFLAG)
12268     s = names32[code - eAX_reg];
12269   else
12270     s = names16[code - eAX_reg];
12271   oappend (s);
12272   *obufp++ = close_char;
12273   *obufp = 0;
12274 }
12275
12276 static void
12277 OP_ESreg (int code, int sizeflag)
12278 {
12279   if (intel_syntax)
12280     {
12281       switch (codep[-1])
12282         {
12283         case 0x6d:      /* insw/insl */
12284           intel_operand_size (z_mode, sizeflag);
12285           break;
12286         case 0xa5:      /* movsw/movsl/movsq */
12287         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12288         case 0xab:      /* stosw/stosl */
12289         case 0xaf:      /* scasw/scasl */
12290           intel_operand_size (v_mode, sizeflag);
12291           break;
12292         default:
12293           intel_operand_size (b_mode, sizeflag);
12294         }
12295     }
12296   oappend ("%es:" + intel_syntax);
12297   ptr_reg (code, sizeflag);
12298 }
12299
12300 static void
12301 OP_DSreg (int code, int sizeflag)
12302 {
12303   if (intel_syntax)
12304     {
12305       switch (codep[-1])
12306         {
12307         case 0x6f:      /* outsw/outsl */
12308           intel_operand_size (z_mode, sizeflag);
12309           break;
12310         case 0xa5:      /* movsw/movsl/movsq */
12311         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12312         case 0xad:      /* lodsw/lodsl/lodsq */
12313           intel_operand_size (v_mode, sizeflag);
12314           break;
12315         default:
12316           intel_operand_size (b_mode, sizeflag);
12317         }
12318     }
12319   if ((prefixes
12320        & (PREFIX_CS
12321           | PREFIX_DS
12322           | PREFIX_SS
12323           | PREFIX_ES
12324           | PREFIX_FS
12325           | PREFIX_GS)) == 0)
12326     prefixes |= PREFIX_DS;
12327   append_seg ();
12328   ptr_reg (code, sizeflag);
12329 }
12330
12331 static void
12332 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12333 {
12334   int add;
12335   if (rex & REX_R)
12336     {
12337       USED_REX (REX_R);
12338       add = 8;
12339     }
12340   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12341     {
12342       lock_prefix = NULL;
12343       used_prefixes |= PREFIX_LOCK;
12344       add = 8;
12345     }
12346   else
12347     add = 0;
12348   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12349   oappend (scratchbuf + intel_syntax);
12350 }
12351
12352 static void
12353 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12354 {
12355   int add;
12356   USED_REX (REX_R);
12357   if (rex & REX_R)
12358     add = 8;
12359   else
12360     add = 0;
12361   if (intel_syntax)
12362     sprintf (scratchbuf, "db%d", modrm.reg + add);
12363   else
12364     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12365   oappend (scratchbuf);
12366 }
12367
12368 static void
12369 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12370 {
12371   sprintf (scratchbuf, "%%tr%d", modrm.reg);
12372   oappend (scratchbuf + intel_syntax);
12373 }
12374
12375 static void
12376 OP_R (int bytemode, int sizeflag)
12377 {
12378   if (modrm.mod == 3)
12379     OP_E (bytemode, sizeflag);
12380   else
12381     BadOp ();
12382 }
12383
12384 static void
12385 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12386 {
12387   used_prefixes |= (prefixes & PREFIX_DATA);
12388   if (prefixes & PREFIX_DATA)
12389     {
12390       int add;
12391       USED_REX (REX_R);
12392       if (rex & REX_R)
12393         add = 8;
12394       else
12395         add = 0;
12396       sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12397     }
12398   else
12399     sprintf (scratchbuf, "%%mm%d", modrm.reg);
12400   oappend (scratchbuf + intel_syntax);
12401 }
12402
12403 static void
12404 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12405 {
12406   int add;
12407   USED_REX (REX_R);
12408   if (rex & REX_R)
12409     add = 8;
12410   else
12411     add = 0;
12412   if (need_vex && bytemode != xmm_mode)
12413     {
12414       switch (vex.length)
12415         {
12416         case 128:
12417           sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12418           break;
12419         case 256:
12420           sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12421           break;
12422         default:
12423           abort ();
12424         }
12425     }
12426   else
12427     sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12428   oappend (scratchbuf + intel_syntax);
12429 }
12430
12431 static void
12432 OP_EM (int bytemode, int sizeflag)
12433 {
12434   if (modrm.mod != 3)
12435     {
12436       if (intel_syntax && bytemode == v_mode)
12437         {
12438           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12439           used_prefixes |= (prefixes & PREFIX_DATA);
12440         }
12441       OP_E (bytemode, sizeflag);
12442       return;
12443     }
12444
12445   /* Skip mod/rm byte.  */
12446   MODRM_CHECK;
12447   codep++;
12448   used_prefixes |= (prefixes & PREFIX_DATA);
12449   if (prefixes & PREFIX_DATA)
12450     {
12451       int add;
12452
12453       USED_REX (REX_B);
12454       if (rex & REX_B)
12455         add = 8;
12456       else
12457         add = 0;
12458       sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12459     }
12460   else
12461     sprintf (scratchbuf, "%%mm%d", modrm.rm);
12462   oappend (scratchbuf + intel_syntax);
12463 }
12464
12465 /* cvt* are the only instructions in sse2 which have
12466    both SSE and MMX operands and also have 0x66 prefix
12467    in their opcode. 0x66 was originally used to differentiate
12468    between SSE and MMX instruction(operands). So we have to handle the
12469    cvt* separately using OP_EMC and OP_MXC */
12470 static void
12471 OP_EMC (int bytemode, int sizeflag)
12472 {
12473   if (modrm.mod != 3)
12474     {
12475       if (intel_syntax && bytemode == v_mode)
12476         {
12477           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12478           used_prefixes |= (prefixes & PREFIX_DATA);
12479         }
12480       OP_E (bytemode, sizeflag);
12481       return;
12482     }
12483
12484   /* Skip mod/rm byte.  */
12485   MODRM_CHECK;
12486   codep++;
12487   used_prefixes |= (prefixes & PREFIX_DATA);
12488   sprintf (scratchbuf, "%%mm%d", modrm.rm);
12489   oappend (scratchbuf + intel_syntax);
12490 }
12491
12492 static void
12493 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12494 {
12495   used_prefixes |= (prefixes & PREFIX_DATA);
12496   sprintf (scratchbuf, "%%mm%d", modrm.reg);
12497   oappend (scratchbuf + intel_syntax);
12498 }
12499
12500 static void
12501 OP_EX (int bytemode, int sizeflag)
12502 {
12503   int add;
12504   if (modrm.mod != 3)
12505     {
12506       OP_E (bytemode, sizeflag);
12507       return;
12508     }
12509   USED_REX (REX_B);
12510   if (rex & REX_B)
12511     add = 8;
12512   else
12513     add = 0;
12514
12515   /* Skip mod/rm byte.  */
12516   MODRM_CHECK;
12517   codep++;
12518   if (need_vex
12519       && bytemode != xmm_mode
12520       && bytemode != xmmq_mode)
12521     {
12522       switch (vex.length)
12523         {
12524         case 128:
12525           sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12526           break;
12527         case 256:
12528           sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12529           break;
12530         default:
12531           abort ();
12532         }
12533     }
12534   else
12535     sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12536   oappend (scratchbuf + intel_syntax);
12537 }
12538
12539 static void
12540 OP_MS (int bytemode, int sizeflag)
12541 {
12542   if (modrm.mod == 3)
12543     OP_EM (bytemode, sizeflag);
12544   else
12545     BadOp ();
12546 }
12547
12548 static void
12549 OP_XS (int bytemode, int sizeflag)
12550 {
12551   if (modrm.mod == 3)
12552     OP_EX (bytemode, sizeflag);
12553   else
12554     BadOp ();
12555 }
12556
12557 static void
12558 OP_M (int bytemode, int sizeflag)
12559 {
12560   if (modrm.mod == 3)
12561     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12562     BadOp ();
12563   else
12564     OP_E (bytemode, sizeflag);
12565 }
12566
12567 static void
12568 OP_0f07 (int bytemode, int sizeflag)
12569 {
12570   if (modrm.mod != 3 || modrm.rm != 0)
12571     BadOp ();
12572   else
12573     OP_E (bytemode, sizeflag);
12574 }
12575
12576 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12577    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
12578
12579 static void
12580 NOP_Fixup1 (int bytemode, int sizeflag)
12581 {
12582   if ((prefixes & PREFIX_DATA) != 0
12583       || (rex != 0
12584           && rex != 0x48
12585           && address_mode == mode_64bit))
12586     OP_REG (bytemode, sizeflag);
12587   else
12588     strcpy (obuf, "nop");
12589 }
12590
12591 static void
12592 NOP_Fixup2 (int bytemode, int sizeflag)
12593 {
12594   if ((prefixes & PREFIX_DATA) != 0
12595       || (rex != 0
12596           && rex != 0x48
12597           && address_mode == mode_64bit))
12598     OP_IMREG (bytemode, sizeflag);
12599 }
12600
12601 static const char *const Suffix3DNow[] = {
12602 /* 00 */        NULL,           NULL,           NULL,           NULL,
12603 /* 04 */        NULL,           NULL,           NULL,           NULL,
12604 /* 08 */        NULL,           NULL,           NULL,           NULL,
12605 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
12606 /* 10 */        NULL,           NULL,           NULL,           NULL,
12607 /* 14 */        NULL,           NULL,           NULL,           NULL,
12608 /* 18 */        NULL,           NULL,           NULL,           NULL,
12609 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
12610 /* 20 */        NULL,           NULL,           NULL,           NULL,
12611 /* 24 */        NULL,           NULL,           NULL,           NULL,
12612 /* 28 */        NULL,           NULL,           NULL,           NULL,
12613 /* 2C */        NULL,           NULL,           NULL,           NULL,
12614 /* 30 */        NULL,           NULL,           NULL,           NULL,
12615 /* 34 */        NULL,           NULL,           NULL,           NULL,
12616 /* 38 */        NULL,           NULL,           NULL,           NULL,
12617 /* 3C */        NULL,           NULL,           NULL,           NULL,
12618 /* 40 */        NULL,           NULL,           NULL,           NULL,
12619 /* 44 */        NULL,           NULL,           NULL,           NULL,
12620 /* 48 */        NULL,           NULL,           NULL,           NULL,
12621 /* 4C */        NULL,           NULL,           NULL,           NULL,
12622 /* 50 */        NULL,           NULL,           NULL,           NULL,
12623 /* 54 */        NULL,           NULL,           NULL,           NULL,
12624 /* 58 */        NULL,           NULL,           NULL,           NULL,
12625 /* 5C */        NULL,           NULL,           NULL,           NULL,
12626 /* 60 */        NULL,           NULL,           NULL,           NULL,
12627 /* 64 */        NULL,           NULL,           NULL,           NULL,
12628 /* 68 */        NULL,           NULL,           NULL,           NULL,
12629 /* 6C */        NULL,           NULL,           NULL,           NULL,
12630 /* 70 */        NULL,           NULL,           NULL,           NULL,
12631 /* 74 */        NULL,           NULL,           NULL,           NULL,
12632 /* 78 */        NULL,           NULL,           NULL,           NULL,
12633 /* 7C */        NULL,           NULL,           NULL,           NULL,
12634 /* 80 */        NULL,           NULL,           NULL,           NULL,
12635 /* 84 */        NULL,           NULL,           NULL,           NULL,
12636 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
12637 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
12638 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
12639 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
12640 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
12641 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
12642 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
12643 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
12644 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
12645 /* AC */        NULL,           NULL,           "pfacc",        NULL,
12646 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
12647 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
12648 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
12649 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
12650 /* C0 */        NULL,           NULL,           NULL,           NULL,
12651 /* C4 */        NULL,           NULL,           NULL,           NULL,
12652 /* C8 */        NULL,           NULL,           NULL,           NULL,
12653 /* CC */        NULL,           NULL,           NULL,           NULL,
12654 /* D0 */        NULL,           NULL,           NULL,           NULL,
12655 /* D4 */        NULL,           NULL,           NULL,           NULL,
12656 /* D8 */        NULL,           NULL,           NULL,           NULL,
12657 /* DC */        NULL,           NULL,           NULL,           NULL,
12658 /* E0 */        NULL,           NULL,           NULL,           NULL,
12659 /* E4 */        NULL,           NULL,           NULL,           NULL,
12660 /* E8 */        NULL,           NULL,           NULL,           NULL,
12661 /* EC */        NULL,           NULL,           NULL,           NULL,
12662 /* F0 */        NULL,           NULL,           NULL,           NULL,
12663 /* F4 */        NULL,           NULL,           NULL,           NULL,
12664 /* F8 */        NULL,           NULL,           NULL,           NULL,
12665 /* FC */        NULL,           NULL,           NULL,           NULL,
12666 };
12667
12668 static void
12669 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12670 {
12671   const char *mnemonic;
12672
12673   FETCH_DATA (the_info, codep + 1);
12674   /* AMD 3DNow! instructions are specified by an opcode suffix in the
12675      place where an 8-bit immediate would normally go.  ie. the last
12676      byte of the instruction.  */
12677   obufp = obuf + strlen (obuf);
12678   mnemonic = Suffix3DNow[*codep++ & 0xff];
12679   if (mnemonic)
12680     oappend (mnemonic);
12681   else
12682     {
12683       /* Since a variable sized modrm/sib chunk is between the start
12684          of the opcode (0x0f0f) and the opcode suffix, we need to do
12685          all the modrm processing first, and don't know until now that
12686          we have a bad opcode.  This necessitates some cleaning up.  */
12687       op_out[0][0] = '\0';
12688       op_out[1][0] = '\0';
12689       BadOp ();
12690     }
12691 }
12692
12693 static const char *simd_cmp_op[] = {
12694   "eq",
12695   "lt",
12696   "le",
12697   "unord",
12698   "neq",
12699   "nlt",
12700   "nle",
12701   "ord"
12702 };
12703
12704 static void
12705 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12706 {
12707   unsigned int cmp_type;
12708
12709   FETCH_DATA (the_info, codep + 1);
12710   cmp_type = *codep++ & 0xff;
12711   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12712     {
12713       char suffix [3];
12714       char *p = obuf + strlen (obuf) - 2;
12715       suffix[0] = p[0];
12716       suffix[1] = p[1];
12717       suffix[2] = '\0';
12718       sprintf (p, "%s%s", simd_cmp_op[cmp_type], suffix);
12719     }
12720   else
12721     {
12722       /* We have a reserved extension byte.  Output it directly.  */
12723       scratchbuf[0] = '$';
12724       print_operand_value (scratchbuf + 1, 1, cmp_type);
12725       oappend (scratchbuf + intel_syntax);
12726       scratchbuf[0] = '\0';
12727     }
12728 }
12729
12730 static void
12731 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12732           int sizeflag ATTRIBUTE_UNUSED)
12733 {
12734   /* mwait %eax,%ecx  */
12735   if (!intel_syntax)
12736     {
12737       const char **names = (address_mode == mode_64bit
12738                             ? names64 : names32);
12739       strcpy (op_out[0], names[0]);
12740       strcpy (op_out[1], names[1]);
12741       two_source_ops = 1;
12742     }
12743   /* Skip mod/rm byte.  */
12744   MODRM_CHECK;
12745   codep++;
12746 }
12747
12748 static void
12749 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12750             int sizeflag ATTRIBUTE_UNUSED)
12751 {
12752   /* monitor %eax,%ecx,%edx"  */
12753   if (!intel_syntax)
12754     {
12755       const char **op1_names;
12756       const char **names = (address_mode == mode_64bit
12757                             ? names64 : names32);
12758
12759       if (!(prefixes & PREFIX_ADDR))
12760         op1_names = (address_mode == mode_16bit
12761                      ? names16 : names);
12762       else
12763         {
12764           /* Remove "addr16/addr32".  */
12765           addr_prefix = NULL;
12766           op1_names = (address_mode != mode_32bit
12767                        ? names32 : names16);
12768           used_prefixes |= PREFIX_ADDR;
12769         }
12770       strcpy (op_out[0], op1_names[0]);
12771       strcpy (op_out[1], names[1]);
12772       strcpy (op_out[2], names[2]);
12773       two_source_ops = 1;
12774     }
12775   /* Skip mod/rm byte.  */
12776   MODRM_CHECK;
12777   codep++;
12778 }
12779
12780 static void
12781 BadOp (void)
12782 {
12783   /* Throw away prefixes and 1st. opcode byte.  */
12784   codep = insn_codep + 1;
12785   oappend ("(bad)");
12786 }
12787
12788 static void
12789 REP_Fixup (int bytemode, int sizeflag)
12790 {
12791   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12792      lods and stos.  */
12793   if (prefixes & PREFIX_REPZ)
12794     repz_prefix = "rep ";
12795
12796   switch (bytemode)
12797     {
12798     case al_reg:
12799     case eAX_reg:
12800     case indir_dx_reg:
12801       OP_IMREG (bytemode, sizeflag);
12802       break;
12803     case eDI_reg:
12804       OP_ESreg (bytemode, sizeflag);
12805       break;
12806     case eSI_reg:
12807       OP_DSreg (bytemode, sizeflag);
12808       break;
12809     default:
12810       abort ();
12811       break;
12812     }
12813 }
12814
12815 static void
12816 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12817 {
12818   USED_REX (REX_W);
12819   if (rex & REX_W)
12820     {
12821       /* Change cmpxchg8b to cmpxchg16b.  */
12822       char *p = obuf + strlen (obuf) - 2;
12823       strcpy (p, "16b");
12824       bytemode = o_mode;
12825     }
12826   OP_M (bytemode, sizeflag);
12827 }
12828
12829 static void
12830 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12831 {
12832   if (need_vex)
12833     {
12834       switch (vex.length)
12835         {
12836         case 128:
12837           sprintf (scratchbuf, "%%xmm%d", reg);
12838           break;
12839         case 256:
12840           sprintf (scratchbuf, "%%ymm%d", reg);
12841           break;
12842         default:
12843           abort ();
12844         }
12845     }
12846   else
12847     sprintf (scratchbuf, "%%xmm%d", reg);
12848   oappend (scratchbuf + intel_syntax);
12849 }
12850
12851 static void
12852 CRC32_Fixup (int bytemode, int sizeflag)
12853 {
12854   /* Add proper suffix to "crc32".  */
12855   char *p = obuf + strlen (obuf);
12856
12857   switch (bytemode)
12858     {
12859     case b_mode:
12860       if (intel_syntax)
12861         break;
12862
12863       *p++ = 'b';
12864       break;
12865     case v_mode:
12866       if (intel_syntax)
12867         break;
12868
12869       USED_REX (REX_W);
12870       if (rex & REX_W)
12871         *p++ = 'q';
12872       else if (sizeflag & DFLAG)
12873         *p++ = 'l';
12874       else
12875         *p++ = 'w';
12876       used_prefixes |= (prefixes & PREFIX_DATA);
12877       break;
12878     default:
12879       oappend (INTERNAL_DISASSEMBLER_ERROR);
12880       break;
12881     }
12882   *p = '\0';
12883
12884   if (modrm.mod == 3)
12885     {
12886       int add;
12887
12888       /* Skip mod/rm byte.  */
12889       MODRM_CHECK;
12890       codep++;
12891
12892       USED_REX (REX_B);
12893       add = (rex & REX_B) ? 8 : 0;
12894       if (bytemode == b_mode)
12895         {
12896           USED_REX (0);
12897           if (rex)
12898             oappend (names8rex[modrm.rm + add]);
12899           else
12900             oappend (names8[modrm.rm + add]);
12901         }
12902       else
12903         {
12904           USED_REX (REX_W);
12905           if (rex & REX_W)
12906             oappend (names64[modrm.rm + add]);
12907           else if ((prefixes & PREFIX_DATA))
12908             oappend (names16[modrm.rm + add]);
12909           else
12910             oappend (names32[modrm.rm + add]);
12911         }
12912     }
12913   else
12914     OP_E (bytemode, sizeflag);
12915 }
12916
12917 /* Print a DREX argument as either a register or memory operation.  */
12918 static void
12919 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
12920 {
12921   if (reg == DREX_REG_UNKNOWN)
12922     BadOp ();
12923
12924   else if (reg != DREX_REG_MEMORY)
12925     {
12926       sprintf (scratchbuf, "%%xmm%d", reg);
12927       oappend (scratchbuf + intel_syntax);
12928     }
12929
12930   else
12931     OP_E_extended (bytemode, sizeflag, 1);
12932 }
12933
12934 /* SSE5 instructions that have 4 arguments are encoded as:
12935    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
12936
12937    The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
12938    the DREX field (0x8) to determine how the arguments are laid out.
12939    The destination register must be the same register as one of the
12940    inputs, and it is encoded in the DREX byte.  No REX prefix is used
12941    for these instructions, since the DREX field contains the 3 extension
12942    bits provided by the REX prefix.
12943
12944    The bytemode argument adds 2 extra bits for passing extra information:
12945         DREX_OC1        -- Set the OC1 bit to indicate dest == 1st arg
12946         DREX_NO_OC0     -- OC0 in DREX is invalid
12947         (but pretend it is set).  */
12948
12949 static void
12950 OP_DREX4 (int flag_bytemode, int sizeflag)
12951 {
12952   unsigned int drex_byte;
12953   unsigned int regs[4];
12954   unsigned int modrm_regmem;
12955   unsigned int modrm_reg;
12956   unsigned int drex_reg;
12957   int bytemode;
12958   int rex_save = rex;
12959   int rex_used_save = rex_used;
12960   int has_sib = 0;
12961   int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
12962   int oc0;
12963   int i;
12964
12965   bytemode = flag_bytemode & ~ DREX_MASK;
12966
12967   for (i = 0; i < 4; i++)
12968     regs[i] = DREX_REG_UNKNOWN;
12969
12970   /* Determine if we have a SIB byte in addition to MODRM before the
12971      DREX byte.  */
12972   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
12973       && (modrm.mod != 3)
12974       && (modrm.rm == 4))
12975     has_sib = 1;
12976
12977   /* Get the DREX byte.  */
12978   FETCH_DATA (the_info, codep + 2 + has_sib);
12979   drex_byte = codep[has_sib+1];
12980   drex_reg = DREX_XMM (drex_byte);
12981   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
12982
12983   /* Is OC0 legal?  If not, hardwire oc0 == 1.  */
12984   if (flag_bytemode & DREX_NO_OC0)
12985     {
12986       oc0 = 1;
12987       if (DREX_OC0 (drex_byte))
12988         BadOp ();
12989     }
12990   else
12991     oc0 = DREX_OC0 (drex_byte);
12992
12993   if (modrm.mod == 3)
12994     {
12995       /* regmem == register  */
12996       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
12997       rex = rex_used = 0;
12998       /* skip modrm/drex since we don't call OP_E_extended  */
12999       codep += 2;
13000     }
13001   else
13002     {
13003       /* regmem == memory, fill in appropriate REX bits  */
13004       modrm_regmem = DREX_REG_MEMORY;
13005       rex = drex_byte & (REX_B | REX_X | REX_R);
13006       if (rex)
13007         rex |= REX_OPCODE;
13008       rex_used = rex;
13009     }
13010
13011   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13012      order.  */
13013   switch (oc0 + oc1)
13014     {
13015     default:
13016       BadOp ();
13017       return;
13018
13019     case 0:
13020       regs[0] = modrm_regmem;
13021       regs[1] = modrm_reg;
13022       regs[2] = drex_reg;
13023       regs[3] = drex_reg;
13024       break;
13025
13026     case 1:
13027       regs[0] = modrm_reg;
13028       regs[1] = modrm_regmem;
13029       regs[2] = drex_reg;
13030       regs[3] = drex_reg;
13031       break;
13032
13033     case 2:
13034       regs[0] = drex_reg;
13035       regs[1] = modrm_regmem;
13036       regs[2] = modrm_reg;
13037       regs[3] = drex_reg;
13038       break;
13039
13040     case 3:
13041       regs[0] = drex_reg;
13042       regs[1] = modrm_reg;
13043       regs[2] = modrm_regmem;
13044       regs[3] = drex_reg;
13045       break;
13046     }
13047
13048   /* Print out the arguments.  */
13049   for (i = 0; i < 4; i++)
13050     {
13051       int j = (intel_syntax) ? 3 - i : i;
13052       if (i > 0)
13053         {
13054           *obufp++ = ',';
13055           *obufp = '\0';
13056         }
13057
13058       print_drex_arg (regs[j], bytemode, sizeflag);
13059     }
13060
13061   rex = rex_save;
13062   rex_used = rex_used_save;
13063 }
13064
13065 /* SSE5 instructions that have 3 arguments, and are encoded as:
13066    0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>    (or)
13067    0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13068
13069    The DREX field has 1 bit (0x8) to determine how the arguments are
13070    laid out. The destination register is encoded in the DREX byte.
13071    No REX prefix is used for these instructions, since the DREX field
13072    contains the 3 extension bits provided by the REX prefix.  */
13073
13074 static void
13075 OP_DREX3 (int flag_bytemode, int sizeflag)
13076 {
13077   unsigned int drex_byte;
13078   unsigned int regs[3];
13079   unsigned int modrm_regmem;
13080   unsigned int modrm_reg;
13081   unsigned int drex_reg;
13082   int bytemode;
13083   int rex_save = rex;
13084   int rex_used_save = rex_used;
13085   int has_sib = 0;
13086   int oc0;
13087   int i;
13088
13089   bytemode = flag_bytemode & ~ DREX_MASK;
13090
13091   for (i = 0; i < 3; i++)
13092     regs[i] = DREX_REG_UNKNOWN;
13093
13094   /* Determine if we have a SIB byte in addition to MODRM before the
13095      DREX byte.  */
13096   if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13097       && (modrm.mod != 3)
13098       && (modrm.rm == 4))
13099     has_sib = 1;
13100
13101   /* Get the DREX byte.  */
13102   FETCH_DATA (the_info, codep + 2 + has_sib);
13103   drex_byte = codep[has_sib+1];
13104   drex_reg = DREX_XMM (drex_byte);
13105   modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13106
13107   /* Is OC0 legal?  If not, hardwire oc0 == 0 */
13108   oc0 = DREX_OC0 (drex_byte);
13109   if ((flag_bytemode & DREX_NO_OC0) && oc0)
13110     BadOp ();
13111
13112   if (modrm.mod == 3)
13113     {
13114       /* regmem == register */
13115       modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13116       rex = rex_used = 0;
13117       /* skip modrm/drex since we don't call OP_E_extended.  */
13118       codep += 2;
13119     }
13120   else
13121     {
13122       /* regmem == memory, fill in appropriate REX bits.  */
13123       modrm_regmem = DREX_REG_MEMORY;
13124       rex = drex_byte & (REX_B | REX_X | REX_R);
13125       if (rex)
13126         rex |= REX_OPCODE;
13127       rex_used = rex;
13128     }
13129
13130   /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13131      order.  */
13132   switch (oc0)
13133     {
13134     default:
13135       BadOp ();
13136       return;
13137
13138     case 0:
13139       regs[0] = modrm_regmem;
13140       regs[1] = modrm_reg;
13141       regs[2] = drex_reg;
13142       break;
13143
13144     case 1:
13145       regs[0] = modrm_reg;
13146       regs[1] = modrm_regmem;
13147       regs[2] = drex_reg;
13148       break;
13149     }
13150
13151   /* Print out the arguments.  */
13152   for (i = 0; i < 3; i++)
13153     {
13154       int j = (intel_syntax) ? 2 - i : i;
13155       if (i > 0)
13156         {
13157           *obufp++ = ',';
13158           *obufp = '\0';
13159         }
13160
13161       print_drex_arg (regs[j], bytemode, sizeflag);
13162     }
13163
13164   rex = rex_save;
13165   rex_used = rex_used_save;
13166 }
13167
13168 /* Emit a floating point comparison for comp<xx> instructions.  */
13169
13170 static void
13171 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13172               int sizeflag ATTRIBUTE_UNUSED)
13173 {
13174   unsigned char byte;
13175
13176   static const char *const cmp_test[] = {
13177     "eq",
13178     "lt",
13179     "le",
13180     "unord",
13181     "ne",
13182     "nlt",
13183     "nle",
13184     "ord",
13185     "ueq",
13186     "ult",
13187     "ule",
13188     "false",
13189     "une",
13190     "unlt",
13191     "unle",
13192     "true"
13193   };
13194
13195   FETCH_DATA (the_info, codep + 1);
13196   byte = *codep & 0xff;
13197
13198   if (byte >= ARRAY_SIZE (cmp_test)
13199       || obuf[0] != 'c'
13200       || obuf[1] != 'o'
13201       || obuf[2] != 'm')
13202     {
13203       /* The instruction isn't one we know about, so just append the
13204          extension byte as a numeric value.  */
13205       OP_I (b_mode, 0);
13206     }
13207
13208   else
13209     {
13210       sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13211       strcpy (obuf, scratchbuf);
13212       codep++;
13213     }
13214 }
13215
13216 /* Emit an integer point comparison for pcom<xx> instructions,
13217    rewriting the instruction to have the test inside of it.  */
13218
13219 static void
13220 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13221               int sizeflag ATTRIBUTE_UNUSED)
13222 {
13223   unsigned char byte;
13224
13225   static const char *const cmp_test[] = {
13226     "lt",
13227     "le",
13228     "gt",
13229     "ge",
13230     "eq",
13231     "ne",
13232     "false",
13233     "true"
13234   };
13235
13236   FETCH_DATA (the_info, codep + 1);
13237   byte = *codep & 0xff;
13238
13239   if (byte >= ARRAY_SIZE (cmp_test)
13240       || obuf[0] != 'p'
13241       || obuf[1] != 'c'
13242       || obuf[2] != 'o'
13243       || obuf[3] != 'm')
13244     {
13245       /* The instruction isn't one we know about, so just print the
13246          comparison test byte as a numeric value.  */
13247       OP_I (b_mode, 0);
13248     }
13249
13250   else
13251     {
13252       sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13253       strcpy (obuf, scratchbuf);
13254       codep++;
13255     }
13256 }
13257
13258 /* Display the destination register operand for instructions with
13259    VEX. */
13260
13261 static void
13262 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13263 {
13264   if (!need_vex)
13265     abort ();
13266
13267   if (!need_vex_reg)
13268     return;
13269
13270   switch (vex.length)
13271     {
13272     case 128:
13273       switch (bytemode)
13274         {
13275         case vex_mode:
13276         case vex128_mode:
13277           break;
13278         default:
13279           abort ();
13280           return;
13281         }
13282
13283       sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13284       break;
13285     case 256:
13286       switch (bytemode)
13287         {
13288         case vex_mode:
13289         case vex256_mode:
13290           break;
13291         default:
13292           abort ();
13293           return;
13294         }
13295
13296       sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13297       break;
13298     default:
13299       abort ();
13300       break;
13301     }
13302   oappend (scratchbuf + intel_syntax);
13303 }
13304
13305 /* Get the VEX immediate byte without moving codep.  */
13306
13307 static unsigned char
13308 get_vex_imm8 (int sizeflag)
13309 {
13310   int bytes_before_imm = 0;
13311
13312   /* Skip mod/rm byte.   */
13313   MODRM_CHECK;
13314   codep++;
13315
13316   if (modrm.mod != 3)
13317     {
13318       /* There are SIB/displacement bytes.  */
13319       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13320         {
13321           /* 32/64 bit address mode */
13322           int base = modrm.rm;
13323
13324           /* Check SIB byte.  */
13325           if (base == 4)
13326             {
13327               FETCH_DATA (the_info, codep + 1);
13328               base = *codep & 7;
13329               bytes_before_imm++;
13330             }
13331
13332           switch (modrm.mod)
13333             {
13334             case 0:
13335               /* When modrm.rm == 5 or modrm.rm == 4 and base in
13336                  SIB == 5, there is a 4 byte displacement.  */
13337               if (base != 5)
13338                 /* No displacement. */
13339                 break;
13340             case 2:
13341               /* 4 byte displacement.  */
13342               bytes_before_imm += 4;
13343               break;
13344             case 1:
13345               /* 1 byte displacement.  */
13346               bytes_before_imm++;
13347               break;
13348             }
13349         }
13350       else
13351         { /* 16 bit address mode */
13352           switch (modrm.mod)
13353             {
13354             case 0:
13355               /* When modrm.rm == 6, there is a 2 byte displacement.  */
13356               if (modrm.rm != 6)
13357                 /* No displacement. */
13358                 break;
13359             case 2:
13360               /* 2 byte displacement.  */
13361               bytes_before_imm += 2;
13362               break;
13363             case 1:
13364               /* 1 byte displacement.  */
13365               bytes_before_imm++;
13366               break;
13367             }
13368         }
13369     }
13370
13371   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13372   return codep [bytes_before_imm];
13373 }
13374
13375 static void
13376 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13377 {
13378   if (reg == -1 && modrm.mod != 3)
13379     {
13380       OP_E_memory (bytemode, sizeflag, 0);
13381       return;
13382     }
13383   else
13384     {
13385       if (reg == -1)
13386         {
13387           reg = modrm.rm;
13388           USED_REX (REX_B);
13389           if (rex & REX_B)
13390             reg += 8;
13391         }
13392       else if (reg > 7 && address_mode != mode_64bit)
13393         BadOp ();
13394     }
13395
13396   switch (vex.length)
13397     {
13398     case 128:
13399       sprintf (scratchbuf, "%%xmm%d", reg);
13400       break;
13401     case 256:
13402       sprintf (scratchbuf, "%%ymm%d", reg);
13403       break;
13404     default:
13405       abort ();
13406     }
13407   oappend (scratchbuf + intel_syntax);
13408 }
13409
13410 static void
13411 OP_EX_VexImmW (int bytemode, int sizeflag)
13412 {
13413   int reg = -1;
13414   static unsigned char vex_imm8;
13415
13416   if (!vex_w_done)
13417     {
13418       vex_imm8 = get_vex_imm8 (sizeflag);
13419       if (vex.w)
13420         reg = vex_imm8 >> 4;
13421       vex_w_done = 1;
13422     }
13423   else
13424     {
13425       if (!vex.w)
13426         reg = vex_imm8 >> 4;
13427     }
13428
13429   OP_EX_VexReg (bytemode, sizeflag, reg);
13430 }
13431
13432 static void
13433 OP_EX_VexW (int bytemode, int sizeflag)
13434 {
13435   int reg = -1;
13436
13437   if (!vex_w_done)
13438     {
13439       vex_w_done = 1;
13440       if (vex.w)
13441         reg = vex.register_specifier;
13442     }
13443   else
13444     {
13445       if (!vex.w)
13446         reg = vex.register_specifier;
13447     }
13448
13449   OP_EX_VexReg (bytemode, sizeflag, reg);
13450 }
13451
13452 static void
13453 OP_VEX_FMA (int bytemode, int sizeflag)
13454 {
13455   int reg = get_vex_imm8 (sizeflag) >> 4;
13456
13457   if (reg > 7 && address_mode != mode_64bit)
13458     BadOp ();
13459
13460   switch (vex.length)
13461     {
13462     case 128:
13463       switch (bytemode)
13464         {
13465         case vex_mode:
13466         case vex128_mode:
13467           break;
13468         default:
13469           abort ();
13470           return;
13471         }
13472
13473       sprintf (scratchbuf, "%%xmm%d", reg);
13474       break;
13475     case 256:
13476       switch (bytemode)
13477         {
13478         case vex_mode:
13479           break;
13480         default:
13481           abort ();
13482           return;
13483         }
13484
13485       sprintf (scratchbuf, "%%ymm%d", reg);
13486       break;
13487     default:
13488       abort ();
13489     }
13490   oappend (scratchbuf + intel_syntax);
13491 }
13492
13493 static void
13494 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13495              int sizeflag ATTRIBUTE_UNUSED)
13496 {
13497   /* Skip the immediate byte and check for invalid bits.  */
13498   FETCH_DATA (the_info, codep + 1);
13499   if (*codep++ & 0xf)
13500     BadOp ();
13501 }
13502
13503 static void
13504 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13505 {
13506   int reg;
13507   FETCH_DATA (the_info, codep + 1);
13508   reg = *codep++;
13509
13510   if (bytemode != x_mode)
13511     abort ();
13512
13513   if (reg & 0xf)
13514       BadOp ();
13515
13516   reg >>= 4;
13517   if (reg > 7 && address_mode != mode_64bit)
13518     BadOp ();
13519
13520   switch (vex.length)
13521     {
13522     case 128:
13523       sprintf (scratchbuf, "%%xmm%d", reg);
13524       break;
13525     case 256:
13526       sprintf (scratchbuf, "%%ymm%d", reg);
13527       break;
13528     default:
13529       abort ();
13530     }
13531   oappend (scratchbuf + intel_syntax);
13532 }
13533
13534 static void
13535 OP_XMM_VexW (int bytemode, int sizeflag)
13536 {
13537   /* Turn off the REX.W bit since it is used for swapping operands
13538      now.  */
13539   rex &= ~REX_W;
13540   OP_XMM (bytemode, sizeflag);
13541 }
13542
13543 static void
13544 OP_EX_Vex (int bytemode, int sizeflag)
13545 {
13546   if (modrm.mod != 3)
13547     {
13548       if (vex.register_specifier != 0)
13549         BadOp ();
13550       need_vex_reg = 0;
13551     }
13552   OP_EX (bytemode, sizeflag);
13553 }
13554
13555 static void
13556 OP_XMM_Vex (int bytemode, int sizeflag)
13557 {
13558   if (modrm.mod != 3)
13559     {
13560       if (vex.register_specifier != 0)
13561         BadOp ();
13562       need_vex_reg = 0;
13563     }
13564   OP_XMM (bytemode, sizeflag);
13565 }
13566
13567 static void
13568 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13569 {
13570   switch (vex.length)
13571     {
13572     case 128:
13573       strcpy (obuf, "vzeroupper");
13574       break;
13575     case 256:
13576       strcpy (obuf, "vzeroall");
13577       break;
13578     default:
13579       abort ();
13580     }
13581 }
13582
13583 static const char *vex_cmp_op[] = {
13584   "eq",
13585   "lt",
13586   "le",
13587   "unord",
13588   "neq",
13589   "nlt",
13590   "nle",
13591   "ord",
13592   "eq_uq",
13593   "nge",
13594   "ngt",
13595   "false",
13596   "neq_oq",
13597   "ge",
13598   "gt",
13599   "true",
13600   "eq_os",
13601   "lt_oq",
13602   "le_oq",
13603   "unord_s",
13604   "neq_us",
13605   "nlt_uq",
13606   "nle_uq",
13607   "ord_s",
13608   "eq_us",
13609   "nge_uq",
13610   "ngt_uq",
13611   "false_os",
13612   "neq_os",
13613   "ge_oq",
13614   "gt_oq",
13615   "true_us"
13616 };
13617
13618 static void
13619 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13620 {
13621   unsigned int cmp_type;
13622
13623   FETCH_DATA (the_info, codep + 1);
13624   cmp_type = *codep++ & 0xff;
13625   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13626     {
13627       char suffix [3];
13628       char *p = obuf + strlen (obuf) - 2;
13629       suffix[0] = p[0];
13630       suffix[1] = p[1];
13631       suffix[2] = '\0';
13632       sprintf (p, "%s%s", vex_cmp_op[cmp_type], suffix);
13633     }
13634   else
13635     {
13636       /* We have a reserved extension byte.  Output it directly.  */
13637       scratchbuf[0] = '$';
13638       print_operand_value (scratchbuf + 1, 1, cmp_type);
13639       oappend (scratchbuf + intel_syntax);
13640       scratchbuf[0] = '\0';
13641     }
13642 }
13643
13644 static const char *pclmul_op[] = {
13645   "lql",
13646   "hql",
13647   "lqh",
13648   "hqh"
13649 };
13650
13651 static void
13652 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13653               int sizeflag ATTRIBUTE_UNUSED)
13654 {
13655   unsigned int pclmul_type;
13656
13657   FETCH_DATA (the_info, codep + 1);
13658   pclmul_type = *codep++ & 0xff;
13659   switch (pclmul_type)
13660     {
13661     case 0x10:
13662       pclmul_type = 2;
13663       break;
13664     case 0x11:
13665       pclmul_type = 3;
13666       break;
13667     default:
13668       break;
13669     }
13670   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13671     {
13672       char suffix [4];
13673       char *p = obuf + strlen (obuf) - 3;
13674       suffix[0] = p[0];
13675       suffix[1] = p[1];
13676       suffix[2] = p[2];
13677       suffix[3] = '\0';
13678       sprintf (p, "%s%s", pclmul_op[pclmul_type], suffix);
13679     }
13680   else
13681     {
13682       /* We have a reserved extension byte.  Output it directly.  */
13683       scratchbuf[0] = '$';
13684       print_operand_value (scratchbuf + 1, 1, pclmul_type);
13685       oappend (scratchbuf + intel_syntax);
13686       scratchbuf[0] = '\0';
13687     }
13688 }
13689
13690 static const char *vpermil2_op[] = {
13691   "td",
13692   "td",
13693   "mo",
13694   "mz"
13695 };
13696
13697 static void
13698 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13699                 int sizeflag ATTRIBUTE_UNUSED)
13700 {
13701   unsigned int vpermil2_type;
13702
13703   FETCH_DATA (the_info, codep + 1);
13704   vpermil2_type = *codep++ & 0xf;
13705   if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13706     {
13707       char suffix [4];
13708       char *p = obuf + strlen (obuf) - 3;
13709       suffix[0] = p[0];
13710       suffix[1] = p[1];
13711       suffix[2] = p[2];
13712       suffix[3] = '\0';
13713       sprintf (p, "%s%s", vpermil2_op[vpermil2_type], suffix);
13714     }
13715   else
13716     {
13717       /* We have a reserved extension byte.  Output it directly.  */
13718       scratchbuf[0] = '$';
13719       print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13720       oappend (scratchbuf + intel_syntax);
13721       scratchbuf[0] = '\0';
13722     }
13723 }
13724
13725 static void
13726 MOVBE_Fixup (int bytemode, int sizeflag)
13727 {
13728   /* Add proper suffix to "movbe".  */
13729   char *p = obuf + strlen (obuf);
13730
13731   switch (bytemode)
13732     {
13733     case v_mode:
13734       if (intel_syntax)
13735         break;
13736
13737       USED_REX (REX_W);
13738       if (sizeflag & SUFFIX_ALWAYS)
13739         {
13740           if (rex & REX_W)
13741             *p++ = 'q';
13742           else if (sizeflag & DFLAG)
13743             *p++ = 'l';
13744           else
13745             *p++ = 'w';
13746         }
13747       used_prefixes |= (prefixes & PREFIX_DATA);
13748       break;
13749     default:
13750       oappend (INTERNAL_DISASSEMBLER_ERROR);
13751       break;
13752     }
13753   *p = '\0';
13754
13755   OP_M (bytemode, sizeflag);
13756 }