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x86: re-arrange order of decode for various mask reg opcodes
[deliverable/binutils-gdb.git] / opcodes / i386-dis.c
1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2021 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 #include <setjmp.h>
43
44 static int print_insn (bfd_vma, disassemble_info *);
45 static void dofloat (int);
46 static void OP_ST (int, int);
47 static void OP_STi (int, int);
48 static int putop (const char *, int);
49 static void oappend (const char *);
50 static void append_seg (void);
51 static void OP_indirE (int, int);
52 static void print_operand_value (char *, int, bfd_vma);
53 static void OP_E_register (int, int);
54 static void OP_E_memory (int, int);
55 static void print_displacement (char *, bfd_vma);
56 static void OP_E (int, int);
57 static void OP_G (int, int);
58 static bfd_vma get64 (void);
59 static bfd_signed_vma get32 (void);
60 static bfd_signed_vma get32s (void);
61 static int get16 (void);
62 static void set_op (bfd_vma, int);
63 static void OP_Skip_MODRM (int, int);
64 static void OP_REG (int, int);
65 static void OP_IMREG (int, int);
66 static void OP_I (int, int);
67 static void OP_I64 (int, int);
68 static void OP_sI (int, int);
69 static void OP_J (int, int);
70 static void OP_SEG (int, int);
71 static void OP_DIR (int, int);
72 static void OP_OFF (int, int);
73 static void OP_OFF64 (int, int);
74 static void ptr_reg (int, int);
75 static void OP_ESreg (int, int);
76 static void OP_DSreg (int, int);
77 static void OP_C (int, int);
78 static void OP_D (int, int);
79 static void OP_T (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_VexR (int, int);
91 static void OP_VexW (int, int);
92 static void OP_Rounding (int, int);
93 static void OP_REG_VexI4 (int, int);
94 static void OP_VexI4 (int, int);
95 static void PCLMUL_Fixup (int, int);
96 static void VPCMP_Fixup (int, int);
97 static void VPCOM_Fixup (int, int);
98 static void OP_0f07 (int, int);
99 static void OP_Monitor (int, int);
100 static void OP_Mwait (int, int);
101 static void NOP_Fixup1 (int, int);
102 static void NOP_Fixup2 (int, int);
103 static void OP_3DNowSuffix (int, int);
104 static void CMP_Fixup (int, int);
105 static void BadOp (void);
106 static void REP_Fixup (int, int);
107 static void SEP_Fixup (int, int);
108 static void BND_Fixup (int, int);
109 static void NOTRACK_Fixup (int, int);
110 static void HLE_Fixup1 (int, int);
111 static void HLE_Fixup2 (int, int);
112 static void HLE_Fixup3 (int, int);
113 static void CMPXCHG8B_Fixup (int, int);
114 static void XMM_Fixup (int, int);
115 static void FXSAVE_Fixup (int, int);
116
117 static void MOVSXD_Fixup (int, int);
118
119 static void OP_Mask (int, int);
120
121 struct dis_private {
122 /* Points to first byte not fetched. */
123 bfd_byte *max_fetched;
124 bfd_byte the_buffer[MAX_MNEM_SIZE];
125 bfd_vma insn_start;
126 int orig_sizeflag;
127 OPCODES_SIGJMP_BUF bailout;
128 };
129
130 enum address_mode
131 {
132 mode_16bit,
133 mode_32bit,
134 mode_64bit
135 };
136
137 enum address_mode address_mode;
138
139 /* Flags for the prefixes for the current instruction. See below. */
140 static int prefixes;
141
142 /* REX prefix the current instruction. See below. */
143 static int rex;
144 /* Bits of REX we've already used. */
145 static int rex_used;
146 /* Mark parts used in the REX prefix. When we are testing for
147 empty prefix (for 8bit register REX extension), just mask it
148 out. Otherwise test for REX bit is excuse for existence of REX
149 only in case value is nonzero. */
150 #define USED_REX(value) \
151 { \
152 if (value) \
153 { \
154 if ((rex & value)) \
155 rex_used |= (value) | REX_OPCODE; \
156 } \
157 else \
158 rex_used |= REX_OPCODE; \
159 }
160
161 /* Flags for prefixes which we somehow handled when printing the
162 current instruction. */
163 static int used_prefixes;
164
165 /* Flags stored in PREFIXES. */
166 #define PREFIX_REPZ 1
167 #define PREFIX_REPNZ 2
168 #define PREFIX_LOCK 4
169 #define PREFIX_CS 8
170 #define PREFIX_SS 0x10
171 #define PREFIX_DS 0x20
172 #define PREFIX_ES 0x40
173 #define PREFIX_FS 0x80
174 #define PREFIX_GS 0x100
175 #define PREFIX_DATA 0x200
176 #define PREFIX_ADDR 0x400
177 #define PREFIX_FWAIT 0x800
178
179 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
180 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
181 on error. */
182 #define FETCH_DATA(info, addr) \
183 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
184 ? 1 : fetch_data ((info), (addr)))
185
186 static int
187 fetch_data (struct disassemble_info *info, bfd_byte *addr)
188 {
189 int status;
190 struct dis_private *priv = (struct dis_private *) info->private_data;
191 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
192
193 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
194 status = (*info->read_memory_func) (start,
195 priv->max_fetched,
196 addr - priv->max_fetched,
197 info);
198 else
199 status = -1;
200 if (status != 0)
201 {
202 /* If we did manage to read at least one byte, then
203 print_insn_i386 will do something sensible. Otherwise, print
204 an error. We do that here because this is where we know
205 STATUS. */
206 if (priv->max_fetched == priv->the_buffer)
207 (*info->memory_error_func) (status, start, info);
208 OPCODES_SIGLONGJMP (priv->bailout, 1);
209 }
210 else
211 priv->max_fetched = addr;
212 return 1;
213 }
214
215 /* Possible values for prefix requirement. */
216 #define PREFIX_IGNORED_SHIFT 16
217 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
218 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
219 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
220 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
221 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
222
223 /* Opcode prefixes. */
224 #define PREFIX_OPCODE (PREFIX_REPZ \
225 | PREFIX_REPNZ \
226 | PREFIX_DATA)
227
228 /* Prefixes ignored. */
229 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
230 | PREFIX_IGNORED_REPNZ \
231 | PREFIX_IGNORED_DATA)
232
233 #define XX { NULL, 0 }
234 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
235
236 #define Eb { OP_E, b_mode }
237 #define Ebnd { OP_E, bnd_mode }
238 #define EbS { OP_E, b_swap_mode }
239 #define EbndS { OP_E, bnd_swap_mode }
240 #define Ev { OP_E, v_mode }
241 #define Eva { OP_E, va_mode }
242 #define Ev_bnd { OP_E, v_bnd_mode }
243 #define EvS { OP_E, v_swap_mode }
244 #define Ed { OP_E, d_mode }
245 #define Edq { OP_E, dq_mode }
246 #define Edqw { OP_E, dqw_mode }
247 #define Edqb { OP_E, dqb_mode }
248 #define Edb { OP_E, db_mode }
249 #define Edw { OP_E, dw_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, indir_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mv { OP_M, v_mode }
265 #define Mv_bnd { OP_M, v_bndmk_mode }
266 #define Mx { OP_M, x_mode }
267 #define Mxmm { OP_M, xmm_mode }
268 #define Gb { OP_G, b_mode }
269 #define Gbnd { OP_G, bnd_mode }
270 #define Gv { OP_G, v_mode }
271 #define Gd { OP_G, d_mode }
272 #define Gdq { OP_G, dq_mode }
273 #define Gm { OP_G, m_mode }
274 #define Gva { OP_G, va_mode }
275 #define Gw { OP_G, w_mode }
276 #define Ib { OP_I, b_mode }
277 #define sIb { OP_sI, b_mode } /* sign extened byte */
278 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
279 #define Iv { OP_I, v_mode }
280 #define sIv { OP_sI, v_mode }
281 #define Iv64 { OP_I64, v_mode }
282 #define Id { OP_I, d_mode }
283 #define Iw { OP_I, w_mode }
284 #define I1 { OP_I, const_1_mode }
285 #define Jb { OP_J, b_mode }
286 #define Jv { OP_J, v_mode }
287 #define Jdqw { OP_J, dqw_mode }
288 #define Cm { OP_C, m_mode }
289 #define Dm { OP_D, m_mode }
290 #define Td { OP_T, d_mode }
291 #define Skip_MODRM { OP_Skip_MODRM, 0 }
292
293 #define RMeAX { OP_REG, eAX_reg }
294 #define RMeBX { OP_REG, eBX_reg }
295 #define RMeCX { OP_REG, eCX_reg }
296 #define RMeDX { OP_REG, eDX_reg }
297 #define RMeSP { OP_REG, eSP_reg }
298 #define RMeBP { OP_REG, eBP_reg }
299 #define RMeSI { OP_REG, eSI_reg }
300 #define RMeDI { OP_REG, eDI_reg }
301 #define RMrAX { OP_REG, rAX_reg }
302 #define RMrBX { OP_REG, rBX_reg }
303 #define RMrCX { OP_REG, rCX_reg }
304 #define RMrDX { OP_REG, rDX_reg }
305 #define RMrSP { OP_REG, rSP_reg }
306 #define RMrBP { OP_REG, rBP_reg }
307 #define RMrSI { OP_REG, rSI_reg }
308 #define RMrDI { OP_REG, rDI_reg }
309 #define RMAL { OP_REG, al_reg }
310 #define RMCL { OP_REG, cl_reg }
311 #define RMDL { OP_REG, dl_reg }
312 #define RMBL { OP_REG, bl_reg }
313 #define RMAH { OP_REG, ah_reg }
314 #define RMCH { OP_REG, ch_reg }
315 #define RMDH { OP_REG, dh_reg }
316 #define RMBH { OP_REG, bh_reg }
317 #define RMAX { OP_REG, ax_reg }
318 #define RMDX { OP_REG, dx_reg }
319
320 #define eAX { OP_IMREG, eAX_reg }
321 #define AL { OP_IMREG, al_reg }
322 #define CL { OP_IMREG, cl_reg }
323 #define zAX { OP_IMREG, z_mode_ax_reg }
324 #define indirDX { OP_IMREG, indir_dx_reg }
325
326 #define Sw { OP_SEG, w_mode }
327 #define Sv { OP_SEG, v_mode }
328 #define Ap { OP_DIR, 0 }
329 #define Ob { OP_OFF64, b_mode }
330 #define Ov { OP_OFF64, v_mode }
331 #define Xb { OP_DSreg, eSI_reg }
332 #define Xv { OP_DSreg, eSI_reg }
333 #define Xz { OP_DSreg, eSI_reg }
334 #define Yb { OP_ESreg, eDI_reg }
335 #define Yv { OP_ESreg, eDI_reg }
336 #define DSBX { OP_DSreg, eBX_reg }
337
338 #define es { OP_REG, es_reg }
339 #define ss { OP_REG, ss_reg }
340 #define cs { OP_REG, cs_reg }
341 #define ds { OP_REG, ds_reg }
342 #define fs { OP_REG, fs_reg }
343 #define gs { OP_REG, gs_reg }
344
345 #define MX { OP_MMX, 0 }
346 #define XM { OP_XMM, 0 }
347 #define XMScalar { OP_XMM, scalar_mode }
348 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
349 #define XMM { OP_XMM, xmm_mode }
350 #define TMM { OP_XMM, tmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXbwUnit { OP_EX, bw_unit_mode }
357 #define EXw { OP_EX, w_mode }
358 #define EXd { OP_EX, d_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXq { OP_EX, q_mode }
361 #define EXqS { OP_EX, q_swap_mode }
362 #define EXx { OP_EX, x_mode }
363 #define EXxS { OP_EX, x_swap_mode }
364 #define EXxmm { OP_EX, xmm_mode }
365 #define EXymm { OP_EX, ymm_mode }
366 #define EXtmm { OP_EX, tmm_mode }
367 #define EXxmmq { OP_EX, xmmq_mode }
368 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
369 #define EXxmm_mb { OP_EX, xmm_mb_mode }
370 #define EXxmm_mw { OP_EX, xmm_mw_mode }
371 #define EXxmm_md { OP_EX, xmm_md_mode }
372 #define EXxmm_mq { OP_EX, xmm_mq_mode }
373 #define EXxmmdw { OP_EX, xmmdw_mode }
374 #define EXxmmqd { OP_EX, xmmqd_mode }
375 #define EXymmq { OP_EX, ymmq_mode }
376 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
377 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
378 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
379 #define MS { OP_MS, v_mode }
380 #define XS { OP_XS, v_mode }
381 #define EMCq { OP_EMC, q_mode }
382 #define MXC { OP_MXC, 0 }
383 #define OPSUF { OP_3DNowSuffix, 0 }
384 #define SEP { SEP_Fixup, 0 }
385 #define CMP { CMP_Fixup, 0 }
386 #define XMM0 { XMM_Fixup, 0 }
387 #define FXSAVE { FXSAVE_Fixup, 0 }
388
389 #define Vex { OP_VEX, vex_mode }
390 #define VexW { OP_VexW, vex_mode }
391 #define VexScalar { OP_VEX, vex_scalar_mode }
392 #define VexScalarR { OP_VexR, vex_scalar_mode }
393 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
394 #define VexGdq { OP_VEX, dq_mode }
395 #define VexTmm { OP_VEX, tmm_mode }
396 #define XMVexI4 { OP_REG_VexI4, x_mode }
397 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
398 #define VexI4 { OP_VexI4, 0 }
399 #define PCLMUL { PCLMUL_Fixup, 0 }
400 #define VPCMP { VPCMP_Fixup, 0 }
401 #define VPCOM { VPCOM_Fixup, 0 }
402
403 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
404 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
405 #define EXxEVexS { OP_Rounding, evex_sae_mode }
406
407 #define XMask { OP_Mask, mask_mode }
408 #define MaskG { OP_G, mask_mode }
409 #define MaskE { OP_E, mask_mode }
410 #define MaskBDE { OP_E, mask_bd_mode }
411 #define MaskVex { OP_VEX, mask_mode }
412
413 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
414 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
415 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
416 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
417
418 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
419
420 /* Used handle "rep" prefix for string instructions. */
421 #define Xbr { REP_Fixup, eSI_reg }
422 #define Xvr { REP_Fixup, eSI_reg }
423 #define Ybr { REP_Fixup, eDI_reg }
424 #define Yvr { REP_Fixup, eDI_reg }
425 #define Yzr { REP_Fixup, eDI_reg }
426 #define indirDXr { REP_Fixup, indir_dx_reg }
427 #define ALr { REP_Fixup, al_reg }
428 #define eAXr { REP_Fixup, eAX_reg }
429
430 /* Used handle HLE prefix for lockable instructions. */
431 #define Ebh1 { HLE_Fixup1, b_mode }
432 #define Evh1 { HLE_Fixup1, v_mode }
433 #define Ebh2 { HLE_Fixup2, b_mode }
434 #define Evh2 { HLE_Fixup2, v_mode }
435 #define Ebh3 { HLE_Fixup3, b_mode }
436 #define Evh3 { HLE_Fixup3, v_mode }
437
438 #define BND { BND_Fixup, 0 }
439 #define NOTRACK { NOTRACK_Fixup, 0 }
440
441 #define cond_jump_flag { NULL, cond_jump_mode }
442 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
443
444 /* bits in sizeflag */
445 #define SUFFIX_ALWAYS 4
446 #define AFLAG 2
447 #define DFLAG 1
448
449 enum
450 {
451 /* byte operand */
452 b_mode = 1,
453 /* byte operand with operand swapped */
454 b_swap_mode,
455 /* byte operand, sign extend like 'T' suffix */
456 b_T_mode,
457 /* operand size depends on prefixes */
458 v_mode,
459 /* operand size depends on prefixes with operand swapped */
460 v_swap_mode,
461 /* operand size depends on address prefix */
462 va_mode,
463 /* word operand */
464 w_mode,
465 /* double word operand */
466 d_mode,
467 /* double word operand with operand swapped */
468 d_swap_mode,
469 /* quad word operand */
470 q_mode,
471 /* quad word operand with operand swapped */
472 q_swap_mode,
473 /* ten-byte operand */
474 t_mode,
475 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
476 broadcast enabled. */
477 x_mode,
478 /* Similar to x_mode, but with different EVEX mem shifts. */
479 evex_x_gscat_mode,
480 /* Similar to x_mode, but with yet different EVEX mem shifts. */
481 bw_unit_mode,
482 /* Similar to x_mode, but with disabled broadcast. */
483 evex_x_nobcst_mode,
484 /* Similar to x_mode, but with operands swapped and disabled broadcast
485 in EVEX. */
486 x_swap_mode,
487 /* 16-byte XMM operand */
488 xmm_mode,
489 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
490 memory operand (depending on vector length). Broadcast isn't
491 allowed. */
492 xmmq_mode,
493 /* Same as xmmq_mode, but broadcast is allowed. */
494 evex_half_bcst_xmmq_mode,
495 /* XMM register or byte memory operand */
496 xmm_mb_mode,
497 /* XMM register or word memory operand */
498 xmm_mw_mode,
499 /* XMM register or double word memory operand */
500 xmm_md_mode,
501 /* XMM register or quad word memory operand */
502 xmm_mq_mode,
503 /* 16-byte XMM, word, double word or quad word operand. */
504 xmmdw_mode,
505 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
506 xmmqd_mode,
507 /* 32-byte YMM operand */
508 ymm_mode,
509 /* quad word, ymmword or zmmword memory operand. */
510 ymmq_mode,
511 /* 32-byte YMM or 16-byte word operand */
512 ymmxmm_mode,
513 /* TMM operand */
514 tmm_mode,
515 /* d_mode in 32bit, q_mode in 64bit mode. */
516 m_mode,
517 /* pair of v_mode operands */
518 a_mode,
519 cond_jump_mode,
520 loop_jcxz_mode,
521 movsxd_mode,
522 v_bnd_mode,
523 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
524 v_bndmk_mode,
525 /* operand size depends on REX prefixes. */
526 dq_mode,
527 /* registers like dq_mode, memory like w_mode, displacements like
528 v_mode without considering Intel64 ISA. */
529 dqw_mode,
530 /* bounds operand */
531 bnd_mode,
532 /* bounds operand with operand swapped */
533 bnd_swap_mode,
534 /* 4- or 6-byte pointer operand */
535 f_mode,
536 const_1_mode,
537 /* v_mode for indirect branch opcodes. */
538 indir_v_mode,
539 /* v_mode for stack-related opcodes. */
540 stack_v_mode,
541 /* non-quad operand size depends on prefixes */
542 z_mode,
543 /* 16-byte operand */
544 o_mode,
545 /* registers like dq_mode, memory like b_mode. */
546 dqb_mode,
547 /* registers like d_mode, memory like b_mode. */
548 db_mode,
549 /* registers like d_mode, memory like w_mode. */
550 dw_mode,
551 /* registers like dq_mode, memory like d_mode. */
552 dqd_mode,
553 /* normal vex mode */
554 vex_mode,
555
556 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
557 vex_vsib_d_w_dq_mode,
558 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
559 vex_vsib_d_w_d_mode,
560 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
561 vex_vsib_q_w_dq_mode,
562 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
563 vex_vsib_q_w_d_mode,
564 /* mandatory non-vector SIB. */
565 vex_sibmem_mode,
566
567 /* scalar, ignore vector length. */
568 scalar_mode,
569 /* like vex_mode, ignore vector length. */
570 vex_scalar_mode,
571 /* Operand size depends on the VEX.W bit, ignore vector length. */
572 vex_scalar_w_dq_mode,
573
574 /* Static rounding. */
575 evex_rounding_mode,
576 /* Static rounding, 64-bit mode only. */
577 evex_rounding_64_mode,
578 /* Supress all exceptions. */
579 evex_sae_mode,
580
581 /* Mask register operand. */
582 mask_mode,
583 /* Mask register operand. */
584 mask_bd_mode,
585
586 es_reg,
587 cs_reg,
588 ss_reg,
589 ds_reg,
590 fs_reg,
591 gs_reg,
592
593 eAX_reg,
594 eCX_reg,
595 eDX_reg,
596 eBX_reg,
597 eSP_reg,
598 eBP_reg,
599 eSI_reg,
600 eDI_reg,
601
602 al_reg,
603 cl_reg,
604 dl_reg,
605 bl_reg,
606 ah_reg,
607 ch_reg,
608 dh_reg,
609 bh_reg,
610
611 ax_reg,
612 cx_reg,
613 dx_reg,
614 bx_reg,
615 sp_reg,
616 bp_reg,
617 si_reg,
618 di_reg,
619
620 rAX_reg,
621 rCX_reg,
622 rDX_reg,
623 rBX_reg,
624 rSP_reg,
625 rBP_reg,
626 rSI_reg,
627 rDI_reg,
628
629 z_mode_ax_reg,
630 indir_dx_reg
631 };
632
633 enum
634 {
635 FLOATCODE = 1,
636 USE_REG_TABLE,
637 USE_MOD_TABLE,
638 USE_RM_TABLE,
639 USE_PREFIX_TABLE,
640 USE_X86_64_TABLE,
641 USE_3BYTE_TABLE,
642 USE_XOP_8F_TABLE,
643 USE_VEX_C4_TABLE,
644 USE_VEX_C5_TABLE,
645 USE_VEX_LEN_TABLE,
646 USE_VEX_W_TABLE,
647 USE_EVEX_TABLE,
648 USE_EVEX_LEN_TABLE
649 };
650
651 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
652
653 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
654 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
655 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
656 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
657 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
658 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
659 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
660 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
661 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
662 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
663 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
664 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
665 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
666 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
667 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
668 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
669
670 enum
671 {
672 REG_80 = 0,
673 REG_81,
674 REG_83,
675 REG_8F,
676 REG_C0,
677 REG_C1,
678 REG_C6,
679 REG_C7,
680 REG_D0,
681 REG_D1,
682 REG_D2,
683 REG_D3,
684 REG_F6,
685 REG_F7,
686 REG_FE,
687 REG_FF,
688 REG_0F00,
689 REG_0F01,
690 REG_0F0D,
691 REG_0F18,
692 REG_0F1C_P_0_MOD_0,
693 REG_0F1E_P_1_MOD_3,
694 REG_0F38D8_PREFIX_1,
695 REG_0F3A0F_PREFIX_1_MOD_3,
696 REG_0F71_MOD_0,
697 REG_0F72_MOD_0,
698 REG_0F73_MOD_0,
699 REG_0FA6,
700 REG_0FA7,
701 REG_0FAE,
702 REG_0FBA,
703 REG_0FC7,
704 REG_VEX_0F71_M_0,
705 REG_VEX_0F72_M_0,
706 REG_VEX_0F73_M_0,
707 REG_VEX_0FAE,
708 REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
709 REG_VEX_0F38F3_L_0,
710
711 REG_0FXOP_09_01_L_0,
712 REG_0FXOP_09_02_L_0,
713 REG_0FXOP_09_12_M_1_L_0,
714 REG_0FXOP_0A_12_L_0,
715
716 REG_EVEX_0F71,
717 REG_EVEX_0F72,
718 REG_EVEX_0F73,
719 REG_EVEX_0F38C6,
720 REG_EVEX_0F38C7
721 };
722
723 enum
724 {
725 MOD_8D = 0,
726 MOD_C6_REG_7,
727 MOD_C7_REG_7,
728 MOD_FF_REG_3,
729 MOD_FF_REG_5,
730 MOD_0F01_REG_0,
731 MOD_0F01_REG_1,
732 MOD_0F01_REG_2,
733 MOD_0F01_REG_3,
734 MOD_0F01_REG_5,
735 MOD_0F01_REG_7,
736 MOD_0F12_PREFIX_0,
737 MOD_0F12_PREFIX_2,
738 MOD_0F13,
739 MOD_0F16_PREFIX_0,
740 MOD_0F16_PREFIX_2,
741 MOD_0F17,
742 MOD_0F18_REG_0,
743 MOD_0F18_REG_1,
744 MOD_0F18_REG_2,
745 MOD_0F18_REG_3,
746 MOD_0F1A_PREFIX_0,
747 MOD_0F1B_PREFIX_0,
748 MOD_0F1B_PREFIX_1,
749 MOD_0F1C_PREFIX_0,
750 MOD_0F1E_PREFIX_1,
751 MOD_0F2B_PREFIX_0,
752 MOD_0F2B_PREFIX_1,
753 MOD_0F2B_PREFIX_2,
754 MOD_0F2B_PREFIX_3,
755 MOD_0F50,
756 MOD_0F71,
757 MOD_0F72,
758 MOD_0F73,
759 MOD_0FAE_REG_0,
760 MOD_0FAE_REG_1,
761 MOD_0FAE_REG_2,
762 MOD_0FAE_REG_3,
763 MOD_0FAE_REG_4,
764 MOD_0FAE_REG_5,
765 MOD_0FAE_REG_6,
766 MOD_0FAE_REG_7,
767 MOD_0FB2,
768 MOD_0FB4,
769 MOD_0FB5,
770 MOD_0FC3,
771 MOD_0FC7_REG_3,
772 MOD_0FC7_REG_4,
773 MOD_0FC7_REG_5,
774 MOD_0FC7_REG_6,
775 MOD_0FC7_REG_7,
776 MOD_0FD7,
777 MOD_0FE7_PREFIX_2,
778 MOD_0FF0_PREFIX_3,
779 MOD_0F382A,
780 MOD_0F38DC_PREFIX_1,
781 MOD_0F38DD_PREFIX_1,
782 MOD_0F38DE_PREFIX_1,
783 MOD_0F38DF_PREFIX_1,
784 MOD_0F38F5,
785 MOD_0F38F6_PREFIX_0,
786 MOD_0F38F8_PREFIX_1,
787 MOD_0F38F8_PREFIX_2,
788 MOD_0F38F8_PREFIX_3,
789 MOD_0F38F9,
790 MOD_0F38FA_PREFIX_1,
791 MOD_0F38FB_PREFIX_1,
792 MOD_0F3A0F_PREFIX_1,
793 MOD_62_32BIT,
794 MOD_C4_32BIT,
795 MOD_C5_32BIT,
796 MOD_VEX_0F12_PREFIX_0,
797 MOD_VEX_0F12_PREFIX_2,
798 MOD_VEX_0F13,
799 MOD_VEX_0F16_PREFIX_0,
800 MOD_VEX_0F16_PREFIX_2,
801 MOD_VEX_0F17,
802 MOD_VEX_0F2B,
803 MOD_VEX_0F41_L_1,
804 MOD_VEX_0F42_L_1,
805 MOD_VEX_0F44_L_0,
806 MOD_VEX_0F45_L_1,
807 MOD_VEX_0F46_L_1,
808 MOD_VEX_0F47_L_1,
809 MOD_VEX_0F4A_L_1,
810 MOD_VEX_0F4B_L_1,
811 MOD_VEX_0F50,
812 MOD_VEX_0F71,
813 MOD_VEX_0F72,
814 MOD_VEX_0F73,
815 MOD_VEX_0F91_L_0,
816 MOD_VEX_0F92_L_0,
817 MOD_VEX_0F93_L_0,
818 MOD_VEX_0F98_L_0,
819 MOD_VEX_0F99_L_0,
820 MOD_VEX_0FAE_REG_2,
821 MOD_VEX_0FAE_REG_3,
822 MOD_VEX_0FD7,
823 MOD_VEX_0FE7,
824 MOD_VEX_0FF0_PREFIX_3,
825 MOD_VEX_0F381A,
826 MOD_VEX_0F382A,
827 MOD_VEX_0F382C,
828 MOD_VEX_0F382D,
829 MOD_VEX_0F382E,
830 MOD_VEX_0F382F,
831 MOD_VEX_0F3849_X86_64_P_0_W_0,
832 MOD_VEX_0F3849_X86_64_P_2_W_0,
833 MOD_VEX_0F3849_X86_64_P_3_W_0,
834 MOD_VEX_0F384B_X86_64_P_1_W_0,
835 MOD_VEX_0F384B_X86_64_P_2_W_0,
836 MOD_VEX_0F384B_X86_64_P_3_W_0,
837 MOD_VEX_0F385A,
838 MOD_VEX_0F385C_X86_64_P_1_W_0,
839 MOD_VEX_0F385E_X86_64_P_0_W_0,
840 MOD_VEX_0F385E_X86_64_P_1_W_0,
841 MOD_VEX_0F385E_X86_64_P_2_W_0,
842 MOD_VEX_0F385E_X86_64_P_3_W_0,
843 MOD_VEX_0F388C,
844 MOD_VEX_0F388E,
845 MOD_VEX_0F3A30_L_0,
846 MOD_VEX_0F3A31_L_0,
847 MOD_VEX_0F3A32_L_0,
848 MOD_VEX_0F3A33_L_0,
849
850 MOD_VEX_0FXOP_09_12,
851
852 MOD_EVEX_0F12_PREFIX_0,
853 MOD_EVEX_0F12_PREFIX_2,
854 MOD_EVEX_0F13,
855 MOD_EVEX_0F16_PREFIX_0,
856 MOD_EVEX_0F16_PREFIX_2,
857 MOD_EVEX_0F17,
858 MOD_EVEX_0F2B,
859 MOD_EVEX_0F381A_W_0,
860 MOD_EVEX_0F381A_W_1,
861 MOD_EVEX_0F381B_W_0,
862 MOD_EVEX_0F381B_W_1,
863 MOD_EVEX_0F3828_P_1,
864 MOD_EVEX_0F382A_P_1_W_1,
865 MOD_EVEX_0F3838_P_1,
866 MOD_EVEX_0F383A_P_1_W_0,
867 MOD_EVEX_0F385A_W_0,
868 MOD_EVEX_0F385A_W_1,
869 MOD_EVEX_0F385B_W_0,
870 MOD_EVEX_0F385B_W_1,
871 MOD_EVEX_0F387A_W_0,
872 MOD_EVEX_0F387B_W_0,
873 MOD_EVEX_0F387C,
874 MOD_EVEX_0F38C6_REG_1,
875 MOD_EVEX_0F38C6_REG_2,
876 MOD_EVEX_0F38C6_REG_5,
877 MOD_EVEX_0F38C6_REG_6,
878 MOD_EVEX_0F38C7_REG_1,
879 MOD_EVEX_0F38C7_REG_2,
880 MOD_EVEX_0F38C7_REG_5,
881 MOD_EVEX_0F38C7_REG_6
882 };
883
884 enum
885 {
886 RM_C6_REG_7 = 0,
887 RM_C7_REG_7,
888 RM_0F01_REG_0,
889 RM_0F01_REG_1,
890 RM_0F01_REG_2,
891 RM_0F01_REG_3,
892 RM_0F01_REG_5_MOD_3,
893 RM_0F01_REG_7_MOD_3,
894 RM_0F1E_P_1_MOD_3_REG_7,
895 RM_0F3A0F_P_1_MOD_3_REG_0,
896 RM_0FAE_REG_6_MOD_3_P_0,
897 RM_0FAE_REG_7_MOD_3,
898 RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
899 };
900
901 enum
902 {
903 PREFIX_90 = 0,
904 PREFIX_0F01_REG_1_RM_4,
905 PREFIX_0F01_REG_1_RM_5,
906 PREFIX_0F01_REG_1_RM_6,
907 PREFIX_0F01_REG_1_RM_7,
908 PREFIX_0F01_REG_3_RM_1,
909 PREFIX_0F01_REG_5_MOD_0,
910 PREFIX_0F01_REG_5_MOD_3_RM_0,
911 PREFIX_0F01_REG_5_MOD_3_RM_1,
912 PREFIX_0F01_REG_5_MOD_3_RM_2,
913 PREFIX_0F01_REG_5_MOD_3_RM_4,
914 PREFIX_0F01_REG_5_MOD_3_RM_5,
915 PREFIX_0F01_REG_5_MOD_3_RM_6,
916 PREFIX_0F01_REG_5_MOD_3_RM_7,
917 PREFIX_0F01_REG_7_MOD_3_RM_2,
918 PREFIX_0F01_REG_7_MOD_3_RM_6,
919 PREFIX_0F01_REG_7_MOD_3_RM_7,
920 PREFIX_0F09,
921 PREFIX_0F10,
922 PREFIX_0F11,
923 PREFIX_0F12,
924 PREFIX_0F16,
925 PREFIX_0F1A,
926 PREFIX_0F1B,
927 PREFIX_0F1C,
928 PREFIX_0F1E,
929 PREFIX_0F2A,
930 PREFIX_0F2B,
931 PREFIX_0F2C,
932 PREFIX_0F2D,
933 PREFIX_0F2E,
934 PREFIX_0F2F,
935 PREFIX_0F51,
936 PREFIX_0F52,
937 PREFIX_0F53,
938 PREFIX_0F58,
939 PREFIX_0F59,
940 PREFIX_0F5A,
941 PREFIX_0F5B,
942 PREFIX_0F5C,
943 PREFIX_0F5D,
944 PREFIX_0F5E,
945 PREFIX_0F5F,
946 PREFIX_0F60,
947 PREFIX_0F61,
948 PREFIX_0F62,
949 PREFIX_0F6F,
950 PREFIX_0F70,
951 PREFIX_0F78,
952 PREFIX_0F79,
953 PREFIX_0F7C,
954 PREFIX_0F7D,
955 PREFIX_0F7E,
956 PREFIX_0F7F,
957 PREFIX_0FAE_REG_0_MOD_3,
958 PREFIX_0FAE_REG_1_MOD_3,
959 PREFIX_0FAE_REG_2_MOD_3,
960 PREFIX_0FAE_REG_3_MOD_3,
961 PREFIX_0FAE_REG_4_MOD_0,
962 PREFIX_0FAE_REG_4_MOD_3,
963 PREFIX_0FAE_REG_5_MOD_3,
964 PREFIX_0FAE_REG_6_MOD_0,
965 PREFIX_0FAE_REG_6_MOD_3,
966 PREFIX_0FAE_REG_7_MOD_0,
967 PREFIX_0FB8,
968 PREFIX_0FBC,
969 PREFIX_0FBD,
970 PREFIX_0FC2,
971 PREFIX_0FC7_REG_6_MOD_0,
972 PREFIX_0FC7_REG_6_MOD_3,
973 PREFIX_0FC7_REG_7_MOD_3,
974 PREFIX_0FD0,
975 PREFIX_0FD6,
976 PREFIX_0FE6,
977 PREFIX_0FE7,
978 PREFIX_0FF0,
979 PREFIX_0FF7,
980 PREFIX_0F38D8,
981 PREFIX_0F38DC,
982 PREFIX_0F38DD,
983 PREFIX_0F38DE,
984 PREFIX_0F38DF,
985 PREFIX_0F38F0,
986 PREFIX_0F38F1,
987 PREFIX_0F38F6,
988 PREFIX_0F38F8,
989 PREFIX_0F38FA,
990 PREFIX_0F38FB,
991 PREFIX_0F3A0F,
992 PREFIX_VEX_0F10,
993 PREFIX_VEX_0F11,
994 PREFIX_VEX_0F12,
995 PREFIX_VEX_0F16,
996 PREFIX_VEX_0F2A,
997 PREFIX_VEX_0F2C,
998 PREFIX_VEX_0F2D,
999 PREFIX_VEX_0F2E,
1000 PREFIX_VEX_0F2F,
1001 PREFIX_VEX_0F41_L_1_M_1_W_0,
1002 PREFIX_VEX_0F41_L_1_M_1_W_1,
1003 PREFIX_VEX_0F42_L_1_M_1_W_0,
1004 PREFIX_VEX_0F42_L_1_M_1_W_1,
1005 PREFIX_VEX_0F44_L_0_M_1_W_0,
1006 PREFIX_VEX_0F44_L_0_M_1_W_1,
1007 PREFIX_VEX_0F45_L_1_M_1_W_0,
1008 PREFIX_VEX_0F45_L_1_M_1_W_1,
1009 PREFIX_VEX_0F46_L_1_M_1_W_0,
1010 PREFIX_VEX_0F46_L_1_M_1_W_1,
1011 PREFIX_VEX_0F47_L_1_M_1_W_0,
1012 PREFIX_VEX_0F47_L_1_M_1_W_1,
1013 PREFIX_VEX_0F4A_L_1_M_1_W_0,
1014 PREFIX_VEX_0F4A_L_1_M_1_W_1,
1015 PREFIX_VEX_0F4B_L_1_M_1_W_0,
1016 PREFIX_VEX_0F4B_L_1_M_1_W_1,
1017 PREFIX_VEX_0F51,
1018 PREFIX_VEX_0F52,
1019 PREFIX_VEX_0F53,
1020 PREFIX_VEX_0F58,
1021 PREFIX_VEX_0F59,
1022 PREFIX_VEX_0F5A,
1023 PREFIX_VEX_0F5B,
1024 PREFIX_VEX_0F5C,
1025 PREFIX_VEX_0F5D,
1026 PREFIX_VEX_0F5E,
1027 PREFIX_VEX_0F5F,
1028 PREFIX_VEX_0F6F,
1029 PREFIX_VEX_0F70,
1030 PREFIX_VEX_0F7C,
1031 PREFIX_VEX_0F7D,
1032 PREFIX_VEX_0F7E,
1033 PREFIX_VEX_0F7F,
1034 PREFIX_VEX_0F90_L_0_W_0,
1035 PREFIX_VEX_0F90_L_0_W_1,
1036 PREFIX_VEX_0F91_L_0_M_0_W_0,
1037 PREFIX_VEX_0F91_L_0_M_0_W_1,
1038 PREFIX_VEX_0F92_L_0_M_1_W_0,
1039 PREFIX_VEX_0F92_L_0_M_1_W_1,
1040 PREFIX_VEX_0F93_L_0_M_1_W_0,
1041 PREFIX_VEX_0F93_L_0_M_1_W_1,
1042 PREFIX_VEX_0F98_L_0_M_1_W_0,
1043 PREFIX_VEX_0F98_L_0_M_1_W_1,
1044 PREFIX_VEX_0F99_L_0_M_1_W_0,
1045 PREFIX_VEX_0F99_L_0_M_1_W_1,
1046 PREFIX_VEX_0FC2,
1047 PREFIX_VEX_0FD0,
1048 PREFIX_VEX_0FE6,
1049 PREFIX_VEX_0FF0,
1050 PREFIX_VEX_0F3849_X86_64,
1051 PREFIX_VEX_0F384B_X86_64,
1052 PREFIX_VEX_0F385C_X86_64,
1053 PREFIX_VEX_0F385E_X86_64,
1054 PREFIX_VEX_0F38F5_L_0,
1055 PREFIX_VEX_0F38F6_L_0,
1056 PREFIX_VEX_0F38F7_L_0,
1057 PREFIX_VEX_0F3AF0_L_0,
1058
1059 PREFIX_EVEX_0F10,
1060 PREFIX_EVEX_0F11,
1061 PREFIX_EVEX_0F12,
1062 PREFIX_EVEX_0F16,
1063 PREFIX_EVEX_0F2A,
1064 PREFIX_EVEX_0F51,
1065 PREFIX_EVEX_0F58,
1066 PREFIX_EVEX_0F59,
1067 PREFIX_EVEX_0F5A,
1068 PREFIX_EVEX_0F5B,
1069 PREFIX_EVEX_0F5C,
1070 PREFIX_EVEX_0F5D,
1071 PREFIX_EVEX_0F5E,
1072 PREFIX_EVEX_0F5F,
1073 PREFIX_EVEX_0F6F,
1074 PREFIX_EVEX_0F70,
1075 PREFIX_EVEX_0F78,
1076 PREFIX_EVEX_0F79,
1077 PREFIX_EVEX_0F7A,
1078 PREFIX_EVEX_0F7B,
1079 PREFIX_EVEX_0F7E,
1080 PREFIX_EVEX_0F7F,
1081 PREFIX_EVEX_0FC2,
1082 PREFIX_EVEX_0FE6,
1083 PREFIX_EVEX_0F3810,
1084 PREFIX_EVEX_0F3811,
1085 PREFIX_EVEX_0F3812,
1086 PREFIX_EVEX_0F3813,
1087 PREFIX_EVEX_0F3814,
1088 PREFIX_EVEX_0F3815,
1089 PREFIX_EVEX_0F3820,
1090 PREFIX_EVEX_0F3821,
1091 PREFIX_EVEX_0F3822,
1092 PREFIX_EVEX_0F3823,
1093 PREFIX_EVEX_0F3824,
1094 PREFIX_EVEX_0F3825,
1095 PREFIX_EVEX_0F3826,
1096 PREFIX_EVEX_0F3827,
1097 PREFIX_EVEX_0F3828,
1098 PREFIX_EVEX_0F3829,
1099 PREFIX_EVEX_0F382A,
1100 PREFIX_EVEX_0F3830,
1101 PREFIX_EVEX_0F3831,
1102 PREFIX_EVEX_0F3832,
1103 PREFIX_EVEX_0F3833,
1104 PREFIX_EVEX_0F3834,
1105 PREFIX_EVEX_0F3835,
1106 PREFIX_EVEX_0F3838,
1107 PREFIX_EVEX_0F3839,
1108 PREFIX_EVEX_0F383A,
1109 PREFIX_EVEX_0F3852,
1110 PREFIX_EVEX_0F3853,
1111 PREFIX_EVEX_0F3868,
1112 PREFIX_EVEX_0F3872,
1113 PREFIX_EVEX_0F389A,
1114 PREFIX_EVEX_0F389B,
1115 PREFIX_EVEX_0F38AA,
1116 PREFIX_EVEX_0F38AB,
1117 };
1118
1119 enum
1120 {
1121 X86_64_06 = 0,
1122 X86_64_07,
1123 X86_64_0E,
1124 X86_64_16,
1125 X86_64_17,
1126 X86_64_1E,
1127 X86_64_1F,
1128 X86_64_27,
1129 X86_64_2F,
1130 X86_64_37,
1131 X86_64_3F,
1132 X86_64_60,
1133 X86_64_61,
1134 X86_64_62,
1135 X86_64_63,
1136 X86_64_6D,
1137 X86_64_6F,
1138 X86_64_82,
1139 X86_64_9A,
1140 X86_64_C2,
1141 X86_64_C3,
1142 X86_64_C4,
1143 X86_64_C5,
1144 X86_64_CE,
1145 X86_64_D4,
1146 X86_64_D5,
1147 X86_64_E8,
1148 X86_64_E9,
1149 X86_64_EA,
1150 X86_64_0F01_REG_0,
1151 X86_64_0F01_REG_1,
1152 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1153 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1154 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1155 X86_64_0F01_REG_2,
1156 X86_64_0F01_REG_3,
1157 X86_64_0F24,
1158 X86_64_0F26,
1159 X86_64_VEX_0F3849,
1160 X86_64_VEX_0F384B,
1161 X86_64_VEX_0F385C,
1162 X86_64_VEX_0F385E,
1163 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1164 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1165 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1166 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1167 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1168 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1169 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1170 X86_64_0FC7_REG_6_MOD_3_PREFIX_1
1171 };
1172
1173 enum
1174 {
1175 THREE_BYTE_0F38 = 0,
1176 THREE_BYTE_0F3A
1177 };
1178
1179 enum
1180 {
1181 XOP_08 = 0,
1182 XOP_09,
1183 XOP_0A
1184 };
1185
1186 enum
1187 {
1188 VEX_0F = 0,
1189 VEX_0F38,
1190 VEX_0F3A
1191 };
1192
1193 enum
1194 {
1195 EVEX_0F = 0,
1196 EVEX_0F38,
1197 EVEX_0F3A
1198 };
1199
1200 enum
1201 {
1202 VEX_LEN_0F12_P_0_M_0 = 0,
1203 VEX_LEN_0F12_P_0_M_1,
1204 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1205 VEX_LEN_0F13_M_0,
1206 VEX_LEN_0F16_P_0_M_0,
1207 VEX_LEN_0F16_P_0_M_1,
1208 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1209 VEX_LEN_0F17_M_0,
1210 VEX_LEN_0F41,
1211 VEX_LEN_0F42,
1212 VEX_LEN_0F44,
1213 VEX_LEN_0F45,
1214 VEX_LEN_0F46,
1215 VEX_LEN_0F47,
1216 VEX_LEN_0F4A,
1217 VEX_LEN_0F4B,
1218 VEX_LEN_0F6E,
1219 VEX_LEN_0F77,
1220 VEX_LEN_0F7E_P_1,
1221 VEX_LEN_0F7E_P_2,
1222 VEX_LEN_0F90,
1223 VEX_LEN_0F91,
1224 VEX_LEN_0F92,
1225 VEX_LEN_0F93,
1226 VEX_LEN_0F98,
1227 VEX_LEN_0F99,
1228 VEX_LEN_0FAE_R_2_M_0,
1229 VEX_LEN_0FAE_R_3_M_0,
1230 VEX_LEN_0FC4,
1231 VEX_LEN_0FC5,
1232 VEX_LEN_0FD6,
1233 VEX_LEN_0FF7,
1234 VEX_LEN_0F3816,
1235 VEX_LEN_0F3819,
1236 VEX_LEN_0F381A_M_0,
1237 VEX_LEN_0F3836,
1238 VEX_LEN_0F3841,
1239 VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1240 VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1241 VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1242 VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1243 VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1244 VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1245 VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1246 VEX_LEN_0F385A_M_0,
1247 VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1248 VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1249 VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1250 VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1251 VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1252 VEX_LEN_0F38DB,
1253 VEX_LEN_0F38F2,
1254 VEX_LEN_0F38F3,
1255 VEX_LEN_0F38F5,
1256 VEX_LEN_0F38F6,
1257 VEX_LEN_0F38F7,
1258 VEX_LEN_0F3A00,
1259 VEX_LEN_0F3A01,
1260 VEX_LEN_0F3A06,
1261 VEX_LEN_0F3A14,
1262 VEX_LEN_0F3A15,
1263 VEX_LEN_0F3A16,
1264 VEX_LEN_0F3A17,
1265 VEX_LEN_0F3A18,
1266 VEX_LEN_0F3A19,
1267 VEX_LEN_0F3A20,
1268 VEX_LEN_0F3A21,
1269 VEX_LEN_0F3A22,
1270 VEX_LEN_0F3A30,
1271 VEX_LEN_0F3A31,
1272 VEX_LEN_0F3A32,
1273 VEX_LEN_0F3A33,
1274 VEX_LEN_0F3A38,
1275 VEX_LEN_0F3A39,
1276 VEX_LEN_0F3A41,
1277 VEX_LEN_0F3A46,
1278 VEX_LEN_0F3A60,
1279 VEX_LEN_0F3A61,
1280 VEX_LEN_0F3A62,
1281 VEX_LEN_0F3A63,
1282 VEX_LEN_0F3ADF,
1283 VEX_LEN_0F3AF0,
1284 VEX_LEN_0FXOP_08_85,
1285 VEX_LEN_0FXOP_08_86,
1286 VEX_LEN_0FXOP_08_87,
1287 VEX_LEN_0FXOP_08_8E,
1288 VEX_LEN_0FXOP_08_8F,
1289 VEX_LEN_0FXOP_08_95,
1290 VEX_LEN_0FXOP_08_96,
1291 VEX_LEN_0FXOP_08_97,
1292 VEX_LEN_0FXOP_08_9E,
1293 VEX_LEN_0FXOP_08_9F,
1294 VEX_LEN_0FXOP_08_A3,
1295 VEX_LEN_0FXOP_08_A6,
1296 VEX_LEN_0FXOP_08_B6,
1297 VEX_LEN_0FXOP_08_C0,
1298 VEX_LEN_0FXOP_08_C1,
1299 VEX_LEN_0FXOP_08_C2,
1300 VEX_LEN_0FXOP_08_C3,
1301 VEX_LEN_0FXOP_08_CC,
1302 VEX_LEN_0FXOP_08_CD,
1303 VEX_LEN_0FXOP_08_CE,
1304 VEX_LEN_0FXOP_08_CF,
1305 VEX_LEN_0FXOP_08_EC,
1306 VEX_LEN_0FXOP_08_ED,
1307 VEX_LEN_0FXOP_08_EE,
1308 VEX_LEN_0FXOP_08_EF,
1309 VEX_LEN_0FXOP_09_01,
1310 VEX_LEN_0FXOP_09_02,
1311 VEX_LEN_0FXOP_09_12_M_1,
1312 VEX_LEN_0FXOP_09_82_W_0,
1313 VEX_LEN_0FXOP_09_83_W_0,
1314 VEX_LEN_0FXOP_09_90,
1315 VEX_LEN_0FXOP_09_91,
1316 VEX_LEN_0FXOP_09_92,
1317 VEX_LEN_0FXOP_09_93,
1318 VEX_LEN_0FXOP_09_94,
1319 VEX_LEN_0FXOP_09_95,
1320 VEX_LEN_0FXOP_09_96,
1321 VEX_LEN_0FXOP_09_97,
1322 VEX_LEN_0FXOP_09_98,
1323 VEX_LEN_0FXOP_09_99,
1324 VEX_LEN_0FXOP_09_9A,
1325 VEX_LEN_0FXOP_09_9B,
1326 VEX_LEN_0FXOP_09_C1,
1327 VEX_LEN_0FXOP_09_C2,
1328 VEX_LEN_0FXOP_09_C3,
1329 VEX_LEN_0FXOP_09_C6,
1330 VEX_LEN_0FXOP_09_C7,
1331 VEX_LEN_0FXOP_09_CB,
1332 VEX_LEN_0FXOP_09_D1,
1333 VEX_LEN_0FXOP_09_D2,
1334 VEX_LEN_0FXOP_09_D3,
1335 VEX_LEN_0FXOP_09_D6,
1336 VEX_LEN_0FXOP_09_D7,
1337 VEX_LEN_0FXOP_09_DB,
1338 VEX_LEN_0FXOP_09_E1,
1339 VEX_LEN_0FXOP_09_E2,
1340 VEX_LEN_0FXOP_09_E3,
1341 VEX_LEN_0FXOP_0A_12,
1342 };
1343
1344 enum
1345 {
1346 EVEX_LEN_0F6E = 0,
1347 EVEX_LEN_0F7E_P_1,
1348 EVEX_LEN_0F7E_P_2,
1349 EVEX_LEN_0FC4,
1350 EVEX_LEN_0FC5,
1351 EVEX_LEN_0FD6,
1352 EVEX_LEN_0F3816,
1353 EVEX_LEN_0F3819_W_0,
1354 EVEX_LEN_0F3819_W_1,
1355 EVEX_LEN_0F381A_W_0_M_0,
1356 EVEX_LEN_0F381A_W_1_M_0,
1357 EVEX_LEN_0F381B_W_0_M_0,
1358 EVEX_LEN_0F381B_W_1_M_0,
1359 EVEX_LEN_0F3836,
1360 EVEX_LEN_0F385A_W_0_M_0,
1361 EVEX_LEN_0F385A_W_1_M_0,
1362 EVEX_LEN_0F385B_W_0_M_0,
1363 EVEX_LEN_0F385B_W_1_M_0,
1364 EVEX_LEN_0F38C6_R_1_M_0,
1365 EVEX_LEN_0F38C6_R_2_M_0,
1366 EVEX_LEN_0F38C6_R_5_M_0,
1367 EVEX_LEN_0F38C6_R_6_M_0,
1368 EVEX_LEN_0F38C7_R_1_M_0_W_0,
1369 EVEX_LEN_0F38C7_R_1_M_0_W_1,
1370 EVEX_LEN_0F38C7_R_2_M_0_W_0,
1371 EVEX_LEN_0F38C7_R_2_M_0_W_1,
1372 EVEX_LEN_0F38C7_R_5_M_0_W_0,
1373 EVEX_LEN_0F38C7_R_5_M_0_W_1,
1374 EVEX_LEN_0F38C7_R_6_M_0_W_0,
1375 EVEX_LEN_0F38C7_R_6_M_0_W_1,
1376 EVEX_LEN_0F3A00_W_1,
1377 EVEX_LEN_0F3A01_W_1,
1378 EVEX_LEN_0F3A14,
1379 EVEX_LEN_0F3A15,
1380 EVEX_LEN_0F3A16,
1381 EVEX_LEN_0F3A17,
1382 EVEX_LEN_0F3A18_W_0,
1383 EVEX_LEN_0F3A18_W_1,
1384 EVEX_LEN_0F3A19_W_0,
1385 EVEX_LEN_0F3A19_W_1,
1386 EVEX_LEN_0F3A1A_W_0,
1387 EVEX_LEN_0F3A1A_W_1,
1388 EVEX_LEN_0F3A1B_W_0,
1389 EVEX_LEN_0F3A1B_W_1,
1390 EVEX_LEN_0F3A20,
1391 EVEX_LEN_0F3A21_W_0,
1392 EVEX_LEN_0F3A22,
1393 EVEX_LEN_0F3A23_W_0,
1394 EVEX_LEN_0F3A23_W_1,
1395 EVEX_LEN_0F3A38_W_0,
1396 EVEX_LEN_0F3A38_W_1,
1397 EVEX_LEN_0F3A39_W_0,
1398 EVEX_LEN_0F3A39_W_1,
1399 EVEX_LEN_0F3A3A_W_0,
1400 EVEX_LEN_0F3A3A_W_1,
1401 EVEX_LEN_0F3A3B_W_0,
1402 EVEX_LEN_0F3A3B_W_1,
1403 EVEX_LEN_0F3A43_W_0,
1404 EVEX_LEN_0F3A43_W_1
1405 };
1406
1407 enum
1408 {
1409 VEX_W_0F41_L_1_M_1 = 0,
1410 VEX_W_0F42_L_1_M_1,
1411 VEX_W_0F44_L_0_M_1,
1412 VEX_W_0F45_L_1_M_1,
1413 VEX_W_0F46_L_1_M_1,
1414 VEX_W_0F47_L_1_M_1,
1415 VEX_W_0F4A_L_1_M_1,
1416 VEX_W_0F4B_L_1_M_1,
1417 VEX_W_0F90_L_0,
1418 VEX_W_0F91_L_0_M_0,
1419 VEX_W_0F92_L_0_M_1,
1420 VEX_W_0F93_L_0_M_1,
1421 VEX_W_0F98_L_0_M_1,
1422 VEX_W_0F99_L_0_M_1,
1423 VEX_W_0F380C,
1424 VEX_W_0F380D,
1425 VEX_W_0F380E,
1426 VEX_W_0F380F,
1427 VEX_W_0F3813,
1428 VEX_W_0F3816_L_1,
1429 VEX_W_0F3818,
1430 VEX_W_0F3819_L_1,
1431 VEX_W_0F381A_M_0_L_1,
1432 VEX_W_0F382C_M_0,
1433 VEX_W_0F382D_M_0,
1434 VEX_W_0F382E_M_0,
1435 VEX_W_0F382F_M_0,
1436 VEX_W_0F3836,
1437 VEX_W_0F3846,
1438 VEX_W_0F3849_X86_64_P_0,
1439 VEX_W_0F3849_X86_64_P_2,
1440 VEX_W_0F3849_X86_64_P_3,
1441 VEX_W_0F384B_X86_64_P_1,
1442 VEX_W_0F384B_X86_64_P_2,
1443 VEX_W_0F384B_X86_64_P_3,
1444 VEX_W_0F3850,
1445 VEX_W_0F3851,
1446 VEX_W_0F3852,
1447 VEX_W_0F3853,
1448 VEX_W_0F3858,
1449 VEX_W_0F3859,
1450 VEX_W_0F385A_M_0_L_0,
1451 VEX_W_0F385C_X86_64_P_1,
1452 VEX_W_0F385E_X86_64_P_0,
1453 VEX_W_0F385E_X86_64_P_1,
1454 VEX_W_0F385E_X86_64_P_2,
1455 VEX_W_0F385E_X86_64_P_3,
1456 VEX_W_0F3878,
1457 VEX_W_0F3879,
1458 VEX_W_0F38CF,
1459 VEX_W_0F3A00_L_1,
1460 VEX_W_0F3A01_L_1,
1461 VEX_W_0F3A02,
1462 VEX_W_0F3A04,
1463 VEX_W_0F3A05,
1464 VEX_W_0F3A06_L_1,
1465 VEX_W_0F3A18_L_1,
1466 VEX_W_0F3A19_L_1,
1467 VEX_W_0F3A1D,
1468 VEX_W_0F3A38_L_1,
1469 VEX_W_0F3A39_L_1,
1470 VEX_W_0F3A46_L_1,
1471 VEX_W_0F3A4A,
1472 VEX_W_0F3A4B,
1473 VEX_W_0F3A4C,
1474 VEX_W_0F3ACE,
1475 VEX_W_0F3ACF,
1476
1477 VEX_W_0FXOP_08_85_L_0,
1478 VEX_W_0FXOP_08_86_L_0,
1479 VEX_W_0FXOP_08_87_L_0,
1480 VEX_W_0FXOP_08_8E_L_0,
1481 VEX_W_0FXOP_08_8F_L_0,
1482 VEX_W_0FXOP_08_95_L_0,
1483 VEX_W_0FXOP_08_96_L_0,
1484 VEX_W_0FXOP_08_97_L_0,
1485 VEX_W_0FXOP_08_9E_L_0,
1486 VEX_W_0FXOP_08_9F_L_0,
1487 VEX_W_0FXOP_08_A6_L_0,
1488 VEX_W_0FXOP_08_B6_L_0,
1489 VEX_W_0FXOP_08_C0_L_0,
1490 VEX_W_0FXOP_08_C1_L_0,
1491 VEX_W_0FXOP_08_C2_L_0,
1492 VEX_W_0FXOP_08_C3_L_0,
1493 VEX_W_0FXOP_08_CC_L_0,
1494 VEX_W_0FXOP_08_CD_L_0,
1495 VEX_W_0FXOP_08_CE_L_0,
1496 VEX_W_0FXOP_08_CF_L_0,
1497 VEX_W_0FXOP_08_EC_L_0,
1498 VEX_W_0FXOP_08_ED_L_0,
1499 VEX_W_0FXOP_08_EE_L_0,
1500 VEX_W_0FXOP_08_EF_L_0,
1501
1502 VEX_W_0FXOP_09_80,
1503 VEX_W_0FXOP_09_81,
1504 VEX_W_0FXOP_09_82,
1505 VEX_W_0FXOP_09_83,
1506 VEX_W_0FXOP_09_C1_L_0,
1507 VEX_W_0FXOP_09_C2_L_0,
1508 VEX_W_0FXOP_09_C3_L_0,
1509 VEX_W_0FXOP_09_C6_L_0,
1510 VEX_W_0FXOP_09_C7_L_0,
1511 VEX_W_0FXOP_09_CB_L_0,
1512 VEX_W_0FXOP_09_D1_L_0,
1513 VEX_W_0FXOP_09_D2_L_0,
1514 VEX_W_0FXOP_09_D3_L_0,
1515 VEX_W_0FXOP_09_D6_L_0,
1516 VEX_W_0FXOP_09_D7_L_0,
1517 VEX_W_0FXOP_09_DB_L_0,
1518 VEX_W_0FXOP_09_E1_L_0,
1519 VEX_W_0FXOP_09_E2_L_0,
1520 VEX_W_0FXOP_09_E3_L_0,
1521
1522 EVEX_W_0F10_P_1,
1523 EVEX_W_0F10_P_3,
1524 EVEX_W_0F11_P_1,
1525 EVEX_W_0F11_P_3,
1526 EVEX_W_0F12_P_0_M_1,
1527 EVEX_W_0F12_P_1,
1528 EVEX_W_0F12_P_3,
1529 EVEX_W_0F16_P_0_M_1,
1530 EVEX_W_0F16_P_1,
1531 EVEX_W_0F2A_P_3,
1532 EVEX_W_0F51_P_1,
1533 EVEX_W_0F51_P_3,
1534 EVEX_W_0F58_P_1,
1535 EVEX_W_0F58_P_3,
1536 EVEX_W_0F59_P_1,
1537 EVEX_W_0F59_P_3,
1538 EVEX_W_0F5A_P_0,
1539 EVEX_W_0F5A_P_1,
1540 EVEX_W_0F5A_P_2,
1541 EVEX_W_0F5A_P_3,
1542 EVEX_W_0F5B_P_0,
1543 EVEX_W_0F5B_P_1,
1544 EVEX_W_0F5B_P_2,
1545 EVEX_W_0F5C_P_1,
1546 EVEX_W_0F5C_P_3,
1547 EVEX_W_0F5D_P_1,
1548 EVEX_W_0F5D_P_3,
1549 EVEX_W_0F5E_P_1,
1550 EVEX_W_0F5E_P_3,
1551 EVEX_W_0F5F_P_1,
1552 EVEX_W_0F5F_P_3,
1553 EVEX_W_0F62,
1554 EVEX_W_0F66,
1555 EVEX_W_0F6A,
1556 EVEX_W_0F6B,
1557 EVEX_W_0F6C,
1558 EVEX_W_0F6D,
1559 EVEX_W_0F6F_P_1,
1560 EVEX_W_0F6F_P_2,
1561 EVEX_W_0F6F_P_3,
1562 EVEX_W_0F70_P_2,
1563 EVEX_W_0F72_R_2,
1564 EVEX_W_0F72_R_6,
1565 EVEX_W_0F73_R_2,
1566 EVEX_W_0F73_R_6,
1567 EVEX_W_0F76,
1568 EVEX_W_0F78_P_0,
1569 EVEX_W_0F78_P_2,
1570 EVEX_W_0F79_P_0,
1571 EVEX_W_0F79_P_2,
1572 EVEX_W_0F7A_P_1,
1573 EVEX_W_0F7A_P_2,
1574 EVEX_W_0F7A_P_3,
1575 EVEX_W_0F7B_P_2,
1576 EVEX_W_0F7B_P_3,
1577 EVEX_W_0F7E_P_1,
1578 EVEX_W_0F7F_P_1,
1579 EVEX_W_0F7F_P_2,
1580 EVEX_W_0F7F_P_3,
1581 EVEX_W_0FC2_P_1,
1582 EVEX_W_0FC2_P_3,
1583 EVEX_W_0FD2,
1584 EVEX_W_0FD3,
1585 EVEX_W_0FD4,
1586 EVEX_W_0FD6_L_0,
1587 EVEX_W_0FE6_P_1,
1588 EVEX_W_0FE6_P_2,
1589 EVEX_W_0FE6_P_3,
1590 EVEX_W_0FE7,
1591 EVEX_W_0FF2,
1592 EVEX_W_0FF3,
1593 EVEX_W_0FF4,
1594 EVEX_W_0FFA,
1595 EVEX_W_0FFB,
1596 EVEX_W_0FFE,
1597 EVEX_W_0F380D,
1598 EVEX_W_0F3810_P_1,
1599 EVEX_W_0F3810_P_2,
1600 EVEX_W_0F3811_P_1,
1601 EVEX_W_0F3811_P_2,
1602 EVEX_W_0F3812_P_1,
1603 EVEX_W_0F3812_P_2,
1604 EVEX_W_0F3813_P_1,
1605 EVEX_W_0F3813_P_2,
1606 EVEX_W_0F3814_P_1,
1607 EVEX_W_0F3815_P_1,
1608 EVEX_W_0F3819,
1609 EVEX_W_0F381A,
1610 EVEX_W_0F381B,
1611 EVEX_W_0F381E,
1612 EVEX_W_0F381F,
1613 EVEX_W_0F3820_P_1,
1614 EVEX_W_0F3821_P_1,
1615 EVEX_W_0F3822_P_1,
1616 EVEX_W_0F3823_P_1,
1617 EVEX_W_0F3824_P_1,
1618 EVEX_W_0F3825_P_1,
1619 EVEX_W_0F3825_P_2,
1620 EVEX_W_0F3828_P_2,
1621 EVEX_W_0F3829_P_2,
1622 EVEX_W_0F382A_P_1,
1623 EVEX_W_0F382A_P_2,
1624 EVEX_W_0F382B,
1625 EVEX_W_0F3830_P_1,
1626 EVEX_W_0F3831_P_1,
1627 EVEX_W_0F3832_P_1,
1628 EVEX_W_0F3833_P_1,
1629 EVEX_W_0F3834_P_1,
1630 EVEX_W_0F3835_P_1,
1631 EVEX_W_0F3835_P_2,
1632 EVEX_W_0F3837,
1633 EVEX_W_0F383A_P_1,
1634 EVEX_W_0F3852_P_1,
1635 EVEX_W_0F3859,
1636 EVEX_W_0F385A,
1637 EVEX_W_0F385B,
1638 EVEX_W_0F3870,
1639 EVEX_W_0F3872_P_1,
1640 EVEX_W_0F3872_P_2,
1641 EVEX_W_0F3872_P_3,
1642 EVEX_W_0F387A,
1643 EVEX_W_0F387B,
1644 EVEX_W_0F3883,
1645 EVEX_W_0F3891,
1646 EVEX_W_0F3893,
1647 EVEX_W_0F38A1,
1648 EVEX_W_0F38A3,
1649 EVEX_W_0F38C7_R_1_M_0,
1650 EVEX_W_0F38C7_R_2_M_0,
1651 EVEX_W_0F38C7_R_5_M_0,
1652 EVEX_W_0F38C7_R_6_M_0,
1653
1654 EVEX_W_0F3A00,
1655 EVEX_W_0F3A01,
1656 EVEX_W_0F3A05,
1657 EVEX_W_0F3A08,
1658 EVEX_W_0F3A09,
1659 EVEX_W_0F3A0A,
1660 EVEX_W_0F3A0B,
1661 EVEX_W_0F3A18,
1662 EVEX_W_0F3A19,
1663 EVEX_W_0F3A1A,
1664 EVEX_W_0F3A1B,
1665 EVEX_W_0F3A21,
1666 EVEX_W_0F3A23,
1667 EVEX_W_0F3A38,
1668 EVEX_W_0F3A39,
1669 EVEX_W_0F3A3A,
1670 EVEX_W_0F3A3B,
1671 EVEX_W_0F3A42,
1672 EVEX_W_0F3A43,
1673 EVEX_W_0F3A70,
1674 EVEX_W_0F3A72,
1675 };
1676
1677 typedef void (*op_rtn) (int bytemode, int sizeflag);
1678
1679 struct dis386 {
1680 const char *name;
1681 struct
1682 {
1683 op_rtn rtn;
1684 int bytemode;
1685 } op[MAX_OPERANDS];
1686 unsigned int prefix_requirement;
1687 };
1688
1689 /* Upper case letters in the instruction names here are macros.
1690 'A' => print 'b' if no register operands or suffix_always is true
1691 'B' => print 'b' if suffix_always is true
1692 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1693 size prefix
1694 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1695 suffix_always is true
1696 'E' => print 'e' if 32-bit form of jcxz
1697 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1698 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1699 'H' => print ",pt" or ",pn" branch hint
1700 'I' unused.
1701 'J' unused.
1702 'K' => print 'd' or 'q' if rex prefix is present.
1703 'L' unused.
1704 'M' => print 'r' if intel_mnemonic is false.
1705 'N' => print 'n' if instruction has no wait "prefix"
1706 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1707 'P' => behave as 'T' except with register operand outside of suffix_always
1708 mode
1709 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1710 is true
1711 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1712 'S' => print 'w', 'l' or 'q' if suffix_always is true
1713 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1714 prefix or if suffix_always is true.
1715 'U' unused.
1716 'V' unused.
1717 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1718 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1719 'Y' unused.
1720 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1721 '!' => change condition from true to false or from false to true.
1722 '%' => add 1 upper case letter to the macro.
1723 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1724 prefix or suffix_always is true (lcall/ljmp).
1725 '@' => in 64bit mode for Intel64 ISA or if instruction
1726 has no operand sizing prefix, print 'q' if suffix_always is true or
1727 nothing otherwise; behave as 'P' in all other cases
1728
1729 2 upper case letter macros:
1730 "XY" => print 'x' or 'y' if suffix_always is true or no register
1731 operands and no broadcast.
1732 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1733 register operands and no broadcast.
1734 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1735 "XV" => print "{vex3}" pseudo prefix
1736 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1737 being false, or no operand at all in 64bit mode, or if suffix_always
1738 is true.
1739 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1740 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1741 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1742 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1743 "BW" => print 'b' or 'w' depending on the VEX.W bit
1744 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1745 an operand size prefix, or suffix_always is true. print
1746 'q' if rex prefix is present.
1747
1748 Many of the above letters print nothing in Intel mode. See "putop"
1749 for the details.
1750
1751 Braces '{' and '}', and vertical bars '|', indicate alternative
1752 mnemonic strings for AT&T and Intel. */
1753
1754 static const struct dis386 dis386[] = {
1755 /* 00 */
1756 { "addB", { Ebh1, Gb }, 0 },
1757 { "addS", { Evh1, Gv }, 0 },
1758 { "addB", { Gb, EbS }, 0 },
1759 { "addS", { Gv, EvS }, 0 },
1760 { "addB", { AL, Ib }, 0 },
1761 { "addS", { eAX, Iv }, 0 },
1762 { X86_64_TABLE (X86_64_06) },
1763 { X86_64_TABLE (X86_64_07) },
1764 /* 08 */
1765 { "orB", { Ebh1, Gb }, 0 },
1766 { "orS", { Evh1, Gv }, 0 },
1767 { "orB", { Gb, EbS }, 0 },
1768 { "orS", { Gv, EvS }, 0 },
1769 { "orB", { AL, Ib }, 0 },
1770 { "orS", { eAX, Iv }, 0 },
1771 { X86_64_TABLE (X86_64_0E) },
1772 { Bad_Opcode }, /* 0x0f extended opcode escape */
1773 /* 10 */
1774 { "adcB", { Ebh1, Gb }, 0 },
1775 { "adcS", { Evh1, Gv }, 0 },
1776 { "adcB", { Gb, EbS }, 0 },
1777 { "adcS", { Gv, EvS }, 0 },
1778 { "adcB", { AL, Ib }, 0 },
1779 { "adcS", { eAX, Iv }, 0 },
1780 { X86_64_TABLE (X86_64_16) },
1781 { X86_64_TABLE (X86_64_17) },
1782 /* 18 */
1783 { "sbbB", { Ebh1, Gb }, 0 },
1784 { "sbbS", { Evh1, Gv }, 0 },
1785 { "sbbB", { Gb, EbS }, 0 },
1786 { "sbbS", { Gv, EvS }, 0 },
1787 { "sbbB", { AL, Ib }, 0 },
1788 { "sbbS", { eAX, Iv }, 0 },
1789 { X86_64_TABLE (X86_64_1E) },
1790 { X86_64_TABLE (X86_64_1F) },
1791 /* 20 */
1792 { "andB", { Ebh1, Gb }, 0 },
1793 { "andS", { Evh1, Gv }, 0 },
1794 { "andB", { Gb, EbS }, 0 },
1795 { "andS", { Gv, EvS }, 0 },
1796 { "andB", { AL, Ib }, 0 },
1797 { "andS", { eAX, Iv }, 0 },
1798 { Bad_Opcode }, /* SEG ES prefix */
1799 { X86_64_TABLE (X86_64_27) },
1800 /* 28 */
1801 { "subB", { Ebh1, Gb }, 0 },
1802 { "subS", { Evh1, Gv }, 0 },
1803 { "subB", { Gb, EbS }, 0 },
1804 { "subS", { Gv, EvS }, 0 },
1805 { "subB", { AL, Ib }, 0 },
1806 { "subS", { eAX, Iv }, 0 },
1807 { Bad_Opcode }, /* SEG CS prefix */
1808 { X86_64_TABLE (X86_64_2F) },
1809 /* 30 */
1810 { "xorB", { Ebh1, Gb }, 0 },
1811 { "xorS", { Evh1, Gv }, 0 },
1812 { "xorB", { Gb, EbS }, 0 },
1813 { "xorS", { Gv, EvS }, 0 },
1814 { "xorB", { AL, Ib }, 0 },
1815 { "xorS", { eAX, Iv }, 0 },
1816 { Bad_Opcode }, /* SEG SS prefix */
1817 { X86_64_TABLE (X86_64_37) },
1818 /* 38 */
1819 { "cmpB", { Eb, Gb }, 0 },
1820 { "cmpS", { Ev, Gv }, 0 },
1821 { "cmpB", { Gb, EbS }, 0 },
1822 { "cmpS", { Gv, EvS }, 0 },
1823 { "cmpB", { AL, Ib }, 0 },
1824 { "cmpS", { eAX, Iv }, 0 },
1825 { Bad_Opcode }, /* SEG DS prefix */
1826 { X86_64_TABLE (X86_64_3F) },
1827 /* 40 */
1828 { "inc{S|}", { RMeAX }, 0 },
1829 { "inc{S|}", { RMeCX }, 0 },
1830 { "inc{S|}", { RMeDX }, 0 },
1831 { "inc{S|}", { RMeBX }, 0 },
1832 { "inc{S|}", { RMeSP }, 0 },
1833 { "inc{S|}", { RMeBP }, 0 },
1834 { "inc{S|}", { RMeSI }, 0 },
1835 { "inc{S|}", { RMeDI }, 0 },
1836 /* 48 */
1837 { "dec{S|}", { RMeAX }, 0 },
1838 { "dec{S|}", { RMeCX }, 0 },
1839 { "dec{S|}", { RMeDX }, 0 },
1840 { "dec{S|}", { RMeBX }, 0 },
1841 { "dec{S|}", { RMeSP }, 0 },
1842 { "dec{S|}", { RMeBP }, 0 },
1843 { "dec{S|}", { RMeSI }, 0 },
1844 { "dec{S|}", { RMeDI }, 0 },
1845 /* 50 */
1846 { "push{!P|}", { RMrAX }, 0 },
1847 { "push{!P|}", { RMrCX }, 0 },
1848 { "push{!P|}", { RMrDX }, 0 },
1849 { "push{!P|}", { RMrBX }, 0 },
1850 { "push{!P|}", { RMrSP }, 0 },
1851 { "push{!P|}", { RMrBP }, 0 },
1852 { "push{!P|}", { RMrSI }, 0 },
1853 { "push{!P|}", { RMrDI }, 0 },
1854 /* 58 */
1855 { "pop{!P|}", { RMrAX }, 0 },
1856 { "pop{!P|}", { RMrCX }, 0 },
1857 { "pop{!P|}", { RMrDX }, 0 },
1858 { "pop{!P|}", { RMrBX }, 0 },
1859 { "pop{!P|}", { RMrSP }, 0 },
1860 { "pop{!P|}", { RMrBP }, 0 },
1861 { "pop{!P|}", { RMrSI }, 0 },
1862 { "pop{!P|}", { RMrDI }, 0 },
1863 /* 60 */
1864 { X86_64_TABLE (X86_64_60) },
1865 { X86_64_TABLE (X86_64_61) },
1866 { X86_64_TABLE (X86_64_62) },
1867 { X86_64_TABLE (X86_64_63) },
1868 { Bad_Opcode }, /* seg fs */
1869 { Bad_Opcode }, /* seg gs */
1870 { Bad_Opcode }, /* op size prefix */
1871 { Bad_Opcode }, /* adr size prefix */
1872 /* 68 */
1873 { "pushP", { sIv }, 0 },
1874 { "imulS", { Gv, Ev, Iv }, 0 },
1875 { "pushP", { sIbT }, 0 },
1876 { "imulS", { Gv, Ev, sIb }, 0 },
1877 { "ins{b|}", { Ybr, indirDX }, 0 },
1878 { X86_64_TABLE (X86_64_6D) },
1879 { "outs{b|}", { indirDXr, Xb }, 0 },
1880 { X86_64_TABLE (X86_64_6F) },
1881 /* 70 */
1882 { "joH", { Jb, BND, cond_jump_flag }, 0 },
1883 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
1884 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
1885 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
1886 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
1887 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
1888 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
1889 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
1890 /* 78 */
1891 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
1892 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
1893 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
1894 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
1895 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
1896 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
1897 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
1898 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
1899 /* 80 */
1900 { REG_TABLE (REG_80) },
1901 { REG_TABLE (REG_81) },
1902 { X86_64_TABLE (X86_64_82) },
1903 { REG_TABLE (REG_83) },
1904 { "testB", { Eb, Gb }, 0 },
1905 { "testS", { Ev, Gv }, 0 },
1906 { "xchgB", { Ebh2, Gb }, 0 },
1907 { "xchgS", { Evh2, Gv }, 0 },
1908 /* 88 */
1909 { "movB", { Ebh3, Gb }, 0 },
1910 { "movS", { Evh3, Gv }, 0 },
1911 { "movB", { Gb, EbS }, 0 },
1912 { "movS", { Gv, EvS }, 0 },
1913 { "movD", { Sv, Sw }, 0 },
1914 { MOD_TABLE (MOD_8D) },
1915 { "movD", { Sw, Sv }, 0 },
1916 { REG_TABLE (REG_8F) },
1917 /* 90 */
1918 { PREFIX_TABLE (PREFIX_90) },
1919 { "xchgS", { RMeCX, eAX }, 0 },
1920 { "xchgS", { RMeDX, eAX }, 0 },
1921 { "xchgS", { RMeBX, eAX }, 0 },
1922 { "xchgS", { RMeSP, eAX }, 0 },
1923 { "xchgS", { RMeBP, eAX }, 0 },
1924 { "xchgS", { RMeSI, eAX }, 0 },
1925 { "xchgS", { RMeDI, eAX }, 0 },
1926 /* 98 */
1927 { "cW{t|}R", { XX }, 0 },
1928 { "cR{t|}O", { XX }, 0 },
1929 { X86_64_TABLE (X86_64_9A) },
1930 { Bad_Opcode }, /* fwait */
1931 { "pushfP", { XX }, 0 },
1932 { "popfP", { XX }, 0 },
1933 { "sahf", { XX }, 0 },
1934 { "lahf", { XX }, 0 },
1935 /* a0 */
1936 { "mov%LB", { AL, Ob }, 0 },
1937 { "mov%LS", { eAX, Ov }, 0 },
1938 { "mov%LB", { Ob, AL }, 0 },
1939 { "mov%LS", { Ov, eAX }, 0 },
1940 { "movs{b|}", { Ybr, Xb }, 0 },
1941 { "movs{R|}", { Yvr, Xv }, 0 },
1942 { "cmps{b|}", { Xb, Yb }, 0 },
1943 { "cmps{R|}", { Xv, Yv }, 0 },
1944 /* a8 */
1945 { "testB", { AL, Ib }, 0 },
1946 { "testS", { eAX, Iv }, 0 },
1947 { "stosB", { Ybr, AL }, 0 },
1948 { "stosS", { Yvr, eAX }, 0 },
1949 { "lodsB", { ALr, Xb }, 0 },
1950 { "lodsS", { eAXr, Xv }, 0 },
1951 { "scasB", { AL, Yb }, 0 },
1952 { "scasS", { eAX, Yv }, 0 },
1953 /* b0 */
1954 { "movB", { RMAL, Ib }, 0 },
1955 { "movB", { RMCL, Ib }, 0 },
1956 { "movB", { RMDL, Ib }, 0 },
1957 { "movB", { RMBL, Ib }, 0 },
1958 { "movB", { RMAH, Ib }, 0 },
1959 { "movB", { RMCH, Ib }, 0 },
1960 { "movB", { RMDH, Ib }, 0 },
1961 { "movB", { RMBH, Ib }, 0 },
1962 /* b8 */
1963 { "mov%LV", { RMeAX, Iv64 }, 0 },
1964 { "mov%LV", { RMeCX, Iv64 }, 0 },
1965 { "mov%LV", { RMeDX, Iv64 }, 0 },
1966 { "mov%LV", { RMeBX, Iv64 }, 0 },
1967 { "mov%LV", { RMeSP, Iv64 }, 0 },
1968 { "mov%LV", { RMeBP, Iv64 }, 0 },
1969 { "mov%LV", { RMeSI, Iv64 }, 0 },
1970 { "mov%LV", { RMeDI, Iv64 }, 0 },
1971 /* c0 */
1972 { REG_TABLE (REG_C0) },
1973 { REG_TABLE (REG_C1) },
1974 { X86_64_TABLE (X86_64_C2) },
1975 { X86_64_TABLE (X86_64_C3) },
1976 { X86_64_TABLE (X86_64_C4) },
1977 { X86_64_TABLE (X86_64_C5) },
1978 { REG_TABLE (REG_C6) },
1979 { REG_TABLE (REG_C7) },
1980 /* c8 */
1981 { "enterP", { Iw, Ib }, 0 },
1982 { "leaveP", { XX }, 0 },
1983 { "{l|}ret{|f}%LP", { Iw }, 0 },
1984 { "{l|}ret{|f}%LP", { XX }, 0 },
1985 { "int3", { XX }, 0 },
1986 { "int", { Ib }, 0 },
1987 { X86_64_TABLE (X86_64_CE) },
1988 { "iret%LP", { XX }, 0 },
1989 /* d0 */
1990 { REG_TABLE (REG_D0) },
1991 { REG_TABLE (REG_D1) },
1992 { REG_TABLE (REG_D2) },
1993 { REG_TABLE (REG_D3) },
1994 { X86_64_TABLE (X86_64_D4) },
1995 { X86_64_TABLE (X86_64_D5) },
1996 { Bad_Opcode },
1997 { "xlat", { DSBX }, 0 },
1998 /* d8 */
1999 { FLOAT },
2000 { FLOAT },
2001 { FLOAT },
2002 { FLOAT },
2003 { FLOAT },
2004 { FLOAT },
2005 { FLOAT },
2006 { FLOAT },
2007 /* e0 */
2008 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2009 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2010 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2011 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2012 { "inB", { AL, Ib }, 0 },
2013 { "inG", { zAX, Ib }, 0 },
2014 { "outB", { Ib, AL }, 0 },
2015 { "outG", { Ib, zAX }, 0 },
2016 /* e8 */
2017 { X86_64_TABLE (X86_64_E8) },
2018 { X86_64_TABLE (X86_64_E9) },
2019 { X86_64_TABLE (X86_64_EA) },
2020 { "jmp", { Jb, BND }, 0 },
2021 { "inB", { AL, indirDX }, 0 },
2022 { "inG", { zAX, indirDX }, 0 },
2023 { "outB", { indirDX, AL }, 0 },
2024 { "outG", { indirDX, zAX }, 0 },
2025 /* f0 */
2026 { Bad_Opcode }, /* lock prefix */
2027 { "icebp", { XX }, 0 },
2028 { Bad_Opcode }, /* repne */
2029 { Bad_Opcode }, /* repz */
2030 { "hlt", { XX }, 0 },
2031 { "cmc", { XX }, 0 },
2032 { REG_TABLE (REG_F6) },
2033 { REG_TABLE (REG_F7) },
2034 /* f8 */
2035 { "clc", { XX }, 0 },
2036 { "stc", { XX }, 0 },
2037 { "cli", { XX }, 0 },
2038 { "sti", { XX }, 0 },
2039 { "cld", { XX }, 0 },
2040 { "std", { XX }, 0 },
2041 { REG_TABLE (REG_FE) },
2042 { REG_TABLE (REG_FF) },
2043 };
2044
2045 static const struct dis386 dis386_twobyte[] = {
2046 /* 00 */
2047 { REG_TABLE (REG_0F00 ) },
2048 { REG_TABLE (REG_0F01 ) },
2049 { "larS", { Gv, Ew }, 0 },
2050 { "lslS", { Gv, Ew }, 0 },
2051 { Bad_Opcode },
2052 { "syscall", { XX }, 0 },
2053 { "clts", { XX }, 0 },
2054 { "sysret%LQ", { XX }, 0 },
2055 /* 08 */
2056 { "invd", { XX }, 0 },
2057 { PREFIX_TABLE (PREFIX_0F09) },
2058 { Bad_Opcode },
2059 { "ud2", { XX }, 0 },
2060 { Bad_Opcode },
2061 { REG_TABLE (REG_0F0D) },
2062 { "femms", { XX }, 0 },
2063 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2064 /* 10 */
2065 { PREFIX_TABLE (PREFIX_0F10) },
2066 { PREFIX_TABLE (PREFIX_0F11) },
2067 { PREFIX_TABLE (PREFIX_0F12) },
2068 { MOD_TABLE (MOD_0F13) },
2069 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2070 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2071 { PREFIX_TABLE (PREFIX_0F16) },
2072 { MOD_TABLE (MOD_0F17) },
2073 /* 18 */
2074 { REG_TABLE (REG_0F18) },
2075 { "nopQ", { Ev }, 0 },
2076 { PREFIX_TABLE (PREFIX_0F1A) },
2077 { PREFIX_TABLE (PREFIX_0F1B) },
2078 { PREFIX_TABLE (PREFIX_0F1C) },
2079 { "nopQ", { Ev }, 0 },
2080 { PREFIX_TABLE (PREFIX_0F1E) },
2081 { "nopQ", { Ev }, 0 },
2082 /* 20 */
2083 { "movZ", { Em, Cm }, 0 },
2084 { "movZ", { Em, Dm }, 0 },
2085 { "movZ", { Cm, Em }, 0 },
2086 { "movZ", { Dm, Em }, 0 },
2087 { X86_64_TABLE (X86_64_0F24) },
2088 { Bad_Opcode },
2089 { X86_64_TABLE (X86_64_0F26) },
2090 { Bad_Opcode },
2091 /* 28 */
2092 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2093 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2094 { PREFIX_TABLE (PREFIX_0F2A) },
2095 { PREFIX_TABLE (PREFIX_0F2B) },
2096 { PREFIX_TABLE (PREFIX_0F2C) },
2097 { PREFIX_TABLE (PREFIX_0F2D) },
2098 { PREFIX_TABLE (PREFIX_0F2E) },
2099 { PREFIX_TABLE (PREFIX_0F2F) },
2100 /* 30 */
2101 { "wrmsr", { XX }, 0 },
2102 { "rdtsc", { XX }, 0 },
2103 { "rdmsr", { XX }, 0 },
2104 { "rdpmc", { XX }, 0 },
2105 { "sysenter", { SEP }, 0 },
2106 { "sysexit%LQ", { SEP }, 0 },
2107 { Bad_Opcode },
2108 { "getsec", { XX }, 0 },
2109 /* 38 */
2110 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2111 { Bad_Opcode },
2112 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2113 { Bad_Opcode },
2114 { Bad_Opcode },
2115 { Bad_Opcode },
2116 { Bad_Opcode },
2117 { Bad_Opcode },
2118 /* 40 */
2119 { "cmovoS", { Gv, Ev }, 0 },
2120 { "cmovnoS", { Gv, Ev }, 0 },
2121 { "cmovbS", { Gv, Ev }, 0 },
2122 { "cmovaeS", { Gv, Ev }, 0 },
2123 { "cmoveS", { Gv, Ev }, 0 },
2124 { "cmovneS", { Gv, Ev }, 0 },
2125 { "cmovbeS", { Gv, Ev }, 0 },
2126 { "cmovaS", { Gv, Ev }, 0 },
2127 /* 48 */
2128 { "cmovsS", { Gv, Ev }, 0 },
2129 { "cmovnsS", { Gv, Ev }, 0 },
2130 { "cmovpS", { Gv, Ev }, 0 },
2131 { "cmovnpS", { Gv, Ev }, 0 },
2132 { "cmovlS", { Gv, Ev }, 0 },
2133 { "cmovgeS", { Gv, Ev }, 0 },
2134 { "cmovleS", { Gv, Ev }, 0 },
2135 { "cmovgS", { Gv, Ev }, 0 },
2136 /* 50 */
2137 { MOD_TABLE (MOD_0F50) },
2138 { PREFIX_TABLE (PREFIX_0F51) },
2139 { PREFIX_TABLE (PREFIX_0F52) },
2140 { PREFIX_TABLE (PREFIX_0F53) },
2141 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2142 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2143 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2144 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2145 /* 58 */
2146 { PREFIX_TABLE (PREFIX_0F58) },
2147 { PREFIX_TABLE (PREFIX_0F59) },
2148 { PREFIX_TABLE (PREFIX_0F5A) },
2149 { PREFIX_TABLE (PREFIX_0F5B) },
2150 { PREFIX_TABLE (PREFIX_0F5C) },
2151 { PREFIX_TABLE (PREFIX_0F5D) },
2152 { PREFIX_TABLE (PREFIX_0F5E) },
2153 { PREFIX_TABLE (PREFIX_0F5F) },
2154 /* 60 */
2155 { PREFIX_TABLE (PREFIX_0F60) },
2156 { PREFIX_TABLE (PREFIX_0F61) },
2157 { PREFIX_TABLE (PREFIX_0F62) },
2158 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2159 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2160 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2161 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2162 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2163 /* 68 */
2164 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2165 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2166 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2167 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2168 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2169 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2170 { "movK", { MX, Edq }, PREFIX_OPCODE },
2171 { PREFIX_TABLE (PREFIX_0F6F) },
2172 /* 70 */
2173 { PREFIX_TABLE (PREFIX_0F70) },
2174 { MOD_TABLE (MOD_0F71) },
2175 { MOD_TABLE (MOD_0F72) },
2176 { MOD_TABLE (MOD_0F73) },
2177 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2178 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2179 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2180 { "emms", { XX }, PREFIX_OPCODE },
2181 /* 78 */
2182 { PREFIX_TABLE (PREFIX_0F78) },
2183 { PREFIX_TABLE (PREFIX_0F79) },
2184 { Bad_Opcode },
2185 { Bad_Opcode },
2186 { PREFIX_TABLE (PREFIX_0F7C) },
2187 { PREFIX_TABLE (PREFIX_0F7D) },
2188 { PREFIX_TABLE (PREFIX_0F7E) },
2189 { PREFIX_TABLE (PREFIX_0F7F) },
2190 /* 80 */
2191 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2192 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2193 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2194 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2195 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2196 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2197 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2198 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2199 /* 88 */
2200 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2201 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2202 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2203 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2204 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2205 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2206 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2207 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2208 /* 90 */
2209 { "seto", { Eb }, 0 },
2210 { "setno", { Eb }, 0 },
2211 { "setb", { Eb }, 0 },
2212 { "setae", { Eb }, 0 },
2213 { "sete", { Eb }, 0 },
2214 { "setne", { Eb }, 0 },
2215 { "setbe", { Eb }, 0 },
2216 { "seta", { Eb }, 0 },
2217 /* 98 */
2218 { "sets", { Eb }, 0 },
2219 { "setns", { Eb }, 0 },
2220 { "setp", { Eb }, 0 },
2221 { "setnp", { Eb }, 0 },
2222 { "setl", { Eb }, 0 },
2223 { "setge", { Eb }, 0 },
2224 { "setle", { Eb }, 0 },
2225 { "setg", { Eb }, 0 },
2226 /* a0 */
2227 { "pushP", { fs }, 0 },
2228 { "popP", { fs }, 0 },
2229 { "cpuid", { XX }, 0 },
2230 { "btS", { Ev, Gv }, 0 },
2231 { "shldS", { Ev, Gv, Ib }, 0 },
2232 { "shldS", { Ev, Gv, CL }, 0 },
2233 { REG_TABLE (REG_0FA6) },
2234 { REG_TABLE (REG_0FA7) },
2235 /* a8 */
2236 { "pushP", { gs }, 0 },
2237 { "popP", { gs }, 0 },
2238 { "rsm", { XX }, 0 },
2239 { "btsS", { Evh1, Gv }, 0 },
2240 { "shrdS", { Ev, Gv, Ib }, 0 },
2241 { "shrdS", { Ev, Gv, CL }, 0 },
2242 { REG_TABLE (REG_0FAE) },
2243 { "imulS", { Gv, Ev }, 0 },
2244 /* b0 */
2245 { "cmpxchgB", { Ebh1, Gb }, 0 },
2246 { "cmpxchgS", { Evh1, Gv }, 0 },
2247 { MOD_TABLE (MOD_0FB2) },
2248 { "btrS", { Evh1, Gv }, 0 },
2249 { MOD_TABLE (MOD_0FB4) },
2250 { MOD_TABLE (MOD_0FB5) },
2251 { "movz{bR|x}", { Gv, Eb }, 0 },
2252 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2253 /* b8 */
2254 { PREFIX_TABLE (PREFIX_0FB8) },
2255 { "ud1S", { Gv, Ev }, 0 },
2256 { REG_TABLE (REG_0FBA) },
2257 { "btcS", { Evh1, Gv }, 0 },
2258 { PREFIX_TABLE (PREFIX_0FBC) },
2259 { PREFIX_TABLE (PREFIX_0FBD) },
2260 { "movs{bR|x}", { Gv, Eb }, 0 },
2261 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2262 /* c0 */
2263 { "xaddB", { Ebh1, Gb }, 0 },
2264 { "xaddS", { Evh1, Gv }, 0 },
2265 { PREFIX_TABLE (PREFIX_0FC2) },
2266 { MOD_TABLE (MOD_0FC3) },
2267 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2268 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2269 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2270 { REG_TABLE (REG_0FC7) },
2271 /* c8 */
2272 { "bswap", { RMeAX }, 0 },
2273 { "bswap", { RMeCX }, 0 },
2274 { "bswap", { RMeDX }, 0 },
2275 { "bswap", { RMeBX }, 0 },
2276 { "bswap", { RMeSP }, 0 },
2277 { "bswap", { RMeBP }, 0 },
2278 { "bswap", { RMeSI }, 0 },
2279 { "bswap", { RMeDI }, 0 },
2280 /* d0 */
2281 { PREFIX_TABLE (PREFIX_0FD0) },
2282 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2283 { "psrld", { MX, EM }, PREFIX_OPCODE },
2284 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2285 { "paddq", { MX, EM }, PREFIX_OPCODE },
2286 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2287 { PREFIX_TABLE (PREFIX_0FD6) },
2288 { MOD_TABLE (MOD_0FD7) },
2289 /* d8 */
2290 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2291 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2292 { "pminub", { MX, EM }, PREFIX_OPCODE },
2293 { "pand", { MX, EM }, PREFIX_OPCODE },
2294 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2295 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2296 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2297 { "pandn", { MX, EM }, PREFIX_OPCODE },
2298 /* e0 */
2299 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2300 { "psraw", { MX, EM }, PREFIX_OPCODE },
2301 { "psrad", { MX, EM }, PREFIX_OPCODE },
2302 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2303 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2304 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2305 { PREFIX_TABLE (PREFIX_0FE6) },
2306 { PREFIX_TABLE (PREFIX_0FE7) },
2307 /* e8 */
2308 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2309 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2310 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2311 { "por", { MX, EM }, PREFIX_OPCODE },
2312 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2313 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2314 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2315 { "pxor", { MX, EM }, PREFIX_OPCODE },
2316 /* f0 */
2317 { PREFIX_TABLE (PREFIX_0FF0) },
2318 { "psllw", { MX, EM }, PREFIX_OPCODE },
2319 { "pslld", { MX, EM }, PREFIX_OPCODE },
2320 { "psllq", { MX, EM }, PREFIX_OPCODE },
2321 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2322 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2323 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2324 { PREFIX_TABLE (PREFIX_0FF7) },
2325 /* f8 */
2326 { "psubb", { MX, EM }, PREFIX_OPCODE },
2327 { "psubw", { MX, EM }, PREFIX_OPCODE },
2328 { "psubd", { MX, EM }, PREFIX_OPCODE },
2329 { "psubq", { MX, EM }, PREFIX_OPCODE },
2330 { "paddb", { MX, EM }, PREFIX_OPCODE },
2331 { "paddw", { MX, EM }, PREFIX_OPCODE },
2332 { "paddd", { MX, EM }, PREFIX_OPCODE },
2333 { "ud0S", { Gv, Ev }, 0 },
2334 };
2335
2336 static const unsigned char onebyte_has_modrm[256] = {
2337 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2338 /* ------------------------------- */
2339 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2340 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2341 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2342 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2343 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2344 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2345 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2346 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2347 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2348 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2349 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2350 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2351 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2352 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2353 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2354 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2355 /* ------------------------------- */
2356 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2357 };
2358
2359 static const unsigned char twobyte_has_modrm[256] = {
2360 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2361 /* ------------------------------- */
2362 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2363 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2364 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2365 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2366 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2367 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2368 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2369 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2370 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2371 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2372 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2373 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2374 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2375 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2376 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2377 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2378 /* ------------------------------- */
2379 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2380 };
2381
2382 static char obuf[100];
2383 static char *obufp;
2384 static char *mnemonicendp;
2385 static char scratchbuf[100];
2386 static unsigned char *start_codep;
2387 static unsigned char *insn_codep;
2388 static unsigned char *codep;
2389 static unsigned char *end_codep;
2390 static int last_lock_prefix;
2391 static int last_repz_prefix;
2392 static int last_repnz_prefix;
2393 static int last_data_prefix;
2394 static int last_addr_prefix;
2395 static int last_rex_prefix;
2396 static int last_seg_prefix;
2397 static int fwait_prefix;
2398 /* The active segment register prefix. */
2399 static int active_seg_prefix;
2400 #define MAX_CODE_LENGTH 15
2401 /* We can up to 14 prefixes since the maximum instruction length is
2402 15bytes. */
2403 static int all_prefixes[MAX_CODE_LENGTH - 1];
2404 static disassemble_info *the_info;
2405 static struct
2406 {
2407 int mod;
2408 int reg;
2409 int rm;
2410 }
2411 modrm;
2412 static unsigned char need_modrm;
2413 static struct
2414 {
2415 int scale;
2416 int index;
2417 int base;
2418 }
2419 sib;
2420 static struct
2421 {
2422 int register_specifier;
2423 int length;
2424 int prefix;
2425 int w;
2426 int evex;
2427 int r;
2428 int v;
2429 int mask_register_specifier;
2430 int zeroing;
2431 int ll;
2432 int b;
2433 }
2434 vex;
2435 static unsigned char need_vex;
2436
2437 struct op
2438 {
2439 const char *name;
2440 unsigned int len;
2441 };
2442
2443 /* If we are accessing mod/rm/reg without need_modrm set, then the
2444 values are stale. Hitting this abort likely indicates that you
2445 need to update onebyte_has_modrm or twobyte_has_modrm. */
2446 #define MODRM_CHECK if (!need_modrm) abort ()
2447
2448 static const char **names64;
2449 static const char **names32;
2450 static const char **names16;
2451 static const char **names8;
2452 static const char **names8rex;
2453 static const char **names_seg;
2454 static const char *index64;
2455 static const char *index32;
2456 static const char **index16;
2457 static const char **names_bnd;
2458
2459 static const char *intel_names64[] = {
2460 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2461 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2462 };
2463 static const char *intel_names32[] = {
2464 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2465 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2466 };
2467 static const char *intel_names16[] = {
2468 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2469 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2470 };
2471 static const char *intel_names8[] = {
2472 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2473 };
2474 static const char *intel_names8rex[] = {
2475 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2476 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2477 };
2478 static const char *intel_names_seg[] = {
2479 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2480 };
2481 static const char *intel_index64 = "riz";
2482 static const char *intel_index32 = "eiz";
2483 static const char *intel_index16[] = {
2484 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2485 };
2486
2487 static const char *att_names64[] = {
2488 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2489 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2490 };
2491 static const char *att_names32[] = {
2492 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2493 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2494 };
2495 static const char *att_names16[] = {
2496 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2497 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2498 };
2499 static const char *att_names8[] = {
2500 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2501 };
2502 static const char *att_names8rex[] = {
2503 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2504 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2505 };
2506 static const char *att_names_seg[] = {
2507 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2508 };
2509 static const char *att_index64 = "%riz";
2510 static const char *att_index32 = "%eiz";
2511 static const char *att_index16[] = {
2512 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2513 };
2514
2515 static const char **names_mm;
2516 static const char *intel_names_mm[] = {
2517 "mm0", "mm1", "mm2", "mm3",
2518 "mm4", "mm5", "mm6", "mm7"
2519 };
2520 static const char *att_names_mm[] = {
2521 "%mm0", "%mm1", "%mm2", "%mm3",
2522 "%mm4", "%mm5", "%mm6", "%mm7"
2523 };
2524
2525 static const char *intel_names_bnd[] = {
2526 "bnd0", "bnd1", "bnd2", "bnd3"
2527 };
2528
2529 static const char *att_names_bnd[] = {
2530 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2531 };
2532
2533 static const char **names_xmm;
2534 static const char *intel_names_xmm[] = {
2535 "xmm0", "xmm1", "xmm2", "xmm3",
2536 "xmm4", "xmm5", "xmm6", "xmm7",
2537 "xmm8", "xmm9", "xmm10", "xmm11",
2538 "xmm12", "xmm13", "xmm14", "xmm15",
2539 "xmm16", "xmm17", "xmm18", "xmm19",
2540 "xmm20", "xmm21", "xmm22", "xmm23",
2541 "xmm24", "xmm25", "xmm26", "xmm27",
2542 "xmm28", "xmm29", "xmm30", "xmm31"
2543 };
2544 static const char *att_names_xmm[] = {
2545 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2546 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2547 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2548 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2549 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2550 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2551 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2552 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2553 };
2554
2555 static const char **names_ymm;
2556 static const char *intel_names_ymm[] = {
2557 "ymm0", "ymm1", "ymm2", "ymm3",
2558 "ymm4", "ymm5", "ymm6", "ymm7",
2559 "ymm8", "ymm9", "ymm10", "ymm11",
2560 "ymm12", "ymm13", "ymm14", "ymm15",
2561 "ymm16", "ymm17", "ymm18", "ymm19",
2562 "ymm20", "ymm21", "ymm22", "ymm23",
2563 "ymm24", "ymm25", "ymm26", "ymm27",
2564 "ymm28", "ymm29", "ymm30", "ymm31"
2565 };
2566 static const char *att_names_ymm[] = {
2567 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2568 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2569 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2570 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2571 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2572 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2573 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2574 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2575 };
2576
2577 static const char **names_zmm;
2578 static const char *intel_names_zmm[] = {
2579 "zmm0", "zmm1", "zmm2", "zmm3",
2580 "zmm4", "zmm5", "zmm6", "zmm7",
2581 "zmm8", "zmm9", "zmm10", "zmm11",
2582 "zmm12", "zmm13", "zmm14", "zmm15",
2583 "zmm16", "zmm17", "zmm18", "zmm19",
2584 "zmm20", "zmm21", "zmm22", "zmm23",
2585 "zmm24", "zmm25", "zmm26", "zmm27",
2586 "zmm28", "zmm29", "zmm30", "zmm31"
2587 };
2588 static const char *att_names_zmm[] = {
2589 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2590 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2591 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2592 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2593 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2594 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2595 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2596 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2597 };
2598
2599 static const char **names_tmm;
2600 static const char *intel_names_tmm[] = {
2601 "tmm0", "tmm1", "tmm2", "tmm3",
2602 "tmm4", "tmm5", "tmm6", "tmm7"
2603 };
2604 static const char *att_names_tmm[] = {
2605 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2606 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2607 };
2608
2609 static const char **names_mask;
2610 static const char *intel_names_mask[] = {
2611 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
2612 };
2613 static const char *att_names_mask[] = {
2614 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2615 };
2616
2617 static const char *names_rounding[] =
2618 {
2619 "{rn-sae}",
2620 "{rd-sae}",
2621 "{ru-sae}",
2622 "{rz-sae}"
2623 };
2624
2625 static const struct dis386 reg_table[][8] = {
2626 /* REG_80 */
2627 {
2628 { "addA", { Ebh1, Ib }, 0 },
2629 { "orA", { Ebh1, Ib }, 0 },
2630 { "adcA", { Ebh1, Ib }, 0 },
2631 { "sbbA", { Ebh1, Ib }, 0 },
2632 { "andA", { Ebh1, Ib }, 0 },
2633 { "subA", { Ebh1, Ib }, 0 },
2634 { "xorA", { Ebh1, Ib }, 0 },
2635 { "cmpA", { Eb, Ib }, 0 },
2636 },
2637 /* REG_81 */
2638 {
2639 { "addQ", { Evh1, Iv }, 0 },
2640 { "orQ", { Evh1, Iv }, 0 },
2641 { "adcQ", { Evh1, Iv }, 0 },
2642 { "sbbQ", { Evh1, Iv }, 0 },
2643 { "andQ", { Evh1, Iv }, 0 },
2644 { "subQ", { Evh1, Iv }, 0 },
2645 { "xorQ", { Evh1, Iv }, 0 },
2646 { "cmpQ", { Ev, Iv }, 0 },
2647 },
2648 /* REG_83 */
2649 {
2650 { "addQ", { Evh1, sIb }, 0 },
2651 { "orQ", { Evh1, sIb }, 0 },
2652 { "adcQ", { Evh1, sIb }, 0 },
2653 { "sbbQ", { Evh1, sIb }, 0 },
2654 { "andQ", { Evh1, sIb }, 0 },
2655 { "subQ", { Evh1, sIb }, 0 },
2656 { "xorQ", { Evh1, sIb }, 0 },
2657 { "cmpQ", { Ev, sIb }, 0 },
2658 },
2659 /* REG_8F */
2660 {
2661 { "pop{P|}", { stackEv }, 0 },
2662 { XOP_8F_TABLE (XOP_09) },
2663 { Bad_Opcode },
2664 { Bad_Opcode },
2665 { Bad_Opcode },
2666 { XOP_8F_TABLE (XOP_09) },
2667 },
2668 /* REG_C0 */
2669 {
2670 { "rolA", { Eb, Ib }, 0 },
2671 { "rorA", { Eb, Ib }, 0 },
2672 { "rclA", { Eb, Ib }, 0 },
2673 { "rcrA", { Eb, Ib }, 0 },
2674 { "shlA", { Eb, Ib }, 0 },
2675 { "shrA", { Eb, Ib }, 0 },
2676 { "shlA", { Eb, Ib }, 0 },
2677 { "sarA", { Eb, Ib }, 0 },
2678 },
2679 /* REG_C1 */
2680 {
2681 { "rolQ", { Ev, Ib }, 0 },
2682 { "rorQ", { Ev, Ib }, 0 },
2683 { "rclQ", { Ev, Ib }, 0 },
2684 { "rcrQ", { Ev, Ib }, 0 },
2685 { "shlQ", { Ev, Ib }, 0 },
2686 { "shrQ", { Ev, Ib }, 0 },
2687 { "shlQ", { Ev, Ib }, 0 },
2688 { "sarQ", { Ev, Ib }, 0 },
2689 },
2690 /* REG_C6 */
2691 {
2692 { "movA", { Ebh3, Ib }, 0 },
2693 { Bad_Opcode },
2694 { Bad_Opcode },
2695 { Bad_Opcode },
2696 { Bad_Opcode },
2697 { Bad_Opcode },
2698 { Bad_Opcode },
2699 { MOD_TABLE (MOD_C6_REG_7) },
2700 },
2701 /* REG_C7 */
2702 {
2703 { "movQ", { Evh3, Iv }, 0 },
2704 { Bad_Opcode },
2705 { Bad_Opcode },
2706 { Bad_Opcode },
2707 { Bad_Opcode },
2708 { Bad_Opcode },
2709 { Bad_Opcode },
2710 { MOD_TABLE (MOD_C7_REG_7) },
2711 },
2712 /* REG_D0 */
2713 {
2714 { "rolA", { Eb, I1 }, 0 },
2715 { "rorA", { Eb, I1 }, 0 },
2716 { "rclA", { Eb, I1 }, 0 },
2717 { "rcrA", { Eb, I1 }, 0 },
2718 { "shlA", { Eb, I1 }, 0 },
2719 { "shrA", { Eb, I1 }, 0 },
2720 { "shlA", { Eb, I1 }, 0 },
2721 { "sarA", { Eb, I1 }, 0 },
2722 },
2723 /* REG_D1 */
2724 {
2725 { "rolQ", { Ev, I1 }, 0 },
2726 { "rorQ", { Ev, I1 }, 0 },
2727 { "rclQ", { Ev, I1 }, 0 },
2728 { "rcrQ", { Ev, I1 }, 0 },
2729 { "shlQ", { Ev, I1 }, 0 },
2730 { "shrQ", { Ev, I1 }, 0 },
2731 { "shlQ", { Ev, I1 }, 0 },
2732 { "sarQ", { Ev, I1 }, 0 },
2733 },
2734 /* REG_D2 */
2735 {
2736 { "rolA", { Eb, CL }, 0 },
2737 { "rorA", { Eb, CL }, 0 },
2738 { "rclA", { Eb, CL }, 0 },
2739 { "rcrA", { Eb, CL }, 0 },
2740 { "shlA", { Eb, CL }, 0 },
2741 { "shrA", { Eb, CL }, 0 },
2742 { "shlA", { Eb, CL }, 0 },
2743 { "sarA", { Eb, CL }, 0 },
2744 },
2745 /* REG_D3 */
2746 {
2747 { "rolQ", { Ev, CL }, 0 },
2748 { "rorQ", { Ev, CL }, 0 },
2749 { "rclQ", { Ev, CL }, 0 },
2750 { "rcrQ", { Ev, CL }, 0 },
2751 { "shlQ", { Ev, CL }, 0 },
2752 { "shrQ", { Ev, CL }, 0 },
2753 { "shlQ", { Ev, CL }, 0 },
2754 { "sarQ", { Ev, CL }, 0 },
2755 },
2756 /* REG_F6 */
2757 {
2758 { "testA", { Eb, Ib }, 0 },
2759 { "testA", { Eb, Ib }, 0 },
2760 { "notA", { Ebh1 }, 0 },
2761 { "negA", { Ebh1 }, 0 },
2762 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2763 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2764 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2765 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2766 },
2767 /* REG_F7 */
2768 {
2769 { "testQ", { Ev, Iv }, 0 },
2770 { "testQ", { Ev, Iv }, 0 },
2771 { "notQ", { Evh1 }, 0 },
2772 { "negQ", { Evh1 }, 0 },
2773 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2774 { "imulQ", { Ev }, 0 },
2775 { "divQ", { Ev }, 0 },
2776 { "idivQ", { Ev }, 0 },
2777 },
2778 /* REG_FE */
2779 {
2780 { "incA", { Ebh1 }, 0 },
2781 { "decA", { Ebh1 }, 0 },
2782 },
2783 /* REG_FF */
2784 {
2785 { "incQ", { Evh1 }, 0 },
2786 { "decQ", { Evh1 }, 0 },
2787 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2788 { MOD_TABLE (MOD_FF_REG_3) },
2789 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2790 { MOD_TABLE (MOD_FF_REG_5) },
2791 { "push{P|}", { stackEv }, 0 },
2792 { Bad_Opcode },
2793 },
2794 /* REG_0F00 */
2795 {
2796 { "sldtD", { Sv }, 0 },
2797 { "strD", { Sv }, 0 },
2798 { "lldt", { Ew }, 0 },
2799 { "ltr", { Ew }, 0 },
2800 { "verr", { Ew }, 0 },
2801 { "verw", { Ew }, 0 },
2802 { Bad_Opcode },
2803 { Bad_Opcode },
2804 },
2805 /* REG_0F01 */
2806 {
2807 { MOD_TABLE (MOD_0F01_REG_0) },
2808 { MOD_TABLE (MOD_0F01_REG_1) },
2809 { MOD_TABLE (MOD_0F01_REG_2) },
2810 { MOD_TABLE (MOD_0F01_REG_3) },
2811 { "smswD", { Sv }, 0 },
2812 { MOD_TABLE (MOD_0F01_REG_5) },
2813 { "lmsw", { Ew }, 0 },
2814 { MOD_TABLE (MOD_0F01_REG_7) },
2815 },
2816 /* REG_0F0D */
2817 {
2818 { "prefetch", { Mb }, 0 },
2819 { "prefetchw", { Mb }, 0 },
2820 { "prefetchwt1", { Mb }, 0 },
2821 { "prefetch", { Mb }, 0 },
2822 { "prefetch", { Mb }, 0 },
2823 { "prefetch", { Mb }, 0 },
2824 { "prefetch", { Mb }, 0 },
2825 { "prefetch", { Mb }, 0 },
2826 },
2827 /* REG_0F18 */
2828 {
2829 { MOD_TABLE (MOD_0F18_REG_0) },
2830 { MOD_TABLE (MOD_0F18_REG_1) },
2831 { MOD_TABLE (MOD_0F18_REG_2) },
2832 { MOD_TABLE (MOD_0F18_REG_3) },
2833 { "nopQ", { Ev }, 0 },
2834 { "nopQ", { Ev }, 0 },
2835 { "nopQ", { Ev }, 0 },
2836 { "nopQ", { Ev }, 0 },
2837 },
2838 /* REG_0F1C_P_0_MOD_0 */
2839 {
2840 { "cldemote", { Mb }, 0 },
2841 { "nopQ", { Ev }, 0 },
2842 { "nopQ", { Ev }, 0 },
2843 { "nopQ", { Ev }, 0 },
2844 { "nopQ", { Ev }, 0 },
2845 { "nopQ", { Ev }, 0 },
2846 { "nopQ", { Ev }, 0 },
2847 { "nopQ", { Ev }, 0 },
2848 },
2849 /* REG_0F1E_P_1_MOD_3 */
2850 {
2851 { "nopQ", { Ev }, PREFIX_IGNORED },
2852 { "rdsspK", { Edq }, 0 },
2853 { "nopQ", { Ev }, PREFIX_IGNORED },
2854 { "nopQ", { Ev }, PREFIX_IGNORED },
2855 { "nopQ", { Ev }, PREFIX_IGNORED },
2856 { "nopQ", { Ev }, PREFIX_IGNORED },
2857 { "nopQ", { Ev }, PREFIX_IGNORED },
2858 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2859 },
2860 /* REG_0F38D8_PREFIX_1 */
2861 {
2862 { "aesencwide128kl", { M }, 0 },
2863 { "aesdecwide128kl", { M }, 0 },
2864 { "aesencwide256kl", { M }, 0 },
2865 { "aesdecwide256kl", { M }, 0 },
2866 },
2867 /* REG_0F3A0F_PREFIX_1_MOD_3 */
2868 {
2869 { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
2870 },
2871 /* REG_0F71_MOD_0 */
2872 {
2873 { Bad_Opcode },
2874 { Bad_Opcode },
2875 { "psrlw", { MS, Ib }, PREFIX_OPCODE },
2876 { Bad_Opcode },
2877 { "psraw", { MS, Ib }, PREFIX_OPCODE },
2878 { Bad_Opcode },
2879 { "psllw", { MS, Ib }, PREFIX_OPCODE },
2880 },
2881 /* REG_0F72_MOD_0 */
2882 {
2883 { Bad_Opcode },
2884 { Bad_Opcode },
2885 { "psrld", { MS, Ib }, PREFIX_OPCODE },
2886 { Bad_Opcode },
2887 { "psrad", { MS, Ib }, PREFIX_OPCODE },
2888 { Bad_Opcode },
2889 { "pslld", { MS, Ib }, PREFIX_OPCODE },
2890 },
2891 /* REG_0F73_MOD_0 */
2892 {
2893 { Bad_Opcode },
2894 { Bad_Opcode },
2895 { "psrlq", { MS, Ib }, PREFIX_OPCODE },
2896 { "psrldq", { XS, Ib }, PREFIX_DATA },
2897 { Bad_Opcode },
2898 { Bad_Opcode },
2899 { "psllq", { MS, Ib }, PREFIX_OPCODE },
2900 { "pslldq", { XS, Ib }, PREFIX_DATA },
2901 },
2902 /* REG_0FA6 */
2903 {
2904 { "montmul", { { OP_0f07, 0 } }, 0 },
2905 { "xsha1", { { OP_0f07, 0 } }, 0 },
2906 { "xsha256", { { OP_0f07, 0 } }, 0 },
2907 },
2908 /* REG_0FA7 */
2909 {
2910 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2911 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2912 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2913 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2914 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2915 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2916 },
2917 /* REG_0FAE */
2918 {
2919 { MOD_TABLE (MOD_0FAE_REG_0) },
2920 { MOD_TABLE (MOD_0FAE_REG_1) },
2921 { MOD_TABLE (MOD_0FAE_REG_2) },
2922 { MOD_TABLE (MOD_0FAE_REG_3) },
2923 { MOD_TABLE (MOD_0FAE_REG_4) },
2924 { MOD_TABLE (MOD_0FAE_REG_5) },
2925 { MOD_TABLE (MOD_0FAE_REG_6) },
2926 { MOD_TABLE (MOD_0FAE_REG_7) },
2927 },
2928 /* REG_0FBA */
2929 {
2930 { Bad_Opcode },
2931 { Bad_Opcode },
2932 { Bad_Opcode },
2933 { Bad_Opcode },
2934 { "btQ", { Ev, Ib }, 0 },
2935 { "btsQ", { Evh1, Ib }, 0 },
2936 { "btrQ", { Evh1, Ib }, 0 },
2937 { "btcQ", { Evh1, Ib }, 0 },
2938 },
2939 /* REG_0FC7 */
2940 {
2941 { Bad_Opcode },
2942 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2943 { Bad_Opcode },
2944 { MOD_TABLE (MOD_0FC7_REG_3) },
2945 { MOD_TABLE (MOD_0FC7_REG_4) },
2946 { MOD_TABLE (MOD_0FC7_REG_5) },
2947 { MOD_TABLE (MOD_0FC7_REG_6) },
2948 { MOD_TABLE (MOD_0FC7_REG_7) },
2949 },
2950 /* REG_VEX_0F71_M_0 */
2951 {
2952 { Bad_Opcode },
2953 { Bad_Opcode },
2954 { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
2955 { Bad_Opcode },
2956 { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
2957 { Bad_Opcode },
2958 { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
2959 },
2960 /* REG_VEX_0F72_M_0 */
2961 {
2962 { Bad_Opcode },
2963 { Bad_Opcode },
2964 { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
2965 { Bad_Opcode },
2966 { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
2967 { Bad_Opcode },
2968 { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
2969 },
2970 /* REG_VEX_0F73_M_0 */
2971 {
2972 { Bad_Opcode },
2973 { Bad_Opcode },
2974 { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
2975 { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
2976 { Bad_Opcode },
2977 { Bad_Opcode },
2978 { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
2979 { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
2980 },
2981 /* REG_VEX_0FAE */
2982 {
2983 { Bad_Opcode },
2984 { Bad_Opcode },
2985 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2986 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2987 },
2988 /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
2989 {
2990 { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
2991 },
2992 /* REG_VEX_0F38F3_L_0 */
2993 {
2994 { Bad_Opcode },
2995 { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
2996 { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
2997 { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
2998 },
2999 /* REG_0FXOP_09_01_L_0 */
3000 {
3001 { Bad_Opcode },
3002 { "blcfill", { VexGdq, Edq }, 0 },
3003 { "blsfill", { VexGdq, Edq }, 0 },
3004 { "blcs", { VexGdq, Edq }, 0 },
3005 { "tzmsk", { VexGdq, Edq }, 0 },
3006 { "blcic", { VexGdq, Edq }, 0 },
3007 { "blsic", { VexGdq, Edq }, 0 },
3008 { "t1mskc", { VexGdq, Edq }, 0 },
3009 },
3010 /* REG_0FXOP_09_02_L_0 */
3011 {
3012 { Bad_Opcode },
3013 { "blcmsk", { VexGdq, Edq }, 0 },
3014 { Bad_Opcode },
3015 { Bad_Opcode },
3016 { Bad_Opcode },
3017 { Bad_Opcode },
3018 { "blci", { VexGdq, Edq }, 0 },
3019 },
3020 /* REG_0FXOP_09_12_M_1_L_0 */
3021 {
3022 { "llwpcb", { Edq }, 0 },
3023 { "slwpcb", { Edq }, 0 },
3024 },
3025 /* REG_0FXOP_0A_12_L_0 */
3026 {
3027 { "lwpins", { VexGdq, Ed, Id }, 0 },
3028 { "lwpval", { VexGdq, Ed, Id }, 0 },
3029 },
3030
3031 #include "i386-dis-evex-reg.h"
3032 };
3033
3034 static const struct dis386 prefix_table[][4] = {
3035 /* PREFIX_90 */
3036 {
3037 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3038 { "pause", { XX }, 0 },
3039 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3040 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3041 },
3042
3043 /* PREFIX_0F01_REG_1_RM_4 */
3044 {
3045 { Bad_Opcode },
3046 { Bad_Opcode },
3047 { "tdcall", { Skip_MODRM }, 0 },
3048 { Bad_Opcode },
3049 },
3050
3051 /* PREFIX_0F01_REG_1_RM_5 */
3052 {
3053 { Bad_Opcode },
3054 { Bad_Opcode },
3055 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3056 { Bad_Opcode },
3057 },
3058
3059 /* PREFIX_0F01_REG_1_RM_6 */
3060 {
3061 { Bad_Opcode },
3062 { Bad_Opcode },
3063 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3064 { Bad_Opcode },
3065 },
3066
3067 /* PREFIX_0F01_REG_1_RM_7 */
3068 {
3069 { "encls", { Skip_MODRM }, 0 },
3070 { Bad_Opcode },
3071 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3072 { Bad_Opcode },
3073 },
3074
3075 /* PREFIX_0F01_REG_3_RM_1 */
3076 {
3077 { "vmmcall", { Skip_MODRM }, 0 },
3078 { "vmgexit", { Skip_MODRM }, 0 },
3079 { Bad_Opcode },
3080 { "vmgexit", { Skip_MODRM }, 0 },
3081 },
3082
3083 /* PREFIX_0F01_REG_5_MOD_0 */
3084 {
3085 { Bad_Opcode },
3086 { "rstorssp", { Mq }, PREFIX_OPCODE },
3087 },
3088
3089 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3090 {
3091 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3092 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3093 { Bad_Opcode },
3094 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3095 },
3096
3097 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3098 {
3099 { Bad_Opcode },
3100 { Bad_Opcode },
3101 { Bad_Opcode },
3102 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3103 },
3104
3105 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3106 {
3107 { Bad_Opcode },
3108 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3109 },
3110
3111 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3112 {
3113 { Bad_Opcode },
3114 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3115 },
3116
3117 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3118 {
3119 { Bad_Opcode },
3120 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3121 },
3122
3123 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3124 {
3125 { "rdpkru", { Skip_MODRM }, 0 },
3126 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3127 },
3128
3129 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3130 {
3131 { "wrpkru", { Skip_MODRM }, 0 },
3132 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3133 },
3134
3135 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3136 {
3137 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3138 { "mcommit", { Skip_MODRM }, 0 },
3139 },
3140
3141 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3142 {
3143 { "invlpgb", { Skip_MODRM }, 0 },
3144 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3145 { Bad_Opcode },
3146 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3147 },
3148
3149 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3150 {
3151 { "tlbsync", { Skip_MODRM }, 0 },
3152 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3153 { Bad_Opcode },
3154 { "pvalidate", { Skip_MODRM }, 0 },
3155 },
3156
3157 /* PREFIX_0F09 */
3158 {
3159 { "wbinvd", { XX }, 0 },
3160 { "wbnoinvd", { XX }, 0 },
3161 },
3162
3163 /* PREFIX_0F10 */
3164 {
3165 { "movups", { XM, EXx }, PREFIX_OPCODE },
3166 { "movss", { XM, EXd }, PREFIX_OPCODE },
3167 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3168 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3169 },
3170
3171 /* PREFIX_0F11 */
3172 {
3173 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3174 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3175 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3176 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3177 },
3178
3179 /* PREFIX_0F12 */
3180 {
3181 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3182 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3183 { MOD_TABLE (MOD_0F12_PREFIX_2) },
3184 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3185 },
3186
3187 /* PREFIX_0F16 */
3188 {
3189 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3190 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3191 { MOD_TABLE (MOD_0F16_PREFIX_2) },
3192 },
3193
3194 /* PREFIX_0F1A */
3195 {
3196 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3197 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3198 { "bndmov", { Gbnd, Ebnd }, 0 },
3199 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3200 },
3201
3202 /* PREFIX_0F1B */
3203 {
3204 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3205 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3206 { "bndmov", { EbndS, Gbnd }, 0 },
3207 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3208 },
3209
3210 /* PREFIX_0F1C */
3211 {
3212 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3213 { "nopQ", { Ev }, PREFIX_IGNORED },
3214 { "nopQ", { Ev }, 0 },
3215 { "nopQ", { Ev }, PREFIX_IGNORED },
3216 },
3217
3218 /* PREFIX_0F1E */
3219 {
3220 { "nopQ", { Ev }, 0 },
3221 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3222 { "nopQ", { Ev }, 0 },
3223 { NULL, { XX }, PREFIX_IGNORED },
3224 },
3225
3226 /* PREFIX_0F2A */
3227 {
3228 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3229 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3230 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3231 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3232 },
3233
3234 /* PREFIX_0F2B */
3235 {
3236 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3237 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3238 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3239 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3240 },
3241
3242 /* PREFIX_0F2C */
3243 {
3244 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3245 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3246 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3247 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3248 },
3249
3250 /* PREFIX_0F2D */
3251 {
3252 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3253 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3254 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3255 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3256 },
3257
3258 /* PREFIX_0F2E */
3259 {
3260 { "ucomiss",{ XM, EXd }, 0 },
3261 { Bad_Opcode },
3262 { "ucomisd",{ XM, EXq }, 0 },
3263 },
3264
3265 /* PREFIX_0F2F */
3266 {
3267 { "comiss", { XM, EXd }, 0 },
3268 { Bad_Opcode },
3269 { "comisd", { XM, EXq }, 0 },
3270 },
3271
3272 /* PREFIX_0F51 */
3273 {
3274 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3275 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3276 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3277 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3278 },
3279
3280 /* PREFIX_0F52 */
3281 {
3282 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3283 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3284 },
3285
3286 /* PREFIX_0F53 */
3287 {
3288 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3289 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3290 },
3291
3292 /* PREFIX_0F58 */
3293 {
3294 { "addps", { XM, EXx }, PREFIX_OPCODE },
3295 { "addss", { XM, EXd }, PREFIX_OPCODE },
3296 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3297 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3298 },
3299
3300 /* PREFIX_0F59 */
3301 {
3302 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3303 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3304 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3305 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3306 },
3307
3308 /* PREFIX_0F5A */
3309 {
3310 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3311 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3312 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3313 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3314 },
3315
3316 /* PREFIX_0F5B */
3317 {
3318 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3319 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3320 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3321 },
3322
3323 /* PREFIX_0F5C */
3324 {
3325 { "subps", { XM, EXx }, PREFIX_OPCODE },
3326 { "subss", { XM, EXd }, PREFIX_OPCODE },
3327 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3328 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3329 },
3330
3331 /* PREFIX_0F5D */
3332 {
3333 { "minps", { XM, EXx }, PREFIX_OPCODE },
3334 { "minss", { XM, EXd }, PREFIX_OPCODE },
3335 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3336 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3337 },
3338
3339 /* PREFIX_0F5E */
3340 {
3341 { "divps", { XM, EXx }, PREFIX_OPCODE },
3342 { "divss", { XM, EXd }, PREFIX_OPCODE },
3343 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3344 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3345 },
3346
3347 /* PREFIX_0F5F */
3348 {
3349 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3350 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3351 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3352 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3353 },
3354
3355 /* PREFIX_0F60 */
3356 {
3357 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3358 { Bad_Opcode },
3359 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3360 },
3361
3362 /* PREFIX_0F61 */
3363 {
3364 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3365 { Bad_Opcode },
3366 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3367 },
3368
3369 /* PREFIX_0F62 */
3370 {
3371 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3372 { Bad_Opcode },
3373 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3374 },
3375
3376 /* PREFIX_0F6F */
3377 {
3378 { "movq", { MX, EM }, PREFIX_OPCODE },
3379 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3380 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3381 },
3382
3383 /* PREFIX_0F70 */
3384 {
3385 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3386 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3387 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3388 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3389 },
3390
3391 /* PREFIX_0F78 */
3392 {
3393 {"vmread", { Em, Gm }, 0 },
3394 { Bad_Opcode },
3395 {"extrq", { XS, Ib, Ib }, 0 },
3396 {"insertq", { XM, XS, Ib, Ib }, 0 },
3397 },
3398
3399 /* PREFIX_0F79 */
3400 {
3401 {"vmwrite", { Gm, Em }, 0 },
3402 { Bad_Opcode },
3403 {"extrq", { XM, XS }, 0 },
3404 {"insertq", { XM, XS }, 0 },
3405 },
3406
3407 /* PREFIX_0F7C */
3408 {
3409 { Bad_Opcode },
3410 { Bad_Opcode },
3411 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3412 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3413 },
3414
3415 /* PREFIX_0F7D */
3416 {
3417 { Bad_Opcode },
3418 { Bad_Opcode },
3419 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3420 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3421 },
3422
3423 /* PREFIX_0F7E */
3424 {
3425 { "movK", { Edq, MX }, PREFIX_OPCODE },
3426 { "movq", { XM, EXq }, PREFIX_OPCODE },
3427 { "movK", { Edq, XM }, PREFIX_OPCODE },
3428 },
3429
3430 /* PREFIX_0F7F */
3431 {
3432 { "movq", { EMS, MX }, PREFIX_OPCODE },
3433 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3434 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3435 },
3436
3437 /* PREFIX_0FAE_REG_0_MOD_3 */
3438 {
3439 { Bad_Opcode },
3440 { "rdfsbase", { Ev }, 0 },
3441 },
3442
3443 /* PREFIX_0FAE_REG_1_MOD_3 */
3444 {
3445 { Bad_Opcode },
3446 { "rdgsbase", { Ev }, 0 },
3447 },
3448
3449 /* PREFIX_0FAE_REG_2_MOD_3 */
3450 {
3451 { Bad_Opcode },
3452 { "wrfsbase", { Ev }, 0 },
3453 },
3454
3455 /* PREFIX_0FAE_REG_3_MOD_3 */
3456 {
3457 { Bad_Opcode },
3458 { "wrgsbase", { Ev }, 0 },
3459 },
3460
3461 /* PREFIX_0FAE_REG_4_MOD_0 */
3462 {
3463 { "xsave", { FXSAVE }, 0 },
3464 { "ptwrite{%LQ|}", { Edq }, 0 },
3465 },
3466
3467 /* PREFIX_0FAE_REG_4_MOD_3 */
3468 {
3469 { Bad_Opcode },
3470 { "ptwrite{%LQ|}", { Edq }, 0 },
3471 },
3472
3473 /* PREFIX_0FAE_REG_5_MOD_3 */
3474 {
3475 { "lfence", { Skip_MODRM }, 0 },
3476 { "incsspK", { Edq }, PREFIX_OPCODE },
3477 },
3478
3479 /* PREFIX_0FAE_REG_6_MOD_0 */
3480 {
3481 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
3482 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3483 { "clwb", { Mb }, PREFIX_OPCODE },
3484 },
3485
3486 /* PREFIX_0FAE_REG_6_MOD_3 */
3487 {
3488 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3489 { "umonitor", { Eva }, PREFIX_OPCODE },
3490 { "tpause", { Edq }, PREFIX_OPCODE },
3491 { "umwait", { Edq }, PREFIX_OPCODE },
3492 },
3493
3494 /* PREFIX_0FAE_REG_7_MOD_0 */
3495 {
3496 { "clflush", { Mb }, 0 },
3497 { Bad_Opcode },
3498 { "clflushopt", { Mb }, 0 },
3499 },
3500
3501 /* PREFIX_0FB8 */
3502 {
3503 { Bad_Opcode },
3504 { "popcntS", { Gv, Ev }, 0 },
3505 },
3506
3507 /* PREFIX_0FBC */
3508 {
3509 { "bsfS", { Gv, Ev }, 0 },
3510 { "tzcntS", { Gv, Ev }, 0 },
3511 { "bsfS", { Gv, Ev }, 0 },
3512 },
3513
3514 /* PREFIX_0FBD */
3515 {
3516 { "bsrS", { Gv, Ev }, 0 },
3517 { "lzcntS", { Gv, Ev }, 0 },
3518 { "bsrS", { Gv, Ev }, 0 },
3519 },
3520
3521 /* PREFIX_0FC2 */
3522 {
3523 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
3524 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
3525 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
3526 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
3527 },
3528
3529 /* PREFIX_0FC7_REG_6_MOD_0 */
3530 {
3531 { "vmptrld",{ Mq }, 0 },
3532 { "vmxon", { Mq }, 0 },
3533 { "vmclear",{ Mq }, 0 },
3534 },
3535
3536 /* PREFIX_0FC7_REG_6_MOD_3 */
3537 {
3538 { "rdrand", { Ev }, 0 },
3539 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3540 { "rdrand", { Ev }, 0 }
3541 },
3542
3543 /* PREFIX_0FC7_REG_7_MOD_3 */
3544 {
3545 { "rdseed", { Ev }, 0 },
3546 { "rdpid", { Em }, 0 },
3547 { "rdseed", { Ev }, 0 },
3548 },
3549
3550 /* PREFIX_0FD0 */
3551 {
3552 { Bad_Opcode },
3553 { Bad_Opcode },
3554 { "addsubpd", { XM, EXx }, 0 },
3555 { "addsubps", { XM, EXx }, 0 },
3556 },
3557
3558 /* PREFIX_0FD6 */
3559 {
3560 { Bad_Opcode },
3561 { "movq2dq",{ XM, MS }, 0 },
3562 { "movq", { EXqS, XM }, 0 },
3563 { "movdq2q",{ MX, XS }, 0 },
3564 },
3565
3566 /* PREFIX_0FE6 */
3567 {
3568 { Bad_Opcode },
3569 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
3570 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
3571 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
3572 },
3573
3574 /* PREFIX_0FE7 */
3575 {
3576 { "movntq", { Mq, MX }, PREFIX_OPCODE },
3577 { Bad_Opcode },
3578 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3579 },
3580
3581 /* PREFIX_0FF0 */
3582 {
3583 { Bad_Opcode },
3584 { Bad_Opcode },
3585 { Bad_Opcode },
3586 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3587 },
3588
3589 /* PREFIX_0FF7 */
3590 {
3591 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
3592 { Bad_Opcode },
3593 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
3594 },
3595
3596 /* PREFIX_0F38D8 */
3597 {
3598 { Bad_Opcode },
3599 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3600 },
3601
3602 /* PREFIX_0F38DC */
3603 {
3604 { Bad_Opcode },
3605 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3606 { "aesenc", { XM, EXx }, 0 },
3607 },
3608
3609 /* PREFIX_0F38DD */
3610 {
3611 { Bad_Opcode },
3612 { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
3613 { "aesenclast", { XM, EXx }, 0 },
3614 },
3615
3616 /* PREFIX_0F38DE */
3617 {
3618 { Bad_Opcode },
3619 { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
3620 { "aesdec", { XM, EXx }, 0 },
3621 },
3622
3623 /* PREFIX_0F38DF */
3624 {
3625 { Bad_Opcode },
3626 { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
3627 { "aesdeclast", { XM, EXx }, 0 },
3628 },
3629
3630 /* PREFIX_0F38F0 */
3631 {
3632 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3633 { Bad_Opcode },
3634 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3635 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3636 },
3637
3638 /* PREFIX_0F38F1 */
3639 {
3640 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3641 { Bad_Opcode },
3642 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3643 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3644 },
3645
3646 /* PREFIX_0F38F6 */
3647 {
3648 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
3649 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
3650 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
3651 { Bad_Opcode },
3652 },
3653
3654 /* PREFIX_0F38F8 */
3655 {
3656 { Bad_Opcode },
3657 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
3658 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
3659 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
3660 },
3661 /* PREFIX_0F38FA */
3662 {
3663 { Bad_Opcode },
3664 { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
3665 },
3666
3667 /* PREFIX_0F38FB */
3668 {
3669 { Bad_Opcode },
3670 { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
3671 },
3672
3673 /* PREFIX_0F3A0F */
3674 {
3675 { Bad_Opcode },
3676 { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
3677 },
3678
3679 /* PREFIX_VEX_0F10 */
3680 {
3681 { "vmovups", { XM, EXx }, 0 },
3682 { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
3683 { "vmovupd", { XM, EXx }, 0 },
3684 { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
3685 },
3686
3687 /* PREFIX_VEX_0F11 */
3688 {
3689 { "vmovups", { EXxS, XM }, 0 },
3690 { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
3691 { "vmovupd", { EXxS, XM }, 0 },
3692 { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
3693 },
3694
3695 /* PREFIX_VEX_0F12 */
3696 {
3697 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3698 { "vmovsldup", { XM, EXx }, 0 },
3699 { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
3700 { "vmovddup", { XM, EXymmq }, 0 },
3701 },
3702
3703 /* PREFIX_VEX_0F16 */
3704 {
3705 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3706 { "vmovshdup", { XM, EXx }, 0 },
3707 { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
3708 },
3709
3710 /* PREFIX_VEX_0F2A */
3711 {
3712 { Bad_Opcode },
3713 { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3714 { Bad_Opcode },
3715 { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
3716 },
3717
3718 /* PREFIX_VEX_0F2C */
3719 {
3720 { Bad_Opcode },
3721 { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
3722 { Bad_Opcode },
3723 { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
3724 },
3725
3726 /* PREFIX_VEX_0F2D */
3727 {
3728 { Bad_Opcode },
3729 { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
3730 { Bad_Opcode },
3731 { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
3732 },
3733
3734 /* PREFIX_VEX_0F2E */
3735 {
3736 { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3737 { Bad_Opcode },
3738 { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3739 },
3740
3741 /* PREFIX_VEX_0F2F */
3742 {
3743 { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
3744 { Bad_Opcode },
3745 { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
3746 },
3747
3748 /* PREFIX_VEX_0F41_L_1_M_1_W_0 */
3749 {
3750 { "kandw", { MaskG, MaskVex, MaskE }, 0 },
3751 { Bad_Opcode },
3752 { "kandb", { MaskG, MaskVex, MaskE }, 0 },
3753 },
3754
3755 /* PREFIX_VEX_0F41_L_1_M_1_W_1 */
3756 {
3757 { "kandq", { MaskG, MaskVex, MaskE }, 0 },
3758 { Bad_Opcode },
3759 { "kandd", { MaskG, MaskVex, MaskE }, 0 },
3760 },
3761
3762 /* PREFIX_VEX_0F42_L_1_M_1_W_0 */
3763 {
3764 { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
3765 { Bad_Opcode },
3766 { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
3767 },
3768
3769 /* PREFIX_VEX_0F42_L_1_M_1_W_1 */
3770 {
3771 { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
3772 { Bad_Opcode },
3773 { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
3774 },
3775
3776 /* PREFIX_VEX_0F44_L_0_M_1_W_0 */
3777 {
3778 { "knotw", { MaskG, MaskE }, 0 },
3779 { Bad_Opcode },
3780 { "knotb", { MaskG, MaskE }, 0 },
3781 },
3782
3783 /* PREFIX_VEX_0F44_L_0_M_1_W_1 */
3784 {
3785 { "knotq", { MaskG, MaskE }, 0 },
3786 { Bad_Opcode },
3787 { "knotd", { MaskG, MaskE }, 0 },
3788 },
3789
3790 /* PREFIX_VEX_0F45_L_1_M_1_W_0 */
3791 {
3792 { "korw", { MaskG, MaskVex, MaskE }, 0 },
3793 { Bad_Opcode },
3794 { "korb", { MaskG, MaskVex, MaskE }, 0 },
3795 },
3796
3797 /* PREFIX_VEX_0F45_L_1_M_1_W_1 */
3798 {
3799 { "korq", { MaskG, MaskVex, MaskE }, 0 },
3800 { Bad_Opcode },
3801 { "kord", { MaskG, MaskVex, MaskE }, 0 },
3802 },
3803
3804 /* PREFIX_VEX_0F46_L_1_M_1_W_0 */
3805 {
3806 { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
3807 { Bad_Opcode },
3808 { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
3809 },
3810
3811 /* PREFIX_VEX_0F46_L_1_M_1_W_1 */
3812 {
3813 { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
3814 { Bad_Opcode },
3815 { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
3816 },
3817
3818 /* PREFIX_VEX_0F47_L_1_M_1_W_0 */
3819 {
3820 { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
3821 { Bad_Opcode },
3822 { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
3823 },
3824
3825 /* PREFIX_VEX_0F47_L_1_M_1_W_1 */
3826 {
3827 { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
3828 { Bad_Opcode },
3829 { "kxord", { MaskG, MaskVex, MaskE }, 0 },
3830 },
3831
3832 /* PREFIX_VEX_0F4A_L_1_M_1_W_0 */
3833 {
3834 { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
3835 { Bad_Opcode },
3836 { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
3837 },
3838
3839 /* PREFIX_VEX_0F4A_L_1_M_1_W_1 */
3840 {
3841 { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
3842 { Bad_Opcode },
3843 { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
3844 },
3845
3846 /* PREFIX_VEX_0F4B_L_1_M_1_W_0 */
3847 {
3848 { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
3849 { Bad_Opcode },
3850 { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
3851 },
3852
3853 /* PREFIX_VEX_0F4B_L_1_M_1_W_1 */
3854 {
3855 { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
3856 },
3857
3858 /* PREFIX_VEX_0F51 */
3859 {
3860 { "vsqrtps", { XM, EXx }, 0 },
3861 { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3862 { "vsqrtpd", { XM, EXx }, 0 },
3863 { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3864 },
3865
3866 /* PREFIX_VEX_0F52 */
3867 {
3868 { "vrsqrtps", { XM, EXx }, 0 },
3869 { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F53 */
3873 {
3874 { "vrcpps", { XM, EXx }, 0 },
3875 { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3876 },
3877
3878 /* PREFIX_VEX_0F58 */
3879 {
3880 { "vaddps", { XM, Vex, EXx }, 0 },
3881 { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3882 { "vaddpd", { XM, Vex, EXx }, 0 },
3883 { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3884 },
3885
3886 /* PREFIX_VEX_0F59 */
3887 {
3888 { "vmulps", { XM, Vex, EXx }, 0 },
3889 { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3890 { "vmulpd", { XM, Vex, EXx }, 0 },
3891 { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3892 },
3893
3894 /* PREFIX_VEX_0F5A */
3895 {
3896 { "vcvtps2pd", { XM, EXxmmq }, 0 },
3897 { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
3898 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
3899 { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3900 },
3901
3902 /* PREFIX_VEX_0F5B */
3903 {
3904 { "vcvtdq2ps", { XM, EXx }, 0 },
3905 { "vcvttps2dq", { XM, EXx }, 0 },
3906 { "vcvtps2dq", { XM, EXx }, 0 },
3907 },
3908
3909 /* PREFIX_VEX_0F5C */
3910 {
3911 { "vsubps", { XM, Vex, EXx }, 0 },
3912 { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3913 { "vsubpd", { XM, Vex, EXx }, 0 },
3914 { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3915 },
3916
3917 /* PREFIX_VEX_0F5D */
3918 {
3919 { "vminps", { XM, Vex, EXx }, 0 },
3920 { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3921 { "vminpd", { XM, Vex, EXx }, 0 },
3922 { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3923 },
3924
3925 /* PREFIX_VEX_0F5E */
3926 {
3927 { "vdivps", { XM, Vex, EXx }, 0 },
3928 { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3929 { "vdivpd", { XM, Vex, EXx }, 0 },
3930 { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3931 },
3932
3933 /* PREFIX_VEX_0F5F */
3934 {
3935 { "vmaxps", { XM, Vex, EXx }, 0 },
3936 { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
3937 { "vmaxpd", { XM, Vex, EXx }, 0 },
3938 { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
3939 },
3940
3941 /* PREFIX_VEX_0F6F */
3942 {
3943 { Bad_Opcode },
3944 { "vmovdqu", { XM, EXx }, 0 },
3945 { "vmovdqa", { XM, EXx }, 0 },
3946 },
3947
3948 /* PREFIX_VEX_0F70 */
3949 {
3950 { Bad_Opcode },
3951 { "vpshufhw", { XM, EXx, Ib }, 0 },
3952 { "vpshufd", { XM, EXx, Ib }, 0 },
3953 { "vpshuflw", { XM, EXx, Ib }, 0 },
3954 },
3955
3956 /* PREFIX_VEX_0F7C */
3957 {
3958 { Bad_Opcode },
3959 { Bad_Opcode },
3960 { "vhaddpd", { XM, Vex, EXx }, 0 },
3961 { "vhaddps", { XM, Vex, EXx }, 0 },
3962 },
3963
3964 /* PREFIX_VEX_0F7D */
3965 {
3966 { Bad_Opcode },
3967 { Bad_Opcode },
3968 { "vhsubpd", { XM, Vex, EXx }, 0 },
3969 { "vhsubps", { XM, Vex, EXx }, 0 },
3970 },
3971
3972 /* PREFIX_VEX_0F7E */
3973 {
3974 { Bad_Opcode },
3975 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3976 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3977 },
3978
3979 /* PREFIX_VEX_0F7F */
3980 {
3981 { Bad_Opcode },
3982 { "vmovdqu", { EXxS, XM }, 0 },
3983 { "vmovdqa", { EXxS, XM }, 0 },
3984 },
3985
3986 /* PREFIX_VEX_0F90_L_0_W_0 */
3987 {
3988 { "kmovw", { MaskG, MaskE }, 0 },
3989 { Bad_Opcode },
3990 { "kmovb", { MaskG, MaskBDE }, 0 },
3991 },
3992
3993 /* PREFIX_VEX_0F90_L_0_W_1 */
3994 {
3995 { "kmovq", { MaskG, MaskE }, 0 },
3996 { Bad_Opcode },
3997 { "kmovd", { MaskG, MaskBDE }, 0 },
3998 },
3999
4000 /* PREFIX_VEX_0F91_L_0_M_0_W_0 */
4001 {
4002 { "kmovw", { Ew, MaskG }, 0 },
4003 { Bad_Opcode },
4004 { "kmovb", { Eb, MaskG }, 0 },
4005 },
4006
4007 /* PREFIX_VEX_0F91_L_0_M_0_W_1 */
4008 {
4009 { "kmovq", { Eq, MaskG }, 0 },
4010 { Bad_Opcode },
4011 { "kmovd", { Ed, MaskG }, 0 },
4012 },
4013
4014 /* PREFIX_VEX_0F92_L_0_M_1_W_0 */
4015 {
4016 { "kmovw", { MaskG, Edq }, 0 },
4017 { Bad_Opcode },
4018 { "kmovb", { MaskG, Edq }, 0 },
4019 { "kmovd", { MaskG, Edq }, 0 },
4020 },
4021
4022 /* PREFIX_VEX_0F92_L_0_M_1_W_1 */
4023 {
4024 { Bad_Opcode },
4025 { Bad_Opcode },
4026 { Bad_Opcode },
4027 { "kmovK", { MaskG, Edq }, 0 },
4028 },
4029
4030 /* PREFIX_VEX_0F93_L_0_M_1_W_0 */
4031 {
4032 { "kmovw", { Gdq, MaskE }, 0 },
4033 { Bad_Opcode },
4034 { "kmovb", { Gdq, MaskE }, 0 },
4035 { "kmovd", { Gdq, MaskE }, 0 },
4036 },
4037
4038 /* PREFIX_VEX_0F93_L_0_M_1_W_1 */
4039 {
4040 { Bad_Opcode },
4041 { Bad_Opcode },
4042 { Bad_Opcode },
4043 { "kmovK", { Gdq, MaskE }, 0 },
4044 },
4045
4046 /* PREFIX_VEX_0F98_L_0_M_1_W_0 */
4047 {
4048 { "kortestw", { MaskG, MaskE }, 0 },
4049 { Bad_Opcode },
4050 { "kortestb", { MaskG, MaskE }, 0 },
4051 },
4052
4053 /* PREFIX_VEX_0F98_L_0_M_1_W_1 */
4054 {
4055 { "kortestq", { MaskG, MaskE }, 0 },
4056 { Bad_Opcode },
4057 { "kortestd", { MaskG, MaskE }, 0 },
4058 },
4059
4060 /* PREFIX_VEX_0F99_L_0_M_1_W_0 */
4061 {
4062 { "ktestw", { MaskG, MaskE }, 0 },
4063 { Bad_Opcode },
4064 { "ktestb", { MaskG, MaskE }, 0 },
4065 },
4066
4067 /* PREFIX_VEX_0F99_L_0_M_1_W_1 */
4068 {
4069 { "ktestq", { MaskG, MaskE }, 0 },
4070 { Bad_Opcode },
4071 { "ktestd", { MaskG, MaskE }, 0 },
4072 },
4073
4074 /* PREFIX_VEX_0FC2 */
4075 {
4076 { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
4077 { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
4078 { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
4079 { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
4080 },
4081
4082 /* PREFIX_VEX_0FD0 */
4083 {
4084 { Bad_Opcode },
4085 { Bad_Opcode },
4086 { "vaddsubpd", { XM, Vex, EXx }, 0 },
4087 { "vaddsubps", { XM, Vex, EXx }, 0 },
4088 },
4089
4090 /* PREFIX_VEX_0FE6 */
4091 {
4092 { Bad_Opcode },
4093 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
4094 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
4095 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
4096 },
4097
4098 /* PREFIX_VEX_0FF0 */
4099 {
4100 { Bad_Opcode },
4101 { Bad_Opcode },
4102 { Bad_Opcode },
4103 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4104 },
4105
4106 /* PREFIX_VEX_0F3849_X86_64 */
4107 {
4108 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
4109 { Bad_Opcode },
4110 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
4111 { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
4112 },
4113
4114 /* PREFIX_VEX_0F384B_X86_64 */
4115 {
4116 { Bad_Opcode },
4117 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
4118 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
4119 { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
4120 },
4121
4122 /* PREFIX_VEX_0F385C_X86_64 */
4123 {
4124 { Bad_Opcode },
4125 { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
4126 { Bad_Opcode },
4127 },
4128
4129 /* PREFIX_VEX_0F385E_X86_64 */
4130 {
4131 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
4132 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
4133 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
4134 { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
4135 },
4136
4137 /* PREFIX_VEX_0F38F5_L_0 */
4138 {
4139 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4140 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4141 { Bad_Opcode },
4142 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4143 },
4144
4145 /* PREFIX_VEX_0F38F6_L_0 */
4146 {
4147 { Bad_Opcode },
4148 { Bad_Opcode },
4149 { Bad_Opcode },
4150 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4151 },
4152
4153 /* PREFIX_VEX_0F38F7_L_0 */
4154 {
4155 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4156 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4157 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4158 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4159 },
4160
4161 /* PREFIX_VEX_0F3AF0_L_0 */
4162 {
4163 { Bad_Opcode },
4164 { Bad_Opcode },
4165 { Bad_Opcode },
4166 { "rorxS", { Gdq, Edq, Ib }, 0 },
4167 },
4168
4169 #include "i386-dis-evex-prefix.h"
4170 };
4171
4172 static const struct dis386 x86_64_table[][2] = {
4173 /* X86_64_06 */
4174 {
4175 { "pushP", { es }, 0 },
4176 },
4177
4178 /* X86_64_07 */
4179 {
4180 { "popP", { es }, 0 },
4181 },
4182
4183 /* X86_64_0E */
4184 {
4185 { "pushP", { cs }, 0 },
4186 },
4187
4188 /* X86_64_16 */
4189 {
4190 { "pushP", { ss }, 0 },
4191 },
4192
4193 /* X86_64_17 */
4194 {
4195 { "popP", { ss }, 0 },
4196 },
4197
4198 /* X86_64_1E */
4199 {
4200 { "pushP", { ds }, 0 },
4201 },
4202
4203 /* X86_64_1F */
4204 {
4205 { "popP", { ds }, 0 },
4206 },
4207
4208 /* X86_64_27 */
4209 {
4210 { "daa", { XX }, 0 },
4211 },
4212
4213 /* X86_64_2F */
4214 {
4215 { "das", { XX }, 0 },
4216 },
4217
4218 /* X86_64_37 */
4219 {
4220 { "aaa", { XX }, 0 },
4221 },
4222
4223 /* X86_64_3F */
4224 {
4225 { "aas", { XX }, 0 },
4226 },
4227
4228 /* X86_64_60 */
4229 {
4230 { "pushaP", { XX }, 0 },
4231 },
4232
4233 /* X86_64_61 */
4234 {
4235 { "popaP", { XX }, 0 },
4236 },
4237
4238 /* X86_64_62 */
4239 {
4240 { MOD_TABLE (MOD_62_32BIT) },
4241 { EVEX_TABLE (EVEX_0F) },
4242 },
4243
4244 /* X86_64_63 */
4245 {
4246 { "arpl", { Ew, Gw }, 0 },
4247 { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4248 },
4249
4250 /* X86_64_6D */
4251 {
4252 { "ins{R|}", { Yzr, indirDX }, 0 },
4253 { "ins{G|}", { Yzr, indirDX }, 0 },
4254 },
4255
4256 /* X86_64_6F */
4257 {
4258 { "outs{R|}", { indirDXr, Xz }, 0 },
4259 { "outs{G|}", { indirDXr, Xz }, 0 },
4260 },
4261
4262 /* X86_64_82 */
4263 {
4264 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4265 { REG_TABLE (REG_80) },
4266 },
4267
4268 /* X86_64_9A */
4269 {
4270 { "{l|}call{P|}", { Ap }, 0 },
4271 },
4272
4273 /* X86_64_C2 */
4274 {
4275 { "retP", { Iw, BND }, 0 },
4276 { "ret@", { Iw, BND }, 0 },
4277 },
4278
4279 /* X86_64_C3 */
4280 {
4281 { "retP", { BND }, 0 },
4282 { "ret@", { BND }, 0 },
4283 },
4284
4285 /* X86_64_C4 */
4286 {
4287 { MOD_TABLE (MOD_C4_32BIT) },
4288 { VEX_C4_TABLE (VEX_0F) },
4289 },
4290
4291 /* X86_64_C5 */
4292 {
4293 { MOD_TABLE (MOD_C5_32BIT) },
4294 { VEX_C5_TABLE (VEX_0F) },
4295 },
4296
4297 /* X86_64_CE */
4298 {
4299 { "into", { XX }, 0 },
4300 },
4301
4302 /* X86_64_D4 */
4303 {
4304 { "aam", { Ib }, 0 },
4305 },
4306
4307 /* X86_64_D5 */
4308 {
4309 { "aad", { Ib }, 0 },
4310 },
4311
4312 /* X86_64_E8 */
4313 {
4314 { "callP", { Jv, BND }, 0 },
4315 { "call@", { Jv, BND }, 0 }
4316 },
4317
4318 /* X86_64_E9 */
4319 {
4320 { "jmpP", { Jv, BND }, 0 },
4321 { "jmp@", { Jv, BND }, 0 }
4322 },
4323
4324 /* X86_64_EA */
4325 {
4326 { "{l|}jmp{P|}", { Ap }, 0 },
4327 },
4328
4329 /* X86_64_0F01_REG_0 */
4330 {
4331 { "sgdt{Q|Q}", { M }, 0 },
4332 { "sgdt", { M }, 0 },
4333 },
4334
4335 /* X86_64_0F01_REG_1 */
4336 {
4337 { "sidt{Q|Q}", { M }, 0 },
4338 { "sidt", { M }, 0 },
4339 },
4340
4341 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4342 {
4343 { Bad_Opcode },
4344 { "seamret", { Skip_MODRM }, 0 },
4345 },
4346
4347 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4348 {
4349 { Bad_Opcode },
4350 { "seamops", { Skip_MODRM }, 0 },
4351 },
4352
4353 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4354 {
4355 { Bad_Opcode },
4356 { "seamcall", { Skip_MODRM }, 0 },
4357 },
4358
4359 /* X86_64_0F01_REG_2 */
4360 {
4361 { "lgdt{Q|Q}", { M }, 0 },
4362 { "lgdt", { M }, 0 },
4363 },
4364
4365 /* X86_64_0F01_REG_3 */
4366 {
4367 { "lidt{Q|Q}", { M }, 0 },
4368 { "lidt", { M }, 0 },
4369 },
4370
4371 {
4372 /* X86_64_0F24 */
4373 { "movZ", { Em, Td }, 0 },
4374 },
4375
4376 {
4377 /* X86_64_0F26 */
4378 { "movZ", { Td, Em }, 0 },
4379 },
4380
4381 /* X86_64_VEX_0F3849 */
4382 {
4383 { Bad_Opcode },
4384 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
4385 },
4386
4387 /* X86_64_VEX_0F384B */
4388 {
4389 { Bad_Opcode },
4390 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
4391 },
4392
4393 /* X86_64_VEX_0F385C */
4394 {
4395 { Bad_Opcode },
4396 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
4397 },
4398
4399 /* X86_64_VEX_0F385E */
4400 {
4401 { Bad_Opcode },
4402 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
4403 },
4404
4405 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4406 {
4407 { Bad_Opcode },
4408 { "uiret", { Skip_MODRM }, 0 },
4409 },
4410
4411 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4412 {
4413 { Bad_Opcode },
4414 { "testui", { Skip_MODRM }, 0 },
4415 },
4416
4417 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4418 {
4419 { Bad_Opcode },
4420 { "clui", { Skip_MODRM }, 0 },
4421 },
4422
4423 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4424 {
4425 { Bad_Opcode },
4426 { "stui", { Skip_MODRM }, 0 },
4427 },
4428
4429 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4430 {
4431 { Bad_Opcode },
4432 { "rmpadjust", { Skip_MODRM }, 0 },
4433 },
4434
4435 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4436 {
4437 { Bad_Opcode },
4438 { "rmpupdate", { Skip_MODRM }, 0 },
4439 },
4440
4441 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4442 {
4443 { Bad_Opcode },
4444 { "psmash", { Skip_MODRM }, 0 },
4445 },
4446
4447 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4448 {
4449 { Bad_Opcode },
4450 { "senduipi", { Eq }, 0 },
4451 },
4452 };
4453
4454 static const struct dis386 three_byte_table[][256] = {
4455
4456 /* THREE_BYTE_0F38 */
4457 {
4458 /* 00 */
4459 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4460 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4461 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4462 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4463 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4464 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4465 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4466 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4467 /* 08 */
4468 { "psignb", { MX, EM }, PREFIX_OPCODE },
4469 { "psignw", { MX, EM }, PREFIX_OPCODE },
4470 { "psignd", { MX, EM }, PREFIX_OPCODE },
4471 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4472 { Bad_Opcode },
4473 { Bad_Opcode },
4474 { Bad_Opcode },
4475 { Bad_Opcode },
4476 /* 10 */
4477 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4478 { Bad_Opcode },
4479 { Bad_Opcode },
4480 { Bad_Opcode },
4481 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4482 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4483 { Bad_Opcode },
4484 { "ptest", { XM, EXx }, PREFIX_DATA },
4485 /* 18 */
4486 { Bad_Opcode },
4487 { Bad_Opcode },
4488 { Bad_Opcode },
4489 { Bad_Opcode },
4490 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4491 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4492 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4493 { Bad_Opcode },
4494 /* 20 */
4495 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4496 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4497 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4498 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4499 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4500 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4501 { Bad_Opcode },
4502 { Bad_Opcode },
4503 /* 28 */
4504 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4505 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4506 { MOD_TABLE (MOD_0F382A) },
4507 { "packusdw", { XM, EXx }, PREFIX_DATA },
4508 { Bad_Opcode },
4509 { Bad_Opcode },
4510 { Bad_Opcode },
4511 { Bad_Opcode },
4512 /* 30 */
4513 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4514 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4515 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4516 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4517 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4518 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4519 { Bad_Opcode },
4520 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4521 /* 38 */
4522 { "pminsb", { XM, EXx }, PREFIX_DATA },
4523 { "pminsd", { XM, EXx }, PREFIX_DATA },
4524 { "pminuw", { XM, EXx }, PREFIX_DATA },
4525 { "pminud", { XM, EXx }, PREFIX_DATA },
4526 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4527 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4528 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4529 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4530 /* 40 */
4531 { "pmulld", { XM, EXx }, PREFIX_DATA },
4532 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4533 { Bad_Opcode },
4534 { Bad_Opcode },
4535 { Bad_Opcode },
4536 { Bad_Opcode },
4537 { Bad_Opcode },
4538 { Bad_Opcode },
4539 /* 48 */
4540 { Bad_Opcode },
4541 { Bad_Opcode },
4542 { Bad_Opcode },
4543 { Bad_Opcode },
4544 { Bad_Opcode },
4545 { Bad_Opcode },
4546 { Bad_Opcode },
4547 { Bad_Opcode },
4548 /* 50 */
4549 { Bad_Opcode },
4550 { Bad_Opcode },
4551 { Bad_Opcode },
4552 { Bad_Opcode },
4553 { Bad_Opcode },
4554 { Bad_Opcode },
4555 { Bad_Opcode },
4556 { Bad_Opcode },
4557 /* 58 */
4558 { Bad_Opcode },
4559 { Bad_Opcode },
4560 { Bad_Opcode },
4561 { Bad_Opcode },
4562 { Bad_Opcode },
4563 { Bad_Opcode },
4564 { Bad_Opcode },
4565 { Bad_Opcode },
4566 /* 60 */
4567 { Bad_Opcode },
4568 { Bad_Opcode },
4569 { Bad_Opcode },
4570 { Bad_Opcode },
4571 { Bad_Opcode },
4572 { Bad_Opcode },
4573 { Bad_Opcode },
4574 { Bad_Opcode },
4575 /* 68 */
4576 { Bad_Opcode },
4577 { Bad_Opcode },
4578 { Bad_Opcode },
4579 { Bad_Opcode },
4580 { Bad_Opcode },
4581 { Bad_Opcode },
4582 { Bad_Opcode },
4583 { Bad_Opcode },
4584 /* 70 */
4585 { Bad_Opcode },
4586 { Bad_Opcode },
4587 { Bad_Opcode },
4588 { Bad_Opcode },
4589 { Bad_Opcode },
4590 { Bad_Opcode },
4591 { Bad_Opcode },
4592 { Bad_Opcode },
4593 /* 78 */
4594 { Bad_Opcode },
4595 { Bad_Opcode },
4596 { Bad_Opcode },
4597 { Bad_Opcode },
4598 { Bad_Opcode },
4599 { Bad_Opcode },
4600 { Bad_Opcode },
4601 { Bad_Opcode },
4602 /* 80 */
4603 { "invept", { Gm, Mo }, PREFIX_DATA },
4604 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4605 { "invpcid", { Gm, M }, PREFIX_DATA },
4606 { Bad_Opcode },
4607 { Bad_Opcode },
4608 { Bad_Opcode },
4609 { Bad_Opcode },
4610 { Bad_Opcode },
4611 /* 88 */
4612 { Bad_Opcode },
4613 { Bad_Opcode },
4614 { Bad_Opcode },
4615 { Bad_Opcode },
4616 { Bad_Opcode },
4617 { Bad_Opcode },
4618 { Bad_Opcode },
4619 { Bad_Opcode },
4620 /* 90 */
4621 { Bad_Opcode },
4622 { Bad_Opcode },
4623 { Bad_Opcode },
4624 { Bad_Opcode },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 /* 98 */
4630 { Bad_Opcode },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { Bad_Opcode },
4635 { Bad_Opcode },
4636 { Bad_Opcode },
4637 { Bad_Opcode },
4638 /* a0 */
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { Bad_Opcode },
4644 { Bad_Opcode },
4645 { Bad_Opcode },
4646 { Bad_Opcode },
4647 /* a8 */
4648 { Bad_Opcode },
4649 { Bad_Opcode },
4650 { Bad_Opcode },
4651 { Bad_Opcode },
4652 { Bad_Opcode },
4653 { Bad_Opcode },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 /* b0 */
4657 { Bad_Opcode },
4658 { Bad_Opcode },
4659 { Bad_Opcode },
4660 { Bad_Opcode },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 /* b8 */
4666 { Bad_Opcode },
4667 { Bad_Opcode },
4668 { Bad_Opcode },
4669 { Bad_Opcode },
4670 { Bad_Opcode },
4671 { Bad_Opcode },
4672 { Bad_Opcode },
4673 { Bad_Opcode },
4674 /* c0 */
4675 { Bad_Opcode },
4676 { Bad_Opcode },
4677 { Bad_Opcode },
4678 { Bad_Opcode },
4679 { Bad_Opcode },
4680 { Bad_Opcode },
4681 { Bad_Opcode },
4682 { Bad_Opcode },
4683 /* c8 */
4684 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4685 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4686 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4687 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4688 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4689 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4690 { Bad_Opcode },
4691 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4692 /* d0 */
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 /* d8 */
4702 { PREFIX_TABLE (PREFIX_0F38D8) },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { "aesimc", { XM, EXx }, PREFIX_DATA },
4706 { PREFIX_TABLE (PREFIX_0F38DC) },
4707 { PREFIX_TABLE (PREFIX_0F38DD) },
4708 { PREFIX_TABLE (PREFIX_0F38DE) },
4709 { PREFIX_TABLE (PREFIX_0F38DF) },
4710 /* e0 */
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 /* e8 */
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 /* f0 */
4729 { PREFIX_TABLE (PREFIX_0F38F0) },
4730 { PREFIX_TABLE (PREFIX_0F38F1) },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { MOD_TABLE (MOD_0F38F5) },
4735 { PREFIX_TABLE (PREFIX_0F38F6) },
4736 { Bad_Opcode },
4737 /* f8 */
4738 { PREFIX_TABLE (PREFIX_0F38F8) },
4739 { MOD_TABLE (MOD_0F38F9) },
4740 { PREFIX_TABLE (PREFIX_0F38FA) },
4741 { PREFIX_TABLE (PREFIX_0F38FB) },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 },
4747 /* THREE_BYTE_0F3A */
4748 {
4749 /* 00 */
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 { Bad_Opcode },
4756 { Bad_Opcode },
4757 { Bad_Opcode },
4758 /* 08 */
4759 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4760 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4761 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4762 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4763 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4764 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4765 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4766 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4767 /* 10 */
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
4773 { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
4774 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4775 { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
4776 /* 18 */
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 { Bad_Opcode },
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 /* 20 */
4786 { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
4787 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4788 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 { Bad_Opcode },
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 /* 28 */
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 { Bad_Opcode },
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 /* 30 */
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 { Bad_Opcode },
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 /* 38 */
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 { Bad_Opcode },
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 /* 40 */
4822 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4823 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4824 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4825 { Bad_Opcode },
4826 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4827 { Bad_Opcode },
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 /* 48 */
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 { Bad_Opcode },
4837 { Bad_Opcode },
4838 { Bad_Opcode },
4839 /* 50 */
4840 { Bad_Opcode },
4841 { Bad_Opcode },
4842 { Bad_Opcode },
4843 { Bad_Opcode },
4844 { Bad_Opcode },
4845 { Bad_Opcode },
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 /* 58 */
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 { Bad_Opcode },
4855 { Bad_Opcode },
4856 { Bad_Opcode },
4857 /* 60 */
4858 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4859 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
4860 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
4861 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
4862 { Bad_Opcode },
4863 { Bad_Opcode },
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 /* 68 */
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 { Bad_Opcode },
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 /* 70 */
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 { Bad_Opcode },
4882 { Bad_Opcode },
4883 { Bad_Opcode },
4884 /* 78 */
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { Bad_Opcode },
4888 { Bad_Opcode },
4889 { Bad_Opcode },
4890 { Bad_Opcode },
4891 { Bad_Opcode },
4892 { Bad_Opcode },
4893 /* 80 */
4894 { Bad_Opcode },
4895 { Bad_Opcode },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 { Bad_Opcode },
4900 { Bad_Opcode },
4901 { Bad_Opcode },
4902 /* 88 */
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 /* 90 */
4912 { Bad_Opcode },
4913 { Bad_Opcode },
4914 { Bad_Opcode },
4915 { Bad_Opcode },
4916 { Bad_Opcode },
4917 { Bad_Opcode },
4918 { Bad_Opcode },
4919 { Bad_Opcode },
4920 /* 98 */
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { Bad_Opcode },
4926 { Bad_Opcode },
4927 { Bad_Opcode },
4928 { Bad_Opcode },
4929 /* a0 */
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 /* a8 */
4939 { Bad_Opcode },
4940 { Bad_Opcode },
4941 { Bad_Opcode },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 /* b0 */
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 /* b8 */
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 /* c0 */
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 /* c8 */
4975 { Bad_Opcode },
4976 { Bad_Opcode },
4977 { Bad_Opcode },
4978 { Bad_Opcode },
4979 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4980 { Bad_Opcode },
4981 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4982 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
4983 /* d0 */
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 /* d8 */
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5001 /* e0 */
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 /* e8 */
5011 { Bad_Opcode },
5012 { Bad_Opcode },
5013 { Bad_Opcode },
5014 { Bad_Opcode },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 /* f0 */
5020 { PREFIX_TABLE (PREFIX_0F3A0F) },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 /* f8 */
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 },
5038 };
5039
5040 static const struct dis386 xop_table[][256] = {
5041 /* XOP_08 */
5042 {
5043 /* 00 */
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 { Bad_Opcode },
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 /* 08 */
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 { Bad_Opcode },
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 /* 10 */
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 { Bad_Opcode },
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 /* 18 */
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 { Bad_Opcode },
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 /* 20 */
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 { Bad_Opcode },
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 /* 28 */
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 { Bad_Opcode },
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 /* 30 */
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 { Bad_Opcode },
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 /* 38 */
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 { Bad_Opcode },
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 /* 40 */
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 { Bad_Opcode },
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 /* 48 */
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 { Bad_Opcode },
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { Bad_Opcode },
5133 /* 50 */
5134 { Bad_Opcode },
5135 { Bad_Opcode },
5136 { Bad_Opcode },
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 /* 58 */
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 { Bad_Opcode },
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 /* 60 */
5152 { Bad_Opcode },
5153 { Bad_Opcode },
5154 { Bad_Opcode },
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 /* 68 */
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 { Bad_Opcode },
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 /* 70 */
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 { Bad_Opcode },
5173 { Bad_Opcode },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 /* 78 */
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 { Bad_Opcode },
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 /* 80 */
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 { Bad_Opcode },
5191 { Bad_Opcode },
5192 { Bad_Opcode },
5193 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
5194 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
5195 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
5196 /* 88 */
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
5204 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
5205 /* 90 */
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
5212 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
5213 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
5214 /* 98 */
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
5222 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
5223 /* a0 */
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5227 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
5231 { Bad_Opcode },
5232 /* a8 */
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 /* b0 */
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
5249 { Bad_Opcode },
5250 /* b8 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* c0 */
5260 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
5261 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
5262 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
5263 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* c8 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
5274 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
5275 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
5276 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
5277 /* d0 */
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 /* d8 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* e0 */
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 /* e8 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
5310 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
5311 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
5312 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
5313 /* f0 */
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* f8 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 },
5332 /* XOP_09 */
5333 {
5334 /* 00 */
5335 { Bad_Opcode },
5336 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
5337 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 { Bad_Opcode },
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 /* 08 */
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { Bad_Opcode },
5347 { Bad_Opcode },
5348 { Bad_Opcode },
5349 { Bad_Opcode },
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 /* 10 */
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
5356 { Bad_Opcode },
5357 { Bad_Opcode },
5358 { Bad_Opcode },
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 /* 18 */
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { Bad_Opcode },
5365 { Bad_Opcode },
5366 { Bad_Opcode },
5367 { Bad_Opcode },
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 /* 20 */
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { Bad_Opcode },
5375 { Bad_Opcode },
5376 { Bad_Opcode },
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 /* 28 */
5380 { Bad_Opcode },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { Bad_Opcode },
5384 { Bad_Opcode },
5385 { Bad_Opcode },
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 /* 30 */
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 { Bad_Opcode },
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 /* 38 */
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { Bad_Opcode },
5402 { Bad_Opcode },
5403 { Bad_Opcode },
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 /* 40 */
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 { Bad_Opcode },
5413 { Bad_Opcode },
5414 { Bad_Opcode },
5415 /* 48 */
5416 { Bad_Opcode },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 { Bad_Opcode },
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 /* 50 */
5425 { Bad_Opcode },
5426 { Bad_Opcode },
5427 { Bad_Opcode },
5428 { Bad_Opcode },
5429 { Bad_Opcode },
5430 { Bad_Opcode },
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 /* 58 */
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 { Bad_Opcode },
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 /* 60 */
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 { Bad_Opcode },
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 /* 68 */
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 { Bad_Opcode },
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 /* 70 */
5461 { Bad_Opcode },
5462 { Bad_Opcode },
5463 { Bad_Opcode },
5464 { Bad_Opcode },
5465 { Bad_Opcode },
5466 { Bad_Opcode },
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 /* 78 */
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 { Bad_Opcode },
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 /* 80 */
5479 { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
5480 { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
5481 { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
5482 { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
5483 { Bad_Opcode },
5484 { Bad_Opcode },
5485 { Bad_Opcode },
5486 { Bad_Opcode },
5487 /* 88 */
5488 { Bad_Opcode },
5489 { Bad_Opcode },
5490 { Bad_Opcode },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 /* 90 */
5497 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
5498 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
5499 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
5500 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
5501 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
5502 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
5503 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
5504 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
5505 /* 98 */
5506 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
5507 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
5508 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
5509 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 /* a0 */
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 /* a8 */
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* b0 */
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 /* b8 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* c0 */
5551 { Bad_Opcode },
5552 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
5553 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
5554 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
5558 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
5559 /* c8 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* d0 */
5569 { Bad_Opcode },
5570 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
5571 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
5572 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
5576 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
5577 /* d8 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* e0 */
5587 { Bad_Opcode },
5588 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
5589 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
5590 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* e8 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* f0 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* f8 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 },
5623 /* XOP_0A */
5624 {
5625 /* 00 */
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 { Bad_Opcode },
5632 { Bad_Opcode },
5633 { Bad_Opcode },
5634 /* 08 */
5635 { Bad_Opcode },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 { Bad_Opcode },
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 /* 10 */
5644 { "bextrS", { Gdq, Edq, Id }, 0 },
5645 { Bad_Opcode },
5646 { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 { Bad_Opcode },
5650 { Bad_Opcode },
5651 { Bad_Opcode },
5652 /* 18 */
5653 { Bad_Opcode },
5654 { Bad_Opcode },
5655 { Bad_Opcode },
5656 { Bad_Opcode },
5657 { Bad_Opcode },
5658 { Bad_Opcode },
5659 { Bad_Opcode },
5660 { Bad_Opcode },
5661 /* 20 */
5662 { Bad_Opcode },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 { Bad_Opcode },
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 /* 28 */
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 { Bad_Opcode },
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 /* 30 */
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 { Bad_Opcode },
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 /* 38 */
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 { Bad_Opcode },
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 /* 40 */
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 { Bad_Opcode },
5704 { Bad_Opcode },
5705 { Bad_Opcode },
5706 /* 48 */
5707 { Bad_Opcode },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { Bad_Opcode },
5711 { Bad_Opcode },
5712 { Bad_Opcode },
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 /* 50 */
5716 { Bad_Opcode },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 { Bad_Opcode },
5722 { Bad_Opcode },
5723 { Bad_Opcode },
5724 /* 58 */
5725 { Bad_Opcode },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { Bad_Opcode },
5729 { Bad_Opcode },
5730 { Bad_Opcode },
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 /* 60 */
5734 { Bad_Opcode },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 { Bad_Opcode },
5740 { Bad_Opcode },
5741 { Bad_Opcode },
5742 /* 68 */
5743 { Bad_Opcode },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 { Bad_Opcode },
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 /* 70 */
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 { Bad_Opcode },
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 /* 78 */
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 { Bad_Opcode },
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 /* 80 */
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 { Bad_Opcode },
5776 { Bad_Opcode },
5777 { Bad_Opcode },
5778 /* 88 */
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 /* 90 */
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 /* 98 */
5797 { Bad_Opcode },
5798 { Bad_Opcode },
5799 { Bad_Opcode },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 /* a0 */
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 /* a8 */
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 /* b0 */
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 /* b8 */
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 /* c0 */
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 /* c8 */
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 /* d0 */
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 /* d8 */
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 /* e0 */
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 /* e8 */
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 /* f0 */
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 /* f8 */
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 },
5914 };
5915
5916 static const struct dis386 vex_table[][256] = {
5917 /* VEX_0F */
5918 {
5919 /* 00 */
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 { Bad_Opcode },
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 /* 08 */
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 { Bad_Opcode },
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 /* 10 */
5938 { PREFIX_TABLE (PREFIX_VEX_0F10) },
5939 { PREFIX_TABLE (PREFIX_VEX_0F11) },
5940 { PREFIX_TABLE (PREFIX_VEX_0F12) },
5941 { MOD_TABLE (MOD_VEX_0F13) },
5942 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5943 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
5944 { PREFIX_TABLE (PREFIX_VEX_0F16) },
5945 { MOD_TABLE (MOD_VEX_0F17) },
5946 /* 18 */
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 { Bad_Opcode },
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 /* 20 */
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 { Bad_Opcode },
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 /* 28 */
5965 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
5966 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
5967 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
5968 { MOD_TABLE (MOD_VEX_0F2B) },
5969 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
5970 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
5971 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
5972 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
5973 /* 30 */
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 { Bad_Opcode },
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 /* 38 */
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 { Bad_Opcode },
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 /* 40 */
5992 { Bad_Opcode },
5993 { VEX_LEN_TABLE (VEX_LEN_0F41) },
5994 { VEX_LEN_TABLE (VEX_LEN_0F42) },
5995 { Bad_Opcode },
5996 { VEX_LEN_TABLE (VEX_LEN_0F44) },
5997 { VEX_LEN_TABLE (VEX_LEN_0F45) },
5998 { VEX_LEN_TABLE (VEX_LEN_0F46) },
5999 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6000 /* 48 */
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6004 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 /* 50 */
6010 { MOD_TABLE (MOD_VEX_0F50) },
6011 { PREFIX_TABLE (PREFIX_VEX_0F51) },
6012 { PREFIX_TABLE (PREFIX_VEX_0F52) },
6013 { PREFIX_TABLE (PREFIX_VEX_0F53) },
6014 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6015 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6016 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6017 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6018 /* 58 */
6019 { PREFIX_TABLE (PREFIX_VEX_0F58) },
6020 { PREFIX_TABLE (PREFIX_VEX_0F59) },
6021 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
6022 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
6023 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
6024 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
6025 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
6026 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
6027 /* 60 */
6028 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6029 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6030 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6031 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6032 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6033 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6034 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6035 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6036 /* 68 */
6037 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6038 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6039 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6040 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6041 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6042 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6043 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6044 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6045 /* 70 */
6046 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6047 { MOD_TABLE (MOD_VEX_0F71) },
6048 { MOD_TABLE (MOD_VEX_0F72) },
6049 { MOD_TABLE (MOD_VEX_0F73) },
6050 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6051 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6052 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6053 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6054 /* 78 */
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 { Bad_Opcode },
6058 { Bad_Opcode },
6059 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
6060 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
6061 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6062 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6063 /* 80 */
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 { Bad_Opcode },
6067 { Bad_Opcode },
6068 { Bad_Opcode },
6069 { Bad_Opcode },
6070 { Bad_Opcode },
6071 { Bad_Opcode },
6072 /* 88 */
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 /* 90 */
6082 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6083 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6084 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6085 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 /* 98 */
6091 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6092 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6093 { Bad_Opcode },
6094 { Bad_Opcode },
6095 { Bad_Opcode },
6096 { Bad_Opcode },
6097 { Bad_Opcode },
6098 { Bad_Opcode },
6099 /* a0 */
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 /* a8 */
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { REG_TABLE (REG_VEX_0FAE) },
6116 { Bad_Opcode },
6117 /* b0 */
6118 { Bad_Opcode },
6119 { Bad_Opcode },
6120 { Bad_Opcode },
6121 { Bad_Opcode },
6122 { Bad_Opcode },
6123 { Bad_Opcode },
6124 { Bad_Opcode },
6125 { Bad_Opcode },
6126 /* b8 */
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 /* c0 */
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
6139 { Bad_Opcode },
6140 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6141 { VEX_LEN_TABLE (VEX_LEN_0FC5) },
6142 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6143 { Bad_Opcode },
6144 /* c8 */
6145 { Bad_Opcode },
6146 { Bad_Opcode },
6147 { Bad_Opcode },
6148 { Bad_Opcode },
6149 { Bad_Opcode },
6150 { Bad_Opcode },
6151 { Bad_Opcode },
6152 { Bad_Opcode },
6153 /* d0 */
6154 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
6155 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6156 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6157 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6158 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6159 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6160 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6161 { MOD_TABLE (MOD_VEX_0FD7) },
6162 /* d8 */
6163 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6164 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6165 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6166 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6167 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6168 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6169 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6170 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6171 /* e0 */
6172 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6173 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6174 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6175 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6176 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6177 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6178 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
6179 { MOD_TABLE (MOD_VEX_0FE7) },
6180 /* e8 */
6181 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6182 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6183 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6184 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6185 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6186 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6187 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6188 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6189 /* f0 */
6190 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
6191 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6192 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6193 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6194 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6196 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6197 { VEX_LEN_TABLE (VEX_LEN_0FF7) },
6198 /* f8 */
6199 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6200 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6201 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6202 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6203 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6204 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6205 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6206 { Bad_Opcode },
6207 },
6208 /* VEX_0F38 */
6209 {
6210 /* 00 */
6211 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6212 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6213 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6214 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6215 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6216 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6217 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6218 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6219 /* 08 */
6220 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6221 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6222 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6223 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6224 { VEX_W_TABLE (VEX_W_0F380C) },
6225 { VEX_W_TABLE (VEX_W_0F380D) },
6226 { VEX_W_TABLE (VEX_W_0F380E) },
6227 { VEX_W_TABLE (VEX_W_0F380F) },
6228 /* 10 */
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { VEX_W_TABLE (VEX_W_0F3813) },
6233 { Bad_Opcode },
6234 { Bad_Opcode },
6235 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6236 { "vptest", { XM, EXx }, PREFIX_DATA },
6237 /* 18 */
6238 { VEX_W_TABLE (VEX_W_0F3818) },
6239 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6240 { MOD_TABLE (MOD_VEX_0F381A) },
6241 { Bad_Opcode },
6242 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6243 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6244 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6245 { Bad_Opcode },
6246 /* 20 */
6247 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6248 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6249 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6250 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6251 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6252 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6253 { Bad_Opcode },
6254 { Bad_Opcode },
6255 /* 28 */
6256 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6257 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6258 { MOD_TABLE (MOD_VEX_0F382A) },
6259 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6260 { MOD_TABLE (MOD_VEX_0F382C) },
6261 { MOD_TABLE (MOD_VEX_0F382D) },
6262 { MOD_TABLE (MOD_VEX_0F382E) },
6263 { MOD_TABLE (MOD_VEX_0F382F) },
6264 /* 30 */
6265 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6266 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6267 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6268 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6269 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6270 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6271 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6272 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6273 /* 38 */
6274 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6275 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6276 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6277 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6278 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6279 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6280 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6281 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6282 /* 40 */
6283 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6284 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6289 { VEX_W_TABLE (VEX_W_0F3846) },
6290 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6291 /* 48 */
6292 { Bad_Opcode },
6293 { X86_64_TABLE (X86_64_VEX_0F3849) },
6294 { Bad_Opcode },
6295 { X86_64_TABLE (X86_64_VEX_0F384B) },
6296 { Bad_Opcode },
6297 { Bad_Opcode },
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 /* 50 */
6301 { VEX_W_TABLE (VEX_W_0F3850) },
6302 { VEX_W_TABLE (VEX_W_0F3851) },
6303 { VEX_W_TABLE (VEX_W_0F3852) },
6304 { VEX_W_TABLE (VEX_W_0F3853) },
6305 { Bad_Opcode },
6306 { Bad_Opcode },
6307 { Bad_Opcode },
6308 { Bad_Opcode },
6309 /* 58 */
6310 { VEX_W_TABLE (VEX_W_0F3858) },
6311 { VEX_W_TABLE (VEX_W_0F3859) },
6312 { MOD_TABLE (MOD_VEX_0F385A) },
6313 { Bad_Opcode },
6314 { X86_64_TABLE (X86_64_VEX_0F385C) },
6315 { Bad_Opcode },
6316 { X86_64_TABLE (X86_64_VEX_0F385E) },
6317 { Bad_Opcode },
6318 /* 60 */
6319 { Bad_Opcode },
6320 { Bad_Opcode },
6321 { Bad_Opcode },
6322 { Bad_Opcode },
6323 { Bad_Opcode },
6324 { Bad_Opcode },
6325 { Bad_Opcode },
6326 { Bad_Opcode },
6327 /* 68 */
6328 { Bad_Opcode },
6329 { Bad_Opcode },
6330 { Bad_Opcode },
6331 { Bad_Opcode },
6332 { Bad_Opcode },
6333 { Bad_Opcode },
6334 { Bad_Opcode },
6335 { Bad_Opcode },
6336 /* 70 */
6337 { Bad_Opcode },
6338 { Bad_Opcode },
6339 { Bad_Opcode },
6340 { Bad_Opcode },
6341 { Bad_Opcode },
6342 { Bad_Opcode },
6343 { Bad_Opcode },
6344 { Bad_Opcode },
6345 /* 78 */
6346 { VEX_W_TABLE (VEX_W_0F3878) },
6347 { VEX_W_TABLE (VEX_W_0F3879) },
6348 { Bad_Opcode },
6349 { Bad_Opcode },
6350 { Bad_Opcode },
6351 { Bad_Opcode },
6352 { Bad_Opcode },
6353 { Bad_Opcode },
6354 /* 80 */
6355 { Bad_Opcode },
6356 { Bad_Opcode },
6357 { Bad_Opcode },
6358 { Bad_Opcode },
6359 { Bad_Opcode },
6360 { Bad_Opcode },
6361 { Bad_Opcode },
6362 { Bad_Opcode },
6363 /* 88 */
6364 { Bad_Opcode },
6365 { Bad_Opcode },
6366 { Bad_Opcode },
6367 { Bad_Opcode },
6368 { MOD_TABLE (MOD_VEX_0F388C) },
6369 { Bad_Opcode },
6370 { MOD_TABLE (MOD_VEX_0F388E) },
6371 { Bad_Opcode },
6372 /* 90 */
6373 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6374 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6375 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
6376 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6377 { Bad_Opcode },
6378 { Bad_Opcode },
6379 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6380 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6381 /* 98 */
6382 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6383 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6384 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6385 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6386 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6387 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6388 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6389 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6390 /* a0 */
6391 { Bad_Opcode },
6392 { Bad_Opcode },
6393 { Bad_Opcode },
6394 { Bad_Opcode },
6395 { Bad_Opcode },
6396 { Bad_Opcode },
6397 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6398 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6399 /* a8 */
6400 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6401 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6402 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6403 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6404 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6405 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6406 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6407 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6408 /* b0 */
6409 { Bad_Opcode },
6410 { Bad_Opcode },
6411 { Bad_Opcode },
6412 { Bad_Opcode },
6413 { Bad_Opcode },
6414 { Bad_Opcode },
6415 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6416 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6417 /* b8 */
6418 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6419 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6420 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6421 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6422 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6423 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6424 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6425 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
6426 /* c0 */
6427 { Bad_Opcode },
6428 { Bad_Opcode },
6429 { Bad_Opcode },
6430 { Bad_Opcode },
6431 { Bad_Opcode },
6432 { Bad_Opcode },
6433 { Bad_Opcode },
6434 { Bad_Opcode },
6435 /* c8 */
6436 { Bad_Opcode },
6437 { Bad_Opcode },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { Bad_Opcode },
6442 { Bad_Opcode },
6443 { VEX_W_TABLE (VEX_W_0F38CF) },
6444 /* d0 */
6445 { Bad_Opcode },
6446 { Bad_Opcode },
6447 { Bad_Opcode },
6448 { Bad_Opcode },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 /* d8 */
6454 { Bad_Opcode },
6455 { Bad_Opcode },
6456 { Bad_Opcode },
6457 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6458 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6459 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6460 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6461 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6462 /* e0 */
6463 { Bad_Opcode },
6464 { Bad_Opcode },
6465 { Bad_Opcode },
6466 { Bad_Opcode },
6467 { Bad_Opcode },
6468 { Bad_Opcode },
6469 { Bad_Opcode },
6470 { Bad_Opcode },
6471 /* e8 */
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 /* f0 */
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6484 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6485 { Bad_Opcode },
6486 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6487 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6488 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6489 /* f8 */
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { Bad_Opcode },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 },
6499 /* VEX_0F3A */
6500 {
6501 /* 00 */
6502 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6504 { VEX_W_TABLE (VEX_W_0F3A02) },
6505 { Bad_Opcode },
6506 { VEX_W_TABLE (VEX_W_0F3A04) },
6507 { VEX_W_TABLE (VEX_W_0F3A05) },
6508 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6509 { Bad_Opcode },
6510 /* 08 */
6511 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6512 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6513 { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
6514 { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
6515 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6516 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6517 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6518 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6519 /* 10 */
6520 { Bad_Opcode },
6521 { Bad_Opcode },
6522 { Bad_Opcode },
6523 { Bad_Opcode },
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6525 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6526 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6527 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6528 /* 18 */
6529 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6530 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6531 { Bad_Opcode },
6532 { Bad_Opcode },
6533 { Bad_Opcode },
6534 { VEX_W_TABLE (VEX_W_0F3A1D) },
6535 { Bad_Opcode },
6536 { Bad_Opcode },
6537 /* 20 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6539 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6540 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6541 { Bad_Opcode },
6542 { Bad_Opcode },
6543 { Bad_Opcode },
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 /* 28 */
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { Bad_Opcode },
6551 { Bad_Opcode },
6552 { Bad_Opcode },
6553 { Bad_Opcode },
6554 { Bad_Opcode },
6555 /* 30 */
6556 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6558 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6560 { Bad_Opcode },
6561 { Bad_Opcode },
6562 { Bad_Opcode },
6563 { Bad_Opcode },
6564 /* 38 */
6565 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6566 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6567 { Bad_Opcode },
6568 { Bad_Opcode },
6569 { Bad_Opcode },
6570 { Bad_Opcode },
6571 { Bad_Opcode },
6572 { Bad_Opcode },
6573 /* 40 */
6574 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6575 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6576 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6577 { Bad_Opcode },
6578 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6579 { Bad_Opcode },
6580 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6581 { Bad_Opcode },
6582 /* 48 */
6583 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6584 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6585 { VEX_W_TABLE (VEX_W_0F3A4A) },
6586 { VEX_W_TABLE (VEX_W_0F3A4B) },
6587 { VEX_W_TABLE (VEX_W_0F3A4C) },
6588 { Bad_Opcode },
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 /* 50 */
6592 { Bad_Opcode },
6593 { Bad_Opcode },
6594 { Bad_Opcode },
6595 { Bad_Opcode },
6596 { Bad_Opcode },
6597 { Bad_Opcode },
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 /* 58 */
6601 { Bad_Opcode },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6606 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6607 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6608 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6609 /* 60 */
6610 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6612 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6614 { Bad_Opcode },
6615 { Bad_Opcode },
6616 { Bad_Opcode },
6617 { Bad_Opcode },
6618 /* 68 */
6619 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6620 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6621 { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6622 { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6623 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6624 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6625 { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6626 { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6627 /* 70 */
6628 { Bad_Opcode },
6629 { Bad_Opcode },
6630 { Bad_Opcode },
6631 { Bad_Opcode },
6632 { Bad_Opcode },
6633 { Bad_Opcode },
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 /* 78 */
6637 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6638 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6639 { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6640 { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6641 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6642 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6643 { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
6644 { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
6645 /* 80 */
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 { Bad_Opcode },
6652 { Bad_Opcode },
6653 { Bad_Opcode },
6654 /* 88 */
6655 { Bad_Opcode },
6656 { Bad_Opcode },
6657 { Bad_Opcode },
6658 { Bad_Opcode },
6659 { Bad_Opcode },
6660 { Bad_Opcode },
6661 { Bad_Opcode },
6662 { Bad_Opcode },
6663 /* 90 */
6664 { Bad_Opcode },
6665 { Bad_Opcode },
6666 { Bad_Opcode },
6667 { Bad_Opcode },
6668 { Bad_Opcode },
6669 { Bad_Opcode },
6670 { Bad_Opcode },
6671 { Bad_Opcode },
6672 /* 98 */
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { Bad_Opcode },
6678 { Bad_Opcode },
6679 { Bad_Opcode },
6680 { Bad_Opcode },
6681 /* a0 */
6682 { Bad_Opcode },
6683 { Bad_Opcode },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { Bad_Opcode },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 /* a8 */
6691 { Bad_Opcode },
6692 { Bad_Opcode },
6693 { Bad_Opcode },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 /* b0 */
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 /* b8 */
6709 { Bad_Opcode },
6710 { Bad_Opcode },
6711 { Bad_Opcode },
6712 { Bad_Opcode },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 /* c0 */
6718 { Bad_Opcode },
6719 { Bad_Opcode },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 /* c8 */
6727 { Bad_Opcode },
6728 { Bad_Opcode },
6729 { Bad_Opcode },
6730 { Bad_Opcode },
6731 { Bad_Opcode },
6732 { Bad_Opcode },
6733 { VEX_W_TABLE (VEX_W_0F3ACE) },
6734 { VEX_W_TABLE (VEX_W_0F3ACF) },
6735 /* d0 */
6736 { Bad_Opcode },
6737 { Bad_Opcode },
6738 { Bad_Opcode },
6739 { Bad_Opcode },
6740 { Bad_Opcode },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 /* d8 */
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6753 /* e0 */
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { Bad_Opcode },
6759 { Bad_Opcode },
6760 { Bad_Opcode },
6761 { Bad_Opcode },
6762 /* e8 */
6763 { Bad_Opcode },
6764 { Bad_Opcode },
6765 { Bad_Opcode },
6766 { Bad_Opcode },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 /* f0 */
6772 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6773 { Bad_Opcode },
6774 { Bad_Opcode },
6775 { Bad_Opcode },
6776 { Bad_Opcode },
6777 { Bad_Opcode },
6778 { Bad_Opcode },
6779 { Bad_Opcode },
6780 /* f8 */
6781 { Bad_Opcode },
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 },
6790 };
6791
6792 #include "i386-dis-evex.h"
6793
6794 static const struct dis386 vex_len_table[][2] = {
6795 /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
6796 {
6797 { "vmovlpX", { XM, Vex, EXq }, 0 },
6798 },
6799
6800 /* VEX_LEN_0F12_P_0_M_1 */
6801 {
6802 { "vmovhlps", { XM, Vex, EXq }, 0 },
6803 },
6804
6805 /* VEX_LEN_0F13_M_0 */
6806 {
6807 { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
6808 },
6809
6810 /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
6811 {
6812 { "vmovhpX", { XM, Vex, EXq }, 0 },
6813 },
6814
6815 /* VEX_LEN_0F16_P_0_M_1 */
6816 {
6817 { "vmovlhps", { XM, Vex, EXq }, 0 },
6818 },
6819
6820 /* VEX_LEN_0F17_M_0 */
6821 {
6822 { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
6823 },
6824
6825 /* VEX_LEN_0F41 */
6826 {
6827 { Bad_Opcode },
6828 { MOD_TABLE (MOD_VEX_0F41_L_1) },
6829 },
6830
6831 /* VEX_LEN_0F42 */
6832 {
6833 { Bad_Opcode },
6834 { MOD_TABLE (MOD_VEX_0F42_L_1) },
6835 },
6836
6837 /* VEX_LEN_0F44 */
6838 {
6839 { MOD_TABLE (MOD_VEX_0F44_L_0) },
6840 },
6841
6842 /* VEX_LEN_0F45 */
6843 {
6844 { Bad_Opcode },
6845 { MOD_TABLE (MOD_VEX_0F45_L_1) },
6846 },
6847
6848 /* VEX_LEN_0F46 */
6849 {
6850 { Bad_Opcode },
6851 { MOD_TABLE (MOD_VEX_0F46_L_1) },
6852 },
6853
6854 /* VEX_LEN_0F47 */
6855 {
6856 { Bad_Opcode },
6857 { MOD_TABLE (MOD_VEX_0F47_L_1) },
6858 },
6859
6860 /* VEX_LEN_0F4A */
6861 {
6862 { Bad_Opcode },
6863 { MOD_TABLE (MOD_VEX_0F4A_L_1) },
6864 },
6865
6866 /* VEX_LEN_0F4B */
6867 {
6868 { Bad_Opcode },
6869 { MOD_TABLE (MOD_VEX_0F4B_L_1) },
6870 },
6871
6872 /* VEX_LEN_0F6E */
6873 {
6874 { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
6875 },
6876
6877 /* VEX_LEN_0F77 */
6878 {
6879 { "vzeroupper", { XX }, 0 },
6880 { "vzeroall", { XX }, 0 },
6881 },
6882
6883 /* VEX_LEN_0F7E_P_1 */
6884 {
6885 { "vmovq", { XMScalar, EXxmm_mq }, 0 },
6886 },
6887
6888 /* VEX_LEN_0F7E_P_2 */
6889 {
6890 { "vmovK", { Edq, XMScalar }, 0 },
6891 },
6892
6893 /* VEX_LEN_0F90 */
6894 {
6895 { VEX_W_TABLE (VEX_W_0F90_L_0) },
6896 },
6897
6898 /* VEX_LEN_0F91 */
6899 {
6900 { MOD_TABLE (MOD_VEX_0F91_L_0) },
6901 },
6902
6903 /* VEX_LEN_0F92 */
6904 {
6905 { MOD_TABLE (MOD_VEX_0F92_L_0) },
6906 },
6907
6908 /* VEX_LEN_0F93 */
6909 {
6910 { MOD_TABLE (MOD_VEX_0F93_L_0) },
6911 },
6912
6913 /* VEX_LEN_0F98 */
6914 {
6915 { MOD_TABLE (MOD_VEX_0F98_L_0) },
6916 },
6917
6918 /* VEX_LEN_0F99 */
6919 {
6920 { MOD_TABLE (MOD_VEX_0F99_L_0) },
6921 },
6922
6923 /* VEX_LEN_0FAE_R_2_M_0 */
6924 {
6925 { "vldmxcsr", { Md }, 0 },
6926 },
6927
6928 /* VEX_LEN_0FAE_R_3_M_0 */
6929 {
6930 { "vstmxcsr", { Md }, 0 },
6931 },
6932
6933 /* VEX_LEN_0FC4 */
6934 {
6935 { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
6936 },
6937
6938 /* VEX_LEN_0FC5 */
6939 {
6940 { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
6941 },
6942
6943 /* VEX_LEN_0FD6 */
6944 {
6945 { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
6946 },
6947
6948 /* VEX_LEN_0FF7 */
6949 {
6950 { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
6951 },
6952
6953 /* VEX_LEN_0F3816 */
6954 {
6955 { Bad_Opcode },
6956 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
6957 },
6958
6959 /* VEX_LEN_0F3819 */
6960 {
6961 { Bad_Opcode },
6962 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
6963 },
6964
6965 /* VEX_LEN_0F381A_M_0 */
6966 {
6967 { Bad_Opcode },
6968 { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
6969 },
6970
6971 /* VEX_LEN_0F3836 */
6972 {
6973 { Bad_Opcode },
6974 { VEX_W_TABLE (VEX_W_0F3836) },
6975 },
6976
6977 /* VEX_LEN_0F3841 */
6978 {
6979 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
6980 },
6981
6982 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
6983 {
6984 { "ldtilecfg", { M }, 0 },
6985 },
6986
6987 /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
6988 {
6989 { "tilerelease", { Skip_MODRM }, 0 },
6990 },
6991
6992 /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
6993 {
6994 { "sttilecfg", { M }, 0 },
6995 },
6996
6997 /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
6998 {
6999 { "tilezero", { TMM, Skip_MODRM }, 0 },
7000 },
7001
7002 /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
7003 {
7004 { "tilestored", { MVexSIBMEM, TMM }, 0 },
7005 },
7006 /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
7007 {
7008 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
7009 },
7010
7011 /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
7012 {
7013 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
7014 },
7015
7016 /* VEX_LEN_0F385A_M_0 */
7017 {
7018 { Bad_Opcode },
7019 { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
7020 },
7021
7022 /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
7023 {
7024 { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
7025 },
7026
7027 /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
7028 {
7029 { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
7030 },
7031
7032 /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
7033 {
7034 { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
7035 },
7036
7037 /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
7038 {
7039 { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
7040 },
7041
7042 /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
7043 {
7044 { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
7045 },
7046
7047 /* VEX_LEN_0F38DB */
7048 {
7049 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7050 },
7051
7052 /* VEX_LEN_0F38F2 */
7053 {
7054 { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
7055 },
7056
7057 /* VEX_LEN_0F38F3 */
7058 {
7059 { REG_TABLE(REG_VEX_0F38F3_L_0) },
7060 },
7061
7062 /* VEX_LEN_0F38F5 */
7063 {
7064 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7065 },
7066
7067 /* VEX_LEN_0F38F6 */
7068 {
7069 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7070 },
7071
7072 /* VEX_LEN_0F38F7 */
7073 {
7074 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7075 },
7076
7077 /* VEX_LEN_0F3A00 */
7078 {
7079 { Bad_Opcode },
7080 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7081 },
7082
7083 /* VEX_LEN_0F3A01 */
7084 {
7085 { Bad_Opcode },
7086 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7087 },
7088
7089 /* VEX_LEN_0F3A06 */
7090 {
7091 { Bad_Opcode },
7092 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7093 },
7094
7095 /* VEX_LEN_0F3A14 */
7096 {
7097 { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
7098 },
7099
7100 /* VEX_LEN_0F3A15 */
7101 {
7102 { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
7103 },
7104
7105 /* VEX_LEN_0F3A16 */
7106 {
7107 { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7108 },
7109
7110 /* VEX_LEN_0F3A17 */
7111 {
7112 { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
7113 },
7114
7115 /* VEX_LEN_0F3A18 */
7116 {
7117 { Bad_Opcode },
7118 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7119 },
7120
7121 /* VEX_LEN_0F3A19 */
7122 {
7123 { Bad_Opcode },
7124 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7125 },
7126
7127 /* VEX_LEN_0F3A20 */
7128 {
7129 { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
7130 },
7131
7132 /* VEX_LEN_0F3A21 */
7133 {
7134 { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7135 },
7136
7137 /* VEX_LEN_0F3A22 */
7138 {
7139 { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7140 },
7141
7142 /* VEX_LEN_0F3A30 */
7143 {
7144 { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
7145 },
7146
7147 /* VEX_LEN_0F3A31 */
7148 {
7149 { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
7150 },
7151
7152 /* VEX_LEN_0F3A32 */
7153 {
7154 { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
7155 },
7156
7157 /* VEX_LEN_0F3A33 */
7158 {
7159 { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
7160 },
7161
7162 /* VEX_LEN_0F3A38 */
7163 {
7164 { Bad_Opcode },
7165 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7166 },
7167
7168 /* VEX_LEN_0F3A39 */
7169 {
7170 { Bad_Opcode },
7171 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7172 },
7173
7174 /* VEX_LEN_0F3A41 */
7175 {
7176 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7177 },
7178
7179 /* VEX_LEN_0F3A46 */
7180 {
7181 { Bad_Opcode },
7182 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7183 },
7184
7185 /* VEX_LEN_0F3A60 */
7186 {
7187 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7188 },
7189
7190 /* VEX_LEN_0F3A61 */
7191 {
7192 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7193 },
7194
7195 /* VEX_LEN_0F3A62 */
7196 {
7197 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7198 },
7199
7200 /* VEX_LEN_0F3A63 */
7201 {
7202 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7203 },
7204
7205 /* VEX_LEN_0F3ADF */
7206 {
7207 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7208 },
7209
7210 /* VEX_LEN_0F3AF0 */
7211 {
7212 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7213 },
7214
7215 /* VEX_LEN_0FXOP_08_85 */
7216 {
7217 { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
7218 },
7219
7220 /* VEX_LEN_0FXOP_08_86 */
7221 {
7222 { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
7223 },
7224
7225 /* VEX_LEN_0FXOP_08_87 */
7226 {
7227 { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
7228 },
7229
7230 /* VEX_LEN_0FXOP_08_8E */
7231 {
7232 { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
7233 },
7234
7235 /* VEX_LEN_0FXOP_08_8F */
7236 {
7237 { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
7238 },
7239
7240 /* VEX_LEN_0FXOP_08_95 */
7241 {
7242 { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
7243 },
7244
7245 /* VEX_LEN_0FXOP_08_96 */
7246 {
7247 { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
7248 },
7249
7250 /* VEX_LEN_0FXOP_08_97 */
7251 {
7252 { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
7253 },
7254
7255 /* VEX_LEN_0FXOP_08_9E */
7256 {
7257 { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
7258 },
7259
7260 /* VEX_LEN_0FXOP_08_9F */
7261 {
7262 { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
7263 },
7264
7265 /* VEX_LEN_0FXOP_08_A3 */
7266 {
7267 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7268 },
7269
7270 /* VEX_LEN_0FXOP_08_A6 */
7271 {
7272 { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
7273 },
7274
7275 /* VEX_LEN_0FXOP_08_B6 */
7276 {
7277 { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
7278 },
7279
7280 /* VEX_LEN_0FXOP_08_C0 */
7281 {
7282 { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
7283 },
7284
7285 /* VEX_LEN_0FXOP_08_C1 */
7286 {
7287 { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
7288 },
7289
7290 /* VEX_LEN_0FXOP_08_C2 */
7291 {
7292 { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
7293 },
7294
7295 /* VEX_LEN_0FXOP_08_C3 */
7296 {
7297 { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
7298 },
7299
7300 /* VEX_LEN_0FXOP_08_CC */
7301 {
7302 { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
7303 },
7304
7305 /* VEX_LEN_0FXOP_08_CD */
7306 {
7307 { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
7308 },
7309
7310 /* VEX_LEN_0FXOP_08_CE */
7311 {
7312 { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
7313 },
7314
7315 /* VEX_LEN_0FXOP_08_CF */
7316 {
7317 { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
7318 },
7319
7320 /* VEX_LEN_0FXOP_08_EC */
7321 {
7322 { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
7323 },
7324
7325 /* VEX_LEN_0FXOP_08_ED */
7326 {
7327 { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
7328 },
7329
7330 /* VEX_LEN_0FXOP_08_EE */
7331 {
7332 { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
7333 },
7334
7335 /* VEX_LEN_0FXOP_08_EF */
7336 {
7337 { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
7338 },
7339
7340 /* VEX_LEN_0FXOP_09_01 */
7341 {
7342 { REG_TABLE (REG_0FXOP_09_01_L_0) },
7343 },
7344
7345 /* VEX_LEN_0FXOP_09_02 */
7346 {
7347 { REG_TABLE (REG_0FXOP_09_02_L_0) },
7348 },
7349
7350 /* VEX_LEN_0FXOP_09_12_M_1 */
7351 {
7352 { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
7353 },
7354
7355 /* VEX_LEN_0FXOP_09_82_W_0 */
7356 {
7357 { "vfrczss", { XM, EXd }, 0 },
7358 },
7359
7360 /* VEX_LEN_0FXOP_09_83_W_0 */
7361 {
7362 { "vfrczsd", { XM, EXq }, 0 },
7363 },
7364
7365 /* VEX_LEN_0FXOP_09_90 */
7366 {
7367 { "vprotb", { XM, EXx, VexW }, 0 },
7368 },
7369
7370 /* VEX_LEN_0FXOP_09_91 */
7371 {
7372 { "vprotw", { XM, EXx, VexW }, 0 },
7373 },
7374
7375 /* VEX_LEN_0FXOP_09_92 */
7376 {
7377 { "vprotd", { XM, EXx, VexW }, 0 },
7378 },
7379
7380 /* VEX_LEN_0FXOP_09_93 */
7381 {
7382 { "vprotq", { XM, EXx, VexW }, 0 },
7383 },
7384
7385 /* VEX_LEN_0FXOP_09_94 */
7386 {
7387 { "vpshlb", { XM, EXx, VexW }, 0 },
7388 },
7389
7390 /* VEX_LEN_0FXOP_09_95 */
7391 {
7392 { "vpshlw", { XM, EXx, VexW }, 0 },
7393 },
7394
7395 /* VEX_LEN_0FXOP_09_96 */
7396 {
7397 { "vpshld", { XM, EXx, VexW }, 0 },
7398 },
7399
7400 /* VEX_LEN_0FXOP_09_97 */
7401 {
7402 { "vpshlq", { XM, EXx, VexW }, 0 },
7403 },
7404
7405 /* VEX_LEN_0FXOP_09_98 */
7406 {
7407 { "vpshab", { XM, EXx, VexW }, 0 },
7408 },
7409
7410 /* VEX_LEN_0FXOP_09_99 */
7411 {
7412 { "vpshaw", { XM, EXx, VexW }, 0 },
7413 },
7414
7415 /* VEX_LEN_0FXOP_09_9A */
7416 {
7417 { "vpshad", { XM, EXx, VexW }, 0 },
7418 },
7419
7420 /* VEX_LEN_0FXOP_09_9B */
7421 {
7422 { "vpshaq", { XM, EXx, VexW }, 0 },
7423 },
7424
7425 /* VEX_LEN_0FXOP_09_C1 */
7426 {
7427 { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
7428 },
7429
7430 /* VEX_LEN_0FXOP_09_C2 */
7431 {
7432 { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
7433 },
7434
7435 /* VEX_LEN_0FXOP_09_C3 */
7436 {
7437 { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
7438 },
7439
7440 /* VEX_LEN_0FXOP_09_C6 */
7441 {
7442 { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
7443 },
7444
7445 /* VEX_LEN_0FXOP_09_C7 */
7446 {
7447 { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
7448 },
7449
7450 /* VEX_LEN_0FXOP_09_CB */
7451 {
7452 { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
7453 },
7454
7455 /* VEX_LEN_0FXOP_09_D1 */
7456 {
7457 { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
7458 },
7459
7460 /* VEX_LEN_0FXOP_09_D2 */
7461 {
7462 { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
7463 },
7464
7465 /* VEX_LEN_0FXOP_09_D3 */
7466 {
7467 { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
7468 },
7469
7470 /* VEX_LEN_0FXOP_09_D6 */
7471 {
7472 { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
7473 },
7474
7475 /* VEX_LEN_0FXOP_09_D7 */
7476 {
7477 { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
7478 },
7479
7480 /* VEX_LEN_0FXOP_09_DB */
7481 {
7482 { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
7483 },
7484
7485 /* VEX_LEN_0FXOP_09_E1 */
7486 {
7487 { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
7488 },
7489
7490 /* VEX_LEN_0FXOP_09_E2 */
7491 {
7492 { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
7493 },
7494
7495 /* VEX_LEN_0FXOP_09_E3 */
7496 {
7497 { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
7498 },
7499
7500 /* VEX_LEN_0FXOP_0A_12 */
7501 {
7502 { REG_TABLE (REG_0FXOP_0A_12_L_0) },
7503 },
7504 };
7505
7506 #include "i386-dis-evex-len.h"
7507
7508 static const struct dis386 vex_w_table[][2] = {
7509 {
7510 /* VEX_W_0F41_L_1_M_1 */
7511 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_0) },
7512 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_M_1_W_1) },
7513 },
7514 {
7515 /* VEX_W_0F42_L_1_M_1 */
7516 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_0) },
7517 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_M_1_W_1) },
7518 },
7519 {
7520 /* VEX_W_0F44_L_0_M_1 */
7521 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_0) },
7522 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_M_1_W_1) },
7523 },
7524 {
7525 /* VEX_W_0F45_L_1_M_1 */
7526 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_0) },
7527 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_M_1_W_1) },
7528 },
7529 {
7530 /* VEX_W_0F46_L_1_M_1 */
7531 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_0) },
7532 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_M_1_W_1) },
7533 },
7534 {
7535 /* VEX_W_0F47_L_1_M_1 */
7536 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_0) },
7537 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_M_1_W_1) },
7538 },
7539 {
7540 /* VEX_W_0F4A_L_1_M_1 */
7541 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_0) },
7542 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_M_1_W_1) },
7543 },
7544 {
7545 /* VEX_W_0F4B_L_1_M_1 */
7546 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_0) },
7547 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_M_1_W_1) },
7548 },
7549 {
7550 /* VEX_W_0F90_L_0 */
7551 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7552 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7553 },
7554 {
7555 /* VEX_W_0F91_L_0_M_0 */
7556 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_0) },
7557 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_M_0_W_1) },
7558 },
7559 {
7560 /* VEX_W_0F92_L_0_M_1 */
7561 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_0) },
7562 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_M_1_W_1) },
7563 },
7564 {
7565 /* VEX_W_0F93_L_0_M_1 */
7566 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_0) },
7567 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_M_1_W_1) },
7568 },
7569 {
7570 /* VEX_W_0F98_L_0_M_1 */
7571 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_0) },
7572 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_M_1_W_1) },
7573 },
7574 {
7575 /* VEX_W_0F99_L_0_M_1 */
7576 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_0) },
7577 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_M_1_W_1) },
7578 },
7579 {
7580 /* VEX_W_0F380C */
7581 { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7582 },
7583 {
7584 /* VEX_W_0F380D */
7585 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7586 },
7587 {
7588 /* VEX_W_0F380E */
7589 { "vtestps", { XM, EXx }, PREFIX_DATA },
7590 },
7591 {
7592 /* VEX_W_0F380F */
7593 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7594 },
7595 {
7596 /* VEX_W_0F3813 */
7597 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7598 },
7599 {
7600 /* VEX_W_0F3816_L_1 */
7601 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7602 },
7603 {
7604 /* VEX_W_0F3818 */
7605 { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
7606 },
7607 {
7608 /* VEX_W_0F3819_L_1 */
7609 { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
7610 },
7611 {
7612 /* VEX_W_0F381A_M_0_L_1 */
7613 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7614 },
7615 {
7616 /* VEX_W_0F382C_M_0 */
7617 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7618 },
7619 {
7620 /* VEX_W_0F382D_M_0 */
7621 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7622 },
7623 {
7624 /* VEX_W_0F382E_M_0 */
7625 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7626 },
7627 {
7628 /* VEX_W_0F382F_M_0 */
7629 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7630 },
7631 {
7632 /* VEX_W_0F3836 */
7633 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7634 },
7635 {
7636 /* VEX_W_0F3846 */
7637 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7638 },
7639 {
7640 /* VEX_W_0F3849_X86_64_P_0 */
7641 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
7642 },
7643 {
7644 /* VEX_W_0F3849_X86_64_P_2 */
7645 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
7646 },
7647 {
7648 /* VEX_W_0F3849_X86_64_P_3 */
7649 { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
7650 },
7651 {
7652 /* VEX_W_0F384B_X86_64_P_1 */
7653 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
7654 },
7655 {
7656 /* VEX_W_0F384B_X86_64_P_2 */
7657 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
7658 },
7659 {
7660 /* VEX_W_0F384B_X86_64_P_3 */
7661 { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
7662 },
7663 {
7664 /* VEX_W_0F3850 */
7665 { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
7666 },
7667 {
7668 /* VEX_W_0F3851 */
7669 { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
7670 },
7671 {
7672 /* VEX_W_0F3852 */
7673 { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
7674 },
7675 {
7676 /* VEX_W_0F3853 */
7677 { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
7678 },
7679 {
7680 /* VEX_W_0F3858 */
7681 { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
7682 },
7683 {
7684 /* VEX_W_0F3859 */
7685 { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
7686 },
7687 {
7688 /* VEX_W_0F385A_M_0_L_0 */
7689 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7690 },
7691 {
7692 /* VEX_W_0F385C_X86_64_P_1 */
7693 { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
7694 },
7695 {
7696 /* VEX_W_0F385E_X86_64_P_0 */
7697 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
7698 },
7699 {
7700 /* VEX_W_0F385E_X86_64_P_1 */
7701 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
7702 },
7703 {
7704 /* VEX_W_0F385E_X86_64_P_2 */
7705 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
7706 },
7707 {
7708 /* VEX_W_0F385E_X86_64_P_3 */
7709 { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
7710 },
7711 {
7712 /* VEX_W_0F3878 */
7713 { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
7714 },
7715 {
7716 /* VEX_W_0F3879 */
7717 { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
7718 },
7719 {
7720 /* VEX_W_0F38CF */
7721 { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7722 },
7723 {
7724 /* VEX_W_0F3A00_L_1 */
7725 { Bad_Opcode },
7726 { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
7727 },
7728 {
7729 /* VEX_W_0F3A01_L_1 */
7730 { Bad_Opcode },
7731 { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7732 },
7733 {
7734 /* VEX_W_0F3A02 */
7735 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7736 },
7737 {
7738 /* VEX_W_0F3A04 */
7739 { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7740 },
7741 {
7742 /* VEX_W_0F3A05 */
7743 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7744 },
7745 {
7746 /* VEX_W_0F3A06_L_1 */
7747 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7748 },
7749 {
7750 /* VEX_W_0F3A18_L_1 */
7751 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7752 },
7753 {
7754 /* VEX_W_0F3A19_L_1 */
7755 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7756 },
7757 {
7758 /* VEX_W_0F3A1D */
7759 { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7760 },
7761 {
7762 /* VEX_W_0F3A38_L_1 */
7763 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7764 },
7765 {
7766 /* VEX_W_0F3A39_L_1 */
7767 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7768 },
7769 {
7770 /* VEX_W_0F3A46_L_1 */
7771 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7772 },
7773 {
7774 /* VEX_W_0F3A4A */
7775 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7776 },
7777 {
7778 /* VEX_W_0F3A4B */
7779 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7780 },
7781 {
7782 /* VEX_W_0F3A4C */
7783 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7784 },
7785 {
7786 /* VEX_W_0F3ACE */
7787 { Bad_Opcode },
7788 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7789 },
7790 {
7791 /* VEX_W_0F3ACF */
7792 { Bad_Opcode },
7793 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7794 },
7795 /* VEX_W_0FXOP_08_85_L_0 */
7796 {
7797 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7798 },
7799 /* VEX_W_0FXOP_08_86_L_0 */
7800 {
7801 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7802 },
7803 /* VEX_W_0FXOP_08_87_L_0 */
7804 {
7805 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7806 },
7807 /* VEX_W_0FXOP_08_8E_L_0 */
7808 {
7809 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7810 },
7811 /* VEX_W_0FXOP_08_8F_L_0 */
7812 {
7813 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7814 },
7815 /* VEX_W_0FXOP_08_95_L_0 */
7816 {
7817 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7818 },
7819 /* VEX_W_0FXOP_08_96_L_0 */
7820 {
7821 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7822 },
7823 /* VEX_W_0FXOP_08_97_L_0 */
7824 {
7825 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7826 },
7827 /* VEX_W_0FXOP_08_9E_L_0 */
7828 {
7829 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7830 },
7831 /* VEX_W_0FXOP_08_9F_L_0 */
7832 {
7833 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7834 },
7835 /* VEX_W_0FXOP_08_A6_L_0 */
7836 {
7837 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7838 },
7839 /* VEX_W_0FXOP_08_B6_L_0 */
7840 {
7841 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7842 },
7843 /* VEX_W_0FXOP_08_C0_L_0 */
7844 {
7845 { "vprotb", { XM, EXx, Ib }, 0 },
7846 },
7847 /* VEX_W_0FXOP_08_C1_L_0 */
7848 {
7849 { "vprotw", { XM, EXx, Ib }, 0 },
7850 },
7851 /* VEX_W_0FXOP_08_C2_L_0 */
7852 {
7853 { "vprotd", { XM, EXx, Ib }, 0 },
7854 },
7855 /* VEX_W_0FXOP_08_C3_L_0 */
7856 {
7857 { "vprotq", { XM, EXx, Ib }, 0 },
7858 },
7859 /* VEX_W_0FXOP_08_CC_L_0 */
7860 {
7861 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
7862 },
7863 /* VEX_W_0FXOP_08_CD_L_0 */
7864 {
7865 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
7866 },
7867 /* VEX_W_0FXOP_08_CE_L_0 */
7868 {
7869 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
7870 },
7871 /* VEX_W_0FXOP_08_CF_L_0 */
7872 {
7873 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
7874 },
7875 /* VEX_W_0FXOP_08_EC_L_0 */
7876 {
7877 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
7878 },
7879 /* VEX_W_0FXOP_08_ED_L_0 */
7880 {
7881 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
7882 },
7883 /* VEX_W_0FXOP_08_EE_L_0 */
7884 {
7885 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
7886 },
7887 /* VEX_W_0FXOP_08_EF_L_0 */
7888 {
7889 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
7890 },
7891 /* VEX_W_0FXOP_09_80 */
7892 {
7893 { "vfrczps", { XM, EXx }, 0 },
7894 },
7895 /* VEX_W_0FXOP_09_81 */
7896 {
7897 { "vfrczpd", { XM, EXx }, 0 },
7898 },
7899 /* VEX_W_0FXOP_09_82 */
7900 {
7901 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
7902 },
7903 /* VEX_W_0FXOP_09_83 */
7904 {
7905 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
7906 },
7907 /* VEX_W_0FXOP_09_C1_L_0 */
7908 {
7909 { "vphaddbw", { XM, EXxmm }, 0 },
7910 },
7911 /* VEX_W_0FXOP_09_C2_L_0 */
7912 {
7913 { "vphaddbd", { XM, EXxmm }, 0 },
7914 },
7915 /* VEX_W_0FXOP_09_C3_L_0 */
7916 {
7917 { "vphaddbq", { XM, EXxmm }, 0 },
7918 },
7919 /* VEX_W_0FXOP_09_C6_L_0 */
7920 {
7921 { "vphaddwd", { XM, EXxmm }, 0 },
7922 },
7923 /* VEX_W_0FXOP_09_C7_L_0 */
7924 {
7925 { "vphaddwq", { XM, EXxmm }, 0 },
7926 },
7927 /* VEX_W_0FXOP_09_CB_L_0 */
7928 {
7929 { "vphadddq", { XM, EXxmm }, 0 },
7930 },
7931 /* VEX_W_0FXOP_09_D1_L_0 */
7932 {
7933 { "vphaddubw", { XM, EXxmm }, 0 },
7934 },
7935 /* VEX_W_0FXOP_09_D2_L_0 */
7936 {
7937 { "vphaddubd", { XM, EXxmm }, 0 },
7938 },
7939 /* VEX_W_0FXOP_09_D3_L_0 */
7940 {
7941 { "vphaddubq", { XM, EXxmm }, 0 },
7942 },
7943 /* VEX_W_0FXOP_09_D6_L_0 */
7944 {
7945 { "vphadduwd", { XM, EXxmm }, 0 },
7946 },
7947 /* VEX_W_0FXOP_09_D7_L_0 */
7948 {
7949 { "vphadduwq", { XM, EXxmm }, 0 },
7950 },
7951 /* VEX_W_0FXOP_09_DB_L_0 */
7952 {
7953 { "vphaddudq", { XM, EXxmm }, 0 },
7954 },
7955 /* VEX_W_0FXOP_09_E1_L_0 */
7956 {
7957 { "vphsubbw", { XM, EXxmm }, 0 },
7958 },
7959 /* VEX_W_0FXOP_09_E2_L_0 */
7960 {
7961 { "vphsubwd", { XM, EXxmm }, 0 },
7962 },
7963 /* VEX_W_0FXOP_09_E3_L_0 */
7964 {
7965 { "vphsubdq", { XM, EXxmm }, 0 },
7966 },
7967
7968 #include "i386-dis-evex-w.h"
7969 };
7970
7971 static const struct dis386 mod_table[][2] = {
7972 {
7973 /* MOD_8D */
7974 { "leaS", { Gv, M }, 0 },
7975 },
7976 {
7977 /* MOD_C6_REG_7 */
7978 { Bad_Opcode },
7979 { RM_TABLE (RM_C6_REG_7) },
7980 },
7981 {
7982 /* MOD_C7_REG_7 */
7983 { Bad_Opcode },
7984 { RM_TABLE (RM_C7_REG_7) },
7985 },
7986 {
7987 /* MOD_FF_REG_3 */
7988 { "{l|}call^", { indirEp }, 0 },
7989 },
7990 {
7991 /* MOD_FF_REG_5 */
7992 { "{l|}jmp^", { indirEp }, 0 },
7993 },
7994 {
7995 /* MOD_0F01_REG_0 */
7996 { X86_64_TABLE (X86_64_0F01_REG_0) },
7997 { RM_TABLE (RM_0F01_REG_0) },
7998 },
7999 {
8000 /* MOD_0F01_REG_1 */
8001 { X86_64_TABLE (X86_64_0F01_REG_1) },
8002 { RM_TABLE (RM_0F01_REG_1) },
8003 },
8004 {
8005 /* MOD_0F01_REG_2 */
8006 { X86_64_TABLE (X86_64_0F01_REG_2) },
8007 { RM_TABLE (RM_0F01_REG_2) },
8008 },
8009 {
8010 /* MOD_0F01_REG_3 */
8011 { X86_64_TABLE (X86_64_0F01_REG_3) },
8012 { RM_TABLE (RM_0F01_REG_3) },
8013 },
8014 {
8015 /* MOD_0F01_REG_5 */
8016 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8017 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8018 },
8019 {
8020 /* MOD_0F01_REG_7 */
8021 { "invlpg", { Mb }, 0 },
8022 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8023 },
8024 {
8025 /* MOD_0F12_PREFIX_0 */
8026 { "movlpX", { XM, EXq }, 0 },
8027 { "movhlps", { XM, EXq }, 0 },
8028 },
8029 {
8030 /* MOD_0F12_PREFIX_2 */
8031 { "movlpX", { XM, EXq }, 0 },
8032 },
8033 {
8034 /* MOD_0F13 */
8035 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
8036 },
8037 {
8038 /* MOD_0F16_PREFIX_0 */
8039 { "movhpX", { XM, EXq }, 0 },
8040 { "movlhps", { XM, EXq }, 0 },
8041 },
8042 {
8043 /* MOD_0F16_PREFIX_2 */
8044 { "movhpX", { XM, EXq }, 0 },
8045 },
8046 {
8047 /* MOD_0F17 */
8048 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
8049 },
8050 {
8051 /* MOD_0F18_REG_0 */
8052 { "prefetchnta", { Mb }, 0 },
8053 { "nopQ", { Ev }, 0 },
8054 },
8055 {
8056 /* MOD_0F18_REG_1 */
8057 { "prefetcht0", { Mb }, 0 },
8058 { "nopQ", { Ev }, 0 },
8059 },
8060 {
8061 /* MOD_0F18_REG_2 */
8062 { "prefetcht1", { Mb }, 0 },
8063 { "nopQ", { Ev }, 0 },
8064 },
8065 {
8066 /* MOD_0F18_REG_3 */
8067 { "prefetcht2", { Mb }, 0 },
8068 { "nopQ", { Ev }, 0 },
8069 },
8070 {
8071 /* MOD_0F1A_PREFIX_0 */
8072 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8073 { "nopQ", { Ev }, 0 },
8074 },
8075 {
8076 /* MOD_0F1B_PREFIX_0 */
8077 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8078 { "nopQ", { Ev }, 0 },
8079 },
8080 {
8081 /* MOD_0F1B_PREFIX_1 */
8082 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8083 { "nopQ", { Ev }, PREFIX_IGNORED },
8084 },
8085 {
8086 /* MOD_0F1C_PREFIX_0 */
8087 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8088 { "nopQ", { Ev }, 0 },
8089 },
8090 {
8091 /* MOD_0F1E_PREFIX_1 */
8092 { "nopQ", { Ev }, PREFIX_IGNORED },
8093 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8094 },
8095 {
8096 /* MOD_0F2B_PREFIX_0 */
8097 {"movntps", { Mx, XM }, PREFIX_OPCODE },
8098 },
8099 {
8100 /* MOD_0F2B_PREFIX_1 */
8101 {"movntss", { Md, XM }, PREFIX_OPCODE },
8102 },
8103 {
8104 /* MOD_0F2B_PREFIX_2 */
8105 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
8106 },
8107 {
8108 /* MOD_0F2B_PREFIX_3 */
8109 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
8110 },
8111 {
8112 /* MOD_0F50 */
8113 { Bad_Opcode },
8114 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
8115 },
8116 {
8117 /* MOD_0F71 */
8118 { Bad_Opcode },
8119 { REG_TABLE (REG_0F71_MOD_0) },
8120 },
8121 {
8122 /* MOD_0F72 */
8123 { Bad_Opcode },
8124 { REG_TABLE (REG_0F72_MOD_0) },
8125 },
8126 {
8127 /* MOD_0F73 */
8128 { Bad_Opcode },
8129 { REG_TABLE (REG_0F73_MOD_0) },
8130 },
8131 {
8132 /* MOD_0FAE_REG_0 */
8133 { "fxsave", { FXSAVE }, 0 },
8134 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8135 },
8136 {
8137 /* MOD_0FAE_REG_1 */
8138 { "fxrstor", { FXSAVE }, 0 },
8139 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8140 },
8141 {
8142 /* MOD_0FAE_REG_2 */
8143 { "ldmxcsr", { Md }, 0 },
8144 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8145 },
8146 {
8147 /* MOD_0FAE_REG_3 */
8148 { "stmxcsr", { Md }, 0 },
8149 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8150 },
8151 {
8152 /* MOD_0FAE_REG_4 */
8153 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8154 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8155 },
8156 {
8157 /* MOD_0FAE_REG_5 */
8158 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
8159 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8160 },
8161 {
8162 /* MOD_0FAE_REG_6 */
8163 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8164 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8165 },
8166 {
8167 /* MOD_0FAE_REG_7 */
8168 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8169 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8170 },
8171 {
8172 /* MOD_0FB2 */
8173 { "lssS", { Gv, Mp }, 0 },
8174 },
8175 {
8176 /* MOD_0FB4 */
8177 { "lfsS", { Gv, Mp }, 0 },
8178 },
8179 {
8180 /* MOD_0FB5 */
8181 { "lgsS", { Gv, Mp }, 0 },
8182 },
8183 {
8184 /* MOD_0FC3 */
8185 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
8186 },
8187 {
8188 /* MOD_0FC7_REG_3 */
8189 { "xrstors", { FXSAVE }, 0 },
8190 },
8191 {
8192 /* MOD_0FC7_REG_4 */
8193 { "xsavec", { FXSAVE }, 0 },
8194 },
8195 {
8196 /* MOD_0FC7_REG_5 */
8197 { "xsaves", { FXSAVE }, 0 },
8198 },
8199 {
8200 /* MOD_0FC7_REG_6 */
8201 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8202 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8203 },
8204 {
8205 /* MOD_0FC7_REG_7 */
8206 { "vmptrst", { Mq }, 0 },
8207 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8208 },
8209 {
8210 /* MOD_0FD7 */
8211 { Bad_Opcode },
8212 { "pmovmskb", { Gdq, MS }, 0 },
8213 },
8214 {
8215 /* MOD_0FE7_PREFIX_2 */
8216 { "movntdq", { Mx, XM }, 0 },
8217 },
8218 {
8219 /* MOD_0FF0_PREFIX_3 */
8220 { "lddqu", { XM, M }, 0 },
8221 },
8222 {
8223 /* MOD_0F382A */
8224 { "movntdqa", { XM, Mx }, PREFIX_DATA },
8225 },
8226 {
8227 /* MOD_0F38DC_PREFIX_1 */
8228 { "aesenc128kl", { XM, M }, 0 },
8229 { "loadiwkey", { XM, EXx }, 0 },
8230 },
8231 {
8232 /* MOD_0F38DD_PREFIX_1 */
8233 { "aesdec128kl", { XM, M }, 0 },
8234 },
8235 {
8236 /* MOD_0F38DE_PREFIX_1 */
8237 { "aesenc256kl", { XM, M }, 0 },
8238 },
8239 {
8240 /* MOD_0F38DF_PREFIX_1 */
8241 { "aesdec256kl", { XM, M }, 0 },
8242 },
8243 {
8244 /* MOD_0F38F5 */
8245 { "wrussK", { M, Gdq }, PREFIX_DATA },
8246 },
8247 {
8248 /* MOD_0F38F6_PREFIX_0 */
8249 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
8250 },
8251 {
8252 /* MOD_0F38F8_PREFIX_1 */
8253 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
8254 },
8255 {
8256 /* MOD_0F38F8_PREFIX_2 */
8257 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
8258 },
8259 {
8260 /* MOD_0F38F8_PREFIX_3 */
8261 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
8262 },
8263 {
8264 /* MOD_0F38F9 */
8265 { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
8266 },
8267 {
8268 /* MOD_0F38FA_PREFIX_1 */
8269 { Bad_Opcode },
8270 { "encodekey128", { Gd, Ed }, 0 },
8271 },
8272 {
8273 /* MOD_0F38FB_PREFIX_1 */
8274 { Bad_Opcode },
8275 { "encodekey256", { Gd, Ed }, 0 },
8276 },
8277 {
8278 /* MOD_0F3A0F_PREFIX_1 */
8279 { Bad_Opcode },
8280 { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
8281 },
8282 {
8283 /* MOD_62_32BIT */
8284 { "bound{S|}", { Gv, Ma }, 0 },
8285 { EVEX_TABLE (EVEX_0F) },
8286 },
8287 {
8288 /* MOD_C4_32BIT */
8289 { "lesS", { Gv, Mp }, 0 },
8290 { VEX_C4_TABLE (VEX_0F) },
8291 },
8292 {
8293 /* MOD_C5_32BIT */
8294 { "ldsS", { Gv, Mp }, 0 },
8295 { VEX_C5_TABLE (VEX_0F) },
8296 },
8297 {
8298 /* MOD_VEX_0F12_PREFIX_0 */
8299 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
8300 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
8301 },
8302 {
8303 /* MOD_VEX_0F12_PREFIX_2 */
8304 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
8305 },
8306 {
8307 /* MOD_VEX_0F13 */
8308 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
8309 },
8310 {
8311 /* MOD_VEX_0F16_PREFIX_0 */
8312 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
8313 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
8314 },
8315 {
8316 /* MOD_VEX_0F16_PREFIX_2 */
8317 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
8318 },
8319 {
8320 /* MOD_VEX_0F17 */
8321 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
8322 },
8323 {
8324 /* MOD_VEX_0F2B */
8325 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
8326 },
8327 {
8328 /* MOD_VEX_0F41_L_1 */
8329 { Bad_Opcode },
8330 { VEX_W_TABLE (VEX_W_0F41_L_1_M_1) },
8331 },
8332 {
8333 /* MOD_VEX_0F42_L_1 */
8334 { Bad_Opcode },
8335 { VEX_W_TABLE (VEX_W_0F42_L_1_M_1) },
8336 },
8337 {
8338 /* MOD_VEX_0F44_L_0 */
8339 { Bad_Opcode },
8340 { VEX_W_TABLE (VEX_W_0F44_L_0_M_1) },
8341 },
8342 {
8343 /* MOD_VEX_0F45_L_1 */
8344 { Bad_Opcode },
8345 { VEX_W_TABLE (VEX_W_0F45_L_1_M_1) },
8346 },
8347 {
8348 /* MOD_VEX_0F46_L_1 */
8349 { Bad_Opcode },
8350 { VEX_W_TABLE (VEX_W_0F46_L_1_M_1) },
8351 },
8352 {
8353 /* MOD_VEX_0F47_L_1 */
8354 { Bad_Opcode },
8355 { VEX_W_TABLE (VEX_W_0F47_L_1_M_1) },
8356 },
8357 {
8358 /* MOD_VEX_0F4A_L_1 */
8359 { Bad_Opcode },
8360 { VEX_W_TABLE (VEX_W_0F4A_L_1_M_1) },
8361 },
8362 {
8363 /* MOD_VEX_0F4B_L_1 */
8364 { Bad_Opcode },
8365 { VEX_W_TABLE (VEX_W_0F4B_L_1_M_1) },
8366 },
8367 {
8368 /* MOD_VEX_0F50 */
8369 { Bad_Opcode },
8370 { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
8371 },
8372 {
8373 /* MOD_VEX_0F71 */
8374 { Bad_Opcode },
8375 { REG_TABLE (REG_VEX_0F71_M_0) },
8376 },
8377 {
8378 /* MOD_VEX_0F72 */
8379 { Bad_Opcode },
8380 { REG_TABLE (REG_VEX_0F72_M_0) },
8381 },
8382 {
8383 /* MOD_VEX_0F73 */
8384 { Bad_Opcode },
8385 { REG_TABLE (REG_VEX_0F73_M_0) },
8386 },
8387 {
8388 /* MOD_VEX_0F91_L_0 */
8389 { VEX_W_TABLE (VEX_W_0F91_L_0_M_0) },
8390 },
8391 {
8392 /* MOD_VEX_0F92_L_0 */
8393 { Bad_Opcode },
8394 { VEX_W_TABLE (VEX_W_0F92_L_0_M_1) },
8395 },
8396 {
8397 /* MOD_VEX_0F93_L_0 */
8398 { Bad_Opcode },
8399 { VEX_W_TABLE (VEX_W_0F93_L_0_M_1) },
8400 },
8401 {
8402 /* MOD_VEX_0F98_L_0 */
8403 { Bad_Opcode },
8404 { VEX_W_TABLE (VEX_W_0F98_L_0_M_1) },
8405 },
8406 {
8407 /* MOD_VEX_0F99_L_0 */
8408 { Bad_Opcode },
8409 { VEX_W_TABLE (VEX_W_0F99_L_0_M_1) },
8410 },
8411 {
8412 /* MOD_VEX_0FAE_REG_2 */
8413 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
8414 },
8415 {
8416 /* MOD_VEX_0FAE_REG_3 */
8417 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
8418 },
8419 {
8420 /* MOD_VEX_0FD7 */
8421 { Bad_Opcode },
8422 { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
8423 },
8424 {
8425 /* MOD_VEX_0FE7 */
8426 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
8427 },
8428 {
8429 /* MOD_VEX_0FF0_PREFIX_3 */
8430 { "vlddqu", { XM, M }, 0 },
8431 },
8432 {
8433 /* MOD_VEX_0F381A */
8434 { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
8435 },
8436 {
8437 /* MOD_VEX_0F382A */
8438 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
8439 },
8440 {
8441 /* MOD_VEX_0F382C */
8442 { VEX_W_TABLE (VEX_W_0F382C_M_0) },
8443 },
8444 {
8445 /* MOD_VEX_0F382D */
8446 { VEX_W_TABLE (VEX_W_0F382D_M_0) },
8447 },
8448 {
8449 /* MOD_VEX_0F382E */
8450 { VEX_W_TABLE (VEX_W_0F382E_M_0) },
8451 },
8452 {
8453 /* MOD_VEX_0F382F */
8454 { VEX_W_TABLE (VEX_W_0F382F_M_0) },
8455 },
8456 {
8457 /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
8458 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
8459 { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
8460 },
8461 {
8462 /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
8463 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
8464 },
8465 {
8466 /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
8467 { Bad_Opcode },
8468 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
8469 },
8470 {
8471 /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
8472 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
8473 },
8474 {
8475 /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
8476 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
8477 },
8478 {
8479 /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
8480 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
8481 },
8482 {
8483 /* MOD_VEX_0F385A */
8484 { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
8485 },
8486 {
8487 /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
8488 { Bad_Opcode },
8489 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
8490 },
8491 {
8492 /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
8493 { Bad_Opcode },
8494 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
8495 },
8496 {
8497 /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
8498 { Bad_Opcode },
8499 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
8500 },
8501 {
8502 /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
8503 { Bad_Opcode },
8504 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
8505 },
8506 {
8507 /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
8508 { Bad_Opcode },
8509 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
8510 },
8511 {
8512 /* MOD_VEX_0F388C */
8513 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
8514 },
8515 {
8516 /* MOD_VEX_0F388E */
8517 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
8518 },
8519 {
8520 /* MOD_VEX_0F3A30_L_0 */
8521 { Bad_Opcode },
8522 { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8523 },
8524 {
8525 /* MOD_VEX_0F3A31_L_0 */
8526 { Bad_Opcode },
8527 { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8528 },
8529 {
8530 /* MOD_VEX_0F3A32_L_0 */
8531 { Bad_Opcode },
8532 { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
8533 },
8534 {
8535 /* MOD_VEX_0F3A33_L_0 */
8536 { Bad_Opcode },
8537 { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
8538 },
8539 {
8540 /* MOD_VEX_0FXOP_09_12 */
8541 { Bad_Opcode },
8542 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
8543 },
8544
8545 #include "i386-dis-evex-mod.h"
8546 };
8547
8548 static const struct dis386 rm_table[][8] = {
8549 {
8550 /* RM_C6_REG_7 */
8551 { "xabort", { Skip_MODRM, Ib }, 0 },
8552 },
8553 {
8554 /* RM_C7_REG_7 */
8555 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8556 },
8557 {
8558 /* RM_0F01_REG_0 */
8559 { "enclv", { Skip_MODRM }, 0 },
8560 { "vmcall", { Skip_MODRM }, 0 },
8561 { "vmlaunch", { Skip_MODRM }, 0 },
8562 { "vmresume", { Skip_MODRM }, 0 },
8563 { "vmxoff", { Skip_MODRM }, 0 },
8564 { "pconfig", { Skip_MODRM }, 0 },
8565 },
8566 {
8567 /* RM_0F01_REG_1 */
8568 { "monitor", { { OP_Monitor, 0 } }, 0 },
8569 { "mwait", { { OP_Mwait, 0 } }, 0 },
8570 { "clac", { Skip_MODRM }, 0 },
8571 { "stac", { Skip_MODRM }, 0 },
8572 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8573 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8574 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8575 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8576 },
8577 {
8578 /* RM_0F01_REG_2 */
8579 { "xgetbv", { Skip_MODRM }, 0 },
8580 { "xsetbv", { Skip_MODRM }, 0 },
8581 { Bad_Opcode },
8582 { Bad_Opcode },
8583 { "vmfunc", { Skip_MODRM }, 0 },
8584 { "xend", { Skip_MODRM }, 0 },
8585 { "xtest", { Skip_MODRM }, 0 },
8586 { "enclu", { Skip_MODRM }, 0 },
8587 },
8588 {
8589 /* RM_0F01_REG_3 */
8590 { "vmrun", { Skip_MODRM }, 0 },
8591 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8592 { "vmload", { Skip_MODRM }, 0 },
8593 { "vmsave", { Skip_MODRM }, 0 },
8594 { "stgi", { Skip_MODRM }, 0 },
8595 { "clgi", { Skip_MODRM }, 0 },
8596 { "skinit", { Skip_MODRM }, 0 },
8597 { "invlpga", { Skip_MODRM }, 0 },
8598 },
8599 {
8600 /* RM_0F01_REG_5_MOD_3 */
8601 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8602 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8603 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8604 { Bad_Opcode },
8605 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8606 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8607 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8608 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8609 },
8610 {
8611 /* RM_0F01_REG_7_MOD_3 */
8612 { "swapgs", { Skip_MODRM }, 0 },
8613 { "rdtscp", { Skip_MODRM }, 0 },
8614 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8615 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8616 { "clzero", { Skip_MODRM }, 0 },
8617 { "rdpru", { Skip_MODRM }, 0 },
8618 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8619 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8620 },
8621 {
8622 /* RM_0F1E_P_1_MOD_3_REG_7 */
8623 { "nopQ", { Ev }, PREFIX_IGNORED },
8624 { "nopQ", { Ev }, PREFIX_IGNORED },
8625 { "endbr64", { Skip_MODRM }, 0 },
8626 { "endbr32", { Skip_MODRM }, 0 },
8627 { "nopQ", { Ev }, PREFIX_IGNORED },
8628 { "nopQ", { Ev }, PREFIX_IGNORED },
8629 { "nopQ", { Ev }, PREFIX_IGNORED },
8630 { "nopQ", { Ev }, PREFIX_IGNORED },
8631 },
8632 {
8633 /* RM_0F3A0F_P_1_MOD_3_REG_0 */
8634 { "hreset", { Skip_MODRM, Ib }, 0 },
8635 },
8636 {
8637 /* RM_0FAE_REG_6_MOD_3 */
8638 { "mfence", { Skip_MODRM }, 0 },
8639 },
8640 {
8641 /* RM_0FAE_REG_7_MOD_3 */
8642 { "sfence", { Skip_MODRM }, 0 },
8643
8644 },
8645 {
8646 /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
8647 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
8648 },
8649 };
8650
8651 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8652
8653 /* We use the high bit to indicate different name for the same
8654 prefix. */
8655 #define REP_PREFIX (0xf3 | 0x100)
8656 #define XACQUIRE_PREFIX (0xf2 | 0x200)
8657 #define XRELEASE_PREFIX (0xf3 | 0x400)
8658 #define BND_PREFIX (0xf2 | 0x400)
8659 #define NOTRACK_PREFIX (0x3e | 0x100)
8660
8661 /* Remember if the current op is a jump instruction. */
8662 static bfd_boolean op_is_jump = FALSE;
8663
8664 static int
8665 ckprefix (void)
8666 {
8667 int newrex, i, length;
8668 rex = 0;
8669 prefixes = 0;
8670 used_prefixes = 0;
8671 rex_used = 0;
8672 last_lock_prefix = -1;
8673 last_repz_prefix = -1;
8674 last_repnz_prefix = -1;
8675 last_data_prefix = -1;
8676 last_addr_prefix = -1;
8677 last_rex_prefix = -1;
8678 last_seg_prefix = -1;
8679 fwait_prefix = -1;
8680 active_seg_prefix = 0;
8681 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
8682 all_prefixes[i] = 0;
8683 i = 0;
8684 length = 0;
8685 /* The maximum instruction length is 15bytes. */
8686 while (length < MAX_CODE_LENGTH - 1)
8687 {
8688 FETCH_DATA (the_info, codep + 1);
8689 newrex = 0;
8690 switch (*codep)
8691 {
8692 /* REX prefixes family. */
8693 case 0x40:
8694 case 0x41:
8695 case 0x42:
8696 case 0x43:
8697 case 0x44:
8698 case 0x45:
8699 case 0x46:
8700 case 0x47:
8701 case 0x48:
8702 case 0x49:
8703 case 0x4a:
8704 case 0x4b:
8705 case 0x4c:
8706 case 0x4d:
8707 case 0x4e:
8708 case 0x4f:
8709 if (address_mode == mode_64bit)
8710 newrex = *codep;
8711 else
8712 return 1;
8713 last_rex_prefix = i;
8714 break;
8715 case 0xf3:
8716 prefixes |= PREFIX_REPZ;
8717 last_repz_prefix = i;
8718 break;
8719 case 0xf2:
8720 prefixes |= PREFIX_REPNZ;
8721 last_repnz_prefix = i;
8722 break;
8723 case 0xf0:
8724 prefixes |= PREFIX_LOCK;
8725 last_lock_prefix = i;
8726 break;
8727 case 0x2e:
8728 prefixes |= PREFIX_CS;
8729 last_seg_prefix = i;
8730
8731 if (address_mode != mode_64bit)
8732 active_seg_prefix = PREFIX_CS;
8733
8734 break;
8735 case 0x36:
8736 prefixes |= PREFIX_SS;
8737 last_seg_prefix = i;
8738
8739 if (address_mode != mode_64bit)
8740 active_seg_prefix = PREFIX_SS;
8741
8742 break;
8743 case 0x3e:
8744 prefixes |= PREFIX_DS;
8745 last_seg_prefix = i;
8746
8747 if (address_mode != mode_64bit)
8748 active_seg_prefix = PREFIX_DS;
8749
8750 break;
8751 case 0x26:
8752 prefixes |= PREFIX_ES;
8753 last_seg_prefix = i;
8754
8755 if (address_mode != mode_64bit)
8756 active_seg_prefix = PREFIX_ES;
8757
8758 break;
8759 case 0x64:
8760 prefixes |= PREFIX_FS;
8761 last_seg_prefix = i;
8762 active_seg_prefix = PREFIX_FS;
8763 break;
8764 case 0x65:
8765 prefixes |= PREFIX_GS;
8766 last_seg_prefix = i;
8767 active_seg_prefix = PREFIX_GS;
8768 break;
8769 case 0x66:
8770 prefixes |= PREFIX_DATA;
8771 last_data_prefix = i;
8772 break;
8773 case 0x67:
8774 prefixes |= PREFIX_ADDR;
8775 last_addr_prefix = i;
8776 break;
8777 case FWAIT_OPCODE:
8778 /* fwait is really an instruction. If there are prefixes
8779 before the fwait, they belong to the fwait, *not* to the
8780 following instruction. */
8781 fwait_prefix = i;
8782 if (prefixes || rex)
8783 {
8784 prefixes |= PREFIX_FWAIT;
8785 codep++;
8786 /* This ensures that the previous REX prefixes are noticed
8787 as unused prefixes, as in the return case below. */
8788 rex_used = rex;
8789 return 1;
8790 }
8791 prefixes = PREFIX_FWAIT;
8792 break;
8793 default:
8794 return 1;
8795 }
8796 /* Rex is ignored when followed by another prefix. */
8797 if (rex)
8798 {
8799 rex_used = rex;
8800 return 1;
8801 }
8802 if (*codep != FWAIT_OPCODE)
8803 all_prefixes[i++] = *codep;
8804 rex = newrex;
8805 codep++;
8806 length++;
8807 }
8808 return 0;
8809 }
8810
8811 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8812 prefix byte. */
8813
8814 static const char *
8815 prefix_name (int pref, int sizeflag)
8816 {
8817 static const char *rexes [16] =
8818 {
8819 "rex", /* 0x40 */
8820 "rex.B", /* 0x41 */
8821 "rex.X", /* 0x42 */
8822 "rex.XB", /* 0x43 */
8823 "rex.R", /* 0x44 */
8824 "rex.RB", /* 0x45 */
8825 "rex.RX", /* 0x46 */
8826 "rex.RXB", /* 0x47 */
8827 "rex.W", /* 0x48 */
8828 "rex.WB", /* 0x49 */
8829 "rex.WX", /* 0x4a */
8830 "rex.WXB", /* 0x4b */
8831 "rex.WR", /* 0x4c */
8832 "rex.WRB", /* 0x4d */
8833 "rex.WRX", /* 0x4e */
8834 "rex.WRXB", /* 0x4f */
8835 };
8836
8837 switch (pref)
8838 {
8839 /* REX prefixes family. */
8840 case 0x40:
8841 case 0x41:
8842 case 0x42:
8843 case 0x43:
8844 case 0x44:
8845 case 0x45:
8846 case 0x46:
8847 case 0x47:
8848 case 0x48:
8849 case 0x49:
8850 case 0x4a:
8851 case 0x4b:
8852 case 0x4c:
8853 case 0x4d:
8854 case 0x4e:
8855 case 0x4f:
8856 return rexes [pref - 0x40];
8857 case 0xf3:
8858 return "repz";
8859 case 0xf2:
8860 return "repnz";
8861 case 0xf0:
8862 return "lock";
8863 case 0x2e:
8864 return "cs";
8865 case 0x36:
8866 return "ss";
8867 case 0x3e:
8868 return "ds";
8869 case 0x26:
8870 return "es";
8871 case 0x64:
8872 return "fs";
8873 case 0x65:
8874 return "gs";
8875 case 0x66:
8876 return (sizeflag & DFLAG) ? "data16" : "data32";
8877 case 0x67:
8878 if (address_mode == mode_64bit)
8879 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8880 else
8881 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8882 case FWAIT_OPCODE:
8883 return "fwait";
8884 case REP_PREFIX:
8885 return "rep";
8886 case XACQUIRE_PREFIX:
8887 return "xacquire";
8888 case XRELEASE_PREFIX:
8889 return "xrelease";
8890 case BND_PREFIX:
8891 return "bnd";
8892 case NOTRACK_PREFIX:
8893 return "notrack";
8894 default:
8895 return NULL;
8896 }
8897 }
8898
8899 static char op_out[MAX_OPERANDS][100];
8900 static int op_ad, op_index[MAX_OPERANDS];
8901 static int two_source_ops;
8902 static bfd_vma op_address[MAX_OPERANDS];
8903 static bfd_vma op_riprel[MAX_OPERANDS];
8904 static bfd_vma start_pc;
8905
8906 /*
8907 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
8908 * (see topic "Redundant prefixes" in the "Differences from 8086"
8909 * section of the "Virtual 8086 Mode" chapter.)
8910 * 'pc' should be the address of this instruction, it will
8911 * be used to print the target address if this is a relative jump or call
8912 * The function returns the length of this instruction in bytes.
8913 */
8914
8915 static char intel_syntax;
8916 static char intel_mnemonic = !SYSV386_COMPAT;
8917 static char open_char;
8918 static char close_char;
8919 static char separator_char;
8920 static char scale_char;
8921
8922 enum x86_64_isa
8923 {
8924 amd64 = 1,
8925 intel64
8926 };
8927
8928 static enum x86_64_isa isa64;
8929
8930 /* Here for backwards compatibility. When gdb stops using
8931 print_insn_i386_att and print_insn_i386_intel these functions can
8932 disappear, and print_insn_i386 be merged into print_insn. */
8933 int
8934 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
8935 {
8936 intel_syntax = 0;
8937
8938 return print_insn (pc, info);
8939 }
8940
8941 int
8942 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
8943 {
8944 intel_syntax = 1;
8945
8946 return print_insn (pc, info);
8947 }
8948
8949 int
8950 print_insn_i386 (bfd_vma pc, disassemble_info *info)
8951 {
8952 intel_syntax = -1;
8953
8954 return print_insn (pc, info);
8955 }
8956
8957 void
8958 print_i386_disassembler_options (FILE *stream)
8959 {
8960 fprintf (stream, _("\n\
8961 The following i386/x86-64 specific disassembler options are supported for use\n\
8962 with the -M switch (multiple options should be separated by commas):\n"));
8963
8964 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8965 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8966 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8967 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8968 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8969 fprintf (stream, _(" att-mnemonic\n"
8970 " Display instruction in AT&T mnemonic\n"));
8971 fprintf (stream, _(" intel-mnemonic\n"
8972 " Display instruction in Intel mnemonic\n"));
8973 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8974 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8975 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8976 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8977 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8978 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8979 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8980 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8981 }
8982
8983 /* Bad opcode. */
8984 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8985
8986 /* Get a pointer to struct dis386 with a valid name. */
8987
8988 static const struct dis386 *
8989 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
8990 {
8991 int vindex, vex_table_index;
8992
8993 if (dp->name != NULL)
8994 return dp;
8995
8996 switch (dp->op[0].bytemode)
8997 {
8998 case USE_REG_TABLE:
8999 dp = &reg_table[dp->op[1].bytemode][modrm.reg];
9000 break;
9001
9002 case USE_MOD_TABLE:
9003 vindex = modrm.mod == 0x3 ? 1 : 0;
9004 dp = &mod_table[dp->op[1].bytemode][vindex];
9005 break;
9006
9007 case USE_RM_TABLE:
9008 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9009 break;
9010
9011 case USE_PREFIX_TABLE:
9012 if (need_vex)
9013 {
9014 /* The prefix in VEX is implicit. */
9015 switch (vex.prefix)
9016 {
9017 case 0:
9018 vindex = 0;
9019 break;
9020 case REPE_PREFIX_OPCODE:
9021 vindex = 1;
9022 break;
9023 case DATA_PREFIX_OPCODE:
9024 vindex = 2;
9025 break;
9026 case REPNE_PREFIX_OPCODE:
9027 vindex = 3;
9028 break;
9029 default:
9030 abort ();
9031 break;
9032 }
9033 }
9034 else
9035 {
9036 int last_prefix = -1;
9037 int prefix = 0;
9038 vindex = 0;
9039 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
9040 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
9041 last one wins. */
9042 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9043 {
9044 if (last_repz_prefix > last_repnz_prefix)
9045 {
9046 vindex = 1;
9047 prefix = PREFIX_REPZ;
9048 last_prefix = last_repz_prefix;
9049 }
9050 else
9051 {
9052 vindex = 3;
9053 prefix = PREFIX_REPNZ;
9054 last_prefix = last_repnz_prefix;
9055 }
9056
9057 /* Check if prefix should be ignored. */
9058 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
9059 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
9060 & prefix) != 0
9061 && !prefix_table[dp->op[1].bytemode][vindex].name)
9062 vindex = 0;
9063 }
9064
9065 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
9066 {
9067 vindex = 2;
9068 prefix = PREFIX_DATA;
9069 last_prefix = last_data_prefix;
9070 }
9071
9072 if (vindex != 0)
9073 {
9074 used_prefixes |= prefix;
9075 all_prefixes[last_prefix] = 0;
9076 }
9077 }
9078 dp = &prefix_table[dp->op[1].bytemode][vindex];
9079 break;
9080
9081 case USE_X86_64_TABLE:
9082 vindex = address_mode == mode_64bit ? 1 : 0;
9083 dp = &x86_64_table[dp->op[1].bytemode][vindex];
9084 break;
9085
9086 case USE_3BYTE_TABLE:
9087 FETCH_DATA (info, codep + 2);
9088 vindex = *codep++;
9089 dp = &three_byte_table[dp->op[1].bytemode][vindex];
9090 end_codep = codep;
9091 modrm.mod = (*codep >> 6) & 3;
9092 modrm.reg = (*codep >> 3) & 7;
9093 modrm.rm = *codep & 7;
9094 break;
9095
9096 case USE_VEX_LEN_TABLE:
9097 if (!need_vex)
9098 abort ();
9099
9100 switch (vex.length)
9101 {
9102 case 128:
9103 vindex = 0;
9104 break;
9105 case 256:
9106 vindex = 1;
9107 break;
9108 default:
9109 abort ();
9110 break;
9111 }
9112
9113 dp = &vex_len_table[dp->op[1].bytemode][vindex];
9114 break;
9115
9116 case USE_EVEX_LEN_TABLE:
9117 if (!vex.evex)
9118 abort ();
9119
9120 switch (vex.length)
9121 {
9122 case 128:
9123 vindex = 0;
9124 break;
9125 case 256:
9126 vindex = 1;
9127 break;
9128 case 512:
9129 vindex = 2;
9130 break;
9131 default:
9132 abort ();
9133 break;
9134 }
9135
9136 dp = &evex_len_table[dp->op[1].bytemode][vindex];
9137 break;
9138
9139 case USE_XOP_8F_TABLE:
9140 FETCH_DATA (info, codep + 3);
9141 rex = ~(*codep >> 5) & 0x7;
9142
9143 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
9144 switch ((*codep & 0x1f))
9145 {
9146 default:
9147 dp = &bad_opcode;
9148 return dp;
9149 case 0x8:
9150 vex_table_index = XOP_08;
9151 break;
9152 case 0x9:
9153 vex_table_index = XOP_09;
9154 break;
9155 case 0xa:
9156 vex_table_index = XOP_0A;
9157 break;
9158 }
9159 codep++;
9160 vex.w = *codep & 0x80;
9161 if (vex.w && address_mode == mode_64bit)
9162 rex |= REX_W;
9163
9164 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9165 if (address_mode != mode_64bit)
9166 {
9167 /* In 16/32-bit mode REX_B is silently ignored. */
9168 rex &= ~REX_B;
9169 }
9170
9171 vex.length = (*codep & 0x4) ? 256 : 128;
9172 switch ((*codep & 0x3))
9173 {
9174 case 0:
9175 break;
9176 case 1:
9177 vex.prefix = DATA_PREFIX_OPCODE;
9178 break;
9179 case 2:
9180 vex.prefix = REPE_PREFIX_OPCODE;
9181 break;
9182 case 3:
9183 vex.prefix = REPNE_PREFIX_OPCODE;
9184 break;
9185 }
9186 need_vex = 1;
9187 codep++;
9188 vindex = *codep++;
9189 dp = &xop_table[vex_table_index][vindex];
9190
9191 end_codep = codep;
9192 FETCH_DATA (info, codep + 1);
9193 modrm.mod = (*codep >> 6) & 3;
9194 modrm.reg = (*codep >> 3) & 7;
9195 modrm.rm = *codep & 7;
9196
9197 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
9198 having to decode the bits for every otherwise valid encoding. */
9199 if (vex.prefix)
9200 return &bad_opcode;
9201 break;
9202
9203 case USE_VEX_C4_TABLE:
9204 /* VEX prefix. */
9205 FETCH_DATA (info, codep + 3);
9206 rex = ~(*codep >> 5) & 0x7;
9207 switch ((*codep & 0x1f))
9208 {
9209 default:
9210 dp = &bad_opcode;
9211 return dp;
9212 case 0x1:
9213 vex_table_index = VEX_0F;
9214 break;
9215 case 0x2:
9216 vex_table_index = VEX_0F38;
9217 break;
9218 case 0x3:
9219 vex_table_index = VEX_0F3A;
9220 break;
9221 }
9222 codep++;
9223 vex.w = *codep & 0x80;
9224 if (address_mode == mode_64bit)
9225 {
9226 if (vex.w)
9227 rex |= REX_W;
9228 }
9229 else
9230 {
9231 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
9232 is ignored, other REX bits are 0 and the highest bit in
9233 VEX.vvvv is also ignored (but we mustn't clear it here). */
9234 rex = 0;
9235 }
9236 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9237 vex.length = (*codep & 0x4) ? 256 : 128;
9238 switch ((*codep & 0x3))
9239 {
9240 case 0:
9241 break;
9242 case 1:
9243 vex.prefix = DATA_PREFIX_OPCODE;
9244 break;
9245 case 2:
9246 vex.prefix = REPE_PREFIX_OPCODE;
9247 break;
9248 case 3:
9249 vex.prefix = REPNE_PREFIX_OPCODE;
9250 break;
9251 }
9252 need_vex = 1;
9253 codep++;
9254 vindex = *codep++;
9255 dp = &vex_table[vex_table_index][vindex];
9256 end_codep = codep;
9257 /* There is no MODRM byte for VEX0F 77. */
9258 if (vex_table_index != VEX_0F || vindex != 0x77)
9259 {
9260 FETCH_DATA (info, codep + 1);
9261 modrm.mod = (*codep >> 6) & 3;
9262 modrm.reg = (*codep >> 3) & 7;
9263 modrm.rm = *codep & 7;
9264 }
9265 break;
9266
9267 case USE_VEX_C5_TABLE:
9268 /* VEX prefix. */
9269 FETCH_DATA (info, codep + 2);
9270 rex = (*codep & 0x80) ? 0 : REX_R;
9271
9272 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9273 VEX.vvvv is 1. */
9274 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9275 vex.length = (*codep & 0x4) ? 256 : 128;
9276 switch ((*codep & 0x3))
9277 {
9278 case 0:
9279 break;
9280 case 1:
9281 vex.prefix = DATA_PREFIX_OPCODE;
9282 break;
9283 case 2:
9284 vex.prefix = REPE_PREFIX_OPCODE;
9285 break;
9286 case 3:
9287 vex.prefix = REPNE_PREFIX_OPCODE;
9288 break;
9289 }
9290 need_vex = 1;
9291 codep++;
9292 vindex = *codep++;
9293 dp = &vex_table[dp->op[1].bytemode][vindex];
9294 end_codep = codep;
9295 /* There is no MODRM byte for VEX 77. */
9296 if (vindex != 0x77)
9297 {
9298 FETCH_DATA (info, codep + 1);
9299 modrm.mod = (*codep >> 6) & 3;
9300 modrm.reg = (*codep >> 3) & 7;
9301 modrm.rm = *codep & 7;
9302 }
9303 break;
9304
9305 case USE_VEX_W_TABLE:
9306 if (!need_vex)
9307 abort ();
9308
9309 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
9310 break;
9311
9312 case USE_EVEX_TABLE:
9313 two_source_ops = 0;
9314 /* EVEX prefix. */
9315 vex.evex = 1;
9316 FETCH_DATA (info, codep + 4);
9317 /* The first byte after 0x62. */
9318 rex = ~(*codep >> 5) & 0x7;
9319 vex.r = *codep & 0x10;
9320 switch ((*codep & 0xf))
9321 {
9322 default:
9323 return &bad_opcode;
9324 case 0x1:
9325 vex_table_index = EVEX_0F;
9326 break;
9327 case 0x2:
9328 vex_table_index = EVEX_0F38;
9329 break;
9330 case 0x3:
9331 vex_table_index = EVEX_0F3A;
9332 break;
9333 }
9334
9335 /* The second byte after 0x62. */
9336 codep++;
9337 vex.w = *codep & 0x80;
9338 if (vex.w && address_mode == mode_64bit)
9339 rex |= REX_W;
9340
9341 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9342
9343 /* The U bit. */
9344 if (!(*codep & 0x4))
9345 return &bad_opcode;
9346
9347 switch ((*codep & 0x3))
9348 {
9349 case 0:
9350 break;
9351 case 1:
9352 vex.prefix = DATA_PREFIX_OPCODE;
9353 break;
9354 case 2:
9355 vex.prefix = REPE_PREFIX_OPCODE;
9356 break;
9357 case 3:
9358 vex.prefix = REPNE_PREFIX_OPCODE;
9359 break;
9360 }
9361
9362 /* The third byte after 0x62. */
9363 codep++;
9364
9365 /* Remember the static rounding bits. */
9366 vex.ll = (*codep >> 5) & 3;
9367 vex.b = (*codep & 0x10) != 0;
9368
9369 vex.v = *codep & 0x8;
9370 vex.mask_register_specifier = *codep & 0x7;
9371 vex.zeroing = *codep & 0x80;
9372
9373 if (address_mode != mode_64bit)
9374 {
9375 /* In 16/32-bit mode silently ignore following bits. */
9376 rex &= ~REX_B;
9377 vex.r = 1;
9378 vex.v = 1;
9379 }
9380
9381 need_vex = 1;
9382 codep++;
9383 vindex = *codep++;
9384 dp = &evex_table[vex_table_index][vindex];
9385 end_codep = codep;
9386 FETCH_DATA (info, codep + 1);
9387 modrm.mod = (*codep >> 6) & 3;
9388 modrm.reg = (*codep >> 3) & 7;
9389 modrm.rm = *codep & 7;
9390
9391 /* Set vector length. */
9392 if (modrm.mod == 3 && vex.b)
9393 vex.length = 512;
9394 else
9395 {
9396 switch (vex.ll)
9397 {
9398 case 0x0:
9399 vex.length = 128;
9400 break;
9401 case 0x1:
9402 vex.length = 256;
9403 break;
9404 case 0x2:
9405 vex.length = 512;
9406 break;
9407 default:
9408 return &bad_opcode;
9409 }
9410 }
9411 break;
9412
9413 case 0:
9414 dp = &bad_opcode;
9415 break;
9416
9417 default:
9418 abort ();
9419 }
9420
9421 if (dp->name != NULL)
9422 return dp;
9423 else
9424 return get_valid_dis386 (dp, info);
9425 }
9426
9427 static void
9428 get_sib (disassemble_info *info, int sizeflag)
9429 {
9430 /* If modrm.mod == 3, operand must be register. */
9431 if (need_modrm
9432 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
9433 && modrm.mod != 3
9434 && modrm.rm == 4)
9435 {
9436 FETCH_DATA (info, codep + 2);
9437 sib.index = (codep [1] >> 3) & 7;
9438 sib.scale = (codep [1] >> 6) & 3;
9439 sib.base = codep [1] & 7;
9440 }
9441 }
9442
9443 static int
9444 print_insn (bfd_vma pc, disassemble_info *info)
9445 {
9446 const struct dis386 *dp;
9447 int i;
9448 char *op_txt[MAX_OPERANDS];
9449 int needcomma;
9450 int sizeflag, orig_sizeflag;
9451 const char *p;
9452 struct dis_private priv;
9453 int prefix_length;
9454
9455 priv.orig_sizeflag = AFLAG | DFLAG;
9456 if ((info->mach & bfd_mach_i386_i386) != 0)
9457 address_mode = mode_32bit;
9458 else if (info->mach == bfd_mach_i386_i8086)
9459 {
9460 address_mode = mode_16bit;
9461 priv.orig_sizeflag = 0;
9462 }
9463 else
9464 address_mode = mode_64bit;
9465
9466 if (intel_syntax == (char) -1)
9467 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
9468
9469 for (p = info->disassembler_options; p != NULL; )
9470 {
9471 if (CONST_STRNEQ (p, "amd64"))
9472 isa64 = amd64;
9473 else if (CONST_STRNEQ (p, "intel64"))
9474 isa64 = intel64;
9475 else if (CONST_STRNEQ (p, "x86-64"))
9476 {
9477 address_mode = mode_64bit;
9478 priv.orig_sizeflag |= AFLAG | DFLAG;
9479 }
9480 else if (CONST_STRNEQ (p, "i386"))
9481 {
9482 address_mode = mode_32bit;
9483 priv.orig_sizeflag |= AFLAG | DFLAG;
9484 }
9485 else if (CONST_STRNEQ (p, "i8086"))
9486 {
9487 address_mode = mode_16bit;
9488 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9489 }
9490 else if (CONST_STRNEQ (p, "intel"))
9491 {
9492 intel_syntax = 1;
9493 if (CONST_STRNEQ (p + 5, "-mnemonic"))
9494 intel_mnemonic = 1;
9495 }
9496 else if (CONST_STRNEQ (p, "att"))
9497 {
9498 intel_syntax = 0;
9499 if (CONST_STRNEQ (p + 3, "-mnemonic"))
9500 intel_mnemonic = 0;
9501 }
9502 else if (CONST_STRNEQ (p, "addr"))
9503 {
9504 if (address_mode == mode_64bit)
9505 {
9506 if (p[4] == '3' && p[5] == '2')
9507 priv.orig_sizeflag &= ~AFLAG;
9508 else if (p[4] == '6' && p[5] == '4')
9509 priv.orig_sizeflag |= AFLAG;
9510 }
9511 else
9512 {
9513 if (p[4] == '1' && p[5] == '6')
9514 priv.orig_sizeflag &= ~AFLAG;
9515 else if (p[4] == '3' && p[5] == '2')
9516 priv.orig_sizeflag |= AFLAG;
9517 }
9518 }
9519 else if (CONST_STRNEQ (p, "data"))
9520 {
9521 if (p[4] == '1' && p[5] == '6')
9522 priv.orig_sizeflag &= ~DFLAG;
9523 else if (p[4] == '3' && p[5] == '2')
9524 priv.orig_sizeflag |= DFLAG;
9525 }
9526 else if (CONST_STRNEQ (p, "suffix"))
9527 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9528
9529 p = strchr (p, ',');
9530 if (p != NULL)
9531 p++;
9532 }
9533
9534 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9535 {
9536 (*info->fprintf_func) (info->stream,
9537 _("64-bit address is disabled"));
9538 return -1;
9539 }
9540
9541 if (intel_syntax)
9542 {
9543 names64 = intel_names64;
9544 names32 = intel_names32;
9545 names16 = intel_names16;
9546 names8 = intel_names8;
9547 names8rex = intel_names8rex;
9548 names_seg = intel_names_seg;
9549 names_mm = intel_names_mm;
9550 names_bnd = intel_names_bnd;
9551 names_xmm = intel_names_xmm;
9552 names_ymm = intel_names_ymm;
9553 names_zmm = intel_names_zmm;
9554 names_tmm = intel_names_tmm;
9555 index64 = intel_index64;
9556 index32 = intel_index32;
9557 names_mask = intel_names_mask;
9558 index16 = intel_index16;
9559 open_char = '[';
9560 close_char = ']';
9561 separator_char = '+';
9562 scale_char = '*';
9563 }
9564 else
9565 {
9566 names64 = att_names64;
9567 names32 = att_names32;
9568 names16 = att_names16;
9569 names8 = att_names8;
9570 names8rex = att_names8rex;
9571 names_seg = att_names_seg;
9572 names_mm = att_names_mm;
9573 names_bnd = att_names_bnd;
9574 names_xmm = att_names_xmm;
9575 names_ymm = att_names_ymm;
9576 names_zmm = att_names_zmm;
9577 names_tmm = att_names_tmm;
9578 index64 = att_index64;
9579 index32 = att_index32;
9580 names_mask = att_names_mask;
9581 index16 = att_index16;
9582 open_char = '(';
9583 close_char = ')';
9584 separator_char = ',';
9585 scale_char = ',';
9586 }
9587
9588 /* The output looks better if we put 7 bytes on a line, since that
9589 puts most long word instructions on a single line. Use 8 bytes
9590 for Intel L1OM. */
9591 if ((info->mach & bfd_mach_l1om) != 0)
9592 info->bytes_per_line = 8;
9593 else
9594 info->bytes_per_line = 7;
9595
9596 info->private_data = &priv;
9597 priv.max_fetched = priv.the_buffer;
9598 priv.insn_start = pc;
9599
9600 obuf[0] = 0;
9601 for (i = 0; i < MAX_OPERANDS; ++i)
9602 {
9603 op_out[i][0] = 0;
9604 op_index[i] = -1;
9605 }
9606
9607 the_info = info;
9608 start_pc = pc;
9609 start_codep = priv.the_buffer;
9610 codep = priv.the_buffer;
9611
9612 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
9613 {
9614 const char *name;
9615
9616 /* Getting here means we tried for data but didn't get it. That
9617 means we have an incomplete instruction of some sort. Just
9618 print the first byte as a prefix or a .byte pseudo-op. */
9619 if (codep > priv.the_buffer)
9620 {
9621 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
9622 if (name != NULL)
9623 (*info->fprintf_func) (info->stream, "%s", name);
9624 else
9625 {
9626 /* Just print the first byte as a .byte instruction. */
9627 (*info->fprintf_func) (info->stream, ".byte 0x%x",
9628 (unsigned int) priv.the_buffer[0]);
9629 }
9630
9631 return 1;
9632 }
9633
9634 return -1;
9635 }
9636
9637 obufp = obuf;
9638 sizeflag = priv.orig_sizeflag;
9639
9640 if (!ckprefix () || rex_used)
9641 {
9642 /* Too many prefixes or unused REX prefixes. */
9643 for (i = 0;
9644 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
9645 i++)
9646 (*info->fprintf_func) (info->stream, "%s%s",
9647 i == 0 ? "" : " ",
9648 prefix_name (all_prefixes[i], sizeflag));
9649 return i;
9650 }
9651
9652 insn_codep = codep;
9653
9654 FETCH_DATA (info, codep + 1);
9655 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
9656
9657 if (((prefixes & PREFIX_FWAIT)
9658 && ((*codep < 0xd8) || (*codep > 0xdf))))
9659 {
9660 /* Handle prefixes before fwait. */
9661 for (i = 0; i < fwait_prefix && all_prefixes[i];
9662 i++)
9663 (*info->fprintf_func) (info->stream, "%s ",
9664 prefix_name (all_prefixes[i], sizeflag));
9665 (*info->fprintf_func) (info->stream, "fwait");
9666 return i + 1;
9667 }
9668
9669 if (*codep == 0x0f)
9670 {
9671 unsigned char threebyte;
9672
9673 codep++;
9674 FETCH_DATA (info, codep + 1);
9675 threebyte = *codep;
9676 dp = &dis386_twobyte[threebyte];
9677 need_modrm = twobyte_has_modrm[threebyte];
9678 codep++;
9679 }
9680 else
9681 {
9682 dp = &dis386[*codep];
9683 need_modrm = onebyte_has_modrm[*codep];
9684 codep++;
9685 }
9686
9687 /* Save sizeflag for printing the extra prefixes later before updating
9688 it for mnemonic and operand processing. The prefix names depend
9689 only on the address mode. */
9690 orig_sizeflag = sizeflag;
9691 if (prefixes & PREFIX_ADDR)
9692 sizeflag ^= AFLAG;
9693 if ((prefixes & PREFIX_DATA))
9694 sizeflag ^= DFLAG;
9695
9696 end_codep = codep;
9697 if (need_modrm)
9698 {
9699 FETCH_DATA (info, codep + 1);
9700 modrm.mod = (*codep >> 6) & 3;
9701 modrm.reg = (*codep >> 3) & 7;
9702 modrm.rm = *codep & 7;
9703 }
9704 else
9705 memset (&modrm, 0, sizeof (modrm));
9706
9707 need_vex = 0;
9708 memset (&vex, 0, sizeof (vex));
9709
9710 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9711 {
9712 get_sib (info, sizeflag);
9713 dofloat (sizeflag);
9714 }
9715 else
9716 {
9717 dp = get_valid_dis386 (dp, info);
9718 if (dp != NULL && putop (dp->name, sizeflag) == 0)
9719 {
9720 get_sib (info, sizeflag);
9721 for (i = 0; i < MAX_OPERANDS; ++i)
9722 {
9723 obufp = op_out[i];
9724 op_ad = MAX_OPERANDS - 1 - i;
9725 if (dp->op[i].rtn)
9726 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
9727 /* For EVEX instruction after the last operand masking
9728 should be printed. */
9729 if (i == 0 && vex.evex)
9730 {
9731 /* Don't print {%k0}. */
9732 if (vex.mask_register_specifier)
9733 {
9734 oappend ("{");
9735 oappend (names_mask[vex.mask_register_specifier]);
9736 oappend ("}");
9737 }
9738 if (vex.zeroing)
9739 oappend ("{z}");
9740 }
9741 }
9742 }
9743 }
9744
9745 /* Clear instruction information. */
9746 if (the_info)
9747 {
9748 the_info->insn_info_valid = 0;
9749 the_info->branch_delay_insns = 0;
9750 the_info->data_size = 0;
9751 the_info->insn_type = dis_noninsn;
9752 the_info->target = 0;
9753 the_info->target2 = 0;
9754 }
9755
9756 /* Reset jump operation indicator. */
9757 op_is_jump = FALSE;
9758
9759 {
9760 int jump_detection = 0;
9761
9762 /* Extract flags. */
9763 for (i = 0; i < MAX_OPERANDS; ++i)
9764 {
9765 if ((dp->op[i].rtn == OP_J)
9766 || (dp->op[i].rtn == OP_indirE))
9767 jump_detection |= 1;
9768 else if ((dp->op[i].rtn == BND_Fixup)
9769 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9770 jump_detection |= 2;
9771 else if ((dp->op[i].bytemode == cond_jump_mode)
9772 || (dp->op[i].bytemode == loop_jcxz_mode))
9773 jump_detection |= 4;
9774 }
9775
9776 /* Determine if this is a jump or branch. */
9777 if ((jump_detection & 0x3) == 0x3)
9778 {
9779 op_is_jump = TRUE;
9780 if (jump_detection & 0x4)
9781 the_info->insn_type = dis_condbranch;
9782 else
9783 the_info->insn_type =
9784 (dp->name && !strncmp(dp->name, "call", 4))
9785 ? dis_jsr : dis_branch;
9786 }
9787 }
9788
9789 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9790 are all 0s in inverted form. */
9791 if (need_vex && vex.register_specifier != 0)
9792 {
9793 (*info->fprintf_func) (info->stream, "(bad)");
9794 return end_codep - priv.the_buffer;
9795 }
9796
9797 switch (dp->prefix_requirement)
9798 {
9799 case PREFIX_DATA:
9800 /* If only the data prefix is marked as mandatory, its absence renders
9801 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9802 if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
9803 {
9804 (*info->fprintf_func) (info->stream, "(bad)");
9805 return end_codep - priv.the_buffer;
9806 }
9807 used_prefixes |= PREFIX_DATA;
9808 /* Fall through. */
9809 case PREFIX_OPCODE:
9810 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9811 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9812 used by putop and MMX/SSE operand and may be overridden by the
9813 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9814 separately. */
9815 if (((need_vex
9816 ? vex.prefix == REPE_PREFIX_OPCODE
9817 || vex.prefix == REPNE_PREFIX_OPCODE
9818 : (prefixes
9819 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9820 && (used_prefixes
9821 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9822 || (((need_vex
9823 ? vex.prefix == DATA_PREFIX_OPCODE
9824 : ((prefixes
9825 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9826 == PREFIX_DATA))
9827 && (used_prefixes & PREFIX_DATA) == 0))
9828 || (vex.evex && dp->prefix_requirement != PREFIX_DATA
9829 && !vex.w != !(used_prefixes & PREFIX_DATA)))
9830 {
9831 (*info->fprintf_func) (info->stream, "(bad)");
9832 return end_codep - priv.the_buffer;
9833 }
9834 break;
9835
9836 case PREFIX_IGNORED:
9837 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9838 origins in all_prefixes. */
9839 used_prefixes &= ~PREFIX_OPCODE;
9840 if (last_data_prefix >= 0)
9841 all_prefixes[last_repz_prefix] = 0x66;
9842 if (last_repz_prefix >= 0)
9843 all_prefixes[last_repz_prefix] = 0xf3;
9844 if (last_repnz_prefix >= 0)
9845 all_prefixes[last_repnz_prefix] = 0xf2;
9846 break;
9847 }
9848
9849 /* Check if the REX prefix is used. */
9850 if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
9851 all_prefixes[last_rex_prefix] = 0;
9852
9853 /* Check if the SEG prefix is used. */
9854 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9855 | PREFIX_FS | PREFIX_GS)) != 0
9856 && (used_prefixes & active_seg_prefix) != 0)
9857 all_prefixes[last_seg_prefix] = 0;
9858
9859 /* Check if the ADDR prefix is used. */
9860 if ((prefixes & PREFIX_ADDR) != 0
9861 && (used_prefixes & PREFIX_ADDR) != 0)
9862 all_prefixes[last_addr_prefix] = 0;
9863
9864 /* Check if the DATA prefix is used. */
9865 if ((prefixes & PREFIX_DATA) != 0
9866 && (used_prefixes & PREFIX_DATA) != 0
9867 && !need_vex)
9868 all_prefixes[last_data_prefix] = 0;
9869
9870 /* Print the extra prefixes. */
9871 prefix_length = 0;
9872 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
9873 if (all_prefixes[i])
9874 {
9875 const char *name;
9876 name = prefix_name (all_prefixes[i], orig_sizeflag);
9877 if (name == NULL)
9878 abort ();
9879 prefix_length += strlen (name) + 1;
9880 (*info->fprintf_func) (info->stream, "%s ", name);
9881 }
9882
9883 /* Check maximum code length. */
9884 if ((codep - start_codep) > MAX_CODE_LENGTH)
9885 {
9886 (*info->fprintf_func) (info->stream, "(bad)");
9887 return MAX_CODE_LENGTH;
9888 }
9889
9890 obufp = mnemonicendp;
9891 for (i = strlen (obuf) + prefix_length; i < 6; i++)
9892 oappend (" ");
9893 oappend (" ");
9894 (*info->fprintf_func) (info->stream, "%s", obuf);
9895
9896 /* The enter and bound instructions are printed with operands in the same
9897 order as the intel book; everything else is printed in reverse order. */
9898 if (intel_syntax || two_source_ops)
9899 {
9900 bfd_vma riprel;
9901
9902 for (i = 0; i < MAX_OPERANDS; ++i)
9903 op_txt[i] = op_out[i];
9904
9905 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9906 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9907 {
9908 op_txt[2] = op_out[3];
9909 op_txt[3] = op_out[2];
9910 }
9911
9912 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9913 {
9914 op_ad = op_index[i];
9915 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
9916 op_index[MAX_OPERANDS - 1 - i] = op_ad;
9917 riprel = op_riprel[i];
9918 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
9919 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9920 }
9921 }
9922 else
9923 {
9924 for (i = 0; i < MAX_OPERANDS; ++i)
9925 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
9926 }
9927
9928 needcomma = 0;
9929 for (i = 0; i < MAX_OPERANDS; ++i)
9930 if (*op_txt[i])
9931 {
9932 if (needcomma)
9933 (*info->fprintf_func) (info->stream, ",");
9934 if (op_index[i] != -1 && !op_riprel[i])
9935 {
9936 bfd_vma target = (bfd_vma) op_address[op_index[i]];
9937
9938 if (the_info && op_is_jump)
9939 {
9940 the_info->insn_info_valid = 1;
9941 the_info->branch_delay_insns = 0;
9942 the_info->data_size = 0;
9943 the_info->target = target;
9944 the_info->target2 = 0;
9945 }
9946 (*info->print_address_func) (target, info);
9947 }
9948 else
9949 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
9950 needcomma = 1;
9951 }
9952
9953 for (i = 0; i < MAX_OPERANDS; i++)
9954 if (op_index[i] != -1 && op_riprel[i])
9955 {
9956 (*info->fprintf_func) (info->stream, " # ");
9957 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
9958 + op_address[op_index[i]]), info);
9959 break;
9960 }
9961 return codep - priv.the_buffer;
9962 }
9963
9964 static const char *float_mem[] = {
9965 /* d8 */
9966 "fadd{s|}",
9967 "fmul{s|}",
9968 "fcom{s|}",
9969 "fcomp{s|}",
9970 "fsub{s|}",
9971 "fsubr{s|}",
9972 "fdiv{s|}",
9973 "fdivr{s|}",
9974 /* d9 */
9975 "fld{s|}",
9976 "(bad)",
9977 "fst{s|}",
9978 "fstp{s|}",
9979 "fldenv{C|C}",
9980 "fldcw",
9981 "fNstenv{C|C}",
9982 "fNstcw",
9983 /* da */
9984 "fiadd{l|}",
9985 "fimul{l|}",
9986 "ficom{l|}",
9987 "ficomp{l|}",
9988 "fisub{l|}",
9989 "fisubr{l|}",
9990 "fidiv{l|}",
9991 "fidivr{l|}",
9992 /* db */
9993 "fild{l|}",
9994 "fisttp{l|}",
9995 "fist{l|}",
9996 "fistp{l|}",
9997 "(bad)",
9998 "fld{t|}",
9999 "(bad)",
10000 "fstp{t|}",
10001 /* dc */
10002 "fadd{l|}",
10003 "fmul{l|}",
10004 "fcom{l|}",
10005 "fcomp{l|}",
10006 "fsub{l|}",
10007 "fsubr{l|}",
10008 "fdiv{l|}",
10009 "fdivr{l|}",
10010 /* dd */
10011 "fld{l|}",
10012 "fisttp{ll|}",
10013 "fst{l||}",
10014 "fstp{l|}",
10015 "frstor{C|C}",
10016 "(bad)",
10017 "fNsave{C|C}",
10018 "fNstsw",
10019 /* de */
10020 "fiadd{s|}",
10021 "fimul{s|}",
10022 "ficom{s|}",
10023 "ficomp{s|}",
10024 "fisub{s|}",
10025 "fisubr{s|}",
10026 "fidiv{s|}",
10027 "fidivr{s|}",
10028 /* df */
10029 "fild{s|}",
10030 "fisttp{s|}",
10031 "fist{s|}",
10032 "fistp{s|}",
10033 "fbld",
10034 "fild{ll|}",
10035 "fbstp",
10036 "fistp{ll|}",
10037 };
10038
10039 static const unsigned char float_mem_mode[] = {
10040 /* d8 */
10041 d_mode,
10042 d_mode,
10043 d_mode,
10044 d_mode,
10045 d_mode,
10046 d_mode,
10047 d_mode,
10048 d_mode,
10049 /* d9 */
10050 d_mode,
10051 0,
10052 d_mode,
10053 d_mode,
10054 0,
10055 w_mode,
10056 0,
10057 w_mode,
10058 /* da */
10059 d_mode,
10060 d_mode,
10061 d_mode,
10062 d_mode,
10063 d_mode,
10064 d_mode,
10065 d_mode,
10066 d_mode,
10067 /* db */
10068 d_mode,
10069 d_mode,
10070 d_mode,
10071 d_mode,
10072 0,
10073 t_mode,
10074 0,
10075 t_mode,
10076 /* dc */
10077 q_mode,
10078 q_mode,
10079 q_mode,
10080 q_mode,
10081 q_mode,
10082 q_mode,
10083 q_mode,
10084 q_mode,
10085 /* dd */
10086 q_mode,
10087 q_mode,
10088 q_mode,
10089 q_mode,
10090 0,
10091 0,
10092 0,
10093 w_mode,
10094 /* de */
10095 w_mode,
10096 w_mode,
10097 w_mode,
10098 w_mode,
10099 w_mode,
10100 w_mode,
10101 w_mode,
10102 w_mode,
10103 /* df */
10104 w_mode,
10105 w_mode,
10106 w_mode,
10107 w_mode,
10108 t_mode,
10109 q_mode,
10110 t_mode,
10111 q_mode
10112 };
10113
10114 #define ST { OP_ST, 0 }
10115 #define STi { OP_STi, 0 }
10116
10117 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10118 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10119 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10120 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10121 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10122 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10123 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10124 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10125 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10126
10127 static const struct dis386 float_reg[][8] = {
10128 /* d8 */
10129 {
10130 { "fadd", { ST, STi }, 0 },
10131 { "fmul", { ST, STi }, 0 },
10132 { "fcom", { STi }, 0 },
10133 { "fcomp", { STi }, 0 },
10134 { "fsub", { ST, STi }, 0 },
10135 { "fsubr", { ST, STi }, 0 },
10136 { "fdiv", { ST, STi }, 0 },
10137 { "fdivr", { ST, STi }, 0 },
10138 },
10139 /* d9 */
10140 {
10141 { "fld", { STi }, 0 },
10142 { "fxch", { STi }, 0 },
10143 { FGRPd9_2 },
10144 { Bad_Opcode },
10145 { FGRPd9_4 },
10146 { FGRPd9_5 },
10147 { FGRPd9_6 },
10148 { FGRPd9_7 },
10149 },
10150 /* da */
10151 {
10152 { "fcmovb", { ST, STi }, 0 },
10153 { "fcmove", { ST, STi }, 0 },
10154 { "fcmovbe",{ ST, STi }, 0 },
10155 { "fcmovu", { ST, STi }, 0 },
10156 { Bad_Opcode },
10157 { FGRPda_5 },
10158 { Bad_Opcode },
10159 { Bad_Opcode },
10160 },
10161 /* db */
10162 {
10163 { "fcmovnb",{ ST, STi }, 0 },
10164 { "fcmovne",{ ST, STi }, 0 },
10165 { "fcmovnbe",{ ST, STi }, 0 },
10166 { "fcmovnu",{ ST, STi }, 0 },
10167 { FGRPdb_4 },
10168 { "fucomi", { ST, STi }, 0 },
10169 { "fcomi", { ST, STi }, 0 },
10170 { Bad_Opcode },
10171 },
10172 /* dc */
10173 {
10174 { "fadd", { STi, ST }, 0 },
10175 { "fmul", { STi, ST }, 0 },
10176 { Bad_Opcode },
10177 { Bad_Opcode },
10178 { "fsub{!M|r}", { STi, ST }, 0 },
10179 { "fsub{M|}", { STi, ST }, 0 },
10180 { "fdiv{!M|r}", { STi, ST }, 0 },
10181 { "fdiv{M|}", { STi, ST }, 0 },
10182 },
10183 /* dd */
10184 {
10185 { "ffree", { STi }, 0 },
10186 { Bad_Opcode },
10187 { "fst", { STi }, 0 },
10188 { "fstp", { STi }, 0 },
10189 { "fucom", { STi }, 0 },
10190 { "fucomp", { STi }, 0 },
10191 { Bad_Opcode },
10192 { Bad_Opcode },
10193 },
10194 /* de */
10195 {
10196 { "faddp", { STi, ST }, 0 },
10197 { "fmulp", { STi, ST }, 0 },
10198 { Bad_Opcode },
10199 { FGRPde_3 },
10200 { "fsub{!M|r}p", { STi, ST }, 0 },
10201 { "fsub{M|}p", { STi, ST }, 0 },
10202 { "fdiv{!M|r}p", { STi, ST }, 0 },
10203 { "fdiv{M|}p", { STi, ST }, 0 },
10204 },
10205 /* df */
10206 {
10207 { "ffreep", { STi }, 0 },
10208 { Bad_Opcode },
10209 { Bad_Opcode },
10210 { Bad_Opcode },
10211 { FGRPdf_4 },
10212 { "fucomip", { ST, STi }, 0 },
10213 { "fcomip", { ST, STi }, 0 },
10214 { Bad_Opcode },
10215 },
10216 };
10217
10218 static char *fgrps[][8] = {
10219 /* Bad opcode 0 */
10220 {
10221 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10222 },
10223
10224 /* d9_2 1 */
10225 {
10226 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10227 },
10228
10229 /* d9_4 2 */
10230 {
10231 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10232 },
10233
10234 /* d9_5 3 */
10235 {
10236 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10237 },
10238
10239 /* d9_6 4 */
10240 {
10241 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10242 },
10243
10244 /* d9_7 5 */
10245 {
10246 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10247 },
10248
10249 /* da_5 6 */
10250 {
10251 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10252 },
10253
10254 /* db_4 7 */
10255 {
10256 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10257 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10258 },
10259
10260 /* de_3 8 */
10261 {
10262 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10263 },
10264
10265 /* df_4 9 */
10266 {
10267 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10268 },
10269 };
10270
10271 static void
10272 swap_operand (void)
10273 {
10274 mnemonicendp[0] = '.';
10275 mnemonicendp[1] = 's';
10276 mnemonicendp += 2;
10277 }
10278
10279 static void
10280 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10281 int sizeflag ATTRIBUTE_UNUSED)
10282 {
10283 /* Skip mod/rm byte. */
10284 MODRM_CHECK;
10285 codep++;
10286 }
10287
10288 static void
10289 dofloat (int sizeflag)
10290 {
10291 const struct dis386 *dp;
10292 unsigned char floatop;
10293
10294 floatop = codep[-1];
10295
10296 if (modrm.mod != 3)
10297 {
10298 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10299
10300 putop (float_mem[fp_indx], sizeflag);
10301 obufp = op_out[0];
10302 op_ad = 2;
10303 OP_E (float_mem_mode[fp_indx], sizeflag);
10304 return;
10305 }
10306 /* Skip mod/rm byte. */
10307 MODRM_CHECK;
10308 codep++;
10309
10310 dp = &float_reg[floatop - 0xd8][modrm.reg];
10311 if (dp->name == NULL)
10312 {
10313 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10314
10315 /* Instruction fnstsw is only one with strange arg. */
10316 if (floatop == 0xdf && codep[-1] == 0xe0)
10317 strcpy (op_out[0], names16[0]);
10318 }
10319 else
10320 {
10321 putop (dp->name, sizeflag);
10322
10323 obufp = op_out[0];
10324 op_ad = 2;
10325 if (dp->op[0].rtn)
10326 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10327
10328 obufp = op_out[1];
10329 op_ad = 1;
10330 if (dp->op[1].rtn)
10331 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10332 }
10333 }
10334
10335 /* Like oappend (below), but S is a string starting with '%'.
10336 In Intel syntax, the '%' is elided. */
10337 static void
10338 oappend_maybe_intel (const char *s)
10339 {
10340 oappend (s + intel_syntax);
10341 }
10342
10343 static void
10344 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10345 {
10346 oappend_maybe_intel ("%st");
10347 }
10348
10349 static void
10350 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10351 {
10352 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10353 oappend_maybe_intel (scratchbuf);
10354 }
10355
10356 /* Capital letters in template are macros. */
10357 static int
10358 putop (const char *in_template, int sizeflag)
10359 {
10360 const char *p;
10361 int alt = 0;
10362 int cond = 1;
10363 unsigned int l = 0, len = 0;
10364 char last[4];
10365
10366 for (p = in_template; *p; p++)
10367 {
10368 if (len > l)
10369 {
10370 if (l >= sizeof (last) || !ISUPPER (*p))
10371 abort ();
10372 last[l++] = *p;
10373 continue;
10374 }
10375 switch (*p)
10376 {
10377 default:
10378 *obufp++ = *p;
10379 break;
10380 case '%':
10381 len++;
10382 break;
10383 case '!':
10384 cond = 0;
10385 break;
10386 case '{':
10387 if (intel_syntax)
10388 {
10389 while (*++p != '|')
10390 if (*p == '}' || *p == '\0')
10391 abort ();
10392 alt = 1;
10393 }
10394 break;
10395 case '|':
10396 while (*++p != '}')
10397 {
10398 if (*p == '\0')
10399 abort ();
10400 }
10401 break;
10402 case '}':
10403 alt = 0;
10404 break;
10405 case 'A':
10406 if (intel_syntax)
10407 break;
10408 if ((need_modrm && modrm.mod != 3)
10409 || (sizeflag & SUFFIX_ALWAYS))
10410 *obufp++ = 'b';
10411 break;
10412 case 'B':
10413 if (l == 0)
10414 {
10415 case_B:
10416 if (intel_syntax)
10417 break;
10418 if (sizeflag & SUFFIX_ALWAYS)
10419 *obufp++ = 'b';
10420 }
10421 else if (l == 1 && last[0] == 'L')
10422 {
10423 if (address_mode == mode_64bit
10424 && !(prefixes & PREFIX_ADDR))
10425 {
10426 *obufp++ = 'a';
10427 *obufp++ = 'b';
10428 *obufp++ = 's';
10429 }
10430
10431 goto case_B;
10432 }
10433 else
10434 abort ();
10435 break;
10436 case 'C':
10437 if (intel_syntax && !alt)
10438 break;
10439 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10440 {
10441 if (sizeflag & DFLAG)
10442 *obufp++ = intel_syntax ? 'd' : 'l';
10443 else
10444 *obufp++ = intel_syntax ? 'w' : 's';
10445 used_prefixes |= (prefixes & PREFIX_DATA);
10446 }
10447 break;
10448 case 'D':
10449 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10450 break;
10451 USED_REX (REX_W);
10452 if (modrm.mod == 3)
10453 {
10454 if (rex & REX_W)
10455 *obufp++ = 'q';
10456 else
10457 {
10458 if (sizeflag & DFLAG)
10459 *obufp++ = intel_syntax ? 'd' : 'l';
10460 else
10461 *obufp++ = 'w';
10462 used_prefixes |= (prefixes & PREFIX_DATA);
10463 }
10464 }
10465 else
10466 *obufp++ = 'w';
10467 break;
10468 case 'E': /* For jcxz/jecxz */
10469 if (address_mode == mode_64bit)
10470 {
10471 if (sizeflag & AFLAG)
10472 *obufp++ = 'r';
10473 else
10474 *obufp++ = 'e';
10475 }
10476 else
10477 if (sizeflag & AFLAG)
10478 *obufp++ = 'e';
10479 used_prefixes |= (prefixes & PREFIX_ADDR);
10480 break;
10481 case 'F':
10482 if (intel_syntax)
10483 break;
10484 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10485 {
10486 if (sizeflag & AFLAG)
10487 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10488 else
10489 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10490 used_prefixes |= (prefixes & PREFIX_ADDR);
10491 }
10492 break;
10493 case 'G':
10494 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10495 break;
10496 if ((rex & REX_W) || (sizeflag & DFLAG))
10497 *obufp++ = 'l';
10498 else
10499 *obufp++ = 'w';
10500 if (!(rex & REX_W))
10501 used_prefixes |= (prefixes & PREFIX_DATA);
10502 break;
10503 case 'H':
10504 if (intel_syntax)
10505 break;
10506 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10507 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10508 {
10509 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10510 *obufp++ = ',';
10511 *obufp++ = 'p';
10512
10513 /* Set active_seg_prefix even if not set in 64-bit mode
10514 because here it is a valid branch hint. */
10515 if (prefixes & PREFIX_DS)
10516 {
10517 active_seg_prefix = PREFIX_DS;
10518 *obufp++ = 't';
10519 }
10520 else
10521 {
10522 active_seg_prefix = PREFIX_CS;
10523 *obufp++ = 'n';
10524 }
10525 }
10526 break;
10527 case 'K':
10528 USED_REX (REX_W);
10529 if (rex & REX_W)
10530 *obufp++ = 'q';
10531 else
10532 *obufp++ = 'd';
10533 break;
10534 case 'L':
10535 abort ();
10536 case 'M':
10537 if (intel_mnemonic != cond)
10538 *obufp++ = 'r';
10539 break;
10540 case 'N':
10541 if ((prefixes & PREFIX_FWAIT) == 0)
10542 *obufp++ = 'n';
10543 else
10544 used_prefixes |= PREFIX_FWAIT;
10545 break;
10546 case 'O':
10547 USED_REX (REX_W);
10548 if (rex & REX_W)
10549 *obufp++ = 'o';
10550 else if (intel_syntax && (sizeflag & DFLAG))
10551 *obufp++ = 'q';
10552 else
10553 *obufp++ = 'd';
10554 if (!(rex & REX_W))
10555 used_prefixes |= (prefixes & PREFIX_DATA);
10556 break;
10557 case '@':
10558 if (address_mode == mode_64bit
10559 && (isa64 == intel64 || (rex & REX_W)
10560 || !(prefixes & PREFIX_DATA)))
10561 {
10562 if (sizeflag & SUFFIX_ALWAYS)
10563 *obufp++ = 'q';
10564 break;
10565 }
10566 /* Fall through. */
10567 case 'P':
10568 if (l == 0)
10569 {
10570 if ((modrm.mod == 3 || !cond)
10571 && !(sizeflag & SUFFIX_ALWAYS))
10572 break;
10573 /* Fall through. */
10574 case 'T':
10575 if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
10576 || ((sizeflag & SUFFIX_ALWAYS)
10577 && address_mode != mode_64bit))
10578 {
10579 *obufp++ = (sizeflag & DFLAG) ?
10580 intel_syntax ? 'd' : 'l' : 'w';
10581 used_prefixes |= (prefixes & PREFIX_DATA);
10582 }
10583 else if (sizeflag & SUFFIX_ALWAYS)
10584 *obufp++ = 'q';
10585 }
10586 else if (l == 1 && last[0] == 'L')
10587 {
10588 if ((prefixes & PREFIX_DATA)
10589 || (rex & REX_W)
10590 || (sizeflag & SUFFIX_ALWAYS))
10591 {
10592 USED_REX (REX_W);
10593 if (rex & REX_W)
10594 *obufp++ = 'q';
10595 else
10596 {
10597 if (sizeflag & DFLAG)
10598 *obufp++ = intel_syntax ? 'd' : 'l';
10599 else
10600 *obufp++ = 'w';
10601 used_prefixes |= (prefixes & PREFIX_DATA);
10602 }
10603 }
10604 }
10605 else
10606 abort ();
10607 break;
10608 case 'Q':
10609 if (l == 0)
10610 {
10611 if (intel_syntax && !alt)
10612 break;
10613 USED_REX (REX_W);
10614 if ((need_modrm && modrm.mod != 3)
10615 || (sizeflag & SUFFIX_ALWAYS))
10616 {
10617 if (rex & REX_W)
10618 *obufp++ = 'q';
10619 else
10620 {
10621 if (sizeflag & DFLAG)
10622 *obufp++ = intel_syntax ? 'd' : 'l';
10623 else
10624 *obufp++ = 'w';
10625 used_prefixes |= (prefixes & PREFIX_DATA);
10626 }
10627 }
10628 }
10629 else if (l == 1 && last[0] == 'D')
10630 *obufp++ = vex.w ? 'q' : 'd';
10631 else if (l == 1 && last[0] == 'L')
10632 {
10633 if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10634 : address_mode != mode_64bit)
10635 break;
10636 if ((rex & REX_W))
10637 {
10638 USED_REX (REX_W);
10639 *obufp++ = 'q';
10640 }
10641 else if((address_mode == mode_64bit && cond)
10642 || (sizeflag & SUFFIX_ALWAYS))
10643 *obufp++ = intel_syntax? 'd' : 'l';
10644 }
10645 else
10646 abort ();
10647 break;
10648 case 'R':
10649 USED_REX (REX_W);
10650 if (rex & REX_W)
10651 *obufp++ = 'q';
10652 else if (sizeflag & DFLAG)
10653 {
10654 if (intel_syntax)
10655 *obufp++ = 'd';
10656 else
10657 *obufp++ = 'l';
10658 }
10659 else
10660 *obufp++ = 'w';
10661 if (intel_syntax && !p[1]
10662 && ((rex & REX_W) || (sizeflag & DFLAG)))
10663 *obufp++ = 'e';
10664 if (!(rex & REX_W))
10665 used_prefixes |= (prefixes & PREFIX_DATA);
10666 break;
10667 case 'S':
10668 if (l == 0)
10669 {
10670 case_S:
10671 if (intel_syntax)
10672 break;
10673 if (sizeflag & SUFFIX_ALWAYS)
10674 {
10675 if (rex & REX_W)
10676 *obufp++ = 'q';
10677 else
10678 {
10679 if (sizeflag & DFLAG)
10680 *obufp++ = 'l';
10681 else
10682 *obufp++ = 'w';
10683 used_prefixes |= (prefixes & PREFIX_DATA);
10684 }
10685 }
10686 }
10687 else if (l == 1 && last[0] == 'L')
10688 {
10689 if (address_mode == mode_64bit
10690 && !(prefixes & PREFIX_ADDR))
10691 {
10692 *obufp++ = 'a';
10693 *obufp++ = 'b';
10694 *obufp++ = 's';
10695 }
10696
10697 goto case_S;
10698 }
10699 else
10700 abort ();
10701 break;
10702 case 'V':
10703 if (l == 0)
10704 abort ();
10705 else if (l == 1
10706 && (last[0] == 'L' || last[0] == 'X'))
10707 {
10708 if (last[0] == 'X')
10709 {
10710 *obufp++ = '{';
10711 *obufp++ = 'v';
10712 *obufp++ = 'e';
10713 *obufp++ = 'x';
10714 *obufp++ = '}';
10715 }
10716 else if (rex & REX_W)
10717 {
10718 *obufp++ = 'a';
10719 *obufp++ = 'b';
10720 *obufp++ = 's';
10721 }
10722 }
10723 else
10724 abort ();
10725 goto case_S;
10726 case 'W':
10727 if (l == 0)
10728 {
10729 /* operand size flag for cwtl, cbtw */
10730 USED_REX (REX_W);
10731 if (rex & REX_W)
10732 {
10733 if (intel_syntax)
10734 *obufp++ = 'd';
10735 else
10736 *obufp++ = 'l';
10737 }
10738 else if (sizeflag & DFLAG)
10739 *obufp++ = 'w';
10740 else
10741 *obufp++ = 'b';
10742 if (!(rex & REX_W))
10743 used_prefixes |= (prefixes & PREFIX_DATA);
10744 }
10745 else if (l == 1)
10746 {
10747 if (!need_vex)
10748 abort ();
10749 if (last[0] == 'X')
10750 *obufp++ = vex.w ? 'd': 's';
10751 else if (last[0] == 'B')
10752 *obufp++ = vex.w ? 'w': 'b';
10753 else
10754 abort ();
10755 }
10756 else
10757 abort ();
10758 break;
10759 case 'X':
10760 if (l != 0)
10761 abort ();
10762 if (need_vex
10763 ? vex.prefix == DATA_PREFIX_OPCODE
10764 : prefixes & PREFIX_DATA)
10765 {
10766 *obufp++ = 'd';
10767 used_prefixes |= PREFIX_DATA;
10768 }
10769 else
10770 *obufp++ = 's';
10771 break;
10772 case 'Y':
10773 if (l == 1 && last[0] == 'X')
10774 {
10775 if (!need_vex)
10776 abort ();
10777 if (intel_syntax
10778 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10779 break;
10780 switch (vex.length)
10781 {
10782 case 128:
10783 *obufp++ = 'x';
10784 break;
10785 case 256:
10786 *obufp++ = 'y';
10787 break;
10788 case 512:
10789 if (!vex.evex)
10790 default:
10791 abort ();
10792 }
10793 }
10794 else
10795 abort ();
10796 break;
10797 case 'Z':
10798 if (l == 0)
10799 {
10800 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10801 modrm.mod = 3;
10802 if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10803 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10804 }
10805 else if (l == 1 && last[0] == 'X')
10806 {
10807 if (!need_vex || !vex.evex)
10808 abort ();
10809 if (intel_syntax
10810 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
10811 break;
10812 switch (vex.length)
10813 {
10814 case 128:
10815 *obufp++ = 'x';
10816 break;
10817 case 256:
10818 *obufp++ = 'y';
10819 break;
10820 case 512:
10821 *obufp++ = 'z';
10822 break;
10823 default:
10824 abort ();
10825 }
10826 }
10827 else
10828 abort ();
10829 break;
10830 case '^':
10831 if (intel_syntax)
10832 break;
10833 if (isa64 == intel64 && (rex & REX_W))
10834 {
10835 USED_REX (REX_W);
10836 *obufp++ = 'q';
10837 break;
10838 }
10839 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10840 {
10841 if (sizeflag & DFLAG)
10842 *obufp++ = 'l';
10843 else
10844 *obufp++ = 'w';
10845 used_prefixes |= (prefixes & PREFIX_DATA);
10846 }
10847 break;
10848 }
10849
10850 if (len == l)
10851 len = l = 0;
10852 }
10853 *obufp = 0;
10854 mnemonicendp = obufp;
10855 return 0;
10856 }
10857
10858 static void
10859 oappend (const char *s)
10860 {
10861 obufp = stpcpy (obufp, s);
10862 }
10863
10864 static void
10865 append_seg (void)
10866 {
10867 /* Only print the active segment register. */
10868 if (!active_seg_prefix)
10869 return;
10870
10871 used_prefixes |= active_seg_prefix;
10872 switch (active_seg_prefix)
10873 {
10874 case PREFIX_CS:
10875 oappend_maybe_intel ("%cs:");
10876 break;
10877 case PREFIX_DS:
10878 oappend_maybe_intel ("%ds:");
10879 break;
10880 case PREFIX_SS:
10881 oappend_maybe_intel ("%ss:");
10882 break;
10883 case PREFIX_ES:
10884 oappend_maybe_intel ("%es:");
10885 break;
10886 case PREFIX_FS:
10887 oappend_maybe_intel ("%fs:");
10888 break;
10889 case PREFIX_GS:
10890 oappend_maybe_intel ("%gs:");
10891 break;
10892 default:
10893 break;
10894 }
10895 }
10896
10897 static void
10898 OP_indirE (int bytemode, int sizeflag)
10899 {
10900 if (!intel_syntax)
10901 oappend ("*");
10902 OP_E (bytemode, sizeflag);
10903 }
10904
10905 static void
10906 print_operand_value (char *buf, int hex, bfd_vma disp)
10907 {
10908 if (address_mode == mode_64bit)
10909 {
10910 if (hex)
10911 {
10912 char tmp[30];
10913 int i;
10914 buf[0] = '0';
10915 buf[1] = 'x';
10916 sprintf_vma (tmp, disp);
10917 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
10918 strcpy (buf + 2, tmp + i);
10919 }
10920 else
10921 {
10922 bfd_signed_vma v = disp;
10923 char tmp[30];
10924 int i;
10925 if (v < 0)
10926 {
10927 *(buf++) = '-';
10928 v = -disp;
10929 /* Check for possible overflow on 0x8000000000000000. */
10930 if (v < 0)
10931 {
10932 strcpy (buf, "9223372036854775808");
10933 return;
10934 }
10935 }
10936 if (!v)
10937 {
10938 strcpy (buf, "0");
10939 return;
10940 }
10941
10942 i = 0;
10943 tmp[29] = 0;
10944 while (v)
10945 {
10946 tmp[28 - i] = (v % 10) + '0';
10947 v /= 10;
10948 i++;
10949 }
10950 strcpy (buf, tmp + 29 - i);
10951 }
10952 }
10953 else
10954 {
10955 if (hex)
10956 sprintf (buf, "0x%x", (unsigned int) disp);
10957 else
10958 sprintf (buf, "%d", (int) disp);
10959 }
10960 }
10961
10962 /* Put DISP in BUF as signed hex number. */
10963
10964 static void
10965 print_displacement (char *buf, bfd_vma disp)
10966 {
10967 bfd_signed_vma val = disp;
10968 char tmp[30];
10969 int i, j = 0;
10970
10971 if (val < 0)
10972 {
10973 buf[j++] = '-';
10974 val = -disp;
10975
10976 /* Check for possible overflow. */
10977 if (val < 0)
10978 {
10979 switch (address_mode)
10980 {
10981 case mode_64bit:
10982 strcpy (buf + j, "0x8000000000000000");
10983 break;
10984 case mode_32bit:
10985 strcpy (buf + j, "0x80000000");
10986 break;
10987 case mode_16bit:
10988 strcpy (buf + j, "0x8000");
10989 break;
10990 }
10991 return;
10992 }
10993 }
10994
10995 buf[j++] = '0';
10996 buf[j++] = 'x';
10997
10998 sprintf_vma (tmp, (bfd_vma) val);
10999 for (i = 0; tmp[i] == '0'; i++)
11000 continue;
11001 if (tmp[i] == '\0')
11002 i--;
11003 strcpy (buf + j, tmp + i);
11004 }
11005
11006 static void
11007 intel_operand_size (int bytemode, int sizeflag)
11008 {
11009 if (vex.evex
11010 && vex.b
11011 && (bytemode == x_mode
11012 || bytemode == evex_half_bcst_xmmq_mode))
11013 {
11014 if (vex.w)
11015 oappend ("QWORD PTR ");
11016 else
11017 oappend ("DWORD PTR ");
11018 return;
11019 }
11020 switch (bytemode)
11021 {
11022 case b_mode:
11023 case b_swap_mode:
11024 case dqb_mode:
11025 case db_mode:
11026 oappend ("BYTE PTR ");
11027 break;
11028 case w_mode:
11029 case dw_mode:
11030 case dqw_mode:
11031 oappend ("WORD PTR ");
11032 break;
11033 case indir_v_mode:
11034 if (address_mode == mode_64bit && isa64 == intel64)
11035 {
11036 oappend ("QWORD PTR ");
11037 break;
11038 }
11039 /* Fall through. */
11040 case stack_v_mode:
11041 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11042 {
11043 oappend ("QWORD PTR ");
11044 break;
11045 }
11046 /* Fall through. */
11047 case v_mode:
11048 case v_swap_mode:
11049 case dq_mode:
11050 USED_REX (REX_W);
11051 if (rex & REX_W)
11052 oappend ("QWORD PTR ");
11053 else if (bytemode == dq_mode)
11054 oappend ("DWORD PTR ");
11055 else
11056 {
11057 if (sizeflag & DFLAG)
11058 oappend ("DWORD PTR ");
11059 else
11060 oappend ("WORD PTR ");
11061 used_prefixes |= (prefixes & PREFIX_DATA);
11062 }
11063 break;
11064 case z_mode:
11065 if ((rex & REX_W) || (sizeflag & DFLAG))
11066 *obufp++ = 'D';
11067 oappend ("WORD PTR ");
11068 if (!(rex & REX_W))
11069 used_prefixes |= (prefixes & PREFIX_DATA);
11070 break;
11071 case a_mode:
11072 if (sizeflag & DFLAG)
11073 oappend ("QWORD PTR ");
11074 else
11075 oappend ("DWORD PTR ");
11076 used_prefixes |= (prefixes & PREFIX_DATA);
11077 break;
11078 case movsxd_mode:
11079 if (!(sizeflag & DFLAG) && isa64 == intel64)
11080 oappend ("WORD PTR ");
11081 else
11082 oappend ("DWORD PTR ");
11083 used_prefixes |= (prefixes & PREFIX_DATA);
11084 break;
11085 case d_mode:
11086 case d_swap_mode:
11087 case dqd_mode:
11088 oappend ("DWORD PTR ");
11089 break;
11090 case q_mode:
11091 case q_swap_mode:
11092 oappend ("QWORD PTR ");
11093 break;
11094 case m_mode:
11095 if (address_mode == mode_64bit)
11096 oappend ("QWORD PTR ");
11097 else
11098 oappend ("DWORD PTR ");
11099 break;
11100 case f_mode:
11101 if (sizeflag & DFLAG)
11102 oappend ("FWORD PTR ");
11103 else
11104 oappend ("DWORD PTR ");
11105 used_prefixes |= (prefixes & PREFIX_DATA);
11106 break;
11107 case t_mode:
11108 oappend ("TBYTE PTR ");
11109 break;
11110 case x_mode:
11111 case x_swap_mode:
11112 case evex_x_gscat_mode:
11113 case evex_x_nobcst_mode:
11114 case bw_unit_mode:
11115 if (need_vex)
11116 {
11117 switch (vex.length)
11118 {
11119 case 128:
11120 oappend ("XMMWORD PTR ");
11121 break;
11122 case 256:
11123 oappend ("YMMWORD PTR ");
11124 break;
11125 case 512:
11126 oappend ("ZMMWORD PTR ");
11127 break;
11128 default:
11129 abort ();
11130 }
11131 }
11132 else
11133 oappend ("XMMWORD PTR ");
11134 break;
11135 case xmm_mode:
11136 oappend ("XMMWORD PTR ");
11137 break;
11138 case ymm_mode:
11139 oappend ("YMMWORD PTR ");
11140 break;
11141 case xmmq_mode:
11142 case evex_half_bcst_xmmq_mode:
11143 if (!need_vex)
11144 abort ();
11145
11146 switch (vex.length)
11147 {
11148 case 128:
11149 oappend ("QWORD PTR ");
11150 break;
11151 case 256:
11152 oappend ("XMMWORD PTR ");
11153 break;
11154 case 512:
11155 oappend ("YMMWORD PTR ");
11156 break;
11157 default:
11158 abort ();
11159 }
11160 break;
11161 case xmm_mb_mode:
11162 if (!need_vex)
11163 abort ();
11164
11165 switch (vex.length)
11166 {
11167 case 128:
11168 case 256:
11169 case 512:
11170 oappend ("BYTE PTR ");
11171 break;
11172 default:
11173 abort ();
11174 }
11175 break;
11176 case xmm_mw_mode:
11177 if (!need_vex)
11178 abort ();
11179
11180 switch (vex.length)
11181 {
11182 case 128:
11183 case 256:
11184 case 512:
11185 oappend ("WORD PTR ");
11186 break;
11187 default:
11188 abort ();
11189 }
11190 break;
11191 case xmm_md_mode:
11192 if (!need_vex)
11193 abort ();
11194
11195 switch (vex.length)
11196 {
11197 case 128:
11198 case 256:
11199 case 512:
11200 oappend ("DWORD PTR ");
11201 break;
11202 default:
11203 abort ();
11204 }
11205 break;
11206 case xmm_mq_mode:
11207 if (!need_vex)
11208 abort ();
11209
11210 switch (vex.length)
11211 {
11212 case 128:
11213 case 256:
11214 case 512:
11215 oappend ("QWORD PTR ");
11216 break;
11217 default:
11218 abort ();
11219 }
11220 break;
11221 case xmmdw_mode:
11222 if (!need_vex)
11223 abort ();
11224
11225 switch (vex.length)
11226 {
11227 case 128:
11228 oappend ("WORD PTR ");
11229 break;
11230 case 256:
11231 oappend ("DWORD PTR ");
11232 break;
11233 case 512:
11234 oappend ("QWORD PTR ");
11235 break;
11236 default:
11237 abort ();
11238 }
11239 break;
11240 case xmmqd_mode:
11241 if (!need_vex)
11242 abort ();
11243
11244 switch (vex.length)
11245 {
11246 case 128:
11247 oappend ("DWORD PTR ");
11248 break;
11249 case 256:
11250 oappend ("QWORD PTR ");
11251 break;
11252 case 512:
11253 oappend ("XMMWORD PTR ");
11254 break;
11255 default:
11256 abort ();
11257 }
11258 break;
11259 case ymmq_mode:
11260 if (!need_vex)
11261 abort ();
11262
11263 switch (vex.length)
11264 {
11265 case 128:
11266 oappend ("QWORD PTR ");
11267 break;
11268 case 256:
11269 oappend ("YMMWORD PTR ");
11270 break;
11271 case 512:
11272 oappend ("ZMMWORD PTR ");
11273 break;
11274 default:
11275 abort ();
11276 }
11277 break;
11278 case ymmxmm_mode:
11279 if (!need_vex)
11280 abort ();
11281
11282 switch (vex.length)
11283 {
11284 case 128:
11285 case 256:
11286 oappend ("XMMWORD PTR ");
11287 break;
11288 default:
11289 abort ();
11290 }
11291 break;
11292 case o_mode:
11293 oappend ("OWORD PTR ");
11294 break;
11295 case vex_scalar_w_dq_mode:
11296 if (!need_vex)
11297 abort ();
11298
11299 if (vex.w)
11300 oappend ("QWORD PTR ");
11301 else
11302 oappend ("DWORD PTR ");
11303 break;
11304 case vex_vsib_d_w_dq_mode:
11305 case vex_vsib_q_w_dq_mode:
11306 if (!need_vex)
11307 abort ();
11308
11309 if (!vex.evex)
11310 {
11311 if (vex.w)
11312 oappend ("QWORD PTR ");
11313 else
11314 oappend ("DWORD PTR ");
11315 }
11316 else
11317 {
11318 switch (vex.length)
11319 {
11320 case 128:
11321 oappend ("XMMWORD PTR ");
11322 break;
11323 case 256:
11324 oappend ("YMMWORD PTR ");
11325 break;
11326 case 512:
11327 oappend ("ZMMWORD PTR ");
11328 break;
11329 default:
11330 abort ();
11331 }
11332 }
11333 break;
11334 case vex_vsib_q_w_d_mode:
11335 case vex_vsib_d_w_d_mode:
11336 if (!need_vex || !vex.evex)
11337 abort ();
11338
11339 switch (vex.length)
11340 {
11341 case 128:
11342 oappend ("QWORD PTR ");
11343 break;
11344 case 256:
11345 oappend ("XMMWORD PTR ");
11346 break;
11347 case 512:
11348 oappend ("YMMWORD PTR ");
11349 break;
11350 default:
11351 abort ();
11352 }
11353
11354 break;
11355 case mask_bd_mode:
11356 if (!need_vex || vex.length != 128)
11357 abort ();
11358 if (vex.w)
11359 oappend ("DWORD PTR ");
11360 else
11361 oappend ("BYTE PTR ");
11362 break;
11363 case mask_mode:
11364 if (!need_vex)
11365 abort ();
11366 if (vex.w)
11367 oappend ("QWORD PTR ");
11368 else
11369 oappend ("WORD PTR ");
11370 break;
11371 case v_bnd_mode:
11372 case v_bndmk_mode:
11373 default:
11374 break;
11375 }
11376 }
11377
11378 static void
11379 OP_E_register (int bytemode, int sizeflag)
11380 {
11381 int reg = modrm.rm;
11382 const char **names;
11383
11384 USED_REX (REX_B);
11385 if ((rex & REX_B))
11386 reg += 8;
11387
11388 if ((sizeflag & SUFFIX_ALWAYS)
11389 && (bytemode == b_swap_mode
11390 || bytemode == bnd_swap_mode
11391 || bytemode == v_swap_mode))
11392 swap_operand ();
11393
11394 switch (bytemode)
11395 {
11396 case b_mode:
11397 case b_swap_mode:
11398 if (reg & 4)
11399 USED_REX (0);
11400 if (rex)
11401 names = names8rex;
11402 else
11403 names = names8;
11404 break;
11405 case w_mode:
11406 names = names16;
11407 break;
11408 case d_mode:
11409 case dw_mode:
11410 case db_mode:
11411 names = names32;
11412 break;
11413 case q_mode:
11414 names = names64;
11415 break;
11416 case m_mode:
11417 case v_bnd_mode:
11418 names = address_mode == mode_64bit ? names64 : names32;
11419 break;
11420 case bnd_mode:
11421 case bnd_swap_mode:
11422 if (reg > 0x3)
11423 {
11424 oappend ("(bad)");
11425 return;
11426 }
11427 names = names_bnd;
11428 break;
11429 case indir_v_mode:
11430 if (address_mode == mode_64bit && isa64 == intel64)
11431 {
11432 names = names64;
11433 break;
11434 }
11435 /* Fall through. */
11436 case stack_v_mode:
11437 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
11438 {
11439 names = names64;
11440 break;
11441 }
11442 bytemode = v_mode;
11443 /* Fall through. */
11444 case v_mode:
11445 case v_swap_mode:
11446 case dq_mode:
11447 case dqb_mode:
11448 case dqd_mode:
11449 case dqw_mode:
11450 USED_REX (REX_W);
11451 if (rex & REX_W)
11452 names = names64;
11453 else if (bytemode != v_mode && bytemode != v_swap_mode)
11454 names = names32;
11455 else
11456 {
11457 if (sizeflag & DFLAG)
11458 names = names32;
11459 else
11460 names = names16;
11461 used_prefixes |= (prefixes & PREFIX_DATA);
11462 }
11463 break;
11464 case movsxd_mode:
11465 if (!(sizeflag & DFLAG) && isa64 == intel64)
11466 names = names16;
11467 else
11468 names = names32;
11469 used_prefixes |= (prefixes & PREFIX_DATA);
11470 break;
11471 case va_mode:
11472 names = (address_mode == mode_64bit
11473 ? names64 : names32);
11474 if (!(prefixes & PREFIX_ADDR))
11475 names = (address_mode == mode_16bit
11476 ? names16 : names);
11477 else
11478 {
11479 /* Remove "addr16/addr32". */
11480 all_prefixes[last_addr_prefix] = 0;
11481 names = (address_mode != mode_32bit
11482 ? names32 : names16);
11483 used_prefixes |= PREFIX_ADDR;
11484 }
11485 break;
11486 case mask_bd_mode:
11487 case mask_mode:
11488 if (reg > 0x7)
11489 {
11490 oappend ("(bad)");
11491 return;
11492 }
11493 names = names_mask;
11494 break;
11495 case 0:
11496 return;
11497 default:
11498 oappend (INTERNAL_DISASSEMBLER_ERROR);
11499 return;
11500 }
11501 oappend (names[reg]);
11502 }
11503
11504 static void
11505 OP_E_memory (int bytemode, int sizeflag)
11506 {
11507 bfd_vma disp = 0;
11508 int add = (rex & REX_B) ? 8 : 0;
11509 int riprel = 0;
11510 int shift;
11511
11512 if (vex.evex)
11513 {
11514 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
11515 if (vex.b
11516 && bytemode != x_mode
11517 && bytemode != xmmq_mode
11518 && bytemode != evex_half_bcst_xmmq_mode)
11519 {
11520 BadOp ();
11521 return;
11522 }
11523 switch (bytemode)
11524 {
11525 case dqw_mode:
11526 case dw_mode:
11527 case xmm_mw_mode:
11528 shift = 1;
11529 break;
11530 case dqb_mode:
11531 case db_mode:
11532 case xmm_mb_mode:
11533 shift = 0;
11534 break;
11535 case dq_mode:
11536 if (address_mode != mode_64bit)
11537 {
11538 case dqd_mode:
11539 case xmm_md_mode:
11540 case d_mode:
11541 case d_swap_mode:
11542 shift = 2;
11543 break;
11544 }
11545 /* fall through */
11546 case vex_scalar_w_dq_mode:
11547 case vex_vsib_d_w_dq_mode:
11548 case vex_vsib_d_w_d_mode:
11549 case vex_vsib_q_w_dq_mode:
11550 case vex_vsib_q_w_d_mode:
11551 case evex_x_gscat_mode:
11552 shift = vex.w ? 3 : 2;
11553 break;
11554 case x_mode:
11555 case evex_half_bcst_xmmq_mode:
11556 case xmmq_mode:
11557 if (vex.b)
11558 {
11559 shift = vex.w ? 3 : 2;
11560 break;
11561 }
11562 /* Fall through. */
11563 case xmmqd_mode:
11564 case xmmdw_mode:
11565 case ymmq_mode:
11566 case evex_x_nobcst_mode:
11567 case x_swap_mode:
11568 switch (vex.length)
11569 {
11570 case 128:
11571 shift = 4;
11572 break;
11573 case 256:
11574 shift = 5;
11575 break;
11576 case 512:
11577 shift = 6;
11578 break;
11579 default:
11580 abort ();
11581 }
11582 /* Make necessary corrections to shift for modes that need it. */
11583 if (bytemode == xmmq_mode
11584 || bytemode == evex_half_bcst_xmmq_mode
11585 || (bytemode == ymmq_mode && vex.length == 128))
11586 shift -= 1;
11587 else if (bytemode == xmmqd_mode)
11588 shift -= 2;
11589 else if (bytemode == xmmdw_mode)
11590 shift -= 3;
11591 break;
11592 case ymm_mode:
11593 shift = 5;
11594 break;
11595 case xmm_mode:
11596 shift = 4;
11597 break;
11598 case xmm_mq_mode:
11599 case q_mode:
11600 case q_swap_mode:
11601 shift = 3;
11602 break;
11603 case bw_unit_mode:
11604 shift = vex.w ? 1 : 0;
11605 break;
11606 default:
11607 abort ();
11608 }
11609 }
11610 else
11611 shift = 0;
11612
11613 USED_REX (REX_B);
11614 if (intel_syntax)
11615 intel_operand_size (bytemode, sizeflag);
11616 append_seg ();
11617
11618 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11619 {
11620 /* 32/64 bit address mode */
11621 int havedisp;
11622 int havesib;
11623 int havebase;
11624 int haveindex;
11625 int needindex;
11626 int needaddr32;
11627 int base, rbase;
11628 int vindex = 0;
11629 int scale = 0;
11630 int addr32flag = !((sizeflag & AFLAG)
11631 || bytemode == v_bnd_mode
11632 || bytemode == v_bndmk_mode
11633 || bytemode == bnd_mode
11634 || bytemode == bnd_swap_mode);
11635 const char **indexes64 = names64;
11636 const char **indexes32 = names32;
11637
11638 havesib = 0;
11639 havebase = 1;
11640 haveindex = 0;
11641 base = modrm.rm;
11642
11643 if (base == 4)
11644 {
11645 havesib = 1;
11646 vindex = sib.index;
11647 USED_REX (REX_X);
11648 if (rex & REX_X)
11649 vindex += 8;
11650 switch (bytemode)
11651 {
11652 case vex_vsib_d_w_dq_mode:
11653 case vex_vsib_d_w_d_mode:
11654 case vex_vsib_q_w_dq_mode:
11655 case vex_vsib_q_w_d_mode:
11656 if (!need_vex)
11657 abort ();
11658 if (vex.evex)
11659 {
11660 if (!vex.v)
11661 vindex += 16;
11662 }
11663
11664 haveindex = 1;
11665 switch (vex.length)
11666 {
11667 case 128:
11668 indexes64 = indexes32 = names_xmm;
11669 break;
11670 case 256:
11671 if (!vex.w
11672 || bytemode == vex_vsib_q_w_dq_mode
11673 || bytemode == vex_vsib_q_w_d_mode)
11674 indexes64 = indexes32 = names_ymm;
11675 else
11676 indexes64 = indexes32 = names_xmm;
11677 break;
11678 case 512:
11679 if (!vex.w
11680 || bytemode == vex_vsib_q_w_dq_mode
11681 || bytemode == vex_vsib_q_w_d_mode)
11682 indexes64 = indexes32 = names_zmm;
11683 else
11684 indexes64 = indexes32 = names_ymm;
11685 break;
11686 default:
11687 abort ();
11688 }
11689 break;
11690 default:
11691 haveindex = vindex != 4;
11692 break;
11693 }
11694 scale = sib.scale;
11695 base = sib.base;
11696 codep++;
11697 }
11698 else
11699 {
11700 /* mandatory non-vector SIB must have sib */
11701 if (bytemode == vex_sibmem_mode)
11702 {
11703 oappend ("(bad)");
11704 return;
11705 }
11706 }
11707 rbase = base + add;
11708
11709 switch (modrm.mod)
11710 {
11711 case 0:
11712 if (base == 5)
11713 {
11714 havebase = 0;
11715 if (address_mode == mode_64bit && !havesib)
11716 riprel = 1;
11717 disp = get32s ();
11718 if (riprel && bytemode == v_bndmk_mode)
11719 {
11720 oappend ("(bad)");
11721 return;
11722 }
11723 }
11724 break;
11725 case 1:
11726 FETCH_DATA (the_info, codep + 1);
11727 disp = *codep++;
11728 if ((disp & 0x80) != 0)
11729 disp -= 0x100;
11730 if (vex.evex && shift > 0)
11731 disp <<= shift;
11732 break;
11733 case 2:
11734 disp = get32s ();
11735 break;
11736 }
11737
11738 needindex = 0;
11739 needaddr32 = 0;
11740 if (havesib
11741 && !havebase
11742 && !haveindex
11743 && address_mode != mode_16bit)
11744 {
11745 if (address_mode == mode_64bit)
11746 {
11747 if (addr32flag)
11748 {
11749 /* Without base nor index registers, zero-extend the
11750 lower 32-bit displacement to 64 bits. */
11751 disp = (unsigned int) disp;
11752 needindex = 1;
11753 }
11754 needaddr32 = 1;
11755 }
11756 else
11757 {
11758 /* In 32-bit mode, we need index register to tell [offset]
11759 from [eiz*1 + offset]. */
11760 needindex = 1;
11761 }
11762 }
11763
11764 havedisp = (havebase
11765 || needindex
11766 || (havesib && (haveindex || scale != 0)));
11767
11768 if (!intel_syntax)
11769 if (modrm.mod != 0 || base == 5)
11770 {
11771 if (havedisp || riprel)
11772 print_displacement (scratchbuf, disp);
11773 else
11774 print_operand_value (scratchbuf, 1, disp);
11775 oappend (scratchbuf);
11776 if (riprel)
11777 {
11778 set_op (disp, 1);
11779 oappend (!addr32flag ? "(%rip)" : "(%eip)");
11780 }
11781 }
11782
11783 if ((havebase || haveindex || needindex || needaddr32 || riprel)
11784 && (address_mode != mode_64bit
11785 || ((bytemode != v_bnd_mode)
11786 && (bytemode != v_bndmk_mode)
11787 && (bytemode != bnd_mode)
11788 && (bytemode != bnd_swap_mode))))
11789 used_prefixes |= PREFIX_ADDR;
11790
11791 if (havedisp || (intel_syntax && riprel))
11792 {
11793 *obufp++ = open_char;
11794 if (intel_syntax && riprel)
11795 {
11796 set_op (disp, 1);
11797 oappend (!addr32flag ? "rip" : "eip");
11798 }
11799 *obufp = '\0';
11800 if (havebase)
11801 oappend (address_mode == mode_64bit && !addr32flag
11802 ? names64[rbase] : names32[rbase]);
11803 if (havesib)
11804 {
11805 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11806 print index to tell base + index from base. */
11807 if (scale != 0
11808 || needindex
11809 || haveindex
11810 || (havebase && base != ESP_REG_NUM))
11811 {
11812 if (!intel_syntax || havebase)
11813 {
11814 *obufp++ = separator_char;
11815 *obufp = '\0';
11816 }
11817 if (haveindex)
11818 oappend (address_mode == mode_64bit && !addr32flag
11819 ? indexes64[vindex] : indexes32[vindex]);
11820 else
11821 oappend (address_mode == mode_64bit && !addr32flag
11822 ? index64 : index32);
11823
11824 *obufp++ = scale_char;
11825 *obufp = '\0';
11826 sprintf (scratchbuf, "%d", 1 << scale);
11827 oappend (scratchbuf);
11828 }
11829 }
11830 if (intel_syntax
11831 && (disp || modrm.mod != 0 || base == 5))
11832 {
11833 if (!havedisp || (bfd_signed_vma) disp >= 0)
11834 {
11835 *obufp++ = '+';
11836 *obufp = '\0';
11837 }
11838 else if (modrm.mod != 1 && disp != -disp)
11839 {
11840 *obufp++ = '-';
11841 *obufp = '\0';
11842 disp = -disp;
11843 }
11844
11845 if (havedisp)
11846 print_displacement (scratchbuf, disp);
11847 else
11848 print_operand_value (scratchbuf, 1, disp);
11849 oappend (scratchbuf);
11850 }
11851
11852 *obufp++ = close_char;
11853 *obufp = '\0';
11854 }
11855 else if (intel_syntax)
11856 {
11857 if (modrm.mod != 0 || base == 5)
11858 {
11859 if (!active_seg_prefix)
11860 {
11861 oappend (names_seg[ds_reg - es_reg]);
11862 oappend (":");
11863 }
11864 print_operand_value (scratchbuf, 1, disp);
11865 oappend (scratchbuf);
11866 }
11867 }
11868 }
11869 else if (bytemode == v_bnd_mode
11870 || bytemode == v_bndmk_mode
11871 || bytemode == bnd_mode
11872 || bytemode == bnd_swap_mode)
11873 {
11874 oappend ("(bad)");
11875 return;
11876 }
11877 else
11878 {
11879 /* 16 bit address mode */
11880 used_prefixes |= prefixes & PREFIX_ADDR;
11881 switch (modrm.mod)
11882 {
11883 case 0:
11884 if (modrm.rm == 6)
11885 {
11886 disp = get16 ();
11887 if ((disp & 0x8000) != 0)
11888 disp -= 0x10000;
11889 }
11890 break;
11891 case 1:
11892 FETCH_DATA (the_info, codep + 1);
11893 disp = *codep++;
11894 if ((disp & 0x80) != 0)
11895 disp -= 0x100;
11896 if (vex.evex && shift > 0)
11897 disp <<= shift;
11898 break;
11899 case 2:
11900 disp = get16 ();
11901 if ((disp & 0x8000) != 0)
11902 disp -= 0x10000;
11903 break;
11904 }
11905
11906 if (!intel_syntax)
11907 if (modrm.mod != 0 || modrm.rm == 6)
11908 {
11909 print_displacement (scratchbuf, disp);
11910 oappend (scratchbuf);
11911 }
11912
11913 if (modrm.mod != 0 || modrm.rm != 6)
11914 {
11915 *obufp++ = open_char;
11916 *obufp = '\0';
11917 oappend (index16[modrm.rm]);
11918 if (intel_syntax
11919 && (disp || modrm.mod != 0 || modrm.rm == 6))
11920 {
11921 if ((bfd_signed_vma) disp >= 0)
11922 {
11923 *obufp++ = '+';
11924 *obufp = '\0';
11925 }
11926 else if (modrm.mod != 1)
11927 {
11928 *obufp++ = '-';
11929 *obufp = '\0';
11930 disp = -disp;
11931 }
11932
11933 print_displacement (scratchbuf, disp);
11934 oappend (scratchbuf);
11935 }
11936
11937 *obufp++ = close_char;
11938 *obufp = '\0';
11939 }
11940 else if (intel_syntax)
11941 {
11942 if (!active_seg_prefix)
11943 {
11944 oappend (names_seg[ds_reg - es_reg]);
11945 oappend (":");
11946 }
11947 print_operand_value (scratchbuf, 1, disp & 0xffff);
11948 oappend (scratchbuf);
11949 }
11950 }
11951 if (vex.evex && vex.b
11952 && (bytemode == x_mode
11953 || bytemode == xmmq_mode
11954 || bytemode == evex_half_bcst_xmmq_mode))
11955 {
11956 if (vex.w
11957 || bytemode == xmmq_mode
11958 || bytemode == evex_half_bcst_xmmq_mode)
11959 {
11960 switch (vex.length)
11961 {
11962 case 128:
11963 oappend ("{1to2}");
11964 break;
11965 case 256:
11966 oappend ("{1to4}");
11967 break;
11968 case 512:
11969 oappend ("{1to8}");
11970 break;
11971 default:
11972 abort ();
11973 }
11974 }
11975 else
11976 {
11977 switch (vex.length)
11978 {
11979 case 128:
11980 oappend ("{1to4}");
11981 break;
11982 case 256:
11983 oappend ("{1to8}");
11984 break;
11985 case 512:
11986 oappend ("{1to16}");
11987 break;
11988 default:
11989 abort ();
11990 }
11991 }
11992 }
11993 }
11994
11995 static void
11996 OP_E (int bytemode, int sizeflag)
11997 {
11998 /* Skip mod/rm byte. */
11999 MODRM_CHECK;
12000 codep++;
12001
12002 if (modrm.mod == 3)
12003 OP_E_register (bytemode, sizeflag);
12004 else
12005 OP_E_memory (bytemode, sizeflag);
12006 }
12007
12008 static void
12009 OP_G (int bytemode, int sizeflag)
12010 {
12011 int add = 0;
12012 const char **names;
12013 USED_REX (REX_R);
12014 if (rex & REX_R)
12015 add += 8;
12016 switch (bytemode)
12017 {
12018 case b_mode:
12019 if (modrm.reg & 4)
12020 USED_REX (0);
12021 if (rex)
12022 oappend (names8rex[modrm.reg + add]);
12023 else
12024 oappend (names8[modrm.reg + add]);
12025 break;
12026 case w_mode:
12027 oappend (names16[modrm.reg + add]);
12028 break;
12029 case d_mode:
12030 case db_mode:
12031 case dw_mode:
12032 oappend (names32[modrm.reg + add]);
12033 break;
12034 case q_mode:
12035 oappend (names64[modrm.reg + add]);
12036 break;
12037 case bnd_mode:
12038 if (modrm.reg > 0x3)
12039 {
12040 oappend ("(bad)");
12041 return;
12042 }
12043 oappend (names_bnd[modrm.reg]);
12044 break;
12045 case v_mode:
12046 case dq_mode:
12047 case dqb_mode:
12048 case dqd_mode:
12049 case dqw_mode:
12050 case movsxd_mode:
12051 USED_REX (REX_W);
12052 if (rex & REX_W)
12053 oappend (names64[modrm.reg + add]);
12054 else if (bytemode != v_mode && bytemode != movsxd_mode)
12055 oappend (names32[modrm.reg + add]);
12056 else
12057 {
12058 if (sizeflag & DFLAG)
12059 oappend (names32[modrm.reg + add]);
12060 else
12061 oappend (names16[modrm.reg + add]);
12062 used_prefixes |= (prefixes & PREFIX_DATA);
12063 }
12064 break;
12065 case va_mode:
12066 names = (address_mode == mode_64bit
12067 ? names64 : names32);
12068 if (!(prefixes & PREFIX_ADDR))
12069 {
12070 if (address_mode == mode_16bit)
12071 names = names16;
12072 }
12073 else
12074 {
12075 /* Remove "addr16/addr32". */
12076 all_prefixes[last_addr_prefix] = 0;
12077 names = (address_mode != mode_32bit
12078 ? names32 : names16);
12079 used_prefixes |= PREFIX_ADDR;
12080 }
12081 oappend (names[modrm.reg + add]);
12082 break;
12083 case m_mode:
12084 if (address_mode == mode_64bit)
12085 oappend (names64[modrm.reg + add]);
12086 else
12087 oappend (names32[modrm.reg + add]);
12088 break;
12089 case mask_bd_mode:
12090 case mask_mode:
12091 if ((modrm.reg + add) > 0x7)
12092 {
12093 oappend ("(bad)");
12094 return;
12095 }
12096 oappend (names_mask[modrm.reg + add]);
12097 break;
12098 default:
12099 oappend (INTERNAL_DISASSEMBLER_ERROR);
12100 break;
12101 }
12102 }
12103
12104 static bfd_vma
12105 get64 (void)
12106 {
12107 bfd_vma x;
12108 #ifdef BFD64
12109 unsigned int a;
12110 unsigned int b;
12111
12112 FETCH_DATA (the_info, codep + 8);
12113 a = *codep++ & 0xff;
12114 a |= (*codep++ & 0xff) << 8;
12115 a |= (*codep++ & 0xff) << 16;
12116 a |= (*codep++ & 0xffu) << 24;
12117 b = *codep++ & 0xff;
12118 b |= (*codep++ & 0xff) << 8;
12119 b |= (*codep++ & 0xff) << 16;
12120 b |= (*codep++ & 0xffu) << 24;
12121 x = a + ((bfd_vma) b << 32);
12122 #else
12123 abort ();
12124 x = 0;
12125 #endif
12126 return x;
12127 }
12128
12129 static bfd_signed_vma
12130 get32 (void)
12131 {
12132 bfd_vma x = 0;
12133
12134 FETCH_DATA (the_info, codep + 4);
12135 x = *codep++ & (bfd_vma) 0xff;
12136 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12137 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12138 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12139 return x;
12140 }
12141
12142 static bfd_signed_vma
12143 get32s (void)
12144 {
12145 bfd_vma x = 0;
12146
12147 FETCH_DATA (the_info, codep + 4);
12148 x = *codep++ & (bfd_vma) 0xff;
12149 x |= (*codep++ & (bfd_vma) 0xff) << 8;
12150 x |= (*codep++ & (bfd_vma) 0xff) << 16;
12151 x |= (*codep++ & (bfd_vma) 0xff) << 24;
12152
12153 x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
12154
12155 return x;
12156 }
12157
12158 static int
12159 get16 (void)
12160 {
12161 int x = 0;
12162
12163 FETCH_DATA (the_info, codep + 2);
12164 x = *codep++ & 0xff;
12165 x |= (*codep++ & 0xff) << 8;
12166 return x;
12167 }
12168
12169 static void
12170 set_op (bfd_vma op, int riprel)
12171 {
12172 op_index[op_ad] = op_ad;
12173 if (address_mode == mode_64bit)
12174 {
12175 op_address[op_ad] = op;
12176 op_riprel[op_ad] = riprel;
12177 }
12178 else
12179 {
12180 /* Mask to get a 32-bit address. */
12181 op_address[op_ad] = op & 0xffffffff;
12182 op_riprel[op_ad] = riprel & 0xffffffff;
12183 }
12184 }
12185
12186 static void
12187 OP_REG (int code, int sizeflag)
12188 {
12189 const char *s;
12190 int add;
12191
12192 switch (code)
12193 {
12194 case es_reg: case ss_reg: case cs_reg:
12195 case ds_reg: case fs_reg: case gs_reg:
12196 oappend (names_seg[code - es_reg]);
12197 return;
12198 }
12199
12200 USED_REX (REX_B);
12201 if (rex & REX_B)
12202 add = 8;
12203 else
12204 add = 0;
12205
12206 switch (code)
12207 {
12208 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12209 case sp_reg: case bp_reg: case si_reg: case di_reg:
12210 s = names16[code - ax_reg + add];
12211 break;
12212 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12213 USED_REX (0);
12214 /* Fall through. */
12215 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12216 if (rex)
12217 s = names8rex[code - al_reg + add];
12218 else
12219 s = names8[code - al_reg];
12220 break;
12221 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12222 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12223 if (address_mode == mode_64bit
12224 && ((sizeflag & DFLAG) || (rex & REX_W)))
12225 {
12226 s = names64[code - rAX_reg + add];
12227 break;
12228 }
12229 code += eAX_reg - rAX_reg;
12230 /* Fall through. */
12231 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12232 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12233 USED_REX (REX_W);
12234 if (rex & REX_W)
12235 s = names64[code - eAX_reg + add];
12236 else
12237 {
12238 if (sizeflag & DFLAG)
12239 s = names32[code - eAX_reg + add];
12240 else
12241 s = names16[code - eAX_reg + add];
12242 used_prefixes |= (prefixes & PREFIX_DATA);
12243 }
12244 break;
12245 default:
12246 s = INTERNAL_DISASSEMBLER_ERROR;
12247 break;
12248 }
12249 oappend (s);
12250 }
12251
12252 static void
12253 OP_IMREG (int code, int sizeflag)
12254 {
12255 const char *s;
12256
12257 switch (code)
12258 {
12259 case indir_dx_reg:
12260 if (intel_syntax)
12261 s = "dx";
12262 else
12263 s = "(%dx)";
12264 break;
12265 case al_reg: case cl_reg:
12266 s = names8[code - al_reg];
12267 break;
12268 case eAX_reg:
12269 USED_REX (REX_W);
12270 if (rex & REX_W)
12271 {
12272 s = *names64;
12273 break;
12274 }
12275 /* Fall through. */
12276 case z_mode_ax_reg:
12277 if ((rex & REX_W) || (sizeflag & DFLAG))
12278 s = *names32;
12279 else
12280 s = *names16;
12281 if (!(rex & REX_W))
12282 used_prefixes |= (prefixes & PREFIX_DATA);
12283 break;
12284 default:
12285 s = INTERNAL_DISASSEMBLER_ERROR;
12286 break;
12287 }
12288 oappend (s);
12289 }
12290
12291 static void
12292 OP_I (int bytemode, int sizeflag)
12293 {
12294 bfd_signed_vma op;
12295 bfd_signed_vma mask = -1;
12296
12297 switch (bytemode)
12298 {
12299 case b_mode:
12300 FETCH_DATA (the_info, codep + 1);
12301 op = *codep++;
12302 mask = 0xff;
12303 break;
12304 case v_mode:
12305 USED_REX (REX_W);
12306 if (rex & REX_W)
12307 op = get32s ();
12308 else
12309 {
12310 if (sizeflag & DFLAG)
12311 {
12312 op = get32 ();
12313 mask = 0xffffffff;
12314 }
12315 else
12316 {
12317 op = get16 ();
12318 mask = 0xfffff;
12319 }
12320 used_prefixes |= (prefixes & PREFIX_DATA);
12321 }
12322 break;
12323 case d_mode:
12324 mask = 0xffffffff;
12325 op = get32 ();
12326 break;
12327 case w_mode:
12328 mask = 0xfffff;
12329 op = get16 ();
12330 break;
12331 case const_1_mode:
12332 if (intel_syntax)
12333 oappend ("1");
12334 return;
12335 default:
12336 oappend (INTERNAL_DISASSEMBLER_ERROR);
12337 return;
12338 }
12339
12340 op &= mask;
12341 scratchbuf[0] = '$';
12342 print_operand_value (scratchbuf + 1, 1, op);
12343 oappend_maybe_intel (scratchbuf);
12344 scratchbuf[0] = '\0';
12345 }
12346
12347 static void
12348 OP_I64 (int bytemode, int sizeflag)
12349 {
12350 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
12351 {
12352 OP_I (bytemode, sizeflag);
12353 return;
12354 }
12355
12356 USED_REX (REX_W);
12357
12358 scratchbuf[0] = '$';
12359 print_operand_value (scratchbuf + 1, 1, get64 ());
12360 oappend_maybe_intel (scratchbuf);
12361 scratchbuf[0] = '\0';
12362 }
12363
12364 static void
12365 OP_sI (int bytemode, int sizeflag)
12366 {
12367 bfd_signed_vma op;
12368
12369 switch (bytemode)
12370 {
12371 case b_mode:
12372 case b_T_mode:
12373 FETCH_DATA (the_info, codep + 1);
12374 op = *codep++;
12375 if ((op & 0x80) != 0)
12376 op -= 0x100;
12377 if (bytemode == b_T_mode)
12378 {
12379 if (address_mode != mode_64bit
12380 || !((sizeflag & DFLAG) || (rex & REX_W)))
12381 {
12382 /* The operand-size prefix is overridden by a REX prefix. */
12383 if ((sizeflag & DFLAG) || (rex & REX_W))
12384 op &= 0xffffffff;
12385 else
12386 op &= 0xffff;
12387 }
12388 }
12389 else
12390 {
12391 if (!(rex & REX_W))
12392 {
12393 if (sizeflag & DFLAG)
12394 op &= 0xffffffff;
12395 else
12396 op &= 0xffff;
12397 }
12398 }
12399 break;
12400 case v_mode:
12401 /* The operand-size prefix is overridden by a REX prefix. */
12402 if ((sizeflag & DFLAG) || (rex & REX_W))
12403 op = get32s ();
12404 else
12405 op = get16 ();
12406 break;
12407 default:
12408 oappend (INTERNAL_DISASSEMBLER_ERROR);
12409 return;
12410 }
12411
12412 scratchbuf[0] = '$';
12413 print_operand_value (scratchbuf + 1, 1, op);
12414 oappend_maybe_intel (scratchbuf);
12415 }
12416
12417 static void
12418 OP_J (int bytemode, int sizeflag)
12419 {
12420 bfd_vma disp;
12421 bfd_vma mask = -1;
12422 bfd_vma segment = 0;
12423
12424 switch (bytemode)
12425 {
12426 case b_mode:
12427 FETCH_DATA (the_info, codep + 1);
12428 disp = *codep++;
12429 if ((disp & 0x80) != 0)
12430 disp -= 0x100;
12431 break;
12432 case v_mode:
12433 case dqw_mode:
12434 if ((sizeflag & DFLAG)
12435 || (address_mode == mode_64bit
12436 && ((isa64 == intel64 && bytemode != dqw_mode)
12437 || (rex & REX_W))))
12438 disp = get32s ();
12439 else
12440 {
12441 disp = get16 ();
12442 if ((disp & 0x8000) != 0)
12443 disp -= 0x10000;
12444 /* In 16bit mode, address is wrapped around at 64k within
12445 the same segment. Otherwise, a data16 prefix on a jump
12446 instruction means that the pc is masked to 16 bits after
12447 the displacement is added! */
12448 mask = 0xffff;
12449 if ((prefixes & PREFIX_DATA) == 0)
12450 segment = ((start_pc + (codep - start_codep))
12451 & ~((bfd_vma) 0xffff));
12452 }
12453 if (address_mode != mode_64bit
12454 || (isa64 != intel64 && !(rex & REX_W)))
12455 used_prefixes |= (prefixes & PREFIX_DATA);
12456 break;
12457 default:
12458 oappend (INTERNAL_DISASSEMBLER_ERROR);
12459 return;
12460 }
12461 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
12462 set_op (disp, 0);
12463 print_operand_value (scratchbuf, 1, disp);
12464 oappend (scratchbuf);
12465 }
12466
12467 static void
12468 OP_SEG (int bytemode, int sizeflag)
12469 {
12470 if (bytemode == w_mode)
12471 oappend (names_seg[modrm.reg]);
12472 else
12473 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12474 }
12475
12476 static void
12477 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12478 {
12479 int seg, offset;
12480
12481 if (sizeflag & DFLAG)
12482 {
12483 offset = get32 ();
12484 seg = get16 ();
12485 }
12486 else
12487 {
12488 offset = get16 ();
12489 seg = get16 ();
12490 }
12491 used_prefixes |= (prefixes & PREFIX_DATA);
12492 if (intel_syntax)
12493 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12494 else
12495 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12496 oappend (scratchbuf);
12497 }
12498
12499 static void
12500 OP_OFF (int bytemode, int sizeflag)
12501 {
12502 bfd_vma off;
12503
12504 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12505 intel_operand_size (bytemode, sizeflag);
12506 append_seg ();
12507
12508 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12509 off = get32 ();
12510 else
12511 off = get16 ();
12512
12513 if (intel_syntax)
12514 {
12515 if (!active_seg_prefix)
12516 {
12517 oappend (names_seg[ds_reg - es_reg]);
12518 oappend (":");
12519 }
12520 }
12521 print_operand_value (scratchbuf, 1, off);
12522 oappend (scratchbuf);
12523 }
12524
12525 static void
12526 OP_OFF64 (int bytemode, int sizeflag)
12527 {
12528 bfd_vma off;
12529
12530 if (address_mode != mode_64bit
12531 || (prefixes & PREFIX_ADDR))
12532 {
12533 OP_OFF (bytemode, sizeflag);
12534 return;
12535 }
12536
12537 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12538 intel_operand_size (bytemode, sizeflag);
12539 append_seg ();
12540
12541 off = get64 ();
12542
12543 if (intel_syntax)
12544 {
12545 if (!active_seg_prefix)
12546 {
12547 oappend (names_seg[ds_reg - es_reg]);
12548 oappend (":");
12549 }
12550 }
12551 print_operand_value (scratchbuf, 1, off);
12552 oappend (scratchbuf);
12553 }
12554
12555 static void
12556 ptr_reg (int code, int sizeflag)
12557 {
12558 const char *s;
12559
12560 *obufp++ = open_char;
12561 used_prefixes |= (prefixes & PREFIX_ADDR);
12562 if (address_mode == mode_64bit)
12563 {
12564 if (!(sizeflag & AFLAG))
12565 s = names32[code - eAX_reg];
12566 else
12567 s = names64[code - eAX_reg];
12568 }
12569 else if (sizeflag & AFLAG)
12570 s = names32[code - eAX_reg];
12571 else
12572 s = names16[code - eAX_reg];
12573 oappend (s);
12574 *obufp++ = close_char;
12575 *obufp = 0;
12576 }
12577
12578 static void
12579 OP_ESreg (int code, int sizeflag)
12580 {
12581 if (intel_syntax)
12582 {
12583 switch (codep[-1])
12584 {
12585 case 0x6d: /* insw/insl */
12586 intel_operand_size (z_mode, sizeflag);
12587 break;
12588 case 0xa5: /* movsw/movsl/movsq */
12589 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12590 case 0xab: /* stosw/stosl */
12591 case 0xaf: /* scasw/scasl */
12592 intel_operand_size (v_mode, sizeflag);
12593 break;
12594 default:
12595 intel_operand_size (b_mode, sizeflag);
12596 }
12597 }
12598 oappend_maybe_intel ("%es:");
12599 ptr_reg (code, sizeflag);
12600 }
12601
12602 static void
12603 OP_DSreg (int code, int sizeflag)
12604 {
12605 if (intel_syntax)
12606 {
12607 switch (codep[-1])
12608 {
12609 case 0x6f: /* outsw/outsl */
12610 intel_operand_size (z_mode, sizeflag);
12611 break;
12612 case 0xa5: /* movsw/movsl/movsq */
12613 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12614 case 0xad: /* lodsw/lodsl/lodsq */
12615 intel_operand_size (v_mode, sizeflag);
12616 break;
12617 default:
12618 intel_operand_size (b_mode, sizeflag);
12619 }
12620 }
12621 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
12622 default segment register DS is printed. */
12623 if (!active_seg_prefix)
12624 active_seg_prefix = PREFIX_DS;
12625 append_seg ();
12626 ptr_reg (code, sizeflag);
12627 }
12628
12629 static void
12630 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12631 {
12632 int add;
12633 if (rex & REX_R)
12634 {
12635 USED_REX (REX_R);
12636 add = 8;
12637 }
12638 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12639 {
12640 all_prefixes[last_lock_prefix] = 0;
12641 used_prefixes |= PREFIX_LOCK;
12642 add = 8;
12643 }
12644 else
12645 add = 0;
12646 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12647 oappend_maybe_intel (scratchbuf);
12648 }
12649
12650 static void
12651 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12652 {
12653 int add;
12654 USED_REX (REX_R);
12655 if (rex & REX_R)
12656 add = 8;
12657 else
12658 add = 0;
12659 if (intel_syntax)
12660 sprintf (scratchbuf, "dr%d", modrm.reg + add);
12661 else
12662 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12663 oappend (scratchbuf);
12664 }
12665
12666 static void
12667 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12668 {
12669 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12670 oappend_maybe_intel (scratchbuf);
12671 }
12672
12673 static void
12674 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12675 {
12676 int reg = modrm.reg;
12677 const char **names;
12678
12679 used_prefixes |= (prefixes & PREFIX_DATA);
12680 if (prefixes & PREFIX_DATA)
12681 {
12682 names = names_xmm;
12683 USED_REX (REX_R);
12684 if (rex & REX_R)
12685 reg += 8;
12686 }
12687 else
12688 names = names_mm;
12689 oappend (names[reg]);
12690 }
12691
12692 static void
12693 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12694 {
12695 int reg = modrm.reg;
12696 const char **names;
12697
12698 USED_REX (REX_R);
12699 if (rex & REX_R)
12700 reg += 8;
12701 if (vex.evex)
12702 {
12703 if (!vex.r)
12704 reg += 16;
12705 }
12706
12707 if (need_vex
12708 && bytemode != xmm_mode
12709 && bytemode != xmmq_mode
12710 && bytemode != evex_half_bcst_xmmq_mode
12711 && bytemode != ymm_mode
12712 && bytemode != tmm_mode
12713 && bytemode != scalar_mode)
12714 {
12715 switch (vex.length)
12716 {
12717 case 128:
12718 names = names_xmm;
12719 break;
12720 case 256:
12721 if (vex.w
12722 || (bytemode != vex_vsib_q_w_dq_mode
12723 && bytemode != vex_vsib_q_w_d_mode))
12724 names = names_ymm;
12725 else
12726 names = names_xmm;
12727 break;
12728 case 512:
12729 names = names_zmm;
12730 break;
12731 default:
12732 abort ();
12733 }
12734 }
12735 else if (bytemode == xmmq_mode
12736 || bytemode == evex_half_bcst_xmmq_mode)
12737 {
12738 switch (vex.length)
12739 {
12740 case 128:
12741 case 256:
12742 names = names_xmm;
12743 break;
12744 case 512:
12745 names = names_ymm;
12746 break;
12747 default:
12748 abort ();
12749 }
12750 }
12751 else if (bytemode == tmm_mode)
12752 {
12753 modrm.reg = reg;
12754 if (reg >= 8)
12755 {
12756 oappend ("(bad)");
12757 return;
12758 }
12759 names = names_tmm;
12760 }
12761 else if (bytemode == ymm_mode)
12762 names = names_ymm;
12763 else
12764 names = names_xmm;
12765 oappend (names[reg]);
12766 }
12767
12768 static void
12769 OP_EM (int bytemode, int sizeflag)
12770 {
12771 int reg;
12772 const char **names;
12773
12774 if (modrm.mod != 3)
12775 {
12776 if (intel_syntax
12777 && (bytemode == v_mode || bytemode == v_swap_mode))
12778 {
12779 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12780 used_prefixes |= (prefixes & PREFIX_DATA);
12781 }
12782 OP_E (bytemode, sizeflag);
12783 return;
12784 }
12785
12786 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12787 swap_operand ();
12788
12789 /* Skip mod/rm byte. */
12790 MODRM_CHECK;
12791 codep++;
12792 used_prefixes |= (prefixes & PREFIX_DATA);
12793 reg = modrm.rm;
12794 if (prefixes & PREFIX_DATA)
12795 {
12796 names = names_xmm;
12797 USED_REX (REX_B);
12798 if (rex & REX_B)
12799 reg += 8;
12800 }
12801 else
12802 names = names_mm;
12803 oappend (names[reg]);
12804 }
12805
12806 /* cvt* are the only instructions in sse2 which have
12807 both SSE and MMX operands and also have 0x66 prefix
12808 in their opcode. 0x66 was originally used to differentiate
12809 between SSE and MMX instruction(operands). So we have to handle the
12810 cvt* separately using OP_EMC and OP_MXC */
12811 static void
12812 OP_EMC (int bytemode, int sizeflag)
12813 {
12814 if (modrm.mod != 3)
12815 {
12816 if (intel_syntax && bytemode == v_mode)
12817 {
12818 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12819 used_prefixes |= (prefixes & PREFIX_DATA);
12820 }
12821 OP_E (bytemode, sizeflag);
12822 return;
12823 }
12824
12825 /* Skip mod/rm byte. */
12826 MODRM_CHECK;
12827 codep++;
12828 used_prefixes |= (prefixes & PREFIX_DATA);
12829 oappend (names_mm[modrm.rm]);
12830 }
12831
12832 static void
12833 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12834 {
12835 used_prefixes |= (prefixes & PREFIX_DATA);
12836 oappend (names_mm[modrm.reg]);
12837 }
12838
12839 static void
12840 OP_EX (int bytemode, int sizeflag)
12841 {
12842 int reg;
12843 const char **names;
12844
12845 /* Skip mod/rm byte. */
12846 MODRM_CHECK;
12847 codep++;
12848
12849 if (modrm.mod != 3)
12850 {
12851 OP_E_memory (bytemode, sizeflag);
12852 return;
12853 }
12854
12855 reg = modrm.rm;
12856 USED_REX (REX_B);
12857 if (rex & REX_B)
12858 reg += 8;
12859 if (vex.evex)
12860 {
12861 USED_REX (REX_X);
12862 if ((rex & REX_X))
12863 reg += 16;
12864 }
12865
12866 if ((sizeflag & SUFFIX_ALWAYS)
12867 && (bytemode == x_swap_mode
12868 || bytemode == d_swap_mode
12869 || bytemode == q_swap_mode))
12870 swap_operand ();
12871
12872 if (need_vex
12873 && bytemode != xmm_mode
12874 && bytemode != xmmdw_mode
12875 && bytemode != xmmqd_mode
12876 && bytemode != xmm_mb_mode
12877 && bytemode != xmm_mw_mode
12878 && bytemode != xmm_md_mode
12879 && bytemode != xmm_mq_mode
12880 && bytemode != xmmq_mode
12881 && bytemode != evex_half_bcst_xmmq_mode
12882 && bytemode != ymm_mode
12883 && bytemode != tmm_mode
12884 && bytemode != vex_scalar_w_dq_mode)
12885 {
12886 switch (vex.length)
12887 {
12888 case 128:
12889 names = names_xmm;
12890 break;
12891 case 256:
12892 names = names_ymm;
12893 break;
12894 case 512:
12895 names = names_zmm;
12896 break;
12897 default:
12898 abort ();
12899 }
12900 }
12901 else if (bytemode == xmmq_mode
12902 || bytemode == evex_half_bcst_xmmq_mode)
12903 {
12904 switch (vex.length)
12905 {
12906 case 128:
12907 case 256:
12908 names = names_xmm;
12909 break;
12910 case 512:
12911 names = names_ymm;
12912 break;
12913 default:
12914 abort ();
12915 }
12916 }
12917 else if (bytemode == tmm_mode)
12918 {
12919 modrm.rm = reg;
12920 if (reg >= 8)
12921 {
12922 oappend ("(bad)");
12923 return;
12924 }
12925 names = names_tmm;
12926 }
12927 else if (bytemode == ymm_mode)
12928 names = names_ymm;
12929 else
12930 names = names_xmm;
12931 oappend (names[reg]);
12932 }
12933
12934 static void
12935 OP_MS (int bytemode, int sizeflag)
12936 {
12937 if (modrm.mod == 3)
12938 OP_EM (bytemode, sizeflag);
12939 else
12940 BadOp ();
12941 }
12942
12943 static void
12944 OP_XS (int bytemode, int sizeflag)
12945 {
12946 if (modrm.mod == 3)
12947 OP_EX (bytemode, sizeflag);
12948 else
12949 BadOp ();
12950 }
12951
12952 static void
12953 OP_M (int bytemode, int sizeflag)
12954 {
12955 if (modrm.mod == 3)
12956 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12957 BadOp ();
12958 else
12959 OP_E (bytemode, sizeflag);
12960 }
12961
12962 static void
12963 OP_0f07 (int bytemode, int sizeflag)
12964 {
12965 if (modrm.mod != 3 || modrm.rm != 0)
12966 BadOp ();
12967 else
12968 OP_E (bytemode, sizeflag);
12969 }
12970
12971 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12972 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12973
12974 static void
12975 NOP_Fixup1 (int bytemode, int sizeflag)
12976 {
12977 if ((prefixes & PREFIX_DATA) != 0
12978 || (rex != 0
12979 && rex != 0x48
12980 && address_mode == mode_64bit))
12981 OP_REG (bytemode, sizeflag);
12982 else
12983 strcpy (obuf, "nop");
12984 }
12985
12986 static void
12987 NOP_Fixup2 (int bytemode, int sizeflag)
12988 {
12989 if ((prefixes & PREFIX_DATA) != 0
12990 || (rex != 0
12991 && rex != 0x48
12992 && address_mode == mode_64bit))
12993 OP_IMREG (bytemode, sizeflag);
12994 }
12995
12996 static const char *const Suffix3DNow[] = {
12997 /* 00 */ NULL, NULL, NULL, NULL,
12998 /* 04 */ NULL, NULL, NULL, NULL,
12999 /* 08 */ NULL, NULL, NULL, NULL,
13000 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13001 /* 10 */ NULL, NULL, NULL, NULL,
13002 /* 14 */ NULL, NULL, NULL, NULL,
13003 /* 18 */ NULL, NULL, NULL, NULL,
13004 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13005 /* 20 */ NULL, NULL, NULL, NULL,
13006 /* 24 */ NULL, NULL, NULL, NULL,
13007 /* 28 */ NULL, NULL, NULL, NULL,
13008 /* 2C */ NULL, NULL, NULL, NULL,
13009 /* 30 */ NULL, NULL, NULL, NULL,
13010 /* 34 */ NULL, NULL, NULL, NULL,
13011 /* 38 */ NULL, NULL, NULL, NULL,
13012 /* 3C */ NULL, NULL, NULL, NULL,
13013 /* 40 */ NULL, NULL, NULL, NULL,
13014 /* 44 */ NULL, NULL, NULL, NULL,
13015 /* 48 */ NULL, NULL, NULL, NULL,
13016 /* 4C */ NULL, NULL, NULL, NULL,
13017 /* 50 */ NULL, NULL, NULL, NULL,
13018 /* 54 */ NULL, NULL, NULL, NULL,
13019 /* 58 */ NULL, NULL, NULL, NULL,
13020 /* 5C */ NULL, NULL, NULL, NULL,
13021 /* 60 */ NULL, NULL, NULL, NULL,
13022 /* 64 */ NULL, NULL, NULL, NULL,
13023 /* 68 */ NULL, NULL, NULL, NULL,
13024 /* 6C */ NULL, NULL, NULL, NULL,
13025 /* 70 */ NULL, NULL, NULL, NULL,
13026 /* 74 */ NULL, NULL, NULL, NULL,
13027 /* 78 */ NULL, NULL, NULL, NULL,
13028 /* 7C */ NULL, NULL, NULL, NULL,
13029 /* 80 */ NULL, NULL, NULL, NULL,
13030 /* 84 */ NULL, NULL, NULL, NULL,
13031 /* 88 */ NULL, NULL, "pfnacc", NULL,
13032 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13033 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13034 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13035 /* 98 */ NULL, NULL, "pfsub", NULL,
13036 /* 9C */ NULL, NULL, "pfadd", NULL,
13037 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13038 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13039 /* A8 */ NULL, NULL, "pfsubr", NULL,
13040 /* AC */ NULL, NULL, "pfacc", NULL,
13041 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13042 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13043 /* B8 */ NULL, NULL, NULL, "pswapd",
13044 /* BC */ NULL, NULL, NULL, "pavgusb",
13045 /* C0 */ NULL, NULL, NULL, NULL,
13046 /* C4 */ NULL, NULL, NULL, NULL,
13047 /* C8 */ NULL, NULL, NULL, NULL,
13048 /* CC */ NULL, NULL, NULL, NULL,
13049 /* D0 */ NULL, NULL, NULL, NULL,
13050 /* D4 */ NULL, NULL, NULL, NULL,
13051 /* D8 */ NULL, NULL, NULL, NULL,
13052 /* DC */ NULL, NULL, NULL, NULL,
13053 /* E0 */ NULL, NULL, NULL, NULL,
13054 /* E4 */ NULL, NULL, NULL, NULL,
13055 /* E8 */ NULL, NULL, NULL, NULL,
13056 /* EC */ NULL, NULL, NULL, NULL,
13057 /* F0 */ NULL, NULL, NULL, NULL,
13058 /* F4 */ NULL, NULL, NULL, NULL,
13059 /* F8 */ NULL, NULL, NULL, NULL,
13060 /* FC */ NULL, NULL, NULL, NULL,
13061 };
13062
13063 static void
13064 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13065 {
13066 const char *mnemonic;
13067
13068 FETCH_DATA (the_info, codep + 1);
13069 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13070 place where an 8-bit immediate would normally go. ie. the last
13071 byte of the instruction. */
13072 obufp = mnemonicendp;
13073 mnemonic = Suffix3DNow[*codep++ & 0xff];
13074 if (mnemonic)
13075 oappend (mnemonic);
13076 else
13077 {
13078 /* Since a variable sized modrm/sib chunk is between the start
13079 of the opcode (0x0f0f) and the opcode suffix, we need to do
13080 all the modrm processing first, and don't know until now that
13081 we have a bad opcode. This necessitates some cleaning up. */
13082 op_out[0][0] = '\0';
13083 op_out[1][0] = '\0';
13084 BadOp ();
13085 }
13086 mnemonicendp = obufp;
13087 }
13088
13089 static const struct op simd_cmp_op[] =
13090 {
13091 { STRING_COMMA_LEN ("eq") },
13092 { STRING_COMMA_LEN ("lt") },
13093 { STRING_COMMA_LEN ("le") },
13094 { STRING_COMMA_LEN ("unord") },
13095 { STRING_COMMA_LEN ("neq") },
13096 { STRING_COMMA_LEN ("nlt") },
13097 { STRING_COMMA_LEN ("nle") },
13098 { STRING_COMMA_LEN ("ord") }
13099 };
13100
13101 static const struct op vex_cmp_op[] =
13102 {
13103 { STRING_COMMA_LEN ("eq_uq") },
13104 { STRING_COMMA_LEN ("nge") },
13105 { STRING_COMMA_LEN ("ngt") },
13106 { STRING_COMMA_LEN ("false") },
13107 { STRING_COMMA_LEN ("neq_oq") },
13108 { STRING_COMMA_LEN ("ge") },
13109 { STRING_COMMA_LEN ("gt") },
13110 { STRING_COMMA_LEN ("true") },
13111 { STRING_COMMA_LEN ("eq_os") },
13112 { STRING_COMMA_LEN ("lt_oq") },
13113 { STRING_COMMA_LEN ("le_oq") },
13114 { STRING_COMMA_LEN ("unord_s") },
13115 { STRING_COMMA_LEN ("neq_us") },
13116 { STRING_COMMA_LEN ("nlt_uq") },
13117 { STRING_COMMA_LEN ("nle_uq") },
13118 { STRING_COMMA_LEN ("ord_s") },
13119 { STRING_COMMA_LEN ("eq_us") },
13120 { STRING_COMMA_LEN ("nge_uq") },
13121 { STRING_COMMA_LEN ("ngt_uq") },
13122 { STRING_COMMA_LEN ("false_os") },
13123 { STRING_COMMA_LEN ("neq_os") },
13124 { STRING_COMMA_LEN ("ge_oq") },
13125 { STRING_COMMA_LEN ("gt_oq") },
13126 { STRING_COMMA_LEN ("true_us") },
13127 };
13128
13129 static void
13130 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13131 {
13132 unsigned int cmp_type;
13133
13134 FETCH_DATA (the_info, codep + 1);
13135 cmp_type = *codep++ & 0xff;
13136 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13137 {
13138 char suffix [3];
13139 char *p = mnemonicendp - 2;
13140 suffix[0] = p[0];
13141 suffix[1] = p[1];
13142 suffix[2] = '\0';
13143 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13144 mnemonicendp += simd_cmp_op[cmp_type].len;
13145 }
13146 else if (need_vex
13147 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13148 {
13149 char suffix [3];
13150 char *p = mnemonicendp - 2;
13151 suffix[0] = p[0];
13152 suffix[1] = p[1];
13153 suffix[2] = '\0';
13154 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13155 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13156 mnemonicendp += vex_cmp_op[cmp_type].len;
13157 }
13158 else
13159 {
13160 /* We have a reserved extension byte. Output it directly. */
13161 scratchbuf[0] = '$';
13162 print_operand_value (scratchbuf + 1, 1, cmp_type);
13163 oappend_maybe_intel (scratchbuf);
13164 scratchbuf[0] = '\0';
13165 }
13166 }
13167
13168 static void
13169 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13170 {
13171 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13172 if (!intel_syntax)
13173 {
13174 strcpy (op_out[0], names32[0]);
13175 strcpy (op_out[1], names32[1]);
13176 if (bytemode == eBX_reg)
13177 strcpy (op_out[2], names32[3]);
13178 two_source_ops = 1;
13179 }
13180 /* Skip mod/rm byte. */
13181 MODRM_CHECK;
13182 codep++;
13183 }
13184
13185 static void
13186 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
13187 int sizeflag ATTRIBUTE_UNUSED)
13188 {
13189 /* monitor %{e,r,}ax,%ecx,%edx" */
13190 if (!intel_syntax)
13191 {
13192 const char **names = (address_mode == mode_64bit
13193 ? names64 : names32);
13194
13195 if (prefixes & PREFIX_ADDR)
13196 {
13197 /* Remove "addr16/addr32". */
13198 all_prefixes[last_addr_prefix] = 0;
13199 names = (address_mode != mode_32bit
13200 ? names32 : names16);
13201 used_prefixes |= PREFIX_ADDR;
13202 }
13203 else if (address_mode == mode_16bit)
13204 names = names16;
13205 strcpy (op_out[0], names[0]);
13206 strcpy (op_out[1], names32[1]);
13207 strcpy (op_out[2], names32[2]);
13208 two_source_ops = 1;
13209 }
13210 /* Skip mod/rm byte. */
13211 MODRM_CHECK;
13212 codep++;
13213 }
13214
13215 static void
13216 BadOp (void)
13217 {
13218 /* Throw away prefixes and 1st. opcode byte. */
13219 codep = insn_codep + 1;
13220 oappend ("(bad)");
13221 }
13222
13223 static void
13224 REP_Fixup (int bytemode, int sizeflag)
13225 {
13226 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13227 lods and stos. */
13228 if (prefixes & PREFIX_REPZ)
13229 all_prefixes[last_repz_prefix] = REP_PREFIX;
13230
13231 switch (bytemode)
13232 {
13233 case al_reg:
13234 case eAX_reg:
13235 case indir_dx_reg:
13236 OP_IMREG (bytemode, sizeflag);
13237 break;
13238 case eDI_reg:
13239 OP_ESreg (bytemode, sizeflag);
13240 break;
13241 case eSI_reg:
13242 OP_DSreg (bytemode, sizeflag);
13243 break;
13244 default:
13245 abort ();
13246 break;
13247 }
13248 }
13249
13250 static void
13251 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13252 {
13253 if ( isa64 != amd64 )
13254 return;
13255
13256 obufp = obuf;
13257 BadOp ();
13258 mnemonicendp = obufp;
13259 ++codep;
13260 }
13261
13262 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13263 "bnd". */
13264
13265 static void
13266 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13267 {
13268 if (prefixes & PREFIX_REPNZ)
13269 all_prefixes[last_repnz_prefix] = BND_PREFIX;
13270 }
13271
13272 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13273 "notrack". */
13274
13275 static void
13276 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
13277 int sizeflag ATTRIBUTE_UNUSED)
13278 {
13279
13280 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13281 we've seen a PREFIX_DS. */
13282 if ((prefixes & PREFIX_DS) != 0
13283 && (address_mode != mode_64bit || last_data_prefix < 0))
13284 {
13285 /* NOTRACK prefix is only valid on indirect branch instructions.
13286 NB: DATA prefix is unsupported for Intel64. */
13287 active_seg_prefix = 0;
13288 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
13289 }
13290 }
13291
13292 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13293 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13294 */
13295
13296 static void
13297 HLE_Fixup1 (int bytemode, int sizeflag)
13298 {
13299 if (modrm.mod != 3
13300 && (prefixes & PREFIX_LOCK) != 0)
13301 {
13302 if (prefixes & PREFIX_REPZ)
13303 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13304 if (prefixes & PREFIX_REPNZ)
13305 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13306 }
13307
13308 OP_E (bytemode, sizeflag);
13309 }
13310
13311 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
13312 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13313 */
13314
13315 static void
13316 HLE_Fixup2 (int bytemode, int sizeflag)
13317 {
13318 if (modrm.mod != 3)
13319 {
13320 if (prefixes & PREFIX_REPZ)
13321 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13322 if (prefixes & PREFIX_REPNZ)
13323 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13324 }
13325
13326 OP_E (bytemode, sizeflag);
13327 }
13328
13329 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13330 "xrelease" for memory operand. No check for LOCK prefix. */
13331
13332 static void
13333 HLE_Fixup3 (int bytemode, int sizeflag)
13334 {
13335 if (modrm.mod != 3
13336 && last_repz_prefix > last_repnz_prefix
13337 && (prefixes & PREFIX_REPZ) != 0)
13338 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13339
13340 OP_E (bytemode, sizeflag);
13341 }
13342
13343 static void
13344 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
13345 {
13346 USED_REX (REX_W);
13347 if (rex & REX_W)
13348 {
13349 /* Change cmpxchg8b to cmpxchg16b. */
13350 char *p = mnemonicendp - 2;
13351 mnemonicendp = stpcpy (p, "16b");
13352 bytemode = o_mode;
13353 }
13354 else if ((prefixes & PREFIX_LOCK) != 0)
13355 {
13356 if (prefixes & PREFIX_REPZ)
13357 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
13358 if (prefixes & PREFIX_REPNZ)
13359 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
13360 }
13361
13362 OP_M (bytemode, sizeflag);
13363 }
13364
13365 static void
13366 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
13367 {
13368 const char **names;
13369
13370 if (need_vex)
13371 {
13372 switch (vex.length)
13373 {
13374 case 128:
13375 names = names_xmm;
13376 break;
13377 case 256:
13378 names = names_ymm;
13379 break;
13380 default:
13381 abort ();
13382 }
13383 }
13384 else
13385 names = names_xmm;
13386 oappend (names[reg]);
13387 }
13388
13389 static void
13390 FXSAVE_Fixup (int bytemode, int sizeflag)
13391 {
13392 /* Add proper suffix to "fxsave" and "fxrstor". */
13393 USED_REX (REX_W);
13394 if (rex & REX_W)
13395 {
13396 char *p = mnemonicendp;
13397 *p++ = '6';
13398 *p++ = '4';
13399 *p = '\0';
13400 mnemonicendp = p;
13401 }
13402 OP_M (bytemode, sizeflag);
13403 }
13404
13405 /* Display the destination register operand for instructions with
13406 VEX. */
13407
13408 static void
13409 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13410 {
13411 int reg;
13412 const char **names;
13413
13414 if (!need_vex)
13415 abort ();
13416
13417 reg = vex.register_specifier;
13418 vex.register_specifier = 0;
13419 if (address_mode != mode_64bit)
13420 reg &= 7;
13421 else if (vex.evex && !vex.v)
13422 reg += 16;
13423
13424 if (bytemode == vex_scalar_mode)
13425 {
13426 oappend (names_xmm[reg]);
13427 return;
13428 }
13429
13430 if (bytemode == tmm_mode)
13431 {
13432 /* All 3 TMM registers must be distinct. */
13433 if (reg >= 8)
13434 oappend ("(bad)");
13435 else
13436 {
13437 /* This must be the 3rd operand. */
13438 if (obufp != op_out[2])
13439 abort ();
13440 oappend (names_tmm[reg]);
13441 if (reg == modrm.reg || reg == modrm.rm)
13442 strcpy (obufp, "/(bad)");
13443 }
13444
13445 if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
13446 {
13447 if (modrm.reg <= 8
13448 && (modrm.reg == modrm.rm || modrm.reg == reg))
13449 strcat (op_out[0], "/(bad)");
13450 if (modrm.rm <= 8
13451 && (modrm.rm == modrm.reg || modrm.rm == reg))
13452 strcat (op_out[1], "/(bad)");
13453 }
13454
13455 return;
13456 }
13457
13458 switch (vex.length)
13459 {
13460 case 128:
13461 switch (bytemode)
13462 {
13463 case vex_mode:
13464 case vex_vsib_q_w_dq_mode:
13465 case vex_vsib_q_w_d_mode:
13466 names = names_xmm;
13467 break;
13468 case dq_mode:
13469 if (rex & REX_W)
13470 names = names64;
13471 else
13472 names = names32;
13473 break;
13474 case mask_bd_mode:
13475 case mask_mode:
13476 if (reg > 0x7)
13477 {
13478 oappend ("(bad)");
13479 return;
13480 }
13481 names = names_mask;
13482 break;
13483 default:
13484 abort ();
13485 return;
13486 }
13487 break;
13488 case 256:
13489 switch (bytemode)
13490 {
13491 case vex_mode:
13492 names = names_ymm;
13493 break;
13494 case vex_vsib_q_w_dq_mode:
13495 case vex_vsib_q_w_d_mode:
13496 names = vex.w ? names_ymm : names_xmm;
13497 break;
13498 case mask_bd_mode:
13499 case mask_mode:
13500 if (reg > 0x7)
13501 {
13502 oappend ("(bad)");
13503 return;
13504 }
13505 names = names_mask;
13506 break;
13507 default:
13508 /* See PR binutils/20893 for a reproducer. */
13509 oappend ("(bad)");
13510 return;
13511 }
13512 break;
13513 case 512:
13514 names = names_zmm;
13515 break;
13516 default:
13517 abort ();
13518 break;
13519 }
13520 oappend (names[reg]);
13521 }
13522
13523 static void
13524 OP_VexR (int bytemode, int sizeflag)
13525 {
13526 if (modrm.mod == 3)
13527 OP_VEX (bytemode, sizeflag);
13528 }
13529
13530 static void
13531 OP_VexW (int bytemode, int sizeflag)
13532 {
13533 OP_VEX (bytemode, sizeflag);
13534
13535 if (vex.w)
13536 {
13537 /* Swap 2nd and 3rd operands. */
13538 strcpy (scratchbuf, op_out[2]);
13539 strcpy (op_out[2], op_out[1]);
13540 strcpy (op_out[1], scratchbuf);
13541 }
13542 }
13543
13544 static void
13545 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13546 {
13547 int reg;
13548 const char **names = names_xmm;
13549
13550 FETCH_DATA (the_info, codep + 1);
13551 reg = *codep++;
13552
13553 if (bytemode != x_mode && bytemode != scalar_mode)
13554 abort ();
13555
13556 reg >>= 4;
13557 if (address_mode != mode_64bit)
13558 reg &= 7;
13559
13560 if (bytemode == x_mode && vex.length == 256)
13561 names = names_ymm;
13562
13563 oappend (names[reg]);
13564
13565 if (vex.w)
13566 {
13567 /* Swap 3rd and 4th operands. */
13568 strcpy (scratchbuf, op_out[3]);
13569 strcpy (op_out[3], op_out[2]);
13570 strcpy (op_out[2], scratchbuf);
13571 }
13572 }
13573
13574 static void
13575 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
13576 int sizeflag ATTRIBUTE_UNUSED)
13577 {
13578 scratchbuf[0] = '$';
13579 print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
13580 oappend_maybe_intel (scratchbuf);
13581 }
13582
13583 static void
13584 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
13585 int sizeflag ATTRIBUTE_UNUSED)
13586 {
13587 unsigned int cmp_type;
13588
13589 if (!vex.evex)
13590 abort ();
13591
13592 FETCH_DATA (the_info, codep + 1);
13593 cmp_type = *codep++ & 0xff;
13594 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13595 If it's the case, print suffix, otherwise - print the immediate. */
13596 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13597 && cmp_type != 3
13598 && cmp_type != 7)
13599 {
13600 char suffix [3];
13601 char *p = mnemonicendp - 2;
13602
13603 /* vpcmp* can have both one- and two-lettered suffix. */
13604 if (p[0] == 'p')
13605 {
13606 p++;
13607 suffix[0] = p[0];
13608 suffix[1] = '\0';
13609 }
13610 else
13611 {
13612 suffix[0] = p[0];
13613 suffix[1] = p[1];
13614 suffix[2] = '\0';
13615 }
13616
13617 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13618 mnemonicendp += simd_cmp_op[cmp_type].len;
13619 }
13620 else
13621 {
13622 /* We have a reserved extension byte. Output it directly. */
13623 scratchbuf[0] = '$';
13624 print_operand_value (scratchbuf + 1, 1, cmp_type);
13625 oappend_maybe_intel (scratchbuf);
13626 scratchbuf[0] = '\0';
13627 }
13628 }
13629
13630 static const struct op xop_cmp_op[] =
13631 {
13632 { STRING_COMMA_LEN ("lt") },
13633 { STRING_COMMA_LEN ("le") },
13634 { STRING_COMMA_LEN ("gt") },
13635 { STRING_COMMA_LEN ("ge") },
13636 { STRING_COMMA_LEN ("eq") },
13637 { STRING_COMMA_LEN ("neq") },
13638 { STRING_COMMA_LEN ("false") },
13639 { STRING_COMMA_LEN ("true") }
13640 };
13641
13642 static void
13643 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
13644 int sizeflag ATTRIBUTE_UNUSED)
13645 {
13646 unsigned int cmp_type;
13647
13648 FETCH_DATA (the_info, codep + 1);
13649 cmp_type = *codep++ & 0xff;
13650 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13651 {
13652 char suffix[3];
13653 char *p = mnemonicendp - 2;
13654
13655 /* vpcom* can have both one- and two-lettered suffix. */
13656 if (p[0] == 'm')
13657 {
13658 p++;
13659 suffix[0] = p[0];
13660 suffix[1] = '\0';
13661 }
13662 else
13663 {
13664 suffix[0] = p[0];
13665 suffix[1] = p[1];
13666 suffix[2] = '\0';
13667 }
13668
13669 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13670 mnemonicendp += xop_cmp_op[cmp_type].len;
13671 }
13672 else
13673 {
13674 /* We have a reserved extension byte. Output it directly. */
13675 scratchbuf[0] = '$';
13676 print_operand_value (scratchbuf + 1, 1, cmp_type);
13677 oappend_maybe_intel (scratchbuf);
13678 scratchbuf[0] = '\0';
13679 }
13680 }
13681
13682 static const struct op pclmul_op[] =
13683 {
13684 { STRING_COMMA_LEN ("lql") },
13685 { STRING_COMMA_LEN ("hql") },
13686 { STRING_COMMA_LEN ("lqh") },
13687 { STRING_COMMA_LEN ("hqh") }
13688 };
13689
13690 static void
13691 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13692 int sizeflag ATTRIBUTE_UNUSED)
13693 {
13694 unsigned int pclmul_type;
13695
13696 FETCH_DATA (the_info, codep + 1);
13697 pclmul_type = *codep++ & 0xff;
13698 switch (pclmul_type)
13699 {
13700 case 0x10:
13701 pclmul_type = 2;
13702 break;
13703 case 0x11:
13704 pclmul_type = 3;
13705 break;
13706 default:
13707 break;
13708 }
13709 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13710 {
13711 char suffix [4];
13712 char *p = mnemonicendp - 3;
13713 suffix[0] = p[0];
13714 suffix[1] = p[1];
13715 suffix[2] = p[2];
13716 suffix[3] = '\0';
13717 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13718 mnemonicendp += pclmul_op[pclmul_type].len;
13719 }
13720 else
13721 {
13722 /* We have a reserved extension byte. Output it directly. */
13723 scratchbuf[0] = '$';
13724 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13725 oappend_maybe_intel (scratchbuf);
13726 scratchbuf[0] = '\0';
13727 }
13728 }
13729
13730 static void
13731 MOVSXD_Fixup (int bytemode, int sizeflag)
13732 {
13733 /* Add proper suffix to "movsxd". */
13734 char *p = mnemonicendp;
13735
13736 switch (bytemode)
13737 {
13738 case movsxd_mode:
13739 if (intel_syntax)
13740 {
13741 *p++ = 'x';
13742 *p++ = 'd';
13743 goto skip;
13744 }
13745
13746 USED_REX (REX_W);
13747 if (rex & REX_W)
13748 {
13749 *p++ = 'l';
13750 *p++ = 'q';
13751 }
13752 else
13753 {
13754 *p++ = 'x';
13755 *p++ = 'd';
13756 }
13757 break;
13758 default:
13759 oappend (INTERNAL_DISASSEMBLER_ERROR);
13760 break;
13761 }
13762
13763 skip:
13764 mnemonicendp = p;
13765 *p = '\0';
13766 OP_E (bytemode, sizeflag);
13767 }
13768
13769 static void
13770 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13771 {
13772 if (!vex.evex
13773 || (bytemode != mask_mode && bytemode != mask_bd_mode))
13774 abort ();
13775
13776 USED_REX (REX_R);
13777 if ((rex & REX_R) != 0 || !vex.r)
13778 {
13779 BadOp ();
13780 return;
13781 }
13782
13783 oappend (names_mask [modrm.reg]);
13784 }
13785
13786 static void
13787 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13788 {
13789 if (modrm.mod == 3 && vex.b)
13790 switch (bytemode)
13791 {
13792 case evex_rounding_64_mode:
13793 if (address_mode != mode_64bit)
13794 {
13795 oappend ("(bad)");
13796 break;
13797 }
13798 /* Fall through. */
13799 case evex_rounding_mode:
13800 oappend (names_rounding[vex.ll]);
13801 break;
13802 case evex_sae_mode:
13803 oappend ("{sae}");
13804 break;
13805 default:
13806 abort ();
13807 break;
13808 }
13809 }
GDB Binutils - Deliverables
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