1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte
*max_fetched
;
133 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
136 OPCODES_SIGJMP_BUF bailout
;
146 enum address_mode address_mode
;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored
;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes
;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
201 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
202 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
204 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
205 status
= (*info
->read_memory_func
) (start
,
207 addr
- priv
->max_fetched
,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv
->max_fetched
== priv
->the_buffer
)
218 (*info
->memory_error_func
) (status
, start
, info
);
219 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
222 priv
->max_fetched
= addr
;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
389 #define EXq { OP_EX, q_mode }
390 #define EXqScalar { OP_EX, q_scalar_mode }
391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
392 #define EXqS { OP_EX, q_swap_mode }
393 #define EXx { OP_EX, x_mode }
394 #define EXxS { OP_EX, x_swap_mode }
395 #define EXxmm { OP_EX, xmm_mode }
396 #define EXymm { OP_EX, ymm_mode }
397 #define EXxmmq { OP_EX, xmmq_mode }
398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
401 #define EXxmm_md { OP_EX, xmm_md_mode }
402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
411 #define MS { OP_MS, v_mode }
412 #define XS { OP_XS, v_mode }
413 #define EMCq { OP_EMC, q_mode }
414 #define MXC { OP_MXC, 0 }
415 #define OPSUF { OP_3DNowSuffix, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
430 #define EXVexW { OP_EX_VexW, x_mode }
431 #define EXdVexW { OP_EX_VexW, d_mode }
432 #define EXqVexW { OP_EX_VexW, q_mode }
433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
434 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
435 #define XMVexW { OP_XMM_VexW, 0 }
436 #define XMVexI4 { OP_REG_VexI4, x_mode }
437 #define PCLMUL { PCLMUL_Fixup, 0 }
438 #define VCMP { VCMP_Fixup, 0 }
439 #define VPCMP { VPCMP_Fixup, 0 }
440 #define VPCOM { VPCOM_Fixup, 0 }
442 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
443 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
446 #define XMask { OP_Mask, mask_mode }
447 #define MaskG { OP_G, mask_mode }
448 #define MaskE { OP_E, mask_mode }
449 #define MaskBDE { OP_E, mask_bd_mode }
450 #define MaskR { OP_R, mask_mode }
451 #define MaskVex { OP_VEX, mask_mode }
453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
458 /* Used handle "rep" prefix for string instructions. */
459 #define Xbr { REP_Fixup, eSI_reg }
460 #define Xvr { REP_Fixup, eSI_reg }
461 #define Ybr { REP_Fixup, eDI_reg }
462 #define Yvr { REP_Fixup, eDI_reg }
463 #define Yzr { REP_Fixup, eDI_reg }
464 #define indirDXr { REP_Fixup, indir_dx_reg }
465 #define ALr { REP_Fixup, al_reg }
466 #define eAXr { REP_Fixup, eAX_reg }
468 /* Used handle HLE prefix for lockable instructions. */
469 #define Ebh1 { HLE_Fixup1, b_mode }
470 #define Evh1 { HLE_Fixup1, v_mode }
471 #define Ebh2 { HLE_Fixup2, b_mode }
472 #define Evh2 { HLE_Fixup2, v_mode }
473 #define Ebh3 { HLE_Fixup3, b_mode }
474 #define Evh3 { HLE_Fixup3, v_mode }
476 #define BND { BND_Fixup, 0 }
477 #define NOTRACK { NOTRACK_Fixup, 0 }
479 #define cond_jump_flag { NULL, cond_jump_mode }
480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
482 /* bits in sizeflag */
483 #define SUFFIX_ALWAYS 4
491 /* byte operand with operand swapped */
493 /* byte operand, sign extend like 'T' suffix */
495 /* operand size depends on prefixes */
497 /* operand size depends on prefixes with operand swapped */
499 /* operand size depends on address prefix */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode
,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* XMM register or double/quad word memory operand, depending on
542 /* 16-byte XMM, word, double word or quad word operand. */
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
546 /* 32-byte YMM operand */
548 /* quad word, ymmword or zmmword memory operand. */
550 /* 32-byte YMM or 16-byte word operand */
552 /* d_mode in 32bit, q_mode in 64bit mode. */
554 /* pair of v_mode operands */
559 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
561 /* operand size depends on REX prefixes. */
563 /* registers like dq_mode, memory like w_mode. */
567 /* bounds operand with operand swapped */
569 /* 4- or 6-byte pointer operand */
572 /* v_mode for indirect branch opcodes. */
574 /* v_mode for stack-related opcodes. */
576 /* non-quad operand size depends on prefixes */
578 /* 16-byte operand */
580 /* registers like dq_mode, memory like b_mode. */
582 /* registers like d_mode, memory like b_mode. */
584 /* registers like d_mode, memory like w_mode. */
586 /* registers like dq_mode, memory like d_mode. */
588 /* normal vex mode */
590 /* 128bit vex mode */
592 /* 256bit vex mode */
594 /* operand size depends on the VEX.W bit. */
597 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
598 vex_vsib_d_w_dq_mode
,
599 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
601 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
602 vex_vsib_q_w_dq_mode
,
603 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
606 /* scalar, ignore vector length. */
608 /* like b_mode, ignore vector length. */
610 /* like w_mode, ignore vector length. */
612 /* like d_mode, ignore vector length. */
614 /* like d_swap_mode, ignore vector length. */
616 /* like q_mode, ignore vector length. */
618 /* like q_swap_mode, ignore vector length. */
620 /* like vex_mode, ignore vector length. */
622 /* like vex_w_dq_mode, ignore vector length. */
623 vex_scalar_w_dq_mode
,
625 /* Static rounding. */
627 /* Static rounding, 64-bit mode only. */
628 evex_rounding_64_mode
,
629 /* Supress all exceptions. */
632 /* Mask register operand. */
634 /* Mask register operand. */
702 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
704 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
705 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
706 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
707 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
708 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
709 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
710 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
711 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
712 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
713 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
714 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
715 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
716 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
717 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
718 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
719 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
847 MOD_VEX_0F12_PREFIX_0
,
849 MOD_VEX_0F16_PREFIX_0
,
852 MOD_VEX_W_0_0F41_P_0_LEN_1
,
853 MOD_VEX_W_1_0F41_P_0_LEN_1
,
854 MOD_VEX_W_0_0F41_P_2_LEN_1
,
855 MOD_VEX_W_1_0F41_P_2_LEN_1
,
856 MOD_VEX_W_0_0F42_P_0_LEN_1
,
857 MOD_VEX_W_1_0F42_P_0_LEN_1
,
858 MOD_VEX_W_0_0F42_P_2_LEN_1
,
859 MOD_VEX_W_1_0F42_P_2_LEN_1
,
860 MOD_VEX_W_0_0F44_P_0_LEN_1
,
861 MOD_VEX_W_1_0F44_P_0_LEN_1
,
862 MOD_VEX_W_0_0F44_P_2_LEN_1
,
863 MOD_VEX_W_1_0F44_P_2_LEN_1
,
864 MOD_VEX_W_0_0F45_P_0_LEN_1
,
865 MOD_VEX_W_1_0F45_P_0_LEN_1
,
866 MOD_VEX_W_0_0F45_P_2_LEN_1
,
867 MOD_VEX_W_1_0F45_P_2_LEN_1
,
868 MOD_VEX_W_0_0F46_P_0_LEN_1
,
869 MOD_VEX_W_1_0F46_P_0_LEN_1
,
870 MOD_VEX_W_0_0F46_P_2_LEN_1
,
871 MOD_VEX_W_1_0F46_P_2_LEN_1
,
872 MOD_VEX_W_0_0F47_P_0_LEN_1
,
873 MOD_VEX_W_1_0F47_P_0_LEN_1
,
874 MOD_VEX_W_0_0F47_P_2_LEN_1
,
875 MOD_VEX_W_1_0F47_P_2_LEN_1
,
876 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
877 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
878 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
879 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
880 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
881 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
882 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
894 MOD_VEX_W_0_0F91_P_0_LEN_0
,
895 MOD_VEX_W_1_0F91_P_0_LEN_0
,
896 MOD_VEX_W_0_0F91_P_2_LEN_0
,
897 MOD_VEX_W_1_0F91_P_2_LEN_0
,
898 MOD_VEX_W_0_0F92_P_0_LEN_0
,
899 MOD_VEX_W_0_0F92_P_2_LEN_0
,
900 MOD_VEX_0F92_P_3_LEN_0
,
901 MOD_VEX_W_0_0F93_P_0_LEN_0
,
902 MOD_VEX_W_0_0F93_P_2_LEN_0
,
903 MOD_VEX_0F93_P_3_LEN_0
,
904 MOD_VEX_W_0_0F98_P_0_LEN_0
,
905 MOD_VEX_W_1_0F98_P_0_LEN_0
,
906 MOD_VEX_W_0_0F98_P_2_LEN_0
,
907 MOD_VEX_W_1_0F98_P_2_LEN_0
,
908 MOD_VEX_W_0_0F99_P_0_LEN_0
,
909 MOD_VEX_W_1_0F99_P_0_LEN_0
,
910 MOD_VEX_W_0_0F99_P_2_LEN_0
,
911 MOD_VEX_W_1_0F99_P_2_LEN_0
,
914 MOD_VEX_0FD7_PREFIX_2
,
915 MOD_VEX_0FE7_PREFIX_2
,
916 MOD_VEX_0FF0_PREFIX_3
,
917 MOD_VEX_0F381A_PREFIX_2
,
918 MOD_VEX_0F382A_PREFIX_2
,
919 MOD_VEX_0F382C_PREFIX_2
,
920 MOD_VEX_0F382D_PREFIX_2
,
921 MOD_VEX_0F382E_PREFIX_2
,
922 MOD_VEX_0F382F_PREFIX_2
,
923 MOD_VEX_0F385A_PREFIX_2
,
924 MOD_VEX_0F388C_PREFIX_2
,
925 MOD_VEX_0F388E_PREFIX_2
,
926 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
927 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
928 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
929 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
930 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
932 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
933 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
935 MOD_EVEX_0F10_PREFIX_1
,
936 MOD_EVEX_0F10_PREFIX_3
,
937 MOD_EVEX_0F11_PREFIX_1
,
938 MOD_EVEX_0F11_PREFIX_3
,
939 MOD_EVEX_0F12_PREFIX_0
,
940 MOD_EVEX_0F16_PREFIX_0
,
941 MOD_EVEX_0F38C6_REG_1
,
942 MOD_EVEX_0F38C6_REG_2
,
943 MOD_EVEX_0F38C6_REG_5
,
944 MOD_EVEX_0F38C6_REG_6
,
945 MOD_EVEX_0F38C7_REG_1
,
946 MOD_EVEX_0F38C7_REG_2
,
947 MOD_EVEX_0F38C7_REG_5
,
948 MOD_EVEX_0F38C7_REG_6
969 PREFIX_MOD_0_0F01_REG_5
,
970 PREFIX_MOD_3_0F01_REG_5_RM_0
,
971 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1017 PREFIX_MOD_0_0FAE_REG_4
,
1018 PREFIX_MOD_3_0FAE_REG_4
,
1019 PREFIX_MOD_0_0FAE_REG_5
,
1020 PREFIX_MOD_3_0FAE_REG_5
,
1021 PREFIX_MOD_0_0FAE_REG_6
,
1022 PREFIX_MOD_1_0FAE_REG_6
,
1029 PREFIX_MOD_0_0FC7_REG_6
,
1030 PREFIX_MOD_3_0FC7_REG_6
,
1031 PREFIX_MOD_3_0FC7_REG_7
,
1161 PREFIX_VEX_0F71_REG_2
,
1162 PREFIX_VEX_0F71_REG_4
,
1163 PREFIX_VEX_0F71_REG_6
,
1164 PREFIX_VEX_0F72_REG_2
,
1165 PREFIX_VEX_0F72_REG_4
,
1166 PREFIX_VEX_0F72_REG_6
,
1167 PREFIX_VEX_0F73_REG_2
,
1168 PREFIX_VEX_0F73_REG_3
,
1169 PREFIX_VEX_0F73_REG_6
,
1170 PREFIX_VEX_0F73_REG_7
,
1343 PREFIX_VEX_0F38F3_REG_1
,
1344 PREFIX_VEX_0F38F3_REG_2
,
1345 PREFIX_VEX_0F38F3_REG_3
,
1464 PREFIX_EVEX_0F71_REG_2
,
1465 PREFIX_EVEX_0F71_REG_4
,
1466 PREFIX_EVEX_0F71_REG_6
,
1467 PREFIX_EVEX_0F72_REG_0
,
1468 PREFIX_EVEX_0F72_REG_1
,
1469 PREFIX_EVEX_0F72_REG_2
,
1470 PREFIX_EVEX_0F72_REG_4
,
1471 PREFIX_EVEX_0F72_REG_6
,
1472 PREFIX_EVEX_0F73_REG_2
,
1473 PREFIX_EVEX_0F73_REG_3
,
1474 PREFIX_EVEX_0F73_REG_6
,
1475 PREFIX_EVEX_0F73_REG_7
,
1672 PREFIX_EVEX_0F38C6_REG_1
,
1673 PREFIX_EVEX_0F38C6_REG_2
,
1674 PREFIX_EVEX_0F38C6_REG_5
,
1675 PREFIX_EVEX_0F38C6_REG_6
,
1676 PREFIX_EVEX_0F38C7_REG_1
,
1677 PREFIX_EVEX_0F38C7_REG_2
,
1678 PREFIX_EVEX_0F38C7_REG_5
,
1679 PREFIX_EVEX_0F38C7_REG_6
,
1781 THREE_BYTE_0F38
= 0,
1808 VEX_LEN_0F12_P_0_M_0
= 0,
1809 VEX_LEN_0F12_P_0_M_1
,
1812 VEX_LEN_0F16_P_0_M_0
,
1813 VEX_LEN_0F16_P_0_M_1
,
1850 VEX_LEN_0FAE_R_2_M_0
,
1851 VEX_LEN_0FAE_R_3_M_0
,
1858 VEX_LEN_0F381A_P_2_M_0
,
1861 VEX_LEN_0F385A_P_2_M_0
,
1864 VEX_LEN_0F38F3_R_1_P_0
,
1865 VEX_LEN_0F38F3_R_2_P_0
,
1866 VEX_LEN_0F38F3_R_3_P_0
,
1909 VEX_LEN_0FXOP_08_CC
,
1910 VEX_LEN_0FXOP_08_CD
,
1911 VEX_LEN_0FXOP_08_CE
,
1912 VEX_LEN_0FXOP_08_CF
,
1913 VEX_LEN_0FXOP_08_EC
,
1914 VEX_LEN_0FXOP_08_ED
,
1915 VEX_LEN_0FXOP_08_EE
,
1916 VEX_LEN_0FXOP_08_EF
,
1917 VEX_LEN_0FXOP_09_80
,
1923 EVEX_LEN_0F6E_P_2
= 0,
1927 EVEX_LEN_0F3819_P_2_W_0
,
1928 EVEX_LEN_0F3819_P_2_W_1
,
1929 EVEX_LEN_0F381A_P_2_W_0
,
1930 EVEX_LEN_0F381A_P_2_W_1
,
1931 EVEX_LEN_0F381B_P_2_W_0
,
1932 EVEX_LEN_0F381B_P_2_W_1
,
1933 EVEX_LEN_0F385A_P_2_W_0
,
1934 EVEX_LEN_0F385A_P_2_W_1
,
1935 EVEX_LEN_0F385B_P_2_W_0
,
1936 EVEX_LEN_0F385B_P_2_W_1
,
1937 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1938 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1939 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1940 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1941 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1943 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1945 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1946 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1947 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1948 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1949 EVEX_LEN_0F3A18_P_2_W_0
,
1950 EVEX_LEN_0F3A18_P_2_W_1
,
1951 EVEX_LEN_0F3A19_P_2_W_0
,
1952 EVEX_LEN_0F3A19_P_2_W_1
,
1953 EVEX_LEN_0F3A1A_P_2_W_0
,
1954 EVEX_LEN_0F3A1A_P_2_W_1
,
1955 EVEX_LEN_0F3A1B_P_2_W_0
,
1956 EVEX_LEN_0F3A1B_P_2_W_1
,
1957 EVEX_LEN_0F3A23_P_2_W_0
,
1958 EVEX_LEN_0F3A23_P_2_W_1
,
1959 EVEX_LEN_0F3A38_P_2_W_0
,
1960 EVEX_LEN_0F3A38_P_2_W_1
,
1961 EVEX_LEN_0F3A39_P_2_W_0
,
1962 EVEX_LEN_0F3A39_P_2_W_1
,
1963 EVEX_LEN_0F3A3A_P_2_W_0
,
1964 EVEX_LEN_0F3A3A_P_2_W_1
,
1965 EVEX_LEN_0F3A3B_P_2_W_0
,
1966 EVEX_LEN_0F3A3B_P_2_W_1
,
1967 EVEX_LEN_0F3A43_P_2_W_0
,
1968 EVEX_LEN_0F3A43_P_2_W_1
1973 VEX_W_0F41_P_0_LEN_1
= 0,
1974 VEX_W_0F41_P_2_LEN_1
,
1975 VEX_W_0F42_P_0_LEN_1
,
1976 VEX_W_0F42_P_2_LEN_1
,
1977 VEX_W_0F44_P_0_LEN_0
,
1978 VEX_W_0F44_P_2_LEN_0
,
1979 VEX_W_0F45_P_0_LEN_1
,
1980 VEX_W_0F45_P_2_LEN_1
,
1981 VEX_W_0F46_P_0_LEN_1
,
1982 VEX_W_0F46_P_2_LEN_1
,
1983 VEX_W_0F47_P_0_LEN_1
,
1984 VEX_W_0F47_P_2_LEN_1
,
1985 VEX_W_0F4A_P_0_LEN_1
,
1986 VEX_W_0F4A_P_2_LEN_1
,
1987 VEX_W_0F4B_P_0_LEN_1
,
1988 VEX_W_0F4B_P_2_LEN_1
,
1989 VEX_W_0F90_P_0_LEN_0
,
1990 VEX_W_0F90_P_2_LEN_0
,
1991 VEX_W_0F91_P_0_LEN_0
,
1992 VEX_W_0F91_P_2_LEN_0
,
1993 VEX_W_0F92_P_0_LEN_0
,
1994 VEX_W_0F92_P_2_LEN_0
,
1995 VEX_W_0F93_P_0_LEN_0
,
1996 VEX_W_0F93_P_2_LEN_0
,
1997 VEX_W_0F98_P_0_LEN_0
,
1998 VEX_W_0F98_P_2_LEN_0
,
1999 VEX_W_0F99_P_0_LEN_0
,
2000 VEX_W_0F99_P_2_LEN_0
,
2008 VEX_W_0F381A_P_2_M_0
,
2009 VEX_W_0F382C_P_2_M_0
,
2010 VEX_W_0F382D_P_2_M_0
,
2011 VEX_W_0F382E_P_2_M_0
,
2012 VEX_W_0F382F_P_2_M_0
,
2017 VEX_W_0F385A_P_2_M_0
,
2029 VEX_W_0F3A30_P_2_LEN_0
,
2030 VEX_W_0F3A31_P_2_LEN_0
,
2031 VEX_W_0F3A32_P_2_LEN_0
,
2032 VEX_W_0F3A33_P_2_LEN_0
,
2045 EVEX_W_0F10_P_1_M_0
,
2046 EVEX_W_0F10_P_1_M_1
,
2048 EVEX_W_0F10_P_3_M_0
,
2049 EVEX_W_0F10_P_3_M_1
,
2051 EVEX_W_0F11_P_1_M_0
,
2052 EVEX_W_0F11_P_1_M_1
,
2054 EVEX_W_0F11_P_3_M_0
,
2055 EVEX_W_0F11_P_3_M_1
,
2056 EVEX_W_0F12_P_0_M_0
,
2057 EVEX_W_0F12_P_0_M_1
,
2067 EVEX_W_0F16_P_0_M_0
,
2068 EVEX_W_0F16_P_0_M_1
,
2137 EVEX_W_0F72_R_2_P_2
,
2138 EVEX_W_0F72_R_6_P_2
,
2139 EVEX_W_0F73_R_2_P_2
,
2140 EVEX_W_0F73_R_6_P_2
,
2250 EVEX_W_0F38C7_R_1_P_2
,
2251 EVEX_W_0F38C7_R_2_P_2
,
2252 EVEX_W_0F38C7_R_5_P_2
,
2253 EVEX_W_0F38C7_R_6_P_2
,
2292 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2301 unsigned int prefix_requirement
;
2304 /* Upper case letters in the instruction names here are macros.
2305 'A' => print 'b' if no register operands or suffix_always is true
2306 'B' => print 'b' if suffix_always is true
2307 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2309 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2310 suffix_always is true
2311 'E' => print 'e' if 32-bit form of jcxz
2312 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2313 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2314 'H' => print ",pt" or ",pn" branch hint
2315 'I' => honor following macro letter even in Intel mode (implemented only
2316 for some of the macro letters)
2318 'K' => print 'd' or 'q' if rex prefix is present.
2319 'L' => print 'l' if suffix_always is true
2320 'M' => print 'r' if intel_mnemonic is false.
2321 'N' => print 'n' if instruction has no wait "prefix"
2322 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2323 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2324 or suffix_always is true. print 'q' if rex prefix is present.
2325 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2327 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2328 'S' => print 'w', 'l' or 'q' if suffix_always is true
2329 'T' => print 'q' in 64bit mode if instruction has no operand size
2330 prefix and behave as 'P' otherwise
2331 'U' => print 'q' in 64bit mode if instruction has no operand size
2332 prefix and behave as 'Q' otherwise
2333 'V' => print 'q' in 64bit mode if instruction has no operand size
2334 prefix and behave as 'S' otherwise
2335 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2336 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2338 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2339 '!' => change condition from true to false or from false to true.
2340 '%' => add 1 upper case letter to the macro.
2341 '^' => print 'w' or 'l' depending on operand size prefix or
2342 suffix_always is true (lcall/ljmp).
2343 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2344 on operand size prefix.
2345 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2346 has no operand size prefix for AMD64 ISA, behave as 'P'
2349 2 upper case letter macros:
2350 "XY" => print 'x' or 'y' if suffix_always is true or no register
2351 operands and no broadcast.
2352 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2353 register operands and no broadcast.
2354 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2355 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2356 or suffix_always is true
2357 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2358 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2359 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2360 "LW" => print 'd', 'q' depending on the VEX.W bit
2361 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2362 an operand size prefix, or suffix_always is true. print
2363 'q' if rex prefix is present.
2365 Many of the above letters print nothing in Intel mode. See "putop"
2368 Braces '{' and '}', and vertical bars '|', indicate alternative
2369 mnemonic strings for AT&T and Intel. */
2371 static const struct dis386 dis386
[] = {
2373 { "addB", { Ebh1
, Gb
}, 0 },
2374 { "addS", { Evh1
, Gv
}, 0 },
2375 { "addB", { Gb
, EbS
}, 0 },
2376 { "addS", { Gv
, EvS
}, 0 },
2377 { "addB", { AL
, Ib
}, 0 },
2378 { "addS", { eAX
, Iv
}, 0 },
2379 { X86_64_TABLE (X86_64_06
) },
2380 { X86_64_TABLE (X86_64_07
) },
2382 { "orB", { Ebh1
, Gb
}, 0 },
2383 { "orS", { Evh1
, Gv
}, 0 },
2384 { "orB", { Gb
, EbS
}, 0 },
2385 { "orS", { Gv
, EvS
}, 0 },
2386 { "orB", { AL
, Ib
}, 0 },
2387 { "orS", { eAX
, Iv
}, 0 },
2388 { X86_64_TABLE (X86_64_0D
) },
2389 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2391 { "adcB", { Ebh1
, Gb
}, 0 },
2392 { "adcS", { Evh1
, Gv
}, 0 },
2393 { "adcB", { Gb
, EbS
}, 0 },
2394 { "adcS", { Gv
, EvS
}, 0 },
2395 { "adcB", { AL
, Ib
}, 0 },
2396 { "adcS", { eAX
, Iv
}, 0 },
2397 { X86_64_TABLE (X86_64_16
) },
2398 { X86_64_TABLE (X86_64_17
) },
2400 { "sbbB", { Ebh1
, Gb
}, 0 },
2401 { "sbbS", { Evh1
, Gv
}, 0 },
2402 { "sbbB", { Gb
, EbS
}, 0 },
2403 { "sbbS", { Gv
, EvS
}, 0 },
2404 { "sbbB", { AL
, Ib
}, 0 },
2405 { "sbbS", { eAX
, Iv
}, 0 },
2406 { X86_64_TABLE (X86_64_1E
) },
2407 { X86_64_TABLE (X86_64_1F
) },
2409 { "andB", { Ebh1
, Gb
}, 0 },
2410 { "andS", { Evh1
, Gv
}, 0 },
2411 { "andB", { Gb
, EbS
}, 0 },
2412 { "andS", { Gv
, EvS
}, 0 },
2413 { "andB", { AL
, Ib
}, 0 },
2414 { "andS", { eAX
, Iv
}, 0 },
2415 { Bad_Opcode
}, /* SEG ES prefix */
2416 { X86_64_TABLE (X86_64_27
) },
2418 { "subB", { Ebh1
, Gb
}, 0 },
2419 { "subS", { Evh1
, Gv
}, 0 },
2420 { "subB", { Gb
, EbS
}, 0 },
2421 { "subS", { Gv
, EvS
}, 0 },
2422 { "subB", { AL
, Ib
}, 0 },
2423 { "subS", { eAX
, Iv
}, 0 },
2424 { Bad_Opcode
}, /* SEG CS prefix */
2425 { X86_64_TABLE (X86_64_2F
) },
2427 { "xorB", { Ebh1
, Gb
}, 0 },
2428 { "xorS", { Evh1
, Gv
}, 0 },
2429 { "xorB", { Gb
, EbS
}, 0 },
2430 { "xorS", { Gv
, EvS
}, 0 },
2431 { "xorB", { AL
, Ib
}, 0 },
2432 { "xorS", { eAX
, Iv
}, 0 },
2433 { Bad_Opcode
}, /* SEG SS prefix */
2434 { X86_64_TABLE (X86_64_37
) },
2436 { "cmpB", { Eb
, Gb
}, 0 },
2437 { "cmpS", { Ev
, Gv
}, 0 },
2438 { "cmpB", { Gb
, EbS
}, 0 },
2439 { "cmpS", { Gv
, EvS
}, 0 },
2440 { "cmpB", { AL
, Ib
}, 0 },
2441 { "cmpS", { eAX
, Iv
}, 0 },
2442 { Bad_Opcode
}, /* SEG DS prefix */
2443 { X86_64_TABLE (X86_64_3F
) },
2445 { "inc{S|}", { RMeAX
}, 0 },
2446 { "inc{S|}", { RMeCX
}, 0 },
2447 { "inc{S|}", { RMeDX
}, 0 },
2448 { "inc{S|}", { RMeBX
}, 0 },
2449 { "inc{S|}", { RMeSP
}, 0 },
2450 { "inc{S|}", { RMeBP
}, 0 },
2451 { "inc{S|}", { RMeSI
}, 0 },
2452 { "inc{S|}", { RMeDI
}, 0 },
2454 { "dec{S|}", { RMeAX
}, 0 },
2455 { "dec{S|}", { RMeCX
}, 0 },
2456 { "dec{S|}", { RMeDX
}, 0 },
2457 { "dec{S|}", { RMeBX
}, 0 },
2458 { "dec{S|}", { RMeSP
}, 0 },
2459 { "dec{S|}", { RMeBP
}, 0 },
2460 { "dec{S|}", { RMeSI
}, 0 },
2461 { "dec{S|}", { RMeDI
}, 0 },
2463 { "pushV", { RMrAX
}, 0 },
2464 { "pushV", { RMrCX
}, 0 },
2465 { "pushV", { RMrDX
}, 0 },
2466 { "pushV", { RMrBX
}, 0 },
2467 { "pushV", { RMrSP
}, 0 },
2468 { "pushV", { RMrBP
}, 0 },
2469 { "pushV", { RMrSI
}, 0 },
2470 { "pushV", { RMrDI
}, 0 },
2472 { "popV", { RMrAX
}, 0 },
2473 { "popV", { RMrCX
}, 0 },
2474 { "popV", { RMrDX
}, 0 },
2475 { "popV", { RMrBX
}, 0 },
2476 { "popV", { RMrSP
}, 0 },
2477 { "popV", { RMrBP
}, 0 },
2478 { "popV", { RMrSI
}, 0 },
2479 { "popV", { RMrDI
}, 0 },
2481 { X86_64_TABLE (X86_64_60
) },
2482 { X86_64_TABLE (X86_64_61
) },
2483 { X86_64_TABLE (X86_64_62
) },
2484 { X86_64_TABLE (X86_64_63
) },
2485 { Bad_Opcode
}, /* seg fs */
2486 { Bad_Opcode
}, /* seg gs */
2487 { Bad_Opcode
}, /* op size prefix */
2488 { Bad_Opcode
}, /* adr size prefix */
2490 { "pushT", { sIv
}, 0 },
2491 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2492 { "pushT", { sIbT
}, 0 },
2493 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2494 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2495 { X86_64_TABLE (X86_64_6D
) },
2496 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2497 { X86_64_TABLE (X86_64_6F
) },
2499 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2508 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2510 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2511 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2512 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2513 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2514 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2515 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2517 { REG_TABLE (REG_80
) },
2518 { REG_TABLE (REG_81
) },
2519 { X86_64_TABLE (X86_64_82
) },
2520 { REG_TABLE (REG_83
) },
2521 { "testB", { Eb
, Gb
}, 0 },
2522 { "testS", { Ev
, Gv
}, 0 },
2523 { "xchgB", { Ebh2
, Gb
}, 0 },
2524 { "xchgS", { Evh2
, Gv
}, 0 },
2526 { "movB", { Ebh3
, Gb
}, 0 },
2527 { "movS", { Evh3
, Gv
}, 0 },
2528 { "movB", { Gb
, EbS
}, 0 },
2529 { "movS", { Gv
, EvS
}, 0 },
2530 { "movD", { Sv
, Sw
}, 0 },
2531 { MOD_TABLE (MOD_8D
) },
2532 { "movD", { Sw
, Sv
}, 0 },
2533 { REG_TABLE (REG_8F
) },
2535 { PREFIX_TABLE (PREFIX_90
) },
2536 { "xchgS", { RMeCX
, eAX
}, 0 },
2537 { "xchgS", { RMeDX
, eAX
}, 0 },
2538 { "xchgS", { RMeBX
, eAX
}, 0 },
2539 { "xchgS", { RMeSP
, eAX
}, 0 },
2540 { "xchgS", { RMeBP
, eAX
}, 0 },
2541 { "xchgS", { RMeSI
, eAX
}, 0 },
2542 { "xchgS", { RMeDI
, eAX
}, 0 },
2544 { "cW{t|}R", { XX
}, 0 },
2545 { "cR{t|}O", { XX
}, 0 },
2546 { X86_64_TABLE (X86_64_9A
) },
2547 { Bad_Opcode
}, /* fwait */
2548 { "pushfT", { XX
}, 0 },
2549 { "popfT", { XX
}, 0 },
2550 { "sahf", { XX
}, 0 },
2551 { "lahf", { XX
}, 0 },
2553 { "mov%LB", { AL
, Ob
}, 0 },
2554 { "mov%LS", { eAX
, Ov
}, 0 },
2555 { "mov%LB", { Ob
, AL
}, 0 },
2556 { "mov%LS", { Ov
, eAX
}, 0 },
2557 { "movs{b|}", { Ybr
, Xb
}, 0 },
2558 { "movs{R|}", { Yvr
, Xv
}, 0 },
2559 { "cmps{b|}", { Xb
, Yb
}, 0 },
2560 { "cmps{R|}", { Xv
, Yv
}, 0 },
2562 { "testB", { AL
, Ib
}, 0 },
2563 { "testS", { eAX
, Iv
}, 0 },
2564 { "stosB", { Ybr
, AL
}, 0 },
2565 { "stosS", { Yvr
, eAX
}, 0 },
2566 { "lodsB", { ALr
, Xb
}, 0 },
2567 { "lodsS", { eAXr
, Xv
}, 0 },
2568 { "scasB", { AL
, Yb
}, 0 },
2569 { "scasS", { eAX
, Yv
}, 0 },
2571 { "movB", { RMAL
, Ib
}, 0 },
2572 { "movB", { RMCL
, Ib
}, 0 },
2573 { "movB", { RMDL
, Ib
}, 0 },
2574 { "movB", { RMBL
, Ib
}, 0 },
2575 { "movB", { RMAH
, Ib
}, 0 },
2576 { "movB", { RMCH
, Ib
}, 0 },
2577 { "movB", { RMDH
, Ib
}, 0 },
2578 { "movB", { RMBH
, Ib
}, 0 },
2580 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2581 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2582 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2583 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2584 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2585 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2586 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2587 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2589 { REG_TABLE (REG_C0
) },
2590 { REG_TABLE (REG_C1
) },
2591 { "retT", { Iw
, BND
}, 0 },
2592 { "retT", { BND
}, 0 },
2593 { X86_64_TABLE (X86_64_C4
) },
2594 { X86_64_TABLE (X86_64_C5
) },
2595 { REG_TABLE (REG_C6
) },
2596 { REG_TABLE (REG_C7
) },
2598 { "enterT", { Iw
, Ib
}, 0 },
2599 { "leaveT", { XX
}, 0 },
2600 { "Jret{|f}P", { Iw
}, 0 },
2601 { "Jret{|f}P", { XX
}, 0 },
2602 { "int3", { XX
}, 0 },
2603 { "int", { Ib
}, 0 },
2604 { X86_64_TABLE (X86_64_CE
) },
2605 { "iret%LP", { XX
}, 0 },
2607 { REG_TABLE (REG_D0
) },
2608 { REG_TABLE (REG_D1
) },
2609 { REG_TABLE (REG_D2
) },
2610 { REG_TABLE (REG_D3
) },
2611 { X86_64_TABLE (X86_64_D4
) },
2612 { X86_64_TABLE (X86_64_D5
) },
2614 { "xlat", { DSBX
}, 0 },
2625 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2626 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2627 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2628 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2629 { "inB", { AL
, Ib
}, 0 },
2630 { "inG", { zAX
, Ib
}, 0 },
2631 { "outB", { Ib
, AL
}, 0 },
2632 { "outG", { Ib
, zAX
}, 0 },
2634 { X86_64_TABLE (X86_64_E8
) },
2635 { X86_64_TABLE (X86_64_E9
) },
2636 { X86_64_TABLE (X86_64_EA
) },
2637 { "jmp", { Jb
, BND
}, 0 },
2638 { "inB", { AL
, indirDX
}, 0 },
2639 { "inG", { zAX
, indirDX
}, 0 },
2640 { "outB", { indirDX
, AL
}, 0 },
2641 { "outG", { indirDX
, zAX
}, 0 },
2643 { Bad_Opcode
}, /* lock prefix */
2644 { "icebp", { XX
}, 0 },
2645 { Bad_Opcode
}, /* repne */
2646 { Bad_Opcode
}, /* repz */
2647 { "hlt", { XX
}, 0 },
2648 { "cmc", { XX
}, 0 },
2649 { REG_TABLE (REG_F6
) },
2650 { REG_TABLE (REG_F7
) },
2652 { "clc", { XX
}, 0 },
2653 { "stc", { XX
}, 0 },
2654 { "cli", { XX
}, 0 },
2655 { "sti", { XX
}, 0 },
2656 { "cld", { XX
}, 0 },
2657 { "std", { XX
}, 0 },
2658 { REG_TABLE (REG_FE
) },
2659 { REG_TABLE (REG_FF
) },
2662 static const struct dis386 dis386_twobyte
[] = {
2664 { REG_TABLE (REG_0F00
) },
2665 { REG_TABLE (REG_0F01
) },
2666 { "larS", { Gv
, Ew
}, 0 },
2667 { "lslS", { Gv
, Ew
}, 0 },
2669 { "syscall", { XX
}, 0 },
2670 { "clts", { XX
}, 0 },
2671 { "sysret%LP", { XX
}, 0 },
2673 { "invd", { XX
}, 0 },
2674 { PREFIX_TABLE (PREFIX_0F09
) },
2676 { "ud2", { XX
}, 0 },
2678 { REG_TABLE (REG_0F0D
) },
2679 { "femms", { XX
}, 0 },
2680 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2682 { PREFIX_TABLE (PREFIX_0F10
) },
2683 { PREFIX_TABLE (PREFIX_0F11
) },
2684 { PREFIX_TABLE (PREFIX_0F12
) },
2685 { MOD_TABLE (MOD_0F13
) },
2686 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2687 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2688 { PREFIX_TABLE (PREFIX_0F16
) },
2689 { MOD_TABLE (MOD_0F17
) },
2691 { REG_TABLE (REG_0F18
) },
2692 { "nopQ", { Ev
}, 0 },
2693 { PREFIX_TABLE (PREFIX_0F1A
) },
2694 { PREFIX_TABLE (PREFIX_0F1B
) },
2695 { PREFIX_TABLE (PREFIX_0F1C
) },
2696 { "nopQ", { Ev
}, 0 },
2697 { PREFIX_TABLE (PREFIX_0F1E
) },
2698 { "nopQ", { Ev
}, 0 },
2700 { "movZ", { Rm
, Cm
}, 0 },
2701 { "movZ", { Rm
, Dm
}, 0 },
2702 { "movZ", { Cm
, Rm
}, 0 },
2703 { "movZ", { Dm
, Rm
}, 0 },
2704 { MOD_TABLE (MOD_0F24
) },
2706 { MOD_TABLE (MOD_0F26
) },
2709 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2710 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2711 { PREFIX_TABLE (PREFIX_0F2A
) },
2712 { PREFIX_TABLE (PREFIX_0F2B
) },
2713 { PREFIX_TABLE (PREFIX_0F2C
) },
2714 { PREFIX_TABLE (PREFIX_0F2D
) },
2715 { PREFIX_TABLE (PREFIX_0F2E
) },
2716 { PREFIX_TABLE (PREFIX_0F2F
) },
2718 { "wrmsr", { XX
}, 0 },
2719 { "rdtsc", { XX
}, 0 },
2720 { "rdmsr", { XX
}, 0 },
2721 { "rdpmc", { XX
}, 0 },
2722 { "sysenter", { XX
}, 0 },
2723 { "sysexit", { XX
}, 0 },
2725 { "getsec", { XX
}, 0 },
2727 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2729 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2736 { "cmovoS", { Gv
, Ev
}, 0 },
2737 { "cmovnoS", { Gv
, Ev
}, 0 },
2738 { "cmovbS", { Gv
, Ev
}, 0 },
2739 { "cmovaeS", { Gv
, Ev
}, 0 },
2740 { "cmoveS", { Gv
, Ev
}, 0 },
2741 { "cmovneS", { Gv
, Ev
}, 0 },
2742 { "cmovbeS", { Gv
, Ev
}, 0 },
2743 { "cmovaS", { Gv
, Ev
}, 0 },
2745 { "cmovsS", { Gv
, Ev
}, 0 },
2746 { "cmovnsS", { Gv
, Ev
}, 0 },
2747 { "cmovpS", { Gv
, Ev
}, 0 },
2748 { "cmovnpS", { Gv
, Ev
}, 0 },
2749 { "cmovlS", { Gv
, Ev
}, 0 },
2750 { "cmovgeS", { Gv
, Ev
}, 0 },
2751 { "cmovleS", { Gv
, Ev
}, 0 },
2752 { "cmovgS", { Gv
, Ev
}, 0 },
2754 { MOD_TABLE (MOD_0F51
) },
2755 { PREFIX_TABLE (PREFIX_0F51
) },
2756 { PREFIX_TABLE (PREFIX_0F52
) },
2757 { PREFIX_TABLE (PREFIX_0F53
) },
2758 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2759 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2760 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2761 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2763 { PREFIX_TABLE (PREFIX_0F58
) },
2764 { PREFIX_TABLE (PREFIX_0F59
) },
2765 { PREFIX_TABLE (PREFIX_0F5A
) },
2766 { PREFIX_TABLE (PREFIX_0F5B
) },
2767 { PREFIX_TABLE (PREFIX_0F5C
) },
2768 { PREFIX_TABLE (PREFIX_0F5D
) },
2769 { PREFIX_TABLE (PREFIX_0F5E
) },
2770 { PREFIX_TABLE (PREFIX_0F5F
) },
2772 { PREFIX_TABLE (PREFIX_0F60
) },
2773 { PREFIX_TABLE (PREFIX_0F61
) },
2774 { PREFIX_TABLE (PREFIX_0F62
) },
2775 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2777 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2778 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2779 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2781 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2782 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2783 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2784 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2785 { PREFIX_TABLE (PREFIX_0F6C
) },
2786 { PREFIX_TABLE (PREFIX_0F6D
) },
2787 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2788 { PREFIX_TABLE (PREFIX_0F6F
) },
2790 { PREFIX_TABLE (PREFIX_0F70
) },
2791 { REG_TABLE (REG_0F71
) },
2792 { REG_TABLE (REG_0F72
) },
2793 { REG_TABLE (REG_0F73
) },
2794 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2795 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2796 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2797 { "emms", { XX
}, PREFIX_OPCODE
},
2799 { PREFIX_TABLE (PREFIX_0F78
) },
2800 { PREFIX_TABLE (PREFIX_0F79
) },
2803 { PREFIX_TABLE (PREFIX_0F7C
) },
2804 { PREFIX_TABLE (PREFIX_0F7D
) },
2805 { PREFIX_TABLE (PREFIX_0F7E
) },
2806 { PREFIX_TABLE (PREFIX_0F7F
) },
2808 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2817 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2819 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2820 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2821 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2822 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2823 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2824 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2826 { "seto", { Eb
}, 0 },
2827 { "setno", { Eb
}, 0 },
2828 { "setb", { Eb
}, 0 },
2829 { "setae", { Eb
}, 0 },
2830 { "sete", { Eb
}, 0 },
2831 { "setne", { Eb
}, 0 },
2832 { "setbe", { Eb
}, 0 },
2833 { "seta", { Eb
}, 0 },
2835 { "sets", { Eb
}, 0 },
2836 { "setns", { Eb
}, 0 },
2837 { "setp", { Eb
}, 0 },
2838 { "setnp", { Eb
}, 0 },
2839 { "setl", { Eb
}, 0 },
2840 { "setge", { Eb
}, 0 },
2841 { "setle", { Eb
}, 0 },
2842 { "setg", { Eb
}, 0 },
2844 { "pushT", { fs
}, 0 },
2845 { "popT", { fs
}, 0 },
2846 { "cpuid", { XX
}, 0 },
2847 { "btS", { Ev
, Gv
}, 0 },
2848 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2849 { "shldS", { Ev
, Gv
, CL
}, 0 },
2850 { REG_TABLE (REG_0FA6
) },
2851 { REG_TABLE (REG_0FA7
) },
2853 { "pushT", { gs
}, 0 },
2854 { "popT", { gs
}, 0 },
2855 { "rsm", { XX
}, 0 },
2856 { "btsS", { Evh1
, Gv
}, 0 },
2857 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2858 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2859 { REG_TABLE (REG_0FAE
) },
2860 { "imulS", { Gv
, Ev
}, 0 },
2862 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2863 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2864 { MOD_TABLE (MOD_0FB2
) },
2865 { "btrS", { Evh1
, Gv
}, 0 },
2866 { MOD_TABLE (MOD_0FB4
) },
2867 { MOD_TABLE (MOD_0FB5
) },
2868 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2869 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2871 { PREFIX_TABLE (PREFIX_0FB8
) },
2872 { "ud1S", { Gv
, Ev
}, 0 },
2873 { REG_TABLE (REG_0FBA
) },
2874 { "btcS", { Evh1
, Gv
}, 0 },
2875 { PREFIX_TABLE (PREFIX_0FBC
) },
2876 { PREFIX_TABLE (PREFIX_0FBD
) },
2877 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2878 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2880 { "xaddB", { Ebh1
, Gb
}, 0 },
2881 { "xaddS", { Evh1
, Gv
}, 0 },
2882 { PREFIX_TABLE (PREFIX_0FC2
) },
2883 { MOD_TABLE (MOD_0FC3
) },
2884 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2885 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2886 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2887 { REG_TABLE (REG_0FC7
) },
2889 { "bswap", { RMeAX
}, 0 },
2890 { "bswap", { RMeCX
}, 0 },
2891 { "bswap", { RMeDX
}, 0 },
2892 { "bswap", { RMeBX
}, 0 },
2893 { "bswap", { RMeSP
}, 0 },
2894 { "bswap", { RMeBP
}, 0 },
2895 { "bswap", { RMeSI
}, 0 },
2896 { "bswap", { RMeDI
}, 0 },
2898 { PREFIX_TABLE (PREFIX_0FD0
) },
2899 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2904 { PREFIX_TABLE (PREFIX_0FD6
) },
2905 { MOD_TABLE (MOD_0FD7
) },
2907 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2914 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2916 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2917 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2922 { PREFIX_TABLE (PREFIX_0FE6
) },
2923 { PREFIX_TABLE (PREFIX_0FE7
) },
2925 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2926 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2927 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2934 { PREFIX_TABLE (PREFIX_0FF0
) },
2935 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { PREFIX_TABLE (PREFIX_0FF7
) },
2943 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2944 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2945 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2946 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2947 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2948 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2949 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2950 { "ud0S", { Gv
, Ev
}, 0 },
2953 static const unsigned char onebyte_has_modrm
[256] = {
2954 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2955 /* ------------------------------- */
2956 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2957 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2958 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2959 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2960 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2961 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2962 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2963 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2964 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2965 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2966 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2967 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2968 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2969 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2970 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2971 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2972 /* ------------------------------- */
2973 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2976 static const unsigned char twobyte_has_modrm
[256] = {
2977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2978 /* ------------------------------- */
2979 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2980 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2981 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2982 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2983 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2984 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2985 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2986 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2987 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2988 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2989 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2990 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2991 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2992 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2993 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2994 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2995 /* ------------------------------- */
2996 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2999 static char obuf
[100];
3001 static char *mnemonicendp
;
3002 static char scratchbuf
[100];
3003 static unsigned char *start_codep
;
3004 static unsigned char *insn_codep
;
3005 static unsigned char *codep
;
3006 static unsigned char *end_codep
;
3007 static int last_lock_prefix
;
3008 static int last_repz_prefix
;
3009 static int last_repnz_prefix
;
3010 static int last_data_prefix
;
3011 static int last_addr_prefix
;
3012 static int last_rex_prefix
;
3013 static int last_seg_prefix
;
3014 static int fwait_prefix
;
3015 /* The active segment register prefix. */
3016 static int active_seg_prefix
;
3017 #define MAX_CODE_LENGTH 15
3018 /* We can up to 14 prefixes since the maximum instruction length is
3020 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3021 static disassemble_info
*the_info
;
3029 static unsigned char need_modrm
;
3039 int register_specifier
;
3046 int mask_register_specifier
;
3052 static unsigned char need_vex
;
3053 static unsigned char need_vex_reg
;
3054 static unsigned char vex_w_done
;
3062 /* If we are accessing mod/rm/reg without need_modrm set, then the
3063 values are stale. Hitting this abort likely indicates that you
3064 need to update onebyte_has_modrm or twobyte_has_modrm. */
3065 #define MODRM_CHECK if (!need_modrm) abort ()
3067 static const char **names64
;
3068 static const char **names32
;
3069 static const char **names16
;
3070 static const char **names8
;
3071 static const char **names8rex
;
3072 static const char **names_seg
;
3073 static const char *index64
;
3074 static const char *index32
;
3075 static const char **index16
;
3076 static const char **names_bnd
;
3078 static const char *intel_names64
[] = {
3079 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3080 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3082 static const char *intel_names32
[] = {
3083 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3084 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3086 static const char *intel_names16
[] = {
3087 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3088 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3090 static const char *intel_names8
[] = {
3091 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3093 static const char *intel_names8rex
[] = {
3094 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3095 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3097 static const char *intel_names_seg
[] = {
3098 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3100 static const char *intel_index64
= "riz";
3101 static const char *intel_index32
= "eiz";
3102 static const char *intel_index16
[] = {
3103 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3106 static const char *att_names64
[] = {
3107 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3108 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3110 static const char *att_names32
[] = {
3111 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3112 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3114 static const char *att_names16
[] = {
3115 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3116 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3118 static const char *att_names8
[] = {
3119 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3121 static const char *att_names8rex
[] = {
3122 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3123 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3125 static const char *att_names_seg
[] = {
3126 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3128 static const char *att_index64
= "%riz";
3129 static const char *att_index32
= "%eiz";
3130 static const char *att_index16
[] = {
3131 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3134 static const char **names_mm
;
3135 static const char *intel_names_mm
[] = {
3136 "mm0", "mm1", "mm2", "mm3",
3137 "mm4", "mm5", "mm6", "mm7"
3139 static const char *att_names_mm
[] = {
3140 "%mm0", "%mm1", "%mm2", "%mm3",
3141 "%mm4", "%mm5", "%mm6", "%mm7"
3144 static const char *intel_names_bnd
[] = {
3145 "bnd0", "bnd1", "bnd2", "bnd3"
3148 static const char *att_names_bnd
[] = {
3149 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3152 static const char **names_xmm
;
3153 static const char *intel_names_xmm
[] = {
3154 "xmm0", "xmm1", "xmm2", "xmm3",
3155 "xmm4", "xmm5", "xmm6", "xmm7",
3156 "xmm8", "xmm9", "xmm10", "xmm11",
3157 "xmm12", "xmm13", "xmm14", "xmm15",
3158 "xmm16", "xmm17", "xmm18", "xmm19",
3159 "xmm20", "xmm21", "xmm22", "xmm23",
3160 "xmm24", "xmm25", "xmm26", "xmm27",
3161 "xmm28", "xmm29", "xmm30", "xmm31"
3163 static const char *att_names_xmm
[] = {
3164 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3165 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3166 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3167 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3168 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3169 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3170 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3171 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3174 static const char **names_ymm
;
3175 static const char *intel_names_ymm
[] = {
3176 "ymm0", "ymm1", "ymm2", "ymm3",
3177 "ymm4", "ymm5", "ymm6", "ymm7",
3178 "ymm8", "ymm9", "ymm10", "ymm11",
3179 "ymm12", "ymm13", "ymm14", "ymm15",
3180 "ymm16", "ymm17", "ymm18", "ymm19",
3181 "ymm20", "ymm21", "ymm22", "ymm23",
3182 "ymm24", "ymm25", "ymm26", "ymm27",
3183 "ymm28", "ymm29", "ymm30", "ymm31"
3185 static const char *att_names_ymm
[] = {
3186 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3187 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3188 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3189 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3190 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3191 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3192 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3193 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3196 static const char **names_zmm
;
3197 static const char *intel_names_zmm
[] = {
3198 "zmm0", "zmm1", "zmm2", "zmm3",
3199 "zmm4", "zmm5", "zmm6", "zmm7",
3200 "zmm8", "zmm9", "zmm10", "zmm11",
3201 "zmm12", "zmm13", "zmm14", "zmm15",
3202 "zmm16", "zmm17", "zmm18", "zmm19",
3203 "zmm20", "zmm21", "zmm22", "zmm23",
3204 "zmm24", "zmm25", "zmm26", "zmm27",
3205 "zmm28", "zmm29", "zmm30", "zmm31"
3207 static const char *att_names_zmm
[] = {
3208 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3209 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3210 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3211 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3212 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3213 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3214 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3215 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3218 static const char **names_mask
;
3219 static const char *intel_names_mask
[] = {
3220 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3222 static const char *att_names_mask
[] = {
3223 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3226 static const char *names_rounding
[] =
3234 static const struct dis386 reg_table
[][8] = {
3237 { "addA", { Ebh1
, Ib
}, 0 },
3238 { "orA", { Ebh1
, Ib
}, 0 },
3239 { "adcA", { Ebh1
, Ib
}, 0 },
3240 { "sbbA", { Ebh1
, Ib
}, 0 },
3241 { "andA", { Ebh1
, Ib
}, 0 },
3242 { "subA", { Ebh1
, Ib
}, 0 },
3243 { "xorA", { Ebh1
, Ib
}, 0 },
3244 { "cmpA", { Eb
, Ib
}, 0 },
3248 { "addQ", { Evh1
, Iv
}, 0 },
3249 { "orQ", { Evh1
, Iv
}, 0 },
3250 { "adcQ", { Evh1
, Iv
}, 0 },
3251 { "sbbQ", { Evh1
, Iv
}, 0 },
3252 { "andQ", { Evh1
, Iv
}, 0 },
3253 { "subQ", { Evh1
, Iv
}, 0 },
3254 { "xorQ", { Evh1
, Iv
}, 0 },
3255 { "cmpQ", { Ev
, Iv
}, 0 },
3259 { "addQ", { Evh1
, sIb
}, 0 },
3260 { "orQ", { Evh1
, sIb
}, 0 },
3261 { "adcQ", { Evh1
, sIb
}, 0 },
3262 { "sbbQ", { Evh1
, sIb
}, 0 },
3263 { "andQ", { Evh1
, sIb
}, 0 },
3264 { "subQ", { Evh1
, sIb
}, 0 },
3265 { "xorQ", { Evh1
, sIb
}, 0 },
3266 { "cmpQ", { Ev
, sIb
}, 0 },
3270 { "popU", { stackEv
}, 0 },
3271 { XOP_8F_TABLE (XOP_09
) },
3275 { XOP_8F_TABLE (XOP_09
) },
3279 { "rolA", { Eb
, Ib
}, 0 },
3280 { "rorA", { Eb
, Ib
}, 0 },
3281 { "rclA", { Eb
, Ib
}, 0 },
3282 { "rcrA", { Eb
, Ib
}, 0 },
3283 { "shlA", { Eb
, Ib
}, 0 },
3284 { "shrA", { Eb
, Ib
}, 0 },
3285 { "shlA", { Eb
, Ib
}, 0 },
3286 { "sarA", { Eb
, Ib
}, 0 },
3290 { "rolQ", { Ev
, Ib
}, 0 },
3291 { "rorQ", { Ev
, Ib
}, 0 },
3292 { "rclQ", { Ev
, Ib
}, 0 },
3293 { "rcrQ", { Ev
, Ib
}, 0 },
3294 { "shlQ", { Ev
, Ib
}, 0 },
3295 { "shrQ", { Ev
, Ib
}, 0 },
3296 { "shlQ", { Ev
, Ib
}, 0 },
3297 { "sarQ", { Ev
, Ib
}, 0 },
3301 { "movA", { Ebh3
, Ib
}, 0 },
3308 { MOD_TABLE (MOD_C6_REG_7
) },
3312 { "movQ", { Evh3
, Iv
}, 0 },
3319 { MOD_TABLE (MOD_C7_REG_7
) },
3323 { "rolA", { Eb
, I1
}, 0 },
3324 { "rorA", { Eb
, I1
}, 0 },
3325 { "rclA", { Eb
, I1
}, 0 },
3326 { "rcrA", { Eb
, I1
}, 0 },
3327 { "shlA", { Eb
, I1
}, 0 },
3328 { "shrA", { Eb
, I1
}, 0 },
3329 { "shlA", { Eb
, I1
}, 0 },
3330 { "sarA", { Eb
, I1
}, 0 },
3334 { "rolQ", { Ev
, I1
}, 0 },
3335 { "rorQ", { Ev
, I1
}, 0 },
3336 { "rclQ", { Ev
, I1
}, 0 },
3337 { "rcrQ", { Ev
, I1
}, 0 },
3338 { "shlQ", { Ev
, I1
}, 0 },
3339 { "shrQ", { Ev
, I1
}, 0 },
3340 { "shlQ", { Ev
, I1
}, 0 },
3341 { "sarQ", { Ev
, I1
}, 0 },
3345 { "rolA", { Eb
, CL
}, 0 },
3346 { "rorA", { Eb
, CL
}, 0 },
3347 { "rclA", { Eb
, CL
}, 0 },
3348 { "rcrA", { Eb
, CL
}, 0 },
3349 { "shlA", { Eb
, CL
}, 0 },
3350 { "shrA", { Eb
, CL
}, 0 },
3351 { "shlA", { Eb
, CL
}, 0 },
3352 { "sarA", { Eb
, CL
}, 0 },
3356 { "rolQ", { Ev
, CL
}, 0 },
3357 { "rorQ", { Ev
, CL
}, 0 },
3358 { "rclQ", { Ev
, CL
}, 0 },
3359 { "rcrQ", { Ev
, CL
}, 0 },
3360 { "shlQ", { Ev
, CL
}, 0 },
3361 { "shrQ", { Ev
, CL
}, 0 },
3362 { "shlQ", { Ev
, CL
}, 0 },
3363 { "sarQ", { Ev
, CL
}, 0 },
3367 { "testA", { Eb
, Ib
}, 0 },
3368 { "testA", { Eb
, Ib
}, 0 },
3369 { "notA", { Ebh1
}, 0 },
3370 { "negA", { Ebh1
}, 0 },
3371 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3372 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3373 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3374 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3378 { "testQ", { Ev
, Iv
}, 0 },
3379 { "testQ", { Ev
, Iv
}, 0 },
3380 { "notQ", { Evh1
}, 0 },
3381 { "negQ", { Evh1
}, 0 },
3382 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3383 { "imulQ", { Ev
}, 0 },
3384 { "divQ", { Ev
}, 0 },
3385 { "idivQ", { Ev
}, 0 },
3389 { "incA", { Ebh1
}, 0 },
3390 { "decA", { Ebh1
}, 0 },
3394 { "incQ", { Evh1
}, 0 },
3395 { "decQ", { Evh1
}, 0 },
3396 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3397 { MOD_TABLE (MOD_FF_REG_3
) },
3398 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3399 { MOD_TABLE (MOD_FF_REG_5
) },
3400 { "pushU", { stackEv
}, 0 },
3405 { "sldtD", { Sv
}, 0 },
3406 { "strD", { Sv
}, 0 },
3407 { "lldt", { Ew
}, 0 },
3408 { "ltr", { Ew
}, 0 },
3409 { "verr", { Ew
}, 0 },
3410 { "verw", { Ew
}, 0 },
3416 { MOD_TABLE (MOD_0F01_REG_0
) },
3417 { MOD_TABLE (MOD_0F01_REG_1
) },
3418 { MOD_TABLE (MOD_0F01_REG_2
) },
3419 { MOD_TABLE (MOD_0F01_REG_3
) },
3420 { "smswD", { Sv
}, 0 },
3421 { MOD_TABLE (MOD_0F01_REG_5
) },
3422 { "lmsw", { Ew
}, 0 },
3423 { MOD_TABLE (MOD_0F01_REG_7
) },
3427 { "prefetch", { Mb
}, 0 },
3428 { "prefetchw", { Mb
}, 0 },
3429 { "prefetchwt1", { Mb
}, 0 },
3430 { "prefetch", { Mb
}, 0 },
3431 { "prefetch", { Mb
}, 0 },
3432 { "prefetch", { Mb
}, 0 },
3433 { "prefetch", { Mb
}, 0 },
3434 { "prefetch", { Mb
}, 0 },
3438 { MOD_TABLE (MOD_0F18_REG_0
) },
3439 { MOD_TABLE (MOD_0F18_REG_1
) },
3440 { MOD_TABLE (MOD_0F18_REG_2
) },
3441 { MOD_TABLE (MOD_0F18_REG_3
) },
3442 { MOD_TABLE (MOD_0F18_REG_4
) },
3443 { MOD_TABLE (MOD_0F18_REG_5
) },
3444 { MOD_TABLE (MOD_0F18_REG_6
) },
3445 { MOD_TABLE (MOD_0F18_REG_7
) },
3447 /* REG_0F1C_MOD_0 */
3449 { "cldemote", { Mb
}, 0 },
3450 { "nopQ", { Ev
}, 0 },
3451 { "nopQ", { Ev
}, 0 },
3452 { "nopQ", { Ev
}, 0 },
3453 { "nopQ", { Ev
}, 0 },
3454 { "nopQ", { Ev
}, 0 },
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3458 /* REG_0F1E_MOD_3 */
3460 { "nopQ", { Ev
}, 0 },
3461 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3462 { "nopQ", { Ev
}, 0 },
3463 { "nopQ", { Ev
}, 0 },
3464 { "nopQ", { Ev
}, 0 },
3465 { "nopQ", { Ev
}, 0 },
3466 { "nopQ", { Ev
}, 0 },
3467 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3473 { MOD_TABLE (MOD_0F71_REG_2
) },
3475 { MOD_TABLE (MOD_0F71_REG_4
) },
3477 { MOD_TABLE (MOD_0F71_REG_6
) },
3483 { MOD_TABLE (MOD_0F72_REG_2
) },
3485 { MOD_TABLE (MOD_0F72_REG_4
) },
3487 { MOD_TABLE (MOD_0F72_REG_6
) },
3493 { MOD_TABLE (MOD_0F73_REG_2
) },
3494 { MOD_TABLE (MOD_0F73_REG_3
) },
3497 { MOD_TABLE (MOD_0F73_REG_6
) },
3498 { MOD_TABLE (MOD_0F73_REG_7
) },
3502 { "montmul", { { OP_0f07
, 0 } }, 0 },
3503 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3504 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3508 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3509 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3510 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3511 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3512 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3513 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3517 { MOD_TABLE (MOD_0FAE_REG_0
) },
3518 { MOD_TABLE (MOD_0FAE_REG_1
) },
3519 { MOD_TABLE (MOD_0FAE_REG_2
) },
3520 { MOD_TABLE (MOD_0FAE_REG_3
) },
3521 { MOD_TABLE (MOD_0FAE_REG_4
) },
3522 { MOD_TABLE (MOD_0FAE_REG_5
) },
3523 { MOD_TABLE (MOD_0FAE_REG_6
) },
3524 { MOD_TABLE (MOD_0FAE_REG_7
) },
3532 { "btQ", { Ev
, Ib
}, 0 },
3533 { "btsQ", { Evh1
, Ib
}, 0 },
3534 { "btrQ", { Evh1
, Ib
}, 0 },
3535 { "btcQ", { Evh1
, Ib
}, 0 },
3540 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3542 { MOD_TABLE (MOD_0FC7_REG_3
) },
3543 { MOD_TABLE (MOD_0FC7_REG_4
) },
3544 { MOD_TABLE (MOD_0FC7_REG_5
) },
3545 { MOD_TABLE (MOD_0FC7_REG_6
) },
3546 { MOD_TABLE (MOD_0FC7_REG_7
) },
3552 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3554 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3556 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3562 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3564 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3566 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3572 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3573 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3576 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3577 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3583 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3584 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3586 /* REG_VEX_0F38F3 */
3589 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3590 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3591 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3595 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3596 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3600 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3601 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3603 /* REG_XOP_TBM_01 */
3606 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3607 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3608 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3609 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3610 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3611 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3612 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3614 /* REG_XOP_TBM_02 */
3617 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3622 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3625 #include "i386-dis-evex-reg.h"
3628 static const struct dis386 prefix_table
[][4] = {
3631 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3632 { "pause", { XX
}, 0 },
3633 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3634 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3637 /* PREFIX_MOD_0_0F01_REG_5 */
3640 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3643 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3646 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3649 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3652 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3657 { "wbinvd", { XX
}, 0 },
3658 { "wbnoinvd", { XX
}, 0 },
3663 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3664 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3665 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3666 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3671 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3672 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3673 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3674 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3679 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3680 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3681 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3682 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3687 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3688 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3689 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3694 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3695 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3696 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3697 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3702 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3703 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3704 { "bndmov", { EbndS
, Gbnd
}, 0 },
3705 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3710 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3711 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3712 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3713 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3718 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3719 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3720 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3721 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3726 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3727 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3728 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3729 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3734 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3735 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3742 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3743 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3744 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3745 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3750 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3751 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3752 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3753 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3758 { "ucomiss",{ XM
, EXd
}, 0 },
3760 { "ucomisd",{ XM
, EXq
}, 0 },
3765 { "comiss", { XM
, EXd
}, 0 },
3767 { "comisd", { XM
, EXq
}, 0 },
3772 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3773 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3774 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3775 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3780 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3781 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3786 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3787 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3792 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3793 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3794 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3795 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3800 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3801 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3802 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3803 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3808 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3809 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3810 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3811 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3816 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3817 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3818 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3823 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3824 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3825 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3826 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3831 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3832 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3833 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3834 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3839 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3840 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3841 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3842 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3847 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3848 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3849 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3855 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3857 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3862 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3864 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3869 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3871 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3878 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3885 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3890 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3891 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3892 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3897 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3898 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3899 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3900 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3903 /* PREFIX_0F73_REG_3 */
3907 { "psrldq", { XS
, Ib
}, 0 },
3910 /* PREFIX_0F73_REG_7 */
3914 { "pslldq", { XS
, Ib
}, 0 },
3919 {"vmread", { Em
, Gm
}, 0 },
3921 {"extrq", { XS
, Ib
, Ib
}, 0 },
3922 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3927 {"vmwrite", { Gm
, Em
}, 0 },
3929 {"extrq", { XM
, XS
}, 0 },
3930 {"insertq", { XM
, XS
}, 0 },
3937 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3938 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3945 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3946 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3951 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3952 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3953 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3958 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3959 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3960 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3963 /* PREFIX_0FAE_REG_0 */
3966 { "rdfsbase", { Ev
}, 0 },
3969 /* PREFIX_0FAE_REG_1 */
3972 { "rdgsbase", { Ev
}, 0 },
3975 /* PREFIX_0FAE_REG_2 */
3978 { "wrfsbase", { Ev
}, 0 },
3981 /* PREFIX_0FAE_REG_3 */
3984 { "wrgsbase", { Ev
}, 0 },
3987 /* PREFIX_MOD_0_0FAE_REG_4 */
3989 { "xsave", { FXSAVE
}, 0 },
3990 { "ptwrite%LQ", { Edq
}, 0 },
3993 /* PREFIX_MOD_3_0FAE_REG_4 */
3996 { "ptwrite%LQ", { Edq
}, 0 },
3999 /* PREFIX_MOD_0_0FAE_REG_5 */
4001 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4004 /* PREFIX_MOD_3_0FAE_REG_5 */
4006 { "lfence", { Skip_MODRM
}, 0 },
4007 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4010 /* PREFIX_MOD_0_0FAE_REG_6 */
4012 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4013 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4014 { "clwb", { Mb
}, PREFIX_OPCODE
},
4017 /* PREFIX_MOD_1_0FAE_REG_6 */
4019 { RM_TABLE (RM_0FAE_REG_6
) },
4020 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4021 { "tpause", { Edq
}, PREFIX_OPCODE
},
4022 { "umwait", { Edq
}, PREFIX_OPCODE
},
4025 /* PREFIX_0FAE_REG_7 */
4027 { "clflush", { Mb
}, 0 },
4029 { "clflushopt", { Mb
}, 0 },
4035 { "popcntS", { Gv
, Ev
}, 0 },
4040 { "bsfS", { Gv
, Ev
}, 0 },
4041 { "tzcntS", { Gv
, Ev
}, 0 },
4042 { "bsfS", { Gv
, Ev
}, 0 },
4047 { "bsrS", { Gv
, Ev
}, 0 },
4048 { "lzcntS", { Gv
, Ev
}, 0 },
4049 { "bsrS", { Gv
, Ev
}, 0 },
4054 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4055 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4056 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4057 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4060 /* PREFIX_MOD_0_0FC3 */
4062 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4065 /* PREFIX_MOD_0_0FC7_REG_6 */
4067 { "vmptrld",{ Mq
}, 0 },
4068 { "vmxon", { Mq
}, 0 },
4069 { "vmclear",{ Mq
}, 0 },
4072 /* PREFIX_MOD_3_0FC7_REG_6 */
4074 { "rdrand", { Ev
}, 0 },
4076 { "rdrand", { Ev
}, 0 }
4079 /* PREFIX_MOD_3_0FC7_REG_7 */
4081 { "rdseed", { Ev
}, 0 },
4082 { "rdpid", { Em
}, 0 },
4083 { "rdseed", { Ev
}, 0 },
4090 { "addsubpd", { XM
, EXx
}, 0 },
4091 { "addsubps", { XM
, EXx
}, 0 },
4097 { "movq2dq",{ XM
, MS
}, 0 },
4098 { "movq", { EXqS
, XM
}, 0 },
4099 { "movdq2q",{ MX
, XS
}, 0 },
4105 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4106 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4107 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4112 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4114 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4122 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4127 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4129 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4136 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4143 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4150 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4157 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4164 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4171 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4178 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4185 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4192 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4199 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4206 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4213 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4220 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4227 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4234 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4241 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4248 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4255 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4262 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4269 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4276 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4283 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4290 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4297 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4304 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4311 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4318 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4325 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4332 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4339 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4346 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4353 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4360 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4367 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4372 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4377 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4382 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4387 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4392 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4397 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4404 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4411 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4418 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4425 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4432 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4439 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4444 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4446 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4447 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4452 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4454 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4455 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4462 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4467 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4468 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4469 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4476 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4477 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4478 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4483 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4490 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4497 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4504 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4511 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4518 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4525 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4532 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4539 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4546 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4553 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4560 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4567 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4574 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4581 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4588 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4595 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4602 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4609 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4616 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4623 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4630 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4637 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4642 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4649 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4656 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4663 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4666 /* PREFIX_VEX_0F10 */
4668 { "vmovups", { XM
, EXx
}, 0 },
4669 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4670 { "vmovupd", { XM
, EXx
}, 0 },
4671 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4674 /* PREFIX_VEX_0F11 */
4676 { "vmovups", { EXxS
, XM
}, 0 },
4677 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4678 { "vmovupd", { EXxS
, XM
}, 0 },
4679 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4682 /* PREFIX_VEX_0F12 */
4684 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4685 { "vmovsldup", { XM
, EXx
}, 0 },
4686 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4687 { "vmovddup", { XM
, EXymmq
}, 0 },
4690 /* PREFIX_VEX_0F16 */
4692 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4693 { "vmovshdup", { XM
, EXx
}, 0 },
4694 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4697 /* PREFIX_VEX_0F2A */
4700 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4702 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4705 /* PREFIX_VEX_0F2C */
4708 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4710 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4713 /* PREFIX_VEX_0F2D */
4716 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4718 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4721 /* PREFIX_VEX_0F2E */
4723 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4725 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4728 /* PREFIX_VEX_0F2F */
4730 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4732 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4735 /* PREFIX_VEX_0F41 */
4737 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4742 /* PREFIX_VEX_0F42 */
4744 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4746 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4749 /* PREFIX_VEX_0F44 */
4751 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4753 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4756 /* PREFIX_VEX_0F45 */
4758 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4760 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4763 /* PREFIX_VEX_0F46 */
4765 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4767 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4770 /* PREFIX_VEX_0F47 */
4772 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4774 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4777 /* PREFIX_VEX_0F4A */
4779 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4781 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4784 /* PREFIX_VEX_0F4B */
4786 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4788 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4791 /* PREFIX_VEX_0F51 */
4793 { "vsqrtps", { XM
, EXx
}, 0 },
4794 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4795 { "vsqrtpd", { XM
, EXx
}, 0 },
4796 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4799 /* PREFIX_VEX_0F52 */
4801 { "vrsqrtps", { XM
, EXx
}, 0 },
4802 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4805 /* PREFIX_VEX_0F53 */
4807 { "vrcpps", { XM
, EXx
}, 0 },
4808 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4811 /* PREFIX_VEX_0F58 */
4813 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4814 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4815 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4816 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4819 /* PREFIX_VEX_0F59 */
4821 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4822 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4823 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4824 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4827 /* PREFIX_VEX_0F5A */
4829 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4830 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4831 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4832 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4835 /* PREFIX_VEX_0F5B */
4837 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4838 { "vcvttps2dq", { XM
, EXx
}, 0 },
4839 { "vcvtps2dq", { XM
, EXx
}, 0 },
4842 /* PREFIX_VEX_0F5C */
4844 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4845 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4846 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4847 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4850 /* PREFIX_VEX_0F5D */
4852 { "vminps", { XM
, Vex
, EXx
}, 0 },
4853 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4854 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4855 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4858 /* PREFIX_VEX_0F5E */
4860 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4861 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4862 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4863 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4866 /* PREFIX_VEX_0F5F */
4868 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4869 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4870 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4871 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4874 /* PREFIX_VEX_0F60 */
4878 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4881 /* PREFIX_VEX_0F61 */
4885 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4888 /* PREFIX_VEX_0F62 */
4892 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4895 /* PREFIX_VEX_0F63 */
4899 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4902 /* PREFIX_VEX_0F64 */
4906 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4909 /* PREFIX_VEX_0F65 */
4913 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4916 /* PREFIX_VEX_0F66 */
4920 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4923 /* PREFIX_VEX_0F67 */
4927 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4930 /* PREFIX_VEX_0F68 */
4934 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4937 /* PREFIX_VEX_0F69 */
4941 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4944 /* PREFIX_VEX_0F6A */
4948 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4951 /* PREFIX_VEX_0F6B */
4955 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4958 /* PREFIX_VEX_0F6C */
4962 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4965 /* PREFIX_VEX_0F6D */
4969 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4972 /* PREFIX_VEX_0F6E */
4976 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4979 /* PREFIX_VEX_0F6F */
4982 { "vmovdqu", { XM
, EXx
}, 0 },
4983 { "vmovdqa", { XM
, EXx
}, 0 },
4986 /* PREFIX_VEX_0F70 */
4989 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4990 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4991 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4994 /* PREFIX_VEX_0F71_REG_2 */
4998 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5001 /* PREFIX_VEX_0F71_REG_4 */
5005 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5008 /* PREFIX_VEX_0F71_REG_6 */
5012 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5015 /* PREFIX_VEX_0F72_REG_2 */
5019 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5022 /* PREFIX_VEX_0F72_REG_4 */
5026 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5029 /* PREFIX_VEX_0F72_REG_6 */
5033 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5036 /* PREFIX_VEX_0F73_REG_2 */
5040 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5043 /* PREFIX_VEX_0F73_REG_3 */
5047 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5050 /* PREFIX_VEX_0F73_REG_6 */
5054 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5057 /* PREFIX_VEX_0F73_REG_7 */
5061 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5064 /* PREFIX_VEX_0F74 */
5068 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5071 /* PREFIX_VEX_0F75 */
5075 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5078 /* PREFIX_VEX_0F76 */
5082 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5085 /* PREFIX_VEX_0F77 */
5087 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5090 /* PREFIX_VEX_0F7C */
5094 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5095 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5098 /* PREFIX_VEX_0F7D */
5102 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5103 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5106 /* PREFIX_VEX_0F7E */
5109 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5110 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5113 /* PREFIX_VEX_0F7F */
5116 { "vmovdqu", { EXxS
, XM
}, 0 },
5117 { "vmovdqa", { EXxS
, XM
}, 0 },
5120 /* PREFIX_VEX_0F90 */
5122 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5124 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5127 /* PREFIX_VEX_0F91 */
5129 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5131 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5134 /* PREFIX_VEX_0F92 */
5136 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5138 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5139 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5142 /* PREFIX_VEX_0F93 */
5144 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5146 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5147 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5150 /* PREFIX_VEX_0F98 */
5152 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5154 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5157 /* PREFIX_VEX_0F99 */
5159 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5161 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5164 /* PREFIX_VEX_0FC2 */
5166 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5167 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5168 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5169 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5172 /* PREFIX_VEX_0FC4 */
5176 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5179 /* PREFIX_VEX_0FC5 */
5183 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5186 /* PREFIX_VEX_0FD0 */
5190 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5191 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5194 /* PREFIX_VEX_0FD1 */
5198 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5201 /* PREFIX_VEX_0FD2 */
5205 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5208 /* PREFIX_VEX_0FD3 */
5212 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5215 /* PREFIX_VEX_0FD4 */
5219 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5222 /* PREFIX_VEX_0FD5 */
5226 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5229 /* PREFIX_VEX_0FD6 */
5233 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5236 /* PREFIX_VEX_0FD7 */
5240 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5243 /* PREFIX_VEX_0FD8 */
5247 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5250 /* PREFIX_VEX_0FD9 */
5254 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5257 /* PREFIX_VEX_0FDA */
5261 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5264 /* PREFIX_VEX_0FDB */
5268 { "vpand", { XM
, Vex
, EXx
}, 0 },
5271 /* PREFIX_VEX_0FDC */
5275 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5278 /* PREFIX_VEX_0FDD */
5282 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5285 /* PREFIX_VEX_0FDE */
5289 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5292 /* PREFIX_VEX_0FDF */
5296 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5299 /* PREFIX_VEX_0FE0 */
5303 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5306 /* PREFIX_VEX_0FE1 */
5310 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5313 /* PREFIX_VEX_0FE2 */
5317 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5320 /* PREFIX_VEX_0FE3 */
5324 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5327 /* PREFIX_VEX_0FE4 */
5331 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5334 /* PREFIX_VEX_0FE5 */
5338 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5341 /* PREFIX_VEX_0FE6 */
5344 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5345 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5346 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5349 /* PREFIX_VEX_0FE7 */
5353 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5356 /* PREFIX_VEX_0FE8 */
5360 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5363 /* PREFIX_VEX_0FE9 */
5367 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5370 /* PREFIX_VEX_0FEA */
5374 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5377 /* PREFIX_VEX_0FEB */
5381 { "vpor", { XM
, Vex
, EXx
}, 0 },
5384 /* PREFIX_VEX_0FEC */
5388 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5391 /* PREFIX_VEX_0FED */
5395 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5398 /* PREFIX_VEX_0FEE */
5402 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5405 /* PREFIX_VEX_0FEF */
5409 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5412 /* PREFIX_VEX_0FF0 */
5417 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5420 /* PREFIX_VEX_0FF1 */
5424 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5427 /* PREFIX_VEX_0FF2 */
5431 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5434 /* PREFIX_VEX_0FF3 */
5438 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5441 /* PREFIX_VEX_0FF4 */
5445 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5448 /* PREFIX_VEX_0FF5 */
5452 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5455 /* PREFIX_VEX_0FF6 */
5459 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5462 /* PREFIX_VEX_0FF7 */
5466 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5469 /* PREFIX_VEX_0FF8 */
5473 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5476 /* PREFIX_VEX_0FF9 */
5480 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5483 /* PREFIX_VEX_0FFA */
5487 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5490 /* PREFIX_VEX_0FFB */
5494 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5497 /* PREFIX_VEX_0FFC */
5501 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5504 /* PREFIX_VEX_0FFD */
5508 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5511 /* PREFIX_VEX_0FFE */
5515 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5518 /* PREFIX_VEX_0F3800 */
5522 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5525 /* PREFIX_VEX_0F3801 */
5529 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5532 /* PREFIX_VEX_0F3802 */
5536 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5539 /* PREFIX_VEX_0F3803 */
5543 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5546 /* PREFIX_VEX_0F3804 */
5550 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5553 /* PREFIX_VEX_0F3805 */
5557 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5560 /* PREFIX_VEX_0F3806 */
5564 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5567 /* PREFIX_VEX_0F3807 */
5571 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5574 /* PREFIX_VEX_0F3808 */
5578 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5581 /* PREFIX_VEX_0F3809 */
5585 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5588 /* PREFIX_VEX_0F380A */
5592 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5595 /* PREFIX_VEX_0F380B */
5599 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5602 /* PREFIX_VEX_0F380C */
5606 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5609 /* PREFIX_VEX_0F380D */
5613 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5616 /* PREFIX_VEX_0F380E */
5620 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5623 /* PREFIX_VEX_0F380F */
5627 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5630 /* PREFIX_VEX_0F3813 */
5634 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5637 /* PREFIX_VEX_0F3816 */
5641 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5644 /* PREFIX_VEX_0F3817 */
5648 { "vptest", { XM
, EXx
}, 0 },
5651 /* PREFIX_VEX_0F3818 */
5655 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5658 /* PREFIX_VEX_0F3819 */
5662 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5665 /* PREFIX_VEX_0F381A */
5669 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5672 /* PREFIX_VEX_0F381C */
5676 { "vpabsb", { XM
, EXx
}, 0 },
5679 /* PREFIX_VEX_0F381D */
5683 { "vpabsw", { XM
, EXx
}, 0 },
5686 /* PREFIX_VEX_0F381E */
5690 { "vpabsd", { XM
, EXx
}, 0 },
5693 /* PREFIX_VEX_0F3820 */
5697 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5700 /* PREFIX_VEX_0F3821 */
5704 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5707 /* PREFIX_VEX_0F3822 */
5711 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5714 /* PREFIX_VEX_0F3823 */
5718 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5721 /* PREFIX_VEX_0F3824 */
5725 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5728 /* PREFIX_VEX_0F3825 */
5732 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5735 /* PREFIX_VEX_0F3828 */
5739 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5742 /* PREFIX_VEX_0F3829 */
5746 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5749 /* PREFIX_VEX_0F382A */
5753 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5756 /* PREFIX_VEX_0F382B */
5760 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5763 /* PREFIX_VEX_0F382C */
5767 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5770 /* PREFIX_VEX_0F382D */
5774 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5777 /* PREFIX_VEX_0F382E */
5781 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5784 /* PREFIX_VEX_0F382F */
5788 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5791 /* PREFIX_VEX_0F3830 */
5795 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5798 /* PREFIX_VEX_0F3831 */
5802 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5805 /* PREFIX_VEX_0F3832 */
5809 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5812 /* PREFIX_VEX_0F3833 */
5816 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5819 /* PREFIX_VEX_0F3834 */
5823 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5826 /* PREFIX_VEX_0F3835 */
5830 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5833 /* PREFIX_VEX_0F3836 */
5837 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5840 /* PREFIX_VEX_0F3837 */
5844 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5847 /* PREFIX_VEX_0F3838 */
5851 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5854 /* PREFIX_VEX_0F3839 */
5858 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5861 /* PREFIX_VEX_0F383A */
5865 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5868 /* PREFIX_VEX_0F383B */
5872 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5875 /* PREFIX_VEX_0F383C */
5879 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5882 /* PREFIX_VEX_0F383D */
5886 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5889 /* PREFIX_VEX_0F383E */
5893 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5896 /* PREFIX_VEX_0F383F */
5900 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5903 /* PREFIX_VEX_0F3840 */
5907 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5910 /* PREFIX_VEX_0F3841 */
5914 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5917 /* PREFIX_VEX_0F3845 */
5921 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5924 /* PREFIX_VEX_0F3846 */
5928 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5931 /* PREFIX_VEX_0F3847 */
5935 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5938 /* PREFIX_VEX_0F3858 */
5942 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5945 /* PREFIX_VEX_0F3859 */
5949 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5952 /* PREFIX_VEX_0F385A */
5956 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5959 /* PREFIX_VEX_0F3878 */
5963 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5966 /* PREFIX_VEX_0F3879 */
5970 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5973 /* PREFIX_VEX_0F388C */
5977 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5980 /* PREFIX_VEX_0F388E */
5984 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5987 /* PREFIX_VEX_0F3890 */
5991 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5994 /* PREFIX_VEX_0F3891 */
5998 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6001 /* PREFIX_VEX_0F3892 */
6005 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6008 /* PREFIX_VEX_0F3893 */
6012 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6015 /* PREFIX_VEX_0F3896 */
6019 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6022 /* PREFIX_VEX_0F3897 */
6026 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6029 /* PREFIX_VEX_0F3898 */
6033 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6036 /* PREFIX_VEX_0F3899 */
6040 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6043 /* PREFIX_VEX_0F389A */
6047 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6050 /* PREFIX_VEX_0F389B */
6054 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6057 /* PREFIX_VEX_0F389C */
6061 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6064 /* PREFIX_VEX_0F389D */
6068 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6071 /* PREFIX_VEX_0F389E */
6075 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6078 /* PREFIX_VEX_0F389F */
6082 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6085 /* PREFIX_VEX_0F38A6 */
6089 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6093 /* PREFIX_VEX_0F38A7 */
6097 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6100 /* PREFIX_VEX_0F38A8 */
6104 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6107 /* PREFIX_VEX_0F38A9 */
6111 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6114 /* PREFIX_VEX_0F38AA */
6118 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6121 /* PREFIX_VEX_0F38AB */
6125 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6128 /* PREFIX_VEX_0F38AC */
6132 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6135 /* PREFIX_VEX_0F38AD */
6139 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6142 /* PREFIX_VEX_0F38AE */
6146 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6149 /* PREFIX_VEX_0F38AF */
6153 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6156 /* PREFIX_VEX_0F38B6 */
6160 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6163 /* PREFIX_VEX_0F38B7 */
6167 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6170 /* PREFIX_VEX_0F38B8 */
6174 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6177 /* PREFIX_VEX_0F38B9 */
6181 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6184 /* PREFIX_VEX_0F38BA */
6188 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6191 /* PREFIX_VEX_0F38BB */
6195 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6198 /* PREFIX_VEX_0F38BC */
6202 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6205 /* PREFIX_VEX_0F38BD */
6209 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6212 /* PREFIX_VEX_0F38BE */
6216 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6219 /* PREFIX_VEX_0F38BF */
6223 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6226 /* PREFIX_VEX_0F38CF */
6230 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6233 /* PREFIX_VEX_0F38DB */
6237 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6240 /* PREFIX_VEX_0F38DC */
6244 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6247 /* PREFIX_VEX_0F38DD */
6251 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6254 /* PREFIX_VEX_0F38DE */
6258 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6261 /* PREFIX_VEX_0F38DF */
6265 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6268 /* PREFIX_VEX_0F38F2 */
6270 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6273 /* PREFIX_VEX_0F38F3_REG_1 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6278 /* PREFIX_VEX_0F38F3_REG_2 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6283 /* PREFIX_VEX_0F38F3_REG_3 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6288 /* PREFIX_VEX_0F38F5 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6291 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6296 /* PREFIX_VEX_0F38F6 */
6301 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6304 /* PREFIX_VEX_0F38F7 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6307 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6312 /* PREFIX_VEX_0F3A00 */
6316 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6319 /* PREFIX_VEX_0F3A01 */
6323 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6326 /* PREFIX_VEX_0F3A02 */
6330 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6333 /* PREFIX_VEX_0F3A04 */
6337 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6340 /* PREFIX_VEX_0F3A05 */
6344 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6347 /* PREFIX_VEX_0F3A06 */
6351 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6354 /* PREFIX_VEX_0F3A08 */
6358 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6361 /* PREFIX_VEX_0F3A09 */
6365 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6368 /* PREFIX_VEX_0F3A0A */
6372 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6375 /* PREFIX_VEX_0F3A0B */
6379 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6382 /* PREFIX_VEX_0F3A0C */
6386 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6389 /* PREFIX_VEX_0F3A0D */
6393 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6396 /* PREFIX_VEX_0F3A0E */
6400 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6403 /* PREFIX_VEX_0F3A0F */
6407 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6410 /* PREFIX_VEX_0F3A14 */
6414 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6417 /* PREFIX_VEX_0F3A15 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6424 /* PREFIX_VEX_0F3A16 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6431 /* PREFIX_VEX_0F3A17 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6438 /* PREFIX_VEX_0F3A18 */
6442 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6445 /* PREFIX_VEX_0F3A19 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6452 /* PREFIX_VEX_0F3A1D */
6456 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6459 /* PREFIX_VEX_0F3A20 */
6463 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6466 /* PREFIX_VEX_0F3A21 */
6470 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6473 /* PREFIX_VEX_0F3A22 */
6477 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6480 /* PREFIX_VEX_0F3A30 */
6484 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6487 /* PREFIX_VEX_0F3A31 */
6491 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6494 /* PREFIX_VEX_0F3A32 */
6498 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6501 /* PREFIX_VEX_0F3A33 */
6505 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6508 /* PREFIX_VEX_0F3A38 */
6512 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6515 /* PREFIX_VEX_0F3A39 */
6519 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6522 /* PREFIX_VEX_0F3A40 */
6526 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6529 /* PREFIX_VEX_0F3A41 */
6533 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6536 /* PREFIX_VEX_0F3A42 */
6540 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6543 /* PREFIX_VEX_0F3A44 */
6547 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6550 /* PREFIX_VEX_0F3A46 */
6554 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6557 /* PREFIX_VEX_0F3A48 */
6561 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6564 /* PREFIX_VEX_0F3A49 */
6568 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6571 /* PREFIX_VEX_0F3A4A */
6575 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6578 /* PREFIX_VEX_0F3A4B */
6582 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6585 /* PREFIX_VEX_0F3A4C */
6589 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6592 /* PREFIX_VEX_0F3A5C */
6596 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6599 /* PREFIX_VEX_0F3A5D */
6603 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6606 /* PREFIX_VEX_0F3A5E */
6610 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6613 /* PREFIX_VEX_0F3A5F */
6617 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6620 /* PREFIX_VEX_0F3A60 */
6624 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6628 /* PREFIX_VEX_0F3A61 */
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6635 /* PREFIX_VEX_0F3A62 */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6642 /* PREFIX_VEX_0F3A63 */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6649 /* PREFIX_VEX_0F3A68 */
6653 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6656 /* PREFIX_VEX_0F3A69 */
6660 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6663 /* PREFIX_VEX_0F3A6A */
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6670 /* PREFIX_VEX_0F3A6B */
6674 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6677 /* PREFIX_VEX_0F3A6C */
6681 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6684 /* PREFIX_VEX_0F3A6D */
6688 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6691 /* PREFIX_VEX_0F3A6E */
6695 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6698 /* PREFIX_VEX_0F3A6F */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6705 /* PREFIX_VEX_0F3A78 */
6709 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6712 /* PREFIX_VEX_0F3A79 */
6716 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6719 /* PREFIX_VEX_0F3A7A */
6723 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6726 /* PREFIX_VEX_0F3A7B */
6730 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6733 /* PREFIX_VEX_0F3A7C */
6737 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6741 /* PREFIX_VEX_0F3A7D */
6745 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6748 /* PREFIX_VEX_0F3A7E */
6752 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6755 /* PREFIX_VEX_0F3A7F */
6759 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6762 /* PREFIX_VEX_0F3ACE */
6766 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6769 /* PREFIX_VEX_0F3ACF */
6773 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6776 /* PREFIX_VEX_0F3ADF */
6780 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6783 /* PREFIX_VEX_0F3AF0 */
6788 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6791 #include "i386-dis-evex-prefix.h"
6794 static const struct dis386 x86_64_table
[][2] = {
6797 { "pushP", { es
}, 0 },
6802 { "popP", { es
}, 0 },
6807 { "pushP", { cs
}, 0 },
6812 { "pushP", { ss
}, 0 },
6817 { "popP", { ss
}, 0 },
6822 { "pushP", { ds
}, 0 },
6827 { "popP", { ds
}, 0 },
6832 { "daa", { XX
}, 0 },
6837 { "das", { XX
}, 0 },
6842 { "aaa", { XX
}, 0 },
6847 { "aas", { XX
}, 0 },
6852 { "pushaP", { XX
}, 0 },
6857 { "popaP", { XX
}, 0 },
6862 { MOD_TABLE (MOD_62_32BIT
) },
6863 { EVEX_TABLE (EVEX_0F
) },
6868 { "arpl", { Ew
, Gw
}, 0 },
6869 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6874 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6875 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6880 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6881 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6886 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6887 { REG_TABLE (REG_80
) },
6892 { "Jcall{T|}", { Ap
}, 0 },
6897 { MOD_TABLE (MOD_C4_32BIT
) },
6898 { VEX_C4_TABLE (VEX_0F
) },
6903 { MOD_TABLE (MOD_C5_32BIT
) },
6904 { VEX_C5_TABLE (VEX_0F
) },
6909 { "into", { XX
}, 0 },
6914 { "aam", { Ib
}, 0 },
6919 { "aad", { Ib
}, 0 },
6924 { "callP", { Jv
, BND
}, 0 },
6925 { "call@", { Jv
, BND
}, 0 }
6930 { "jmpP", { Jv
, BND
}, 0 },
6931 { "jmp@", { Jv
, BND
}, 0 }
6936 { "Jjmp{T|}", { Ap
}, 0 },
6939 /* X86_64_0F01_REG_0 */
6941 { "sgdt{Q|IQ}", { M
}, 0 },
6942 { "sgdt", { M
}, 0 },
6945 /* X86_64_0F01_REG_1 */
6947 { "sidt{Q|IQ}", { M
}, 0 },
6948 { "sidt", { M
}, 0 },
6951 /* X86_64_0F01_REG_2 */
6953 { "lgdt{Q|Q}", { M
}, 0 },
6954 { "lgdt", { M
}, 0 },
6957 /* X86_64_0F01_REG_3 */
6959 { "lidt{Q|Q}", { M
}, 0 },
6960 { "lidt", { M
}, 0 },
6964 static const struct dis386 three_byte_table
[][256] = {
6966 /* THREE_BYTE_0F38 */
6969 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6970 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6971 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6972 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6973 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6974 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6979 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6987 { PREFIX_TABLE (PREFIX_0F3810
) },
6991 { PREFIX_TABLE (PREFIX_0F3814
) },
6992 { PREFIX_TABLE (PREFIX_0F3815
) },
6994 { PREFIX_TABLE (PREFIX_0F3817
) },
7000 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7001 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7002 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7005 { PREFIX_TABLE (PREFIX_0F3820
) },
7006 { PREFIX_TABLE (PREFIX_0F3821
) },
7007 { PREFIX_TABLE (PREFIX_0F3822
) },
7008 { PREFIX_TABLE (PREFIX_0F3823
) },
7009 { PREFIX_TABLE (PREFIX_0F3824
) },
7010 { PREFIX_TABLE (PREFIX_0F3825
) },
7014 { PREFIX_TABLE (PREFIX_0F3828
) },
7015 { PREFIX_TABLE (PREFIX_0F3829
) },
7016 { PREFIX_TABLE (PREFIX_0F382A
) },
7017 { PREFIX_TABLE (PREFIX_0F382B
) },
7023 { PREFIX_TABLE (PREFIX_0F3830
) },
7024 { PREFIX_TABLE (PREFIX_0F3831
) },
7025 { PREFIX_TABLE (PREFIX_0F3832
) },
7026 { PREFIX_TABLE (PREFIX_0F3833
) },
7027 { PREFIX_TABLE (PREFIX_0F3834
) },
7028 { PREFIX_TABLE (PREFIX_0F3835
) },
7030 { PREFIX_TABLE (PREFIX_0F3837
) },
7032 { PREFIX_TABLE (PREFIX_0F3838
) },
7033 { PREFIX_TABLE (PREFIX_0F3839
) },
7034 { PREFIX_TABLE (PREFIX_0F383A
) },
7035 { PREFIX_TABLE (PREFIX_0F383B
) },
7036 { PREFIX_TABLE (PREFIX_0F383C
) },
7037 { PREFIX_TABLE (PREFIX_0F383D
) },
7038 { PREFIX_TABLE (PREFIX_0F383E
) },
7039 { PREFIX_TABLE (PREFIX_0F383F
) },
7041 { PREFIX_TABLE (PREFIX_0F3840
) },
7042 { PREFIX_TABLE (PREFIX_0F3841
) },
7113 { PREFIX_TABLE (PREFIX_0F3880
) },
7114 { PREFIX_TABLE (PREFIX_0F3881
) },
7115 { PREFIX_TABLE (PREFIX_0F3882
) },
7194 { PREFIX_TABLE (PREFIX_0F38C8
) },
7195 { PREFIX_TABLE (PREFIX_0F38C9
) },
7196 { PREFIX_TABLE (PREFIX_0F38CA
) },
7197 { PREFIX_TABLE (PREFIX_0F38CB
) },
7198 { PREFIX_TABLE (PREFIX_0F38CC
) },
7199 { PREFIX_TABLE (PREFIX_0F38CD
) },
7201 { PREFIX_TABLE (PREFIX_0F38CF
) },
7215 { PREFIX_TABLE (PREFIX_0F38DB
) },
7216 { PREFIX_TABLE (PREFIX_0F38DC
) },
7217 { PREFIX_TABLE (PREFIX_0F38DD
) },
7218 { PREFIX_TABLE (PREFIX_0F38DE
) },
7219 { PREFIX_TABLE (PREFIX_0F38DF
) },
7239 { PREFIX_TABLE (PREFIX_0F38F0
) },
7240 { PREFIX_TABLE (PREFIX_0F38F1
) },
7244 { PREFIX_TABLE (PREFIX_0F38F5
) },
7245 { PREFIX_TABLE (PREFIX_0F38F6
) },
7248 { PREFIX_TABLE (PREFIX_0F38F8
) },
7249 { PREFIX_TABLE (PREFIX_0F38F9
) },
7257 /* THREE_BYTE_0F3A */
7269 { PREFIX_TABLE (PREFIX_0F3A08
) },
7270 { PREFIX_TABLE (PREFIX_0F3A09
) },
7271 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7272 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7273 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7274 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7275 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7276 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7282 { PREFIX_TABLE (PREFIX_0F3A14
) },
7283 { PREFIX_TABLE (PREFIX_0F3A15
) },
7284 { PREFIX_TABLE (PREFIX_0F3A16
) },
7285 { PREFIX_TABLE (PREFIX_0F3A17
) },
7296 { PREFIX_TABLE (PREFIX_0F3A20
) },
7297 { PREFIX_TABLE (PREFIX_0F3A21
) },
7298 { PREFIX_TABLE (PREFIX_0F3A22
) },
7332 { PREFIX_TABLE (PREFIX_0F3A40
) },
7333 { PREFIX_TABLE (PREFIX_0F3A41
) },
7334 { PREFIX_TABLE (PREFIX_0F3A42
) },
7336 { PREFIX_TABLE (PREFIX_0F3A44
) },
7368 { PREFIX_TABLE (PREFIX_0F3A60
) },
7369 { PREFIX_TABLE (PREFIX_0F3A61
) },
7370 { PREFIX_TABLE (PREFIX_0F3A62
) },
7371 { PREFIX_TABLE (PREFIX_0F3A63
) },
7489 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7491 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7492 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7510 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7550 static const struct dis386 xop_table
[][256] = {
7703 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7704 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7705 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7713 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7714 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7721 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7722 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7723 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7731 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7732 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7736 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7737 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7740 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7758 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7770 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7771 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7772 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7773 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7783 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7784 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7785 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7786 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7819 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7820 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7821 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7822 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7846 { REG_TABLE (REG_XOP_TBM_01
) },
7847 { REG_TABLE (REG_XOP_TBM_02
) },
7865 { REG_TABLE (REG_XOP_LWPCB
) },
7989 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7990 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7991 { "vfrczss", { XM
, EXd
}, 0 },
7992 { "vfrczsd", { XM
, EXq
}, 0 },
8007 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8008 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8009 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8010 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8011 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8012 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8013 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8014 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8017 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8062 { "vphaddbw", { XM
, EXxmm
}, 0 },
8063 { "vphaddbd", { XM
, EXxmm
}, 0 },
8064 { "vphaddbq", { XM
, EXxmm
}, 0 },
8067 { "vphaddwd", { XM
, EXxmm
}, 0 },
8068 { "vphaddwq", { XM
, EXxmm
}, 0 },
8073 { "vphadddq", { XM
, EXxmm
}, 0 },
8080 { "vphaddubw", { XM
, EXxmm
}, 0 },
8081 { "vphaddubd", { XM
, EXxmm
}, 0 },
8082 { "vphaddubq", { XM
, EXxmm
}, 0 },
8085 { "vphadduwd", { XM
, EXxmm
}, 0 },
8086 { "vphadduwq", { XM
, EXxmm
}, 0 },
8091 { "vphaddudq", { XM
, EXxmm
}, 0 },
8098 { "vphsubbw", { XM
, EXxmm
}, 0 },
8099 { "vphsubwd", { XM
, EXxmm
}, 0 },
8100 { "vphsubdq", { XM
, EXxmm
}, 0 },
8154 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8156 { REG_TABLE (REG_XOP_LWP
) },
8426 static const struct dis386 vex_table
[][256] = {
8448 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8449 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8450 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8451 { MOD_TABLE (MOD_VEX_0F13
) },
8452 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8453 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8454 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8455 { MOD_TABLE (MOD_VEX_0F17
) },
8475 { "vmovapX", { XM
, EXx
}, 0 },
8476 { "vmovapX", { EXxS
, XM
}, 0 },
8477 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8478 { MOD_TABLE (MOD_VEX_0F2B
) },
8479 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8480 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8503 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8504 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8507 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8520 { MOD_TABLE (MOD_VEX_0F50
) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8522 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8524 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8525 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8526 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8527 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8529 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8531 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8557 { REG_TABLE (REG_VEX_0F71
) },
8558 { REG_TABLE (REG_VEX_0F72
) },
8559 { REG_TABLE (REG_VEX_0F73
) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8625 { REG_TABLE (REG_VEX_0FAE
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8651 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8652 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8664 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8665 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8666 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8746 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8994 { REG_TABLE (REG_VEX_0F38F3
) },
8996 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9243 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9244 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9302 #include "i386-dis-evex.h"
9304 static const struct dis386 vex_len_table
[][2] = {
9305 /* VEX_LEN_0F12_P_0_M_0 */
9307 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9310 /* VEX_LEN_0F12_P_0_M_1 */
9312 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9315 /* VEX_LEN_0F12_P_2 */
9317 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9320 /* VEX_LEN_0F13_M_0 */
9322 { "vmovlpX", { EXq
, XM
}, 0 },
9325 /* VEX_LEN_0F16_P_0_M_0 */
9327 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9330 /* VEX_LEN_0F16_P_0_M_1 */
9332 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9335 /* VEX_LEN_0F16_P_2 */
9337 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9340 /* VEX_LEN_0F17_M_0 */
9342 { "vmovhpX", { EXq
, XM
}, 0 },
9345 /* VEX_LEN_0F41_P_0 */
9348 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9350 /* VEX_LEN_0F41_P_2 */
9353 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9355 /* VEX_LEN_0F42_P_0 */
9358 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9360 /* VEX_LEN_0F42_P_2 */
9363 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9365 /* VEX_LEN_0F44_P_0 */
9367 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9369 /* VEX_LEN_0F44_P_2 */
9371 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9373 /* VEX_LEN_0F45_P_0 */
9376 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9378 /* VEX_LEN_0F45_P_2 */
9381 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9383 /* VEX_LEN_0F46_P_0 */
9386 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9388 /* VEX_LEN_0F46_P_2 */
9391 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9393 /* VEX_LEN_0F47_P_0 */
9396 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9398 /* VEX_LEN_0F47_P_2 */
9401 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9403 /* VEX_LEN_0F4A_P_0 */
9406 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9408 /* VEX_LEN_0F4A_P_2 */
9411 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9413 /* VEX_LEN_0F4B_P_0 */
9416 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9418 /* VEX_LEN_0F4B_P_2 */
9421 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9424 /* VEX_LEN_0F6E_P_2 */
9426 { "vmovK", { XMScalar
, Edq
}, 0 },
9429 /* VEX_LEN_0F77_P_1 */
9431 { "vzeroupper", { XX
}, 0 },
9432 { "vzeroall", { XX
}, 0 },
9435 /* VEX_LEN_0F7E_P_1 */
9437 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9440 /* VEX_LEN_0F7E_P_2 */
9442 { "vmovK", { Edq
, XMScalar
}, 0 },
9445 /* VEX_LEN_0F90_P_0 */
9447 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9450 /* VEX_LEN_0F90_P_2 */
9452 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9455 /* VEX_LEN_0F91_P_0 */
9457 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9460 /* VEX_LEN_0F91_P_2 */
9462 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9465 /* VEX_LEN_0F92_P_0 */
9467 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9470 /* VEX_LEN_0F92_P_2 */
9472 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9475 /* VEX_LEN_0F92_P_3 */
9477 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9480 /* VEX_LEN_0F93_P_0 */
9482 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9485 /* VEX_LEN_0F93_P_2 */
9487 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9490 /* VEX_LEN_0F93_P_3 */
9492 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9495 /* VEX_LEN_0F98_P_0 */
9497 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9500 /* VEX_LEN_0F98_P_2 */
9502 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9505 /* VEX_LEN_0F99_P_0 */
9507 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9510 /* VEX_LEN_0F99_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9515 /* VEX_LEN_0FAE_R_2_M_0 */
9517 { "vldmxcsr", { Md
}, 0 },
9520 /* VEX_LEN_0FAE_R_3_M_0 */
9522 { "vstmxcsr", { Md
}, 0 },
9525 /* VEX_LEN_0FC4_P_2 */
9527 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9530 /* VEX_LEN_0FC5_P_2 */
9532 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9535 /* VEX_LEN_0FD6_P_2 */
9537 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9540 /* VEX_LEN_0FF7_P_2 */
9542 { "vmaskmovdqu", { XM
, XS
}, 0 },
9545 /* VEX_LEN_0F3816_P_2 */
9548 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9551 /* VEX_LEN_0F3819_P_2 */
9554 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9557 /* VEX_LEN_0F381A_P_2_M_0 */
9560 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9563 /* VEX_LEN_0F3836_P_2 */
9566 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9569 /* VEX_LEN_0F3841_P_2 */
9571 { "vphminposuw", { XM
, EXx
}, 0 },
9574 /* VEX_LEN_0F385A_P_2_M_0 */
9577 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9580 /* VEX_LEN_0F38DB_P_2 */
9582 { "vaesimc", { XM
, EXx
}, 0 },
9585 /* VEX_LEN_0F38F2_P_0 */
9587 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9590 /* VEX_LEN_0F38F3_R_1_P_0 */
9592 { "blsrS", { VexGdq
, Edq
}, 0 },
9595 /* VEX_LEN_0F38F3_R_2_P_0 */
9597 { "blsmskS", { VexGdq
, Edq
}, 0 },
9600 /* VEX_LEN_0F38F3_R_3_P_0 */
9602 { "blsiS", { VexGdq
, Edq
}, 0 },
9605 /* VEX_LEN_0F38F5_P_0 */
9607 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9610 /* VEX_LEN_0F38F5_P_1 */
9612 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9615 /* VEX_LEN_0F38F5_P_3 */
9617 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9620 /* VEX_LEN_0F38F6_P_3 */
9622 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9625 /* VEX_LEN_0F38F7_P_0 */
9627 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9630 /* VEX_LEN_0F38F7_P_1 */
9632 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9635 /* VEX_LEN_0F38F7_P_2 */
9637 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9640 /* VEX_LEN_0F38F7_P_3 */
9642 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9645 /* VEX_LEN_0F3A00_P_2 */
9648 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9651 /* VEX_LEN_0F3A01_P_2 */
9654 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9657 /* VEX_LEN_0F3A06_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9663 /* VEX_LEN_0F3A14_P_2 */
9665 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9668 /* VEX_LEN_0F3A15_P_2 */
9670 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9673 /* VEX_LEN_0F3A16_P_2 */
9675 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9678 /* VEX_LEN_0F3A17_P_2 */
9680 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9683 /* VEX_LEN_0F3A18_P_2 */
9686 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9689 /* VEX_LEN_0F3A19_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9695 /* VEX_LEN_0F3A20_P_2 */
9697 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9700 /* VEX_LEN_0F3A21_P_2 */
9702 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9705 /* VEX_LEN_0F3A22_P_2 */
9707 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9710 /* VEX_LEN_0F3A30_P_2 */
9712 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9715 /* VEX_LEN_0F3A31_P_2 */
9717 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9720 /* VEX_LEN_0F3A32_P_2 */
9722 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9725 /* VEX_LEN_0F3A33_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9730 /* VEX_LEN_0F3A38_P_2 */
9733 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9736 /* VEX_LEN_0F3A39_P_2 */
9739 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9742 /* VEX_LEN_0F3A41_P_2 */
9744 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9747 /* VEX_LEN_0F3A46_P_2 */
9750 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9753 /* VEX_LEN_0F3A60_P_2 */
9755 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9758 /* VEX_LEN_0F3A61_P_2 */
9760 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9763 /* VEX_LEN_0F3A62_P_2 */
9765 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9768 /* VEX_LEN_0F3A63_P_2 */
9770 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9773 /* VEX_LEN_0F3A6A_P_2 */
9775 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9778 /* VEX_LEN_0F3A6B_P_2 */
9780 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9783 /* VEX_LEN_0F3A6E_P_2 */
9785 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9788 /* VEX_LEN_0F3A6F_P_2 */
9790 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9793 /* VEX_LEN_0F3A7A_P_2 */
9795 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9798 /* VEX_LEN_0F3A7B_P_2 */
9800 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9803 /* VEX_LEN_0F3A7E_P_2 */
9805 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9808 /* VEX_LEN_0F3A7F_P_2 */
9810 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9813 /* VEX_LEN_0F3ADF_P_2 */
9815 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9818 /* VEX_LEN_0F3AF0_P_3 */
9820 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9823 /* VEX_LEN_0FXOP_08_CC */
9825 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9828 /* VEX_LEN_0FXOP_08_CD */
9830 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9833 /* VEX_LEN_0FXOP_08_CE */
9835 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9838 /* VEX_LEN_0FXOP_08_CF */
9840 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9843 /* VEX_LEN_0FXOP_08_EC */
9845 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9848 /* VEX_LEN_0FXOP_08_ED */
9850 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9853 /* VEX_LEN_0FXOP_08_EE */
9855 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9858 /* VEX_LEN_0FXOP_08_EF */
9860 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9863 /* VEX_LEN_0FXOP_09_80 */
9865 { "vfrczps", { XM
, EXxmm
}, 0 },
9866 { "vfrczps", { XM
, EXymmq
}, 0 },
9869 /* VEX_LEN_0FXOP_09_81 */
9871 { "vfrczpd", { XM
, EXxmm
}, 0 },
9872 { "vfrczpd", { XM
, EXymmq
}, 0 },
9876 #include "i386-dis-evex-len.h"
9878 static const struct dis386 vex_w_table
[][2] = {
9880 /* VEX_W_0F41_P_0_LEN_1 */
9881 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9882 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9885 /* VEX_W_0F41_P_2_LEN_1 */
9886 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9887 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9890 /* VEX_W_0F42_P_0_LEN_1 */
9891 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9892 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9895 /* VEX_W_0F42_P_2_LEN_1 */
9896 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9897 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9900 /* VEX_W_0F44_P_0_LEN_0 */
9901 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9902 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9905 /* VEX_W_0F44_P_2_LEN_0 */
9906 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9907 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9910 /* VEX_W_0F45_P_0_LEN_1 */
9911 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9912 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9915 /* VEX_W_0F45_P_2_LEN_1 */
9916 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9917 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9920 /* VEX_W_0F46_P_0_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9925 /* VEX_W_0F46_P_2_LEN_1 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9930 /* VEX_W_0F47_P_0_LEN_1 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9935 /* VEX_W_0F47_P_2_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9940 /* VEX_W_0F4A_P_0_LEN_1 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9945 /* VEX_W_0F4A_P_2_LEN_1 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9950 /* VEX_W_0F4B_P_0_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9955 /* VEX_W_0F4B_P_2_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9959 /* VEX_W_0F90_P_0_LEN_0 */
9960 { "kmovw", { MaskG
, MaskE
}, 0 },
9961 { "kmovq", { MaskG
, MaskE
}, 0 },
9964 /* VEX_W_0F90_P_2_LEN_0 */
9965 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9966 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9969 /* VEX_W_0F91_P_0_LEN_0 */
9970 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9971 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9974 /* VEX_W_0F91_P_2_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9976 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9979 /* VEX_W_0F92_P_0_LEN_0 */
9980 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9983 /* VEX_W_0F92_P_2_LEN_0 */
9984 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9987 /* VEX_W_0F93_P_0_LEN_0 */
9988 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9991 /* VEX_W_0F93_P_2_LEN_0 */
9992 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9995 /* VEX_W_0F98_P_0_LEN_0 */
9996 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9997 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10000 /* VEX_W_0F98_P_2_LEN_0 */
10001 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10002 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10005 /* VEX_W_0F99_P_0_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10007 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10010 /* VEX_W_0F99_P_2_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10015 /* VEX_W_0F380C_P_2 */
10016 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10019 /* VEX_W_0F380D_P_2 */
10020 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10023 /* VEX_W_0F380E_P_2 */
10024 { "vtestps", { XM
, EXx
}, 0 },
10027 /* VEX_W_0F380F_P_2 */
10028 { "vtestpd", { XM
, EXx
}, 0 },
10031 /* VEX_W_0F3816_P_2 */
10032 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10035 /* VEX_W_0F3818_P_2 */
10036 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10039 /* VEX_W_0F3819_P_2 */
10040 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10043 /* VEX_W_0F381A_P_2_M_0 */
10044 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10047 /* VEX_W_0F382C_P_2_M_0 */
10048 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10051 /* VEX_W_0F382D_P_2_M_0 */
10052 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10055 /* VEX_W_0F382E_P_2_M_0 */
10056 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10059 /* VEX_W_0F382F_P_2_M_0 */
10060 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10063 /* VEX_W_0F3836_P_2 */
10064 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10067 /* VEX_W_0F3846_P_2 */
10068 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10071 /* VEX_W_0F3858_P_2 */
10072 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10075 /* VEX_W_0F3859_P_2 */
10076 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10079 /* VEX_W_0F385A_P_2_M_0 */
10080 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10083 /* VEX_W_0F3878_P_2 */
10084 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10087 /* VEX_W_0F3879_P_2 */
10088 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10091 /* VEX_W_0F38CF_P_2 */
10092 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10095 /* VEX_W_0F3A00_P_2 */
10097 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10100 /* VEX_W_0F3A01_P_2 */
10102 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10105 /* VEX_W_0F3A02_P_2 */
10106 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10109 /* VEX_W_0F3A04_P_2 */
10110 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10113 /* VEX_W_0F3A05_P_2 */
10114 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10117 /* VEX_W_0F3A06_P_2 */
10118 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10121 /* VEX_W_0F3A18_P_2 */
10122 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10125 /* VEX_W_0F3A19_P_2 */
10126 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10129 /* VEX_W_0F3A30_P_2_LEN_0 */
10130 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10131 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10134 /* VEX_W_0F3A31_P_2_LEN_0 */
10135 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10136 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10139 /* VEX_W_0F3A32_P_2_LEN_0 */
10140 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10141 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10144 /* VEX_W_0F3A33_P_2_LEN_0 */
10145 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10146 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10149 /* VEX_W_0F3A38_P_2 */
10150 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10153 /* VEX_W_0F3A39_P_2 */
10154 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10157 /* VEX_W_0F3A46_P_2 */
10158 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10161 /* VEX_W_0F3A48_P_2 */
10162 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10163 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10166 /* VEX_W_0F3A49_P_2 */
10167 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10168 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10171 /* VEX_W_0F3A4A_P_2 */
10172 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10175 /* VEX_W_0F3A4B_P_2 */
10176 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10179 /* VEX_W_0F3A4C_P_2 */
10180 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10183 /* VEX_W_0F3ACE_P_2 */
10185 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10188 /* VEX_W_0F3ACF_P_2 */
10190 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10193 #include "i386-dis-evex-w.h"
10196 static const struct dis386 mod_table
[][2] = {
10199 { "leaS", { Gv
, M
}, 0 },
10204 { RM_TABLE (RM_C6_REG_7
) },
10209 { RM_TABLE (RM_C7_REG_7
) },
10213 { "Jcall^", { indirEp
}, 0 },
10217 { "Jjmp^", { indirEp
}, 0 },
10220 /* MOD_0F01_REG_0 */
10221 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10222 { RM_TABLE (RM_0F01_REG_0
) },
10225 /* MOD_0F01_REG_1 */
10226 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10227 { RM_TABLE (RM_0F01_REG_1
) },
10230 /* MOD_0F01_REG_2 */
10231 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10232 { RM_TABLE (RM_0F01_REG_2
) },
10235 /* MOD_0F01_REG_3 */
10236 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10237 { RM_TABLE (RM_0F01_REG_3
) },
10240 /* MOD_0F01_REG_5 */
10241 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
10242 { RM_TABLE (RM_0F01_REG_5
) },
10245 /* MOD_0F01_REG_7 */
10246 { "invlpg", { Mb
}, 0 },
10247 { RM_TABLE (RM_0F01_REG_7
) },
10250 /* MOD_0F12_PREFIX_0 */
10251 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10252 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10256 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10259 /* MOD_0F16_PREFIX_0 */
10260 { "movhps", { XM
, EXq
}, 0 },
10261 { "movlhps", { XM
, EXq
}, 0 },
10265 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10268 /* MOD_0F18_REG_0 */
10269 { "prefetchnta", { Mb
}, 0 },
10272 /* MOD_0F18_REG_1 */
10273 { "prefetcht0", { Mb
}, 0 },
10276 /* MOD_0F18_REG_2 */
10277 { "prefetcht1", { Mb
}, 0 },
10280 /* MOD_0F18_REG_3 */
10281 { "prefetcht2", { Mb
}, 0 },
10284 /* MOD_0F18_REG_4 */
10285 { "nop/reserved", { Mb
}, 0 },
10288 /* MOD_0F18_REG_5 */
10289 { "nop/reserved", { Mb
}, 0 },
10292 /* MOD_0F18_REG_6 */
10293 { "nop/reserved", { Mb
}, 0 },
10296 /* MOD_0F18_REG_7 */
10297 { "nop/reserved", { Mb
}, 0 },
10300 /* MOD_0F1A_PREFIX_0 */
10301 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10302 { "nopQ", { Ev
}, 0 },
10305 /* MOD_0F1B_PREFIX_0 */
10306 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10307 { "nopQ", { Ev
}, 0 },
10310 /* MOD_0F1B_PREFIX_1 */
10311 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10312 { "nopQ", { Ev
}, 0 },
10315 /* MOD_0F1C_PREFIX_0 */
10316 { REG_TABLE (REG_0F1C_MOD_0
) },
10317 { "nopQ", { Ev
}, 0 },
10320 /* MOD_0F1E_PREFIX_1 */
10321 { "nopQ", { Ev
}, 0 },
10322 { REG_TABLE (REG_0F1E_MOD_3
) },
10327 { "movL", { Rd
, Td
}, 0 },
10332 { "movL", { Td
, Rd
}, 0 },
10335 /* MOD_0F2B_PREFIX_0 */
10336 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10339 /* MOD_0F2B_PREFIX_1 */
10340 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10343 /* MOD_0F2B_PREFIX_2 */
10344 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10347 /* MOD_0F2B_PREFIX_3 */
10348 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10353 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10356 /* MOD_0F71_REG_2 */
10358 { "psrlw", { MS
, Ib
}, 0 },
10361 /* MOD_0F71_REG_4 */
10363 { "psraw", { MS
, Ib
}, 0 },
10366 /* MOD_0F71_REG_6 */
10368 { "psllw", { MS
, Ib
}, 0 },
10371 /* MOD_0F72_REG_2 */
10373 { "psrld", { MS
, Ib
}, 0 },
10376 /* MOD_0F72_REG_4 */
10378 { "psrad", { MS
, Ib
}, 0 },
10381 /* MOD_0F72_REG_6 */
10383 { "pslld", { MS
, Ib
}, 0 },
10386 /* MOD_0F73_REG_2 */
10388 { "psrlq", { MS
, Ib
}, 0 },
10391 /* MOD_0F73_REG_3 */
10393 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10396 /* MOD_0F73_REG_6 */
10398 { "psllq", { MS
, Ib
}, 0 },
10401 /* MOD_0F73_REG_7 */
10403 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10406 /* MOD_0FAE_REG_0 */
10407 { "fxsave", { FXSAVE
}, 0 },
10408 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
10411 /* MOD_0FAE_REG_1 */
10412 { "fxrstor", { FXSAVE
}, 0 },
10413 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
10416 /* MOD_0FAE_REG_2 */
10417 { "ldmxcsr", { Md
}, 0 },
10418 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
10421 /* MOD_0FAE_REG_3 */
10422 { "stmxcsr", { Md
}, 0 },
10423 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
10426 /* MOD_0FAE_REG_4 */
10427 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
10428 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
10431 /* MOD_0FAE_REG_5 */
10432 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
10433 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
10436 /* MOD_0FAE_REG_6 */
10437 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6
) },
10438 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6
) },
10441 /* MOD_0FAE_REG_7 */
10442 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
10443 { RM_TABLE (RM_0FAE_REG_7
) },
10447 { "lssS", { Gv
, Mp
}, 0 },
10451 { "lfsS", { Gv
, Mp
}, 0 },
10455 { "lgsS", { Gv
, Mp
}, 0 },
10459 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
10462 /* MOD_0FC7_REG_3 */
10463 { "xrstors", { FXSAVE
}, 0 },
10466 /* MOD_0FC7_REG_4 */
10467 { "xsavec", { FXSAVE
}, 0 },
10470 /* MOD_0FC7_REG_5 */
10471 { "xsaves", { FXSAVE
}, 0 },
10474 /* MOD_0FC7_REG_6 */
10475 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
10476 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
10479 /* MOD_0FC7_REG_7 */
10480 { "vmptrst", { Mq
}, 0 },
10481 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
10486 { "pmovmskb", { Gdq
, MS
}, 0 },
10489 /* MOD_0FE7_PREFIX_2 */
10490 { "movntdq", { Mx
, XM
}, 0 },
10493 /* MOD_0FF0_PREFIX_3 */
10494 { "lddqu", { XM
, M
}, 0 },
10497 /* MOD_0F382A_PREFIX_2 */
10498 { "movntdqa", { XM
, Mx
}, 0 },
10501 /* MOD_0F38F5_PREFIX_2 */
10502 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10505 /* MOD_0F38F6_PREFIX_0 */
10506 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10509 /* MOD_0F38F8_PREFIX_1 */
10510 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10513 /* MOD_0F38F8_PREFIX_2 */
10514 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10517 /* MOD_0F38F8_PREFIX_3 */
10518 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10521 /* MOD_0F38F9_PREFIX_0 */
10522 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10526 { "bound{S|}", { Gv
, Ma
}, 0 },
10527 { EVEX_TABLE (EVEX_0F
) },
10531 { "lesS", { Gv
, Mp
}, 0 },
10532 { VEX_C4_TABLE (VEX_0F
) },
10536 { "ldsS", { Gv
, Mp
}, 0 },
10537 { VEX_C5_TABLE (VEX_0F
) },
10540 /* MOD_VEX_0F12_PREFIX_0 */
10541 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10542 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10546 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10549 /* MOD_VEX_0F16_PREFIX_0 */
10550 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10551 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10555 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10559 { "vmovntpX", { Mx
, XM
}, 0 },
10562 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10564 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10567 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10569 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10572 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10574 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10577 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10579 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10582 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10584 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10587 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10589 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10592 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10594 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10597 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10599 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10602 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10604 { "knotw", { MaskG
, MaskR
}, 0 },
10607 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10609 { "knotq", { MaskG
, MaskR
}, 0 },
10612 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10614 { "knotb", { MaskG
, MaskR
}, 0 },
10617 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10619 { "knotd", { MaskG
, MaskR
}, 0 },
10622 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10624 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10627 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10629 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10632 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10634 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10637 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10639 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10642 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10644 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10647 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10649 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10652 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10654 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10657 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10659 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10662 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10664 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10667 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10669 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10672 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10674 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10677 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10679 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10682 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10684 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10687 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10689 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10692 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10694 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10697 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10699 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10702 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10704 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10707 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10709 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10712 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10714 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10719 { "vmovmskpX", { Gdq
, XS
}, 0 },
10722 /* MOD_VEX_0F71_REG_2 */
10724 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10727 /* MOD_VEX_0F71_REG_4 */
10729 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10732 /* MOD_VEX_0F71_REG_6 */
10734 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10737 /* MOD_VEX_0F72_REG_2 */
10739 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10742 /* MOD_VEX_0F72_REG_4 */
10744 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10747 /* MOD_VEX_0F72_REG_6 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10752 /* MOD_VEX_0F73_REG_2 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10757 /* MOD_VEX_0F73_REG_3 */
10759 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10762 /* MOD_VEX_0F73_REG_6 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10767 /* MOD_VEX_0F73_REG_7 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10772 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10773 { "kmovw", { Ew
, MaskG
}, 0 },
10777 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778 { "kmovq", { Eq
, MaskG
}, 0 },
10782 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10783 { "kmovb", { Eb
, MaskG
}, 0 },
10787 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788 { "kmovd", { Ed
, MaskG
}, 0 },
10792 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10794 { "kmovw", { MaskG
, Rdq
}, 0 },
10797 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10799 { "kmovb", { MaskG
, Rdq
}, 0 },
10802 /* MOD_VEX_0F92_P_3_LEN_0 */
10804 { "kmovK", { MaskG
, Rdq
}, 0 },
10807 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10809 { "kmovw", { Gdq
, MaskR
}, 0 },
10812 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10814 { "kmovb", { Gdq
, MaskR
}, 0 },
10817 /* MOD_VEX_0F93_P_3_LEN_0 */
10819 { "kmovK", { Gdq
, MaskR
}, 0 },
10822 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10824 { "kortestw", { MaskG
, MaskR
}, 0 },
10827 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10829 { "kortestq", { MaskG
, MaskR
}, 0 },
10832 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10834 { "kortestb", { MaskG
, MaskR
}, 0 },
10837 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10839 { "kortestd", { MaskG
, MaskR
}, 0 },
10842 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10844 { "ktestw", { MaskG
, MaskR
}, 0 },
10847 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10849 { "ktestq", { MaskG
, MaskR
}, 0 },
10852 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10854 { "ktestb", { MaskG
, MaskR
}, 0 },
10857 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10859 { "ktestd", { MaskG
, MaskR
}, 0 },
10862 /* MOD_VEX_0FAE_REG_2 */
10863 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10866 /* MOD_VEX_0FAE_REG_3 */
10867 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10870 /* MOD_VEX_0FD7_PREFIX_2 */
10872 { "vpmovmskb", { Gdq
, XS
}, 0 },
10875 /* MOD_VEX_0FE7_PREFIX_2 */
10876 { "vmovntdq", { Mx
, XM
}, 0 },
10879 /* MOD_VEX_0FF0_PREFIX_3 */
10880 { "vlddqu", { XM
, M
}, 0 },
10883 /* MOD_VEX_0F381A_PREFIX_2 */
10884 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10887 /* MOD_VEX_0F382A_PREFIX_2 */
10888 { "vmovntdqa", { XM
, Mx
}, 0 },
10891 /* MOD_VEX_0F382C_PREFIX_2 */
10892 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10895 /* MOD_VEX_0F382D_PREFIX_2 */
10896 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10899 /* MOD_VEX_0F382E_PREFIX_2 */
10900 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10903 /* MOD_VEX_0F382F_PREFIX_2 */
10904 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10907 /* MOD_VEX_0F385A_PREFIX_2 */
10908 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10911 /* MOD_VEX_0F388C_PREFIX_2 */
10912 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10915 /* MOD_VEX_0F388E_PREFIX_2 */
10916 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10919 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10921 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10924 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10926 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10929 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10931 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10934 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10936 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10939 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10941 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10944 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10946 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10949 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10951 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10954 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10956 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10959 #include "i386-dis-evex-mod.h"
10962 static const struct dis386 rm_table
[][8] = {
10965 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10969 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10972 /* RM_0F01_REG_0 */
10973 { "enclv", { Skip_MODRM
}, 0 },
10974 { "vmcall", { Skip_MODRM
}, 0 },
10975 { "vmlaunch", { Skip_MODRM
}, 0 },
10976 { "vmresume", { Skip_MODRM
}, 0 },
10977 { "vmxoff", { Skip_MODRM
}, 0 },
10978 { "pconfig", { Skip_MODRM
}, 0 },
10981 /* RM_0F01_REG_1 */
10982 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10983 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10984 { "clac", { Skip_MODRM
}, 0 },
10985 { "stac", { Skip_MODRM
}, 0 },
10989 { "encls", { Skip_MODRM
}, 0 },
10992 /* RM_0F01_REG_2 */
10993 { "xgetbv", { Skip_MODRM
}, 0 },
10994 { "xsetbv", { Skip_MODRM
}, 0 },
10997 { "vmfunc", { Skip_MODRM
}, 0 },
10998 { "xend", { Skip_MODRM
}, 0 },
10999 { "xtest", { Skip_MODRM
}, 0 },
11000 { "enclu", { Skip_MODRM
}, 0 },
11003 /* RM_0F01_REG_3 */
11004 { "vmrun", { Skip_MODRM
}, 0 },
11005 { "vmmcall", { Skip_MODRM
}, 0 },
11006 { "vmload", { Skip_MODRM
}, 0 },
11007 { "vmsave", { Skip_MODRM
}, 0 },
11008 { "stgi", { Skip_MODRM
}, 0 },
11009 { "clgi", { Skip_MODRM
}, 0 },
11010 { "skinit", { Skip_MODRM
}, 0 },
11011 { "invlpga", { Skip_MODRM
}, 0 },
11014 /* RM_0F01_REG_5 */
11015 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
11017 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
11021 { "rdpkru", { Skip_MODRM
}, 0 },
11022 { "wrpkru", { Skip_MODRM
}, 0 },
11025 /* RM_0F01_REG_7 */
11026 { "swapgs", { Skip_MODRM
}, 0 },
11027 { "rdtscp", { Skip_MODRM
}, 0 },
11028 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
11029 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
11030 { "clzero", { Skip_MODRM
}, 0 },
11033 /* RM_0F1E_MOD_3_REG_7 */
11034 { "nopQ", { Ev
}, 0 },
11035 { "nopQ", { Ev
}, 0 },
11036 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11037 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11038 { "nopQ", { Ev
}, 0 },
11039 { "nopQ", { Ev
}, 0 },
11040 { "nopQ", { Ev
}, 0 },
11041 { "nopQ", { Ev
}, 0 },
11044 /* RM_0FAE_REG_6 */
11045 { "mfence", { Skip_MODRM
}, 0 },
11048 /* RM_0FAE_REG_7 */
11049 { "sfence", { Skip_MODRM
}, 0 },
11054 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11056 /* We use the high bit to indicate different name for the same
11058 #define REP_PREFIX (0xf3 | 0x100)
11059 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11060 #define XRELEASE_PREFIX (0xf3 | 0x400)
11061 #define BND_PREFIX (0xf2 | 0x400)
11062 #define NOTRACK_PREFIX (0x3e | 0x100)
11067 int newrex
, i
, length
;
11073 last_lock_prefix
= -1;
11074 last_repz_prefix
= -1;
11075 last_repnz_prefix
= -1;
11076 last_data_prefix
= -1;
11077 last_addr_prefix
= -1;
11078 last_rex_prefix
= -1;
11079 last_seg_prefix
= -1;
11081 active_seg_prefix
= 0;
11082 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11083 all_prefixes
[i
] = 0;
11086 /* The maximum instruction length is 15bytes. */
11087 while (length
< MAX_CODE_LENGTH
- 1)
11089 FETCH_DATA (the_info
, codep
+ 1);
11093 /* REX prefixes family. */
11110 if (address_mode
== mode_64bit
)
11114 last_rex_prefix
= i
;
11117 prefixes
|= PREFIX_REPZ
;
11118 last_repz_prefix
= i
;
11121 prefixes
|= PREFIX_REPNZ
;
11122 last_repnz_prefix
= i
;
11125 prefixes
|= PREFIX_LOCK
;
11126 last_lock_prefix
= i
;
11129 prefixes
|= PREFIX_CS
;
11130 last_seg_prefix
= i
;
11131 active_seg_prefix
= PREFIX_CS
;
11134 prefixes
|= PREFIX_SS
;
11135 last_seg_prefix
= i
;
11136 active_seg_prefix
= PREFIX_SS
;
11139 prefixes
|= PREFIX_DS
;
11140 last_seg_prefix
= i
;
11141 active_seg_prefix
= PREFIX_DS
;
11144 prefixes
|= PREFIX_ES
;
11145 last_seg_prefix
= i
;
11146 active_seg_prefix
= PREFIX_ES
;
11149 prefixes
|= PREFIX_FS
;
11150 last_seg_prefix
= i
;
11151 active_seg_prefix
= PREFIX_FS
;
11154 prefixes
|= PREFIX_GS
;
11155 last_seg_prefix
= i
;
11156 active_seg_prefix
= PREFIX_GS
;
11159 prefixes
|= PREFIX_DATA
;
11160 last_data_prefix
= i
;
11163 prefixes
|= PREFIX_ADDR
;
11164 last_addr_prefix
= i
;
11167 /* fwait is really an instruction. If there are prefixes
11168 before the fwait, they belong to the fwait, *not* to the
11169 following instruction. */
11171 if (prefixes
|| rex
)
11173 prefixes
|= PREFIX_FWAIT
;
11175 /* This ensures that the previous REX prefixes are noticed
11176 as unused prefixes, as in the return case below. */
11180 prefixes
= PREFIX_FWAIT
;
11185 /* Rex is ignored when followed by another prefix. */
11191 if (*codep
!= FWAIT_OPCODE
)
11192 all_prefixes
[i
++] = *codep
;
11200 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11203 static const char *
11204 prefix_name (int pref
, int sizeflag
)
11206 static const char *rexes
[16] =
11209 "rex.B", /* 0x41 */
11210 "rex.X", /* 0x42 */
11211 "rex.XB", /* 0x43 */
11212 "rex.R", /* 0x44 */
11213 "rex.RB", /* 0x45 */
11214 "rex.RX", /* 0x46 */
11215 "rex.RXB", /* 0x47 */
11216 "rex.W", /* 0x48 */
11217 "rex.WB", /* 0x49 */
11218 "rex.WX", /* 0x4a */
11219 "rex.WXB", /* 0x4b */
11220 "rex.WR", /* 0x4c */
11221 "rex.WRB", /* 0x4d */
11222 "rex.WRX", /* 0x4e */
11223 "rex.WRXB", /* 0x4f */
11228 /* REX prefixes family. */
11245 return rexes
[pref
- 0x40];
11265 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11267 if (address_mode
== mode_64bit
)
11268 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11270 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11275 case XACQUIRE_PREFIX
:
11277 case XRELEASE_PREFIX
:
11281 case NOTRACK_PREFIX
:
11288 static char op_out
[MAX_OPERANDS
][100];
11289 static int op_ad
, op_index
[MAX_OPERANDS
];
11290 static int two_source_ops
;
11291 static bfd_vma op_address
[MAX_OPERANDS
];
11292 static bfd_vma op_riprel
[MAX_OPERANDS
];
11293 static bfd_vma start_pc
;
11296 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11297 * (see topic "Redundant prefixes" in the "Differences from 8086"
11298 * section of the "Virtual 8086 Mode" chapter.)
11299 * 'pc' should be the address of this instruction, it will
11300 * be used to print the target address if this is a relative jump or call
11301 * The function returns the length of this instruction in bytes.
11304 static char intel_syntax
;
11305 static char intel_mnemonic
= !SYSV386_COMPAT
;
11306 static char open_char
;
11307 static char close_char
;
11308 static char separator_char
;
11309 static char scale_char
;
11317 static enum x86_64_isa isa64
;
11319 /* Here for backwards compatibility. When gdb stops using
11320 print_insn_i386_att and print_insn_i386_intel these functions can
11321 disappear, and print_insn_i386 be merged into print_insn. */
11323 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11327 return print_insn (pc
, info
);
11331 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11335 return print_insn (pc
, info
);
11339 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11343 return print_insn (pc
, info
);
11347 print_i386_disassembler_options (FILE *stream
)
11349 fprintf (stream
, _("\n\
11350 The following i386/x86-64 specific disassembler options are supported for use\n\
11351 with the -M switch (multiple options should be separated by commas):\n"));
11353 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11354 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11355 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11356 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11357 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11358 fprintf (stream
, _(" att-mnemonic\n"
11359 " Display instruction in AT&T mnemonic\n"));
11360 fprintf (stream
, _(" intel-mnemonic\n"
11361 " Display instruction in Intel mnemonic\n"));
11362 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11363 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11364 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11365 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11366 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11367 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11368 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11369 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11373 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11375 /* Get a pointer to struct dis386 with a valid name. */
11377 static const struct dis386
*
11378 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11380 int vindex
, vex_table_index
;
11382 if (dp
->name
!= NULL
)
11385 switch (dp
->op
[0].bytemode
)
11387 case USE_REG_TABLE
:
11388 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11391 case USE_MOD_TABLE
:
11392 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11393 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11397 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11400 case USE_PREFIX_TABLE
:
11403 /* The prefix in VEX is implicit. */
11404 switch (vex
.prefix
)
11409 case REPE_PREFIX_OPCODE
:
11412 case DATA_PREFIX_OPCODE
:
11415 case REPNE_PREFIX_OPCODE
:
11425 int last_prefix
= -1;
11428 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11429 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11431 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11433 if (last_repz_prefix
> last_repnz_prefix
)
11436 prefix
= PREFIX_REPZ
;
11437 last_prefix
= last_repz_prefix
;
11442 prefix
= PREFIX_REPNZ
;
11443 last_prefix
= last_repnz_prefix
;
11446 /* Check if prefix should be ignored. */
11447 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11448 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11453 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11456 prefix
= PREFIX_DATA
;
11457 last_prefix
= last_data_prefix
;
11462 used_prefixes
|= prefix
;
11463 all_prefixes
[last_prefix
] = 0;
11466 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11469 case USE_X86_64_TABLE
:
11470 vindex
= address_mode
== mode_64bit
? 1 : 0;
11471 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11474 case USE_3BYTE_TABLE
:
11475 FETCH_DATA (info
, codep
+ 2);
11477 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11479 modrm
.mod
= (*codep
>> 6) & 3;
11480 modrm
.reg
= (*codep
>> 3) & 7;
11481 modrm
.rm
= *codep
& 7;
11484 case USE_VEX_LEN_TABLE
:
11488 switch (vex
.length
)
11501 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11504 case USE_EVEX_LEN_TABLE
:
11508 switch (vex
.length
)
11524 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11527 case USE_XOP_8F_TABLE
:
11528 FETCH_DATA (info
, codep
+ 3);
11529 /* All bits in the REX prefix are ignored. */
11531 rex
= ~(*codep
>> 5) & 0x7;
11533 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11534 switch ((*codep
& 0x1f))
11540 vex_table_index
= XOP_08
;
11543 vex_table_index
= XOP_09
;
11546 vex_table_index
= XOP_0A
;
11550 vex
.w
= *codep
& 0x80;
11551 if (vex
.w
&& address_mode
== mode_64bit
)
11554 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11555 if (address_mode
!= mode_64bit
)
11557 /* In 16/32-bit mode REX_B is silently ignored. */
11561 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11562 switch ((*codep
& 0x3))
11567 vex
.prefix
= DATA_PREFIX_OPCODE
;
11570 vex
.prefix
= REPE_PREFIX_OPCODE
;
11573 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11580 dp
= &xop_table
[vex_table_index
][vindex
];
11583 FETCH_DATA (info
, codep
+ 1);
11584 modrm
.mod
= (*codep
>> 6) & 3;
11585 modrm
.reg
= (*codep
>> 3) & 7;
11586 modrm
.rm
= *codep
& 7;
11589 case USE_VEX_C4_TABLE
:
11591 FETCH_DATA (info
, codep
+ 3);
11592 /* All bits in the REX prefix are ignored. */
11594 rex
= ~(*codep
>> 5) & 0x7;
11595 switch ((*codep
& 0x1f))
11601 vex_table_index
= VEX_0F
;
11604 vex_table_index
= VEX_0F38
;
11607 vex_table_index
= VEX_0F3A
;
11611 vex
.w
= *codep
& 0x80;
11612 if (address_mode
== mode_64bit
)
11619 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11620 is ignored, other REX bits are 0 and the highest bit in
11621 VEX.vvvv is also ignored (but we mustn't clear it here). */
11624 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11625 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11626 switch ((*codep
& 0x3))
11631 vex
.prefix
= DATA_PREFIX_OPCODE
;
11634 vex
.prefix
= REPE_PREFIX_OPCODE
;
11637 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11644 dp
= &vex_table
[vex_table_index
][vindex
];
11646 /* There is no MODRM byte for VEX0F 77. */
11647 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11649 FETCH_DATA (info
, codep
+ 1);
11650 modrm
.mod
= (*codep
>> 6) & 3;
11651 modrm
.reg
= (*codep
>> 3) & 7;
11652 modrm
.rm
= *codep
& 7;
11656 case USE_VEX_C5_TABLE
:
11658 FETCH_DATA (info
, codep
+ 2);
11659 /* All bits in the REX prefix are ignored. */
11661 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11663 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11665 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11666 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11667 switch ((*codep
& 0x3))
11672 vex
.prefix
= DATA_PREFIX_OPCODE
;
11675 vex
.prefix
= REPE_PREFIX_OPCODE
;
11678 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11685 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11687 /* There is no MODRM byte for VEX 77. */
11688 if (vindex
!= 0x77)
11690 FETCH_DATA (info
, codep
+ 1);
11691 modrm
.mod
= (*codep
>> 6) & 3;
11692 modrm
.reg
= (*codep
>> 3) & 7;
11693 modrm
.rm
= *codep
& 7;
11697 case USE_VEX_W_TABLE
:
11701 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11704 case USE_EVEX_TABLE
:
11705 two_source_ops
= 0;
11708 FETCH_DATA (info
, codep
+ 4);
11709 /* All bits in the REX prefix are ignored. */
11711 /* The first byte after 0x62. */
11712 rex
= ~(*codep
>> 5) & 0x7;
11713 vex
.r
= *codep
& 0x10;
11714 switch ((*codep
& 0xf))
11717 return &bad_opcode
;
11719 vex_table_index
= EVEX_0F
;
11722 vex_table_index
= EVEX_0F38
;
11725 vex_table_index
= EVEX_0F3A
;
11729 /* The second byte after 0x62. */
11731 vex
.w
= *codep
& 0x80;
11732 if (vex
.w
&& address_mode
== mode_64bit
)
11735 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11738 if (!(*codep
& 0x4))
11739 return &bad_opcode
;
11741 switch ((*codep
& 0x3))
11746 vex
.prefix
= DATA_PREFIX_OPCODE
;
11749 vex
.prefix
= REPE_PREFIX_OPCODE
;
11752 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11756 /* The third byte after 0x62. */
11759 /* Remember the static rounding bits. */
11760 vex
.ll
= (*codep
>> 5) & 3;
11761 vex
.b
= (*codep
& 0x10) != 0;
11763 vex
.v
= *codep
& 0x8;
11764 vex
.mask_register_specifier
= *codep
& 0x7;
11765 vex
.zeroing
= *codep
& 0x80;
11767 if (address_mode
!= mode_64bit
)
11769 /* In 16/32-bit mode silently ignore following bits. */
11779 dp
= &evex_table
[vex_table_index
][vindex
];
11781 FETCH_DATA (info
, codep
+ 1);
11782 modrm
.mod
= (*codep
>> 6) & 3;
11783 modrm
.reg
= (*codep
>> 3) & 7;
11784 modrm
.rm
= *codep
& 7;
11786 /* Set vector length. */
11787 if (modrm
.mod
== 3 && vex
.b
)
11803 return &bad_opcode
;
11816 if (dp
->name
!= NULL
)
11819 return get_valid_dis386 (dp
, info
);
11823 get_sib (disassemble_info
*info
, int sizeflag
)
11825 /* If modrm.mod == 3, operand must be register. */
11827 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11831 FETCH_DATA (info
, codep
+ 2);
11832 sib
.index
= (codep
[1] >> 3) & 7;
11833 sib
.scale
= (codep
[1] >> 6) & 3;
11834 sib
.base
= codep
[1] & 7;
11839 print_insn (bfd_vma pc
, disassemble_info
*info
)
11841 const struct dis386
*dp
;
11843 char *op_txt
[MAX_OPERANDS
];
11845 int sizeflag
, orig_sizeflag
;
11847 struct dis_private priv
;
11850 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11851 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11852 address_mode
= mode_32bit
;
11853 else if (info
->mach
== bfd_mach_i386_i8086
)
11855 address_mode
= mode_16bit
;
11856 priv
.orig_sizeflag
= 0;
11859 address_mode
= mode_64bit
;
11861 if (intel_syntax
== (char) -1)
11862 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11864 for (p
= info
->disassembler_options
; p
!= NULL
; )
11866 if (CONST_STRNEQ (p
, "amd64"))
11868 else if (CONST_STRNEQ (p
, "intel64"))
11870 else if (CONST_STRNEQ (p
, "x86-64"))
11872 address_mode
= mode_64bit
;
11873 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11875 else if (CONST_STRNEQ (p
, "i386"))
11877 address_mode
= mode_32bit
;
11878 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11880 else if (CONST_STRNEQ (p
, "i8086"))
11882 address_mode
= mode_16bit
;
11883 priv
.orig_sizeflag
= 0;
11885 else if (CONST_STRNEQ (p
, "intel"))
11888 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11889 intel_mnemonic
= 1;
11891 else if (CONST_STRNEQ (p
, "att"))
11894 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11895 intel_mnemonic
= 0;
11897 else if (CONST_STRNEQ (p
, "addr"))
11899 if (address_mode
== mode_64bit
)
11901 if (p
[4] == '3' && p
[5] == '2')
11902 priv
.orig_sizeflag
&= ~AFLAG
;
11903 else if (p
[4] == '6' && p
[5] == '4')
11904 priv
.orig_sizeflag
|= AFLAG
;
11908 if (p
[4] == '1' && p
[5] == '6')
11909 priv
.orig_sizeflag
&= ~AFLAG
;
11910 else if (p
[4] == '3' && p
[5] == '2')
11911 priv
.orig_sizeflag
|= AFLAG
;
11914 else if (CONST_STRNEQ (p
, "data"))
11916 if (p
[4] == '1' && p
[5] == '6')
11917 priv
.orig_sizeflag
&= ~DFLAG
;
11918 else if (p
[4] == '3' && p
[5] == '2')
11919 priv
.orig_sizeflag
|= DFLAG
;
11921 else if (CONST_STRNEQ (p
, "suffix"))
11922 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11924 p
= strchr (p
, ',');
11929 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11931 (*info
->fprintf_func
) (info
->stream
,
11932 _("64-bit address is disabled"));
11938 names64
= intel_names64
;
11939 names32
= intel_names32
;
11940 names16
= intel_names16
;
11941 names8
= intel_names8
;
11942 names8rex
= intel_names8rex
;
11943 names_seg
= intel_names_seg
;
11944 names_mm
= intel_names_mm
;
11945 names_bnd
= intel_names_bnd
;
11946 names_xmm
= intel_names_xmm
;
11947 names_ymm
= intel_names_ymm
;
11948 names_zmm
= intel_names_zmm
;
11949 index64
= intel_index64
;
11950 index32
= intel_index32
;
11951 names_mask
= intel_names_mask
;
11952 index16
= intel_index16
;
11955 separator_char
= '+';
11960 names64
= att_names64
;
11961 names32
= att_names32
;
11962 names16
= att_names16
;
11963 names8
= att_names8
;
11964 names8rex
= att_names8rex
;
11965 names_seg
= att_names_seg
;
11966 names_mm
= att_names_mm
;
11967 names_bnd
= att_names_bnd
;
11968 names_xmm
= att_names_xmm
;
11969 names_ymm
= att_names_ymm
;
11970 names_zmm
= att_names_zmm
;
11971 index64
= att_index64
;
11972 index32
= att_index32
;
11973 names_mask
= att_names_mask
;
11974 index16
= att_index16
;
11977 separator_char
= ',';
11981 /* The output looks better if we put 7 bytes on a line, since that
11982 puts most long word instructions on a single line. Use 8 bytes
11984 if ((info
->mach
& bfd_mach_l1om
) != 0)
11985 info
->bytes_per_line
= 8;
11987 info
->bytes_per_line
= 7;
11989 info
->private_data
= &priv
;
11990 priv
.max_fetched
= priv
.the_buffer
;
11991 priv
.insn_start
= pc
;
11994 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12002 start_codep
= priv
.the_buffer
;
12003 codep
= priv
.the_buffer
;
12005 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12009 /* Getting here means we tried for data but didn't get it. That
12010 means we have an incomplete instruction of some sort. Just
12011 print the first byte as a prefix or a .byte pseudo-op. */
12012 if (codep
> priv
.the_buffer
)
12014 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12016 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12019 /* Just print the first byte as a .byte instruction. */
12020 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12021 (unsigned int) priv
.the_buffer
[0]);
12031 sizeflag
= priv
.orig_sizeflag
;
12033 if (!ckprefix () || rex_used
)
12035 /* Too many prefixes or unused REX prefixes. */
12037 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12039 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12041 prefix_name (all_prefixes
[i
], sizeflag
));
12045 insn_codep
= codep
;
12047 FETCH_DATA (info
, codep
+ 1);
12048 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12050 if (((prefixes
& PREFIX_FWAIT
)
12051 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12053 /* Handle prefixes before fwait. */
12054 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12056 (*info
->fprintf_func
) (info
->stream
, "%s ",
12057 prefix_name (all_prefixes
[i
], sizeflag
));
12058 (*info
->fprintf_func
) (info
->stream
, "fwait");
12062 if (*codep
== 0x0f)
12064 unsigned char threebyte
;
12067 FETCH_DATA (info
, codep
+ 1);
12068 threebyte
= *codep
;
12069 dp
= &dis386_twobyte
[threebyte
];
12070 need_modrm
= twobyte_has_modrm
[*codep
];
12075 dp
= &dis386
[*codep
];
12076 need_modrm
= onebyte_has_modrm
[*codep
];
12080 /* Save sizeflag for printing the extra prefixes later before updating
12081 it for mnemonic and operand processing. The prefix names depend
12082 only on the address mode. */
12083 orig_sizeflag
= sizeflag
;
12084 if (prefixes
& PREFIX_ADDR
)
12086 if ((prefixes
& PREFIX_DATA
))
12092 FETCH_DATA (info
, codep
+ 1);
12093 modrm
.mod
= (*codep
>> 6) & 3;
12094 modrm
.reg
= (*codep
>> 3) & 7;
12095 modrm
.rm
= *codep
& 7;
12101 memset (&vex
, 0, sizeof (vex
));
12103 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12105 get_sib (info
, sizeflag
);
12106 dofloat (sizeflag
);
12110 dp
= get_valid_dis386 (dp
, info
);
12111 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12113 get_sib (info
, sizeflag
);
12114 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12117 op_ad
= MAX_OPERANDS
- 1 - i
;
12119 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12120 /* For EVEX instruction after the last operand masking
12121 should be printed. */
12122 if (i
== 0 && vex
.evex
)
12124 /* Don't print {%k0}. */
12125 if (vex
.mask_register_specifier
)
12128 oappend (names_mask
[vex
.mask_register_specifier
]);
12138 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12139 are all 0s in inverted form. */
12140 if (need_vex
&& vex
.register_specifier
!= 0)
12142 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12143 return end_codep
- priv
.the_buffer
;
12146 /* Check if the REX prefix is used. */
12147 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12148 all_prefixes
[last_rex_prefix
] = 0;
12150 /* Check if the SEG prefix is used. */
12151 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12152 | PREFIX_FS
| PREFIX_GS
)) != 0
12153 && (used_prefixes
& active_seg_prefix
) != 0)
12154 all_prefixes
[last_seg_prefix
] = 0;
12156 /* Check if the ADDR prefix is used. */
12157 if ((prefixes
& PREFIX_ADDR
) != 0
12158 && (used_prefixes
& PREFIX_ADDR
) != 0)
12159 all_prefixes
[last_addr_prefix
] = 0;
12161 /* Check if the DATA prefix is used. */
12162 if ((prefixes
& PREFIX_DATA
) != 0
12163 && (used_prefixes
& PREFIX_DATA
) != 0)
12164 all_prefixes
[last_data_prefix
] = 0;
12166 /* Print the extra prefixes. */
12168 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12169 if (all_prefixes
[i
])
12172 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12175 prefix_length
+= strlen (name
) + 1;
12176 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12179 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12180 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12181 used by putop and MMX/SSE operand and may be overriden by the
12182 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12184 if (dp
->prefix_requirement
== PREFIX_OPCODE
12185 && dp
!= &bad_opcode
12187 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12189 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12191 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12193 && (used_prefixes
& PREFIX_DATA
) == 0))))
12195 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12196 return end_codep
- priv
.the_buffer
;
12199 /* Check maximum code length. */
12200 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12202 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12203 return MAX_CODE_LENGTH
;
12206 obufp
= mnemonicendp
;
12207 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12210 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12212 /* The enter and bound instructions are printed with operands in the same
12213 order as the intel book; everything else is printed in reverse order. */
12214 if (intel_syntax
|| two_source_ops
)
12218 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12219 op_txt
[i
] = op_out
[i
];
12221 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12222 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12224 op_txt
[2] = op_out
[3];
12225 op_txt
[3] = op_out
[2];
12228 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12230 op_ad
= op_index
[i
];
12231 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12232 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12233 riprel
= op_riprel
[i
];
12234 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12235 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12240 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12241 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12245 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12249 (*info
->fprintf_func
) (info
->stream
, ",");
12250 if (op_index
[i
] != -1 && !op_riprel
[i
])
12251 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12253 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12257 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12258 if (op_index
[i
] != -1 && op_riprel
[i
])
12260 (*info
->fprintf_func
) (info
->stream
, " # ");
12261 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12262 + op_address
[op_index
[i
]]), info
);
12265 return codep
- priv
.the_buffer
;
12268 static const char *float_mem
[] = {
12343 static const unsigned char float_mem_mode
[] = {
12418 #define ST { OP_ST, 0 }
12419 #define STi { OP_STi, 0 }
12421 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12422 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12423 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12424 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12425 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12426 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12427 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12428 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12429 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12431 static const struct dis386 float_reg
[][8] = {
12434 { "fadd", { ST
, STi
}, 0 },
12435 { "fmul", { ST
, STi
}, 0 },
12436 { "fcom", { STi
}, 0 },
12437 { "fcomp", { STi
}, 0 },
12438 { "fsub", { ST
, STi
}, 0 },
12439 { "fsubr", { ST
, STi
}, 0 },
12440 { "fdiv", { ST
, STi
}, 0 },
12441 { "fdivr", { ST
, STi
}, 0 },
12445 { "fld", { STi
}, 0 },
12446 { "fxch", { STi
}, 0 },
12456 { "fcmovb", { ST
, STi
}, 0 },
12457 { "fcmove", { ST
, STi
}, 0 },
12458 { "fcmovbe",{ ST
, STi
}, 0 },
12459 { "fcmovu", { ST
, STi
}, 0 },
12467 { "fcmovnb",{ ST
, STi
}, 0 },
12468 { "fcmovne",{ ST
, STi
}, 0 },
12469 { "fcmovnbe",{ ST
, STi
}, 0 },
12470 { "fcmovnu",{ ST
, STi
}, 0 },
12472 { "fucomi", { ST
, STi
}, 0 },
12473 { "fcomi", { ST
, STi
}, 0 },
12478 { "fadd", { STi
, ST
}, 0 },
12479 { "fmul", { STi
, ST
}, 0 },
12482 { "fsub{!M|r}", { STi
, ST
}, 0 },
12483 { "fsub{M|}", { STi
, ST
}, 0 },
12484 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12485 { "fdiv{M|}", { STi
, ST
}, 0 },
12489 { "ffree", { STi
}, 0 },
12491 { "fst", { STi
}, 0 },
12492 { "fstp", { STi
}, 0 },
12493 { "fucom", { STi
}, 0 },
12494 { "fucomp", { STi
}, 0 },
12500 { "faddp", { STi
, ST
}, 0 },
12501 { "fmulp", { STi
, ST
}, 0 },
12504 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12505 { "fsub{M|}p", { STi
, ST
}, 0 },
12506 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12507 { "fdiv{M|}p", { STi
, ST
}, 0 },
12511 { "ffreep", { STi
}, 0 },
12516 { "fucomip", { ST
, STi
}, 0 },
12517 { "fcomip", { ST
, STi
}, 0 },
12522 static char *fgrps
[][8] = {
12525 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12530 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12535 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12540 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12545 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12550 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12555 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12560 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12561 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12566 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12571 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12576 swap_operand (void)
12578 mnemonicendp
[0] = '.';
12579 mnemonicendp
[1] = 's';
12584 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12585 int sizeflag ATTRIBUTE_UNUSED
)
12587 /* Skip mod/rm byte. */
12593 dofloat (int sizeflag
)
12595 const struct dis386
*dp
;
12596 unsigned char floatop
;
12598 floatop
= codep
[-1];
12600 if (modrm
.mod
!= 3)
12602 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12604 putop (float_mem
[fp_indx
], sizeflag
);
12607 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12610 /* Skip mod/rm byte. */
12614 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12615 if (dp
->name
== NULL
)
12617 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12619 /* Instruction fnstsw is only one with strange arg. */
12620 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12621 strcpy (op_out
[0], names16
[0]);
12625 putop (dp
->name
, sizeflag
);
12630 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12635 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12639 /* Like oappend (below), but S is a string starting with '%'.
12640 In Intel syntax, the '%' is elided. */
12642 oappend_maybe_intel (const char *s
)
12644 oappend (s
+ intel_syntax
);
12648 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12650 oappend_maybe_intel ("%st");
12654 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12656 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12657 oappend_maybe_intel (scratchbuf
);
12660 /* Capital letters in template are macros. */
12662 putop (const char *in_template
, int sizeflag
)
12667 unsigned int l
= 0, len
= 1;
12670 #define SAVE_LAST(c) \
12671 if (l < len && l < sizeof (last)) \
12676 for (p
= in_template
; *p
; p
++)
12692 while (*++p
!= '|')
12693 if (*p
== '}' || *p
== '\0')
12696 /* Fall through. */
12701 while (*++p
!= '}')
12712 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12716 if (l
== 0 && len
== 1)
12721 if (sizeflag
& SUFFIX_ALWAYS
)
12734 if (address_mode
== mode_64bit
12735 && !(prefixes
& PREFIX_ADDR
))
12746 if (intel_syntax
&& !alt
)
12748 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12750 if (sizeflag
& DFLAG
)
12751 *obufp
++ = intel_syntax
? 'd' : 'l';
12753 *obufp
++ = intel_syntax
? 'w' : 's';
12754 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12758 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12761 if (modrm
.mod
== 3)
12767 if (sizeflag
& DFLAG
)
12768 *obufp
++ = intel_syntax
? 'd' : 'l';
12771 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12777 case 'E': /* For jcxz/jecxz */
12778 if (address_mode
== mode_64bit
)
12780 if (sizeflag
& AFLAG
)
12786 if (sizeflag
& AFLAG
)
12788 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12793 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12795 if (sizeflag
& AFLAG
)
12796 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12798 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12799 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12803 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12805 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12809 if (!(rex
& REX_W
))
12810 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12815 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12816 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12818 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12821 if (prefixes
& PREFIX_DS
)
12840 if (l
!= 0 || len
!= 1)
12842 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12847 if (!need_vex
|| !vex
.evex
)
12850 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12852 switch (vex
.length
)
12870 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12875 /* Fall through. */
12878 if (l
!= 0 || len
!= 1)
12886 if (sizeflag
& SUFFIX_ALWAYS
)
12890 if (intel_mnemonic
!= cond
)
12894 if ((prefixes
& PREFIX_FWAIT
) == 0)
12897 used_prefixes
|= PREFIX_FWAIT
;
12903 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12907 if (!(rex
& REX_W
))
12908 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12912 && address_mode
== mode_64bit
12913 && isa64
== intel64
)
12918 /* Fall through. */
12921 && address_mode
== mode_64bit
12922 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12927 /* Fall through. */
12930 if (l
== 0 && len
== 1)
12935 if ((rex
& REX_W
) == 0
12936 && (prefixes
& PREFIX_DATA
))
12938 if ((sizeflag
& DFLAG
) == 0)
12940 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12944 if ((prefixes
& PREFIX_DATA
)
12946 || (sizeflag
& SUFFIX_ALWAYS
))
12953 if (sizeflag
& DFLAG
)
12957 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12963 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12969 if ((prefixes
& PREFIX_DATA
)
12971 || (sizeflag
& SUFFIX_ALWAYS
))
12978 if (sizeflag
& DFLAG
)
12979 *obufp
++ = intel_syntax
? 'd' : 'l';
12982 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12990 if (address_mode
== mode_64bit
12991 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12993 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12997 /* Fall through. */
13000 if (l
== 0 && len
== 1)
13003 if (intel_syntax
&& !alt
)
13006 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13012 if (sizeflag
& DFLAG
)
13013 *obufp
++ = intel_syntax
? 'd' : 'l';
13016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13022 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13028 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13043 else if (sizeflag
& DFLAG
)
13052 if (intel_syntax
&& !p
[1]
13053 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13055 if (!(rex
& REX_W
))
13056 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13059 if (l
== 0 && len
== 1)
13063 if (address_mode
== mode_64bit
13064 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13066 if (sizeflag
& SUFFIX_ALWAYS
)
13088 /* Fall through. */
13091 if (l
== 0 && len
== 1)
13096 if (sizeflag
& SUFFIX_ALWAYS
)
13102 if (sizeflag
& DFLAG
)
13106 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13120 if (address_mode
== mode_64bit
13121 && !(prefixes
& PREFIX_ADDR
))
13132 if (l
!= 0 || len
!= 1)
13137 if (need_vex
&& vex
.prefix
)
13139 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13146 if (prefixes
& PREFIX_DATA
)
13150 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13154 if (l
== 0 && len
== 1)
13158 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13166 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13168 switch (vex
.length
)
13184 if (l
== 0 && len
== 1)
13186 /* operand size flag for cwtl, cbtw */
13195 else if (sizeflag
& DFLAG
)
13199 if (!(rex
& REX_W
))
13200 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13207 && last
[0] != 'L'))
13214 if (last
[0] == 'X')
13215 *obufp
++ = vex
.w
? 'd': 's';
13217 *obufp
++ = vex
.w
? 'q': 'd';
13223 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13225 if (sizeflag
& DFLAG
)
13229 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13235 if (address_mode
== mode_64bit
13236 && (isa64
== intel64
13237 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13239 else if ((prefixes
& PREFIX_DATA
))
13241 if (!(sizeflag
& DFLAG
))
13243 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13250 mnemonicendp
= obufp
;
13255 oappend (const char *s
)
13257 obufp
= stpcpy (obufp
, s
);
13263 /* Only print the active segment register. */
13264 if (!active_seg_prefix
)
13267 used_prefixes
|= active_seg_prefix
;
13268 switch (active_seg_prefix
)
13271 oappend_maybe_intel ("%cs:");
13274 oappend_maybe_intel ("%ds:");
13277 oappend_maybe_intel ("%ss:");
13280 oappend_maybe_intel ("%es:");
13283 oappend_maybe_intel ("%fs:");
13286 oappend_maybe_intel ("%gs:");
13294 OP_indirE (int bytemode
, int sizeflag
)
13298 OP_E (bytemode
, sizeflag
);
13302 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13304 if (address_mode
== mode_64bit
)
13312 sprintf_vma (tmp
, disp
);
13313 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13314 strcpy (buf
+ 2, tmp
+ i
);
13318 bfd_signed_vma v
= disp
;
13325 /* Check for possible overflow on 0x8000000000000000. */
13328 strcpy (buf
, "9223372036854775808");
13342 tmp
[28 - i
] = (v
% 10) + '0';
13346 strcpy (buf
, tmp
+ 29 - i
);
13352 sprintf (buf
, "0x%x", (unsigned int) disp
);
13354 sprintf (buf
, "%d", (int) disp
);
13358 /* Put DISP in BUF as signed hex number. */
13361 print_displacement (char *buf
, bfd_vma disp
)
13363 bfd_signed_vma val
= disp
;
13372 /* Check for possible overflow. */
13375 switch (address_mode
)
13378 strcpy (buf
+ j
, "0x8000000000000000");
13381 strcpy (buf
+ j
, "0x80000000");
13384 strcpy (buf
+ j
, "0x8000");
13394 sprintf_vma (tmp
, (bfd_vma
) val
);
13395 for (i
= 0; tmp
[i
] == '0'; i
++)
13397 if (tmp
[i
] == '\0')
13399 strcpy (buf
+ j
, tmp
+ i
);
13403 intel_operand_size (int bytemode
, int sizeflag
)
13407 && (bytemode
== x_mode
13408 || bytemode
== evex_half_bcst_xmmq_mode
))
13411 oappend ("QWORD PTR ");
13413 oappend ("DWORD PTR ");
13422 oappend ("BYTE PTR ");
13427 oappend ("WORD PTR ");
13430 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13432 oappend ("QWORD PTR ");
13435 /* Fall through. */
13437 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13439 oappend ("QWORD PTR ");
13442 /* Fall through. */
13448 oappend ("QWORD PTR ");
13451 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13452 oappend ("DWORD PTR ");
13454 oappend ("WORD PTR ");
13455 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13459 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13461 oappend ("WORD PTR ");
13462 if (!(rex
& REX_W
))
13463 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13466 if (sizeflag
& DFLAG
)
13467 oappend ("QWORD PTR ");
13469 oappend ("DWORD PTR ");
13470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13473 case d_scalar_mode
:
13474 case d_scalar_swap_mode
:
13477 oappend ("DWORD PTR ");
13480 case q_scalar_mode
:
13481 case q_scalar_swap_mode
:
13483 oappend ("QWORD PTR ");
13486 if (address_mode
== mode_64bit
)
13487 oappend ("QWORD PTR ");
13489 oappend ("DWORD PTR ");
13492 if (sizeflag
& DFLAG
)
13493 oappend ("FWORD PTR ");
13495 oappend ("DWORD PTR ");
13496 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13499 oappend ("TBYTE PTR ");
13503 case evex_x_gscat_mode
:
13504 case evex_x_nobcst_mode
:
13505 case b_scalar_mode
:
13506 case w_scalar_mode
:
13509 switch (vex
.length
)
13512 oappend ("XMMWORD PTR ");
13515 oappend ("YMMWORD PTR ");
13518 oappend ("ZMMWORD PTR ");
13525 oappend ("XMMWORD PTR ");
13528 oappend ("XMMWORD PTR ");
13531 oappend ("YMMWORD PTR ");
13534 case evex_half_bcst_xmmq_mode
:
13538 switch (vex
.length
)
13541 oappend ("QWORD PTR ");
13544 oappend ("XMMWORD PTR ");
13547 oappend ("YMMWORD PTR ");
13557 switch (vex
.length
)
13562 oappend ("BYTE PTR ");
13572 switch (vex
.length
)
13577 oappend ("WORD PTR ");
13587 switch (vex
.length
)
13592 oappend ("DWORD PTR ");
13602 switch (vex
.length
)
13607 oappend ("QWORD PTR ");
13617 switch (vex
.length
)
13620 oappend ("WORD PTR ");
13623 oappend ("DWORD PTR ");
13626 oappend ("QWORD PTR ");
13636 switch (vex
.length
)
13639 oappend ("DWORD PTR ");
13642 oappend ("QWORD PTR ");
13645 oappend ("XMMWORD PTR ");
13655 switch (vex
.length
)
13658 oappend ("QWORD PTR ");
13661 oappend ("YMMWORD PTR ");
13664 oappend ("ZMMWORD PTR ");
13674 switch (vex
.length
)
13678 oappend ("XMMWORD PTR ");
13685 oappend ("OWORD PTR ");
13688 case vex_w_dq_mode
:
13689 case vex_scalar_w_dq_mode
:
13694 oappend ("QWORD PTR ");
13696 oappend ("DWORD PTR ");
13698 case vex_vsib_d_w_dq_mode
:
13699 case vex_vsib_q_w_dq_mode
:
13706 oappend ("QWORD PTR ");
13708 oappend ("DWORD PTR ");
13712 switch (vex
.length
)
13715 oappend ("XMMWORD PTR ");
13718 oappend ("YMMWORD PTR ");
13721 oappend ("ZMMWORD PTR ");
13728 case vex_vsib_q_w_d_mode
:
13729 case vex_vsib_d_w_d_mode
:
13730 if (!need_vex
|| !vex
.evex
)
13733 switch (vex
.length
)
13736 oappend ("QWORD PTR ");
13739 oappend ("XMMWORD PTR ");
13742 oappend ("YMMWORD PTR ");
13750 if (!need_vex
|| vex
.length
!= 128)
13753 oappend ("DWORD PTR ");
13755 oappend ("BYTE PTR ");
13761 oappend ("QWORD PTR ");
13763 oappend ("WORD PTR ");
13773 OP_E_register (int bytemode
, int sizeflag
)
13775 int reg
= modrm
.rm
;
13776 const char **names
;
13782 if ((sizeflag
& SUFFIX_ALWAYS
)
13783 && (bytemode
== b_swap_mode
13784 || bytemode
== bnd_swap_mode
13785 || bytemode
== v_swap_mode
))
13811 names
= address_mode
== mode_64bit
? names64
: names32
;
13814 case bnd_swap_mode
:
13823 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13828 /* Fall through. */
13830 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13836 /* Fall through. */
13848 if ((sizeflag
& DFLAG
)
13849 || (bytemode
!= v_mode
13850 && bytemode
!= v_swap_mode
))
13854 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13858 names
= (address_mode
== mode_64bit
13859 ? names64
: names32
);
13860 if (!(prefixes
& PREFIX_ADDR
))
13861 names
= (address_mode
== mode_16bit
13862 ? names16
: names
);
13865 /* Remove "addr16/addr32". */
13866 all_prefixes
[last_addr_prefix
] = 0;
13867 names
= (address_mode
!= mode_32bit
13868 ? names32
: names16
);
13869 used_prefixes
|= PREFIX_ADDR
;
13879 names
= names_mask
;
13884 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13887 oappend (names
[reg
]);
13891 OP_E_memory (int bytemode
, int sizeflag
)
13894 int add
= (rex
& REX_B
) ? 8 : 0;
13900 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13902 && bytemode
!= x_mode
13903 && bytemode
!= xmmq_mode
13904 && bytemode
!= evex_half_bcst_xmmq_mode
)
13920 if (address_mode
!= mode_64bit
)
13926 case vex_vsib_d_w_dq_mode
:
13927 case vex_vsib_d_w_d_mode
:
13928 case vex_vsib_q_w_dq_mode
:
13929 case vex_vsib_q_w_d_mode
:
13930 case evex_x_gscat_mode
:
13932 shift
= vex
.w
? 3 : 2;
13935 case evex_half_bcst_xmmq_mode
:
13939 shift
= vex
.w
? 3 : 2;
13942 /* Fall through. */
13946 case evex_x_nobcst_mode
:
13948 switch (vex
.length
)
13971 case q_scalar_mode
:
13973 case q_scalar_swap_mode
:
13979 case d_scalar_mode
:
13981 case d_scalar_swap_mode
:
13984 case w_scalar_mode
:
13988 case b_scalar_mode
:
13995 /* Make necessary corrections to shift for modes that need it.
13996 For these modes we currently have shift 4, 5 or 6 depending on
13997 vex.length (it corresponds to xmmword, ymmword or zmmword
13998 operand). We might want to make it 3, 4 or 5 (e.g. for
13999 xmmq_mode). In case of broadcast enabled the corrections
14000 aren't needed, as element size is always 32 or 64 bits. */
14002 && (bytemode
== xmmq_mode
14003 || bytemode
== evex_half_bcst_xmmq_mode
))
14005 else if (bytemode
== xmmqd_mode
)
14007 else if (bytemode
== xmmdw_mode
)
14009 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14017 intel_operand_size (bytemode
, sizeflag
);
14020 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14022 /* 32/64 bit address mode */
14032 int addr32flag
= !((sizeflag
& AFLAG
)
14033 || bytemode
== v_bnd_mode
14034 || bytemode
== v_bndmk_mode
14035 || bytemode
== bnd_mode
14036 || bytemode
== bnd_swap_mode
);
14037 const char **indexes64
= names64
;
14038 const char **indexes32
= names32
;
14048 vindex
= sib
.index
;
14054 case vex_vsib_d_w_dq_mode
:
14055 case vex_vsib_d_w_d_mode
:
14056 case vex_vsib_q_w_dq_mode
:
14057 case vex_vsib_q_w_d_mode
:
14067 switch (vex
.length
)
14070 indexes64
= indexes32
= names_xmm
;
14074 || bytemode
== vex_vsib_q_w_dq_mode
14075 || bytemode
== vex_vsib_q_w_d_mode
)
14076 indexes64
= indexes32
= names_ymm
;
14078 indexes64
= indexes32
= names_xmm
;
14082 || bytemode
== vex_vsib_q_w_dq_mode
14083 || bytemode
== vex_vsib_q_w_d_mode
)
14084 indexes64
= indexes32
= names_zmm
;
14086 indexes64
= indexes32
= names_ymm
;
14093 haveindex
= vindex
!= 4;
14100 rbase
= base
+ add
;
14108 if (address_mode
== mode_64bit
&& !havesib
)
14111 if (riprel
&& bytemode
== v_bndmk_mode
)
14119 FETCH_DATA (the_info
, codep
+ 1);
14121 if ((disp
& 0x80) != 0)
14123 if (vex
.evex
&& shift
> 0)
14136 && address_mode
!= mode_16bit
)
14138 if (address_mode
== mode_64bit
)
14140 /* Display eiz instead of addr32. */
14141 needindex
= addr32flag
;
14146 /* In 32-bit mode, we need index register to tell [offset]
14147 from [eiz*1 + offset]. */
14152 havedisp
= (havebase
14154 || (havesib
&& (haveindex
|| scale
!= 0)));
14157 if (modrm
.mod
!= 0 || base
== 5)
14159 if (havedisp
|| riprel
)
14160 print_displacement (scratchbuf
, disp
);
14162 print_operand_value (scratchbuf
, 1, disp
);
14163 oappend (scratchbuf
);
14167 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14171 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14172 && (bytemode
!= v_bnd_mode
)
14173 && (bytemode
!= v_bndmk_mode
)
14174 && (bytemode
!= bnd_mode
)
14175 && (bytemode
!= bnd_swap_mode
))
14176 used_prefixes
|= PREFIX_ADDR
;
14178 if (havedisp
|| (intel_syntax
&& riprel
))
14180 *obufp
++ = open_char
;
14181 if (intel_syntax
&& riprel
)
14184 oappend (!addr32flag
? "rip" : "eip");
14188 oappend (address_mode
== mode_64bit
&& !addr32flag
14189 ? names64
[rbase
] : names32
[rbase
]);
14192 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14193 print index to tell base + index from base. */
14197 || (havebase
&& base
!= ESP_REG_NUM
))
14199 if (!intel_syntax
|| havebase
)
14201 *obufp
++ = separator_char
;
14205 oappend (address_mode
== mode_64bit
&& !addr32flag
14206 ? indexes64
[vindex
] : indexes32
[vindex
]);
14208 oappend (address_mode
== mode_64bit
&& !addr32flag
14209 ? index64
: index32
);
14211 *obufp
++ = scale_char
;
14213 sprintf (scratchbuf
, "%d", 1 << scale
);
14214 oappend (scratchbuf
);
14218 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14220 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14225 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14229 disp
= - (bfd_signed_vma
) disp
;
14233 print_displacement (scratchbuf
, disp
);
14235 print_operand_value (scratchbuf
, 1, disp
);
14236 oappend (scratchbuf
);
14239 *obufp
++ = close_char
;
14242 else if (intel_syntax
)
14244 if (modrm
.mod
!= 0 || base
== 5)
14246 if (!active_seg_prefix
)
14248 oappend (names_seg
[ds_reg
- es_reg
]);
14251 print_operand_value (scratchbuf
, 1, disp
);
14252 oappend (scratchbuf
);
14258 /* 16 bit address mode */
14259 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14266 if ((disp
& 0x8000) != 0)
14271 FETCH_DATA (the_info
, codep
+ 1);
14273 if ((disp
& 0x80) != 0)
14275 if (vex
.evex
&& shift
> 0)
14280 if ((disp
& 0x8000) != 0)
14286 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14288 print_displacement (scratchbuf
, disp
);
14289 oappend (scratchbuf
);
14292 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14294 *obufp
++ = open_char
;
14296 oappend (index16
[modrm
.rm
]);
14298 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14300 if ((bfd_signed_vma
) disp
>= 0)
14305 else if (modrm
.mod
!= 1)
14309 disp
= - (bfd_signed_vma
) disp
;
14312 print_displacement (scratchbuf
, disp
);
14313 oappend (scratchbuf
);
14316 *obufp
++ = close_char
;
14319 else if (intel_syntax
)
14321 if (!active_seg_prefix
)
14323 oappend (names_seg
[ds_reg
- es_reg
]);
14326 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14327 oappend (scratchbuf
);
14330 if (vex
.evex
&& vex
.b
14331 && (bytemode
== x_mode
14332 || bytemode
== xmmq_mode
14333 || bytemode
== evex_half_bcst_xmmq_mode
))
14336 || bytemode
== xmmq_mode
14337 || bytemode
== evex_half_bcst_xmmq_mode
)
14339 switch (vex
.length
)
14342 oappend ("{1to2}");
14345 oappend ("{1to4}");
14348 oappend ("{1to8}");
14356 switch (vex
.length
)
14359 oappend ("{1to4}");
14362 oappend ("{1to8}");
14365 oappend ("{1to16}");
14375 OP_E (int bytemode
, int sizeflag
)
14377 /* Skip mod/rm byte. */
14381 if (modrm
.mod
== 3)
14382 OP_E_register (bytemode
, sizeflag
);
14384 OP_E_memory (bytemode
, sizeflag
);
14388 OP_G (int bytemode
, int sizeflag
)
14391 const char **names
;
14400 oappend (names8rex
[modrm
.reg
+ add
]);
14402 oappend (names8
[modrm
.reg
+ add
]);
14405 oappend (names16
[modrm
.reg
+ add
]);
14410 oappend (names32
[modrm
.reg
+ add
]);
14413 oappend (names64
[modrm
.reg
+ add
]);
14416 if (modrm
.reg
> 0x3)
14421 oappend (names_bnd
[modrm
.reg
]);
14430 oappend (names64
[modrm
.reg
+ add
]);
14433 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14434 oappend (names32
[modrm
.reg
+ add
]);
14436 oappend (names16
[modrm
.reg
+ add
]);
14437 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14441 names
= (address_mode
== mode_64bit
14442 ? names64
: names32
);
14443 if (!(prefixes
& PREFIX_ADDR
))
14445 if (address_mode
== mode_16bit
)
14450 /* Remove "addr16/addr32". */
14451 all_prefixes
[last_addr_prefix
] = 0;
14452 names
= (address_mode
!= mode_32bit
14453 ? names32
: names16
);
14454 used_prefixes
|= PREFIX_ADDR
;
14456 oappend (names
[modrm
.reg
+ add
]);
14459 if (address_mode
== mode_64bit
)
14460 oappend (names64
[modrm
.reg
+ add
]);
14462 oappend (names32
[modrm
.reg
+ add
]);
14466 if ((modrm
.reg
+ add
) > 0x7)
14471 oappend (names_mask
[modrm
.reg
+ add
]);
14474 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14487 FETCH_DATA (the_info
, codep
+ 8);
14488 a
= *codep
++ & 0xff;
14489 a
|= (*codep
++ & 0xff) << 8;
14490 a
|= (*codep
++ & 0xff) << 16;
14491 a
|= (*codep
++ & 0xffu
) << 24;
14492 b
= *codep
++ & 0xff;
14493 b
|= (*codep
++ & 0xff) << 8;
14494 b
|= (*codep
++ & 0xff) << 16;
14495 b
|= (*codep
++ & 0xffu
) << 24;
14496 x
= a
+ ((bfd_vma
) b
<< 32);
14504 static bfd_signed_vma
14507 bfd_signed_vma x
= 0;
14509 FETCH_DATA (the_info
, codep
+ 4);
14510 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14511 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14512 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14513 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14517 static bfd_signed_vma
14520 bfd_signed_vma x
= 0;
14522 FETCH_DATA (the_info
, codep
+ 4);
14523 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14524 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14525 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14526 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14528 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14538 FETCH_DATA (the_info
, codep
+ 2);
14539 x
= *codep
++ & 0xff;
14540 x
|= (*codep
++ & 0xff) << 8;
14545 set_op (bfd_vma op
, int riprel
)
14547 op_index
[op_ad
] = op_ad
;
14548 if (address_mode
== mode_64bit
)
14550 op_address
[op_ad
] = op
;
14551 op_riprel
[op_ad
] = riprel
;
14555 /* Mask to get a 32-bit address. */
14556 op_address
[op_ad
] = op
& 0xffffffff;
14557 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14562 OP_REG (int code
, int sizeflag
)
14569 case es_reg
: case ss_reg
: case cs_reg
:
14570 case ds_reg
: case fs_reg
: case gs_reg
:
14571 oappend (names_seg
[code
- es_reg
]);
14583 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14584 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14585 s
= names16
[code
- ax_reg
+ add
];
14587 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14588 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14591 s
= names8rex
[code
- al_reg
+ add
];
14593 s
= names8
[code
- al_reg
];
14595 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14596 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14597 if (address_mode
== mode_64bit
14598 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14600 s
= names64
[code
- rAX_reg
+ add
];
14603 code
+= eAX_reg
- rAX_reg
;
14604 /* Fall through. */
14605 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14606 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14609 s
= names64
[code
- eAX_reg
+ add
];
14612 if (sizeflag
& DFLAG
)
14613 s
= names32
[code
- eAX_reg
+ add
];
14615 s
= names16
[code
- eAX_reg
+ add
];
14616 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14620 s
= INTERNAL_DISASSEMBLER_ERROR
;
14627 OP_IMREG (int code
, int sizeflag
)
14639 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14640 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14641 s
= names16
[code
- ax_reg
];
14643 case es_reg
: case ss_reg
: case cs_reg
:
14644 case ds_reg
: case fs_reg
: case gs_reg
:
14645 s
= names_seg
[code
- es_reg
];
14647 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14648 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14651 s
= names8rex
[code
- al_reg
];
14653 s
= names8
[code
- al_reg
];
14655 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14656 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14659 s
= names64
[code
- eAX_reg
];
14662 if (sizeflag
& DFLAG
)
14663 s
= names32
[code
- eAX_reg
];
14665 s
= names16
[code
- eAX_reg
];
14666 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14669 case z_mode_ax_reg
:
14670 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14674 if (!(rex
& REX_W
))
14675 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14678 s
= INTERNAL_DISASSEMBLER_ERROR
;
14685 OP_I (int bytemode
, int sizeflag
)
14688 bfd_signed_vma mask
= -1;
14693 FETCH_DATA (the_info
, codep
+ 1);
14703 if (sizeflag
& DFLAG
)
14713 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14729 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14734 scratchbuf
[0] = '$';
14735 print_operand_value (scratchbuf
+ 1, 1, op
);
14736 oappend_maybe_intel (scratchbuf
);
14737 scratchbuf
[0] = '\0';
14741 OP_I64 (int bytemode
, int sizeflag
)
14743 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14745 OP_I (bytemode
, sizeflag
);
14751 scratchbuf
[0] = '$';
14752 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14753 oappend_maybe_intel (scratchbuf
);
14754 scratchbuf
[0] = '\0';
14758 OP_sI (int bytemode
, int sizeflag
)
14766 FETCH_DATA (the_info
, codep
+ 1);
14768 if ((op
& 0x80) != 0)
14770 if (bytemode
== b_T_mode
)
14772 if (address_mode
!= mode_64bit
14773 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14775 /* The operand-size prefix is overridden by a REX prefix. */
14776 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14784 if (!(rex
& REX_W
))
14786 if (sizeflag
& DFLAG
)
14794 /* The operand-size prefix is overridden by a REX prefix. */
14795 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14801 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14805 scratchbuf
[0] = '$';
14806 print_operand_value (scratchbuf
+ 1, 1, op
);
14807 oappend_maybe_intel (scratchbuf
);
14811 OP_J (int bytemode
, int sizeflag
)
14815 bfd_vma segment
= 0;
14820 FETCH_DATA (the_info
, codep
+ 1);
14822 if ((disp
& 0x80) != 0)
14826 if (isa64
== amd64
)
14828 if ((sizeflag
& DFLAG
)
14829 || (address_mode
== mode_64bit
14830 && (isa64
!= amd64
|| (rex
& REX_W
))))
14835 if ((disp
& 0x8000) != 0)
14837 /* In 16bit mode, address is wrapped around at 64k within
14838 the same segment. Otherwise, a data16 prefix on a jump
14839 instruction means that the pc is masked to 16 bits after
14840 the displacement is added! */
14842 if ((prefixes
& PREFIX_DATA
) == 0)
14843 segment
= ((start_pc
+ (codep
- start_codep
))
14844 & ~((bfd_vma
) 0xffff));
14846 if (address_mode
!= mode_64bit
14847 || (isa64
== amd64
&& !(rex
& REX_W
)))
14848 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14851 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14854 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14856 print_operand_value (scratchbuf
, 1, disp
);
14857 oappend (scratchbuf
);
14861 OP_SEG (int bytemode
, int sizeflag
)
14863 if (bytemode
== w_mode
)
14864 oappend (names_seg
[modrm
.reg
]);
14866 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14870 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14874 if (sizeflag
& DFLAG
)
14884 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14886 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14888 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14889 oappend (scratchbuf
);
14893 OP_OFF (int bytemode
, int sizeflag
)
14897 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14898 intel_operand_size (bytemode
, sizeflag
);
14901 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14908 if (!active_seg_prefix
)
14910 oappend (names_seg
[ds_reg
- es_reg
]);
14914 print_operand_value (scratchbuf
, 1, off
);
14915 oappend (scratchbuf
);
14919 OP_OFF64 (int bytemode
, int sizeflag
)
14923 if (address_mode
!= mode_64bit
14924 || (prefixes
& PREFIX_ADDR
))
14926 OP_OFF (bytemode
, sizeflag
);
14930 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14931 intel_operand_size (bytemode
, sizeflag
);
14938 if (!active_seg_prefix
)
14940 oappend (names_seg
[ds_reg
- es_reg
]);
14944 print_operand_value (scratchbuf
, 1, off
);
14945 oappend (scratchbuf
);
14949 ptr_reg (int code
, int sizeflag
)
14953 *obufp
++ = open_char
;
14954 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14955 if (address_mode
== mode_64bit
)
14957 if (!(sizeflag
& AFLAG
))
14958 s
= names32
[code
- eAX_reg
];
14960 s
= names64
[code
- eAX_reg
];
14962 else if (sizeflag
& AFLAG
)
14963 s
= names32
[code
- eAX_reg
];
14965 s
= names16
[code
- eAX_reg
];
14967 *obufp
++ = close_char
;
14972 OP_ESreg (int code
, int sizeflag
)
14978 case 0x6d: /* insw/insl */
14979 intel_operand_size (z_mode
, sizeflag
);
14981 case 0xa5: /* movsw/movsl/movsq */
14982 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14983 case 0xab: /* stosw/stosl */
14984 case 0xaf: /* scasw/scasl */
14985 intel_operand_size (v_mode
, sizeflag
);
14988 intel_operand_size (b_mode
, sizeflag
);
14991 oappend_maybe_intel ("%es:");
14992 ptr_reg (code
, sizeflag
);
14996 OP_DSreg (int code
, int sizeflag
)
15002 case 0x6f: /* outsw/outsl */
15003 intel_operand_size (z_mode
, sizeflag
);
15005 case 0xa5: /* movsw/movsl/movsq */
15006 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15007 case 0xad: /* lodsw/lodsl/lodsq */
15008 intel_operand_size (v_mode
, sizeflag
);
15011 intel_operand_size (b_mode
, sizeflag
);
15014 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15015 default segment register DS is printed. */
15016 if (!active_seg_prefix
)
15017 active_seg_prefix
= PREFIX_DS
;
15019 ptr_reg (code
, sizeflag
);
15023 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15031 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15033 all_prefixes
[last_lock_prefix
] = 0;
15034 used_prefixes
|= PREFIX_LOCK
;
15039 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15040 oappend_maybe_intel (scratchbuf
);
15044 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15053 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15055 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15056 oappend (scratchbuf
);
15060 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15062 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15063 oappend_maybe_intel (scratchbuf
);
15067 OP_R (int bytemode
, int sizeflag
)
15069 /* Skip mod/rm byte. */
15072 OP_E_register (bytemode
, sizeflag
);
15076 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15078 int reg
= modrm
.reg
;
15079 const char **names
;
15081 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15082 if (prefixes
& PREFIX_DATA
)
15091 oappend (names
[reg
]);
15095 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15097 int reg
= modrm
.reg
;
15098 const char **names
;
15110 && bytemode
!= xmm_mode
15111 && bytemode
!= xmmq_mode
15112 && bytemode
!= evex_half_bcst_xmmq_mode
15113 && bytemode
!= ymm_mode
15114 && bytemode
!= scalar_mode
)
15116 switch (vex
.length
)
15123 || (bytemode
!= vex_vsib_q_w_dq_mode
15124 && bytemode
!= vex_vsib_q_w_d_mode
))
15136 else if (bytemode
== xmmq_mode
15137 || bytemode
== evex_half_bcst_xmmq_mode
)
15139 switch (vex
.length
)
15152 else if (bytemode
== ymm_mode
)
15156 oappend (names
[reg
]);
15160 OP_EM (int bytemode
, int sizeflag
)
15163 const char **names
;
15165 if (modrm
.mod
!= 3)
15168 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15170 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15171 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15173 OP_E (bytemode
, sizeflag
);
15177 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15180 /* Skip mod/rm byte. */
15183 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15185 if (prefixes
& PREFIX_DATA
)
15194 oappend (names
[reg
]);
15197 /* cvt* are the only instructions in sse2 which have
15198 both SSE and MMX operands and also have 0x66 prefix
15199 in their opcode. 0x66 was originally used to differentiate
15200 between SSE and MMX instruction(operands). So we have to handle the
15201 cvt* separately using OP_EMC and OP_MXC */
15203 OP_EMC (int bytemode
, int sizeflag
)
15205 if (modrm
.mod
!= 3)
15207 if (intel_syntax
&& bytemode
== v_mode
)
15209 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15210 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15212 OP_E (bytemode
, sizeflag
);
15216 /* Skip mod/rm byte. */
15219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15220 oappend (names_mm
[modrm
.rm
]);
15224 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15226 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15227 oappend (names_mm
[modrm
.reg
]);
15231 OP_EX (int bytemode
, int sizeflag
)
15234 const char **names
;
15236 /* Skip mod/rm byte. */
15240 if (modrm
.mod
!= 3)
15242 OP_E_memory (bytemode
, sizeflag
);
15257 if ((sizeflag
& SUFFIX_ALWAYS
)
15258 && (bytemode
== x_swap_mode
15259 || bytemode
== d_swap_mode
15260 || bytemode
== d_scalar_swap_mode
15261 || bytemode
== q_swap_mode
15262 || bytemode
== q_scalar_swap_mode
))
15266 && bytemode
!= xmm_mode
15267 && bytemode
!= xmmdw_mode
15268 && bytemode
!= xmmqd_mode
15269 && bytemode
!= xmm_mb_mode
15270 && bytemode
!= xmm_mw_mode
15271 && bytemode
!= xmm_md_mode
15272 && bytemode
!= xmm_mq_mode
15273 && bytemode
!= xmm_mdq_mode
15274 && bytemode
!= xmmq_mode
15275 && bytemode
!= evex_half_bcst_xmmq_mode
15276 && bytemode
!= ymm_mode
15277 && bytemode
!= d_scalar_mode
15278 && bytemode
!= d_scalar_swap_mode
15279 && bytemode
!= q_scalar_mode
15280 && bytemode
!= q_scalar_swap_mode
15281 && bytemode
!= vex_scalar_w_dq_mode
)
15283 switch (vex
.length
)
15298 else if (bytemode
== xmmq_mode
15299 || bytemode
== evex_half_bcst_xmmq_mode
)
15301 switch (vex
.length
)
15314 else if (bytemode
== ymm_mode
)
15318 oappend (names
[reg
]);
15322 OP_MS (int bytemode
, int sizeflag
)
15324 if (modrm
.mod
== 3)
15325 OP_EM (bytemode
, sizeflag
);
15331 OP_XS (int bytemode
, int sizeflag
)
15333 if (modrm
.mod
== 3)
15334 OP_EX (bytemode
, sizeflag
);
15340 OP_M (int bytemode
, int sizeflag
)
15342 if (modrm
.mod
== 3)
15343 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15346 OP_E (bytemode
, sizeflag
);
15350 OP_0f07 (int bytemode
, int sizeflag
)
15352 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15355 OP_E (bytemode
, sizeflag
);
15358 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15359 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15362 NOP_Fixup1 (int bytemode
, int sizeflag
)
15364 if ((prefixes
& PREFIX_DATA
) != 0
15367 && address_mode
== mode_64bit
))
15368 OP_REG (bytemode
, sizeflag
);
15370 strcpy (obuf
, "nop");
15374 NOP_Fixup2 (int bytemode
, int sizeflag
)
15376 if ((prefixes
& PREFIX_DATA
) != 0
15379 && address_mode
== mode_64bit
))
15380 OP_IMREG (bytemode
, sizeflag
);
15383 static const char *const Suffix3DNow
[] = {
15384 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15385 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15386 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15387 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15388 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15389 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15390 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15391 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15392 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15393 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15394 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15395 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15396 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15397 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15398 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15399 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15400 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15401 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15402 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15403 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15404 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15405 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15406 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15407 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15408 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15409 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15410 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15411 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15412 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15413 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15414 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15415 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15416 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15417 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15418 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15419 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15420 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15421 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15422 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15423 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15424 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15425 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15426 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15427 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15428 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15429 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15430 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15431 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15432 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15433 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15434 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15435 /* CC */ NULL
, NULL
, NULL
, NULL
,
15436 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15437 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15438 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15439 /* DC */ NULL
, NULL
, NULL
, NULL
,
15440 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15441 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15442 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15443 /* EC */ NULL
, NULL
, NULL
, NULL
,
15444 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15445 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15446 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15447 /* FC */ NULL
, NULL
, NULL
, NULL
,
15451 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15453 const char *mnemonic
;
15455 FETCH_DATA (the_info
, codep
+ 1);
15456 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15457 place where an 8-bit immediate would normally go. ie. the last
15458 byte of the instruction. */
15459 obufp
= mnemonicendp
;
15460 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15462 oappend (mnemonic
);
15465 /* Since a variable sized modrm/sib chunk is between the start
15466 of the opcode (0x0f0f) and the opcode suffix, we need to do
15467 all the modrm processing first, and don't know until now that
15468 we have a bad opcode. This necessitates some cleaning up. */
15469 op_out
[0][0] = '\0';
15470 op_out
[1][0] = '\0';
15473 mnemonicendp
= obufp
;
15476 static struct op simd_cmp_op
[] =
15478 { STRING_COMMA_LEN ("eq") },
15479 { STRING_COMMA_LEN ("lt") },
15480 { STRING_COMMA_LEN ("le") },
15481 { STRING_COMMA_LEN ("unord") },
15482 { STRING_COMMA_LEN ("neq") },
15483 { STRING_COMMA_LEN ("nlt") },
15484 { STRING_COMMA_LEN ("nle") },
15485 { STRING_COMMA_LEN ("ord") }
15489 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15491 unsigned int cmp_type
;
15493 FETCH_DATA (the_info
, codep
+ 1);
15494 cmp_type
= *codep
++ & 0xff;
15495 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15498 char *p
= mnemonicendp
- 2;
15502 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15503 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15507 /* We have a reserved extension byte. Output it directly. */
15508 scratchbuf
[0] = '$';
15509 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15510 oappend_maybe_intel (scratchbuf
);
15511 scratchbuf
[0] = '\0';
15516 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
15517 int sizeflag ATTRIBUTE_UNUSED
)
15519 /* mwaitx %eax,%ecx,%ebx */
15522 const char **names
= (address_mode
== mode_64bit
15523 ? names64
: names32
);
15524 strcpy (op_out
[0], names
[0]);
15525 strcpy (op_out
[1], names
[1]);
15526 strcpy (op_out
[2], names
[3]);
15527 two_source_ops
= 1;
15529 /* Skip mod/rm byte. */
15535 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15536 int sizeflag ATTRIBUTE_UNUSED
)
15538 /* mwait %eax,%ecx */
15541 const char **names
= (address_mode
== mode_64bit
15542 ? names64
: names32
);
15543 strcpy (op_out
[0], names
[0]);
15544 strcpy (op_out
[1], names
[1]);
15545 two_source_ops
= 1;
15547 /* Skip mod/rm byte. */
15553 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15554 int sizeflag ATTRIBUTE_UNUSED
)
15556 /* monitor %eax,%ecx,%edx" */
15559 const char **op1_names
;
15560 const char **names
= (address_mode
== mode_64bit
15561 ? names64
: names32
);
15563 if (!(prefixes
& PREFIX_ADDR
))
15564 op1_names
= (address_mode
== mode_16bit
15565 ? names16
: names
);
15568 /* Remove "addr16/addr32". */
15569 all_prefixes
[last_addr_prefix
] = 0;
15570 op1_names
= (address_mode
!= mode_32bit
15571 ? names32
: names16
);
15572 used_prefixes
|= PREFIX_ADDR
;
15574 strcpy (op_out
[0], op1_names
[0]);
15575 strcpy (op_out
[1], names
[1]);
15576 strcpy (op_out
[2], names
[2]);
15577 two_source_ops
= 1;
15579 /* Skip mod/rm byte. */
15587 /* Throw away prefixes and 1st. opcode byte. */
15588 codep
= insn_codep
+ 1;
15593 REP_Fixup (int bytemode
, int sizeflag
)
15595 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15597 if (prefixes
& PREFIX_REPZ
)
15598 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15605 OP_IMREG (bytemode
, sizeflag
);
15608 OP_ESreg (bytemode
, sizeflag
);
15611 OP_DSreg (bytemode
, sizeflag
);
15619 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15623 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15625 if (prefixes
& PREFIX_REPNZ
)
15626 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15629 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15633 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15634 int sizeflag ATTRIBUTE_UNUSED
)
15636 if (active_seg_prefix
== PREFIX_DS
15637 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15639 /* NOTRACK prefix is only valid on indirect branch instructions.
15640 NB: DATA prefix is unsupported for Intel64. */
15641 active_seg_prefix
= 0;
15642 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15646 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15647 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15651 HLE_Fixup1 (int bytemode
, int sizeflag
)
15654 && (prefixes
& PREFIX_LOCK
) != 0)
15656 if (prefixes
& PREFIX_REPZ
)
15657 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15658 if (prefixes
& PREFIX_REPNZ
)
15659 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15662 OP_E (bytemode
, sizeflag
);
15665 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15666 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15670 HLE_Fixup2 (int bytemode
, int sizeflag
)
15672 if (modrm
.mod
!= 3)
15674 if (prefixes
& PREFIX_REPZ
)
15675 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15676 if (prefixes
& PREFIX_REPNZ
)
15677 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15680 OP_E (bytemode
, sizeflag
);
15683 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15684 "xrelease" for memory operand. No check for LOCK prefix. */
15687 HLE_Fixup3 (int bytemode
, int sizeflag
)
15690 && last_repz_prefix
> last_repnz_prefix
15691 && (prefixes
& PREFIX_REPZ
) != 0)
15692 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15694 OP_E (bytemode
, sizeflag
);
15698 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15703 /* Change cmpxchg8b to cmpxchg16b. */
15704 char *p
= mnemonicendp
- 2;
15705 mnemonicendp
= stpcpy (p
, "16b");
15708 else if ((prefixes
& PREFIX_LOCK
) != 0)
15710 if (prefixes
& PREFIX_REPZ
)
15711 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15712 if (prefixes
& PREFIX_REPNZ
)
15713 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15716 OP_M (bytemode
, sizeflag
);
15720 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15722 const char **names
;
15726 switch (vex
.length
)
15740 oappend (names
[reg
]);
15744 CRC32_Fixup (int bytemode
, int sizeflag
)
15746 /* Add proper suffix to "crc32". */
15747 char *p
= mnemonicendp
;
15766 if (sizeflag
& DFLAG
)
15770 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15774 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15781 if (modrm
.mod
== 3)
15785 /* Skip mod/rm byte. */
15790 add
= (rex
& REX_B
) ? 8 : 0;
15791 if (bytemode
== b_mode
)
15795 oappend (names8rex
[modrm
.rm
+ add
]);
15797 oappend (names8
[modrm
.rm
+ add
]);
15803 oappend (names64
[modrm
.rm
+ add
]);
15804 else if ((prefixes
& PREFIX_DATA
))
15805 oappend (names16
[modrm
.rm
+ add
]);
15807 oappend (names32
[modrm
.rm
+ add
]);
15811 OP_E (bytemode
, sizeflag
);
15815 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15817 /* Add proper suffix to "fxsave" and "fxrstor". */
15821 char *p
= mnemonicendp
;
15827 OP_M (bytemode
, sizeflag
);
15831 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15833 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15836 char *p
= mnemonicendp
;
15841 else if (sizeflag
& SUFFIX_ALWAYS
)
15848 OP_EX (bytemode
, sizeflag
);
15851 /* Display the destination register operand for instructions with
15855 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15858 const char **names
;
15866 reg
= vex
.register_specifier
;
15867 vex
.register_specifier
= 0;
15868 if (address_mode
!= mode_64bit
)
15870 else if (vex
.evex
&& !vex
.v
)
15873 if (bytemode
== vex_scalar_mode
)
15875 oappend (names_xmm
[reg
]);
15879 switch (vex
.length
)
15886 case vex_vsib_q_w_dq_mode
:
15887 case vex_vsib_q_w_d_mode
:
15903 names
= names_mask
;
15917 case vex_vsib_q_w_dq_mode
:
15918 case vex_vsib_q_w_d_mode
:
15919 names
= vex
.w
? names_ymm
: names_xmm
;
15928 names
= names_mask
;
15931 /* See PR binutils/20893 for a reproducer. */
15943 oappend (names
[reg
]);
15946 /* Get the VEX immediate byte without moving codep. */
15948 static unsigned char
15949 get_vex_imm8 (int sizeflag
, int opnum
)
15951 int bytes_before_imm
= 0;
15953 if (modrm
.mod
!= 3)
15955 /* There are SIB/displacement bytes. */
15956 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15958 /* 32/64 bit address mode */
15959 int base
= modrm
.rm
;
15961 /* Check SIB byte. */
15964 FETCH_DATA (the_info
, codep
+ 1);
15966 /* When decoding the third source, don't increase
15967 bytes_before_imm as this has already been incremented
15968 by one in OP_E_memory while decoding the second
15971 bytes_before_imm
++;
15974 /* Don't increase bytes_before_imm when decoding the third source,
15975 it has already been incremented by OP_E_memory while decoding
15976 the second source operand. */
15982 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15983 SIB == 5, there is a 4 byte displacement. */
15985 /* No displacement. */
15987 /* Fall through. */
15989 /* 4 byte displacement. */
15990 bytes_before_imm
+= 4;
15993 /* 1 byte displacement. */
15994 bytes_before_imm
++;
16001 /* 16 bit address mode */
16002 /* Don't increase bytes_before_imm when decoding the third source,
16003 it has already been incremented by OP_E_memory while decoding
16004 the second source operand. */
16010 /* When modrm.rm == 6, there is a 2 byte displacement. */
16012 /* No displacement. */
16014 /* Fall through. */
16016 /* 2 byte displacement. */
16017 bytes_before_imm
+= 2;
16020 /* 1 byte displacement: when decoding the third source,
16021 don't increase bytes_before_imm as this has already
16022 been incremented by one in OP_E_memory while decoding
16023 the second source operand. */
16025 bytes_before_imm
++;
16033 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16034 return codep
[bytes_before_imm
];
16038 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16040 const char **names
;
16042 if (reg
== -1 && modrm
.mod
!= 3)
16044 OP_E_memory (bytemode
, sizeflag
);
16056 if (address_mode
!= mode_64bit
)
16060 switch (vex
.length
)
16071 oappend (names
[reg
]);
16075 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16078 static unsigned char vex_imm8
;
16080 if (vex_w_done
== 0)
16084 /* Skip mod/rm byte. */
16088 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16091 reg
= vex_imm8
>> 4;
16093 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16095 else if (vex_w_done
== 1)
16100 reg
= vex_imm8
>> 4;
16102 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16106 /* Output the imm8 directly. */
16107 scratchbuf
[0] = '$';
16108 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16109 oappend_maybe_intel (scratchbuf
);
16110 scratchbuf
[0] = '\0';
16116 OP_Vex_2src (int bytemode
, int sizeflag
)
16118 if (modrm
.mod
== 3)
16120 int reg
= modrm
.rm
;
16124 oappend (names_xmm
[reg
]);
16129 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16131 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16132 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16134 OP_E (bytemode
, sizeflag
);
16139 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16141 if (modrm
.mod
== 3)
16143 /* Skip mod/rm byte. */
16150 unsigned int reg
= vex
.register_specifier
;
16151 vex
.register_specifier
= 0;
16153 if (address_mode
!= mode_64bit
)
16155 oappend (names_xmm
[reg
]);
16158 OP_Vex_2src (bytemode
, sizeflag
);
16162 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16165 OP_Vex_2src (bytemode
, sizeflag
);
16168 unsigned int reg
= vex
.register_specifier
;
16169 vex
.register_specifier
= 0;
16171 if (address_mode
!= mode_64bit
)
16173 oappend (names_xmm
[reg
]);
16178 OP_EX_VexW (int bytemode
, int sizeflag
)
16184 /* Skip mod/rm byte. */
16189 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16194 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16197 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16205 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16208 const char **names
;
16210 FETCH_DATA (the_info
, codep
+ 1);
16213 if (bytemode
!= x_mode
)
16217 if (address_mode
!= mode_64bit
)
16220 switch (vex
.length
)
16231 oappend (names
[reg
]);
16235 OP_XMM_VexW (int bytemode
, int sizeflag
)
16237 /* Turn off the REX.W bit since it is used for swapping operands
16240 OP_XMM (bytemode
, sizeflag
);
16244 OP_EX_Vex (int bytemode
, int sizeflag
)
16246 if (modrm
.mod
!= 3)
16248 OP_EX (bytemode
, sizeflag
);
16252 OP_XMM_Vex (int bytemode
, int sizeflag
)
16254 if (modrm
.mod
!= 3)
16256 OP_XMM (bytemode
, sizeflag
);
16259 static struct op vex_cmp_op
[] =
16261 { STRING_COMMA_LEN ("eq") },
16262 { STRING_COMMA_LEN ("lt") },
16263 { STRING_COMMA_LEN ("le") },
16264 { STRING_COMMA_LEN ("unord") },
16265 { STRING_COMMA_LEN ("neq") },
16266 { STRING_COMMA_LEN ("nlt") },
16267 { STRING_COMMA_LEN ("nle") },
16268 { STRING_COMMA_LEN ("ord") },
16269 { STRING_COMMA_LEN ("eq_uq") },
16270 { STRING_COMMA_LEN ("nge") },
16271 { STRING_COMMA_LEN ("ngt") },
16272 { STRING_COMMA_LEN ("false") },
16273 { STRING_COMMA_LEN ("neq_oq") },
16274 { STRING_COMMA_LEN ("ge") },
16275 { STRING_COMMA_LEN ("gt") },
16276 { STRING_COMMA_LEN ("true") },
16277 { STRING_COMMA_LEN ("eq_os") },
16278 { STRING_COMMA_LEN ("lt_oq") },
16279 { STRING_COMMA_LEN ("le_oq") },
16280 { STRING_COMMA_LEN ("unord_s") },
16281 { STRING_COMMA_LEN ("neq_us") },
16282 { STRING_COMMA_LEN ("nlt_uq") },
16283 { STRING_COMMA_LEN ("nle_uq") },
16284 { STRING_COMMA_LEN ("ord_s") },
16285 { STRING_COMMA_LEN ("eq_us") },
16286 { STRING_COMMA_LEN ("nge_uq") },
16287 { STRING_COMMA_LEN ("ngt_uq") },
16288 { STRING_COMMA_LEN ("false_os") },
16289 { STRING_COMMA_LEN ("neq_os") },
16290 { STRING_COMMA_LEN ("ge_oq") },
16291 { STRING_COMMA_LEN ("gt_oq") },
16292 { STRING_COMMA_LEN ("true_us") },
16296 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16298 unsigned int cmp_type
;
16300 FETCH_DATA (the_info
, codep
+ 1);
16301 cmp_type
= *codep
++ & 0xff;
16302 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16305 char *p
= mnemonicendp
- 2;
16309 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16310 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16314 /* We have a reserved extension byte. Output it directly. */
16315 scratchbuf
[0] = '$';
16316 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16317 oappend_maybe_intel (scratchbuf
);
16318 scratchbuf
[0] = '\0';
16323 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16324 int sizeflag ATTRIBUTE_UNUSED
)
16326 unsigned int cmp_type
;
16331 FETCH_DATA (the_info
, codep
+ 1);
16332 cmp_type
= *codep
++ & 0xff;
16333 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16334 If it's the case, print suffix, otherwise - print the immediate. */
16335 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16340 char *p
= mnemonicendp
- 2;
16342 /* vpcmp* can have both one- and two-lettered suffix. */
16356 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16357 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16361 /* We have a reserved extension byte. Output it directly. */
16362 scratchbuf
[0] = '$';
16363 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16364 oappend_maybe_intel (scratchbuf
);
16365 scratchbuf
[0] = '\0';
16369 static const struct op xop_cmp_op
[] =
16371 { STRING_COMMA_LEN ("lt") },
16372 { STRING_COMMA_LEN ("le") },
16373 { STRING_COMMA_LEN ("gt") },
16374 { STRING_COMMA_LEN ("ge") },
16375 { STRING_COMMA_LEN ("eq") },
16376 { STRING_COMMA_LEN ("neq") },
16377 { STRING_COMMA_LEN ("false") },
16378 { STRING_COMMA_LEN ("true") }
16382 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16383 int sizeflag ATTRIBUTE_UNUSED
)
16385 unsigned int cmp_type
;
16387 FETCH_DATA (the_info
, codep
+ 1);
16388 cmp_type
= *codep
++ & 0xff;
16389 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16392 char *p
= mnemonicendp
- 2;
16394 /* vpcom* can have both one- and two-lettered suffix. */
16408 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16409 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16413 /* We have a reserved extension byte. Output it directly. */
16414 scratchbuf
[0] = '$';
16415 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16416 oappend_maybe_intel (scratchbuf
);
16417 scratchbuf
[0] = '\0';
16421 static const struct op pclmul_op
[] =
16423 { STRING_COMMA_LEN ("lql") },
16424 { STRING_COMMA_LEN ("hql") },
16425 { STRING_COMMA_LEN ("lqh") },
16426 { STRING_COMMA_LEN ("hqh") }
16430 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16431 int sizeflag ATTRIBUTE_UNUSED
)
16433 unsigned int pclmul_type
;
16435 FETCH_DATA (the_info
, codep
+ 1);
16436 pclmul_type
= *codep
++ & 0xff;
16437 switch (pclmul_type
)
16448 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16451 char *p
= mnemonicendp
- 3;
16456 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16457 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16461 /* We have a reserved extension byte. Output it directly. */
16462 scratchbuf
[0] = '$';
16463 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16464 oappend_maybe_intel (scratchbuf
);
16465 scratchbuf
[0] = '\0';
16470 MOVBE_Fixup (int bytemode
, int sizeflag
)
16472 /* Add proper suffix to "movbe". */
16473 char *p
= mnemonicendp
;
16482 if (sizeflag
& SUFFIX_ALWAYS
)
16488 if (sizeflag
& DFLAG
)
16492 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16497 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16504 OP_M (bytemode
, sizeflag
);
16508 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16511 const char **names
;
16513 /* Skip mod/rm byte. */
16527 oappend (names
[reg
]);
16531 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16533 const char **names
;
16534 unsigned int reg
= vex
.register_specifier
;
16535 vex
.register_specifier
= 0;
16542 if (address_mode
!= mode_64bit
)
16544 oappend (names
[reg
]);
16548 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16551 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16555 if ((rex
& REX_R
) != 0 || !vex
.r
)
16561 oappend (names_mask
[modrm
.reg
]);
16565 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16568 || (bytemode
!= evex_rounding_mode
16569 && bytemode
!= evex_rounding_64_mode
16570 && bytemode
!= evex_sae_mode
))
16572 if (modrm
.mod
== 3 && vex
.b
)
16575 case evex_rounding_64_mode
:
16576 if (address_mode
!= mode_64bit
)
16581 /* Fall through. */
16582 case evex_rounding_mode
:
16583 oappend (names_rounding
[vex
.ll
]);
16585 case evex_sae_mode
: