opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Ev_bnd { OP_E, v_bnd_mode }
 253 #define EvS { OP_E, v_swap_mode }
 254 #define Ed { OP_E, d_mode }
 255 #define Edq { OP_E, dq_mode }
 256 #define Edqw { OP_E, dqw_mode }
 257 #define Edqb { OP_E, dqb_mode }
 258 #define Edb { OP_E, db_mode }
 259 #define Edw { OP_E, dw_mode }
 260 #define Edqd { OP_E, dqd_mode }
 261 #define Eq { OP_E, q_mode }
 262 #define indirEv { OP_indirE, indir_v_mode }
 263 #define indirEp { OP_indirE, f_mode }
 264 #define stackEv { OP_E, stack_v_mode }
 265 #define Em { OP_E, m_mode }
 266 #define Ew { OP_E, w_mode }
 267 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 268 #define Ma { OP_M, a_mode }
 269 #define Mb { OP_M, b_mode }
 270 #define Md { OP_M, d_mode }
 271 #define Mo { OP_M, o_mode }
 272 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 273 #define Mq { OP_M, q_mode }
 274 #define Mx { OP_M, x_mode }
 275 #define Mxmm { OP_M, xmm_mode }
 276 #define Gb { OP_G, b_mode }
 277 #define Gbnd { OP_G, bnd_mode }
 278 #define Gv { OP_G, v_mode }
 279 #define Gd { OP_G, d_mode }
 280 #define Gdq { OP_G, dq_mode }
 281 #define Gm { OP_G, m_mode }
 282 #define Gw { OP_G, w_mode }
 283 #define Rd { OP_R, d_mode }
 284 #define Rdq { OP_R, dq_mode }
 285 #define Rm { OP_R, m_mode }
 286 #define Ib { OP_I, b_mode }
 287 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 289 #define Iv { OP_I, v_mode }
 290 #define sIv { OP_sI, v_mode }
 291 #define Iq { OP_I, q_mode }
 292 #define Iv64 { OP_I64, v_mode }
 293 #define Iw { OP_I, w_mode }
 294 #define I1 { OP_I, const_1_mode }
 295 #define Jb { OP_J, b_mode }
 296 #define Jv { OP_J, v_mode }
 297 #define Cm { OP_C, m_mode }
 298 #define Dm { OP_D, m_mode }
 299 #define Td { OP_T, d_mode }
 300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 301
 302 #define RMeAX { OP_REG, eAX_reg }
 303 #define RMeBX { OP_REG, eBX_reg }
 304 #define RMeCX { OP_REG, eCX_reg }
 305 #define RMeDX { OP_REG, eDX_reg }
 306 #define RMeSP { OP_REG, eSP_reg }
 307 #define RMeBP { OP_REG, eBP_reg }
 308 #define RMeSI { OP_REG, eSI_reg }
 309 #define RMeDI { OP_REG, eDI_reg }
 310 #define RMrAX { OP_REG, rAX_reg }
 311 #define RMrBX { OP_REG, rBX_reg }
 312 #define RMrCX { OP_REG, rCX_reg }
 313 #define RMrDX { OP_REG, rDX_reg }
 314 #define RMrSP { OP_REG, rSP_reg }
 315 #define RMrBP { OP_REG, rBP_reg }
 316 #define RMrSI { OP_REG, rSI_reg }
 317 #define RMrDI { OP_REG, rDI_reg }
 318 #define RMAL { OP_REG, al_reg }
 319 #define RMCL { OP_REG, cl_reg }
 320 #define RMDL { OP_REG, dl_reg }
 321 #define RMBL { OP_REG, bl_reg }
 322 #define RMAH { OP_REG, ah_reg }
 323 #define RMCH { OP_REG, ch_reg }
 324 #define RMDH { OP_REG, dh_reg }
 325 #define RMBH { OP_REG, bh_reg }
 326 #define RMAX { OP_REG, ax_reg }
 327 #define RMDX { OP_REG, dx_reg }
 328
 329 #define eAX { OP_IMREG, eAX_reg }
 330 #define eBX { OP_IMREG, eBX_reg }
 331 #define eCX { OP_IMREG, eCX_reg }
 332 #define eDX { OP_IMREG, eDX_reg }
 333 #define eSP { OP_IMREG, eSP_reg }
 334 #define eBP { OP_IMREG, eBP_reg }
 335 #define eSI { OP_IMREG, eSI_reg }
 336 #define eDI { OP_IMREG, eDI_reg }
 337 #define AL { OP_IMREG, al_reg }
 338 #define CL { OP_IMREG, cl_reg }
 339 #define DL { OP_IMREG, dl_reg }
 340 #define BL { OP_IMREG, bl_reg }
 341 #define AH { OP_IMREG, ah_reg }
 342 #define CH { OP_IMREG, ch_reg }
 343 #define DH { OP_IMREG, dh_reg }
 344 #define BH { OP_IMREG, bh_reg }
 345 #define AX { OP_IMREG, ax_reg }
 346 #define DX { OP_IMREG, dx_reg }
 347 #define zAX { OP_IMREG, z_mode_ax_reg }
 348 #define indirDX { OP_IMREG, indir_dx_reg }
 349
 350 #define Sw { OP_SEG, w_mode }
 351 #define Sv { OP_SEG, v_mode }
 352 #define Ap { OP_DIR, 0 }
 353 #define Ob { OP_OFF64, b_mode }
 354 #define Ov { OP_OFF64, v_mode }
 355 #define Xb { OP_DSreg, eSI_reg }
 356 #define Xv { OP_DSreg, eSI_reg }
 357 #define Xz { OP_DSreg, eSI_reg }
 358 #define Yb { OP_ESreg, eDI_reg }
 359 #define Yv { OP_ESreg, eDI_reg }
 360 #define DSBX { OP_DSreg, eBX_reg }
 361
 362 #define es { OP_REG, es_reg }
 363 #define ss { OP_REG, ss_reg }
 364 #define cs { OP_REG, cs_reg }
 365 #define ds { OP_REG, ds_reg }
 366 #define fs { OP_REG, fs_reg }
 367 #define gs { OP_REG, gs_reg }
 368
 369 #define MX { OP_MMX, 0 }
 370 #define XM { OP_XMM, 0 }
 371 #define XMScalar { OP_XMM, scalar_mode }
 372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 373 #define XMM { OP_XMM, xmm_mode }
 374 #define XMxmmq { OP_XMM, xmmq_mode }
 375 #define EM { OP_EM, v_mode }
 376 #define EMS { OP_EM, v_swap_mode }
 377 #define EMd { OP_EM, d_mode }
 378 #define EMx { OP_EM, x_mode }
 379 #define EXw { OP_EX, w_mode }
 380 #define EXd { OP_EX, d_mode }
 381 #define EXdScalar { OP_EX, d_scalar_mode }
 382 #define EXdS { OP_EX, d_swap_mode }
 383 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 384 #define EXq { OP_EX, q_mode }
 385 #define EXqScalar { OP_EX, q_scalar_mode }
 386 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 387 #define EXqS { OP_EX, q_swap_mode }
 388 #define EXx { OP_EX, x_mode }
 389 #define EXxS { OP_EX, x_swap_mode }
 390 #define EXxmm { OP_EX, xmm_mode }
 391 #define EXymm { OP_EX, ymm_mode }
 392 #define EXxmmq { OP_EX, xmmq_mode }
 393 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 394 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 395 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 396 #define EXxmm_md { OP_EX, xmm_md_mode }
 397 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 398 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 399 #define EXxmmdw { OP_EX, xmmdw_mode }
 400 #define EXxmmqd { OP_EX, xmmqd_mode }
 401 #define EXymmq { OP_EX, ymmq_mode }
 402 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 403 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 404 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 405 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 406 #define MS { OP_MS, v_mode }
 407 #define XS { OP_XS, v_mode }
 408 #define EMCq { OP_EMC, q_mode }
 409 #define MXC { OP_MXC, 0 }
 410 #define OPSUF { OP_3DNowSuffix, 0 }
 411 #define CMP { CMP_Fixup, 0 }
 412 #define XMM0 { XMM_Fixup, 0 }
 413 #define FXSAVE { FXSAVE_Fixup, 0 }
 414 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 415 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 416
 417 #define Vex { OP_VEX, vex_mode }
 418 #define VexScalar { OP_VEX, vex_scalar_mode }
 419 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 420 #define Vex128 { OP_VEX, vex128_mode }
 421 #define Vex256 { OP_VEX, vex256_mode }
 422 #define VexGdq { OP_VEX, dq_mode }
 423 #define VexI4 { VEXI4_Fixup, 0}
 424 #define EXdVex { OP_EX_Vex, d_mode }
 425 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 427 #define EXqVex { OP_EX_Vex, q_mode }
 428 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 429 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 430 #define EXVexW { OP_EX_VexW, x_mode }
 431 #define EXdVexW { OP_EX_VexW, d_mode }
 432 #define EXqVexW { OP_EX_VexW, q_mode }
 433 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 434 #define XMVex { OP_XMM_Vex, 0 }
 435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 436 #define XMVexW { OP_XMM_VexW, 0 }
 437 #define XMVexI4 { OP_REG_VexI4, x_mode }
 438 #define PCLMUL { PCLMUL_Fixup, 0 }
 439 #define VZERO { VZERO_Fixup, 0 }
 440 #define VCMP { VCMP_Fixup, 0 }
 441 #define VPCMP { VPCMP_Fixup, 0 }
 442
 443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 444 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 445
 446 #define XMask { OP_Mask, mask_mode }
 447 #define MaskG { OP_G, mask_mode }
 448 #define MaskE { OP_E, mask_mode }
 449 #define MaskBDE { OP_E, mask_bd_mode }
 450 #define MaskR { OP_R, mask_mode }
 451 #define MaskVex { OP_VEX, mask_mode }
 452
 453 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 454 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 455 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 456 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 457
 458 /* Used handle "rep" prefix for string instructions.  */
 459 #define Xbr { REP_Fixup, eSI_reg }
 460 #define Xvr { REP_Fixup, eSI_reg }
 461 #define Ybr { REP_Fixup, eDI_reg }
 462 #define Yvr { REP_Fixup, eDI_reg }
 463 #define Yzr { REP_Fixup, eDI_reg }
 464 #define indirDXr { REP_Fixup, indir_dx_reg }
 465 #define ALr { REP_Fixup, al_reg }
 466 #define eAXr { REP_Fixup, eAX_reg }
 467
 468 /* Used handle HLE prefix for lockable instructions.  */
 469 #define Ebh1 { HLE_Fixup1, b_mode }
 470 #define Evh1 { HLE_Fixup1, v_mode }
 471 #define Ebh2 { HLE_Fixup2, b_mode }
 472 #define Evh2 { HLE_Fixup2, v_mode }
 473 #define Ebh3 { HLE_Fixup3, b_mode }
 474 #define Evh3 { HLE_Fixup3, v_mode }
 475
 476 #define BND { BND_Fixup, 0 }
 477 #define NOTRACK { NOTRACK_Fixup, 0 }
 478
 479 #define cond_jump_flag { NULL, cond_jump_mode }
 480 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 481
 482 /* bits in sizeflag */
 483 #define SUFFIX_ALWAYS 4
 484 #define AFLAG 2
 485 #define DFLAG 1
 486
 487 enum
 488 {
 489   /* byte operand */
 490   b_mode = 1,
 491   /* byte operand with operand swapped */
 492   b_swap_mode,
 493   /* byte operand, sign extend like 'T' suffix */
 494   b_T_mode,
 495   /* operand size depends on prefixes */
 496   v_mode,
 497   /* operand size depends on prefixes with operand swapped */
 498   v_swap_mode,
 499   /* word operand */
 500   w_mode,
 501   /* double word operand  */
 502   d_mode,
 503   /* double word operand with operand swapped */
 504   d_swap_mode,
 505   /* quad word operand */
 506   q_mode,
 507   /* quad word operand with operand swapped */
 508   q_swap_mode,
 509   /* ten-byte operand */
 510   t_mode,
 511   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 512      broadcast enabled.  */
 513   x_mode,
 514   /* Similar to x_mode, but with different EVEX mem shifts.  */
 515   evex_x_gscat_mode,
 516   /* Similar to x_mode, but with disabled broadcast.  */
 517   evex_x_nobcst_mode,
 518   /* Similar to x_mode, but with operands swapped and disabled broadcast
 519      in EVEX.  */
 520   x_swap_mode,
 521   /* 16-byte XMM operand */
 522   xmm_mode,
 523   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 524      memory operand (depending on vector length).  Broadcast isn't
 525      allowed.  */
 526   xmmq_mode,
 527   /* Same as xmmq_mode, but broadcast is allowed.  */
 528   evex_half_bcst_xmmq_mode,
 529   /* XMM register or byte memory operand */
 530   xmm_mb_mode,
 531   /* XMM register or word memory operand */
 532   xmm_mw_mode,
 533   /* XMM register or double word memory operand */
 534   xmm_md_mode,
 535   /* XMM register or quad word memory operand */
 536   xmm_mq_mode,
 537   /* XMM register or double/quad word memory operand, depending on
 538      VEX.W.  */
 539   xmm_mdq_mode,
 540   /* 16-byte XMM, word, double word or quad word operand.  */
 541   xmmdw_mode,
 542   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 543   xmmqd_mode,
 544   /* 32-byte YMM operand */
 545   ymm_mode,
 546   /* quad word, ymmword or zmmword memory operand.  */
 547   ymmq_mode,
 548   /* 32-byte YMM or 16-byte word operand */
 549   ymmxmm_mode,
 550   /* d_mode in 32bit, q_mode in 64bit mode.  */
 551   m_mode,
 552   /* pair of v_mode operands */
 553   a_mode,
 554   cond_jump_mode,
 555   loop_jcxz_mode,
 556   v_bnd_mode,
 557   /* operand size depends on REX prefixes.  */
 558   dq_mode,
 559   /* registers like dq_mode, memory like w_mode.  */
 560   dqw_mode,
 561   bnd_mode,
 562   /* 4- or 6-byte pointer operand */
 563   f_mode,
 564   const_1_mode,
 565   /* v_mode for indirect branch opcodes.  */
 566   indir_v_mode,
 567   /* v_mode for stack-related opcodes.  */
 568   stack_v_mode,
 569   /* non-quad operand size depends on prefixes */
 570   z_mode,
 571   /* 16-byte operand */
 572   o_mode,
 573   /* registers like dq_mode, memory like b_mode.  */
 574   dqb_mode,
 575   /* registers like d_mode, memory like b_mode.  */
 576   db_mode,
 577   /* registers like d_mode, memory like w_mode.  */
 578   dw_mode,
 579   /* registers like dq_mode, memory like d_mode.  */
 580   dqd_mode,
 581   /* normal vex mode */
 582   vex_mode,
 583   /* 128bit vex mode */
 584   vex128_mode,
 585   /* 256bit vex mode */
 586   vex256_mode,
 587   /* operand size depends on the VEX.W bit.  */
 588   vex_w_dq_mode,
 589
 590   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 591   vex_vsib_d_w_dq_mode,
 592   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 593   vex_vsib_d_w_d_mode,
 594   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 595   vex_vsib_q_w_dq_mode,
 596   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 597   vex_vsib_q_w_d_mode,
 598
 599   /* scalar, ignore vector length.  */
 600   scalar_mode,
 601   /* like d_mode, ignore vector length.  */
 602   d_scalar_mode,
 603   /* like d_swap_mode, ignore vector length.  */
 604   d_scalar_swap_mode,
 605   /* like q_mode, ignore vector length.  */
 606   q_scalar_mode,
 607   /* like q_swap_mode, ignore vector length.  */
 608   q_scalar_swap_mode,
 609   /* like vex_mode, ignore vector length.  */
 610   vex_scalar_mode,
 611   /* like vex_w_dq_mode, ignore vector length.  */
 612   vex_scalar_w_dq_mode,
 613
 614   /* Static rounding.  */
 615   evex_rounding_mode,
 616   /* Supress all exceptions.  */
 617   evex_sae_mode,
 618
 619   /* Mask register operand.  */
 620   mask_mode,
 621   /* Mask register operand.  */
 622   mask_bd_mode,
 623
 624   es_reg,
 625   cs_reg,
 626   ss_reg,
 627   ds_reg,
 628   fs_reg,
 629   gs_reg,
 630
 631   eAX_reg,
 632   eCX_reg,
 633   eDX_reg,
 634   eBX_reg,
 635   eSP_reg,
 636   eBP_reg,
 637   eSI_reg,
 638   eDI_reg,
 639
 640   al_reg,
 641   cl_reg,
 642   dl_reg,
 643   bl_reg,
 644   ah_reg,
 645   ch_reg,
 646   dh_reg,
 647   bh_reg,
 648
 649   ax_reg,
 650   cx_reg,
 651   dx_reg,
 652   bx_reg,
 653   sp_reg,
 654   bp_reg,
 655   si_reg,
 656   di_reg,
 657
 658   rAX_reg,
 659   rCX_reg,
 660   rDX_reg,
 661   rBX_reg,
 662   rSP_reg,
 663   rBP_reg,
 664   rSI_reg,
 665   rDI_reg,
 666
 667   z_mode_ax_reg,
 668   indir_dx_reg
 669 };
 670
 671 enum
 672 {
 673   FLOATCODE = 1,
 674   USE_REG_TABLE,
 675   USE_MOD_TABLE,
 676   USE_RM_TABLE,
 677   USE_PREFIX_TABLE,
 678   USE_X86_64_TABLE,
 679   USE_3BYTE_TABLE,
 680   USE_XOP_8F_TABLE,
 681   USE_VEX_C4_TABLE,
 682   USE_VEX_C5_TABLE,
 683   USE_VEX_LEN_TABLE,
 684   USE_VEX_W_TABLE,
 685   USE_EVEX_TABLE
 686 };
 687
 688 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 689
 690 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 691 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 692 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 693 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 694 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 695 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 696 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 697 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 698 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 699 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 700 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 701 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 702 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 703 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 704 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 705
 706 enum
 707 {
 708   REG_80 = 0,
 709   REG_81,
 710   REG_83,
 711   REG_8F,
 712   REG_C0,
 713   REG_C1,
 714   REG_C6,
 715   REG_C7,
 716   REG_D0,
 717   REG_D1,
 718   REG_D2,
 719   REG_D3,
 720   REG_F6,
 721   REG_F7,
 722   REG_FE,
 723   REG_FF,
 724   REG_0F00,
 725   REG_0F01,
 726   REG_0F0D,
 727   REG_0F18,
 728   REG_0F1E_MOD_3,
 729   REG_0F71,
 730   REG_0F72,
 731   REG_0F73,
 732   REG_0FA6,
 733   REG_0FA7,
 734   REG_0FAE,
 735   REG_0FBA,
 736   REG_0FC7,
 737   REG_VEX_0F71,
 738   REG_VEX_0F72,
 739   REG_VEX_0F73,
 740   REG_VEX_0FAE,
 741   REG_VEX_0F38F3,
 742   REG_XOP_LWPCB,
 743   REG_XOP_LWP,
 744   REG_XOP_TBM_01,
 745   REG_XOP_TBM_02,
 746
 747   REG_EVEX_0F71,
 748   REG_EVEX_0F72,
 749   REG_EVEX_0F73,
 750   REG_EVEX_0F38C6,
 751   REG_EVEX_0F38C7
 752 };
 753
 754 enum
 755 {
 756   MOD_8D = 0,
 757   MOD_C6_REG_7,
 758   MOD_C7_REG_7,
 759   MOD_FF_REG_3,
 760   MOD_FF_REG_5,
 761   MOD_0F01_REG_0,
 762   MOD_0F01_REG_1,
 763   MOD_0F01_REG_2,
 764   MOD_0F01_REG_3,
 765   MOD_0F01_REG_5,
 766   MOD_0F01_REG_7,
 767   MOD_0F12_PREFIX_0,
 768   MOD_0F13,
 769   MOD_0F16_PREFIX_0,
 770   MOD_0F17,
 771   MOD_0F18_REG_0,
 772   MOD_0F18_REG_1,
 773   MOD_0F18_REG_2,
 774   MOD_0F18_REG_3,
 775   MOD_0F18_REG_4,
 776   MOD_0F18_REG_5,
 777   MOD_0F18_REG_6,
 778   MOD_0F18_REG_7,
 779   MOD_0F1A_PREFIX_0,
 780   MOD_0F1B_PREFIX_0,
 781   MOD_0F1B_PREFIX_1,
 782   MOD_0F1E_PREFIX_1,
 783   MOD_0F24,
 784   MOD_0F26,
 785   MOD_0F2B_PREFIX_0,
 786   MOD_0F2B_PREFIX_1,
 787   MOD_0F2B_PREFIX_2,
 788   MOD_0F2B_PREFIX_3,
 789   MOD_0F51,
 790   MOD_0F71_REG_2,
 791   MOD_0F71_REG_4,
 792   MOD_0F71_REG_6,
 793   MOD_0F72_REG_2,
 794   MOD_0F72_REG_4,
 795   MOD_0F72_REG_6,
 796   MOD_0F73_REG_2,
 797   MOD_0F73_REG_3,
 798   MOD_0F73_REG_6,
 799   MOD_0F73_REG_7,
 800   MOD_0FAE_REG_0,
 801   MOD_0FAE_REG_1,
 802   MOD_0FAE_REG_2,
 803   MOD_0FAE_REG_3,
 804   MOD_0FAE_REG_4,
 805   MOD_0FAE_REG_5,
 806   MOD_0FAE_REG_6,
 807   MOD_0FAE_REG_7,
 808   MOD_0FB2,
 809   MOD_0FB4,
 810   MOD_0FB5,
 811   MOD_0FC3,
 812   MOD_0FC7_REG_3,
 813   MOD_0FC7_REG_4,
 814   MOD_0FC7_REG_5,
 815   MOD_0FC7_REG_6,
 816   MOD_0FC7_REG_7,
 817   MOD_0FD7,
 818   MOD_0FE7_PREFIX_2,
 819   MOD_0FF0_PREFIX_3,
 820   MOD_0F382A_PREFIX_2,
 821   MOD_0F38F5_PREFIX_2,
 822   MOD_0F38F6_PREFIX_0,
 823   MOD_62_32BIT,
 824   MOD_C4_32BIT,
 825   MOD_C5_32BIT,
 826   MOD_VEX_0F12_PREFIX_0,
 827   MOD_VEX_0F13,
 828   MOD_VEX_0F16_PREFIX_0,
 829   MOD_VEX_0F17,
 830   MOD_VEX_0F2B,
 831   MOD_VEX_W_0_0F41_P_0_LEN_1,
 832   MOD_VEX_W_1_0F41_P_0_LEN_1,
 833   MOD_VEX_W_0_0F41_P_2_LEN_1,
 834   MOD_VEX_W_1_0F41_P_2_LEN_1,
 835   MOD_VEX_W_0_0F42_P_0_LEN_1,
 836   MOD_VEX_W_1_0F42_P_0_LEN_1,
 837   MOD_VEX_W_0_0F42_P_2_LEN_1,
 838   MOD_VEX_W_1_0F42_P_2_LEN_1,
 839   MOD_VEX_W_0_0F44_P_0_LEN_1,
 840   MOD_VEX_W_1_0F44_P_0_LEN_1,
 841   MOD_VEX_W_0_0F44_P_2_LEN_1,
 842   MOD_VEX_W_1_0F44_P_2_LEN_1,
 843   MOD_VEX_W_0_0F45_P_0_LEN_1,
 844   MOD_VEX_W_1_0F45_P_0_LEN_1,
 845   MOD_VEX_W_0_0F45_P_2_LEN_1,
 846   MOD_VEX_W_1_0F45_P_2_LEN_1,
 847   MOD_VEX_W_0_0F46_P_0_LEN_1,
 848   MOD_VEX_W_1_0F46_P_0_LEN_1,
 849   MOD_VEX_W_0_0F46_P_2_LEN_1,
 850   MOD_VEX_W_1_0F46_P_2_LEN_1,
 851   MOD_VEX_W_0_0F47_P_0_LEN_1,
 852   MOD_VEX_W_1_0F47_P_0_LEN_1,
 853   MOD_VEX_W_0_0F47_P_2_LEN_1,
 854   MOD_VEX_W_1_0F47_P_2_LEN_1,
 855   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 856   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 857   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 858   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 859   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 860   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 861   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 862   MOD_VEX_0F50,
 863   MOD_VEX_0F71_REG_2,
 864   MOD_VEX_0F71_REG_4,
 865   MOD_VEX_0F71_REG_6,
 866   MOD_VEX_0F72_REG_2,
 867   MOD_VEX_0F72_REG_4,
 868   MOD_VEX_0F72_REG_6,
 869   MOD_VEX_0F73_REG_2,
 870   MOD_VEX_0F73_REG_3,
 871   MOD_VEX_0F73_REG_6,
 872   MOD_VEX_0F73_REG_7,
 873   MOD_VEX_W_0_0F91_P_0_LEN_0,
 874   MOD_VEX_W_1_0F91_P_0_LEN_0,
 875   MOD_VEX_W_0_0F91_P_2_LEN_0,
 876   MOD_VEX_W_1_0F91_P_2_LEN_0,
 877   MOD_VEX_W_0_0F92_P_0_LEN_0,
 878   MOD_VEX_W_0_0F92_P_2_LEN_0,
 879   MOD_VEX_W_0_0F92_P_3_LEN_0,
 880   MOD_VEX_W_1_0F92_P_3_LEN_0,
 881   MOD_VEX_W_0_0F93_P_0_LEN_0,
 882   MOD_VEX_W_0_0F93_P_2_LEN_0,
 883   MOD_VEX_W_0_0F93_P_3_LEN_0,
 884   MOD_VEX_W_1_0F93_P_3_LEN_0,
 885   MOD_VEX_W_0_0F98_P_0_LEN_0,
 886   MOD_VEX_W_1_0F98_P_0_LEN_0,
 887   MOD_VEX_W_0_0F98_P_2_LEN_0,
 888   MOD_VEX_W_1_0F98_P_2_LEN_0,
 889   MOD_VEX_W_0_0F99_P_0_LEN_0,
 890   MOD_VEX_W_1_0F99_P_0_LEN_0,
 891   MOD_VEX_W_0_0F99_P_2_LEN_0,
 892   MOD_VEX_W_1_0F99_P_2_LEN_0,
 893   MOD_VEX_0FAE_REG_2,
 894   MOD_VEX_0FAE_REG_3,
 895   MOD_VEX_0FD7_PREFIX_2,
 896   MOD_VEX_0FE7_PREFIX_2,
 897   MOD_VEX_0FF0_PREFIX_3,
 898   MOD_VEX_0F381A_PREFIX_2,
 899   MOD_VEX_0F382A_PREFIX_2,
 900   MOD_VEX_0F382C_PREFIX_2,
 901   MOD_VEX_0F382D_PREFIX_2,
 902   MOD_VEX_0F382E_PREFIX_2,
 903   MOD_VEX_0F382F_PREFIX_2,
 904   MOD_VEX_0F385A_PREFIX_2,
 905   MOD_VEX_0F388C_PREFIX_2,
 906   MOD_VEX_0F388E_PREFIX_2,
 907   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 908   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 909   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 910   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 911   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 912   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 913   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 914   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 915
 916   MOD_EVEX_0F10_PREFIX_1,
 917   MOD_EVEX_0F10_PREFIX_3,
 918   MOD_EVEX_0F11_PREFIX_1,
 919   MOD_EVEX_0F11_PREFIX_3,
 920   MOD_EVEX_0F12_PREFIX_0,
 921   MOD_EVEX_0F16_PREFIX_0,
 922   MOD_EVEX_0F38C6_REG_1,
 923   MOD_EVEX_0F38C6_REG_2,
 924   MOD_EVEX_0F38C6_REG_5,
 925   MOD_EVEX_0F38C6_REG_6,
 926   MOD_EVEX_0F38C7_REG_1,
 927   MOD_EVEX_0F38C7_REG_2,
 928   MOD_EVEX_0F38C7_REG_5,
 929   MOD_EVEX_0F38C7_REG_6
 930 };
 931
 932 enum
 933 {
 934   RM_C6_REG_7 = 0,
 935   RM_C7_REG_7,
 936   RM_0F01_REG_0,
 937   RM_0F01_REG_1,
 938   RM_0F01_REG_2,
 939   RM_0F01_REG_3,
 940   RM_0F01_REG_5,
 941   RM_0F01_REG_7,
 942   RM_0F1E_MOD_3_REG_7,
 943   RM_0FAE_REG_6,
 944   RM_0FAE_REG_7
 945 };
 946
 947 enum
 948 {
 949   PREFIX_90 = 0,
 950   PREFIX_MOD_0_0F01_REG_5,
 951   PREFIX_MOD_3_0F01_REG_5_RM_0,
 952   PREFIX_MOD_3_0F01_REG_5_RM_2,
 953   PREFIX_0F10,
 954   PREFIX_0F11,
 955   PREFIX_0F12,
 956   PREFIX_0F16,
 957   PREFIX_0F1A,
 958   PREFIX_0F1B,
 959   PREFIX_0F1E,
 960   PREFIX_0F2A,
 961   PREFIX_0F2B,
 962   PREFIX_0F2C,
 963   PREFIX_0F2D,
 964   PREFIX_0F2E,
 965   PREFIX_0F2F,
 966   PREFIX_0F51,
 967   PREFIX_0F52,
 968   PREFIX_0F53,
 969   PREFIX_0F58,
 970   PREFIX_0F59,
 971   PREFIX_0F5A,
 972   PREFIX_0F5B,
 973   PREFIX_0F5C,
 974   PREFIX_0F5D,
 975   PREFIX_0F5E,
 976   PREFIX_0F5F,
 977   PREFIX_0F60,
 978   PREFIX_0F61,
 979   PREFIX_0F62,
 980   PREFIX_0F6C,
 981   PREFIX_0F6D,
 982   PREFIX_0F6F,
 983   PREFIX_0F70,
 984   PREFIX_0F73_REG_3,
 985   PREFIX_0F73_REG_7,
 986   PREFIX_0F78,
 987   PREFIX_0F79,
 988   PREFIX_0F7C,
 989   PREFIX_0F7D,
 990   PREFIX_0F7E,
 991   PREFIX_0F7F,
 992   PREFIX_0FAE_REG_0,
 993   PREFIX_0FAE_REG_1,
 994   PREFIX_0FAE_REG_2,
 995   PREFIX_0FAE_REG_3,
 996   PREFIX_MOD_0_0FAE_REG_4,
 997   PREFIX_MOD_3_0FAE_REG_4,
 998   PREFIX_MOD_0_0FAE_REG_5,
 999   PREFIX_MOD_3_0FAE_REG_5,
1000   PREFIX_0FAE_REG_6,
1001   PREFIX_0FAE_REG_7,
1002   PREFIX_0FB8,
1003   PREFIX_0FBC,
1004   PREFIX_0FBD,
1005   PREFIX_0FC2,
1006   PREFIX_MOD_0_0FC3,
1007   PREFIX_MOD_0_0FC7_REG_6,
1008   PREFIX_MOD_3_0FC7_REG_6,
1009   PREFIX_MOD_3_0FC7_REG_7,
1010   PREFIX_0FD0,
1011   PREFIX_0FD6,
1012   PREFIX_0FE6,
1013   PREFIX_0FE7,
1014   PREFIX_0FF0,
1015   PREFIX_0FF7,
1016   PREFIX_0F3810,
1017   PREFIX_0F3814,
1018   PREFIX_0F3815,
1019   PREFIX_0F3817,
1020   PREFIX_0F3820,
1021   PREFIX_0F3821,
1022   PREFIX_0F3822,
1023   PREFIX_0F3823,
1024   PREFIX_0F3824,
1025   PREFIX_0F3825,
1026   PREFIX_0F3828,
1027   PREFIX_0F3829,
1028   PREFIX_0F382A,
1029   PREFIX_0F382B,
1030   PREFIX_0F3830,
1031   PREFIX_0F3831,
1032   PREFIX_0F3832,
1033   PREFIX_0F3833,
1034   PREFIX_0F3834,
1035   PREFIX_0F3835,
1036   PREFIX_0F3837,
1037   PREFIX_0F3838,
1038   PREFIX_0F3839,
1039   PREFIX_0F383A,
1040   PREFIX_0F383B,
1041   PREFIX_0F383C,
1042   PREFIX_0F383D,
1043   PREFIX_0F383E,
1044   PREFIX_0F383F,
1045   PREFIX_0F3840,
1046   PREFIX_0F3841,
1047   PREFIX_0F3880,
1048   PREFIX_0F3881,
1049   PREFIX_0F3882,
1050   PREFIX_0F38C8,
1051   PREFIX_0F38C9,
1052   PREFIX_0F38CA,
1053   PREFIX_0F38CB,
1054   PREFIX_0F38CC,
1055   PREFIX_0F38CD,
1056   PREFIX_0F38DB,
1057   PREFIX_0F38DC,
1058   PREFIX_0F38DD,
1059   PREFIX_0F38DE,
1060   PREFIX_0F38DF,
1061   PREFIX_0F38F0,
1062   PREFIX_0F38F1,
1063   PREFIX_0F38F5,
1064   PREFIX_0F38F6,
1065   PREFIX_0F3A08,
1066   PREFIX_0F3A09,
1067   PREFIX_0F3A0A,
1068   PREFIX_0F3A0B,
1069   PREFIX_0F3A0C,
1070   PREFIX_0F3A0D,
1071   PREFIX_0F3A0E,
1072   PREFIX_0F3A14,
1073   PREFIX_0F3A15,
1074   PREFIX_0F3A16,
1075   PREFIX_0F3A17,
1076   PREFIX_0F3A20,
1077   PREFIX_0F3A21,
1078   PREFIX_0F3A22,
1079   PREFIX_0F3A40,
1080   PREFIX_0F3A41,
1081   PREFIX_0F3A42,
1082   PREFIX_0F3A44,
1083   PREFIX_0F3A60,
1084   PREFIX_0F3A61,
1085   PREFIX_0F3A62,
1086   PREFIX_0F3A63,
1087   PREFIX_0F3ACC,
1088   PREFIX_0F3ADF,
1089   PREFIX_VEX_0F10,
1090   PREFIX_VEX_0F11,
1091   PREFIX_VEX_0F12,
1092   PREFIX_VEX_0F16,
1093   PREFIX_VEX_0F2A,
1094   PREFIX_VEX_0F2C,
1095   PREFIX_VEX_0F2D,
1096   PREFIX_VEX_0F2E,
1097   PREFIX_VEX_0F2F,
1098   PREFIX_VEX_0F41,
1099   PREFIX_VEX_0F42,
1100   PREFIX_VEX_0F44,
1101   PREFIX_VEX_0F45,
1102   PREFIX_VEX_0F46,
1103   PREFIX_VEX_0F47,
1104   PREFIX_VEX_0F4A,
1105   PREFIX_VEX_0F4B,
1106   PREFIX_VEX_0F51,
1107   PREFIX_VEX_0F52,
1108   PREFIX_VEX_0F53,
1109   PREFIX_VEX_0F58,
1110   PREFIX_VEX_0F59,
1111   PREFIX_VEX_0F5A,
1112   PREFIX_VEX_0F5B,
1113   PREFIX_VEX_0F5C,
1114   PREFIX_VEX_0F5D,
1115   PREFIX_VEX_0F5E,
1116   PREFIX_VEX_0F5F,
1117   PREFIX_VEX_0F60,
1118   PREFIX_VEX_0F61,
1119   PREFIX_VEX_0F62,
1120   PREFIX_VEX_0F63,
1121   PREFIX_VEX_0F64,
1122   PREFIX_VEX_0F65,
1123   PREFIX_VEX_0F66,
1124   PREFIX_VEX_0F67,
1125   PREFIX_VEX_0F68,
1126   PREFIX_VEX_0F69,
1127   PREFIX_VEX_0F6A,
1128   PREFIX_VEX_0F6B,
1129   PREFIX_VEX_0F6C,
1130   PREFIX_VEX_0F6D,
1131   PREFIX_VEX_0F6E,
1132   PREFIX_VEX_0F6F,
1133   PREFIX_VEX_0F70,
1134   PREFIX_VEX_0F71_REG_2,
1135   PREFIX_VEX_0F71_REG_4,
1136   PREFIX_VEX_0F71_REG_6,
1137   PREFIX_VEX_0F72_REG_2,
1138   PREFIX_VEX_0F72_REG_4,
1139   PREFIX_VEX_0F72_REG_6,
1140   PREFIX_VEX_0F73_REG_2,
1141   PREFIX_VEX_0F73_REG_3,
1142   PREFIX_VEX_0F73_REG_6,
1143   PREFIX_VEX_0F73_REG_7,
1144   PREFIX_VEX_0F74,
1145   PREFIX_VEX_0F75,
1146   PREFIX_VEX_0F76,
1147   PREFIX_VEX_0F77,
1148   PREFIX_VEX_0F7C,
1149   PREFIX_VEX_0F7D,
1150   PREFIX_VEX_0F7E,
1151   PREFIX_VEX_0F7F,
1152   PREFIX_VEX_0F90,
1153   PREFIX_VEX_0F91,
1154   PREFIX_VEX_0F92,
1155   PREFIX_VEX_0F93,
1156   PREFIX_VEX_0F98,
1157   PREFIX_VEX_0F99,
1158   PREFIX_VEX_0FC2,
1159   PREFIX_VEX_0FC4,
1160   PREFIX_VEX_0FC5,
1161   PREFIX_VEX_0FD0,
1162   PREFIX_VEX_0FD1,
1163   PREFIX_VEX_0FD2,
1164   PREFIX_VEX_0FD3,
1165   PREFIX_VEX_0FD4,
1166   PREFIX_VEX_0FD5,
1167   PREFIX_VEX_0FD6,
1168   PREFIX_VEX_0FD7,
1169   PREFIX_VEX_0FD8,
1170   PREFIX_VEX_0FD9,
1171   PREFIX_VEX_0FDA,
1172   PREFIX_VEX_0FDB,
1173   PREFIX_VEX_0FDC,
1174   PREFIX_VEX_0FDD,
1175   PREFIX_VEX_0FDE,
1176   PREFIX_VEX_0FDF,
1177   PREFIX_VEX_0FE0,
1178   PREFIX_VEX_0FE1,
1179   PREFIX_VEX_0FE2,
1180   PREFIX_VEX_0FE3,
1181   PREFIX_VEX_0FE4,
1182   PREFIX_VEX_0FE5,
1183   PREFIX_VEX_0FE6,
1184   PREFIX_VEX_0FE7,
1185   PREFIX_VEX_0FE8,
1186   PREFIX_VEX_0FE9,
1187   PREFIX_VEX_0FEA,
1188   PREFIX_VEX_0FEB,
1189   PREFIX_VEX_0FEC,
1190   PREFIX_VEX_0FED,
1191   PREFIX_VEX_0FEE,
1192   PREFIX_VEX_0FEF,
1193   PREFIX_VEX_0FF0,
1194   PREFIX_VEX_0FF1,
1195   PREFIX_VEX_0FF2,
1196   PREFIX_VEX_0FF3,
1197   PREFIX_VEX_0FF4,
1198   PREFIX_VEX_0FF5,
1199   PREFIX_VEX_0FF6,
1200   PREFIX_VEX_0FF7,
1201   PREFIX_VEX_0FF8,
1202   PREFIX_VEX_0FF9,
1203   PREFIX_VEX_0FFA,
1204   PREFIX_VEX_0FFB,
1205   PREFIX_VEX_0FFC,
1206   PREFIX_VEX_0FFD,
1207   PREFIX_VEX_0FFE,
1208   PREFIX_VEX_0F3800,
1209   PREFIX_VEX_0F3801,
1210   PREFIX_VEX_0F3802,
1211   PREFIX_VEX_0F3803,
1212   PREFIX_VEX_0F3804,
1213   PREFIX_VEX_0F3805,
1214   PREFIX_VEX_0F3806,
1215   PREFIX_VEX_0F3807,
1216   PREFIX_VEX_0F3808,
1217   PREFIX_VEX_0F3809,
1218   PREFIX_VEX_0F380A,
1219   PREFIX_VEX_0F380B,
1220   PREFIX_VEX_0F380C,
1221   PREFIX_VEX_0F380D,
1222   PREFIX_VEX_0F380E,
1223   PREFIX_VEX_0F380F,
1224   PREFIX_VEX_0F3813,
1225   PREFIX_VEX_0F3816,
1226   PREFIX_VEX_0F3817,
1227   PREFIX_VEX_0F3818,
1228   PREFIX_VEX_0F3819,
1229   PREFIX_VEX_0F381A,
1230   PREFIX_VEX_0F381C,
1231   PREFIX_VEX_0F381D,
1232   PREFIX_VEX_0F381E,
1233   PREFIX_VEX_0F3820,
1234   PREFIX_VEX_0F3821,
1235   PREFIX_VEX_0F3822,
1236   PREFIX_VEX_0F3823,
1237   PREFIX_VEX_0F3824,
1238   PREFIX_VEX_0F3825,
1239   PREFIX_VEX_0F3828,
1240   PREFIX_VEX_0F3829,
1241   PREFIX_VEX_0F382A,
1242   PREFIX_VEX_0F382B,
1243   PREFIX_VEX_0F382C,
1244   PREFIX_VEX_0F382D,
1245   PREFIX_VEX_0F382E,
1246   PREFIX_VEX_0F382F,
1247   PREFIX_VEX_0F3830,
1248   PREFIX_VEX_0F3831,
1249   PREFIX_VEX_0F3832,
1250   PREFIX_VEX_0F3833,
1251   PREFIX_VEX_0F3834,
1252   PREFIX_VEX_0F3835,
1253   PREFIX_VEX_0F3836,
1254   PREFIX_VEX_0F3837,
1255   PREFIX_VEX_0F3838,
1256   PREFIX_VEX_0F3839,
1257   PREFIX_VEX_0F383A,
1258   PREFIX_VEX_0F383B,
1259   PREFIX_VEX_0F383C,
1260   PREFIX_VEX_0F383D,
1261   PREFIX_VEX_0F383E,
1262   PREFIX_VEX_0F383F,
1263   PREFIX_VEX_0F3840,
1264   PREFIX_VEX_0F3841,
1265   PREFIX_VEX_0F3845,
1266   PREFIX_VEX_0F3846,
1267   PREFIX_VEX_0F3847,
1268   PREFIX_VEX_0F3858,
1269   PREFIX_VEX_0F3859,
1270   PREFIX_VEX_0F385A,
1271   PREFIX_VEX_0F3878,
1272   PREFIX_VEX_0F3879,
1273   PREFIX_VEX_0F388C,
1274   PREFIX_VEX_0F388E,
1275   PREFIX_VEX_0F3890,
1276   PREFIX_VEX_0F3891,
1277   PREFIX_VEX_0F3892,
1278   PREFIX_VEX_0F3893,
1279   PREFIX_VEX_0F3896,
1280   PREFIX_VEX_0F3897,
1281   PREFIX_VEX_0F3898,
1282   PREFIX_VEX_0F3899,
1283   PREFIX_VEX_0F389A,
1284   PREFIX_VEX_0F389B,
1285   PREFIX_VEX_0F389C,
1286   PREFIX_VEX_0F389D,
1287   PREFIX_VEX_0F389E,
1288   PREFIX_VEX_0F389F,
1289   PREFIX_VEX_0F38A6,
1290   PREFIX_VEX_0F38A7,
1291   PREFIX_VEX_0F38A8,
1292   PREFIX_VEX_0F38A9,
1293   PREFIX_VEX_0F38AA,
1294   PREFIX_VEX_0F38AB,
1295   PREFIX_VEX_0F38AC,
1296   PREFIX_VEX_0F38AD,
1297   PREFIX_VEX_0F38AE,
1298   PREFIX_VEX_0F38AF,
1299   PREFIX_VEX_0F38B6,
1300   PREFIX_VEX_0F38B7,
1301   PREFIX_VEX_0F38B8,
1302   PREFIX_VEX_0F38B9,
1303   PREFIX_VEX_0F38BA,
1304   PREFIX_VEX_0F38BB,
1305   PREFIX_VEX_0F38BC,
1306   PREFIX_VEX_0F38BD,
1307   PREFIX_VEX_0F38BE,
1308   PREFIX_VEX_0F38BF,
1309   PREFIX_VEX_0F38DB,
1310   PREFIX_VEX_0F38DC,
1311   PREFIX_VEX_0F38DD,
1312   PREFIX_VEX_0F38DE,
1313   PREFIX_VEX_0F38DF,
1314   PREFIX_VEX_0F38F2,
1315   PREFIX_VEX_0F38F3_REG_1,
1316   PREFIX_VEX_0F38F3_REG_2,
1317   PREFIX_VEX_0F38F3_REG_3,
1318   PREFIX_VEX_0F38F5,
1319   PREFIX_VEX_0F38F6,
1320   PREFIX_VEX_0F38F7,
1321   PREFIX_VEX_0F3A00,
1322   PREFIX_VEX_0F3A01,
1323   PREFIX_VEX_0F3A02,
1324   PREFIX_VEX_0F3A04,
1325   PREFIX_VEX_0F3A05,
1326   PREFIX_VEX_0F3A06,
1327   PREFIX_VEX_0F3A08,
1328   PREFIX_VEX_0F3A09,
1329   PREFIX_VEX_0F3A0A,
1330   PREFIX_VEX_0F3A0B,
1331   PREFIX_VEX_0F3A0C,
1332   PREFIX_VEX_0F3A0D,
1333   PREFIX_VEX_0F3A0E,
1334   PREFIX_VEX_0F3A0F,
1335   PREFIX_VEX_0F3A14,
1336   PREFIX_VEX_0F3A15,
1337   PREFIX_VEX_0F3A16,
1338   PREFIX_VEX_0F3A17,
1339   PREFIX_VEX_0F3A18,
1340   PREFIX_VEX_0F3A19,
1341   PREFIX_VEX_0F3A1D,
1342   PREFIX_VEX_0F3A20,
1343   PREFIX_VEX_0F3A21,
1344   PREFIX_VEX_0F3A22,
1345   PREFIX_VEX_0F3A30,
1346   PREFIX_VEX_0F3A31,
1347   PREFIX_VEX_0F3A32,
1348   PREFIX_VEX_0F3A33,
1349   PREFIX_VEX_0F3A38,
1350   PREFIX_VEX_0F3A39,
1351   PREFIX_VEX_0F3A40,
1352   PREFIX_VEX_0F3A41,
1353   PREFIX_VEX_0F3A42,
1354   PREFIX_VEX_0F3A44,
1355   PREFIX_VEX_0F3A46,
1356   PREFIX_VEX_0F3A48,
1357   PREFIX_VEX_0F3A49,
1358   PREFIX_VEX_0F3A4A,
1359   PREFIX_VEX_0F3A4B,
1360   PREFIX_VEX_0F3A4C,
1361   PREFIX_VEX_0F3A5C,
1362   PREFIX_VEX_0F3A5D,
1363   PREFIX_VEX_0F3A5E,
1364   PREFIX_VEX_0F3A5F,
1365   PREFIX_VEX_0F3A60,
1366   PREFIX_VEX_0F3A61,
1367   PREFIX_VEX_0F3A62,
1368   PREFIX_VEX_0F3A63,
1369   PREFIX_VEX_0F3A68,
1370   PREFIX_VEX_0F3A69,
1371   PREFIX_VEX_0F3A6A,
1372   PREFIX_VEX_0F3A6B,
1373   PREFIX_VEX_0F3A6C,
1374   PREFIX_VEX_0F3A6D,
1375   PREFIX_VEX_0F3A6E,
1376   PREFIX_VEX_0F3A6F,
1377   PREFIX_VEX_0F3A78,
1378   PREFIX_VEX_0F3A79,
1379   PREFIX_VEX_0F3A7A,
1380   PREFIX_VEX_0F3A7B,
1381   PREFIX_VEX_0F3A7C,
1382   PREFIX_VEX_0F3A7D,
1383   PREFIX_VEX_0F3A7E,
1384   PREFIX_VEX_0F3A7F,
1385   PREFIX_VEX_0F3ADF,
1386   PREFIX_VEX_0F3AF0,
1387
1388   PREFIX_EVEX_0F10,
1389   PREFIX_EVEX_0F11,
1390   PREFIX_EVEX_0F12,
1391   PREFIX_EVEX_0F13,
1392   PREFIX_EVEX_0F14,
1393   PREFIX_EVEX_0F15,
1394   PREFIX_EVEX_0F16,
1395   PREFIX_EVEX_0F17,
1396   PREFIX_EVEX_0F28,
1397   PREFIX_EVEX_0F29,
1398   PREFIX_EVEX_0F2A,
1399   PREFIX_EVEX_0F2B,
1400   PREFIX_EVEX_0F2C,
1401   PREFIX_EVEX_0F2D,
1402   PREFIX_EVEX_0F2E,
1403   PREFIX_EVEX_0F2F,
1404   PREFIX_EVEX_0F51,
1405   PREFIX_EVEX_0F54,
1406   PREFIX_EVEX_0F55,
1407   PREFIX_EVEX_0F56,
1408   PREFIX_EVEX_0F57,
1409   PREFIX_EVEX_0F58,
1410   PREFIX_EVEX_0F59,
1411   PREFIX_EVEX_0F5A,
1412   PREFIX_EVEX_0F5B,
1413   PREFIX_EVEX_0F5C,
1414   PREFIX_EVEX_0F5D,
1415   PREFIX_EVEX_0F5E,
1416   PREFIX_EVEX_0F5F,
1417   PREFIX_EVEX_0F60,
1418   PREFIX_EVEX_0F61,
1419   PREFIX_EVEX_0F62,
1420   PREFIX_EVEX_0F63,
1421   PREFIX_EVEX_0F64,
1422   PREFIX_EVEX_0F65,
1423   PREFIX_EVEX_0F66,
1424   PREFIX_EVEX_0F67,
1425   PREFIX_EVEX_0F68,
1426   PREFIX_EVEX_0F69,
1427   PREFIX_EVEX_0F6A,
1428   PREFIX_EVEX_0F6B,
1429   PREFIX_EVEX_0F6C,
1430   PREFIX_EVEX_0F6D,
1431   PREFIX_EVEX_0F6E,
1432   PREFIX_EVEX_0F6F,
1433   PREFIX_EVEX_0F70,
1434   PREFIX_EVEX_0F71_REG_2,
1435   PREFIX_EVEX_0F71_REG_4,
1436   PREFIX_EVEX_0F71_REG_6,
1437   PREFIX_EVEX_0F72_REG_0,
1438   PREFIX_EVEX_0F72_REG_1,
1439   PREFIX_EVEX_0F72_REG_2,
1440   PREFIX_EVEX_0F72_REG_4,
1441   PREFIX_EVEX_0F72_REG_6,
1442   PREFIX_EVEX_0F73_REG_2,
1443   PREFIX_EVEX_0F73_REG_3,
1444   PREFIX_EVEX_0F73_REG_6,
1445   PREFIX_EVEX_0F73_REG_7,
1446   PREFIX_EVEX_0F74,
1447   PREFIX_EVEX_0F75,
1448   PREFIX_EVEX_0F76,
1449   PREFIX_EVEX_0F78,
1450   PREFIX_EVEX_0F79,
1451   PREFIX_EVEX_0F7A,
1452   PREFIX_EVEX_0F7B,
1453   PREFIX_EVEX_0F7E,
1454   PREFIX_EVEX_0F7F,
1455   PREFIX_EVEX_0FC2,
1456   PREFIX_EVEX_0FC4,
1457   PREFIX_EVEX_0FC5,
1458   PREFIX_EVEX_0FC6,
1459   PREFIX_EVEX_0FD1,
1460   PREFIX_EVEX_0FD2,
1461   PREFIX_EVEX_0FD3,
1462   PREFIX_EVEX_0FD4,
1463   PREFIX_EVEX_0FD5,
1464   PREFIX_EVEX_0FD6,
1465   PREFIX_EVEX_0FD8,
1466   PREFIX_EVEX_0FD9,
1467   PREFIX_EVEX_0FDA,
1468   PREFIX_EVEX_0FDB,
1469   PREFIX_EVEX_0FDC,
1470   PREFIX_EVEX_0FDD,
1471   PREFIX_EVEX_0FDE,
1472   PREFIX_EVEX_0FDF,
1473   PREFIX_EVEX_0FE0,
1474   PREFIX_EVEX_0FE1,
1475   PREFIX_EVEX_0FE2,
1476   PREFIX_EVEX_0FE3,
1477   PREFIX_EVEX_0FE4,
1478   PREFIX_EVEX_0FE5,
1479   PREFIX_EVEX_0FE6,
1480   PREFIX_EVEX_0FE7,
1481   PREFIX_EVEX_0FE8,
1482   PREFIX_EVEX_0FE9,
1483   PREFIX_EVEX_0FEA,
1484   PREFIX_EVEX_0FEB,
1485   PREFIX_EVEX_0FEC,
1486   PREFIX_EVEX_0FED,
1487   PREFIX_EVEX_0FEE,
1488   PREFIX_EVEX_0FEF,
1489   PREFIX_EVEX_0FF1,
1490   PREFIX_EVEX_0FF2,
1491   PREFIX_EVEX_0FF3,
1492   PREFIX_EVEX_0FF4,
1493   PREFIX_EVEX_0FF5,
1494   PREFIX_EVEX_0FF6,
1495   PREFIX_EVEX_0FF8,
1496   PREFIX_EVEX_0FF9,
1497   PREFIX_EVEX_0FFA,
1498   PREFIX_EVEX_0FFB,
1499   PREFIX_EVEX_0FFC,
1500   PREFIX_EVEX_0FFD,
1501   PREFIX_EVEX_0FFE,
1502   PREFIX_EVEX_0F3800,
1503   PREFIX_EVEX_0F3804,
1504   PREFIX_EVEX_0F380B,
1505   PREFIX_EVEX_0F380C,
1506   PREFIX_EVEX_0F380D,
1507   PREFIX_EVEX_0F3810,
1508   PREFIX_EVEX_0F3811,
1509   PREFIX_EVEX_0F3812,
1510   PREFIX_EVEX_0F3813,
1511   PREFIX_EVEX_0F3814,
1512   PREFIX_EVEX_0F3815,
1513   PREFIX_EVEX_0F3816,
1514   PREFIX_EVEX_0F3818,
1515   PREFIX_EVEX_0F3819,
1516   PREFIX_EVEX_0F381A,
1517   PREFIX_EVEX_0F381B,
1518   PREFIX_EVEX_0F381C,
1519   PREFIX_EVEX_0F381D,
1520   PREFIX_EVEX_0F381E,
1521   PREFIX_EVEX_0F381F,
1522   PREFIX_EVEX_0F3820,
1523   PREFIX_EVEX_0F3821,
1524   PREFIX_EVEX_0F3822,
1525   PREFIX_EVEX_0F3823,
1526   PREFIX_EVEX_0F3824,
1527   PREFIX_EVEX_0F3825,
1528   PREFIX_EVEX_0F3826,
1529   PREFIX_EVEX_0F3827,
1530   PREFIX_EVEX_0F3828,
1531   PREFIX_EVEX_0F3829,
1532   PREFIX_EVEX_0F382A,
1533   PREFIX_EVEX_0F382B,
1534   PREFIX_EVEX_0F382C,
1535   PREFIX_EVEX_0F382D,
1536   PREFIX_EVEX_0F3830,
1537   PREFIX_EVEX_0F3831,
1538   PREFIX_EVEX_0F3832,
1539   PREFIX_EVEX_0F3833,
1540   PREFIX_EVEX_0F3834,
1541   PREFIX_EVEX_0F3835,
1542   PREFIX_EVEX_0F3836,
1543   PREFIX_EVEX_0F3837,
1544   PREFIX_EVEX_0F3838,
1545   PREFIX_EVEX_0F3839,
1546   PREFIX_EVEX_0F383A,
1547   PREFIX_EVEX_0F383B,
1548   PREFIX_EVEX_0F383C,
1549   PREFIX_EVEX_0F383D,
1550   PREFIX_EVEX_0F383E,
1551   PREFIX_EVEX_0F383F,
1552   PREFIX_EVEX_0F3840,
1553   PREFIX_EVEX_0F3842,
1554   PREFIX_EVEX_0F3843,
1555   PREFIX_EVEX_0F3844,
1556   PREFIX_EVEX_0F3845,
1557   PREFIX_EVEX_0F3846,
1558   PREFIX_EVEX_0F3847,
1559   PREFIX_EVEX_0F384C,
1560   PREFIX_EVEX_0F384D,
1561   PREFIX_EVEX_0F384E,
1562   PREFIX_EVEX_0F384F,
1563   PREFIX_EVEX_0F3852,
1564   PREFIX_EVEX_0F3853,
1565   PREFIX_EVEX_0F3855,
1566   PREFIX_EVEX_0F3858,
1567   PREFIX_EVEX_0F3859,
1568   PREFIX_EVEX_0F385A,
1569   PREFIX_EVEX_0F385B,
1570   PREFIX_EVEX_0F3864,
1571   PREFIX_EVEX_0F3865,
1572   PREFIX_EVEX_0F3866,
1573   PREFIX_EVEX_0F3875,
1574   PREFIX_EVEX_0F3876,
1575   PREFIX_EVEX_0F3877,
1576   PREFIX_EVEX_0F3878,
1577   PREFIX_EVEX_0F3879,
1578   PREFIX_EVEX_0F387A,
1579   PREFIX_EVEX_0F387B,
1580   PREFIX_EVEX_0F387C,
1581   PREFIX_EVEX_0F387D,
1582   PREFIX_EVEX_0F387E,
1583   PREFIX_EVEX_0F387F,
1584   PREFIX_EVEX_0F3883,
1585   PREFIX_EVEX_0F3888,
1586   PREFIX_EVEX_0F3889,
1587   PREFIX_EVEX_0F388A,
1588   PREFIX_EVEX_0F388B,
1589   PREFIX_EVEX_0F388D,
1590   PREFIX_EVEX_0F3890,
1591   PREFIX_EVEX_0F3891,
1592   PREFIX_EVEX_0F3892,
1593   PREFIX_EVEX_0F3893,
1594   PREFIX_EVEX_0F3896,
1595   PREFIX_EVEX_0F3897,
1596   PREFIX_EVEX_0F3898,
1597   PREFIX_EVEX_0F3899,
1598   PREFIX_EVEX_0F389A,
1599   PREFIX_EVEX_0F389B,
1600   PREFIX_EVEX_0F389C,
1601   PREFIX_EVEX_0F389D,
1602   PREFIX_EVEX_0F389E,
1603   PREFIX_EVEX_0F389F,
1604   PREFIX_EVEX_0F38A0,
1605   PREFIX_EVEX_0F38A1,
1606   PREFIX_EVEX_0F38A2,
1607   PREFIX_EVEX_0F38A3,
1608   PREFIX_EVEX_0F38A6,
1609   PREFIX_EVEX_0F38A7,
1610   PREFIX_EVEX_0F38A8,
1611   PREFIX_EVEX_0F38A9,
1612   PREFIX_EVEX_0F38AA,
1613   PREFIX_EVEX_0F38AB,
1614   PREFIX_EVEX_0F38AC,
1615   PREFIX_EVEX_0F38AD,
1616   PREFIX_EVEX_0F38AE,
1617   PREFIX_EVEX_0F38AF,
1618   PREFIX_EVEX_0F38B4,
1619   PREFIX_EVEX_0F38B5,
1620   PREFIX_EVEX_0F38B6,
1621   PREFIX_EVEX_0F38B7,
1622   PREFIX_EVEX_0F38B8,
1623   PREFIX_EVEX_0F38B9,
1624   PREFIX_EVEX_0F38BA,
1625   PREFIX_EVEX_0F38BB,
1626   PREFIX_EVEX_0F38BC,
1627   PREFIX_EVEX_0F38BD,
1628   PREFIX_EVEX_0F38BE,
1629   PREFIX_EVEX_0F38BF,
1630   PREFIX_EVEX_0F38C4,
1631   PREFIX_EVEX_0F38C6_REG_1,
1632   PREFIX_EVEX_0F38C6_REG_2,
1633   PREFIX_EVEX_0F38C6_REG_5,
1634   PREFIX_EVEX_0F38C6_REG_6,
1635   PREFIX_EVEX_0F38C7_REG_1,
1636   PREFIX_EVEX_0F38C7_REG_2,
1637   PREFIX_EVEX_0F38C7_REG_5,
1638   PREFIX_EVEX_0F38C7_REG_6,
1639   PREFIX_EVEX_0F38C8,
1640   PREFIX_EVEX_0F38CA,
1641   PREFIX_EVEX_0F38CB,
1642   PREFIX_EVEX_0F38CC,
1643   PREFIX_EVEX_0F38CD,
1644
1645   PREFIX_EVEX_0F3A00,
1646   PREFIX_EVEX_0F3A01,
1647   PREFIX_EVEX_0F3A03,
1648   PREFIX_EVEX_0F3A04,
1649   PREFIX_EVEX_0F3A05,
1650   PREFIX_EVEX_0F3A08,
1651   PREFIX_EVEX_0F3A09,
1652   PREFIX_EVEX_0F3A0A,
1653   PREFIX_EVEX_0F3A0B,
1654   PREFIX_EVEX_0F3A0F,
1655   PREFIX_EVEX_0F3A14,
1656   PREFIX_EVEX_0F3A15,
1657   PREFIX_EVEX_0F3A16,
1658   PREFIX_EVEX_0F3A17,
1659   PREFIX_EVEX_0F3A18,
1660   PREFIX_EVEX_0F3A19,
1661   PREFIX_EVEX_0F3A1A,
1662   PREFIX_EVEX_0F3A1B,
1663   PREFIX_EVEX_0F3A1D,
1664   PREFIX_EVEX_0F3A1E,
1665   PREFIX_EVEX_0F3A1F,
1666   PREFIX_EVEX_0F3A20,
1667   PREFIX_EVEX_0F3A21,
1668   PREFIX_EVEX_0F3A22,
1669   PREFIX_EVEX_0F3A23,
1670   PREFIX_EVEX_0F3A25,
1671   PREFIX_EVEX_0F3A26,
1672   PREFIX_EVEX_0F3A27,
1673   PREFIX_EVEX_0F3A38,
1674   PREFIX_EVEX_0F3A39,
1675   PREFIX_EVEX_0F3A3A,
1676   PREFIX_EVEX_0F3A3B,
1677   PREFIX_EVEX_0F3A3E,
1678   PREFIX_EVEX_0F3A3F,
1679   PREFIX_EVEX_0F3A42,
1680   PREFIX_EVEX_0F3A43,
1681   PREFIX_EVEX_0F3A50,
1682   PREFIX_EVEX_0F3A51,
1683   PREFIX_EVEX_0F3A54,
1684   PREFIX_EVEX_0F3A55,
1685   PREFIX_EVEX_0F3A56,
1686   PREFIX_EVEX_0F3A57,
1687   PREFIX_EVEX_0F3A66,
1688   PREFIX_EVEX_0F3A67
1689 };
1690
1691 enum
1692 {
1693   X86_64_06 = 0,
1694   X86_64_07,
1695   X86_64_0D,
1696   X86_64_16,
1697   X86_64_17,
1698   X86_64_1E,
1699   X86_64_1F,
1700   X86_64_27,
1701   X86_64_2F,
1702   X86_64_37,
1703   X86_64_3F,
1704   X86_64_60,
1705   X86_64_61,
1706   X86_64_62,
1707   X86_64_63,
1708   X86_64_6D,
1709   X86_64_6F,
1710   X86_64_82,
1711   X86_64_9A,
1712   X86_64_C4,
1713   X86_64_C5,
1714   X86_64_CE,
1715   X86_64_D4,
1716   X86_64_D5,
1717   X86_64_E8,
1718   X86_64_E9,
1719   X86_64_EA,
1720   X86_64_0F01_REG_0,
1721   X86_64_0F01_REG_1,
1722   X86_64_0F01_REG_2,
1723   X86_64_0F01_REG_3
1724 };
1725
1726 enum
1727 {
1728   THREE_BYTE_0F38 = 0,
1729   THREE_BYTE_0F3A
1730 };
1731
1732 enum
1733 {
1734   XOP_08 = 0,
1735   XOP_09,
1736   XOP_0A
1737 };
1738
1739 enum
1740 {
1741   VEX_0F = 0,
1742   VEX_0F38,
1743   VEX_0F3A
1744 };
1745
1746 enum
1747 {
1748   EVEX_0F = 0,
1749   EVEX_0F38,
1750   EVEX_0F3A
1751 };
1752
1753 enum
1754 {
1755   VEX_LEN_0F10_P_1 = 0,
1756   VEX_LEN_0F10_P_3,
1757   VEX_LEN_0F11_P_1,
1758   VEX_LEN_0F11_P_3,
1759   VEX_LEN_0F12_P_0_M_0,
1760   VEX_LEN_0F12_P_0_M_1,
1761   VEX_LEN_0F12_P_2,
1762   VEX_LEN_0F13_M_0,
1763   VEX_LEN_0F16_P_0_M_0,
1764   VEX_LEN_0F16_P_0_M_1,
1765   VEX_LEN_0F16_P_2,
1766   VEX_LEN_0F17_M_0,
1767   VEX_LEN_0F2A_P_1,
1768   VEX_LEN_0F2A_P_3,
1769   VEX_LEN_0F2C_P_1,
1770   VEX_LEN_0F2C_P_3,
1771   VEX_LEN_0F2D_P_1,
1772   VEX_LEN_0F2D_P_3,
1773   VEX_LEN_0F2E_P_0,
1774   VEX_LEN_0F2E_P_2,
1775   VEX_LEN_0F2F_P_0,
1776   VEX_LEN_0F2F_P_2,
1777   VEX_LEN_0F41_P_0,
1778   VEX_LEN_0F41_P_2,
1779   VEX_LEN_0F42_P_0,
1780   VEX_LEN_0F42_P_2,
1781   VEX_LEN_0F44_P_0,
1782   VEX_LEN_0F44_P_2,
1783   VEX_LEN_0F45_P_0,
1784   VEX_LEN_0F45_P_2,
1785   VEX_LEN_0F46_P_0,
1786   VEX_LEN_0F46_P_2,
1787   VEX_LEN_0F47_P_0,
1788   VEX_LEN_0F47_P_2,
1789   VEX_LEN_0F4A_P_0,
1790   VEX_LEN_0F4A_P_2,
1791   VEX_LEN_0F4B_P_0,
1792   VEX_LEN_0F4B_P_2,
1793   VEX_LEN_0F51_P_1,
1794   VEX_LEN_0F51_P_3,
1795   VEX_LEN_0F52_P_1,
1796   VEX_LEN_0F53_P_1,
1797   VEX_LEN_0F58_P_1,
1798   VEX_LEN_0F58_P_3,
1799   VEX_LEN_0F59_P_1,
1800   VEX_LEN_0F59_P_3,
1801   VEX_LEN_0F5A_P_1,
1802   VEX_LEN_0F5A_P_3,
1803   VEX_LEN_0F5C_P_1,
1804   VEX_LEN_0F5C_P_3,
1805   VEX_LEN_0F5D_P_1,
1806   VEX_LEN_0F5D_P_3,
1807   VEX_LEN_0F5E_P_1,
1808   VEX_LEN_0F5E_P_3,
1809   VEX_LEN_0F5F_P_1,
1810   VEX_LEN_0F5F_P_3,
1811   VEX_LEN_0F6E_P_2,
1812   VEX_LEN_0F7E_P_1,
1813   VEX_LEN_0F7E_P_2,
1814   VEX_LEN_0F90_P_0,
1815   VEX_LEN_0F90_P_2,
1816   VEX_LEN_0F91_P_0,
1817   VEX_LEN_0F91_P_2,
1818   VEX_LEN_0F92_P_0,
1819   VEX_LEN_0F92_P_2,
1820   VEX_LEN_0F92_P_3,
1821   VEX_LEN_0F93_P_0,
1822   VEX_LEN_0F93_P_2,
1823   VEX_LEN_0F93_P_3,
1824   VEX_LEN_0F98_P_0,
1825   VEX_LEN_0F98_P_2,
1826   VEX_LEN_0F99_P_0,
1827   VEX_LEN_0F99_P_2,
1828   VEX_LEN_0FAE_R_2_M_0,
1829   VEX_LEN_0FAE_R_3_M_0,
1830   VEX_LEN_0FC2_P_1,
1831   VEX_LEN_0FC2_P_3,
1832   VEX_LEN_0FC4_P_2,
1833   VEX_LEN_0FC5_P_2,
1834   VEX_LEN_0FD6_P_2,
1835   VEX_LEN_0FF7_P_2,
1836   VEX_LEN_0F3816_P_2,
1837   VEX_LEN_0F3819_P_2,
1838   VEX_LEN_0F381A_P_2_M_0,
1839   VEX_LEN_0F3836_P_2,
1840   VEX_LEN_0F3841_P_2,
1841   VEX_LEN_0F385A_P_2_M_0,
1842   VEX_LEN_0F38DB_P_2,
1843   VEX_LEN_0F38DC_P_2,
1844   VEX_LEN_0F38DD_P_2,
1845   VEX_LEN_0F38DE_P_2,
1846   VEX_LEN_0F38DF_P_2,
1847   VEX_LEN_0F38F2_P_0,
1848   VEX_LEN_0F38F3_R_1_P_0,
1849   VEX_LEN_0F38F3_R_2_P_0,
1850   VEX_LEN_0F38F3_R_3_P_0,
1851   VEX_LEN_0F38F5_P_0,
1852   VEX_LEN_0F38F5_P_1,
1853   VEX_LEN_0F38F5_P_3,
1854   VEX_LEN_0F38F6_P_3,
1855   VEX_LEN_0F38F7_P_0,
1856   VEX_LEN_0F38F7_P_1,
1857   VEX_LEN_0F38F7_P_2,
1858   VEX_LEN_0F38F7_P_3,
1859   VEX_LEN_0F3A00_P_2,
1860   VEX_LEN_0F3A01_P_2,
1861   VEX_LEN_0F3A06_P_2,
1862   VEX_LEN_0F3A0A_P_2,
1863   VEX_LEN_0F3A0B_P_2,
1864   VEX_LEN_0F3A14_P_2,
1865   VEX_LEN_0F3A15_P_2,
1866   VEX_LEN_0F3A16_P_2,
1867   VEX_LEN_0F3A17_P_2,
1868   VEX_LEN_0F3A18_P_2,
1869   VEX_LEN_0F3A19_P_2,
1870   VEX_LEN_0F3A20_P_2,
1871   VEX_LEN_0F3A21_P_2,
1872   VEX_LEN_0F3A22_P_2,
1873   VEX_LEN_0F3A30_P_2,
1874   VEX_LEN_0F3A31_P_2,
1875   VEX_LEN_0F3A32_P_2,
1876   VEX_LEN_0F3A33_P_2,
1877   VEX_LEN_0F3A38_P_2,
1878   VEX_LEN_0F3A39_P_2,
1879   VEX_LEN_0F3A41_P_2,
1880   VEX_LEN_0F3A44_P_2,
1881   VEX_LEN_0F3A46_P_2,
1882   VEX_LEN_0F3A60_P_2,
1883   VEX_LEN_0F3A61_P_2,
1884   VEX_LEN_0F3A62_P_2,
1885   VEX_LEN_0F3A63_P_2,
1886   VEX_LEN_0F3A6A_P_2,
1887   VEX_LEN_0F3A6B_P_2,
1888   VEX_LEN_0F3A6E_P_2,
1889   VEX_LEN_0F3A6F_P_2,
1890   VEX_LEN_0F3A7A_P_2,
1891   VEX_LEN_0F3A7B_P_2,
1892   VEX_LEN_0F3A7E_P_2,
1893   VEX_LEN_0F3A7F_P_2,
1894   VEX_LEN_0F3ADF_P_2,
1895   VEX_LEN_0F3AF0_P_3,
1896   VEX_LEN_0FXOP_08_CC,
1897   VEX_LEN_0FXOP_08_CD,
1898   VEX_LEN_0FXOP_08_CE,
1899   VEX_LEN_0FXOP_08_CF,
1900   VEX_LEN_0FXOP_08_EC,
1901   VEX_LEN_0FXOP_08_ED,
1902   VEX_LEN_0FXOP_08_EE,
1903   VEX_LEN_0FXOP_08_EF,
1904   VEX_LEN_0FXOP_09_80,
1905   VEX_LEN_0FXOP_09_81
1906 };
1907
1908 enum
1909 {
1910   VEX_W_0F10_P_0 = 0,
1911   VEX_W_0F10_P_1,
1912   VEX_W_0F10_P_2,
1913   VEX_W_0F10_P_3,
1914   VEX_W_0F11_P_0,
1915   VEX_W_0F11_P_1,
1916   VEX_W_0F11_P_2,
1917   VEX_W_0F11_P_3,
1918   VEX_W_0F12_P_0_M_0,
1919   VEX_W_0F12_P_0_M_1,
1920   VEX_W_0F12_P_1,
1921   VEX_W_0F12_P_2,
1922   VEX_W_0F12_P_3,
1923   VEX_W_0F13_M_0,
1924   VEX_W_0F14,
1925   VEX_W_0F15,
1926   VEX_W_0F16_P_0_M_0,
1927   VEX_W_0F16_P_0_M_1,
1928   VEX_W_0F16_P_1,
1929   VEX_W_0F16_P_2,
1930   VEX_W_0F17_M_0,
1931   VEX_W_0F28,
1932   VEX_W_0F29,
1933   VEX_W_0F2B_M_0,
1934   VEX_W_0F2E_P_0,
1935   VEX_W_0F2E_P_2,
1936   VEX_W_0F2F_P_0,
1937   VEX_W_0F2F_P_2,
1938   VEX_W_0F41_P_0_LEN_1,
1939   VEX_W_0F41_P_2_LEN_1,
1940   VEX_W_0F42_P_0_LEN_1,
1941   VEX_W_0F42_P_2_LEN_1,
1942   VEX_W_0F44_P_0_LEN_0,
1943   VEX_W_0F44_P_2_LEN_0,
1944   VEX_W_0F45_P_0_LEN_1,
1945   VEX_W_0F45_P_2_LEN_1,
1946   VEX_W_0F46_P_0_LEN_1,
1947   VEX_W_0F46_P_2_LEN_1,
1948   VEX_W_0F47_P_0_LEN_1,
1949   VEX_W_0F47_P_2_LEN_1,
1950   VEX_W_0F4A_P_0_LEN_1,
1951   VEX_W_0F4A_P_2_LEN_1,
1952   VEX_W_0F4B_P_0_LEN_1,
1953   VEX_W_0F4B_P_2_LEN_1,
1954   VEX_W_0F50_M_0,
1955   VEX_W_0F51_P_0,
1956   VEX_W_0F51_P_1,
1957   VEX_W_0F51_P_2,
1958   VEX_W_0F51_P_3,
1959   VEX_W_0F52_P_0,
1960   VEX_W_0F52_P_1,
1961   VEX_W_0F53_P_0,
1962   VEX_W_0F53_P_1,
1963   VEX_W_0F58_P_0,
1964   VEX_W_0F58_P_1,
1965   VEX_W_0F58_P_2,
1966   VEX_W_0F58_P_3,
1967   VEX_W_0F59_P_0,
1968   VEX_W_0F59_P_1,
1969   VEX_W_0F59_P_2,
1970   VEX_W_0F59_P_3,
1971   VEX_W_0F5A_P_0,
1972   VEX_W_0F5A_P_1,
1973   VEX_W_0F5A_P_3,
1974   VEX_W_0F5B_P_0,
1975   VEX_W_0F5B_P_1,
1976   VEX_W_0F5B_P_2,
1977   VEX_W_0F5C_P_0,
1978   VEX_W_0F5C_P_1,
1979   VEX_W_0F5C_P_2,
1980   VEX_W_0F5C_P_3,
1981   VEX_W_0F5D_P_0,
1982   VEX_W_0F5D_P_1,
1983   VEX_W_0F5D_P_2,
1984   VEX_W_0F5D_P_3,
1985   VEX_W_0F5E_P_0,
1986   VEX_W_0F5E_P_1,
1987   VEX_W_0F5E_P_2,
1988   VEX_W_0F5E_P_3,
1989   VEX_W_0F5F_P_0,
1990   VEX_W_0F5F_P_1,
1991   VEX_W_0F5F_P_2,
1992   VEX_W_0F5F_P_3,
1993   VEX_W_0F60_P_2,
1994   VEX_W_0F61_P_2,
1995   VEX_W_0F62_P_2,
1996   VEX_W_0F63_P_2,
1997   VEX_W_0F64_P_2,
1998   VEX_W_0F65_P_2,
1999   VEX_W_0F66_P_2,
2000   VEX_W_0F67_P_2,
2001   VEX_W_0F68_P_2,
2002   VEX_W_0F69_P_2,
2003   VEX_W_0F6A_P_2,
2004   VEX_W_0F6B_P_2,
2005   VEX_W_0F6C_P_2,
2006   VEX_W_0F6D_P_2,
2007   VEX_W_0F6F_P_1,
2008   VEX_W_0F6F_P_2,
2009   VEX_W_0F70_P_1,
2010   VEX_W_0F70_P_2,
2011   VEX_W_0F70_P_3,
2012   VEX_W_0F71_R_2_P_2,
2013   VEX_W_0F71_R_4_P_2,
2014   VEX_W_0F71_R_6_P_2,
2015   VEX_W_0F72_R_2_P_2,
2016   VEX_W_0F72_R_4_P_2,
2017   VEX_W_0F72_R_6_P_2,
2018   VEX_W_0F73_R_2_P_2,
2019   VEX_W_0F73_R_3_P_2,
2020   VEX_W_0F73_R_6_P_2,
2021   VEX_W_0F73_R_7_P_2,
2022   VEX_W_0F74_P_2,
2023   VEX_W_0F75_P_2,
2024   VEX_W_0F76_P_2,
2025   VEX_W_0F77_P_0,
2026   VEX_W_0F7C_P_2,
2027   VEX_W_0F7C_P_3,
2028   VEX_W_0F7D_P_2,
2029   VEX_W_0F7D_P_3,
2030   VEX_W_0F7E_P_1,
2031   VEX_W_0F7F_P_1,
2032   VEX_W_0F7F_P_2,
2033   VEX_W_0F90_P_0_LEN_0,
2034   VEX_W_0F90_P_2_LEN_0,
2035   VEX_W_0F91_P_0_LEN_0,
2036   VEX_W_0F91_P_2_LEN_0,
2037   VEX_W_0F92_P_0_LEN_0,
2038   VEX_W_0F92_P_2_LEN_0,
2039   VEX_W_0F92_P_3_LEN_0,
2040   VEX_W_0F93_P_0_LEN_0,
2041   VEX_W_0F93_P_2_LEN_0,
2042   VEX_W_0F93_P_3_LEN_0,
2043   VEX_W_0F98_P_0_LEN_0,
2044   VEX_W_0F98_P_2_LEN_0,
2045   VEX_W_0F99_P_0_LEN_0,
2046   VEX_W_0F99_P_2_LEN_0,
2047   VEX_W_0FAE_R_2_M_0,
2048   VEX_W_0FAE_R_3_M_0,
2049   VEX_W_0FC2_P_0,
2050   VEX_W_0FC2_P_1,
2051   VEX_W_0FC2_P_2,
2052   VEX_W_0FC2_P_3,
2053   VEX_W_0FC4_P_2,
2054   VEX_W_0FC5_P_2,
2055   VEX_W_0FD0_P_2,
2056   VEX_W_0FD0_P_3,
2057   VEX_W_0FD1_P_2,
2058   VEX_W_0FD2_P_2,
2059   VEX_W_0FD3_P_2,
2060   VEX_W_0FD4_P_2,
2061   VEX_W_0FD5_P_2,
2062   VEX_W_0FD6_P_2,
2063   VEX_W_0FD7_P_2_M_1,
2064   VEX_W_0FD8_P_2,
2065   VEX_W_0FD9_P_2,
2066   VEX_W_0FDA_P_2,
2067   VEX_W_0FDB_P_2,
2068   VEX_W_0FDC_P_2,
2069   VEX_W_0FDD_P_2,
2070   VEX_W_0FDE_P_2,
2071   VEX_W_0FDF_P_2,
2072   VEX_W_0FE0_P_2,
2073   VEX_W_0FE1_P_2,
2074   VEX_W_0FE2_P_2,
2075   VEX_W_0FE3_P_2,
2076   VEX_W_0FE4_P_2,
2077   VEX_W_0FE5_P_2,
2078   VEX_W_0FE6_P_1,
2079   VEX_W_0FE6_P_2,
2080   VEX_W_0FE6_P_3,
2081   VEX_W_0FE7_P_2_M_0,
2082   VEX_W_0FE8_P_2,
2083   VEX_W_0FE9_P_2,
2084   VEX_W_0FEA_P_2,
2085   VEX_W_0FEB_P_2,
2086   VEX_W_0FEC_P_2,
2087   VEX_W_0FED_P_2,
2088   VEX_W_0FEE_P_2,
2089   VEX_W_0FEF_P_2,
2090   VEX_W_0FF0_P_3_M_0,
2091   VEX_W_0FF1_P_2,
2092   VEX_W_0FF2_P_2,
2093   VEX_W_0FF3_P_2,
2094   VEX_W_0FF4_P_2,
2095   VEX_W_0FF5_P_2,
2096   VEX_W_0FF6_P_2,
2097   VEX_W_0FF7_P_2,
2098   VEX_W_0FF8_P_2,
2099   VEX_W_0FF9_P_2,
2100   VEX_W_0FFA_P_2,
2101   VEX_W_0FFB_P_2,
2102   VEX_W_0FFC_P_2,
2103   VEX_W_0FFD_P_2,
2104   VEX_W_0FFE_P_2,
2105   VEX_W_0F3800_P_2,
2106   VEX_W_0F3801_P_2,
2107   VEX_W_0F3802_P_2,
2108   VEX_W_0F3803_P_2,
2109   VEX_W_0F3804_P_2,
2110   VEX_W_0F3805_P_2,
2111   VEX_W_0F3806_P_2,
2112   VEX_W_0F3807_P_2,
2113   VEX_W_0F3808_P_2,
2114   VEX_W_0F3809_P_2,
2115   VEX_W_0F380A_P_2,
2116   VEX_W_0F380B_P_2,
2117   VEX_W_0F380C_P_2,
2118   VEX_W_0F380D_P_2,
2119   VEX_W_0F380E_P_2,
2120   VEX_W_0F380F_P_2,
2121   VEX_W_0F3816_P_2,
2122   VEX_W_0F3817_P_2,
2123   VEX_W_0F3818_P_2,
2124   VEX_W_0F3819_P_2,
2125   VEX_W_0F381A_P_2_M_0,
2126   VEX_W_0F381C_P_2,
2127   VEX_W_0F381D_P_2,
2128   VEX_W_0F381E_P_2,
2129   VEX_W_0F3820_P_2,
2130   VEX_W_0F3821_P_2,
2131   VEX_W_0F3822_P_2,
2132   VEX_W_0F3823_P_2,
2133   VEX_W_0F3824_P_2,
2134   VEX_W_0F3825_P_2,
2135   VEX_W_0F3828_P_2,
2136   VEX_W_0F3829_P_2,
2137   VEX_W_0F382A_P_2_M_0,
2138   VEX_W_0F382B_P_2,
2139   VEX_W_0F382C_P_2_M_0,
2140   VEX_W_0F382D_P_2_M_0,
2141   VEX_W_0F382E_P_2_M_0,
2142   VEX_W_0F382F_P_2_M_0,
2143   VEX_W_0F3830_P_2,
2144   VEX_W_0F3831_P_2,
2145   VEX_W_0F3832_P_2,
2146   VEX_W_0F3833_P_2,
2147   VEX_W_0F3834_P_2,
2148   VEX_W_0F3835_P_2,
2149   VEX_W_0F3836_P_2,
2150   VEX_W_0F3837_P_2,
2151   VEX_W_0F3838_P_2,
2152   VEX_W_0F3839_P_2,
2153   VEX_W_0F383A_P_2,
2154   VEX_W_0F383B_P_2,
2155   VEX_W_0F383C_P_2,
2156   VEX_W_0F383D_P_2,
2157   VEX_W_0F383E_P_2,
2158   VEX_W_0F383F_P_2,
2159   VEX_W_0F3840_P_2,
2160   VEX_W_0F3841_P_2,
2161   VEX_W_0F3846_P_2,
2162   VEX_W_0F3858_P_2,
2163   VEX_W_0F3859_P_2,
2164   VEX_W_0F385A_P_2_M_0,
2165   VEX_W_0F3878_P_2,
2166   VEX_W_0F3879_P_2,
2167   VEX_W_0F38DB_P_2,
2168   VEX_W_0F38DC_P_2,
2169   VEX_W_0F38DD_P_2,
2170   VEX_W_0F38DE_P_2,
2171   VEX_W_0F38DF_P_2,
2172   VEX_W_0F3A00_P_2,
2173   VEX_W_0F3A01_P_2,
2174   VEX_W_0F3A02_P_2,
2175   VEX_W_0F3A04_P_2,
2176   VEX_W_0F3A05_P_2,
2177   VEX_W_0F3A06_P_2,
2178   VEX_W_0F3A08_P_2,
2179   VEX_W_0F3A09_P_2,
2180   VEX_W_0F3A0A_P_2,
2181   VEX_W_0F3A0B_P_2,
2182   VEX_W_0F3A0C_P_2,
2183   VEX_W_0F3A0D_P_2,
2184   VEX_W_0F3A0E_P_2,
2185   VEX_W_0F3A0F_P_2,
2186   VEX_W_0F3A14_P_2,
2187   VEX_W_0F3A15_P_2,
2188   VEX_W_0F3A18_P_2,
2189   VEX_W_0F3A19_P_2,
2190   VEX_W_0F3A20_P_2,
2191   VEX_W_0F3A21_P_2,
2192   VEX_W_0F3A30_P_2_LEN_0,
2193   VEX_W_0F3A31_P_2_LEN_0,
2194   VEX_W_0F3A32_P_2_LEN_0,
2195   VEX_W_0F3A33_P_2_LEN_0,
2196   VEX_W_0F3A38_P_2,
2197   VEX_W_0F3A39_P_2,
2198   VEX_W_0F3A40_P_2,
2199   VEX_W_0F3A41_P_2,
2200   VEX_W_0F3A42_P_2,
2201   VEX_W_0F3A44_P_2,
2202   VEX_W_0F3A46_P_2,
2203   VEX_W_0F3A48_P_2,
2204   VEX_W_0F3A49_P_2,
2205   VEX_W_0F3A4A_P_2,
2206   VEX_W_0F3A4B_P_2,
2207   VEX_W_0F3A4C_P_2,
2208   VEX_W_0F3A62_P_2,
2209   VEX_W_0F3A63_P_2,
2210   VEX_W_0F3ADF_P_2,
2211
2212   EVEX_W_0F10_P_0,
2213   EVEX_W_0F10_P_1_M_0,
2214   EVEX_W_0F10_P_1_M_1,
2215   EVEX_W_0F10_P_2,
2216   EVEX_W_0F10_P_3_M_0,
2217   EVEX_W_0F10_P_3_M_1,
2218   EVEX_W_0F11_P_0,
2219   EVEX_W_0F11_P_1_M_0,
2220   EVEX_W_0F11_P_1_M_1,
2221   EVEX_W_0F11_P_2,
2222   EVEX_W_0F11_P_3_M_0,
2223   EVEX_W_0F11_P_3_M_1,
2224   EVEX_W_0F12_P_0_M_0,
2225   EVEX_W_0F12_P_0_M_1,
2226   EVEX_W_0F12_P_1,
2227   EVEX_W_0F12_P_2,
2228   EVEX_W_0F12_P_3,
2229   EVEX_W_0F13_P_0,
2230   EVEX_W_0F13_P_2,
2231   EVEX_W_0F14_P_0,
2232   EVEX_W_0F14_P_2,
2233   EVEX_W_0F15_P_0,
2234   EVEX_W_0F15_P_2,
2235   EVEX_W_0F16_P_0_M_0,
2236   EVEX_W_0F16_P_0_M_1,
2237   EVEX_W_0F16_P_1,
2238   EVEX_W_0F16_P_2,
2239   EVEX_W_0F17_P_0,
2240   EVEX_W_0F17_P_2,
2241   EVEX_W_0F28_P_0,
2242   EVEX_W_0F28_P_2,
2243   EVEX_W_0F29_P_0,
2244   EVEX_W_0F29_P_2,
2245   EVEX_W_0F2A_P_1,
2246   EVEX_W_0F2A_P_3,
2247   EVEX_W_0F2B_P_0,
2248   EVEX_W_0F2B_P_2,
2249   EVEX_W_0F2E_P_0,
2250   EVEX_W_0F2E_P_2,
2251   EVEX_W_0F2F_P_0,
2252   EVEX_W_0F2F_P_2,
2253   EVEX_W_0F51_P_0,
2254   EVEX_W_0F51_P_1,
2255   EVEX_W_0F51_P_2,
2256   EVEX_W_0F51_P_3,
2257   EVEX_W_0F54_P_0,
2258   EVEX_W_0F54_P_2,
2259   EVEX_W_0F55_P_0,
2260   EVEX_W_0F55_P_2,
2261   EVEX_W_0F56_P_0,
2262   EVEX_W_0F56_P_2,
2263   EVEX_W_0F57_P_0,
2264   EVEX_W_0F57_P_2,
2265   EVEX_W_0F58_P_0,
2266   EVEX_W_0F58_P_1,
2267   EVEX_W_0F58_P_2,
2268   EVEX_W_0F58_P_3,
2269   EVEX_W_0F59_P_0,
2270   EVEX_W_0F59_P_1,
2271   EVEX_W_0F59_P_2,
2272   EVEX_W_0F59_P_3,
2273   EVEX_W_0F5A_P_0,
2274   EVEX_W_0F5A_P_1,
2275   EVEX_W_0F5A_P_2,
2276   EVEX_W_0F5A_P_3,
2277   EVEX_W_0F5B_P_0,
2278   EVEX_W_0F5B_P_1,
2279   EVEX_W_0F5B_P_2,
2280   EVEX_W_0F5C_P_0,
2281   EVEX_W_0F5C_P_1,
2282   EVEX_W_0F5C_P_2,
2283   EVEX_W_0F5C_P_3,
2284   EVEX_W_0F5D_P_0,
2285   EVEX_W_0F5D_P_1,
2286   EVEX_W_0F5D_P_2,
2287   EVEX_W_0F5D_P_3,
2288   EVEX_W_0F5E_P_0,
2289   EVEX_W_0F5E_P_1,
2290   EVEX_W_0F5E_P_2,
2291   EVEX_W_0F5E_P_3,
2292   EVEX_W_0F5F_P_0,
2293   EVEX_W_0F5F_P_1,
2294   EVEX_W_0F5F_P_2,
2295   EVEX_W_0F5F_P_3,
2296   EVEX_W_0F62_P_2,
2297   EVEX_W_0F66_P_2,
2298   EVEX_W_0F6A_P_2,
2299   EVEX_W_0F6B_P_2,
2300   EVEX_W_0F6C_P_2,
2301   EVEX_W_0F6D_P_2,
2302   EVEX_W_0F6E_P_2,
2303   EVEX_W_0F6F_P_1,
2304   EVEX_W_0F6F_P_2,
2305   EVEX_W_0F6F_P_3,
2306   EVEX_W_0F70_P_2,
2307   EVEX_W_0F72_R_2_P_2,
2308   EVEX_W_0F72_R_6_P_2,
2309   EVEX_W_0F73_R_2_P_2,
2310   EVEX_W_0F73_R_6_P_2,
2311   EVEX_W_0F76_P_2,
2312   EVEX_W_0F78_P_0,
2313   EVEX_W_0F78_P_2,
2314   EVEX_W_0F79_P_0,
2315   EVEX_W_0F79_P_2,
2316   EVEX_W_0F7A_P_1,
2317   EVEX_W_0F7A_P_2,
2318   EVEX_W_0F7A_P_3,
2319   EVEX_W_0F7B_P_1,
2320   EVEX_W_0F7B_P_2,
2321   EVEX_W_0F7B_P_3,
2322   EVEX_W_0F7E_P_1,
2323   EVEX_W_0F7E_P_2,
2324   EVEX_W_0F7F_P_1,
2325   EVEX_W_0F7F_P_2,
2326   EVEX_W_0F7F_P_3,
2327   EVEX_W_0FC2_P_0,
2328   EVEX_W_0FC2_P_1,
2329   EVEX_W_0FC2_P_2,
2330   EVEX_W_0FC2_P_3,
2331   EVEX_W_0FC6_P_0,
2332   EVEX_W_0FC6_P_2,
2333   EVEX_W_0FD2_P_2,
2334   EVEX_W_0FD3_P_2,
2335   EVEX_W_0FD4_P_2,
2336   EVEX_W_0FD6_P_2,
2337   EVEX_W_0FE6_P_1,
2338   EVEX_W_0FE6_P_2,
2339   EVEX_W_0FE6_P_3,
2340   EVEX_W_0FE7_P_2,
2341   EVEX_W_0FF2_P_2,
2342   EVEX_W_0FF3_P_2,
2343   EVEX_W_0FF4_P_2,
2344   EVEX_W_0FFA_P_2,
2345   EVEX_W_0FFB_P_2,
2346   EVEX_W_0FFE_P_2,
2347   EVEX_W_0F380C_P_2,
2348   EVEX_W_0F380D_P_2,
2349   EVEX_W_0F3810_P_1,
2350   EVEX_W_0F3810_P_2,
2351   EVEX_W_0F3811_P_1,
2352   EVEX_W_0F3811_P_2,
2353   EVEX_W_0F3812_P_1,
2354   EVEX_W_0F3812_P_2,
2355   EVEX_W_0F3813_P_1,
2356   EVEX_W_0F3813_P_2,
2357   EVEX_W_0F3814_P_1,
2358   EVEX_W_0F3815_P_1,
2359   EVEX_W_0F3818_P_2,
2360   EVEX_W_0F3819_P_2,
2361   EVEX_W_0F381A_P_2,
2362   EVEX_W_0F381B_P_2,
2363   EVEX_W_0F381E_P_2,
2364   EVEX_W_0F381F_P_2,
2365   EVEX_W_0F3820_P_1,
2366   EVEX_W_0F3821_P_1,
2367   EVEX_W_0F3822_P_1,
2368   EVEX_W_0F3823_P_1,
2369   EVEX_W_0F3824_P_1,
2370   EVEX_W_0F3825_P_1,
2371   EVEX_W_0F3825_P_2,
2372   EVEX_W_0F3826_P_1,
2373   EVEX_W_0F3826_P_2,
2374   EVEX_W_0F3828_P_1,
2375   EVEX_W_0F3828_P_2,
2376   EVEX_W_0F3829_P_1,
2377   EVEX_W_0F3829_P_2,
2378   EVEX_W_0F382A_P_1,
2379   EVEX_W_0F382A_P_2,
2380   EVEX_W_0F382B_P_2,
2381   EVEX_W_0F3830_P_1,
2382   EVEX_W_0F3831_P_1,
2383   EVEX_W_0F3832_P_1,
2384   EVEX_W_0F3833_P_1,
2385   EVEX_W_0F3834_P_1,
2386   EVEX_W_0F3835_P_1,
2387   EVEX_W_0F3835_P_2,
2388   EVEX_W_0F3837_P_2,
2389   EVEX_W_0F3838_P_1,
2390   EVEX_W_0F3839_P_1,
2391   EVEX_W_0F383A_P_1,
2392   EVEX_W_0F3840_P_2,
2393   EVEX_W_0F3855_P_2,
2394   EVEX_W_0F3858_P_2,
2395   EVEX_W_0F3859_P_2,
2396   EVEX_W_0F385A_P_2,
2397   EVEX_W_0F385B_P_2,
2398   EVEX_W_0F3866_P_2,
2399   EVEX_W_0F3875_P_2,
2400   EVEX_W_0F3878_P_2,
2401   EVEX_W_0F3879_P_2,
2402   EVEX_W_0F387A_P_2,
2403   EVEX_W_0F387B_P_2,
2404   EVEX_W_0F387D_P_2,
2405   EVEX_W_0F3883_P_2,
2406   EVEX_W_0F388D_P_2,
2407   EVEX_W_0F3891_P_2,
2408   EVEX_W_0F3893_P_2,
2409   EVEX_W_0F38A1_P_2,
2410   EVEX_W_0F38A3_P_2,
2411   EVEX_W_0F38C7_R_1_P_2,
2412   EVEX_W_0F38C7_R_2_P_2,
2413   EVEX_W_0F38C7_R_5_P_2,
2414   EVEX_W_0F38C7_R_6_P_2,
2415
2416   EVEX_W_0F3A00_P_2,
2417   EVEX_W_0F3A01_P_2,
2418   EVEX_W_0F3A04_P_2,
2419   EVEX_W_0F3A05_P_2,
2420   EVEX_W_0F3A08_P_2,
2421   EVEX_W_0F3A09_P_2,
2422   EVEX_W_0F3A0A_P_2,
2423   EVEX_W_0F3A0B_P_2,
2424   EVEX_W_0F3A16_P_2,
2425   EVEX_W_0F3A18_P_2,
2426   EVEX_W_0F3A19_P_2,
2427   EVEX_W_0F3A1A_P_2,
2428   EVEX_W_0F3A1B_P_2,
2429   EVEX_W_0F3A1D_P_2,
2430   EVEX_W_0F3A21_P_2,
2431   EVEX_W_0F3A22_P_2,
2432   EVEX_W_0F3A23_P_2,
2433   EVEX_W_0F3A38_P_2,
2434   EVEX_W_0F3A39_P_2,
2435   EVEX_W_0F3A3A_P_2,
2436   EVEX_W_0F3A3B_P_2,
2437   EVEX_W_0F3A3E_P_2,
2438   EVEX_W_0F3A3F_P_2,
2439   EVEX_W_0F3A42_P_2,
2440   EVEX_W_0F3A43_P_2,
2441   EVEX_W_0F3A50_P_2,
2442   EVEX_W_0F3A51_P_2,
2443   EVEX_W_0F3A56_P_2,
2444   EVEX_W_0F3A57_P_2,
2445   EVEX_W_0F3A66_P_2,
2446   EVEX_W_0F3A67_P_2
2447 };
2448
2449 typedef void (*op_rtn) (int bytemode, int sizeflag);
2450
2451 struct dis386 {
2452   const char *name;
2453   struct
2454     {
2455       op_rtn rtn;
2456       int bytemode;
2457     } op[MAX_OPERANDS];
2458   unsigned int prefix_requirement;
2459 };
2460
2461 /* Upper case letters in the instruction names here are macros.
2462    'A' => print 'b' if no register operands or suffix_always is true
2463    'B' => print 'b' if suffix_always is true
2464    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2465           size prefix
2466    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2467           suffix_always is true
2468    'E' => print 'e' if 32-bit form of jcxz
2469    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2470    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2471    'H' => print ",pt" or ",pn" branch hint
2472    'I' => honor following macro letter even in Intel mode (implemented only
2473           for some of the macro letters)
2474    'J' => print 'l'
2475    'K' => print 'd' or 'q' if rex prefix is present.
2476    'L' => print 'l' if suffix_always is true
2477    'M' => print 'r' if intel_mnemonic is false.
2478    'N' => print 'n' if instruction has no wait "prefix"
2479    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2480    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2481           or suffix_always is true.  print 'q' if rex prefix is present.
2482    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2483           is true
2484    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2485    'S' => print 'w', 'l' or 'q' if suffix_always is true
2486    'T' => print 'q' in 64bit mode if instruction has no operand size
2487           prefix and behave as 'P' otherwise
2488    'U' => print 'q' in 64bit mode if instruction has no operand size
2489           prefix and behave as 'Q' otherwise
2490    'V' => print 'q' in 64bit mode if instruction has no operand size
2491           prefix and behave as 'S' otherwise
2492    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2493    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2494    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2495           suffix_always is true.
2496    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2497    '!' => change condition from true to false or from false to true.
2498    '%' => add 1 upper case letter to the macro.
2499    '^' => print 'w' or 'l' depending on operand size prefix or
2500           suffix_always is true (lcall/ljmp).
2501    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2502           on operand size prefix.
2503    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2504           has no operand size prefix for AMD64 ISA, behave as 'P'
2505           otherwise
2506
2507    2 upper case letter macros:
2508    "XY" => print 'x' or 'y' if suffix_always is true or no register
2509            operands and no broadcast.
2510    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2511            register operands and no broadcast.
2512    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2513    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2514            or suffix_always is true
2515    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2516    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2517    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2518    "LW" => print 'd', 'q' depending on the VEX.W bit
2519    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2520            an operand size prefix, or suffix_always is true.  print
2521            'q' if rex prefix is present.
2522
2523    Many of the above letters print nothing in Intel mode.  See "putop"
2524    for the details.
2525
2526    Braces '{' and '}', and vertical bars '|', indicate alternative
2527    mnemonic strings for AT&T and Intel.  */
2528
2529 static const struct dis386 dis386[] = {
2530   /* 00 */
2531   { "addB",             { Ebh1, Gb }, 0 },
2532   { "addS",             { Evh1, Gv }, 0 },
2533   { "addB",             { Gb, EbS }, 0 },
2534   { "addS",             { Gv, EvS }, 0 },
2535   { "addB",             { AL, Ib }, 0 },
2536   { "addS",             { eAX, Iv }, 0 },
2537   { X86_64_TABLE (X86_64_06) },
2538   { X86_64_TABLE (X86_64_07) },
2539   /* 08 */
2540   { "orB",              { Ebh1, Gb }, 0 },
2541   { "orS",              { Evh1, Gv }, 0 },
2542   { "orB",              { Gb, EbS }, 0 },
2543   { "orS",              { Gv, EvS }, 0 },
2544   { "orB",              { AL, Ib }, 0 },
2545   { "orS",              { eAX, Iv }, 0 },
2546   { X86_64_TABLE (X86_64_0D) },
2547   { Bad_Opcode },       /* 0x0f extended opcode escape */
2548   /* 10 */
2549   { "adcB",             { Ebh1, Gb }, 0 },
2550   { "adcS",             { Evh1, Gv }, 0 },
2551   { "adcB",             { Gb, EbS }, 0 },
2552   { "adcS",             { Gv, EvS }, 0 },
2553   { "adcB",             { AL, Ib }, 0 },
2554   { "adcS",             { eAX, Iv }, 0 },
2555   { X86_64_TABLE (X86_64_16) },
2556   { X86_64_TABLE (X86_64_17) },
2557   /* 18 */
2558   { "sbbB",             { Ebh1, Gb }, 0 },
2559   { "sbbS",             { Evh1, Gv }, 0 },
2560   { "sbbB",             { Gb, EbS }, 0 },
2561   { "sbbS",             { Gv, EvS }, 0 },
2562   { "sbbB",             { AL, Ib }, 0 },
2563   { "sbbS",             { eAX, Iv }, 0 },
2564   { X86_64_TABLE (X86_64_1E) },
2565   { X86_64_TABLE (X86_64_1F) },
2566   /* 20 */
2567   { "andB",             { Ebh1, Gb }, 0 },
2568   { "andS",             { Evh1, Gv }, 0 },
2569   { "andB",             { Gb, EbS }, 0 },
2570   { "andS",             { Gv, EvS }, 0 },
2571   { "andB",             { AL, Ib }, 0 },
2572   { "andS",             { eAX, Iv }, 0 },
2573   { Bad_Opcode },       /* SEG ES prefix */
2574   { X86_64_TABLE (X86_64_27) },
2575   /* 28 */
2576   { "subB",             { Ebh1, Gb }, 0 },
2577   { "subS",             { Evh1, Gv }, 0 },
2578   { "subB",             { Gb, EbS }, 0 },
2579   { "subS",             { Gv, EvS }, 0 },
2580   { "subB",             { AL, Ib }, 0 },
2581   { "subS",             { eAX, Iv }, 0 },
2582   { Bad_Opcode },       /* SEG CS prefix */
2583   { X86_64_TABLE (X86_64_2F) },
2584   /* 30 */
2585   { "xorB",             { Ebh1, Gb }, 0 },
2586   { "xorS",             { Evh1, Gv }, 0 },
2587   { "xorB",             { Gb, EbS }, 0 },
2588   { "xorS",             { Gv, EvS }, 0 },
2589   { "xorB",             { AL, Ib }, 0 },
2590   { "xorS",             { eAX, Iv }, 0 },
2591   { Bad_Opcode },       /* SEG SS prefix */
2592   { X86_64_TABLE (X86_64_37) },
2593   /* 38 */
2594   { "cmpB",             { Eb, Gb }, 0 },
2595   { "cmpS",             { Ev, Gv }, 0 },
2596   { "cmpB",             { Gb, EbS }, 0 },
2597   { "cmpS",             { Gv, EvS }, 0 },
2598   { "cmpB",             { AL, Ib }, 0 },
2599   { "cmpS",             { eAX, Iv }, 0 },
2600   { Bad_Opcode },       /* SEG DS prefix */
2601   { X86_64_TABLE (X86_64_3F) },
2602   /* 40 */
2603   { "inc{S|}",          { RMeAX }, 0 },
2604   { "inc{S|}",          { RMeCX }, 0 },
2605   { "inc{S|}",          { RMeDX }, 0 },
2606   { "inc{S|}",          { RMeBX }, 0 },
2607   { "inc{S|}",          { RMeSP }, 0 },
2608   { "inc{S|}",          { RMeBP }, 0 },
2609   { "inc{S|}",          { RMeSI }, 0 },
2610   { "inc{S|}",          { RMeDI }, 0 },
2611   /* 48 */
2612   { "dec{S|}",          { RMeAX }, 0 },
2613   { "dec{S|}",          { RMeCX }, 0 },
2614   { "dec{S|}",          { RMeDX }, 0 },
2615   { "dec{S|}",          { RMeBX }, 0 },
2616   { "dec{S|}",          { RMeSP }, 0 },
2617   { "dec{S|}",          { RMeBP }, 0 },
2618   { "dec{S|}",          { RMeSI }, 0 },
2619   { "dec{S|}",          { RMeDI }, 0 },
2620   /* 50 */
2621   { "pushV",            { RMrAX }, 0 },
2622   { "pushV",            { RMrCX }, 0 },
2623   { "pushV",            { RMrDX }, 0 },
2624   { "pushV",            { RMrBX }, 0 },
2625   { "pushV",            { RMrSP }, 0 },
2626   { "pushV",            { RMrBP }, 0 },
2627   { "pushV",            { RMrSI }, 0 },
2628   { "pushV",            { RMrDI }, 0 },
2629   /* 58 */
2630   { "popV",             { RMrAX }, 0 },
2631   { "popV",             { RMrCX }, 0 },
2632   { "popV",             { RMrDX }, 0 },
2633   { "popV",             { RMrBX }, 0 },
2634   { "popV",             { RMrSP }, 0 },
2635   { "popV",             { RMrBP }, 0 },
2636   { "popV",             { RMrSI }, 0 },
2637   { "popV",             { RMrDI }, 0 },
2638   /* 60 */
2639   { X86_64_TABLE (X86_64_60) },
2640   { X86_64_TABLE (X86_64_61) },
2641   { X86_64_TABLE (X86_64_62) },
2642   { X86_64_TABLE (X86_64_63) },
2643   { Bad_Opcode },       /* seg fs */
2644   { Bad_Opcode },       /* seg gs */
2645   { Bad_Opcode },       /* op size prefix */
2646   { Bad_Opcode },       /* adr size prefix */
2647   /* 68 */
2648   { "pushT",            { sIv }, 0 },
2649   { "imulS",            { Gv, Ev, Iv }, 0 },
2650   { "pushT",            { sIbT }, 0 },
2651   { "imulS",            { Gv, Ev, sIb }, 0 },
2652   { "ins{b|}",          { Ybr, indirDX }, 0 },
2653   { X86_64_TABLE (X86_64_6D) },
2654   { "outs{b|}",         { indirDXr, Xb }, 0 },
2655   { X86_64_TABLE (X86_64_6F) },
2656   /* 70 */
2657   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2658   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2659   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2660   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2662   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2663   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2664   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2665   /* 78 */
2666   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2667   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2668   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2669   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2670   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2671   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2672   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2673   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2674   /* 80 */
2675   { REG_TABLE (REG_80) },
2676   { REG_TABLE (REG_81) },
2677   { X86_64_TABLE (X86_64_82) },
2678   { REG_TABLE (REG_83) },
2679   { "testB",            { Eb, Gb }, 0 },
2680   { "testS",            { Ev, Gv }, 0 },
2681   { "xchgB",            { Ebh2, Gb }, 0 },
2682   { "xchgS",            { Evh2, Gv }, 0 },
2683   /* 88 */
2684   { "movB",             { Ebh3, Gb }, 0 },
2685   { "movS",             { Evh3, Gv }, 0 },
2686   { "movB",             { Gb, EbS }, 0 },
2687   { "movS",             { Gv, EvS }, 0 },
2688   { "movD",             { Sv, Sw }, 0 },
2689   { MOD_TABLE (MOD_8D) },
2690   { "movD",             { Sw, Sv }, 0 },
2691   { REG_TABLE (REG_8F) },
2692   /* 90 */
2693   { PREFIX_TABLE (PREFIX_90) },
2694   { "xchgS",            { RMeCX, eAX }, 0 },
2695   { "xchgS",            { RMeDX, eAX }, 0 },
2696   { "xchgS",            { RMeBX, eAX }, 0 },
2697   { "xchgS",            { RMeSP, eAX }, 0 },
2698   { "xchgS",            { RMeBP, eAX }, 0 },
2699   { "xchgS",            { RMeSI, eAX }, 0 },
2700   { "xchgS",            { RMeDI, eAX }, 0 },
2701   /* 98 */
2702   { "cW{t|}R",          { XX }, 0 },
2703   { "cR{t|}O",          { XX }, 0 },
2704   { X86_64_TABLE (X86_64_9A) },
2705   { Bad_Opcode },       /* fwait */
2706   { "pushfT",           { XX }, 0 },
2707   { "popfT",            { XX }, 0 },
2708   { "sahf",             { XX }, 0 },
2709   { "lahf",             { XX }, 0 },
2710   /* a0 */
2711   { "mov%LB",           { AL, Ob }, 0 },
2712   { "mov%LS",           { eAX, Ov }, 0 },
2713   { "mov%LB",           { Ob, AL }, 0 },
2714   { "mov%LS",           { Ov, eAX }, 0 },
2715   { "movs{b|}",         { Ybr, Xb }, 0 },
2716   { "movs{R|}",         { Yvr, Xv }, 0 },
2717   { "cmps{b|}",         { Xb, Yb }, 0 },
2718   { "cmps{R|}",         { Xv, Yv }, 0 },
2719   /* a8 */
2720   { "testB",            { AL, Ib }, 0 },
2721   { "testS",            { eAX, Iv }, 0 },
2722   { "stosB",            { Ybr, AL }, 0 },
2723   { "stosS",            { Yvr, eAX }, 0 },
2724   { "lodsB",            { ALr, Xb }, 0 },
2725   { "lodsS",            { eAXr, Xv }, 0 },
2726   { "scasB",            { AL, Yb }, 0 },
2727   { "scasS",            { eAX, Yv }, 0 },
2728   /* b0 */
2729   { "movB",             { RMAL, Ib }, 0 },
2730   { "movB",             { RMCL, Ib }, 0 },
2731   { "movB",             { RMDL, Ib }, 0 },
2732   { "movB",             { RMBL, Ib }, 0 },
2733   { "movB",             { RMAH, Ib }, 0 },
2734   { "movB",             { RMCH, Ib }, 0 },
2735   { "movB",             { RMDH, Ib }, 0 },
2736   { "movB",             { RMBH, Ib }, 0 },
2737   /* b8 */
2738   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2739   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2740   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2741   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2742   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2743   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2744   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2745   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2746   /* c0 */
2747   { REG_TABLE (REG_C0) },
2748   { REG_TABLE (REG_C1) },
2749   { "retT",             { Iw, BND }, 0 },
2750   { "retT",             { BND }, 0 },
2751   { X86_64_TABLE (X86_64_C4) },
2752   { X86_64_TABLE (X86_64_C5) },
2753   { REG_TABLE (REG_C6) },
2754   { REG_TABLE (REG_C7) },
2755   /* c8 */
2756   { "enterT",           { Iw, Ib }, 0 },
2757   { "leaveT",           { XX }, 0 },
2758   { "Jret{|f}P",        { Iw }, 0 },
2759   { "Jret{|f}P",        { XX }, 0 },
2760   { "int3",             { XX }, 0 },
2761   { "int",              { Ib }, 0 },
2762   { X86_64_TABLE (X86_64_CE) },
2763   { "iret%LP",          { XX }, 0 },
2764   /* d0 */
2765   { REG_TABLE (REG_D0) },
2766   { REG_TABLE (REG_D1) },
2767   { REG_TABLE (REG_D2) },
2768   { REG_TABLE (REG_D3) },
2769   { X86_64_TABLE (X86_64_D4) },
2770   { X86_64_TABLE (X86_64_D5) },
2771   { Bad_Opcode },
2772   { "xlat",             { DSBX }, 0 },
2773   /* d8 */
2774   { FLOAT },
2775   { FLOAT },
2776   { FLOAT },
2777   { FLOAT },
2778   { FLOAT },
2779   { FLOAT },
2780   { FLOAT },
2781   { FLOAT },
2782   /* e0 */
2783   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2784   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2785   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2786   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2787   { "inB",              { AL, Ib }, 0 },
2788   { "inG",              { zAX, Ib }, 0 },
2789   { "outB",             { Ib, AL }, 0 },
2790   { "outG",             { Ib, zAX }, 0 },
2791   /* e8 */
2792   { X86_64_TABLE (X86_64_E8) },
2793   { X86_64_TABLE (X86_64_E9) },
2794   { X86_64_TABLE (X86_64_EA) },
2795   { "jmp",              { Jb, BND }, 0 },
2796   { "inB",              { AL, indirDX }, 0 },
2797   { "inG",              { zAX, indirDX }, 0 },
2798   { "outB",             { indirDX, AL }, 0 },
2799   { "outG",             { indirDX, zAX }, 0 },
2800   /* f0 */
2801   { Bad_Opcode },       /* lock prefix */
2802   { "icebp",            { XX }, 0 },
2803   { Bad_Opcode },       /* repne */
2804   { Bad_Opcode },       /* repz */
2805   { "hlt",              { XX }, 0 },
2806   { "cmc",              { XX }, 0 },
2807   { REG_TABLE (REG_F6) },
2808   { REG_TABLE (REG_F7) },
2809   /* f8 */
2810   { "clc",              { XX }, 0 },
2811   { "stc",              { XX }, 0 },
2812   { "cli",              { XX }, 0 },
2813   { "sti",              { XX }, 0 },
2814   { "cld",              { XX }, 0 },
2815   { "std",              { XX }, 0 },
2816   { REG_TABLE (REG_FE) },
2817   { REG_TABLE (REG_FF) },
2818 };
2819
2820 static const struct dis386 dis386_twobyte[] = {
2821   /* 00 */
2822   { REG_TABLE (REG_0F00 ) },
2823   { REG_TABLE (REG_0F01 ) },
2824   { "larS",             { Gv, Ew }, 0 },
2825   { "lslS",             { Gv, Ew }, 0 },
2826   { Bad_Opcode },
2827   { "syscall",          { XX }, 0 },
2828   { "clts",             { XX }, 0 },
2829   { "sysret%LP",                { XX }, 0 },
2830   /* 08 */
2831   { "invd",             { XX }, 0 },
2832   { "wbinvd",           { XX }, 0 },
2833   { Bad_Opcode },
2834   { "ud2",              { XX }, 0 },
2835   { Bad_Opcode },
2836   { REG_TABLE (REG_0F0D) },
2837   { "femms",            { XX }, 0 },
2838   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2839   /* 10 */
2840   { PREFIX_TABLE (PREFIX_0F10) },
2841   { PREFIX_TABLE (PREFIX_0F11) },
2842   { PREFIX_TABLE (PREFIX_0F12) },
2843   { MOD_TABLE (MOD_0F13) },
2844   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2845   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2846   { PREFIX_TABLE (PREFIX_0F16) },
2847   { MOD_TABLE (MOD_0F17) },
2848   /* 18 */
2849   { REG_TABLE (REG_0F18) },
2850   { "nopQ",             { Ev }, 0 },
2851   { PREFIX_TABLE (PREFIX_0F1A) },
2852   { PREFIX_TABLE (PREFIX_0F1B) },
2853   { "nopQ",             { Ev }, 0 },
2854   { "nopQ",             { Ev }, 0 },
2855   { PREFIX_TABLE (PREFIX_0F1E) },
2856   { "nopQ",             { Ev }, 0 },
2857   /* 20 */
2858   { "movZ",             { Rm, Cm }, 0 },
2859   { "movZ",             { Rm, Dm }, 0 },
2860   { "movZ",             { Cm, Rm }, 0 },
2861   { "movZ",             { Dm, Rm }, 0 },
2862   { MOD_TABLE (MOD_0F24) },
2863   { Bad_Opcode },
2864   { MOD_TABLE (MOD_0F26) },
2865   { Bad_Opcode },
2866   /* 28 */
2867   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2868   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2869   { PREFIX_TABLE (PREFIX_0F2A) },
2870   { PREFIX_TABLE (PREFIX_0F2B) },
2871   { PREFIX_TABLE (PREFIX_0F2C) },
2872   { PREFIX_TABLE (PREFIX_0F2D) },
2873   { PREFIX_TABLE (PREFIX_0F2E) },
2874   { PREFIX_TABLE (PREFIX_0F2F) },
2875   /* 30 */
2876   { "wrmsr",            { XX }, 0 },
2877   { "rdtsc",            { XX }, 0 },
2878   { "rdmsr",            { XX }, 0 },
2879   { "rdpmc",            { XX }, 0 },
2880   { "sysenter",         { XX }, 0 },
2881   { "sysexit",          { XX }, 0 },
2882   { Bad_Opcode },
2883   { "getsec",           { XX }, 0 },
2884   /* 38 */
2885   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2886   { Bad_Opcode },
2887   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2888   { Bad_Opcode },
2889   { Bad_Opcode },
2890   { Bad_Opcode },
2891   { Bad_Opcode },
2892   { Bad_Opcode },
2893   /* 40 */
2894   { "cmovoS",           { Gv, Ev }, 0 },
2895   { "cmovnoS",          { Gv, Ev }, 0 },
2896   { "cmovbS",           { Gv, Ev }, 0 },
2897   { "cmovaeS",          { Gv, Ev }, 0 },
2898   { "cmoveS",           { Gv, Ev }, 0 },
2899   { "cmovneS",          { Gv, Ev }, 0 },
2900   { "cmovbeS",          { Gv, Ev }, 0 },
2901   { "cmovaS",           { Gv, Ev }, 0 },
2902   /* 48 */
2903   { "cmovsS",           { Gv, Ev }, 0 },
2904   { "cmovnsS",          { Gv, Ev }, 0 },
2905   { "cmovpS",           { Gv, Ev }, 0 },
2906   { "cmovnpS",          { Gv, Ev }, 0 },
2907   { "cmovlS",           { Gv, Ev }, 0 },
2908   { "cmovgeS",          { Gv, Ev }, 0 },
2909   { "cmovleS",          { Gv, Ev }, 0 },
2910   { "cmovgS",           { Gv, Ev }, 0 },
2911   /* 50 */
2912   { MOD_TABLE (MOD_0F51) },
2913   { PREFIX_TABLE (PREFIX_0F51) },
2914   { PREFIX_TABLE (PREFIX_0F52) },
2915   { PREFIX_TABLE (PREFIX_0F53) },
2916   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2917   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2918   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2919   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2920   /* 58 */
2921   { PREFIX_TABLE (PREFIX_0F58) },
2922   { PREFIX_TABLE (PREFIX_0F59) },
2923   { PREFIX_TABLE (PREFIX_0F5A) },
2924   { PREFIX_TABLE (PREFIX_0F5B) },
2925   { PREFIX_TABLE (PREFIX_0F5C) },
2926   { PREFIX_TABLE (PREFIX_0F5D) },
2927   { PREFIX_TABLE (PREFIX_0F5E) },
2928   { PREFIX_TABLE (PREFIX_0F5F) },
2929   /* 60 */
2930   { PREFIX_TABLE (PREFIX_0F60) },
2931   { PREFIX_TABLE (PREFIX_0F61) },
2932   { PREFIX_TABLE (PREFIX_0F62) },
2933   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2934   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2935   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2936   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2937   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2938   /* 68 */
2939   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2940   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2941   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2942   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2943   { PREFIX_TABLE (PREFIX_0F6C) },
2944   { PREFIX_TABLE (PREFIX_0F6D) },
2945   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2946   { PREFIX_TABLE (PREFIX_0F6F) },
2947   /* 70 */
2948   { PREFIX_TABLE (PREFIX_0F70) },
2949   { REG_TABLE (REG_0F71) },
2950   { REG_TABLE (REG_0F72) },
2951   { REG_TABLE (REG_0F73) },
2952   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2953   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2954   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2955   { "emms",             { XX }, PREFIX_OPCODE },
2956   /* 78 */
2957   { PREFIX_TABLE (PREFIX_0F78) },
2958   { PREFIX_TABLE (PREFIX_0F79) },
2959   { Bad_Opcode },
2960   { Bad_Opcode },
2961   { PREFIX_TABLE (PREFIX_0F7C) },
2962   { PREFIX_TABLE (PREFIX_0F7D) },
2963   { PREFIX_TABLE (PREFIX_0F7E) },
2964   { PREFIX_TABLE (PREFIX_0F7F) },
2965   /* 80 */
2966   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2967   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2968   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2969   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2971   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2972   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2973   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2974   /* 88 */
2975   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2976   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2977   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2978   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2979   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2980   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2981   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2982   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2983   /* 90 */
2984   { "seto",             { Eb }, 0 },
2985   { "setno",            { Eb }, 0 },
2986   { "setb",             { Eb }, 0 },
2987   { "setae",            { Eb }, 0 },
2988   { "sete",             { Eb }, 0 },
2989   { "setne",            { Eb }, 0 },
2990   { "setbe",            { Eb }, 0 },
2991   { "seta",             { Eb }, 0 },
2992   /* 98 */
2993   { "sets",             { Eb }, 0 },
2994   { "setns",            { Eb }, 0 },
2995   { "setp",             { Eb }, 0 },
2996   { "setnp",            { Eb }, 0 },
2997   { "setl",             { Eb }, 0 },
2998   { "setge",            { Eb }, 0 },
2999   { "setle",            { Eb }, 0 },
3000   { "setg",             { Eb }, 0 },
3001   /* a0 */
3002   { "pushT",            { fs }, 0 },
3003   { "popT",             { fs }, 0 },
3004   { "cpuid",            { XX }, 0 },
3005   { "btS",              { Ev, Gv }, 0 },
3006   { "shldS",            { Ev, Gv, Ib }, 0 },
3007   { "shldS",            { Ev, Gv, CL }, 0 },
3008   { REG_TABLE (REG_0FA6) },
3009   { REG_TABLE (REG_0FA7) },
3010   /* a8 */
3011   { "pushT",            { gs }, 0 },
3012   { "popT",             { gs }, 0 },
3013   { "rsm",              { XX }, 0 },
3014   { "btsS",             { Evh1, Gv }, 0 },
3015   { "shrdS",            { Ev, Gv, Ib }, 0 },
3016   { "shrdS",            { Ev, Gv, CL }, 0 },
3017   { REG_TABLE (REG_0FAE) },
3018   { "imulS",            { Gv, Ev }, 0 },
3019   /* b0 */
3020   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3021   { "cmpxchgS",         { Evh1, Gv }, 0 },
3022   { MOD_TABLE (MOD_0FB2) },
3023   { "btrS",             { Evh1, Gv }, 0 },
3024   { MOD_TABLE (MOD_0FB4) },
3025   { MOD_TABLE (MOD_0FB5) },
3026   { "movz{bR|x}",       { Gv, Eb }, 0 },
3027   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3028   /* b8 */
3029   { PREFIX_TABLE (PREFIX_0FB8) },
3030   { "ud1",              { XX }, 0 },
3031   { REG_TABLE (REG_0FBA) },
3032   { "btcS",             { Evh1, Gv }, 0 },
3033   { PREFIX_TABLE (PREFIX_0FBC) },
3034   { PREFIX_TABLE (PREFIX_0FBD) },
3035   { "movs{bR|x}",       { Gv, Eb }, 0 },
3036   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3037   /* c0 */
3038   { "xaddB",            { Ebh1, Gb }, 0 },
3039   { "xaddS",            { Evh1, Gv }, 0 },
3040   { PREFIX_TABLE (PREFIX_0FC2) },
3041   { MOD_TABLE (MOD_0FC3) },
3042   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3043   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3044   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3045   { REG_TABLE (REG_0FC7) },
3046   /* c8 */
3047   { "bswap",            { RMeAX }, 0 },
3048   { "bswap",            { RMeCX }, 0 },
3049   { "bswap",            { RMeDX }, 0 },
3050   { "bswap",            { RMeBX }, 0 },
3051   { "bswap",            { RMeSP }, 0 },
3052   { "bswap",            { RMeBP }, 0 },
3053   { "bswap",            { RMeSI }, 0 },
3054   { "bswap",            { RMeDI }, 0 },
3055   /* d0 */
3056   { PREFIX_TABLE (PREFIX_0FD0) },
3057   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3058   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3059   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3060   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3061   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3062   { PREFIX_TABLE (PREFIX_0FD6) },
3063   { MOD_TABLE (MOD_0FD7) },
3064   /* d8 */
3065   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3066   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3067   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3068   { "pand",             { MX, EM }, PREFIX_OPCODE },
3069   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3070   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3071   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3072   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3073   /* e0 */
3074   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3075   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3076   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3077   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3078   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3079   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3080   { PREFIX_TABLE (PREFIX_0FE6) },
3081   { PREFIX_TABLE (PREFIX_0FE7) },
3082   /* e8 */
3083   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3084   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3085   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3086   { "por",              { MX, EM }, PREFIX_OPCODE },
3087   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3088   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3089   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3090   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3091   /* f0 */
3092   { PREFIX_TABLE (PREFIX_0FF0) },
3093   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3094   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3095   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3096   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3097   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3098   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3099   { PREFIX_TABLE (PREFIX_0FF7) },
3100   /* f8 */
3101   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3102   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3103   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3104   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3105   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3106   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3107   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3108   { Bad_Opcode },
3109 };
3110
3111 static const unsigned char onebyte_has_modrm[256] = {
3112   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3113   /*       -------------------------------        */
3114   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3115   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3116   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3117   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3118   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3119   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3120   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3121   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3122   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3123   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3124   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3125   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3126   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3127   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3128   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3129   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3130   /*       -------------------------------        */
3131   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3132 };
3133
3134 static const unsigned char twobyte_has_modrm[256] = {
3135   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3136   /*       -------------------------------        */
3137   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3138   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3139   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3140   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3141   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3142   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3143   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3144   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3145   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3146   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3147   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3148   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3149   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3150   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3151   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3152   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3153   /*       -------------------------------        */
3154   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3155 };
3156
3157 static char obuf[100];
3158 static char *obufp;
3159 static char *mnemonicendp;
3160 static char scratchbuf[100];
3161 static unsigned char *start_codep;
3162 static unsigned char *insn_codep;
3163 static unsigned char *codep;
3164 static unsigned char *end_codep;
3165 static int last_lock_prefix;
3166 static int last_repz_prefix;
3167 static int last_repnz_prefix;
3168 static int last_data_prefix;
3169 static int last_addr_prefix;
3170 static int last_rex_prefix;
3171 static int last_seg_prefix;
3172 static int last_active_prefix;
3173 static int fwait_prefix;
3174 /* The active segment register prefix.  */
3175 static int active_seg_prefix;
3176 #define MAX_CODE_LENGTH 15
3177 /* We can up to 14 prefixes since the maximum instruction length is
3178    15bytes.  */
3179 static int all_prefixes[MAX_CODE_LENGTH - 1];
3180 static disassemble_info *the_info;
3181 static struct
3182   {
3183     int mod;
3184     int reg;
3185     int rm;
3186   }
3187 modrm;
3188 static unsigned char need_modrm;
3189 static struct
3190   {
3191     int scale;
3192     int index;
3193     int base;
3194   }
3195 sib;
3196 static struct
3197   {
3198     int register_specifier;
3199     int length;
3200     int prefix;
3201     int w;
3202     int evex;
3203     int r;
3204     int v;
3205     int mask_register_specifier;
3206     int zeroing;
3207     int ll;
3208     int b;
3209   }
3210 vex;
3211 static unsigned char need_vex;
3212 static unsigned char need_vex_reg;
3213 static unsigned char vex_w_done;
3214
3215 struct op
3216   {
3217     const char *name;
3218     unsigned int len;
3219   };
3220
3221 /* If we are accessing mod/rm/reg without need_modrm set, then the
3222    values are stale.  Hitting this abort likely indicates that you
3223    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3224 #define MODRM_CHECK  if (!need_modrm) abort ()
3225
3226 static const char **names64;
3227 static const char **names32;
3228 static const char **names16;
3229 static const char **names8;
3230 static const char **names8rex;
3231 static const char **names_seg;
3232 static const char *index64;
3233 static const char *index32;
3234 static const char **index16;
3235 static const char **names_bnd;
3236
3237 static const char *intel_names64[] = {
3238   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3239   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3240 };
3241 static const char *intel_names32[] = {
3242   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3243   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3244 };
3245 static const char *intel_names16[] = {
3246   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3247   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3248 };
3249 static const char *intel_names8[] = {
3250   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3251 };
3252 static const char *intel_names8rex[] = {
3253   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3254   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3255 };
3256 static const char *intel_names_seg[] = {
3257   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3258 };
3259 static const char *intel_index64 = "riz";
3260 static const char *intel_index32 = "eiz";
3261 static const char *intel_index16[] = {
3262   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3263 };
3264
3265 static const char *att_names64[] = {
3266   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3267   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3268 };
3269 static const char *att_names32[] = {
3270   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3271   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3272 };
3273 static const char *att_names16[] = {
3274   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3275   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3276 };
3277 static const char *att_names8[] = {
3278   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3279 };
3280 static const char *att_names8rex[] = {
3281   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3282   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3283 };
3284 static const char *att_names_seg[] = {
3285   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3286 };
3287 static const char *att_index64 = "%riz";
3288 static const char *att_index32 = "%eiz";
3289 static const char *att_index16[] = {
3290   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3291 };
3292
3293 static const char **names_mm;
3294 static const char *intel_names_mm[] = {
3295   "mm0", "mm1", "mm2", "mm3",
3296   "mm4", "mm5", "mm6", "mm7"
3297 };
3298 static const char *att_names_mm[] = {
3299   "%mm0", "%mm1", "%mm2", "%mm3",
3300   "%mm4", "%mm5", "%mm6", "%mm7"
3301 };
3302
3303 static const char *intel_names_bnd[] = {
3304   "bnd0", "bnd1", "bnd2", "bnd3"
3305 };
3306
3307 static const char *att_names_bnd[] = {
3308   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3309 };
3310
3311 static const char **names_xmm;
3312 static const char *intel_names_xmm[] = {
3313   "xmm0", "xmm1", "xmm2", "xmm3",
3314   "xmm4", "xmm5", "xmm6", "xmm7",
3315   "xmm8", "xmm9", "xmm10", "xmm11",
3316   "xmm12", "xmm13", "xmm14", "xmm15",
3317   "xmm16", "xmm17", "xmm18", "xmm19",
3318   "xmm20", "xmm21", "xmm22", "xmm23",
3319   "xmm24", "xmm25", "xmm26", "xmm27",
3320   "xmm28", "xmm29", "xmm30", "xmm31"
3321 };
3322 static const char *att_names_xmm[] = {
3323   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3324   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3325   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3326   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3327   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3328   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3329   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3330   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3331 };
3332
3333 static const char **names_ymm;
3334 static const char *intel_names_ymm[] = {
3335   "ymm0", "ymm1", "ymm2", "ymm3",
3336   "ymm4", "ymm5", "ymm6", "ymm7",
3337   "ymm8", "ymm9", "ymm10", "ymm11",
3338   "ymm12", "ymm13", "ymm14", "ymm15",
3339   "ymm16", "ymm17", "ymm18", "ymm19",
3340   "ymm20", "ymm21", "ymm22", "ymm23",
3341   "ymm24", "ymm25", "ymm26", "ymm27",
3342   "ymm28", "ymm29", "ymm30", "ymm31"
3343 };
3344 static const char *att_names_ymm[] = {
3345   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3346   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3347   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3348   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3349   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3350   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3351   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3352   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3353 };
3354
3355 static const char **names_zmm;
3356 static const char *intel_names_zmm[] = {
3357   "zmm0", "zmm1", "zmm2", "zmm3",
3358   "zmm4", "zmm5", "zmm6", "zmm7",
3359   "zmm8", "zmm9", "zmm10", "zmm11",
3360   "zmm12", "zmm13", "zmm14", "zmm15",
3361   "zmm16", "zmm17", "zmm18", "zmm19",
3362   "zmm20", "zmm21", "zmm22", "zmm23",
3363   "zmm24", "zmm25", "zmm26", "zmm27",
3364   "zmm28", "zmm29", "zmm30", "zmm31"
3365 };
3366 static const char *att_names_zmm[] = {
3367   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3368   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3369   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3370   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3371   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3372   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3373   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3374   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3375 };
3376
3377 static const char **names_mask;
3378 static const char *intel_names_mask[] = {
3379   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3380 };
3381 static const char *att_names_mask[] = {
3382   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3383 };
3384
3385 static const char *names_rounding[] =
3386 {
3387   "{rn-sae}",
3388   "{rd-sae}",
3389   "{ru-sae}",
3390   "{rz-sae}"
3391 };
3392
3393 static const struct dis386 reg_table[][8] = {
3394   /* REG_80 */
3395   {
3396     { "addA",   { Ebh1, Ib }, 0 },
3397     { "orA",    { Ebh1, Ib }, 0 },
3398     { "adcA",   { Ebh1, Ib }, 0 },
3399     { "sbbA",   { Ebh1, Ib }, 0 },
3400     { "andA",   { Ebh1, Ib }, 0 },
3401     { "subA",   { Ebh1, Ib }, 0 },
3402     { "xorA",   { Ebh1, Ib }, 0 },
3403     { "cmpA",   { Eb, Ib }, 0 },
3404   },
3405   /* REG_81 */
3406   {
3407     { "addQ",   { Evh1, Iv }, 0 },
3408     { "orQ",    { Evh1, Iv }, 0 },
3409     { "adcQ",   { Evh1, Iv }, 0 },
3410     { "sbbQ",   { Evh1, Iv }, 0 },
3411     { "andQ",   { Evh1, Iv }, 0 },
3412     { "subQ",   { Evh1, Iv }, 0 },
3413     { "xorQ",   { Evh1, Iv }, 0 },
3414     { "cmpQ",   { Ev, Iv }, 0 },
3415   },
3416   /* REG_83 */
3417   {
3418     { "addQ",   { Evh1, sIb }, 0 },
3419     { "orQ",    { Evh1, sIb }, 0 },
3420     { "adcQ",   { Evh1, sIb }, 0 },
3421     { "sbbQ",   { Evh1, sIb }, 0 },
3422     { "andQ",   { Evh1, sIb }, 0 },
3423     { "subQ",   { Evh1, sIb }, 0 },
3424     { "xorQ",   { Evh1, sIb }, 0 },
3425     { "cmpQ",   { Ev, sIb }, 0 },
3426   },
3427   /* REG_8F */
3428   {
3429     { "popU",   { stackEv }, 0 },
3430     { XOP_8F_TABLE (XOP_09) },
3431     { Bad_Opcode },
3432     { Bad_Opcode },
3433     { Bad_Opcode },
3434     { XOP_8F_TABLE (XOP_09) },
3435   },
3436   /* REG_C0 */
3437   {
3438     { "rolA",   { Eb, Ib }, 0 },
3439     { "rorA",   { Eb, Ib }, 0 },
3440     { "rclA",   { Eb, Ib }, 0 },
3441     { "rcrA",   { Eb, Ib }, 0 },
3442     { "shlA",   { Eb, Ib }, 0 },
3443     { "shrA",   { Eb, Ib }, 0 },
3444     { Bad_Opcode },
3445     { "sarA",   { Eb, Ib }, 0 },
3446   },
3447   /* REG_C1 */
3448   {
3449     { "rolQ",   { Ev, Ib }, 0 },
3450     { "rorQ",   { Ev, Ib }, 0 },
3451     { "rclQ",   { Ev, Ib }, 0 },
3452     { "rcrQ",   { Ev, Ib }, 0 },
3453     { "shlQ",   { Ev, Ib }, 0 },
3454     { "shrQ",   { Ev, Ib }, 0 },
3455     { Bad_Opcode },
3456     { "sarQ",   { Ev, Ib }, 0 },
3457   },
3458   /* REG_C6 */
3459   {
3460     { "movA",   { Ebh3, Ib }, 0 },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { Bad_Opcode },
3466     { Bad_Opcode },
3467     { MOD_TABLE (MOD_C6_REG_7) },
3468   },
3469   /* REG_C7 */
3470   {
3471     { "movQ",   { Evh3, Iv }, 0 },
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { Bad_Opcode },
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_C7_REG_7) },
3479   },
3480   /* REG_D0 */
3481   {
3482     { "rolA",   { Eb, I1 }, 0 },
3483     { "rorA",   { Eb, I1 }, 0 },
3484     { "rclA",   { Eb, I1 }, 0 },
3485     { "rcrA",   { Eb, I1 }, 0 },
3486     { "shlA",   { Eb, I1 }, 0 },
3487     { "shrA",   { Eb, I1 }, 0 },
3488     { Bad_Opcode },
3489     { "sarA",   { Eb, I1 }, 0 },
3490   },
3491   /* REG_D1 */
3492   {
3493     { "rolQ",   { Ev, I1 }, 0 },
3494     { "rorQ",   { Ev, I1 }, 0 },
3495     { "rclQ",   { Ev, I1 }, 0 },
3496     { "rcrQ",   { Ev, I1 }, 0 },
3497     { "shlQ",   { Ev, I1 }, 0 },
3498     { "shrQ",   { Ev, I1 }, 0 },
3499     { Bad_Opcode },
3500     { "sarQ",   { Ev, I1 }, 0 },
3501   },
3502   /* REG_D2 */
3503   {
3504     { "rolA",   { Eb, CL }, 0 },
3505     { "rorA",   { Eb, CL }, 0 },
3506     { "rclA",   { Eb, CL }, 0 },
3507     { "rcrA",   { Eb, CL }, 0 },
3508     { "shlA",   { Eb, CL }, 0 },
3509     { "shrA",   { Eb, CL }, 0 },
3510     { Bad_Opcode },
3511     { "sarA",   { Eb, CL }, 0 },
3512   },
3513   /* REG_D3 */
3514   {
3515     { "rolQ",   { Ev, CL }, 0 },
3516     { "rorQ",   { Ev, CL }, 0 },
3517     { "rclQ",   { Ev, CL }, 0 },
3518     { "rcrQ",   { Ev, CL }, 0 },
3519     { "shlQ",   { Ev, CL }, 0 },
3520     { "shrQ",   { Ev, CL }, 0 },
3521     { Bad_Opcode },
3522     { "sarQ",   { Ev, CL }, 0 },
3523   },
3524   /* REG_F6 */
3525   {
3526     { "testA",  { Eb, Ib }, 0 },
3527     { "testA",  { Eb, Ib }, 0 },
3528     { "notA",   { Ebh1 }, 0 },
3529     { "negA",   { Ebh1 }, 0 },
3530     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3531     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3532     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3533     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3534   },
3535   /* REG_F7 */
3536   {
3537     { "testQ",  { Ev, Iv }, 0 },
3538     { "testQ",  { Ev, Iv }, 0 },
3539     { "notQ",   { Evh1 }, 0 },
3540     { "negQ",   { Evh1 }, 0 },
3541     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3542     { "imulQ",  { Ev }, 0 },
3543     { "divQ",   { Ev }, 0 },
3544     { "idivQ",  { Ev }, 0 },
3545   },
3546   /* REG_FE */
3547   {
3548     { "incA",   { Ebh1 }, 0 },
3549     { "decA",   { Ebh1 }, 0 },
3550   },
3551   /* REG_FF */
3552   {
3553     { "incQ",   { Evh1 }, 0 },
3554     { "decQ",   { Evh1 }, 0 },
3555     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3556     { MOD_TABLE (MOD_FF_REG_3) },
3557     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3558     { MOD_TABLE (MOD_FF_REG_5) },
3559     { "pushU",  { stackEv }, 0 },
3560     { Bad_Opcode },
3561   },
3562   /* REG_0F00 */
3563   {
3564     { "sldtD",  { Sv }, 0 },
3565     { "strD",   { Sv }, 0 },
3566     { "lldt",   { Ew }, 0 },
3567     { "ltr",    { Ew }, 0 },
3568     { "verr",   { Ew }, 0 },
3569     { "verw",   { Ew }, 0 },
3570     { Bad_Opcode },
3571     { Bad_Opcode },
3572   },
3573   /* REG_0F01 */
3574   {
3575     { MOD_TABLE (MOD_0F01_REG_0) },
3576     { MOD_TABLE (MOD_0F01_REG_1) },
3577     { MOD_TABLE (MOD_0F01_REG_2) },
3578     { MOD_TABLE (MOD_0F01_REG_3) },
3579     { "smswD",  { Sv }, 0 },
3580     { MOD_TABLE (MOD_0F01_REG_5) },
3581     { "lmsw",   { Ew }, 0 },
3582     { MOD_TABLE (MOD_0F01_REG_7) },
3583   },
3584   /* REG_0F0D */
3585   {
3586     { "prefetch",       { Mb }, 0 },
3587     { "prefetchw",      { Mb }, 0 },
3588     { "prefetchwt1",    { Mb }, 0 },
3589     { "prefetch",       { Mb }, 0 },
3590     { "prefetch",       { Mb }, 0 },
3591     { "prefetch",       { Mb }, 0 },
3592     { "prefetch",       { Mb }, 0 },
3593     { "prefetch",       { Mb }, 0 },
3594   },
3595   /* REG_0F18 */
3596   {
3597     { MOD_TABLE (MOD_0F18_REG_0) },
3598     { MOD_TABLE (MOD_0F18_REG_1) },
3599     { MOD_TABLE (MOD_0F18_REG_2) },
3600     { MOD_TABLE (MOD_0F18_REG_3) },
3601     { MOD_TABLE (MOD_0F18_REG_4) },
3602     { MOD_TABLE (MOD_0F18_REG_5) },
3603     { MOD_TABLE (MOD_0F18_REG_6) },
3604     { MOD_TABLE (MOD_0F18_REG_7) },
3605   },
3606   /* REG_0F1E_MOD_3 */
3607   {
3608     { "nopQ",           { Ev }, 0 },
3609     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3610     { "nopQ",           { Ev }, 0 },
3611     { "nopQ",           { Ev }, 0 },
3612     { "nopQ",           { Ev }, 0 },
3613     { "nopQ",           { Ev }, 0 },
3614     { "nopQ",           { Ev }, 0 },
3615     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3616   },
3617   /* REG_0F71 */
3618   {
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_0F71_REG_2) },
3622     { Bad_Opcode },
3623     { MOD_TABLE (MOD_0F71_REG_4) },
3624     { Bad_Opcode },
3625     { MOD_TABLE (MOD_0F71_REG_6) },
3626   },
3627   /* REG_0F72 */
3628   {
3629     { Bad_Opcode },
3630     { Bad_Opcode },
3631     { MOD_TABLE (MOD_0F72_REG_2) },
3632     { Bad_Opcode },
3633     { MOD_TABLE (MOD_0F72_REG_4) },
3634     { Bad_Opcode },
3635     { MOD_TABLE (MOD_0F72_REG_6) },
3636   },
3637   /* REG_0F73 */
3638   {
3639     { Bad_Opcode },
3640     { Bad_Opcode },
3641     { MOD_TABLE (MOD_0F73_REG_2) },
3642     { MOD_TABLE (MOD_0F73_REG_3) },
3643     { Bad_Opcode },
3644     { Bad_Opcode },
3645     { MOD_TABLE (MOD_0F73_REG_6) },
3646     { MOD_TABLE (MOD_0F73_REG_7) },
3647   },
3648   /* REG_0FA6 */
3649   {
3650     { "montmul",        { { OP_0f07, 0 } }, 0 },
3651     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3652     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3653   },
3654   /* REG_0FA7 */
3655   {
3656     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3657     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3658     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3659     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3660     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3661     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3662   },
3663   /* REG_0FAE */
3664   {
3665     { MOD_TABLE (MOD_0FAE_REG_0) },
3666     { MOD_TABLE (MOD_0FAE_REG_1) },
3667     { MOD_TABLE (MOD_0FAE_REG_2) },
3668     { MOD_TABLE (MOD_0FAE_REG_3) },
3669     { MOD_TABLE (MOD_0FAE_REG_4) },
3670     { MOD_TABLE (MOD_0FAE_REG_5) },
3671     { MOD_TABLE (MOD_0FAE_REG_6) },
3672     { MOD_TABLE (MOD_0FAE_REG_7) },
3673   },
3674   /* REG_0FBA */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { Bad_Opcode },
3679     { Bad_Opcode },
3680     { "btQ",    { Ev, Ib }, 0 },
3681     { "btsQ",   { Evh1, Ib }, 0 },
3682     { "btrQ",   { Evh1, Ib }, 0 },
3683     { "btcQ",   { Evh1, Ib }, 0 },
3684   },
3685   /* REG_0FC7 */
3686   {
3687     { Bad_Opcode },
3688     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3689     { Bad_Opcode },
3690     { MOD_TABLE (MOD_0FC7_REG_3) },
3691     { MOD_TABLE (MOD_0FC7_REG_4) },
3692     { MOD_TABLE (MOD_0FC7_REG_5) },
3693     { MOD_TABLE (MOD_0FC7_REG_6) },
3694     { MOD_TABLE (MOD_0FC7_REG_7) },
3695   },
3696   /* REG_VEX_0F71 */
3697   {
3698     { Bad_Opcode },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3701     { Bad_Opcode },
3702     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3703     { Bad_Opcode },
3704     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3705   },
3706   /* REG_VEX_0F72 */
3707   {
3708     { Bad_Opcode },
3709     { Bad_Opcode },
3710     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3711     { Bad_Opcode },
3712     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3713     { Bad_Opcode },
3714     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3715   },
3716   /* REG_VEX_0F73 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3721     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3722     { Bad_Opcode },
3723     { Bad_Opcode },
3724     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3725     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3726   },
3727   /* REG_VEX_0FAE */
3728   {
3729     { Bad_Opcode },
3730     { Bad_Opcode },
3731     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3732     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3733   },
3734   /* REG_VEX_0F38F3 */
3735   {
3736     { Bad_Opcode },
3737     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3738     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3739     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3740   },
3741   /* REG_XOP_LWPCB */
3742   {
3743     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3744     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3745   },
3746   /* REG_XOP_LWP */
3747   {
3748     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3749     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3750   },
3751   /* REG_XOP_TBM_01 */
3752   {
3753     { Bad_Opcode },
3754     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3755     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3756     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3757     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3758     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3759     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3760     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3761   },
3762   /* REG_XOP_TBM_02 */
3763   {
3764     { Bad_Opcode },
3765     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3766     { Bad_Opcode },
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { Bad_Opcode },
3770     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3771   },
3772 #define NEED_REG_TABLE
3773 #include "i386-dis-evex.h"
3774 #undef NEED_REG_TABLE
3775 };
3776
3777 static const struct dis386 prefix_table[][4] = {
3778   /* PREFIX_90 */
3779   {
3780     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3781     { "pause", { XX }, 0 },
3782     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3783     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3784   },
3785
3786   /* PREFIX_MOD_0_0F01_REG_5 */
3787   {
3788     { Bad_Opcode },
3789     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3793   {
3794     { Bad_Opcode },
3795     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3799   {
3800     { Bad_Opcode },
3801     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3802   },
3803
3804   /* PREFIX_0F10 */
3805   {
3806     { "movups", { XM, EXx }, PREFIX_OPCODE },
3807     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3808     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3809     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F11 */
3813   {
3814     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3815     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3816     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3817     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F12 */
3821   {
3822     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3823     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3824     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3825     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F16 */
3829   {
3830     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3831     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3832     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3833   },
3834
3835   /* PREFIX_0F1A */
3836   {
3837     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3838     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3839     { "bndmov", { Gbnd, Ebnd }, 0 },
3840     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3841   },
3842
3843   /* PREFIX_0F1B */
3844   {
3845     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3846     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3847     { "bndmov", { Ebnd, Gbnd }, 0 },
3848     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3849   },
3850
3851   /* PREFIX_0F1E */
3852   {
3853     { "nopQ",   { Ev }, PREFIX_OPCODE },
3854     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3855     { "nopQ",   { Ev }, PREFIX_OPCODE },
3856     { "nopQ",   { Ev }, PREFIX_OPCODE },
3857   },
3858
3859   /* PREFIX_0F2A */
3860   {
3861     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3862     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3863     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3864     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3865   },
3866
3867   /* PREFIX_0F2B */
3868   {
3869     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3870     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3871     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3872     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3873   },
3874
3875   /* PREFIX_0F2C */
3876   {
3877     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3878     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3879     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3880     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F2D */
3884   {
3885     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3886     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3887     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3888     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F2E */
3892   {
3893     { "ucomiss",{ XM, EXd }, 0 },
3894     { Bad_Opcode },
3895     { "ucomisd",{ XM, EXq }, 0 },
3896   },
3897
3898   /* PREFIX_0F2F */
3899   {
3900     { "comiss", { XM, EXd }, 0 },
3901     { Bad_Opcode },
3902     { "comisd", { XM, EXq }, 0 },
3903   },
3904
3905   /* PREFIX_0F51 */
3906   {
3907     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3908     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3909     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3910     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3911   },
3912
3913   /* PREFIX_0F52 */
3914   {
3915     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3916     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3917   },
3918
3919   /* PREFIX_0F53 */
3920   {
3921     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3922     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3923   },
3924
3925   /* PREFIX_0F58 */
3926   {
3927     { "addps", { XM, EXx }, PREFIX_OPCODE },
3928     { "addss", { XM, EXd }, PREFIX_OPCODE },
3929     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3930     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3931   },
3932
3933   /* PREFIX_0F59 */
3934   {
3935     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3936     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3937     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3938     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3939   },
3940
3941   /* PREFIX_0F5A */
3942   {
3943     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3944     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3945     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3946     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F5B */
3950   {
3951     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3952     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3953     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3954   },
3955
3956   /* PREFIX_0F5C */
3957   {
3958     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3959     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3960     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3961     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F5D */
3965   {
3966     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3967     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3968     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3969     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3970   },
3971
3972   /* PREFIX_0F5E */
3973   {
3974     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3975     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3976     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3977     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F5F */
3981   {
3982     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3983     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3984     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3985     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_0F60 */
3989   {
3990     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3991     { Bad_Opcode },
3992     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0F61 */
3996   {
3997     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3998     { Bad_Opcode },
3999     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F62 */
4003   {
4004     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4005     { Bad_Opcode },
4006     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4007   },
4008
4009   /* PREFIX_0F6C */
4010   {
4011     { Bad_Opcode },
4012     { Bad_Opcode },
4013     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0F6D */
4017   {
4018     { Bad_Opcode },
4019     { Bad_Opcode },
4020     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4021   },
4022
4023   /* PREFIX_0F6F */
4024   {
4025     { "movq",   { MX, EM }, PREFIX_OPCODE },
4026     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4027     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4028   },
4029
4030   /* PREFIX_0F70 */
4031   {
4032     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4033     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4034     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4035     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4036   },
4037
4038   /* PREFIX_0F73_REG_3 */
4039   {
4040     { Bad_Opcode },
4041     { Bad_Opcode },
4042     { "psrldq", { XS, Ib }, 0 },
4043   },
4044
4045   /* PREFIX_0F73_REG_7 */
4046   {
4047     { Bad_Opcode },
4048     { Bad_Opcode },
4049     { "pslldq", { XS, Ib }, 0 },
4050   },
4051
4052   /* PREFIX_0F78 */
4053   {
4054     {"vmread",  { Em, Gm }, 0 },
4055     { Bad_Opcode },
4056     {"extrq",   { XS, Ib, Ib }, 0 },
4057     {"insertq", { XM, XS, Ib, Ib }, 0 },
4058   },
4059
4060   /* PREFIX_0F79 */
4061   {
4062     {"vmwrite", { Gm, Em }, 0 },
4063     { Bad_Opcode },
4064     {"extrq",   { XM, XS }, 0 },
4065     {"insertq", { XM, XS }, 0 },
4066   },
4067
4068   /* PREFIX_0F7C */
4069   {
4070     { Bad_Opcode },
4071     { Bad_Opcode },
4072     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4073     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4074   },
4075
4076   /* PREFIX_0F7D */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4081     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4082   },
4083
4084   /* PREFIX_0F7E */
4085   {
4086     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4087     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4088     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0F7F */
4092   {
4093     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4094     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4095     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4096   },
4097
4098   /* PREFIX_0FAE_REG_0 */
4099   {
4100     { Bad_Opcode },
4101     { "rdfsbase", { Ev }, 0 },
4102   },
4103
4104   /* PREFIX_0FAE_REG_1 */
4105   {
4106     { Bad_Opcode },
4107     { "rdgsbase", { Ev }, 0 },
4108   },
4109
4110   /* PREFIX_0FAE_REG_2 */
4111   {
4112     { Bad_Opcode },
4113     { "wrfsbase", { Ev }, 0 },
4114   },
4115
4116   /* PREFIX_0FAE_REG_3 */
4117   {
4118     { Bad_Opcode },
4119     { "wrgsbase", { Ev }, 0 },
4120   },
4121
4122   /* PREFIX_MOD_0_0FAE_REG_4 */
4123   {
4124     { "xsave",  { FXSAVE }, 0 },
4125     { "ptwrite%LQ", { Edq }, 0 },
4126   },
4127
4128   /* PREFIX_MOD_3_0FAE_REG_4 */
4129   {
4130     { Bad_Opcode },
4131     { "ptwrite%LQ", { Edq }, 0 },
4132   },
4133
4134   /* PREFIX_MOD_0_0FAE_REG_5 */
4135   {
4136     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4137   },
4138
4139   /* PREFIX_MOD_3_0FAE_REG_5 */
4140   {
4141     { "lfence",         { Skip_MODRM }, 0 },
4142     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4143   },
4144
4145   /* PREFIX_0FAE_REG_6 */
4146   {
4147     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4148     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4149     { "clwb",   { Mb }, PREFIX_OPCODE },
4150   },
4151
4152   /* PREFIX_0FAE_REG_7 */
4153   {
4154     { "clflush",        { Mb }, 0 },
4155     { Bad_Opcode },
4156     { "clflushopt",     { Mb }, 0 },
4157   },
4158
4159   /* PREFIX_0FB8 */
4160   {
4161     { Bad_Opcode },
4162     { "popcntS", { Gv, Ev }, 0 },
4163   },
4164
4165   /* PREFIX_0FBC */
4166   {
4167     { "bsfS",   { Gv, Ev }, 0 },
4168     { "tzcntS", { Gv, Ev }, 0 },
4169     { "bsfS",   { Gv, Ev }, 0 },
4170   },
4171
4172   /* PREFIX_0FBD */
4173   {
4174     { "bsrS",   { Gv, Ev }, 0 },
4175     { "lzcntS", { Gv, Ev }, 0 },
4176     { "bsrS",   { Gv, Ev }, 0 },
4177   },
4178
4179   /* PREFIX_0FC2 */
4180   {
4181     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4182     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4183     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4184     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4185   },
4186
4187   /* PREFIX_MOD_0_0FC3 */
4188   {
4189     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4190   },
4191
4192   /* PREFIX_MOD_0_0FC7_REG_6 */
4193   {
4194     { "vmptrld",{ Mq }, 0 },
4195     { "vmxon",  { Mq }, 0 },
4196     { "vmclear",{ Mq }, 0 },
4197   },
4198
4199   /* PREFIX_MOD_3_0FC7_REG_6 */
4200   {
4201     { "rdrand", { Ev }, 0 },
4202     { Bad_Opcode },
4203     { "rdrand", { Ev }, 0 }
4204   },
4205
4206   /* PREFIX_MOD_3_0FC7_REG_7 */
4207   {
4208     { "rdseed", { Ev }, 0 },
4209     { "rdpid",  { Em }, 0 },
4210     { "rdseed", { Ev }, 0 },
4211   },
4212
4213   /* PREFIX_0FD0 */
4214   {
4215     { Bad_Opcode },
4216     { Bad_Opcode },
4217     { "addsubpd", { XM, EXx }, 0 },
4218     { "addsubps", { XM, EXx }, 0 },
4219   },
4220
4221   /* PREFIX_0FD6 */
4222   {
4223     { Bad_Opcode },
4224     { "movq2dq",{ XM, MS }, 0 },
4225     { "movq",   { EXqS, XM }, 0 },
4226     { "movdq2q",{ MX, XS }, 0 },
4227   },
4228
4229   /* PREFIX_0FE6 */
4230   {
4231     { Bad_Opcode },
4232     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4233     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4234     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4235   },
4236
4237   /* PREFIX_0FE7 */
4238   {
4239     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4240     { Bad_Opcode },
4241     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4242   },
4243
4244   /* PREFIX_0FF0 */
4245   {
4246     { Bad_Opcode },
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4250   },
4251
4252   /* PREFIX_0FF7 */
4253   {
4254     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4255     { Bad_Opcode },
4256     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3810 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F3814 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F3815 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F3817 */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F3820 */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3821 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F3822 */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F3823 */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F3824 */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F3825 */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F3828 */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F3829 */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F382A */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4348   },
4349
4350   /* PREFIX_0F382B */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3830 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3831 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3832 */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F3833 */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F3834 */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F3835 */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3837 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3838 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3839 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F383A */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F383B */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F383C */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F383D */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F383E */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F383F */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3840 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3841 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3880 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3881 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3882 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F38C8 */
4498   {
4499     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F38C9 */
4503   {
4504     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4505   },
4506
4507   /* PREFIX_0F38CA */
4508   {
4509     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F38CB */
4513   {
4514     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F38CC */
4518   {
4519     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F38CD */
4523   {
4524     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4525   },
4526
4527   /* PREFIX_0F38DB */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4532   },
4533
4534   /* PREFIX_0F38DC */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4539   },
4540
4541   /* PREFIX_0F38DD */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4546   },
4547
4548   /* PREFIX_0F38DE */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4553   },
4554
4555   /* PREFIX_0F38DF */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4560   },
4561
4562   /* PREFIX_0F38F0 */
4563   {
4564     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4565     { Bad_Opcode },
4566     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4567     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4568   },
4569
4570   /* PREFIX_0F38F1 */
4571   {
4572     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4573     { Bad_Opcode },
4574     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4575     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F38F5 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4583   },
4584
4585   /* PREFIX_0F38F6 */
4586   {
4587     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4588     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4589     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4590     { Bad_Opcode },
4591   },
4592
4593   /* PREFIX_0F3A08 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A09 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3A0A */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3A0B */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3A0C */
4622   {
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4626   },
4627
4628   /* PREFIX_0F3A0D */
4629   {
4630     { Bad_Opcode },
4631     { Bad_Opcode },
4632     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4633   },
4634
4635   /* PREFIX_0F3A0E */
4636   {
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4640   },
4641
4642   /* PREFIX_0F3A14 */
4643   {
4644     { Bad_Opcode },
4645     { Bad_Opcode },
4646     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4647   },
4648
4649   /* PREFIX_0F3A15 */
4650   {
4651     { Bad_Opcode },
4652     { Bad_Opcode },
4653     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4654   },
4655
4656   /* PREFIX_0F3A16 */
4657   {
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4661   },
4662
4663   /* PREFIX_0F3A17 */
4664   {
4665     { Bad_Opcode },
4666     { Bad_Opcode },
4667     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4668   },
4669
4670   /* PREFIX_0F3A20 */
4671   {
4672     { Bad_Opcode },
4673     { Bad_Opcode },
4674     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4675   },
4676
4677   /* PREFIX_0F3A21 */
4678   {
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4682   },
4683
4684   /* PREFIX_0F3A22 */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4689   },
4690
4691   /* PREFIX_0F3A40 */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4696   },
4697
4698   /* PREFIX_0F3A41 */
4699   {
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4703   },
4704
4705   /* PREFIX_0F3A42 */
4706   {
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4710   },
4711
4712   /* PREFIX_0F3A44 */
4713   {
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4717   },
4718
4719   /* PREFIX_0F3A60 */
4720   {
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4724   },
4725
4726   /* PREFIX_0F3A61 */
4727   {
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4731   },
4732
4733   /* PREFIX_0F3A62 */
4734   {
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4738   },
4739
4740   /* PREFIX_0F3A63 */
4741   {
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4745   },
4746
4747   /* PREFIX_0F3ACC */
4748   {
4749     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4750   },
4751
4752   /* PREFIX_0F3ADF */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4757   },
4758
4759   /* PREFIX_VEX_0F10 */
4760   {
4761     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4762     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4763     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4764     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4765   },
4766
4767   /* PREFIX_VEX_0F11 */
4768   {
4769     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4770     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4771     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4772     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4773   },
4774
4775   /* PREFIX_VEX_0F12 */
4776   {
4777     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4778     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4779     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4780     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4781   },
4782
4783   /* PREFIX_VEX_0F16 */
4784   {
4785     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4786     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4787     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4788   },
4789
4790   /* PREFIX_VEX_0F2A */
4791   {
4792     { Bad_Opcode },
4793     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4794     { Bad_Opcode },
4795     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4796   },
4797
4798   /* PREFIX_VEX_0F2C */
4799   {
4800     { Bad_Opcode },
4801     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4802     { Bad_Opcode },
4803     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4804   },
4805
4806   /* PREFIX_VEX_0F2D */
4807   {
4808     { Bad_Opcode },
4809     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4810     { Bad_Opcode },
4811     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4812   },
4813
4814   /* PREFIX_VEX_0F2E */
4815   {
4816     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4817     { Bad_Opcode },
4818     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4819   },
4820
4821   /* PREFIX_VEX_0F2F */
4822   {
4823     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4824     { Bad_Opcode },
4825     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4826   },
4827
4828   /* PREFIX_VEX_0F41 */
4829   {
4830     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4831     { Bad_Opcode },
4832     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4833   },
4834
4835   /* PREFIX_VEX_0F42 */
4836   {
4837     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4838     { Bad_Opcode },
4839     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4840   },
4841
4842   /* PREFIX_VEX_0F44 */
4843   {
4844     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4845     { Bad_Opcode },
4846     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4847   },
4848
4849   /* PREFIX_VEX_0F45 */
4850   {
4851     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4852     { Bad_Opcode },
4853     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4854   },
4855
4856   /* PREFIX_VEX_0F46 */
4857   {
4858     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4859     { Bad_Opcode },
4860     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4861   },
4862
4863   /* PREFIX_VEX_0F47 */
4864   {
4865     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4866     { Bad_Opcode },
4867     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4868   },
4869
4870   /* PREFIX_VEX_0F4A */
4871   {
4872     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4873     { Bad_Opcode },
4874     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4875   },
4876
4877   /* PREFIX_VEX_0F4B */
4878   {
4879     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4880     { Bad_Opcode },
4881     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4882   },
4883
4884   /* PREFIX_VEX_0F51 */
4885   {
4886     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4887     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4888     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4889     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4890   },
4891
4892   /* PREFIX_VEX_0F52 */
4893   {
4894     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4895     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4896   },
4897
4898   /* PREFIX_VEX_0F53 */
4899   {
4900     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4901     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4902   },
4903
4904   /* PREFIX_VEX_0F58 */
4905   {
4906     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4907     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4908     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4909     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4910   },
4911
4912   /* PREFIX_VEX_0F59 */
4913   {
4914     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4915     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4916     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4917     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4918   },
4919
4920   /* PREFIX_VEX_0F5A */
4921   {
4922     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4923     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4924     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4925     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4926   },
4927
4928   /* PREFIX_VEX_0F5B */
4929   {
4930     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4931     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4932     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4933   },
4934
4935   /* PREFIX_VEX_0F5C */
4936   {
4937     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4938     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4939     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4940     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4941   },
4942
4943   /* PREFIX_VEX_0F5D */
4944   {
4945     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4946     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4947     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4948     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4949   },
4950
4951   /* PREFIX_VEX_0F5E */
4952   {
4953     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4954     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4955     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4956     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4957   },
4958
4959   /* PREFIX_VEX_0F5F */
4960   {
4961     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4962     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4963     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4964     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4965   },
4966
4967   /* PREFIX_VEX_0F60 */
4968   {
4969     { Bad_Opcode },
4970     { Bad_Opcode },
4971     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4972   },
4973
4974   /* PREFIX_VEX_0F61 */
4975   {
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4979   },
4980
4981   /* PREFIX_VEX_0F62 */
4982   {
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4986   },
4987
4988   /* PREFIX_VEX_0F63 */
4989   {
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4993   },
4994
4995   /* PREFIX_VEX_0F64 */
4996   {
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5000   },
5001
5002   /* PREFIX_VEX_0F65 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5007   },
5008
5009   /* PREFIX_VEX_0F66 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5014   },
5015
5016   /* PREFIX_VEX_0F67 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5021   },
5022
5023   /* PREFIX_VEX_0F68 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5028   },
5029
5030   /* PREFIX_VEX_0F69 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5035   },
5036
5037   /* PREFIX_VEX_0F6A */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5042   },
5043
5044   /* PREFIX_VEX_0F6B */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5049   },
5050
5051   /* PREFIX_VEX_0F6C */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5056   },
5057
5058   /* PREFIX_VEX_0F6D */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5063   },
5064
5065   /* PREFIX_VEX_0F6E */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5070   },
5071
5072   /* PREFIX_VEX_0F6F */
5073   {
5074     { Bad_Opcode },
5075     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5076     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5077   },
5078
5079   /* PREFIX_VEX_0F70 */
5080   {
5081     { Bad_Opcode },
5082     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5083     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5084     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5085   },
5086
5087   /* PREFIX_VEX_0F71_REG_2 */
5088   {
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F71_REG_4 */
5095   {
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5099   },
5100
5101   /* PREFIX_VEX_0F71_REG_6 */
5102   {
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F72_REG_2 */
5109   {
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F72_REG_4 */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5120   },
5121
5122   /* PREFIX_VEX_0F72_REG_6 */
5123   {
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5127   },
5128
5129   /* PREFIX_VEX_0F73_REG_2 */
5130   {
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5134   },
5135
5136   /* PREFIX_VEX_0F73_REG_3 */
5137   {
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5141   },
5142
5143   /* PREFIX_VEX_0F73_REG_6 */
5144   {
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5148   },
5149
5150   /* PREFIX_VEX_0F73_REG_7 */
5151   {
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5155   },
5156
5157   /* PREFIX_VEX_0F74 */
5158   {
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5162   },
5163
5164   /* PREFIX_VEX_0F75 */
5165   {
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5169   },
5170
5171   /* PREFIX_VEX_0F76 */
5172   {
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5176   },
5177
5178   /* PREFIX_VEX_0F77 */
5179   {
5180     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5181   },
5182
5183   /* PREFIX_VEX_0F7C */
5184   {
5185     { Bad_Opcode },
5186     { Bad_Opcode },
5187     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5188     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5189   },
5190
5191   /* PREFIX_VEX_0F7D */
5192   {
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5196     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5197   },
5198
5199   /* PREFIX_VEX_0F7E */
5200   {
5201     { Bad_Opcode },
5202     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5203     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5204   },
5205
5206   /* PREFIX_VEX_0F7F */
5207   {
5208     { Bad_Opcode },
5209     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5210     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5211   },
5212
5213   /* PREFIX_VEX_0F90 */
5214   {
5215     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5216     { Bad_Opcode },
5217     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5218   },
5219
5220   /* PREFIX_VEX_0F91 */
5221   {
5222     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5223     { Bad_Opcode },
5224     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0F92 */
5228   {
5229     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5230     { Bad_Opcode },
5231     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5232     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5233   },
5234
5235   /* PREFIX_VEX_0F93 */
5236   {
5237     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5238     { Bad_Opcode },
5239     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5240     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5241   },
5242
5243   /* PREFIX_VEX_0F98 */
5244   {
5245     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5246     { Bad_Opcode },
5247     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5248   },
5249
5250   /* PREFIX_VEX_0F99 */
5251   {
5252     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5253     { Bad_Opcode },
5254     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5255   },
5256
5257   /* PREFIX_VEX_0FC2 */
5258   {
5259     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5260     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5261     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5262     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5263   },
5264
5265   /* PREFIX_VEX_0FC4 */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5270   },
5271
5272   /* PREFIX_VEX_0FC5 */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5277   },
5278
5279   /* PREFIX_VEX_0FD0 */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5284     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5285   },
5286
5287   /* PREFIX_VEX_0FD1 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5292   },
5293
5294   /* PREFIX_VEX_0FD2 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5299   },
5300
5301   /* PREFIX_VEX_0FD3 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5306   },
5307
5308   /* PREFIX_VEX_0FD4 */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5313   },
5314
5315   /* PREFIX_VEX_0FD5 */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5320   },
5321
5322   /* PREFIX_VEX_0FD6 */
5323   {
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5327   },
5328
5329   /* PREFIX_VEX_0FD7 */
5330   {
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5334   },
5335
5336   /* PREFIX_VEX_0FD8 */
5337   {
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5341   },
5342
5343   /* PREFIX_VEX_0FD9 */
5344   {
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5348   },
5349
5350   /* PREFIX_VEX_0FDA */
5351   {
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5355   },
5356
5357   /* PREFIX_VEX_0FDB */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FDC */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5369   },
5370
5371   /* PREFIX_VEX_0FDD */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5376   },
5377
5378   /* PREFIX_VEX_0FDE */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5383   },
5384
5385   /* PREFIX_VEX_0FDF */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5390   },
5391
5392   /* PREFIX_VEX_0FE0 */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5397   },
5398
5399   /* PREFIX_VEX_0FE1 */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5404   },
5405
5406   /* PREFIX_VEX_0FE2 */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5411   },
5412
5413   /* PREFIX_VEX_0FE3 */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5418   },
5419
5420   /* PREFIX_VEX_0FE4 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5425   },
5426
5427   /* PREFIX_VEX_0FE5 */
5428   {
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5432   },
5433
5434   /* PREFIX_VEX_0FE6 */
5435   {
5436     { Bad_Opcode },
5437     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5438     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5439     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5440   },
5441
5442   /* PREFIX_VEX_0FE7 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5447   },
5448
5449   /* PREFIX_VEX_0FE8 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5454   },
5455
5456   /* PREFIX_VEX_0FE9 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5461   },
5462
5463   /* PREFIX_VEX_0FEA */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5468   },
5469
5470   /* PREFIX_VEX_0FEB */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0FEC */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5482   },
5483
5484   /* PREFIX_VEX_0FED */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5489   },
5490
5491   /* PREFIX_VEX_0FEE */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5496   },
5497
5498   /* PREFIX_VEX_0FEF */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5503   },
5504
5505   /* PREFIX_VEX_0FF0 */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5511   },
5512
5513   /* PREFIX_VEX_0FF1 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5518   },
5519
5520   /* PREFIX_VEX_0FF2 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5525   },
5526
5527   /* PREFIX_VEX_0FF3 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5532   },
5533
5534   /* PREFIX_VEX_0FF4 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5539   },
5540
5541   /* PREFIX_VEX_0FF5 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5546   },
5547
5548   /* PREFIX_VEX_0FF6 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5553   },
5554
5555   /* PREFIX_VEX_0FF7 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5560   },
5561
5562   /* PREFIX_VEX_0FF8 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5567   },
5568
5569   /* PREFIX_VEX_0FF9 */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5574   },
5575
5576   /* PREFIX_VEX_0FFA */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5581   },
5582
5583   /* PREFIX_VEX_0FFB */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0FFC */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0FFD */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0FFE */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3800 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F3801 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F3802 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5630   },
5631
5632   /* PREFIX_VEX_0F3803 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3804 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F3805 */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F3806 */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5658   },
5659
5660   /* PREFIX_VEX_0F3807 */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5665   },
5666
5667   /* PREFIX_VEX_0F3808 */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5672   },
5673
5674   /* PREFIX_VEX_0F3809 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5679   },
5680
5681   /* PREFIX_VEX_0F380A */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5686   },
5687
5688   /* PREFIX_VEX_0F380B */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5693   },
5694
5695   /* PREFIX_VEX_0F380C */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5700   },
5701
5702   /* PREFIX_VEX_0F380D */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5707   },
5708
5709   /* PREFIX_VEX_0F380E */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5714   },
5715
5716   /* PREFIX_VEX_0F380F */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5721   },
5722
5723   /* PREFIX_VEX_0F3813 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F3816 */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F3817 */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5742   },
5743
5744   /* PREFIX_VEX_0F3818 */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F3819 */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F381A */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F381C */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F381D */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5777   },
5778
5779   /* PREFIX_VEX_0F381E */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5784   },
5785
5786   /* PREFIX_VEX_0F3820 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5791   },
5792
5793   /* PREFIX_VEX_0F3821 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5798   },
5799
5800   /* PREFIX_VEX_0F3822 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5805   },
5806
5807   /* PREFIX_VEX_0F3823 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5812   },
5813
5814   /* PREFIX_VEX_0F3824 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F3825 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5826   },
5827
5828   /* PREFIX_VEX_0F3828 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5833   },
5834
5835   /* PREFIX_VEX_0F3829 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5840   },
5841
5842   /* PREFIX_VEX_0F382A */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5847   },
5848
5849   /* PREFIX_VEX_0F382B */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5854   },
5855
5856   /* PREFIX_VEX_0F382C */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5861   },
5862
5863   /* PREFIX_VEX_0F382D */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5868   },
5869
5870   /* PREFIX_VEX_0F382E */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5875   },
5876
5877   /* PREFIX_VEX_0F382F */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5882   },
5883
5884   /* PREFIX_VEX_0F3830 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5889   },
5890
5891   /* PREFIX_VEX_0F3831 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F3832 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5903   },
5904
5905   /* PREFIX_VEX_0F3833 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F3834 */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5917   },
5918
5919   /* PREFIX_VEX_0F3835 */
5920   {
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5924   },
5925
5926   /* PREFIX_VEX_0F3836 */
5927   {
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5931   },
5932
5933   /* PREFIX_VEX_0F3837 */
5934   {
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5938   },
5939
5940   /* PREFIX_VEX_0F3838 */
5941   {
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5945   },
5946
5947   /* PREFIX_VEX_0F3839 */
5948   {
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5952   },
5953
5954   /* PREFIX_VEX_0F383A */
5955   {
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5959   },
5960
5961   /* PREFIX_VEX_0F383B */
5962   {
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5966   },
5967
5968   /* PREFIX_VEX_0F383C */
5969   {
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5973   },
5974
5975   /* PREFIX_VEX_0F383D */
5976   {
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5980   },
5981
5982   /* PREFIX_VEX_0F383E */
5983   {
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5987   },
5988
5989   /* PREFIX_VEX_0F383F */
5990   {
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5994   },
5995
5996   /* PREFIX_VEX_0F3840 */
5997   {
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6001   },
6002
6003   /* PREFIX_VEX_0F3841 */
6004   {
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6008   },
6009
6010   /* PREFIX_VEX_0F3845 */
6011   {
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6015   },
6016
6017   /* PREFIX_VEX_0F3846 */
6018   {
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6022   },
6023
6024   /* PREFIX_VEX_0F3847 */
6025   {
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6029   },
6030
6031   /* PREFIX_VEX_0F3858 */
6032   {
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6036   },
6037
6038   /* PREFIX_VEX_0F3859 */
6039   {
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6043   },
6044
6045   /* PREFIX_VEX_0F385A */
6046   {
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6050   },
6051
6052   /* PREFIX_VEX_0F3878 */
6053   {
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6057   },
6058
6059   /* PREFIX_VEX_0F3879 */
6060   {
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6064   },
6065
6066   /* PREFIX_VEX_0F388C */
6067   {
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6071   },
6072
6073   /* PREFIX_VEX_0F388E */
6074   {
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6078   },
6079
6080   /* PREFIX_VEX_0F3890 */
6081   {
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6085   },
6086
6087   /* PREFIX_VEX_0F3891 */
6088   {
6089     { Bad_Opcode },
6090     { Bad_Opcode },
6091     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6092   },
6093
6094   /* PREFIX_VEX_0F3892 */
6095   {
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6099   },
6100
6101   /* PREFIX_VEX_0F3893 */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F3896 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6113   },
6114
6115   /* PREFIX_VEX_0F3897 */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6120   },
6121
6122   /* PREFIX_VEX_0F3898 */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F3899 */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F389A */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F389B */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F389C */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F389D */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F389E */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F389F */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F38A6 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6183     { Bad_Opcode },
6184   },
6185
6186   /* PREFIX_VEX_0F38A7 */
6187   {
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6191   },
6192
6193   /* PREFIX_VEX_0F38A8 */
6194   {
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6198   },
6199
6200   /* PREFIX_VEX_0F38A9 */
6201   {
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6205   },
6206
6207   /* PREFIX_VEX_0F38AA */
6208   {
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6212   },
6213
6214   /* PREFIX_VEX_0F38AB */
6215   {
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6219   },
6220
6221   /* PREFIX_VEX_0F38AC */
6222   {
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6226   },
6227
6228   /* PREFIX_VEX_0F38AD */
6229   {
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6233   },
6234
6235   /* PREFIX_VEX_0F38AE */
6236   {
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6240   },
6241
6242   /* PREFIX_VEX_0F38AF */
6243   {
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6247   },
6248
6249   /* PREFIX_VEX_0F38B6 */
6250   {
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6254   },
6255
6256   /* PREFIX_VEX_0F38B7 */
6257   {
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6261   },
6262
6263   /* PREFIX_VEX_0F38B8 */
6264   {
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6268   },
6269
6270   /* PREFIX_VEX_0F38B9 */
6271   {
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6275   },
6276
6277   /* PREFIX_VEX_0F38BA */
6278   {
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6282   },
6283
6284   /* PREFIX_VEX_0F38BB */
6285   {
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6289   },
6290
6291   /* PREFIX_VEX_0F38BC */
6292   {
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6296   },
6297
6298   /* PREFIX_VEX_0F38BD */
6299   {
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6303   },
6304
6305   /* PREFIX_VEX_0F38BE */
6306   {
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6310   },
6311
6312   /* PREFIX_VEX_0F38BF */
6313   {
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6317   },
6318
6319   /* PREFIX_VEX_0F38DB */
6320   {
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6324   },
6325
6326   /* PREFIX_VEX_0F38DC */
6327   {
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6331   },
6332
6333   /* PREFIX_VEX_0F38DD */
6334   {
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6338   },
6339
6340   /* PREFIX_VEX_0F38DE */
6341   {
6342     { Bad_Opcode },
6343     { Bad_Opcode },
6344     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6345   },
6346
6347   /* PREFIX_VEX_0F38DF */
6348   {
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6352   },
6353
6354   /* PREFIX_VEX_0F38F2 */
6355   {
6356     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6357   },
6358
6359   /* PREFIX_VEX_0F38F3_REG_1 */
6360   {
6361     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6362   },
6363
6364   /* PREFIX_VEX_0F38F3_REG_2 */
6365   {
6366     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6367   },
6368
6369   /* PREFIX_VEX_0F38F3_REG_3 */
6370   {
6371     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6372   },
6373
6374   /* PREFIX_VEX_0F38F5 */
6375   {
6376     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6377     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6378     { Bad_Opcode },
6379     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6380   },
6381
6382   /* PREFIX_VEX_0F38F6 */
6383   {
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6388   },
6389
6390   /* PREFIX_VEX_0F38F7 */
6391   {
6392     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6393     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6394     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6395     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6396   },
6397
6398   /* PREFIX_VEX_0F3A00 */
6399   {
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6403   },
6404
6405   /* PREFIX_VEX_0F3A01 */
6406   {
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6410   },
6411
6412   /* PREFIX_VEX_0F3A02 */
6413   {
6414     { Bad_Opcode },
6415     { Bad_Opcode },
6416     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6417   },
6418
6419   /* PREFIX_VEX_0F3A04 */
6420   {
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6424   },
6425
6426   /* PREFIX_VEX_0F3A05 */
6427   {
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6431   },
6432
6433   /* PREFIX_VEX_0F3A06 */
6434   {
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6438   },
6439
6440   /* PREFIX_VEX_0F3A08 */
6441   {
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6445   },
6446
6447   /* PREFIX_VEX_0F3A09 */
6448   {
6449     { Bad_Opcode },
6450     { Bad_Opcode },
6451     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6452   },
6453
6454   /* PREFIX_VEX_0F3A0A */
6455   {
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6459   },
6460
6461   /* PREFIX_VEX_0F3A0B */
6462   {
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6466   },
6467
6468   /* PREFIX_VEX_0F3A0C */
6469   {
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6473   },
6474
6475   /* PREFIX_VEX_0F3A0D */
6476   {
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6480   },
6481
6482   /* PREFIX_VEX_0F3A0E */
6483   {
6484     { Bad_Opcode },
6485     { Bad_Opcode },
6486     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6487   },
6488
6489   /* PREFIX_VEX_0F3A0F */
6490   {
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6494   },
6495
6496   /* PREFIX_VEX_0F3A14 */
6497   {
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6501   },
6502
6503   /* PREFIX_VEX_0F3A15 */
6504   {
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6508   },
6509
6510   /* PREFIX_VEX_0F3A16 */
6511   {
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6515   },
6516
6517   /* PREFIX_VEX_0F3A17 */
6518   {
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6522   },
6523
6524   /* PREFIX_VEX_0F3A18 */
6525   {
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6529   },
6530
6531   /* PREFIX_VEX_0F3A19 */
6532   {
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6536   },
6537
6538   /* PREFIX_VEX_0F3A1D */
6539   {
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6543   },
6544
6545   /* PREFIX_VEX_0F3A20 */
6546   {
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6550   },
6551
6552   /* PREFIX_VEX_0F3A21 */
6553   {
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6557   },
6558
6559   /* PREFIX_VEX_0F3A22 */
6560   {
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6564   },
6565
6566   /* PREFIX_VEX_0F3A30 */
6567   {
6568     { Bad_Opcode },
6569     { Bad_Opcode },
6570     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6571   },
6572
6573   /* PREFIX_VEX_0F3A31 */
6574   {
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6578   },
6579
6580   /* PREFIX_VEX_0F3A32 */
6581   {
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6585   },
6586
6587   /* PREFIX_VEX_0F3A33 */
6588   {
6589     { Bad_Opcode },
6590     { Bad_Opcode },
6591     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6592   },
6593
6594   /* PREFIX_VEX_0F3A38 */
6595   {
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6599   },
6600
6601   /* PREFIX_VEX_0F3A39 */
6602   {
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6606   },
6607
6608   /* PREFIX_VEX_0F3A40 */
6609   {
6610     { Bad_Opcode },
6611     { Bad_Opcode },
6612     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6613   },
6614
6615   /* PREFIX_VEX_0F3A41 */
6616   {
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6620   },
6621
6622   /* PREFIX_VEX_0F3A42 */
6623   {
6624     { Bad_Opcode },
6625     { Bad_Opcode },
6626     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6627   },
6628
6629   /* PREFIX_VEX_0F3A44 */
6630   {
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6634   },
6635
6636   /* PREFIX_VEX_0F3A46 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6641   },
6642
6643   /* PREFIX_VEX_0F3A48 */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A49 */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A4A */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6662   },
6663
6664   /* PREFIX_VEX_0F3A4B */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6669   },
6670
6671   /* PREFIX_VEX_0F3A4C */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A5C */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6683   },
6684
6685   /* PREFIX_VEX_0F3A5D */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3A5E */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6697   },
6698
6699   /* PREFIX_VEX_0F3A5F */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6704   },
6705
6706   /* PREFIX_VEX_0F3A60 */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6711     { Bad_Opcode },
6712   },
6713
6714   /* PREFIX_VEX_0F3A61 */
6715   {
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6719   },
6720
6721   /* PREFIX_VEX_0F3A62 */
6722   {
6723     { Bad_Opcode },
6724     { Bad_Opcode },
6725     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6726   },
6727
6728   /* PREFIX_VEX_0F3A63 */
6729   {
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6733   },
6734
6735   /* PREFIX_VEX_0F3A68 */
6736   {
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6740   },
6741
6742   /* PREFIX_VEX_0F3A69 */
6743   {
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6747   },
6748
6749   /* PREFIX_VEX_0F3A6A */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6754   },
6755
6756   /* PREFIX_VEX_0F3A6B */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6761   },
6762
6763   /* PREFIX_VEX_0F3A6C */
6764   {
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6768   },
6769
6770   /* PREFIX_VEX_0F3A6D */
6771   {
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6775   },
6776
6777   /* PREFIX_VEX_0F3A6E */
6778   {
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6782   },
6783
6784   /* PREFIX_VEX_0F3A6F */
6785   {
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6789   },
6790
6791   /* PREFIX_VEX_0F3A78 */
6792   {
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6796   },
6797
6798   /* PREFIX_VEX_0F3A79 */
6799   {
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6803   },
6804
6805   /* PREFIX_VEX_0F3A7A */
6806   {
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6810   },
6811
6812   /* PREFIX_VEX_0F3A7B */
6813   {
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6817   },
6818
6819   /* PREFIX_VEX_0F3A7C */
6820   {
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6824     { Bad_Opcode },
6825   },
6826
6827   /* PREFIX_VEX_0F3A7D */
6828   {
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6832   },
6833
6834   /* PREFIX_VEX_0F3A7E */
6835   {
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6839   },
6840
6841   /* PREFIX_VEX_0F3A7F */
6842   {
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6846   },
6847
6848   /* PREFIX_VEX_0F3ADF */
6849   {
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6853   },
6854
6855   /* PREFIX_VEX_0F3AF0 */
6856   {
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6861   },
6862
6863 #define NEED_PREFIX_TABLE
6864 #include "i386-dis-evex.h"
6865 #undef NEED_PREFIX_TABLE
6866 };
6867
6868 static const struct dis386 x86_64_table[][2] = {
6869   /* X86_64_06 */
6870   {
6871     { "pushP", { es }, 0 },
6872   },
6873
6874   /* X86_64_07 */
6875   {
6876     { "popP", { es }, 0 },
6877   },
6878
6879   /* X86_64_0D */
6880   {
6881     { "pushP", { cs }, 0 },
6882   },
6883
6884   /* X86_64_16 */
6885   {
6886     { "pushP", { ss }, 0 },
6887   },
6888
6889   /* X86_64_17 */
6890   {
6891     { "popP", { ss }, 0 },
6892   },
6893
6894   /* X86_64_1E */
6895   {
6896     { "pushP", { ds }, 0 },
6897   },
6898
6899   /* X86_64_1F */
6900   {
6901     { "popP", { ds }, 0 },
6902   },
6903
6904   /* X86_64_27 */
6905   {
6906     { "daa", { XX }, 0 },
6907   },
6908
6909   /* X86_64_2F */
6910   {
6911     { "das", { XX }, 0 },
6912   },
6913
6914   /* X86_64_37 */
6915   {
6916     { "aaa", { XX }, 0 },
6917   },
6918
6919   /* X86_64_3F */
6920   {
6921     { "aas", { XX }, 0 },
6922   },
6923
6924   /* X86_64_60 */
6925   {
6926     { "pushaP", { XX }, 0 },
6927   },
6928
6929   /* X86_64_61 */
6930   {
6931     { "popaP", { XX }, 0 },
6932   },
6933
6934   /* X86_64_62 */
6935   {
6936     { MOD_TABLE (MOD_62_32BIT) },
6937     { EVEX_TABLE (EVEX_0F) },
6938   },
6939
6940   /* X86_64_63 */
6941   {
6942     { "arpl", { Ew, Gw }, 0 },
6943     { "movs{lq|xd}", { Gv, Ed }, 0 },
6944   },
6945
6946   /* X86_64_6D */
6947   {
6948     { "ins{R|}", { Yzr, indirDX }, 0 },
6949     { "ins{G|}", { Yzr, indirDX }, 0 },
6950   },
6951
6952   /* X86_64_6F */
6953   {
6954     { "outs{R|}", { indirDXr, Xz }, 0 },
6955     { "outs{G|}", { indirDXr, Xz }, 0 },
6956   },
6957
6958   /* X86_64_82 */
6959   {
6960     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6961     { REG_TABLE (REG_80) },
6962   },
6963
6964   /* X86_64_9A */
6965   {
6966     { "Jcall{T|}", { Ap }, 0 },
6967   },
6968
6969   /* X86_64_C4 */
6970   {
6971     { MOD_TABLE (MOD_C4_32BIT) },
6972     { VEX_C4_TABLE (VEX_0F) },
6973   },
6974
6975   /* X86_64_C5 */
6976   {
6977     { MOD_TABLE (MOD_C5_32BIT) },
6978     { VEX_C5_TABLE (VEX_0F) },
6979   },
6980
6981   /* X86_64_CE */
6982   {
6983     { "into", { XX }, 0 },
6984   },
6985
6986   /* X86_64_D4 */
6987   {
6988     { "aam", { Ib }, 0 },
6989   },
6990
6991   /* X86_64_D5 */
6992   {
6993     { "aad", { Ib }, 0 },
6994   },
6995
6996   /* X86_64_E8 */
6997   {
6998     { "callP",          { Jv, BND }, 0 },
6999     { "call@",          { Jv, BND }, 0 }
7000   },
7001
7002   /* X86_64_E9 */
7003   {
7004     { "jmpP",           { Jv, BND }, 0 },
7005     { "jmp@",           { Jv, BND }, 0 }
7006   },
7007
7008   /* X86_64_EA */
7009   {
7010     { "Jjmp{T|}", { Ap }, 0 },
7011   },
7012
7013   /* X86_64_0F01_REG_0 */
7014   {
7015     { "sgdt{Q|IQ}", { M }, 0 },
7016     { "sgdt", { M }, 0 },
7017   },
7018
7019   /* X86_64_0F01_REG_1 */
7020   {
7021     { "sidt{Q|IQ}", { M }, 0 },
7022     { "sidt", { M }, 0 },
7023   },
7024
7025   /* X86_64_0F01_REG_2 */
7026   {
7027     { "lgdt{Q|Q}", { M }, 0 },
7028     { "lgdt", { M }, 0 },
7029   },
7030
7031   /* X86_64_0F01_REG_3 */
7032   {
7033     { "lidt{Q|Q}", { M }, 0 },
7034     { "lidt", { M }, 0 },
7035   },
7036 };
7037
7038 static const struct dis386 three_byte_table[][256] = {
7039
7040   /* THREE_BYTE_0F38 */
7041   {
7042     /* 00 */
7043     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7044     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7045     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7046     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7047     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7048     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7049     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7050     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7051     /* 08 */
7052     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7053     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7054     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7055     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* 10 */
7061     { PREFIX_TABLE (PREFIX_0F3810) },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { PREFIX_TABLE (PREFIX_0F3814) },
7066     { PREFIX_TABLE (PREFIX_0F3815) },
7067     { Bad_Opcode },
7068     { PREFIX_TABLE (PREFIX_0F3817) },
7069     /* 18 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7075     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7076     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7077     { Bad_Opcode },
7078     /* 20 */
7079     { PREFIX_TABLE (PREFIX_0F3820) },
7080     { PREFIX_TABLE (PREFIX_0F3821) },
7081     { PREFIX_TABLE (PREFIX_0F3822) },
7082     { PREFIX_TABLE (PREFIX_0F3823) },
7083     { PREFIX_TABLE (PREFIX_0F3824) },
7084     { PREFIX_TABLE (PREFIX_0F3825) },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* 28 */
7088     { PREFIX_TABLE (PREFIX_0F3828) },
7089     { PREFIX_TABLE (PREFIX_0F3829) },
7090     { PREFIX_TABLE (PREFIX_0F382A) },
7091     { PREFIX_TABLE (PREFIX_0F382B) },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* 30 */
7097     { PREFIX_TABLE (PREFIX_0F3830) },
7098     { PREFIX_TABLE (PREFIX_0F3831) },
7099     { PREFIX_TABLE (PREFIX_0F3832) },
7100     { PREFIX_TABLE (PREFIX_0F3833) },
7101     { PREFIX_TABLE (PREFIX_0F3834) },
7102     { PREFIX_TABLE (PREFIX_0F3835) },
7103     { Bad_Opcode },
7104     { PREFIX_TABLE (PREFIX_0F3837) },
7105     /* 38 */
7106     { PREFIX_TABLE (PREFIX_0F3838) },
7107     { PREFIX_TABLE (PREFIX_0F3839) },
7108     { PREFIX_TABLE (PREFIX_0F383A) },
7109     { PREFIX_TABLE (PREFIX_0F383B) },
7110     { PREFIX_TABLE (PREFIX_0F383C) },
7111     { PREFIX_TABLE (PREFIX_0F383D) },
7112     { PREFIX_TABLE (PREFIX_0F383E) },
7113     { PREFIX_TABLE (PREFIX_0F383F) },
7114     /* 40 */
7115     { PREFIX_TABLE (PREFIX_0F3840) },
7116     { PREFIX_TABLE (PREFIX_0F3841) },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* 48 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* 50 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* 58 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* 60 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* 68 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* 70 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* 78 */
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     /* 80 */
7187     { PREFIX_TABLE (PREFIX_0F3880) },
7188     { PREFIX_TABLE (PREFIX_0F3881) },
7189     { PREFIX_TABLE (PREFIX_0F3882) },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     /* 88 */
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* 90 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* 98 */
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     /* a0 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* a8 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     /* b0 */
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     /* b8 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     /* c0 */
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     /* c8 */
7268     { PREFIX_TABLE (PREFIX_0F38C8) },
7269     { PREFIX_TABLE (PREFIX_0F38C9) },
7270     { PREFIX_TABLE (PREFIX_0F38CA) },
7271     { PREFIX_TABLE (PREFIX_0F38CB) },
7272     { PREFIX_TABLE (PREFIX_0F38CC) },
7273     { PREFIX_TABLE (PREFIX_0F38CD) },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     /* d0 */
7277     { Bad_Opcode },
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     /* d8 */
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { PREFIX_TABLE (PREFIX_0F38DB) },
7290     { PREFIX_TABLE (PREFIX_0F38DC) },
7291     { PREFIX_TABLE (PREFIX_0F38DD) },
7292     { PREFIX_TABLE (PREFIX_0F38DE) },
7293     { PREFIX_TABLE (PREFIX_0F38DF) },
7294     /* e0 */
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     /* e8 */
7304     { Bad_Opcode },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     /* f0 */
7313     { PREFIX_TABLE (PREFIX_0F38F0) },
7314     { PREFIX_TABLE (PREFIX_0F38F1) },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { PREFIX_TABLE (PREFIX_0F38F5) },
7319     { PREFIX_TABLE (PREFIX_0F38F6) },
7320     { Bad_Opcode },
7321     /* f8 */
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330   },
7331   /* THREE_BYTE_0F3A */
7332   {
7333     /* 00 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 08 */
7343     { PREFIX_TABLE (PREFIX_0F3A08) },
7344     { PREFIX_TABLE (PREFIX_0F3A09) },
7345     { PREFIX_TABLE (PREFIX_0F3A0A) },
7346     { PREFIX_TABLE (PREFIX_0F3A0B) },
7347     { PREFIX_TABLE (PREFIX_0F3A0C) },
7348     { PREFIX_TABLE (PREFIX_0F3A0D) },
7349     { PREFIX_TABLE (PREFIX_0F3A0E) },
7350     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7351     /* 10 */
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { PREFIX_TABLE (PREFIX_0F3A14) },
7357     { PREFIX_TABLE (PREFIX_0F3A15) },
7358     { PREFIX_TABLE (PREFIX_0F3A16) },
7359     { PREFIX_TABLE (PREFIX_0F3A17) },
7360     /* 18 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 20 */
7370     { PREFIX_TABLE (PREFIX_0F3A20) },
7371     { PREFIX_TABLE (PREFIX_0F3A21) },
7372     { PREFIX_TABLE (PREFIX_0F3A22) },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 28 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 30 */
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* 38 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 40 */
7406     { PREFIX_TABLE (PREFIX_0F3A40) },
7407     { PREFIX_TABLE (PREFIX_0F3A41) },
7408     { PREFIX_TABLE (PREFIX_0F3A42) },
7409     { Bad_Opcode },
7410     { PREFIX_TABLE (PREFIX_0F3A44) },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* 48 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 50 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* 58 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* 60 */
7442     { PREFIX_TABLE (PREFIX_0F3A60) },
7443     { PREFIX_TABLE (PREFIX_0F3A61) },
7444     { PREFIX_TABLE (PREFIX_0F3A62) },
7445     { PREFIX_TABLE (PREFIX_0F3A63) },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* 68 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* 70 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     /* 78 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* 80 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     /* 88 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* 90 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* 98 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     /* a0 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* a8 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     /* b0 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* b8 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* c0 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* c8 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { PREFIX_TABLE (PREFIX_0F3ACC) },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     /* d0 */
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     /* d8 */
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { PREFIX_TABLE (PREFIX_0F3ADF) },
7585     /* e0 */
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     /* e8 */
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     /* f0 */
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     /* f8 */
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621   },
7622 };
7623
7624 static const struct dis386 xop_table[][256] = {
7625   /* XOP_08 */
7626   {
7627     /* 00 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* 08 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* 10 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* 18 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* 20 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* 28 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* 30 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* 38 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* 40 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* 48 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     /* 50 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* 58 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     /* 60 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* 68 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     /* 70 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     /* 78 */
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* 80 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7778     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7779     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7780     /* 88 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7788     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7789     /* 90 */
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7796     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7797     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7798     /* 98 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7806     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7807     /* a0 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7811     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7815     { Bad_Opcode },
7816     /* a8 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* b0 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7833     { Bad_Opcode },
7834     /* b8 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     /* c0 */
7844     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7845     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7846     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7847     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* c8 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7858     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7859     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7860     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7861     /* d0 */
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     /* d8 */
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     /* e0 */
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     /* e8 */
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7894     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7895     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7896     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7897     /* f0 */
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     /* f8 */
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915   },
7916   /* XOP_09 */
7917   {
7918     /* 00 */
7919     { Bad_Opcode },
7920     { REG_TABLE (REG_XOP_TBM_01) },
7921     { REG_TABLE (REG_XOP_TBM_02) },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 08 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* 10 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { REG_TABLE (REG_XOP_LWPCB) },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* 18 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* 20 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* 28 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* 30 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* 38 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* 40 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* 48 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* 50 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* 58 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* 60 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* 68 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* 70 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* 78 */
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     /* 80 */
8063     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8064     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8065     { "vfrczss",        { XM, EXd }, 0 },
8066     { "vfrczsd",        { XM, EXq }, 0 },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* 88 */
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* 90 */
8081     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8082     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8083     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8084     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8085     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8086     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8087     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8088     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8089     /* 98 */
8090     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8091     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8092     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8093     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* a0 */
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     /* a8 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* b0 */
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* b8 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* c0 */
8135     { Bad_Opcode },
8136     { "vphaddbw",       { XM, EXxmm }, 0 },
8137     { "vphaddbd",       { XM, EXxmm }, 0 },
8138     { "vphaddbq",       { XM, EXxmm }, 0 },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { "vphaddwd",       { XM, EXxmm }, 0 },
8142     { "vphaddwq",       { XM, EXxmm }, 0 },
8143     /* c8 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { "vphadddq",       { XM, EXxmm }, 0 },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     /* d0 */
8153     { Bad_Opcode },
8154     { "vphaddubw",      { XM, EXxmm }, 0 },
8155     { "vphaddubd",      { XM, EXxmm }, 0 },
8156     { "vphaddubq",      { XM, EXxmm }, 0 },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { "vphadduwd",      { XM, EXxmm }, 0 },
8160     { "vphadduwq",      { XM, EXxmm }, 0 },
8161     /* d8 */
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { "vphaddudq",      { XM, EXxmm }, 0 },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     /* e0 */
8171     { Bad_Opcode },
8172     { "vphsubbw",       { XM, EXxmm }, 0 },
8173     { "vphsubwd",       { XM, EXxmm }, 0 },
8174     { "vphsubdq",       { XM, EXxmm }, 0 },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     /* e8 */
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     /* f0 */
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     /* f8 */
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206   },
8207   /* XOP_0A */
8208   {
8209     /* 00 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 08 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 10 */
8228     { "bextr",  { Gv, Ev, Iq }, 0 },
8229     { Bad_Opcode },
8230     { REG_TABLE (REG_XOP_LWP) },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* 18 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* 20 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* 28 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* 30 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* 38 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* 40 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* 48 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* 50 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* 58 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* 60 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* 68 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* 70 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* 78 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* 80 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* 88 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* 90 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* 98 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* a0 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* a8 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* b0 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* b8 */
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     /* c0 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* c8 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     /* d0 */
8444     { Bad_Opcode },
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     /* d8 */
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     /* e0 */
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     /* e8 */
8471     { Bad_Opcode },
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     /* f0 */
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     /* f8 */
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497   },
8498 };
8499
8500 static const struct dis386 vex_table[][256] = {
8501   /* VEX_0F */
8502   {
8503     /* 00 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* 08 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* 10 */
8522     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8525     { MOD_TABLE (MOD_VEX_0F13) },
8526     { VEX_W_TABLE (VEX_W_0F14) },
8527     { VEX_W_TABLE (VEX_W_0F15) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8529     { MOD_TABLE (MOD_VEX_0F17) },
8530     /* 18 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* 20 */
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     /* 28 */
8549     { VEX_W_TABLE (VEX_W_0F28) },
8550     { VEX_W_TABLE (VEX_W_0F29) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8552     { MOD_TABLE (MOD_VEX_0F2B) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8557     /* 30 */
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { Bad_Opcode },
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     /* 38 */
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     /* 40 */
8576     { Bad_Opcode },
8577     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8579     { Bad_Opcode },
8580     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8584     /* 48 */
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     /* 50 */
8594     { MOD_TABLE (MOD_VEX_0F50) },
8595     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8598     { "vandpX",         { XM, Vex, EXx }, 0 },
8599     { "vandnpX",        { XM, Vex, EXx }, 0 },
8600     { "vorpX",          { XM, Vex, EXx }, 0 },
8601     { "vxorpX",         { XM, Vex, EXx }, 0 },
8602     /* 58 */
8603     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8604     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8605     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8606     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8607     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8611     /* 60 */
8612     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8616     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8617     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8620     /* 68 */
8621     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8623     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8624     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8625     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8626     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8627     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8628     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8629     /* 70 */
8630     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8631     { REG_TABLE (REG_VEX_0F71) },
8632     { REG_TABLE (REG_VEX_0F72) },
8633     { REG_TABLE (REG_VEX_0F73) },
8634     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8635     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8636     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8637     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8638     /* 78 */
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8644     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8645     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8646     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8647     /* 80 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     /* 88 */
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     /* 90 */
8666     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8667     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { Bad_Opcode },
8674     /* 98 */
8675     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8676     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     /* a0 */
8684     { Bad_Opcode },
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     /* a8 */
8693     { Bad_Opcode },
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { Bad_Opcode },
8697     { Bad_Opcode },
8698     { Bad_Opcode },
8699     { REG_TABLE (REG_VEX_0FAE) },
8700     { Bad_Opcode },
8701     /* b0 */
8702     { Bad_Opcode },
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     /* b8 */
8711     { Bad_Opcode },
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     /* c0 */
8720     { Bad_Opcode },
8721     { Bad_Opcode },
8722     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8723     { Bad_Opcode },
8724     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8726     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8727     { Bad_Opcode },
8728     /* c8 */
8729     { Bad_Opcode },
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { Bad_Opcode },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     /* d0 */
8738     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8739     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8746     /* d8 */
8747     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8748     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8755     /* e0 */
8756     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8757     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8758     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8759     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8760     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8763     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8764     /* e8 */
8765     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8766     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8767     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8768     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8769     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8770     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8771     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8772     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8773     /* f0 */
8774     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8775     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8776     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8777     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8778     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8779     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8780     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8781     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8782     /* f8 */
8783     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8784     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8785     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8786     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8787     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8788     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8789     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8790     { Bad_Opcode },
8791   },
8792   /* VEX_0F38 */
8793   {
8794     /* 00 */
8795     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8803     /* 08 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8812     /* 10 */
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8821     /* 18 */
8822     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8823     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8825     { Bad_Opcode },
8826     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8829     { Bad_Opcode },
8830     /* 20 */
8831     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8832     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* 28 */
8840     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8843     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8844     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8845     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8846     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8848     /* 30 */
8849     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8850     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8851     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8852     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8853     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8854     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8855     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8856     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8857     /* 38 */
8858     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8859     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8860     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8861     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8862     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8864     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8865     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8866     /* 40 */
8867     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8868     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8873     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8874     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8875     /* 48 */
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     /* 50 */
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     /* 58 */
8894     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     /* 60 */
8903     { Bad_Opcode },
8904     { Bad_Opcode },
8905     { Bad_Opcode },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     /* 68 */
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     /* 70 */
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     /* 78 */
8930     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { Bad_Opcode },
8938     /* 80 */
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     /* 88 */
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8953     { Bad_Opcode },
8954     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8955     { Bad_Opcode },
8956     /* 90 */
8957     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8958     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8965     /* 98 */
8966     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8967     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8970     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8971     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8974     /* a0 */
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8983     /* a8 */
8984     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8985     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8992     /* b0 */
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9001     /* b8 */
9002     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9010     /* c0 */
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { Bad_Opcode },
9018     { Bad_Opcode },
9019     /* c8 */
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     /* d0 */
9029     { Bad_Opcode },
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     /* d8 */
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9046     /* e0 */
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     /* e8 */
9056     { Bad_Opcode },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     /* f0 */
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9068     { REG_TABLE (REG_VEX_0F38F3) },
9069     { Bad_Opcode },
9070     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9073     /* f8 */
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082   },
9083   /* VEX_0F3A */
9084   {
9085     /* 00 */
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9089     { Bad_Opcode },
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9093     { Bad_Opcode },
9094     /* 08 */
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9103     /* 10 */
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9112     /* 18 */
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* 20 */
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* 28 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     { Bad_Opcode },
9138     { Bad_Opcode },
9139     /* 30 */
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* 38 */
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     /* 40 */
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9161     { Bad_Opcode },
9162     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9163     { Bad_Opcode },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9165     { Bad_Opcode },
9166     /* 48 */
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     /* 50 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* 58 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9191     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9192     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9193     /* 60 */
9194     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* 68 */
9203     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9204     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9205     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9206     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9207     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9208     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9209     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9210     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9211     /* 70 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     /* 78 */
9221     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9222     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9223     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9224     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9225     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9226     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9227     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9228     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9229     /* 80 */
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     /* 88 */
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     /* 90 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     /* 98 */
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     /* a0 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     /* a8 */
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     /* b0 */
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     /* b8 */
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     /* c0 */
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     /* c8 */
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     /* d0 */
9320     { Bad_Opcode },
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     /* d8 */
9329     { Bad_Opcode },
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9337     /* e0 */
9338     { Bad_Opcode },
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     /* e8 */
9347     { Bad_Opcode },
9348     { Bad_Opcode },
9349     { Bad_Opcode },
9350     { Bad_Opcode },
9351     { Bad_Opcode },
9352     { Bad_Opcode },
9353     { Bad_Opcode },
9354     { Bad_Opcode },
9355     /* f0 */
9356     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     /* f8 */
9365     { Bad_Opcode },
9366     { Bad_Opcode },
9367     { Bad_Opcode },
9368     { Bad_Opcode },
9369     { Bad_Opcode },
9370     { Bad_Opcode },
9371     { Bad_Opcode },
9372     { Bad_Opcode },
9373   },
9374 };
9375
9376 #define NEED_OPCODE_TABLE
9377 #include "i386-dis-evex.h"
9378 #undef NEED_OPCODE_TABLE
9379 static const struct dis386 vex_len_table[][2] = {
9380   /* VEX_LEN_0F10_P_1 */
9381   {
9382     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9383     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9384   },
9385
9386   /* VEX_LEN_0F10_P_3 */
9387   {
9388     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9389     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9390   },
9391
9392   /* VEX_LEN_0F11_P_1 */
9393   {
9394     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9395     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9396   },
9397
9398   /* VEX_LEN_0F11_P_3 */
9399   {
9400     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9401     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9402   },
9403
9404   /* VEX_LEN_0F12_P_0_M_0 */
9405   {
9406     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9407   },
9408
9409   /* VEX_LEN_0F12_P_0_M_1 */
9410   {
9411     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9412   },
9413
9414   /* VEX_LEN_0F12_P_2 */
9415   {
9416     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9417   },
9418
9419   /* VEX_LEN_0F13_M_0 */
9420   {
9421     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9422   },
9423
9424   /* VEX_LEN_0F16_P_0_M_0 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9427   },
9428
9429   /* VEX_LEN_0F16_P_0_M_1 */
9430   {
9431     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9432   },
9433
9434   /* VEX_LEN_0F16_P_2 */
9435   {
9436     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9437   },
9438
9439   /* VEX_LEN_0F17_M_0 */
9440   {
9441     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9442   },
9443
9444   /* VEX_LEN_0F2A_P_1 */
9445   {
9446     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9447     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9448   },
9449
9450   /* VEX_LEN_0F2A_P_3 */
9451   {
9452     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9453     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9454   },
9455
9456   /* VEX_LEN_0F2C_P_1 */
9457   {
9458     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9459     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9460   },
9461
9462   /* VEX_LEN_0F2C_P_3 */
9463   {
9464     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9465     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9466   },
9467
9468   /* VEX_LEN_0F2D_P_1 */
9469   {
9470     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9471     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9472   },
9473
9474   /* VEX_LEN_0F2D_P_3 */
9475   {
9476     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9477     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9478   },
9479
9480   /* VEX_LEN_0F2E_P_0 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9483     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9484   },
9485
9486   /* VEX_LEN_0F2E_P_2 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9489     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9490   },
9491
9492   /* VEX_LEN_0F2F_P_0 */
9493   {
9494     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9495     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9496   },
9497
9498   /* VEX_LEN_0F2F_P_2 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9501     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9502   },
9503
9504   /* VEX_LEN_0F41_P_0 */
9505   {
9506     { Bad_Opcode },
9507     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9508   },
9509   /* VEX_LEN_0F41_P_2 */
9510   {
9511     { Bad_Opcode },
9512     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9513   },
9514   /* VEX_LEN_0F42_P_0 */
9515   {
9516     { Bad_Opcode },
9517     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9518   },
9519   /* VEX_LEN_0F42_P_2 */
9520   {
9521     { Bad_Opcode },
9522     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9523   },
9524   /* VEX_LEN_0F44_P_0 */
9525   {
9526     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9527   },
9528   /* VEX_LEN_0F44_P_2 */
9529   {
9530     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9531   },
9532   /* VEX_LEN_0F45_P_0 */
9533   {
9534     { Bad_Opcode },
9535     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9536   },
9537   /* VEX_LEN_0F45_P_2 */
9538   {
9539     { Bad_Opcode },
9540     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9541   },
9542   /* VEX_LEN_0F46_P_0 */
9543   {
9544     { Bad_Opcode },
9545     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9546   },
9547   /* VEX_LEN_0F46_P_2 */
9548   {
9549     { Bad_Opcode },
9550     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9551   },
9552   /* VEX_LEN_0F47_P_0 */
9553   {
9554     { Bad_Opcode },
9555     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9556   },
9557   /* VEX_LEN_0F47_P_2 */
9558   {
9559     { Bad_Opcode },
9560     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9561   },
9562   /* VEX_LEN_0F4A_P_0 */
9563   {
9564     { Bad_Opcode },
9565     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9566   },
9567   /* VEX_LEN_0F4A_P_2 */
9568   {
9569     { Bad_Opcode },
9570     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9571   },
9572   /* VEX_LEN_0F4B_P_0 */
9573   {
9574     { Bad_Opcode },
9575     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9576   },
9577   /* VEX_LEN_0F4B_P_2 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9581   },
9582
9583   /* VEX_LEN_0F51_P_1 */
9584   {
9585     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9586     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9587   },
9588
9589   /* VEX_LEN_0F51_P_3 */
9590   {
9591     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9592     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9593   },
9594
9595   /* VEX_LEN_0F52_P_1 */
9596   {
9597     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9598     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9599   },
9600
9601   /* VEX_LEN_0F53_P_1 */
9602   {
9603     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9604     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9605   },
9606
9607   /* VEX_LEN_0F58_P_1 */
9608   {
9609     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9610     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9611   },
9612
9613   /* VEX_LEN_0F58_P_3 */
9614   {
9615     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9616     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9617   },
9618
9619   /* VEX_LEN_0F59_P_1 */
9620   {
9621     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9622     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9623   },
9624
9625   /* VEX_LEN_0F59_P_3 */
9626   {
9627     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9628     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9629   },
9630
9631   /* VEX_LEN_0F5A_P_1 */
9632   {
9633     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9634     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9635   },
9636
9637   /* VEX_LEN_0F5A_P_3 */
9638   {
9639     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9640     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9641   },
9642
9643   /* VEX_LEN_0F5C_P_1 */
9644   {
9645     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9646     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9647   },
9648
9649   /* VEX_LEN_0F5C_P_3 */
9650   {
9651     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9652     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9653   },
9654
9655   /* VEX_LEN_0F5D_P_1 */
9656   {
9657     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9658     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9659   },
9660
9661   /* VEX_LEN_0F5D_P_3 */
9662   {
9663     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9664     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9665   },
9666
9667   /* VEX_LEN_0F5E_P_1 */
9668   {
9669     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9670     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9671   },
9672
9673   /* VEX_LEN_0F5E_P_3 */
9674   {
9675     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9676     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9677   },
9678
9679   /* VEX_LEN_0F5F_P_1 */
9680   {
9681     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9682     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9683   },
9684
9685   /* VEX_LEN_0F5F_P_3 */
9686   {
9687     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9688     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9689   },
9690
9691   /* VEX_LEN_0F6E_P_2 */
9692   {
9693     { "vmovK",          { XMScalar, Edq }, 0 },
9694     { "vmovK",          { XMScalar, Edq }, 0 },
9695   },
9696
9697   /* VEX_LEN_0F7E_P_1 */
9698   {
9699     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9700     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9701   },
9702
9703   /* VEX_LEN_0F7E_P_2 */
9704   {
9705     { "vmovK",          { Edq, XMScalar }, 0 },
9706     { "vmovK",          { Edq, XMScalar }, 0 },
9707   },
9708
9709   /* VEX_LEN_0F90_P_0 */
9710   {
9711     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9712   },
9713
9714   /* VEX_LEN_0F90_P_2 */
9715   {
9716     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9717   },
9718
9719   /* VEX_LEN_0F91_P_0 */
9720   {
9721     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9722   },
9723
9724   /* VEX_LEN_0F91_P_2 */
9725   {
9726     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9727   },
9728
9729   /* VEX_LEN_0F92_P_0 */
9730   {
9731     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9732   },
9733
9734   /* VEX_LEN_0F92_P_2 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9737   },
9738
9739   /* VEX_LEN_0F92_P_3 */
9740   {
9741     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9742   },
9743
9744   /* VEX_LEN_0F93_P_0 */
9745   {
9746     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9747   },
9748
9749   /* VEX_LEN_0F93_P_2 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9752   },
9753
9754   /* VEX_LEN_0F93_P_3 */
9755   {
9756     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9757   },
9758
9759   /* VEX_LEN_0F98_P_0 */
9760   {
9761     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9762   },
9763
9764   /* VEX_LEN_0F98_P_2 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9767   },
9768
9769   /* VEX_LEN_0F99_P_0 */
9770   {
9771     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9772   },
9773
9774   /* VEX_LEN_0F99_P_2 */
9775   {
9776     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9777   },
9778
9779   /* VEX_LEN_0FAE_R_2_M_0 */
9780   {
9781     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9782   },
9783
9784   /* VEX_LEN_0FAE_R_3_M_0 */
9785   {
9786     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9787   },
9788
9789   /* VEX_LEN_0FC2_P_1 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9792     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9793   },
9794
9795   /* VEX_LEN_0FC2_P_3 */
9796   {
9797     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9798     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9799   },
9800
9801   /* VEX_LEN_0FC4_P_2 */
9802   {
9803     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9804   },
9805
9806   /* VEX_LEN_0FC5_P_2 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9809   },
9810
9811   /* VEX_LEN_0FD6_P_2 */
9812   {
9813     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9814     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9815   },
9816
9817   /* VEX_LEN_0FF7_P_2 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9820   },
9821
9822   /* VEX_LEN_0F3816_P_2 */
9823   {
9824     { Bad_Opcode },
9825     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9826   },
9827
9828   /* VEX_LEN_0F3819_P_2 */
9829   {
9830     { Bad_Opcode },
9831     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9832   },
9833
9834   /* VEX_LEN_0F381A_P_2_M_0 */
9835   {
9836     { Bad_Opcode },
9837     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9838   },
9839
9840   /* VEX_LEN_0F3836_P_2 */
9841   {
9842     { Bad_Opcode },
9843     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9844   },
9845
9846   /* VEX_LEN_0F3841_P_2 */
9847   {
9848     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9849   },
9850
9851   /* VEX_LEN_0F385A_P_2_M_0 */
9852   {
9853     { Bad_Opcode },
9854     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9855   },
9856
9857   /* VEX_LEN_0F38DB_P_2 */
9858   {
9859     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9860   },
9861
9862   /* VEX_LEN_0F38DC_P_2 */
9863   {
9864     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9865   },
9866
9867   /* VEX_LEN_0F38DD_P_2 */
9868   {
9869     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9870   },
9871
9872   /* VEX_LEN_0F38DE_P_2 */
9873   {
9874     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9875   },
9876
9877   /* VEX_LEN_0F38DF_P_2 */
9878   {
9879     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9880   },
9881
9882   /* VEX_LEN_0F38F2_P_0 */
9883   {
9884     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9885   },
9886
9887   /* VEX_LEN_0F38F3_R_1_P_0 */
9888   {
9889     { "blsrS",          { VexGdq, Edq }, 0 },
9890   },
9891
9892   /* VEX_LEN_0F38F3_R_2_P_0 */
9893   {
9894     { "blsmskS",        { VexGdq, Edq }, 0 },
9895   },
9896
9897   /* VEX_LEN_0F38F3_R_3_P_0 */
9898   {
9899     { "blsiS",          { VexGdq, Edq }, 0 },
9900   },
9901
9902   /* VEX_LEN_0F38F5_P_0 */
9903   {
9904     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9905   },
9906
9907   /* VEX_LEN_0F38F5_P_1 */
9908   {
9909     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9910   },
9911
9912   /* VEX_LEN_0F38F5_P_3 */
9913   {
9914     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9915   },
9916
9917   /* VEX_LEN_0F38F6_P_3 */
9918   {
9919     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9920   },
9921
9922   /* VEX_LEN_0F38F7_P_0 */
9923   {
9924     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9925   },
9926
9927   /* VEX_LEN_0F38F7_P_1 */
9928   {
9929     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9930   },
9931
9932   /* VEX_LEN_0F38F7_P_2 */
9933   {
9934     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9935   },
9936
9937   /* VEX_LEN_0F38F7_P_3 */
9938   {
9939     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9940   },
9941
9942   /* VEX_LEN_0F3A00_P_2 */
9943   {
9944     { Bad_Opcode },
9945     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9946   },
9947
9948   /* VEX_LEN_0F3A01_P_2 */
9949   {
9950     { Bad_Opcode },
9951     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9952   },
9953
9954   /* VEX_LEN_0F3A06_P_2 */
9955   {
9956     { Bad_Opcode },
9957     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9958   },
9959
9960   /* VEX_LEN_0F3A0A_P_2 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9963     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9964   },
9965
9966   /* VEX_LEN_0F3A0B_P_2 */
9967   {
9968     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9969     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9970   },
9971
9972   /* VEX_LEN_0F3A14_P_2 */
9973   {
9974     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9975   },
9976
9977   /* VEX_LEN_0F3A15_P_2 */
9978   {
9979     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9980   },
9981
9982   /* VEX_LEN_0F3A16_P_2  */
9983   {
9984     { "vpextrK",        { Edq, XM, Ib }, 0 },
9985   },
9986
9987   /* VEX_LEN_0F3A17_P_2 */
9988   {
9989     { "vextractps",     { Edqd, XM, Ib }, 0 },
9990   },
9991
9992   /* VEX_LEN_0F3A18_P_2 */
9993   {
9994     { Bad_Opcode },
9995     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9996   },
9997
9998   /* VEX_LEN_0F3A19_P_2 */
9999   {
10000     { Bad_Opcode },
10001     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10002   },
10003
10004   /* VEX_LEN_0F3A20_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F3A21_P_2 */
10010   {
10011     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10012   },
10013
10014   /* VEX_LEN_0F3A22_P_2 */
10015   {
10016     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10017   },
10018
10019   /* VEX_LEN_0F3A30_P_2 */
10020   {
10021     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10022   },
10023
10024   /* VEX_LEN_0F3A31_P_2 */
10025   {
10026     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10027   },
10028
10029   /* VEX_LEN_0F3A32_P_2 */
10030   {
10031     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10032   },
10033
10034   /* VEX_LEN_0F3A33_P_2 */
10035   {
10036     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10037   },
10038
10039   /* VEX_LEN_0F3A38_P_2 */
10040   {
10041     { Bad_Opcode },
10042     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10043   },
10044
10045   /* VEX_LEN_0F3A39_P_2 */
10046   {
10047     { Bad_Opcode },
10048     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10049   },
10050
10051   /* VEX_LEN_0F3A41_P_2 */
10052   {
10053     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10054   },
10055
10056   /* VEX_LEN_0F3A44_P_2 */
10057   {
10058     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10059   },
10060
10061   /* VEX_LEN_0F3A46_P_2 */
10062   {
10063     { Bad_Opcode },
10064     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10065   },
10066
10067   /* VEX_LEN_0F3A60_P_2 */
10068   {
10069     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10070   },
10071
10072   /* VEX_LEN_0F3A61_P_2 */
10073   {
10074     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10075   },
10076
10077   /* VEX_LEN_0F3A62_P_2 */
10078   {
10079     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10080   },
10081
10082   /* VEX_LEN_0F3A63_P_2 */
10083   {
10084     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10085   },
10086
10087   /* VEX_LEN_0F3A6A_P_2 */
10088   {
10089     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10090   },
10091
10092   /* VEX_LEN_0F3A6B_P_2 */
10093   {
10094     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10095   },
10096
10097   /* VEX_LEN_0F3A6E_P_2 */
10098   {
10099     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10100   },
10101
10102   /* VEX_LEN_0F3A6F_P_2 */
10103   {
10104     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10105   },
10106
10107   /* VEX_LEN_0F3A7A_P_2 */
10108   {
10109     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F3A7B_P_2 */
10113   {
10114     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F3A7E_P_2 */
10118   {
10119     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10120   },
10121
10122   /* VEX_LEN_0F3A7F_P_2 */
10123   {
10124     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10125   },
10126
10127   /* VEX_LEN_0F3ADF_P_2 */
10128   {
10129     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10130   },
10131
10132   /* VEX_LEN_0F3AF0_P_3 */
10133   {
10134     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10135   },
10136
10137   /* VEX_LEN_0FXOP_08_CC */
10138   {
10139      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10140   },
10141
10142   /* VEX_LEN_0FXOP_08_CD */
10143   {
10144      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10145   },
10146
10147   /* VEX_LEN_0FXOP_08_CE */
10148   {
10149      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10150   },
10151
10152   /* VEX_LEN_0FXOP_08_CF */
10153   {
10154      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10155   },
10156
10157   /* VEX_LEN_0FXOP_08_EC */
10158   {
10159      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10160   },
10161
10162   /* VEX_LEN_0FXOP_08_ED */
10163   {
10164      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10165   },
10166
10167   /* VEX_LEN_0FXOP_08_EE */
10168   {
10169      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10170   },
10171
10172   /* VEX_LEN_0FXOP_08_EF */
10173   {
10174      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10175   },
10176
10177   /* VEX_LEN_0FXOP_09_80 */
10178   {
10179     { "vfrczps",        { XM, EXxmm }, 0 },
10180     { "vfrczps",        { XM, EXymmq }, 0 },
10181   },
10182
10183   /* VEX_LEN_0FXOP_09_81 */
10184   {
10185     { "vfrczpd",        { XM, EXxmm }, 0 },
10186     { "vfrczpd",        { XM, EXymmq }, 0 },
10187   },
10188 };
10189
10190 static const struct dis386 vex_w_table[][2] = {
10191   {
10192     /* VEX_W_0F10_P_0 */
10193     { "vmovups",        { XM, EXx }, 0 },
10194   },
10195   {
10196     /* VEX_W_0F10_P_1 */
10197     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10198   },
10199   {
10200     /* VEX_W_0F10_P_2 */
10201     { "vmovupd",        { XM, EXx }, 0 },
10202   },
10203   {
10204     /* VEX_W_0F10_P_3 */
10205     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F11_P_0 */
10209     { "vmovups",        { EXxS, XM }, 0 },
10210   },
10211   {
10212     /* VEX_W_0F11_P_1 */
10213     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10214   },
10215   {
10216     /* VEX_W_0F11_P_2 */
10217     { "vmovupd",        { EXxS, XM }, 0 },
10218   },
10219   {
10220     /* VEX_W_0F11_P_3 */
10221     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10222   },
10223   {
10224     /* VEX_W_0F12_P_0_M_0 */
10225     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10226   },
10227   {
10228     /* VEX_W_0F12_P_0_M_1 */
10229     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10230   },
10231   {
10232     /* VEX_W_0F12_P_1 */
10233     { "vmovsldup",      { XM, EXx }, 0 },
10234   },
10235   {
10236     /* VEX_W_0F12_P_2 */
10237     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10238   },
10239   {
10240     /* VEX_W_0F12_P_3 */
10241     { "vmovddup",       { XM, EXymmq }, 0 },
10242   },
10243   {
10244     /* VEX_W_0F13_M_0 */
10245     { "vmovlpX",        { EXq, XM }, 0 },
10246   },
10247   {
10248     /* VEX_W_0F14 */
10249     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10250   },
10251   {
10252     /* VEX_W_0F15 */
10253     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10254   },
10255   {
10256     /* VEX_W_0F16_P_0_M_0 */
10257     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10258   },
10259   {
10260     /* VEX_W_0F16_P_0_M_1 */
10261     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10262   },
10263   {
10264     /* VEX_W_0F16_P_1 */
10265     { "vmovshdup",      { XM, EXx }, 0 },
10266   },
10267   {
10268     /* VEX_W_0F16_P_2 */
10269     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10270   },
10271   {
10272     /* VEX_W_0F17_M_0 */
10273     { "vmovhpX",        { EXq, XM }, 0 },
10274   },
10275   {
10276     /* VEX_W_0F28 */
10277     { "vmovapX",        { XM, EXx }, 0 },
10278   },
10279   {
10280     /* VEX_W_0F29 */
10281     { "vmovapX",        { EXxS, XM }, 0 },
10282   },
10283   {
10284     /* VEX_W_0F2B_M_0 */
10285     { "vmovntpX",       { Mx, XM }, 0 },
10286   },
10287   {
10288     /* VEX_W_0F2E_P_0 */
10289     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10290   },
10291   {
10292     /* VEX_W_0F2E_P_2 */
10293     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10294   },
10295   {
10296     /* VEX_W_0F2F_P_0 */
10297     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10298   },
10299   {
10300     /* VEX_W_0F2F_P_2 */
10301     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10302   },
10303   {
10304     /* VEX_W_0F41_P_0_LEN_1 */
10305     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10306     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10307   },
10308   {
10309     /* VEX_W_0F41_P_2_LEN_1 */
10310     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10311     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10312   },
10313   {
10314     /* VEX_W_0F42_P_0_LEN_1 */
10315     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10316     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10317   },
10318   {
10319     /* VEX_W_0F42_P_2_LEN_1 */
10320     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10321     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10322   },
10323   {
10324     /* VEX_W_0F44_P_0_LEN_0 */
10325     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10326     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10327   },
10328   {
10329     /* VEX_W_0F44_P_2_LEN_0 */
10330     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10331     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10332   },
10333   {
10334     /* VEX_W_0F45_P_0_LEN_1 */
10335     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10336     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10337   },
10338   {
10339     /* VEX_W_0F45_P_2_LEN_1 */
10340     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10341     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10342   },
10343   {
10344     /* VEX_W_0F46_P_0_LEN_1 */
10345     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10346     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10347   },
10348   {
10349     /* VEX_W_0F46_P_2_LEN_1 */
10350     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10351     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10352   },
10353   {
10354     /* VEX_W_0F47_P_0_LEN_1 */
10355     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10356     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10357   },
10358   {
10359     /* VEX_W_0F47_P_2_LEN_1 */
10360     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10361     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10362   },
10363   {
10364     /* VEX_W_0F4A_P_0_LEN_1 */
10365     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10366     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10367   },
10368   {
10369     /* VEX_W_0F4A_P_2_LEN_1 */
10370     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10371     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10372   },
10373   {
10374     /* VEX_W_0F4B_P_0_LEN_1 */
10375     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10376     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10377   },
10378   {
10379     /* VEX_W_0F4B_P_2_LEN_1 */
10380     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10381   },
10382   {
10383     /* VEX_W_0F50_M_0 */
10384     { "vmovmskpX",      { Gdq, XS }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F51_P_0 */
10388     { "vsqrtps",        { XM, EXx }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F51_P_1 */
10392     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F51_P_2  */
10396     { "vsqrtpd",        { XM, EXx }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F51_P_3 */
10400     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F52_P_0 */
10404     { "vrsqrtps",       { XM, EXx }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F52_P_1 */
10408     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F53_P_0  */
10412     { "vrcpps",         { XM, EXx }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F53_P_1  */
10416     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F58_P_0  */
10420     { "vaddps",         { XM, Vex, EXx }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F58_P_1  */
10424     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F58_P_2  */
10428     { "vaddpd",         { XM, Vex, EXx }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F58_P_3  */
10432     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F59_P_0  */
10436     { "vmulps",         { XM, Vex, EXx }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F59_P_1  */
10440     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F59_P_2  */
10444     { "vmulpd",         { XM, Vex, EXx }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F59_P_3  */
10448     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F5A_P_0  */
10452     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F5A_P_1  */
10456     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F5A_P_3  */
10460     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F5B_P_0  */
10464     { "vcvtdq2ps",      { XM, EXx }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F5B_P_1  */
10468     { "vcvttps2dq",     { XM, EXx }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F5B_P_2  */
10472     { "vcvtps2dq",      { XM, EXx }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F5C_P_0  */
10476     { "vsubps",         { XM, Vex, EXx }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F5C_P_1  */
10480     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F5C_P_2  */
10484     { "vsubpd",         { XM, Vex, EXx }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F5C_P_3  */
10488     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F5D_P_0  */
10492     { "vminps",         { XM, Vex, EXx }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F5D_P_1  */
10496     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F5D_P_2  */
10500     { "vminpd",         { XM, Vex, EXx }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F5D_P_3  */
10504     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F5E_P_0  */
10508     { "vdivps",         { XM, Vex, EXx }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F5E_P_1  */
10512     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F5E_P_2  */
10516     { "vdivpd",         { XM, Vex, EXx }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F5E_P_3  */
10520     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F5F_P_0  */
10524     { "vmaxps",         { XM, Vex, EXx }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F5F_P_1  */
10528     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F5F_P_2  */
10532     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F5F_P_3  */
10536     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F60_P_2  */
10540     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F61_P_2  */
10544     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F62_P_2  */
10548     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F63_P_2  */
10552     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F64_P_2  */
10556     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F65_P_2  */
10560     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F66_P_2  */
10564     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F67_P_2  */
10568     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F68_P_2  */
10572     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F69_P_2  */
10576     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F6A_P_2  */
10580     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F6B_P_2  */
10584     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F6C_P_2  */
10588     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F6D_P_2  */
10592     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F6F_P_1  */
10596     { "vmovdqu",        { XM, EXx }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F6F_P_2  */
10600     { "vmovdqa",        { XM, EXx }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F70_P_1 */
10604     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F70_P_2 */
10608     { "vpshufd",        { XM, EXx, Ib }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F70_P_3 */
10612     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F71_R_2_P_2  */
10616     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F71_R_4_P_2  */
10620     { "vpsraw",         { Vex, XS, Ib }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F71_R_6_P_2  */
10624     { "vpsllw",         { Vex, XS, Ib }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F72_R_2_P_2  */
10628     { "vpsrld",         { Vex, XS, Ib }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F72_R_4_P_2  */
10632     { "vpsrad",         { Vex, XS, Ib }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F72_R_6_P_2  */
10636     { "vpslld",         { Vex, XS, Ib }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F73_R_2_P_2  */
10640     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F73_R_3_P_2  */
10644     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F73_R_6_P_2  */
10648     { "vpsllq",         { Vex, XS, Ib }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F73_R_7_P_2  */
10652     { "vpslldq",        { Vex, XS, Ib }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F74_P_2 */
10656     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F75_P_2 */
10660     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F76_P_2 */
10664     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F77_P_0 */
10668     { "",               { VZERO }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F7C_P_2 */
10672     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F7C_P_3 */
10676     { "vhaddps",        { XM, Vex, EXx }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F7D_P_2 */
10680     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F7D_P_3 */
10684     { "vhsubps",        { XM, Vex, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F7E_P_1 */
10688     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F7F_P_1 */
10692     { "vmovdqu",        { EXxS, XM }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F7F_P_2 */
10696     { "vmovdqa",        { EXxS, XM }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F90_P_0_LEN_0 */
10700     { "kmovw",          { MaskG, MaskE }, 0 },
10701     { "kmovq",          { MaskG, MaskE }, 0 },
10702   },
10703   {
10704     /* VEX_W_0F90_P_2_LEN_0 */
10705     { "kmovb",          { MaskG, MaskBDE }, 0 },
10706     { "kmovd",          { MaskG, MaskBDE }, 0 },
10707   },
10708   {
10709     /* VEX_W_0F91_P_0_LEN_0 */
10710     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10711     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10712   },
10713   {
10714     /* VEX_W_0F91_P_2_LEN_0 */
10715     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10716     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10717   },
10718   {
10719     /* VEX_W_0F92_P_0_LEN_0 */
10720     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10721   },
10722   {
10723     /* VEX_W_0F92_P_2_LEN_0 */
10724     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10725   },
10726   {
10727     /* VEX_W_0F92_P_3_LEN_0 */
10728     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10729     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10730   },
10731   {
10732     /* VEX_W_0F93_P_0_LEN_0 */
10733     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10734   },
10735   {
10736     /* VEX_W_0F93_P_2_LEN_0 */
10737     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10738   },
10739   {
10740     /* VEX_W_0F93_P_3_LEN_0 */
10741     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10742     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10743   },
10744   {
10745     /* VEX_W_0F98_P_0_LEN_0 */
10746     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10747     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10748   },
10749   {
10750     /* VEX_W_0F98_P_2_LEN_0 */
10751     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10752     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10753   },
10754   {
10755     /* VEX_W_0F99_P_0_LEN_0 */
10756     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10757     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10758   },
10759   {
10760     /* VEX_W_0F99_P_2_LEN_0 */
10761     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10762     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10763   },
10764   {
10765     /* VEX_W_0FAE_R_2_M_0 */
10766     { "vldmxcsr",       { Md }, 0 },
10767   },
10768   {
10769     /* VEX_W_0FAE_R_3_M_0 */
10770     { "vstmxcsr",       { Md }, 0 },
10771   },
10772   {
10773     /* VEX_W_0FC2_P_0 */
10774     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10775   },
10776   {
10777     /* VEX_W_0FC2_P_1 */
10778     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10779   },
10780   {
10781     /* VEX_W_0FC2_P_2 */
10782     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10783   },
10784   {
10785     /* VEX_W_0FC2_P_3 */
10786     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10787   },
10788   {
10789     /* VEX_W_0FC4_P_2 */
10790     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10791   },
10792   {
10793     /* VEX_W_0FC5_P_2 */
10794     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10795   },
10796   {
10797     /* VEX_W_0FD0_P_2 */
10798     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10799   },
10800   {
10801     /* VEX_W_0FD0_P_3 */
10802     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10803   },
10804   {
10805     /* VEX_W_0FD1_P_2 */
10806     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10807   },
10808   {
10809     /* VEX_W_0FD2_P_2 */
10810     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10811   },
10812   {
10813     /* VEX_W_0FD3_P_2 */
10814     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10815   },
10816   {
10817     /* VEX_W_0FD4_P_2 */
10818     { "vpaddq",         { XM, Vex, EXx }, 0 },
10819   },
10820   {
10821     /* VEX_W_0FD5_P_2 */
10822     { "vpmullw",        { XM, Vex, EXx }, 0 },
10823   },
10824   {
10825     /* VEX_W_0FD6_P_2 */
10826     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10827   },
10828   {
10829     /* VEX_W_0FD7_P_2_M_1 */
10830     { "vpmovmskb",      { Gdq, XS }, 0 },
10831   },
10832   {
10833     /* VEX_W_0FD8_P_2 */
10834     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10835   },
10836   {
10837     /* VEX_W_0FD9_P_2 */
10838     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10839   },
10840   {
10841     /* VEX_W_0FDA_P_2 */
10842     { "vpminub",        { XM, Vex, EXx }, 0 },
10843   },
10844   {
10845     /* VEX_W_0FDB_P_2 */
10846     { "vpand",          { XM, Vex, EXx }, 0 },
10847   },
10848   {
10849     /* VEX_W_0FDC_P_2 */
10850     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10851   },
10852   {
10853     /* VEX_W_0FDD_P_2 */
10854     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10855   },
10856   {
10857     /* VEX_W_0FDE_P_2 */
10858     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10859   },
10860   {
10861     /* VEX_W_0FDF_P_2 */
10862     { "vpandn",         { XM, Vex, EXx }, 0 },
10863   },
10864   {
10865     /* VEX_W_0FE0_P_2  */
10866     { "vpavgb",         { XM, Vex, EXx }, 0 },
10867   },
10868   {
10869     /* VEX_W_0FE1_P_2  */
10870     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10871   },
10872   {
10873     /* VEX_W_0FE2_P_2  */
10874     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10875   },
10876   {
10877     /* VEX_W_0FE3_P_2  */
10878     { "vpavgw",         { XM, Vex, EXx }, 0 },
10879   },
10880   {
10881     /* VEX_W_0FE4_P_2  */
10882     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10883   },
10884   {
10885     /* VEX_W_0FE5_P_2  */
10886     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FE6_P_1  */
10890     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FE6_P_2  */
10894     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FE6_P_3  */
10898     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FE7_P_2_M_0 */
10902     { "vmovntdq",       { Mx, XM }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FE8_P_2  */
10906     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FE9_P_2  */
10910     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FEA_P_2  */
10914     { "vpminsw",        { XM, Vex, EXx }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FEB_P_2  */
10918     { "vpor",           { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FEC_P_2  */
10922     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FED_P_2  */
10926     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FEE_P_2  */
10930     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FEF_P_2  */
10934     { "vpxor",          { XM, Vex, EXx }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FF0_P_3_M_0 */
10938     { "vlddqu",         { XM, M }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FF1_P_2 */
10942     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FF2_P_2 */
10946     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FF3_P_2 */
10950     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FF4_P_2 */
10954     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FF5_P_2 */
10958     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FF6_P_2 */
10962     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FF7_P_2 */
10966     { "vmaskmovdqu",    { XM, XS }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FF8_P_2 */
10970     { "vpsubb",         { XM, Vex, EXx }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FF9_P_2 */
10974     { "vpsubw",         { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FFA_P_2 */
10978     { "vpsubd",         { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FFB_P_2 */
10982     { "vpsubq",         { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FFC_P_2 */
10986     { "vpaddb",         { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FFD_P_2 */
10990     { "vpaddw",         { XM, Vex, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FFE_P_2 */
10994     { "vpaddd",         { XM, Vex, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0F3800_P_2  */
10998     { "vpshufb",        { XM, Vex, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0F3801_P_2  */
11002     { "vphaddw",        { XM, Vex, EXx }, 0 },
11003   },
11004   {
11005     /* VEX_W_0F3802_P_2  */
11006     { "vphaddd",        { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0F3803_P_2  */
11010     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11011   },
11012   {
11013     /* VEX_W_0F3804_P_2  */
11014     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0F3805_P_2  */
11018     { "vphsubw",        { XM, Vex, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0F3806_P_2  */
11022     { "vphsubd",        { XM, Vex, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0F3807_P_2  */
11026     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0F3808_P_2  */
11030     { "vpsignb",        { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0F3809_P_2  */
11034     { "vpsignw",        { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0F380A_P_2  */
11038     { "vpsignd",        { XM, Vex, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0F380B_P_2  */
11042     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0F380C_P_2  */
11046     { "vpermilps",      { XM, Vex, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0F380D_P_2  */
11050     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0F380E_P_2  */
11054     { "vtestps",        { XM, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0F380F_P_2  */
11058     { "vtestpd",        { XM, EXx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0F3816_P_2  */
11062     { "vpermps",        { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0F3817_P_2 */
11066     { "vptest",         { XM, EXx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0F3818_P_2 */
11070     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11071   },
11072   {
11073     /* VEX_W_0F3819_P_2 */
11074     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11075   },
11076   {
11077     /* VEX_W_0F381A_P_2_M_0 */
11078     { "vbroadcastf128", { XM, Mxmm }, 0 },
11079   },
11080   {
11081     /* VEX_W_0F381C_P_2 */
11082     { "vpabsb",         { XM, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0F381D_P_2 */
11086     { "vpabsw",         { XM, EXx }, 0 },
11087   },
11088   {
11089     /* VEX_W_0F381E_P_2 */
11090     { "vpabsd",         { XM, EXx }, 0 },
11091   },
11092   {
11093     /* VEX_W_0F3820_P_2 */
11094     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11095   },
11096   {
11097     /* VEX_W_0F3821_P_2 */
11098     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11099   },
11100   {
11101     /* VEX_W_0F3822_P_2 */
11102     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11103   },
11104   {
11105     /* VEX_W_0F3823_P_2 */
11106     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11107   },
11108   {
11109     /* VEX_W_0F3824_P_2 */
11110     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11111   },
11112   {
11113     /* VEX_W_0F3825_P_2 */
11114     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F3828_P_2 */
11118     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F3829_P_2 */
11122     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F382A_P_2_M_0 */
11126     { "vmovntdqa",      { XM, Mx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F382B_P_2 */
11130     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F382C_P_2_M_0 */
11134     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F382D_P_2_M_0 */
11138     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F382E_P_2_M_0 */
11142     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F382F_P_2_M_0 */
11146     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3830_P_2 */
11150     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3831_P_2 */
11154     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3832_P_2 */
11158     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3833_P_2 */
11162     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F3834_P_2 */
11166     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3835_P_2 */
11170     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3836_P_2  */
11174     { "vpermd",         { XM, Vex, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F3837_P_2 */
11178     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F3838_P_2 */
11182     { "vpminsb",        { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F3839_P_2 */
11186     { "vpminsd",        { XM, Vex, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F383A_P_2 */
11190     { "vpminuw",        { XM, Vex, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F383B_P_2 */
11194     { "vpminud",        { XM, Vex, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F383C_P_2 */
11198     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F383D_P_2 */
11202     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F383E_P_2 */
11206     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F383F_P_2 */
11210     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3840_P_2 */
11214     { "vpmulld",        { XM, Vex, EXx }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3841_P_2 */
11218     { "vphminposuw",    { XM, EXx }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3846_P_2 */
11222     { "vpsravd",        { XM, Vex, EXx }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3858_P_2 */
11226     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3859_P_2 */
11230     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F385A_P_2_M_0 */
11234     { "vbroadcasti128", { XM, Mxmm }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3878_P_2 */
11238     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3879_P_2 */
11242     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F38DB_P_2 */
11246     { "vaesimc",        { XM, EXx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F38DC_P_2 */
11250     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F38DD_P_2 */
11254     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F38DE_P_2 */
11258     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F38DF_P_2 */
11262     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F3A00_P_2 */
11266     { Bad_Opcode },
11267     { "vpermq",         { XM, EXx, Ib }, 0 },
11268   },
11269   {
11270     /* VEX_W_0F3A01_P_2 */
11271     { Bad_Opcode },
11272     { "vpermpd",        { XM, EXx, Ib }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3A02_P_2 */
11276     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3A04_P_2 */
11280     { "vpermilps",      { XM, EXx, Ib }, 0 },
11281   },
11282   {
11283     /* VEX_W_0F3A05_P_2 */
11284     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11285   },
11286   {
11287     /* VEX_W_0F3A06_P_2 */
11288     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11289   },
11290   {
11291     /* VEX_W_0F3A08_P_2 */
11292     { "vroundps",       { XM, EXx, Ib }, 0 },
11293   },
11294   {
11295     /* VEX_W_0F3A09_P_2 */
11296     { "vroundpd",       { XM, EXx, Ib }, 0 },
11297   },
11298   {
11299     /* VEX_W_0F3A0A_P_2 */
11300     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3A0B_P_2 */
11304     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3A0C_P_2 */
11308     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3A0D_P_2 */
11312     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F3A0E_P_2 */
11316     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3A0F_P_2 */
11320     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F3A14_P_2 */
11324     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F3A15_P_2 */
11328     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11329   },
11330   {
11331     /* VEX_W_0F3A18_P_2 */
11332     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11333   },
11334   {
11335     /* VEX_W_0F3A19_P_2 */
11336     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11337   },
11338   {
11339     /* VEX_W_0F3A20_P_2 */
11340     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11341   },
11342   {
11343     /* VEX_W_0F3A21_P_2 */
11344     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11345   },
11346   {
11347     /* VEX_W_0F3A30_P_2_LEN_0 */
11348     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11349     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11350   },
11351   {
11352     /* VEX_W_0F3A31_P_2_LEN_0 */
11353     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11354     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11355   },
11356   {
11357     /* VEX_W_0F3A32_P_2_LEN_0 */
11358     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11359     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11360   },
11361   {
11362     /* VEX_W_0F3A33_P_2_LEN_0 */
11363     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11364     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11365   },
11366   {
11367     /* VEX_W_0F3A38_P_2 */
11368     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11369   },
11370   {
11371     /* VEX_W_0F3A39_P_2 */
11372     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11373   },
11374   {
11375     /* VEX_W_0F3A40_P_2 */
11376     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11377   },
11378   {
11379     /* VEX_W_0F3A41_P_2 */
11380     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3A42_P_2 */
11384     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3A44_P_2 */
11388     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3A46_P_2 */
11392     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3A48_P_2 */
11396     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11397     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11398   },
11399   {
11400     /* VEX_W_0F3A49_P_2 */
11401     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11402     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11403   },
11404   {
11405     /* VEX_W_0F3A4A_P_2 */
11406     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11407   },
11408   {
11409     /* VEX_W_0F3A4B_P_2 */
11410     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11411   },
11412   {
11413     /* VEX_W_0F3A4C_P_2 */
11414     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11415   },
11416   {
11417     /* VEX_W_0F3A62_P_2 */
11418     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11419   },
11420   {
11421     /* VEX_W_0F3A63_P_2 */
11422     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11423   },
11424   {
11425     /* VEX_W_0F3ADF_P_2 */
11426     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11427   },
11428 #define NEED_VEX_W_TABLE
11429 #include "i386-dis-evex.h"
11430 #undef NEED_VEX_W_TABLE
11431 };
11432
11433 static const struct dis386 mod_table[][2] = {
11434   {
11435     /* MOD_8D */
11436     { "leaS",           { Gv, M }, 0 },
11437   },
11438   {
11439     /* MOD_C6_REG_7 */
11440     { Bad_Opcode },
11441     { RM_TABLE (RM_C6_REG_7) },
11442   },
11443   {
11444     /* MOD_C7_REG_7 */
11445     { Bad_Opcode },
11446     { RM_TABLE (RM_C7_REG_7) },
11447   },
11448   {
11449     /* MOD_FF_REG_3 */
11450     { "Jcall^", { indirEp }, 0 },
11451   },
11452   {
11453     /* MOD_FF_REG_5 */
11454     { "Jjmp^", { indirEp }, 0 },
11455   },
11456   {
11457     /* MOD_0F01_REG_0 */
11458     { X86_64_TABLE (X86_64_0F01_REG_0) },
11459     { RM_TABLE (RM_0F01_REG_0) },
11460   },
11461   {
11462     /* MOD_0F01_REG_1 */
11463     { X86_64_TABLE (X86_64_0F01_REG_1) },
11464     { RM_TABLE (RM_0F01_REG_1) },
11465   },
11466   {
11467     /* MOD_0F01_REG_2 */
11468     { X86_64_TABLE (X86_64_0F01_REG_2) },
11469     { RM_TABLE (RM_0F01_REG_2) },
11470   },
11471   {
11472     /* MOD_0F01_REG_3 */
11473     { X86_64_TABLE (X86_64_0F01_REG_3) },
11474     { RM_TABLE (RM_0F01_REG_3) },
11475   },
11476   {
11477     /* MOD_0F01_REG_5 */
11478     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11479     { RM_TABLE (RM_0F01_REG_5) },
11480   },
11481   {
11482     /* MOD_0F01_REG_7 */
11483     { "invlpg",         { Mb }, 0 },
11484     { RM_TABLE (RM_0F01_REG_7) },
11485   },
11486   {
11487     /* MOD_0F12_PREFIX_0 */
11488     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11489     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11490   },
11491   {
11492     /* MOD_0F13 */
11493     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11494   },
11495   {
11496     /* MOD_0F16_PREFIX_0 */
11497     { "movhps",         { XM, EXq }, 0 },
11498     { "movlhps",        { XM, EXq }, 0 },
11499   },
11500   {
11501     /* MOD_0F17 */
11502     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11503   },
11504   {
11505     /* MOD_0F18_REG_0 */
11506     { "prefetchnta",    { Mb }, 0 },
11507   },
11508   {
11509     /* MOD_0F18_REG_1 */
11510     { "prefetcht0",     { Mb }, 0 },
11511   },
11512   {
11513     /* MOD_0F18_REG_2 */
11514     { "prefetcht1",     { Mb }, 0 },
11515   },
11516   {
11517     /* MOD_0F18_REG_3 */
11518     { "prefetcht2",     { Mb }, 0 },
11519   },
11520   {
11521     /* MOD_0F18_REG_4 */
11522     { "nop/reserved",   { Mb }, 0 },
11523   },
11524   {
11525     /* MOD_0F18_REG_5 */
11526     { "nop/reserved",   { Mb }, 0 },
11527   },
11528   {
11529     /* MOD_0F18_REG_6 */
11530     { "nop/reserved",   { Mb }, 0 },
11531   },
11532   {
11533     /* MOD_0F18_REG_7 */
11534     { "nop/reserved",   { Mb }, 0 },
11535   },
11536   {
11537     /* MOD_0F1A_PREFIX_0 */
11538     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11539     { "nopQ",           { Ev }, 0 },
11540   },
11541   {
11542     /* MOD_0F1B_PREFIX_0 */
11543     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11544     { "nopQ",           { Ev }, 0 },
11545   },
11546   {
11547     /* MOD_0F1B_PREFIX_1 */
11548     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11549     { "nopQ",           { Ev }, 0 },
11550   },
11551   {
11552     /* MOD_0F1E_PREFIX_1 */
11553     { "nopQ",           { Ev }, 0 },
11554     { REG_TABLE (REG_0F1E_MOD_3) },
11555   },
11556   {
11557     /* MOD_0F24 */
11558     { Bad_Opcode },
11559     { "movL",           { Rd, Td }, 0 },
11560   },
11561   {
11562     /* MOD_0F26 */
11563     { Bad_Opcode },
11564     { "movL",           { Td, Rd }, 0 },
11565   },
11566   {
11567     /* MOD_0F2B_PREFIX_0 */
11568     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11569   },
11570   {
11571     /* MOD_0F2B_PREFIX_1 */
11572     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11573   },
11574   {
11575     /* MOD_0F2B_PREFIX_2 */
11576     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11577   },
11578   {
11579     /* MOD_0F2B_PREFIX_3 */
11580     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11581   },
11582   {
11583     /* MOD_0F51 */
11584     { Bad_Opcode },
11585     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11586   },
11587   {
11588     /* MOD_0F71_REG_2 */
11589     { Bad_Opcode },
11590     { "psrlw",          { MS, Ib }, 0 },
11591   },
11592   {
11593     /* MOD_0F71_REG_4 */
11594     { Bad_Opcode },
11595     { "psraw",          { MS, Ib }, 0 },
11596   },
11597   {
11598     /* MOD_0F71_REG_6 */
11599     { Bad_Opcode },
11600     { "psllw",          { MS, Ib }, 0 },
11601   },
11602   {
11603     /* MOD_0F72_REG_2 */
11604     { Bad_Opcode },
11605     { "psrld",          { MS, Ib }, 0 },
11606   },
11607   {
11608     /* MOD_0F72_REG_4 */
11609     { Bad_Opcode },
11610     { "psrad",          { MS, Ib }, 0 },
11611   },
11612   {
11613     /* MOD_0F72_REG_6 */
11614     { Bad_Opcode },
11615     { "pslld",          { MS, Ib }, 0 },
11616   },
11617   {
11618     /* MOD_0F73_REG_2 */
11619     { Bad_Opcode },
11620     { "psrlq",          { MS, Ib }, 0 },
11621   },
11622   {
11623     /* MOD_0F73_REG_3 */
11624     { Bad_Opcode },
11625     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11626   },
11627   {
11628     /* MOD_0F73_REG_6 */
11629     { Bad_Opcode },
11630     { "psllq",          { MS, Ib }, 0 },
11631   },
11632   {
11633     /* MOD_0F73_REG_7 */
11634     { Bad_Opcode },
11635     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11636   },
11637   {
11638     /* MOD_0FAE_REG_0 */
11639     { "fxsave",         { FXSAVE }, 0 },
11640     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11641   },
11642   {
11643     /* MOD_0FAE_REG_1 */
11644     { "fxrstor",        { FXSAVE }, 0 },
11645     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11646   },
11647   {
11648     /* MOD_0FAE_REG_2 */
11649     { "ldmxcsr",        { Md }, 0 },
11650     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11651   },
11652   {
11653     /* MOD_0FAE_REG_3 */
11654     { "stmxcsr",        { Md }, 0 },
11655     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11656   },
11657   {
11658     /* MOD_0FAE_REG_4 */
11659     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11660     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11661   },
11662   {
11663     /* MOD_0FAE_REG_5 */
11664     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11665     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11666   },
11667   {
11668     /* MOD_0FAE_REG_6 */
11669     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11670     { RM_TABLE (RM_0FAE_REG_6) },
11671   },
11672   {
11673     /* MOD_0FAE_REG_7 */
11674     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11675     { RM_TABLE (RM_0FAE_REG_7) },
11676   },
11677   {
11678     /* MOD_0FB2 */
11679     { "lssS",           { Gv, Mp }, 0 },
11680   },
11681   {
11682     /* MOD_0FB4 */
11683     { "lfsS",           { Gv, Mp }, 0 },
11684   },
11685   {
11686     /* MOD_0FB5 */
11687     { "lgsS",           { Gv, Mp }, 0 },
11688   },
11689   {
11690     /* MOD_0FC3 */
11691     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11692   },
11693   {
11694     /* MOD_0FC7_REG_3 */
11695     { "xrstors",        { FXSAVE }, 0 },
11696   },
11697   {
11698     /* MOD_0FC7_REG_4 */
11699     { "xsavec",         { FXSAVE }, 0 },
11700   },
11701   {
11702     /* MOD_0FC7_REG_5 */
11703     { "xsaves",         { FXSAVE }, 0 },
11704   },
11705   {
11706     /* MOD_0FC7_REG_6 */
11707     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11708     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11709   },
11710   {
11711     /* MOD_0FC7_REG_7 */
11712     { "vmptrst",        { Mq }, 0 },
11713     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11714   },
11715   {
11716     /* MOD_0FD7 */
11717     { Bad_Opcode },
11718     { "pmovmskb",       { Gdq, MS }, 0 },
11719   },
11720   {
11721     /* MOD_0FE7_PREFIX_2 */
11722     { "movntdq",        { Mx, XM }, 0 },
11723   },
11724   {
11725     /* MOD_0FF0_PREFIX_3 */
11726     { "lddqu",          { XM, M }, 0 },
11727   },
11728   {
11729     /* MOD_0F382A_PREFIX_2 */
11730     { "movntdqa",       { XM, Mx }, 0 },
11731   },
11732   {
11733     /* MOD_0F38F5_PREFIX_2 */
11734     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11735   },
11736   {
11737     /* MOD_0F38F6_PREFIX_0 */
11738     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11739   },
11740   {
11741     /* MOD_62_32BIT */
11742     { "bound{S|}",      { Gv, Ma }, 0 },
11743     { EVEX_TABLE (EVEX_0F) },
11744   },
11745   {
11746     /* MOD_C4_32BIT */
11747     { "lesS",           { Gv, Mp }, 0 },
11748     { VEX_C4_TABLE (VEX_0F) },
11749   },
11750   {
11751     /* MOD_C5_32BIT */
11752     { "ldsS",           { Gv, Mp }, 0 },
11753     { VEX_C5_TABLE (VEX_0F) },
11754   },
11755   {
11756     /* MOD_VEX_0F12_PREFIX_0 */
11757     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11758     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11759   },
11760   {
11761     /* MOD_VEX_0F13 */
11762     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11763   },
11764   {
11765     /* MOD_VEX_0F16_PREFIX_0 */
11766     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11767     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11768   },
11769   {
11770     /* MOD_VEX_0F17 */
11771     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11772   },
11773   {
11774     /* MOD_VEX_0F2B */
11775     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11776   },
11777   {
11778     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11779     { Bad_Opcode },
11780     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11781   },
11782   {
11783     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11784     { Bad_Opcode },
11785     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11786   },
11787   {
11788     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11789     { Bad_Opcode },
11790     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11791   },
11792   {
11793     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11794     { Bad_Opcode },
11795     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11796   },
11797   {
11798     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11799     { Bad_Opcode },
11800     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11801   },
11802   {
11803     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11804     { Bad_Opcode },
11805     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11806   },
11807   {
11808     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11809     { Bad_Opcode },
11810     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11811   },
11812   {
11813     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11814     { Bad_Opcode },
11815     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11816   },
11817   {
11818     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11819     { Bad_Opcode },
11820     { "knotw",          { MaskG, MaskR }, 0 },
11821   },
11822   {
11823     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11824     { Bad_Opcode },
11825     { "knotq",          { MaskG, MaskR }, 0 },
11826   },
11827   {
11828     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11829     { Bad_Opcode },
11830     { "knotb",          { MaskG, MaskR }, 0 },
11831   },
11832   {
11833     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11834     { Bad_Opcode },
11835     { "knotd",          { MaskG, MaskR }, 0 },
11836   },
11837   {
11838     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11839     { Bad_Opcode },
11840     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11841   },
11842   {
11843     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11844     { Bad_Opcode },
11845     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11846   },
11847   {
11848     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11849     { Bad_Opcode },
11850     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11851   },
11852   {
11853     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11854     { Bad_Opcode },
11855     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11856   },
11857  {
11858     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11859     { Bad_Opcode },
11860     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11861   },
11862   {
11863     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11864     { Bad_Opcode },
11865     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11866   },
11867   {
11868     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11869     { Bad_Opcode },
11870     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11871   },
11872   {
11873     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11874     { Bad_Opcode },
11875     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11876   },
11877   {
11878     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11879     { Bad_Opcode },
11880     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11881   },
11882   {
11883     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11884     { Bad_Opcode },
11885     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11886   },
11887   {
11888     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11889     { Bad_Opcode },
11890     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11891   },
11892   {
11893     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11894     { Bad_Opcode },
11895     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11896   },
11897   {
11898     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11899     { Bad_Opcode },
11900     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11901   },
11902   {
11903     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11904     { Bad_Opcode },
11905     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11906   },
11907   {
11908     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11909     { Bad_Opcode },
11910     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11911   },
11912   {
11913     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11914     { Bad_Opcode },
11915     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11916   },
11917   {
11918     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11919     { Bad_Opcode },
11920     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11921   },
11922   {
11923     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11924     { Bad_Opcode },
11925     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11926   },
11927   {
11928     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11929     { Bad_Opcode },
11930     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11931   },
11932   {
11933     /* MOD_VEX_0F50 */
11934     { Bad_Opcode },
11935     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11936   },
11937   {
11938     /* MOD_VEX_0F71_REG_2 */
11939     { Bad_Opcode },
11940     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11941   },
11942   {
11943     /* MOD_VEX_0F71_REG_4 */
11944     { Bad_Opcode },
11945     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11946   },
11947   {
11948     /* MOD_VEX_0F71_REG_6 */
11949     { Bad_Opcode },
11950     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11951   },
11952   {
11953     /* MOD_VEX_0F72_REG_2 */
11954     { Bad_Opcode },
11955     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11956   },
11957   {
11958     /* MOD_VEX_0F72_REG_4 */
11959     { Bad_Opcode },
11960     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11961   },
11962   {
11963     /* MOD_VEX_0F72_REG_6 */
11964     { Bad_Opcode },
11965     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11966   },
11967   {
11968     /* MOD_VEX_0F73_REG_2 */
11969     { Bad_Opcode },
11970     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11971   },
11972   {
11973     /* MOD_VEX_0F73_REG_3 */
11974     { Bad_Opcode },
11975     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11976   },
11977   {
11978     /* MOD_VEX_0F73_REG_6 */
11979     { Bad_Opcode },
11980     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11981   },
11982   {
11983     /* MOD_VEX_0F73_REG_7 */
11984     { Bad_Opcode },
11985     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11986   },
11987   {
11988     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11989     { "kmovw",          { Ew, MaskG }, 0 },
11990     { Bad_Opcode },
11991   },
11992   {
11993     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11994     { "kmovq",          { Eq, MaskG }, 0 },
11995     { Bad_Opcode },
11996   },
11997   {
11998     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11999     { "kmovb",          { Eb, MaskG }, 0 },
12000     { Bad_Opcode },
12001   },
12002   {
12003     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12004     { "kmovd",          { Ed, MaskG }, 0 },
12005     { Bad_Opcode },
12006   },
12007   {
12008     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12009     { Bad_Opcode },
12010     { "kmovw",          { MaskG, Rdq }, 0 },
12011   },
12012   {
12013     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12014     { Bad_Opcode },
12015     { "kmovb",          { MaskG, Rdq }, 0 },
12016   },
12017   {
12018     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12019     { Bad_Opcode },
12020     { "kmovd",          { MaskG, Rdq }, 0 },
12021   },
12022   {
12023     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12024     { Bad_Opcode },
12025     { "kmovq",          { MaskG, Rdq }, 0 },
12026   },
12027   {
12028     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12029     { Bad_Opcode },
12030     { "kmovw",          { Gdq, MaskR }, 0 },
12031   },
12032   {
12033     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12034     { Bad_Opcode },
12035     { "kmovb",          { Gdq, MaskR }, 0 },
12036   },
12037   {
12038     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12039     { Bad_Opcode },
12040     { "kmovd",          { Gdq, MaskR }, 0 },
12041   },
12042   {
12043     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12044     { Bad_Opcode },
12045     { "kmovq",          { Gdq, MaskR }, 0 },
12046   },
12047   {
12048     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12049     { Bad_Opcode },
12050     { "kortestw", { MaskG, MaskR }, 0 },
12051   },
12052   {
12053     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12054     { Bad_Opcode },
12055     { "kortestq", { MaskG, MaskR }, 0 },
12056   },
12057   {
12058     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12059     { Bad_Opcode },
12060     { "kortestb", { MaskG, MaskR }, 0 },
12061   },
12062   {
12063     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12064     { Bad_Opcode },
12065     { "kortestd", { MaskG, MaskR }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12069     { Bad_Opcode },
12070     { "ktestw", { MaskG, MaskR }, 0 },
12071   },
12072   {
12073     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12074     { Bad_Opcode },
12075     { "ktestq", { MaskG, MaskR }, 0 },
12076   },
12077   {
12078     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12079     { Bad_Opcode },
12080     { "ktestb", { MaskG, MaskR }, 0 },
12081   },
12082   {
12083     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12084     { Bad_Opcode },
12085     { "ktestd", { MaskG, MaskR }, 0 },
12086   },
12087   {
12088     /* MOD_VEX_0FAE_REG_2 */
12089     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12090   },
12091   {
12092     /* MOD_VEX_0FAE_REG_3 */
12093     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12094   },
12095   {
12096     /* MOD_VEX_0FD7_PREFIX_2 */
12097     { Bad_Opcode },
12098     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12099   },
12100   {
12101     /* MOD_VEX_0FE7_PREFIX_2 */
12102     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12103   },
12104   {
12105     /* MOD_VEX_0FF0_PREFIX_3 */
12106     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12107   },
12108   {
12109     /* MOD_VEX_0F381A_PREFIX_2 */
12110     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12111   },
12112   {
12113     /* MOD_VEX_0F382A_PREFIX_2 */
12114     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12115   },
12116   {
12117     /* MOD_VEX_0F382C_PREFIX_2 */
12118     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12119   },
12120   {
12121     /* MOD_VEX_0F382D_PREFIX_2 */
12122     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12123   },
12124   {
12125     /* MOD_VEX_0F382E_PREFIX_2 */
12126     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12127   },
12128   {
12129     /* MOD_VEX_0F382F_PREFIX_2 */
12130     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12131   },
12132   {
12133     /* MOD_VEX_0F385A_PREFIX_2 */
12134     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12135   },
12136   {
12137     /* MOD_VEX_0F388C_PREFIX_2 */
12138     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12139   },
12140   {
12141     /* MOD_VEX_0F388E_PREFIX_2 */
12142     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12143   },
12144   {
12145     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12146     { Bad_Opcode },
12147     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12148   },
12149   {
12150     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12151     { Bad_Opcode },
12152     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12153   },
12154   {
12155     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12156     { Bad_Opcode },
12157     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12158   },
12159   {
12160     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12161     { Bad_Opcode },
12162     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12163   },
12164   {
12165     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12166     { Bad_Opcode },
12167     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12168   },
12169   {
12170     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12171     { Bad_Opcode },
12172     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12173   },
12174   {
12175     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12176     { Bad_Opcode },
12177     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12178   },
12179   {
12180     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12181     { Bad_Opcode },
12182     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12183   },
12184 #define NEED_MOD_TABLE
12185 #include "i386-dis-evex.h"
12186 #undef NEED_MOD_TABLE
12187 };
12188
12189 static const struct dis386 rm_table[][8] = {
12190   {
12191     /* RM_C6_REG_7 */
12192     { "xabort",         { Skip_MODRM, Ib }, 0 },
12193   },
12194   {
12195     /* RM_C7_REG_7 */
12196     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12197   },
12198   {
12199     /* RM_0F01_REG_0 */
12200     { Bad_Opcode },
12201     { "vmcall",         { Skip_MODRM }, 0 },
12202     { "vmlaunch",       { Skip_MODRM }, 0 },
12203     { "vmresume",       { Skip_MODRM }, 0 },
12204     { "vmxoff",         { Skip_MODRM }, 0 },
12205   },
12206   {
12207     /* RM_0F01_REG_1 */
12208     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12209     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12210     { "clac",           { Skip_MODRM }, 0 },
12211     { "stac",           { Skip_MODRM }, 0 },
12212     { Bad_Opcode },
12213     { Bad_Opcode },
12214     { Bad_Opcode },
12215     { "encls",          { Skip_MODRM }, 0 },
12216   },
12217   {
12218     /* RM_0F01_REG_2 */
12219     { "xgetbv",         { Skip_MODRM }, 0 },
12220     { "xsetbv",         { Skip_MODRM }, 0 },
12221     { Bad_Opcode },
12222     { Bad_Opcode },
12223     { "vmfunc",         { Skip_MODRM }, 0 },
12224     { "xend",           { Skip_MODRM }, 0 },
12225     { "xtest",          { Skip_MODRM }, 0 },
12226     { "enclu",          { Skip_MODRM }, 0 },
12227   },
12228   {
12229     /* RM_0F01_REG_3 */
12230     { "vmrun",          { Skip_MODRM }, 0 },
12231     { "vmmcall",        { Skip_MODRM }, 0 },
12232     { "vmload",         { Skip_MODRM }, 0 },
12233     { "vmsave",         { Skip_MODRM }, 0 },
12234     { "stgi",           { Skip_MODRM }, 0 },
12235     { "clgi",           { Skip_MODRM }, 0 },
12236     { "skinit",         { Skip_MODRM }, 0 },
12237     { "invlpga",        { Skip_MODRM }, 0 },
12238   },
12239   {
12240     /* RM_0F01_REG_5 */
12241     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12242     { Bad_Opcode },
12243     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12244     { Bad_Opcode },
12245     { Bad_Opcode },
12246     { Bad_Opcode },
12247     { "rdpkru",         { Skip_MODRM }, 0 },
12248     { "wrpkru",         { Skip_MODRM }, 0 },
12249   },
12250   {
12251     /* RM_0F01_REG_7 */
12252     { "swapgs",         { Skip_MODRM }, 0  },
12253     { "rdtscp",         { Skip_MODRM }, 0  },
12254     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12255     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12256     { "clzero",         { Skip_MODRM }, 0  },
12257   },
12258   {
12259     /* RM_0F1E_MOD_3_REG_7 */
12260     { "nopQ",           { Ev }, 0 },
12261     { "nopQ",           { Ev }, 0 },
12262     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12263     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12264     { "nopQ",           { Ev }, 0 },
12265     { "nopQ",           { Ev }, 0 },
12266     { "nopQ",           { Ev }, 0 },
12267     { "nopQ",           { Ev }, 0 },
12268   },
12269   {
12270     /* RM_0FAE_REG_6 */
12271     { "mfence",         { Skip_MODRM }, 0 },
12272   },
12273   {
12274     /* RM_0FAE_REG_7 */
12275     { "sfence",         { Skip_MODRM }, 0 },
12276
12277   },
12278 };
12279
12280 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12281
12282 /* We use the high bit to indicate different name for the same
12283    prefix.  */
12284 #define REP_PREFIX      (0xf3 | 0x100)
12285 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12286 #define XRELEASE_PREFIX (0xf3 | 0x400)
12287 #define BND_PREFIX      (0xf2 | 0x400)
12288 #define NOTRACK_PREFIX  (0x3e | 0x100)
12289
12290 static int
12291 ckprefix (void)
12292 {
12293   int newrex, i, length;
12294   rex = 0;
12295   rex_ignored = 0;
12296   prefixes = 0;
12297   used_prefixes = 0;
12298   rex_used = 0;
12299   last_lock_prefix = -1;
12300   last_repz_prefix = -1;
12301   last_repnz_prefix = -1;
12302   last_data_prefix = -1;
12303   last_addr_prefix = -1;
12304   last_rex_prefix = -1;
12305   last_seg_prefix = -1;
12306   last_active_prefix = -1;
12307   fwait_prefix = -1;
12308   active_seg_prefix = 0;
12309   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12310     all_prefixes[i] = 0;
12311   i = 0;
12312   length = 0;
12313   /* The maximum instruction length is 15bytes.  */
12314   while (length < MAX_CODE_LENGTH - 1)
12315     {
12316       FETCH_DATA (the_info, codep + 1);
12317       newrex = 0;
12318       switch (*codep)
12319         {
12320         /* REX prefixes family.  */
12321         case 0x40:
12322         case 0x41:
12323         case 0x42:
12324         case 0x43:
12325         case 0x44:
12326         case 0x45:
12327         case 0x46:
12328         case 0x47:
12329         case 0x48:
12330         case 0x49:
12331         case 0x4a:
12332         case 0x4b:
12333         case 0x4c:
12334         case 0x4d:
12335         case 0x4e:
12336         case 0x4f:
12337           if (address_mode == mode_64bit)
12338             newrex = *codep;
12339           else
12340             return 1;
12341           last_rex_prefix = i;
12342           break;
12343         case 0xf3:
12344           prefixes |= PREFIX_REPZ;
12345           last_repz_prefix = i;
12346           break;
12347         case 0xf2:
12348           prefixes |= PREFIX_REPNZ;
12349           last_repnz_prefix = i;
12350           break;
12351         case 0xf0:
12352           prefixes |= PREFIX_LOCK;
12353           last_lock_prefix = i;
12354           break;
12355         case 0x2e:
12356           prefixes |= PREFIX_CS;
12357           last_seg_prefix = i;
12358           active_seg_prefix = PREFIX_CS;
12359           break;
12360         case 0x36:
12361           prefixes |= PREFIX_SS;
12362           last_seg_prefix = i;
12363           active_seg_prefix = PREFIX_SS;
12364           break;
12365         case 0x3e:
12366           prefixes |= PREFIX_DS;
12367           last_seg_prefix = i;
12368           active_seg_prefix = PREFIX_DS;
12369           break;
12370         case 0x26:
12371           prefixes |= PREFIX_ES;
12372           last_seg_prefix = i;
12373           active_seg_prefix = PREFIX_ES;
12374           break;
12375         case 0x64:
12376           prefixes |= PREFIX_FS;
12377           last_seg_prefix = i;
12378           active_seg_prefix = PREFIX_FS;
12379           break;
12380         case 0x65:
12381           prefixes |= PREFIX_GS;
12382           last_seg_prefix = i;
12383           active_seg_prefix = PREFIX_GS;
12384           break;
12385         case 0x66:
12386           prefixes |= PREFIX_DATA;
12387           last_data_prefix = i;
12388           break;
12389         case 0x67:
12390           prefixes |= PREFIX_ADDR;
12391           last_addr_prefix = i;
12392           break;
12393         case FWAIT_OPCODE:
12394           /* fwait is really an instruction.  If there are prefixes
12395              before the fwait, they belong to the fwait, *not* to the
12396              following instruction.  */
12397           fwait_prefix = i;
12398           if (prefixes || rex)
12399             {
12400               prefixes |= PREFIX_FWAIT;
12401               codep++;
12402               /* This ensures that the previous REX prefixes are noticed
12403                  as unused prefixes, as in the return case below.  */
12404               rex_used = rex;
12405               return 1;
12406             }
12407           prefixes = PREFIX_FWAIT;
12408           break;
12409         default:
12410           return 1;
12411         }
12412       /* Rex is ignored when followed by another prefix.  */
12413       if (rex)
12414         {
12415           rex_used = rex;
12416           return 1;
12417         }
12418       if (*codep != FWAIT_OPCODE)
12419         {
12420           last_active_prefix = i;
12421           all_prefixes[i++] = *codep;
12422         }
12423       rex = newrex;
12424       codep++;
12425       length++;
12426     }
12427   return 0;
12428 }
12429
12430 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12431    prefix byte.  */
12432
12433 static const char *
12434 prefix_name (int pref, int sizeflag)
12435 {
12436   static const char *rexes [16] =
12437     {
12438       "rex",            /* 0x40 */
12439       "rex.B",          /* 0x41 */
12440       "rex.X",          /* 0x42 */
12441       "rex.XB",         /* 0x43 */
12442       "rex.R",          /* 0x44 */
12443       "rex.RB",         /* 0x45 */
12444       "rex.RX",         /* 0x46 */
12445       "rex.RXB",        /* 0x47 */
12446       "rex.W",          /* 0x48 */
12447       "rex.WB",         /* 0x49 */
12448       "rex.WX",         /* 0x4a */
12449       "rex.WXB",        /* 0x4b */
12450       "rex.WR",         /* 0x4c */
12451       "rex.WRB",        /* 0x4d */
12452       "rex.WRX",        /* 0x4e */
12453       "rex.WRXB",       /* 0x4f */
12454     };
12455
12456   switch (pref)
12457     {
12458     /* REX prefixes family.  */
12459     case 0x40:
12460     case 0x41:
12461     case 0x42:
12462     case 0x43:
12463     case 0x44:
12464     case 0x45:
12465     case 0x46:
12466     case 0x47:
12467     case 0x48:
12468     case 0x49:
12469     case 0x4a:
12470     case 0x4b:
12471     case 0x4c:
12472     case 0x4d:
12473     case 0x4e:
12474     case 0x4f:
12475       return rexes [pref - 0x40];
12476     case 0xf3:
12477       return "repz";
12478     case 0xf2:
12479       return "repnz";
12480     case 0xf0:
12481       return "lock";
12482     case 0x2e:
12483       return "cs";
12484     case 0x36:
12485       return "ss";
12486     case 0x3e:
12487       return "ds";
12488     case 0x26:
12489       return "es";
12490     case 0x64:
12491       return "fs";
12492     case 0x65:
12493       return "gs";
12494     case 0x66:
12495       return (sizeflag & DFLAG) ? "data16" : "data32";
12496     case 0x67:
12497       if (address_mode == mode_64bit)
12498         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12499       else
12500         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12501     case FWAIT_OPCODE:
12502       return "fwait";
12503     case REP_PREFIX:
12504       return "rep";
12505     case XACQUIRE_PREFIX:
12506       return "xacquire";
12507     case XRELEASE_PREFIX:
12508       return "xrelease";
12509     case BND_PREFIX:
12510       return "bnd";
12511     case NOTRACK_PREFIX:
12512       return "notrack";
12513     default:
12514       return NULL;
12515     }
12516 }
12517
12518 static char op_out[MAX_OPERANDS][100];
12519 static int op_ad, op_index[MAX_OPERANDS];
12520 static int two_source_ops;
12521 static bfd_vma op_address[MAX_OPERANDS];
12522 static bfd_vma op_riprel[MAX_OPERANDS];
12523 static bfd_vma start_pc;
12524
12525 /*
12526  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12527  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12528  *   section of the "Virtual 8086 Mode" chapter.)
12529  * 'pc' should be the address of this instruction, it will
12530  *   be used to print the target address if this is a relative jump or call
12531  * The function returns the length of this instruction in bytes.
12532  */
12533
12534 static char intel_syntax;
12535 static char intel_mnemonic = !SYSV386_COMPAT;
12536 static char open_char;
12537 static char close_char;
12538 static char separator_char;
12539 static char scale_char;
12540
12541 enum x86_64_isa
12542 {
12543   amd64 = 0,
12544   intel64
12545 };
12546
12547 static enum x86_64_isa isa64;
12548
12549 /* Here for backwards compatibility.  When gdb stops using
12550    print_insn_i386_att and print_insn_i386_intel these functions can
12551    disappear, and print_insn_i386 be merged into print_insn.  */
12552 int
12553 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12554 {
12555   intel_syntax = 0;
12556
12557   return print_insn (pc, info);
12558 }
12559
12560 int
12561 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12562 {
12563   intel_syntax = 1;
12564
12565   return print_insn (pc, info);
12566 }
12567
12568 int
12569 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12570 {
12571   intel_syntax = -1;
12572
12573   return print_insn (pc, info);
12574 }
12575
12576 void
12577 print_i386_disassembler_options (FILE *stream)
12578 {
12579   fprintf (stream, _("\n\
12580 The following i386/x86-64 specific disassembler options are supported for use\n\
12581 with the -M switch (multiple options should be separated by commas):\n"));
12582
12583   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12584   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12585   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12586   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12587   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12588   fprintf (stream, _("  att-mnemonic\n"
12589                      "              Display instruction in AT&T mnemonic\n"));
12590   fprintf (stream, _("  intel-mnemonic\n"
12591                      "              Display instruction in Intel mnemonic\n"));
12592   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12593   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12594   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12595   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12596   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12597   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12598   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12599   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12600 }
12601
12602 /* Bad opcode.  */
12603 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12604
12605 /* Get a pointer to struct dis386 with a valid name.  */
12606
12607 static const struct dis386 *
12608 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12609 {
12610   int vindex, vex_table_index;
12611
12612   if (dp->name != NULL)
12613     return dp;
12614
12615   switch (dp->op[0].bytemode)
12616     {
12617     case USE_REG_TABLE:
12618       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12619       break;
12620
12621     case USE_MOD_TABLE:
12622       vindex = modrm.mod == 0x3 ? 1 : 0;
12623       dp = &mod_table[dp->op[1].bytemode][vindex];
12624       break;
12625
12626     case USE_RM_TABLE:
12627       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12628       break;
12629
12630     case USE_PREFIX_TABLE:
12631       if (need_vex)
12632         {
12633           /* The prefix in VEX is implicit.  */
12634           switch (vex.prefix)
12635             {
12636             case 0:
12637               vindex = 0;
12638               break;
12639             case REPE_PREFIX_OPCODE:
12640               vindex = 1;
12641               break;
12642             case DATA_PREFIX_OPCODE:
12643               vindex = 2;
12644               break;
12645             case REPNE_PREFIX_OPCODE:
12646               vindex = 3;
12647               break;
12648             default:
12649               abort ();
12650               break;
12651             }
12652         }
12653       else
12654         {
12655           int last_prefix = -1;
12656           int prefix = 0;
12657           vindex = 0;
12658           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12659              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12660              last one wins.  */
12661           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12662             {
12663               if (last_repz_prefix > last_repnz_prefix)
12664                 {
12665                   vindex = 1;
12666                   prefix = PREFIX_REPZ;
12667                   last_prefix = last_repz_prefix;
12668                 }
12669               else
12670                 {
12671                   vindex = 3;
12672                   prefix = PREFIX_REPNZ;
12673                   last_prefix = last_repnz_prefix;
12674                 }
12675
12676               /* Check if prefix should be ignored.  */
12677               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12678                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12679                    & prefix) != 0)
12680                 vindex = 0;
12681             }
12682
12683           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12684             {
12685               vindex = 2;
12686               prefix = PREFIX_DATA;
12687               last_prefix = last_data_prefix;
12688             }
12689
12690           if (vindex != 0)
12691             {
12692               used_prefixes |= prefix;
12693               all_prefixes[last_prefix] = 0;
12694             }
12695         }
12696       dp = &prefix_table[dp->op[1].bytemode][vindex];
12697       break;
12698
12699     case USE_X86_64_TABLE:
12700       vindex = address_mode == mode_64bit ? 1 : 0;
12701       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12702       break;
12703
12704     case USE_3BYTE_TABLE:
12705       FETCH_DATA (info, codep + 2);
12706       vindex = *codep++;
12707       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12708       end_codep = codep;
12709       modrm.mod = (*codep >> 6) & 3;
12710       modrm.reg = (*codep >> 3) & 7;
12711       modrm.rm = *codep & 7;
12712       break;
12713
12714     case USE_VEX_LEN_TABLE:
12715       if (!need_vex)
12716         abort ();
12717
12718       switch (vex.length)
12719         {
12720         case 128:
12721           vindex = 0;
12722           break;
12723         case 256:
12724           vindex = 1;
12725           break;
12726         default:
12727           abort ();
12728           break;
12729         }
12730
12731       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12732       break;
12733
12734     case USE_XOP_8F_TABLE:
12735       FETCH_DATA (info, codep + 3);
12736       /* All bits in the REX prefix are ignored.  */
12737       rex_ignored = rex;
12738       rex = ~(*codep >> 5) & 0x7;
12739
12740       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12741       switch ((*codep & 0x1f))
12742         {
12743         default:
12744           dp = &bad_opcode;
12745           return dp;
12746         case 0x8:
12747           vex_table_index = XOP_08;
12748           break;
12749         case 0x9:
12750           vex_table_index = XOP_09;
12751           break;
12752         case 0xa:
12753           vex_table_index = XOP_0A;
12754           break;
12755         }
12756       codep++;
12757       vex.w = *codep & 0x80;
12758       if (vex.w && address_mode == mode_64bit)
12759         rex |= REX_W;
12760
12761       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12762       if (address_mode != mode_64bit)
12763         {
12764           /* In 16/32-bit mode REX_B is silently ignored.  */
12765           rex &= ~REX_B;
12766           if (vex.register_specifier > 0x7)
12767             {
12768               dp = &bad_opcode;
12769               return dp;
12770             }
12771         }
12772
12773       vex.length = (*codep & 0x4) ? 256 : 128;
12774       switch ((*codep & 0x3))
12775         {
12776         case 0:
12777           vex.prefix = 0;
12778           break;
12779         case 1:
12780           vex.prefix = DATA_PREFIX_OPCODE;
12781           break;
12782         case 2:
12783           vex.prefix = REPE_PREFIX_OPCODE;
12784           break;
12785         case 3:
12786           vex.prefix = REPNE_PREFIX_OPCODE;
12787           break;
12788         }
12789       need_vex = 1;
12790       need_vex_reg = 1;
12791       codep++;
12792       vindex = *codep++;
12793       dp = &xop_table[vex_table_index][vindex];
12794
12795       end_codep = codep;
12796       FETCH_DATA (info, codep + 1);
12797       modrm.mod = (*codep >> 6) & 3;
12798       modrm.reg = (*codep >> 3) & 7;
12799       modrm.rm = *codep & 7;
12800       break;
12801
12802     case USE_VEX_C4_TABLE:
12803       /* VEX prefix.  */
12804       FETCH_DATA (info, codep + 3);
12805       /* All bits in the REX prefix are ignored.  */
12806       rex_ignored = rex;
12807       rex = ~(*codep >> 5) & 0x7;
12808       switch ((*codep & 0x1f))
12809         {
12810         default:
12811           dp = &bad_opcode;
12812           return dp;
12813         case 0x1:
12814           vex_table_index = VEX_0F;
12815           break;
12816         case 0x2:
12817           vex_table_index = VEX_0F38;
12818           break;
12819         case 0x3:
12820           vex_table_index = VEX_0F3A;
12821           break;
12822         }
12823       codep++;
12824       vex.w = *codep & 0x80;
12825       if (address_mode == mode_64bit)
12826         {
12827           if (vex.w)
12828             rex |= REX_W;
12829           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12830         }
12831       else
12832         {
12833           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12834              is ignored, other REX bits are 0 and the highest bit in
12835              VEX.vvvv is also ignored.  */
12836           rex = 0;
12837           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12838         }
12839       vex.length = (*codep & 0x4) ? 256 : 128;
12840       switch ((*codep & 0x3))
12841         {
12842         case 0:
12843           vex.prefix = 0;
12844           break;
12845         case 1:
12846           vex.prefix = DATA_PREFIX_OPCODE;
12847           break;
12848         case 2:
12849           vex.prefix = REPE_PREFIX_OPCODE;
12850           break;
12851         case 3:
12852           vex.prefix = REPNE_PREFIX_OPCODE;
12853           break;
12854         }
12855       need_vex = 1;
12856       need_vex_reg = 1;
12857       codep++;
12858       vindex = *codep++;
12859       dp = &vex_table[vex_table_index][vindex];
12860       end_codep = codep;
12861       /* There is no MODRM byte for VEX0F 77.  */
12862       if (vex_table_index != VEX_0F || vindex != 0x77)
12863         {
12864           FETCH_DATA (info, codep + 1);
12865           modrm.mod = (*codep >> 6) & 3;
12866           modrm.reg = (*codep >> 3) & 7;
12867           modrm.rm = *codep & 7;
12868         }
12869       break;
12870
12871     case USE_VEX_C5_TABLE:
12872       /* VEX prefix.  */
12873       FETCH_DATA (info, codep + 2);
12874       /* All bits in the REX prefix are ignored.  */
12875       rex_ignored = rex;
12876       rex = (*codep & 0x80) ? 0 : REX_R;
12877
12878       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12879          VEX.vvvv is 1.  */
12880       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12881       vex.w = 0;
12882       vex.length = (*codep & 0x4) ? 256 : 128;
12883       switch ((*codep & 0x3))
12884         {
12885         case 0:
12886           vex.prefix = 0;
12887           break;
12888         case 1:
12889           vex.prefix = DATA_PREFIX_OPCODE;
12890           break;
12891         case 2:
12892           vex.prefix = REPE_PREFIX_OPCODE;
12893           break;
12894         case 3:
12895           vex.prefix = REPNE_PREFIX_OPCODE;
12896           break;
12897         }
12898       need_vex = 1;
12899       need_vex_reg = 1;
12900       codep++;
12901       vindex = *codep++;
12902       dp = &vex_table[dp->op[1].bytemode][vindex];
12903       end_codep = codep;
12904       /* There is no MODRM byte for VEX 77.  */
12905       if (vindex != 0x77)
12906         {
12907           FETCH_DATA (info, codep + 1);
12908           modrm.mod = (*codep >> 6) & 3;
12909           modrm.reg = (*codep >> 3) & 7;
12910           modrm.rm = *codep & 7;
12911         }
12912       break;
12913
12914     case USE_VEX_W_TABLE:
12915       if (!need_vex)
12916         abort ();
12917
12918       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12919       break;
12920
12921     case USE_EVEX_TABLE:
12922       two_source_ops = 0;
12923       /* EVEX prefix.  */
12924       vex.evex = 1;
12925       FETCH_DATA (info, codep + 4);
12926       /* All bits in the REX prefix are ignored.  */
12927       rex_ignored = rex;
12928       /* The first byte after 0x62.  */
12929       rex = ~(*codep >> 5) & 0x7;
12930       vex.r = *codep & 0x10;
12931       switch ((*codep & 0xf))
12932         {
12933         default:
12934           return &bad_opcode;
12935         case 0x1:
12936           vex_table_index = EVEX_0F;
12937           break;
12938         case 0x2:
12939           vex_table_index = EVEX_0F38;
12940           break;
12941         case 0x3:
12942           vex_table_index = EVEX_0F3A;
12943           break;
12944         }
12945
12946       /* The second byte after 0x62.  */
12947       codep++;
12948       vex.w = *codep & 0x80;
12949       if (vex.w && address_mode == mode_64bit)
12950         rex |= REX_W;
12951
12952       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12953       if (address_mode != mode_64bit)
12954         {
12955           /* In 16/32-bit mode silently ignore following bits.  */
12956           rex &= ~REX_B;
12957           vex.r = 1;
12958           vex.v = 1;
12959           vex.register_specifier &= 0x7;
12960         }
12961
12962       /* The U bit.  */
12963       if (!(*codep & 0x4))
12964         return &bad_opcode;
12965
12966       switch ((*codep & 0x3))
12967         {
12968         case 0:
12969           vex.prefix = 0;
12970           break;
12971         case 1:
12972           vex.prefix = DATA_PREFIX_OPCODE;
12973           break;
12974         case 2:
12975           vex.prefix = REPE_PREFIX_OPCODE;
12976           break;
12977         case 3:
12978           vex.prefix = REPNE_PREFIX_OPCODE;
12979           break;
12980         }
12981
12982       /* The third byte after 0x62.  */
12983       codep++;
12984
12985       /* Remember the static rounding bits.  */
12986       vex.ll = (*codep >> 5) & 3;
12987       vex.b = (*codep & 0x10) != 0;
12988
12989       vex.v = *codep & 0x8;
12990       vex.mask_register_specifier = *codep & 0x7;
12991       vex.zeroing = *codep & 0x80;
12992
12993       need_vex = 1;
12994       need_vex_reg = 1;
12995       codep++;
12996       vindex = *codep++;
12997       dp = &evex_table[vex_table_index][vindex];
12998       end_codep = codep;
12999       FETCH_DATA (info, codep + 1);
13000       modrm.mod = (*codep >> 6) & 3;
13001       modrm.reg = (*codep >> 3) & 7;
13002       modrm.rm = *codep & 7;
13003
13004       /* Set vector length.  */
13005       if (modrm.mod == 3 && vex.b)
13006         vex.length = 512;
13007       else
13008         {
13009           switch (vex.ll)
13010             {
13011             case 0x0:
13012               vex.length = 128;
13013               break;
13014             case 0x1:
13015               vex.length = 256;
13016               break;
13017             case 0x2:
13018               vex.length = 512;
13019               break;
13020             default:
13021               return &bad_opcode;
13022             }
13023         }
13024       break;
13025
13026     case 0:
13027       dp = &bad_opcode;
13028       break;
13029
13030     default:
13031       abort ();
13032     }
13033
13034   if (dp->name != NULL)
13035     return dp;
13036   else
13037     return get_valid_dis386 (dp, info);
13038 }
13039
13040 static void
13041 get_sib (disassemble_info *info, int sizeflag)
13042 {
13043   /* If modrm.mod == 3, operand must be register.  */
13044   if (need_modrm
13045       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13046       && modrm.mod != 3
13047       && modrm.rm == 4)
13048     {
13049       FETCH_DATA (info, codep + 2);
13050       sib.index = (codep [1] >> 3) & 7;
13051       sib.scale = (codep [1] >> 6) & 3;
13052       sib.base = codep [1] & 7;
13053     }
13054 }
13055
13056 static int
13057 print_insn (bfd_vma pc, disassemble_info *info)
13058 {
13059   const struct dis386 *dp;
13060   int i;
13061   char *op_txt[MAX_OPERANDS];
13062   int needcomma;
13063   int sizeflag, orig_sizeflag;
13064   const char *p;
13065   struct dis_private priv;
13066   int prefix_length;
13067
13068   priv.orig_sizeflag = AFLAG | DFLAG;
13069   if ((info->mach & bfd_mach_i386_i386) != 0)
13070     address_mode = mode_32bit;
13071   else if (info->mach == bfd_mach_i386_i8086)
13072     {
13073       address_mode = mode_16bit;
13074       priv.orig_sizeflag = 0;
13075     }
13076   else
13077     address_mode = mode_64bit;
13078
13079   if (intel_syntax == (char) -1)
13080     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13081
13082   for (p = info->disassembler_options; p != NULL; )
13083     {
13084       if (CONST_STRNEQ (p, "amd64"))
13085         isa64 = amd64;
13086       else if (CONST_STRNEQ (p, "intel64"))
13087         isa64 = intel64;
13088       else if (CONST_STRNEQ (p, "x86-64"))
13089         {
13090           address_mode = mode_64bit;
13091           priv.orig_sizeflag = AFLAG | DFLAG;
13092         }
13093       else if (CONST_STRNEQ (p, "i386"))
13094         {
13095           address_mode = mode_32bit;
13096           priv.orig_sizeflag = AFLAG | DFLAG;
13097         }
13098       else if (CONST_STRNEQ (p, "i8086"))
13099         {
13100           address_mode = mode_16bit;
13101           priv.orig_sizeflag = 0;
13102         }
13103       else if (CONST_STRNEQ (p, "intel"))
13104         {
13105           intel_syntax = 1;
13106           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13107             intel_mnemonic = 1;
13108         }
13109       else if (CONST_STRNEQ (p, "att"))
13110         {
13111           intel_syntax = 0;
13112           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13113             intel_mnemonic = 0;
13114         }
13115       else if (CONST_STRNEQ (p, "addr"))
13116         {
13117           if (address_mode == mode_64bit)
13118             {
13119               if (p[4] == '3' && p[5] == '2')
13120                 priv.orig_sizeflag &= ~AFLAG;
13121               else if (p[4] == '6' && p[5] == '4')
13122                 priv.orig_sizeflag |= AFLAG;
13123             }
13124           else
13125             {
13126               if (p[4] == '1' && p[5] == '6')
13127                 priv.orig_sizeflag &= ~AFLAG;
13128               else if (p[4] == '3' && p[5] == '2')
13129                 priv.orig_sizeflag |= AFLAG;
13130             }
13131         }
13132       else if (CONST_STRNEQ (p, "data"))
13133         {
13134           if (p[4] == '1' && p[5] == '6')
13135             priv.orig_sizeflag &= ~DFLAG;
13136           else if (p[4] == '3' && p[5] == '2')
13137             priv.orig_sizeflag |= DFLAG;
13138         }
13139       else if (CONST_STRNEQ (p, "suffix"))
13140         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13141
13142       p = strchr (p, ',');
13143       if (p != NULL)
13144         p++;
13145     }
13146
13147   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13148     {
13149       (*info->fprintf_func) (info->stream,
13150                              _("64-bit address is disabled"));
13151       return -1;
13152     }
13153
13154   if (intel_syntax)
13155     {
13156       names64 = intel_names64;
13157       names32 = intel_names32;
13158       names16 = intel_names16;
13159       names8 = intel_names8;
13160       names8rex = intel_names8rex;
13161       names_seg = intel_names_seg;
13162       names_mm = intel_names_mm;
13163       names_bnd = intel_names_bnd;
13164       names_xmm = intel_names_xmm;
13165       names_ymm = intel_names_ymm;
13166       names_zmm = intel_names_zmm;
13167       index64 = intel_index64;
13168       index32 = intel_index32;
13169       names_mask = intel_names_mask;
13170       index16 = intel_index16;
13171       open_char = '[';
13172       close_char = ']';
13173       separator_char = '+';
13174       scale_char = '*';
13175     }
13176   else
13177     {
13178       names64 = att_names64;
13179       names32 = att_names32;
13180       names16 = att_names16;
13181       names8 = att_names8;
13182       names8rex = att_names8rex;
13183       names_seg = att_names_seg;
13184       names_mm = att_names_mm;
13185       names_bnd = att_names_bnd;
13186       names_xmm = att_names_xmm;
13187       names_ymm = att_names_ymm;
13188       names_zmm = att_names_zmm;
13189       index64 = att_index64;
13190       index32 = att_index32;
13191       names_mask = att_names_mask;
13192       index16 = att_index16;
13193       open_char = '(';
13194       close_char =  ')';
13195       separator_char = ',';
13196       scale_char = ',';
13197     }
13198
13199   /* The output looks better if we put 7 bytes on a line, since that
13200      puts most long word instructions on a single line.  Use 8 bytes
13201      for Intel L1OM.  */
13202   if ((info->mach & bfd_mach_l1om) != 0)
13203     info->bytes_per_line = 8;
13204   else
13205     info->bytes_per_line = 7;
13206
13207   info->private_data = &priv;
13208   priv.max_fetched = priv.the_buffer;
13209   priv.insn_start = pc;
13210
13211   obuf[0] = 0;
13212   for (i = 0; i < MAX_OPERANDS; ++i)
13213     {
13214       op_out[i][0] = 0;
13215       op_index[i] = -1;
13216     }
13217
13218   the_info = info;
13219   start_pc = pc;
13220   start_codep = priv.the_buffer;
13221   codep = priv.the_buffer;
13222
13223   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13224     {
13225       const char *name;
13226
13227       /* Getting here means we tried for data but didn't get it.  That
13228          means we have an incomplete instruction of some sort.  Just
13229          print the first byte as a prefix or a .byte pseudo-op.  */
13230       if (codep > priv.the_buffer)
13231         {
13232           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13233           if (name != NULL)
13234             (*info->fprintf_func) (info->stream, "%s", name);
13235           else
13236             {
13237               /* Just print the first byte as a .byte instruction.  */
13238               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13239                                      (unsigned int) priv.the_buffer[0]);
13240             }
13241
13242           return 1;
13243         }
13244
13245       return -1;
13246     }
13247
13248   obufp = obuf;
13249   sizeflag = priv.orig_sizeflag;
13250
13251   if (!ckprefix () || rex_used)
13252     {
13253       /* Too many prefixes or unused REX prefixes.  */
13254       for (i = 0;
13255            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13256            i++)
13257         (*info->fprintf_func) (info->stream, "%s%s",
13258                                i == 0 ? "" : " ",
13259                                prefix_name (all_prefixes[i], sizeflag));
13260       return i;
13261     }
13262
13263   insn_codep = codep;
13264
13265   FETCH_DATA (info, codep + 1);
13266   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13267
13268   if (((prefixes & PREFIX_FWAIT)
13269        && ((*codep < 0xd8) || (*codep > 0xdf))))
13270     {
13271       /* Handle prefixes before fwait.  */
13272       for (i = 0; i < fwait_prefix && all_prefixes[i];
13273            i++)
13274         (*info->fprintf_func) (info->stream, "%s ",
13275                                prefix_name (all_prefixes[i], sizeflag));
13276       (*info->fprintf_func) (info->stream, "fwait");
13277       return i + 1;
13278     }
13279
13280   if (*codep == 0x0f)
13281     {
13282       unsigned char threebyte;
13283
13284       codep++;
13285       FETCH_DATA (info, codep + 1);
13286       threebyte = *codep;
13287       dp = &dis386_twobyte[threebyte];
13288       need_modrm = twobyte_has_modrm[*codep];
13289       codep++;
13290     }
13291   else
13292     {
13293       dp = &dis386[*codep];
13294       need_modrm = onebyte_has_modrm[*codep];
13295       codep++;
13296     }
13297
13298   /* Save sizeflag for printing the extra prefixes later before updating
13299      it for mnemonic and operand processing.  The prefix names depend
13300      only on the address mode.  */
13301   orig_sizeflag = sizeflag;
13302   if (prefixes & PREFIX_ADDR)
13303     sizeflag ^= AFLAG;
13304   if ((prefixes & PREFIX_DATA))
13305     sizeflag ^= DFLAG;
13306
13307   end_codep = codep;
13308   if (need_modrm)
13309     {
13310       FETCH_DATA (info, codep + 1);
13311       modrm.mod = (*codep >> 6) & 3;
13312       modrm.reg = (*codep >> 3) & 7;
13313       modrm.rm = *codep & 7;
13314     }
13315
13316   need_vex = 0;
13317   need_vex_reg = 0;
13318   vex_w_done = 0;
13319   vex.evex = 0;
13320
13321   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13322     {
13323       get_sib (info, sizeflag);
13324       dofloat (sizeflag);
13325     }
13326   else
13327     {
13328       dp = get_valid_dis386 (dp, info);
13329       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13330         {
13331           get_sib (info, sizeflag);
13332           for (i = 0; i < MAX_OPERANDS; ++i)
13333             {
13334               obufp = op_out[i];
13335               op_ad = MAX_OPERANDS - 1 - i;
13336               if (dp->op[i].rtn)
13337                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13338               /* For EVEX instruction after the last operand masking
13339                  should be printed.  */
13340               if (i == 0 && vex.evex)
13341                 {
13342                   /* Don't print {%k0}.  */
13343                   if (vex.mask_register_specifier)
13344                     {
13345                       oappend ("{");
13346                       oappend (names_mask[vex.mask_register_specifier]);
13347                       oappend ("}");
13348                     }
13349                   if (vex.zeroing)
13350                     oappend ("{z}");
13351                 }
13352             }
13353         }
13354     }
13355
13356   /* Check if the REX prefix is used.  */
13357   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13358     all_prefixes[last_rex_prefix] = 0;
13359
13360   /* Check if the SEG prefix is used.  */
13361   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13362                    | PREFIX_FS | PREFIX_GS)) != 0
13363       && (used_prefixes & active_seg_prefix) != 0)
13364     all_prefixes[last_seg_prefix] = 0;
13365
13366   /* Check if the ADDR prefix is used.  */
13367   if ((prefixes & PREFIX_ADDR) != 0
13368       && (used_prefixes & PREFIX_ADDR) != 0)
13369     all_prefixes[last_addr_prefix] = 0;
13370
13371   /* Check if the DATA prefix is used.  */
13372   if ((prefixes & PREFIX_DATA) != 0
13373       && (used_prefixes & PREFIX_DATA) != 0)
13374     all_prefixes[last_data_prefix] = 0;
13375
13376   /* Print the extra prefixes.  */
13377   prefix_length = 0;
13378   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13379     if (all_prefixes[i])
13380       {
13381         const char *name;
13382         name = prefix_name (all_prefixes[i], orig_sizeflag);
13383         if (name == NULL)
13384           abort ();
13385         prefix_length += strlen (name) + 1;
13386         (*info->fprintf_func) (info->stream, "%s ", name);
13387       }
13388
13389   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13390      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13391      used by putop and MMX/SSE operand and may be overriden by the
13392      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13393      separately.  */
13394   if (dp->prefix_requirement == PREFIX_OPCODE
13395       && dp != &bad_opcode
13396       && (((prefixes
13397             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13398            && (used_prefixes
13399                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13400           || ((((prefixes
13401                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13402                 == PREFIX_DATA)
13403                && (used_prefixes & PREFIX_DATA) == 0))))
13404     {
13405       (*info->fprintf_func) (info->stream, "(bad)");
13406       return end_codep - priv.the_buffer;
13407     }
13408
13409   /* Check maximum code length.  */
13410   if ((codep - start_codep) > MAX_CODE_LENGTH)
13411     {
13412       (*info->fprintf_func) (info->stream, "(bad)");
13413       return MAX_CODE_LENGTH;
13414     }
13415
13416   obufp = mnemonicendp;
13417   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13418     oappend (" ");
13419   oappend (" ");
13420   (*info->fprintf_func) (info->stream, "%s", obuf);
13421
13422   /* The enter and bound instructions are printed with operands in the same
13423      order as the intel book; everything else is printed in reverse order.  */
13424   if (intel_syntax || two_source_ops)
13425     {
13426       bfd_vma riprel;
13427
13428       for (i = 0; i < MAX_OPERANDS; ++i)
13429         op_txt[i] = op_out[i];
13430
13431       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13432           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13433         {
13434           op_txt[2] = op_out[3];
13435           op_txt[3] = op_out[2];
13436         }
13437
13438       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13439         {
13440           op_ad = op_index[i];
13441           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13442           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13443           riprel = op_riprel[i];
13444           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13445           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13446         }
13447     }
13448   else
13449     {
13450       for (i = 0; i < MAX_OPERANDS; ++i)
13451         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13452     }
13453
13454   needcomma = 0;
13455   for (i = 0; i < MAX_OPERANDS; ++i)
13456     if (*op_txt[i])
13457       {
13458         if (needcomma)
13459           (*info->fprintf_func) (info->stream, ",");
13460         if (op_index[i] != -1 && !op_riprel[i])
13461           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13462         else
13463           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13464         needcomma = 1;
13465       }
13466
13467   for (i = 0; i < MAX_OPERANDS; i++)
13468     if (op_index[i] != -1 && op_riprel[i])
13469       {
13470         (*info->fprintf_func) (info->stream, "        # ");
13471         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13472                                                 + op_address[op_index[i]]), info);
13473         break;
13474       }
13475   return codep - priv.the_buffer;
13476 }
13477
13478 static const char *float_mem[] = {
13479   /* d8 */
13480   "fadd{s|}",
13481   "fmul{s|}",
13482   "fcom{s|}",
13483   "fcomp{s|}",
13484   "fsub{s|}",
13485   "fsubr{s|}",
13486   "fdiv{s|}",
13487   "fdivr{s|}",
13488   /* d9 */
13489   "fld{s|}",
13490   "(bad)",
13491   "fst{s|}",
13492   "fstp{s|}",
13493   "fldenvIC",
13494   "fldcw",
13495   "fNstenvIC",
13496   "fNstcw",
13497   /* da */
13498   "fiadd{l|}",
13499   "fimul{l|}",
13500   "ficom{l|}",
13501   "ficomp{l|}",
13502   "fisub{l|}",
13503   "fisubr{l|}",
13504   "fidiv{l|}",
13505   "fidivr{l|}",
13506   /* db */
13507   "fild{l|}",
13508   "fisttp{l|}",
13509   "fist{l|}",
13510   "fistp{l|}",
13511   "(bad)",
13512   "fld{t||t|}",
13513   "(bad)",
13514   "fstp{t||t|}",
13515   /* dc */
13516   "fadd{l|}",
13517   "fmul{l|}",
13518   "fcom{l|}",
13519   "fcomp{l|}",
13520   "fsub{l|}",
13521   "fsubr{l|}",
13522   "fdiv{l|}",
13523   "fdivr{l|}",
13524   /* dd */
13525   "fld{l|}",
13526   "fisttp{ll|}",
13527   "fst{l||}",
13528   "fstp{l|}",
13529   "frstorIC",
13530   "(bad)",
13531   "fNsaveIC",
13532   "fNstsw",
13533   /* de */
13534   "fiadd",
13535   "fimul",
13536   "ficom",
13537   "ficomp",
13538   "fisub",
13539   "fisubr",
13540   "fidiv",
13541   "fidivr",
13542   /* df */
13543   "fild",
13544   "fisttp",
13545   "fist",
13546   "fistp",
13547   "fbld",
13548   "fild{ll|}",
13549   "fbstp",
13550   "fistp{ll|}",
13551 };
13552
13553 static const unsigned char float_mem_mode[] = {
13554   /* d8 */
13555   d_mode,
13556   d_mode,
13557   d_mode,
13558   d_mode,
13559   d_mode,
13560   d_mode,
13561   d_mode,
13562   d_mode,
13563   /* d9 */
13564   d_mode,
13565   0,
13566   d_mode,
13567   d_mode,
13568   0,
13569   w_mode,
13570   0,
13571   w_mode,
13572   /* da */
13573   d_mode,
13574   d_mode,
13575   d_mode,
13576   d_mode,
13577   d_mode,
13578   d_mode,
13579   d_mode,
13580   d_mode,
13581   /* db */
13582   d_mode,
13583   d_mode,
13584   d_mode,
13585   d_mode,
13586   0,
13587   t_mode,
13588   0,
13589   t_mode,
13590   /* dc */
13591   q_mode,
13592   q_mode,
13593   q_mode,
13594   q_mode,
13595   q_mode,
13596   q_mode,
13597   q_mode,
13598   q_mode,
13599   /* dd */
13600   q_mode,
13601   q_mode,
13602   q_mode,
13603   q_mode,
13604   0,
13605   0,
13606   0,
13607   w_mode,
13608   /* de */
13609   w_mode,
13610   w_mode,
13611   w_mode,
13612   w_mode,
13613   w_mode,
13614   w_mode,
13615   w_mode,
13616   w_mode,
13617   /* df */
13618   w_mode,
13619   w_mode,
13620   w_mode,
13621   w_mode,
13622   t_mode,
13623   q_mode,
13624   t_mode,
13625   q_mode
13626 };
13627
13628 #define ST { OP_ST, 0 }
13629 #define STi { OP_STi, 0 }
13630
13631 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13632 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13633 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13634 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13635 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13636 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13637 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13638 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13639 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13640
13641 static const struct dis386 float_reg[][8] = {
13642   /* d8 */
13643   {
13644     { "fadd",   { ST, STi }, 0 },
13645     { "fmul",   { ST, STi }, 0 },
13646     { "fcom",   { STi }, 0 },
13647     { "fcomp",  { STi }, 0 },
13648     { "fsub",   { ST, STi }, 0 },
13649     { "fsubr",  { ST, STi }, 0 },
13650     { "fdiv",   { ST, STi }, 0 },
13651     { "fdivr",  { ST, STi }, 0 },
13652   },
13653   /* d9 */
13654   {
13655     { "fld",    { STi }, 0 },
13656     { "fxch",   { STi }, 0 },
13657     { FGRPd9_2 },
13658     { Bad_Opcode },
13659     { FGRPd9_4 },
13660     { FGRPd9_5 },
13661     { FGRPd9_6 },
13662     { FGRPd9_7 },
13663   },
13664   /* da */
13665   {
13666     { "fcmovb", { ST, STi }, 0 },
13667     { "fcmove", { ST, STi }, 0 },
13668     { "fcmovbe",{ ST, STi }, 0 },
13669     { "fcmovu", { ST, STi }, 0 },
13670     { Bad_Opcode },
13671     { FGRPda_5 },
13672     { Bad_Opcode },
13673     { Bad_Opcode },
13674   },
13675   /* db */
13676   {
13677     { "fcmovnb",{ ST, STi }, 0 },
13678     { "fcmovne",{ ST, STi }, 0 },
13679     { "fcmovnbe",{ ST, STi }, 0 },
13680     { "fcmovnu",{ ST, STi }, 0 },
13681     { FGRPdb_4 },
13682     { "fucomi", { ST, STi }, 0 },
13683     { "fcomi",  { ST, STi }, 0 },
13684     { Bad_Opcode },
13685   },
13686   /* dc */
13687   {
13688     { "fadd",   { STi, ST }, 0 },
13689     { "fmul",   { STi, ST }, 0 },
13690     { Bad_Opcode },
13691     { Bad_Opcode },
13692     { "fsub!M", { STi, ST }, 0 },
13693     { "fsubM",  { STi, ST }, 0 },
13694     { "fdiv!M", { STi, ST }, 0 },
13695     { "fdivM",  { STi, ST }, 0 },
13696   },
13697   /* dd */
13698   {
13699     { "ffree",  { STi }, 0 },
13700     { Bad_Opcode },
13701     { "fst",    { STi }, 0 },
13702     { "fstp",   { STi }, 0 },
13703     { "fucom",  { STi }, 0 },
13704     { "fucomp", { STi }, 0 },
13705     { Bad_Opcode },
13706     { Bad_Opcode },
13707   },
13708   /* de */
13709   {
13710     { "faddp",  { STi, ST }, 0 },
13711     { "fmulp",  { STi, ST }, 0 },
13712     { Bad_Opcode },
13713     { FGRPde_3 },
13714     { "fsub!Mp", { STi, ST }, 0 },
13715     { "fsubMp", { STi, ST }, 0 },
13716     { "fdiv!Mp", { STi, ST }, 0 },
13717     { "fdivMp", { STi, ST }, 0 },
13718   },
13719   /* df */
13720   {
13721     { "ffreep", { STi }, 0 },
13722     { Bad_Opcode },
13723     { Bad_Opcode },
13724     { Bad_Opcode },
13725     { FGRPdf_4 },
13726     { "fucomip", { ST, STi }, 0 },
13727     { "fcomip", { ST, STi }, 0 },
13728     { Bad_Opcode },
13729   },
13730 };
13731
13732 static char *fgrps[][8] = {
13733   /* Bad opcode 0 */
13734   {
13735     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13736   },
13737
13738   /* d9_2  1 */
13739   {
13740     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13741   },
13742
13743   /* d9_4  2 */
13744   {
13745     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13746   },
13747
13748   /* d9_5  3 */
13749   {
13750     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13751   },
13752
13753   /* d9_6  4 */
13754   {
13755     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13756   },
13757
13758   /* d9_7  5 */
13759   {
13760     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13761   },
13762
13763   /* da_5  6 */
13764   {
13765     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13766   },
13767
13768   /* db_4  7 */
13769   {
13770     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13771     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13772   },
13773
13774   /* de_3  8 */
13775   {
13776     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13777   },
13778
13779   /* df_4  9 */
13780   {
13781     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13782   },
13783 };
13784
13785 static void
13786 swap_operand (void)
13787 {
13788   mnemonicendp[0] = '.';
13789   mnemonicendp[1] = 's';
13790   mnemonicendp += 2;
13791 }
13792
13793 static void
13794 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13795                int sizeflag ATTRIBUTE_UNUSED)
13796 {
13797   /* Skip mod/rm byte.  */
13798   MODRM_CHECK;
13799   codep++;
13800 }
13801
13802 static void
13803 dofloat (int sizeflag)
13804 {
13805   const struct dis386 *dp;
13806   unsigned char floatop;
13807
13808   floatop = codep[-1];
13809
13810   if (modrm.mod != 3)
13811     {
13812       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13813
13814       putop (float_mem[fp_indx], sizeflag);
13815       obufp = op_out[0];
13816       op_ad = 2;
13817       OP_E (float_mem_mode[fp_indx], sizeflag);
13818       return;
13819     }
13820   /* Skip mod/rm byte.  */
13821   MODRM_CHECK;
13822   codep++;
13823
13824   dp = &float_reg[floatop - 0xd8][modrm.reg];
13825   if (dp->name == NULL)
13826     {
13827       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13828
13829       /* Instruction fnstsw is only one with strange arg.  */
13830       if (floatop == 0xdf && codep[-1] == 0xe0)
13831         strcpy (op_out[0], names16[0]);
13832     }
13833   else
13834     {
13835       putop (dp->name, sizeflag);
13836
13837       obufp = op_out[0];
13838       op_ad = 2;
13839       if (dp->op[0].rtn)
13840         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13841
13842       obufp = op_out[1];
13843       op_ad = 1;
13844       if (dp->op[1].rtn)
13845         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13846     }
13847 }
13848
13849 /* Like oappend (below), but S is a string starting with '%'.
13850    In Intel syntax, the '%' is elided.  */
13851 static void
13852 oappend_maybe_intel (const char *s)
13853 {
13854   oappend (s + intel_syntax);
13855 }
13856
13857 static void
13858 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13859 {
13860   oappend_maybe_intel ("%st");
13861 }
13862
13863 static void
13864 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13865 {
13866   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13867   oappend_maybe_intel (scratchbuf);
13868 }
13869
13870 /* Capital letters in template are macros.  */
13871 static int
13872 putop (const char *in_template, int sizeflag)
13873 {
13874   const char *p;
13875   int alt = 0;
13876   int cond = 1;
13877   unsigned int l = 0, len = 1;
13878   char last[4];
13879
13880 #define SAVE_LAST(c)                    \
13881   if (l < len && l < sizeof (last))     \
13882     last[l++] = c;                      \
13883   else                                  \
13884     abort ();
13885
13886   for (p = in_template; *p; p++)
13887     {
13888       switch (*p)
13889         {
13890         default:
13891           *obufp++ = *p;
13892           break;
13893         case '%':
13894           len++;
13895           break;
13896         case '!':
13897           cond = 0;
13898           break;
13899         case '{':
13900           if (intel_syntax)
13901             {
13902               while (*++p != '|')
13903                 if (*p == '}' || *p == '\0')
13904                   abort ();
13905             }
13906           /* Fall through.  */
13907         case 'I':
13908           alt = 1;
13909           continue;
13910         case '|':
13911           while (*++p != '}')
13912             {
13913               if (*p == '\0')
13914                 abort ();
13915             }
13916           break;
13917         case '}':
13918           break;
13919         case 'A':
13920           if (intel_syntax)
13921             break;
13922           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13923             *obufp++ = 'b';
13924           break;
13925         case 'B':
13926           if (l == 0 && len == 1)
13927             {
13928 case_B:
13929               if (intel_syntax)
13930                 break;
13931               if (sizeflag & SUFFIX_ALWAYS)
13932                 *obufp++ = 'b';
13933             }
13934           else
13935             {
13936               if (l != 1
13937                   || len != 2
13938                   || last[0] != 'L')
13939                 {
13940                   SAVE_LAST (*p);
13941                   break;
13942                 }
13943
13944               if (address_mode == mode_64bit
13945                   && !(prefixes & PREFIX_ADDR))
13946                 {
13947                   *obufp++ = 'a';
13948                   *obufp++ = 'b';
13949                   *obufp++ = 's';
13950                 }
13951
13952               goto case_B;
13953             }
13954           break;
13955         case 'C':
13956           if (intel_syntax && !alt)
13957             break;
13958           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13959             {
13960               if (sizeflag & DFLAG)
13961                 *obufp++ = intel_syntax ? 'd' : 'l';
13962               else
13963                 *obufp++ = intel_syntax ? 'w' : 's';
13964               used_prefixes |= (prefixes & PREFIX_DATA);
13965             }
13966           break;
13967         case 'D':
13968           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13969             break;
13970           USED_REX (REX_W);
13971           if (modrm.mod == 3)
13972             {
13973               if (rex & REX_W)
13974                 *obufp++ = 'q';
13975               else
13976                 {
13977                   if (sizeflag & DFLAG)
13978                     *obufp++ = intel_syntax ? 'd' : 'l';
13979                   else
13980                     *obufp++ = 'w';
13981                   used_prefixes |= (prefixes & PREFIX_DATA);
13982                 }
13983             }
13984           else
13985             *obufp++ = 'w';
13986           break;
13987         case 'E':               /* For jcxz/jecxz */
13988           if (address_mode == mode_64bit)
13989             {
13990               if (sizeflag & AFLAG)
13991                 *obufp++ = 'r';
13992               else
13993                 *obufp++ = 'e';
13994             }
13995           else
13996             if (sizeflag & AFLAG)
13997               *obufp++ = 'e';
13998           used_prefixes |= (prefixes & PREFIX_ADDR);
13999           break;
14000         case 'F':
14001           if (intel_syntax)
14002             break;
14003           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14004             {
14005               if (sizeflag & AFLAG)
14006                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14007               else
14008                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14009               used_prefixes |= (prefixes & PREFIX_ADDR);
14010             }
14011           break;
14012         case 'G':
14013           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14014             break;
14015           if ((rex & REX_W) || (sizeflag & DFLAG))
14016             *obufp++ = 'l';
14017           else
14018             *obufp++ = 'w';
14019           if (!(rex & REX_W))
14020             used_prefixes |= (prefixes & PREFIX_DATA);
14021           break;
14022         case 'H':
14023           if (intel_syntax)
14024             break;
14025           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14026               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14027             {
14028               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14029               *obufp++ = ',';
14030               *obufp++ = 'p';
14031               if (prefixes & PREFIX_DS)
14032                 *obufp++ = 't';
14033               else
14034                 *obufp++ = 'n';
14035             }
14036           break;
14037         case 'J':
14038           if (intel_syntax)
14039             break;
14040           *obufp++ = 'l';
14041           break;
14042         case 'K':
14043           USED_REX (REX_W);
14044           if (rex & REX_W)
14045             *obufp++ = 'q';
14046           else
14047             *obufp++ = 'd';
14048           break;
14049         case 'Z':
14050           if (l != 0 || len != 1)
14051             {
14052               if (l != 1 || len != 2 || last[0] != 'X')
14053                 {
14054                   SAVE_LAST (*p);
14055                   break;
14056                 }
14057               if (!need_vex || !vex.evex)
14058                 abort ();
14059               if (intel_syntax
14060                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14061                 break;
14062               switch (vex.length)
14063                 {
14064                 case 128:
14065                   *obufp++ = 'x';
14066                   break;
14067                 case 256:
14068                   *obufp++ = 'y';
14069                   break;
14070                 case 512:
14071                   *obufp++ = 'z';
14072                   break;
14073                 default:
14074                   abort ();
14075                 }
14076               break;
14077             }
14078           if (intel_syntax)
14079             break;
14080           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14081             {
14082               *obufp++ = 'q';
14083               break;
14084             }
14085           /* Fall through.  */
14086           goto case_L;
14087         case 'L':
14088           if (l != 0 || len != 1)
14089             {
14090               SAVE_LAST (*p);
14091               break;
14092             }
14093 case_L:
14094           if (intel_syntax)
14095             break;
14096           if (sizeflag & SUFFIX_ALWAYS)
14097             *obufp++ = 'l';
14098           break;
14099         case 'M':
14100           if (intel_mnemonic != cond)
14101             *obufp++ = 'r';
14102           break;
14103         case 'N':
14104           if ((prefixes & PREFIX_FWAIT) == 0)
14105             *obufp++ = 'n';
14106           else
14107             used_prefixes |= PREFIX_FWAIT;
14108           break;
14109         case 'O':
14110           USED_REX (REX_W);
14111           if (rex & REX_W)
14112             *obufp++ = 'o';
14113           else if (intel_syntax && (sizeflag & DFLAG))
14114             *obufp++ = 'q';
14115           else
14116             *obufp++ = 'd';
14117           if (!(rex & REX_W))
14118             used_prefixes |= (prefixes & PREFIX_DATA);
14119           break;
14120         case '&':
14121           if (!intel_syntax
14122               && address_mode == mode_64bit
14123               && isa64 == intel64)
14124             {
14125               *obufp++ = 'q';
14126               break;
14127             }
14128           /* Fall through.  */
14129         case 'T':
14130           if (!intel_syntax
14131               && address_mode == mode_64bit
14132               && ((sizeflag & DFLAG) || (rex & REX_W)))
14133             {
14134               *obufp++ = 'q';
14135               break;
14136             }
14137           /* Fall through.  */
14138           goto case_P;
14139         case 'P':
14140           if (l == 0 && len == 1)
14141             {
14142 case_P:
14143               if (intel_syntax)
14144                 {
14145                   if ((rex & REX_W) == 0
14146                       && (prefixes & PREFIX_DATA))
14147                     {
14148                       if ((sizeflag & DFLAG) == 0)
14149                         *obufp++ = 'w';
14150                       used_prefixes |= (prefixes & PREFIX_DATA);
14151                     }
14152                   break;
14153                 }
14154               if ((prefixes & PREFIX_DATA)
14155                   || (rex & REX_W)
14156                   || (sizeflag & SUFFIX_ALWAYS))
14157                 {
14158                   USED_REX (REX_W);
14159                   if (rex & REX_W)
14160                     *obufp++ = 'q';
14161                   else
14162                     {
14163                       if (sizeflag & DFLAG)
14164                         *obufp++ = 'l';
14165                       else
14166                         *obufp++ = 'w';
14167                       used_prefixes |= (prefixes & PREFIX_DATA);
14168                     }
14169                 }
14170             }
14171           else
14172             {
14173               if (l != 1 || len != 2 || last[0] != 'L')
14174                 {
14175                   SAVE_LAST (*p);
14176                   break;
14177                 }
14178
14179               if ((prefixes & PREFIX_DATA)
14180                   || (rex & REX_W)
14181                   || (sizeflag & SUFFIX_ALWAYS))
14182                 {
14183                   USED_REX (REX_W);
14184                   if (rex & REX_W)
14185                     *obufp++ = 'q';
14186                   else
14187                     {
14188                       if (sizeflag & DFLAG)
14189                         *obufp++ = intel_syntax ? 'd' : 'l';
14190                       else
14191                         *obufp++ = 'w';
14192                       used_prefixes |= (prefixes & PREFIX_DATA);
14193                     }
14194                 }
14195             }
14196           break;
14197         case 'U':
14198           if (intel_syntax)
14199             break;
14200           if (address_mode == mode_64bit
14201               && ((sizeflag & DFLAG) || (rex & REX_W)))
14202             {
14203               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14204                 *obufp++ = 'q';
14205               break;
14206             }
14207           /* Fall through.  */
14208           goto case_Q;
14209         case 'Q':
14210           if (l == 0 && len == 1)
14211             {
14212 case_Q:
14213               if (intel_syntax && !alt)
14214                 break;
14215               USED_REX (REX_W);
14216               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14217                 {
14218                   if (rex & REX_W)
14219                     *obufp++ = 'q';
14220                   else
14221                     {
14222                       if (sizeflag & DFLAG)
14223                         *obufp++ = intel_syntax ? 'd' : 'l';
14224                       else
14225                         *obufp++ = 'w';
14226                       used_prefixes |= (prefixes & PREFIX_DATA);
14227                     }
14228                 }
14229             }
14230           else
14231             {
14232               if (l != 1 || len != 2 || last[0] != 'L')
14233                 {
14234                   SAVE_LAST (*p);
14235                   break;
14236                 }
14237               if (intel_syntax
14238                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14239                 break;
14240               if ((rex & REX_W))
14241                 {
14242                   USED_REX (REX_W);
14243                   *obufp++ = 'q';
14244                 }
14245               else
14246                 *obufp++ = 'l';
14247             }
14248           break;
14249         case 'R':
14250           USED_REX (REX_W);
14251           if (rex & REX_W)
14252             *obufp++ = 'q';
14253           else if (sizeflag & DFLAG)
14254             {
14255               if (intel_syntax)
14256                   *obufp++ = 'd';
14257               else
14258                   *obufp++ = 'l';
14259             }
14260           else
14261             *obufp++ = 'w';
14262           if (intel_syntax && !p[1]
14263               && ((rex & REX_W) || (sizeflag & DFLAG)))
14264             *obufp++ = 'e';
14265           if (!(rex & REX_W))
14266             used_prefixes |= (prefixes & PREFIX_DATA);
14267           break;
14268         case 'V':
14269           if (l == 0 && len == 1)
14270             {
14271               if (intel_syntax)
14272                 break;
14273               if (address_mode == mode_64bit
14274                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14275                 {
14276                   if (sizeflag & SUFFIX_ALWAYS)
14277                     *obufp++ = 'q';
14278                   break;
14279                 }
14280             }
14281           else
14282             {
14283               if (l != 1
14284                   || len != 2
14285                   || last[0] != 'L')
14286                 {
14287                   SAVE_LAST (*p);
14288                   break;
14289                 }
14290
14291               if (rex & REX_W)
14292                 {
14293                   *obufp++ = 'a';
14294                   *obufp++ = 'b';
14295                   *obufp++ = 's';
14296                 }
14297             }
14298           /* Fall through.  */
14299           goto case_S;
14300         case 'S':
14301           if (l == 0 && len == 1)
14302             {
14303 case_S:
14304               if (intel_syntax)
14305                 break;
14306               if (sizeflag & SUFFIX_ALWAYS)
14307                 {
14308                   if (rex & REX_W)
14309                     *obufp++ = 'q';
14310                   else
14311                     {
14312                       if (sizeflag & DFLAG)
14313                         *obufp++ = 'l';
14314                       else
14315                         *obufp++ = 'w';
14316                       used_prefixes |= (prefixes & PREFIX_DATA);
14317                     }
14318                 }
14319             }
14320           else
14321             {
14322               if (l != 1
14323                   || len != 2
14324                   || last[0] != 'L')
14325                 {
14326                   SAVE_LAST (*p);
14327                   break;
14328                 }
14329
14330               if (address_mode == mode_64bit
14331                   && !(prefixes & PREFIX_ADDR))
14332                 {
14333                   *obufp++ = 'a';
14334                   *obufp++ = 'b';
14335                   *obufp++ = 's';
14336                 }
14337
14338               goto case_S;
14339             }
14340           break;
14341         case 'X':
14342           if (l != 0 || len != 1)
14343             {
14344               SAVE_LAST (*p);
14345               break;
14346             }
14347           if (need_vex && vex.prefix)
14348             {
14349               if (vex.prefix == DATA_PREFIX_OPCODE)
14350                 *obufp++ = 'd';
14351               else
14352                 *obufp++ = 's';
14353             }
14354           else
14355             {
14356               if (prefixes & PREFIX_DATA)
14357                 *obufp++ = 'd';
14358               else
14359                 *obufp++ = 's';
14360               used_prefixes |= (prefixes & PREFIX_DATA);
14361             }
14362           break;
14363         case 'Y':
14364           if (l == 0 && len == 1)
14365             {
14366               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14367                 break;
14368               if (rex & REX_W)
14369                 {
14370                   USED_REX (REX_W);
14371                   *obufp++ = 'q';
14372                 }
14373               break;
14374             }
14375           else
14376             {
14377               if (l != 1 || len != 2 || last[0] != 'X')
14378                 {
14379                   SAVE_LAST (*p);
14380                   break;
14381                 }
14382               if (!need_vex)
14383                 abort ();
14384               if (intel_syntax
14385                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14386                 break;
14387               switch (vex.length)
14388                 {
14389                 case 128:
14390                   *obufp++ = 'x';
14391                   break;
14392                 case 256:
14393                   *obufp++ = 'y';
14394                   break;
14395                 case 512:
14396                   if (!vex.evex)
14397                 default:
14398                     abort ();
14399                 }
14400             }
14401           break;
14402         case 'W':
14403           if (l == 0 && len == 1)
14404             {
14405               /* operand size flag for cwtl, cbtw */
14406               USED_REX (REX_W);
14407               if (rex & REX_W)
14408                 {
14409                   if (intel_syntax)
14410                     *obufp++ = 'd';
14411                   else
14412                     *obufp++ = 'l';
14413                 }
14414               else if (sizeflag & DFLAG)
14415                 *obufp++ = 'w';
14416               else
14417                 *obufp++ = 'b';
14418               if (!(rex & REX_W))
14419                 used_prefixes |= (prefixes & PREFIX_DATA);
14420             }
14421           else
14422             {
14423               if (l != 1
14424                   || len != 2
14425                   || (last[0] != 'X'
14426                       && last[0] != 'L'))
14427                 {
14428                   SAVE_LAST (*p);
14429                   break;
14430                 }
14431               if (!need_vex)
14432                 abort ();
14433               if (last[0] == 'X')
14434                 *obufp++ = vex.w ? 'd': 's';
14435               else
14436                 *obufp++ = vex.w ? 'q': 'd';
14437             }
14438           break;
14439         case '^':
14440           if (intel_syntax)
14441             break;
14442           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14443             {
14444               if (sizeflag & DFLAG)
14445                 *obufp++ = 'l';
14446               else
14447                 *obufp++ = 'w';
14448               used_prefixes |= (prefixes & PREFIX_DATA);
14449             }
14450           break;
14451         case '@':
14452           if (intel_syntax)
14453             break;
14454           if (address_mode == mode_64bit
14455               && (isa64 == intel64
14456                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14457               *obufp++ = 'q';
14458           else if ((prefixes & PREFIX_DATA))
14459             {
14460               if (!(sizeflag & DFLAG))
14461                 *obufp++ = 'w';
14462               used_prefixes |= (prefixes & PREFIX_DATA);
14463             }
14464           break;
14465         }
14466       alt = 0;
14467     }
14468   *obufp = 0;
14469   mnemonicendp = obufp;
14470   return 0;
14471 }
14472
14473 static void
14474 oappend (const char *s)
14475 {
14476   obufp = stpcpy (obufp, s);
14477 }
14478
14479 static void
14480 append_seg (void)
14481 {
14482   /* Only print the active segment register.  */
14483   if (!active_seg_prefix)
14484     return;
14485
14486   used_prefixes |= active_seg_prefix;
14487   switch (active_seg_prefix)
14488     {
14489     case PREFIX_CS:
14490       oappend_maybe_intel ("%cs:");
14491       break;
14492     case PREFIX_DS:
14493       oappend_maybe_intel ("%ds:");
14494       break;
14495     case PREFIX_SS:
14496       oappend_maybe_intel ("%ss:");
14497       break;
14498     case PREFIX_ES:
14499       oappend_maybe_intel ("%es:");
14500       break;
14501     case PREFIX_FS:
14502       oappend_maybe_intel ("%fs:");
14503       break;
14504     case PREFIX_GS:
14505       oappend_maybe_intel ("%gs:");
14506       break;
14507     default:
14508       break;
14509     }
14510 }
14511
14512 static void
14513 OP_indirE (int bytemode, int sizeflag)
14514 {
14515   if (!intel_syntax)
14516     oappend ("*");
14517   OP_E (bytemode, sizeflag);
14518 }
14519
14520 static void
14521 print_operand_value (char *buf, int hex, bfd_vma disp)
14522 {
14523   if (address_mode == mode_64bit)
14524     {
14525       if (hex)
14526         {
14527           char tmp[30];
14528           int i;
14529           buf[0] = '0';
14530           buf[1] = 'x';
14531           sprintf_vma (tmp, disp);
14532           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14533           strcpy (buf + 2, tmp + i);
14534         }
14535       else
14536         {
14537           bfd_signed_vma v = disp;
14538           char tmp[30];
14539           int i;
14540           if (v < 0)
14541             {
14542               *(buf++) = '-';
14543               v = -disp;
14544               /* Check for possible overflow on 0x8000000000000000.  */
14545               if (v < 0)
14546                 {
14547                   strcpy (buf, "9223372036854775808");
14548                   return;
14549                 }
14550             }
14551           if (!v)
14552             {
14553               strcpy (buf, "0");
14554               return;
14555             }
14556
14557           i = 0;
14558           tmp[29] = 0;
14559           while (v)
14560             {
14561               tmp[28 - i] = (v % 10) + '0';
14562               v /= 10;
14563               i++;
14564             }
14565           strcpy (buf, tmp + 29 - i);
14566         }
14567     }
14568   else
14569     {
14570       if (hex)
14571         sprintf (buf, "0x%x", (unsigned int) disp);
14572       else
14573         sprintf (buf, "%d", (int) disp);
14574     }
14575 }
14576
14577 /* Put DISP in BUF as signed hex number.  */
14578
14579 static void
14580 print_displacement (char *buf, bfd_vma disp)
14581 {
14582   bfd_signed_vma val = disp;
14583   char tmp[30];
14584   int i, j = 0;
14585
14586   if (val < 0)
14587     {
14588       buf[j++] = '-';
14589       val = -disp;
14590
14591       /* Check for possible overflow.  */
14592       if (val < 0)
14593         {
14594           switch (address_mode)
14595             {
14596             case mode_64bit:
14597               strcpy (buf + j, "0x8000000000000000");
14598               break;
14599             case mode_32bit:
14600               strcpy (buf + j, "0x80000000");
14601               break;
14602             case mode_16bit:
14603               strcpy (buf + j, "0x8000");
14604               break;
14605             }
14606           return;
14607         }
14608     }
14609
14610   buf[j++] = '0';
14611   buf[j++] = 'x';
14612
14613   sprintf_vma (tmp, (bfd_vma) val);
14614   for (i = 0; tmp[i] == '0'; i++)
14615     continue;
14616   if (tmp[i] == '\0')
14617     i--;
14618   strcpy (buf + j, tmp + i);
14619 }
14620
14621 static void
14622 intel_operand_size (int bytemode, int sizeflag)
14623 {
14624   if (vex.evex
14625       && vex.b
14626       && (bytemode == x_mode
14627           || bytemode == evex_half_bcst_xmmq_mode))
14628     {
14629       if (vex.w)
14630         oappend ("QWORD PTR ");
14631       else
14632         oappend ("DWORD PTR ");
14633       return;
14634     }
14635   switch (bytemode)
14636     {
14637     case b_mode:
14638     case b_swap_mode:
14639     case dqb_mode:
14640     case db_mode:
14641       oappend ("BYTE PTR ");
14642       break;
14643     case w_mode:
14644     case dw_mode:
14645     case dqw_mode:
14646       oappend ("WORD PTR ");
14647       break;
14648     case indir_v_mode:
14649       if (address_mode == mode_64bit && isa64 == intel64)
14650         {
14651           oappend ("QWORD PTR ");
14652           break;
14653         }
14654       /* Fall through.  */
14655     case stack_v_mode:
14656       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14657         {
14658           oappend ("QWORD PTR ");
14659           break;
14660         }
14661       /* Fall through.  */
14662     case v_mode:
14663     case v_swap_mode:
14664     case dq_mode:
14665       USED_REX (REX_W);
14666       if (rex & REX_W)
14667         oappend ("QWORD PTR ");
14668       else
14669         {
14670           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14671             oappend ("DWORD PTR ");
14672           else
14673             oappend ("WORD PTR ");
14674           used_prefixes |= (prefixes & PREFIX_DATA);
14675         }
14676       break;
14677     case z_mode:
14678       if ((rex & REX_W) || (sizeflag & DFLAG))
14679         *obufp++ = 'D';
14680       oappend ("WORD PTR ");
14681       if (!(rex & REX_W))
14682         used_prefixes |= (prefixes & PREFIX_DATA);
14683       break;
14684     case a_mode:
14685       if (sizeflag & DFLAG)
14686         oappend ("QWORD PTR ");
14687       else
14688         oappend ("DWORD PTR ");
14689       used_prefixes |= (prefixes & PREFIX_DATA);
14690       break;
14691     case d_mode:
14692     case d_scalar_mode:
14693     case d_scalar_swap_mode:
14694     case d_swap_mode:
14695     case dqd_mode:
14696       oappend ("DWORD PTR ");
14697       break;
14698     case q_mode:
14699     case q_scalar_mode:
14700     case q_scalar_swap_mode:
14701     case q_swap_mode:
14702       oappend ("QWORD PTR ");
14703       break;
14704     case m_mode:
14705       if (address_mode == mode_64bit)
14706         oappend ("QWORD PTR ");
14707       else
14708         oappend ("DWORD PTR ");
14709       break;
14710     case f_mode:
14711       if (sizeflag & DFLAG)
14712         oappend ("FWORD PTR ");
14713       else
14714         oappend ("DWORD PTR ");
14715       used_prefixes |= (prefixes & PREFIX_DATA);
14716       break;
14717     case t_mode:
14718       oappend ("TBYTE PTR ");
14719       break;
14720     case x_mode:
14721     case x_swap_mode:
14722     case evex_x_gscat_mode:
14723     case evex_x_nobcst_mode:
14724       if (need_vex)
14725         {
14726           switch (vex.length)
14727             {
14728             case 128:
14729               oappend ("XMMWORD PTR ");
14730               break;
14731             case 256:
14732               oappend ("YMMWORD PTR ");
14733               break;
14734             case 512:
14735               oappend ("ZMMWORD PTR ");
14736               break;
14737             default:
14738               abort ();
14739             }
14740         }
14741       else
14742         oappend ("XMMWORD PTR ");
14743       break;
14744     case xmm_mode:
14745       oappend ("XMMWORD PTR ");
14746       break;
14747     case ymm_mode:
14748       oappend ("YMMWORD PTR ");
14749       break;
14750     case xmmq_mode:
14751     case evex_half_bcst_xmmq_mode:
14752       if (!need_vex)
14753         abort ();
14754
14755       switch (vex.length)
14756         {
14757         case 128:
14758           oappend ("QWORD PTR ");
14759           break;
14760         case 256:
14761           oappend ("XMMWORD PTR ");
14762           break;
14763         case 512:
14764           oappend ("YMMWORD PTR ");
14765           break;
14766         default:
14767           abort ();
14768         }
14769       break;
14770     case xmm_mb_mode:
14771       if (!need_vex)
14772         abort ();
14773
14774       switch (vex.length)
14775         {
14776         case 128:
14777         case 256:
14778         case 512:
14779           oappend ("BYTE PTR ");
14780           break;
14781         default:
14782           abort ();
14783         }
14784       break;
14785     case xmm_mw_mode:
14786       if (!need_vex)
14787         abort ();
14788
14789       switch (vex.length)
14790         {
14791         case 128:
14792         case 256:
14793         case 512:
14794           oappend ("WORD PTR ");
14795           break;
14796         default:
14797           abort ();
14798         }
14799       break;
14800     case xmm_md_mode:
14801       if (!need_vex)
14802         abort ();
14803
14804       switch (vex.length)
14805         {
14806         case 128:
14807         case 256:
14808         case 512:
14809           oappend ("DWORD PTR ");
14810           break;
14811         default:
14812           abort ();
14813         }
14814       break;
14815     case xmm_mq_mode:
14816       if (!need_vex)
14817         abort ();
14818
14819       switch (vex.length)
14820         {
14821         case 128:
14822         case 256:
14823         case 512:
14824           oappend ("QWORD PTR ");
14825           break;
14826         default:
14827           abort ();
14828         }
14829       break;
14830     case xmmdw_mode:
14831       if (!need_vex)
14832         abort ();
14833
14834       switch (vex.length)
14835         {
14836         case 128:
14837           oappend ("WORD PTR ");
14838           break;
14839         case 256:
14840           oappend ("DWORD PTR ");
14841           break;
14842         case 512:
14843           oappend ("QWORD PTR ");
14844           break;
14845         default:
14846           abort ();
14847         }
14848       break;
14849     case xmmqd_mode:
14850       if (!need_vex)
14851         abort ();
14852
14853       switch (vex.length)
14854         {
14855         case 128:
14856           oappend ("DWORD PTR ");
14857           break;
14858         case 256:
14859           oappend ("QWORD PTR ");
14860           break;
14861         case 512:
14862           oappend ("XMMWORD PTR ");
14863           break;
14864         default:
14865           abort ();
14866         }
14867       break;
14868     case ymmq_mode:
14869       if (!need_vex)
14870         abort ();
14871
14872       switch (vex.length)
14873         {
14874         case 128:
14875           oappend ("QWORD PTR ");
14876           break;
14877         case 256:
14878           oappend ("YMMWORD PTR ");
14879           break;
14880         case 512:
14881           oappend ("ZMMWORD PTR ");
14882           break;
14883         default:
14884           abort ();
14885         }
14886       break;
14887     case ymmxmm_mode:
14888       if (!need_vex)
14889         abort ();
14890
14891       switch (vex.length)
14892         {
14893         case 128:
14894         case 256:
14895           oappend ("XMMWORD PTR ");
14896           break;
14897         default:
14898           abort ();
14899         }
14900       break;
14901     case o_mode:
14902       oappend ("OWORD PTR ");
14903       break;
14904     case xmm_mdq_mode:
14905     case vex_w_dq_mode:
14906     case vex_scalar_w_dq_mode:
14907       if (!need_vex)
14908         abort ();
14909
14910       if (vex.w)
14911         oappend ("QWORD PTR ");
14912       else
14913         oappend ("DWORD PTR ");
14914       break;
14915     case vex_vsib_d_w_dq_mode:
14916     case vex_vsib_q_w_dq_mode:
14917       if (!need_vex)
14918         abort ();
14919
14920       if (!vex.evex)
14921         {
14922           if (vex.w)
14923             oappend ("QWORD PTR ");
14924           else
14925             oappend ("DWORD PTR ");
14926         }
14927       else
14928         {
14929           switch (vex.length)
14930             {
14931             case 128:
14932               oappend ("XMMWORD PTR ");
14933               break;
14934             case 256:
14935               oappend ("YMMWORD PTR ");
14936               break;
14937             case 512:
14938               oappend ("ZMMWORD PTR ");
14939               break;
14940             default:
14941               abort ();
14942             }
14943         }
14944       break;
14945     case vex_vsib_q_w_d_mode:
14946     case vex_vsib_d_w_d_mode:
14947       if (!need_vex || !vex.evex)
14948         abort ();
14949
14950       switch (vex.length)
14951         {
14952         case 128:
14953           oappend ("QWORD PTR ");
14954           break;
14955         case 256:
14956           oappend ("XMMWORD PTR ");
14957           break;
14958         case 512:
14959           oappend ("YMMWORD PTR ");
14960           break;
14961         default:
14962           abort ();
14963         }
14964
14965       break;
14966     case mask_bd_mode:
14967       if (!need_vex || vex.length != 128)
14968         abort ();
14969       if (vex.w)
14970         oappend ("DWORD PTR ");
14971       else
14972         oappend ("BYTE PTR ");
14973       break;
14974     case mask_mode:
14975       if (!need_vex)
14976         abort ();
14977       if (vex.w)
14978         oappend ("QWORD PTR ");
14979       else
14980         oappend ("WORD PTR ");
14981       break;
14982     case v_bnd_mode:
14983     default:
14984       break;
14985     }
14986 }
14987
14988 static void
14989 OP_E_register (int bytemode, int sizeflag)
14990 {
14991   int reg = modrm.rm;
14992   const char **names;
14993
14994   USED_REX (REX_B);
14995   if ((rex & REX_B))
14996     reg += 8;
14997
14998   if ((sizeflag & SUFFIX_ALWAYS)
14999       && (bytemode == b_swap_mode
15000           || bytemode == v_swap_mode))
15001     swap_operand ();
15002
15003   switch (bytemode)
15004     {
15005     case b_mode:
15006     case b_swap_mode:
15007       USED_REX (0);
15008       if (rex)
15009         names = names8rex;
15010       else
15011         names = names8;
15012       break;
15013     case w_mode:
15014       names = names16;
15015       break;
15016     case d_mode:
15017     case dw_mode:
15018     case db_mode:
15019       names = names32;
15020       break;
15021     case q_mode:
15022       names = names64;
15023       break;
15024     case m_mode:
15025     case v_bnd_mode:
15026       names = address_mode == mode_64bit ? names64 : names32;
15027       break;
15028     case bnd_mode:
15029       if (reg > 0x3)
15030         {
15031           oappend ("(bad)");
15032           return;
15033         }
15034       names = names_bnd;
15035       break;
15036     case indir_v_mode:
15037       if (address_mode == mode_64bit && isa64 == intel64)
15038         {
15039           names = names64;
15040           break;
15041         }
15042       /* Fall through.  */
15043     case stack_v_mode:
15044       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15045         {
15046           names = names64;
15047           break;
15048         }
15049       bytemode = v_mode;
15050       /* Fall through.  */
15051     case v_mode:
15052     case v_swap_mode:
15053     case dq_mode:
15054     case dqb_mode:
15055     case dqd_mode:
15056     case dqw_mode:
15057       USED_REX (REX_W);
15058       if (rex & REX_W)
15059         names = names64;
15060       else
15061         {
15062           if ((sizeflag & DFLAG)
15063               || (bytemode != v_mode
15064                   && bytemode != v_swap_mode))
15065             names = names32;
15066           else
15067             names = names16;
15068           used_prefixes |= (prefixes & PREFIX_DATA);
15069         }
15070       break;
15071     case mask_bd_mode:
15072     case mask_mode:
15073       if (reg > 0x7)
15074         {
15075           oappend ("(bad)");
15076           return;
15077         }
15078       names = names_mask;
15079       break;
15080     case 0:
15081       return;
15082     default:
15083       oappend (INTERNAL_DISASSEMBLER_ERROR);
15084       return;
15085     }
15086   oappend (names[reg]);
15087 }
15088
15089 static void
15090 OP_E_memory (int bytemode, int sizeflag)
15091 {
15092   bfd_vma disp = 0;
15093   int add = (rex & REX_B) ? 8 : 0;
15094   int riprel = 0;
15095   int shift;
15096
15097   if (vex.evex)
15098     {
15099       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15100       if (vex.b
15101           && bytemode != x_mode
15102           && bytemode != xmmq_mode
15103           && bytemode != evex_half_bcst_xmmq_mode)
15104         {
15105           BadOp ();
15106           return;
15107         }
15108       switch (bytemode)
15109         {
15110         case dqw_mode:
15111         case dw_mode:
15112           shift = 1;
15113           break;
15114         case dqb_mode:
15115         case db_mode:
15116           shift = 0;
15117           break;
15118         case vex_vsib_d_w_dq_mode:
15119         case vex_vsib_d_w_d_mode:
15120         case vex_vsib_q_w_dq_mode:
15121         case vex_vsib_q_w_d_mode:
15122         case evex_x_gscat_mode:
15123         case xmm_mdq_mode:
15124           shift = vex.w ? 3 : 2;
15125           break;
15126         case x_mode:
15127         case evex_half_bcst_xmmq_mode:
15128         case xmmq_mode:
15129           if (vex.b)
15130             {
15131               shift = vex.w ? 3 : 2;
15132               break;
15133             }
15134           /* Fall through.  */
15135         case xmmqd_mode:
15136         case xmmdw_mode:
15137         case ymmq_mode:
15138         case evex_x_nobcst_mode:
15139         case x_swap_mode:
15140           switch (vex.length)
15141             {
15142             case 128:
15143               shift = 4;
15144               break;
15145             case 256:
15146               shift = 5;
15147               break;
15148             case 512:
15149               shift = 6;
15150               break;
15151             default:
15152               abort ();
15153             }
15154           break;
15155         case ymm_mode:
15156           shift = 5;
15157           break;
15158         case xmm_mode:
15159           shift = 4;
15160           break;
15161         case xmm_mq_mode:
15162         case q_mode:
15163         case q_scalar_mode:
15164         case q_swap_mode:
15165         case q_scalar_swap_mode:
15166           shift = 3;
15167           break;
15168         case dqd_mode:
15169         case xmm_md_mode:
15170         case d_mode:
15171         case d_scalar_mode:
15172         case d_swap_mode:
15173         case d_scalar_swap_mode:
15174           shift = 2;
15175           break;
15176         case xmm_mw_mode:
15177           shift = 1;
15178           break;
15179         case xmm_mb_mode:
15180           shift = 0;
15181           break;
15182         default:
15183           abort ();
15184         }
15185       /* Make necessary corrections to shift for modes that need it.
15186          For these modes we currently have shift 4, 5 or 6 depending on
15187          vex.length (it corresponds to xmmword, ymmword or zmmword
15188          operand).  We might want to make it 3, 4 or 5 (e.g. for
15189          xmmq_mode).  In case of broadcast enabled the corrections
15190          aren't needed, as element size is always 32 or 64 bits.  */
15191       if (!vex.b
15192           && (bytemode == xmmq_mode
15193               || bytemode == evex_half_bcst_xmmq_mode))
15194         shift -= 1;
15195       else if (bytemode == xmmqd_mode)
15196         shift -= 2;
15197       else if (bytemode == xmmdw_mode)
15198         shift -= 3;
15199       else if (bytemode == ymmq_mode && vex.length == 128)
15200         shift -= 1;
15201     }
15202   else
15203     shift = 0;
15204
15205   USED_REX (REX_B);
15206   if (intel_syntax)
15207     intel_operand_size (bytemode, sizeflag);
15208   append_seg ();
15209
15210   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15211     {
15212       /* 32/64 bit address mode */
15213       int havedisp;
15214       int havesib;
15215       int havebase;
15216       int haveindex;
15217       int needindex;
15218       int base, rbase;
15219       int vindex = 0;
15220       int scale = 0;
15221       int addr32flag = !((sizeflag & AFLAG)
15222                          || bytemode == v_bnd_mode
15223                          || bytemode == bnd_mode);
15224       const char **indexes64 = names64;
15225       const char **indexes32 = names32;
15226
15227       havesib = 0;
15228       havebase = 1;
15229       haveindex = 0;
15230       base = modrm.rm;
15231
15232       if (base == 4)
15233         {
15234           havesib = 1;
15235           vindex = sib.index;
15236           USED_REX (REX_X);
15237           if (rex & REX_X)
15238             vindex += 8;
15239           switch (bytemode)
15240             {
15241             case vex_vsib_d_w_dq_mode:
15242             case vex_vsib_d_w_d_mode:
15243             case vex_vsib_q_w_dq_mode:
15244             case vex_vsib_q_w_d_mode:
15245               if (!need_vex)
15246                 abort ();
15247               if (vex.evex)
15248                 {
15249                   if (!vex.v)
15250                     vindex += 16;
15251                 }
15252
15253               haveindex = 1;
15254               switch (vex.length)
15255                 {
15256                 case 128:
15257                   indexes64 = indexes32 = names_xmm;
15258                   break;
15259                 case 256:
15260                   if (!vex.w
15261                       || bytemode == vex_vsib_q_w_dq_mode
15262                       || bytemode == vex_vsib_q_w_d_mode)
15263                     indexes64 = indexes32 = names_ymm;
15264                   else
15265                     indexes64 = indexes32 = names_xmm;
15266                   break;
15267                 case 512:
15268                   if (!vex.w
15269                       || bytemode == vex_vsib_q_w_dq_mode
15270                       || bytemode == vex_vsib_q_w_d_mode)
15271                     indexes64 = indexes32 = names_zmm;
15272                   else
15273                     indexes64 = indexes32 = names_ymm;
15274                   break;
15275                 default:
15276                   abort ();
15277                 }
15278               break;
15279             default:
15280               haveindex = vindex != 4;
15281               break;
15282             }
15283           scale = sib.scale;
15284           base = sib.base;
15285           codep++;
15286         }
15287       rbase = base + add;
15288
15289       switch (modrm.mod)
15290         {
15291         case 0:
15292           if (base == 5)
15293             {
15294               havebase = 0;
15295               if (address_mode == mode_64bit && !havesib)
15296                 riprel = 1;
15297               disp = get32s ();
15298             }
15299           break;
15300         case 1:
15301           FETCH_DATA (the_info, codep + 1);
15302           disp = *codep++;
15303           if ((disp & 0x80) != 0)
15304             disp -= 0x100;
15305           if (vex.evex && shift > 0)
15306             disp <<= shift;
15307           break;
15308         case 2:
15309           disp = get32s ();
15310           break;
15311         }
15312
15313       /* In 32bit mode, we need index register to tell [offset] from
15314          [eiz*1 + offset].  */
15315       needindex = (havesib
15316                    && !havebase
15317                    && !haveindex
15318                    && address_mode == mode_32bit);
15319       havedisp = (havebase
15320                   || needindex
15321                   || (havesib && (haveindex || scale != 0)));
15322
15323       if (!intel_syntax)
15324         if (modrm.mod != 0 || base == 5)
15325           {
15326             if (havedisp || riprel)
15327               print_displacement (scratchbuf, disp);
15328             else
15329               print_operand_value (scratchbuf, 1, disp);
15330             oappend (scratchbuf);
15331             if (riprel)
15332               {
15333                 set_op (disp, 1);
15334                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15335               }
15336           }
15337
15338       if ((havebase || haveindex || riprel)
15339           && (bytemode != v_bnd_mode)
15340           && (bytemode != bnd_mode))
15341         used_prefixes |= PREFIX_ADDR;
15342
15343       if (havedisp || (intel_syntax && riprel))
15344         {
15345           *obufp++ = open_char;
15346           if (intel_syntax && riprel)
15347             {
15348               set_op (disp, 1);
15349               oappend (!addr32flag ? "rip" : "eip");
15350             }
15351           *obufp = '\0';
15352           if (havebase)
15353             oappend (address_mode == mode_64bit && !addr32flag
15354                      ? names64[rbase] : names32[rbase]);
15355           if (havesib)
15356             {
15357               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15358                  print index to tell base + index from base.  */
15359               if (scale != 0
15360                   || needindex
15361                   || haveindex
15362                   || (havebase && base != ESP_REG_NUM))
15363                 {
15364                   if (!intel_syntax || havebase)
15365                     {
15366                       *obufp++ = separator_char;
15367                       *obufp = '\0';
15368                     }
15369                   if (haveindex)
15370                     oappend (address_mode == mode_64bit && !addr32flag
15371                              ? indexes64[vindex] : indexes32[vindex]);
15372                   else
15373                     oappend (address_mode == mode_64bit && !addr32flag
15374                              ? index64 : index32);
15375
15376                   *obufp++ = scale_char;
15377                   *obufp = '\0';
15378                   sprintf (scratchbuf, "%d", 1 << scale);
15379                   oappend (scratchbuf);
15380                 }
15381             }
15382           if (intel_syntax
15383               && (disp || modrm.mod != 0 || base == 5))
15384             {
15385               if (!havedisp || (bfd_signed_vma) disp >= 0)
15386                 {
15387                   *obufp++ = '+';
15388                   *obufp = '\0';
15389                 }
15390               else if (modrm.mod != 1 && disp != -disp)
15391                 {
15392                   *obufp++ = '-';
15393                   *obufp = '\0';
15394                   disp = - (bfd_signed_vma) disp;
15395                 }
15396
15397               if (havedisp)
15398                 print_displacement (scratchbuf, disp);
15399               else
15400                 print_operand_value (scratchbuf, 1, disp);
15401               oappend (scratchbuf);
15402             }
15403
15404           *obufp++ = close_char;
15405           *obufp = '\0';
15406         }
15407       else if (intel_syntax)
15408         {
15409           if (modrm.mod != 0 || base == 5)
15410             {
15411               if (!active_seg_prefix)
15412                 {
15413                   oappend (names_seg[ds_reg - es_reg]);
15414                   oappend (":");
15415                 }
15416               print_operand_value (scratchbuf, 1, disp);
15417               oappend (scratchbuf);
15418             }
15419         }
15420     }
15421   else
15422     {
15423       /* 16 bit address mode */
15424       used_prefixes |= prefixes & PREFIX_ADDR;
15425       switch (modrm.mod)
15426         {
15427         case 0:
15428           if (modrm.rm == 6)
15429             {
15430               disp = get16 ();
15431               if ((disp & 0x8000) != 0)
15432                 disp -= 0x10000;
15433             }
15434           break;
15435         case 1:
15436           FETCH_DATA (the_info, codep + 1);
15437           disp = *codep++;
15438           if ((disp & 0x80) != 0)
15439             disp -= 0x100;
15440           break;
15441         case 2:
15442           disp = get16 ();
15443           if ((disp & 0x8000) != 0)
15444             disp -= 0x10000;
15445           break;
15446         }
15447
15448       if (!intel_syntax)
15449         if (modrm.mod != 0 || modrm.rm == 6)
15450           {
15451             print_displacement (scratchbuf, disp);
15452             oappend (scratchbuf);
15453           }
15454
15455       if (modrm.mod != 0 || modrm.rm != 6)
15456         {
15457           *obufp++ = open_char;
15458           *obufp = '\0';
15459           oappend (index16[modrm.rm]);
15460           if (intel_syntax
15461               && (disp || modrm.mod != 0 || modrm.rm == 6))
15462             {
15463               if ((bfd_signed_vma) disp >= 0)
15464                 {
15465                   *obufp++ = '+';
15466                   *obufp = '\0';
15467                 }
15468               else if (modrm.mod != 1)
15469                 {
15470                   *obufp++ = '-';
15471                   *obufp = '\0';
15472                   disp = - (bfd_signed_vma) disp;
15473                 }
15474
15475               print_displacement (scratchbuf, disp);
15476               oappend (scratchbuf);
15477             }
15478
15479           *obufp++ = close_char;
15480           *obufp = '\0';
15481         }
15482       else if (intel_syntax)
15483         {
15484           if (!active_seg_prefix)
15485             {
15486               oappend (names_seg[ds_reg - es_reg]);
15487               oappend (":");
15488             }
15489           print_operand_value (scratchbuf, 1, disp & 0xffff);
15490           oappend (scratchbuf);
15491         }
15492     }
15493   if (vex.evex && vex.b
15494       && (bytemode == x_mode
15495           || bytemode == xmmq_mode
15496           || bytemode == evex_half_bcst_xmmq_mode))
15497     {
15498       if (vex.w
15499           || bytemode == xmmq_mode
15500           || bytemode == evex_half_bcst_xmmq_mode)
15501         {
15502           switch (vex.length)
15503             {
15504             case 128:
15505               oappend ("{1to2}");
15506               break;
15507             case 256:
15508               oappend ("{1to4}");
15509               break;
15510             case 512:
15511               oappend ("{1to8}");
15512               break;
15513             default:
15514               abort ();
15515             }
15516         }
15517       else
15518         {
15519           switch (vex.length)
15520             {
15521             case 128:
15522               oappend ("{1to4}");
15523               break;
15524             case 256:
15525               oappend ("{1to8}");
15526               break;
15527             case 512:
15528               oappend ("{1to16}");
15529               break;
15530             default:
15531               abort ();
15532             }
15533         }
15534     }
15535 }
15536
15537 static void
15538 OP_E (int bytemode, int sizeflag)
15539 {
15540   /* Skip mod/rm byte.  */
15541   MODRM_CHECK;
15542   codep++;
15543
15544   if (modrm.mod == 3)
15545     OP_E_register (bytemode, sizeflag);
15546   else
15547     OP_E_memory (bytemode, sizeflag);
15548 }
15549
15550 static void
15551 OP_G (int bytemode, int sizeflag)
15552 {
15553   int add = 0;
15554   USED_REX (REX_R);
15555   if (rex & REX_R)
15556     add += 8;
15557   switch (bytemode)
15558     {
15559     case b_mode:
15560       USED_REX (0);
15561       if (rex)
15562         oappend (names8rex[modrm.reg + add]);
15563       else
15564         oappend (names8[modrm.reg + add]);
15565       break;
15566     case w_mode:
15567       oappend (names16[modrm.reg + add]);
15568       break;
15569     case d_mode:
15570     case db_mode:
15571     case dw_mode:
15572       oappend (names32[modrm.reg + add]);
15573       break;
15574     case q_mode:
15575       oappend (names64[modrm.reg + add]);
15576       break;
15577     case bnd_mode:
15578       if (modrm.reg > 0x3)
15579         {
15580           oappend ("(bad)");
15581           return;
15582         }
15583       oappend (names_bnd[modrm.reg]);
15584       break;
15585     case v_mode:
15586     case dq_mode:
15587     case dqb_mode:
15588     case dqd_mode:
15589     case dqw_mode:
15590       USED_REX (REX_W);
15591       if (rex & REX_W)
15592         oappend (names64[modrm.reg + add]);
15593       else
15594         {
15595           if ((sizeflag & DFLAG) || bytemode != v_mode)
15596             oappend (names32[modrm.reg + add]);
15597           else
15598             oappend (names16[modrm.reg + add]);
15599           used_prefixes |= (prefixes & PREFIX_DATA);
15600         }
15601       break;
15602     case m_mode:
15603       if (address_mode == mode_64bit)
15604         oappend (names64[modrm.reg + add]);
15605       else
15606         oappend (names32[modrm.reg + add]);
15607       break;
15608     case mask_bd_mode:
15609     case mask_mode:
15610       if ((modrm.reg + add) > 0x7)
15611         {
15612           oappend ("(bad)");
15613           return;
15614         }
15615       oappend (names_mask[modrm.reg + add]);
15616       break;
15617     default:
15618       oappend (INTERNAL_DISASSEMBLER_ERROR);
15619       break;
15620     }
15621 }
15622
15623 static bfd_vma
15624 get64 (void)
15625 {
15626   bfd_vma x;
15627 #ifdef BFD64
15628   unsigned int a;
15629   unsigned int b;
15630
15631   FETCH_DATA (the_info, codep + 8);
15632   a = *codep++ & 0xff;
15633   a |= (*codep++ & 0xff) << 8;
15634   a |= (*codep++ & 0xff) << 16;
15635   a |= (*codep++ & 0xffu) << 24;
15636   b = *codep++ & 0xff;
15637   b |= (*codep++ & 0xff) << 8;
15638   b |= (*codep++ & 0xff) << 16;
15639   b |= (*codep++ & 0xffu) << 24;
15640   x = a + ((bfd_vma) b << 32);
15641 #else
15642   abort ();
15643   x = 0;
15644 #endif
15645   return x;
15646 }
15647
15648 static bfd_signed_vma
15649 get32 (void)
15650 {
15651   bfd_signed_vma x = 0;
15652
15653   FETCH_DATA (the_info, codep + 4);
15654   x = *codep++ & (bfd_signed_vma) 0xff;
15655   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15656   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15657   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15658   return x;
15659 }
15660
15661 static bfd_signed_vma
15662 get32s (void)
15663 {
15664   bfd_signed_vma x = 0;
15665
15666   FETCH_DATA (the_info, codep + 4);
15667   x = *codep++ & (bfd_signed_vma) 0xff;
15668   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15669   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15670   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15671
15672   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15673
15674   return x;
15675 }
15676
15677 static int
15678 get16 (void)
15679 {
15680   int x = 0;
15681
15682   FETCH_DATA (the_info, codep + 2);
15683   x = *codep++ & 0xff;
15684   x |= (*codep++ & 0xff) << 8;
15685   return x;
15686 }
15687
15688 static void
15689 set_op (bfd_vma op, int riprel)
15690 {
15691   op_index[op_ad] = op_ad;
15692   if (address_mode == mode_64bit)
15693     {
15694       op_address[op_ad] = op;
15695       op_riprel[op_ad] = riprel;
15696     }
15697   else
15698     {
15699       /* Mask to get a 32-bit address.  */
15700       op_address[op_ad] = op & 0xffffffff;
15701       op_riprel[op_ad] = riprel & 0xffffffff;
15702     }
15703 }
15704
15705 static void
15706 OP_REG (int code, int sizeflag)
15707 {
15708   const char *s;
15709   int add;
15710
15711   switch (code)
15712     {
15713     case es_reg: case ss_reg: case cs_reg:
15714     case ds_reg: case fs_reg: case gs_reg:
15715       oappend (names_seg[code - es_reg]);
15716       return;
15717     }
15718
15719   USED_REX (REX_B);
15720   if (rex & REX_B)
15721     add = 8;
15722   else
15723     add = 0;
15724
15725   switch (code)
15726     {
15727     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15728     case sp_reg: case bp_reg: case si_reg: case di_reg:
15729       s = names16[code - ax_reg + add];
15730       break;
15731     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15732     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15733       USED_REX (0);
15734       if (rex)
15735         s = names8rex[code - al_reg + add];
15736       else
15737         s = names8[code - al_reg];
15738       break;
15739     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15740     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15741       if (address_mode == mode_64bit
15742           && ((sizeflag & DFLAG) || (rex & REX_W)))
15743         {
15744           s = names64[code - rAX_reg + add];
15745           break;
15746         }
15747       code += eAX_reg - rAX_reg;
15748       /* Fall through.  */
15749     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15750     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15751       USED_REX (REX_W);
15752       if (rex & REX_W)
15753         s = names64[code - eAX_reg + add];
15754       else
15755         {
15756           if (sizeflag & DFLAG)
15757             s = names32[code - eAX_reg + add];
15758           else
15759             s = names16[code - eAX_reg + add];
15760           used_prefixes |= (prefixes & PREFIX_DATA);
15761         }
15762       break;
15763     default:
15764       s = INTERNAL_DISASSEMBLER_ERROR;
15765       break;
15766     }
15767   oappend (s);
15768 }
15769
15770 static void
15771 OP_IMREG (int code, int sizeflag)
15772 {
15773   const char *s;
15774
15775   switch (code)
15776     {
15777     case indir_dx_reg:
15778       if (intel_syntax)
15779         s = "dx";
15780       else
15781         s = "(%dx)";
15782       break;
15783     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15784     case sp_reg: case bp_reg: case si_reg: case di_reg:
15785       s = names16[code - ax_reg];
15786       break;
15787     case es_reg: case ss_reg: case cs_reg:
15788     case ds_reg: case fs_reg: case gs_reg:
15789       s = names_seg[code - es_reg];
15790       break;
15791     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15792     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15793       USED_REX (0);
15794       if (rex)
15795         s = names8rex[code - al_reg];
15796       else
15797         s = names8[code - al_reg];
15798       break;
15799     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15800     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15801       USED_REX (REX_W);
15802       if (rex & REX_W)
15803         s = names64[code - eAX_reg];
15804       else
15805         {
15806           if (sizeflag & DFLAG)
15807             s = names32[code - eAX_reg];
15808           else
15809             s = names16[code - eAX_reg];
15810           used_prefixes |= (prefixes & PREFIX_DATA);
15811         }
15812       break;
15813     case z_mode_ax_reg:
15814       if ((rex & REX_W) || (sizeflag & DFLAG))
15815         s = *names32;
15816       else
15817         s = *names16;
15818       if (!(rex & REX_W))
15819         used_prefixes |= (prefixes & PREFIX_DATA);
15820       break;
15821     default:
15822       s = INTERNAL_DISASSEMBLER_ERROR;
15823       break;
15824     }
15825   oappend (s);
15826 }
15827
15828 static void
15829 OP_I (int bytemode, int sizeflag)
15830 {
15831   bfd_signed_vma op;
15832   bfd_signed_vma mask = -1;
15833
15834   switch (bytemode)
15835     {
15836     case b_mode:
15837       FETCH_DATA (the_info, codep + 1);
15838       op = *codep++;
15839       mask = 0xff;
15840       break;
15841     case q_mode:
15842       if (address_mode == mode_64bit)
15843         {
15844           op = get32s ();
15845           break;
15846         }
15847       /* Fall through.  */
15848     case v_mode:
15849       USED_REX (REX_W);
15850       if (rex & REX_W)
15851         op = get32s ();
15852       else
15853         {
15854           if (sizeflag & DFLAG)
15855             {
15856               op = get32 ();
15857               mask = 0xffffffff;
15858             }
15859           else
15860             {
15861               op = get16 ();
15862               mask = 0xfffff;
15863             }
15864           used_prefixes |= (prefixes & PREFIX_DATA);
15865         }
15866       break;
15867     case w_mode:
15868       mask = 0xfffff;
15869       op = get16 ();
15870       break;
15871     case const_1_mode:
15872       if (intel_syntax)
15873         oappend ("1");
15874       return;
15875     default:
15876       oappend (INTERNAL_DISASSEMBLER_ERROR);
15877       return;
15878     }
15879
15880   op &= mask;
15881   scratchbuf[0] = '$';
15882   print_operand_value (scratchbuf + 1, 1, op);
15883   oappend_maybe_intel (scratchbuf);
15884   scratchbuf[0] = '\0';
15885 }
15886
15887 static void
15888 OP_I64 (int bytemode, int sizeflag)
15889 {
15890   bfd_signed_vma op;
15891   bfd_signed_vma mask = -1;
15892
15893   if (address_mode != mode_64bit)
15894     {
15895       OP_I (bytemode, sizeflag);
15896       return;
15897     }
15898
15899   switch (bytemode)
15900     {
15901     case b_mode:
15902       FETCH_DATA (the_info, codep + 1);
15903       op = *codep++;
15904       mask = 0xff;
15905       break;
15906     case v_mode:
15907       USED_REX (REX_W);
15908       if (rex & REX_W)
15909         op = get64 ();
15910       else
15911         {
15912           if (sizeflag & DFLAG)
15913             {
15914               op = get32 ();
15915               mask = 0xffffffff;
15916             }
15917           else
15918             {
15919               op = get16 ();
15920               mask = 0xfffff;
15921             }
15922           used_prefixes |= (prefixes & PREFIX_DATA);
15923         }
15924       break;
15925     case w_mode:
15926       mask = 0xfffff;
15927       op = get16 ();
15928       break;
15929     default:
15930       oappend (INTERNAL_DISASSEMBLER_ERROR);
15931       return;
15932     }
15933
15934   op &= mask;
15935   scratchbuf[0] = '$';
15936   print_operand_value (scratchbuf + 1, 1, op);
15937   oappend_maybe_intel (scratchbuf);
15938   scratchbuf[0] = '\0';
15939 }
15940
15941 static void
15942 OP_sI (int bytemode, int sizeflag)
15943 {
15944   bfd_signed_vma op;
15945
15946   switch (bytemode)
15947     {
15948     case b_mode:
15949     case b_T_mode:
15950       FETCH_DATA (the_info, codep + 1);
15951       op = *codep++;
15952       if ((op & 0x80) != 0)
15953         op -= 0x100;
15954       if (bytemode == b_T_mode)
15955         {
15956           if (address_mode != mode_64bit
15957               || !((sizeflag & DFLAG) || (rex & REX_W)))
15958             {
15959               /* The operand-size prefix is overridden by a REX prefix.  */
15960               if ((sizeflag & DFLAG) || (rex & REX_W))
15961                 op &= 0xffffffff;
15962               else
15963                 op &= 0xffff;
15964           }
15965         }
15966       else
15967         {
15968           if (!(rex & REX_W))
15969             {
15970               if (sizeflag & DFLAG)
15971                 op &= 0xffffffff;
15972               else
15973                 op &= 0xffff;
15974             }
15975         }
15976       break;
15977     case v_mode:
15978       /* The operand-size prefix is overridden by a REX prefix.  */
15979       if ((sizeflag & DFLAG) || (rex & REX_W))
15980         op = get32s ();
15981       else
15982         op = get16 ();
15983       break;
15984     default:
15985       oappend (INTERNAL_DISASSEMBLER_ERROR);
15986       return;
15987     }
15988
15989   scratchbuf[0] = '$';
15990   print_operand_value (scratchbuf + 1, 1, op);
15991   oappend_maybe_intel (scratchbuf);
15992 }
15993
15994 static void
15995 OP_J (int bytemode, int sizeflag)
15996 {
15997   bfd_vma disp;
15998   bfd_vma mask = -1;
15999   bfd_vma segment = 0;
16000
16001   switch (bytemode)
16002     {
16003     case b_mode:
16004       FETCH_DATA (the_info, codep + 1);
16005       disp = *codep++;
16006       if ((disp & 0x80) != 0)
16007         disp -= 0x100;
16008       break;
16009     case v_mode:
16010       if (isa64 == amd64)
16011         USED_REX (REX_W);
16012       if ((sizeflag & DFLAG)
16013           || (address_mode == mode_64bit
16014               && (isa64 != amd64 || (rex & REX_W))))
16015         disp = get32s ();
16016       else
16017         {
16018           disp = get16 ();
16019           if ((disp & 0x8000) != 0)
16020             disp -= 0x10000;
16021           /* In 16bit mode, address is wrapped around at 64k within
16022              the same segment.  Otherwise, a data16 prefix on a jump
16023              instruction means that the pc is masked to 16 bits after
16024              the displacement is added!  */
16025           mask = 0xffff;
16026           if ((prefixes & PREFIX_DATA) == 0)
16027             segment = ((start_pc + (codep - start_codep))
16028                        & ~((bfd_vma) 0xffff));
16029         }
16030       if (address_mode != mode_64bit
16031           || (isa64 == amd64 && !(rex & REX_W)))
16032         used_prefixes |= (prefixes & PREFIX_DATA);
16033       break;
16034     default:
16035       oappend (INTERNAL_DISASSEMBLER_ERROR);
16036       return;
16037     }
16038   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16039   set_op (disp, 0);
16040   print_operand_value (scratchbuf, 1, disp);
16041   oappend (scratchbuf);
16042 }
16043
16044 static void
16045 OP_SEG (int bytemode, int sizeflag)
16046 {
16047   if (bytemode == w_mode)
16048     oappend (names_seg[modrm.reg]);
16049   else
16050     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16051 }
16052
16053 static void
16054 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16055 {
16056   int seg, offset;
16057
16058   if (sizeflag & DFLAG)
16059     {
16060       offset = get32 ();
16061       seg = get16 ();
16062     }
16063   else
16064     {
16065       offset = get16 ();
16066       seg = get16 ();
16067     }
16068   used_prefixes |= (prefixes & PREFIX_DATA);
16069   if (intel_syntax)
16070     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16071   else
16072     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16073   oappend (scratchbuf);
16074 }
16075
16076 static void
16077 OP_OFF (int bytemode, int sizeflag)
16078 {
16079   bfd_vma off;
16080
16081   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16082     intel_operand_size (bytemode, sizeflag);
16083   append_seg ();
16084
16085   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16086     off = get32 ();
16087   else
16088     off = get16 ();
16089
16090   if (intel_syntax)
16091     {
16092       if (!active_seg_prefix)
16093         {
16094           oappend (names_seg[ds_reg - es_reg]);
16095           oappend (":");
16096         }
16097     }
16098   print_operand_value (scratchbuf, 1, off);
16099   oappend (scratchbuf);
16100 }
16101
16102 static void
16103 OP_OFF64 (int bytemode, int sizeflag)
16104 {
16105   bfd_vma off;
16106
16107   if (address_mode != mode_64bit
16108       || (prefixes & PREFIX_ADDR))
16109     {
16110       OP_OFF (bytemode, sizeflag);
16111       return;
16112     }
16113
16114   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16115     intel_operand_size (bytemode, sizeflag);
16116   append_seg ();
16117
16118   off = get64 ();
16119
16120   if (intel_syntax)
16121     {
16122       if (!active_seg_prefix)
16123         {
16124           oappend (names_seg[ds_reg - es_reg]);
16125           oappend (":");
16126         }
16127     }
16128   print_operand_value (scratchbuf, 1, off);
16129   oappend (scratchbuf);
16130 }
16131
16132 static void
16133 ptr_reg (int code, int sizeflag)
16134 {
16135   const char *s;
16136
16137   *obufp++ = open_char;
16138   used_prefixes |= (prefixes & PREFIX_ADDR);
16139   if (address_mode == mode_64bit)
16140     {
16141       if (!(sizeflag & AFLAG))
16142         s = names32[code - eAX_reg];
16143       else
16144         s = names64[code - eAX_reg];
16145     }
16146   else if (sizeflag & AFLAG)
16147     s = names32[code - eAX_reg];
16148   else
16149     s = names16[code - eAX_reg];
16150   oappend (s);
16151   *obufp++ = close_char;
16152   *obufp = 0;
16153 }
16154
16155 static void
16156 OP_ESreg (int code, int sizeflag)
16157 {
16158   if (intel_syntax)
16159     {
16160       switch (codep[-1])
16161         {
16162         case 0x6d:      /* insw/insl */
16163           intel_operand_size (z_mode, sizeflag);
16164           break;
16165         case 0xa5:      /* movsw/movsl/movsq */
16166         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16167         case 0xab:      /* stosw/stosl */
16168         case 0xaf:      /* scasw/scasl */
16169           intel_operand_size (v_mode, sizeflag);
16170           break;
16171         default:
16172           intel_operand_size (b_mode, sizeflag);
16173         }
16174     }
16175   oappend_maybe_intel ("%es:");
16176   ptr_reg (code, sizeflag);
16177 }
16178
16179 static void
16180 OP_DSreg (int code, int sizeflag)
16181 {
16182   if (intel_syntax)
16183     {
16184       switch (codep[-1])
16185         {
16186         case 0x6f:      /* outsw/outsl */
16187           intel_operand_size (z_mode, sizeflag);
16188           break;
16189         case 0xa5:      /* movsw/movsl/movsq */
16190         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16191         case 0xad:      /* lodsw/lodsl/lodsq */
16192           intel_operand_size (v_mode, sizeflag);
16193           break;
16194         default:
16195           intel_operand_size (b_mode, sizeflag);
16196         }
16197     }
16198   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16199      default segment register DS is printed.  */
16200   if (!active_seg_prefix)
16201     active_seg_prefix = PREFIX_DS;
16202   append_seg ();
16203   ptr_reg (code, sizeflag);
16204 }
16205
16206 static void
16207 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16208 {
16209   int add;
16210   if (rex & REX_R)
16211     {
16212       USED_REX (REX_R);
16213       add = 8;
16214     }
16215   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16216     {
16217       all_prefixes[last_lock_prefix] = 0;
16218       used_prefixes |= PREFIX_LOCK;
16219       add = 8;
16220     }
16221   else
16222     add = 0;
16223   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16224   oappend_maybe_intel (scratchbuf);
16225 }
16226
16227 static void
16228 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16229 {
16230   int add;
16231   USED_REX (REX_R);
16232   if (rex & REX_R)
16233     add = 8;
16234   else
16235     add = 0;
16236   if (intel_syntax)
16237     sprintf (scratchbuf, "db%d", modrm.reg + add);
16238   else
16239     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16240   oappend (scratchbuf);
16241 }
16242
16243 static void
16244 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16245 {
16246   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16247   oappend_maybe_intel (scratchbuf);
16248 }
16249
16250 static void
16251 OP_R (int bytemode, int sizeflag)
16252 {
16253   /* Skip mod/rm byte.  */
16254   MODRM_CHECK;
16255   codep++;
16256   OP_E_register (bytemode, sizeflag);
16257 }
16258
16259 static void
16260 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16261 {
16262   int reg = modrm.reg;
16263   const char **names;
16264
16265   used_prefixes |= (prefixes & PREFIX_DATA);
16266   if (prefixes & PREFIX_DATA)
16267     {
16268       names = names_xmm;
16269       USED_REX (REX_R);
16270       if (rex & REX_R)
16271         reg += 8;
16272     }
16273   else
16274     names = names_mm;
16275   oappend (names[reg]);
16276 }
16277
16278 static void
16279 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16280 {
16281   int reg = modrm.reg;
16282   const char **names;
16283
16284   USED_REX (REX_R);
16285   if (rex & REX_R)
16286     reg += 8;
16287   if (vex.evex)
16288     {
16289       if (!vex.r)
16290         reg += 16;
16291     }
16292
16293   if (need_vex
16294       && bytemode != xmm_mode
16295       && bytemode != xmmq_mode
16296       && bytemode != evex_half_bcst_xmmq_mode
16297       && bytemode != ymm_mode
16298       && bytemode != scalar_mode)
16299     {
16300       switch (vex.length)
16301         {
16302         case 128:
16303           names = names_xmm;
16304           break;
16305         case 256:
16306           if (vex.w
16307               || (bytemode != vex_vsib_q_w_dq_mode
16308                   && bytemode != vex_vsib_q_w_d_mode))
16309             names = names_ymm;
16310           else
16311             names = names_xmm;
16312           break;
16313         case 512:
16314           names = names_zmm;
16315           break;
16316         default:
16317           abort ();
16318         }
16319     }
16320   else if (bytemode == xmmq_mode
16321            || bytemode == evex_half_bcst_xmmq_mode)
16322     {
16323       switch (vex.length)
16324         {
16325         case 128:
16326         case 256:
16327           names = names_xmm;
16328           break;
16329         case 512:
16330           names = names_ymm;
16331           break;
16332         default:
16333           abort ();
16334         }
16335     }
16336   else if (bytemode == ymm_mode)
16337     names = names_ymm;
16338   else
16339     names = names_xmm;
16340   oappend (names[reg]);
16341 }
16342
16343 static void
16344 OP_EM (int bytemode, int sizeflag)
16345 {
16346   int reg;
16347   const char **names;
16348
16349   if (modrm.mod != 3)
16350     {
16351       if (intel_syntax
16352           && (bytemode == v_mode || bytemode == v_swap_mode))
16353         {
16354           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16355           used_prefixes |= (prefixes & PREFIX_DATA);
16356         }
16357       OP_E (bytemode, sizeflag);
16358       return;
16359     }
16360
16361   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16362     swap_operand ();
16363
16364   /* Skip mod/rm byte.  */
16365   MODRM_CHECK;
16366   codep++;
16367   used_prefixes |= (prefixes & PREFIX_DATA);
16368   reg = modrm.rm;
16369   if (prefixes & PREFIX_DATA)
16370     {
16371       names = names_xmm;
16372       USED_REX (REX_B);
16373       if (rex & REX_B)
16374         reg += 8;
16375     }
16376   else
16377     names = names_mm;
16378   oappend (names[reg]);
16379 }
16380
16381 /* cvt* are the only instructions in sse2 which have
16382    both SSE and MMX operands and also have 0x66 prefix
16383    in their opcode. 0x66 was originally used to differentiate
16384    between SSE and MMX instruction(operands). So we have to handle the
16385    cvt* separately using OP_EMC and OP_MXC */
16386 static void
16387 OP_EMC (int bytemode, int sizeflag)
16388 {
16389   if (modrm.mod != 3)
16390     {
16391       if (intel_syntax && bytemode == v_mode)
16392         {
16393           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16394           used_prefixes |= (prefixes & PREFIX_DATA);
16395         }
16396       OP_E (bytemode, sizeflag);
16397       return;
16398     }
16399
16400   /* Skip mod/rm byte.  */
16401   MODRM_CHECK;
16402   codep++;
16403   used_prefixes |= (prefixes & PREFIX_DATA);
16404   oappend (names_mm[modrm.rm]);
16405 }
16406
16407 static void
16408 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16409 {
16410   used_prefixes |= (prefixes & PREFIX_DATA);
16411   oappend (names_mm[modrm.reg]);
16412 }
16413
16414 static void
16415 OP_EX (int bytemode, int sizeflag)
16416 {
16417   int reg;
16418   const char **names;
16419
16420   /* Skip mod/rm byte.  */
16421   MODRM_CHECK;
16422   codep++;
16423
16424   if (modrm.mod != 3)
16425     {
16426       OP_E_memory (bytemode, sizeflag);
16427       return;
16428     }
16429
16430   reg = modrm.rm;
16431   USED_REX (REX_B);
16432   if (rex & REX_B)
16433     reg += 8;
16434   if (vex.evex)
16435     {
16436       USED_REX (REX_X);
16437       if ((rex & REX_X))
16438         reg += 16;
16439     }
16440
16441   if ((sizeflag & SUFFIX_ALWAYS)
16442       && (bytemode == x_swap_mode
16443           || bytemode == d_swap_mode
16444           || bytemode == d_scalar_swap_mode
16445           || bytemode == q_swap_mode
16446           || bytemode == q_scalar_swap_mode))
16447     swap_operand ();
16448
16449   if (need_vex
16450       && bytemode != xmm_mode
16451       && bytemode != xmmdw_mode
16452       && bytemode != xmmqd_mode
16453       && bytemode != xmm_mb_mode
16454       && bytemode != xmm_mw_mode
16455       && bytemode != xmm_md_mode
16456       && bytemode != xmm_mq_mode
16457       && bytemode != xmm_mdq_mode
16458       && bytemode != xmmq_mode
16459       && bytemode != evex_half_bcst_xmmq_mode
16460       && bytemode != ymm_mode
16461       && bytemode != d_scalar_mode
16462       && bytemode != d_scalar_swap_mode
16463       && bytemode != q_scalar_mode
16464       && bytemode != q_scalar_swap_mode
16465       && bytemode != vex_scalar_w_dq_mode)
16466     {
16467       switch (vex.length)
16468         {
16469         case 128:
16470           names = names_xmm;
16471           break;
16472         case 256:
16473           names = names_ymm;
16474           break;
16475         case 512:
16476           names = names_zmm;
16477           break;
16478         default:
16479           abort ();
16480         }
16481     }
16482   else if (bytemode == xmmq_mode
16483            || bytemode == evex_half_bcst_xmmq_mode)
16484     {
16485       switch (vex.length)
16486         {
16487         case 128:
16488         case 256:
16489           names = names_xmm;
16490           break;
16491         case 512:
16492           names = names_ymm;
16493           break;
16494         default:
16495           abort ();
16496         }
16497     }
16498   else if (bytemode == ymm_mode)
16499     names = names_ymm;
16500   else
16501     names = names_xmm;
16502   oappend (names[reg]);
16503 }
16504
16505 static void
16506 OP_MS (int bytemode, int sizeflag)
16507 {
16508   if (modrm.mod == 3)
16509     OP_EM (bytemode, sizeflag);
16510   else
16511     BadOp ();
16512 }
16513
16514 static void
16515 OP_XS (int bytemode, int sizeflag)
16516 {
16517   if (modrm.mod == 3)
16518     OP_EX (bytemode, sizeflag);
16519   else
16520     BadOp ();
16521 }
16522
16523 static void
16524 OP_M (int bytemode, int sizeflag)
16525 {
16526   if (modrm.mod == 3)
16527     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16528     BadOp ();
16529   else
16530     OP_E (bytemode, sizeflag);
16531 }
16532
16533 static void
16534 OP_0f07 (int bytemode, int sizeflag)
16535 {
16536   if (modrm.mod != 3 || modrm.rm != 0)
16537     BadOp ();
16538   else
16539     OP_E (bytemode, sizeflag);
16540 }
16541
16542 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16543    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16544
16545 static void
16546 NOP_Fixup1 (int bytemode, int sizeflag)
16547 {
16548   if ((prefixes & PREFIX_DATA) != 0
16549       || (rex != 0
16550           && rex != 0x48
16551           && address_mode == mode_64bit))
16552     OP_REG (bytemode, sizeflag);
16553   else
16554     strcpy (obuf, "nop");
16555 }
16556
16557 static void
16558 NOP_Fixup2 (int bytemode, int sizeflag)
16559 {
16560   if ((prefixes & PREFIX_DATA) != 0
16561       || (rex != 0
16562           && rex != 0x48
16563           && address_mode == mode_64bit))
16564     OP_IMREG (bytemode, sizeflag);
16565 }
16566
16567 static const char *const Suffix3DNow[] = {
16568 /* 00 */        NULL,           NULL,           NULL,           NULL,
16569 /* 04 */        NULL,           NULL,           NULL,           NULL,
16570 /* 08 */        NULL,           NULL,           NULL,           NULL,
16571 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16572 /* 10 */        NULL,           NULL,           NULL,           NULL,
16573 /* 14 */        NULL,           NULL,           NULL,           NULL,
16574 /* 18 */        NULL,           NULL,           NULL,           NULL,
16575 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16576 /* 20 */        NULL,           NULL,           NULL,           NULL,
16577 /* 24 */        NULL,           NULL,           NULL,           NULL,
16578 /* 28 */        NULL,           NULL,           NULL,           NULL,
16579 /* 2C */        NULL,           NULL,           NULL,           NULL,
16580 /* 30 */        NULL,           NULL,           NULL,           NULL,
16581 /* 34 */        NULL,           NULL,           NULL,           NULL,
16582 /* 38 */        NULL,           NULL,           NULL,           NULL,
16583 /* 3C */        NULL,           NULL,           NULL,           NULL,
16584 /* 40 */        NULL,           NULL,           NULL,           NULL,
16585 /* 44 */        NULL,           NULL,           NULL,           NULL,
16586 /* 48 */        NULL,           NULL,           NULL,           NULL,
16587 /* 4C */        NULL,           NULL,           NULL,           NULL,
16588 /* 50 */        NULL,           NULL,           NULL,           NULL,
16589 /* 54 */        NULL,           NULL,           NULL,           NULL,
16590 /* 58 */        NULL,           NULL,           NULL,           NULL,
16591 /* 5C */        NULL,           NULL,           NULL,           NULL,
16592 /* 60 */        NULL,           NULL,           NULL,           NULL,
16593 /* 64 */        NULL,           NULL,           NULL,           NULL,
16594 /* 68 */        NULL,           NULL,           NULL,           NULL,
16595 /* 6C */        NULL,           NULL,           NULL,           NULL,
16596 /* 70 */        NULL,           NULL,           NULL,           NULL,
16597 /* 74 */        NULL,           NULL,           NULL,           NULL,
16598 /* 78 */        NULL,           NULL,           NULL,           NULL,
16599 /* 7C */        NULL,           NULL,           NULL,           NULL,
16600 /* 80 */        NULL,           NULL,           NULL,           NULL,
16601 /* 84 */        NULL,           NULL,           NULL,           NULL,
16602 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16603 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16604 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16605 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16606 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16607 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16608 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16609 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16610 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16611 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16612 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16613 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16614 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16615 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16616 /* C0 */        NULL,           NULL,           NULL,           NULL,
16617 /* C4 */        NULL,           NULL,           NULL,           NULL,
16618 /* C8 */        NULL,           NULL,           NULL,           NULL,
16619 /* CC */        NULL,           NULL,           NULL,           NULL,
16620 /* D0 */        NULL,           NULL,           NULL,           NULL,
16621 /* D4 */        NULL,           NULL,           NULL,           NULL,
16622 /* D8 */        NULL,           NULL,           NULL,           NULL,
16623 /* DC */        NULL,           NULL,           NULL,           NULL,
16624 /* E0 */        NULL,           NULL,           NULL,           NULL,
16625 /* E4 */        NULL,           NULL,           NULL,           NULL,
16626 /* E8 */        NULL,           NULL,           NULL,           NULL,
16627 /* EC */        NULL,           NULL,           NULL,           NULL,
16628 /* F0 */        NULL,           NULL,           NULL,           NULL,
16629 /* F4 */        NULL,           NULL,           NULL,           NULL,
16630 /* F8 */        NULL,           NULL,           NULL,           NULL,
16631 /* FC */        NULL,           NULL,           NULL,           NULL,
16632 };
16633
16634 static void
16635 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16636 {
16637   const char *mnemonic;
16638
16639   FETCH_DATA (the_info, codep + 1);
16640   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16641      place where an 8-bit immediate would normally go.  ie. the last
16642      byte of the instruction.  */
16643   obufp = mnemonicendp;
16644   mnemonic = Suffix3DNow[*codep++ & 0xff];
16645   if (mnemonic)
16646     oappend (mnemonic);
16647   else
16648     {
16649       /* Since a variable sized modrm/sib chunk is between the start
16650          of the opcode (0x0f0f) and the opcode suffix, we need to do
16651          all the modrm processing first, and don't know until now that
16652          we have a bad opcode.  This necessitates some cleaning up.  */
16653       op_out[0][0] = '\0';
16654       op_out[1][0] = '\0';
16655       BadOp ();
16656     }
16657   mnemonicendp = obufp;
16658 }
16659
16660 static struct op simd_cmp_op[] =
16661 {
16662   { STRING_COMMA_LEN ("eq") },
16663   { STRING_COMMA_LEN ("lt") },
16664   { STRING_COMMA_LEN ("le") },
16665   { STRING_COMMA_LEN ("unord") },
16666   { STRING_COMMA_LEN ("neq") },
16667   { STRING_COMMA_LEN ("nlt") },
16668   { STRING_COMMA_LEN ("nle") },
16669   { STRING_COMMA_LEN ("ord") }
16670 };
16671
16672 static void
16673 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16674 {
16675   unsigned int cmp_type;
16676
16677   FETCH_DATA (the_info, codep + 1);
16678   cmp_type = *codep++ & 0xff;
16679   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16680     {
16681       char suffix [3];
16682       char *p = mnemonicendp - 2;
16683       suffix[0] = p[0];
16684       suffix[1] = p[1];
16685       suffix[2] = '\0';
16686       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16687       mnemonicendp += simd_cmp_op[cmp_type].len;
16688     }
16689   else
16690     {
16691       /* We have a reserved extension byte.  Output it directly.  */
16692       scratchbuf[0] = '$';
16693       print_operand_value (scratchbuf + 1, 1, cmp_type);
16694       oappend_maybe_intel (scratchbuf);
16695       scratchbuf[0] = '\0';
16696     }
16697 }
16698
16699 static void
16700 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16701           int sizeflag ATTRIBUTE_UNUSED)
16702 {
16703   /* mwaitx %eax,%ecx,%ebx */
16704   if (!intel_syntax)
16705     {
16706       const char **names = (address_mode == mode_64bit
16707                             ? names64 : names32);
16708       strcpy (op_out[0], names[0]);
16709       strcpy (op_out[1], names[1]);
16710       strcpy (op_out[2], names[3]);
16711       two_source_ops = 1;
16712     }
16713   /* Skip mod/rm byte.  */
16714   MODRM_CHECK;
16715   codep++;
16716 }
16717
16718 static void
16719 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16720           int sizeflag ATTRIBUTE_UNUSED)
16721 {
16722   /* mwait %eax,%ecx  */
16723   if (!intel_syntax)
16724     {
16725       const char **names = (address_mode == mode_64bit
16726                             ? names64 : names32);
16727       strcpy (op_out[0], names[0]);
16728       strcpy (op_out[1], names[1]);
16729       two_source_ops = 1;
16730     }
16731   /* Skip mod/rm byte.  */
16732   MODRM_CHECK;
16733   codep++;
16734 }
16735
16736 static void
16737 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16738             int sizeflag ATTRIBUTE_UNUSED)
16739 {
16740   /* monitor %eax,%ecx,%edx"  */
16741   if (!intel_syntax)
16742     {
16743       const char **op1_names;
16744       const char **names = (address_mode == mode_64bit
16745                             ? names64 : names32);
16746
16747       if (!(prefixes & PREFIX_ADDR))
16748         op1_names = (address_mode == mode_16bit
16749                      ? names16 : names);
16750       else
16751         {
16752           /* Remove "addr16/addr32".  */
16753           all_prefixes[last_addr_prefix] = 0;
16754           op1_names = (address_mode != mode_32bit
16755                        ? names32 : names16);
16756           used_prefixes |= PREFIX_ADDR;
16757         }
16758       strcpy (op_out[0], op1_names[0]);
16759       strcpy (op_out[1], names[1]);
16760       strcpy (op_out[2], names[2]);
16761       two_source_ops = 1;
16762     }
16763   /* Skip mod/rm byte.  */
16764   MODRM_CHECK;
16765   codep++;
16766 }
16767
16768 static void
16769 BadOp (void)
16770 {
16771   /* Throw away prefixes and 1st. opcode byte.  */
16772   codep = insn_codep + 1;
16773   oappend ("(bad)");
16774 }
16775
16776 static void
16777 REP_Fixup (int bytemode, int sizeflag)
16778 {
16779   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16780      lods and stos.  */
16781   if (prefixes & PREFIX_REPZ)
16782     all_prefixes[last_repz_prefix] = REP_PREFIX;
16783
16784   switch (bytemode)
16785     {
16786     case al_reg:
16787     case eAX_reg:
16788     case indir_dx_reg:
16789       OP_IMREG (bytemode, sizeflag);
16790       break;
16791     case eDI_reg:
16792       OP_ESreg (bytemode, sizeflag);
16793       break;
16794     case eSI_reg:
16795       OP_DSreg (bytemode, sizeflag);
16796       break;
16797     default:
16798       abort ();
16799       break;
16800     }
16801 }
16802
16803 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16804    "bnd".  */
16805
16806 static void
16807 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16808 {
16809   if (prefixes & PREFIX_REPNZ)
16810     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16811 }
16812
16813 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16814    "notrack".  */
16815
16816 static void
16817 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16818                int sizeflag ATTRIBUTE_UNUSED)
16819 {
16820   if (active_seg_prefix == PREFIX_DS
16821       && (address_mode != mode_64bit || last_data_prefix < 0))
16822     {
16823       /* NOTRACK prefix is only valid on indirect branch instructions
16824          and it must be the last prefix before REX prefix and opcode.
16825          NB: DATA prefix is unsupported for Intel64.  */
16826       if (last_active_prefix >= 0)
16827         {
16828           int notrack_prefix = last_active_prefix;
16829           if (last_rex_prefix == last_active_prefix)
16830             notrack_prefix--;
16831           if (all_prefixes[notrack_prefix] != NOTRACK_PREFIX_OPCODE)
16832             return;
16833         }
16834       active_seg_prefix = 0;
16835       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16836     }
16837 }
16838
16839 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16840    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16841  */
16842
16843 static void
16844 HLE_Fixup1 (int bytemode, int sizeflag)
16845 {
16846   if (modrm.mod != 3
16847       && (prefixes & PREFIX_LOCK) != 0)
16848     {
16849       if (prefixes & PREFIX_REPZ)
16850         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16851       if (prefixes & PREFIX_REPNZ)
16852         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16853     }
16854
16855   OP_E (bytemode, sizeflag);
16856 }
16857
16858 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16859    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16860  */
16861
16862 static void
16863 HLE_Fixup2 (int bytemode, int sizeflag)
16864 {
16865   if (modrm.mod != 3)
16866     {
16867       if (prefixes & PREFIX_REPZ)
16868         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16869       if (prefixes & PREFIX_REPNZ)
16870         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16871     }
16872
16873   OP_E (bytemode, sizeflag);
16874 }
16875
16876 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16877    "xrelease" for memory operand.  No check for LOCK prefix.   */
16878
16879 static void
16880 HLE_Fixup3 (int bytemode, int sizeflag)
16881 {
16882   if (modrm.mod != 3
16883       && last_repz_prefix > last_repnz_prefix
16884       && (prefixes & PREFIX_REPZ) != 0)
16885     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16886
16887   OP_E (bytemode, sizeflag);
16888 }
16889
16890 static void
16891 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16892 {
16893   USED_REX (REX_W);
16894   if (rex & REX_W)
16895     {
16896       /* Change cmpxchg8b to cmpxchg16b.  */
16897       char *p = mnemonicendp - 2;
16898       mnemonicendp = stpcpy (p, "16b");
16899       bytemode = o_mode;
16900     }
16901   else if ((prefixes & PREFIX_LOCK) != 0)
16902     {
16903       if (prefixes & PREFIX_REPZ)
16904         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16905       if (prefixes & PREFIX_REPNZ)
16906         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16907     }
16908
16909   OP_M (bytemode, sizeflag);
16910 }
16911
16912 static void
16913 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16914 {
16915   const char **names;
16916
16917   if (need_vex)
16918     {
16919       switch (vex.length)
16920         {
16921         case 128:
16922           names = names_xmm;
16923           break;
16924         case 256:
16925           names = names_ymm;
16926           break;
16927         default:
16928           abort ();
16929         }
16930     }
16931   else
16932     names = names_xmm;
16933   oappend (names[reg]);
16934 }
16935
16936 static void
16937 CRC32_Fixup (int bytemode, int sizeflag)
16938 {
16939   /* Add proper suffix to "crc32".  */
16940   char *p = mnemonicendp;
16941
16942   switch (bytemode)
16943     {
16944     case b_mode:
16945       if (intel_syntax)
16946         goto skip;
16947
16948       *p++ = 'b';
16949       break;
16950     case v_mode:
16951       if (intel_syntax)
16952         goto skip;
16953
16954       USED_REX (REX_W);
16955       if (rex & REX_W)
16956         *p++ = 'q';
16957       else
16958         {
16959           if (sizeflag & DFLAG)
16960             *p++ = 'l';
16961           else
16962             *p++ = 'w';
16963           used_prefixes |= (prefixes & PREFIX_DATA);
16964         }
16965       break;
16966     default:
16967       oappend (INTERNAL_DISASSEMBLER_ERROR);
16968       break;
16969     }
16970   mnemonicendp = p;
16971   *p = '\0';
16972
16973 skip:
16974   if (modrm.mod == 3)
16975     {
16976       int add;
16977
16978       /* Skip mod/rm byte.  */
16979       MODRM_CHECK;
16980       codep++;
16981
16982       USED_REX (REX_B);
16983       add = (rex & REX_B) ? 8 : 0;
16984       if (bytemode == b_mode)
16985         {
16986           USED_REX (0);
16987           if (rex)
16988             oappend (names8rex[modrm.rm + add]);
16989           else
16990             oappend (names8[modrm.rm + add]);
16991         }
16992       else
16993         {
16994           USED_REX (REX_W);
16995           if (rex & REX_W)
16996             oappend (names64[modrm.rm + add]);
16997           else if ((prefixes & PREFIX_DATA))
16998             oappend (names16[modrm.rm + add]);
16999           else
17000             oappend (names32[modrm.rm + add]);
17001         }
17002     }
17003   else
17004     OP_E (bytemode, sizeflag);
17005 }
17006
17007 static void
17008 FXSAVE_Fixup (int bytemode, int sizeflag)
17009 {
17010   /* Add proper suffix to "fxsave" and "fxrstor".  */
17011   USED_REX (REX_W);
17012   if (rex & REX_W)
17013     {
17014       char *p = mnemonicendp;
17015       *p++ = '6';
17016       *p++ = '4';
17017       *p = '\0';
17018       mnemonicendp = p;
17019     }
17020   OP_M (bytemode, sizeflag);
17021 }
17022
17023 static void
17024 PCMPESTR_Fixup (int bytemode, int sizeflag)
17025 {
17026   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17027   if (!intel_syntax)
17028     {
17029       char *p = mnemonicendp;
17030
17031       USED_REX (REX_W);
17032       if (rex & REX_W)
17033         *p++ = 'q';
17034       else if (sizeflag & SUFFIX_ALWAYS)
17035         *p++ = 'l';
17036
17037       *p = '\0';
17038       mnemonicendp = p;
17039     }
17040
17041   OP_EX (bytemode, sizeflag);
17042 }
17043
17044 /* Display the destination register operand for instructions with
17045    VEX. */
17046
17047 static void
17048 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17049 {
17050   int reg;
17051   const char **names;
17052
17053   if (!need_vex)
17054     abort ();
17055
17056   if (!need_vex_reg)
17057     return;
17058
17059   reg = vex.register_specifier;
17060   if (vex.evex)
17061     {
17062       if (!vex.v)
17063         reg += 16;
17064     }
17065
17066   if (bytemode == vex_scalar_mode)
17067     {
17068       oappend (names_xmm[reg]);
17069       return;
17070     }
17071
17072   switch (vex.length)
17073     {
17074     case 128:
17075       switch (bytemode)
17076         {
17077         case vex_mode:
17078         case vex128_mode:
17079         case vex_vsib_q_w_dq_mode:
17080         case vex_vsib_q_w_d_mode:
17081           names = names_xmm;
17082           break;
17083         case dq_mode:
17084           if (vex.w)
17085             names = names64;
17086           else
17087             names = names32;
17088           break;
17089         case mask_bd_mode:
17090         case mask_mode:
17091           if (reg > 0x7)
17092             {
17093               oappend ("(bad)");
17094               return;
17095             }
17096           names = names_mask;
17097           break;
17098         default:
17099           abort ();
17100           return;
17101         }
17102       break;
17103     case 256:
17104       switch (bytemode)
17105         {
17106         case vex_mode:
17107         case vex256_mode:
17108           names = names_ymm;
17109           break;
17110         case vex_vsib_q_w_dq_mode:
17111         case vex_vsib_q_w_d_mode:
17112           names = vex.w ? names_ymm : names_xmm;
17113           break;
17114         case mask_bd_mode:
17115         case mask_mode:
17116           if (reg > 0x7)
17117             {
17118               oappend ("(bad)");
17119               return;
17120             }
17121           names = names_mask;
17122           break;
17123         default:
17124           /* See PR binutils/20893 for a reproducer.  */
17125           oappend ("(bad)");
17126           return;
17127         }
17128       break;
17129     case 512:
17130       names = names_zmm;
17131       break;
17132     default:
17133       abort ();
17134       break;
17135     }
17136   oappend (names[reg]);
17137 }
17138
17139 /* Get the VEX immediate byte without moving codep.  */
17140
17141 static unsigned char
17142 get_vex_imm8 (int sizeflag, int opnum)
17143 {
17144   int bytes_before_imm = 0;
17145
17146   if (modrm.mod != 3)
17147     {
17148       /* There are SIB/displacement bytes.  */
17149       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17150         {
17151           /* 32/64 bit address mode */
17152           int base = modrm.rm;
17153
17154           /* Check SIB byte.  */
17155           if (base == 4)
17156             {
17157               FETCH_DATA (the_info, codep + 1);
17158               base = *codep & 7;
17159               /* When decoding the third source, don't increase
17160                  bytes_before_imm as this has already been incremented
17161                  by one in OP_E_memory while decoding the second
17162                  source operand.  */
17163               if (opnum == 0)
17164                 bytes_before_imm++;
17165             }
17166
17167           /* Don't increase bytes_before_imm when decoding the third source,
17168              it has already been incremented by OP_E_memory while decoding
17169              the second source operand.  */
17170           if (opnum == 0)
17171             {
17172               switch (modrm.mod)
17173                 {
17174                   case 0:
17175                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17176                        SIB == 5, there is a 4 byte displacement.  */
17177                     if (base != 5)
17178                       /* No displacement. */
17179                       break;
17180                     /* Fall through.  */
17181                   case 2:
17182                     /* 4 byte displacement.  */
17183                     bytes_before_imm += 4;
17184                     break;
17185                   case 1:
17186                     /* 1 byte displacement.  */
17187                     bytes_before_imm++;
17188                     break;
17189                 }
17190             }
17191         }
17192       else
17193         {
17194           /* 16 bit address mode */
17195           /* Don't increase bytes_before_imm when decoding the third source,
17196              it has already been incremented by OP_E_memory while decoding
17197              the second source operand.  */
17198           if (opnum == 0)
17199             {
17200               switch (modrm.mod)
17201                 {
17202                 case 0:
17203                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17204                   if (modrm.rm != 6)
17205                     /* No displacement. */
17206                     break;
17207                   /* Fall through.  */
17208                 case 2:
17209                   /* 2 byte displacement.  */
17210                   bytes_before_imm += 2;
17211                   break;
17212                 case 1:
17213                   /* 1 byte displacement: when decoding the third source,
17214                      don't increase bytes_before_imm as this has already
17215                      been incremented by one in OP_E_memory while decoding
17216                      the second source operand.  */
17217                   if (opnum == 0)
17218                     bytes_before_imm++;
17219
17220                   break;
17221                 }
17222             }
17223         }
17224     }
17225
17226   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17227   return codep [bytes_before_imm];
17228 }
17229
17230 static void
17231 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17232 {
17233   const char **names;
17234
17235   if (reg == -1 && modrm.mod != 3)
17236     {
17237       OP_E_memory (bytemode, sizeflag);
17238       return;
17239     }
17240   else
17241     {
17242       if (reg == -1)
17243         {
17244           reg = modrm.rm;
17245           USED_REX (REX_B);
17246           if (rex & REX_B)
17247             reg += 8;
17248         }
17249       else if (reg > 7 && address_mode != mode_64bit)
17250         BadOp ();
17251     }
17252
17253   switch (vex.length)
17254     {
17255     case 128:
17256       names = names_xmm;
17257       break;
17258     case 256:
17259       names = names_ymm;
17260       break;
17261     default:
17262       abort ();
17263     }
17264   oappend (names[reg]);
17265 }
17266
17267 static void
17268 OP_EX_VexImmW (int bytemode, int sizeflag)
17269 {
17270   int reg = -1;
17271   static unsigned char vex_imm8;
17272
17273   if (vex_w_done == 0)
17274     {
17275       vex_w_done = 1;
17276
17277       /* Skip mod/rm byte.  */
17278       MODRM_CHECK;
17279       codep++;
17280
17281       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17282
17283       if (vex.w)
17284           reg = vex_imm8 >> 4;
17285
17286       OP_EX_VexReg (bytemode, sizeflag, reg);
17287     }
17288   else if (vex_w_done == 1)
17289     {
17290       vex_w_done = 2;
17291
17292       if (!vex.w)
17293           reg = vex_imm8 >> 4;
17294
17295       OP_EX_VexReg (bytemode, sizeflag, reg);
17296     }
17297   else
17298     {
17299       /* Output the imm8 directly.  */
17300       scratchbuf[0] = '$';
17301       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17302       oappend_maybe_intel (scratchbuf);
17303       scratchbuf[0] = '\0';
17304       codep++;
17305     }
17306 }
17307
17308 static void
17309 OP_Vex_2src (int bytemode, int sizeflag)
17310 {
17311   if (modrm.mod == 3)
17312     {
17313       int reg = modrm.rm;
17314       USED_REX (REX_B);
17315       if (rex & REX_B)
17316         reg += 8;
17317       oappend (names_xmm[reg]);
17318     }
17319   else
17320     {
17321       if (intel_syntax
17322           && (bytemode == v_mode || bytemode == v_swap_mode))
17323         {
17324           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17325           used_prefixes |= (prefixes & PREFIX_DATA);
17326         }
17327       OP_E (bytemode, sizeflag);
17328     }
17329 }
17330
17331 static void
17332 OP_Vex_2src_1 (int bytemode, int sizeflag)
17333 {
17334   if (modrm.mod == 3)
17335     {
17336       /* Skip mod/rm byte.   */
17337       MODRM_CHECK;
17338       codep++;
17339     }
17340
17341   if (vex.w)
17342     oappend (names_xmm[vex.register_specifier]);
17343   else
17344     OP_Vex_2src (bytemode, sizeflag);
17345 }
17346
17347 static void
17348 OP_Vex_2src_2 (int bytemode, int sizeflag)
17349 {
17350   if (vex.w)
17351     OP_Vex_2src (bytemode, sizeflag);
17352   else
17353     oappend (names_xmm[vex.register_specifier]);
17354 }
17355
17356 static void
17357 OP_EX_VexW (int bytemode, int sizeflag)
17358 {
17359   int reg = -1;
17360
17361   if (!vex_w_done)
17362     {
17363       vex_w_done = 1;
17364
17365       /* Skip mod/rm byte.  */
17366       MODRM_CHECK;
17367       codep++;
17368
17369       if (vex.w)
17370         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17371     }
17372   else
17373     {
17374       if (!vex.w)
17375         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17376     }
17377
17378   OP_EX_VexReg (bytemode, sizeflag, reg);
17379 }
17380
17381 static void
17382 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17383              int sizeflag ATTRIBUTE_UNUSED)
17384 {
17385   /* Skip the immediate byte and check for invalid bits.  */
17386   FETCH_DATA (the_info, codep + 1);
17387   if (*codep++ & 0xf)
17388     BadOp ();
17389 }
17390
17391 static void
17392 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17393 {
17394   int reg;
17395   const char **names;
17396
17397   FETCH_DATA (the_info, codep + 1);
17398   reg = *codep++;
17399
17400   if (bytemode != x_mode)
17401     abort ();
17402
17403   if (reg & 0xf)
17404       BadOp ();
17405
17406   reg >>= 4;
17407   if (reg > 7 && address_mode != mode_64bit)
17408     BadOp ();
17409
17410   switch (vex.length)
17411     {
17412     case 128:
17413       names = names_xmm;
17414       break;
17415     case 256:
17416       names = names_ymm;
17417       break;
17418     default:
17419       abort ();
17420     }
17421   oappend (names[reg]);
17422 }
17423
17424 static void
17425 OP_XMM_VexW (int bytemode, int sizeflag)
17426 {
17427   /* Turn off the REX.W bit since it is used for swapping operands
17428      now.  */
17429   rex &= ~REX_W;
17430   OP_XMM (bytemode, sizeflag);
17431 }
17432
17433 static void
17434 OP_EX_Vex (int bytemode, int sizeflag)
17435 {
17436   if (modrm.mod != 3)
17437     {
17438       if (vex.register_specifier != 0)
17439         BadOp ();
17440       need_vex_reg = 0;
17441     }
17442   OP_EX (bytemode, sizeflag);
17443 }
17444
17445 static void
17446 OP_XMM_Vex (int bytemode, int sizeflag)
17447 {
17448   if (modrm.mod != 3)
17449     {
17450       if (vex.register_specifier != 0)
17451         BadOp ();
17452       need_vex_reg = 0;
17453     }
17454   OP_XMM (bytemode, sizeflag);
17455 }
17456
17457 static void
17458 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17459 {
17460   switch (vex.length)
17461     {
17462     case 128:
17463       mnemonicendp = stpcpy (obuf, "vzeroupper");
17464       break;
17465     case 256:
17466       mnemonicendp = stpcpy (obuf, "vzeroall");
17467       break;
17468     default:
17469       abort ();
17470     }
17471 }
17472
17473 static struct op vex_cmp_op[] =
17474 {
17475   { STRING_COMMA_LEN ("eq") },
17476   { STRING_COMMA_LEN ("lt") },
17477   { STRING_COMMA_LEN ("le") },
17478   { STRING_COMMA_LEN ("unord") },
17479   { STRING_COMMA_LEN ("neq") },
17480   { STRING_COMMA_LEN ("nlt") },
17481   { STRING_COMMA_LEN ("nle") },
17482   { STRING_COMMA_LEN ("ord") },
17483   { STRING_COMMA_LEN ("eq_uq") },
17484   { STRING_COMMA_LEN ("nge") },
17485   { STRING_COMMA_LEN ("ngt") },
17486   { STRING_COMMA_LEN ("false") },
17487   { STRING_COMMA_LEN ("neq_oq") },
17488   { STRING_COMMA_LEN ("ge") },
17489   { STRING_COMMA_LEN ("gt") },
17490   { STRING_COMMA_LEN ("true") },
17491   { STRING_COMMA_LEN ("eq_os") },
17492   { STRING_COMMA_LEN ("lt_oq") },
17493   { STRING_COMMA_LEN ("le_oq") },
17494   { STRING_COMMA_LEN ("unord_s") },
17495   { STRING_COMMA_LEN ("neq_us") },
17496   { STRING_COMMA_LEN ("nlt_uq") },
17497   { STRING_COMMA_LEN ("nle_uq") },
17498   { STRING_COMMA_LEN ("ord_s") },
17499   { STRING_COMMA_LEN ("eq_us") },
17500   { STRING_COMMA_LEN ("nge_uq") },
17501   { STRING_COMMA_LEN ("ngt_uq") },
17502   { STRING_COMMA_LEN ("false_os") },
17503   { STRING_COMMA_LEN ("neq_os") },
17504   { STRING_COMMA_LEN ("ge_oq") },
17505   { STRING_COMMA_LEN ("gt_oq") },
17506   { STRING_COMMA_LEN ("true_us") },
17507 };
17508
17509 static void
17510 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17511 {
17512   unsigned int cmp_type;
17513
17514   FETCH_DATA (the_info, codep + 1);
17515   cmp_type = *codep++ & 0xff;
17516   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17517     {
17518       char suffix [3];
17519       char *p = mnemonicendp - 2;
17520       suffix[0] = p[0];
17521       suffix[1] = p[1];
17522       suffix[2] = '\0';
17523       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17524       mnemonicendp += vex_cmp_op[cmp_type].len;
17525     }
17526   else
17527     {
17528       /* We have a reserved extension byte.  Output it directly.  */
17529       scratchbuf[0] = '$';
17530       print_operand_value (scratchbuf + 1, 1, cmp_type);
17531       oappend_maybe_intel (scratchbuf);
17532       scratchbuf[0] = '\0';
17533     }
17534 }
17535
17536 static void
17537 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17538              int sizeflag ATTRIBUTE_UNUSED)
17539 {
17540   unsigned int cmp_type;
17541
17542   if (!vex.evex)
17543     abort ();
17544
17545   FETCH_DATA (the_info, codep + 1);
17546   cmp_type = *codep++ & 0xff;
17547   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17548      If it's the case, print suffix, otherwise - print the immediate.  */
17549   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17550       && cmp_type != 3
17551       && cmp_type != 7)
17552     {
17553       char suffix [3];
17554       char *p = mnemonicendp - 2;
17555
17556       /* vpcmp* can have both one- and two-lettered suffix.  */
17557       if (p[0] == 'p')
17558         {
17559           p++;
17560           suffix[0] = p[0];
17561           suffix[1] = '\0';
17562         }
17563       else
17564         {
17565           suffix[0] = p[0];
17566           suffix[1] = p[1];
17567           suffix[2] = '\0';
17568         }
17569
17570       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17571       mnemonicendp += simd_cmp_op[cmp_type].len;
17572     }
17573   else
17574     {
17575       /* We have a reserved extension byte.  Output it directly.  */
17576       scratchbuf[0] = '$';
17577       print_operand_value (scratchbuf + 1, 1, cmp_type);
17578       oappend_maybe_intel (scratchbuf);
17579       scratchbuf[0] = '\0';
17580     }
17581 }
17582
17583 static const struct op pclmul_op[] =
17584 {
17585   { STRING_COMMA_LEN ("lql") },
17586   { STRING_COMMA_LEN ("hql") },
17587   { STRING_COMMA_LEN ("lqh") },
17588   { STRING_COMMA_LEN ("hqh") }
17589 };
17590
17591 static void
17592 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17593               int sizeflag ATTRIBUTE_UNUSED)
17594 {
17595   unsigned int pclmul_type;
17596
17597   FETCH_DATA (the_info, codep + 1);
17598   pclmul_type = *codep++ & 0xff;
17599   switch (pclmul_type)
17600     {
17601     case 0x10:
17602       pclmul_type = 2;
17603       break;
17604     case 0x11:
17605       pclmul_type = 3;
17606       break;
17607     default:
17608       break;
17609     }
17610   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17611     {
17612       char suffix [4];
17613       char *p = mnemonicendp - 3;
17614       suffix[0] = p[0];
17615       suffix[1] = p[1];
17616       suffix[2] = p[2];
17617       suffix[3] = '\0';
17618       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17619       mnemonicendp += pclmul_op[pclmul_type].len;
17620     }
17621   else
17622     {
17623       /* We have a reserved extension byte.  Output it directly.  */
17624       scratchbuf[0] = '$';
17625       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17626       oappend_maybe_intel (scratchbuf);
17627       scratchbuf[0] = '\0';
17628     }
17629 }
17630
17631 static void
17632 MOVBE_Fixup (int bytemode, int sizeflag)
17633 {
17634   /* Add proper suffix to "movbe".  */
17635   char *p = mnemonicendp;
17636
17637   switch (bytemode)
17638     {
17639     case v_mode:
17640       if (intel_syntax)
17641         goto skip;
17642
17643       USED_REX (REX_W);
17644       if (sizeflag & SUFFIX_ALWAYS)
17645         {
17646           if (rex & REX_W)
17647             *p++ = 'q';
17648           else
17649             {
17650               if (sizeflag & DFLAG)
17651                 *p++ = 'l';
17652               else
17653                 *p++ = 'w';
17654               used_prefixes |= (prefixes & PREFIX_DATA);
17655             }
17656         }
17657       break;
17658     default:
17659       oappend (INTERNAL_DISASSEMBLER_ERROR);
17660       break;
17661     }
17662   mnemonicendp = p;
17663   *p = '\0';
17664
17665 skip:
17666   OP_M (bytemode, sizeflag);
17667 }
17668
17669 static void
17670 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17671 {
17672   int reg;
17673   const char **names;
17674
17675   /* Skip mod/rm byte.  */
17676   MODRM_CHECK;
17677   codep++;
17678
17679   if (vex.w)
17680     names = names64;
17681   else
17682     names = names32;
17683
17684   reg = modrm.rm;
17685   USED_REX (REX_B);
17686   if (rex & REX_B)
17687     reg += 8;
17688
17689   oappend (names[reg]);
17690 }
17691
17692 static void
17693 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17694 {
17695   const char **names;
17696
17697   if (vex.w)
17698     names = names64;
17699   else
17700     names = names32;
17701
17702   oappend (names[vex.register_specifier]);
17703 }
17704
17705 static void
17706 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17707 {
17708   if (!vex.evex
17709       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17710     abort ();
17711
17712   USED_REX (REX_R);
17713   if ((rex & REX_R) != 0 || !vex.r)
17714     {
17715       BadOp ();
17716       return;
17717     }
17718
17719   oappend (names_mask [modrm.reg]);
17720 }
17721
17722 static void
17723 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17724 {
17725   if (!vex.evex
17726       || (bytemode != evex_rounding_mode
17727           && bytemode != evex_sae_mode))
17728     abort ();
17729   if (modrm.mod == 3 && vex.b)
17730     switch (bytemode)
17731       {
17732       case evex_rounding_mode:
17733         oappend (names_rounding[vex.ll]);
17734         break;
17735       case evex_sae_mode:
17736         oappend ("{sae}");
17737         break;
17738       default:
17739         break;
17740       }
17741 }