opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 #include <setjmp.h>
  43
  44 static int print_insn (bfd_vma, disassemble_info *);
  45 static void dofloat (int);
  46 static void OP_ST (int, int);
  47 static void OP_STi (int, int);
  48 static int putop (const char *, int);
  49 static void oappend (const char *);
  50 static void append_seg (void);
  51 static void OP_indirE (int, int);
  52 static void print_operand_value (char *, int, bfd_vma);
  53 static void OP_E_register (int, int);
  54 static void OP_E_memory (int, int);
  55 static void print_displacement (char *, bfd_vma);
  56 static void OP_E (int, int);
  57 static void OP_G (int, int);
  58 static bfd_vma get64 (void);
  59 static bfd_signed_vma get32 (void);
  60 static bfd_signed_vma get32s (void);
  61 static int get16 (void);
  62 static void set_op (bfd_vma, int);
  63 static void OP_Skip_MODRM (int, int);
  64 static void OP_REG (int, int);
  65 static void OP_IMREG (int, int);
  66 static void OP_I (int, int);
  67 static void OP_I64 (int, int);
  68 static void OP_sI (int, int);
  69 static void OP_J (int, int);
  70 static void OP_SEG (int, int);
  71 static void OP_DIR (int, int);
  72 static void OP_OFF (int, int);
  73 static void OP_OFF64 (int, int);
  74 static void ptr_reg (int, int);
  75 static void OP_ESreg (int, int);
  76 static void OP_DSreg (int, int);
  77 static void OP_C (int, int);
  78 static void OP_D (int, int);
  79 static void OP_T (int, int);
  80 static void OP_R (int, int);
  81 static void OP_MMX (int, int);
  82 static void OP_XMM (int, int);
  83 static void OP_EM (int, int);
  84 static void OP_EX (int, int);
  85 static void OP_EMC (int,int);
  86 static void OP_MXC (int,int);
  87 static void OP_MS (int, int);
  88 static void OP_XS (int, int);
  89 static void OP_M (int, int);
  90 static void OP_VEX (int, int);
  91 static void OP_VexW (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_Rounding (int, int);
  95 static void OP_REG_VexI4 (int, int);
  96 static void OP_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void FXSAVE_Fixup (int, int);
 119 static void PCMPESTR_Fixup (int, int);
 120
 121 static void MOVBE_Fixup (int, int);
 122 static void MOVSXD_Fixup (int, int);
 123
 124 static void OP_Mask (int, int);
 125
 126 struct dis_private {
 127   /* Points to first byte not fetched.  */
 128   bfd_byte *max_fetched;
 129   bfd_byte the_buffer[MAX_MNEM_SIZE];
 130   bfd_vma insn_start;
 131   int orig_sizeflag;
 132   OPCODES_SIGJMP_BUF bailout;
 133 };
 134
 135 enum address_mode
 136 {
 137   mode_16bit,
 138   mode_32bit,
 139   mode_64bit
 140 };
 141
 142 enum address_mode address_mode;
 143
 144 /* Flags for the prefixes for the current instruction.  See below.  */
 145 static int prefixes;
 146
 147 /* REX prefix the current instruction.  See below.  */
 148 static int rex;
 149 /* Bits of REX we've already used.  */
 150 static int rex_used;
 151 /* Mark parts used in the REX prefix.  When we are testing for
 152    empty prefix (for 8bit register REX extension), just mask it
 153    out.  Otherwise test for REX bit is excuse for existence of REX
 154    only in case value is nonzero.  */
 155 #define USED_REX(value)                                 \
 156   {                                                     \
 157     if (value)                                          \
 158       {                                                 \
 159         if ((rex & value))                              \
 160           rex_used |= (value) | REX_OPCODE;             \
 161       }                                                 \
 162     else                                                \
 163       rex_used |= REX_OPCODE;                           \
 164   }
 165
 166 /* Flags for prefixes which we somehow handled when printing the
 167    current instruction.  */
 168 static int used_prefixes;
 169
 170 /* Flags stored in PREFIXES.  */
 171 #define PREFIX_REPZ 1
 172 #define PREFIX_REPNZ 2
 173 #define PREFIX_LOCK 4
 174 #define PREFIX_CS 8
 175 #define PREFIX_SS 0x10
 176 #define PREFIX_DS 0x20
 177 #define PREFIX_ES 0x40
 178 #define PREFIX_FS 0x80
 179 #define PREFIX_GS 0x100
 180 #define PREFIX_DATA 0x200
 181 #define PREFIX_ADDR 0x400
 182 #define PREFIX_FWAIT 0x800
 183
 184 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 185    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 186    on error.  */
 187 #define FETCH_DATA(info, addr) \
 188   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 189    ? 1 : fetch_data ((info), (addr)))
 190
 191 static int
 192 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 193 {
 194   int status;
 195   struct dis_private *priv = (struct dis_private *) info->private_data;
 196   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 197
 198   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 199     status = (*info->read_memory_func) (start,
 200                                         priv->max_fetched,
 201                                         addr - priv->max_fetched,
 202                                         info);
 203   else
 204     status = -1;
 205   if (status != 0)
 206     {
 207       /* If we did manage to read at least one byte, then
 208          print_insn_i386 will do something sensible.  Otherwise, print
 209          an error.  We do that here because this is where we know
 210          STATUS.  */
 211       if (priv->max_fetched == priv->the_buffer)
 212         (*info->memory_error_func) (status, start, info);
 213       OPCODES_SIGLONGJMP (priv->bailout, 1);
 214     }
 215   else
 216     priv->max_fetched = addr;
 217   return 1;
 218 }
 219
 220 /* Possible values for prefix requirement.  */
 221 #define PREFIX_IGNORED_SHIFT    16
 222 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 223 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 224 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 225 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 226 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 227
 228 /* Opcode prefixes.  */
 229 #define PREFIX_OPCODE           (PREFIX_REPZ \
 230                                  | PREFIX_REPNZ \
 231                                  | PREFIX_DATA)
 232
 233 /* Prefixes ignored.  */
 234 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 235                                  | PREFIX_IGNORED_REPNZ \
 236                                  | PREFIX_IGNORED_DATA)
 237
 238 #define XX { NULL, 0 }
 239 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 240
 241 #define Eb { OP_E, b_mode }
 242 #define Ebnd { OP_E, bnd_mode }
 243 #define EbS { OP_E, b_swap_mode }
 244 #define EbndS { OP_E, bnd_swap_mode }
 245 #define Ev { OP_E, v_mode }
 246 #define Eva { OP_E, va_mode }
 247 #define Ev_bnd { OP_E, v_bnd_mode }
 248 #define EvS { OP_E, v_swap_mode }
 249 #define Ed { OP_E, d_mode }
 250 #define Edq { OP_E, dq_mode }
 251 #define Edqw { OP_E, dqw_mode }
 252 #define Edqb { OP_E, dqb_mode }
 253 #define Edb { OP_E, db_mode }
 254 #define Edw { OP_E, dw_mode }
 255 #define Edqd { OP_E, dqd_mode }
 256 #define Eq { OP_E, q_mode }
 257 #define indirEv { OP_indirE, indir_v_mode }
 258 #define indirEp { OP_indirE, f_mode }
 259 #define stackEv { OP_E, stack_v_mode }
 260 #define Em { OP_E, m_mode }
 261 #define Ew { OP_E, w_mode }
 262 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 263 #define Ma { OP_M, a_mode }
 264 #define Mb { OP_M, b_mode }
 265 #define Md { OP_M, d_mode }
 266 #define Mo { OP_M, o_mode }
 267 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 268 #define Mq { OP_M, q_mode }
 269 #define Mv_bnd { OP_M, v_bndmk_mode }
 270 #define Mx { OP_M, x_mode }
 271 #define Mxmm { OP_M, xmm_mode }
 272 #define Gb { OP_G, b_mode }
 273 #define Gbnd { OP_G, bnd_mode }
 274 #define Gv { OP_G, v_mode }
 275 #define Gd { OP_G, d_mode }
 276 #define Gdq { OP_G, dq_mode }
 277 #define Gm { OP_G, m_mode }
 278 #define Gva { OP_G, va_mode }
 279 #define Gw { OP_G, w_mode }
 280 #define Rd { OP_R, d_mode }
 281 #define Rdq { OP_R, dq_mode }
 282 #define Rm { OP_R, m_mode }
 283 #define Ib { OP_I, b_mode }
 284 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 285 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 286 #define Iv { OP_I, v_mode }
 287 #define sIv { OP_sI, v_mode }
 288 #define Iv64 { OP_I64, v_mode }
 289 #define Id { OP_I, d_mode }
 290 #define Iw { OP_I, w_mode }
 291 #define I1 { OP_I, const_1_mode }
 292 #define Jb { OP_J, b_mode }
 293 #define Jv { OP_J, v_mode }
 294 #define Jdqw { OP_J, dqw_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define AL { OP_IMREG, al_reg }
 329 #define CL { OP_IMREG, cl_reg }
 330 #define zAX { OP_IMREG, z_mode_ax_reg }
 331 #define indirDX { OP_IMREG, indir_dx_reg }
 332
 333 #define Sw { OP_SEG, w_mode }
 334 #define Sv { OP_SEG, v_mode }
 335 #define Ap { OP_DIR, 0 }
 336 #define Ob { OP_OFF64, b_mode }
 337 #define Ov { OP_OFF64, v_mode }
 338 #define Xb { OP_DSreg, eSI_reg }
 339 #define Xv { OP_DSreg, eSI_reg }
 340 #define Xz { OP_DSreg, eSI_reg }
 341 #define Yb { OP_ESreg, eDI_reg }
 342 #define Yv { OP_ESreg, eDI_reg }
 343 #define DSBX { OP_DSreg, eBX_reg }
 344
 345 #define es { OP_REG, es_reg }
 346 #define ss { OP_REG, ss_reg }
 347 #define cs { OP_REG, cs_reg }
 348 #define ds { OP_REG, ds_reg }
 349 #define fs { OP_REG, fs_reg }
 350 #define gs { OP_REG, gs_reg }
 351
 352 #define MX { OP_MMX, 0 }
 353 #define XM { OP_XMM, 0 }
 354 #define XMScalar { OP_XMM, scalar_mode }
 355 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 356 #define XMM { OP_XMM, xmm_mode }
 357 #define TMM { OP_XMM, tmm_mode }
 358 #define XMxmmq { OP_XMM, xmmq_mode }
 359 #define EM { OP_EM, v_mode }
 360 #define EMS { OP_EM, v_swap_mode }
 361 #define EMd { OP_EM, d_mode }
 362 #define EMx { OP_EM, x_mode }
 363 #define EXbScalar { OP_EX, b_scalar_mode }
 364 #define EXw { OP_EX, w_mode }
 365 #define EXwScalar { OP_EX, w_scalar_mode }
 366 #define EXd { OP_EX, d_mode }
 367 #define EXdS { OP_EX, d_swap_mode }
 368 #define EXq { OP_EX, q_mode }
 369 #define EXqS { OP_EX, q_swap_mode }
 370 #define EXx { OP_EX, x_mode }
 371 #define EXxS { OP_EX, x_swap_mode }
 372 #define EXxmm { OP_EX, xmm_mode }
 373 #define EXymm { OP_EX, ymm_mode }
 374 #define EXtmm { OP_EX, tmm_mode }
 375 #define EXxmmq { OP_EX, xmmq_mode }
 376 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 377 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 378 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 379 #define EXxmm_md { OP_EX, xmm_md_mode }
 380 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 381 #define EXxmmdw { OP_EX, xmmdw_mode }
 382 #define EXxmmqd { OP_EX, xmmqd_mode }
 383 #define EXymmq { OP_EX, ymmq_mode }
 384 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 385 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 386 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 387 #define MS { OP_MS, v_mode }
 388 #define XS { OP_XS, v_mode }
 389 #define EMCq { OP_EMC, q_mode }
 390 #define MXC { OP_MXC, 0 }
 391 #define OPSUF { OP_3DNowSuffix, 0 }
 392 #define SEP { SEP_Fixup, 0 }
 393 #define CMP { CMP_Fixup, 0 }
 394 #define XMM0 { XMM_Fixup, 0 }
 395 #define FXSAVE { FXSAVE_Fixup, 0 }
 396
 397 #define Vex { OP_VEX, vex_mode }
 398 #define VexW { OP_VexW, vex_mode }
 399 #define VexScalar { OP_VEX, vex_scalar_mode }
 400 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 401 #define Vex128 { OP_VEX, vex128_mode }
 402 #define Vex256 { OP_VEX, vex256_mode }
 403 #define VexGdq { OP_VEX, dq_mode }
 404 #define VexTmm { OP_VEX, tmm_mode }
 405 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 407 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 408 #define XMVexI4 { OP_REG_VexI4, x_mode }
 409 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 410 #define VexI4 { OP_VexI4, 0 }
 411 #define PCLMUL { PCLMUL_Fixup, 0 }
 412 #define VCMP { VCMP_Fixup, 0 }
 413 #define VPCMP { VPCMP_Fixup, 0 }
 414 #define VPCOM { VPCOM_Fixup, 0 }
 415
 416 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 417 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 418 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 419
 420 #define XMask { OP_Mask, mask_mode }
 421 #define MaskG { OP_G, mask_mode }
 422 #define MaskE { OP_E, mask_mode }
 423 #define MaskBDE { OP_E, mask_bd_mode }
 424 #define MaskR { OP_R, mask_mode }
 425 #define MaskVex { OP_VEX, mask_mode }
 426
 427 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 428 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 429 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 430 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 431
 432 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 433
 434 /* Used handle "rep" prefix for string instructions.  */
 435 #define Xbr { REP_Fixup, eSI_reg }
 436 #define Xvr { REP_Fixup, eSI_reg }
 437 #define Ybr { REP_Fixup, eDI_reg }
 438 #define Yvr { REP_Fixup, eDI_reg }
 439 #define Yzr { REP_Fixup, eDI_reg }
 440 #define indirDXr { REP_Fixup, indir_dx_reg }
 441 #define ALr { REP_Fixup, al_reg }
 442 #define eAXr { REP_Fixup, eAX_reg }
 443
 444 /* Used handle HLE prefix for lockable instructions.  */
 445 #define Ebh1 { HLE_Fixup1, b_mode }
 446 #define Evh1 { HLE_Fixup1, v_mode }
 447 #define Ebh2 { HLE_Fixup2, b_mode }
 448 #define Evh2 { HLE_Fixup2, v_mode }
 449 #define Ebh3 { HLE_Fixup3, b_mode }
 450 #define Evh3 { HLE_Fixup3, v_mode }
 451
 452 #define BND { BND_Fixup, 0 }
 453 #define NOTRACK { NOTRACK_Fixup, 0 }
 454
 455 #define cond_jump_flag { NULL, cond_jump_mode }
 456 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 457
 458 /* bits in sizeflag */
 459 #define SUFFIX_ALWAYS 4
 460 #define AFLAG 2
 461 #define DFLAG 1
 462
 463 enum
 464 {
 465   /* byte operand */
 466   b_mode = 1,
 467   /* byte operand with operand swapped */
 468   b_swap_mode,
 469   /* byte operand, sign extend like 'T' suffix */
 470   b_T_mode,
 471   /* operand size depends on prefixes */
 472   v_mode,
 473   /* operand size depends on prefixes with operand swapped */
 474   v_swap_mode,
 475   /* operand size depends on address prefix */
 476   va_mode,
 477   /* word operand */
 478   w_mode,
 479   /* double word operand  */
 480   d_mode,
 481   /* double word operand with operand swapped */
 482   d_swap_mode,
 483   /* quad word operand */
 484   q_mode,
 485   /* quad word operand with operand swapped */
 486   q_swap_mode,
 487   /* ten-byte operand */
 488   t_mode,
 489   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 490      broadcast enabled.  */
 491   x_mode,
 492   /* Similar to x_mode, but with different EVEX mem shifts.  */
 493   evex_x_gscat_mode,
 494   /* Similar to x_mode, but with disabled broadcast.  */
 495   evex_x_nobcst_mode,
 496   /* Similar to x_mode, but with operands swapped and disabled broadcast
 497      in EVEX.  */
 498   x_swap_mode,
 499   /* 16-byte XMM operand */
 500   xmm_mode,
 501   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 502      memory operand (depending on vector length).  Broadcast isn't
 503      allowed.  */
 504   xmmq_mode,
 505   /* Same as xmmq_mode, but broadcast is allowed.  */
 506   evex_half_bcst_xmmq_mode,
 507   /* XMM register or byte memory operand */
 508   xmm_mb_mode,
 509   /* XMM register or word memory operand */
 510   xmm_mw_mode,
 511   /* XMM register or double word memory operand */
 512   xmm_md_mode,
 513   /* XMM register or quad word memory operand */
 514   xmm_mq_mode,
 515   /* 16-byte XMM, word, double word or quad word operand.  */
 516   xmmdw_mode,
 517   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 518   xmmqd_mode,
 519   /* 32-byte YMM operand */
 520   ymm_mode,
 521   /* quad word, ymmword or zmmword memory operand.  */
 522   ymmq_mode,
 523   /* 32-byte YMM or 16-byte word operand */
 524   ymmxmm_mode,
 525   /* TMM operand */
 526   tmm_mode,
 527   /* d_mode in 32bit, q_mode in 64bit mode.  */
 528   m_mode,
 529   /* pair of v_mode operands */
 530   a_mode,
 531   cond_jump_mode,
 532   loop_jcxz_mode,
 533   movsxd_mode,
 534   v_bnd_mode,
 535   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 536   v_bndmk_mode,
 537   /* operand size depends on REX prefixes.  */
 538   dq_mode,
 539   /* registers like dq_mode, memory like w_mode, displacements like
 540      v_mode without considering Intel64 ISA.  */
 541   dqw_mode,
 542   /* bounds operand */
 543   bnd_mode,
 544   /* bounds operand with operand swapped */
 545   bnd_swap_mode,
 546   /* 4- or 6-byte pointer operand */
 547   f_mode,
 548   const_1_mode,
 549   /* v_mode for indirect branch opcodes.  */
 550   indir_v_mode,
 551   /* v_mode for stack-related opcodes.  */
 552   stack_v_mode,
 553   /* non-quad operand size depends on prefixes */
 554   z_mode,
 555   /* 16-byte operand */
 556   o_mode,
 557   /* registers like dq_mode, memory like b_mode.  */
 558   dqb_mode,
 559   /* registers like d_mode, memory like b_mode.  */
 560   db_mode,
 561   /* registers like d_mode, memory like w_mode.  */
 562   dw_mode,
 563   /* registers like dq_mode, memory like d_mode.  */
 564   dqd_mode,
 565   /* normal vex mode */
 566   vex_mode,
 567   /* 128bit vex mode */
 568   vex128_mode,
 569   /* 256bit vex mode */
 570   vex256_mode,
 571
 572   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 573   vex_vsib_d_w_dq_mode,
 574   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 575   vex_vsib_d_w_d_mode,
 576   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 577   vex_vsib_q_w_dq_mode,
 578   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 579   vex_vsib_q_w_d_mode,
 580   /* mandatory non-vector SIB.  */
 581   vex_sibmem_mode,
 582
 583   /* scalar, ignore vector length.  */
 584   scalar_mode,
 585   /* like b_mode, ignore vector length.  */
 586   b_scalar_mode,
 587   /* like w_mode, ignore vector length.  */
 588   w_scalar_mode,
 589   /* like d_swap_mode, ignore vector length.  */
 590   d_scalar_swap_mode,
 591   /* like q_swap_mode, ignore vector length.  */
 592   q_scalar_swap_mode,
 593   /* like vex_mode, ignore vector length.  */
 594   vex_scalar_mode,
 595   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 596   vex_scalar_w_dq_mode,
 597
 598   /* Static rounding.  */
 599   evex_rounding_mode,
 600   /* Static rounding, 64-bit mode only.  */
 601   evex_rounding_64_mode,
 602   /* Supress all exceptions.  */
 603   evex_sae_mode,
 604
 605   /* Mask register operand.  */
 606   mask_mode,
 607   /* Mask register operand.  */
 608   mask_bd_mode,
 609
 610   es_reg,
 611   cs_reg,
 612   ss_reg,
 613   ds_reg,
 614   fs_reg,
 615   gs_reg,
 616
 617   eAX_reg,
 618   eCX_reg,
 619   eDX_reg,
 620   eBX_reg,
 621   eSP_reg,
 622   eBP_reg,
 623   eSI_reg,
 624   eDI_reg,
 625
 626   al_reg,
 627   cl_reg,
 628   dl_reg,
 629   bl_reg,
 630   ah_reg,
 631   ch_reg,
 632   dh_reg,
 633   bh_reg,
 634
 635   ax_reg,
 636   cx_reg,
 637   dx_reg,
 638   bx_reg,
 639   sp_reg,
 640   bp_reg,
 641   si_reg,
 642   di_reg,
 643
 644   rAX_reg,
 645   rCX_reg,
 646   rDX_reg,
 647   rBX_reg,
 648   rSP_reg,
 649   rBP_reg,
 650   rSI_reg,
 651   rDI_reg,
 652
 653   z_mode_ax_reg,
 654   indir_dx_reg
 655 };
 656
 657 enum
 658 {
 659   FLOATCODE = 1,
 660   USE_REG_TABLE,
 661   USE_MOD_TABLE,
 662   USE_RM_TABLE,
 663   USE_PREFIX_TABLE,
 664   USE_X86_64_TABLE,
 665   USE_3BYTE_TABLE,
 666   USE_XOP_8F_TABLE,
 667   USE_VEX_C4_TABLE,
 668   USE_VEX_C5_TABLE,
 669   USE_VEX_LEN_TABLE,
 670   USE_VEX_W_TABLE,
 671   USE_EVEX_TABLE,
 672   USE_EVEX_LEN_TABLE
 673 };
 674
 675 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 676
 677 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 678 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 679 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 680 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 681 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 682 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 683 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 684 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 685 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 686 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 687 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 688 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 689 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 690 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 691 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 692 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 693
 694 enum
 695 {
 696   REG_80 = 0,
 697   REG_81,
 698   REG_83,
 699   REG_8F,
 700   REG_C0,
 701   REG_C1,
 702   REG_C6,
 703   REG_C7,
 704   REG_D0,
 705   REG_D1,
 706   REG_D2,
 707   REG_D3,
 708   REG_F6,
 709   REG_F7,
 710   REG_FE,
 711   REG_FF,
 712   REG_0F00,
 713   REG_0F01,
 714   REG_0F0D,
 715   REG_0F18,
 716   REG_0F1C_P_0_MOD_0,
 717   REG_0F1E_P_1_MOD_3,
 718   REG_0F71,
 719   REG_0F72,
 720   REG_0F73,
 721   REG_0FA6,
 722   REG_0FA7,
 723   REG_0FAE,
 724   REG_0FBA,
 725   REG_0FC7,
 726   REG_VEX_0F71,
 727   REG_VEX_0F72,
 728   REG_VEX_0F73,
 729   REG_VEX_0FAE,
 730   REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
 731   REG_VEX_0F38F3,
 732
 733   REG_0FXOP_09_01_L_0,
 734   REG_0FXOP_09_02_L_0,
 735   REG_0FXOP_09_12_M_1_L_0,
 736   REG_0FXOP_0A_12_L_0,
 737
 738   REG_EVEX_0F71,
 739   REG_EVEX_0F72,
 740   REG_EVEX_0F73,
 741   REG_EVEX_0F38C6,
 742   REG_EVEX_0F38C7
 743 };
 744
 745 enum
 746 {
 747   MOD_8D = 0,
 748   MOD_C6_REG_7,
 749   MOD_C7_REG_7,
 750   MOD_FF_REG_3,
 751   MOD_FF_REG_5,
 752   MOD_0F01_REG_0,
 753   MOD_0F01_REG_1,
 754   MOD_0F01_REG_2,
 755   MOD_0F01_REG_3,
 756   MOD_0F01_REG_5,
 757   MOD_0F01_REG_7,
 758   MOD_0F12_PREFIX_0,
 759   MOD_0F12_PREFIX_2,
 760   MOD_0F13,
 761   MOD_0F16_PREFIX_0,
 762   MOD_0F16_PREFIX_2,
 763   MOD_0F17,
 764   MOD_0F18_REG_0,
 765   MOD_0F18_REG_1,
 766   MOD_0F18_REG_2,
 767   MOD_0F18_REG_3,
 768   MOD_0F18_REG_4,
 769   MOD_0F18_REG_5,
 770   MOD_0F18_REG_6,
 771   MOD_0F18_REG_7,
 772   MOD_0F1A_PREFIX_0,
 773   MOD_0F1B_PREFIX_0,
 774   MOD_0F1B_PREFIX_1,
 775   MOD_0F1C_PREFIX_0,
 776   MOD_0F1E_PREFIX_1,
 777   MOD_0F24,
 778   MOD_0F26,
 779   MOD_0F2B_PREFIX_0,
 780   MOD_0F2B_PREFIX_1,
 781   MOD_0F2B_PREFIX_2,
 782   MOD_0F2B_PREFIX_3,
 783   MOD_0F50,
 784   MOD_0F71_REG_2,
 785   MOD_0F71_REG_4,
 786   MOD_0F71_REG_6,
 787   MOD_0F72_REG_2,
 788   MOD_0F72_REG_4,
 789   MOD_0F72_REG_6,
 790   MOD_0F73_REG_2,
 791   MOD_0F73_REG_3,
 792   MOD_0F73_REG_6,
 793   MOD_0F73_REG_7,
 794   MOD_0FAE_REG_0,
 795   MOD_0FAE_REG_1,
 796   MOD_0FAE_REG_2,
 797   MOD_0FAE_REG_3,
 798   MOD_0FAE_REG_4,
 799   MOD_0FAE_REG_5,
 800   MOD_0FAE_REG_6,
 801   MOD_0FAE_REG_7,
 802   MOD_0FB2,
 803   MOD_0FB4,
 804   MOD_0FB5,
 805   MOD_0FC3,
 806   MOD_0FC7_REG_3,
 807   MOD_0FC7_REG_4,
 808   MOD_0FC7_REG_5,
 809   MOD_0FC7_REG_6,
 810   MOD_0FC7_REG_7,
 811   MOD_0FD7,
 812   MOD_0FE7_PREFIX_2,
 813   MOD_0FF0_PREFIX_3,
 814   MOD_0F382A_PREFIX_2,
 815   MOD_VEX_0F3849_X86_64_P_0_W_0,
 816   MOD_VEX_0F3849_X86_64_P_2_W_0,
 817   MOD_VEX_0F3849_X86_64_P_3_W_0,
 818   MOD_VEX_0F384B_X86_64_P_1_W_0,
 819   MOD_VEX_0F384B_X86_64_P_2_W_0,
 820   MOD_VEX_0F384B_X86_64_P_3_W_0,
 821   MOD_VEX_0F385C_X86_64_P_1_W_0,
 822   MOD_VEX_0F385E_X86_64_P_0_W_0,
 823   MOD_VEX_0F385E_X86_64_P_1_W_0,
 824   MOD_VEX_0F385E_X86_64_P_2_W_0,
 825   MOD_VEX_0F385E_X86_64_P_3_W_0,
 826   MOD_0F38F5_PREFIX_2,
 827   MOD_0F38F6_PREFIX_0,
 828   MOD_0F38F8_PREFIX_1,
 829   MOD_0F38F8_PREFIX_2,
 830   MOD_0F38F8_PREFIX_3,
 831   MOD_0F38F9_PREFIX_0,
 832   MOD_62_32BIT,
 833   MOD_C4_32BIT,
 834   MOD_C5_32BIT,
 835   MOD_VEX_0F12_PREFIX_0,
 836   MOD_VEX_0F12_PREFIX_2,
 837   MOD_VEX_0F13,
 838   MOD_VEX_0F16_PREFIX_0,
 839   MOD_VEX_0F16_PREFIX_2,
 840   MOD_VEX_0F17,
 841   MOD_VEX_0F2B,
 842   MOD_VEX_W_0_0F41_P_0_LEN_1,
 843   MOD_VEX_W_1_0F41_P_0_LEN_1,
 844   MOD_VEX_W_0_0F41_P_2_LEN_1,
 845   MOD_VEX_W_1_0F41_P_2_LEN_1,
 846   MOD_VEX_W_0_0F42_P_0_LEN_1,
 847   MOD_VEX_W_1_0F42_P_0_LEN_1,
 848   MOD_VEX_W_0_0F42_P_2_LEN_1,
 849   MOD_VEX_W_1_0F42_P_2_LEN_1,
 850   MOD_VEX_W_0_0F44_P_0_LEN_1,
 851   MOD_VEX_W_1_0F44_P_0_LEN_1,
 852   MOD_VEX_W_0_0F44_P_2_LEN_1,
 853   MOD_VEX_W_1_0F44_P_2_LEN_1,
 854   MOD_VEX_W_0_0F45_P_0_LEN_1,
 855   MOD_VEX_W_1_0F45_P_0_LEN_1,
 856   MOD_VEX_W_0_0F45_P_2_LEN_1,
 857   MOD_VEX_W_1_0F45_P_2_LEN_1,
 858   MOD_VEX_W_0_0F46_P_0_LEN_1,
 859   MOD_VEX_W_1_0F46_P_0_LEN_1,
 860   MOD_VEX_W_0_0F46_P_2_LEN_1,
 861   MOD_VEX_W_1_0F46_P_2_LEN_1,
 862   MOD_VEX_W_0_0F47_P_0_LEN_1,
 863   MOD_VEX_W_1_0F47_P_0_LEN_1,
 864   MOD_VEX_W_0_0F47_P_2_LEN_1,
 865   MOD_VEX_W_1_0F47_P_2_LEN_1,
 866   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 867   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 868   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 869   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 870   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 871   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 872   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 873   MOD_VEX_0F50,
 874   MOD_VEX_0F71_REG_2,
 875   MOD_VEX_0F71_REG_4,
 876   MOD_VEX_0F71_REG_6,
 877   MOD_VEX_0F72_REG_2,
 878   MOD_VEX_0F72_REG_4,
 879   MOD_VEX_0F72_REG_6,
 880   MOD_VEX_0F73_REG_2,
 881   MOD_VEX_0F73_REG_3,
 882   MOD_VEX_0F73_REG_6,
 883   MOD_VEX_0F73_REG_7,
 884   MOD_VEX_W_0_0F91_P_0_LEN_0,
 885   MOD_VEX_W_1_0F91_P_0_LEN_0,
 886   MOD_VEX_W_0_0F91_P_2_LEN_0,
 887   MOD_VEX_W_1_0F91_P_2_LEN_0,
 888   MOD_VEX_W_0_0F92_P_0_LEN_0,
 889   MOD_VEX_W_0_0F92_P_2_LEN_0,
 890   MOD_VEX_0F92_P_3_LEN_0,
 891   MOD_VEX_W_0_0F93_P_0_LEN_0,
 892   MOD_VEX_W_0_0F93_P_2_LEN_0,
 893   MOD_VEX_0F93_P_3_LEN_0,
 894   MOD_VEX_W_0_0F98_P_0_LEN_0,
 895   MOD_VEX_W_1_0F98_P_0_LEN_0,
 896   MOD_VEX_W_0_0F98_P_2_LEN_0,
 897   MOD_VEX_W_1_0F98_P_2_LEN_0,
 898   MOD_VEX_W_0_0F99_P_0_LEN_0,
 899   MOD_VEX_W_1_0F99_P_0_LEN_0,
 900   MOD_VEX_W_0_0F99_P_2_LEN_0,
 901   MOD_VEX_W_1_0F99_P_2_LEN_0,
 902   MOD_VEX_0FAE_REG_2,
 903   MOD_VEX_0FAE_REG_3,
 904   MOD_VEX_0FD7_PREFIX_2,
 905   MOD_VEX_0FE7_PREFIX_2,
 906   MOD_VEX_0FF0_PREFIX_3,
 907   MOD_VEX_0F381A_PREFIX_2,
 908   MOD_VEX_0F382A_PREFIX_2,
 909   MOD_VEX_0F382C_PREFIX_2,
 910   MOD_VEX_0F382D_PREFIX_2,
 911   MOD_VEX_0F382E_PREFIX_2,
 912   MOD_VEX_0F382F_PREFIX_2,
 913   MOD_VEX_0F385A_PREFIX_2,
 914   MOD_VEX_0F388C_PREFIX_2,
 915   MOD_VEX_0F388E_PREFIX_2,
 916   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 917   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 918   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 919   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 920   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 921   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 922   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 923   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 924
 925   MOD_VEX_0FXOP_09_12,
 926
 927   MOD_EVEX_0F12_PREFIX_0,
 928   MOD_EVEX_0F12_PREFIX_2,
 929   MOD_EVEX_0F13,
 930   MOD_EVEX_0F16_PREFIX_0,
 931   MOD_EVEX_0F16_PREFIX_2,
 932   MOD_EVEX_0F17,
 933   MOD_EVEX_0F2B,
 934   MOD_EVEX_0F381A_P_2_W_0,
 935   MOD_EVEX_0F381A_P_2_W_1,
 936   MOD_EVEX_0F381B_P_2_W_0,
 937   MOD_EVEX_0F381B_P_2_W_1,
 938   MOD_EVEX_0F385A_P_2_W_0,
 939   MOD_EVEX_0F385A_P_2_W_1,
 940   MOD_EVEX_0F385B_P_2_W_0,
 941   MOD_EVEX_0F385B_P_2_W_1,
 942   MOD_EVEX_0F38C6_REG_1,
 943   MOD_EVEX_0F38C6_REG_2,
 944   MOD_EVEX_0F38C6_REG_5,
 945   MOD_EVEX_0F38C6_REG_6,
 946   MOD_EVEX_0F38C7_REG_1,
 947   MOD_EVEX_0F38C7_REG_2,
 948   MOD_EVEX_0F38C7_REG_5,
 949   MOD_EVEX_0F38C7_REG_6
 950 };
 951
 952 enum
 953 {
 954   RM_C6_REG_7 = 0,
 955   RM_C7_REG_7,
 956   RM_0F01_REG_0,
 957   RM_0F01_REG_1,
 958   RM_0F01_REG_2,
 959   RM_0F01_REG_3,
 960   RM_0F01_REG_5_MOD_3,
 961   RM_0F01_REG_7_MOD_3,
 962   RM_0F1E_P_1_MOD_3_REG_7,
 963   RM_0FAE_REG_6_MOD_3_P_0,
 964   RM_0FAE_REG_7_MOD_3,
 965   RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_0F01_REG_3_RM_1,
 972   PREFIX_0F01_REG_5_MOD_0,
 973   PREFIX_0F01_REG_5_MOD_3_RM_0,
 974   PREFIX_0F01_REG_5_MOD_3_RM_1,
 975   PREFIX_0F01_REG_5_MOD_3_RM_2,
 976   PREFIX_0F01_REG_7_MOD_3_RM_2,
 977   PREFIX_0F01_REG_7_MOD_3_RM_3,
 978   PREFIX_0F09,
 979   PREFIX_0F10,
 980   PREFIX_0F11,
 981   PREFIX_0F12,
 982   PREFIX_0F16,
 983   PREFIX_0F1A,
 984   PREFIX_0F1B,
 985   PREFIX_0F1C,
 986   PREFIX_0F1E,
 987   PREFIX_0F2A,
 988   PREFIX_0F2B,
 989   PREFIX_0F2C,
 990   PREFIX_0F2D,
 991   PREFIX_0F2E,
 992   PREFIX_0F2F,
 993   PREFIX_0F51,
 994   PREFIX_0F52,
 995   PREFIX_0F53,
 996   PREFIX_0F58,
 997   PREFIX_0F59,
 998   PREFIX_0F5A,
 999   PREFIX_0F5B,
1000   PREFIX_0F5C,
1001   PREFIX_0F5D,
1002   PREFIX_0F5E,
1003   PREFIX_0F5F,
1004   PREFIX_0F60,
1005   PREFIX_0F61,
1006   PREFIX_0F62,
1007   PREFIX_0F6C,
1008   PREFIX_0F6D,
1009   PREFIX_0F6F,
1010   PREFIX_0F70,
1011   PREFIX_0F73_REG_3,
1012   PREFIX_0F73_REG_7,
1013   PREFIX_0F78,
1014   PREFIX_0F79,
1015   PREFIX_0F7C,
1016   PREFIX_0F7D,
1017   PREFIX_0F7E,
1018   PREFIX_0F7F,
1019   PREFIX_0FAE_REG_0_MOD_3,
1020   PREFIX_0FAE_REG_1_MOD_3,
1021   PREFIX_0FAE_REG_2_MOD_3,
1022   PREFIX_0FAE_REG_3_MOD_3,
1023   PREFIX_0FAE_REG_4_MOD_0,
1024   PREFIX_0FAE_REG_4_MOD_3,
1025   PREFIX_0FAE_REG_5_MOD_0,
1026   PREFIX_0FAE_REG_5_MOD_3,
1027   PREFIX_0FAE_REG_6_MOD_0,
1028   PREFIX_0FAE_REG_6_MOD_3,
1029   PREFIX_0FAE_REG_7_MOD_0,
1030   PREFIX_0FB8,
1031   PREFIX_0FBC,
1032   PREFIX_0FBD,
1033   PREFIX_0FC2,
1034   PREFIX_0FC3_MOD_0,
1035   PREFIX_0FC7_REG_6_MOD_0,
1036   PREFIX_0FC7_REG_6_MOD_3,
1037   PREFIX_0FC7_REG_7_MOD_3,
1038   PREFIX_0FD0,
1039   PREFIX_0FD6,
1040   PREFIX_0FE6,
1041   PREFIX_0FE7,
1042   PREFIX_0FF0,
1043   PREFIX_0FF7,
1044   PREFIX_0F3810,
1045   PREFIX_0F3814,
1046   PREFIX_0F3815,
1047   PREFIX_0F3817,
1048   PREFIX_0F3820,
1049   PREFIX_0F3821,
1050   PREFIX_0F3822,
1051   PREFIX_0F3823,
1052   PREFIX_0F3824,
1053   PREFIX_0F3825,
1054   PREFIX_0F3828,
1055   PREFIX_0F3829,
1056   PREFIX_0F382A,
1057   PREFIX_0F382B,
1058   PREFIX_0F3830,
1059   PREFIX_0F3831,
1060   PREFIX_0F3832,
1061   PREFIX_0F3833,
1062   PREFIX_0F3834,
1063   PREFIX_0F3835,
1064   PREFIX_0F3837,
1065   PREFIX_0F3838,
1066   PREFIX_0F3839,
1067   PREFIX_0F383A,
1068   PREFIX_0F383B,
1069   PREFIX_0F383C,
1070   PREFIX_0F383D,
1071   PREFIX_0F383E,
1072   PREFIX_0F383F,
1073   PREFIX_0F3840,
1074   PREFIX_0F3841,
1075   PREFIX_0F3880,
1076   PREFIX_0F3881,
1077   PREFIX_0F3882,
1078   PREFIX_0F38C8,
1079   PREFIX_0F38C9,
1080   PREFIX_0F38CA,
1081   PREFIX_0F38CB,
1082   PREFIX_0F38CC,
1083   PREFIX_0F38CD,
1084   PREFIX_0F38CF,
1085   PREFIX_0F38DB,
1086   PREFIX_0F38DC,
1087   PREFIX_0F38DD,
1088   PREFIX_0F38DE,
1089   PREFIX_0F38DF,
1090   PREFIX_0F38F0,
1091   PREFIX_0F38F1,
1092   PREFIX_0F38F5,
1093   PREFIX_0F38F6,
1094   PREFIX_0F38F8,
1095   PREFIX_0F38F9,
1096   PREFIX_0F3A08,
1097   PREFIX_0F3A09,
1098   PREFIX_0F3A0A,
1099   PREFIX_0F3A0B,
1100   PREFIX_0F3A0C,
1101   PREFIX_0F3A0D,
1102   PREFIX_0F3A0E,
1103   PREFIX_0F3A14,
1104   PREFIX_0F3A15,
1105   PREFIX_0F3A16,
1106   PREFIX_0F3A17,
1107   PREFIX_0F3A20,
1108   PREFIX_0F3A21,
1109   PREFIX_0F3A22,
1110   PREFIX_0F3A40,
1111   PREFIX_0F3A41,
1112   PREFIX_0F3A42,
1113   PREFIX_0F3A44,
1114   PREFIX_0F3A60,
1115   PREFIX_0F3A61,
1116   PREFIX_0F3A62,
1117   PREFIX_0F3A63,
1118   PREFIX_0F3ACC,
1119   PREFIX_0F3ACE,
1120   PREFIX_0F3ACF,
1121   PREFIX_0F3ADF,
1122   PREFIX_VEX_0F10,
1123   PREFIX_VEX_0F11,
1124   PREFIX_VEX_0F12,
1125   PREFIX_VEX_0F16,
1126   PREFIX_VEX_0F2A,
1127   PREFIX_VEX_0F2C,
1128   PREFIX_VEX_0F2D,
1129   PREFIX_VEX_0F2E,
1130   PREFIX_VEX_0F2F,
1131   PREFIX_VEX_0F41,
1132   PREFIX_VEX_0F42,
1133   PREFIX_VEX_0F44,
1134   PREFIX_VEX_0F45,
1135   PREFIX_VEX_0F46,
1136   PREFIX_VEX_0F47,
1137   PREFIX_VEX_0F4A,
1138   PREFIX_VEX_0F4B,
1139   PREFIX_VEX_0F51,
1140   PREFIX_VEX_0F52,
1141   PREFIX_VEX_0F53,
1142   PREFIX_VEX_0F58,
1143   PREFIX_VEX_0F59,
1144   PREFIX_VEX_0F5A,
1145   PREFIX_VEX_0F5B,
1146   PREFIX_VEX_0F5C,
1147   PREFIX_VEX_0F5D,
1148   PREFIX_VEX_0F5E,
1149   PREFIX_VEX_0F5F,
1150   PREFIX_VEX_0F60,
1151   PREFIX_VEX_0F61,
1152   PREFIX_VEX_0F62,
1153   PREFIX_VEX_0F63,
1154   PREFIX_VEX_0F64,
1155   PREFIX_VEX_0F65,
1156   PREFIX_VEX_0F66,
1157   PREFIX_VEX_0F67,
1158   PREFIX_VEX_0F68,
1159   PREFIX_VEX_0F69,
1160   PREFIX_VEX_0F6A,
1161   PREFIX_VEX_0F6B,
1162   PREFIX_VEX_0F6C,
1163   PREFIX_VEX_0F6D,
1164   PREFIX_VEX_0F6E,
1165   PREFIX_VEX_0F6F,
1166   PREFIX_VEX_0F70,
1167   PREFIX_VEX_0F71_REG_2,
1168   PREFIX_VEX_0F71_REG_4,
1169   PREFIX_VEX_0F71_REG_6,
1170   PREFIX_VEX_0F72_REG_2,
1171   PREFIX_VEX_0F72_REG_4,
1172   PREFIX_VEX_0F72_REG_6,
1173   PREFIX_VEX_0F73_REG_2,
1174   PREFIX_VEX_0F73_REG_3,
1175   PREFIX_VEX_0F73_REG_6,
1176   PREFIX_VEX_0F73_REG_7,
1177   PREFIX_VEX_0F74,
1178   PREFIX_VEX_0F75,
1179   PREFIX_VEX_0F76,
1180   PREFIX_VEX_0F77,
1181   PREFIX_VEX_0F7C,
1182   PREFIX_VEX_0F7D,
1183   PREFIX_VEX_0F7E,
1184   PREFIX_VEX_0F7F,
1185   PREFIX_VEX_0F90,
1186   PREFIX_VEX_0F91,
1187   PREFIX_VEX_0F92,
1188   PREFIX_VEX_0F93,
1189   PREFIX_VEX_0F98,
1190   PREFIX_VEX_0F99,
1191   PREFIX_VEX_0FC2,
1192   PREFIX_VEX_0FC4,
1193   PREFIX_VEX_0FC5,
1194   PREFIX_VEX_0FD0,
1195   PREFIX_VEX_0FD1,
1196   PREFIX_VEX_0FD2,
1197   PREFIX_VEX_0FD3,
1198   PREFIX_VEX_0FD4,
1199   PREFIX_VEX_0FD5,
1200   PREFIX_VEX_0FD6,
1201   PREFIX_VEX_0FD7,
1202   PREFIX_VEX_0FD8,
1203   PREFIX_VEX_0FD9,
1204   PREFIX_VEX_0FDA,
1205   PREFIX_VEX_0FDB,
1206   PREFIX_VEX_0FDC,
1207   PREFIX_VEX_0FDD,
1208   PREFIX_VEX_0FDE,
1209   PREFIX_VEX_0FDF,
1210   PREFIX_VEX_0FE0,
1211   PREFIX_VEX_0FE1,
1212   PREFIX_VEX_0FE2,
1213   PREFIX_VEX_0FE3,
1214   PREFIX_VEX_0FE4,
1215   PREFIX_VEX_0FE5,
1216   PREFIX_VEX_0FE6,
1217   PREFIX_VEX_0FE7,
1218   PREFIX_VEX_0FE8,
1219   PREFIX_VEX_0FE9,
1220   PREFIX_VEX_0FEA,
1221   PREFIX_VEX_0FEB,
1222   PREFIX_VEX_0FEC,
1223   PREFIX_VEX_0FED,
1224   PREFIX_VEX_0FEE,
1225   PREFIX_VEX_0FEF,
1226   PREFIX_VEX_0FF0,
1227   PREFIX_VEX_0FF1,
1228   PREFIX_VEX_0FF2,
1229   PREFIX_VEX_0FF3,
1230   PREFIX_VEX_0FF4,
1231   PREFIX_VEX_0FF5,
1232   PREFIX_VEX_0FF6,
1233   PREFIX_VEX_0FF7,
1234   PREFIX_VEX_0FF8,
1235   PREFIX_VEX_0FF9,
1236   PREFIX_VEX_0FFA,
1237   PREFIX_VEX_0FFB,
1238   PREFIX_VEX_0FFC,
1239   PREFIX_VEX_0FFD,
1240   PREFIX_VEX_0FFE,
1241   PREFIX_VEX_0F3800,
1242   PREFIX_VEX_0F3801,
1243   PREFIX_VEX_0F3802,
1244   PREFIX_VEX_0F3803,
1245   PREFIX_VEX_0F3804,
1246   PREFIX_VEX_0F3805,
1247   PREFIX_VEX_0F3806,
1248   PREFIX_VEX_0F3807,
1249   PREFIX_VEX_0F3808,
1250   PREFIX_VEX_0F3809,
1251   PREFIX_VEX_0F380A,
1252   PREFIX_VEX_0F380B,
1253   PREFIX_VEX_0F380C,
1254   PREFIX_VEX_0F380D,
1255   PREFIX_VEX_0F380E,
1256   PREFIX_VEX_0F380F,
1257   PREFIX_VEX_0F3813,
1258   PREFIX_VEX_0F3816,
1259   PREFIX_VEX_0F3817,
1260   PREFIX_VEX_0F3818,
1261   PREFIX_VEX_0F3819,
1262   PREFIX_VEX_0F381A,
1263   PREFIX_VEX_0F381C,
1264   PREFIX_VEX_0F381D,
1265   PREFIX_VEX_0F381E,
1266   PREFIX_VEX_0F3820,
1267   PREFIX_VEX_0F3821,
1268   PREFIX_VEX_0F3822,
1269   PREFIX_VEX_0F3823,
1270   PREFIX_VEX_0F3824,
1271   PREFIX_VEX_0F3825,
1272   PREFIX_VEX_0F3828,
1273   PREFIX_VEX_0F3829,
1274   PREFIX_VEX_0F382A,
1275   PREFIX_VEX_0F382B,
1276   PREFIX_VEX_0F382C,
1277   PREFIX_VEX_0F382D,
1278   PREFIX_VEX_0F382E,
1279   PREFIX_VEX_0F382F,
1280   PREFIX_VEX_0F3830,
1281   PREFIX_VEX_0F3831,
1282   PREFIX_VEX_0F3832,
1283   PREFIX_VEX_0F3833,
1284   PREFIX_VEX_0F3834,
1285   PREFIX_VEX_0F3835,
1286   PREFIX_VEX_0F3836,
1287   PREFIX_VEX_0F3837,
1288   PREFIX_VEX_0F3838,
1289   PREFIX_VEX_0F3839,
1290   PREFIX_VEX_0F383A,
1291   PREFIX_VEX_0F383B,
1292   PREFIX_VEX_0F383C,
1293   PREFIX_VEX_0F383D,
1294   PREFIX_VEX_0F383E,
1295   PREFIX_VEX_0F383F,
1296   PREFIX_VEX_0F3840,
1297   PREFIX_VEX_0F3841,
1298   PREFIX_VEX_0F3845,
1299   PREFIX_VEX_0F3846,
1300   PREFIX_VEX_0F3847,
1301   PREFIX_VEX_0F3849_X86_64,
1302   PREFIX_VEX_0F384B_X86_64,
1303   PREFIX_VEX_0F3858,
1304   PREFIX_VEX_0F3859,
1305   PREFIX_VEX_0F385A,
1306   PREFIX_VEX_0F385C_X86_64,
1307   PREFIX_VEX_0F385E_X86_64,
1308   PREFIX_VEX_0F3878,
1309   PREFIX_VEX_0F3879,
1310   PREFIX_VEX_0F388C,
1311   PREFIX_VEX_0F388E,
1312   PREFIX_VEX_0F3890,
1313   PREFIX_VEX_0F3891,
1314   PREFIX_VEX_0F3892,
1315   PREFIX_VEX_0F3893,
1316   PREFIX_VEX_0F3896,
1317   PREFIX_VEX_0F3897,
1318   PREFIX_VEX_0F3898,
1319   PREFIX_VEX_0F3899,
1320   PREFIX_VEX_0F389A,
1321   PREFIX_VEX_0F389B,
1322   PREFIX_VEX_0F389C,
1323   PREFIX_VEX_0F389D,
1324   PREFIX_VEX_0F389E,
1325   PREFIX_VEX_0F389F,
1326   PREFIX_VEX_0F38A6,
1327   PREFIX_VEX_0F38A7,
1328   PREFIX_VEX_0F38A8,
1329   PREFIX_VEX_0F38A9,
1330   PREFIX_VEX_0F38AA,
1331   PREFIX_VEX_0F38AB,
1332   PREFIX_VEX_0F38AC,
1333   PREFIX_VEX_0F38AD,
1334   PREFIX_VEX_0F38AE,
1335   PREFIX_VEX_0F38AF,
1336   PREFIX_VEX_0F38B6,
1337   PREFIX_VEX_0F38B7,
1338   PREFIX_VEX_0F38B8,
1339   PREFIX_VEX_0F38B9,
1340   PREFIX_VEX_0F38BA,
1341   PREFIX_VEX_0F38BB,
1342   PREFIX_VEX_0F38BC,
1343   PREFIX_VEX_0F38BD,
1344   PREFIX_VEX_0F38BE,
1345   PREFIX_VEX_0F38BF,
1346   PREFIX_VEX_0F38CF,
1347   PREFIX_VEX_0F38DB,
1348   PREFIX_VEX_0F38DC,
1349   PREFIX_VEX_0F38DD,
1350   PREFIX_VEX_0F38DE,
1351   PREFIX_VEX_0F38DF,
1352   PREFIX_VEX_0F38F2,
1353   PREFIX_VEX_0F38F3_REG_1,
1354   PREFIX_VEX_0F38F3_REG_2,
1355   PREFIX_VEX_0F38F3_REG_3,
1356   PREFIX_VEX_0F38F5,
1357   PREFIX_VEX_0F38F6,
1358   PREFIX_VEX_0F38F7,
1359   PREFIX_VEX_0F3A00,
1360   PREFIX_VEX_0F3A01,
1361   PREFIX_VEX_0F3A02,
1362   PREFIX_VEX_0F3A04,
1363   PREFIX_VEX_0F3A05,
1364   PREFIX_VEX_0F3A06,
1365   PREFIX_VEX_0F3A08,
1366   PREFIX_VEX_0F3A09,
1367   PREFIX_VEX_0F3A0A,
1368   PREFIX_VEX_0F3A0B,
1369   PREFIX_VEX_0F3A0C,
1370   PREFIX_VEX_0F3A0D,
1371   PREFIX_VEX_0F3A0E,
1372   PREFIX_VEX_0F3A0F,
1373   PREFIX_VEX_0F3A14,
1374   PREFIX_VEX_0F3A15,
1375   PREFIX_VEX_0F3A16,
1376   PREFIX_VEX_0F3A17,
1377   PREFIX_VEX_0F3A18,
1378   PREFIX_VEX_0F3A19,
1379   PREFIX_VEX_0F3A1D,
1380   PREFIX_VEX_0F3A20,
1381   PREFIX_VEX_0F3A21,
1382   PREFIX_VEX_0F3A22,
1383   PREFIX_VEX_0F3A30,
1384   PREFIX_VEX_0F3A31,
1385   PREFIX_VEX_0F3A32,
1386   PREFIX_VEX_0F3A33,
1387   PREFIX_VEX_0F3A38,
1388   PREFIX_VEX_0F3A39,
1389   PREFIX_VEX_0F3A40,
1390   PREFIX_VEX_0F3A41,
1391   PREFIX_VEX_0F3A42,
1392   PREFIX_VEX_0F3A44,
1393   PREFIX_VEX_0F3A46,
1394   PREFIX_VEX_0F3A48,
1395   PREFIX_VEX_0F3A49,
1396   PREFIX_VEX_0F3A4A,
1397   PREFIX_VEX_0F3A4B,
1398   PREFIX_VEX_0F3A4C,
1399   PREFIX_VEX_0F3A5C,
1400   PREFIX_VEX_0F3A5D,
1401   PREFIX_VEX_0F3A5E,
1402   PREFIX_VEX_0F3A5F,
1403   PREFIX_VEX_0F3A60,
1404   PREFIX_VEX_0F3A61,
1405   PREFIX_VEX_0F3A62,
1406   PREFIX_VEX_0F3A63,
1407   PREFIX_VEX_0F3A68,
1408   PREFIX_VEX_0F3A69,
1409   PREFIX_VEX_0F3A6A,
1410   PREFIX_VEX_0F3A6B,
1411   PREFIX_VEX_0F3A6C,
1412   PREFIX_VEX_0F3A6D,
1413   PREFIX_VEX_0F3A6E,
1414   PREFIX_VEX_0F3A6F,
1415   PREFIX_VEX_0F3A78,
1416   PREFIX_VEX_0F3A79,
1417   PREFIX_VEX_0F3A7A,
1418   PREFIX_VEX_0F3A7B,
1419   PREFIX_VEX_0F3A7C,
1420   PREFIX_VEX_0F3A7D,
1421   PREFIX_VEX_0F3A7E,
1422   PREFIX_VEX_0F3A7F,
1423   PREFIX_VEX_0F3ACE,
1424   PREFIX_VEX_0F3ACF,
1425   PREFIX_VEX_0F3ADF,
1426   PREFIX_VEX_0F3AF0,
1427
1428   PREFIX_EVEX_0F10,
1429   PREFIX_EVEX_0F11,
1430   PREFIX_EVEX_0F12,
1431   PREFIX_EVEX_0F16,
1432   PREFIX_EVEX_0F2A,
1433   PREFIX_EVEX_0F2C,
1434   PREFIX_EVEX_0F2D,
1435   PREFIX_EVEX_0F2E,
1436   PREFIX_EVEX_0F2F,
1437   PREFIX_EVEX_0F51,
1438   PREFIX_EVEX_0F58,
1439   PREFIX_EVEX_0F59,
1440   PREFIX_EVEX_0F5A,
1441   PREFIX_EVEX_0F5B,
1442   PREFIX_EVEX_0F5C,
1443   PREFIX_EVEX_0F5D,
1444   PREFIX_EVEX_0F5E,
1445   PREFIX_EVEX_0F5F,
1446   PREFIX_EVEX_0F64,
1447   PREFIX_EVEX_0F65,
1448   PREFIX_EVEX_0F66,
1449   PREFIX_EVEX_0F6E,
1450   PREFIX_EVEX_0F6F,
1451   PREFIX_EVEX_0F70,
1452   PREFIX_EVEX_0F71_REG_2,
1453   PREFIX_EVEX_0F71_REG_4,
1454   PREFIX_EVEX_0F71_REG_6,
1455   PREFIX_EVEX_0F72_REG_0,
1456   PREFIX_EVEX_0F72_REG_1,
1457   PREFIX_EVEX_0F72_REG_2,
1458   PREFIX_EVEX_0F72_REG_4,
1459   PREFIX_EVEX_0F72_REG_6,
1460   PREFIX_EVEX_0F73_REG_2,
1461   PREFIX_EVEX_0F73_REG_3,
1462   PREFIX_EVEX_0F73_REG_6,
1463   PREFIX_EVEX_0F73_REG_7,
1464   PREFIX_EVEX_0F74,
1465   PREFIX_EVEX_0F75,
1466   PREFIX_EVEX_0F76,
1467   PREFIX_EVEX_0F78,
1468   PREFIX_EVEX_0F79,
1469   PREFIX_EVEX_0F7A,
1470   PREFIX_EVEX_0F7B,
1471   PREFIX_EVEX_0F7E,
1472   PREFIX_EVEX_0F7F,
1473   PREFIX_EVEX_0FC2,
1474   PREFIX_EVEX_0FC4,
1475   PREFIX_EVEX_0FC5,
1476   PREFIX_EVEX_0FD6,
1477   PREFIX_EVEX_0FDB,
1478   PREFIX_EVEX_0FDF,
1479   PREFIX_EVEX_0FE2,
1480   PREFIX_EVEX_0FE6,
1481   PREFIX_EVEX_0FE7,
1482   PREFIX_EVEX_0FEB,
1483   PREFIX_EVEX_0FEF,
1484   PREFIX_EVEX_0F380D,
1485   PREFIX_EVEX_0F3810,
1486   PREFIX_EVEX_0F3811,
1487   PREFIX_EVEX_0F3812,
1488   PREFIX_EVEX_0F3813,
1489   PREFIX_EVEX_0F3814,
1490   PREFIX_EVEX_0F3815,
1491   PREFIX_EVEX_0F3816,
1492   PREFIX_EVEX_0F3819,
1493   PREFIX_EVEX_0F381A,
1494   PREFIX_EVEX_0F381B,
1495   PREFIX_EVEX_0F381E,
1496   PREFIX_EVEX_0F381F,
1497   PREFIX_EVEX_0F3820,
1498   PREFIX_EVEX_0F3821,
1499   PREFIX_EVEX_0F3822,
1500   PREFIX_EVEX_0F3823,
1501   PREFIX_EVEX_0F3824,
1502   PREFIX_EVEX_0F3825,
1503   PREFIX_EVEX_0F3826,
1504   PREFIX_EVEX_0F3827,
1505   PREFIX_EVEX_0F3828,
1506   PREFIX_EVEX_0F3829,
1507   PREFIX_EVEX_0F382A,
1508   PREFIX_EVEX_0F382C,
1509   PREFIX_EVEX_0F382D,
1510   PREFIX_EVEX_0F3830,
1511   PREFIX_EVEX_0F3831,
1512   PREFIX_EVEX_0F3832,
1513   PREFIX_EVEX_0F3833,
1514   PREFIX_EVEX_0F3834,
1515   PREFIX_EVEX_0F3835,
1516   PREFIX_EVEX_0F3836,
1517   PREFIX_EVEX_0F3837,
1518   PREFIX_EVEX_0F3838,
1519   PREFIX_EVEX_0F3839,
1520   PREFIX_EVEX_0F383A,
1521   PREFIX_EVEX_0F383B,
1522   PREFIX_EVEX_0F383D,
1523   PREFIX_EVEX_0F383F,
1524   PREFIX_EVEX_0F3840,
1525   PREFIX_EVEX_0F3842,
1526   PREFIX_EVEX_0F3843,
1527   PREFIX_EVEX_0F3844,
1528   PREFIX_EVEX_0F3845,
1529   PREFIX_EVEX_0F3846,
1530   PREFIX_EVEX_0F3847,
1531   PREFIX_EVEX_0F384C,
1532   PREFIX_EVEX_0F384D,
1533   PREFIX_EVEX_0F384E,
1534   PREFIX_EVEX_0F384F,
1535   PREFIX_EVEX_0F3850,
1536   PREFIX_EVEX_0F3851,
1537   PREFIX_EVEX_0F3852,
1538   PREFIX_EVEX_0F3853,
1539   PREFIX_EVEX_0F3854,
1540   PREFIX_EVEX_0F3855,
1541   PREFIX_EVEX_0F3859,
1542   PREFIX_EVEX_0F385A,
1543   PREFIX_EVEX_0F385B,
1544   PREFIX_EVEX_0F3862,
1545   PREFIX_EVEX_0F3863,
1546   PREFIX_EVEX_0F3864,
1547   PREFIX_EVEX_0F3865,
1548   PREFIX_EVEX_0F3866,
1549   PREFIX_EVEX_0F3868,
1550   PREFIX_EVEX_0F3870,
1551   PREFIX_EVEX_0F3871,
1552   PREFIX_EVEX_0F3872,
1553   PREFIX_EVEX_0F3873,
1554   PREFIX_EVEX_0F3875,
1555   PREFIX_EVEX_0F3876,
1556   PREFIX_EVEX_0F3877,
1557   PREFIX_EVEX_0F387A,
1558   PREFIX_EVEX_0F387B,
1559   PREFIX_EVEX_0F387C,
1560   PREFIX_EVEX_0F387D,
1561   PREFIX_EVEX_0F387E,
1562   PREFIX_EVEX_0F387F,
1563   PREFIX_EVEX_0F3883,
1564   PREFIX_EVEX_0F3888,
1565   PREFIX_EVEX_0F3889,
1566   PREFIX_EVEX_0F388A,
1567   PREFIX_EVEX_0F388B,
1568   PREFIX_EVEX_0F388D,
1569   PREFIX_EVEX_0F388F,
1570   PREFIX_EVEX_0F3890,
1571   PREFIX_EVEX_0F3891,
1572   PREFIX_EVEX_0F3892,
1573   PREFIX_EVEX_0F3893,
1574   PREFIX_EVEX_0F389A,
1575   PREFIX_EVEX_0F389B,
1576   PREFIX_EVEX_0F38A0,
1577   PREFIX_EVEX_0F38A1,
1578   PREFIX_EVEX_0F38A2,
1579   PREFIX_EVEX_0F38A3,
1580   PREFIX_EVEX_0F38AA,
1581   PREFIX_EVEX_0F38AB,
1582   PREFIX_EVEX_0F38B4,
1583   PREFIX_EVEX_0F38B5,
1584   PREFIX_EVEX_0F38C4,
1585   PREFIX_EVEX_0F38C6_REG_1,
1586   PREFIX_EVEX_0F38C6_REG_2,
1587   PREFIX_EVEX_0F38C6_REG_5,
1588   PREFIX_EVEX_0F38C6_REG_6,
1589   PREFIX_EVEX_0F38C7_REG_1,
1590   PREFIX_EVEX_0F38C7_REG_2,
1591   PREFIX_EVEX_0F38C7_REG_5,
1592   PREFIX_EVEX_0F38C7_REG_6,
1593   PREFIX_EVEX_0F38C8,
1594   PREFIX_EVEX_0F38CA,
1595   PREFIX_EVEX_0F38CB,
1596   PREFIX_EVEX_0F38CC,
1597   PREFIX_EVEX_0F38CD,
1598
1599   PREFIX_EVEX_0F3A00,
1600   PREFIX_EVEX_0F3A01,
1601   PREFIX_EVEX_0F3A03,
1602   PREFIX_EVEX_0F3A05,
1603   PREFIX_EVEX_0F3A08,
1604   PREFIX_EVEX_0F3A09,
1605   PREFIX_EVEX_0F3A0A,
1606   PREFIX_EVEX_0F3A0B,
1607   PREFIX_EVEX_0F3A14,
1608   PREFIX_EVEX_0F3A15,
1609   PREFIX_EVEX_0F3A16,
1610   PREFIX_EVEX_0F3A17,
1611   PREFIX_EVEX_0F3A18,
1612   PREFIX_EVEX_0F3A19,
1613   PREFIX_EVEX_0F3A1A,
1614   PREFIX_EVEX_0F3A1B,
1615   PREFIX_EVEX_0F3A1E,
1616   PREFIX_EVEX_0F3A1F,
1617   PREFIX_EVEX_0F3A20,
1618   PREFIX_EVEX_0F3A21,
1619   PREFIX_EVEX_0F3A22,
1620   PREFIX_EVEX_0F3A23,
1621   PREFIX_EVEX_0F3A25,
1622   PREFIX_EVEX_0F3A26,
1623   PREFIX_EVEX_0F3A27,
1624   PREFIX_EVEX_0F3A38,
1625   PREFIX_EVEX_0F3A39,
1626   PREFIX_EVEX_0F3A3A,
1627   PREFIX_EVEX_0F3A3B,
1628   PREFIX_EVEX_0F3A3E,
1629   PREFIX_EVEX_0F3A3F,
1630   PREFIX_EVEX_0F3A42,
1631   PREFIX_EVEX_0F3A43,
1632   PREFIX_EVEX_0F3A50,
1633   PREFIX_EVEX_0F3A51,
1634   PREFIX_EVEX_0F3A54,
1635   PREFIX_EVEX_0F3A55,
1636   PREFIX_EVEX_0F3A56,
1637   PREFIX_EVEX_0F3A57,
1638   PREFIX_EVEX_0F3A66,
1639   PREFIX_EVEX_0F3A67,
1640   PREFIX_EVEX_0F3A70,
1641   PREFIX_EVEX_0F3A71,
1642   PREFIX_EVEX_0F3A72,
1643   PREFIX_EVEX_0F3A73,
1644 };
1645
1646 enum
1647 {
1648   X86_64_06 = 0,
1649   X86_64_07,
1650   X86_64_0E,
1651   X86_64_16,
1652   X86_64_17,
1653   X86_64_1E,
1654   X86_64_1F,
1655   X86_64_27,
1656   X86_64_2F,
1657   X86_64_37,
1658   X86_64_3F,
1659   X86_64_60,
1660   X86_64_61,
1661   X86_64_62,
1662   X86_64_63,
1663   X86_64_6D,
1664   X86_64_6F,
1665   X86_64_82,
1666   X86_64_9A,
1667   X86_64_C2,
1668   X86_64_C3,
1669   X86_64_C4,
1670   X86_64_C5,
1671   X86_64_CE,
1672   X86_64_D4,
1673   X86_64_D5,
1674   X86_64_E8,
1675   X86_64_E9,
1676   X86_64_EA,
1677   X86_64_0F01_REG_0,
1678   X86_64_0F01_REG_1,
1679   X86_64_0F01_REG_2,
1680   X86_64_0F01_REG_3,
1681   X86_64_VEX_0F3849,
1682   X86_64_VEX_0F384B,
1683   X86_64_VEX_0F385C,
1684   X86_64_VEX_0F385E
1685 };
1686
1687 enum
1688 {
1689   THREE_BYTE_0F38 = 0,
1690   THREE_BYTE_0F3A
1691 };
1692
1693 enum
1694 {
1695   XOP_08 = 0,
1696   XOP_09,
1697   XOP_0A
1698 };
1699
1700 enum
1701 {
1702   VEX_0F = 0,
1703   VEX_0F38,
1704   VEX_0F3A
1705 };
1706
1707 enum
1708 {
1709   EVEX_0F = 0,
1710   EVEX_0F38,
1711   EVEX_0F3A
1712 };
1713
1714 enum
1715 {
1716   VEX_LEN_0F12_P_0_M_0 = 0,
1717   VEX_LEN_0F12_P_0_M_1,
1718 #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
1719   VEX_LEN_0F13_M_0,
1720   VEX_LEN_0F16_P_0_M_0,
1721   VEX_LEN_0F16_P_0_M_1,
1722 #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
1723   VEX_LEN_0F17_M_0,
1724   VEX_LEN_0F41_P_0,
1725   VEX_LEN_0F41_P_2,
1726   VEX_LEN_0F42_P_0,
1727   VEX_LEN_0F42_P_2,
1728   VEX_LEN_0F44_P_0,
1729   VEX_LEN_0F44_P_2,
1730   VEX_LEN_0F45_P_0,
1731   VEX_LEN_0F45_P_2,
1732   VEX_LEN_0F46_P_0,
1733   VEX_LEN_0F46_P_2,
1734   VEX_LEN_0F47_P_0,
1735   VEX_LEN_0F47_P_2,
1736   VEX_LEN_0F4A_P_0,
1737   VEX_LEN_0F4A_P_2,
1738   VEX_LEN_0F4B_P_0,
1739   VEX_LEN_0F4B_P_2,
1740   VEX_LEN_0F6E_P_2,
1741   VEX_LEN_0F77_P_0,
1742   VEX_LEN_0F7E_P_1,
1743   VEX_LEN_0F7E_P_2,
1744   VEX_LEN_0F90_P_0,
1745   VEX_LEN_0F90_P_2,
1746   VEX_LEN_0F91_P_0,
1747   VEX_LEN_0F91_P_2,
1748   VEX_LEN_0F92_P_0,
1749   VEX_LEN_0F92_P_2,
1750   VEX_LEN_0F92_P_3,
1751   VEX_LEN_0F93_P_0,
1752   VEX_LEN_0F93_P_2,
1753   VEX_LEN_0F93_P_3,
1754   VEX_LEN_0F98_P_0,
1755   VEX_LEN_0F98_P_2,
1756   VEX_LEN_0F99_P_0,
1757   VEX_LEN_0F99_P_2,
1758   VEX_LEN_0FAE_R_2_M_0,
1759   VEX_LEN_0FAE_R_3_M_0,
1760   VEX_LEN_0FC4_P_2,
1761   VEX_LEN_0FC5_P_2,
1762   VEX_LEN_0FD6_P_2,
1763   VEX_LEN_0FF7_P_2,
1764   VEX_LEN_0F3816_P_2,
1765   VEX_LEN_0F3819_P_2,
1766   VEX_LEN_0F381A_P_2_M_0,
1767   VEX_LEN_0F3836_P_2,
1768   VEX_LEN_0F3841_P_2,
1769   VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
1770   VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
1771   VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
1772   VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
1773   VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
1774   VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
1775   VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
1776   VEX_LEN_0F385A_P_2_M_0,
1777   VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
1778   VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
1779   VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
1780   VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
1781   VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
1782   VEX_LEN_0F38DB_P_2,
1783   VEX_LEN_0F38F2_P_0,
1784   VEX_LEN_0F38F3_R_1_P_0,
1785   VEX_LEN_0F38F3_R_2_P_0,
1786   VEX_LEN_0F38F3_R_3_P_0,
1787   VEX_LEN_0F38F5_P_0,
1788   VEX_LEN_0F38F5_P_1,
1789   VEX_LEN_0F38F5_P_3,
1790   VEX_LEN_0F38F6_P_3,
1791   VEX_LEN_0F38F7_P_0,
1792   VEX_LEN_0F38F7_P_1,
1793   VEX_LEN_0F38F7_P_2,
1794   VEX_LEN_0F38F7_P_3,
1795   VEX_LEN_0F3A00_P_2,
1796   VEX_LEN_0F3A01_P_2,
1797   VEX_LEN_0F3A06_P_2,
1798   VEX_LEN_0F3A14_P_2,
1799   VEX_LEN_0F3A15_P_2,
1800   VEX_LEN_0F3A16_P_2,
1801   VEX_LEN_0F3A17_P_2,
1802   VEX_LEN_0F3A18_P_2,
1803   VEX_LEN_0F3A19_P_2,
1804   VEX_LEN_0F3A20_P_2,
1805   VEX_LEN_0F3A21_P_2,
1806   VEX_LEN_0F3A22_P_2,
1807   VEX_LEN_0F3A30_P_2,
1808   VEX_LEN_0F3A31_P_2,
1809   VEX_LEN_0F3A32_P_2,
1810   VEX_LEN_0F3A33_P_2,
1811   VEX_LEN_0F3A38_P_2,
1812   VEX_LEN_0F3A39_P_2,
1813   VEX_LEN_0F3A41_P_2,
1814   VEX_LEN_0F3A46_P_2,
1815   VEX_LEN_0F3A60_P_2,
1816   VEX_LEN_0F3A61_P_2,
1817   VEX_LEN_0F3A62_P_2,
1818   VEX_LEN_0F3A63_P_2,
1819   VEX_LEN_0F3ADF_P_2,
1820   VEX_LEN_0F3AF0_P_3,
1821   VEX_LEN_0FXOP_08_85,
1822   VEX_LEN_0FXOP_08_86,
1823   VEX_LEN_0FXOP_08_87,
1824   VEX_LEN_0FXOP_08_8E,
1825   VEX_LEN_0FXOP_08_8F,
1826   VEX_LEN_0FXOP_08_95,
1827   VEX_LEN_0FXOP_08_96,
1828   VEX_LEN_0FXOP_08_97,
1829   VEX_LEN_0FXOP_08_9E,
1830   VEX_LEN_0FXOP_08_9F,
1831   VEX_LEN_0FXOP_08_A3,
1832   VEX_LEN_0FXOP_08_A6,
1833   VEX_LEN_0FXOP_08_B6,
1834   VEX_LEN_0FXOP_08_C0,
1835   VEX_LEN_0FXOP_08_C1,
1836   VEX_LEN_0FXOP_08_C2,
1837   VEX_LEN_0FXOP_08_C3,
1838   VEX_LEN_0FXOP_08_CC,
1839   VEX_LEN_0FXOP_08_CD,
1840   VEX_LEN_0FXOP_08_CE,
1841   VEX_LEN_0FXOP_08_CF,
1842   VEX_LEN_0FXOP_08_EC,
1843   VEX_LEN_0FXOP_08_ED,
1844   VEX_LEN_0FXOP_08_EE,
1845   VEX_LEN_0FXOP_08_EF,
1846   VEX_LEN_0FXOP_09_01,
1847   VEX_LEN_0FXOP_09_02,
1848   VEX_LEN_0FXOP_09_12_M_1,
1849   VEX_LEN_0FXOP_09_82_W_0,
1850   VEX_LEN_0FXOP_09_83_W_0,
1851   VEX_LEN_0FXOP_09_90,
1852   VEX_LEN_0FXOP_09_91,
1853   VEX_LEN_0FXOP_09_92,
1854   VEX_LEN_0FXOP_09_93,
1855   VEX_LEN_0FXOP_09_94,
1856   VEX_LEN_0FXOP_09_95,
1857   VEX_LEN_0FXOP_09_96,
1858   VEX_LEN_0FXOP_09_97,
1859   VEX_LEN_0FXOP_09_98,
1860   VEX_LEN_0FXOP_09_99,
1861   VEX_LEN_0FXOP_09_9A,
1862   VEX_LEN_0FXOP_09_9B,
1863   VEX_LEN_0FXOP_09_C1,
1864   VEX_LEN_0FXOP_09_C2,
1865   VEX_LEN_0FXOP_09_C3,
1866   VEX_LEN_0FXOP_09_C6,
1867   VEX_LEN_0FXOP_09_C7,
1868   VEX_LEN_0FXOP_09_CB,
1869   VEX_LEN_0FXOP_09_D1,
1870   VEX_LEN_0FXOP_09_D2,
1871   VEX_LEN_0FXOP_09_D3,
1872   VEX_LEN_0FXOP_09_D6,
1873   VEX_LEN_0FXOP_09_D7,
1874   VEX_LEN_0FXOP_09_DB,
1875   VEX_LEN_0FXOP_09_E1,
1876   VEX_LEN_0FXOP_09_E2,
1877   VEX_LEN_0FXOP_09_E3,
1878   VEX_LEN_0FXOP_0A_12,
1879 };
1880
1881 enum
1882 {
1883   EVEX_LEN_0F6E_P_2 = 0,
1884   EVEX_LEN_0F7E_P_1,
1885   EVEX_LEN_0F7E_P_2,
1886   EVEX_LEN_0FC4_P_2,
1887   EVEX_LEN_0FC5_P_2,
1888   EVEX_LEN_0FD6_P_2,
1889   EVEX_LEN_0F3816_P_2,
1890   EVEX_LEN_0F3819_P_2_W_0,
1891   EVEX_LEN_0F3819_P_2_W_1,
1892   EVEX_LEN_0F381A_P_2_W_0_M_0,
1893   EVEX_LEN_0F381A_P_2_W_1_M_0,
1894   EVEX_LEN_0F381B_P_2_W_0_M_0,
1895   EVEX_LEN_0F381B_P_2_W_1_M_0,
1896   EVEX_LEN_0F3836_P_2,
1897   EVEX_LEN_0F385A_P_2_W_0_M_0,
1898   EVEX_LEN_0F385A_P_2_W_1_M_0,
1899   EVEX_LEN_0F385B_P_2_W_0_M_0,
1900   EVEX_LEN_0F385B_P_2_W_1_M_0,
1901   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1902   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1903   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1904   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1905   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1906   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1907   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1908   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1909   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1910   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1911   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1912   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1913   EVEX_LEN_0F3A00_P_2_W_1,
1914   EVEX_LEN_0F3A01_P_2_W_1,
1915   EVEX_LEN_0F3A14_P_2,
1916   EVEX_LEN_0F3A15_P_2,
1917   EVEX_LEN_0F3A16_P_2,
1918   EVEX_LEN_0F3A17_P_2,
1919   EVEX_LEN_0F3A18_P_2_W_0,
1920   EVEX_LEN_0F3A18_P_2_W_1,
1921   EVEX_LEN_0F3A19_P_2_W_0,
1922   EVEX_LEN_0F3A19_P_2_W_1,
1923   EVEX_LEN_0F3A1A_P_2_W_0,
1924   EVEX_LEN_0F3A1A_P_2_W_1,
1925   EVEX_LEN_0F3A1B_P_2_W_0,
1926   EVEX_LEN_0F3A1B_P_2_W_1,
1927   EVEX_LEN_0F3A20_P_2,
1928   EVEX_LEN_0F3A21_P_2_W_0,
1929   EVEX_LEN_0F3A22_P_2,
1930   EVEX_LEN_0F3A23_P_2_W_0,
1931   EVEX_LEN_0F3A23_P_2_W_1,
1932   EVEX_LEN_0F3A38_P_2_W_0,
1933   EVEX_LEN_0F3A38_P_2_W_1,
1934   EVEX_LEN_0F3A39_P_2_W_0,
1935   EVEX_LEN_0F3A39_P_2_W_1,
1936   EVEX_LEN_0F3A3A_P_2_W_0,
1937   EVEX_LEN_0F3A3A_P_2_W_1,
1938   EVEX_LEN_0F3A3B_P_2_W_0,
1939   EVEX_LEN_0F3A3B_P_2_W_1,
1940   EVEX_LEN_0F3A43_P_2_W_0,
1941   EVEX_LEN_0F3A43_P_2_W_1
1942 };
1943
1944 enum
1945 {
1946   VEX_W_0F41_P_0_LEN_1 = 0,
1947   VEX_W_0F41_P_2_LEN_1,
1948   VEX_W_0F42_P_0_LEN_1,
1949   VEX_W_0F42_P_2_LEN_1,
1950   VEX_W_0F44_P_0_LEN_0,
1951   VEX_W_0F44_P_2_LEN_0,
1952   VEX_W_0F45_P_0_LEN_1,
1953   VEX_W_0F45_P_2_LEN_1,
1954   VEX_W_0F46_P_0_LEN_1,
1955   VEX_W_0F46_P_2_LEN_1,
1956   VEX_W_0F47_P_0_LEN_1,
1957   VEX_W_0F47_P_2_LEN_1,
1958   VEX_W_0F4A_P_0_LEN_1,
1959   VEX_W_0F4A_P_2_LEN_1,
1960   VEX_W_0F4B_P_0_LEN_1,
1961   VEX_W_0F4B_P_2_LEN_1,
1962   VEX_W_0F90_P_0_LEN_0,
1963   VEX_W_0F90_P_2_LEN_0,
1964   VEX_W_0F91_P_0_LEN_0,
1965   VEX_W_0F91_P_2_LEN_0,
1966   VEX_W_0F92_P_0_LEN_0,
1967   VEX_W_0F92_P_2_LEN_0,
1968   VEX_W_0F93_P_0_LEN_0,
1969   VEX_W_0F93_P_2_LEN_0,
1970   VEX_W_0F98_P_0_LEN_0,
1971   VEX_W_0F98_P_2_LEN_0,
1972   VEX_W_0F99_P_0_LEN_0,
1973   VEX_W_0F99_P_2_LEN_0,
1974   VEX_W_0F380C_P_2,
1975   VEX_W_0F380D_P_2,
1976   VEX_W_0F380E_P_2,
1977   VEX_W_0F380F_P_2,
1978   VEX_W_0F3813_P_2,
1979   VEX_W_0F3816_P_2,
1980   VEX_W_0F3818_P_2,
1981   VEX_W_0F3819_P_2,
1982   VEX_W_0F381A_P_2_M_0,
1983   VEX_W_0F382C_P_2_M_0,
1984   VEX_W_0F382D_P_2_M_0,
1985   VEX_W_0F382E_P_2_M_0,
1986   VEX_W_0F382F_P_2_M_0,
1987   VEX_W_0F3836_P_2,
1988   VEX_W_0F3846_P_2,
1989   VEX_W_0F3849_X86_64_P_0,
1990   VEX_W_0F3849_X86_64_P_2,
1991   VEX_W_0F3849_X86_64_P_3,
1992   VEX_W_0F384B_X86_64_P_1,
1993   VEX_W_0F384B_X86_64_P_2,
1994   VEX_W_0F384B_X86_64_P_3,
1995   VEX_W_0F3858_P_2,
1996   VEX_W_0F3859_P_2,
1997   VEX_W_0F385A_P_2_M_0,
1998   VEX_W_0F385C_X86_64_P_1,
1999   VEX_W_0F385E_X86_64_P_0,
2000   VEX_W_0F385E_X86_64_P_1,
2001   VEX_W_0F385E_X86_64_P_2,
2002   VEX_W_0F385E_X86_64_P_3,
2003   VEX_W_0F3878_P_2,
2004   VEX_W_0F3879_P_2,
2005   VEX_W_0F38CF_P_2,
2006   VEX_W_0F3A00_P_2,
2007   VEX_W_0F3A01_P_2,
2008   VEX_W_0F3A02_P_2,
2009   VEX_W_0F3A04_P_2,
2010   VEX_W_0F3A05_P_2,
2011   VEX_W_0F3A06_P_2,
2012   VEX_W_0F3A18_P_2,
2013   VEX_W_0F3A19_P_2,
2014   VEX_W_0F3A1D_P_2,
2015   VEX_W_0F3A30_P_2_LEN_0,
2016   VEX_W_0F3A31_P_2_LEN_0,
2017   VEX_W_0F3A32_P_2_LEN_0,
2018   VEX_W_0F3A33_P_2_LEN_0,
2019   VEX_W_0F3A38_P_2,
2020   VEX_W_0F3A39_P_2,
2021   VEX_W_0F3A46_P_2,
2022   VEX_W_0F3A4A_P_2,
2023   VEX_W_0F3A4B_P_2,
2024   VEX_W_0F3A4C_P_2,
2025   VEX_W_0F3ACE_P_2,
2026   VEX_W_0F3ACF_P_2,
2027
2028   VEX_W_0FXOP_08_85_L_0,
2029   VEX_W_0FXOP_08_86_L_0,
2030   VEX_W_0FXOP_08_87_L_0,
2031   VEX_W_0FXOP_08_8E_L_0,
2032   VEX_W_0FXOP_08_8F_L_0,
2033   VEX_W_0FXOP_08_95_L_0,
2034   VEX_W_0FXOP_08_96_L_0,
2035   VEX_W_0FXOP_08_97_L_0,
2036   VEX_W_0FXOP_08_9E_L_0,
2037   VEX_W_0FXOP_08_9F_L_0,
2038   VEX_W_0FXOP_08_A6_L_0,
2039   VEX_W_0FXOP_08_B6_L_0,
2040   VEX_W_0FXOP_08_C0_L_0,
2041   VEX_W_0FXOP_08_C1_L_0,
2042   VEX_W_0FXOP_08_C2_L_0,
2043   VEX_W_0FXOP_08_C3_L_0,
2044   VEX_W_0FXOP_08_CC_L_0,
2045   VEX_W_0FXOP_08_CD_L_0,
2046   VEX_W_0FXOP_08_CE_L_0,
2047   VEX_W_0FXOP_08_CF_L_0,
2048   VEX_W_0FXOP_08_EC_L_0,
2049   VEX_W_0FXOP_08_ED_L_0,
2050   VEX_W_0FXOP_08_EE_L_0,
2051   VEX_W_0FXOP_08_EF_L_0,
2052
2053   VEX_W_0FXOP_09_80,
2054   VEX_W_0FXOP_09_81,
2055   VEX_W_0FXOP_09_82,
2056   VEX_W_0FXOP_09_83,
2057   VEX_W_0FXOP_09_C1_L_0,
2058   VEX_W_0FXOP_09_C2_L_0,
2059   VEX_W_0FXOP_09_C3_L_0,
2060   VEX_W_0FXOP_09_C6_L_0,
2061   VEX_W_0FXOP_09_C7_L_0,
2062   VEX_W_0FXOP_09_CB_L_0,
2063   VEX_W_0FXOP_09_D1_L_0,
2064   VEX_W_0FXOP_09_D2_L_0,
2065   VEX_W_0FXOP_09_D3_L_0,
2066   VEX_W_0FXOP_09_D6_L_0,
2067   VEX_W_0FXOP_09_D7_L_0,
2068   VEX_W_0FXOP_09_DB_L_0,
2069   VEX_W_0FXOP_09_E1_L_0,
2070   VEX_W_0FXOP_09_E2_L_0,
2071   VEX_W_0FXOP_09_E3_L_0,
2072
2073   EVEX_W_0F10_P_1,
2074   EVEX_W_0F10_P_3,
2075   EVEX_W_0F11_P_1,
2076   EVEX_W_0F11_P_3,
2077   EVEX_W_0F12_P_0_M_1,
2078   EVEX_W_0F12_P_1,
2079   EVEX_W_0F12_P_3,
2080   EVEX_W_0F16_P_0_M_1,
2081   EVEX_W_0F16_P_1,
2082   EVEX_W_0F2A_P_3,
2083   EVEX_W_0F51_P_1,
2084   EVEX_W_0F51_P_3,
2085   EVEX_W_0F58_P_1,
2086   EVEX_W_0F58_P_3,
2087   EVEX_W_0F59_P_1,
2088   EVEX_W_0F59_P_3,
2089   EVEX_W_0F5A_P_0,
2090   EVEX_W_0F5A_P_1,
2091   EVEX_W_0F5A_P_2,
2092   EVEX_W_0F5A_P_3,
2093   EVEX_W_0F5B_P_0,
2094   EVEX_W_0F5B_P_1,
2095   EVEX_W_0F5B_P_2,
2096   EVEX_W_0F5C_P_1,
2097   EVEX_W_0F5C_P_3,
2098   EVEX_W_0F5D_P_1,
2099   EVEX_W_0F5D_P_3,
2100   EVEX_W_0F5E_P_1,
2101   EVEX_W_0F5E_P_3,
2102   EVEX_W_0F5F_P_1,
2103   EVEX_W_0F5F_P_3,
2104   EVEX_W_0F62,
2105   EVEX_W_0F66_P_2,
2106   EVEX_W_0F6A,
2107   EVEX_W_0F6B,
2108   EVEX_W_0F6C,
2109   EVEX_W_0F6D,
2110   EVEX_W_0F6F_P_1,
2111   EVEX_W_0F6F_P_2,
2112   EVEX_W_0F6F_P_3,
2113   EVEX_W_0F70_P_2,
2114   EVEX_W_0F72_R_2_P_2,
2115   EVEX_W_0F72_R_6_P_2,
2116   EVEX_W_0F73_R_2_P_2,
2117   EVEX_W_0F73_R_6_P_2,
2118   EVEX_W_0F76_P_2,
2119   EVEX_W_0F78_P_0,
2120   EVEX_W_0F78_P_2,
2121   EVEX_W_0F79_P_0,
2122   EVEX_W_0F79_P_2,
2123   EVEX_W_0F7A_P_1,
2124   EVEX_W_0F7A_P_2,
2125   EVEX_W_0F7A_P_3,
2126   EVEX_W_0F7B_P_2,
2127   EVEX_W_0F7B_P_3,
2128   EVEX_W_0F7E_P_1,
2129   EVEX_W_0F7F_P_1,
2130   EVEX_W_0F7F_P_2,
2131   EVEX_W_0F7F_P_3,
2132   EVEX_W_0FC2_P_1,
2133   EVEX_W_0FC2_P_3,
2134   EVEX_W_0FD2,
2135   EVEX_W_0FD3,
2136   EVEX_W_0FD4,
2137   EVEX_W_0FD6_P_2,
2138   EVEX_W_0FE6_P_1,
2139   EVEX_W_0FE6_P_2,
2140   EVEX_W_0FE6_P_3,
2141   EVEX_W_0FE7_P_2,
2142   EVEX_W_0FF2,
2143   EVEX_W_0FF3,
2144   EVEX_W_0FF4,
2145   EVEX_W_0FFA,
2146   EVEX_W_0FFB,
2147   EVEX_W_0FFE,
2148   EVEX_W_0F380D_P_2,
2149   EVEX_W_0F3810_P_1,
2150   EVEX_W_0F3810_P_2,
2151   EVEX_W_0F3811_P_1,
2152   EVEX_W_0F3811_P_2,
2153   EVEX_W_0F3812_P_1,
2154   EVEX_W_0F3812_P_2,
2155   EVEX_W_0F3813_P_1,
2156   EVEX_W_0F3813_P_2,
2157   EVEX_W_0F3814_P_1,
2158   EVEX_W_0F3815_P_1,
2159   EVEX_W_0F3819_P_2,
2160   EVEX_W_0F381A_P_2,
2161   EVEX_W_0F381B_P_2,
2162   EVEX_W_0F381E_P_2,
2163   EVEX_W_0F381F_P_2,
2164   EVEX_W_0F3820_P_1,
2165   EVEX_W_0F3821_P_1,
2166   EVEX_W_0F3822_P_1,
2167   EVEX_W_0F3823_P_1,
2168   EVEX_W_0F3824_P_1,
2169   EVEX_W_0F3825_P_1,
2170   EVEX_W_0F3825_P_2,
2171   EVEX_W_0F3828_P_2,
2172   EVEX_W_0F3829_P_2,
2173   EVEX_W_0F382A_P_1,
2174   EVEX_W_0F382A_P_2,
2175   EVEX_W_0F382B,
2176   EVEX_W_0F3830_P_1,
2177   EVEX_W_0F3831_P_1,
2178   EVEX_W_0F3832_P_1,
2179   EVEX_W_0F3833_P_1,
2180   EVEX_W_0F3834_P_1,
2181   EVEX_W_0F3835_P_1,
2182   EVEX_W_0F3835_P_2,
2183   EVEX_W_0F3837_P_2,
2184   EVEX_W_0F383A_P_1,
2185   EVEX_W_0F3852_P_1,
2186   EVEX_W_0F3859_P_2,
2187   EVEX_W_0F385A_P_2,
2188   EVEX_W_0F385B_P_2,
2189   EVEX_W_0F3862_P_2,
2190   EVEX_W_0F3863_P_2,
2191   EVEX_W_0F3870_P_2,
2192   EVEX_W_0F3872_P_1,
2193   EVEX_W_0F3872_P_2,
2194   EVEX_W_0F3872_P_3,
2195   EVEX_W_0F387A_P_2,
2196   EVEX_W_0F387B_P_2,
2197   EVEX_W_0F3883_P_2,
2198   EVEX_W_0F3891_P_2,
2199   EVEX_W_0F3893_P_2,
2200   EVEX_W_0F38A1_P_2,
2201   EVEX_W_0F38A3_P_2,
2202   EVEX_W_0F38C7_R_1_P_2,
2203   EVEX_W_0F38C7_R_2_P_2,
2204   EVEX_W_0F38C7_R_5_P_2,
2205   EVEX_W_0F38C7_R_6_P_2,
2206
2207   EVEX_W_0F3A00_P_2,
2208   EVEX_W_0F3A01_P_2,
2209   EVEX_W_0F3A05_P_2,
2210   EVEX_W_0F3A08_P_2,
2211   EVEX_W_0F3A09_P_2,
2212   EVEX_W_0F3A0A_P_2,
2213   EVEX_W_0F3A0B_P_2,
2214   EVEX_W_0F3A18_P_2,
2215   EVEX_W_0F3A19_P_2,
2216   EVEX_W_0F3A1A_P_2,
2217   EVEX_W_0F3A1B_P_2,
2218   EVEX_W_0F3A21_P_2,
2219   EVEX_W_0F3A23_P_2,
2220   EVEX_W_0F3A38_P_2,
2221   EVEX_W_0F3A39_P_2,
2222   EVEX_W_0F3A3A_P_2,
2223   EVEX_W_0F3A3B_P_2,
2224   EVEX_W_0F3A42_P_2,
2225   EVEX_W_0F3A43_P_2,
2226   EVEX_W_0F3A70_P_2,
2227   EVEX_W_0F3A72_P_2,
2228 };
2229
2230 typedef void (*op_rtn) (int bytemode, int sizeflag);
2231
2232 struct dis386 {
2233   const char *name;
2234   struct
2235     {
2236       op_rtn rtn;
2237       int bytemode;
2238     } op[MAX_OPERANDS];
2239   unsigned int prefix_requirement;
2240 };
2241
2242 /* Upper case letters in the instruction names here are macros.
2243    'A' => print 'b' if no register operands or suffix_always is true
2244    'B' => print 'b' if suffix_always is true
2245    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2246           size prefix
2247    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2248           suffix_always is true
2249    'E' => print 'e' if 32-bit form of jcxz
2250    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2251    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2252    'H' => print ",pt" or ",pn" branch hint
2253    'I' unused.
2254    'J' unused.
2255    'K' => print 'd' or 'q' if rex prefix is present.
2256    'L' => print 'l' if suffix_always is true
2257    'M' => print 'r' if intel_mnemonic is false.
2258    'N' => print 'n' if instruction has no wait "prefix"
2259    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2260    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2261           or suffix_always is true.  print 'q' if rex prefix is present.
2262    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2263           is true
2264    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2265    'S' => print 'w', 'l' or 'q' if suffix_always is true
2266    'T' => print 'q' in 64bit mode if instruction has no operand size
2267           prefix and behave as 'P' otherwise
2268    'U' => print 'q' in 64bit mode if instruction has no operand size
2269           prefix and behave as 'Q' otherwise
2270    'V' => print 'q' in 64bit mode if instruction has no operand size
2271           prefix and behave as 'S' otherwise
2272    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2273    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2274    'Y' unused.
2275    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2276    '!' => change condition from true to false or from false to true.
2277    '%' => add 1 upper case letter to the macro.
2278    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
2279           prefix or suffix_always is true (lcall/ljmp).
2280    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2281           on operand size prefix.
2282    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2283           has no operand size prefix for AMD64 ISA, behave as 'P'
2284           otherwise
2285
2286    2 upper case letter macros:
2287    "XY" => print 'x' or 'y' if suffix_always is true or no register
2288            operands and no broadcast.
2289    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2290            register operands and no broadcast.
2291    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2292    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
2293            operand or no operand at all in 64bit mode, or if suffix_always
2294            is true.
2295    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2296    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2297    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2298    "LW" => print 'd', 'q' depending on the VEX.W bit
2299    "BW" => print 'b' or 'w' depending on the EVEX.W bit
2300    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2301            an operand size prefix, or suffix_always is true.  print
2302            'q' if rex prefix is present.
2303
2304    Many of the above letters print nothing in Intel mode.  See "putop"
2305    for the details.
2306
2307    Braces '{' and '}', and vertical bars '|', indicate alternative
2308    mnemonic strings for AT&T and Intel.  */
2309
2310 static const struct dis386 dis386[] = {
2311   /* 00 */
2312   { "addB",             { Ebh1, Gb }, 0 },
2313   { "addS",             { Evh1, Gv }, 0 },
2314   { "addB",             { Gb, EbS }, 0 },
2315   { "addS",             { Gv, EvS }, 0 },
2316   { "addB",             { AL, Ib }, 0 },
2317   { "addS",             { eAX, Iv }, 0 },
2318   { X86_64_TABLE (X86_64_06) },
2319   { X86_64_TABLE (X86_64_07) },
2320   /* 08 */
2321   { "orB",              { Ebh1, Gb }, 0 },
2322   { "orS",              { Evh1, Gv }, 0 },
2323   { "orB",              { Gb, EbS }, 0 },
2324   { "orS",              { Gv, EvS }, 0 },
2325   { "orB",              { AL, Ib }, 0 },
2326   { "orS",              { eAX, Iv }, 0 },
2327   { X86_64_TABLE (X86_64_0E) },
2328   { Bad_Opcode },       /* 0x0f extended opcode escape */
2329   /* 10 */
2330   { "adcB",             { Ebh1, Gb }, 0 },
2331   { "adcS",             { Evh1, Gv }, 0 },
2332   { "adcB",             { Gb, EbS }, 0 },
2333   { "adcS",             { Gv, EvS }, 0 },
2334   { "adcB",             { AL, Ib }, 0 },
2335   { "adcS",             { eAX, Iv }, 0 },
2336   { X86_64_TABLE (X86_64_16) },
2337   { X86_64_TABLE (X86_64_17) },
2338   /* 18 */
2339   { "sbbB",             { Ebh1, Gb }, 0 },
2340   { "sbbS",             { Evh1, Gv }, 0 },
2341   { "sbbB",             { Gb, EbS }, 0 },
2342   { "sbbS",             { Gv, EvS }, 0 },
2343   { "sbbB",             { AL, Ib }, 0 },
2344   { "sbbS",             { eAX, Iv }, 0 },
2345   { X86_64_TABLE (X86_64_1E) },
2346   { X86_64_TABLE (X86_64_1F) },
2347   /* 20 */
2348   { "andB",             { Ebh1, Gb }, 0 },
2349   { "andS",             { Evh1, Gv }, 0 },
2350   { "andB",             { Gb, EbS }, 0 },
2351   { "andS",             { Gv, EvS }, 0 },
2352   { "andB",             { AL, Ib }, 0 },
2353   { "andS",             { eAX, Iv }, 0 },
2354   { Bad_Opcode },       /* SEG ES prefix */
2355   { X86_64_TABLE (X86_64_27) },
2356   /* 28 */
2357   { "subB",             { Ebh1, Gb }, 0 },
2358   { "subS",             { Evh1, Gv }, 0 },
2359   { "subB",             { Gb, EbS }, 0 },
2360   { "subS",             { Gv, EvS }, 0 },
2361   { "subB",             { AL, Ib }, 0 },
2362   { "subS",             { eAX, Iv }, 0 },
2363   { Bad_Opcode },       /* SEG CS prefix */
2364   { X86_64_TABLE (X86_64_2F) },
2365   /* 30 */
2366   { "xorB",             { Ebh1, Gb }, 0 },
2367   { "xorS",             { Evh1, Gv }, 0 },
2368   { "xorB",             { Gb, EbS }, 0 },
2369   { "xorS",             { Gv, EvS }, 0 },
2370   { "xorB",             { AL, Ib }, 0 },
2371   { "xorS",             { eAX, Iv }, 0 },
2372   { Bad_Opcode },       /* SEG SS prefix */
2373   { X86_64_TABLE (X86_64_37) },
2374   /* 38 */
2375   { "cmpB",             { Eb, Gb }, 0 },
2376   { "cmpS",             { Ev, Gv }, 0 },
2377   { "cmpB",             { Gb, EbS }, 0 },
2378   { "cmpS",             { Gv, EvS }, 0 },
2379   { "cmpB",             { AL, Ib }, 0 },
2380   { "cmpS",             { eAX, Iv }, 0 },
2381   { Bad_Opcode },       /* SEG DS prefix */
2382   { X86_64_TABLE (X86_64_3F) },
2383   /* 40 */
2384   { "inc{S|}",          { RMeAX }, 0 },
2385   { "inc{S|}",          { RMeCX }, 0 },
2386   { "inc{S|}",          { RMeDX }, 0 },
2387   { "inc{S|}",          { RMeBX }, 0 },
2388   { "inc{S|}",          { RMeSP }, 0 },
2389   { "inc{S|}",          { RMeBP }, 0 },
2390   { "inc{S|}",          { RMeSI }, 0 },
2391   { "inc{S|}",          { RMeDI }, 0 },
2392   /* 48 */
2393   { "dec{S|}",          { RMeAX }, 0 },
2394   { "dec{S|}",          { RMeCX }, 0 },
2395   { "dec{S|}",          { RMeDX }, 0 },
2396   { "dec{S|}",          { RMeBX }, 0 },
2397   { "dec{S|}",          { RMeSP }, 0 },
2398   { "dec{S|}",          { RMeBP }, 0 },
2399   { "dec{S|}",          { RMeSI }, 0 },
2400   { "dec{S|}",          { RMeDI }, 0 },
2401   /* 50 */
2402   { "pushV",            { RMrAX }, 0 },
2403   { "pushV",            { RMrCX }, 0 },
2404   { "pushV",            { RMrDX }, 0 },
2405   { "pushV",            { RMrBX }, 0 },
2406   { "pushV",            { RMrSP }, 0 },
2407   { "pushV",            { RMrBP }, 0 },
2408   { "pushV",            { RMrSI }, 0 },
2409   { "pushV",            { RMrDI }, 0 },
2410   /* 58 */
2411   { "popV",             { RMrAX }, 0 },
2412   { "popV",             { RMrCX }, 0 },
2413   { "popV",             { RMrDX }, 0 },
2414   { "popV",             { RMrBX }, 0 },
2415   { "popV",             { RMrSP }, 0 },
2416   { "popV",             { RMrBP }, 0 },
2417   { "popV",             { RMrSI }, 0 },
2418   { "popV",             { RMrDI }, 0 },
2419   /* 60 */
2420   { X86_64_TABLE (X86_64_60) },
2421   { X86_64_TABLE (X86_64_61) },
2422   { X86_64_TABLE (X86_64_62) },
2423   { X86_64_TABLE (X86_64_63) },
2424   { Bad_Opcode },       /* seg fs */
2425   { Bad_Opcode },       /* seg gs */
2426   { Bad_Opcode },       /* op size prefix */
2427   { Bad_Opcode },       /* adr size prefix */
2428   /* 68 */
2429   { "pushT",            { sIv }, 0 },
2430   { "imulS",            { Gv, Ev, Iv }, 0 },
2431   { "pushT",            { sIbT }, 0 },
2432   { "imulS",            { Gv, Ev, sIb }, 0 },
2433   { "ins{b|}",          { Ybr, indirDX }, 0 },
2434   { X86_64_TABLE (X86_64_6D) },
2435   { "outs{b|}",         { indirDXr, Xb }, 0 },
2436   { X86_64_TABLE (X86_64_6F) },
2437   /* 70 */
2438   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2439   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2440   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2441   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2442   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2443   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2444   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2445   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2446   /* 78 */
2447   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2448   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2449   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2450   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2451   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2452   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2453   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2454   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2455   /* 80 */
2456   { REG_TABLE (REG_80) },
2457   { REG_TABLE (REG_81) },
2458   { X86_64_TABLE (X86_64_82) },
2459   { REG_TABLE (REG_83) },
2460   { "testB",            { Eb, Gb }, 0 },
2461   { "testS",            { Ev, Gv }, 0 },
2462   { "xchgB",            { Ebh2, Gb }, 0 },
2463   { "xchgS",            { Evh2, Gv }, 0 },
2464   /* 88 */
2465   { "movB",             { Ebh3, Gb }, 0 },
2466   { "movS",             { Evh3, Gv }, 0 },
2467   { "movB",             { Gb, EbS }, 0 },
2468   { "movS",             { Gv, EvS }, 0 },
2469   { "movD",             { Sv, Sw }, 0 },
2470   { MOD_TABLE (MOD_8D) },
2471   { "movD",             { Sw, Sv }, 0 },
2472   { REG_TABLE (REG_8F) },
2473   /* 90 */
2474   { PREFIX_TABLE (PREFIX_90) },
2475   { "xchgS",            { RMeCX, eAX }, 0 },
2476   { "xchgS",            { RMeDX, eAX }, 0 },
2477   { "xchgS",            { RMeBX, eAX }, 0 },
2478   { "xchgS",            { RMeSP, eAX }, 0 },
2479   { "xchgS",            { RMeBP, eAX }, 0 },
2480   { "xchgS",            { RMeSI, eAX }, 0 },
2481   { "xchgS",            { RMeDI, eAX }, 0 },
2482   /* 98 */
2483   { "cW{t|}R",          { XX }, 0 },
2484   { "cR{t|}O",          { XX }, 0 },
2485   { X86_64_TABLE (X86_64_9A) },
2486   { Bad_Opcode },       /* fwait */
2487   { "pushfT",           { XX }, 0 },
2488   { "popfT",            { XX }, 0 },
2489   { "sahf",             { XX }, 0 },
2490   { "lahf",             { XX }, 0 },
2491   /* a0 */
2492   { "mov%LB",           { AL, Ob }, 0 },
2493   { "mov%LS",           { eAX, Ov }, 0 },
2494   { "mov%LB",           { Ob, AL }, 0 },
2495   { "mov%LS",           { Ov, eAX }, 0 },
2496   { "movs{b|}",         { Ybr, Xb }, 0 },
2497   { "movs{R|}",         { Yvr, Xv }, 0 },
2498   { "cmps{b|}",         { Xb, Yb }, 0 },
2499   { "cmps{R|}",         { Xv, Yv }, 0 },
2500   /* a8 */
2501   { "testB",            { AL, Ib }, 0 },
2502   { "testS",            { eAX, Iv }, 0 },
2503   { "stosB",            { Ybr, AL }, 0 },
2504   { "stosS",            { Yvr, eAX }, 0 },
2505   { "lodsB",            { ALr, Xb }, 0 },
2506   { "lodsS",            { eAXr, Xv }, 0 },
2507   { "scasB",            { AL, Yb }, 0 },
2508   { "scasS",            { eAX, Yv }, 0 },
2509   /* b0 */
2510   { "movB",             { RMAL, Ib }, 0 },
2511   { "movB",             { RMCL, Ib }, 0 },
2512   { "movB",             { RMDL, Ib }, 0 },
2513   { "movB",             { RMBL, Ib }, 0 },
2514   { "movB",             { RMAH, Ib }, 0 },
2515   { "movB",             { RMCH, Ib }, 0 },
2516   { "movB",             { RMDH, Ib }, 0 },
2517   { "movB",             { RMBH, Ib }, 0 },
2518   /* b8 */
2519   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2520   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2521   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2522   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2523   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2524   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2525   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2526   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2527   /* c0 */
2528   { REG_TABLE (REG_C0) },
2529   { REG_TABLE (REG_C1) },
2530   { X86_64_TABLE (X86_64_C2) },
2531   { X86_64_TABLE (X86_64_C3) },
2532   { X86_64_TABLE (X86_64_C4) },
2533   { X86_64_TABLE (X86_64_C5) },
2534   { REG_TABLE (REG_C6) },
2535   { REG_TABLE (REG_C7) },
2536   /* c8 */
2537   { "enterT",           { Iw, Ib }, 0 },
2538   { "leaveT",           { XX }, 0 },
2539   { "{l|}ret{|f}P",     { Iw }, 0 },
2540   { "{l|}ret{|f}P",     { XX }, 0 },
2541   { "int3",             { XX }, 0 },
2542   { "int",              { Ib }, 0 },
2543   { X86_64_TABLE (X86_64_CE) },
2544   { "iret%LP",          { XX }, 0 },
2545   /* d0 */
2546   { REG_TABLE (REG_D0) },
2547   { REG_TABLE (REG_D1) },
2548   { REG_TABLE (REG_D2) },
2549   { REG_TABLE (REG_D3) },
2550   { X86_64_TABLE (X86_64_D4) },
2551   { X86_64_TABLE (X86_64_D5) },
2552   { Bad_Opcode },
2553   { "xlat",             { DSBX }, 0 },
2554   /* d8 */
2555   { FLOAT },
2556   { FLOAT },
2557   { FLOAT },
2558   { FLOAT },
2559   { FLOAT },
2560   { FLOAT },
2561   { FLOAT },
2562   { FLOAT },
2563   /* e0 */
2564   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2565   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2566   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2567   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2568   { "inB",              { AL, Ib }, 0 },
2569   { "inG",              { zAX, Ib }, 0 },
2570   { "outB",             { Ib, AL }, 0 },
2571   { "outG",             { Ib, zAX }, 0 },
2572   /* e8 */
2573   { X86_64_TABLE (X86_64_E8) },
2574   { X86_64_TABLE (X86_64_E9) },
2575   { X86_64_TABLE (X86_64_EA) },
2576   { "jmp",              { Jb, BND }, 0 },
2577   { "inB",              { AL, indirDX }, 0 },
2578   { "inG",              { zAX, indirDX }, 0 },
2579   { "outB",             { indirDX, AL }, 0 },
2580   { "outG",             { indirDX, zAX }, 0 },
2581   /* f0 */
2582   { Bad_Opcode },       /* lock prefix */
2583   { "icebp",            { XX }, 0 },
2584   { Bad_Opcode },       /* repne */
2585   { Bad_Opcode },       /* repz */
2586   { "hlt",              { XX }, 0 },
2587   { "cmc",              { XX }, 0 },
2588   { REG_TABLE (REG_F6) },
2589   { REG_TABLE (REG_F7) },
2590   /* f8 */
2591   { "clc",              { XX }, 0 },
2592   { "stc",              { XX }, 0 },
2593   { "cli",              { XX }, 0 },
2594   { "sti",              { XX }, 0 },
2595   { "cld",              { XX }, 0 },
2596   { "std",              { XX }, 0 },
2597   { REG_TABLE (REG_FE) },
2598   { REG_TABLE (REG_FF) },
2599 };
2600
2601 static const struct dis386 dis386_twobyte[] = {
2602   /* 00 */
2603   { REG_TABLE (REG_0F00 ) },
2604   { REG_TABLE (REG_0F01 ) },
2605   { "larS",             { Gv, Ew }, 0 },
2606   { "lslS",             { Gv, Ew }, 0 },
2607   { Bad_Opcode },
2608   { "syscall",          { XX }, 0 },
2609   { "clts",             { XX }, 0 },
2610   { "sysret%LQ",                { XX }, 0 },
2611   /* 08 */
2612   { "invd",             { XX }, 0 },
2613   { PREFIX_TABLE (PREFIX_0F09) },
2614   { Bad_Opcode },
2615   { "ud2",              { XX }, 0 },
2616   { Bad_Opcode },
2617   { REG_TABLE (REG_0F0D) },
2618   { "femms",            { XX }, 0 },
2619   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2620   /* 10 */
2621   { PREFIX_TABLE (PREFIX_0F10) },
2622   { PREFIX_TABLE (PREFIX_0F11) },
2623   { PREFIX_TABLE (PREFIX_0F12) },
2624   { MOD_TABLE (MOD_0F13) },
2625   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2626   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2627   { PREFIX_TABLE (PREFIX_0F16) },
2628   { MOD_TABLE (MOD_0F17) },
2629   /* 18 */
2630   { REG_TABLE (REG_0F18) },
2631   { "nopQ",             { Ev }, 0 },
2632   { PREFIX_TABLE (PREFIX_0F1A) },
2633   { PREFIX_TABLE (PREFIX_0F1B) },
2634   { PREFIX_TABLE (PREFIX_0F1C) },
2635   { "nopQ",             { Ev }, 0 },
2636   { PREFIX_TABLE (PREFIX_0F1E) },
2637   { "nopQ",             { Ev }, 0 },
2638   /* 20 */
2639   { "movZ",             { Rm, Cm }, 0 },
2640   { "movZ",             { Rm, Dm }, 0 },
2641   { "movZ",             { Cm, Rm }, 0 },
2642   { "movZ",             { Dm, Rm }, 0 },
2643   { MOD_TABLE (MOD_0F24) },
2644   { Bad_Opcode },
2645   { MOD_TABLE (MOD_0F26) },
2646   { Bad_Opcode },
2647   /* 28 */
2648   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2649   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2650   { PREFIX_TABLE (PREFIX_0F2A) },
2651   { PREFIX_TABLE (PREFIX_0F2B) },
2652   { PREFIX_TABLE (PREFIX_0F2C) },
2653   { PREFIX_TABLE (PREFIX_0F2D) },
2654   { PREFIX_TABLE (PREFIX_0F2E) },
2655   { PREFIX_TABLE (PREFIX_0F2F) },
2656   /* 30 */
2657   { "wrmsr",            { XX }, 0 },
2658   { "rdtsc",            { XX }, 0 },
2659   { "rdmsr",            { XX }, 0 },
2660   { "rdpmc",            { XX }, 0 },
2661   { "sysenter",         { SEP }, 0 },
2662   { "sysexit",          { SEP }, 0 },
2663   { Bad_Opcode },
2664   { "getsec",           { XX }, 0 },
2665   /* 38 */
2666   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2667   { Bad_Opcode },
2668   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2669   { Bad_Opcode },
2670   { Bad_Opcode },
2671   { Bad_Opcode },
2672   { Bad_Opcode },
2673   { Bad_Opcode },
2674   /* 40 */
2675   { "cmovoS",           { Gv, Ev }, 0 },
2676   { "cmovnoS",          { Gv, Ev }, 0 },
2677   { "cmovbS",           { Gv, Ev }, 0 },
2678   { "cmovaeS",          { Gv, Ev }, 0 },
2679   { "cmoveS",           { Gv, Ev }, 0 },
2680   { "cmovneS",          { Gv, Ev }, 0 },
2681   { "cmovbeS",          { Gv, Ev }, 0 },
2682   { "cmovaS",           { Gv, Ev }, 0 },
2683   /* 48 */
2684   { "cmovsS",           { Gv, Ev }, 0 },
2685   { "cmovnsS",          { Gv, Ev }, 0 },
2686   { "cmovpS",           { Gv, Ev }, 0 },
2687   { "cmovnpS",          { Gv, Ev }, 0 },
2688   { "cmovlS",           { Gv, Ev }, 0 },
2689   { "cmovgeS",          { Gv, Ev }, 0 },
2690   { "cmovleS",          { Gv, Ev }, 0 },
2691   { "cmovgS",           { Gv, Ev }, 0 },
2692   /* 50 */
2693   { MOD_TABLE (MOD_0F50) },
2694   { PREFIX_TABLE (PREFIX_0F51) },
2695   { PREFIX_TABLE (PREFIX_0F52) },
2696   { PREFIX_TABLE (PREFIX_0F53) },
2697   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2698   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2699   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2700   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2701   /* 58 */
2702   { PREFIX_TABLE (PREFIX_0F58) },
2703   { PREFIX_TABLE (PREFIX_0F59) },
2704   { PREFIX_TABLE (PREFIX_0F5A) },
2705   { PREFIX_TABLE (PREFIX_0F5B) },
2706   { PREFIX_TABLE (PREFIX_0F5C) },
2707   { PREFIX_TABLE (PREFIX_0F5D) },
2708   { PREFIX_TABLE (PREFIX_0F5E) },
2709   { PREFIX_TABLE (PREFIX_0F5F) },
2710   /* 60 */
2711   { PREFIX_TABLE (PREFIX_0F60) },
2712   { PREFIX_TABLE (PREFIX_0F61) },
2713   { PREFIX_TABLE (PREFIX_0F62) },
2714   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2715   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2716   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2717   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2718   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2719   /* 68 */
2720   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2721   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2722   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2723   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2724   { PREFIX_TABLE (PREFIX_0F6C) },
2725   { PREFIX_TABLE (PREFIX_0F6D) },
2726   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2727   { PREFIX_TABLE (PREFIX_0F6F) },
2728   /* 70 */
2729   { PREFIX_TABLE (PREFIX_0F70) },
2730   { REG_TABLE (REG_0F71) },
2731   { REG_TABLE (REG_0F72) },
2732   { REG_TABLE (REG_0F73) },
2733   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2734   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2735   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2736   { "emms",             { XX }, PREFIX_OPCODE },
2737   /* 78 */
2738   { PREFIX_TABLE (PREFIX_0F78) },
2739   { PREFIX_TABLE (PREFIX_0F79) },
2740   { Bad_Opcode },
2741   { Bad_Opcode },
2742   { PREFIX_TABLE (PREFIX_0F7C) },
2743   { PREFIX_TABLE (PREFIX_0F7D) },
2744   { PREFIX_TABLE (PREFIX_0F7E) },
2745   { PREFIX_TABLE (PREFIX_0F7F) },
2746   /* 80 */
2747   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2748   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2749   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2750   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2751   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2752   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2753   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2754   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2755   /* 88 */
2756   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2757   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2758   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2759   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2760   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2761   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2762   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2763   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2764   /* 90 */
2765   { "seto",             { Eb }, 0 },
2766   { "setno",            { Eb }, 0 },
2767   { "setb",             { Eb }, 0 },
2768   { "setae",            { Eb }, 0 },
2769   { "sete",             { Eb }, 0 },
2770   { "setne",            { Eb }, 0 },
2771   { "setbe",            { Eb }, 0 },
2772   { "seta",             { Eb }, 0 },
2773   /* 98 */
2774   { "sets",             { Eb }, 0 },
2775   { "setns",            { Eb }, 0 },
2776   { "setp",             { Eb }, 0 },
2777   { "setnp",            { Eb }, 0 },
2778   { "setl",             { Eb }, 0 },
2779   { "setge",            { Eb }, 0 },
2780   { "setle",            { Eb }, 0 },
2781   { "setg",             { Eb }, 0 },
2782   /* a0 */
2783   { "pushT",            { fs }, 0 },
2784   { "popT",             { fs }, 0 },
2785   { "cpuid",            { XX }, 0 },
2786   { "btS",              { Ev, Gv }, 0 },
2787   { "shldS",            { Ev, Gv, Ib }, 0 },
2788   { "shldS",            { Ev, Gv, CL }, 0 },
2789   { REG_TABLE (REG_0FA6) },
2790   { REG_TABLE (REG_0FA7) },
2791   /* a8 */
2792   { "pushT",            { gs }, 0 },
2793   { "popT",             { gs }, 0 },
2794   { "rsm",              { XX }, 0 },
2795   { "btsS",             { Evh1, Gv }, 0 },
2796   { "shrdS",            { Ev, Gv, Ib }, 0 },
2797   { "shrdS",            { Ev, Gv, CL }, 0 },
2798   { REG_TABLE (REG_0FAE) },
2799   { "imulS",            { Gv, Ev }, 0 },
2800   /* b0 */
2801   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2802   { "cmpxchgS",         { Evh1, Gv }, 0 },
2803   { MOD_TABLE (MOD_0FB2) },
2804   { "btrS",             { Evh1, Gv }, 0 },
2805   { MOD_TABLE (MOD_0FB4) },
2806   { MOD_TABLE (MOD_0FB5) },
2807   { "movz{bR|x}",       { Gv, Eb }, 0 },
2808   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2809   /* b8 */
2810   { PREFIX_TABLE (PREFIX_0FB8) },
2811   { "ud1S",             { Gv, Ev }, 0 },
2812   { REG_TABLE (REG_0FBA) },
2813   { "btcS",             { Evh1, Gv }, 0 },
2814   { PREFIX_TABLE (PREFIX_0FBC) },
2815   { PREFIX_TABLE (PREFIX_0FBD) },
2816   { "movs{bR|x}",       { Gv, Eb }, 0 },
2817   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2818   /* c0 */
2819   { "xaddB",            { Ebh1, Gb }, 0 },
2820   { "xaddS",            { Evh1, Gv }, 0 },
2821   { PREFIX_TABLE (PREFIX_0FC2) },
2822   { MOD_TABLE (MOD_0FC3) },
2823   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2824   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2825   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2826   { REG_TABLE (REG_0FC7) },
2827   /* c8 */
2828   { "bswap",            { RMeAX }, 0 },
2829   { "bswap",            { RMeCX }, 0 },
2830   { "bswap",            { RMeDX }, 0 },
2831   { "bswap",            { RMeBX }, 0 },
2832   { "bswap",            { RMeSP }, 0 },
2833   { "bswap",            { RMeBP }, 0 },
2834   { "bswap",            { RMeSI }, 0 },
2835   { "bswap",            { RMeDI }, 0 },
2836   /* d0 */
2837   { PREFIX_TABLE (PREFIX_0FD0) },
2838   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2839   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2840   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2841   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2842   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2843   { PREFIX_TABLE (PREFIX_0FD6) },
2844   { MOD_TABLE (MOD_0FD7) },
2845   /* d8 */
2846   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2847   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2848   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2849   { "pand",             { MX, EM }, PREFIX_OPCODE },
2850   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2851   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2852   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2853   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2854   /* e0 */
2855   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2856   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2857   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2858   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2859   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2860   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2861   { PREFIX_TABLE (PREFIX_0FE6) },
2862   { PREFIX_TABLE (PREFIX_0FE7) },
2863   /* e8 */
2864   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2865   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2866   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2867   { "por",              { MX, EM }, PREFIX_OPCODE },
2868   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2869   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2870   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2871   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2872   /* f0 */
2873   { PREFIX_TABLE (PREFIX_0FF0) },
2874   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2875   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2876   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2877   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2878   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2879   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2880   { PREFIX_TABLE (PREFIX_0FF7) },
2881   /* f8 */
2882   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2883   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2884   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2885   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2886   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2887   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2888   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2889   { "ud0S",             { Gv, Ev }, 0 },
2890 };
2891
2892 static const unsigned char onebyte_has_modrm[256] = {
2893   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2894   /*       -------------------------------        */
2895   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2896   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2897   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2898   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2899   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2900   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2901   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2902   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2903   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2904   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2905   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2906   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2907   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2908   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2909   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2910   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2911   /*       -------------------------------        */
2912   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2913 };
2914
2915 static const unsigned char twobyte_has_modrm[256] = {
2916   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2917   /*       -------------------------------        */
2918   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2919   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2920   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2921   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2922   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2923   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2924   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2925   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2926   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2927   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2928   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2929   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2930   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2931   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2932   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2933   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2934   /*       -------------------------------        */
2935   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2936 };
2937
2938 static char obuf[100];
2939 static char *obufp;
2940 static char *mnemonicendp;
2941 static char scratchbuf[100];
2942 static unsigned char *start_codep;
2943 static unsigned char *insn_codep;
2944 static unsigned char *codep;
2945 static unsigned char *end_codep;
2946 static int last_lock_prefix;
2947 static int last_repz_prefix;
2948 static int last_repnz_prefix;
2949 static int last_data_prefix;
2950 static int last_addr_prefix;
2951 static int last_rex_prefix;
2952 static int last_seg_prefix;
2953 static int fwait_prefix;
2954 /* The active segment register prefix.  */
2955 static int active_seg_prefix;
2956 #define MAX_CODE_LENGTH 15
2957 /* We can up to 14 prefixes since the maximum instruction length is
2958    15bytes.  */
2959 static int all_prefixes[MAX_CODE_LENGTH - 1];
2960 static disassemble_info *the_info;
2961 static struct
2962   {
2963     int mod;
2964     int reg;
2965     int rm;
2966   }
2967 modrm;
2968 static unsigned char need_modrm;
2969 static struct
2970   {
2971     int scale;
2972     int index;
2973     int base;
2974   }
2975 sib;
2976 static struct
2977   {
2978     int register_specifier;
2979     int length;
2980     int prefix;
2981     int w;
2982     int evex;
2983     int r;
2984     int v;
2985     int mask_register_specifier;
2986     int zeroing;
2987     int ll;
2988     int b;
2989   }
2990 vex;
2991 static unsigned char need_vex;
2992 static unsigned char need_vex_reg;
2993
2994 struct op
2995   {
2996     const char *name;
2997     unsigned int len;
2998   };
2999
3000 /* If we are accessing mod/rm/reg without need_modrm set, then the
3001    values are stale.  Hitting this abort likely indicates that you
3002    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3003 #define MODRM_CHECK  if (!need_modrm) abort ()
3004
3005 static const char **names64;
3006 static const char **names32;
3007 static const char **names16;
3008 static const char **names8;
3009 static const char **names8rex;
3010 static const char **names_seg;
3011 static const char *index64;
3012 static const char *index32;
3013 static const char **index16;
3014 static const char **names_bnd;
3015
3016 static const char *intel_names64[] = {
3017   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3018   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3019 };
3020 static const char *intel_names32[] = {
3021   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3022   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3023 };
3024 static const char *intel_names16[] = {
3025   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3026   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3027 };
3028 static const char *intel_names8[] = {
3029   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3030 };
3031 static const char *intel_names8rex[] = {
3032   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3033   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3034 };
3035 static const char *intel_names_seg[] = {
3036   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3037 };
3038 static const char *intel_index64 = "riz";
3039 static const char *intel_index32 = "eiz";
3040 static const char *intel_index16[] = {
3041   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3042 };
3043
3044 static const char *att_names64[] = {
3045   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3046   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3047 };
3048 static const char *att_names32[] = {
3049   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3050   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3051 };
3052 static const char *att_names16[] = {
3053   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3054   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3055 };
3056 static const char *att_names8[] = {
3057   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3058 };
3059 static const char *att_names8rex[] = {
3060   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3061   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3062 };
3063 static const char *att_names_seg[] = {
3064   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3065 };
3066 static const char *att_index64 = "%riz";
3067 static const char *att_index32 = "%eiz";
3068 static const char *att_index16[] = {
3069   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3070 };
3071
3072 static const char **names_mm;
3073 static const char *intel_names_mm[] = {
3074   "mm0", "mm1", "mm2", "mm3",
3075   "mm4", "mm5", "mm6", "mm7"
3076 };
3077 static const char *att_names_mm[] = {
3078   "%mm0", "%mm1", "%mm2", "%mm3",
3079   "%mm4", "%mm5", "%mm6", "%mm7"
3080 };
3081
3082 static const char *intel_names_bnd[] = {
3083   "bnd0", "bnd1", "bnd2", "bnd3"
3084 };
3085
3086 static const char *att_names_bnd[] = {
3087   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3088 };
3089
3090 static const char **names_xmm;
3091 static const char *intel_names_xmm[] = {
3092   "xmm0", "xmm1", "xmm2", "xmm3",
3093   "xmm4", "xmm5", "xmm6", "xmm7",
3094   "xmm8", "xmm9", "xmm10", "xmm11",
3095   "xmm12", "xmm13", "xmm14", "xmm15",
3096   "xmm16", "xmm17", "xmm18", "xmm19",
3097   "xmm20", "xmm21", "xmm22", "xmm23",
3098   "xmm24", "xmm25", "xmm26", "xmm27",
3099   "xmm28", "xmm29", "xmm30", "xmm31"
3100 };
3101 static const char *att_names_xmm[] = {
3102   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3103   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3104   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3105   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3106   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3107   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3108   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3109   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3110 };
3111
3112 static const char **names_ymm;
3113 static const char *intel_names_ymm[] = {
3114   "ymm0", "ymm1", "ymm2", "ymm3",
3115   "ymm4", "ymm5", "ymm6", "ymm7",
3116   "ymm8", "ymm9", "ymm10", "ymm11",
3117   "ymm12", "ymm13", "ymm14", "ymm15",
3118   "ymm16", "ymm17", "ymm18", "ymm19",
3119   "ymm20", "ymm21", "ymm22", "ymm23",
3120   "ymm24", "ymm25", "ymm26", "ymm27",
3121   "ymm28", "ymm29", "ymm30", "ymm31"
3122 };
3123 static const char *att_names_ymm[] = {
3124   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3125   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3126   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3127   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3128   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3129   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3130   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3131   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3132 };
3133
3134 static const char **names_zmm;
3135 static const char *intel_names_zmm[] = {
3136   "zmm0", "zmm1", "zmm2", "zmm3",
3137   "zmm4", "zmm5", "zmm6", "zmm7",
3138   "zmm8", "zmm9", "zmm10", "zmm11",
3139   "zmm12", "zmm13", "zmm14", "zmm15",
3140   "zmm16", "zmm17", "zmm18", "zmm19",
3141   "zmm20", "zmm21", "zmm22", "zmm23",
3142   "zmm24", "zmm25", "zmm26", "zmm27",
3143   "zmm28", "zmm29", "zmm30", "zmm31"
3144 };
3145 static const char *att_names_zmm[] = {
3146   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3147   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3148   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3149   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3150   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3151   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3152   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3153   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3154 };
3155
3156 static const char **names_tmm;
3157 static const char *intel_names_tmm[] = {
3158   "tmm0", "tmm1", "tmm2", "tmm3",
3159   "tmm4", "tmm5", "tmm6", "tmm7"
3160 };
3161 static const char *att_names_tmm[] = {
3162   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
3163   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
3164 };
3165
3166 static const char **names_mask;
3167 static const char *intel_names_mask[] = {
3168   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3169 };
3170 static const char *att_names_mask[] = {
3171   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3172 };
3173
3174 static const char *names_rounding[] =
3175 {
3176   "{rn-sae}",
3177   "{rd-sae}",
3178   "{ru-sae}",
3179   "{rz-sae}"
3180 };
3181
3182 static const struct dis386 reg_table[][8] = {
3183   /* REG_80 */
3184   {
3185     { "addA",   { Ebh1, Ib }, 0 },
3186     { "orA",    { Ebh1, Ib }, 0 },
3187     { "adcA",   { Ebh1, Ib }, 0 },
3188     { "sbbA",   { Ebh1, Ib }, 0 },
3189     { "andA",   { Ebh1, Ib }, 0 },
3190     { "subA",   { Ebh1, Ib }, 0 },
3191     { "xorA",   { Ebh1, Ib }, 0 },
3192     { "cmpA",   { Eb, Ib }, 0 },
3193   },
3194   /* REG_81 */
3195   {
3196     { "addQ",   { Evh1, Iv }, 0 },
3197     { "orQ",    { Evh1, Iv }, 0 },
3198     { "adcQ",   { Evh1, Iv }, 0 },
3199     { "sbbQ",   { Evh1, Iv }, 0 },
3200     { "andQ",   { Evh1, Iv }, 0 },
3201     { "subQ",   { Evh1, Iv }, 0 },
3202     { "xorQ",   { Evh1, Iv }, 0 },
3203     { "cmpQ",   { Ev, Iv }, 0 },
3204   },
3205   /* REG_83 */
3206   {
3207     { "addQ",   { Evh1, sIb }, 0 },
3208     { "orQ",    { Evh1, sIb }, 0 },
3209     { "adcQ",   { Evh1, sIb }, 0 },
3210     { "sbbQ",   { Evh1, sIb }, 0 },
3211     { "andQ",   { Evh1, sIb }, 0 },
3212     { "subQ",   { Evh1, sIb }, 0 },
3213     { "xorQ",   { Evh1, sIb }, 0 },
3214     { "cmpQ",   { Ev, sIb }, 0 },
3215   },
3216   /* REG_8F */
3217   {
3218     { "popU",   { stackEv }, 0 },
3219     { XOP_8F_TABLE (XOP_09) },
3220     { Bad_Opcode },
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { XOP_8F_TABLE (XOP_09) },
3224   },
3225   /* REG_C0 */
3226   {
3227     { "rolA",   { Eb, Ib }, 0 },
3228     { "rorA",   { Eb, Ib }, 0 },
3229     { "rclA",   { Eb, Ib }, 0 },
3230     { "rcrA",   { Eb, Ib }, 0 },
3231     { "shlA",   { Eb, Ib }, 0 },
3232     { "shrA",   { Eb, Ib }, 0 },
3233     { "shlA",   { Eb, Ib }, 0 },
3234     { "sarA",   { Eb, Ib }, 0 },
3235   },
3236   /* REG_C1 */
3237   {
3238     { "rolQ",   { Ev, Ib }, 0 },
3239     { "rorQ",   { Ev, Ib }, 0 },
3240     { "rclQ",   { Ev, Ib }, 0 },
3241     { "rcrQ",   { Ev, Ib }, 0 },
3242     { "shlQ",   { Ev, Ib }, 0 },
3243     { "shrQ",   { Ev, Ib }, 0 },
3244     { "shlQ",   { Ev, Ib }, 0 },
3245     { "sarQ",   { Ev, Ib }, 0 },
3246   },
3247   /* REG_C6 */
3248   {
3249     { "movA",   { Ebh3, Ib }, 0 },
3250     { Bad_Opcode },
3251     { Bad_Opcode },
3252     { Bad_Opcode },
3253     { Bad_Opcode },
3254     { Bad_Opcode },
3255     { Bad_Opcode },
3256     { MOD_TABLE (MOD_C6_REG_7) },
3257   },
3258   /* REG_C7 */
3259   {
3260     { "movQ",   { Evh3, Iv }, 0 },
3261     { Bad_Opcode },
3262     { Bad_Opcode },
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { Bad_Opcode },
3267     { MOD_TABLE (MOD_C7_REG_7) },
3268   },
3269   /* REG_D0 */
3270   {
3271     { "rolA",   { Eb, I1 }, 0 },
3272     { "rorA",   { Eb, I1 }, 0 },
3273     { "rclA",   { Eb, I1 }, 0 },
3274     { "rcrA",   { Eb, I1 }, 0 },
3275     { "shlA",   { Eb, I1 }, 0 },
3276     { "shrA",   { Eb, I1 }, 0 },
3277     { "shlA",   { Eb, I1 }, 0 },
3278     { "sarA",   { Eb, I1 }, 0 },
3279   },
3280   /* REG_D1 */
3281   {
3282     { "rolQ",   { Ev, I1 }, 0 },
3283     { "rorQ",   { Ev, I1 }, 0 },
3284     { "rclQ",   { Ev, I1 }, 0 },
3285     { "rcrQ",   { Ev, I1 }, 0 },
3286     { "shlQ",   { Ev, I1 }, 0 },
3287     { "shrQ",   { Ev, I1 }, 0 },
3288     { "shlQ",   { Ev, I1 }, 0 },
3289     { "sarQ",   { Ev, I1 }, 0 },
3290   },
3291   /* REG_D2 */
3292   {
3293     { "rolA",   { Eb, CL }, 0 },
3294     { "rorA",   { Eb, CL }, 0 },
3295     { "rclA",   { Eb, CL }, 0 },
3296     { "rcrA",   { Eb, CL }, 0 },
3297     { "shlA",   { Eb, CL }, 0 },
3298     { "shrA",   { Eb, CL }, 0 },
3299     { "shlA",   { Eb, CL }, 0 },
3300     { "sarA",   { Eb, CL }, 0 },
3301   },
3302   /* REG_D3 */
3303   {
3304     { "rolQ",   { Ev, CL }, 0 },
3305     { "rorQ",   { Ev, CL }, 0 },
3306     { "rclQ",   { Ev, CL }, 0 },
3307     { "rcrQ",   { Ev, CL }, 0 },
3308     { "shlQ",   { Ev, CL }, 0 },
3309     { "shrQ",   { Ev, CL }, 0 },
3310     { "shlQ",   { Ev, CL }, 0 },
3311     { "sarQ",   { Ev, CL }, 0 },
3312   },
3313   /* REG_F6 */
3314   {
3315     { "testA",  { Eb, Ib }, 0 },
3316     { "testA",  { Eb, Ib }, 0 },
3317     { "notA",   { Ebh1 }, 0 },
3318     { "negA",   { Ebh1 }, 0 },
3319     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3320     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3321     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3322     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3323   },
3324   /* REG_F7 */
3325   {
3326     { "testQ",  { Ev, Iv }, 0 },
3327     { "testQ",  { Ev, Iv }, 0 },
3328     { "notQ",   { Evh1 }, 0 },
3329     { "negQ",   { Evh1 }, 0 },
3330     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3331     { "imulQ",  { Ev }, 0 },
3332     { "divQ",   { Ev }, 0 },
3333     { "idivQ",  { Ev }, 0 },
3334   },
3335   /* REG_FE */
3336   {
3337     { "incA",   { Ebh1 }, 0 },
3338     { "decA",   { Ebh1 }, 0 },
3339   },
3340   /* REG_FF */
3341   {
3342     { "incQ",   { Evh1 }, 0 },
3343     { "decQ",   { Evh1 }, 0 },
3344     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3345     { MOD_TABLE (MOD_FF_REG_3) },
3346     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3347     { MOD_TABLE (MOD_FF_REG_5) },
3348     { "pushU",  { stackEv }, 0 },
3349     { Bad_Opcode },
3350   },
3351   /* REG_0F00 */
3352   {
3353     { "sldtD",  { Sv }, 0 },
3354     { "strD",   { Sv }, 0 },
3355     { "lldt",   { Ew }, 0 },
3356     { "ltr",    { Ew }, 0 },
3357     { "verr",   { Ew }, 0 },
3358     { "verw",   { Ew }, 0 },
3359     { Bad_Opcode },
3360     { Bad_Opcode },
3361   },
3362   /* REG_0F01 */
3363   {
3364     { MOD_TABLE (MOD_0F01_REG_0) },
3365     { MOD_TABLE (MOD_0F01_REG_1) },
3366     { MOD_TABLE (MOD_0F01_REG_2) },
3367     { MOD_TABLE (MOD_0F01_REG_3) },
3368     { "smswD",  { Sv }, 0 },
3369     { MOD_TABLE (MOD_0F01_REG_5) },
3370     { "lmsw",   { Ew }, 0 },
3371     { MOD_TABLE (MOD_0F01_REG_7) },
3372   },
3373   /* REG_0F0D */
3374   {
3375     { "prefetch",       { Mb }, 0 },
3376     { "prefetchw",      { Mb }, 0 },
3377     { "prefetchwt1",    { Mb }, 0 },
3378     { "prefetch",       { Mb }, 0 },
3379     { "prefetch",       { Mb }, 0 },
3380     { "prefetch",       { Mb }, 0 },
3381     { "prefetch",       { Mb }, 0 },
3382     { "prefetch",       { Mb }, 0 },
3383   },
3384   /* REG_0F18 */
3385   {
3386     { MOD_TABLE (MOD_0F18_REG_0) },
3387     { MOD_TABLE (MOD_0F18_REG_1) },
3388     { MOD_TABLE (MOD_0F18_REG_2) },
3389     { MOD_TABLE (MOD_0F18_REG_3) },
3390     { MOD_TABLE (MOD_0F18_REG_4) },
3391     { MOD_TABLE (MOD_0F18_REG_5) },
3392     { MOD_TABLE (MOD_0F18_REG_6) },
3393     { MOD_TABLE (MOD_0F18_REG_7) },
3394   },
3395   /* REG_0F1C_P_0_MOD_0 */
3396   {
3397     { "cldemote",       { Mb }, 0 },
3398     { "nopQ",           { Ev }, 0 },
3399     { "nopQ",           { Ev }, 0 },
3400     { "nopQ",           { Ev }, 0 },
3401     { "nopQ",           { Ev }, 0 },
3402     { "nopQ",           { Ev }, 0 },
3403     { "nopQ",           { Ev }, 0 },
3404     { "nopQ",           { Ev }, 0 },
3405   },
3406   /* REG_0F1E_P_1_MOD_3 */
3407   {
3408     { "nopQ",           { Ev }, 0 },
3409     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3410     { "nopQ",           { Ev }, 0 },
3411     { "nopQ",           { Ev }, 0 },
3412     { "nopQ",           { Ev }, 0 },
3413     { "nopQ",           { Ev }, 0 },
3414     { "nopQ",           { Ev }, 0 },
3415     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3416   },
3417   /* REG_0F71 */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { MOD_TABLE (MOD_0F71_REG_2) },
3422     { Bad_Opcode },
3423     { MOD_TABLE (MOD_0F71_REG_4) },
3424     { Bad_Opcode },
3425     { MOD_TABLE (MOD_0F71_REG_6) },
3426   },
3427   /* REG_0F72 */
3428   {
3429     { Bad_Opcode },
3430     { Bad_Opcode },
3431     { MOD_TABLE (MOD_0F72_REG_2) },
3432     { Bad_Opcode },
3433     { MOD_TABLE (MOD_0F72_REG_4) },
3434     { Bad_Opcode },
3435     { MOD_TABLE (MOD_0F72_REG_6) },
3436   },
3437   /* REG_0F73 */
3438   {
3439     { Bad_Opcode },
3440     { Bad_Opcode },
3441     { MOD_TABLE (MOD_0F73_REG_2) },
3442     { MOD_TABLE (MOD_0F73_REG_3) },
3443     { Bad_Opcode },
3444     { Bad_Opcode },
3445     { MOD_TABLE (MOD_0F73_REG_6) },
3446     { MOD_TABLE (MOD_0F73_REG_7) },
3447   },
3448   /* REG_0FA6 */
3449   {
3450     { "montmul",        { { OP_0f07, 0 } }, 0 },
3451     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3452     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3453   },
3454   /* REG_0FA7 */
3455   {
3456     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3457     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3458     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3459     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3460     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3461     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3462   },
3463   /* REG_0FAE */
3464   {
3465     { MOD_TABLE (MOD_0FAE_REG_0) },
3466     { MOD_TABLE (MOD_0FAE_REG_1) },
3467     { MOD_TABLE (MOD_0FAE_REG_2) },
3468     { MOD_TABLE (MOD_0FAE_REG_3) },
3469     { MOD_TABLE (MOD_0FAE_REG_4) },
3470     { MOD_TABLE (MOD_0FAE_REG_5) },
3471     { MOD_TABLE (MOD_0FAE_REG_6) },
3472     { MOD_TABLE (MOD_0FAE_REG_7) },
3473   },
3474   /* REG_0FBA */
3475   {
3476     { Bad_Opcode },
3477     { Bad_Opcode },
3478     { Bad_Opcode },
3479     { Bad_Opcode },
3480     { "btQ",    { Ev, Ib }, 0 },
3481     { "btsQ",   { Evh1, Ib }, 0 },
3482     { "btrQ",   { Evh1, Ib }, 0 },
3483     { "btcQ",   { Evh1, Ib }, 0 },
3484   },
3485   /* REG_0FC7 */
3486   {
3487     { Bad_Opcode },
3488     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0FC7_REG_3) },
3491     { MOD_TABLE (MOD_0FC7_REG_4) },
3492     { MOD_TABLE (MOD_0FC7_REG_5) },
3493     { MOD_TABLE (MOD_0FC7_REG_6) },
3494     { MOD_TABLE (MOD_0FC7_REG_7) },
3495   },
3496   /* REG_VEX_0F71 */
3497   {
3498     { Bad_Opcode },
3499     { Bad_Opcode },
3500     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3501     { Bad_Opcode },
3502     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3503     { Bad_Opcode },
3504     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3505   },
3506   /* REG_VEX_0F72 */
3507   {
3508     { Bad_Opcode },
3509     { Bad_Opcode },
3510     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3511     { Bad_Opcode },
3512     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3513     { Bad_Opcode },
3514     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3515   },
3516   /* REG_VEX_0F73 */
3517   {
3518     { Bad_Opcode },
3519     { Bad_Opcode },
3520     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3521     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3525     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3526   },
3527   /* REG_VEX_0FAE */
3528   {
3529     { Bad_Opcode },
3530     { Bad_Opcode },
3531     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3532     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3533   },
3534   /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
3535   {
3536     { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
3537   },
3538   /* REG_VEX_0F38F3 */
3539   {
3540     { Bad_Opcode },
3541     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3542     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3543     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3544   },
3545   /* REG_0FXOP_09_01_L_0 */
3546   {
3547     { Bad_Opcode },
3548     { "blcfill",        { VexGdq, Edq }, 0 },
3549     { "blsfill",        { VexGdq, Edq }, 0 },
3550     { "blcs",   { VexGdq, Edq }, 0 },
3551     { "tzmsk",  { VexGdq, Edq }, 0 },
3552     { "blcic",  { VexGdq, Edq }, 0 },
3553     { "blsic",  { VexGdq, Edq }, 0 },
3554     { "t1mskc", { VexGdq, Edq }, 0 },
3555   },
3556   /* REG_0FXOP_09_02_L_0 */
3557   {
3558     { Bad_Opcode },
3559     { "blcmsk", { VexGdq, Edq }, 0 },
3560     { Bad_Opcode },
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { Bad_Opcode },
3564     { "blci",   { VexGdq, Edq }, 0 },
3565   },
3566   /* REG_0FXOP_09_12_M_1_L_0 */
3567   {
3568     { "llwpcb", { Edq }, 0 },
3569     { "slwpcb", { Edq }, 0 },
3570   },
3571   /* REG_0FXOP_0A_12_L_0 */
3572   {
3573     { "lwpins", { VexGdq, Ed, Id }, 0 },
3574     { "lwpval", { VexGdq, Ed, Id }, 0 },
3575   },
3576
3577 #include "i386-dis-evex-reg.h"
3578 };
3579
3580 static const struct dis386 prefix_table[][4] = {
3581   /* PREFIX_90 */
3582   {
3583     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3584     { "pause", { XX }, 0 },
3585     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3586     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3587   },
3588
3589   /* PREFIX_0F01_REG_3_RM_1 */
3590   {
3591     { "vmmcall",        { Skip_MODRM }, 0 },
3592     { "vmgexit",        { Skip_MODRM }, 0 },
3593     { Bad_Opcode },
3594     { "vmgexit",        { Skip_MODRM }, 0 },
3595   },
3596
3597   /* PREFIX_0F01_REG_5_MOD_0 */
3598   {
3599     { Bad_Opcode },
3600     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3601   },
3602
3603   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3604   {
3605     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3606     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3607     { Bad_Opcode },
3608     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3609   },
3610
3611   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3612   {
3613     { Bad_Opcode },
3614     { Bad_Opcode },
3615     { Bad_Opcode },
3616     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3617   },
3618
3619   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3620   {
3621     { Bad_Opcode },
3622     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3623   },
3624
3625   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3626   {
3627     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3628     { "mcommit",        { Skip_MODRM }, 0 },
3629   },
3630
3631   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3632   {
3633     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3634   },
3635
3636   /* PREFIX_0F09 */
3637   {
3638     { "wbinvd",   { XX }, 0 },
3639     { "wbnoinvd", { XX }, 0 },
3640   },
3641
3642   /* PREFIX_0F10 */
3643   {
3644     { "movups", { XM, EXx }, PREFIX_OPCODE },
3645     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3646     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3647     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3648   },
3649
3650   /* PREFIX_0F11 */
3651   {
3652     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3653     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3654     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3655     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3656   },
3657
3658   /* PREFIX_0F12 */
3659   {
3660     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3661     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3662     { MOD_TABLE (MOD_0F12_PREFIX_2) },
3663     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3664   },
3665
3666   /* PREFIX_0F16 */
3667   {
3668     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3669     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3670     { MOD_TABLE (MOD_0F16_PREFIX_2) },
3671   },
3672
3673   /* PREFIX_0F1A */
3674   {
3675     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3676     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3677     { "bndmov", { Gbnd, Ebnd }, 0 },
3678     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3679   },
3680
3681   /* PREFIX_0F1B */
3682   {
3683     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3684     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3685     { "bndmov", { EbndS, Gbnd }, 0 },
3686     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3687   },
3688
3689   /* PREFIX_0F1C */
3690   {
3691     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3692     { "nopQ",   { Ev }, PREFIX_OPCODE },
3693     { "nopQ",   { Ev }, PREFIX_OPCODE },
3694     { "nopQ",   { Ev }, PREFIX_OPCODE },
3695   },
3696
3697   /* PREFIX_0F1E */
3698   {
3699     { "nopQ",   { Ev }, PREFIX_OPCODE },
3700     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3701     { "nopQ",   { Ev }, PREFIX_OPCODE },
3702     { "nopQ",   { Ev }, PREFIX_OPCODE },
3703   },
3704
3705   /* PREFIX_0F2A */
3706   {
3707     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3708     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3709     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3710     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3711   },
3712
3713   /* PREFIX_0F2B */
3714   {
3715     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3716     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3717     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3718     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3719   },
3720
3721   /* PREFIX_0F2C */
3722   {
3723     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3724     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3725     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3726     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3727   },
3728
3729   /* PREFIX_0F2D */
3730   {
3731     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3732     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3733     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3734     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3735   },
3736
3737   /* PREFIX_0F2E */
3738   {
3739     { "ucomiss",{ XM, EXd }, 0 },
3740     { Bad_Opcode },
3741     { "ucomisd",{ XM, EXq }, 0 },
3742   },
3743
3744   /* PREFIX_0F2F */
3745   {
3746     { "comiss", { XM, EXd }, 0 },
3747     { Bad_Opcode },
3748     { "comisd", { XM, EXq }, 0 },
3749   },
3750
3751   /* PREFIX_0F51 */
3752   {
3753     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3754     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3755     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3756     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3757   },
3758
3759   /* PREFIX_0F52 */
3760   {
3761     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3762     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3763   },
3764
3765   /* PREFIX_0F53 */
3766   {
3767     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3768     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3769   },
3770
3771   /* PREFIX_0F58 */
3772   {
3773     { "addps", { XM, EXx }, PREFIX_OPCODE },
3774     { "addss", { XM, EXd }, PREFIX_OPCODE },
3775     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3776     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3777   },
3778
3779   /* PREFIX_0F59 */
3780   {
3781     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3782     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3783     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3784     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3785   },
3786
3787   /* PREFIX_0F5A */
3788   {
3789     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3790     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3791     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3792     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3793   },
3794
3795   /* PREFIX_0F5B */
3796   {
3797     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3798     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3799     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3800   },
3801
3802   /* PREFIX_0F5C */
3803   {
3804     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3805     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3806     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3807     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3808   },
3809
3810   /* PREFIX_0F5D */
3811   {
3812     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3813     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3814     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3815     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3816   },
3817
3818   /* PREFIX_0F5E */
3819   {
3820     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3821     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3822     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3823     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3824   },
3825
3826   /* PREFIX_0F5F */
3827   {
3828     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3829     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3830     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3831     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3832   },
3833
3834   /* PREFIX_0F60 */
3835   {
3836     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3837     { Bad_Opcode },
3838     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F61 */
3842   {
3843     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3844     { Bad_Opcode },
3845     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3846   },
3847
3848   /* PREFIX_0F62 */
3849   {
3850     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3851     { Bad_Opcode },
3852     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3853   },
3854
3855   /* PREFIX_0F6C */
3856   {
3857     { Bad_Opcode },
3858     { Bad_Opcode },
3859     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3860   },
3861
3862   /* PREFIX_0F6D */
3863   {
3864     { Bad_Opcode },
3865     { Bad_Opcode },
3866     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F6F */
3870   {
3871     { "movq",   { MX, EM }, PREFIX_OPCODE },
3872     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3873     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3874   },
3875
3876   /* PREFIX_0F70 */
3877   {
3878     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3879     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3880     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3881     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3882   },
3883
3884   /* PREFIX_0F73_REG_3 */
3885   {
3886     { Bad_Opcode },
3887     { Bad_Opcode },
3888     { "psrldq", { XS, Ib }, 0 },
3889   },
3890
3891   /* PREFIX_0F73_REG_7 */
3892   {
3893     { Bad_Opcode },
3894     { Bad_Opcode },
3895     { "pslldq", { XS, Ib }, 0 },
3896   },
3897
3898   /* PREFIX_0F78 */
3899   {
3900     {"vmread",  { Em, Gm }, 0 },
3901     { Bad_Opcode },
3902     {"extrq",   { XS, Ib, Ib }, 0 },
3903     {"insertq", { XM, XS, Ib, Ib }, 0 },
3904   },
3905
3906   /* PREFIX_0F79 */
3907   {
3908     {"vmwrite", { Gm, Em }, 0 },
3909     { Bad_Opcode },
3910     {"extrq",   { XM, XS }, 0 },
3911     {"insertq", { XM, XS }, 0 },
3912   },
3913
3914   /* PREFIX_0F7C */
3915   {
3916     { Bad_Opcode },
3917     { Bad_Opcode },
3918     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3919     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F7D */
3923   {
3924     { Bad_Opcode },
3925     { Bad_Opcode },
3926     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3927     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F7E */
3931   {
3932     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3933     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3934     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3935   },
3936
3937   /* PREFIX_0F7F */
3938   {
3939     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3940     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3941     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3942   },
3943
3944   /* PREFIX_0FAE_REG_0_MOD_3 */
3945   {
3946     { Bad_Opcode },
3947     { "rdfsbase", { Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0FAE_REG_1_MOD_3 */
3951   {
3952     { Bad_Opcode },
3953     { "rdgsbase", { Ev }, 0 },
3954   },
3955
3956   /* PREFIX_0FAE_REG_2_MOD_3 */
3957   {
3958     { Bad_Opcode },
3959     { "wrfsbase", { Ev }, 0 },
3960   },
3961
3962   /* PREFIX_0FAE_REG_3_MOD_3 */
3963   {
3964     { Bad_Opcode },
3965     { "wrgsbase", { Ev }, 0 },
3966   },
3967
3968   /* PREFIX_0FAE_REG_4_MOD_0 */
3969   {
3970     { "xsave",  { FXSAVE }, 0 },
3971     { "ptwrite%LQ", { Edq }, 0 },
3972   },
3973
3974   /* PREFIX_0FAE_REG_4_MOD_3 */
3975   {
3976     { Bad_Opcode },
3977     { "ptwrite%LQ", { Edq }, 0 },
3978   },
3979
3980   /* PREFIX_0FAE_REG_5_MOD_0 */
3981   {
3982     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3983   },
3984
3985   /* PREFIX_0FAE_REG_5_MOD_3 */
3986   {
3987     { "lfence",         { Skip_MODRM }, 0 },
3988     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3989   },
3990
3991   /* PREFIX_0FAE_REG_6_MOD_0 */
3992   {
3993     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
3994     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3995     { "clwb",   { Mb }, PREFIX_OPCODE },
3996   },
3997
3998   /* PREFIX_0FAE_REG_6_MOD_3 */
3999   {
4000     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4001     { "umonitor",       { Eva }, PREFIX_OPCODE },
4002     { "tpause", { Edq }, PREFIX_OPCODE },
4003     { "umwait", { Edq }, PREFIX_OPCODE },
4004   },
4005
4006   /* PREFIX_0FAE_REG_7_MOD_0 */
4007   {
4008     { "clflush",        { Mb }, 0 },
4009     { Bad_Opcode },
4010     { "clflushopt",     { Mb }, 0 },
4011   },
4012
4013   /* PREFIX_0FB8 */
4014   {
4015     { Bad_Opcode },
4016     { "popcntS", { Gv, Ev }, 0 },
4017   },
4018
4019   /* PREFIX_0FBC */
4020   {
4021     { "bsfS",   { Gv, Ev }, 0 },
4022     { "tzcntS", { Gv, Ev }, 0 },
4023     { "bsfS",   { Gv, Ev }, 0 },
4024   },
4025
4026   /* PREFIX_0FBD */
4027   {
4028     { "bsrS",   { Gv, Ev }, 0 },
4029     { "lzcntS", { Gv, Ev }, 0 },
4030     { "bsrS",   { Gv, Ev }, 0 },
4031   },
4032
4033   /* PREFIX_0FC2 */
4034   {
4035     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4036     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4037     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4038     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0FC3_MOD_0 */
4042   {
4043     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4044   },
4045
4046   /* PREFIX_0FC7_REG_6_MOD_0 */
4047   {
4048     { "vmptrld",{ Mq }, 0 },
4049     { "vmxon",  { Mq }, 0 },
4050     { "vmclear",{ Mq }, 0 },
4051   },
4052
4053   /* PREFIX_0FC7_REG_6_MOD_3 */
4054   {
4055     { "rdrand", { Ev }, 0 },
4056     { Bad_Opcode },
4057     { "rdrand", { Ev }, 0 }
4058   },
4059
4060   /* PREFIX_0FC7_REG_7_MOD_3 */
4061   {
4062     { "rdseed", { Ev }, 0 },
4063     { "rdpid",  { Em }, 0 },
4064     { "rdseed", { Ev }, 0 },
4065   },
4066
4067   /* PREFIX_0FD0 */
4068   {
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { "addsubpd", { XM, EXx }, 0 },
4072     { "addsubps", { XM, EXx }, 0 },
4073   },
4074
4075   /* PREFIX_0FD6 */
4076   {
4077     { Bad_Opcode },
4078     { "movq2dq",{ XM, MS }, 0 },
4079     { "movq",   { EXqS, XM }, 0 },
4080     { "movdq2q",{ MX, XS }, 0 },
4081   },
4082
4083   /* PREFIX_0FE6 */
4084   {
4085     { Bad_Opcode },
4086     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4087     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4088     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4089   },
4090
4091   /* PREFIX_0FE7 */
4092   {
4093     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4094     { Bad_Opcode },
4095     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4096   },
4097
4098   /* PREFIX_0FF0 */
4099   {
4100     { Bad_Opcode },
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4104   },
4105
4106   /* PREFIX_0FF7 */
4107   {
4108     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4109     { Bad_Opcode },
4110     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F3810 */
4114   {
4115     { Bad_Opcode },
4116     { Bad_Opcode },
4117     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4118   },
4119
4120   /* PREFIX_0F3814 */
4121   {
4122     { Bad_Opcode },
4123     { Bad_Opcode },
4124     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4125   },
4126
4127   /* PREFIX_0F3815 */
4128   {
4129     { Bad_Opcode },
4130     { Bad_Opcode },
4131     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4132   },
4133
4134   /* PREFIX_0F3817 */
4135   {
4136     { Bad_Opcode },
4137     { Bad_Opcode },
4138     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4139   },
4140
4141   /* PREFIX_0F3820 */
4142   {
4143     { Bad_Opcode },
4144     { Bad_Opcode },
4145     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4146   },
4147
4148   /* PREFIX_0F3821 */
4149   {
4150     { Bad_Opcode },
4151     { Bad_Opcode },
4152     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4153   },
4154
4155   /* PREFIX_0F3822 */
4156   {
4157     { Bad_Opcode },
4158     { Bad_Opcode },
4159     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4160   },
4161
4162   /* PREFIX_0F3823 */
4163   {
4164     { Bad_Opcode },
4165     { Bad_Opcode },
4166     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4167   },
4168
4169   /* PREFIX_0F3824 */
4170   {
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0F3825 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4181   },
4182
4183   /* PREFIX_0F3828 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4188   },
4189
4190   /* PREFIX_0F3829 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4195   },
4196
4197   /* PREFIX_0F382A */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4202   },
4203
4204   /* PREFIX_0F382B */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4209   },
4210
4211   /* PREFIX_0F3830 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4216   },
4217
4218   /* PREFIX_0F3831 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4223   },
4224
4225   /* PREFIX_0F3832 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4230   },
4231
4232   /* PREFIX_0F3833 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4237   },
4238
4239   /* PREFIX_0F3834 */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4244   },
4245
4246   /* PREFIX_0F3835 */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4251   },
4252
4253   /* PREFIX_0F3837 */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4258   },
4259
4260   /* PREFIX_0F3838 */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4265   },
4266
4267   /* PREFIX_0F3839 */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4272   },
4273
4274   /* PREFIX_0F383A */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4279   },
4280
4281   /* PREFIX_0F383B */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4286   },
4287
4288   /* PREFIX_0F383C */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4293   },
4294
4295   /* PREFIX_0F383D */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4300   },
4301
4302   /* PREFIX_0F383E */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4307   },
4308
4309   /* PREFIX_0F383F */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4314   },
4315
4316   /* PREFIX_0F3840 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4321   },
4322
4323   /* PREFIX_0F3841 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4328   },
4329
4330   /* PREFIX_0F3880 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4335   },
4336
4337   /* PREFIX_0F3881 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4342   },
4343
4344   /* PREFIX_0F3882 */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4349   },
4350
4351   /* PREFIX_0F38C8 */
4352   {
4353     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4354   },
4355
4356   /* PREFIX_0F38C9 */
4357   {
4358     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38CA */
4362   {
4363     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38CB */
4367   {
4368     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F38CC */
4372   {
4373     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38CD */
4377   {
4378     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38CF */
4382   {
4383     { Bad_Opcode },
4384     { Bad_Opcode },
4385     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38DB */
4389   {
4390     { Bad_Opcode },
4391     { Bad_Opcode },
4392     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4393   },
4394
4395   /* PREFIX_0F38DC */
4396   {
4397     { Bad_Opcode },
4398     { Bad_Opcode },
4399     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4400   },
4401
4402   /* PREFIX_0F38DD */
4403   {
4404     { Bad_Opcode },
4405     { Bad_Opcode },
4406     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4407   },
4408
4409   /* PREFIX_0F38DE */
4410   {
4411     { Bad_Opcode },
4412     { Bad_Opcode },
4413     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4414   },
4415
4416   /* PREFIX_0F38DF */
4417   {
4418     { Bad_Opcode },
4419     { Bad_Opcode },
4420     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4421   },
4422
4423   /* PREFIX_0F38F0 */
4424   {
4425     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4426     { Bad_Opcode },
4427     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4428     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
4429   },
4430
4431   /* PREFIX_0F38F1 */
4432   {
4433     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4434     { Bad_Opcode },
4435     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4436     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
4437   },
4438
4439   /* PREFIX_0F38F5 */
4440   {
4441     { Bad_Opcode },
4442     { Bad_Opcode },
4443     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4444   },
4445
4446   /* PREFIX_0F38F6 */
4447   {
4448     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4449     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4450     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4451     { Bad_Opcode },
4452   },
4453
4454   /* PREFIX_0F38F8 */
4455   {
4456     { Bad_Opcode },
4457     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4458     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4459     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4460   },
4461
4462   /* PREFIX_0F38F9 */
4463   {
4464     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4465   },
4466
4467   /* PREFIX_0F3A08 */
4468   {
4469     { Bad_Opcode },
4470     { Bad_Opcode },
4471     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4472   },
4473
4474   /* PREFIX_0F3A09 */
4475   {
4476     { Bad_Opcode },
4477     { Bad_Opcode },
4478     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4479   },
4480
4481   /* PREFIX_0F3A0A */
4482   {
4483     { Bad_Opcode },
4484     { Bad_Opcode },
4485     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4486   },
4487
4488   /* PREFIX_0F3A0B */
4489   {
4490     { Bad_Opcode },
4491     { Bad_Opcode },
4492     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4493   },
4494
4495   /* PREFIX_0F3A0C */
4496   {
4497     { Bad_Opcode },
4498     { Bad_Opcode },
4499     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4500   },
4501
4502   /* PREFIX_0F3A0D */
4503   {
4504     { Bad_Opcode },
4505     { Bad_Opcode },
4506     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F3A0E */
4510   {
4511     { Bad_Opcode },
4512     { Bad_Opcode },
4513     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4514   },
4515
4516   /* PREFIX_0F3A14 */
4517   {
4518     { Bad_Opcode },
4519     { Bad_Opcode },
4520     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4521   },
4522
4523   /* PREFIX_0F3A15 */
4524   {
4525     { Bad_Opcode },
4526     { Bad_Opcode },
4527     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4528   },
4529
4530   /* PREFIX_0F3A16 */
4531   {
4532     { Bad_Opcode },
4533     { Bad_Opcode },
4534     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4535   },
4536
4537   /* PREFIX_0F3A17 */
4538   {
4539     { Bad_Opcode },
4540     { Bad_Opcode },
4541     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4542   },
4543
4544   /* PREFIX_0F3A20 */
4545   {
4546     { Bad_Opcode },
4547     { Bad_Opcode },
4548     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4549   },
4550
4551   /* PREFIX_0F3A21 */
4552   {
4553     { Bad_Opcode },
4554     { Bad_Opcode },
4555     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4556   },
4557
4558   /* PREFIX_0F3A22 */
4559   {
4560     { Bad_Opcode },
4561     { Bad_Opcode },
4562     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4563   },
4564
4565   /* PREFIX_0F3A40 */
4566   {
4567     { Bad_Opcode },
4568     { Bad_Opcode },
4569     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4570   },
4571
4572   /* PREFIX_0F3A41 */
4573   {
4574     { Bad_Opcode },
4575     { Bad_Opcode },
4576     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4577   },
4578
4579   /* PREFIX_0F3A42 */
4580   {
4581     { Bad_Opcode },
4582     { Bad_Opcode },
4583     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4584   },
4585
4586   /* PREFIX_0F3A44 */
4587   {
4588     { Bad_Opcode },
4589     { Bad_Opcode },
4590     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F3A60 */
4594   {
4595     { Bad_Opcode },
4596     { Bad_Opcode },
4597     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4598   },
4599
4600   /* PREFIX_0F3A61 */
4601   {
4602     { Bad_Opcode },
4603     { Bad_Opcode },
4604     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4605   },
4606
4607   /* PREFIX_0F3A62 */
4608   {
4609     { Bad_Opcode },
4610     { Bad_Opcode },
4611     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4612   },
4613
4614   /* PREFIX_0F3A63 */
4615   {
4616     { Bad_Opcode },
4617     { Bad_Opcode },
4618     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4619   },
4620
4621   /* PREFIX_0F3ACC */
4622   {
4623     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4624   },
4625
4626   /* PREFIX_0F3ACE */
4627   {
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4631   },
4632
4633   /* PREFIX_0F3ACF */
4634   {
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4638   },
4639
4640   /* PREFIX_0F3ADF */
4641   {
4642     { Bad_Opcode },
4643     { Bad_Opcode },
4644     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4645   },
4646
4647   /* PREFIX_VEX_0F10 */
4648   {
4649     { "vmovups",        { XM, EXx }, 0 },
4650     { "vmovss",         { XMVexScalar, VexScalar, EXxmm_md }, 0 },
4651     { "vmovupd",        { XM, EXx }, 0 },
4652     { "vmovsd",         { XMVexScalar, VexScalar, EXxmm_mq }, 0 },
4653   },
4654
4655   /* PREFIX_VEX_0F11 */
4656   {
4657     { "vmovups",        { EXxS, XM }, 0 },
4658     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4659     { "vmovupd",        { EXxS, XM }, 0 },
4660     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4661   },
4662
4663   /* PREFIX_VEX_0F12 */
4664   {
4665     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4666     { "vmovsldup",      { XM, EXx }, 0 },
4667     { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
4668     { "vmovddup",       { XM, EXymmq }, 0 },
4669   },
4670
4671   /* PREFIX_VEX_0F16 */
4672   {
4673     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4674     { "vmovshdup",      { XM, EXx }, 0 },
4675     { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
4676   },
4677
4678   /* PREFIX_VEX_0F2A */
4679   {
4680     { Bad_Opcode },
4681     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4682     { Bad_Opcode },
4683     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4684   },
4685
4686   /* PREFIX_VEX_0F2C */
4687   {
4688     { Bad_Opcode },
4689     { "vcvttss2si",     { Gdq, EXxmm_md }, 0 },
4690     { Bad_Opcode },
4691     { "vcvttsd2si",     { Gdq, EXxmm_mq }, 0 },
4692   },
4693
4694   /* PREFIX_VEX_0F2D */
4695   {
4696     { Bad_Opcode },
4697     { "vcvtss2si",      { Gdq, EXxmm_md }, 0 },
4698     { Bad_Opcode },
4699     { "vcvtsd2si",      { Gdq, EXxmm_mq }, 0 },
4700   },
4701
4702   /* PREFIX_VEX_0F2E */
4703   {
4704     { "vucomiss",       { XMScalar, EXxmm_md }, 0 },
4705     { Bad_Opcode },
4706     { "vucomisd",       { XMScalar, EXxmm_mq }, 0 },
4707   },
4708
4709   /* PREFIX_VEX_0F2F */
4710   {
4711     { "vcomiss",        { XMScalar, EXxmm_md }, 0 },
4712     { Bad_Opcode },
4713     { "vcomisd",        { XMScalar, EXxmm_mq }, 0 },
4714   },
4715
4716   /* PREFIX_VEX_0F41 */
4717   {
4718     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4719     { Bad_Opcode },
4720     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4721   },
4722
4723   /* PREFIX_VEX_0F42 */
4724   {
4725     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4726     { Bad_Opcode },
4727     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4728   },
4729
4730   /* PREFIX_VEX_0F44 */
4731   {
4732     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4733     { Bad_Opcode },
4734     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4735   },
4736
4737   /* PREFIX_VEX_0F45 */
4738   {
4739     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4742   },
4743
4744   /* PREFIX_VEX_0F46 */
4745   {
4746     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4747     { Bad_Opcode },
4748     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4749   },
4750
4751   /* PREFIX_VEX_0F47 */
4752   {
4753     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4754     { Bad_Opcode },
4755     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4756   },
4757
4758   /* PREFIX_VEX_0F4A */
4759   {
4760     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4761     { Bad_Opcode },
4762     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4763   },
4764
4765   /* PREFIX_VEX_0F4B */
4766   {
4767     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4768     { Bad_Opcode },
4769     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4770   },
4771
4772   /* PREFIX_VEX_0F51 */
4773   {
4774     { "vsqrtps",        { XM, EXx }, 0 },
4775     { "vsqrtss",        { XMScalar, VexScalar, EXxmm_md }, 0 },
4776     { "vsqrtpd",        { XM, EXx }, 0 },
4777     { "vsqrtsd",        { XMScalar, VexScalar, EXxmm_mq }, 0 },
4778   },
4779
4780   /* PREFIX_VEX_0F52 */
4781   {
4782     { "vrsqrtps",       { XM, EXx }, 0 },
4783     { "vrsqrtss",       { XMScalar, VexScalar, EXxmm_md }, 0 },
4784   },
4785
4786   /* PREFIX_VEX_0F53 */
4787   {
4788     { "vrcpps",         { XM, EXx }, 0 },
4789     { "vrcpss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4790   },
4791
4792   /* PREFIX_VEX_0F58 */
4793   {
4794     { "vaddps",         { XM, Vex, EXx }, 0 },
4795     { "vaddss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4796     { "vaddpd",         { XM, Vex, EXx }, 0 },
4797     { "vaddsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4798   },
4799
4800   /* PREFIX_VEX_0F59 */
4801   {
4802     { "vmulps",         { XM, Vex, EXx }, 0 },
4803     { "vmulss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4804     { "vmulpd",         { XM, Vex, EXx }, 0 },
4805     { "vmulsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4806   },
4807
4808   /* PREFIX_VEX_0F5A */
4809   {
4810     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4811     { "vcvtss2sd",      { XMScalar, VexScalar, EXxmm_md }, 0 },
4812     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4813     { "vcvtsd2ss",      { XMScalar, VexScalar, EXxmm_mq }, 0 },
4814   },
4815
4816   /* PREFIX_VEX_0F5B */
4817   {
4818     { "vcvtdq2ps",      { XM, EXx }, 0 },
4819     { "vcvttps2dq",     { XM, EXx }, 0 },
4820     { "vcvtps2dq",      { XM, EXx }, 0 },
4821   },
4822
4823   /* PREFIX_VEX_0F5C */
4824   {
4825     { "vsubps",         { XM, Vex, EXx }, 0 },
4826     { "vsubss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4827     { "vsubpd",         { XM, Vex, EXx }, 0 },
4828     { "vsubsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4829   },
4830
4831   /* PREFIX_VEX_0F5D */
4832   {
4833     { "vminps",         { XM, Vex, EXx }, 0 },
4834     { "vminss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4835     { "vminpd",         { XM, Vex, EXx }, 0 },
4836     { "vminsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4837   },
4838
4839   /* PREFIX_VEX_0F5E */
4840   {
4841     { "vdivps",         { XM, Vex, EXx }, 0 },
4842     { "vdivss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4843     { "vdivpd",         { XM, Vex, EXx }, 0 },
4844     { "vdivsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4845   },
4846
4847   /* PREFIX_VEX_0F5F */
4848   {
4849     { "vmaxps",         { XM, Vex, EXx }, 0 },
4850     { "vmaxss",         { XMScalar, VexScalar, EXxmm_md }, 0 },
4851     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4852     { "vmaxsd",         { XMScalar, VexScalar, EXxmm_mq }, 0 },
4853   },
4854
4855   /* PREFIX_VEX_0F60 */
4856   {
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4860   },
4861
4862   /* PREFIX_VEX_0F61 */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4867   },
4868
4869   /* PREFIX_VEX_0F62 */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4874   },
4875
4876   /* PREFIX_VEX_0F63 */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4881   },
4882
4883   /* PREFIX_VEX_0F64 */
4884   {
4885     { Bad_Opcode },
4886     { Bad_Opcode },
4887     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4888   },
4889
4890   /* PREFIX_VEX_0F65 */
4891   {
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4895   },
4896
4897   /* PREFIX_VEX_0F66 */
4898   {
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4902   },
4903
4904   /* PREFIX_VEX_0F67 */
4905   {
4906     { Bad_Opcode },
4907     { Bad_Opcode },
4908     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4909   },
4910
4911   /* PREFIX_VEX_0F68 */
4912   {
4913     { Bad_Opcode },
4914     { Bad_Opcode },
4915     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4916   },
4917
4918   /* PREFIX_VEX_0F69 */
4919   {
4920     { Bad_Opcode },
4921     { Bad_Opcode },
4922     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4923   },
4924
4925   /* PREFIX_VEX_0F6A */
4926   {
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4930   },
4931
4932   /* PREFIX_VEX_0F6B */
4933   {
4934     { Bad_Opcode },
4935     { Bad_Opcode },
4936     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4937   },
4938
4939   /* PREFIX_VEX_0F6C */
4940   {
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4944   },
4945
4946   /* PREFIX_VEX_0F6D */
4947   {
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4951   },
4952
4953   /* PREFIX_VEX_0F6E */
4954   {
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4958   },
4959
4960   /* PREFIX_VEX_0F6F */
4961   {
4962     { Bad_Opcode },
4963     { "vmovdqu",        { XM, EXx }, 0 },
4964     { "vmovdqa",        { XM, EXx }, 0 },
4965   },
4966
4967   /* PREFIX_VEX_0F70 */
4968   {
4969     { Bad_Opcode },
4970     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4971     { "vpshufd",        { XM, EXx, Ib }, 0 },
4972     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4973   },
4974
4975   /* PREFIX_VEX_0F71_REG_2 */
4976   {
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4980   },
4981
4982   /* PREFIX_VEX_0F71_REG_4 */
4983   {
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { "vpsraw",         { Vex, XS, Ib }, 0 },
4987   },
4988
4989   /* PREFIX_VEX_0F71_REG_6 */
4990   {
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { "vpsllw",         { Vex, XS, Ib }, 0 },
4994   },
4995
4996   /* PREFIX_VEX_0F72_REG_2 */
4997   {
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { "vpsrld",         { Vex, XS, Ib }, 0 },
5001   },
5002
5003   /* PREFIX_VEX_0F72_REG_4 */
5004   {
5005     { Bad_Opcode },
5006     { Bad_Opcode },
5007     { "vpsrad",         { Vex, XS, Ib }, 0 },
5008   },
5009
5010   /* PREFIX_VEX_0F72_REG_6 */
5011   {
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { "vpslld",         { Vex, XS, Ib }, 0 },
5015   },
5016
5017   /* PREFIX_VEX_0F73_REG_2 */
5018   {
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5022   },
5023
5024   /* PREFIX_VEX_0F73_REG_3 */
5025   {
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5029   },
5030
5031   /* PREFIX_VEX_0F73_REG_6 */
5032   {
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { "vpsllq",         { Vex, XS, Ib }, 0 },
5036   },
5037
5038   /* PREFIX_VEX_0F73_REG_7 */
5039   {
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { "vpslldq",        { Vex, XS, Ib }, 0 },
5043   },
5044
5045   /* PREFIX_VEX_0F74 */
5046   {
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5050   },
5051
5052   /* PREFIX_VEX_0F75 */
5053   {
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5057   },
5058
5059   /* PREFIX_VEX_0F76 */
5060   {
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5064   },
5065
5066   /* PREFIX_VEX_0F77 */
5067   {
5068     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5069   },
5070
5071   /* PREFIX_VEX_0F7C */
5072   {
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5076     { "vhaddps",        { XM, Vex, EXx }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0F7D */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5084     { "vhsubps",        { XM, Vex, EXx }, 0 },
5085   },
5086
5087   /* PREFIX_VEX_0F7E */
5088   {
5089     { Bad_Opcode },
5090     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5091     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5092   },
5093
5094   /* PREFIX_VEX_0F7F */
5095   {
5096     { Bad_Opcode },
5097     { "vmovdqu",        { EXxS, XM }, 0 },
5098     { "vmovdqa",        { EXxS, XM }, 0 },
5099   },
5100
5101   /* PREFIX_VEX_0F90 */
5102   {
5103     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5104     { Bad_Opcode },
5105     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5106   },
5107
5108   /* PREFIX_VEX_0F91 */
5109   {
5110     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5111     { Bad_Opcode },
5112     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5113   },
5114
5115   /* PREFIX_VEX_0F92 */
5116   {
5117     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5118     { Bad_Opcode },
5119     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5120     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5121   },
5122
5123   /* PREFIX_VEX_0F93 */
5124   {
5125     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5126     { Bad_Opcode },
5127     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5128     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5129   },
5130
5131   /* PREFIX_VEX_0F98 */
5132   {
5133     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F99 */
5139   {
5140     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0FC2 */
5146   {
5147     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5148     { "vcmpss",         { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 },
5149     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5150     { "vcmpsd",         { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 },
5151   },
5152
5153   /* PREFIX_VEX_0FC4 */
5154   {
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5158   },
5159
5160   /* PREFIX_VEX_0FC5 */
5161   {
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5165   },
5166
5167   /* PREFIX_VEX_0FD0 */
5168   {
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5172     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5173   },
5174
5175   /* PREFIX_VEX_0FD1 */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5180   },
5181
5182   /* PREFIX_VEX_0FD2 */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5187   },
5188
5189   /* PREFIX_VEX_0FD3 */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5194   },
5195
5196   /* PREFIX_VEX_0FD4 */
5197   {
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { "vpaddq",         { XM, Vex, EXx }, 0 },
5201   },
5202
5203   /* PREFIX_VEX_0FD5 */
5204   {
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { "vpmullw",        { XM, Vex, EXx }, 0 },
5208   },
5209
5210   /* PREFIX_VEX_0FD6 */
5211   {
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5215   },
5216
5217   /* PREFIX_VEX_0FD7 */
5218   {
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5222   },
5223
5224   /* PREFIX_VEX_0FD8 */
5225   {
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5229   },
5230
5231   /* PREFIX_VEX_0FD9 */
5232   {
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5236   },
5237
5238   /* PREFIX_VEX_0FDA */
5239   {
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { "vpminub",        { XM, Vex, EXx }, 0 },
5243   },
5244
5245   /* PREFIX_VEX_0FDB */
5246   {
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { "vpand",          { XM, Vex, EXx }, 0 },
5250   },
5251
5252   /* PREFIX_VEX_0FDC */
5253   {
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5257   },
5258
5259   /* PREFIX_VEX_0FDD */
5260   {
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5264   },
5265
5266   /* PREFIX_VEX_0FDE */
5267   {
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5271   },
5272
5273   /* PREFIX_VEX_0FDF */
5274   {
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { "vpandn",         { XM, Vex, EXx }, 0 },
5278   },
5279
5280   /* PREFIX_VEX_0FE0 */
5281   {
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { "vpavgb",         { XM, Vex, EXx }, 0 },
5285   },
5286
5287   /* PREFIX_VEX_0FE1 */
5288   {
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5292   },
5293
5294   /* PREFIX_VEX_0FE2 */
5295   {
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5299   },
5300
5301   /* PREFIX_VEX_0FE3 */
5302   {
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { "vpavgw",         { XM, Vex, EXx }, 0 },
5306   },
5307
5308   /* PREFIX_VEX_0FE4 */
5309   {
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5313   },
5314
5315   /* PREFIX_VEX_0FE5 */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5320   },
5321
5322   /* PREFIX_VEX_0FE6 */
5323   {
5324     { Bad_Opcode },
5325     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5326     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5327     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5328   },
5329
5330   /* PREFIX_VEX_0FE7 */
5331   {
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5335   },
5336
5337   /* PREFIX_VEX_0FE8 */
5338   {
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5342   },
5343
5344   /* PREFIX_VEX_0FE9 */
5345   {
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5349   },
5350
5351   /* PREFIX_VEX_0FEA */
5352   {
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { "vpminsw",        { XM, Vex, EXx }, 0 },
5356   },
5357
5358   /* PREFIX_VEX_0FEB */
5359   {
5360     { Bad_Opcode },
5361     { Bad_Opcode },
5362     { "vpor",           { XM, Vex, EXx }, 0 },
5363   },
5364
5365   /* PREFIX_VEX_0FEC */
5366   {
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5370   },
5371
5372   /* PREFIX_VEX_0FED */
5373   {
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5377   },
5378
5379   /* PREFIX_VEX_0FEE */
5380   {
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5384   },
5385
5386   /* PREFIX_VEX_0FEF */
5387   {
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { "vpxor",          { XM, Vex, EXx }, 0 },
5391   },
5392
5393   /* PREFIX_VEX_0FF0 */
5394   {
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { Bad_Opcode },
5398     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5399   },
5400
5401   /* PREFIX_VEX_0FF1 */
5402   {
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5406   },
5407
5408   /* PREFIX_VEX_0FF2 */
5409   {
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5413   },
5414
5415   /* PREFIX_VEX_0FF3 */
5416   {
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5420   },
5421
5422   /* PREFIX_VEX_0FF4 */
5423   {
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5427   },
5428
5429   /* PREFIX_VEX_0FF5 */
5430   {
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5434   },
5435
5436   /* PREFIX_VEX_0FF6 */
5437   {
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5441   },
5442
5443   /* PREFIX_VEX_0FF7 */
5444   {
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5448   },
5449
5450   /* PREFIX_VEX_0FF8 */
5451   {
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { "vpsubb",         { XM, Vex, EXx }, 0 },
5455   },
5456
5457   /* PREFIX_VEX_0FF9 */
5458   {
5459     { Bad_Opcode },
5460     { Bad_Opcode },
5461     { "vpsubw",         { XM, Vex, EXx }, 0 },
5462   },
5463
5464   /* PREFIX_VEX_0FFA */
5465   {
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { "vpsubd",         { XM, Vex, EXx }, 0 },
5469   },
5470
5471   /* PREFIX_VEX_0FFB */
5472   {
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { "vpsubq",         { XM, Vex, EXx }, 0 },
5476   },
5477
5478   /* PREFIX_VEX_0FFC */
5479   {
5480     { Bad_Opcode },
5481     { Bad_Opcode },
5482     { "vpaddb",         { XM, Vex, EXx }, 0 },
5483   },
5484
5485   /* PREFIX_VEX_0FFD */
5486   {
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { "vpaddw",         { XM, Vex, EXx }, 0 },
5490   },
5491
5492   /* PREFIX_VEX_0FFE */
5493   {
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { "vpaddd",         { XM, Vex, EXx }, 0 },
5497   },
5498
5499   /* PREFIX_VEX_0F3800 */
5500   {
5501     { Bad_Opcode },
5502     { Bad_Opcode },
5503     { "vpshufb",        { XM, Vex, EXx }, 0 },
5504   },
5505
5506   /* PREFIX_VEX_0F3801 */
5507   {
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { "vphaddw",        { XM, Vex, EXx }, 0 },
5511   },
5512
5513   /* PREFIX_VEX_0F3802 */
5514   {
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { "vphaddd",        { XM, Vex, EXx }, 0 },
5518   },
5519
5520   /* PREFIX_VEX_0F3803 */
5521   {
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5525   },
5526
5527   /* PREFIX_VEX_0F3804 */
5528   {
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5532   },
5533
5534   /* PREFIX_VEX_0F3805 */
5535   {
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { "vphsubw",        { XM, Vex, EXx }, 0 },
5539   },
5540
5541   /* PREFIX_VEX_0F3806 */
5542   {
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { "vphsubd",        { XM, Vex, EXx }, 0 },
5546   },
5547
5548   /* PREFIX_VEX_0F3807 */
5549   {
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5553   },
5554
5555   /* PREFIX_VEX_0F3808 */
5556   {
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { "vpsignb",        { XM, Vex, EXx }, 0 },
5560   },
5561
5562   /* PREFIX_VEX_0F3809 */
5563   {
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { "vpsignw",        { XM, Vex, EXx }, 0 },
5567   },
5568
5569   /* PREFIX_VEX_0F380A */
5570   {
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { "vpsignd",        { XM, Vex, EXx }, 0 },
5574   },
5575
5576   /* PREFIX_VEX_0F380B */
5577   {
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5581   },
5582
5583   /* PREFIX_VEX_0F380C */
5584   {
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5588   },
5589
5590   /* PREFIX_VEX_0F380D */
5591   {
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5595   },
5596
5597   /* PREFIX_VEX_0F380E */
5598   {
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5602   },
5603
5604   /* PREFIX_VEX_0F380F */
5605   {
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5609   },
5610
5611   /* PREFIX_VEX_0F3813 */
5612   {
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { VEX_W_TABLE (VEX_W_0F3813_P_2) },
5616   },
5617
5618   /* PREFIX_VEX_0F3816 */
5619   {
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5623   },
5624
5625   /* PREFIX_VEX_0F3817 */
5626   {
5627     { Bad_Opcode },
5628     { Bad_Opcode },
5629     { "vptest",         { XM, EXx }, 0 },
5630   },
5631
5632   /* PREFIX_VEX_0F3818 */
5633   {
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5637   },
5638
5639   /* PREFIX_VEX_0F3819 */
5640   {
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5644   },
5645
5646   /* PREFIX_VEX_0F381A */
5647   {
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5651   },
5652
5653   /* PREFIX_VEX_0F381C */
5654   {
5655     { Bad_Opcode },
5656     { Bad_Opcode },
5657     { "vpabsb",         { XM, EXx }, 0 },
5658   },
5659
5660   /* PREFIX_VEX_0F381D */
5661   {
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { "vpabsw",         { XM, EXx }, 0 },
5665   },
5666
5667   /* PREFIX_VEX_0F381E */
5668   {
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { "vpabsd",         { XM, EXx }, 0 },
5672   },
5673
5674   /* PREFIX_VEX_0F3820 */
5675   {
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5679   },
5680
5681   /* PREFIX_VEX_0F3821 */
5682   {
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5686   },
5687
5688   /* PREFIX_VEX_0F3822 */
5689   {
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5693   },
5694
5695   /* PREFIX_VEX_0F3823 */
5696   {
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5700   },
5701
5702   /* PREFIX_VEX_0F3824 */
5703   {
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5707   },
5708
5709   /* PREFIX_VEX_0F3825 */
5710   {
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5714   },
5715
5716   /* PREFIX_VEX_0F3828 */
5717   {
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5721   },
5722
5723   /* PREFIX_VEX_0F3829 */
5724   {
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5728   },
5729
5730   /* PREFIX_VEX_0F382A */
5731   {
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5735   },
5736
5737   /* PREFIX_VEX_0F382B */
5738   {
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5742   },
5743
5744   /* PREFIX_VEX_0F382C */
5745   {
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5749   },
5750
5751   /* PREFIX_VEX_0F382D */
5752   {
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5756   },
5757
5758   /* PREFIX_VEX_0F382E */
5759   {
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5763   },
5764
5765   /* PREFIX_VEX_0F382F */
5766   {
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5770   },
5771
5772   /* PREFIX_VEX_0F3830 */
5773   {
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5777   },
5778
5779   /* PREFIX_VEX_0F3831 */
5780   {
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5784   },
5785
5786   /* PREFIX_VEX_0F3832 */
5787   {
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5791   },
5792
5793   /* PREFIX_VEX_0F3833 */
5794   {
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5798   },
5799
5800   /* PREFIX_VEX_0F3834 */
5801   {
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5805   },
5806
5807   /* PREFIX_VEX_0F3835 */
5808   {
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5812   },
5813
5814   /* PREFIX_VEX_0F3836 */
5815   {
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5819   },
5820
5821   /* PREFIX_VEX_0F3837 */
5822   {
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5826   },
5827
5828   /* PREFIX_VEX_0F3838 */
5829   {
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { "vpminsb",        { XM, Vex, EXx }, 0 },
5833   },
5834
5835   /* PREFIX_VEX_0F3839 */
5836   {
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { "vpminsd",        { XM, Vex, EXx }, 0 },
5840   },
5841
5842   /* PREFIX_VEX_0F383A */
5843   {
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { "vpminuw",        { XM, Vex, EXx }, 0 },
5847   },
5848
5849   /* PREFIX_VEX_0F383B */
5850   {
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { "vpminud",        { XM, Vex, EXx }, 0 },
5854   },
5855
5856   /* PREFIX_VEX_0F383C */
5857   {
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5861   },
5862
5863   /* PREFIX_VEX_0F383D */
5864   {
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5868   },
5869
5870   /* PREFIX_VEX_0F383E */
5871   {
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5875   },
5876
5877   /* PREFIX_VEX_0F383F */
5878   {
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5882   },
5883
5884   /* PREFIX_VEX_0F3840 */
5885   {
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { "vpmulld",        { XM, Vex, EXx }, 0 },
5889   },
5890
5891   /* PREFIX_VEX_0F3841 */
5892   {
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5896   },
5897
5898   /* PREFIX_VEX_0F3845 */
5899   {
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5903   },
5904
5905   /* PREFIX_VEX_0F3846 */
5906   {
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5910   },
5911
5912   /* PREFIX_VEX_0F3847 */
5913   {
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5917   },
5918
5919   /* PREFIX_VEX_0F3849_X86_64 */
5920   {
5921     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
5922     { Bad_Opcode },
5923     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
5924     { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
5925   },
5926
5927   /* PREFIX_VEX_0F384B_X86_64 */
5928   {
5929     { Bad_Opcode },
5930     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
5931     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
5932     { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
5933   },
5934
5935   /* PREFIX_VEX_0F3858 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F3859 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5947   },
5948
5949   /* PREFIX_VEX_0F385A */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F385C_X86_64 */
5957   {
5958     { Bad_Opcode },
5959     { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
5960     { Bad_Opcode },
5961   },
5962
5963   /* PREFIX_VEX_0F385E_X86_64 */
5964   {
5965     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
5966     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
5967     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
5968     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
5969   },
5970
5971   /* PREFIX_VEX_0F3878 */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F3879 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5983   },
5984
5985   /* PREFIX_VEX_0F388C */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5990   },
5991
5992   /* PREFIX_VEX_0F388E */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5997   },
5998
5999   /* PREFIX_VEX_0F3890 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3891 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3892 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3893 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3896 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F3897 */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F3898 */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F3899 */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389A */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389B */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389C */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F389D */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6081   },
6082
6083   /* PREFIX_VEX_0F389E */
6084   {
6085     { Bad_Opcode },
6086     { Bad_Opcode },
6087     { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6088   },
6089
6090   /* PREFIX_VEX_0F389F */
6091   {
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6095   },
6096
6097   /* PREFIX_VEX_0F38A6 */
6098   {
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6102     { Bad_Opcode },
6103   },
6104
6105   /* PREFIX_VEX_0F38A7 */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38A8 */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38A9 */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AA */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AB */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AC */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38AD */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38AE */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38AF */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B6 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38B7 */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38B8 */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38B9 */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BA */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BB */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BC */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38BD */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6222   },
6223
6224   /* PREFIX_VEX_0F38BE */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 },
6229   },
6230
6231   /* PREFIX_VEX_0F38BF */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38CF */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6243   },
6244
6245   /* PREFIX_VEX_0F38DB */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6250   },
6251
6252   /* PREFIX_VEX_0F38DC */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesenc",        { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38DD */
6260   {
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6264   },
6265
6266   /* PREFIX_VEX_0F38DE */
6267   {
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { "vaesdec",        { XM, Vex, EXx }, 0 },
6271   },
6272
6273   /* PREFIX_VEX_0F38DF */
6274   {
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6278   },
6279
6280   /* PREFIX_VEX_0F38F2 */
6281   {
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6283   },
6284
6285   /* PREFIX_VEX_0F38F3_REG_1 */
6286   {
6287     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6288   },
6289
6290   /* PREFIX_VEX_0F38F3_REG_2 */
6291   {
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6293   },
6294
6295   /* PREFIX_VEX_0F38F3_REG_3 */
6296   {
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6298   },
6299
6300   /* PREFIX_VEX_0F38F5 */
6301   {
6302     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6303     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6304     { Bad_Opcode },
6305     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6306   },
6307
6308   /* PREFIX_VEX_0F38F6 */
6309   {
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6314   },
6315
6316   /* PREFIX_VEX_0F38F7 */
6317   {
6318     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6319     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6320     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6321     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A00 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A01 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A02 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A04 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6350   },
6351
6352   /* PREFIX_VEX_0F3A05 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6357   },
6358
6359   /* PREFIX_VEX_0F3A06 */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6364   },
6365
6366   /* PREFIX_VEX_0F3A08 */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundps",       { XM, EXx, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A09 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vroundpd",       { XM, EXx, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0A */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vroundss",       { XMScalar, VexScalar, EXxmm_md, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0B */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vroundsd",       { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0C */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A0D */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F3A0E */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F3A0F */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6420   },
6421
6422   /* PREFIX_VEX_0F3A14 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A15 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A16 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A17 */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F3A18 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A19 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A1D */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_W_TABLE (VEX_W_0F3A1D_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A20 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A21 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A22 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A30 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A31 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A32 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A33 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6518   },
6519
6520   /* PREFIX_VEX_0F3A38 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A39 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6532   },
6533
6534   /* PREFIX_VEX_0F3A40 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6539   },
6540
6541   /* PREFIX_VEX_0F3A41 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A42 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6553   },
6554
6555   /* PREFIX_VEX_0F3A44 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6560   },
6561
6562   /* PREFIX_VEX_0F3A46 */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A48 */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6574   },
6575
6576   /* PREFIX_VEX_0F3A49 */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, 0 },
6581   },
6582
6583   /* PREFIX_VEX_0F3A4A */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6588   },
6589
6590   /* PREFIX_VEX_0F3A4B */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6595   },
6596
6597   /* PREFIX_VEX_0F3A4C */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5C */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A5D */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6616   },
6617
6618   /* PREFIX_VEX_0F3A5E */
6619   {
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6623   },
6624
6625   /* PREFIX_VEX_0F3A5F */
6626   {
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6630   },
6631
6632   /* PREFIX_VEX_0F3A60 */
6633   {
6634     { Bad_Opcode },
6635     { Bad_Opcode },
6636     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6637     { Bad_Opcode },
6638   },
6639
6640   /* PREFIX_VEX_0F3A61 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6645   },
6646
6647   /* PREFIX_VEX_0F3A62 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6652   },
6653
6654   /* PREFIX_VEX_0F3A63 */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A68 */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6666   },
6667
6668   /* PREFIX_VEX_0F3A69 */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6A */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfmaddss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6B */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { "vfmaddsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6C */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6694   },
6695
6696   /* PREFIX_VEX_0F3A6D */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6701   },
6702
6703   /* PREFIX_VEX_0F3A6E */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfmsubss",       { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A6F */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { "vfmsubsd",       { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6715   },
6716
6717   /* PREFIX_VEX_0F3A78 */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 },
6722   },
6723
6724   /* PREFIX_VEX_0F3A79 */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6729   },
6730
6731   /* PREFIX_VEX_0F3A7A */
6732   {
6733     { Bad_Opcode },
6734     { Bad_Opcode },
6735     { "vfnmaddss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6736   },
6737
6738   /* PREFIX_VEX_0F3A7B */
6739   {
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { "vfnmaddsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6743   },
6744
6745   /* PREFIX_VEX_0F3A7C */
6746   {
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 },
6750     { Bad_Opcode },
6751   },
6752
6753   /* PREFIX_VEX_0F3A7D */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 },
6758   },
6759
6760   /* PREFIX_VEX_0F3A7E */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { "vfnmsubss",      { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, 0 },
6765   },
6766
6767   /* PREFIX_VEX_0F3A7F */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { "vfnmsubsd",      { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, 0 },
6772   },
6773
6774   /* PREFIX_VEX_0F3ACE */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3ACF */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3ADF */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6793   },
6794
6795   /* PREFIX_VEX_0F3AF0 */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6801   },
6802
6803 #include "i386-dis-evex-prefix.h"
6804 };
6805
6806 static const struct dis386 x86_64_table[][2] = {
6807   /* X86_64_06 */
6808   {
6809     { "pushP", { es }, 0 },
6810   },
6811
6812   /* X86_64_07 */
6813   {
6814     { "popP", { es }, 0 },
6815   },
6816
6817   /* X86_64_0E */
6818   {
6819     { "pushP", { cs }, 0 },
6820   },
6821
6822   /* X86_64_16 */
6823   {
6824     { "pushP", { ss }, 0 },
6825   },
6826
6827   /* X86_64_17 */
6828   {
6829     { "popP", { ss }, 0 },
6830   },
6831
6832   /* X86_64_1E */
6833   {
6834     { "pushP", { ds }, 0 },
6835   },
6836
6837   /* X86_64_1F */
6838   {
6839     { "popP", { ds }, 0 },
6840   },
6841
6842   /* X86_64_27 */
6843   {
6844     { "daa", { XX }, 0 },
6845   },
6846
6847   /* X86_64_2F */
6848   {
6849     { "das", { XX }, 0 },
6850   },
6851
6852   /* X86_64_37 */
6853   {
6854     { "aaa", { XX }, 0 },
6855   },
6856
6857   /* X86_64_3F */
6858   {
6859     { "aas", { XX }, 0 },
6860   },
6861
6862   /* X86_64_60 */
6863   {
6864     { "pushaP", { XX }, 0 },
6865   },
6866
6867   /* X86_64_61 */
6868   {
6869     { "popaP", { XX }, 0 },
6870   },
6871
6872   /* X86_64_62 */
6873   {
6874     { MOD_TABLE (MOD_62_32BIT) },
6875     { EVEX_TABLE (EVEX_0F) },
6876   },
6877
6878   /* X86_64_63 */
6879   {
6880     { "arpl", { Ew, Gw }, 0 },
6881     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6882   },
6883
6884   /* X86_64_6D */
6885   {
6886     { "ins{R|}", { Yzr, indirDX }, 0 },
6887     { "ins{G|}", { Yzr, indirDX }, 0 },
6888   },
6889
6890   /* X86_64_6F */
6891   {
6892     { "outs{R|}", { indirDXr, Xz }, 0 },
6893     { "outs{G|}", { indirDXr, Xz }, 0 },
6894   },
6895
6896   /* X86_64_82 */
6897   {
6898     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6899     { REG_TABLE (REG_80) },
6900   },
6901
6902   /* X86_64_9A */
6903   {
6904     { "{l|}call{T|}", { Ap }, 0 },
6905   },
6906
6907   /* X86_64_C2 */
6908   {
6909     { "retP",           { Iw, BND }, 0 },
6910     { "ret@",           { Iw, BND }, 0 },
6911   },
6912
6913   /* X86_64_C3 */
6914   {
6915     { "retP",           { BND }, 0 },
6916     { "ret@",           { BND }, 0 },
6917   },
6918
6919   /* X86_64_C4 */
6920   {
6921     { MOD_TABLE (MOD_C4_32BIT) },
6922     { VEX_C4_TABLE (VEX_0F) },
6923   },
6924
6925   /* X86_64_C5 */
6926   {
6927     { MOD_TABLE (MOD_C5_32BIT) },
6928     { VEX_C5_TABLE (VEX_0F) },
6929   },
6930
6931   /* X86_64_CE */
6932   {
6933     { "into", { XX }, 0 },
6934   },
6935
6936   /* X86_64_D4 */
6937   {
6938     { "aam", { Ib }, 0 },
6939   },
6940
6941   /* X86_64_D5 */
6942   {
6943     { "aad", { Ib }, 0 },
6944   },
6945
6946   /* X86_64_E8 */
6947   {
6948     { "callP",          { Jv, BND }, 0 },
6949     { "call@",          { Jv, BND }, 0 }
6950   },
6951
6952   /* X86_64_E9 */
6953   {
6954     { "jmpP",           { Jv, BND }, 0 },
6955     { "jmp@",           { Jv, BND }, 0 }
6956   },
6957
6958   /* X86_64_EA */
6959   {
6960     { "{l|}jmp{T|}", { Ap }, 0 },
6961   },
6962
6963   /* X86_64_0F01_REG_0 */
6964   {
6965     { "sgdt{Q|Q}", { M }, 0 },
6966     { "sgdt", { M }, 0 },
6967   },
6968
6969   /* X86_64_0F01_REG_1 */
6970   {
6971     { "sidt{Q|Q}", { M }, 0 },
6972     { "sidt", { M }, 0 },
6973   },
6974
6975   /* X86_64_0F01_REG_2 */
6976   {
6977     { "lgdt{Q|Q}", { M }, 0 },
6978     { "lgdt", { M }, 0 },
6979   },
6980
6981   /* X86_64_0F01_REG_3 */
6982   {
6983     { "lidt{Q|Q}", { M }, 0 },
6984     { "lidt", { M }, 0 },
6985   },
6986
6987   /* X86_64_VEX_0F3849 */
6988   {
6989     { Bad_Opcode },
6990     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
6991   },
6992
6993   /* X86_64_VEX_0F384B */
6994   {
6995     { Bad_Opcode },
6996     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
6997   },
6998
6999   /* X86_64_VEX_0F385C */
7000   {
7001     { Bad_Opcode },
7002     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
7003   },
7004
7005   /* X86_64_VEX_0F385E */
7006   {
7007     { Bad_Opcode },
7008     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
7009   },
7010 };
7011
7012 static const struct dis386 three_byte_table[][256] = {
7013
7014   /* THREE_BYTE_0F38 */
7015   {
7016     /* 00 */
7017     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7018     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7019     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7020     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7021     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7022     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7023     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7024     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7025     /* 08 */
7026     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7027     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7028     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7029     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     { Bad_Opcode },
7034     /* 10 */
7035     { PREFIX_TABLE (PREFIX_0F3810) },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { PREFIX_TABLE (PREFIX_0F3814) },
7040     { PREFIX_TABLE (PREFIX_0F3815) },
7041     { Bad_Opcode },
7042     { PREFIX_TABLE (PREFIX_0F3817) },
7043     /* 18 */
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7049     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7050     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7051     { Bad_Opcode },
7052     /* 20 */
7053     { PREFIX_TABLE (PREFIX_0F3820) },
7054     { PREFIX_TABLE (PREFIX_0F3821) },
7055     { PREFIX_TABLE (PREFIX_0F3822) },
7056     { PREFIX_TABLE (PREFIX_0F3823) },
7057     { PREFIX_TABLE (PREFIX_0F3824) },
7058     { PREFIX_TABLE (PREFIX_0F3825) },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     /* 28 */
7062     { PREFIX_TABLE (PREFIX_0F3828) },
7063     { PREFIX_TABLE (PREFIX_0F3829) },
7064     { PREFIX_TABLE (PREFIX_0F382A) },
7065     { PREFIX_TABLE (PREFIX_0F382B) },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     /* 30 */
7071     { PREFIX_TABLE (PREFIX_0F3830) },
7072     { PREFIX_TABLE (PREFIX_0F3831) },
7073     { PREFIX_TABLE (PREFIX_0F3832) },
7074     { PREFIX_TABLE (PREFIX_0F3833) },
7075     { PREFIX_TABLE (PREFIX_0F3834) },
7076     { PREFIX_TABLE (PREFIX_0F3835) },
7077     { Bad_Opcode },
7078     { PREFIX_TABLE (PREFIX_0F3837) },
7079     /* 38 */
7080     { PREFIX_TABLE (PREFIX_0F3838) },
7081     { PREFIX_TABLE (PREFIX_0F3839) },
7082     { PREFIX_TABLE (PREFIX_0F383A) },
7083     { PREFIX_TABLE (PREFIX_0F383B) },
7084     { PREFIX_TABLE (PREFIX_0F383C) },
7085     { PREFIX_TABLE (PREFIX_0F383D) },
7086     { PREFIX_TABLE (PREFIX_0F383E) },
7087     { PREFIX_TABLE (PREFIX_0F383F) },
7088     /* 40 */
7089     { PREFIX_TABLE (PREFIX_0F3840) },
7090     { PREFIX_TABLE (PREFIX_0F3841) },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     /* 48 */
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     /* 50 */
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     /* 58 */
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     /* 60 */
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     /* 68 */
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     /* 70 */
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     /* 78 */
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     /* 80 */
7161     { PREFIX_TABLE (PREFIX_0F3880) },
7162     { PREFIX_TABLE (PREFIX_0F3881) },
7163     { PREFIX_TABLE (PREFIX_0F3882) },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     /* 88 */
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     /* 90 */
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     /* 98 */
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     /* a0 */
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     /* a8 */
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     /* b0 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     /* b8 */
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* c0 */
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* c8 */
7242     { PREFIX_TABLE (PREFIX_0F38C8) },
7243     { PREFIX_TABLE (PREFIX_0F38C9) },
7244     { PREFIX_TABLE (PREFIX_0F38CA) },
7245     { PREFIX_TABLE (PREFIX_0F38CB) },
7246     { PREFIX_TABLE (PREFIX_0F38CC) },
7247     { PREFIX_TABLE (PREFIX_0F38CD) },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F38CF) },
7250     /* d0 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* d8 */
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { PREFIX_TABLE (PREFIX_0F38DB) },
7264     { PREFIX_TABLE (PREFIX_0F38DC) },
7265     { PREFIX_TABLE (PREFIX_0F38DD) },
7266     { PREFIX_TABLE (PREFIX_0F38DE) },
7267     { PREFIX_TABLE (PREFIX_0F38DF) },
7268     /* e0 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* e8 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* f0 */
7287     { PREFIX_TABLE (PREFIX_0F38F0) },
7288     { PREFIX_TABLE (PREFIX_0F38F1) },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { PREFIX_TABLE (PREFIX_0F38F5) },
7293     { PREFIX_TABLE (PREFIX_0F38F6) },
7294     { Bad_Opcode },
7295     /* f8 */
7296     { PREFIX_TABLE (PREFIX_0F38F8) },
7297     { PREFIX_TABLE (PREFIX_0F38F9) },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304   },
7305   /* THREE_BYTE_0F3A */
7306   {
7307     /* 00 */
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     /* 08 */
7317     { PREFIX_TABLE (PREFIX_0F3A08) },
7318     { PREFIX_TABLE (PREFIX_0F3A09) },
7319     { PREFIX_TABLE (PREFIX_0F3A0A) },
7320     { PREFIX_TABLE (PREFIX_0F3A0B) },
7321     { PREFIX_TABLE (PREFIX_0F3A0C) },
7322     { PREFIX_TABLE (PREFIX_0F3A0D) },
7323     { PREFIX_TABLE (PREFIX_0F3A0E) },
7324     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7325     /* 10 */
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { PREFIX_TABLE (PREFIX_0F3A14) },
7331     { PREFIX_TABLE (PREFIX_0F3A15) },
7332     { PREFIX_TABLE (PREFIX_0F3A16) },
7333     { PREFIX_TABLE (PREFIX_0F3A17) },
7334     /* 18 */
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     /* 20 */
7344     { PREFIX_TABLE (PREFIX_0F3A20) },
7345     { PREFIX_TABLE (PREFIX_0F3A21) },
7346     { PREFIX_TABLE (PREFIX_0F3A22) },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     /* 28 */
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     /* 30 */
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     /* 38 */
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     /* 40 */
7380     { PREFIX_TABLE (PREFIX_0F3A40) },
7381     { PREFIX_TABLE (PREFIX_0F3A41) },
7382     { PREFIX_TABLE (PREFIX_0F3A42) },
7383     { Bad_Opcode },
7384     { PREFIX_TABLE (PREFIX_0F3A44) },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     /* 48 */
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     /* 50 */
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     /* 58 */
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     /* 60 */
7416     { PREFIX_TABLE (PREFIX_0F3A60) },
7417     { PREFIX_TABLE (PREFIX_0F3A61) },
7418     { PREFIX_TABLE (PREFIX_0F3A62) },
7419     { PREFIX_TABLE (PREFIX_0F3A63) },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     /* 68 */
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     /* 70 */
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     /* 78 */
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     /* 80 */
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     /* 88 */
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     /* 90 */
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     /* 98 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* a0 */
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     /* a8 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     /* b0 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* b8 */
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* c0 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* c8 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { PREFIX_TABLE (PREFIX_0F3ACC) },
7538     { Bad_Opcode },
7539     { PREFIX_TABLE (PREFIX_0F3ACE) },
7540     { PREFIX_TABLE (PREFIX_0F3ACF) },
7541     /* d0 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* d8 */
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { PREFIX_TABLE (PREFIX_0F3ADF) },
7559     /* e0 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* e8 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* f0 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* f8 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595   },
7596 };
7597
7598 static const struct dis386 xop_table[][256] = {
7599   /* XOP_08 */
7600   {
7601     /* 00 */
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     /* 08 */
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     /* 10 */
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     /* 18 */
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     /* 20 */
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     /* 28 */
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     /* 30 */
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     /* 38 */
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     /* 40 */
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     /* 48 */
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     /* 50 */
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     /* 58 */
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     /* 60 */
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     /* 68 */
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     /* 70 */
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     /* 78 */
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     /* 80 */
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
7752     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
7753     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
7754     /* 88 */
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
7762     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
7763     /* 90 */
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
7770     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
7771     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
7772     /* 98 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
7780     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
7781     /* a0 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
7785     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
7789     { Bad_Opcode },
7790     /* a8 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* b0 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
7807     { Bad_Opcode },
7808     /* b8 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* c0 */
7818     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
7819     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
7820     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
7821     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     /* c8 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7832     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7833     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7834     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7835     /* d0 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* d8 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* e0 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* e8 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7868     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7869     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7870     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7871     /* f0 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* f8 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889   },
7890   /* XOP_09 */
7891   {
7892     /* 00 */
7893     { Bad_Opcode },
7894     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
7895     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     /* 08 */
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     /* 10 */
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     /* 18 */
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     /* 20 */
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     /* 28 */
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     /* 30 */
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     /* 38 */
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     /* 40 */
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     /* 48 */
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     /* 50 */
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     /* 58 */
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     /* 60 */
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     /* 68 */
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     /* 70 */
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     /* 78 */
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     /* 80 */
8037     { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
8038     { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
8039     { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
8040     { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     /* 88 */
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     /* 90 */
8055     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
8056     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
8057     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
8058     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
8059     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
8060     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
8061     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
8062     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
8063     /* 98 */
8064     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
8065     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
8066     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
8067     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* a0 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* a8 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* b0 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* b8 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* c0 */
8109     { Bad_Opcode },
8110     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
8111     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
8112     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
8116     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
8117     /* c8 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* d0 */
8127     { Bad_Opcode },
8128     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
8129     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
8130     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
8134     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
8135     /* d8 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* e0 */
8145     { Bad_Opcode },
8146     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
8147     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
8148     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* e8 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* f0 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* f8 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180   },
8181   /* XOP_0A */
8182   {
8183     /* 00 */
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     /* 08 */
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     /* 10 */
8202     { "bextrS", { Gdq, Edq, Id }, 0 },
8203     { Bad_Opcode },
8204     { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     /* 18 */
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     /* 20 */
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     /* 28 */
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     /* 30 */
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     /* 38 */
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     /* 40 */
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     /* 48 */
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     /* 50 */
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     /* 58 */
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     /* 60 */
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     /* 68 */
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     /* 70 */
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     /* 78 */
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     /* 80 */
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     /* 88 */
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     /* 90 */
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     /* 98 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* a0 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* a8 */
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* b0 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* b8 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* c0 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* c8 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* d0 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* d8 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* e0 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* e8 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* f0 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* f8 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471   },
8472 };
8473
8474 static const struct dis386 vex_table[][256] = {
8475   /* VEX_0F */
8476   {
8477     /* 00 */
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     /* 08 */
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     /* 10 */
8496     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8497     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8499     { MOD_TABLE (MOD_VEX_0F13) },
8500     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8501     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
8502     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8503     { MOD_TABLE (MOD_VEX_0F17) },
8504     /* 18 */
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     /* 20 */
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     /* 28 */
8523     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
8524     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
8525     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8526     { MOD_TABLE (MOD_VEX_0F2B) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8531     /* 30 */
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     { Bad_Opcode },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     /* 38 */
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     { Bad_Opcode },
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     /* 40 */
8550     { Bad_Opcode },
8551     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8553     { Bad_Opcode },
8554     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8558     /* 48 */
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     /* 50 */
8568     { MOD_TABLE (MOD_VEX_0F50) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8572     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8573     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
8574     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
8575     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
8576     /* 58 */
8577     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8579     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8585     /* 60 */
8586     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8587     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8588     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8589     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8594     /* 68 */
8595     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8596     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8597     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8598     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8602     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8603     /* 70 */
8604     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8605     { REG_TABLE (REG_VEX_0F71) },
8606     { REG_TABLE (REG_VEX_0F72) },
8607     { REG_TABLE (REG_VEX_0F73) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8609     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8610     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8611     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8612     /* 78 */
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { Bad_Opcode },
8617     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8618     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8619     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8620     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8621     /* 80 */
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     /* 88 */
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     /* 90 */
8640     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8641     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8642     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8643     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     /* 98 */
8649     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8650     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     /* a0 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* a8 */
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     { Bad_Opcode },
8670     { Bad_Opcode },
8671     { Bad_Opcode },
8672     { Bad_Opcode },
8673     { REG_TABLE (REG_VEX_0FAE) },
8674     { Bad_Opcode },
8675     /* b0 */
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     /* b8 */
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     /* c0 */
8694     { Bad_Opcode },
8695     { Bad_Opcode },
8696     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8697     { Bad_Opcode },
8698     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8700     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
8701     { Bad_Opcode },
8702     /* c8 */
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     /* d0 */
8712     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8720     /* d8 */
8721     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8728     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8729     /* e0 */
8730     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8736     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8737     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8738     /* e8 */
8739     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8740     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8741     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8742     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8743     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8744     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8745     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8746     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8747     /* f0 */
8748     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8749     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8750     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8751     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8752     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8753     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8754     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8755     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8756     /* f8 */
8757     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8758     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8759     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8760     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8761     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8762     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8763     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8764     { Bad_Opcode },
8765   },
8766   /* VEX_0F38 */
8767   {
8768     /* 00 */
8769     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8777     /* 08 */
8778     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8786     /* 10 */
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { Bad_Opcode },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8791     { Bad_Opcode },
8792     { Bad_Opcode },
8793     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8795     /* 18 */
8796     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8799     { Bad_Opcode },
8800     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8803     { Bad_Opcode },
8804     /* 20 */
8805     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     /* 28 */
8814     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8815     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8816     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8817     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8818     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8822     /* 30 */
8823     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8824     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8825     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8826     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8829     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8830     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8831     /* 38 */
8832     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8833     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8834     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8835     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8836     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8837     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8838     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8839     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8840     /* 40 */
8841     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8847     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8849     /* 48 */
8850     { Bad_Opcode },
8851     { X86_64_TABLE (X86_64_VEX_0F3849) },
8852     { Bad_Opcode },
8853     { X86_64_TABLE (X86_64_VEX_0F384B) },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     /* 50 */
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     /* 58 */
8868     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8869     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8870     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8871     { Bad_Opcode },
8872     { X86_64_TABLE (X86_64_VEX_0F385C) },
8873     { Bad_Opcode },
8874     { X86_64_TABLE (X86_64_VEX_0F385E) },
8875     { Bad_Opcode },
8876     /* 60 */
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { Bad_Opcode },
8885     /* 68 */
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     /* 70 */
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { Bad_Opcode },
8899     { Bad_Opcode },
8900     { Bad_Opcode },
8901     { Bad_Opcode },
8902     { Bad_Opcode },
8903     /* 78 */
8904     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8906     { Bad_Opcode },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     /* 80 */
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { Bad_Opcode },
8917     { Bad_Opcode },
8918     { Bad_Opcode },
8919     { Bad_Opcode },
8920     { Bad_Opcode },
8921     /* 88 */
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8927     { Bad_Opcode },
8928     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8929     { Bad_Opcode },
8930     /* 90 */
8931     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8935     { Bad_Opcode },
8936     { Bad_Opcode },
8937     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8939     /* 98 */
8940     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8948     /* a0 */
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8957     /* a8 */
8958     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8963     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8964     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8966     /* b0 */
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8975     /* b8 */
8976     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8982     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8983     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8984     /* c0 */
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { Bad_Opcode },
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     /* c8 */
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9002     /* d0 */
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     /* d8 */
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014     { Bad_Opcode },
9015     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9020     /* e0 */
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* e8 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* f0 */
9039     { Bad_Opcode },
9040     { Bad_Opcode },
9041     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9042     { REG_TABLE (REG_VEX_0F38F3) },
9043     { Bad_Opcode },
9044     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9047     /* f8 */
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056   },
9057   /* VEX_0F3A */
9058   {
9059     /* 00 */
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9061     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9062     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9063     { Bad_Opcode },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9065     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9067     { Bad_Opcode },
9068     /* 08 */
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9071     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9077     /* 10 */
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9083     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9086     /* 18 */
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     /* 20 */
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9097     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9098     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     /* 28 */
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     /* 30 */
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     /* 38 */
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     /* 40 */
9132     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9135     { Bad_Opcode },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9137     { Bad_Opcode },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9139     { Bad_Opcode },
9140     /* 48 */
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     /* 50 */
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     { Bad_Opcode },
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     /* 58 */
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9164     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9165     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9166     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9167     /* 60 */
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     /* 68 */
9177     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9178     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9179     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9180     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9181     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9182     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9183     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9184     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9185     /* 70 */
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     /* 78 */
9195     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9196     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9197     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9198     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9199     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9200     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9201     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9202     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9203     /* 80 */
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     /* 88 */
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     /* 90 */
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     /* 98 */
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     /* a0 */
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     /* a8 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     /* b0 */
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* b8 */
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* c0 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* c8 */
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9292     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9293     /* d0 */
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     /* d8 */
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9311     /* e0 */
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     /* e8 */
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     /* f0 */
9330     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { Bad_Opcode },
9335     { Bad_Opcode },
9336     { Bad_Opcode },
9337     { Bad_Opcode },
9338     /* f8 */
9339     { Bad_Opcode },
9340     { Bad_Opcode },
9341     { Bad_Opcode },
9342     { Bad_Opcode },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347   },
9348 };
9349
9350 #include "i386-dis-evex.h"
9351
9352 static const struct dis386 vex_len_table[][2] = {
9353   /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
9354   {
9355     { "vmovlpX",        { XM, Vex128, EXq }, 0 },
9356   },
9357
9358   /* VEX_LEN_0F12_P_0_M_1 */
9359   {
9360     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9361   },
9362
9363   /* VEX_LEN_0F13_M_0 */
9364   {
9365     { "vmovlpX",        { EXq, XM }, PREFIX_OPCODE },
9366   },
9367
9368   /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
9369   {
9370     { "vmovhpX",        { XM, Vex128, EXq }, 0 },
9371   },
9372
9373   /* VEX_LEN_0F16_P_0_M_1 */
9374   {
9375     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9376   },
9377
9378   /* VEX_LEN_0F17_M_0 */
9379   {
9380     { "vmovhpX",        { EXq, XM }, PREFIX_OPCODE },
9381   },
9382
9383   /* VEX_LEN_0F41_P_0 */
9384   {
9385     { Bad_Opcode },
9386     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9387   },
9388   /* VEX_LEN_0F41_P_2 */
9389   {
9390     { Bad_Opcode },
9391     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9392   },
9393   /* VEX_LEN_0F42_P_0 */
9394   {
9395     { Bad_Opcode },
9396     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9397   },
9398   /* VEX_LEN_0F42_P_2 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9402   },
9403   /* VEX_LEN_0F44_P_0 */
9404   {
9405     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9406   },
9407   /* VEX_LEN_0F44_P_2 */
9408   {
9409     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9410   },
9411   /* VEX_LEN_0F45_P_0 */
9412   {
9413     { Bad_Opcode },
9414     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9415   },
9416   /* VEX_LEN_0F45_P_2 */
9417   {
9418     { Bad_Opcode },
9419     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9420   },
9421   /* VEX_LEN_0F46_P_0 */
9422   {
9423     { Bad_Opcode },
9424     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9425   },
9426   /* VEX_LEN_0F46_P_2 */
9427   {
9428     { Bad_Opcode },
9429     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9430   },
9431   /* VEX_LEN_0F47_P_0 */
9432   {
9433     { Bad_Opcode },
9434     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9435   },
9436   /* VEX_LEN_0F47_P_2 */
9437   {
9438     { Bad_Opcode },
9439     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9440   },
9441   /* VEX_LEN_0F4A_P_0 */
9442   {
9443     { Bad_Opcode },
9444     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9445   },
9446   /* VEX_LEN_0F4A_P_2 */
9447   {
9448     { Bad_Opcode },
9449     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9450   },
9451   /* VEX_LEN_0F4B_P_0 */
9452   {
9453     { Bad_Opcode },
9454     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9455   },
9456   /* VEX_LEN_0F4B_P_2 */
9457   {
9458     { Bad_Opcode },
9459     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9460   },
9461
9462   /* VEX_LEN_0F6E_P_2 */
9463   {
9464     { "vmovK",          { XMScalar, Edq }, 0 },
9465   },
9466
9467   /* VEX_LEN_0F77_P_1 */
9468   {
9469     { "vzeroupper",     { XX }, 0 },
9470     { "vzeroall",       { XX }, 0 },
9471   },
9472
9473   /* VEX_LEN_0F7E_P_1 */
9474   {
9475     { "vmovq",          { XMScalar, EXxmm_mq }, 0 },
9476   },
9477
9478   /* VEX_LEN_0F7E_P_2 */
9479   {
9480     { "vmovK",          { Edq, XMScalar }, 0 },
9481   },
9482
9483   /* VEX_LEN_0F90_P_0 */
9484   {
9485     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9486   },
9487
9488   /* VEX_LEN_0F90_P_2 */
9489   {
9490     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9491   },
9492
9493   /* VEX_LEN_0F91_P_0 */
9494   {
9495     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9496   },
9497
9498   /* VEX_LEN_0F91_P_2 */
9499   {
9500     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9501   },
9502
9503   /* VEX_LEN_0F92_P_0 */
9504   {
9505     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9506   },
9507
9508   /* VEX_LEN_0F92_P_2 */
9509   {
9510     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9511   },
9512
9513   /* VEX_LEN_0F92_P_3 */
9514   {
9515     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9516   },
9517
9518   /* VEX_LEN_0F93_P_0 */
9519   {
9520     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9521   },
9522
9523   /* VEX_LEN_0F93_P_2 */
9524   {
9525     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9526   },
9527
9528   /* VEX_LEN_0F93_P_3 */
9529   {
9530     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9531   },
9532
9533   /* VEX_LEN_0F98_P_0 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9536   },
9537
9538   /* VEX_LEN_0F98_P_2 */
9539   {
9540     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9541   },
9542
9543   /* VEX_LEN_0F99_P_0 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9546   },
9547
9548   /* VEX_LEN_0F99_P_2 */
9549   {
9550     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9551   },
9552
9553   /* VEX_LEN_0FAE_R_2_M_0 */
9554   {
9555     { "vldmxcsr",       { Md }, 0 },
9556   },
9557
9558   /* VEX_LEN_0FAE_R_3_M_0 */
9559   {
9560     { "vstmxcsr",       { Md }, 0 },
9561   },
9562
9563   /* VEX_LEN_0FC4_P_2 */
9564   {
9565     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9566   },
9567
9568   /* VEX_LEN_0FC5_P_2 */
9569   {
9570     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9571   },
9572
9573   /* VEX_LEN_0FD6_P_2 */
9574   {
9575     { "vmovq",          { EXqVexScalarS, XMScalar }, 0 },
9576   },
9577
9578   /* VEX_LEN_0FF7_P_2 */
9579   {
9580     { "vmaskmovdqu",    { XM, XS }, 0 },
9581   },
9582
9583   /* VEX_LEN_0F3816_P_2 */
9584   {
9585     { Bad_Opcode },
9586     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9587   },
9588
9589   /* VEX_LEN_0F3819_P_2 */
9590   {
9591     { Bad_Opcode },
9592     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9593   },
9594
9595   /* VEX_LEN_0F381A_P_2_M_0 */
9596   {
9597     { Bad_Opcode },
9598     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9599   },
9600
9601   /* VEX_LEN_0F3836_P_2 */
9602   {
9603     { Bad_Opcode },
9604     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9605   },
9606
9607   /* VEX_LEN_0F3841_P_2 */
9608   {
9609     { "vphminposuw",    { XM, EXx }, 0 },
9610   },
9611
9612    /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
9613   {
9614     { "ldtilecfg", { M }, 0 },
9615   },
9616
9617   /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
9618   {
9619     { "tilerelease", { Skip_MODRM }, 0 },
9620   },
9621
9622   /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
9623   {
9624     { "sttilecfg", { M }, 0 },
9625   },
9626
9627   /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
9628   {
9629     { "tilezero", { TMM, Skip_MODRM }, 0 },
9630   },
9631
9632   /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
9633   {
9634     { "tilestored", { MVexSIBMEM, TMM }, 0 },
9635   },
9636   /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
9637   {
9638     { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
9642   {
9643     { "tileloadd", { TMM, MVexSIBMEM }, 0 },
9644   },
9645
9646   /* VEX_LEN_0F385A_P_2_M_0 */
9647   {
9648     { Bad_Opcode },
9649     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9650   },
9651
9652   /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
9653   {
9654     { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
9655   },
9656
9657   /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
9658   {
9659     { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
9660   },
9661
9662   /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
9663   {
9664     { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
9665   },
9666
9667   /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
9668   {
9669     { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
9670   },
9671
9672   /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
9673   {
9674     { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
9675   },
9676
9677   /* VEX_LEN_0F38DB_P_2 */
9678   {
9679     { "vaesimc",        { XM, EXx }, 0 },
9680   },
9681
9682   /* VEX_LEN_0F38F2_P_0 */
9683   {
9684     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9685   },
9686
9687   /* VEX_LEN_0F38F3_R_1_P_0 */
9688   {
9689     { "blsrS",          { VexGdq, Edq }, 0 },
9690   },
9691
9692   /* VEX_LEN_0F38F3_R_2_P_0 */
9693   {
9694     { "blsmskS",        { VexGdq, Edq }, 0 },
9695   },
9696
9697   /* VEX_LEN_0F38F3_R_3_P_0 */
9698   {
9699     { "blsiS",          { VexGdq, Edq }, 0 },
9700   },
9701
9702   /* VEX_LEN_0F38F5_P_0 */
9703   {
9704     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9705   },
9706
9707   /* VEX_LEN_0F38F5_P_1 */
9708   {
9709     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9710   },
9711
9712   /* VEX_LEN_0F38F5_P_3 */
9713   {
9714     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9715   },
9716
9717   /* VEX_LEN_0F38F6_P_3 */
9718   {
9719     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9720   },
9721
9722   /* VEX_LEN_0F38F7_P_0 */
9723   {
9724     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9725   },
9726
9727   /* VEX_LEN_0F38F7_P_1 */
9728   {
9729     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9730   },
9731
9732   /* VEX_LEN_0F38F7_P_2 */
9733   {
9734     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9735   },
9736
9737   /* VEX_LEN_0F38F7_P_3 */
9738   {
9739     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9740   },
9741
9742   /* VEX_LEN_0F3A00_P_2 */
9743   {
9744     { Bad_Opcode },
9745     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9746   },
9747
9748   /* VEX_LEN_0F3A01_P_2 */
9749   {
9750     { Bad_Opcode },
9751     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9752   },
9753
9754   /* VEX_LEN_0F3A06_P_2 */
9755   {
9756     { Bad_Opcode },
9757     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9758   },
9759
9760   /* VEX_LEN_0F3A14_P_2 */
9761   {
9762     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9763   },
9764
9765   /* VEX_LEN_0F3A15_P_2 */
9766   {
9767     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9768   },
9769
9770   /* VEX_LEN_0F3A16_P_2  */
9771   {
9772     { "vpextrK",        { Edq, XM, Ib }, 0 },
9773   },
9774
9775   /* VEX_LEN_0F3A17_P_2 */
9776   {
9777     { "vextractps",     { Edqd, XM, Ib }, 0 },
9778   },
9779
9780   /* VEX_LEN_0F3A18_P_2 */
9781   {
9782     { Bad_Opcode },
9783     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9784   },
9785
9786   /* VEX_LEN_0F3A19_P_2 */
9787   {
9788     { Bad_Opcode },
9789     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9790   },
9791
9792   /* VEX_LEN_0F3A20_P_2 */
9793   {
9794     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9795   },
9796
9797   /* VEX_LEN_0F3A21_P_2 */
9798   {
9799     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9800   },
9801
9802   /* VEX_LEN_0F3A22_P_2 */
9803   {
9804     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9805   },
9806
9807   /* VEX_LEN_0F3A30_P_2 */
9808   {
9809     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9810   },
9811
9812   /* VEX_LEN_0F3A31_P_2 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9815   },
9816
9817   /* VEX_LEN_0F3A32_P_2 */
9818   {
9819     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9820   },
9821
9822   /* VEX_LEN_0F3A33_P_2 */
9823   {
9824     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9825   },
9826
9827   /* VEX_LEN_0F3A38_P_2 */
9828   {
9829     { Bad_Opcode },
9830     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9831   },
9832
9833   /* VEX_LEN_0F3A39_P_2 */
9834   {
9835     { Bad_Opcode },
9836     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9837   },
9838
9839   /* VEX_LEN_0F3A41_P_2 */
9840   {
9841     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9842   },
9843
9844   /* VEX_LEN_0F3A46_P_2 */
9845   {
9846     { Bad_Opcode },
9847     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9848   },
9849
9850   /* VEX_LEN_0F3A60_P_2 */
9851   {
9852     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9853   },
9854
9855   /* VEX_LEN_0F3A61_P_2 */
9856   {
9857     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9858   },
9859
9860   /* VEX_LEN_0F3A62_P_2 */
9861   {
9862     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9863   },
9864
9865   /* VEX_LEN_0F3A63_P_2 */
9866   {
9867     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9868   },
9869
9870   /* VEX_LEN_0F3ADF_P_2 */
9871   {
9872     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9873   },
9874
9875   /* VEX_LEN_0F3AF0_P_3 */
9876   {
9877     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9878   },
9879
9880   /* VEX_LEN_0FXOP_08_85 */
9881   {
9882     { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
9883   },
9884
9885   /* VEX_LEN_0FXOP_08_86 */
9886   {
9887     { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
9888   },
9889
9890   /* VEX_LEN_0FXOP_08_87 */
9891   {
9892     { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
9893   },
9894
9895   /* VEX_LEN_0FXOP_08_8E */
9896   {
9897     { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
9898   },
9899
9900   /* VEX_LEN_0FXOP_08_8F */
9901   {
9902     { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
9903   },
9904
9905   /* VEX_LEN_0FXOP_08_95 */
9906   {
9907     { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
9908   },
9909
9910   /* VEX_LEN_0FXOP_08_96 */
9911   {
9912     { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
9913   },
9914
9915   /* VEX_LEN_0FXOP_08_97 */
9916   {
9917     { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
9918   },
9919
9920   /* VEX_LEN_0FXOP_08_9E */
9921   {
9922     { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
9923   },
9924
9925   /* VEX_LEN_0FXOP_08_9F */
9926   {
9927     { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
9928   },
9929
9930   /* VEX_LEN_0FXOP_08_A3 */
9931   {
9932     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
9933   },
9934
9935   /* VEX_LEN_0FXOP_08_A6 */
9936   {
9937     { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
9938   },
9939
9940   /* VEX_LEN_0FXOP_08_B6 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
9943   },
9944
9945   /* VEX_LEN_0FXOP_08_C0 */
9946   {
9947     { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
9948   },
9949
9950   /* VEX_LEN_0FXOP_08_C1 */
9951   {
9952     { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
9953   },
9954
9955   /* VEX_LEN_0FXOP_08_C2 */
9956   {
9957     { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
9958   },
9959
9960   /* VEX_LEN_0FXOP_08_C3 */
9961   {
9962     { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
9963   },
9964
9965   /* VEX_LEN_0FXOP_08_CC */
9966   {
9967     { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
9968   },
9969
9970   /* VEX_LEN_0FXOP_08_CD */
9971   {
9972     { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
9973   },
9974
9975   /* VEX_LEN_0FXOP_08_CE */
9976   {
9977     { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
9978   },
9979
9980   /* VEX_LEN_0FXOP_08_CF */
9981   {
9982     { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
9983   },
9984
9985   /* VEX_LEN_0FXOP_08_EC */
9986   {
9987     { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
9988   },
9989
9990   /* VEX_LEN_0FXOP_08_ED */
9991   {
9992     { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
9993   },
9994
9995   /* VEX_LEN_0FXOP_08_EE */
9996   {
9997     { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
9998   },
9999
10000   /* VEX_LEN_0FXOP_08_EF */
10001   {
10002     { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
10003   },
10004
10005   /* VEX_LEN_0FXOP_09_01 */
10006   {
10007     { REG_TABLE (REG_0FXOP_09_01_L_0) },
10008   },
10009
10010   /* VEX_LEN_0FXOP_09_02 */
10011   {
10012     { REG_TABLE (REG_0FXOP_09_02_L_0) },
10013   },
10014
10015   /* VEX_LEN_0FXOP_09_12_M_1 */
10016   {
10017     { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
10018   },
10019
10020   /* VEX_LEN_0FXOP_09_82_W_0 */
10021   {
10022     { "vfrczss",        { XM, EXd }, 0 },
10023   },
10024
10025   /* VEX_LEN_0FXOP_09_83_W_0 */
10026   {
10027     { "vfrczsd",        { XM, EXq }, 0 },
10028   },
10029
10030   /* VEX_LEN_0FXOP_09_90 */
10031   {
10032     { "vprotb",         { XM, EXx, VexW }, 0 },
10033   },
10034
10035   /* VEX_LEN_0FXOP_09_91 */
10036   {
10037     { "vprotw",         { XM, EXx, VexW }, 0 },
10038   },
10039
10040   /* VEX_LEN_0FXOP_09_92 */
10041   {
10042     { "vprotd",         { XM, EXx, VexW }, 0 },
10043   },
10044
10045   /* VEX_LEN_0FXOP_09_93 */
10046   {
10047     { "vprotq",         { XM, EXx, VexW }, 0 },
10048   },
10049
10050   /* VEX_LEN_0FXOP_09_94 */
10051   {
10052     { "vpshlb",         { XM, EXx, VexW }, 0 },
10053   },
10054
10055   /* VEX_LEN_0FXOP_09_95 */
10056   {
10057     { "vpshlw",         { XM, EXx, VexW }, 0 },
10058   },
10059
10060   /* VEX_LEN_0FXOP_09_96 */
10061   {
10062     { "vpshld",         { XM, EXx, VexW }, 0 },
10063   },
10064
10065   /* VEX_LEN_0FXOP_09_97 */
10066   {
10067     { "vpshlq",         { XM, EXx, VexW }, 0 },
10068   },
10069
10070   /* VEX_LEN_0FXOP_09_98 */
10071   {
10072     { "vpshab",         { XM, EXx, VexW }, 0 },
10073   },
10074
10075   /* VEX_LEN_0FXOP_09_99 */
10076   {
10077     { "vpshaw",         { XM, EXx, VexW }, 0 },
10078   },
10079
10080   /* VEX_LEN_0FXOP_09_9A */
10081   {
10082     { "vpshad",         { XM, EXx, VexW }, 0 },
10083   },
10084
10085   /* VEX_LEN_0FXOP_09_9B */
10086   {
10087     { "vpshaq",         { XM, EXx, VexW }, 0 },
10088   },
10089
10090   /* VEX_LEN_0FXOP_09_C1 */
10091   {
10092     { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
10093   },
10094
10095   /* VEX_LEN_0FXOP_09_C2 */
10096   {
10097     { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
10098   },
10099
10100   /* VEX_LEN_0FXOP_09_C3 */
10101   {
10102     { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
10103   },
10104
10105   /* VEX_LEN_0FXOP_09_C6 */
10106   {
10107     { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
10108   },
10109
10110   /* VEX_LEN_0FXOP_09_C7 */
10111   {
10112     { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
10113   },
10114
10115   /* VEX_LEN_0FXOP_09_CB */
10116   {
10117     { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
10118   },
10119
10120   /* VEX_LEN_0FXOP_09_D1 */
10121   {
10122     { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
10123   },
10124
10125   /* VEX_LEN_0FXOP_09_D2 */
10126   {
10127     { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
10128   },
10129
10130   /* VEX_LEN_0FXOP_09_D3 */
10131   {
10132     { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
10133   },
10134
10135   /* VEX_LEN_0FXOP_09_D6 */
10136   {
10137     { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
10138   },
10139
10140   /* VEX_LEN_0FXOP_09_D7 */
10141   {
10142     { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
10143   },
10144
10145   /* VEX_LEN_0FXOP_09_DB */
10146   {
10147     { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
10148   },
10149
10150   /* VEX_LEN_0FXOP_09_E1 */
10151   {
10152     { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
10153   },
10154
10155   /* VEX_LEN_0FXOP_09_E2 */
10156   {
10157     { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
10158   },
10159
10160   /* VEX_LEN_0FXOP_09_E3 */
10161   {
10162     { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
10163   },
10164
10165   /* VEX_LEN_0FXOP_0A_12 */
10166   {
10167     { REG_TABLE (REG_0FXOP_0A_12_L_0) },
10168   },
10169 };
10170
10171 #include "i386-dis-evex-len.h"
10172
10173 static const struct dis386 vex_w_table[][2] = {
10174   {
10175     /* VEX_W_0F41_P_0_LEN_1 */
10176     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10177     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10178   },
10179   {
10180     /* VEX_W_0F41_P_2_LEN_1 */
10181     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10182     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10183   },
10184   {
10185     /* VEX_W_0F42_P_0_LEN_1 */
10186     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10187     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10188   },
10189   {
10190     /* VEX_W_0F42_P_2_LEN_1 */
10191     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10192     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10193   },
10194   {
10195     /* VEX_W_0F44_P_0_LEN_0 */
10196     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10197     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10198   },
10199   {
10200     /* VEX_W_0F44_P_2_LEN_0 */
10201     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10202     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10203   },
10204   {
10205     /* VEX_W_0F45_P_0_LEN_1 */
10206     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10207     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10208   },
10209   {
10210     /* VEX_W_0F45_P_2_LEN_1 */
10211     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10212     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10213   },
10214   {
10215     /* VEX_W_0F46_P_0_LEN_1 */
10216     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10217     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10218   },
10219   {
10220     /* VEX_W_0F46_P_2_LEN_1 */
10221     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10222     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10223   },
10224   {
10225     /* VEX_W_0F47_P_0_LEN_1 */
10226     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10227     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10228   },
10229   {
10230     /* VEX_W_0F47_P_2_LEN_1 */
10231     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10232     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10233   },
10234   {
10235     /* VEX_W_0F4A_P_0_LEN_1 */
10236     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10237     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10238   },
10239   {
10240     /* VEX_W_0F4A_P_2_LEN_1 */
10241     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10242     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10243   },
10244   {
10245     /* VEX_W_0F4B_P_0_LEN_1 */
10246     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10247     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10248   },
10249   {
10250     /* VEX_W_0F4B_P_2_LEN_1 */
10251     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10252   },
10253   {
10254     /* VEX_W_0F90_P_0_LEN_0 */
10255     { "kmovw",          { MaskG, MaskE }, 0 },
10256     { "kmovq",          { MaskG, MaskE }, 0 },
10257   },
10258   {
10259     /* VEX_W_0F90_P_2_LEN_0 */
10260     { "kmovb",          { MaskG, MaskBDE }, 0 },
10261     { "kmovd",          { MaskG, MaskBDE }, 0 },
10262   },
10263   {
10264     /* VEX_W_0F91_P_0_LEN_0 */
10265     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10266     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10267   },
10268   {
10269     /* VEX_W_0F91_P_2_LEN_0 */
10270     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10271     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10272   },
10273   {
10274     /* VEX_W_0F92_P_0_LEN_0 */
10275     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10276   },
10277   {
10278     /* VEX_W_0F92_P_2_LEN_0 */
10279     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10280   },
10281   {
10282     /* VEX_W_0F93_P_0_LEN_0 */
10283     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10284   },
10285   {
10286     /* VEX_W_0F93_P_2_LEN_0 */
10287     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10288   },
10289   {
10290     /* VEX_W_0F98_P_0_LEN_0 */
10291     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10292     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10293   },
10294   {
10295     /* VEX_W_0F98_P_2_LEN_0 */
10296     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10297     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10298   },
10299   {
10300     /* VEX_W_0F99_P_0_LEN_0 */
10301     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10302     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10303   },
10304   {
10305     /* VEX_W_0F99_P_2_LEN_0 */
10306     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10307     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10308   },
10309   {
10310     /* VEX_W_0F380C_P_2  */
10311     { "vpermilps",      { XM, Vex, EXx }, 0 },
10312   },
10313   {
10314     /* VEX_W_0F380D_P_2  */
10315     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10316   },
10317   {
10318     /* VEX_W_0F380E_P_2  */
10319     { "vtestps",        { XM, EXx }, 0 },
10320   },
10321   {
10322     /* VEX_W_0F380F_P_2  */
10323     { "vtestpd",        { XM, EXx }, 0 },
10324   },
10325   {
10326     /* VEX_W_0F3813_P_2 */
10327     { "vcvtph2ps", { XM, EXxmmq }, 0 },
10328   },
10329   {
10330     /* VEX_W_0F3816_P_2  */
10331     { "vpermps",        { XM, Vex, EXx }, 0 },
10332   },
10333   {
10334     /* VEX_W_0F3818_P_2 */
10335     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10336   },
10337   {
10338     /* VEX_W_0F3819_P_2 */
10339     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10340   },
10341   {
10342     /* VEX_W_0F381A_P_2_M_0 */
10343     { "vbroadcastf128", { XM, Mxmm }, 0 },
10344   },
10345   {
10346     /* VEX_W_0F382C_P_2_M_0 */
10347     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10348   },
10349   {
10350     /* VEX_W_0F382D_P_2_M_0 */
10351     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10352   },
10353   {
10354     /* VEX_W_0F382E_P_2_M_0 */
10355     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10356   },
10357   {
10358     /* VEX_W_0F382F_P_2_M_0 */
10359     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10360   },
10361   {
10362     /* VEX_W_0F3836_P_2  */
10363     { "vpermd",         { XM, Vex, EXx }, 0 },
10364   },
10365   {
10366     /* VEX_W_0F3846_P_2 */
10367     { "vpsravd",        { XM, Vex, EXx }, 0 },
10368   },
10369   {
10370     /* VEX_W_0F3849_X86_64_P_0 */
10371     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
10372   },
10373   {
10374     /* VEX_W_0F3849_X86_64_P_2 */
10375     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
10376   },
10377   {
10378     /* VEX_W_0F3849_X86_64_P_3 */
10379     { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
10380   },
10381   {
10382     /* VEX_W_0F384B_X86_64_P_1 */
10383     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
10384   },
10385   {
10386     /* VEX_W_0F384B_X86_64_P_2 */
10387     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
10388   },
10389   {
10390     /* VEX_W_0F384B_X86_64_P_3 */
10391     { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
10392   },
10393   {
10394     /* VEX_W_0F3858_P_2 */
10395     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10396   },
10397   {
10398     /* VEX_W_0F3859_P_2 */
10399     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10400   },
10401   {
10402     /* VEX_W_0F385A_P_2_M_0 */
10403     { "vbroadcasti128", { XM, Mxmm }, 0 },
10404   },
10405   {
10406     /* VEX_W_0F385C_X86_64_P_1 */
10407     { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
10408   },
10409   {
10410     /* VEX_W_0F385E_X86_64_P_0 */
10411     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
10412   },
10413   {
10414     /* VEX_W_0F385E_X86_64_P_1 */
10415     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
10416   },
10417   {
10418     /* VEX_W_0F385E_X86_64_P_2 */
10419     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
10420   },
10421   {
10422     /* VEX_W_0F385E_X86_64_P_3 */
10423     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
10424   },
10425   {
10426     /* VEX_W_0F3878_P_2 */
10427     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10428   },
10429   {
10430     /* VEX_W_0F3879_P_2 */
10431     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10432   },
10433   {
10434     /* VEX_W_0F38CF_P_2 */
10435     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10436   },
10437   {
10438     /* VEX_W_0F3A00_P_2 */
10439     { Bad_Opcode },
10440     { "vpermq",         { XM, EXx, Ib }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F3A01_P_2 */
10444     { Bad_Opcode },
10445     { "vpermpd",        { XM, EXx, Ib }, 0 },
10446   },
10447   {
10448     /* VEX_W_0F3A02_P_2 */
10449     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10450   },
10451   {
10452     /* VEX_W_0F3A04_P_2 */
10453     { "vpermilps",      { XM, EXx, Ib }, 0 },
10454   },
10455   {
10456     /* VEX_W_0F3A05_P_2 */
10457     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10458   },
10459   {
10460     /* VEX_W_0F3A06_P_2 */
10461     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10462   },
10463   {
10464     /* VEX_W_0F3A18_P_2 */
10465     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10466   },
10467   {
10468     /* VEX_W_0F3A19_P_2 */
10469     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10470   },
10471   {
10472     /* VEX_W_0F3A1D_P_2 */
10473     { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 },
10474   },
10475   {
10476     /* VEX_W_0F3A30_P_2_LEN_0 */
10477     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10478     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10479   },
10480   {
10481     /* VEX_W_0F3A31_P_2_LEN_0 */
10482     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10483     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10484   },
10485   {
10486     /* VEX_W_0F3A32_P_2_LEN_0 */
10487     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10488     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10489   },
10490   {
10491     /* VEX_W_0F3A33_P_2_LEN_0 */
10492     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10493     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10494   },
10495   {
10496     /* VEX_W_0F3A38_P_2 */
10497     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10498   },
10499   {
10500     /* VEX_W_0F3A39_P_2 */
10501     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10502   },
10503   {
10504     /* VEX_W_0F3A46_P_2 */
10505     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10506   },
10507   {
10508     /* VEX_W_0F3A4A_P_2 */
10509     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10510   },
10511   {
10512     /* VEX_W_0F3A4B_P_2 */
10513     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10514   },
10515   {
10516     /* VEX_W_0F3A4C_P_2 */
10517     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10518   },
10519   {
10520     /* VEX_W_0F3ACE_P_2 */
10521     { Bad_Opcode },
10522     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10523   },
10524   {
10525     /* VEX_W_0F3ACF_P_2 */
10526     { Bad_Opcode },
10527     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10528   },
10529   /* VEX_W_0FXOP_08_85_L_0 */
10530   {
10531     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
10532   },
10533   /* VEX_W_0FXOP_08_86_L_0 */
10534   {
10535     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10536   },
10537   /* VEX_W_0FXOP_08_87_L_0 */
10538   {
10539     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
10540   },
10541   /* VEX_W_0FXOP_08_8E_L_0 */
10542   {
10543     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10544   },
10545   /* VEX_W_0FXOP_08_8F_L_0 */
10546   {
10547     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
10548   },
10549   /* VEX_W_0FXOP_08_95_L_0 */
10550   {
10551     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
10552   },
10553   /* VEX_W_0FXOP_08_96_L_0 */
10554   {
10555     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10556   },
10557   /* VEX_W_0FXOP_08_97_L_0 */
10558   {
10559     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
10560   },
10561   /* VEX_W_0FXOP_08_9E_L_0 */
10562   {
10563     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
10564   },
10565   /* VEX_W_0FXOP_08_9F_L_0 */
10566   {
10567     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
10568   },
10569   /* VEX_W_0FXOP_08_A6_L_0 */
10570   {
10571     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
10572   },
10573   /* VEX_W_0FXOP_08_B6_L_0 */
10574   {
10575     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10576   },
10577   /* VEX_W_0FXOP_08_C0_L_0 */
10578   {
10579     { "vprotb",         { XM, EXx, Ib }, 0 },
10580   },
10581   /* VEX_W_0FXOP_08_C1_L_0 */
10582   {
10583     { "vprotw",         { XM, EXx, Ib }, 0 },
10584   },
10585   /* VEX_W_0FXOP_08_C2_L_0 */
10586   {
10587     { "vprotd",         { XM, EXx, Ib }, 0 },
10588   },
10589   /* VEX_W_0FXOP_08_C3_L_0 */
10590   {
10591     { "vprotq",         { XM, EXx, Ib }, 0 },
10592   },
10593   /* VEX_W_0FXOP_08_CC_L_0 */
10594   {
10595      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10596   },
10597   /* VEX_W_0FXOP_08_CD_L_0 */
10598   {
10599      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10600   },
10601   /* VEX_W_0FXOP_08_CE_L_0 */
10602   {
10603      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10604   },
10605   /* VEX_W_0FXOP_08_CF_L_0 */
10606   {
10607      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10608   },
10609   /* VEX_W_0FXOP_08_EC_L_0 */
10610   {
10611      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10612   },
10613   /* VEX_W_0FXOP_08_ED_L_0 */
10614   {
10615      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10616   },
10617   /* VEX_W_0FXOP_08_EE_L_0 */
10618   {
10619      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10620   },
10621   /* VEX_W_0FXOP_08_EF_L_0 */
10622   {
10623      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10624   },
10625   /* VEX_W_0FXOP_09_80 */
10626   {
10627     { "vfrczps",        { XM, EXx }, 0 },
10628   },
10629   /* VEX_W_0FXOP_09_81 */
10630   {
10631     { "vfrczpd",        { XM, EXx }, 0 },
10632   },
10633   /* VEX_W_0FXOP_09_82 */
10634   {
10635     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
10636   },
10637   /* VEX_W_0FXOP_09_83 */
10638   {
10639     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
10640   },
10641   /* VEX_W_0FXOP_09_C1_L_0 */
10642   {
10643     { "vphaddbw",       { XM, EXxmm }, 0 },
10644   },
10645   /* VEX_W_0FXOP_09_C2_L_0 */
10646   {
10647     { "vphaddbd",       { XM, EXxmm }, 0 },
10648   },
10649   /* VEX_W_0FXOP_09_C3_L_0 */
10650   {
10651     { "vphaddbq",       { XM, EXxmm }, 0 },
10652   },
10653   /* VEX_W_0FXOP_09_C6_L_0 */
10654   {
10655     { "vphaddwd",       { XM, EXxmm }, 0 },
10656   },
10657   /* VEX_W_0FXOP_09_C7_L_0 */
10658   {
10659     { "vphaddwq",       { XM, EXxmm }, 0 },
10660   },
10661   /* VEX_W_0FXOP_09_CB_L_0 */
10662   {
10663     { "vphadddq",       { XM, EXxmm }, 0 },
10664   },
10665   /* VEX_W_0FXOP_09_D1_L_0 */
10666   {
10667     { "vphaddubw",      { XM, EXxmm }, 0 },
10668   },
10669   /* VEX_W_0FXOP_09_D2_L_0 */
10670   {
10671     { "vphaddubd",      { XM, EXxmm }, 0 },
10672   },
10673   /* VEX_W_0FXOP_09_D3_L_0 */
10674   {
10675     { "vphaddubq",      { XM, EXxmm }, 0 },
10676   },
10677   /* VEX_W_0FXOP_09_D6_L_0 */
10678   {
10679     { "vphadduwd",      { XM, EXxmm }, 0 },
10680   },
10681   /* VEX_W_0FXOP_09_D7_L_0 */
10682   {
10683     { "vphadduwq",      { XM, EXxmm }, 0 },
10684   },
10685   /* VEX_W_0FXOP_09_DB_L_0 */
10686   {
10687     { "vphaddudq",      { XM, EXxmm }, 0 },
10688   },
10689   /* VEX_W_0FXOP_09_E1_L_0 */
10690   {
10691     { "vphsubbw",       { XM, EXxmm }, 0 },
10692   },
10693   /* VEX_W_0FXOP_09_E2_L_0 */
10694   {
10695     { "vphsubwd",       { XM, EXxmm }, 0 },
10696   },
10697   /* VEX_W_0FXOP_09_E3_L_0 */
10698   {
10699     { "vphsubdq",       { XM, EXxmm }, 0 },
10700   },
10701
10702 #include "i386-dis-evex-w.h"
10703 };
10704
10705 static const struct dis386 mod_table[][2] = {
10706   {
10707     /* MOD_8D */
10708     { "leaS",           { Gv, M }, 0 },
10709   },
10710   {
10711     /* MOD_C6_REG_7 */
10712     { Bad_Opcode },
10713     { RM_TABLE (RM_C6_REG_7) },
10714   },
10715   {
10716     /* MOD_C7_REG_7 */
10717     { Bad_Opcode },
10718     { RM_TABLE (RM_C7_REG_7) },
10719   },
10720   {
10721     /* MOD_FF_REG_3 */
10722     { "{l|}call^", { indirEp }, 0 },
10723   },
10724   {
10725     /* MOD_FF_REG_5 */
10726     { "{l|}jmp^", { indirEp }, 0 },
10727   },
10728   {
10729     /* MOD_0F01_REG_0 */
10730     { X86_64_TABLE (X86_64_0F01_REG_0) },
10731     { RM_TABLE (RM_0F01_REG_0) },
10732   },
10733   {
10734     /* MOD_0F01_REG_1 */
10735     { X86_64_TABLE (X86_64_0F01_REG_1) },
10736     { RM_TABLE (RM_0F01_REG_1) },
10737   },
10738   {
10739     /* MOD_0F01_REG_2 */
10740     { X86_64_TABLE (X86_64_0F01_REG_2) },
10741     { RM_TABLE (RM_0F01_REG_2) },
10742   },
10743   {
10744     /* MOD_0F01_REG_3 */
10745     { X86_64_TABLE (X86_64_0F01_REG_3) },
10746     { RM_TABLE (RM_0F01_REG_3) },
10747   },
10748   {
10749     /* MOD_0F01_REG_5 */
10750     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10751     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10752   },
10753   {
10754     /* MOD_0F01_REG_7 */
10755     { "invlpg",         { Mb }, 0 },
10756     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10757   },
10758   {
10759     /* MOD_0F12_PREFIX_0 */
10760     { "movlpX",         { XM, EXq }, 0 },
10761     { "movhlps",        { XM, EXq }, 0 },
10762   },
10763   {
10764     /* MOD_0F12_PREFIX_2 */
10765     { "movlpX", { XM, EXq }, 0 },
10766   },
10767   {
10768     /* MOD_0F13 */
10769     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10770   },
10771   {
10772     /* MOD_0F16_PREFIX_0 */
10773     { "movhpX",         { XM, EXq }, 0 },
10774     { "movlhps",        { XM, EXq }, 0 },
10775   },
10776   {
10777     /* MOD_0F16_PREFIX_2 */
10778     { "movhpX", { XM, EXq }, 0 },
10779   },
10780   {
10781     /* MOD_0F17 */
10782     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10783   },
10784   {
10785     /* MOD_0F18_REG_0 */
10786     { "prefetchnta",    { Mb }, 0 },
10787   },
10788   {
10789     /* MOD_0F18_REG_1 */
10790     { "prefetcht0",     { Mb }, 0 },
10791   },
10792   {
10793     /* MOD_0F18_REG_2 */
10794     { "prefetcht1",     { Mb }, 0 },
10795   },
10796   {
10797     /* MOD_0F18_REG_3 */
10798     { "prefetcht2",     { Mb }, 0 },
10799   },
10800   {
10801     /* MOD_0F18_REG_4 */
10802     { "nop/reserved",   { Mb }, 0 },
10803   },
10804   {
10805     /* MOD_0F18_REG_5 */
10806     { "nop/reserved",   { Mb }, 0 },
10807   },
10808   {
10809     /* MOD_0F18_REG_6 */
10810     { "nop/reserved",   { Mb }, 0 },
10811   },
10812   {
10813     /* MOD_0F18_REG_7 */
10814     { "nop/reserved",   { Mb }, 0 },
10815   },
10816   {
10817     /* MOD_0F1A_PREFIX_0 */
10818     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10819     { "nopQ",           { Ev }, 0 },
10820   },
10821   {
10822     /* MOD_0F1B_PREFIX_0 */
10823     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10824     { "nopQ",           { Ev }, 0 },
10825   },
10826   {
10827     /* MOD_0F1B_PREFIX_1 */
10828     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10829     { "nopQ",           { Ev }, 0 },
10830   },
10831   {
10832     /* MOD_0F1C_PREFIX_0 */
10833     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10834     { "nopQ",           { Ev }, 0 },
10835   },
10836   {
10837     /* MOD_0F1E_PREFIX_1 */
10838     { "nopQ",           { Ev }, 0 },
10839     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10840   },
10841   {
10842     /* MOD_0F24 */
10843     { Bad_Opcode },
10844     { "movL",           { Rd, Td }, 0 },
10845   },
10846   {
10847     /* MOD_0F26 */
10848     { Bad_Opcode },
10849     { "movL",           { Td, Rd }, 0 },
10850   },
10851   {
10852     /* MOD_0F2B_PREFIX_0 */
10853     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10854   },
10855   {
10856     /* MOD_0F2B_PREFIX_1 */
10857     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10858   },
10859   {
10860     /* MOD_0F2B_PREFIX_2 */
10861     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10862   },
10863   {
10864     /* MOD_0F2B_PREFIX_3 */
10865     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10866   },
10867   {
10868     /* MOD_0F50 */
10869     { Bad_Opcode },
10870     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10871   },
10872   {
10873     /* MOD_0F71_REG_2 */
10874     { Bad_Opcode },
10875     { "psrlw",          { MS, Ib }, 0 },
10876   },
10877   {
10878     /* MOD_0F71_REG_4 */
10879     { Bad_Opcode },
10880     { "psraw",          { MS, Ib }, 0 },
10881   },
10882   {
10883     /* MOD_0F71_REG_6 */
10884     { Bad_Opcode },
10885     { "psllw",          { MS, Ib }, 0 },
10886   },
10887   {
10888     /* MOD_0F72_REG_2 */
10889     { Bad_Opcode },
10890     { "psrld",          { MS, Ib }, 0 },
10891   },
10892   {
10893     /* MOD_0F72_REG_4 */
10894     { Bad_Opcode },
10895     { "psrad",          { MS, Ib }, 0 },
10896   },
10897   {
10898     /* MOD_0F72_REG_6 */
10899     { Bad_Opcode },
10900     { "pslld",          { MS, Ib }, 0 },
10901   },
10902   {
10903     /* MOD_0F73_REG_2 */
10904     { Bad_Opcode },
10905     { "psrlq",          { MS, Ib }, 0 },
10906   },
10907   {
10908     /* MOD_0F73_REG_3 */
10909     { Bad_Opcode },
10910     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10911   },
10912   {
10913     /* MOD_0F73_REG_6 */
10914     { Bad_Opcode },
10915     { "psllq",          { MS, Ib }, 0 },
10916   },
10917   {
10918     /* MOD_0F73_REG_7 */
10919     { Bad_Opcode },
10920     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10921   },
10922   {
10923     /* MOD_0FAE_REG_0 */
10924     { "fxsave",         { FXSAVE }, 0 },
10925     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10926   },
10927   {
10928     /* MOD_0FAE_REG_1 */
10929     { "fxrstor",        { FXSAVE }, 0 },
10930     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10931   },
10932   {
10933     /* MOD_0FAE_REG_2 */
10934     { "ldmxcsr",        { Md }, 0 },
10935     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10936   },
10937   {
10938     /* MOD_0FAE_REG_3 */
10939     { "stmxcsr",        { Md }, 0 },
10940     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10941   },
10942   {
10943     /* MOD_0FAE_REG_4 */
10944     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10945     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10946   },
10947   {
10948     /* MOD_0FAE_REG_5 */
10949     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10950     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10951   },
10952   {
10953     /* MOD_0FAE_REG_6 */
10954     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10955     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10956   },
10957   {
10958     /* MOD_0FAE_REG_7 */
10959     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10960     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10961   },
10962   {
10963     /* MOD_0FB2 */
10964     { "lssS",           { Gv, Mp }, 0 },
10965   },
10966   {
10967     /* MOD_0FB4 */
10968     { "lfsS",           { Gv, Mp }, 0 },
10969   },
10970   {
10971     /* MOD_0FB5 */
10972     { "lgsS",           { Gv, Mp }, 0 },
10973   },
10974   {
10975     /* MOD_0FC3 */
10976     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10977   },
10978   {
10979     /* MOD_0FC7_REG_3 */
10980     { "xrstors",        { FXSAVE }, 0 },
10981   },
10982   {
10983     /* MOD_0FC7_REG_4 */
10984     { "xsavec",         { FXSAVE }, 0 },
10985   },
10986   {
10987     /* MOD_0FC7_REG_5 */
10988     { "xsaves",         { FXSAVE }, 0 },
10989   },
10990   {
10991     /* MOD_0FC7_REG_6 */
10992     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10993     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10994   },
10995   {
10996     /* MOD_0FC7_REG_7 */
10997     { "vmptrst",        { Mq }, 0 },
10998     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10999   },
11000   {
11001     /* MOD_0FD7 */
11002     { Bad_Opcode },
11003     { "pmovmskb",       { Gdq, MS }, 0 },
11004   },
11005   {
11006     /* MOD_0FE7_PREFIX_2 */
11007     { "movntdq",        { Mx, XM }, 0 },
11008   },
11009   {
11010     /* MOD_0FF0_PREFIX_3 */
11011     { "lddqu",          { XM, M }, 0 },
11012   },
11013   {
11014     /* MOD_0F382A_PREFIX_2 */
11015     { "movntdqa",       { XM, Mx }, 0 },
11016   },
11017   {
11018     /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
11019     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
11020     { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
11021   },
11022   {
11023     /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
11024     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
11025   },
11026   {
11027     /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
11028     { Bad_Opcode },
11029     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
11030   },
11031   {
11032     /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
11033     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
11034   },
11035   {
11036     /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
11037     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
11038   },
11039   {
11040     /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
11041     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
11042   },
11043   {
11044     /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
11045     { Bad_Opcode },
11046     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
11047   },
11048   {
11049     /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
11050     { Bad_Opcode },
11051     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
11052   },
11053   {
11054     /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
11055     { Bad_Opcode },
11056     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
11057   },
11058   {
11059     /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
11060     { Bad_Opcode },
11061     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
11062   },
11063   {
11064     /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
11065     { Bad_Opcode },
11066     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
11067   },
11068   {
11069     /* MOD_0F38F5_PREFIX_2 */
11070     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11071   },
11072   {
11073     /* MOD_0F38F6_PREFIX_0 */
11074     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11075   },
11076   {
11077     /* MOD_0F38F8_PREFIX_1 */
11078     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
11079   },
11080   {
11081     /* MOD_0F38F8_PREFIX_2 */
11082     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11083   },
11084   {
11085     /* MOD_0F38F8_PREFIX_3 */
11086     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
11087   },
11088   {
11089     /* MOD_0F38F9_PREFIX_0 */
11090     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
11091   },
11092   {
11093     /* MOD_62_32BIT */
11094     { "bound{S|}",      { Gv, Ma }, 0 },
11095     { EVEX_TABLE (EVEX_0F) },
11096   },
11097   {
11098     /* MOD_C4_32BIT */
11099     { "lesS",           { Gv, Mp }, 0 },
11100     { VEX_C4_TABLE (VEX_0F) },
11101   },
11102   {
11103     /* MOD_C5_32BIT */
11104     { "ldsS",           { Gv, Mp }, 0 },
11105     { VEX_C5_TABLE (VEX_0F) },
11106   },
11107   {
11108     /* MOD_VEX_0F12_PREFIX_0 */
11109     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11110     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11111   },
11112   {
11113     /* MOD_VEX_0F12_PREFIX_2 */
11114     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
11115   },
11116   {
11117     /* MOD_VEX_0F13 */
11118     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11119   },
11120   {
11121     /* MOD_VEX_0F16_PREFIX_0 */
11122     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11123     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11124   },
11125   {
11126     /* MOD_VEX_0F16_PREFIX_2 */
11127     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
11128   },
11129   {
11130     /* MOD_VEX_0F17 */
11131     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11132   },
11133   {
11134     /* MOD_VEX_0F2B */
11135     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
11136   },
11137   {
11138     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11139     { Bad_Opcode },
11140     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11141   },
11142   {
11143     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11144     { Bad_Opcode },
11145     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11146   },
11147   {
11148     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11149     { Bad_Opcode },
11150     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11151   },
11152   {
11153     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11154     { Bad_Opcode },
11155     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11156   },
11157   {
11158     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11159     { Bad_Opcode },
11160     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11161   },
11162   {
11163     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11164     { Bad_Opcode },
11165     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11166   },
11167   {
11168     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11169     { Bad_Opcode },
11170     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11171   },
11172   {
11173     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11174     { Bad_Opcode },
11175     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11176   },
11177   {
11178     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11179     { Bad_Opcode },
11180     { "knotw",          { MaskG, MaskR }, 0 },
11181   },
11182   {
11183     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11184     { Bad_Opcode },
11185     { "knotq",          { MaskG, MaskR }, 0 },
11186   },
11187   {
11188     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11189     { Bad_Opcode },
11190     { "knotb",          { MaskG, MaskR }, 0 },
11191   },
11192   {
11193     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11194     { Bad_Opcode },
11195     { "knotd",          { MaskG, MaskR }, 0 },
11196   },
11197   {
11198     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11199     { Bad_Opcode },
11200     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11201   },
11202   {
11203     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11204     { Bad_Opcode },
11205     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11206   },
11207   {
11208     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11209     { Bad_Opcode },
11210     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11211   },
11212   {
11213     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11214     { Bad_Opcode },
11215     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11216   },
11217  {
11218     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11219     { Bad_Opcode },
11220     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11221   },
11222   {
11223     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11224     { Bad_Opcode },
11225     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11226   },
11227   {
11228     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11229     { Bad_Opcode },
11230     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11231   },
11232   {
11233     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11234     { Bad_Opcode },
11235     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11236   },
11237   {
11238     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11239     { Bad_Opcode },
11240     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11241   },
11242   {
11243     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11244     { Bad_Opcode },
11245     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11246   },
11247   {
11248     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11249     { Bad_Opcode },
11250     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11251   },
11252   {
11253     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11254     { Bad_Opcode },
11255     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11256   },
11257   {
11258     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11259     { Bad_Opcode },
11260     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11261   },
11262   {
11263     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11264     { Bad_Opcode },
11265     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11266   },
11267   {
11268     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11269     { Bad_Opcode },
11270     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11271   },
11272   {
11273     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11274     { Bad_Opcode },
11275     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11276   },
11277   {
11278     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11279     { Bad_Opcode },
11280     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11281   },
11282   {
11283     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11284     { Bad_Opcode },
11285     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11286   },
11287   {
11288     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11289     { Bad_Opcode },
11290     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11291   },
11292   {
11293     /* MOD_VEX_0F50 */
11294     { Bad_Opcode },
11295     { "vmovmskpX",      { Gdq, XS }, PREFIX_OPCODE },
11296   },
11297   {
11298     /* MOD_VEX_0F71_REG_2 */
11299     { Bad_Opcode },
11300     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11301   },
11302   {
11303     /* MOD_VEX_0F71_REG_4 */
11304     { Bad_Opcode },
11305     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11306   },
11307   {
11308     /* MOD_VEX_0F71_REG_6 */
11309     { Bad_Opcode },
11310     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11311   },
11312   {
11313     /* MOD_VEX_0F72_REG_2 */
11314     { Bad_Opcode },
11315     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11316   },
11317   {
11318     /* MOD_VEX_0F72_REG_4 */
11319     { Bad_Opcode },
11320     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11321   },
11322   {
11323     /* MOD_VEX_0F72_REG_6 */
11324     { Bad_Opcode },
11325     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11326   },
11327   {
11328     /* MOD_VEX_0F73_REG_2 */
11329     { Bad_Opcode },
11330     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11331   },
11332   {
11333     /* MOD_VEX_0F73_REG_3 */
11334     { Bad_Opcode },
11335     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11336   },
11337   {
11338     /* MOD_VEX_0F73_REG_6 */
11339     { Bad_Opcode },
11340     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11341   },
11342   {
11343     /* MOD_VEX_0F73_REG_7 */
11344     { Bad_Opcode },
11345     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11346   },
11347   {
11348     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11349     { "kmovw",          { Ew, MaskG }, 0 },
11350     { Bad_Opcode },
11351   },
11352   {
11353     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11354     { "kmovq",          { Eq, MaskG }, 0 },
11355     { Bad_Opcode },
11356   },
11357   {
11358     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11359     { "kmovb",          { Eb, MaskG }, 0 },
11360     { Bad_Opcode },
11361   },
11362   {
11363     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11364     { "kmovd",          { Ed, MaskG }, 0 },
11365     { Bad_Opcode },
11366   },
11367   {
11368     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11369     { Bad_Opcode },
11370     { "kmovw",          { MaskG, Rdq }, 0 },
11371   },
11372   {
11373     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11374     { Bad_Opcode },
11375     { "kmovb",          { MaskG, Rdq }, 0 },
11376   },
11377   {
11378     /* MOD_VEX_0F92_P_3_LEN_0 */
11379     { Bad_Opcode },
11380     { "kmovK",          { MaskG, Rdq }, 0 },
11381   },
11382   {
11383     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11384     { Bad_Opcode },
11385     { "kmovw",          { Gdq, MaskR }, 0 },
11386   },
11387   {
11388     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11389     { Bad_Opcode },
11390     { "kmovb",          { Gdq, MaskR }, 0 },
11391   },
11392   {
11393     /* MOD_VEX_0F93_P_3_LEN_0 */
11394     { Bad_Opcode },
11395     { "kmovK",          { Gdq, MaskR }, 0 },
11396   },
11397   {
11398     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11399     { Bad_Opcode },
11400     { "kortestw", { MaskG, MaskR }, 0 },
11401   },
11402   {
11403     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11404     { Bad_Opcode },
11405     { "kortestq", { MaskG, MaskR }, 0 },
11406   },
11407   {
11408     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11409     { Bad_Opcode },
11410     { "kortestb", { MaskG, MaskR }, 0 },
11411   },
11412   {
11413     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11414     { Bad_Opcode },
11415     { "kortestd", { MaskG, MaskR }, 0 },
11416   },
11417   {
11418     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11419     { Bad_Opcode },
11420     { "ktestw", { MaskG, MaskR }, 0 },
11421   },
11422   {
11423     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
11424     { Bad_Opcode },
11425     { "ktestq", { MaskG, MaskR }, 0 },
11426   },
11427   {
11428     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
11429     { Bad_Opcode },
11430     { "ktestb", { MaskG, MaskR }, 0 },
11431   },
11432   {
11433     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
11434     { Bad_Opcode },
11435     { "ktestd", { MaskG, MaskR }, 0 },
11436   },
11437   {
11438     /* MOD_VEX_0FAE_REG_2 */
11439     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11440   },
11441   {
11442     /* MOD_VEX_0FAE_REG_3 */
11443     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11444   },
11445   {
11446     /* MOD_VEX_0FD7_PREFIX_2 */
11447     { Bad_Opcode },
11448     { "vpmovmskb",      { Gdq, XS }, 0 },
11449   },
11450   {
11451     /* MOD_VEX_0FE7_PREFIX_2 */
11452     { "vmovntdq",       { Mx, XM }, 0 },
11453   },
11454   {
11455     /* MOD_VEX_0FF0_PREFIX_3 */
11456     { "vlddqu",         { XM, M }, 0 },
11457   },
11458   {
11459     /* MOD_VEX_0F381A_PREFIX_2 */
11460     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11461   },
11462   {
11463     /* MOD_VEX_0F382A_PREFIX_2 */
11464     { "vmovntdqa",      { XM, Mx }, 0 },
11465   },
11466   {
11467     /* MOD_VEX_0F382C_PREFIX_2 */
11468     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11469   },
11470   {
11471     /* MOD_VEX_0F382D_PREFIX_2 */
11472     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11473   },
11474   {
11475     /* MOD_VEX_0F382E_PREFIX_2 */
11476     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11477   },
11478   {
11479     /* MOD_VEX_0F382F_PREFIX_2 */
11480     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11481   },
11482   {
11483     /* MOD_VEX_0F385A_PREFIX_2 */
11484     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11485   },
11486   {
11487     /* MOD_VEX_0F388C_PREFIX_2 */
11488     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
11489   },
11490   {
11491     /* MOD_VEX_0F388E_PREFIX_2 */
11492     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
11493   },
11494   {
11495     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
11496     { Bad_Opcode },
11497     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
11498   },
11499   {
11500     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
11501     { Bad_Opcode },
11502     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
11503   },
11504   {
11505     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
11506     { Bad_Opcode },
11507     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
11508   },
11509   {
11510     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
11511     { Bad_Opcode },
11512     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
11513   },
11514   {
11515     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
11516     { Bad_Opcode },
11517     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
11518   },
11519   {
11520     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
11521     { Bad_Opcode },
11522     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
11523   },
11524   {
11525     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11526     { Bad_Opcode },
11527     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
11528   },
11529   {
11530     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11531     { Bad_Opcode },
11532     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
11533   },
11534   {
11535     /* MOD_VEX_0FXOP_09_12 */
11536     { Bad_Opcode },
11537     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
11538   },
11539
11540 #include "i386-dis-evex-mod.h"
11541 };
11542
11543 static const struct dis386 rm_table[][8] = {
11544   {
11545     /* RM_C6_REG_7 */
11546     { "xabort",         { Skip_MODRM, Ib }, 0 },
11547   },
11548   {
11549     /* RM_C7_REG_7 */
11550     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
11551   },
11552   {
11553     /* RM_0F01_REG_0 */
11554     { "enclv",          { Skip_MODRM }, 0 },
11555     { "vmcall",         { Skip_MODRM }, 0 },
11556     { "vmlaunch",       { Skip_MODRM }, 0 },
11557     { "vmresume",       { Skip_MODRM }, 0 },
11558     { "vmxoff",         { Skip_MODRM }, 0 },
11559     { "pconfig",        { Skip_MODRM }, 0 },
11560   },
11561   {
11562     /* RM_0F01_REG_1 */
11563     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11564     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11565     { "clac",           { Skip_MODRM }, 0 },
11566     { "stac",           { Skip_MODRM }, 0 },
11567     { Bad_Opcode },
11568     { Bad_Opcode },
11569     { Bad_Opcode },
11570     { "encls",          { Skip_MODRM }, 0 },
11571   },
11572   {
11573     /* RM_0F01_REG_2 */
11574     { "xgetbv",         { Skip_MODRM }, 0 },
11575     { "xsetbv",         { Skip_MODRM }, 0 },
11576     { Bad_Opcode },
11577     { Bad_Opcode },
11578     { "vmfunc",         { Skip_MODRM }, 0 },
11579     { "xend",           { Skip_MODRM }, 0 },
11580     { "xtest",          { Skip_MODRM }, 0 },
11581     { "enclu",          { Skip_MODRM }, 0 },
11582   },
11583   {
11584     /* RM_0F01_REG_3 */
11585     { "vmrun",          { Skip_MODRM }, 0 },
11586     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
11587     { "vmload",         { Skip_MODRM }, 0 },
11588     { "vmsave",         { Skip_MODRM }, 0 },
11589     { "stgi",           { Skip_MODRM }, 0 },
11590     { "clgi",           { Skip_MODRM }, 0 },
11591     { "skinit",         { Skip_MODRM }, 0 },
11592     { "invlpga",        { Skip_MODRM }, 0 },
11593   },
11594   {
11595     /* RM_0F01_REG_5_MOD_3 */
11596     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11597     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
11598     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11599     { Bad_Opcode },
11600     { Bad_Opcode },
11601     { Bad_Opcode },
11602     { "rdpkru",         { Skip_MODRM }, 0 },
11603     { "wrpkru",         { Skip_MODRM }, 0 },
11604   },
11605   {
11606     /* RM_0F01_REG_7_MOD_3 */
11607     { "swapgs",         { Skip_MODRM }, 0  },
11608     { "rdtscp",         { Skip_MODRM }, 0  },
11609     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11610     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11611     { "clzero",         { Skip_MODRM }, 0  },
11612     { "rdpru",          { Skip_MODRM }, 0  },
11613   },
11614   {
11615     /* RM_0F1E_P_1_MOD_3_REG_7 */
11616     { "nopQ",           { Ev }, 0 },
11617     { "nopQ",           { Ev }, 0 },
11618     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11619     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11620     { "nopQ",           { Ev }, 0 },
11621     { "nopQ",           { Ev }, 0 },
11622     { "nopQ",           { Ev }, 0 },
11623     { "nopQ",           { Ev }, 0 },
11624   },
11625   {
11626     /* RM_0FAE_REG_6_MOD_3 */
11627     { "mfence",         { Skip_MODRM }, 0 },
11628   },
11629   {
11630     /* RM_0FAE_REG_7_MOD_3 */
11631     { "sfence",         { Skip_MODRM }, 0 },
11632
11633   },
11634   {
11635     /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
11636     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
11637   },
11638 };
11639
11640 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11641
11642 /* We use the high bit to indicate different name for the same
11643    prefix.  */
11644 #define REP_PREFIX      (0xf3 | 0x100)
11645 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11646 #define XRELEASE_PREFIX (0xf3 | 0x400)
11647 #define BND_PREFIX      (0xf2 | 0x400)
11648 #define NOTRACK_PREFIX  (0x3e | 0x100)
11649
11650 /* Remember if the current op is a jump instruction.  */
11651 static bfd_boolean op_is_jump = FALSE;
11652
11653 static int
11654 ckprefix (void)
11655 {
11656   int newrex, i, length;
11657   rex = 0;
11658   prefixes = 0;
11659   used_prefixes = 0;
11660   rex_used = 0;
11661   last_lock_prefix = -1;
11662   last_repz_prefix = -1;
11663   last_repnz_prefix = -1;
11664   last_data_prefix = -1;
11665   last_addr_prefix = -1;
11666   last_rex_prefix = -1;
11667   last_seg_prefix = -1;
11668   fwait_prefix = -1;
11669   active_seg_prefix = 0;
11670   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11671     all_prefixes[i] = 0;
11672   i = 0;
11673   length = 0;
11674   /* The maximum instruction length is 15bytes.  */
11675   while (length < MAX_CODE_LENGTH - 1)
11676     {
11677       FETCH_DATA (the_info, codep + 1);
11678       newrex = 0;
11679       switch (*codep)
11680         {
11681         /* REX prefixes family.  */
11682         case 0x40:
11683         case 0x41:
11684         case 0x42:
11685         case 0x43:
11686         case 0x44:
11687         case 0x45:
11688         case 0x46:
11689         case 0x47:
11690         case 0x48:
11691         case 0x49:
11692         case 0x4a:
11693         case 0x4b:
11694         case 0x4c:
11695         case 0x4d:
11696         case 0x4e:
11697         case 0x4f:
11698           if (address_mode == mode_64bit)
11699             newrex = *codep;
11700           else
11701             return 1;
11702           last_rex_prefix = i;
11703           break;
11704         case 0xf3:
11705           prefixes |= PREFIX_REPZ;
11706           last_repz_prefix = i;
11707           break;
11708         case 0xf2:
11709           prefixes |= PREFIX_REPNZ;
11710           last_repnz_prefix = i;
11711           break;
11712         case 0xf0:
11713           prefixes |= PREFIX_LOCK;
11714           last_lock_prefix = i;
11715           break;
11716         case 0x2e:
11717           prefixes |= PREFIX_CS;
11718           last_seg_prefix = i;
11719           active_seg_prefix = PREFIX_CS;
11720           break;
11721         case 0x36:
11722           prefixes |= PREFIX_SS;
11723           last_seg_prefix = i;
11724           active_seg_prefix = PREFIX_SS;
11725           break;
11726         case 0x3e:
11727           prefixes |= PREFIX_DS;
11728           last_seg_prefix = i;
11729           active_seg_prefix = PREFIX_DS;
11730           break;
11731         case 0x26:
11732           prefixes |= PREFIX_ES;
11733           last_seg_prefix = i;
11734           active_seg_prefix = PREFIX_ES;
11735           break;
11736         case 0x64:
11737           prefixes |= PREFIX_FS;
11738           last_seg_prefix = i;
11739           active_seg_prefix = PREFIX_FS;
11740           break;
11741         case 0x65:
11742           prefixes |= PREFIX_GS;
11743           last_seg_prefix = i;
11744           active_seg_prefix = PREFIX_GS;
11745           break;
11746         case 0x66:
11747           prefixes |= PREFIX_DATA;
11748           last_data_prefix = i;
11749           break;
11750         case 0x67:
11751           prefixes |= PREFIX_ADDR;
11752           last_addr_prefix = i;
11753           break;
11754         case FWAIT_OPCODE:
11755           /* fwait is really an instruction.  If there are prefixes
11756              before the fwait, they belong to the fwait, *not* to the
11757              following instruction.  */
11758           fwait_prefix = i;
11759           if (prefixes || rex)
11760             {
11761               prefixes |= PREFIX_FWAIT;
11762               codep++;
11763               /* This ensures that the previous REX prefixes are noticed
11764                  as unused prefixes, as in the return case below.  */
11765               rex_used = rex;
11766               return 1;
11767             }
11768           prefixes = PREFIX_FWAIT;
11769           break;
11770         default:
11771           return 1;
11772         }
11773       /* Rex is ignored when followed by another prefix.  */
11774       if (rex)
11775         {
11776           rex_used = rex;
11777           return 1;
11778         }
11779       if (*codep != FWAIT_OPCODE)
11780         all_prefixes[i++] = *codep;
11781       rex = newrex;
11782       codep++;
11783       length++;
11784     }
11785   return 0;
11786 }
11787
11788 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11789    prefix byte.  */
11790
11791 static const char *
11792 prefix_name (int pref, int sizeflag)
11793 {
11794   static const char *rexes [16] =
11795     {
11796       "rex",            /* 0x40 */
11797       "rex.B",          /* 0x41 */
11798       "rex.X",          /* 0x42 */
11799       "rex.XB",         /* 0x43 */
11800       "rex.R",          /* 0x44 */
11801       "rex.RB",         /* 0x45 */
11802       "rex.RX",         /* 0x46 */
11803       "rex.RXB",        /* 0x47 */
11804       "rex.W",          /* 0x48 */
11805       "rex.WB",         /* 0x49 */
11806       "rex.WX",         /* 0x4a */
11807       "rex.WXB",        /* 0x4b */
11808       "rex.WR",         /* 0x4c */
11809       "rex.WRB",        /* 0x4d */
11810       "rex.WRX",        /* 0x4e */
11811       "rex.WRXB",       /* 0x4f */
11812     };
11813
11814   switch (pref)
11815     {
11816     /* REX prefixes family.  */
11817     case 0x40:
11818     case 0x41:
11819     case 0x42:
11820     case 0x43:
11821     case 0x44:
11822     case 0x45:
11823     case 0x46:
11824     case 0x47:
11825     case 0x48:
11826     case 0x49:
11827     case 0x4a:
11828     case 0x4b:
11829     case 0x4c:
11830     case 0x4d:
11831     case 0x4e:
11832     case 0x4f:
11833       return rexes [pref - 0x40];
11834     case 0xf3:
11835       return "repz";
11836     case 0xf2:
11837       return "repnz";
11838     case 0xf0:
11839       return "lock";
11840     case 0x2e:
11841       return "cs";
11842     case 0x36:
11843       return "ss";
11844     case 0x3e:
11845       return "ds";
11846     case 0x26:
11847       return "es";
11848     case 0x64:
11849       return "fs";
11850     case 0x65:
11851       return "gs";
11852     case 0x66:
11853       return (sizeflag & DFLAG) ? "data16" : "data32";
11854     case 0x67:
11855       if (address_mode == mode_64bit)
11856         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11857       else
11858         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11859     case FWAIT_OPCODE:
11860       return "fwait";
11861     case REP_PREFIX:
11862       return "rep";
11863     case XACQUIRE_PREFIX:
11864       return "xacquire";
11865     case XRELEASE_PREFIX:
11866       return "xrelease";
11867     case BND_PREFIX:
11868       return "bnd";
11869     case NOTRACK_PREFIX:
11870       return "notrack";
11871     default:
11872       return NULL;
11873     }
11874 }
11875
11876 static char op_out[MAX_OPERANDS][100];
11877 static int op_ad, op_index[MAX_OPERANDS];
11878 static int two_source_ops;
11879 static bfd_vma op_address[MAX_OPERANDS];
11880 static bfd_vma op_riprel[MAX_OPERANDS];
11881 static bfd_vma start_pc;
11882
11883 /*
11884  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11885  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11886  *   section of the "Virtual 8086 Mode" chapter.)
11887  * 'pc' should be the address of this instruction, it will
11888  *   be used to print the target address if this is a relative jump or call
11889  * The function returns the length of this instruction in bytes.
11890  */
11891
11892 static char intel_syntax;
11893 static char intel_mnemonic = !SYSV386_COMPAT;
11894 static char open_char;
11895 static char close_char;
11896 static char separator_char;
11897 static char scale_char;
11898
11899 enum x86_64_isa
11900 {
11901   amd64 = 1,
11902   intel64
11903 };
11904
11905 static enum x86_64_isa isa64;
11906
11907 /* Here for backwards compatibility.  When gdb stops using
11908    print_insn_i386_att and print_insn_i386_intel these functions can
11909    disappear, and print_insn_i386 be merged into print_insn.  */
11910 int
11911 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11912 {
11913   intel_syntax = 0;
11914
11915   return print_insn (pc, info);
11916 }
11917
11918 int
11919 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11920 {
11921   intel_syntax = 1;
11922
11923   return print_insn (pc, info);
11924 }
11925
11926 int
11927 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11928 {
11929   intel_syntax = -1;
11930
11931   return print_insn (pc, info);
11932 }
11933
11934 void
11935 print_i386_disassembler_options (FILE *stream)
11936 {
11937   fprintf (stream, _("\n\
11938 The following i386/x86-64 specific disassembler options are supported for use\n\
11939 with the -M switch (multiple options should be separated by commas):\n"));
11940
11941   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11942   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11943   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11944   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11945   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11946   fprintf (stream, _("  att-mnemonic\n"
11947                      "              Display instruction in AT&T mnemonic\n"));
11948   fprintf (stream, _("  intel-mnemonic\n"
11949                      "              Display instruction in Intel mnemonic\n"));
11950   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11951   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11952   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11953   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11954   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11955   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11956   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11957   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11958 }
11959
11960 /* Bad opcode.  */
11961 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11962
11963 /* Get a pointer to struct dis386 with a valid name.  */
11964
11965 static const struct dis386 *
11966 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11967 {
11968   int vindex, vex_table_index;
11969
11970   if (dp->name != NULL)
11971     return dp;
11972
11973   switch (dp->op[0].bytemode)
11974     {
11975     case USE_REG_TABLE:
11976       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11977       break;
11978
11979     case USE_MOD_TABLE:
11980       vindex = modrm.mod == 0x3 ? 1 : 0;
11981       dp = &mod_table[dp->op[1].bytemode][vindex];
11982       break;
11983
11984     case USE_RM_TABLE:
11985       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11986       break;
11987
11988     case USE_PREFIX_TABLE:
11989       if (need_vex)
11990         {
11991           /* The prefix in VEX is implicit.  */
11992           switch (vex.prefix)
11993             {
11994             case 0:
11995               vindex = 0;
11996               break;
11997             case REPE_PREFIX_OPCODE:
11998               vindex = 1;
11999               break;
12000             case DATA_PREFIX_OPCODE:
12001               vindex = 2;
12002               break;
12003             case REPNE_PREFIX_OPCODE:
12004               vindex = 3;
12005               break;
12006             default:
12007               abort ();
12008               break;
12009             }
12010         }
12011       else
12012         {
12013           int last_prefix = -1;
12014           int prefix = 0;
12015           vindex = 0;
12016           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12017              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12018              last one wins.  */
12019           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12020             {
12021               if (last_repz_prefix > last_repnz_prefix)
12022                 {
12023                   vindex = 1;
12024                   prefix = PREFIX_REPZ;
12025                   last_prefix = last_repz_prefix;
12026                 }
12027               else
12028                 {
12029                   vindex = 3;
12030                   prefix = PREFIX_REPNZ;
12031                   last_prefix = last_repnz_prefix;
12032                 }
12033
12034               /* Check if prefix should be ignored.  */
12035               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12036                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12037                    & prefix) != 0)
12038                 vindex = 0;
12039             }
12040
12041           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12042             {
12043               vindex = 2;
12044               prefix = PREFIX_DATA;
12045               last_prefix = last_data_prefix;
12046             }
12047
12048           if (vindex != 0)
12049             {
12050               used_prefixes |= prefix;
12051               all_prefixes[last_prefix] = 0;
12052             }
12053         }
12054       dp = &prefix_table[dp->op[1].bytemode][vindex];
12055       break;
12056
12057     case USE_X86_64_TABLE:
12058       vindex = address_mode == mode_64bit ? 1 : 0;
12059       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12060       break;
12061
12062     case USE_3BYTE_TABLE:
12063       FETCH_DATA (info, codep + 2);
12064       vindex = *codep++;
12065       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12066       end_codep = codep;
12067       modrm.mod = (*codep >> 6) & 3;
12068       modrm.reg = (*codep >> 3) & 7;
12069       modrm.rm = *codep & 7;
12070       break;
12071
12072     case USE_VEX_LEN_TABLE:
12073       if (!need_vex)
12074         abort ();
12075
12076       switch (vex.length)
12077         {
12078         case 128:
12079           vindex = 0;
12080           break;
12081         case 256:
12082           vindex = 1;
12083           break;
12084         default:
12085           abort ();
12086           break;
12087         }
12088
12089       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12090       break;
12091
12092     case USE_EVEX_LEN_TABLE:
12093       if (!vex.evex)
12094         abort ();
12095
12096       switch (vex.length)
12097         {
12098         case 128:
12099           vindex = 0;
12100           break;
12101         case 256:
12102           vindex = 1;
12103           break;
12104         case 512:
12105           vindex = 2;
12106           break;
12107         default:
12108           abort ();
12109           break;
12110         }
12111
12112       dp = &evex_len_table[dp->op[1].bytemode][vindex];
12113       break;
12114
12115     case USE_XOP_8F_TABLE:
12116       FETCH_DATA (info, codep + 3);
12117       rex = ~(*codep >> 5) & 0x7;
12118
12119       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12120       switch ((*codep & 0x1f))
12121         {
12122         default:
12123           dp = &bad_opcode;
12124           return dp;
12125         case 0x8:
12126           vex_table_index = XOP_08;
12127           break;
12128         case 0x9:
12129           vex_table_index = XOP_09;
12130           break;
12131         case 0xa:
12132           vex_table_index = XOP_0A;
12133           break;
12134         }
12135       codep++;
12136       vex.w = *codep & 0x80;
12137       if (vex.w && address_mode == mode_64bit)
12138         rex |= REX_W;
12139
12140       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12141       if (address_mode != mode_64bit)
12142         {
12143           /* In 16/32-bit mode REX_B is silently ignored.  */
12144           rex &= ~REX_B;
12145         }
12146
12147       vex.length = (*codep & 0x4) ? 256 : 128;
12148       switch ((*codep & 0x3))
12149         {
12150         case 0:
12151           break;
12152         case 1:
12153           vex.prefix = DATA_PREFIX_OPCODE;
12154           break;
12155         case 2:
12156           vex.prefix = REPE_PREFIX_OPCODE;
12157           break;
12158         case 3:
12159           vex.prefix = REPNE_PREFIX_OPCODE;
12160           break;
12161         }
12162       need_vex = 1;
12163       need_vex_reg = 1;
12164       codep++;
12165       vindex = *codep++;
12166       dp = &xop_table[vex_table_index][vindex];
12167
12168       end_codep = codep;
12169       FETCH_DATA (info, codep + 1);
12170       modrm.mod = (*codep >> 6) & 3;
12171       modrm.reg = (*codep >> 3) & 7;
12172       modrm.rm = *codep & 7;
12173
12174       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
12175          having to decode the bits for every otherwise valid encoding.  */
12176       if (vex.prefix)
12177         return &bad_opcode;
12178       break;
12179
12180     case USE_VEX_C4_TABLE:
12181       /* VEX prefix.  */
12182       FETCH_DATA (info, codep + 3);
12183       rex = ~(*codep >> 5) & 0x7;
12184       switch ((*codep & 0x1f))
12185         {
12186         default:
12187           dp = &bad_opcode;
12188           return dp;
12189         case 0x1:
12190           vex_table_index = VEX_0F;
12191           break;
12192         case 0x2:
12193           vex_table_index = VEX_0F38;
12194           break;
12195         case 0x3:
12196           vex_table_index = VEX_0F3A;
12197           break;
12198         }
12199       codep++;
12200       vex.w = *codep & 0x80;
12201       if (address_mode == mode_64bit)
12202         {
12203           if (vex.w)
12204             rex |= REX_W;
12205         }
12206       else
12207         {
12208           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12209              is ignored, other REX bits are 0 and the highest bit in
12210              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12211           rex = 0;
12212         }
12213       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12214       vex.length = (*codep & 0x4) ? 256 : 128;
12215       switch ((*codep & 0x3))
12216         {
12217         case 0:
12218           break;
12219         case 1:
12220           vex.prefix = DATA_PREFIX_OPCODE;
12221           break;
12222         case 2:
12223           vex.prefix = REPE_PREFIX_OPCODE;
12224           break;
12225         case 3:
12226           vex.prefix = REPNE_PREFIX_OPCODE;
12227           break;
12228         }
12229       need_vex = 1;
12230       need_vex_reg = 1;
12231       codep++;
12232       vindex = *codep++;
12233       dp = &vex_table[vex_table_index][vindex];
12234       end_codep = codep;
12235       /* There is no MODRM byte for VEX0F 77.  */
12236       if (vex_table_index != VEX_0F || vindex != 0x77)
12237         {
12238           FETCH_DATA (info, codep + 1);
12239           modrm.mod = (*codep >> 6) & 3;
12240           modrm.reg = (*codep >> 3) & 7;
12241           modrm.rm = *codep & 7;
12242         }
12243       break;
12244
12245     case USE_VEX_C5_TABLE:
12246       /* VEX prefix.  */
12247       FETCH_DATA (info, codep + 2);
12248       rex = (*codep & 0x80) ? 0 : REX_R;
12249
12250       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12251          VEX.vvvv is 1.  */
12252       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12253       vex.length = (*codep & 0x4) ? 256 : 128;
12254       switch ((*codep & 0x3))
12255         {
12256         case 0:
12257           break;
12258         case 1:
12259           vex.prefix = DATA_PREFIX_OPCODE;
12260           break;
12261         case 2:
12262           vex.prefix = REPE_PREFIX_OPCODE;
12263           break;
12264         case 3:
12265           vex.prefix = REPNE_PREFIX_OPCODE;
12266           break;
12267         }
12268       need_vex = 1;
12269       need_vex_reg = 1;
12270       codep++;
12271       vindex = *codep++;
12272       dp = &vex_table[dp->op[1].bytemode][vindex];
12273       end_codep = codep;
12274       /* There is no MODRM byte for VEX 77.  */
12275       if (vindex != 0x77)
12276         {
12277           FETCH_DATA (info, codep + 1);
12278           modrm.mod = (*codep >> 6) & 3;
12279           modrm.reg = (*codep >> 3) & 7;
12280           modrm.rm = *codep & 7;
12281         }
12282       break;
12283
12284     case USE_VEX_W_TABLE:
12285       if (!need_vex)
12286         abort ();
12287
12288       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12289       break;
12290
12291     case USE_EVEX_TABLE:
12292       two_source_ops = 0;
12293       /* EVEX prefix.  */
12294       vex.evex = 1;
12295       FETCH_DATA (info, codep + 4);
12296       /* The first byte after 0x62.  */
12297       rex = ~(*codep >> 5) & 0x7;
12298       vex.r = *codep & 0x10;
12299       switch ((*codep & 0xf))
12300         {
12301         default:
12302           return &bad_opcode;
12303         case 0x1:
12304           vex_table_index = EVEX_0F;
12305           break;
12306         case 0x2:
12307           vex_table_index = EVEX_0F38;
12308           break;
12309         case 0x3:
12310           vex_table_index = EVEX_0F3A;
12311           break;
12312         }
12313
12314       /* The second byte after 0x62.  */
12315       codep++;
12316       vex.w = *codep & 0x80;
12317       if (vex.w && address_mode == mode_64bit)
12318         rex |= REX_W;
12319
12320       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12321
12322       /* The U bit.  */
12323       if (!(*codep & 0x4))
12324         return &bad_opcode;
12325
12326       switch ((*codep & 0x3))
12327         {
12328         case 0:
12329           break;
12330         case 1:
12331           vex.prefix = DATA_PREFIX_OPCODE;
12332           break;
12333         case 2:
12334           vex.prefix = REPE_PREFIX_OPCODE;
12335           break;
12336         case 3:
12337           vex.prefix = REPNE_PREFIX_OPCODE;
12338           break;
12339         }
12340
12341       /* The third byte after 0x62.  */
12342       codep++;
12343
12344       /* Remember the static rounding bits.  */
12345       vex.ll = (*codep >> 5) & 3;
12346       vex.b = (*codep & 0x10) != 0;
12347
12348       vex.v = *codep & 0x8;
12349       vex.mask_register_specifier = *codep & 0x7;
12350       vex.zeroing = *codep & 0x80;
12351
12352       if (address_mode != mode_64bit)
12353         {
12354           /* In 16/32-bit mode silently ignore following bits.  */
12355           rex &= ~REX_B;
12356           vex.r = 1;
12357           vex.v = 1;
12358         }
12359
12360       need_vex = 1;
12361       need_vex_reg = 1;
12362       codep++;
12363       vindex = *codep++;
12364       dp = &evex_table[vex_table_index][vindex];
12365       end_codep = codep;
12366       FETCH_DATA (info, codep + 1);
12367       modrm.mod = (*codep >> 6) & 3;
12368       modrm.reg = (*codep >> 3) & 7;
12369       modrm.rm = *codep & 7;
12370
12371       /* Set vector length.  */
12372       if (modrm.mod == 3 && vex.b)
12373         vex.length = 512;
12374       else
12375         {
12376           switch (vex.ll)
12377             {
12378             case 0x0:
12379               vex.length = 128;
12380               break;
12381             case 0x1:
12382               vex.length = 256;
12383               break;
12384             case 0x2:
12385               vex.length = 512;
12386               break;
12387             default:
12388               return &bad_opcode;
12389             }
12390         }
12391       break;
12392
12393     case 0:
12394       dp = &bad_opcode;
12395       break;
12396
12397     default:
12398       abort ();
12399     }
12400
12401   if (dp->name != NULL)
12402     return dp;
12403   else
12404     return get_valid_dis386 (dp, info);
12405 }
12406
12407 static void
12408 get_sib (disassemble_info *info, int sizeflag)
12409 {
12410   /* If modrm.mod == 3, operand must be register.  */
12411   if (need_modrm
12412       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12413       && modrm.mod != 3
12414       && modrm.rm == 4)
12415     {
12416       FETCH_DATA (info, codep + 2);
12417       sib.index = (codep [1] >> 3) & 7;
12418       sib.scale = (codep [1] >> 6) & 3;
12419       sib.base = codep [1] & 7;
12420     }
12421 }
12422
12423 static int
12424 print_insn (bfd_vma pc, disassemble_info *info)
12425 {
12426   const struct dis386 *dp;
12427   int i;
12428   char *op_txt[MAX_OPERANDS];
12429   int needcomma;
12430   int sizeflag, orig_sizeflag;
12431   const char *p;
12432   struct dis_private priv;
12433   int prefix_length;
12434
12435   priv.orig_sizeflag = AFLAG | DFLAG;
12436   if ((info->mach & bfd_mach_i386_i386) != 0)
12437     address_mode = mode_32bit;
12438   else if (info->mach == bfd_mach_i386_i8086)
12439     {
12440       address_mode = mode_16bit;
12441       priv.orig_sizeflag = 0;
12442     }
12443   else
12444     address_mode = mode_64bit;
12445
12446   if (intel_syntax == (char) -1)
12447     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12448
12449   for (p = info->disassembler_options; p != NULL; )
12450     {
12451       if (CONST_STRNEQ (p, "amd64"))
12452         isa64 = amd64;
12453       else if (CONST_STRNEQ (p, "intel64"))
12454         isa64 = intel64;
12455       else if (CONST_STRNEQ (p, "x86-64"))
12456         {
12457           address_mode = mode_64bit;
12458           priv.orig_sizeflag |= AFLAG | DFLAG;
12459         }
12460       else if (CONST_STRNEQ (p, "i386"))
12461         {
12462           address_mode = mode_32bit;
12463           priv.orig_sizeflag |= AFLAG | DFLAG;
12464         }
12465       else if (CONST_STRNEQ (p, "i8086"))
12466         {
12467           address_mode = mode_16bit;
12468           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
12469         }
12470       else if (CONST_STRNEQ (p, "intel"))
12471         {
12472           intel_syntax = 1;
12473           if (CONST_STRNEQ (p + 5, "-mnemonic"))
12474             intel_mnemonic = 1;
12475         }
12476       else if (CONST_STRNEQ (p, "att"))
12477         {
12478           intel_syntax = 0;
12479           if (CONST_STRNEQ (p + 3, "-mnemonic"))
12480             intel_mnemonic = 0;
12481         }
12482       else if (CONST_STRNEQ (p, "addr"))
12483         {
12484           if (address_mode == mode_64bit)
12485             {
12486               if (p[4] == '3' && p[5] == '2')
12487                 priv.orig_sizeflag &= ~AFLAG;
12488               else if (p[4] == '6' && p[5] == '4')
12489                 priv.orig_sizeflag |= AFLAG;
12490             }
12491           else
12492             {
12493               if (p[4] == '1' && p[5] == '6')
12494                 priv.orig_sizeflag &= ~AFLAG;
12495               else if (p[4] == '3' && p[5] == '2')
12496                 priv.orig_sizeflag |= AFLAG;
12497             }
12498         }
12499       else if (CONST_STRNEQ (p, "data"))
12500         {
12501           if (p[4] == '1' && p[5] == '6')
12502             priv.orig_sizeflag &= ~DFLAG;
12503           else if (p[4] == '3' && p[5] == '2')
12504             priv.orig_sizeflag |= DFLAG;
12505         }
12506       else if (CONST_STRNEQ (p, "suffix"))
12507         priv.orig_sizeflag |= SUFFIX_ALWAYS;
12508
12509       p = strchr (p, ',');
12510       if (p != NULL)
12511         p++;
12512     }
12513
12514   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
12515     {
12516       (*info->fprintf_func) (info->stream,
12517                              _("64-bit address is disabled"));
12518       return -1;
12519     }
12520
12521   if (intel_syntax)
12522     {
12523       names64 = intel_names64;
12524       names32 = intel_names32;
12525       names16 = intel_names16;
12526       names8 = intel_names8;
12527       names8rex = intel_names8rex;
12528       names_seg = intel_names_seg;
12529       names_mm = intel_names_mm;
12530       names_bnd = intel_names_bnd;
12531       names_xmm = intel_names_xmm;
12532       names_ymm = intel_names_ymm;
12533       names_zmm = intel_names_zmm;
12534       names_tmm = intel_names_tmm;
12535       index64 = intel_index64;
12536       index32 = intel_index32;
12537       names_mask = intel_names_mask;
12538       index16 = intel_index16;
12539       open_char = '[';
12540       close_char = ']';
12541       separator_char = '+';
12542       scale_char = '*';
12543     }
12544   else
12545     {
12546       names64 = att_names64;
12547       names32 = att_names32;
12548       names16 = att_names16;
12549       names8 = att_names8;
12550       names8rex = att_names8rex;
12551       names_seg = att_names_seg;
12552       names_mm = att_names_mm;
12553       names_bnd = att_names_bnd;
12554       names_xmm = att_names_xmm;
12555       names_ymm = att_names_ymm;
12556       names_zmm = att_names_zmm;
12557       names_tmm = att_names_tmm;
12558       index64 = att_index64;
12559       index32 = att_index32;
12560       names_mask = att_names_mask;
12561       index16 = att_index16;
12562       open_char = '(';
12563       close_char =  ')';
12564       separator_char = ',';
12565       scale_char = ',';
12566     }
12567
12568   /* The output looks better if we put 7 bytes on a line, since that
12569      puts most long word instructions on a single line.  Use 8 bytes
12570      for Intel L1OM.  */
12571   if ((info->mach & bfd_mach_l1om) != 0)
12572     info->bytes_per_line = 8;
12573   else
12574     info->bytes_per_line = 7;
12575
12576   info->private_data = &priv;
12577   priv.max_fetched = priv.the_buffer;
12578   priv.insn_start = pc;
12579
12580   obuf[0] = 0;
12581   for (i = 0; i < MAX_OPERANDS; ++i)
12582     {
12583       op_out[i][0] = 0;
12584       op_index[i] = -1;
12585     }
12586
12587   the_info = info;
12588   start_pc = pc;
12589   start_codep = priv.the_buffer;
12590   codep = priv.the_buffer;
12591
12592   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12593     {
12594       const char *name;
12595
12596       /* Getting here means we tried for data but didn't get it.  That
12597          means we have an incomplete instruction of some sort.  Just
12598          print the first byte as a prefix or a .byte pseudo-op.  */
12599       if (codep > priv.the_buffer)
12600         {
12601           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12602           if (name != NULL)
12603             (*info->fprintf_func) (info->stream, "%s", name);
12604           else
12605             {
12606               /* Just print the first byte as a .byte instruction.  */
12607               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12608                                      (unsigned int) priv.the_buffer[0]);
12609             }
12610
12611           return 1;
12612         }
12613
12614       return -1;
12615     }
12616
12617   obufp = obuf;
12618   sizeflag = priv.orig_sizeflag;
12619
12620   if (!ckprefix () || rex_used)
12621     {
12622       /* Too many prefixes or unused REX prefixes.  */
12623       for (i = 0;
12624            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12625            i++)
12626         (*info->fprintf_func) (info->stream, "%s%s",
12627                                i == 0 ? "" : " ",
12628                                prefix_name (all_prefixes[i], sizeflag));
12629       return i;
12630     }
12631
12632   insn_codep = codep;
12633
12634   FETCH_DATA (info, codep + 1);
12635   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12636
12637   if (((prefixes & PREFIX_FWAIT)
12638        && ((*codep < 0xd8) || (*codep > 0xdf))))
12639     {
12640       /* Handle prefixes before fwait.  */
12641       for (i = 0; i < fwait_prefix && all_prefixes[i];
12642            i++)
12643         (*info->fprintf_func) (info->stream, "%s ",
12644                                prefix_name (all_prefixes[i], sizeflag));
12645       (*info->fprintf_func) (info->stream, "fwait");
12646       return i + 1;
12647     }
12648
12649   if (*codep == 0x0f)
12650     {
12651       unsigned char threebyte;
12652
12653       codep++;
12654       FETCH_DATA (info, codep + 1);
12655       threebyte = *codep;
12656       dp = &dis386_twobyte[threebyte];
12657       need_modrm = twobyte_has_modrm[*codep];
12658       codep++;
12659     }
12660   else
12661     {
12662       dp = &dis386[*codep];
12663       need_modrm = onebyte_has_modrm[*codep];
12664       codep++;
12665     }
12666
12667   /* Save sizeflag for printing the extra prefixes later before updating
12668      it for mnemonic and operand processing.  The prefix names depend
12669      only on the address mode.  */
12670   orig_sizeflag = sizeflag;
12671   if (prefixes & PREFIX_ADDR)
12672     sizeflag ^= AFLAG;
12673   if ((prefixes & PREFIX_DATA))
12674     sizeflag ^= DFLAG;
12675
12676   end_codep = codep;
12677   if (need_modrm)
12678     {
12679       FETCH_DATA (info, codep + 1);
12680       modrm.mod = (*codep >> 6) & 3;
12681       modrm.reg = (*codep >> 3) & 7;
12682       modrm.rm = *codep & 7;
12683     }
12684
12685   need_vex = 0;
12686   need_vex_reg = 0;
12687   memset (&vex, 0, sizeof (vex));
12688
12689   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12690     {
12691       get_sib (info, sizeflag);
12692       dofloat (sizeflag);
12693     }
12694   else
12695     {
12696       dp = get_valid_dis386 (dp, info);
12697       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12698         {
12699           get_sib (info, sizeflag);
12700           for (i = 0; i < MAX_OPERANDS; ++i)
12701             {
12702               obufp = op_out[i];
12703               op_ad = MAX_OPERANDS - 1 - i;
12704               if (dp->op[i].rtn)
12705                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12706               /* For EVEX instruction after the last operand masking
12707                  should be printed.  */
12708               if (i == 0 && vex.evex)
12709                 {
12710                   /* Don't print {%k0}.  */
12711                   if (vex.mask_register_specifier)
12712                     {
12713                       oappend ("{");
12714                       oappend (names_mask[vex.mask_register_specifier]);
12715                       oappend ("}");
12716                     }
12717                   if (vex.zeroing)
12718                     oappend ("{z}");
12719                 }
12720             }
12721         }
12722     }
12723
12724   /* Clear instruction information.  */
12725   if (the_info)
12726     {
12727       the_info->insn_info_valid = 0;
12728       the_info->branch_delay_insns = 0;
12729       the_info->data_size = 0;
12730       the_info->insn_type = dis_noninsn;
12731       the_info->target = 0;
12732       the_info->target2 = 0;
12733     }
12734
12735   /* Reset jump operation indicator.  */
12736   op_is_jump = FALSE;
12737
12738   {
12739     int jump_detection = 0;
12740
12741     /* Extract flags.  */
12742     for (i = 0; i < MAX_OPERANDS; ++i)
12743       {
12744         if ((dp->op[i].rtn == OP_J)
12745             || (dp->op[i].rtn == OP_indirE))
12746           jump_detection |= 1;
12747         else if ((dp->op[i].rtn == BND_Fixup)
12748                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12749           jump_detection |= 2;
12750         else if ((dp->op[i].bytemode == cond_jump_mode)
12751                  || (dp->op[i].bytemode == loop_jcxz_mode))
12752           jump_detection |= 4;
12753       }
12754
12755     /* Determine if this is a jump or branch.  */
12756     if ((jump_detection & 0x3) == 0x3)
12757       {
12758         op_is_jump = TRUE;
12759         if (jump_detection & 0x4)
12760           the_info->insn_type = dis_condbranch;
12761         else
12762           the_info->insn_type =
12763             (dp->name && !strncmp(dp->name, "call", 4))
12764             ? dis_jsr : dis_branch;
12765       }
12766   }
12767
12768   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12769      are all 0s in inverted form.  */
12770   if (need_vex && vex.register_specifier != 0)
12771     {
12772       (*info->fprintf_func) (info->stream, "(bad)");
12773       return end_codep - priv.the_buffer;
12774     }
12775
12776   /* Check if the REX prefix is used.  */
12777   if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
12778     all_prefixes[last_rex_prefix] = 0;
12779
12780   /* Check if the SEG prefix is used.  */
12781   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12782                    | PREFIX_FS | PREFIX_GS)) != 0
12783       && (used_prefixes & active_seg_prefix) != 0)
12784     all_prefixes[last_seg_prefix] = 0;
12785
12786   /* Check if the ADDR prefix is used.  */
12787   if ((prefixes & PREFIX_ADDR) != 0
12788       && (used_prefixes & PREFIX_ADDR) != 0)
12789     all_prefixes[last_addr_prefix] = 0;
12790
12791   /* Check if the DATA prefix is used.  */
12792   if ((prefixes & PREFIX_DATA) != 0
12793       && (used_prefixes & PREFIX_DATA) != 0
12794       && !need_vex)
12795     all_prefixes[last_data_prefix] = 0;
12796
12797   /* Print the extra prefixes.  */
12798   prefix_length = 0;
12799   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12800     if (all_prefixes[i])
12801       {
12802         const char *name;
12803         name = prefix_name (all_prefixes[i], orig_sizeflag);
12804         if (name == NULL)
12805           abort ();
12806         prefix_length += strlen (name) + 1;
12807         (*info->fprintf_func) (info->stream, "%s ", name);
12808       }
12809
12810   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12811      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12812      used by putop and MMX/SSE operand and may be overriden by the
12813      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12814      separately.  */
12815   if (dp->prefix_requirement == PREFIX_OPCODE
12816       && (((need_vex
12817             ? vex.prefix == REPE_PREFIX_OPCODE
12818               || vex.prefix == REPNE_PREFIX_OPCODE
12819             : (prefixes
12820                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12821            && (used_prefixes
12822                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12823           || (((need_vex
12824                 ? vex.prefix == DATA_PREFIX_OPCODE
12825                 : ((prefixes
12826                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12827                    == PREFIX_DATA))
12828                && (used_prefixes & PREFIX_DATA) == 0))
12829           || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
12830     {
12831       (*info->fprintf_func) (info->stream, "(bad)");
12832       return end_codep - priv.the_buffer;
12833     }
12834
12835   /* Check maximum code length.  */
12836   if ((codep - start_codep) > MAX_CODE_LENGTH)
12837     {
12838       (*info->fprintf_func) (info->stream, "(bad)");
12839       return MAX_CODE_LENGTH;
12840     }
12841
12842   obufp = mnemonicendp;
12843   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12844     oappend (" ");
12845   oappend (" ");
12846   (*info->fprintf_func) (info->stream, "%s", obuf);
12847
12848   /* The enter and bound instructions are printed with operands in the same
12849      order as the intel book; everything else is printed in reverse order.  */
12850   if (intel_syntax || two_source_ops)
12851     {
12852       bfd_vma riprel;
12853
12854       for (i = 0; i < MAX_OPERANDS; ++i)
12855         op_txt[i] = op_out[i];
12856
12857       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12858           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12859         {
12860           op_txt[2] = op_out[3];
12861           op_txt[3] = op_out[2];
12862         }
12863
12864       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12865         {
12866           op_ad = op_index[i];
12867           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12868           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12869           riprel = op_riprel[i];
12870           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12871           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12872         }
12873     }
12874   else
12875     {
12876       for (i = 0; i < MAX_OPERANDS; ++i)
12877         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12878     }
12879
12880   needcomma = 0;
12881   for (i = 0; i < MAX_OPERANDS; ++i)
12882     if (*op_txt[i])
12883       {
12884         if (needcomma)
12885           (*info->fprintf_func) (info->stream, ",");
12886         if (op_index[i] != -1 && !op_riprel[i])
12887           {
12888             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12889
12890             if (the_info && op_is_jump)
12891               {
12892                 the_info->insn_info_valid = 1;
12893                 the_info->branch_delay_insns = 0;
12894                 the_info->data_size = 0;
12895                 the_info->target = target;
12896                 the_info->target2 = 0;
12897               }
12898             (*info->print_address_func) (target, info);
12899           }
12900         else
12901           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12902         needcomma = 1;
12903       }
12904
12905   for (i = 0; i < MAX_OPERANDS; i++)
12906     if (op_index[i] != -1 && op_riprel[i])
12907       {
12908         (*info->fprintf_func) (info->stream, "        # ");
12909         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12910                                                 + op_address[op_index[i]]), info);
12911         break;
12912       }
12913   return codep - priv.the_buffer;
12914 }
12915
12916 static const char *float_mem[] = {
12917   /* d8 */
12918   "fadd{s|}",
12919   "fmul{s|}",
12920   "fcom{s|}",
12921   "fcomp{s|}",
12922   "fsub{s|}",
12923   "fsubr{s|}",
12924   "fdiv{s|}",
12925   "fdivr{s|}",
12926   /* d9 */
12927   "fld{s|}",
12928   "(bad)",
12929   "fst{s|}",
12930   "fstp{s|}",
12931   "fldenv{C|C}",
12932   "fldcw",
12933   "fNstenv{C|C}",
12934   "fNstcw",
12935   /* da */
12936   "fiadd{l|}",
12937   "fimul{l|}",
12938   "ficom{l|}",
12939   "ficomp{l|}",
12940   "fisub{l|}",
12941   "fisubr{l|}",
12942   "fidiv{l|}",
12943   "fidivr{l|}",
12944   /* db */
12945   "fild{l|}",
12946   "fisttp{l|}",
12947   "fist{l|}",
12948   "fistp{l|}",
12949   "(bad)",
12950   "fld{t|}",
12951   "(bad)",
12952   "fstp{t|}",
12953   /* dc */
12954   "fadd{l|}",
12955   "fmul{l|}",
12956   "fcom{l|}",
12957   "fcomp{l|}",
12958   "fsub{l|}",
12959   "fsubr{l|}",
12960   "fdiv{l|}",
12961   "fdivr{l|}",
12962   /* dd */
12963   "fld{l|}",
12964   "fisttp{ll|}",
12965   "fst{l||}",
12966   "fstp{l|}",
12967   "frstor{C|C}",
12968   "(bad)",
12969   "fNsave{C|C}",
12970   "fNstsw",
12971   /* de */
12972   "fiadd{s|}",
12973   "fimul{s|}",
12974   "ficom{s|}",
12975   "ficomp{s|}",
12976   "fisub{s|}",
12977   "fisubr{s|}",
12978   "fidiv{s|}",
12979   "fidivr{s|}",
12980   /* df */
12981   "fild{s|}",
12982   "fisttp{s|}",
12983   "fist{s|}",
12984   "fistp{s|}",
12985   "fbld",
12986   "fild{ll|}",
12987   "fbstp",
12988   "fistp{ll|}",
12989 };
12990
12991 static const unsigned char float_mem_mode[] = {
12992   /* d8 */
12993   d_mode,
12994   d_mode,
12995   d_mode,
12996   d_mode,
12997   d_mode,
12998   d_mode,
12999   d_mode,
13000   d_mode,
13001   /* d9 */
13002   d_mode,
13003   0,
13004   d_mode,
13005   d_mode,
13006   0,
13007   w_mode,
13008   0,
13009   w_mode,
13010   /* da */
13011   d_mode,
13012   d_mode,
13013   d_mode,
13014   d_mode,
13015   d_mode,
13016   d_mode,
13017   d_mode,
13018   d_mode,
13019   /* db */
13020   d_mode,
13021   d_mode,
13022   d_mode,
13023   d_mode,
13024   0,
13025   t_mode,
13026   0,
13027   t_mode,
13028   /* dc */
13029   q_mode,
13030   q_mode,
13031   q_mode,
13032   q_mode,
13033   q_mode,
13034   q_mode,
13035   q_mode,
13036   q_mode,
13037   /* dd */
13038   q_mode,
13039   q_mode,
13040   q_mode,
13041   q_mode,
13042   0,
13043   0,
13044   0,
13045   w_mode,
13046   /* de */
13047   w_mode,
13048   w_mode,
13049   w_mode,
13050   w_mode,
13051   w_mode,
13052   w_mode,
13053   w_mode,
13054   w_mode,
13055   /* df */
13056   w_mode,
13057   w_mode,
13058   w_mode,
13059   w_mode,
13060   t_mode,
13061   q_mode,
13062   t_mode,
13063   q_mode
13064 };
13065
13066 #define ST { OP_ST, 0 }
13067 #define STi { OP_STi, 0 }
13068
13069 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13070 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13071 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13072 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13073 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13074 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13075 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13076 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13077 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13078
13079 static const struct dis386 float_reg[][8] = {
13080   /* d8 */
13081   {
13082     { "fadd",   { ST, STi }, 0 },
13083     { "fmul",   { ST, STi }, 0 },
13084     { "fcom",   { STi }, 0 },
13085     { "fcomp",  { STi }, 0 },
13086     { "fsub",   { ST, STi }, 0 },
13087     { "fsubr",  { ST, STi }, 0 },
13088     { "fdiv",   { ST, STi }, 0 },
13089     { "fdivr",  { ST, STi }, 0 },
13090   },
13091   /* d9 */
13092   {
13093     { "fld",    { STi }, 0 },
13094     { "fxch",   { STi }, 0 },
13095     { FGRPd9_2 },
13096     { Bad_Opcode },
13097     { FGRPd9_4 },
13098     { FGRPd9_5 },
13099     { FGRPd9_6 },
13100     { FGRPd9_7 },
13101   },
13102   /* da */
13103   {
13104     { "fcmovb", { ST, STi }, 0 },
13105     { "fcmove", { ST, STi }, 0 },
13106     { "fcmovbe",{ ST, STi }, 0 },
13107     { "fcmovu", { ST, STi }, 0 },
13108     { Bad_Opcode },
13109     { FGRPda_5 },
13110     { Bad_Opcode },
13111     { Bad_Opcode },
13112   },
13113   /* db */
13114   {
13115     { "fcmovnb",{ ST, STi }, 0 },
13116     { "fcmovne",{ ST, STi }, 0 },
13117     { "fcmovnbe",{ ST, STi }, 0 },
13118     { "fcmovnu",{ ST, STi }, 0 },
13119     { FGRPdb_4 },
13120     { "fucomi", { ST, STi }, 0 },
13121     { "fcomi",  { ST, STi }, 0 },
13122     { Bad_Opcode },
13123   },
13124   /* dc */
13125   {
13126     { "fadd",   { STi, ST }, 0 },
13127     { "fmul",   { STi, ST }, 0 },
13128     { Bad_Opcode },
13129     { Bad_Opcode },
13130     { "fsub{!M|r}",     { STi, ST }, 0 },
13131     { "fsub{M|}",       { STi, ST }, 0 },
13132     { "fdiv{!M|r}",     { STi, ST }, 0 },
13133     { "fdiv{M|}",       { STi, ST }, 0 },
13134   },
13135   /* dd */
13136   {
13137     { "ffree",  { STi }, 0 },
13138     { Bad_Opcode },
13139     { "fst",    { STi }, 0 },
13140     { "fstp",   { STi }, 0 },
13141     { "fucom",  { STi }, 0 },
13142     { "fucomp", { STi }, 0 },
13143     { Bad_Opcode },
13144     { Bad_Opcode },
13145   },
13146   /* de */
13147   {
13148     { "faddp",  { STi, ST }, 0 },
13149     { "fmulp",  { STi, ST }, 0 },
13150     { Bad_Opcode },
13151     { FGRPde_3 },
13152     { "fsub{!M|r}p",    { STi, ST }, 0 },
13153     { "fsub{M|}p",      { STi, ST }, 0 },
13154     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13155     { "fdiv{M|}p",      { STi, ST }, 0 },
13156   },
13157   /* df */
13158   {
13159     { "ffreep", { STi }, 0 },
13160     { Bad_Opcode },
13161     { Bad_Opcode },
13162     { Bad_Opcode },
13163     { FGRPdf_4 },
13164     { "fucomip", { ST, STi }, 0 },
13165     { "fcomip", { ST, STi }, 0 },
13166     { Bad_Opcode },
13167   },
13168 };
13169
13170 static char *fgrps[][8] = {
13171   /* Bad opcode 0 */
13172   {
13173     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13174   },
13175
13176   /* d9_2  1 */
13177   {
13178     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13179   },
13180
13181   /* d9_4  2 */
13182   {
13183     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13184   },
13185
13186   /* d9_5  3 */
13187   {
13188     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13189   },
13190
13191   /* d9_6  4 */
13192   {
13193     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13194   },
13195
13196   /* d9_7  5 */
13197   {
13198     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13199   },
13200
13201   /* da_5  6 */
13202   {
13203     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13204   },
13205
13206   /* db_4  7 */
13207   {
13208     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13209     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13210   },
13211
13212   /* de_3  8 */
13213   {
13214     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13215   },
13216
13217   /* df_4  9 */
13218   {
13219     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13220   },
13221 };
13222
13223 static void
13224 swap_operand (void)
13225 {
13226   mnemonicendp[0] = '.';
13227   mnemonicendp[1] = 's';
13228   mnemonicendp += 2;
13229 }
13230
13231 static void
13232 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13233                int sizeflag ATTRIBUTE_UNUSED)
13234 {
13235   /* Skip mod/rm byte.  */
13236   MODRM_CHECK;
13237   codep++;
13238 }
13239
13240 static void
13241 dofloat (int sizeflag)
13242 {
13243   const struct dis386 *dp;
13244   unsigned char floatop;
13245
13246   floatop = codep[-1];
13247
13248   if (modrm.mod != 3)
13249     {
13250       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13251
13252       putop (float_mem[fp_indx], sizeflag);
13253       obufp = op_out[0];
13254       op_ad = 2;
13255       OP_E (float_mem_mode[fp_indx], sizeflag);
13256       return;
13257     }
13258   /* Skip mod/rm byte.  */
13259   MODRM_CHECK;
13260   codep++;
13261
13262   dp = &float_reg[floatop - 0xd8][modrm.reg];
13263   if (dp->name == NULL)
13264     {
13265       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13266
13267       /* Instruction fnstsw is only one with strange arg.  */
13268       if (floatop == 0xdf && codep[-1] == 0xe0)
13269         strcpy (op_out[0], names16[0]);
13270     }
13271   else
13272     {
13273       putop (dp->name, sizeflag);
13274
13275       obufp = op_out[0];
13276       op_ad = 2;
13277       if (dp->op[0].rtn)
13278         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13279
13280       obufp = op_out[1];
13281       op_ad = 1;
13282       if (dp->op[1].rtn)
13283         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13284     }
13285 }
13286
13287 /* Like oappend (below), but S is a string starting with '%'.
13288    In Intel syntax, the '%' is elided.  */
13289 static void
13290 oappend_maybe_intel (const char *s)
13291 {
13292   oappend (s + intel_syntax);
13293 }
13294
13295 static void
13296 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13297 {
13298   oappend_maybe_intel ("%st");
13299 }
13300
13301 static void
13302 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13303 {
13304   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13305   oappend_maybe_intel (scratchbuf);
13306 }
13307
13308 /* Capital letters in template are macros.  */
13309 static int
13310 putop (const char *in_template, int sizeflag)
13311 {
13312   const char *p;
13313   int alt = 0;
13314   int cond = 1;
13315   unsigned int l = 0, len = 0;
13316   char last[4];
13317
13318   for (p = in_template; *p; p++)
13319     {
13320       if (len > l)
13321         {
13322           if (l >= sizeof (last) || !ISUPPER (*p))
13323             abort ();
13324           last[l++] = *p;
13325           continue;
13326         }
13327       switch (*p)
13328         {
13329         default:
13330           *obufp++ = *p;
13331           break;
13332         case '%':
13333           len++;
13334           break;
13335         case '!':
13336           cond = 0;
13337           break;
13338         case '{':
13339           if (intel_syntax)
13340             {
13341               while (*++p != '|')
13342                 if (*p == '}' || *p == '\0')
13343                   abort ();
13344               alt = 1;
13345             }
13346           break;
13347         case '|':
13348           while (*++p != '}')
13349             {
13350               if (*p == '\0')
13351                 abort ();
13352             }
13353           break;
13354         case '}':
13355           alt = 0;
13356           break;
13357         case 'A':
13358           if (intel_syntax)
13359             break;
13360           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13361             *obufp++ = 'b';
13362           break;
13363         case 'B':
13364           if (l == 0)
13365             {
13366             case_B:
13367               if (intel_syntax)
13368                 break;
13369               if (sizeflag & SUFFIX_ALWAYS)
13370                 *obufp++ = 'b';
13371             }
13372           else if (l == 1 && last[0] == 'L')
13373             {
13374               if (address_mode == mode_64bit
13375                   && !(prefixes & PREFIX_ADDR))
13376                 {
13377                   *obufp++ = 'a';
13378                   *obufp++ = 'b';
13379                   *obufp++ = 's';
13380                 }
13381
13382               goto case_B;
13383             }
13384           else
13385             abort ();
13386           break;
13387         case 'C':
13388           if (intel_syntax && !alt)
13389             break;
13390           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13391             {
13392               if (sizeflag & DFLAG)
13393                 *obufp++ = intel_syntax ? 'd' : 'l';
13394               else
13395                 *obufp++ = intel_syntax ? 'w' : 's';
13396               used_prefixes |= (prefixes & PREFIX_DATA);
13397             }
13398           break;
13399         case 'D':
13400           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13401             break;
13402           USED_REX (REX_W);
13403           if (modrm.mod == 3)
13404             {
13405               if (rex & REX_W)
13406                 *obufp++ = 'q';
13407               else
13408                 {
13409                   if (sizeflag & DFLAG)
13410                     *obufp++ = intel_syntax ? 'd' : 'l';
13411                   else
13412                     *obufp++ = 'w';
13413                   used_prefixes |= (prefixes & PREFIX_DATA);
13414                 }
13415             }
13416           else
13417             *obufp++ = 'w';
13418           break;
13419         case 'E':               /* For jcxz/jecxz */
13420           if (address_mode == mode_64bit)
13421             {
13422               if (sizeflag & AFLAG)
13423                 *obufp++ = 'r';
13424               else
13425                 *obufp++ = 'e';
13426             }
13427           else
13428             if (sizeflag & AFLAG)
13429               *obufp++ = 'e';
13430           used_prefixes |= (prefixes & PREFIX_ADDR);
13431           break;
13432         case 'F':
13433           if (intel_syntax)
13434             break;
13435           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13436             {
13437               if (sizeflag & AFLAG)
13438                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13439               else
13440                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13441               used_prefixes |= (prefixes & PREFIX_ADDR);
13442             }
13443           break;
13444         case 'G':
13445           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13446             break;
13447           if ((rex & REX_W) || (sizeflag & DFLAG))
13448             *obufp++ = 'l';
13449           else
13450             *obufp++ = 'w';
13451           if (!(rex & REX_W))
13452             used_prefixes |= (prefixes & PREFIX_DATA);
13453           break;
13454         case 'H':
13455           if (intel_syntax)
13456             break;
13457           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13458               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13459             {
13460               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13461               *obufp++ = ',';
13462               *obufp++ = 'p';
13463               if (prefixes & PREFIX_DS)
13464                 *obufp++ = 't';
13465               else
13466                 *obufp++ = 'n';
13467             }
13468           break;
13469         case 'K':
13470           USED_REX (REX_W);
13471           if (rex & REX_W)
13472             *obufp++ = 'q';
13473           else
13474             *obufp++ = 'd';
13475           break;
13476         case 'Z':
13477           if (l != 0)
13478             {
13479               if (l != 1 || last[0] != 'X')
13480                 abort ();
13481               if (!need_vex || !vex.evex)
13482                 abort ();
13483               if (intel_syntax
13484                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13485                 break;
13486               switch (vex.length)
13487                 {
13488                 case 128:
13489                   *obufp++ = 'x';
13490                   break;
13491                 case 256:
13492                   *obufp++ = 'y';
13493                   break;
13494                 case 512:
13495                   *obufp++ = 'z';
13496                   break;
13497                 default:
13498                   abort ();
13499                 }
13500               break;
13501             }
13502           if (intel_syntax)
13503             break;
13504           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13505             {
13506               *obufp++ = 'q';
13507               break;
13508             }
13509           /* Fall through.  */
13510           goto case_L;
13511         case 'L':
13512           if (l != 0)
13513             abort ();
13514         case_L:
13515           if (intel_syntax)
13516             break;
13517           if (sizeflag & SUFFIX_ALWAYS)
13518             *obufp++ = 'l';
13519           break;
13520         case 'M':
13521           if (intel_mnemonic != cond)
13522             *obufp++ = 'r';
13523           break;
13524         case 'N':
13525           if ((prefixes & PREFIX_FWAIT) == 0)
13526             *obufp++ = 'n';
13527           else
13528             used_prefixes |= PREFIX_FWAIT;
13529           break;
13530         case 'O':
13531           USED_REX (REX_W);
13532           if (rex & REX_W)
13533             *obufp++ = 'o';
13534           else if (intel_syntax && (sizeflag & DFLAG))
13535             *obufp++ = 'q';
13536           else
13537             *obufp++ = 'd';
13538           if (!(rex & REX_W))
13539             used_prefixes |= (prefixes & PREFIX_DATA);
13540           break;
13541         case '&':
13542           if (!intel_syntax
13543               && address_mode == mode_64bit
13544               && isa64 == intel64)
13545             {
13546               *obufp++ = 'q';
13547               break;
13548             }
13549           /* Fall through.  */
13550         case 'T':
13551           if (!intel_syntax
13552               && address_mode == mode_64bit
13553               && ((sizeflag & DFLAG) || (rex & REX_W)))
13554             {
13555               *obufp++ = 'q';
13556               break;
13557             }
13558           /* Fall through.  */
13559           goto case_P;
13560         case 'P':
13561           if (l == 0)
13562             {
13563             case_P:
13564               if (intel_syntax)
13565                 {
13566                   if ((rex & REX_W) == 0
13567                       && (prefixes & PREFIX_DATA))
13568                     {
13569                       if ((sizeflag & DFLAG) == 0)
13570                         *obufp++ = 'w';
13571                       used_prefixes |= (prefixes & PREFIX_DATA);
13572                     }
13573                   break;
13574                 }
13575               if ((prefixes & PREFIX_DATA)
13576                   || (rex & REX_W)
13577                   || (sizeflag & SUFFIX_ALWAYS))
13578                 {
13579                   USED_REX (REX_W);
13580                   if (rex & REX_W)
13581                     *obufp++ = 'q';
13582                   else
13583                     {
13584                       if (sizeflag & DFLAG)
13585                         *obufp++ = 'l';
13586                       else
13587                         *obufp++ = 'w';
13588                       used_prefixes |= (prefixes & PREFIX_DATA);
13589                     }
13590                 }
13591             }
13592           else if (l == 1 && last[0] == 'L')
13593             {
13594               if ((prefixes & PREFIX_DATA)
13595                   || (rex & REX_W)
13596                   || (sizeflag & SUFFIX_ALWAYS))
13597                 {
13598                   USED_REX (REX_W);
13599                   if (rex & REX_W)
13600                     *obufp++ = 'q';
13601                   else
13602                     {
13603                       if (sizeflag & DFLAG)
13604                         *obufp++ = intel_syntax ? 'd' : 'l';
13605                       else
13606                         *obufp++ = 'w';
13607                       used_prefixes |= (prefixes & PREFIX_DATA);
13608                     }
13609                 }
13610             }
13611           else
13612             abort ();
13613           break;
13614         case 'U':
13615           if (intel_syntax)
13616             break;
13617           if (address_mode == mode_64bit
13618               && ((sizeflag & DFLAG) || (rex & REX_W)))
13619             {
13620               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13621                 *obufp++ = 'q';
13622               break;
13623             }
13624           /* Fall through.  */
13625           goto case_Q;
13626         case 'Q':
13627           if (l == 0)
13628             {
13629             case_Q:
13630               if (intel_syntax && !alt)
13631                 break;
13632               USED_REX (REX_W);
13633               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13634                 {
13635                   if (rex & REX_W)
13636                     *obufp++ = 'q';
13637                   else
13638                     {
13639                       if (sizeflag & DFLAG)
13640                         *obufp++ = intel_syntax ? 'd' : 'l';
13641                       else
13642                         *obufp++ = 'w';
13643                       used_prefixes |= (prefixes & PREFIX_DATA);
13644                     }
13645                 }
13646             }
13647           else if (l == 1 && last[0] == 'L')
13648             {
13649               if ((intel_syntax && need_modrm)
13650                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13651                 break;
13652               if ((rex & REX_W))
13653                 {
13654                   USED_REX (REX_W);
13655                   *obufp++ = 'q';
13656                 }
13657               else if((address_mode == mode_64bit && need_modrm)
13658                       || (sizeflag & SUFFIX_ALWAYS))
13659                 *obufp++ = intel_syntax? 'd' : 'l';
13660             }
13661           else
13662             abort ();
13663           break;
13664         case 'R':
13665           USED_REX (REX_W);
13666           if (rex & REX_W)
13667             *obufp++ = 'q';
13668           else if (sizeflag & DFLAG)
13669             {
13670               if (intel_syntax)
13671                   *obufp++ = 'd';
13672               else
13673                   *obufp++ = 'l';
13674             }
13675           else
13676             *obufp++ = 'w';
13677           if (intel_syntax && !p[1]
13678               && ((rex & REX_W) || (sizeflag & DFLAG)))
13679             *obufp++ = 'e';
13680           if (!(rex & REX_W))
13681             used_prefixes |= (prefixes & PREFIX_DATA);
13682           break;
13683         case 'V':
13684           if (l == 0)
13685             {
13686               if (intel_syntax)
13687                 break;
13688               if (address_mode == mode_64bit
13689                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13690                 {
13691                   if (sizeflag & SUFFIX_ALWAYS)
13692                     *obufp++ = 'q';
13693                   break;
13694                 }
13695             }
13696           else if (l == 1 && last[0] == 'L')
13697             {
13698               if (rex & REX_W)
13699                 {
13700                   *obufp++ = 'a';
13701                   *obufp++ = 'b';
13702                   *obufp++ = 's';
13703                 }
13704             }
13705           else
13706             abort ();
13707           /* Fall through.  */
13708           goto case_S;
13709         case 'S':
13710           if (l == 0)
13711             {
13712             case_S:
13713               if (intel_syntax)
13714                 break;
13715               if (sizeflag & SUFFIX_ALWAYS)
13716                 {
13717                   if (rex & REX_W)
13718                     *obufp++ = 'q';
13719                   else
13720                     {
13721                       if (sizeflag & DFLAG)
13722                         *obufp++ = 'l';
13723                       else
13724                         *obufp++ = 'w';
13725                       used_prefixes |= (prefixes & PREFIX_DATA);
13726                     }
13727                 }
13728             }
13729           else if (l == 1 && last[0] == 'L')
13730             {
13731               if (address_mode == mode_64bit
13732                   && !(prefixes & PREFIX_ADDR))
13733                 {
13734                   *obufp++ = 'a';
13735                   *obufp++ = 'b';
13736                   *obufp++ = 's';
13737                 }
13738
13739               goto case_S;
13740             }
13741           else
13742             abort ();
13743           break;
13744         case 'X':
13745           if (l != 0)
13746             abort ();
13747           if (need_vex
13748               ? vex.prefix == DATA_PREFIX_OPCODE
13749               : prefixes & PREFIX_DATA)
13750             {
13751               *obufp++ = 'd';
13752               used_prefixes |= PREFIX_DATA;
13753             }
13754           else
13755             *obufp++ = 's';
13756           break;
13757         case 'Y':
13758           if (l == 1 && last[0] == 'X')
13759             {
13760               if (!need_vex)
13761                 abort ();
13762               if (intel_syntax
13763                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13764                 break;
13765               switch (vex.length)
13766                 {
13767                 case 128:
13768                   *obufp++ = 'x';
13769                   break;
13770                 case 256:
13771                   *obufp++ = 'y';
13772                   break;
13773                 case 512:
13774                   if (!vex.evex)
13775                 default:
13776                     abort ();
13777                 }
13778             }
13779           else
13780             abort ();
13781           break;
13782         case 'W':
13783           if (l == 0)
13784             {
13785               /* operand size flag for cwtl, cbtw */
13786               USED_REX (REX_W);
13787               if (rex & REX_W)
13788                 {
13789                   if (intel_syntax)
13790                     *obufp++ = 'd';
13791                   else
13792                     *obufp++ = 'l';
13793                 }
13794               else if (sizeflag & DFLAG)
13795                 *obufp++ = 'w';
13796               else
13797                 *obufp++ = 'b';
13798               if (!(rex & REX_W))
13799                 used_prefixes |= (prefixes & PREFIX_DATA);
13800             }
13801           else if (l == 1)
13802             {
13803               if (!need_vex)
13804                 abort ();
13805               if (last[0] == 'X')
13806                 *obufp++ = vex.w ? 'd': 's';
13807               else if (last[0] == 'L')
13808                 *obufp++ = vex.w ? 'q': 'd';
13809               else if (last[0] == 'B')
13810                 *obufp++ = vex.w ? 'w': 'b';
13811               else
13812                 abort ();
13813             }
13814           else
13815             abort ();
13816           break;
13817         case '^':
13818           if (intel_syntax)
13819             break;
13820           if (isa64 == intel64 && (rex & REX_W))
13821             {
13822               USED_REX (REX_W);
13823               *obufp++ = 'q';
13824               break;
13825             }
13826           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13827             {
13828               if (sizeflag & DFLAG)
13829                 *obufp++ = 'l';
13830               else
13831                 *obufp++ = 'w';
13832               used_prefixes |= (prefixes & PREFIX_DATA);
13833             }
13834           break;
13835         case '@':
13836           if (intel_syntax)
13837             break;
13838           if (address_mode == mode_64bit
13839               && (isa64 == intel64
13840                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13841               *obufp++ = 'q';
13842           else if ((prefixes & PREFIX_DATA))
13843             {
13844               if (!(sizeflag & DFLAG))
13845                 *obufp++ = 'w';
13846               used_prefixes |= (prefixes & PREFIX_DATA);
13847             }
13848           break;
13849         }
13850
13851       if (len == l)
13852         len = l = 0;
13853     }
13854   *obufp = 0;
13855   mnemonicendp = obufp;
13856   return 0;
13857 }
13858
13859 static void
13860 oappend (const char *s)
13861 {
13862   obufp = stpcpy (obufp, s);
13863 }
13864
13865 static void
13866 append_seg (void)
13867 {
13868   /* Only print the active segment register.  */
13869   if (!active_seg_prefix)
13870     return;
13871
13872   used_prefixes |= active_seg_prefix;
13873   switch (active_seg_prefix)
13874     {
13875     case PREFIX_CS:
13876       oappend_maybe_intel ("%cs:");
13877       break;
13878     case PREFIX_DS:
13879       oappend_maybe_intel ("%ds:");
13880       break;
13881     case PREFIX_SS:
13882       oappend_maybe_intel ("%ss:");
13883       break;
13884     case PREFIX_ES:
13885       oappend_maybe_intel ("%es:");
13886       break;
13887     case PREFIX_FS:
13888       oappend_maybe_intel ("%fs:");
13889       break;
13890     case PREFIX_GS:
13891       oappend_maybe_intel ("%gs:");
13892       break;
13893     default:
13894       break;
13895     }
13896 }
13897
13898 static void
13899 OP_indirE (int bytemode, int sizeflag)
13900 {
13901   if (!intel_syntax)
13902     oappend ("*");
13903   OP_E (bytemode, sizeflag);
13904 }
13905
13906 static void
13907 print_operand_value (char *buf, int hex, bfd_vma disp)
13908 {
13909   if (address_mode == mode_64bit)
13910     {
13911       if (hex)
13912         {
13913           char tmp[30];
13914           int i;
13915           buf[0] = '0';
13916           buf[1] = 'x';
13917           sprintf_vma (tmp, disp);
13918           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13919           strcpy (buf + 2, tmp + i);
13920         }
13921       else
13922         {
13923           bfd_signed_vma v = disp;
13924           char tmp[30];
13925           int i;
13926           if (v < 0)
13927             {
13928               *(buf++) = '-';
13929               v = -disp;
13930               /* Check for possible overflow on 0x8000000000000000.  */
13931               if (v < 0)
13932                 {
13933                   strcpy (buf, "9223372036854775808");
13934                   return;
13935                 }
13936             }
13937           if (!v)
13938             {
13939               strcpy (buf, "0");
13940               return;
13941             }
13942
13943           i = 0;
13944           tmp[29] = 0;
13945           while (v)
13946             {
13947               tmp[28 - i] = (v % 10) + '0';
13948               v /= 10;
13949               i++;
13950             }
13951           strcpy (buf, tmp + 29 - i);
13952         }
13953     }
13954   else
13955     {
13956       if (hex)
13957         sprintf (buf, "0x%x", (unsigned int) disp);
13958       else
13959         sprintf (buf, "%d", (int) disp);
13960     }
13961 }
13962
13963 /* Put DISP in BUF as signed hex number.  */
13964
13965 static void
13966 print_displacement (char *buf, bfd_vma disp)
13967 {
13968   bfd_signed_vma val = disp;
13969   char tmp[30];
13970   int i, j = 0;
13971
13972   if (val < 0)
13973     {
13974       buf[j++] = '-';
13975       val = -disp;
13976
13977       /* Check for possible overflow.  */
13978       if (val < 0)
13979         {
13980           switch (address_mode)
13981             {
13982             case mode_64bit:
13983               strcpy (buf + j, "0x8000000000000000");
13984               break;
13985             case mode_32bit:
13986               strcpy (buf + j, "0x80000000");
13987               break;
13988             case mode_16bit:
13989               strcpy (buf + j, "0x8000");
13990               break;
13991             }
13992           return;
13993         }
13994     }
13995
13996   buf[j++] = '0';
13997   buf[j++] = 'x';
13998
13999   sprintf_vma (tmp, (bfd_vma) val);
14000   for (i = 0; tmp[i] == '0'; i++)
14001     continue;
14002   if (tmp[i] == '\0')
14003     i--;
14004   strcpy (buf + j, tmp + i);
14005 }
14006
14007 static void
14008 intel_operand_size (int bytemode, int sizeflag)
14009 {
14010   if (vex.evex
14011       && vex.b
14012       && (bytemode == x_mode
14013           || bytemode == evex_half_bcst_xmmq_mode))
14014     {
14015       if (vex.w)
14016         oappend ("QWORD PTR ");
14017       else
14018         oappend ("DWORD PTR ");
14019       return;
14020     }
14021   switch (bytemode)
14022     {
14023     case b_mode:
14024     case b_swap_mode:
14025     case dqb_mode:
14026     case db_mode:
14027       oappend ("BYTE PTR ");
14028       break;
14029     case w_mode:
14030     case dw_mode:
14031     case dqw_mode:
14032       oappend ("WORD PTR ");
14033       break;
14034     case indir_v_mode:
14035       if (address_mode == mode_64bit && isa64 == intel64)
14036         {
14037           oappend ("QWORD PTR ");
14038           break;
14039         }
14040       /* Fall through.  */
14041     case stack_v_mode:
14042       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14043         {
14044           oappend ("QWORD PTR ");
14045           break;
14046         }
14047       /* Fall through.  */
14048     case v_mode:
14049     case v_swap_mode:
14050     case dq_mode:
14051       USED_REX (REX_W);
14052       if (rex & REX_W)
14053         oappend ("QWORD PTR ");
14054       else
14055         {
14056           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14057             oappend ("DWORD PTR ");
14058           else
14059             oappend ("WORD PTR ");
14060           used_prefixes |= (prefixes & PREFIX_DATA);
14061         }
14062       break;
14063     case z_mode:
14064       if ((rex & REX_W) || (sizeflag & DFLAG))
14065         *obufp++ = 'D';
14066       oappend ("WORD PTR ");
14067       if (!(rex & REX_W))
14068         used_prefixes |= (prefixes & PREFIX_DATA);
14069       break;
14070     case a_mode:
14071       if (sizeflag & DFLAG)
14072         oappend ("QWORD PTR ");
14073       else
14074         oappend ("DWORD PTR ");
14075       used_prefixes |= (prefixes & PREFIX_DATA);
14076       break;
14077     case movsxd_mode:
14078       if (!(sizeflag & DFLAG) && isa64 == intel64)
14079         oappend ("WORD PTR ");
14080       else
14081         oappend ("DWORD PTR ");
14082       used_prefixes |= (prefixes & PREFIX_DATA);
14083       break;
14084     case d_mode:
14085     case d_scalar_swap_mode:
14086     case d_swap_mode:
14087     case dqd_mode:
14088       oappend ("DWORD PTR ");
14089       break;
14090     case q_mode:
14091     case q_scalar_swap_mode:
14092     case q_swap_mode:
14093       oappend ("QWORD PTR ");
14094       break;
14095     case m_mode:
14096       if (address_mode == mode_64bit)
14097         oappend ("QWORD PTR ");
14098       else
14099         oappend ("DWORD PTR ");
14100       break;
14101     case f_mode:
14102       if (sizeflag & DFLAG)
14103         oappend ("FWORD PTR ");
14104       else
14105         oappend ("DWORD PTR ");
14106       used_prefixes |= (prefixes & PREFIX_DATA);
14107       break;
14108     case t_mode:
14109       oappend ("TBYTE PTR ");
14110       break;
14111     case x_mode:
14112     case x_swap_mode:
14113     case evex_x_gscat_mode:
14114     case evex_x_nobcst_mode:
14115     case b_scalar_mode:
14116     case w_scalar_mode:
14117       if (need_vex)
14118         {
14119           switch (vex.length)
14120             {
14121             case 128:
14122               oappend ("XMMWORD PTR ");
14123               break;
14124             case 256:
14125               oappend ("YMMWORD PTR ");
14126               break;
14127             case 512:
14128               oappend ("ZMMWORD PTR ");
14129               break;
14130             default:
14131               abort ();
14132             }
14133         }
14134       else
14135         oappend ("XMMWORD PTR ");
14136       break;
14137     case xmm_mode:
14138       oappend ("XMMWORD PTR ");
14139       break;
14140     case ymm_mode:
14141       oappend ("YMMWORD PTR ");
14142       break;
14143     case xmmq_mode:
14144     case evex_half_bcst_xmmq_mode:
14145       if (!need_vex)
14146         abort ();
14147
14148       switch (vex.length)
14149         {
14150         case 128:
14151           oappend ("QWORD PTR ");
14152           break;
14153         case 256:
14154           oappend ("XMMWORD PTR ");
14155           break;
14156         case 512:
14157           oappend ("YMMWORD PTR ");
14158           break;
14159         default:
14160           abort ();
14161         }
14162       break;
14163     case xmm_mb_mode:
14164       if (!need_vex)
14165         abort ();
14166
14167       switch (vex.length)
14168         {
14169         case 128:
14170         case 256:
14171         case 512:
14172           oappend ("BYTE PTR ");
14173           break;
14174         default:
14175           abort ();
14176         }
14177       break;
14178     case xmm_mw_mode:
14179       if (!need_vex)
14180         abort ();
14181
14182       switch (vex.length)
14183         {
14184         case 128:
14185         case 256:
14186         case 512:
14187           oappend ("WORD PTR ");
14188           break;
14189         default:
14190           abort ();
14191         }
14192       break;
14193     case xmm_md_mode:
14194       if (!need_vex)
14195         abort ();
14196
14197       switch (vex.length)
14198         {
14199         case 128:
14200         case 256:
14201         case 512:
14202           oappend ("DWORD PTR ");
14203           break;
14204         default:
14205           abort ();
14206         }
14207       break;
14208     case xmm_mq_mode:
14209       if (!need_vex)
14210         abort ();
14211
14212       switch (vex.length)
14213         {
14214         case 128:
14215         case 256:
14216         case 512:
14217           oappend ("QWORD PTR ");
14218           break;
14219         default:
14220           abort ();
14221         }
14222       break;
14223     case xmmdw_mode:
14224       if (!need_vex)
14225         abort ();
14226
14227       switch (vex.length)
14228         {
14229         case 128:
14230           oappend ("WORD PTR ");
14231           break;
14232         case 256:
14233           oappend ("DWORD PTR ");
14234           break;
14235         case 512:
14236           oappend ("QWORD PTR ");
14237           break;
14238         default:
14239           abort ();
14240         }
14241       break;
14242     case xmmqd_mode:
14243       if (!need_vex)
14244         abort ();
14245
14246       switch (vex.length)
14247         {
14248         case 128:
14249           oappend ("DWORD PTR ");
14250           break;
14251         case 256:
14252           oappend ("QWORD PTR ");
14253           break;
14254         case 512:
14255           oappend ("XMMWORD PTR ");
14256           break;
14257         default:
14258           abort ();
14259         }
14260       break;
14261     case ymmq_mode:
14262       if (!need_vex)
14263         abort ();
14264
14265       switch (vex.length)
14266         {
14267         case 128:
14268           oappend ("QWORD PTR ");
14269           break;
14270         case 256:
14271           oappend ("YMMWORD PTR ");
14272           break;
14273         case 512:
14274           oappend ("ZMMWORD PTR ");
14275           break;
14276         default:
14277           abort ();
14278         }
14279       break;
14280     case ymmxmm_mode:
14281       if (!need_vex)
14282         abort ();
14283
14284       switch (vex.length)
14285         {
14286         case 128:
14287         case 256:
14288           oappend ("XMMWORD PTR ");
14289           break;
14290         default:
14291           abort ();
14292         }
14293       break;
14294     case o_mode:
14295       oappend ("OWORD PTR ");
14296       break;
14297     case vex_scalar_w_dq_mode:
14298       if (!need_vex)
14299         abort ();
14300
14301       if (vex.w)
14302         oappend ("QWORD PTR ");
14303       else
14304         oappend ("DWORD PTR ");
14305       break;
14306     case vex_vsib_d_w_dq_mode:
14307     case vex_vsib_q_w_dq_mode:
14308       if (!need_vex)
14309         abort ();
14310
14311       if (!vex.evex)
14312         {
14313           if (vex.w)
14314             oappend ("QWORD PTR ");
14315           else
14316             oappend ("DWORD PTR ");
14317         }
14318       else
14319         {
14320           switch (vex.length)
14321             {
14322             case 128:
14323               oappend ("XMMWORD PTR ");
14324               break;
14325             case 256:
14326               oappend ("YMMWORD PTR ");
14327               break;
14328             case 512:
14329               oappend ("ZMMWORD PTR ");
14330               break;
14331             default:
14332               abort ();
14333             }
14334         }
14335       break;
14336     case vex_vsib_q_w_d_mode:
14337     case vex_vsib_d_w_d_mode:
14338       if (!need_vex || !vex.evex)
14339         abort ();
14340
14341       switch (vex.length)
14342         {
14343         case 128:
14344           oappend ("QWORD PTR ");
14345           break;
14346         case 256:
14347           oappend ("XMMWORD PTR ");
14348           break;
14349         case 512:
14350           oappend ("YMMWORD PTR ");
14351           break;
14352         default:
14353           abort ();
14354         }
14355
14356       break;
14357     case mask_bd_mode:
14358       if (!need_vex || vex.length != 128)
14359         abort ();
14360       if (vex.w)
14361         oappend ("DWORD PTR ");
14362       else
14363         oappend ("BYTE PTR ");
14364       break;
14365     case mask_mode:
14366       if (!need_vex)
14367         abort ();
14368       if (vex.w)
14369         oappend ("QWORD PTR ");
14370       else
14371         oappend ("WORD PTR ");
14372       break;
14373     case v_bnd_mode:
14374     case v_bndmk_mode:
14375     default:
14376       break;
14377     }
14378 }
14379
14380 static void
14381 OP_E_register (int bytemode, int sizeflag)
14382 {
14383   int reg = modrm.rm;
14384   const char **names;
14385
14386   USED_REX (REX_B);
14387   if ((rex & REX_B))
14388     reg += 8;
14389
14390   if ((sizeflag & SUFFIX_ALWAYS)
14391       && (bytemode == b_swap_mode
14392           || bytemode == bnd_swap_mode
14393           || bytemode == v_swap_mode))
14394     swap_operand ();
14395
14396   switch (bytemode)
14397     {
14398     case b_mode:
14399     case b_swap_mode:
14400       if (reg & 4)
14401         USED_REX (0);
14402       if (rex)
14403         names = names8rex;
14404       else
14405         names = names8;
14406       break;
14407     case w_mode:
14408       names = names16;
14409       break;
14410     case d_mode:
14411     case dw_mode:
14412     case db_mode:
14413       names = names32;
14414       break;
14415     case q_mode:
14416       names = names64;
14417       break;
14418     case m_mode:
14419     case v_bnd_mode:
14420       names = address_mode == mode_64bit ? names64 : names32;
14421       break;
14422     case bnd_mode:
14423     case bnd_swap_mode:
14424       if (reg > 0x3)
14425         {
14426           oappend ("(bad)");
14427           return;
14428         }
14429       names = names_bnd;
14430       break;
14431     case indir_v_mode:
14432       if (address_mode == mode_64bit && isa64 == intel64)
14433         {
14434           names = names64;
14435           break;
14436         }
14437       /* Fall through.  */
14438     case stack_v_mode:
14439       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14440         {
14441           names = names64;
14442           break;
14443         }
14444       bytemode = v_mode;
14445       /* Fall through.  */
14446     case v_mode:
14447     case v_swap_mode:
14448     case dq_mode:
14449     case dqb_mode:
14450     case dqd_mode:
14451     case dqw_mode:
14452       USED_REX (REX_W);
14453       if (rex & REX_W)
14454         names = names64;
14455       else
14456         {
14457           if ((sizeflag & DFLAG)
14458               || (bytemode != v_mode
14459                   && bytemode != v_swap_mode))
14460             names = names32;
14461           else
14462             names = names16;
14463           used_prefixes |= (prefixes & PREFIX_DATA);
14464         }
14465       break;
14466     case movsxd_mode:
14467       if (!(sizeflag & DFLAG) && isa64 == intel64)
14468         names = names16;
14469       else
14470         names = names32;
14471       used_prefixes |= (prefixes & PREFIX_DATA);
14472       break;
14473     case va_mode:
14474       names = (address_mode == mode_64bit
14475                ? names64 : names32);
14476       if (!(prefixes & PREFIX_ADDR))
14477         names = (address_mode == mode_16bit
14478                      ? names16 : names);
14479       else
14480         {
14481           /* Remove "addr16/addr32".  */
14482           all_prefixes[last_addr_prefix] = 0;
14483           names = (address_mode != mode_32bit
14484                        ? names32 : names16);
14485           used_prefixes |= PREFIX_ADDR;
14486         }
14487       break;
14488     case mask_bd_mode:
14489     case mask_mode:
14490       if (reg > 0x7)
14491         {
14492           oappend ("(bad)");
14493           return;
14494         }
14495       names = names_mask;
14496       break;
14497     case 0:
14498       return;
14499     default:
14500       oappend (INTERNAL_DISASSEMBLER_ERROR);
14501       return;
14502     }
14503   oappend (names[reg]);
14504 }
14505
14506 static void
14507 OP_E_memory (int bytemode, int sizeflag)
14508 {
14509   bfd_vma disp = 0;
14510   int add = (rex & REX_B) ? 8 : 0;
14511   int riprel = 0;
14512   int shift;
14513
14514   if (vex.evex)
14515     {
14516       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14517       if (vex.b
14518           && bytemode != x_mode
14519           && bytemode != xmmq_mode
14520           && bytemode != evex_half_bcst_xmmq_mode)
14521         {
14522           BadOp ();
14523           return;
14524         }
14525       switch (bytemode)
14526         {
14527         case dqw_mode:
14528         case dw_mode:
14529           shift = 1;
14530           break;
14531         case dqb_mode:
14532         case db_mode:
14533           shift = 0;
14534           break;
14535         case dq_mode:
14536           if (address_mode != mode_64bit)
14537             {
14538               shift = 2;
14539               break;
14540             }
14541             /* fall through */
14542         case vex_scalar_w_dq_mode:
14543         case vex_vsib_d_w_dq_mode:
14544         case vex_vsib_d_w_d_mode:
14545         case vex_vsib_q_w_dq_mode:
14546         case vex_vsib_q_w_d_mode:
14547         case evex_x_gscat_mode:
14548           shift = vex.w ? 3 : 2;
14549           break;
14550         case x_mode:
14551         case evex_half_bcst_xmmq_mode:
14552         case xmmq_mode:
14553           if (vex.b)
14554             {
14555               shift = vex.w ? 3 : 2;
14556               break;
14557             }
14558           /* Fall through.  */
14559         case xmmqd_mode:
14560         case xmmdw_mode:
14561         case ymmq_mode:
14562         case evex_x_nobcst_mode:
14563         case x_swap_mode:
14564           switch (vex.length)
14565             {
14566             case 128:
14567               shift = 4;
14568               break;
14569             case 256:
14570               shift = 5;
14571               break;
14572             case 512:
14573               shift = 6;
14574               break;
14575             default:
14576               abort ();
14577             }
14578           break;
14579         case ymm_mode:
14580           shift = 5;
14581           break;
14582         case xmm_mode:
14583           shift = 4;
14584           break;
14585         case xmm_mq_mode:
14586         case q_mode:
14587         case q_swap_mode:
14588         case q_scalar_swap_mode:
14589           shift = 3;
14590           break;
14591         case dqd_mode:
14592         case xmm_md_mode:
14593         case d_mode:
14594         case d_swap_mode:
14595         case d_scalar_swap_mode:
14596           shift = 2;
14597           break;
14598         case w_scalar_mode:
14599         case xmm_mw_mode:
14600           shift = 1;
14601           break;
14602         case b_scalar_mode:
14603         case xmm_mb_mode:
14604           shift = 0;
14605           break;
14606         default:
14607           abort ();
14608         }
14609       /* Make necessary corrections to shift for modes that need it.
14610          For these modes we currently have shift 4, 5 or 6 depending on
14611          vex.length (it corresponds to xmmword, ymmword or zmmword
14612          operand).  We might want to make it 3, 4 or 5 (e.g. for
14613          xmmq_mode).  In case of broadcast enabled the corrections
14614          aren't needed, as element size is always 32 or 64 bits.  */
14615       if (!vex.b
14616           && (bytemode == xmmq_mode
14617               || bytemode == evex_half_bcst_xmmq_mode))
14618         shift -= 1;
14619       else if (bytemode == xmmqd_mode)
14620         shift -= 2;
14621       else if (bytemode == xmmdw_mode)
14622         shift -= 3;
14623       else if (bytemode == ymmq_mode && vex.length == 128)
14624         shift -= 1;
14625     }
14626   else
14627     shift = 0;
14628
14629   USED_REX (REX_B);
14630   if (intel_syntax)
14631     intel_operand_size (bytemode, sizeflag);
14632   append_seg ();
14633
14634   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14635     {
14636       /* 32/64 bit address mode */
14637       int havedisp;
14638       int havesib;
14639       int havebase;
14640       int haveindex;
14641       int needindex;
14642       int needaddr32;
14643       int base, rbase;
14644       int vindex = 0;
14645       int scale = 0;
14646       int addr32flag = !((sizeflag & AFLAG)
14647                          || bytemode == v_bnd_mode
14648                          || bytemode == v_bndmk_mode
14649                          || bytemode == bnd_mode
14650                          || bytemode == bnd_swap_mode);
14651       const char **indexes64 = names64;
14652       const char **indexes32 = names32;
14653
14654       havesib = 0;
14655       havebase = 1;
14656       haveindex = 0;
14657       base = modrm.rm;
14658
14659       if (base == 4)
14660         {
14661           havesib = 1;
14662           vindex = sib.index;
14663           USED_REX (REX_X);
14664           if (rex & REX_X)
14665             vindex += 8;
14666           switch (bytemode)
14667             {
14668             case vex_vsib_d_w_dq_mode:
14669             case vex_vsib_d_w_d_mode:
14670             case vex_vsib_q_w_dq_mode:
14671             case vex_vsib_q_w_d_mode:
14672               if (!need_vex)
14673                 abort ();
14674               if (vex.evex)
14675                 {
14676                   if (!vex.v)
14677                     vindex += 16;
14678                 }
14679
14680               haveindex = 1;
14681               switch (vex.length)
14682                 {
14683                 case 128:
14684                   indexes64 = indexes32 = names_xmm;
14685                   break;
14686                 case 256:
14687                   if (!vex.w
14688                       || bytemode == vex_vsib_q_w_dq_mode
14689                       || bytemode == vex_vsib_q_w_d_mode)
14690                     indexes64 = indexes32 = names_ymm;
14691                   else
14692                     indexes64 = indexes32 = names_xmm;
14693                   break;
14694                 case 512:
14695                   if (!vex.w
14696                       || bytemode == vex_vsib_q_w_dq_mode
14697                       || bytemode == vex_vsib_q_w_d_mode)
14698                     indexes64 = indexes32 = names_zmm;
14699                   else
14700                     indexes64 = indexes32 = names_ymm;
14701                   break;
14702                 default:
14703                   abort ();
14704                 }
14705               break;
14706             default:
14707               haveindex = vindex != 4;
14708               break;
14709             }
14710           scale = sib.scale;
14711           base = sib.base;
14712           codep++;
14713         }
14714       else
14715         {
14716           /* mandatory non-vector SIB must have sib */
14717           if (bytemode == vex_sibmem_mode)
14718             {
14719               oappend ("(bad)");
14720               return;
14721             }
14722         }
14723       rbase = base + add;
14724
14725       switch (modrm.mod)
14726         {
14727         case 0:
14728           if (base == 5)
14729             {
14730               havebase = 0;
14731               if (address_mode == mode_64bit && !havesib)
14732                 riprel = 1;
14733               disp = get32s ();
14734               if (riprel && bytemode == v_bndmk_mode)
14735                 {
14736                   oappend ("(bad)");
14737                   return;
14738                 }
14739             }
14740           break;
14741         case 1:
14742           FETCH_DATA (the_info, codep + 1);
14743           disp = *codep++;
14744           if ((disp & 0x80) != 0)
14745             disp -= 0x100;
14746           if (vex.evex && shift > 0)
14747             disp <<= shift;
14748           break;
14749         case 2:
14750           disp = get32s ();
14751           break;
14752         }
14753
14754       needindex = 0;
14755       needaddr32 = 0;
14756       if (havesib
14757           && !havebase
14758           && !haveindex
14759           && address_mode != mode_16bit)
14760         {
14761           if (address_mode == mode_64bit)
14762             {
14763               /* Display eiz instead of addr32.  */
14764               needindex = addr32flag;
14765               needaddr32 = 1;
14766             }
14767           else
14768             {
14769               /* In 32-bit mode, we need index register to tell [offset]
14770                  from [eiz*1 + offset].  */
14771               needindex = 1;
14772             }
14773         }
14774
14775       havedisp = (havebase
14776                   || needindex
14777                   || (havesib && (haveindex || scale != 0)));
14778
14779       if (!intel_syntax)
14780         if (modrm.mod != 0 || base == 5)
14781           {
14782             if (havedisp || riprel)
14783               print_displacement (scratchbuf, disp);
14784             else
14785               print_operand_value (scratchbuf, 1, disp);
14786             oappend (scratchbuf);
14787             if (riprel)
14788               {
14789                 set_op (disp, 1);
14790                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14791               }
14792           }
14793
14794       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14795           && (address_mode != mode_64bit
14796               || ((bytemode != v_bnd_mode)
14797                   && (bytemode != v_bndmk_mode)
14798                   && (bytemode != bnd_mode)
14799                   && (bytemode != bnd_swap_mode))))
14800         used_prefixes |= PREFIX_ADDR;
14801
14802       if (havedisp || (intel_syntax && riprel))
14803         {
14804           *obufp++ = open_char;
14805           if (intel_syntax && riprel)
14806             {
14807               set_op (disp, 1);
14808               oappend (!addr32flag ? "rip" : "eip");
14809             }
14810           *obufp = '\0';
14811           if (havebase)
14812             oappend (address_mode == mode_64bit && !addr32flag
14813                      ? names64[rbase] : names32[rbase]);
14814           if (havesib)
14815             {
14816               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14817                  print index to tell base + index from base.  */
14818               if (scale != 0
14819                   || needindex
14820                   || haveindex
14821                   || (havebase && base != ESP_REG_NUM))
14822                 {
14823                   if (!intel_syntax || havebase)
14824                     {
14825                       *obufp++ = separator_char;
14826                       *obufp = '\0';
14827                     }
14828                   if (haveindex)
14829                     oappend (address_mode == mode_64bit && !addr32flag
14830                              ? indexes64[vindex] : indexes32[vindex]);
14831                   else
14832                     oappend (address_mode == mode_64bit && !addr32flag
14833                              ? index64 : index32);
14834
14835                   *obufp++ = scale_char;
14836                   *obufp = '\0';
14837                   sprintf (scratchbuf, "%d", 1 << scale);
14838                   oappend (scratchbuf);
14839                 }
14840             }
14841           if (intel_syntax
14842               && (disp || modrm.mod != 0 || base == 5))
14843             {
14844               if (!havedisp || (bfd_signed_vma) disp >= 0)
14845                 {
14846                   *obufp++ = '+';
14847                   *obufp = '\0';
14848                 }
14849               else if (modrm.mod != 1 && disp != -disp)
14850                 {
14851                   *obufp++ = '-';
14852                   *obufp = '\0';
14853                   disp = - (bfd_signed_vma) disp;
14854                 }
14855
14856               if (havedisp)
14857                 print_displacement (scratchbuf, disp);
14858               else
14859                 print_operand_value (scratchbuf, 1, disp);
14860               oappend (scratchbuf);
14861             }
14862
14863           *obufp++ = close_char;
14864           *obufp = '\0';
14865         }
14866       else if (intel_syntax)
14867         {
14868           if (modrm.mod != 0 || base == 5)
14869             {
14870               if (!active_seg_prefix)
14871                 {
14872                   oappend (names_seg[ds_reg - es_reg]);
14873                   oappend (":");
14874                 }
14875               print_operand_value (scratchbuf, 1, disp);
14876               oappend (scratchbuf);
14877             }
14878         }
14879     }
14880   else if (bytemode == v_bnd_mode
14881            || bytemode == v_bndmk_mode
14882            || bytemode == bnd_mode
14883            || bytemode == bnd_swap_mode)
14884     {
14885       oappend ("(bad)");
14886       return;
14887     }
14888   else
14889     {
14890       /* 16 bit address mode */
14891       used_prefixes |= prefixes & PREFIX_ADDR;
14892       switch (modrm.mod)
14893         {
14894         case 0:
14895           if (modrm.rm == 6)
14896             {
14897               disp = get16 ();
14898               if ((disp & 0x8000) != 0)
14899                 disp -= 0x10000;
14900             }
14901           break;
14902         case 1:
14903           FETCH_DATA (the_info, codep + 1);
14904           disp = *codep++;
14905           if ((disp & 0x80) != 0)
14906             disp -= 0x100;
14907           if (vex.evex && shift > 0)
14908             disp <<= shift;
14909           break;
14910         case 2:
14911           disp = get16 ();
14912           if ((disp & 0x8000) != 0)
14913             disp -= 0x10000;
14914           break;
14915         }
14916
14917       if (!intel_syntax)
14918         if (modrm.mod != 0 || modrm.rm == 6)
14919           {
14920             print_displacement (scratchbuf, disp);
14921             oappend (scratchbuf);
14922           }
14923
14924       if (modrm.mod != 0 || modrm.rm != 6)
14925         {
14926           *obufp++ = open_char;
14927           *obufp = '\0';
14928           oappend (index16[modrm.rm]);
14929           if (intel_syntax
14930               && (disp || modrm.mod != 0 || modrm.rm == 6))
14931             {
14932               if ((bfd_signed_vma) disp >= 0)
14933                 {
14934                   *obufp++ = '+';
14935                   *obufp = '\0';
14936                 }
14937               else if (modrm.mod != 1)
14938                 {
14939                   *obufp++ = '-';
14940                   *obufp = '\0';
14941                   disp = - (bfd_signed_vma) disp;
14942                 }
14943
14944               print_displacement (scratchbuf, disp);
14945               oappend (scratchbuf);
14946             }
14947
14948           *obufp++ = close_char;
14949           *obufp = '\0';
14950         }
14951       else if (intel_syntax)
14952         {
14953           if (!active_seg_prefix)
14954             {
14955               oappend (names_seg[ds_reg - es_reg]);
14956               oappend (":");
14957             }
14958           print_operand_value (scratchbuf, 1, disp & 0xffff);
14959           oappend (scratchbuf);
14960         }
14961     }
14962   if (vex.evex && vex.b
14963       && (bytemode == x_mode
14964           || bytemode == xmmq_mode
14965           || bytemode == evex_half_bcst_xmmq_mode))
14966     {
14967       if (vex.w
14968           || bytemode == xmmq_mode
14969           || bytemode == evex_half_bcst_xmmq_mode)
14970         {
14971           switch (vex.length)
14972             {
14973             case 128:
14974               oappend ("{1to2}");
14975               break;
14976             case 256:
14977               oappend ("{1to4}");
14978               break;
14979             case 512:
14980               oappend ("{1to8}");
14981               break;
14982             default:
14983               abort ();
14984             }
14985         }
14986       else
14987         {
14988           switch (vex.length)
14989             {
14990             case 128:
14991               oappend ("{1to4}");
14992               break;
14993             case 256:
14994               oappend ("{1to8}");
14995               break;
14996             case 512:
14997               oappend ("{1to16}");
14998               break;
14999             default:
15000               abort ();
15001             }
15002         }
15003     }
15004 }
15005
15006 static void
15007 OP_E (int bytemode, int sizeflag)
15008 {
15009   /* Skip mod/rm byte.  */
15010   MODRM_CHECK;
15011   codep++;
15012
15013   if (modrm.mod == 3)
15014     OP_E_register (bytemode, sizeflag);
15015   else
15016     OP_E_memory (bytemode, sizeflag);
15017 }
15018
15019 static void
15020 OP_G (int bytemode, int sizeflag)
15021 {
15022   int add = 0;
15023   const char **names;
15024   USED_REX (REX_R);
15025   if (rex & REX_R)
15026     add += 8;
15027   switch (bytemode)
15028     {
15029     case b_mode:
15030       if (modrm.reg & 4)
15031         USED_REX (0);
15032       if (rex)
15033         oappend (names8rex[modrm.reg + add]);
15034       else
15035         oappend (names8[modrm.reg + add]);
15036       break;
15037     case w_mode:
15038       oappend (names16[modrm.reg + add]);
15039       break;
15040     case d_mode:
15041     case db_mode:
15042     case dw_mode:
15043       oappend (names32[modrm.reg + add]);
15044       break;
15045     case q_mode:
15046       oappend (names64[modrm.reg + add]);
15047       break;
15048     case bnd_mode:
15049       if (modrm.reg > 0x3)
15050         {
15051           oappend ("(bad)");
15052           return;
15053         }
15054       oappend (names_bnd[modrm.reg]);
15055       break;
15056     case v_mode:
15057     case dq_mode:
15058     case dqb_mode:
15059     case dqd_mode:
15060     case dqw_mode:
15061     case movsxd_mode:
15062       USED_REX (REX_W);
15063       if (rex & REX_W)
15064         oappend (names64[modrm.reg + add]);
15065       else
15066         {
15067           if ((sizeflag & DFLAG)
15068               || (bytemode != v_mode && bytemode != movsxd_mode))
15069             oappend (names32[modrm.reg + add]);
15070           else
15071             oappend (names16[modrm.reg + add]);
15072           used_prefixes |= (prefixes & PREFIX_DATA);
15073         }
15074       break;
15075     case va_mode:
15076       names = (address_mode == mode_64bit
15077                ? names64 : names32);
15078       if (!(prefixes & PREFIX_ADDR))
15079         {
15080           if (address_mode == mode_16bit)
15081             names = names16;
15082         }
15083       else
15084         {
15085           /* Remove "addr16/addr32".  */
15086           all_prefixes[last_addr_prefix] = 0;
15087           names = (address_mode != mode_32bit
15088                        ? names32 : names16);
15089           used_prefixes |= PREFIX_ADDR;
15090         }
15091       oappend (names[modrm.reg + add]);
15092       break;
15093     case m_mode:
15094       if (address_mode == mode_64bit)
15095         oappend (names64[modrm.reg + add]);
15096       else
15097         oappend (names32[modrm.reg + add]);
15098       break;
15099     case mask_bd_mode:
15100     case mask_mode:
15101       if ((modrm.reg + add) > 0x7)
15102         {
15103           oappend ("(bad)");
15104           return;
15105         }
15106       oappend (names_mask[modrm.reg + add]);
15107       break;
15108     default:
15109       oappend (INTERNAL_DISASSEMBLER_ERROR);
15110       break;
15111     }
15112 }
15113
15114 static bfd_vma
15115 get64 (void)
15116 {
15117   bfd_vma x;
15118 #ifdef BFD64
15119   unsigned int a;
15120   unsigned int b;
15121
15122   FETCH_DATA (the_info, codep + 8);
15123   a = *codep++ & 0xff;
15124   a |= (*codep++ & 0xff) << 8;
15125   a |= (*codep++ & 0xff) << 16;
15126   a |= (*codep++ & 0xffu) << 24;
15127   b = *codep++ & 0xff;
15128   b |= (*codep++ & 0xff) << 8;
15129   b |= (*codep++ & 0xff) << 16;
15130   b |= (*codep++ & 0xffu) << 24;
15131   x = a + ((bfd_vma) b << 32);
15132 #else
15133   abort ();
15134   x = 0;
15135 #endif
15136   return x;
15137 }
15138
15139 static bfd_signed_vma
15140 get32 (void)
15141 {
15142   bfd_signed_vma x = 0;
15143
15144   FETCH_DATA (the_info, codep + 4);
15145   x = *codep++ & (bfd_signed_vma) 0xff;
15146   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15147   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15148   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15149   return x;
15150 }
15151
15152 static bfd_signed_vma
15153 get32s (void)
15154 {
15155   bfd_signed_vma x = 0;
15156
15157   FETCH_DATA (the_info, codep + 4);
15158   x = *codep++ & (bfd_signed_vma) 0xff;
15159   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15160   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15161   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15162
15163   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15164
15165   return x;
15166 }
15167
15168 static int
15169 get16 (void)
15170 {
15171   int x = 0;
15172
15173   FETCH_DATA (the_info, codep + 2);
15174   x = *codep++ & 0xff;
15175   x |= (*codep++ & 0xff) << 8;
15176   return x;
15177 }
15178
15179 static void
15180 set_op (bfd_vma op, int riprel)
15181 {
15182   op_index[op_ad] = op_ad;
15183   if (address_mode == mode_64bit)
15184     {
15185       op_address[op_ad] = op;
15186       op_riprel[op_ad] = riprel;
15187     }
15188   else
15189     {
15190       /* Mask to get a 32-bit address.  */
15191       op_address[op_ad] = op & 0xffffffff;
15192       op_riprel[op_ad] = riprel & 0xffffffff;
15193     }
15194 }
15195
15196 static void
15197 OP_REG (int code, int sizeflag)
15198 {
15199   const char *s;
15200   int add;
15201
15202   switch (code)
15203     {
15204     case es_reg: case ss_reg: case cs_reg:
15205     case ds_reg: case fs_reg: case gs_reg:
15206       oappend (names_seg[code - es_reg]);
15207       return;
15208     }
15209
15210   USED_REX (REX_B);
15211   if (rex & REX_B)
15212     add = 8;
15213   else
15214     add = 0;
15215
15216   switch (code)
15217     {
15218     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15219     case sp_reg: case bp_reg: case si_reg: case di_reg:
15220       s = names16[code - ax_reg + add];
15221       break;
15222     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
15223       USED_REX (0);
15224       /* Fall through.  */
15225     case al_reg: case cl_reg: case dl_reg: case bl_reg:
15226       if (rex)
15227         s = names8rex[code - al_reg + add];
15228       else
15229         s = names8[code - al_reg];
15230       break;
15231     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15232     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15233       if (address_mode == mode_64bit
15234           && ((sizeflag & DFLAG) || (rex & REX_W)))
15235         {
15236           s = names64[code - rAX_reg + add];
15237           break;
15238         }
15239       code += eAX_reg - rAX_reg;
15240       /* Fall through.  */
15241     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15242     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15243       USED_REX (REX_W);
15244       if (rex & REX_W)
15245         s = names64[code - eAX_reg + add];
15246       else
15247         {
15248           if (sizeflag & DFLAG)
15249             s = names32[code - eAX_reg + add];
15250           else
15251             s = names16[code - eAX_reg + add];
15252           used_prefixes |= (prefixes & PREFIX_DATA);
15253         }
15254       break;
15255     default:
15256       s = INTERNAL_DISASSEMBLER_ERROR;
15257       break;
15258     }
15259   oappend (s);
15260 }
15261
15262 static void
15263 OP_IMREG (int code, int sizeflag)
15264 {
15265   const char *s;
15266
15267   switch (code)
15268     {
15269     case indir_dx_reg:
15270       if (intel_syntax)
15271         s = "dx";
15272       else
15273         s = "(%dx)";
15274       break;
15275     case al_reg: case cl_reg:
15276       s = names8[code - al_reg];
15277       break;
15278     case eAX_reg:
15279       USED_REX (REX_W);
15280       if (rex & REX_W)
15281         {
15282           s = *names64;
15283           break;
15284         }
15285       /* Fall through.  */
15286     case z_mode_ax_reg:
15287       if ((rex & REX_W) || (sizeflag & DFLAG))
15288         s = *names32;
15289       else
15290         s = *names16;
15291       if (!(rex & REX_W))
15292         used_prefixes |= (prefixes & PREFIX_DATA);
15293       break;
15294     default:
15295       s = INTERNAL_DISASSEMBLER_ERROR;
15296       break;
15297     }
15298   oappend (s);
15299 }
15300
15301 static void
15302 OP_I (int bytemode, int sizeflag)
15303 {
15304   bfd_signed_vma op;
15305   bfd_signed_vma mask = -1;
15306
15307   switch (bytemode)
15308     {
15309     case b_mode:
15310       FETCH_DATA (the_info, codep + 1);
15311       op = *codep++;
15312       mask = 0xff;
15313       break;
15314     case v_mode:
15315       USED_REX (REX_W);
15316       if (rex & REX_W)
15317         op = get32s ();
15318       else
15319         {
15320           if (sizeflag & DFLAG)
15321             {
15322               op = get32 ();
15323               mask = 0xffffffff;
15324             }
15325           else
15326             {
15327               op = get16 ();
15328               mask = 0xfffff;
15329             }
15330           used_prefixes |= (prefixes & PREFIX_DATA);
15331         }
15332       break;
15333     case d_mode:
15334       mask = 0xffffffff;
15335       op = get32 ();
15336       break;
15337     case w_mode:
15338       mask = 0xfffff;
15339       op = get16 ();
15340       break;
15341     case const_1_mode:
15342       if (intel_syntax)
15343         oappend ("1");
15344       return;
15345     default:
15346       oappend (INTERNAL_DISASSEMBLER_ERROR);
15347       return;
15348     }
15349
15350   op &= mask;
15351   scratchbuf[0] = '$';
15352   print_operand_value (scratchbuf + 1, 1, op);
15353   oappend_maybe_intel (scratchbuf);
15354   scratchbuf[0] = '\0';
15355 }
15356
15357 static void
15358 OP_I64 (int bytemode, int sizeflag)
15359 {
15360   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
15361     {
15362       OP_I (bytemode, sizeflag);
15363       return;
15364     }
15365
15366   USED_REX (REX_W);
15367
15368   scratchbuf[0] = '$';
15369   print_operand_value (scratchbuf + 1, 1, get64 ());
15370   oappend_maybe_intel (scratchbuf);
15371   scratchbuf[0] = '\0';
15372 }
15373
15374 static void
15375 OP_sI (int bytemode, int sizeflag)
15376 {
15377   bfd_signed_vma op;
15378
15379   switch (bytemode)
15380     {
15381     case b_mode:
15382     case b_T_mode:
15383       FETCH_DATA (the_info, codep + 1);
15384       op = *codep++;
15385       if ((op & 0x80) != 0)
15386         op -= 0x100;
15387       if (bytemode == b_T_mode)
15388         {
15389           if (address_mode != mode_64bit
15390               || !((sizeflag & DFLAG) || (rex & REX_W)))
15391             {
15392               /* The operand-size prefix is overridden by a REX prefix.  */
15393               if ((sizeflag & DFLAG) || (rex & REX_W))
15394                 op &= 0xffffffff;
15395               else
15396                 op &= 0xffff;
15397           }
15398         }
15399       else
15400         {
15401           if (!(rex & REX_W))
15402             {
15403               if (sizeflag & DFLAG)
15404                 op &= 0xffffffff;
15405               else
15406                 op &= 0xffff;
15407             }
15408         }
15409       break;
15410     case v_mode:
15411       /* The operand-size prefix is overridden by a REX prefix.  */
15412       if ((sizeflag & DFLAG) || (rex & REX_W))
15413         op = get32s ();
15414       else
15415         op = get16 ();
15416       break;
15417     default:
15418       oappend (INTERNAL_DISASSEMBLER_ERROR);
15419       return;
15420     }
15421
15422   scratchbuf[0] = '$';
15423   print_operand_value (scratchbuf + 1, 1, op);
15424   oappend_maybe_intel (scratchbuf);
15425 }
15426
15427 static void
15428 OP_J (int bytemode, int sizeflag)
15429 {
15430   bfd_vma disp;
15431   bfd_vma mask = -1;
15432   bfd_vma segment = 0;
15433
15434   switch (bytemode)
15435     {
15436     case b_mode:
15437       FETCH_DATA (the_info, codep + 1);
15438       disp = *codep++;
15439       if ((disp & 0x80) != 0)
15440         disp -= 0x100;
15441       break;
15442     case v_mode:
15443       if (isa64 != intel64)
15444     case dqw_mode:
15445         USED_REX (REX_W);
15446       if ((sizeflag & DFLAG)
15447           || (address_mode == mode_64bit
15448               && ((isa64 == intel64 && bytemode != dqw_mode)
15449                   || (rex & REX_W))))
15450         disp = get32s ();
15451       else
15452         {
15453           disp = get16 ();
15454           if ((disp & 0x8000) != 0)
15455             disp -= 0x10000;
15456           /* In 16bit mode, address is wrapped around at 64k within
15457              the same segment.  Otherwise, a data16 prefix on a jump
15458              instruction means that the pc is masked to 16 bits after
15459              the displacement is added!  */
15460           mask = 0xffff;
15461           if ((prefixes & PREFIX_DATA) == 0)
15462             segment = ((start_pc + (codep - start_codep))
15463                        & ~((bfd_vma) 0xffff));
15464         }
15465       if (address_mode != mode_64bit
15466           || (isa64 != intel64 && !(rex & REX_W)))
15467         used_prefixes |= (prefixes & PREFIX_DATA);
15468       break;
15469     default:
15470       oappend (INTERNAL_DISASSEMBLER_ERROR);
15471       return;
15472     }
15473   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15474   set_op (disp, 0);
15475   print_operand_value (scratchbuf, 1, disp);
15476   oappend (scratchbuf);
15477 }
15478
15479 static void
15480 OP_SEG (int bytemode, int sizeflag)
15481 {
15482   if (bytemode == w_mode)
15483     oappend (names_seg[modrm.reg]);
15484   else
15485     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15486 }
15487
15488 static void
15489 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15490 {
15491   int seg, offset;
15492
15493   if (sizeflag & DFLAG)
15494     {
15495       offset = get32 ();
15496       seg = get16 ();
15497     }
15498   else
15499     {
15500       offset = get16 ();
15501       seg = get16 ();
15502     }
15503   used_prefixes |= (prefixes & PREFIX_DATA);
15504   if (intel_syntax)
15505     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15506   else
15507     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15508   oappend (scratchbuf);
15509 }
15510
15511 static void
15512 OP_OFF (int bytemode, int sizeflag)
15513 {
15514   bfd_vma off;
15515
15516   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15517     intel_operand_size (bytemode, sizeflag);
15518   append_seg ();
15519
15520   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15521     off = get32 ();
15522   else
15523     off = get16 ();
15524
15525   if (intel_syntax)
15526     {
15527       if (!active_seg_prefix)
15528         {
15529           oappend (names_seg[ds_reg - es_reg]);
15530           oappend (":");
15531         }
15532     }
15533   print_operand_value (scratchbuf, 1, off);
15534   oappend (scratchbuf);
15535 }
15536
15537 static void
15538 OP_OFF64 (int bytemode, int sizeflag)
15539 {
15540   bfd_vma off;
15541
15542   if (address_mode != mode_64bit
15543       || (prefixes & PREFIX_ADDR))
15544     {
15545       OP_OFF (bytemode, sizeflag);
15546       return;
15547     }
15548
15549   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15550     intel_operand_size (bytemode, sizeflag);
15551   append_seg ();
15552
15553   off = get64 ();
15554
15555   if (intel_syntax)
15556     {
15557       if (!active_seg_prefix)
15558         {
15559           oappend (names_seg[ds_reg - es_reg]);
15560           oappend (":");
15561         }
15562     }
15563   print_operand_value (scratchbuf, 1, off);
15564   oappend (scratchbuf);
15565 }
15566
15567 static void
15568 ptr_reg (int code, int sizeflag)
15569 {
15570   const char *s;
15571
15572   *obufp++ = open_char;
15573   used_prefixes |= (prefixes & PREFIX_ADDR);
15574   if (address_mode == mode_64bit)
15575     {
15576       if (!(sizeflag & AFLAG))
15577         s = names32[code - eAX_reg];
15578       else
15579         s = names64[code - eAX_reg];
15580     }
15581   else if (sizeflag & AFLAG)
15582     s = names32[code - eAX_reg];
15583   else
15584     s = names16[code - eAX_reg];
15585   oappend (s);
15586   *obufp++ = close_char;
15587   *obufp = 0;
15588 }
15589
15590 static void
15591 OP_ESreg (int code, int sizeflag)
15592 {
15593   if (intel_syntax)
15594     {
15595       switch (codep[-1])
15596         {
15597         case 0x6d:      /* insw/insl */
15598           intel_operand_size (z_mode, sizeflag);
15599           break;
15600         case 0xa5:      /* movsw/movsl/movsq */
15601         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15602         case 0xab:      /* stosw/stosl */
15603         case 0xaf:      /* scasw/scasl */
15604           intel_operand_size (v_mode, sizeflag);
15605           break;
15606         default:
15607           intel_operand_size (b_mode, sizeflag);
15608         }
15609     }
15610   oappend_maybe_intel ("%es:");
15611   ptr_reg (code, sizeflag);
15612 }
15613
15614 static void
15615 OP_DSreg (int code, int sizeflag)
15616 {
15617   if (intel_syntax)
15618     {
15619       switch (codep[-1])
15620         {
15621         case 0x6f:      /* outsw/outsl */
15622           intel_operand_size (z_mode, sizeflag);
15623           break;
15624         case 0xa5:      /* movsw/movsl/movsq */
15625         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15626         case 0xad:      /* lodsw/lodsl/lodsq */
15627           intel_operand_size (v_mode, sizeflag);
15628           break;
15629         default:
15630           intel_operand_size (b_mode, sizeflag);
15631         }
15632     }
15633   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15634      default segment register DS is printed.  */
15635   if (!active_seg_prefix)
15636     active_seg_prefix = PREFIX_DS;
15637   append_seg ();
15638   ptr_reg (code, sizeflag);
15639 }
15640
15641 static void
15642 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15643 {
15644   int add;
15645   if (rex & REX_R)
15646     {
15647       USED_REX (REX_R);
15648       add = 8;
15649     }
15650   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15651     {
15652       all_prefixes[last_lock_prefix] = 0;
15653       used_prefixes |= PREFIX_LOCK;
15654       add = 8;
15655     }
15656   else
15657     add = 0;
15658   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15659   oappend_maybe_intel (scratchbuf);
15660 }
15661
15662 static void
15663 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15664 {
15665   int add;
15666   USED_REX (REX_R);
15667   if (rex & REX_R)
15668     add = 8;
15669   else
15670     add = 0;
15671   if (intel_syntax)
15672     sprintf (scratchbuf, "db%d", modrm.reg + add);
15673   else
15674     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15675   oappend (scratchbuf);
15676 }
15677
15678 static void
15679 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15680 {
15681   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15682   oappend_maybe_intel (scratchbuf);
15683 }
15684
15685 static void
15686 OP_R (int bytemode, int sizeflag)
15687 {
15688   /* Skip mod/rm byte.  */
15689   MODRM_CHECK;
15690   codep++;
15691   OP_E_register (bytemode, sizeflag);
15692 }
15693
15694 static void
15695 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15696 {
15697   int reg = modrm.reg;
15698   const char **names;
15699
15700   used_prefixes |= (prefixes & PREFIX_DATA);
15701   if (prefixes & PREFIX_DATA)
15702     {
15703       names = names_xmm;
15704       USED_REX (REX_R);
15705       if (rex & REX_R)
15706         reg += 8;
15707     }
15708   else
15709     names = names_mm;
15710   oappend (names[reg]);
15711 }
15712
15713 static void
15714 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15715 {
15716   int reg = modrm.reg;
15717   const char **names;
15718
15719   USED_REX (REX_R);
15720   if (rex & REX_R)
15721     reg += 8;
15722   if (vex.evex)
15723     {
15724       if (!vex.r)
15725         reg += 16;
15726     }
15727
15728   if (need_vex
15729       && bytemode != xmm_mode
15730       && bytemode != xmmq_mode
15731       && bytemode != evex_half_bcst_xmmq_mode
15732       && bytemode != ymm_mode
15733       && bytemode != tmm_mode
15734       && bytemode != scalar_mode)
15735     {
15736       switch (vex.length)
15737         {
15738         case 128:
15739           names = names_xmm;
15740           break;
15741         case 256:
15742           if (vex.w
15743               || (bytemode != vex_vsib_q_w_dq_mode
15744                   && bytemode != vex_vsib_q_w_d_mode))
15745             names = names_ymm;
15746           else
15747             names = names_xmm;
15748           break;
15749         case 512:
15750           names = names_zmm;
15751           break;
15752         default:
15753           abort ();
15754         }
15755     }
15756   else if (bytemode == xmmq_mode
15757            || bytemode == evex_half_bcst_xmmq_mode)
15758     {
15759       switch (vex.length)
15760         {
15761         case 128:
15762         case 256:
15763           names = names_xmm;
15764           break;
15765         case 512:
15766           names = names_ymm;
15767           break;
15768         default:
15769           abort ();
15770         }
15771     }
15772   else if (bytemode == tmm_mode)
15773     {
15774       modrm.reg = reg;
15775       if (reg >= 8)
15776         {
15777           oappend ("(bad)");
15778           return;
15779         }
15780       names = names_tmm;
15781     }
15782   else if (bytemode == ymm_mode)
15783     names = names_ymm;
15784   else
15785     names = names_xmm;
15786   oappend (names[reg]);
15787 }
15788
15789 static void
15790 OP_EM (int bytemode, int sizeflag)
15791 {
15792   int reg;
15793   const char **names;
15794
15795   if (modrm.mod != 3)
15796     {
15797       if (intel_syntax
15798           && (bytemode == v_mode || bytemode == v_swap_mode))
15799         {
15800           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15801           used_prefixes |= (prefixes & PREFIX_DATA);
15802         }
15803       OP_E (bytemode, sizeflag);
15804       return;
15805     }
15806
15807   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15808     swap_operand ();
15809
15810   /* Skip mod/rm byte.  */
15811   MODRM_CHECK;
15812   codep++;
15813   used_prefixes |= (prefixes & PREFIX_DATA);
15814   reg = modrm.rm;
15815   if (prefixes & PREFIX_DATA)
15816     {
15817       names = names_xmm;
15818       USED_REX (REX_B);
15819       if (rex & REX_B)
15820         reg += 8;
15821     }
15822   else
15823     names = names_mm;
15824   oappend (names[reg]);
15825 }
15826
15827 /* cvt* are the only instructions in sse2 which have
15828    both SSE and MMX operands and also have 0x66 prefix
15829    in their opcode. 0x66 was originally used to differentiate
15830    between SSE and MMX instruction(operands). So we have to handle the
15831    cvt* separately using OP_EMC and OP_MXC */
15832 static void
15833 OP_EMC (int bytemode, int sizeflag)
15834 {
15835   if (modrm.mod != 3)
15836     {
15837       if (intel_syntax && bytemode == v_mode)
15838         {
15839           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15840           used_prefixes |= (prefixes & PREFIX_DATA);
15841         }
15842       OP_E (bytemode, sizeflag);
15843       return;
15844     }
15845
15846   /* Skip mod/rm byte.  */
15847   MODRM_CHECK;
15848   codep++;
15849   used_prefixes |= (prefixes & PREFIX_DATA);
15850   oappend (names_mm[modrm.rm]);
15851 }
15852
15853 static void
15854 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15855 {
15856   used_prefixes |= (prefixes & PREFIX_DATA);
15857   oappend (names_mm[modrm.reg]);
15858 }
15859
15860 static void
15861 OP_EX (int bytemode, int sizeflag)
15862 {
15863   int reg;
15864   const char **names;
15865
15866   /* Skip mod/rm byte.  */
15867   MODRM_CHECK;
15868   codep++;
15869
15870   if (modrm.mod != 3)
15871     {
15872       OP_E_memory (bytemode, sizeflag);
15873       return;
15874     }
15875
15876   reg = modrm.rm;
15877   USED_REX (REX_B);
15878   if (rex & REX_B)
15879     reg += 8;
15880   if (vex.evex)
15881     {
15882       USED_REX (REX_X);
15883       if ((rex & REX_X))
15884         reg += 16;
15885     }
15886
15887   if ((sizeflag & SUFFIX_ALWAYS)
15888       && (bytemode == x_swap_mode
15889           || bytemode == d_swap_mode
15890           || bytemode == d_scalar_swap_mode
15891           || bytemode == q_swap_mode
15892           || bytemode == q_scalar_swap_mode))
15893     swap_operand ();
15894
15895   if (need_vex
15896       && bytemode != xmm_mode
15897       && bytemode != xmmdw_mode
15898       && bytemode != xmmqd_mode
15899       && bytemode != xmm_mb_mode
15900       && bytemode != xmm_mw_mode
15901       && bytemode != xmm_md_mode
15902       && bytemode != xmm_mq_mode
15903       && bytemode != xmmq_mode
15904       && bytemode != evex_half_bcst_xmmq_mode
15905       && bytemode != ymm_mode
15906       && bytemode != tmm_mode
15907       && bytemode != d_scalar_swap_mode
15908       && bytemode != q_scalar_swap_mode
15909       && bytemode != vex_scalar_w_dq_mode)
15910     {
15911       switch (vex.length)
15912         {
15913         case 128:
15914           names = names_xmm;
15915           break;
15916         case 256:
15917           names = names_ymm;
15918           break;
15919         case 512:
15920           names = names_zmm;
15921           break;
15922         default:
15923           abort ();
15924         }
15925     }
15926   else if (bytemode == xmmq_mode
15927            || bytemode == evex_half_bcst_xmmq_mode)
15928     {
15929       switch (vex.length)
15930         {
15931         case 128:
15932         case 256:
15933           names = names_xmm;
15934           break;
15935         case 512:
15936           names = names_ymm;
15937           break;
15938         default:
15939           abort ();
15940         }
15941     }
15942   else if (bytemode == tmm_mode)
15943     {
15944       modrm.rm = reg;
15945       if (reg >= 8)
15946         {
15947           oappend ("(bad)");
15948           return;
15949         }
15950       names = names_tmm;
15951     }
15952   else if (bytemode == ymm_mode)
15953     names = names_ymm;
15954   else
15955     names = names_xmm;
15956   oappend (names[reg]);
15957 }
15958
15959 static void
15960 OP_MS (int bytemode, int sizeflag)
15961 {
15962   if (modrm.mod == 3)
15963     OP_EM (bytemode, sizeflag);
15964   else
15965     BadOp ();
15966 }
15967
15968 static void
15969 OP_XS (int bytemode, int sizeflag)
15970 {
15971   if (modrm.mod == 3)
15972     OP_EX (bytemode, sizeflag);
15973   else
15974     BadOp ();
15975 }
15976
15977 static void
15978 OP_M (int bytemode, int sizeflag)
15979 {
15980   if (modrm.mod == 3)
15981     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15982     BadOp ();
15983   else
15984     OP_E (bytemode, sizeflag);
15985 }
15986
15987 static void
15988 OP_0f07 (int bytemode, int sizeflag)
15989 {
15990   if (modrm.mod != 3 || modrm.rm != 0)
15991     BadOp ();
15992   else
15993     OP_E (bytemode, sizeflag);
15994 }
15995
15996 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15997    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15998
15999 static void
16000 NOP_Fixup1 (int bytemode, int sizeflag)
16001 {
16002   if ((prefixes & PREFIX_DATA) != 0
16003       || (rex != 0
16004           && rex != 0x48
16005           && address_mode == mode_64bit))
16006     OP_REG (bytemode, sizeflag);
16007   else
16008     strcpy (obuf, "nop");
16009 }
16010
16011 static void
16012 NOP_Fixup2 (int bytemode, int sizeflag)
16013 {
16014   if ((prefixes & PREFIX_DATA) != 0
16015       || (rex != 0
16016           && rex != 0x48
16017           && address_mode == mode_64bit))
16018     OP_IMREG (bytemode, sizeflag);
16019 }
16020
16021 static const char *const Suffix3DNow[] = {
16022 /* 00 */        NULL,           NULL,           NULL,           NULL,
16023 /* 04 */        NULL,           NULL,           NULL,           NULL,
16024 /* 08 */        NULL,           NULL,           NULL,           NULL,
16025 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16026 /* 10 */        NULL,           NULL,           NULL,           NULL,
16027 /* 14 */        NULL,           NULL,           NULL,           NULL,
16028 /* 18 */        NULL,           NULL,           NULL,           NULL,
16029 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16030 /* 20 */        NULL,           NULL,           NULL,           NULL,
16031 /* 24 */        NULL,           NULL,           NULL,           NULL,
16032 /* 28 */        NULL,           NULL,           NULL,           NULL,
16033 /* 2C */        NULL,           NULL,           NULL,           NULL,
16034 /* 30 */        NULL,           NULL,           NULL,           NULL,
16035 /* 34 */        NULL,           NULL,           NULL,           NULL,
16036 /* 38 */        NULL,           NULL,           NULL,           NULL,
16037 /* 3C */        NULL,           NULL,           NULL,           NULL,
16038 /* 40 */        NULL,           NULL,           NULL,           NULL,
16039 /* 44 */        NULL,           NULL,           NULL,           NULL,
16040 /* 48 */        NULL,           NULL,           NULL,           NULL,
16041 /* 4C */        NULL,           NULL,           NULL,           NULL,
16042 /* 50 */        NULL,           NULL,           NULL,           NULL,
16043 /* 54 */        NULL,           NULL,           NULL,           NULL,
16044 /* 58 */        NULL,           NULL,           NULL,           NULL,
16045 /* 5C */        NULL,           NULL,           NULL,           NULL,
16046 /* 60 */        NULL,           NULL,           NULL,           NULL,
16047 /* 64 */        NULL,           NULL,           NULL,           NULL,
16048 /* 68 */        NULL,           NULL,           NULL,           NULL,
16049 /* 6C */        NULL,           NULL,           NULL,           NULL,
16050 /* 70 */        NULL,           NULL,           NULL,           NULL,
16051 /* 74 */        NULL,           NULL,           NULL,           NULL,
16052 /* 78 */        NULL,           NULL,           NULL,           NULL,
16053 /* 7C */        NULL,           NULL,           NULL,           NULL,
16054 /* 80 */        NULL,           NULL,           NULL,           NULL,
16055 /* 84 */        NULL,           NULL,           NULL,           NULL,
16056 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16057 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16058 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16059 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16060 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16061 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16062 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16063 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16064 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16065 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16066 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16067 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16068 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16069 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16070 /* C0 */        NULL,           NULL,           NULL,           NULL,
16071 /* C4 */        NULL,           NULL,           NULL,           NULL,
16072 /* C8 */        NULL,           NULL,           NULL,           NULL,
16073 /* CC */        NULL,           NULL,           NULL,           NULL,
16074 /* D0 */        NULL,           NULL,           NULL,           NULL,
16075 /* D4 */        NULL,           NULL,           NULL,           NULL,
16076 /* D8 */        NULL,           NULL,           NULL,           NULL,
16077 /* DC */        NULL,           NULL,           NULL,           NULL,
16078 /* E0 */        NULL,           NULL,           NULL,           NULL,
16079 /* E4 */        NULL,           NULL,           NULL,           NULL,
16080 /* E8 */        NULL,           NULL,           NULL,           NULL,
16081 /* EC */        NULL,           NULL,           NULL,           NULL,
16082 /* F0 */        NULL,           NULL,           NULL,           NULL,
16083 /* F4 */        NULL,           NULL,           NULL,           NULL,
16084 /* F8 */        NULL,           NULL,           NULL,           NULL,
16085 /* FC */        NULL,           NULL,           NULL,           NULL,
16086 };
16087
16088 static void
16089 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16090 {
16091   const char *mnemonic;
16092
16093   FETCH_DATA (the_info, codep + 1);
16094   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16095      place where an 8-bit immediate would normally go.  ie. the last
16096      byte of the instruction.  */
16097   obufp = mnemonicendp;
16098   mnemonic = Suffix3DNow[*codep++ & 0xff];
16099   if (mnemonic)
16100     oappend (mnemonic);
16101   else
16102     {
16103       /* Since a variable sized modrm/sib chunk is between the start
16104          of the opcode (0x0f0f) and the opcode suffix, we need to do
16105          all the modrm processing first, and don't know until now that
16106          we have a bad opcode.  This necessitates some cleaning up.  */
16107       op_out[0][0] = '\0';
16108       op_out[1][0] = '\0';
16109       BadOp ();
16110     }
16111   mnemonicendp = obufp;
16112 }
16113
16114 static struct op simd_cmp_op[] =
16115 {
16116   { STRING_COMMA_LEN ("eq") },
16117   { STRING_COMMA_LEN ("lt") },
16118   { STRING_COMMA_LEN ("le") },
16119   { STRING_COMMA_LEN ("unord") },
16120   { STRING_COMMA_LEN ("neq") },
16121   { STRING_COMMA_LEN ("nlt") },
16122   { STRING_COMMA_LEN ("nle") },
16123   { STRING_COMMA_LEN ("ord") }
16124 };
16125
16126 static void
16127 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16128 {
16129   unsigned int cmp_type;
16130
16131   FETCH_DATA (the_info, codep + 1);
16132   cmp_type = *codep++ & 0xff;
16133   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16134     {
16135       char suffix [3];
16136       char *p = mnemonicendp - 2;
16137       suffix[0] = p[0];
16138       suffix[1] = p[1];
16139       suffix[2] = '\0';
16140       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16141       mnemonicendp += simd_cmp_op[cmp_type].len;
16142     }
16143   else
16144     {
16145       /* We have a reserved extension byte.  Output it directly.  */
16146       scratchbuf[0] = '$';
16147       print_operand_value (scratchbuf + 1, 1, cmp_type);
16148       oappend_maybe_intel (scratchbuf);
16149       scratchbuf[0] = '\0';
16150     }
16151 }
16152
16153 static void
16154 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16155 {
16156   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
16157   if (!intel_syntax)
16158     {
16159       strcpy (op_out[0], names32[0]);
16160       strcpy (op_out[1], names32[1]);
16161       if (bytemode == eBX_reg)
16162         strcpy (op_out[2], names32[3]);
16163       two_source_ops = 1;
16164     }
16165   /* Skip mod/rm byte.  */
16166   MODRM_CHECK;
16167   codep++;
16168 }
16169
16170 static void
16171 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16172             int sizeflag ATTRIBUTE_UNUSED)
16173 {
16174   /* monitor %{e,r,}ax,%ecx,%edx"  */
16175   if (!intel_syntax)
16176     {
16177       const char **names = (address_mode == mode_64bit
16178                             ? names64 : names32);
16179
16180       if (prefixes & PREFIX_ADDR)
16181         {
16182           /* Remove "addr16/addr32".  */
16183           all_prefixes[last_addr_prefix] = 0;
16184           names = (address_mode != mode_32bit
16185                    ? names32 : names16);
16186           used_prefixes |= PREFIX_ADDR;
16187         }
16188       else if (address_mode == mode_16bit)
16189         names = names16;
16190       strcpy (op_out[0], names[0]);
16191       strcpy (op_out[1], names32[1]);
16192       strcpy (op_out[2], names32[2]);
16193       two_source_ops = 1;
16194     }
16195   /* Skip mod/rm byte.  */
16196   MODRM_CHECK;
16197   codep++;
16198 }
16199
16200 static void
16201 BadOp (void)
16202 {
16203   /* Throw away prefixes and 1st. opcode byte.  */
16204   codep = insn_codep + 1;
16205   oappend ("(bad)");
16206 }
16207
16208 static void
16209 REP_Fixup (int bytemode, int sizeflag)
16210 {
16211   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16212      lods and stos.  */
16213   if (prefixes & PREFIX_REPZ)
16214     all_prefixes[last_repz_prefix] = REP_PREFIX;
16215
16216   switch (bytemode)
16217     {
16218     case al_reg:
16219     case eAX_reg:
16220     case indir_dx_reg:
16221       OP_IMREG (bytemode, sizeflag);
16222       break;
16223     case eDI_reg:
16224       OP_ESreg (bytemode, sizeflag);
16225       break;
16226     case eSI_reg:
16227       OP_DSreg (bytemode, sizeflag);
16228       break;
16229     default:
16230       abort ();
16231       break;
16232     }
16233 }
16234
16235 static void
16236 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16237 {
16238   if ( isa64 != amd64 )
16239     return;
16240
16241   obufp = obuf;
16242   BadOp ();
16243   mnemonicendp = obufp;
16244   ++codep;
16245 }
16246
16247 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16248    "bnd".  */
16249
16250 static void
16251 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16252 {
16253   if (prefixes & PREFIX_REPNZ)
16254     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16255 }
16256
16257 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16258    "notrack".  */
16259
16260 static void
16261 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16262                int sizeflag ATTRIBUTE_UNUSED)
16263 {
16264   if (active_seg_prefix == PREFIX_DS
16265       && (address_mode != mode_64bit || last_data_prefix < 0))
16266     {
16267       /* NOTRACK prefix is only valid on indirect branch instructions.
16268          NB: DATA prefix is unsupported for Intel64.  */
16269       active_seg_prefix = 0;
16270       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16271     }
16272 }
16273
16274 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16275    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16276  */
16277
16278 static void
16279 HLE_Fixup1 (int bytemode, int sizeflag)
16280 {
16281   if (modrm.mod != 3
16282       && (prefixes & PREFIX_LOCK) != 0)
16283     {
16284       if (prefixes & PREFIX_REPZ)
16285         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16286       if (prefixes & PREFIX_REPNZ)
16287         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16288     }
16289
16290   OP_E (bytemode, sizeflag);
16291 }
16292
16293 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16294    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16295  */
16296
16297 static void
16298 HLE_Fixup2 (int bytemode, int sizeflag)
16299 {
16300   if (modrm.mod != 3)
16301     {
16302       if (prefixes & PREFIX_REPZ)
16303         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16304       if (prefixes & PREFIX_REPNZ)
16305         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16306     }
16307
16308   OP_E (bytemode, sizeflag);
16309 }
16310
16311 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16312    "xrelease" for memory operand.  No check for LOCK prefix.   */
16313
16314 static void
16315 HLE_Fixup3 (int bytemode, int sizeflag)
16316 {
16317   if (modrm.mod != 3
16318       && last_repz_prefix > last_repnz_prefix
16319       && (prefixes & PREFIX_REPZ) != 0)
16320     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16321
16322   OP_E (bytemode, sizeflag);
16323 }
16324
16325 static void
16326 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16327 {
16328   USED_REX (REX_W);
16329   if (rex & REX_W)
16330     {
16331       /* Change cmpxchg8b to cmpxchg16b.  */
16332       char *p = mnemonicendp - 2;
16333       mnemonicendp = stpcpy (p, "16b");
16334       bytemode = o_mode;
16335     }
16336   else if ((prefixes & PREFIX_LOCK) != 0)
16337     {
16338       if (prefixes & PREFIX_REPZ)
16339         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16340       if (prefixes & PREFIX_REPNZ)
16341         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16342     }
16343
16344   OP_M (bytemode, sizeflag);
16345 }
16346
16347 static void
16348 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16349 {
16350   const char **names;
16351
16352   if (need_vex)
16353     {
16354       switch (vex.length)
16355         {
16356         case 128:
16357           names = names_xmm;
16358           break;
16359         case 256:
16360           names = names_ymm;
16361           break;
16362         default:
16363           abort ();
16364         }
16365     }
16366   else
16367     names = names_xmm;
16368   oappend (names[reg]);
16369 }
16370
16371 static void
16372 FXSAVE_Fixup (int bytemode, int sizeflag)
16373 {
16374   /* Add proper suffix to "fxsave" and "fxrstor".  */
16375   USED_REX (REX_W);
16376   if (rex & REX_W)
16377     {
16378       char *p = mnemonicendp;
16379       *p++ = '6';
16380       *p++ = '4';
16381       *p = '\0';
16382       mnemonicendp = p;
16383     }
16384   OP_M (bytemode, sizeflag);
16385 }
16386
16387 static void
16388 PCMPESTR_Fixup (int bytemode, int sizeflag)
16389 {
16390   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
16391   if (!intel_syntax)
16392     {
16393       char *p = mnemonicendp;
16394
16395       USED_REX (REX_W);
16396       if (rex & REX_W)
16397         *p++ = 'q';
16398       else if (sizeflag & SUFFIX_ALWAYS)
16399         *p++ = 'l';
16400
16401       *p = '\0';
16402       mnemonicendp = p;
16403     }
16404
16405   OP_EX (bytemode, sizeflag);
16406 }
16407
16408 /* Display the destination register operand for instructions with
16409    VEX. */
16410
16411 static void
16412 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16413 {
16414   int reg;
16415   const char **names;
16416
16417   if (!need_vex)
16418     abort ();
16419
16420   if (!need_vex_reg)
16421     return;
16422
16423   reg = vex.register_specifier;
16424   vex.register_specifier = 0;
16425   if (address_mode != mode_64bit)
16426     reg &= 7;
16427   else if (vex.evex && !vex.v)
16428     reg += 16;
16429
16430   if (bytemode == vex_scalar_mode)
16431     {
16432       oappend (names_xmm[reg]);
16433       return;
16434     }
16435
16436   if (bytemode == tmm_mode)
16437     {
16438       /* All 3 TMM registers must be distinct.  */
16439       if (reg >= 8)
16440         oappend ("(bad)");
16441       else
16442         {
16443           /* This must be the 3rd operand.  */
16444           if (obufp != op_out[2])
16445             abort ();
16446           oappend (names_tmm[reg]);
16447           if (reg == modrm.reg || reg == modrm.rm)
16448             strcpy (obufp, "/(bad)");
16449         }
16450
16451       if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
16452         {
16453           if (modrm.reg <= 8
16454               && (modrm.reg == modrm.rm || modrm.reg == reg))
16455             strcat (op_out[0], "/(bad)");
16456           if (modrm.rm <= 8
16457               && (modrm.rm == modrm.reg || modrm.rm == reg))
16458             strcat (op_out[1], "/(bad)");
16459         }
16460
16461       return;
16462     }
16463
16464   switch (vex.length)
16465     {
16466     case 128:
16467       switch (bytemode)
16468         {
16469         case vex_mode:
16470         case vex128_mode:
16471         case vex_vsib_q_w_dq_mode:
16472         case vex_vsib_q_w_d_mode:
16473           names = names_xmm;
16474           break;
16475         case dq_mode:
16476           if (rex & REX_W)
16477             names = names64;
16478           else
16479             names = names32;
16480           break;
16481         case mask_bd_mode:
16482         case mask_mode:
16483           if (reg > 0x7)
16484             {
16485               oappend ("(bad)");
16486               return;
16487             }
16488           names = names_mask;
16489           break;
16490         default:
16491           abort ();
16492           return;
16493         }
16494       break;
16495     case 256:
16496       switch (bytemode)
16497         {
16498         case vex_mode:
16499         case vex256_mode:
16500           names = names_ymm;
16501           break;
16502         case vex_vsib_q_w_dq_mode:
16503         case vex_vsib_q_w_d_mode:
16504           names = vex.w ? names_ymm : names_xmm;
16505           break;
16506         case mask_bd_mode:
16507         case mask_mode:
16508           if (reg > 0x7)
16509             {
16510               oappend ("(bad)");
16511               return;
16512             }
16513           names = names_mask;
16514           break;
16515         default:
16516           /* See PR binutils/20893 for a reproducer.  */
16517           oappend ("(bad)");
16518           return;
16519         }
16520       break;
16521     case 512:
16522       names = names_zmm;
16523       break;
16524     default:
16525       abort ();
16526       break;
16527     }
16528   oappend (names[reg]);
16529 }
16530
16531 static void
16532 OP_VexW (int bytemode, int sizeflag)
16533 {
16534   OP_VEX (bytemode, sizeflag);
16535
16536   if (vex.w)
16537     {
16538       /* Swap 2nd and 3rd operands.  */
16539       strcpy (scratchbuf, op_out[2]);
16540       strcpy (op_out[2], op_out[1]);
16541       strcpy (op_out[1], scratchbuf);
16542     }
16543 }
16544
16545 static void
16546 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16547 {
16548   int reg;
16549   const char **names = names_xmm;
16550
16551   FETCH_DATA (the_info, codep + 1);
16552   reg = *codep++;
16553
16554   if (bytemode != x_mode && bytemode != scalar_mode)
16555     abort ();
16556
16557   reg >>= 4;
16558   if (address_mode != mode_64bit)
16559     reg &= 7;
16560
16561   if (bytemode == x_mode && vex.length == 256)
16562     names = names_ymm;
16563
16564   oappend (names[reg]);
16565
16566   if (vex.w)
16567     {
16568       /* Swap 3rd and 4th operands.  */
16569       strcpy (scratchbuf, op_out[3]);
16570       strcpy (op_out[3], op_out[2]);
16571       strcpy (op_out[2], scratchbuf);
16572     }
16573 }
16574
16575 static void
16576 OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
16577           int sizeflag ATTRIBUTE_UNUSED)
16578 {
16579   scratchbuf[0] = '$';
16580   print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
16581   oappend_maybe_intel (scratchbuf);
16582 }
16583
16584 static void
16585 OP_EX_Vex (int bytemode, int sizeflag)
16586 {
16587   if (modrm.mod != 3)
16588     need_vex_reg = 0;
16589   OP_EX (bytemode, sizeflag);
16590 }
16591
16592 static void
16593 OP_XMM_Vex (int bytemode, int sizeflag)
16594 {
16595   if (modrm.mod != 3)
16596     need_vex_reg = 0;
16597   OP_XMM (bytemode, sizeflag);
16598 }
16599
16600 static struct op vex_cmp_op[] =
16601 {
16602   { STRING_COMMA_LEN ("eq") },
16603   { STRING_COMMA_LEN ("lt") },
16604   { STRING_COMMA_LEN ("le") },
16605   { STRING_COMMA_LEN ("unord") },
16606   { STRING_COMMA_LEN ("neq") },
16607   { STRING_COMMA_LEN ("nlt") },
16608   { STRING_COMMA_LEN ("nle") },
16609   { STRING_COMMA_LEN ("ord") },
16610   { STRING_COMMA_LEN ("eq_uq") },
16611   { STRING_COMMA_LEN ("nge") },
16612   { STRING_COMMA_LEN ("ngt") },
16613   { STRING_COMMA_LEN ("false") },
16614   { STRING_COMMA_LEN ("neq_oq") },
16615   { STRING_COMMA_LEN ("ge") },
16616   { STRING_COMMA_LEN ("gt") },
16617   { STRING_COMMA_LEN ("true") },
16618   { STRING_COMMA_LEN ("eq_os") },
16619   { STRING_COMMA_LEN ("lt_oq") },
16620   { STRING_COMMA_LEN ("le_oq") },
16621   { STRING_COMMA_LEN ("unord_s") },
16622   { STRING_COMMA_LEN ("neq_us") },
16623   { STRING_COMMA_LEN ("nlt_uq") },
16624   { STRING_COMMA_LEN ("nle_uq") },
16625   { STRING_COMMA_LEN ("ord_s") },
16626   { STRING_COMMA_LEN ("eq_us") },
16627   { STRING_COMMA_LEN ("nge_uq") },
16628   { STRING_COMMA_LEN ("ngt_uq") },
16629   { STRING_COMMA_LEN ("false_os") },
16630   { STRING_COMMA_LEN ("neq_os") },
16631   { STRING_COMMA_LEN ("ge_oq") },
16632   { STRING_COMMA_LEN ("gt_oq") },
16633   { STRING_COMMA_LEN ("true_us") },
16634 };
16635
16636 static void
16637 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16638 {
16639   unsigned int cmp_type;
16640
16641   FETCH_DATA (the_info, codep + 1);
16642   cmp_type = *codep++ & 0xff;
16643   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16644     {
16645       char suffix [3];
16646       char *p = mnemonicendp - 2;
16647       suffix[0] = p[0];
16648       suffix[1] = p[1];
16649       suffix[2] = '\0';
16650       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16651       mnemonicendp += vex_cmp_op[cmp_type].len;
16652     }
16653   else
16654     {
16655       /* We have a reserved extension byte.  Output it directly.  */
16656       scratchbuf[0] = '$';
16657       print_operand_value (scratchbuf + 1, 1, cmp_type);
16658       oappend_maybe_intel (scratchbuf);
16659       scratchbuf[0] = '\0';
16660     }
16661 }
16662
16663 static void
16664 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16665              int sizeflag ATTRIBUTE_UNUSED)
16666 {
16667   unsigned int cmp_type;
16668
16669   if (!vex.evex)
16670     abort ();
16671
16672   FETCH_DATA (the_info, codep + 1);
16673   cmp_type = *codep++ & 0xff;
16674   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16675      If it's the case, print suffix, otherwise - print the immediate.  */
16676   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16677       && cmp_type != 3
16678       && cmp_type != 7)
16679     {
16680       char suffix [3];
16681       char *p = mnemonicendp - 2;
16682
16683       /* vpcmp* can have both one- and two-lettered suffix.  */
16684       if (p[0] == 'p')
16685         {
16686           p++;
16687           suffix[0] = p[0];
16688           suffix[1] = '\0';
16689         }
16690       else
16691         {
16692           suffix[0] = p[0];
16693           suffix[1] = p[1];
16694           suffix[2] = '\0';
16695         }
16696
16697       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16698       mnemonicendp += simd_cmp_op[cmp_type].len;
16699     }
16700   else
16701     {
16702       /* We have a reserved extension byte.  Output it directly.  */
16703       scratchbuf[0] = '$';
16704       print_operand_value (scratchbuf + 1, 1, cmp_type);
16705       oappend_maybe_intel (scratchbuf);
16706       scratchbuf[0] = '\0';
16707     }
16708 }
16709
16710 static const struct op xop_cmp_op[] =
16711 {
16712   { STRING_COMMA_LEN ("lt") },
16713   { STRING_COMMA_LEN ("le") },
16714   { STRING_COMMA_LEN ("gt") },
16715   { STRING_COMMA_LEN ("ge") },
16716   { STRING_COMMA_LEN ("eq") },
16717   { STRING_COMMA_LEN ("neq") },
16718   { STRING_COMMA_LEN ("false") },
16719   { STRING_COMMA_LEN ("true") }
16720 };
16721
16722 static void
16723 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16724              int sizeflag ATTRIBUTE_UNUSED)
16725 {
16726   unsigned int cmp_type;
16727
16728   FETCH_DATA (the_info, codep + 1);
16729   cmp_type = *codep++ & 0xff;
16730   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16731     {
16732       char suffix[3];
16733       char *p = mnemonicendp - 2;
16734
16735       /* vpcom* can have both one- and two-lettered suffix.  */
16736       if (p[0] == 'm')
16737         {
16738           p++;
16739           suffix[0] = p[0];
16740           suffix[1] = '\0';
16741         }
16742       else
16743         {
16744           suffix[0] = p[0];
16745           suffix[1] = p[1];
16746           suffix[2] = '\0';
16747         }
16748
16749       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16750       mnemonicendp += xop_cmp_op[cmp_type].len;
16751     }
16752   else
16753     {
16754       /* We have a reserved extension byte.  Output it directly.  */
16755       scratchbuf[0] = '$';
16756       print_operand_value (scratchbuf + 1, 1, cmp_type);
16757       oappend_maybe_intel (scratchbuf);
16758       scratchbuf[0] = '\0';
16759     }
16760 }
16761
16762 static const struct op pclmul_op[] =
16763 {
16764   { STRING_COMMA_LEN ("lql") },
16765   { STRING_COMMA_LEN ("hql") },
16766   { STRING_COMMA_LEN ("lqh") },
16767   { STRING_COMMA_LEN ("hqh") }
16768 };
16769
16770 static void
16771 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16772               int sizeflag ATTRIBUTE_UNUSED)
16773 {
16774   unsigned int pclmul_type;
16775
16776   FETCH_DATA (the_info, codep + 1);
16777   pclmul_type = *codep++ & 0xff;
16778   switch (pclmul_type)
16779     {
16780     case 0x10:
16781       pclmul_type = 2;
16782       break;
16783     case 0x11:
16784       pclmul_type = 3;
16785       break;
16786     default:
16787       break;
16788     }
16789   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16790     {
16791       char suffix [4];
16792       char *p = mnemonicendp - 3;
16793       suffix[0] = p[0];
16794       suffix[1] = p[1];
16795       suffix[2] = p[2];
16796       suffix[3] = '\0';
16797       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16798       mnemonicendp += pclmul_op[pclmul_type].len;
16799     }
16800   else
16801     {
16802       /* We have a reserved extension byte.  Output it directly.  */
16803       scratchbuf[0] = '$';
16804       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16805       oappend_maybe_intel (scratchbuf);
16806       scratchbuf[0] = '\0';
16807     }
16808 }
16809
16810 static void
16811 MOVBE_Fixup (int bytemode, int sizeflag)
16812 {
16813   /* Add proper suffix to "movbe".  */
16814   char *p = mnemonicendp;
16815
16816   switch (bytemode)
16817     {
16818     case v_mode:
16819       if (intel_syntax)
16820         goto skip;
16821
16822       USED_REX (REX_W);
16823       if (sizeflag & SUFFIX_ALWAYS)
16824         {
16825           if (rex & REX_W)
16826             *p++ = 'q';
16827           else
16828             {
16829               if (sizeflag & DFLAG)
16830                 *p++ = 'l';
16831               else
16832                 *p++ = 'w';
16833               used_prefixes |= (prefixes & PREFIX_DATA);
16834             }
16835         }
16836       break;
16837     default:
16838       oappend (INTERNAL_DISASSEMBLER_ERROR);
16839       break;
16840     }
16841   mnemonicendp = p;
16842   *p = '\0';
16843
16844  skip:
16845   OP_M (bytemode, sizeflag);
16846 }
16847
16848 static void
16849 MOVSXD_Fixup (int bytemode, int sizeflag)
16850 {
16851   /* Add proper suffix to "movsxd".  */
16852   char *p = mnemonicendp;
16853
16854   switch (bytemode)
16855     {
16856     case movsxd_mode:
16857       if (intel_syntax)
16858         {
16859           *p++ = 'x';
16860           *p++ = 'd';
16861           goto skip;
16862         }
16863
16864       USED_REX (REX_W);
16865       if (rex & REX_W)
16866         {
16867           *p++ = 'l';
16868           *p++ = 'q';
16869         }
16870       else
16871         {
16872           *p++ = 'x';
16873           *p++ = 'd';
16874         }
16875       break;
16876     default:
16877       oappend (INTERNAL_DISASSEMBLER_ERROR);
16878       break;
16879     }
16880
16881  skip:
16882   mnemonicendp = p;
16883   *p = '\0';
16884   OP_E (bytemode, sizeflag);
16885 }
16886
16887 static void
16888 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16889 {
16890   if (!vex.evex
16891       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16892     abort ();
16893
16894   USED_REX (REX_R);
16895   if ((rex & REX_R) != 0 || !vex.r)
16896     {
16897       BadOp ();
16898       return;
16899     }
16900
16901   oappend (names_mask [modrm.reg]);
16902 }
16903
16904 static void
16905 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16906 {
16907   if (modrm.mod == 3 && vex.b)
16908     switch (bytemode)
16909       {
16910       case evex_rounding_64_mode:
16911         if (address_mode != mode_64bit)
16912           {
16913             oappend ("(bad)");
16914             break;
16915           }
16916         /* Fall through.  */
16917       case evex_rounding_mode:
16918         oappend (names_rounding[vex.ll]);
16919         break;
16920       case evex_sae_mode:
16921         oappend ("{sae}");
16922         break;
16923       default:
16924         abort ();
16925         break;
16926       }
16927 }