opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
   4    Free Software Foundation, Inc.
   5
   6    This file is part of the GNU opcodes library.
   7
   8    This library is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    It is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23
  24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  25    July 1988
  26     modified by John Hassey (hassey@dg-rtp.dg.com)
  27     x86-64 support added by Jan Hubicka (jh@suse.cz)
  28     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  29
  30 /* The main tables describing the instructions is essentially a copy
  31    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  32    Programmers Manual.  Usually, there is a capital letter, followed
  33    by a small letter.  The capital letter tell the addressing mode,
  34    and the small letter tells about the operand size.  Refer to
  35    the Intel manual for details.  */
  36
  37 #include "sysdep.h"
  38 #include "dis-asm.h"
  39 #include "opintl.h"
  40 #include "opcode/i386.h"
  41 #include "libiberty.h"
  42
  43 #include <setjmp.h>
  44
  45 static int print_insn (bfd_vma, disassemble_info *);
  46 static void dofloat (int);
  47 static void OP_ST (int, int);
  48 static void OP_STi (int, int);
  49 static int putop (const char *, int);
  50 static void oappend (const char *);
  51 static void append_seg (void);
  52 static void OP_indirE (int, int);
  53 static void print_operand_value (char *, int, bfd_vma);
  54 static void OP_E_register (int, int);
  55 static void OP_E_memory (int, int);
  56 static void print_displacement (char *, bfd_vma);
  57 static void OP_E (int, int);
  58 static void OP_G (int, int);
  59 static bfd_vma get64 (void);
  60 static bfd_signed_vma get32 (void);
  61 static bfd_signed_vma get32s (void);
  62 static int get16 (void);
  63 static void set_op (bfd_vma, int);
  64 static void OP_Skip_MODRM (int, int);
  65 static void OP_REG (int, int);
  66 static void OP_IMREG (int, int);
  67 static void OP_I (int, int);
  68 static void OP_I64 (int, int);
  69 static void OP_sI (int, int);
  70 static void OP_J (int, int);
  71 static void OP_SEG (int, int);
  72 static void OP_DIR (int, int);
  73 static void OP_OFF (int, int);
  74 static void OP_OFF64 (int, int);
  75 static void ptr_reg (int, int);
  76 static void OP_ESreg (int, int);
  77 static void OP_DSreg (int, int);
  78 static void OP_C (int, int);
  79 static void OP_D (int, int);
  80 static void OP_T (int, int);
  81 static void OP_R (int, int);
  82 static void OP_MMX (int, int);
  83 static void OP_XMM (int, int);
  84 static void OP_EM (int, int);
  85 static void OP_EX (int, int);
  86 static void OP_EMC (int,int);
  87 static void OP_MXC (int,int);
  88 static void OP_MS (int, int);
  89 static void OP_XS (int, int);
  90 static void OP_M (int, int);
  91 static void OP_VEX (int, int);
  92 static void OP_EX_Vex (int, int);
  93 static void OP_EX_VexW (int, int);
  94 static void OP_XMM_Vex (int, int);
  95 static void OP_XMM_VexW (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void CMPXCHG8B_Fixup (int, int);
 111 static void XMM_Fixup (int, int);
 112 static void CRC32_Fixup (int, int);
 113 static void FXSAVE_Fixup (int, int);
 114 static void OP_LWPCB_E (int, int);
 115 static void OP_LWP_E (int, int);
 116 static void OP_LWP_I (int, int);
 117 static void OP_Vex_2src_1 (int, int);
 118 static void OP_Vex_2src_2 (int, int);
 119
 120 static void MOVBE_Fixup (int, int);
 121
 122 struct dis_private {
 123   /* Points to first byte not fetched.  */
 124   bfd_byte *max_fetched;
 125   bfd_byte the_buffer[MAX_MNEM_SIZE];
 126   bfd_vma insn_start;
 127   int orig_sizeflag;
 128   jmp_buf bailout;
 129 };
 130
 131 enum address_mode
 132 {
 133   mode_16bit,
 134   mode_32bit,
 135   mode_64bit
 136 };
 137
 138 enum address_mode address_mode;
 139
 140 /* Flags for the prefixes for the current instruction.  See below.  */
 141 static int prefixes;
 142
 143 /* REX prefix the current instruction.  See below.  */
 144 static int rex;
 145 /* Bits of REX we've already used.  */
 146 static int rex_used;
 147 /* REX bits in original REX prefix ignored.  */
 148 static int rex_ignored;
 149 /* Mark parts used in the REX prefix.  When we are testing for
 150    empty prefix (for 8bit register REX extension), just mask it
 151    out.  Otherwise test for REX bit is excuse for existence of REX
 152    only in case value is nonzero.  */
 153 #define USED_REX(value)                                 \
 154   {                                                     \
 155     if (value)                                          \
 156       {                                                 \
 157         if ((rex & value))                              \
 158           rex_used |= (value) | REX_OPCODE;             \
 159       }                                                 \
 160     else                                                \
 161       rex_used |= REX_OPCODE;                           \
 162   }
 163
 164 /* Flags for prefixes which we somehow handled when printing the
 165    current instruction.  */
 166 static int used_prefixes;
 167
 168 /* Flags stored in PREFIXES.  */
 169 #define PREFIX_REPZ 1
 170 #define PREFIX_REPNZ 2
 171 #define PREFIX_LOCK 4
 172 #define PREFIX_CS 8
 173 #define PREFIX_SS 0x10
 174 #define PREFIX_DS 0x20
 175 #define PREFIX_ES 0x40
 176 #define PREFIX_FS 0x80
 177 #define PREFIX_GS 0x100
 178 #define PREFIX_DATA 0x200
 179 #define PREFIX_ADDR 0x400
 180 #define PREFIX_FWAIT 0x800
 181
 182 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 183    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 184    on error.  */
 185 #define FETCH_DATA(info, addr) \
 186   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 187    ? 1 : fetch_data ((info), (addr)))
 188
 189 static int
 190 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 191 {
 192   int status;
 193   struct dis_private *priv = (struct dis_private *) info->private_data;
 194   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 195
 196   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 197     status = (*info->read_memory_func) (start,
 198                                         priv->max_fetched,
 199                                         addr - priv->max_fetched,
 200                                         info);
 201   else
 202     status = -1;
 203   if (status != 0)
 204     {
 205       /* If we did manage to read at least one byte, then
 206          print_insn_i386 will do something sensible.  Otherwise, print
 207          an error.  We do that here because this is where we know
 208          STATUS.  */
 209       if (priv->max_fetched == priv->the_buffer)
 210         (*info->memory_error_func) (status, start, info);
 211       longjmp (priv->bailout, 1);
 212     }
 213   else
 214     priv->max_fetched = addr;
 215   return 1;
 216 }
 217
 218 #define XX { NULL, 0 }
 219 #define Bad_Opcode NULL, { { NULL, 0 } }
 220
 221 #define Eb { OP_E, b_mode }
 222 #define EbS { OP_E, b_swap_mode }
 223 #define Ev { OP_E, v_mode }
 224 #define EvS { OP_E, v_swap_mode }
 225 #define Ed { OP_E, d_mode }
 226 #define Edq { OP_E, dq_mode }
 227 #define Edqw { OP_E, dqw_mode }
 228 #define Edqb { OP_E, dqb_mode }
 229 #define Edqd { OP_E, dqd_mode }
 230 #define Eq { OP_E, q_mode }
 231 #define indirEv { OP_indirE, stack_v_mode }
 232 #define indirEp { OP_indirE, f_mode }
 233 #define stackEv { OP_E, stack_v_mode }
 234 #define Em { OP_E, m_mode }
 235 #define Ew { OP_E, w_mode }
 236 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 237 #define Ma { OP_M, a_mode }
 238 #define Mb { OP_M, b_mode }
 239 #define Md { OP_M, d_mode }
 240 #define Mo { OP_M, o_mode }
 241 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 242 #define Mq { OP_M, q_mode }
 243 #define Mx { OP_M, x_mode }
 244 #define Mxmm { OP_M, xmm_mode }
 245 #define Gb { OP_G, b_mode }
 246 #define Gv { OP_G, v_mode }
 247 #define Gd { OP_G, d_mode }
 248 #define Gdq { OP_G, dq_mode }
 249 #define Gm { OP_G, m_mode }
 250 #define Gw { OP_G, w_mode }
 251 #define Rd { OP_R, d_mode }
 252 #define Rm { OP_R, m_mode }
 253 #define Ib { OP_I, b_mode }
 254 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 255 #define Iv { OP_I, v_mode }
 256 #define Iq { OP_I, q_mode }
 257 #define Iv64 { OP_I64, v_mode }
 258 #define Iw { OP_I, w_mode }
 259 #define I1 { OP_I, const_1_mode }
 260 #define Jb { OP_J, b_mode }
 261 #define Jv { OP_J, v_mode }
 262 #define Cm { OP_C, m_mode }
 263 #define Dm { OP_D, m_mode }
 264 #define Td { OP_T, d_mode }
 265 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 266
 267 #define RMeAX { OP_REG, eAX_reg }
 268 #define RMeBX { OP_REG, eBX_reg }
 269 #define RMeCX { OP_REG, eCX_reg }
 270 #define RMeDX { OP_REG, eDX_reg }
 271 #define RMeSP { OP_REG, eSP_reg }
 272 #define RMeBP { OP_REG, eBP_reg }
 273 #define RMeSI { OP_REG, eSI_reg }
 274 #define RMeDI { OP_REG, eDI_reg }
 275 #define RMrAX { OP_REG, rAX_reg }
 276 #define RMrBX { OP_REG, rBX_reg }
 277 #define RMrCX { OP_REG, rCX_reg }
 278 #define RMrDX { OP_REG, rDX_reg }
 279 #define RMrSP { OP_REG, rSP_reg }
 280 #define RMrBP { OP_REG, rBP_reg }
 281 #define RMrSI { OP_REG, rSI_reg }
 282 #define RMrDI { OP_REG, rDI_reg }
 283 #define RMAL { OP_REG, al_reg }
 284 #define RMAL { OP_REG, al_reg }
 285 #define RMCL { OP_REG, cl_reg }
 286 #define RMDL { OP_REG, dl_reg }
 287 #define RMBL { OP_REG, bl_reg }
 288 #define RMAH { OP_REG, ah_reg }
 289 #define RMCH { OP_REG, ch_reg }
 290 #define RMDH { OP_REG, dh_reg }
 291 #define RMBH { OP_REG, bh_reg }
 292 #define RMAX { OP_REG, ax_reg }
 293 #define RMDX { OP_REG, dx_reg }
 294
 295 #define eAX { OP_IMREG, eAX_reg }
 296 #define eBX { OP_IMREG, eBX_reg }
 297 #define eCX { OP_IMREG, eCX_reg }
 298 #define eDX { OP_IMREG, eDX_reg }
 299 #define eSP { OP_IMREG, eSP_reg }
 300 #define eBP { OP_IMREG, eBP_reg }
 301 #define eSI { OP_IMREG, eSI_reg }
 302 #define eDI { OP_IMREG, eDI_reg }
 303 #define AL { OP_IMREG, al_reg }
 304 #define CL { OP_IMREG, cl_reg }
 305 #define DL { OP_IMREG, dl_reg }
 306 #define BL { OP_IMREG, bl_reg }
 307 #define AH { OP_IMREG, ah_reg }
 308 #define CH { OP_IMREG, ch_reg }
 309 #define DH { OP_IMREG, dh_reg }
 310 #define BH { OP_IMREG, bh_reg }
 311 #define AX { OP_IMREG, ax_reg }
 312 #define DX { OP_IMREG, dx_reg }
 313 #define zAX { OP_IMREG, z_mode_ax_reg }
 314 #define indirDX { OP_IMREG, indir_dx_reg }
 315
 316 #define Sw { OP_SEG, w_mode }
 317 #define Sv { OP_SEG, v_mode }
 318 #define Ap { OP_DIR, 0 }
 319 #define Ob { OP_OFF64, b_mode }
 320 #define Ov { OP_OFF64, v_mode }
 321 #define Xb { OP_DSreg, eSI_reg }
 322 #define Xv { OP_DSreg, eSI_reg }
 323 #define Xz { OP_DSreg, eSI_reg }
 324 #define Yb { OP_ESreg, eDI_reg }
 325 #define Yv { OP_ESreg, eDI_reg }
 326 #define DSBX { OP_DSreg, eBX_reg }
 327
 328 #define es { OP_REG, es_reg }
 329 #define ss { OP_REG, ss_reg }
 330 #define cs { OP_REG, cs_reg }
 331 #define ds { OP_REG, ds_reg }
 332 #define fs { OP_REG, fs_reg }
 333 #define gs { OP_REG, gs_reg }
 334
 335 #define MX { OP_MMX, 0 }
 336 #define XM { OP_XMM, 0 }
 337 #define XMM { OP_XMM, xmm_mode }
 338 #define EM { OP_EM, v_mode }
 339 #define EMS { OP_EM, v_swap_mode }
 340 #define EMd { OP_EM, d_mode }
 341 #define EMx { OP_EM, x_mode }
 342 #define EXw { OP_EX, w_mode }
 343 #define EXd { OP_EX, d_mode }
 344 #define EXdS { OP_EX, d_swap_mode }
 345 #define EXq { OP_EX, q_mode }
 346 #define EXqS { OP_EX, q_swap_mode }
 347 #define EXx { OP_EX, x_mode }
 348 #define EXxS { OP_EX, x_swap_mode }
 349 #define EXxmm { OP_EX, xmm_mode }
 350 #define EXxmmq { OP_EX, xmmq_mode }
 351 #define EXymmq { OP_EX, ymmq_mode }
 352 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 353 #define MS { OP_MS, v_mode }
 354 #define XS { OP_XS, v_mode }
 355 #define EMCq { OP_EMC, q_mode }
 356 #define MXC { OP_MXC, 0 }
 357 #define OPSUF { OP_3DNowSuffix, 0 }
 358 #define CMP { CMP_Fixup, 0 }
 359 #define XMM0 { XMM_Fixup, 0 }
 360 #define FXSAVE { FXSAVE_Fixup, 0 }
 361 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 362 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 363
 364 #define Vex { OP_VEX, vex_mode }
 365 #define Vex128 { OP_VEX, vex128_mode }
 366 #define Vex256 { OP_VEX, vex256_mode }
 367 #define VexI4 { VEXI4_Fixup, 0}
 368 #define EXdVex { OP_EX_Vex, d_mode }
 369 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 370 #define EXqVex { OP_EX_Vex, q_mode }
 371 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 372 #define EXVexW { OP_EX_VexW, x_mode }
 373 #define EXdVexW { OP_EX_VexW, d_mode }
 374 #define EXqVexW { OP_EX_VexW, q_mode }
 375 #define XMVex { OP_XMM_Vex, 0 }
 376 #define XMVexW { OP_XMM_VexW, 0 }
 377 #define XMVexI4 { OP_REG_VexI4, x_mode }
 378 #define PCLMUL { PCLMUL_Fixup, 0 }
 379 #define VZERO { VZERO_Fixup, 0 }
 380 #define VCMP { VCMP_Fixup, 0 }
 381
 382 /* Used handle "rep" prefix for string instructions.  */
 383 #define Xbr { REP_Fixup, eSI_reg }
 384 #define Xvr { REP_Fixup, eSI_reg }
 385 #define Ybr { REP_Fixup, eDI_reg }
 386 #define Yvr { REP_Fixup, eDI_reg }
 387 #define Yzr { REP_Fixup, eDI_reg }
 388 #define indirDXr { REP_Fixup, indir_dx_reg }
 389 #define ALr { REP_Fixup, al_reg }
 390 #define eAXr { REP_Fixup, eAX_reg }
 391
 392 #define cond_jump_flag { NULL, cond_jump_mode }
 393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 394
 395 /* bits in sizeflag */
 396 #define SUFFIX_ALWAYS 4
 397 #define AFLAG 2
 398 #define DFLAG 1
 399
 400 enum
 401 {
 402   /* byte operand */
 403   b_mode = 1,
 404   /* byte operand with operand swapped */
 405   b_swap_mode,
 406   /* operand size depends on prefixes */
 407   v_mode,
 408   /* operand size depends on prefixes with operand swapped */
 409   v_swap_mode,
 410   /* word operand */
 411   w_mode,
 412   /* double word operand  */
 413   d_mode,
 414   /* double word operand with operand swapped */
 415   d_swap_mode,
 416   /* quad word operand */
 417   q_mode,
 418   /* quad word operand with operand swapped */
 419   q_swap_mode,
 420   /* ten-byte operand */
 421   t_mode,
 422   /* 16-byte XMM or 32-byte YMM operand */
 423   x_mode,
 424   /* 16-byte XMM or 32-byte YMM operand with operand swapped */
 425   x_swap_mode,
 426   /* 16-byte XMM operand */
 427   xmm_mode,
 428   /* 16-byte XMM or quad word operand */
 429   xmmq_mode,
 430   /* 32-byte YMM or quad word operand */
 431   ymmq_mode,
 432   /* d_mode in 32bit, q_mode in 64bit mode.  */
 433   m_mode,
 434   /* pair of v_mode operands */
 435   a_mode,
 436   cond_jump_mode,
 437   loop_jcxz_mode,
 438   /* operand size depends on REX prefixes.  */
 439   dq_mode,
 440   /* registers like dq_mode, memory like w_mode.  */
 441   dqw_mode,
 442   /* 4- or 6-byte pointer operand */
 443   f_mode,
 444   const_1_mode,
 445   /* v_mode for stack-related opcodes.  */
 446   stack_v_mode,
 447   /* non-quad operand size depends on prefixes */
 448   z_mode,
 449   /* 16-byte operand */
 450   o_mode,
 451   /* registers like dq_mode, memory like b_mode.  */
 452   dqb_mode,
 453   /* registers like dq_mode, memory like d_mode.  */
 454   dqd_mode,
 455   /* normal vex mode */
 456   vex_mode,
 457   /* 128bit vex mode */
 458   vex128_mode,
 459   /* 256bit vex mode */
 460   vex256_mode,
 461   /* operand size depends on the VEX.W bit.  */
 462   vex_w_dq_mode,
 463
 464   es_reg,
 465   cs_reg,
 466   ss_reg,
 467   ds_reg,
 468   fs_reg,
 469   gs_reg,
 470
 471   eAX_reg,
 472   eCX_reg,
 473   eDX_reg,
 474   eBX_reg,
 475   eSP_reg,
 476   eBP_reg,
 477   eSI_reg,
 478   eDI_reg,
 479
 480   al_reg,
 481   cl_reg,
 482   dl_reg,
 483   bl_reg,
 484   ah_reg,
 485   ch_reg,
 486   dh_reg,
 487   bh_reg,
 488
 489   ax_reg,
 490   cx_reg,
 491   dx_reg,
 492   bx_reg,
 493   sp_reg,
 494   bp_reg,
 495   si_reg,
 496   di_reg,
 497
 498   rAX_reg,
 499   rCX_reg,
 500   rDX_reg,
 501   rBX_reg,
 502   rSP_reg,
 503   rBP_reg,
 504   rSI_reg,
 505   rDI_reg,
 506
 507   z_mode_ax_reg,
 508   indir_dx_reg
 509 };
 510
 511 enum
 512 {
 513   FLOATCODE = 1,
 514   USE_REG_TABLE,
 515   USE_MOD_TABLE,
 516   USE_RM_TABLE,
 517   USE_PREFIX_TABLE,
 518   USE_X86_64_TABLE,
 519   USE_3BYTE_TABLE,
 520   USE_XOP_8F_TABLE,
 521   USE_VEX_C4_TABLE,
 522   USE_VEX_C5_TABLE,
 523   USE_VEX_LEN_TABLE,
 524   USE_VEX_W_TABLE
 525 };
 526
 527 #define FLOAT                   NULL, { { NULL, FLOATCODE } }
 528
 529 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }
 530 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 531 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 532 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 533 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 534 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 535 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 536 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 537 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 538 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 539 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 540 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 541
 542 enum
 543 {
 544   REG_80 = 0,
 545   REG_81,
 546   REG_82,
 547   REG_8F,
 548   REG_C0,
 549   REG_C1,
 550   REG_C6,
 551   REG_C7,
 552   REG_D0,
 553   REG_D1,
 554   REG_D2,
 555   REG_D3,
 556   REG_F6,
 557   REG_F7,
 558   REG_FE,
 559   REG_FF,
 560   REG_0F00,
 561   REG_0F01,
 562   REG_0F0D,
 563   REG_0F18,
 564   REG_0F71,
 565   REG_0F72,
 566   REG_0F73,
 567   REG_0FA6,
 568   REG_0FA7,
 569   REG_0FAE,
 570   REG_0FBA,
 571   REG_0FC7,
 572   REG_VEX_71,
 573   REG_VEX_72,
 574   REG_VEX_73,
 575   REG_VEX_AE,
 576   REG_XOP_LWPCB,
 577   REG_XOP_LWP
 578 };
 579
 580 enum
 581 {
 582   MOD_8D = 0,
 583   MOD_0F01_REG_0,
 584   MOD_0F01_REG_1,
 585   MOD_0F01_REG_2,
 586   MOD_0F01_REG_3,
 587   MOD_0F01_REG_7,
 588   MOD_0F12_PREFIX_0,
 589   MOD_0F13,
 590   MOD_0F16_PREFIX_0,
 591   MOD_0F17,
 592   MOD_0F18_REG_0,
 593   MOD_0F18_REG_1,
 594   MOD_0F18_REG_2,
 595   MOD_0F18_REG_3,
 596   MOD_0F20,
 597   MOD_0F21,
 598   MOD_0F22,
 599   MOD_0F23,
 600   MOD_0F24,
 601   MOD_0F26,
 602   MOD_0F2B_PREFIX_0,
 603   MOD_0F2B_PREFIX_1,
 604   MOD_0F2B_PREFIX_2,
 605   MOD_0F2B_PREFIX_3,
 606   MOD_0F51,
 607   MOD_0F71_REG_2,
 608   MOD_0F71_REG_4,
 609   MOD_0F71_REG_6,
 610   MOD_0F72_REG_2,
 611   MOD_0F72_REG_4,
 612   MOD_0F72_REG_6,
 613   MOD_0F73_REG_2,
 614   MOD_0F73_REG_3,
 615   MOD_0F73_REG_6,
 616   MOD_0F73_REG_7,
 617   MOD_0FAE_REG_0,
 618   MOD_0FAE_REG_1,
 619   MOD_0FAE_REG_2,
 620   MOD_0FAE_REG_3,
 621   MOD_0FAE_REG_4,
 622   MOD_0FAE_REG_5,
 623   MOD_0FAE_REG_6,
 624   MOD_0FAE_REG_7,
 625   MOD_0FB2,
 626   MOD_0FB4,
 627   MOD_0FB5,
 628   MOD_0FC7_REG_6,
 629   MOD_0FC7_REG_7,
 630   MOD_0FD7,
 631   MOD_0FE7_PREFIX_2,
 632   MOD_0FF0_PREFIX_3,
 633   MOD_0F382A_PREFIX_2,
 634   MOD_62_32BIT,
 635   MOD_C4_32BIT,
 636   MOD_C5_32BIT,
 637   MOD_VEX_12_PREFIX_0,
 638   MOD_VEX_13,
 639   MOD_VEX_16_PREFIX_0,
 640   MOD_VEX_17,
 641   MOD_VEX_2B,
 642   MOD_VEX_50,
 643   MOD_VEX_71_REG_2,
 644   MOD_VEX_71_REG_4,
 645   MOD_VEX_71_REG_6,
 646   MOD_VEX_72_REG_2,
 647   MOD_VEX_72_REG_4,
 648   MOD_VEX_72_REG_6,
 649   MOD_VEX_73_REG_2,
 650   MOD_VEX_73_REG_3,
 651   MOD_VEX_73_REG_6,
 652   MOD_VEX_73_REG_7,
 653   MOD_VEX_AE_REG_2,
 654   MOD_VEX_AE_REG_3,
 655   MOD_VEX_D7_PREFIX_2,
 656   MOD_VEX_E7_PREFIX_2,
 657   MOD_VEX_F0_PREFIX_3,
 658   MOD_VEX_3818_PREFIX_2,
 659   MOD_VEX_3819_PREFIX_2,
 660   MOD_VEX_381A_PREFIX_2,
 661   MOD_VEX_382A_PREFIX_2,
 662   MOD_VEX_382C_PREFIX_2,
 663   MOD_VEX_382D_PREFIX_2,
 664   MOD_VEX_382E_PREFIX_2,
 665   MOD_VEX_382F_PREFIX_2
 666 };
 667
 668 enum
 669 {
 670   RM_0F01_REG_0 = 0,
 671   RM_0F01_REG_1,
 672   RM_0F01_REG_2,
 673   RM_0F01_REG_3,
 674   RM_0F01_REG_7,
 675   RM_0FAE_REG_5,
 676   RM_0FAE_REG_6,
 677   RM_0FAE_REG_7
 678 };
 679
 680 enum
 681 {
 682   PREFIX_90 = 0,
 683   PREFIX_0F10,
 684   PREFIX_0F11,
 685   PREFIX_0F12,
 686   PREFIX_0F16,
 687   PREFIX_0F2A,
 688   PREFIX_0F2B,
 689   PREFIX_0F2C,
 690   PREFIX_0F2D,
 691   PREFIX_0F2E,
 692   PREFIX_0F2F,
 693   PREFIX_0F51,
 694   PREFIX_0F52,
 695   PREFIX_0F53,
 696   PREFIX_0F58,
 697   PREFIX_0F59,
 698   PREFIX_0F5A,
 699   PREFIX_0F5B,
 700   PREFIX_0F5C,
 701   PREFIX_0F5D,
 702   PREFIX_0F5E,
 703   PREFIX_0F5F,
 704   PREFIX_0F60,
 705   PREFIX_0F61,
 706   PREFIX_0F62,
 707   PREFIX_0F6C,
 708   PREFIX_0F6D,
 709   PREFIX_0F6F,
 710   PREFIX_0F70,
 711   PREFIX_0F73_REG_3,
 712   PREFIX_0F73_REG_7,
 713   PREFIX_0F78,
 714   PREFIX_0F79,
 715   PREFIX_0F7C,
 716   PREFIX_0F7D,
 717   PREFIX_0F7E,
 718   PREFIX_0F7F,
 719   PREFIX_0FB8,
 720   PREFIX_0FBD,
 721   PREFIX_0FC2,
 722   PREFIX_0FC3,
 723   PREFIX_0FC7_REG_6,
 724   PREFIX_0FD0,
 725   PREFIX_0FD6,
 726   PREFIX_0FE6,
 727   PREFIX_0FE7,
 728   PREFIX_0FF0,
 729   PREFIX_0FF7,
 730   PREFIX_0F3810,
 731   PREFIX_0F3814,
 732   PREFIX_0F3815,
 733   PREFIX_0F3817,
 734   PREFIX_0F3820,
 735   PREFIX_0F3821,
 736   PREFIX_0F3822,
 737   PREFIX_0F3823,
 738   PREFIX_0F3824,
 739   PREFIX_0F3825,
 740   PREFIX_0F3828,
 741   PREFIX_0F3829,
 742   PREFIX_0F382A,
 743   PREFIX_0F382B,
 744   PREFIX_0F3830,
 745   PREFIX_0F3831,
 746   PREFIX_0F3832,
 747   PREFIX_0F3833,
 748   PREFIX_0F3834,
 749   PREFIX_0F3835,
 750   PREFIX_0F3837,
 751   PREFIX_0F3838,
 752   PREFIX_0F3839,
 753   PREFIX_0F383A,
 754   PREFIX_0F383B,
 755   PREFIX_0F383C,
 756   PREFIX_0F383D,
 757   PREFIX_0F383E,
 758   PREFIX_0F383F,
 759   PREFIX_0F3840,
 760   PREFIX_0F3841,
 761   PREFIX_0F3880,
 762   PREFIX_0F3881,
 763   PREFIX_0F38DB,
 764   PREFIX_0F38DC,
 765   PREFIX_0F38DD,
 766   PREFIX_0F38DE,
 767   PREFIX_0F38DF,
 768   PREFIX_0F38F0,
 769   PREFIX_0F38F1,
 770   PREFIX_0F3A08,
 771   PREFIX_0F3A09,
 772   PREFIX_0F3A0A,
 773   PREFIX_0F3A0B,
 774   PREFIX_0F3A0C,
 775   PREFIX_0F3A0D,
 776   PREFIX_0F3A0E,
 777   PREFIX_0F3A14,
 778   PREFIX_0F3A15,
 779   PREFIX_0F3A16,
 780   PREFIX_0F3A17,
 781   PREFIX_0F3A20,
 782   PREFIX_0F3A21,
 783   PREFIX_0F3A22,
 784   PREFIX_0F3A40,
 785   PREFIX_0F3A41,
 786   PREFIX_0F3A42,
 787   PREFIX_0F3A44,
 788   PREFIX_0F3A60,
 789   PREFIX_0F3A61,
 790   PREFIX_0F3A62,
 791   PREFIX_0F3A63,
 792   PREFIX_0F3ADF,
 793   PREFIX_VEX_10,
 794   PREFIX_VEX_11,
 795   PREFIX_VEX_12,
 796   PREFIX_VEX_16,
 797   PREFIX_VEX_2A,
 798   PREFIX_VEX_2C,
 799   PREFIX_VEX_2D,
 800   PREFIX_VEX_2E,
 801   PREFIX_VEX_2F,
 802   PREFIX_VEX_51,
 803   PREFIX_VEX_52,
 804   PREFIX_VEX_53,
 805   PREFIX_VEX_58,
 806   PREFIX_VEX_59,
 807   PREFIX_VEX_5A,
 808   PREFIX_VEX_5B,
 809   PREFIX_VEX_5C,
 810   PREFIX_VEX_5D,
 811   PREFIX_VEX_5E,
 812   PREFIX_VEX_5F,
 813   PREFIX_VEX_60,
 814   PREFIX_VEX_61,
 815   PREFIX_VEX_62,
 816   PREFIX_VEX_63,
 817   PREFIX_VEX_64,
 818   PREFIX_VEX_65,
 819   PREFIX_VEX_66,
 820   PREFIX_VEX_67,
 821   PREFIX_VEX_68,
 822   PREFIX_VEX_69,
 823   PREFIX_VEX_6A,
 824   PREFIX_VEX_6B,
 825   PREFIX_VEX_6C,
 826   PREFIX_VEX_6D,
 827   PREFIX_VEX_6E,
 828   PREFIX_VEX_6F,
 829   PREFIX_VEX_70,
 830   PREFIX_VEX_71_REG_2,
 831   PREFIX_VEX_71_REG_4,
 832   PREFIX_VEX_71_REG_6,
 833   PREFIX_VEX_72_REG_2,
 834   PREFIX_VEX_72_REG_4,
 835   PREFIX_VEX_72_REG_6,
 836   PREFIX_VEX_73_REG_2,
 837   PREFIX_VEX_73_REG_3,
 838   PREFIX_VEX_73_REG_6,
 839   PREFIX_VEX_73_REG_7,
 840   PREFIX_VEX_74,
 841   PREFIX_VEX_75,
 842   PREFIX_VEX_76,
 843   PREFIX_VEX_77,
 844   PREFIX_VEX_7C,
 845   PREFIX_VEX_7D,
 846   PREFIX_VEX_7E,
 847   PREFIX_VEX_7F,
 848   PREFIX_VEX_C2,
 849   PREFIX_VEX_C4,
 850   PREFIX_VEX_C5,
 851   PREFIX_VEX_D0,
 852   PREFIX_VEX_D1,
 853   PREFIX_VEX_D2,
 854   PREFIX_VEX_D3,
 855   PREFIX_VEX_D4,
 856   PREFIX_VEX_D5,
 857   PREFIX_VEX_D6,
 858   PREFIX_VEX_D7,
 859   PREFIX_VEX_D8,
 860   PREFIX_VEX_D9,
 861   PREFIX_VEX_DA,
 862   PREFIX_VEX_DB,
 863   PREFIX_VEX_DC,
 864   PREFIX_VEX_DD,
 865   PREFIX_VEX_DE,
 866   PREFIX_VEX_DF,
 867   PREFIX_VEX_E0,
 868   PREFIX_VEX_E1,
 869   PREFIX_VEX_E2,
 870   PREFIX_VEX_E3,
 871   PREFIX_VEX_E4,
 872   PREFIX_VEX_E5,
 873   PREFIX_VEX_E6,
 874   PREFIX_VEX_E7,
 875   PREFIX_VEX_E8,
 876   PREFIX_VEX_E9,
 877   PREFIX_VEX_EA,
 878   PREFIX_VEX_EB,
 879   PREFIX_VEX_EC,
 880   PREFIX_VEX_ED,
 881   PREFIX_VEX_EE,
 882   PREFIX_VEX_EF,
 883   PREFIX_VEX_F0,
 884   PREFIX_VEX_F1,
 885   PREFIX_VEX_F2,
 886   PREFIX_VEX_F3,
 887   PREFIX_VEX_F4,
 888   PREFIX_VEX_F5,
 889   PREFIX_VEX_F6,
 890   PREFIX_VEX_F7,
 891   PREFIX_VEX_F8,
 892   PREFIX_VEX_F9,
 893   PREFIX_VEX_FA,
 894   PREFIX_VEX_FB,
 895   PREFIX_VEX_FC,
 896   PREFIX_VEX_FD,
 897   PREFIX_VEX_FE,
 898   PREFIX_VEX_3800,
 899   PREFIX_VEX_3801,
 900   PREFIX_VEX_3802,
 901   PREFIX_VEX_3803,
 902   PREFIX_VEX_3804,
 903   PREFIX_VEX_3805,
 904   PREFIX_VEX_3806,
 905   PREFIX_VEX_3807,
 906   PREFIX_VEX_3808,
 907   PREFIX_VEX_3809,
 908   PREFIX_VEX_380A,
 909   PREFIX_VEX_380B,
 910   PREFIX_VEX_380C,
 911   PREFIX_VEX_380D,
 912   PREFIX_VEX_380E,
 913   PREFIX_VEX_380F,
 914   PREFIX_VEX_3817,
 915   PREFIX_VEX_3818,
 916   PREFIX_VEX_3819,
 917   PREFIX_VEX_381A,
 918   PREFIX_VEX_381C,
 919   PREFIX_VEX_381D,
 920   PREFIX_VEX_381E,
 921   PREFIX_VEX_3820,
 922   PREFIX_VEX_3821,
 923   PREFIX_VEX_3822,
 924   PREFIX_VEX_3823,
 925   PREFIX_VEX_3824,
 926   PREFIX_VEX_3825,
 927   PREFIX_VEX_3828,
 928   PREFIX_VEX_3829,
 929   PREFIX_VEX_382A,
 930   PREFIX_VEX_382B,
 931   PREFIX_VEX_382C,
 932   PREFIX_VEX_382D,
 933   PREFIX_VEX_382E,
 934   PREFIX_VEX_382F,
 935   PREFIX_VEX_3830,
 936   PREFIX_VEX_3831,
 937   PREFIX_VEX_3832,
 938   PREFIX_VEX_3833,
 939   PREFIX_VEX_3834,
 940   PREFIX_VEX_3835,
 941   PREFIX_VEX_3837,
 942   PREFIX_VEX_3838,
 943   PREFIX_VEX_3839,
 944   PREFIX_VEX_383A,
 945   PREFIX_VEX_383B,
 946   PREFIX_VEX_383C,
 947   PREFIX_VEX_383D,
 948   PREFIX_VEX_383E,
 949   PREFIX_VEX_383F,
 950   PREFIX_VEX_3840,
 951   PREFIX_VEX_3841,
 952   PREFIX_VEX_3896,
 953   PREFIX_VEX_3897,
 954   PREFIX_VEX_3898,
 955   PREFIX_VEX_3899,
 956   PREFIX_VEX_389A,
 957   PREFIX_VEX_389B,
 958   PREFIX_VEX_389C,
 959   PREFIX_VEX_389D,
 960   PREFIX_VEX_389E,
 961   PREFIX_VEX_389F,
 962   PREFIX_VEX_38A6,
 963   PREFIX_VEX_38A7,
 964   PREFIX_VEX_38A8,
 965   PREFIX_VEX_38A9,
 966   PREFIX_VEX_38AA,
 967   PREFIX_VEX_38AB,
 968   PREFIX_VEX_38AC,
 969   PREFIX_VEX_38AD,
 970   PREFIX_VEX_38AE,
 971   PREFIX_VEX_38AF,
 972   PREFIX_VEX_38B6,
 973   PREFIX_VEX_38B7,
 974   PREFIX_VEX_38B8,
 975   PREFIX_VEX_38B9,
 976   PREFIX_VEX_38BA,
 977   PREFIX_VEX_38BB,
 978   PREFIX_VEX_38BC,
 979   PREFIX_VEX_38BD,
 980   PREFIX_VEX_38BE,
 981   PREFIX_VEX_38BF,
 982   PREFIX_VEX_38DB,
 983   PREFIX_VEX_38DC,
 984   PREFIX_VEX_38DD,
 985   PREFIX_VEX_38DE,
 986   PREFIX_VEX_38DF,
 987   PREFIX_VEX_3A04,
 988   PREFIX_VEX_3A05,
 989   PREFIX_VEX_3A06,
 990   PREFIX_VEX_3A08,
 991   PREFIX_VEX_3A09,
 992   PREFIX_VEX_3A0A,
 993   PREFIX_VEX_3A0B,
 994   PREFIX_VEX_3A0C,
 995   PREFIX_VEX_3A0D,
 996   PREFIX_VEX_3A0E,
 997   PREFIX_VEX_3A0F,
 998   PREFIX_VEX_3A14,
 999   PREFIX_VEX_3A15,
1000   PREFIX_VEX_3A16,
1001   PREFIX_VEX_3A17,
1002   PREFIX_VEX_3A18,
1003   PREFIX_VEX_3A19,
1004   PREFIX_VEX_3A20,
1005   PREFIX_VEX_3A21,
1006   PREFIX_VEX_3A22,
1007   PREFIX_VEX_3A40,
1008   PREFIX_VEX_3A41,
1009   PREFIX_VEX_3A42,
1010   PREFIX_VEX_3A44,
1011   PREFIX_VEX_3A4A,
1012   PREFIX_VEX_3A4B,
1013   PREFIX_VEX_3A4C,
1014   PREFIX_VEX_3A5C,
1015   PREFIX_VEX_3A5D,
1016   PREFIX_VEX_3A5E,
1017   PREFIX_VEX_3A5F,
1018   PREFIX_VEX_3A60,
1019   PREFIX_VEX_3A61,
1020   PREFIX_VEX_3A62,
1021   PREFIX_VEX_3A63,
1022   PREFIX_VEX_3A68,
1023   PREFIX_VEX_3A69,
1024   PREFIX_VEX_3A6A,
1025   PREFIX_VEX_3A6B,
1026   PREFIX_VEX_3A6C,
1027   PREFIX_VEX_3A6D,
1028   PREFIX_VEX_3A6E,
1029   PREFIX_VEX_3A6F,
1030   PREFIX_VEX_3A78,
1031   PREFIX_VEX_3A79,
1032   PREFIX_VEX_3A7A,
1033   PREFIX_VEX_3A7B,
1034   PREFIX_VEX_3A7C,
1035   PREFIX_VEX_3A7D,
1036   PREFIX_VEX_3A7E,
1037   PREFIX_VEX_3A7F,
1038   PREFIX_VEX_3ADF
1039 };
1040
1041 enum
1042 {
1043   X86_64_06 = 0,
1044   X86_64_07,
1045   X86_64_0D,
1046   X86_64_16,
1047   X86_64_17,
1048   X86_64_1E,
1049   X86_64_1F,
1050   X86_64_27,
1051   X86_64_2F,
1052   X86_64_37,
1053   X86_64_3F,
1054   X86_64_60,
1055   X86_64_61,
1056   X86_64_62,
1057   X86_64_63,
1058   X86_64_6D,
1059   X86_64_6F,
1060   X86_64_9A,
1061   X86_64_C4,
1062   X86_64_C5,
1063   X86_64_CE,
1064   X86_64_D4,
1065   X86_64_D5,
1066   X86_64_EA,
1067   X86_64_0F01_REG_0,
1068   X86_64_0F01_REG_1,
1069   X86_64_0F01_REG_2,
1070   X86_64_0F01_REG_3
1071 };
1072
1073 enum
1074 {
1075   THREE_BYTE_0F38 = 0,
1076   THREE_BYTE_0F3A,
1077   THREE_BYTE_0F7A
1078 };
1079
1080 enum
1081 {
1082   XOP_08 = 0,
1083   XOP_09,
1084   XOP_0A
1085 };
1086
1087 enum
1088 {
1089   VEX_0F = 0,
1090   VEX_0F38,
1091   VEX_0F3A
1092 };
1093
1094 enum
1095 {
1096   VEX_LEN_10_P_1 = 0,
1097   VEX_LEN_10_P_3,
1098   VEX_LEN_11_P_1,
1099   VEX_LEN_11_P_3,
1100   VEX_LEN_12_P_0_M_0,
1101   VEX_LEN_12_P_0_M_1,
1102   VEX_LEN_12_P_2,
1103   VEX_LEN_13_M_0,
1104   VEX_LEN_16_P_0_M_0,
1105   VEX_LEN_16_P_0_M_1,
1106   VEX_LEN_16_P_2,
1107   VEX_LEN_17_M_0,
1108   VEX_LEN_2A_P_1,
1109   VEX_LEN_2A_P_3,
1110   VEX_LEN_2C_P_1,
1111   VEX_LEN_2C_P_3,
1112   VEX_LEN_2D_P_1,
1113   VEX_LEN_2D_P_3,
1114   VEX_LEN_2E_P_0,
1115   VEX_LEN_2E_P_2,
1116   VEX_LEN_2F_P_0,
1117   VEX_LEN_2F_P_2,
1118   VEX_LEN_51_P_1,
1119   VEX_LEN_51_P_3,
1120   VEX_LEN_52_P_1,
1121   VEX_LEN_53_P_1,
1122   VEX_LEN_58_P_1,
1123   VEX_LEN_58_P_3,
1124   VEX_LEN_59_P_1,
1125   VEX_LEN_59_P_3,
1126   VEX_LEN_5A_P_1,
1127   VEX_LEN_5A_P_3,
1128   VEX_LEN_5C_P_1,
1129   VEX_LEN_5C_P_3,
1130   VEX_LEN_5D_P_1,
1131   VEX_LEN_5D_P_3,
1132   VEX_LEN_5E_P_1,
1133   VEX_LEN_5E_P_3,
1134   VEX_LEN_5F_P_1,
1135   VEX_LEN_5F_P_3,
1136   VEX_LEN_60_P_2,
1137   VEX_LEN_61_P_2,
1138   VEX_LEN_62_P_2,
1139   VEX_LEN_63_P_2,
1140   VEX_LEN_64_P_2,
1141   VEX_LEN_65_P_2,
1142   VEX_LEN_66_P_2,
1143   VEX_LEN_67_P_2,
1144   VEX_LEN_68_P_2,
1145   VEX_LEN_69_P_2,
1146   VEX_LEN_6A_P_2,
1147   VEX_LEN_6B_P_2,
1148   VEX_LEN_6C_P_2,
1149   VEX_LEN_6D_P_2,
1150   VEX_LEN_6E_P_2,
1151   VEX_LEN_70_P_1,
1152   VEX_LEN_70_P_2,
1153   VEX_LEN_70_P_3,
1154   VEX_LEN_71_R_2_P_2,
1155   VEX_LEN_71_R_4_P_2,
1156   VEX_LEN_71_R_6_P_2,
1157   VEX_LEN_72_R_2_P_2,
1158   VEX_LEN_72_R_4_P_2,
1159   VEX_LEN_72_R_6_P_2,
1160   VEX_LEN_73_R_2_P_2,
1161   VEX_LEN_73_R_3_P_2,
1162   VEX_LEN_73_R_6_P_2,
1163   VEX_LEN_73_R_7_P_2,
1164   VEX_LEN_74_P_2,
1165   VEX_LEN_75_P_2,
1166   VEX_LEN_76_P_2,
1167   VEX_LEN_7E_P_1,
1168   VEX_LEN_7E_P_2,
1169   VEX_LEN_AE_R_2_M_0,
1170   VEX_LEN_AE_R_3_M_0,
1171   VEX_LEN_C2_P_1,
1172   VEX_LEN_C2_P_3,
1173   VEX_LEN_C4_P_2,
1174   VEX_LEN_C5_P_2,
1175   VEX_LEN_D1_P_2,
1176   VEX_LEN_D2_P_2,
1177   VEX_LEN_D3_P_2,
1178   VEX_LEN_D4_P_2,
1179   VEX_LEN_D5_P_2,
1180   VEX_LEN_D6_P_2,
1181   VEX_LEN_D7_P_2_M_1,
1182   VEX_LEN_D8_P_2,
1183   VEX_LEN_D9_P_2,
1184   VEX_LEN_DA_P_2,
1185   VEX_LEN_DB_P_2,
1186   VEX_LEN_DC_P_2,
1187   VEX_LEN_DD_P_2,
1188   VEX_LEN_DE_P_2,
1189   VEX_LEN_DF_P_2,
1190   VEX_LEN_E0_P_2,
1191   VEX_LEN_E1_P_2,
1192   VEX_LEN_E2_P_2,
1193   VEX_LEN_E3_P_2,
1194   VEX_LEN_E4_P_2,
1195   VEX_LEN_E5_P_2,
1196   VEX_LEN_E8_P_2,
1197   VEX_LEN_E9_P_2,
1198   VEX_LEN_EA_P_2,
1199   VEX_LEN_EB_P_2,
1200   VEX_LEN_EC_P_2,
1201   VEX_LEN_ED_P_2,
1202   VEX_LEN_EE_P_2,
1203   VEX_LEN_EF_P_2,
1204   VEX_LEN_F1_P_2,
1205   VEX_LEN_F2_P_2,
1206   VEX_LEN_F3_P_2,
1207   VEX_LEN_F4_P_2,
1208   VEX_LEN_F5_P_2,
1209   VEX_LEN_F6_P_2,
1210   VEX_LEN_F7_P_2,
1211   VEX_LEN_F8_P_2,
1212   VEX_LEN_F9_P_2,
1213   VEX_LEN_FA_P_2,
1214   VEX_LEN_FB_P_2,
1215   VEX_LEN_FC_P_2,
1216   VEX_LEN_FD_P_2,
1217   VEX_LEN_FE_P_2,
1218   VEX_LEN_3800_P_2,
1219   VEX_LEN_3801_P_2,
1220   VEX_LEN_3802_P_2,
1221   VEX_LEN_3803_P_2,
1222   VEX_LEN_3804_P_2,
1223   VEX_LEN_3805_P_2,
1224   VEX_LEN_3806_P_2,
1225   VEX_LEN_3807_P_2,
1226   VEX_LEN_3808_P_2,
1227   VEX_LEN_3809_P_2,
1228   VEX_LEN_380A_P_2,
1229   VEX_LEN_380B_P_2,
1230   VEX_LEN_3819_P_2_M_0,
1231   VEX_LEN_381A_P_2_M_0,
1232   VEX_LEN_381C_P_2,
1233   VEX_LEN_381D_P_2,
1234   VEX_LEN_381E_P_2,
1235   VEX_LEN_3820_P_2,
1236   VEX_LEN_3821_P_2,
1237   VEX_LEN_3822_P_2,
1238   VEX_LEN_3823_P_2,
1239   VEX_LEN_3824_P_2,
1240   VEX_LEN_3825_P_2,
1241   VEX_LEN_3828_P_2,
1242   VEX_LEN_3829_P_2,
1243   VEX_LEN_382A_P_2_M_0,
1244   VEX_LEN_382B_P_2,
1245   VEX_LEN_3830_P_2,
1246   VEX_LEN_3831_P_2,
1247   VEX_LEN_3832_P_2,
1248   VEX_LEN_3833_P_2,
1249   VEX_LEN_3834_P_2,
1250   VEX_LEN_3835_P_2,
1251   VEX_LEN_3837_P_2,
1252   VEX_LEN_3838_P_2,
1253   VEX_LEN_3839_P_2,
1254   VEX_LEN_383A_P_2,
1255   VEX_LEN_383B_P_2,
1256   VEX_LEN_383C_P_2,
1257   VEX_LEN_383D_P_2,
1258   VEX_LEN_383E_P_2,
1259   VEX_LEN_383F_P_2,
1260   VEX_LEN_3840_P_2,
1261   VEX_LEN_3841_P_2,
1262   VEX_LEN_38DB_P_2,
1263   VEX_LEN_38DC_P_2,
1264   VEX_LEN_38DD_P_2,
1265   VEX_LEN_38DE_P_2,
1266   VEX_LEN_38DF_P_2,
1267   VEX_LEN_3A06_P_2,
1268   VEX_LEN_3A0A_P_2,
1269   VEX_LEN_3A0B_P_2,
1270   VEX_LEN_3A0E_P_2,
1271   VEX_LEN_3A0F_P_2,
1272   VEX_LEN_3A14_P_2,
1273   VEX_LEN_3A15_P_2,
1274   VEX_LEN_3A16_P_2,
1275   VEX_LEN_3A17_P_2,
1276   VEX_LEN_3A18_P_2,
1277   VEX_LEN_3A19_P_2,
1278   VEX_LEN_3A20_P_2,
1279   VEX_LEN_3A21_P_2,
1280   VEX_LEN_3A22_P_2,
1281   VEX_LEN_3A41_P_2,
1282   VEX_LEN_3A42_P_2,
1283   VEX_LEN_3A44_P_2,
1284   VEX_LEN_3A4C_P_2,
1285   VEX_LEN_3A60_P_2,
1286   VEX_LEN_3A61_P_2,
1287   VEX_LEN_3A62_P_2,
1288   VEX_LEN_3A63_P_2,
1289   VEX_LEN_3A6A_P_2,
1290   VEX_LEN_3A6B_P_2,
1291   VEX_LEN_3A6E_P_2,
1292   VEX_LEN_3A6F_P_2,
1293   VEX_LEN_3A7A_P_2,
1294   VEX_LEN_3A7B_P_2,
1295   VEX_LEN_3A7E_P_2,
1296   VEX_LEN_3A7F_P_2,
1297   VEX_LEN_3ADF_P_2,
1298   VEX_LEN_XOP_09_80,
1299   VEX_LEN_XOP_09_81
1300 };
1301
1302 enum
1303 {
1304   VEX_W_10_P_0 = 0,
1305   VEX_W_10_P_1,
1306   VEX_W_10_P_2,
1307   VEX_W_10_P_3,
1308   VEX_W_11_P_0,
1309   VEX_W_11_P_1,
1310   VEX_W_11_P_2,
1311   VEX_W_11_P_3,
1312   VEX_W_12_P_0_M_0,
1313   VEX_W_12_P_0_M_1,
1314   VEX_W_12_P_1,
1315   VEX_W_12_P_2,
1316   VEX_W_12_P_3,
1317   VEX_W_13_M_0,
1318   VEX_W_14,
1319   VEX_W_15,
1320   VEX_W_16_P_0_M_0,
1321   VEX_W_16_P_0_M_1,
1322   VEX_W_16_P_1,
1323   VEX_W_16_P_2,
1324   VEX_W_17_M_0,
1325   VEX_W_28,
1326   VEX_W_29,
1327   VEX_W_2B_M_0,
1328   VEX_W_2E_P_0,
1329   VEX_W_2E_P_2,
1330   VEX_W_2F_P_0,
1331   VEX_W_2F_P_2,
1332   VEX_W_50_M_0,
1333   VEX_W_51_P_0,
1334   VEX_W_51_P_1,
1335   VEX_W_51_P_2,
1336   VEX_W_51_P_3,
1337   VEX_W_52_P_0,
1338   VEX_W_52_P_1,
1339   VEX_W_53_P_0,
1340   VEX_W_53_P_1,
1341   VEX_W_58_P_0,
1342   VEX_W_58_P_1,
1343   VEX_W_58_P_2,
1344   VEX_W_58_P_3,
1345   VEX_W_59_P_0,
1346   VEX_W_59_P_1,
1347   VEX_W_59_P_2,
1348   VEX_W_59_P_3,
1349   VEX_W_5A_P_0,
1350   VEX_W_5A_P_1,
1351   VEX_W_5A_P_3,
1352   VEX_W_5B_P_0,
1353   VEX_W_5B_P_1,
1354   VEX_W_5B_P_2,
1355   VEX_W_5C_P_0,
1356   VEX_W_5C_P_1,
1357   VEX_W_5C_P_2,
1358   VEX_W_5C_P_3,
1359   VEX_W_5D_P_0,
1360   VEX_W_5D_P_1,
1361   VEX_W_5D_P_2,
1362   VEX_W_5D_P_3,
1363   VEX_W_5E_P_0,
1364   VEX_W_5E_P_1,
1365   VEX_W_5E_P_2,
1366   VEX_W_5E_P_3,
1367   VEX_W_5F_P_0,
1368   VEX_W_5F_P_1,
1369   VEX_W_5F_P_2,
1370   VEX_W_5F_P_3,
1371   VEX_W_60_P_2,
1372   VEX_W_61_P_2,
1373   VEX_W_62_P_2,
1374   VEX_W_63_P_2,
1375   VEX_W_64_P_2,
1376   VEX_W_65_P_2,
1377   VEX_W_66_P_2,
1378   VEX_W_67_P_2,
1379   VEX_W_68_P_2,
1380   VEX_W_69_P_2,
1381   VEX_W_6A_P_2,
1382   VEX_W_6B_P_2,
1383   VEX_W_6C_P_2,
1384   VEX_W_6D_P_2,
1385   VEX_W_6F_P_1,
1386   VEX_W_6F_P_2,
1387   VEX_W_70_P_1,
1388   VEX_W_70_P_2,
1389   VEX_W_70_P_3,
1390   VEX_W_71_R_2_P_2,
1391   VEX_W_71_R_4_P_2,
1392   VEX_W_71_R_6_P_2,
1393   VEX_W_72_R_2_P_2,
1394   VEX_W_72_R_4_P_2,
1395   VEX_W_72_R_6_P_2,
1396   VEX_W_73_R_2_P_2,
1397   VEX_W_73_R_3_P_2,
1398   VEX_W_73_R_6_P_2,
1399   VEX_W_73_R_7_P_2,
1400   VEX_W_74_P_2,
1401   VEX_W_75_P_2,
1402   VEX_W_76_P_2,
1403   VEX_W_77_P_0,
1404   VEX_W_7C_P_2,
1405   VEX_W_7C_P_3,
1406   VEX_W_7D_P_2,
1407   VEX_W_7D_P_3,
1408   VEX_W_7E_P_1,
1409   VEX_W_7F_P_1,
1410   VEX_W_7F_P_2,
1411   VEX_W_AE_R_2_M_0,
1412   VEX_W_AE_R_3_M_0,
1413   VEX_W_C2_P_0,
1414   VEX_W_C2_P_1,
1415   VEX_W_C2_P_2,
1416   VEX_W_C2_P_3,
1417   VEX_W_C4_P_2,
1418   VEX_W_C5_P_2,
1419   VEX_W_D0_P_2,
1420   VEX_W_D0_P_3,
1421   VEX_W_D1_P_2,
1422   VEX_W_D2_P_2,
1423   VEX_W_D3_P_2,
1424   VEX_W_D4_P_2,
1425   VEX_W_D5_P_2,
1426   VEX_W_D6_P_2,
1427   VEX_W_D7_P_2_M_1,
1428   VEX_W_D8_P_2,
1429   VEX_W_D9_P_2,
1430   VEX_W_DA_P_2,
1431   VEX_W_DB_P_2,
1432   VEX_W_DC_P_2,
1433   VEX_W_DD_P_2,
1434   VEX_W_DE_P_2,
1435   VEX_W_DF_P_2,
1436   VEX_W_E0_P_2,
1437   VEX_W_E1_P_2,
1438   VEX_W_E2_P_2,
1439   VEX_W_E3_P_2,
1440   VEX_W_E4_P_2,
1441   VEX_W_E5_P_2,
1442   VEX_W_E6_P_1,
1443   VEX_W_E6_P_2,
1444   VEX_W_E6_P_3,
1445   VEX_W_E7_P_2_M_0,
1446   VEX_W_E8_P_2,
1447   VEX_W_E9_P_2,
1448   VEX_W_EA_P_2,
1449   VEX_W_EB_P_2,
1450   VEX_W_EC_P_2,
1451   VEX_W_ED_P_2,
1452   VEX_W_EE_P_2,
1453   VEX_W_EF_P_2,
1454   VEX_W_F0_P_3_M_0,
1455   VEX_W_F1_P_2,
1456   VEX_W_F2_P_2,
1457   VEX_W_F3_P_2,
1458   VEX_W_F4_P_2,
1459   VEX_W_F5_P_2,
1460   VEX_W_F6_P_2,
1461   VEX_W_F7_P_2,
1462   VEX_W_F8_P_2,
1463   VEX_W_F9_P_2,
1464   VEX_W_FA_P_2,
1465   VEX_W_FB_P_2,
1466   VEX_W_FC_P_2,
1467   VEX_W_FD_P_2,
1468   VEX_W_FE_P_2,
1469   VEX_W_3800_P_2,
1470   VEX_W_3801_P_2,
1471   VEX_W_3802_P_2,
1472   VEX_W_3803_P_2,
1473   VEX_W_3804_P_2,
1474   VEX_W_3805_P_2,
1475   VEX_W_3806_P_2,
1476   VEX_W_3807_P_2,
1477   VEX_W_3808_P_2,
1478   VEX_W_3809_P_2,
1479   VEX_W_380A_P_2,
1480   VEX_W_380B_P_2,
1481   VEX_W_380C_P_2,
1482   VEX_W_380D_P_2,
1483   VEX_W_380E_P_2,
1484   VEX_W_380F_P_2,
1485   VEX_W_3817_P_2,
1486   VEX_W_3818_P_2_M_0,
1487   VEX_W_3819_P_2_M_0,
1488   VEX_W_381A_P_2_M_0,
1489   VEX_W_381C_P_2,
1490   VEX_W_381D_P_2,
1491   VEX_W_381E_P_2,
1492   VEX_W_3820_P_2,
1493   VEX_W_3821_P_2,
1494   VEX_W_3822_P_2,
1495   VEX_W_3823_P_2,
1496   VEX_W_3824_P_2,
1497   VEX_W_3825_P_2,
1498   VEX_W_3828_P_2,
1499   VEX_W_3829_P_2,
1500   VEX_W_382A_P_2_M_0,
1501   VEX_W_382B_P_2,
1502   VEX_W_382C_P_2_M_0,
1503   VEX_W_382D_P_2_M_0,
1504   VEX_W_382E_P_2_M_0,
1505   VEX_W_382F_P_2_M_0,
1506   VEX_W_3830_P_2,
1507   VEX_W_3831_P_2,
1508   VEX_W_3832_P_2,
1509   VEX_W_3833_P_2,
1510   VEX_W_3834_P_2,
1511   VEX_W_3835_P_2,
1512   VEX_W_3837_P_2,
1513   VEX_W_3838_P_2,
1514   VEX_W_3839_P_2,
1515   VEX_W_383A_P_2,
1516   VEX_W_383B_P_2,
1517   VEX_W_383C_P_2,
1518   VEX_W_383D_P_2,
1519   VEX_W_383E_P_2,
1520   VEX_W_383F_P_2,
1521   VEX_W_3840_P_2,
1522   VEX_W_3841_P_2,
1523   VEX_W_38DB_P_2,
1524   VEX_W_38DC_P_2,
1525   VEX_W_38DD_P_2,
1526   VEX_W_38DE_P_2,
1527   VEX_W_38DF_P_2,
1528   VEX_W_3A04_P_2,
1529   VEX_W_3A05_P_2,
1530   VEX_W_3A06_P_2,
1531   VEX_W_3A08_P_2,
1532   VEX_W_3A09_P_2,
1533   VEX_W_3A0A_P_2,
1534   VEX_W_3A0B_P_2,
1535   VEX_W_3A0C_P_2,
1536   VEX_W_3A0D_P_2,
1537   VEX_W_3A0E_P_2,
1538   VEX_W_3A0F_P_2,
1539   VEX_W_3A14_P_2,
1540   VEX_W_3A15_P_2,
1541   VEX_W_3A18_P_2,
1542   VEX_W_3A19_P_2,
1543   VEX_W_3A20_P_2,
1544   VEX_W_3A21_P_2,
1545   VEX_W_3A40_P_2,
1546   VEX_W_3A41_P_2,
1547   VEX_W_3A42_P_2,
1548   VEX_W_3A44_P_2,
1549   VEX_W_3A4A_P_2,
1550   VEX_W_3A4B_P_2,
1551   VEX_W_3A4C_P_2,
1552   VEX_W_3A60_P_2,
1553   VEX_W_3A61_P_2,
1554   VEX_W_3A62_P_2,
1555   VEX_W_3A63_P_2,
1556   VEX_W_3ADF_P_2
1557 };
1558
1559 typedef void (*op_rtn) (int bytemode, int sizeflag);
1560
1561 struct dis386 {
1562   const char *name;
1563   struct
1564     {
1565       op_rtn rtn;
1566       int bytemode;
1567     } op[MAX_OPERANDS];
1568 };
1569
1570 /* Upper case letters in the instruction names here are macros.
1571    'A' => print 'b' if no register operands or suffix_always is true
1572    'B' => print 'b' if suffix_always is true
1573    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1574           size prefix
1575    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1576           suffix_always is true
1577    'E' => print 'e' if 32-bit form of jcxz
1578    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1579    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1580    'H' => print ",pt" or ",pn" branch hint
1581    'I' => honor following macro letter even in Intel mode (implemented only
1582           for some of the macro letters)
1583    'J' => print 'l'
1584    'K' => print 'd' or 'q' if rex prefix is present.
1585    'L' => print 'l' if suffix_always is true
1586    'M' => print 'r' if intel_mnemonic is false.
1587    'N' => print 'n' if instruction has no wait "prefix"
1588    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1589    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1590           or suffix_always is true.  print 'q' if rex prefix is present.
1591    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1592           is true
1593    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1594    'S' => print 'w', 'l' or 'q' if suffix_always is true
1595    'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1596    'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1597    'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1598    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1599    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1600    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1601           suffix_always is true.
1602    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1603    '!' => change condition from true to false or from false to true.
1604    '%' => add 1 upper case letter to the macro.
1605
1606    2 upper case letter macros:
1607    "XY" => print 'x' or 'y' if no register operands or suffix_always
1608            is true.
1609    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1610    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1611            or suffix_always is true
1612    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1613    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1614    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1615
1616    Many of the above letters print nothing in Intel mode.  See "putop"
1617    for the details.
1618
1619    Braces '{' and '}', and vertical bars '|', indicate alternative
1620    mnemonic strings for AT&T and Intel.  */
1621
1622 static const struct dis386 dis386[] = {
1623   /* 00 */
1624   { "addB",             { Eb, Gb } },
1625   { "addS",             { Ev, Gv } },
1626   { "addB",             { Gb, EbS } },
1627   { "addS",             { Gv, EvS } },
1628   { "addB",             { AL, Ib } },
1629   { "addS",             { eAX, Iv } },
1630   { X86_64_TABLE (X86_64_06) },
1631   { X86_64_TABLE (X86_64_07) },
1632   /* 08 */
1633   { "orB",              { Eb, Gb } },
1634   { "orS",              { Ev, Gv } },
1635   { "orB",              { Gb, EbS } },
1636   { "orS",              { Gv, EvS } },
1637   { "orB",              { AL, Ib } },
1638   { "orS",              { eAX, Iv } },
1639   { X86_64_TABLE (X86_64_0D) },
1640   { Bad_Opcode },       /* 0x0f extended opcode escape */
1641   /* 10 */
1642   { "adcB",             { Eb, Gb } },
1643   { "adcS",             { Ev, Gv } },
1644   { "adcB",             { Gb, EbS } },
1645   { "adcS",             { Gv, EvS } },
1646   { "adcB",             { AL, Ib } },
1647   { "adcS",             { eAX, Iv } },
1648   { X86_64_TABLE (X86_64_16) },
1649   { X86_64_TABLE (X86_64_17) },
1650   /* 18 */
1651   { "sbbB",             { Eb, Gb } },
1652   { "sbbS",             { Ev, Gv } },
1653   { "sbbB",             { Gb, EbS } },
1654   { "sbbS",             { Gv, EvS } },
1655   { "sbbB",             { AL, Ib } },
1656   { "sbbS",             { eAX, Iv } },
1657   { X86_64_TABLE (X86_64_1E) },
1658   { X86_64_TABLE (X86_64_1F) },
1659   /* 20 */
1660   { "andB",             { Eb, Gb } },
1661   { "andS",             { Ev, Gv } },
1662   { "andB",             { Gb, EbS } },
1663   { "andS",             { Gv, EvS } },
1664   { "andB",             { AL, Ib } },
1665   { "andS",             { eAX, Iv } },
1666   { Bad_Opcode },       /* SEG ES prefix */
1667   { X86_64_TABLE (X86_64_27) },
1668   /* 28 */
1669   { "subB",             { Eb, Gb } },
1670   { "subS",             { Ev, Gv } },
1671   { "subB",             { Gb, EbS } },
1672   { "subS",             { Gv, EvS } },
1673   { "subB",             { AL, Ib } },
1674   { "subS",             { eAX, Iv } },
1675   { Bad_Opcode },       /* SEG CS prefix */
1676   { X86_64_TABLE (X86_64_2F) },
1677   /* 30 */
1678   { "xorB",             { Eb, Gb } },
1679   { "xorS",             { Ev, Gv } },
1680   { "xorB",             { Gb, EbS } },
1681   { "xorS",             { Gv, EvS } },
1682   { "xorB",             { AL, Ib } },
1683   { "xorS",             { eAX, Iv } },
1684   { Bad_Opcode },       /* SEG SS prefix */
1685   { X86_64_TABLE (X86_64_37) },
1686   /* 38 */
1687   { "cmpB",             { Eb, Gb } },
1688   { "cmpS",             { Ev, Gv } },
1689   { "cmpB",             { Gb, EbS } },
1690   { "cmpS",             { Gv, EvS } },
1691   { "cmpB",             { AL, Ib } },
1692   { "cmpS",             { eAX, Iv } },
1693   { Bad_Opcode },       /* SEG DS prefix */
1694   { X86_64_TABLE (X86_64_3F) },
1695   /* 40 */
1696   { "inc{S|}",          { RMeAX } },
1697   { "inc{S|}",          { RMeCX } },
1698   { "inc{S|}",          { RMeDX } },
1699   { "inc{S|}",          { RMeBX } },
1700   { "inc{S|}",          { RMeSP } },
1701   { "inc{S|}",          { RMeBP } },
1702   { "inc{S|}",          { RMeSI } },
1703   { "inc{S|}",          { RMeDI } },
1704   /* 48 */
1705   { "dec{S|}",          { RMeAX } },
1706   { "dec{S|}",          { RMeCX } },
1707   { "dec{S|}",          { RMeDX } },
1708   { "dec{S|}",          { RMeBX } },
1709   { "dec{S|}",          { RMeSP } },
1710   { "dec{S|}",          { RMeBP } },
1711   { "dec{S|}",          { RMeSI } },
1712   { "dec{S|}",          { RMeDI } },
1713   /* 50 */
1714   { "pushV",            { RMrAX } },
1715   { "pushV",            { RMrCX } },
1716   { "pushV",            { RMrDX } },
1717   { "pushV",            { RMrBX } },
1718   { "pushV",            { RMrSP } },
1719   { "pushV",            { RMrBP } },
1720   { "pushV",            { RMrSI } },
1721   { "pushV",            { RMrDI } },
1722   /* 58 */
1723   { "popV",             { RMrAX } },
1724   { "popV",             { RMrCX } },
1725   { "popV",             { RMrDX } },
1726   { "popV",             { RMrBX } },
1727   { "popV",             { RMrSP } },
1728   { "popV",             { RMrBP } },
1729   { "popV",             { RMrSI } },
1730   { "popV",             { RMrDI } },
1731   /* 60 */
1732   { X86_64_TABLE (X86_64_60) },
1733   { X86_64_TABLE (X86_64_61) },
1734   { X86_64_TABLE (X86_64_62) },
1735   { X86_64_TABLE (X86_64_63) },
1736   { Bad_Opcode },       /* seg fs */
1737   { Bad_Opcode },       /* seg gs */
1738   { Bad_Opcode },       /* op size prefix */
1739   { Bad_Opcode },       /* adr size prefix */
1740   /* 68 */
1741   { "pushT",            { Iq } },
1742   { "imulS",            { Gv, Ev, Iv } },
1743   { "pushT",            { sIb } },
1744   { "imulS",            { Gv, Ev, sIb } },
1745   { "ins{b|}",          { Ybr, indirDX } },
1746   { X86_64_TABLE (X86_64_6D) },
1747   { "outs{b|}",         { indirDXr, Xb } },
1748   { X86_64_TABLE (X86_64_6F) },
1749   /* 70 */
1750   { "joH",              { Jb, XX, cond_jump_flag } },
1751   { "jnoH",             { Jb, XX, cond_jump_flag } },
1752   { "jbH",              { Jb, XX, cond_jump_flag } },
1753   { "jaeH",             { Jb, XX, cond_jump_flag } },
1754   { "jeH",              { Jb, XX, cond_jump_flag } },
1755   { "jneH",             { Jb, XX, cond_jump_flag } },
1756   { "jbeH",             { Jb, XX, cond_jump_flag } },
1757   { "jaH",              { Jb, XX, cond_jump_flag } },
1758   /* 78 */
1759   { "jsH",              { Jb, XX, cond_jump_flag } },
1760   { "jnsH",             { Jb, XX, cond_jump_flag } },
1761   { "jpH",              { Jb, XX, cond_jump_flag } },
1762   { "jnpH",             { Jb, XX, cond_jump_flag } },
1763   { "jlH",              { Jb, XX, cond_jump_flag } },
1764   { "jgeH",             { Jb, XX, cond_jump_flag } },
1765   { "jleH",             { Jb, XX, cond_jump_flag } },
1766   { "jgH",              { Jb, XX, cond_jump_flag } },
1767   /* 80 */
1768   { REG_TABLE (REG_80) },
1769   { REG_TABLE (REG_81) },
1770   { Bad_Opcode },
1771   { REG_TABLE (REG_82) },
1772   { "testB",            { Eb, Gb } },
1773   { "testS",            { Ev, Gv } },
1774   { "xchgB",            { Eb, Gb } },
1775   { "xchgS",            { Ev, Gv } },
1776   /* 88 */
1777   { "movB",             { Eb, Gb } },
1778   { "movS",             { Ev, Gv } },
1779   { "movB",             { Gb, EbS } },
1780   { "movS",             { Gv, EvS } },
1781   { "movD",             { Sv, Sw } },
1782   { MOD_TABLE (MOD_8D) },
1783   { "movD",             { Sw, Sv } },
1784   { REG_TABLE (REG_8F) },
1785   /* 90 */
1786   { PREFIX_TABLE (PREFIX_90) },
1787   { "xchgS",            { RMeCX, eAX } },
1788   { "xchgS",            { RMeDX, eAX } },
1789   { "xchgS",            { RMeBX, eAX } },
1790   { "xchgS",            { RMeSP, eAX } },
1791   { "xchgS",            { RMeBP, eAX } },
1792   { "xchgS",            { RMeSI, eAX } },
1793   { "xchgS",            { RMeDI, eAX } },
1794   /* 98 */
1795   { "cW{t|}R",          { XX } },
1796   { "cR{t|}O",          { XX } },
1797   { X86_64_TABLE (X86_64_9A) },
1798   { Bad_Opcode },       /* fwait */
1799   { "pushfT",           { XX } },
1800   { "popfT",            { XX } },
1801   { "sahf",             { XX } },
1802   { "lahf",             { XX } },
1803   /* a0 */
1804   { "mov%LB",           { AL, Ob } },
1805   { "mov%LS",           { eAX, Ov } },
1806   { "mov%LB",           { Ob, AL } },
1807   { "mov%LS",           { Ov, eAX } },
1808   { "movs{b|}",         { Ybr, Xb } },
1809   { "movs{R|}",         { Yvr, Xv } },
1810   { "cmps{b|}",         { Xb, Yb } },
1811   { "cmps{R|}",         { Xv, Yv } },
1812   /* a8 */
1813   { "testB",            { AL, Ib } },
1814   { "testS",            { eAX, Iv } },
1815   { "stosB",            { Ybr, AL } },
1816   { "stosS",            { Yvr, eAX } },
1817   { "lodsB",            { ALr, Xb } },
1818   { "lodsS",            { eAXr, Xv } },
1819   { "scasB",            { AL, Yb } },
1820   { "scasS",            { eAX, Yv } },
1821   /* b0 */
1822   { "movB",             { RMAL, Ib } },
1823   { "movB",             { RMCL, Ib } },
1824   { "movB",             { RMDL, Ib } },
1825   { "movB",             { RMBL, Ib } },
1826   { "movB",             { RMAH, Ib } },
1827   { "movB",             { RMCH, Ib } },
1828   { "movB",             { RMDH, Ib } },
1829   { "movB",             { RMBH, Ib } },
1830   /* b8 */
1831   { "mov%LV",           { RMeAX, Iv64 } },
1832   { "mov%LV",           { RMeCX, Iv64 } },
1833   { "mov%LV",           { RMeDX, Iv64 } },
1834   { "mov%LV",           { RMeBX, Iv64 } },
1835   { "mov%LV",           { RMeSP, Iv64 } },
1836   { "mov%LV",           { RMeBP, Iv64 } },
1837   { "mov%LV",           { RMeSI, Iv64 } },
1838   { "mov%LV",           { RMeDI, Iv64 } },
1839   /* c0 */
1840   { REG_TABLE (REG_C0) },
1841   { REG_TABLE (REG_C1) },
1842   { "retT",             { Iw } },
1843   { "retT",             { XX } },
1844   { X86_64_TABLE (X86_64_C4) },
1845   { X86_64_TABLE (X86_64_C5) },
1846   { REG_TABLE (REG_C6) },
1847   { REG_TABLE (REG_C7) },
1848   /* c8 */
1849   { "enterT",           { Iw, Ib } },
1850   { "leaveT",           { XX } },
1851   { "Jret{|f}P",        { Iw } },
1852   { "Jret{|f}P",        { XX } },
1853   { "int3",             { XX } },
1854   { "int",              { Ib } },
1855   { X86_64_TABLE (X86_64_CE) },
1856   { "iretP",            { XX } },
1857   /* d0 */
1858   { REG_TABLE (REG_D0) },
1859   { REG_TABLE (REG_D1) },
1860   { REG_TABLE (REG_D2) },
1861   { REG_TABLE (REG_D3) },
1862   { X86_64_TABLE (X86_64_D4) },
1863   { X86_64_TABLE (X86_64_D5) },
1864   { Bad_Opcode },
1865   { "xlat",             { DSBX } },
1866   /* d8 */
1867   { FLOAT },
1868   { FLOAT },
1869   { FLOAT },
1870   { FLOAT },
1871   { FLOAT },
1872   { FLOAT },
1873   { FLOAT },
1874   { FLOAT },
1875   /* e0 */
1876   { "loopneFH",         { Jb, XX, loop_jcxz_flag } },
1877   { "loopeFH",          { Jb, XX, loop_jcxz_flag } },
1878   { "loopFH",           { Jb, XX, loop_jcxz_flag } },
1879   { "jEcxzH",           { Jb, XX, loop_jcxz_flag } },
1880   { "inB",              { AL, Ib } },
1881   { "inG",              { zAX, Ib } },
1882   { "outB",             { Ib, AL } },
1883   { "outG",             { Ib, zAX } },
1884   /* e8 */
1885   { "callT",            { Jv } },
1886   { "jmpT",             { Jv } },
1887   { X86_64_TABLE (X86_64_EA) },
1888   { "jmp",              { Jb } },
1889   { "inB",              { AL, indirDX } },
1890   { "inG",              { zAX, indirDX } },
1891   { "outB",             { indirDX, AL } },
1892   { "outG",             { indirDX, zAX } },
1893   /* f0 */
1894   { Bad_Opcode },       /* lock prefix */
1895   { "icebp",            { XX } },
1896   { Bad_Opcode },       /* repne */
1897   { Bad_Opcode },       /* repz */
1898   { "hlt",              { XX } },
1899   { "cmc",              { XX } },
1900   { REG_TABLE (REG_F6) },
1901   { REG_TABLE (REG_F7) },
1902   /* f8 */
1903   { "clc",              { XX } },
1904   { "stc",              { XX } },
1905   { "cli",              { XX } },
1906   { "sti",              { XX } },
1907   { "cld",              { XX } },
1908   { "std",              { XX } },
1909   { REG_TABLE (REG_FE) },
1910   { REG_TABLE (REG_FF) },
1911 };
1912
1913 static const struct dis386 dis386_twobyte[] = {
1914   /* 00 */
1915   { REG_TABLE (REG_0F00 ) },
1916   { REG_TABLE (REG_0F01 ) },
1917   { "larS",             { Gv, Ew } },
1918   { "lslS",             { Gv, Ew } },
1919   { Bad_Opcode },
1920   { "syscall",          { XX } },
1921   { "clts",             { XX } },
1922   { "sysretP",          { XX } },
1923   /* 08 */
1924   { "invd",             { XX } },
1925   { "wbinvd",           { XX } },
1926   { Bad_Opcode },
1927   { "ud2a",             { XX } },
1928   { Bad_Opcode },
1929   { REG_TABLE (REG_0F0D) },
1930   { "femms",            { XX } },
1931   { "",                 { MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
1932   /* 10 */
1933   { PREFIX_TABLE (PREFIX_0F10) },
1934   { PREFIX_TABLE (PREFIX_0F11) },
1935   { PREFIX_TABLE (PREFIX_0F12) },
1936   { MOD_TABLE (MOD_0F13) },
1937   { "unpcklpX",         { XM, EXx } },
1938   { "unpckhpX",         { XM, EXx } },
1939   { PREFIX_TABLE (PREFIX_0F16) },
1940   { MOD_TABLE (MOD_0F17) },
1941   /* 18 */
1942   { REG_TABLE (REG_0F18) },
1943   { "nopQ",             { Ev } },
1944   { "nopQ",             { Ev } },
1945   { "nopQ",             { Ev } },
1946   { "nopQ",             { Ev } },
1947   { "nopQ",             { Ev } },
1948   { "nopQ",             { Ev } },
1949   { "nopQ",             { Ev } },
1950   /* 20 */
1951   { MOD_TABLE (MOD_0F20) },
1952   { MOD_TABLE (MOD_0F21) },
1953   { MOD_TABLE (MOD_0F22) },
1954   { MOD_TABLE (MOD_0F23) },
1955   { MOD_TABLE (MOD_0F24) },
1956   { Bad_Opcode },
1957   { MOD_TABLE (MOD_0F26) },
1958   { Bad_Opcode },
1959   /* 28 */
1960   { "movapX",           { XM, EXx } },
1961   { "movapX",           { EXxS, XM } },
1962   { PREFIX_TABLE (PREFIX_0F2A) },
1963   { PREFIX_TABLE (PREFIX_0F2B) },
1964   { PREFIX_TABLE (PREFIX_0F2C) },
1965   { PREFIX_TABLE (PREFIX_0F2D) },
1966   { PREFIX_TABLE (PREFIX_0F2E) },
1967   { PREFIX_TABLE (PREFIX_0F2F) },
1968   /* 30 */
1969   { "wrmsr",            { XX } },
1970   { "rdtsc",            { XX } },
1971   { "rdmsr",            { XX } },
1972   { "rdpmc",            { XX } },
1973   { "sysenter",         { XX } },
1974   { "sysexit",          { XX } },
1975   { Bad_Opcode },
1976   { "getsec",           { XX } },
1977   /* 38 */
1978   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1979   { Bad_Opcode },
1980   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1981   { Bad_Opcode },
1982   { Bad_Opcode },
1983   { Bad_Opcode },
1984   { Bad_Opcode },
1985   { Bad_Opcode },
1986   /* 40 */
1987   { "cmovoS",           { Gv, Ev } },
1988   { "cmovnoS",          { Gv, Ev } },
1989   { "cmovbS",           { Gv, Ev } },
1990   { "cmovaeS",          { Gv, Ev } },
1991   { "cmoveS",           { Gv, Ev } },
1992   { "cmovneS",          { Gv, Ev } },
1993   { "cmovbeS",          { Gv, Ev } },
1994   { "cmovaS",           { Gv, Ev } },
1995   /* 48 */
1996   { "cmovsS",           { Gv, Ev } },
1997   { "cmovnsS",          { Gv, Ev } },
1998   { "cmovpS",           { Gv, Ev } },
1999   { "cmovnpS",          { Gv, Ev } },
2000   { "cmovlS",           { Gv, Ev } },
2001   { "cmovgeS",          { Gv, Ev } },
2002   { "cmovleS",          { Gv, Ev } },
2003   { "cmovgS",           { Gv, Ev } },
2004   /* 50 */
2005   { MOD_TABLE (MOD_0F51) },
2006   { PREFIX_TABLE (PREFIX_0F51) },
2007   { PREFIX_TABLE (PREFIX_0F52) },
2008   { PREFIX_TABLE (PREFIX_0F53) },
2009   { "andpX",            { XM, EXx } },
2010   { "andnpX",           { XM, EXx } },
2011   { "orpX",             { XM, EXx } },
2012   { "xorpX",            { XM, EXx } },
2013   /* 58 */
2014   { PREFIX_TABLE (PREFIX_0F58) },
2015   { PREFIX_TABLE (PREFIX_0F59) },
2016   { PREFIX_TABLE (PREFIX_0F5A) },
2017   { PREFIX_TABLE (PREFIX_0F5B) },
2018   { PREFIX_TABLE (PREFIX_0F5C) },
2019   { PREFIX_TABLE (PREFIX_0F5D) },
2020   { PREFIX_TABLE (PREFIX_0F5E) },
2021   { PREFIX_TABLE (PREFIX_0F5F) },
2022   /* 60 */
2023   { PREFIX_TABLE (PREFIX_0F60) },
2024   { PREFIX_TABLE (PREFIX_0F61) },
2025   { PREFIX_TABLE (PREFIX_0F62) },
2026   { "packsswb",         { MX, EM } },
2027   { "pcmpgtb",          { MX, EM } },
2028   { "pcmpgtw",          { MX, EM } },
2029   { "pcmpgtd",          { MX, EM } },
2030   { "packuswb",         { MX, EM } },
2031   /* 68 */
2032   { "punpckhbw",        { MX, EM } },
2033   { "punpckhwd",        { MX, EM } },
2034   { "punpckhdq",        { MX, EM } },
2035   { "packssdw",         { MX, EM } },
2036   { PREFIX_TABLE (PREFIX_0F6C) },
2037   { PREFIX_TABLE (PREFIX_0F6D) },
2038   { "movK",             { MX, Edq } },
2039   { PREFIX_TABLE (PREFIX_0F6F) },
2040   /* 70 */
2041   { PREFIX_TABLE (PREFIX_0F70) },
2042   { REG_TABLE (REG_0F71) },
2043   { REG_TABLE (REG_0F72) },
2044   { REG_TABLE (REG_0F73) },
2045   { "pcmpeqb",          { MX, EM } },
2046   { "pcmpeqw",          { MX, EM } },
2047   { "pcmpeqd",          { MX, EM } },
2048   { "emms",             { XX } },
2049   /* 78 */
2050   { PREFIX_TABLE (PREFIX_0F78) },
2051   { PREFIX_TABLE (PREFIX_0F79) },
2052   { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2053   { Bad_Opcode },
2054   { PREFIX_TABLE (PREFIX_0F7C) },
2055   { PREFIX_TABLE (PREFIX_0F7D) },
2056   { PREFIX_TABLE (PREFIX_0F7E) },
2057   { PREFIX_TABLE (PREFIX_0F7F) },
2058   /* 80 */
2059   { "joH",              { Jv, XX, cond_jump_flag } },
2060   { "jnoH",             { Jv, XX, cond_jump_flag } },
2061   { "jbH",              { Jv, XX, cond_jump_flag } },
2062   { "jaeH",             { Jv, XX, cond_jump_flag } },
2063   { "jeH",              { Jv, XX, cond_jump_flag } },
2064   { "jneH",             { Jv, XX, cond_jump_flag } },
2065   { "jbeH",             { Jv, XX, cond_jump_flag } },
2066   { "jaH",              { Jv, XX, cond_jump_flag } },
2067   /* 88 */
2068   { "jsH",              { Jv, XX, cond_jump_flag } },
2069   { "jnsH",             { Jv, XX, cond_jump_flag } },
2070   { "jpH",              { Jv, XX, cond_jump_flag } },
2071   { "jnpH",             { Jv, XX, cond_jump_flag } },
2072   { "jlH",              { Jv, XX, cond_jump_flag } },
2073   { "jgeH",             { Jv, XX, cond_jump_flag } },
2074   { "jleH",             { Jv, XX, cond_jump_flag } },
2075   { "jgH",              { Jv, XX, cond_jump_flag } },
2076   /* 90 */
2077   { "seto",             { Eb } },
2078   { "setno",            { Eb } },
2079   { "setb",             { Eb } },
2080   { "setae",            { Eb } },
2081   { "sete",             { Eb } },
2082   { "setne",            { Eb } },
2083   { "setbe",            { Eb } },
2084   { "seta",             { Eb } },
2085   /* 98 */
2086   { "sets",             { Eb } },
2087   { "setns",            { Eb } },
2088   { "setp",             { Eb } },
2089   { "setnp",            { Eb } },
2090   { "setl",             { Eb } },
2091   { "setge",            { Eb } },
2092   { "setle",            { Eb } },
2093   { "setg",             { Eb } },
2094   /* a0 */
2095   { "pushT",            { fs } },
2096   { "popT",             { fs } },
2097   { "cpuid",            { XX } },
2098   { "btS",              { Ev, Gv } },
2099   { "shldS",            { Ev, Gv, Ib } },
2100   { "shldS",            { Ev, Gv, CL } },
2101   { REG_TABLE (REG_0FA6) },
2102   { REG_TABLE (REG_0FA7) },
2103   /* a8 */
2104   { "pushT",            { gs } },
2105   { "popT",             { gs } },
2106   { "rsm",              { XX } },
2107   { "btsS",             { Ev, Gv } },
2108   { "shrdS",            { Ev, Gv, Ib } },
2109   { "shrdS",            { Ev, Gv, CL } },
2110   { REG_TABLE (REG_0FAE) },
2111   { "imulS",            { Gv, Ev } },
2112   /* b0 */
2113   { "cmpxchgB",         { Eb, Gb } },
2114   { "cmpxchgS",         { Ev, Gv } },
2115   { MOD_TABLE (MOD_0FB2) },
2116   { "btrS",             { Ev, Gv } },
2117   { MOD_TABLE (MOD_0FB4) },
2118   { MOD_TABLE (MOD_0FB5) },
2119   { "movz{bR|x}",       { Gv, Eb } },
2120   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
2121   /* b8 */
2122   { PREFIX_TABLE (PREFIX_0FB8) },
2123   { "ud2b",             { XX } },
2124   { REG_TABLE (REG_0FBA) },
2125   { "btcS",             { Ev, Gv } },
2126   { "bsfS",             { Gv, Ev } },
2127   { PREFIX_TABLE (PREFIX_0FBD) },
2128   { "movs{bR|x}",       { Gv, Eb } },
2129   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
2130   /* c0 */
2131   { "xaddB",            { Eb, Gb } },
2132   { "xaddS",            { Ev, Gv } },
2133   { PREFIX_TABLE (PREFIX_0FC2) },
2134   { PREFIX_TABLE (PREFIX_0FC3) },
2135   { "pinsrw",           { MX, Edqw, Ib } },
2136   { "pextrw",           { Gdq, MS, Ib } },
2137   { "shufpX",           { XM, EXx, Ib } },
2138   { REG_TABLE (REG_0FC7) },
2139   /* c8 */
2140   { "bswap",            { RMeAX } },
2141   { "bswap",            { RMeCX } },
2142   { "bswap",            { RMeDX } },
2143   { "bswap",            { RMeBX } },
2144   { "bswap",            { RMeSP } },
2145   { "bswap",            { RMeBP } },
2146   { "bswap",            { RMeSI } },
2147   { "bswap",            { RMeDI } },
2148   /* d0 */
2149   { PREFIX_TABLE (PREFIX_0FD0) },
2150   { "psrlw",            { MX, EM } },
2151   { "psrld",            { MX, EM } },
2152   { "psrlq",            { MX, EM } },
2153   { "paddq",            { MX, EM } },
2154   { "pmullw",           { MX, EM } },
2155   { PREFIX_TABLE (PREFIX_0FD6) },
2156   { MOD_TABLE (MOD_0FD7) },
2157   /* d8 */
2158   { "psubusb",          { MX, EM } },
2159   { "psubusw",          { MX, EM } },
2160   { "pminub",           { MX, EM } },
2161   { "pand",             { MX, EM } },
2162   { "paddusb",          { MX, EM } },
2163   { "paddusw",          { MX, EM } },
2164   { "pmaxub",           { MX, EM } },
2165   { "pandn",            { MX, EM } },
2166   /* e0 */
2167   { "pavgb",            { MX, EM } },
2168   { "psraw",            { MX, EM } },
2169   { "psrad",            { MX, EM } },
2170   { "pavgw",            { MX, EM } },
2171   { "pmulhuw",          { MX, EM } },
2172   { "pmulhw",           { MX, EM } },
2173   { PREFIX_TABLE (PREFIX_0FE6) },
2174   { PREFIX_TABLE (PREFIX_0FE7) },
2175   /* e8 */
2176   { "psubsb",           { MX, EM } },
2177   { "psubsw",           { MX, EM } },
2178   { "pminsw",           { MX, EM } },
2179   { "por",              { MX, EM } },
2180   { "paddsb",           { MX, EM } },
2181   { "paddsw",           { MX, EM } },
2182   { "pmaxsw",           { MX, EM } },
2183   { "pxor",             { MX, EM } },
2184   /* f0 */
2185   { PREFIX_TABLE (PREFIX_0FF0) },
2186   { "psllw",            { MX, EM } },
2187   { "pslld",            { MX, EM } },
2188   { "psllq",            { MX, EM } },
2189   { "pmuludq",          { MX, EM } },
2190   { "pmaddwd",          { MX, EM } },
2191   { "psadbw",           { MX, EM } },
2192   { PREFIX_TABLE (PREFIX_0FF7) },
2193   /* f8 */
2194   { "psubb",            { MX, EM } },
2195   { "psubw",            { MX, EM } },
2196   { "psubd",            { MX, EM } },
2197   { "psubq",            { MX, EM } },
2198   { "paddb",            { MX, EM } },
2199   { "paddw",            { MX, EM } },
2200   { "paddd",            { MX, EM } },
2201   { Bad_Opcode },
2202 };
2203
2204 static const unsigned char onebyte_has_modrm[256] = {
2205   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2206   /*       -------------------------------        */
2207   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2208   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2209   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2210   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2211   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2212   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2213   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2214   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2215   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2216   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2217   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2218   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2219   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2220   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2221   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2222   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2223   /*       -------------------------------        */
2224   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2225 };
2226
2227 static const unsigned char twobyte_has_modrm[256] = {
2228   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2229   /*       -------------------------------        */
2230   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2231   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2232   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2233   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2234   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2235   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2236   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2237   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2238   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2239   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2240   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2241   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2242   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2243   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2244   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2245   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
2246   /*       -------------------------------        */
2247   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2248 };
2249
2250 static char obuf[100];
2251 static char *obufp;
2252 static char *mnemonicendp;
2253 static char scratchbuf[100];
2254 static unsigned char *start_codep;
2255 static unsigned char *insn_codep;
2256 static unsigned char *codep;
2257 static int last_lock_prefix;
2258 static int last_repz_prefix;
2259 static int last_repnz_prefix;
2260 static int last_data_prefix;
2261 static int last_addr_prefix;
2262 static int last_rex_prefix;
2263 static int last_seg_prefix;
2264 #define MAX_CODE_LENGTH 15
2265 /* We can up to 14 prefixes since the maximum instruction length is
2266    15bytes.  */
2267 static int all_prefixes[MAX_CODE_LENGTH - 1];
2268 static disassemble_info *the_info;
2269 static struct
2270   {
2271     int mod;
2272     int reg;
2273     int rm;
2274   }
2275 modrm;
2276 static unsigned char need_modrm;
2277 static struct
2278   {
2279     int register_specifier;
2280     int length;
2281     int prefix;
2282     int w;
2283   }
2284 vex;
2285 static unsigned char need_vex;
2286 static unsigned char need_vex_reg;
2287 static unsigned char vex_w_done;
2288
2289 struct op
2290   {
2291     const char *name;
2292     unsigned int len;
2293   };
2294
2295 /* If we are accessing mod/rm/reg without need_modrm set, then the
2296    values are stale.  Hitting this abort likely indicates that you
2297    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2298 #define MODRM_CHECK  if (!need_modrm) abort ()
2299
2300 static const char **names64;
2301 static const char **names32;
2302 static const char **names16;
2303 static const char **names8;
2304 static const char **names8rex;
2305 static const char **names_seg;
2306 static const char *index64;
2307 static const char *index32;
2308 static const char **index16;
2309
2310 static const char *intel_names64[] = {
2311   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2312   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2313 };
2314 static const char *intel_names32[] = {
2315   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2316   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2317 };
2318 static const char *intel_names16[] = {
2319   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2320   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2321 };
2322 static const char *intel_names8[] = {
2323   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2324 };
2325 static const char *intel_names8rex[] = {
2326   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2327   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2328 };
2329 static const char *intel_names_seg[] = {
2330   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2331 };
2332 static const char *intel_index64 = "riz";
2333 static const char *intel_index32 = "eiz";
2334 static const char *intel_index16[] = {
2335   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2336 };
2337
2338 static const char *att_names64[] = {
2339   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2340   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2341 };
2342 static const char *att_names32[] = {
2343   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2344   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2345 };
2346 static const char *att_names16[] = {
2347   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2348   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2349 };
2350 static const char *att_names8[] = {
2351   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2352 };
2353 static const char *att_names8rex[] = {
2354   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2355   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2356 };
2357 static const char *att_names_seg[] = {
2358   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2359 };
2360 static const char *att_index64 = "%riz";
2361 static const char *att_index32 = "%eiz";
2362 static const char *att_index16[] = {
2363   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2364 };
2365
2366 static const char **names_mm;
2367 static const char *intel_names_mm[] = {
2368   "mm0", "mm1", "mm2", "mm3",
2369   "mm4", "mm5", "mm6", "mm7"
2370 };
2371 static const char *att_names_mm[] = {
2372   "%mm0", "%mm1", "%mm2", "%mm3",
2373   "%mm4", "%mm5", "%mm6", "%mm7"
2374 };
2375
2376 static const char **names_xmm;
2377 static const char *intel_names_xmm[] = {
2378   "xmm0", "xmm1", "xmm2", "xmm3",
2379   "xmm4", "xmm5", "xmm6", "xmm7",
2380   "xmm8", "xmm9", "xmm10", "xmm11",
2381   "xmm12", "xmm13", "xmm14", "xmm15"
2382 };
2383 static const char *att_names_xmm[] = {
2384   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2385   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2386   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2387   "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2388 };
2389
2390 static const char **names_ymm;
2391 static const char *intel_names_ymm[] = {
2392   "ymm0", "ymm1", "ymm2", "ymm3",
2393   "ymm4", "ymm5", "ymm6", "ymm7",
2394   "ymm8", "ymm9", "ymm10", "ymm11",
2395   "ymm12", "ymm13", "ymm14", "ymm15"
2396 };
2397 static const char *att_names_ymm[] = {
2398   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2399   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2400   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2401   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2402 };
2403
2404 static const struct dis386 reg_table[][8] = {
2405   /* REG_80 */
2406   {
2407     { "addA",   { Eb, Ib } },
2408     { "orA",    { Eb, Ib } },
2409     { "adcA",   { Eb, Ib } },
2410     { "sbbA",   { Eb, Ib } },
2411     { "andA",   { Eb, Ib } },
2412     { "subA",   { Eb, Ib } },
2413     { "xorA",   { Eb, Ib } },
2414     { "cmpA",   { Eb, Ib } },
2415   },
2416   /* REG_81 */
2417   {
2418     { "addQ",   { Ev, Iv } },
2419     { "orQ",    { Ev, Iv } },
2420     { "adcQ",   { Ev, Iv } },
2421     { "sbbQ",   { Ev, Iv } },
2422     { "andQ",   { Ev, Iv } },
2423     { "subQ",   { Ev, Iv } },
2424     { "xorQ",   { Ev, Iv } },
2425     { "cmpQ",   { Ev, Iv } },
2426   },
2427   /* REG_82 */
2428   {
2429     { "addQ",   { Ev, sIb } },
2430     { "orQ",    { Ev, sIb } },
2431     { "adcQ",   { Ev, sIb } },
2432     { "sbbQ",   { Ev, sIb } },
2433     { "andQ",   { Ev, sIb } },
2434     { "subQ",   { Ev, sIb } },
2435     { "xorQ",   { Ev, sIb } },
2436     { "cmpQ",   { Ev, sIb } },
2437   },
2438   /* REG_8F */
2439   {
2440     { "popU",   { stackEv } },
2441     { XOP_8F_TABLE (XOP_09) },
2442     { Bad_Opcode },
2443     { Bad_Opcode },
2444     { Bad_Opcode },
2445     { XOP_8F_TABLE (XOP_09) },
2446   },
2447   /* REG_C0 */
2448   {
2449     { "rolA",   { Eb, Ib } },
2450     { "rorA",   { Eb, Ib } },
2451     { "rclA",   { Eb, Ib } },
2452     { "rcrA",   { Eb, Ib } },
2453     { "shlA",   { Eb, Ib } },
2454     { "shrA",   { Eb, Ib } },
2455     { Bad_Opcode },
2456     { "sarA",   { Eb, Ib } },
2457   },
2458   /* REG_C1 */
2459   {
2460     { "rolQ",   { Ev, Ib } },
2461     { "rorQ",   { Ev, Ib } },
2462     { "rclQ",   { Ev, Ib } },
2463     { "rcrQ",   { Ev, Ib } },
2464     { "shlQ",   { Ev, Ib } },
2465     { "shrQ",   { Ev, Ib } },
2466     { Bad_Opcode },
2467     { "sarQ",   { Ev, Ib } },
2468   },
2469   /* REG_C6 */
2470   {
2471     { "movA",   { Eb, Ib } },
2472   },
2473   /* REG_C7 */
2474   {
2475     { "movQ",   { Ev, Iv } },
2476   },
2477   /* REG_D0 */
2478   {
2479     { "rolA",   { Eb, I1 } },
2480     { "rorA",   { Eb, I1 } },
2481     { "rclA",   { Eb, I1 } },
2482     { "rcrA",   { Eb, I1 } },
2483     { "shlA",   { Eb, I1 } },
2484     { "shrA",   { Eb, I1 } },
2485     { Bad_Opcode },
2486     { "sarA",   { Eb, I1 } },
2487   },
2488   /* REG_D1 */
2489   {
2490     { "rolQ",   { Ev, I1 } },
2491     { "rorQ",   { Ev, I1 } },
2492     { "rclQ",   { Ev, I1 } },
2493     { "rcrQ",   { Ev, I1 } },
2494     { "shlQ",   { Ev, I1 } },
2495     { "shrQ",   { Ev, I1 } },
2496     { Bad_Opcode },
2497     { "sarQ",   { Ev, I1 } },
2498   },
2499   /* REG_D2 */
2500   {
2501     { "rolA",   { Eb, CL } },
2502     { "rorA",   { Eb, CL } },
2503     { "rclA",   { Eb, CL } },
2504     { "rcrA",   { Eb, CL } },
2505     { "shlA",   { Eb, CL } },
2506     { "shrA",   { Eb, CL } },
2507     { Bad_Opcode },
2508     { "sarA",   { Eb, CL } },
2509   },
2510   /* REG_D3 */
2511   {
2512     { "rolQ",   { Ev, CL } },
2513     { "rorQ",   { Ev, CL } },
2514     { "rclQ",   { Ev, CL } },
2515     { "rcrQ",   { Ev, CL } },
2516     { "shlQ",   { Ev, CL } },
2517     { "shrQ",   { Ev, CL } },
2518     { Bad_Opcode },
2519     { "sarQ",   { Ev, CL } },
2520   },
2521   /* REG_F6 */
2522   {
2523     { "testA",  { Eb, Ib } },
2524     { Bad_Opcode },
2525     { "notA",   { Eb } },
2526     { "negA",   { Eb } },
2527     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
2528     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
2529     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
2530     { "idivA",  { Eb } },       /* and idiv for consistency.               */
2531   },
2532   /* REG_F7 */
2533   {
2534     { "testQ",  { Ev, Iv } },
2535     { Bad_Opcode },
2536     { "notQ",   { Ev } },
2537     { "negQ",   { Ev } },
2538     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
2539     { "imulQ",  { Ev } },
2540     { "divQ",   { Ev } },
2541     { "idivQ",  { Ev } },
2542   },
2543   /* REG_FE */
2544   {
2545     { "incA",   { Eb } },
2546     { "decA",   { Eb } },
2547   },
2548   /* REG_FF */
2549   {
2550     { "incQ",   { Ev } },
2551     { "decQ",   { Ev } },
2552     { "callT",  { indirEv } },
2553     { "JcallT", { indirEp } },
2554     { "jmpT",   { indirEv } },
2555     { "JjmpT",  { indirEp } },
2556     { "pushU",  { stackEv } },
2557     { Bad_Opcode },
2558   },
2559   /* REG_0F00 */
2560   {
2561     { "sldtD",  { Sv } },
2562     { "strD",   { Sv } },
2563     { "lldt",   { Ew } },
2564     { "ltr",    { Ew } },
2565     { "verr",   { Ew } },
2566     { "verw",   { Ew } },
2567     { Bad_Opcode },
2568     { Bad_Opcode },
2569   },
2570   /* REG_0F01 */
2571   {
2572     { MOD_TABLE (MOD_0F01_REG_0) },
2573     { MOD_TABLE (MOD_0F01_REG_1) },
2574     { MOD_TABLE (MOD_0F01_REG_2) },
2575     { MOD_TABLE (MOD_0F01_REG_3) },
2576     { "smswD",  { Sv } },
2577     { Bad_Opcode },
2578     { "lmsw",   { Ew } },
2579     { MOD_TABLE (MOD_0F01_REG_7) },
2580   },
2581   /* REG_0F0D */
2582   {
2583     { "prefetch",       { Eb } },
2584     { "prefetchw",      { Eb } },
2585   },
2586   /* REG_0F18 */
2587   {
2588     { MOD_TABLE (MOD_0F18_REG_0) },
2589     { MOD_TABLE (MOD_0F18_REG_1) },
2590     { MOD_TABLE (MOD_0F18_REG_2) },
2591     { MOD_TABLE (MOD_0F18_REG_3) },
2592   },
2593   /* REG_0F71 */
2594   {
2595     { Bad_Opcode },
2596     { Bad_Opcode },
2597     { MOD_TABLE (MOD_0F71_REG_2) },
2598     { Bad_Opcode },
2599     { MOD_TABLE (MOD_0F71_REG_4) },
2600     { Bad_Opcode },
2601     { MOD_TABLE (MOD_0F71_REG_6) },
2602   },
2603   /* REG_0F72 */
2604   {
2605     { Bad_Opcode },
2606     { Bad_Opcode },
2607     { MOD_TABLE (MOD_0F72_REG_2) },
2608     { Bad_Opcode },
2609     { MOD_TABLE (MOD_0F72_REG_4) },
2610     { Bad_Opcode },
2611     { MOD_TABLE (MOD_0F72_REG_6) },
2612   },
2613   /* REG_0F73 */
2614   {
2615     { Bad_Opcode },
2616     { Bad_Opcode },
2617     { MOD_TABLE (MOD_0F73_REG_2) },
2618     { MOD_TABLE (MOD_0F73_REG_3) },
2619     { Bad_Opcode },
2620     { Bad_Opcode },
2621     { MOD_TABLE (MOD_0F73_REG_6) },
2622     { MOD_TABLE (MOD_0F73_REG_7) },
2623   },
2624   /* REG_0FA6 */
2625   {
2626     { "montmul",        { { OP_0f07, 0 } } },
2627     { "xsha1",          { { OP_0f07, 0 } } },
2628     { "xsha256",        { { OP_0f07, 0 } } },
2629   },
2630   /* REG_0FA7 */
2631   {
2632     { "xstore-rng",     { { OP_0f07, 0 } } },
2633     { "xcrypt-ecb",     { { OP_0f07, 0 } } },
2634     { "xcrypt-cbc",     { { OP_0f07, 0 } } },
2635     { "xcrypt-ctr",     { { OP_0f07, 0 } } },
2636     { "xcrypt-cfb",     { { OP_0f07, 0 } } },
2637     { "xcrypt-ofb",     { { OP_0f07, 0 } } },
2638   },
2639   /* REG_0FAE */
2640   {
2641     { MOD_TABLE (MOD_0FAE_REG_0) },
2642     { MOD_TABLE (MOD_0FAE_REG_1) },
2643     { MOD_TABLE (MOD_0FAE_REG_2) },
2644     { MOD_TABLE (MOD_0FAE_REG_3) },
2645     { MOD_TABLE (MOD_0FAE_REG_4) },
2646     { MOD_TABLE (MOD_0FAE_REG_5) },
2647     { MOD_TABLE (MOD_0FAE_REG_6) },
2648     { MOD_TABLE (MOD_0FAE_REG_7) },
2649   },
2650   /* REG_0FBA */
2651   {
2652     { Bad_Opcode },
2653     { Bad_Opcode },
2654     { Bad_Opcode },
2655     { Bad_Opcode },
2656     { "btQ",    { Ev, Ib } },
2657     { "btsQ",   { Ev, Ib } },
2658     { "btrQ",   { Ev, Ib } },
2659     { "btcQ",   { Ev, Ib } },
2660   },
2661   /* REG_0FC7 */
2662   {
2663     { Bad_Opcode },
2664     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2665     { Bad_Opcode },
2666     { Bad_Opcode },
2667     { Bad_Opcode },
2668     { Bad_Opcode },
2669     { MOD_TABLE (MOD_0FC7_REG_6) },
2670     { MOD_TABLE (MOD_0FC7_REG_7) },
2671   },
2672   /* REG_VEX_71 */
2673   {
2674     { Bad_Opcode },
2675     { Bad_Opcode },
2676     { MOD_TABLE (MOD_VEX_71_REG_2) },
2677     { Bad_Opcode },
2678     { MOD_TABLE (MOD_VEX_71_REG_4) },
2679     { Bad_Opcode },
2680     { MOD_TABLE (MOD_VEX_71_REG_6) },
2681   },
2682   /* REG_VEX_72 */
2683   {
2684     { Bad_Opcode },
2685     { Bad_Opcode },
2686     { MOD_TABLE (MOD_VEX_72_REG_2) },
2687     { Bad_Opcode },
2688     { MOD_TABLE (MOD_VEX_72_REG_4) },
2689     { Bad_Opcode },
2690     { MOD_TABLE (MOD_VEX_72_REG_6) },
2691   },
2692   /* REG_VEX_73 */
2693   {
2694     { Bad_Opcode },
2695     { Bad_Opcode },
2696     { MOD_TABLE (MOD_VEX_73_REG_2) },
2697     { MOD_TABLE (MOD_VEX_73_REG_3) },
2698     { Bad_Opcode },
2699     { Bad_Opcode },
2700     { MOD_TABLE (MOD_VEX_73_REG_6) },
2701     { MOD_TABLE (MOD_VEX_73_REG_7) },
2702   },
2703   /* REG_VEX_AE */
2704   {
2705     { Bad_Opcode },
2706     { Bad_Opcode },
2707     { MOD_TABLE (MOD_VEX_AE_REG_2) },
2708     { MOD_TABLE (MOD_VEX_AE_REG_3) },
2709   },
2710   /* REG_XOP_LWPCB */
2711   {
2712     { "llwpcb", { { OP_LWPCB_E, 0 } } },
2713     { "slwpcb", { { OP_LWPCB_E, 0 } } },
2714   },
2715   /* REG_XOP_LWP */
2716   {
2717     { "lwpins", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2718     { "lwpval", { { OP_LWP_E, 0 }, Ed, { OP_LWP_I, 0 } } },
2719   },
2720 };
2721
2722 static const struct dis386 prefix_table[][4] = {
2723   /* PREFIX_90 */
2724   {
2725     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2726     { "pause", { XX } },
2727     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2728   },
2729
2730   /* PREFIX_0F10 */
2731   {
2732     { "movups", { XM, EXx } },
2733     { "movss",  { XM, EXd } },
2734     { "movupd", { XM, EXx } },
2735     { "movsd",  { XM, EXq } },
2736   },
2737
2738   /* PREFIX_0F11 */
2739   {
2740     { "movups", { EXxS, XM } },
2741     { "movss",  { EXdS, XM } },
2742     { "movupd", { EXxS, XM } },
2743     { "movsd",  { EXqS, XM } },
2744   },
2745
2746   /* PREFIX_0F12 */
2747   {
2748     { MOD_TABLE (MOD_0F12_PREFIX_0) },
2749     { "movsldup", { XM, EXx } },
2750     { "movlpd", { XM, EXq } },
2751     { "movddup", { XM, EXq } },
2752   },
2753
2754   /* PREFIX_0F16 */
2755   {
2756     { MOD_TABLE (MOD_0F16_PREFIX_0) },
2757     { "movshdup", { XM, EXx } },
2758     { "movhpd", { XM, EXq } },
2759   },
2760
2761   /* PREFIX_0F2A */
2762   {
2763     { "cvtpi2ps", { XM, EMCq } },
2764     { "cvtsi2ss%LQ", { XM, Ev } },
2765     { "cvtpi2pd", { XM, EMCq } },
2766     { "cvtsi2sd%LQ", { XM, Ev } },
2767   },
2768
2769   /* PREFIX_0F2B */
2770   {
2771     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2772     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2773     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2774     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2775   },
2776
2777   /* PREFIX_0F2C */
2778   {
2779     { "cvttps2pi", { MXC, EXq } },
2780     { "cvttss2siY", { Gv, EXd } },
2781     { "cvttpd2pi", { MXC, EXx } },
2782     { "cvttsd2siY", { Gv, EXq } },
2783   },
2784
2785   /* PREFIX_0F2D */
2786   {
2787     { "cvtps2pi", { MXC, EXq } },
2788     { "cvtss2siY", { Gv, EXd } },
2789     { "cvtpd2pi", { MXC, EXx } },
2790     { "cvtsd2siY", { Gv, EXq } },
2791   },
2792
2793   /* PREFIX_0F2E */
2794   {
2795     { "ucomiss",{ XM, EXd } },
2796     { Bad_Opcode },
2797     { "ucomisd",{ XM, EXq } },
2798   },
2799
2800   /* PREFIX_0F2F */
2801   {
2802     { "comiss", { XM, EXd } },
2803     { Bad_Opcode },
2804     { "comisd", { XM, EXq } },
2805   },
2806
2807   /* PREFIX_0F51 */
2808   {
2809     { "sqrtps", { XM, EXx } },
2810     { "sqrtss", { XM, EXd } },
2811     { "sqrtpd", { XM, EXx } },
2812     { "sqrtsd", { XM, EXq } },
2813   },
2814
2815   /* PREFIX_0F52 */
2816   {
2817     { "rsqrtps",{ XM, EXx } },
2818     { "rsqrtss",{ XM, EXd } },
2819   },
2820
2821   /* PREFIX_0F53 */
2822   {
2823     { "rcpps",  { XM, EXx } },
2824     { "rcpss",  { XM, EXd } },
2825   },
2826
2827   /* PREFIX_0F58 */
2828   {
2829     { "addps", { XM, EXx } },
2830     { "addss", { XM, EXd } },
2831     { "addpd", { XM, EXx } },
2832     { "addsd", { XM, EXq } },
2833   },
2834
2835   /* PREFIX_0F59 */
2836   {
2837     { "mulps",  { XM, EXx } },
2838     { "mulss",  { XM, EXd } },
2839     { "mulpd",  { XM, EXx } },
2840     { "mulsd",  { XM, EXq } },
2841   },
2842
2843   /* PREFIX_0F5A */
2844   {
2845     { "cvtps2pd", { XM, EXq } },
2846     { "cvtss2sd", { XM, EXd } },
2847     { "cvtpd2ps", { XM, EXx } },
2848     { "cvtsd2ss", { XM, EXq } },
2849   },
2850
2851   /* PREFIX_0F5B */
2852   {
2853     { "cvtdq2ps", { XM, EXx } },
2854     { "cvttps2dq", { XM, EXx } },
2855     { "cvtps2dq", { XM, EXx } },
2856   },
2857
2858   /* PREFIX_0F5C */
2859   {
2860     { "subps",  { XM, EXx } },
2861     { "subss",  { XM, EXd } },
2862     { "subpd",  { XM, EXx } },
2863     { "subsd",  { XM, EXq } },
2864   },
2865
2866   /* PREFIX_0F5D */
2867   {
2868     { "minps",  { XM, EXx } },
2869     { "minss",  { XM, EXd } },
2870     { "minpd",  { XM, EXx } },
2871     { "minsd",  { XM, EXq } },
2872   },
2873
2874   /* PREFIX_0F5E */
2875   {
2876     { "divps",  { XM, EXx } },
2877     { "divss",  { XM, EXd } },
2878     { "divpd",  { XM, EXx } },
2879     { "divsd",  { XM, EXq } },
2880   },
2881
2882   /* PREFIX_0F5F */
2883   {
2884     { "maxps",  { XM, EXx } },
2885     { "maxss",  { XM, EXd } },
2886     { "maxpd",  { XM, EXx } },
2887     { "maxsd",  { XM, EXq } },
2888   },
2889
2890   /* PREFIX_0F60 */
2891   {
2892     { "punpcklbw",{ MX, EMd } },
2893     { Bad_Opcode },
2894     { "punpcklbw",{ MX, EMx } },
2895   },
2896
2897   /* PREFIX_0F61 */
2898   {
2899     { "punpcklwd",{ MX, EMd } },
2900     { Bad_Opcode },
2901     { "punpcklwd",{ MX, EMx } },
2902   },
2903
2904   /* PREFIX_0F62 */
2905   {
2906     { "punpckldq",{ MX, EMd } },
2907     { Bad_Opcode },
2908     { "punpckldq",{ MX, EMx } },
2909   },
2910
2911   /* PREFIX_0F6C */
2912   {
2913     { Bad_Opcode },
2914     { Bad_Opcode },
2915     { "punpcklqdq", { XM, EXx } },
2916   },
2917
2918   /* PREFIX_0F6D */
2919   {
2920     { Bad_Opcode },
2921     { Bad_Opcode },
2922     { "punpckhqdq", { XM, EXx } },
2923   },
2924
2925   /* PREFIX_0F6F */
2926   {
2927     { "movq",   { MX, EM } },
2928     { "movdqu", { XM, EXx } },
2929     { "movdqa", { XM, EXx } },
2930   },
2931
2932   /* PREFIX_0F70 */
2933   {
2934     { "pshufw", { MX, EM, Ib } },
2935     { "pshufhw",{ XM, EXx, Ib } },
2936     { "pshufd", { XM, EXx, Ib } },
2937     { "pshuflw",{ XM, EXx, Ib } },
2938   },
2939
2940   /* PREFIX_0F73_REG_3 */
2941   {
2942     { Bad_Opcode },
2943     { Bad_Opcode },
2944     { "psrldq", { XS, Ib } },
2945   },
2946
2947   /* PREFIX_0F73_REG_7 */
2948   {
2949     { Bad_Opcode },
2950     { Bad_Opcode },
2951     { "pslldq", { XS, Ib } },
2952   },
2953
2954   /* PREFIX_0F78 */
2955   {
2956     {"vmread",  { Em, Gm } },
2957     { Bad_Opcode },
2958     {"extrq",   { XS, Ib, Ib } },
2959     {"insertq", { XM, XS, Ib, Ib } },
2960   },
2961
2962   /* PREFIX_0F79 */
2963   {
2964     {"vmwrite", { Gm, Em } },
2965     { Bad_Opcode },
2966     {"extrq",   { XM, XS } },
2967     {"insertq", { XM, XS } },
2968   },
2969
2970   /* PREFIX_0F7C */
2971   {
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { "haddpd", { XM, EXx } },
2975     { "haddps", { XM, EXx } },
2976   },
2977
2978   /* PREFIX_0F7D */
2979   {
2980     { Bad_Opcode },
2981     { Bad_Opcode },
2982     { "hsubpd", { XM, EXx } },
2983     { "hsubps", { XM, EXx } },
2984   },
2985
2986   /* PREFIX_0F7E */
2987   {
2988     { "movK",   { Edq, MX } },
2989     { "movq",   { XM, EXq } },
2990     { "movK",   { Edq, XM } },
2991   },
2992
2993   /* PREFIX_0F7F */
2994   {
2995     { "movq",   { EMS, MX } },
2996     { "movdqu", { EXxS, XM } },
2997     { "movdqa", { EXxS, XM } },
2998   },
2999
3000   /* PREFIX_0FB8 */
3001   {
3002     { Bad_Opcode },
3003     { "popcntS", { Gv, Ev } },
3004   },
3005
3006   /* PREFIX_0FBD */
3007   {
3008     { "bsrS",   { Gv, Ev } },
3009     { "lzcntS", { Gv, Ev } },
3010     { "bsrS",   { Gv, Ev } },
3011   },
3012
3013   /* PREFIX_0FC2 */
3014   {
3015     { "cmpps",  { XM, EXx, CMP } },
3016     { "cmpss",  { XM, EXd, CMP } },
3017     { "cmppd",  { XM, EXx, CMP } },
3018     { "cmpsd",  { XM, EXq, CMP } },
3019   },
3020
3021   /* PREFIX_0FC3 */
3022   {
3023     { "movntiS", { Ma, Gv } },
3024   },
3025
3026   /* PREFIX_0FC7_REG_6 */
3027   {
3028     { "vmptrld",{ Mq } },
3029     { "vmxon",  { Mq } },
3030     { "vmclear",{ Mq } },
3031   },
3032
3033   /* PREFIX_0FD0 */
3034   {
3035     { Bad_Opcode },
3036     { Bad_Opcode },
3037     { "addsubpd", { XM, EXx } },
3038     { "addsubps", { XM, EXx } },
3039   },
3040
3041   /* PREFIX_0FD6 */
3042   {
3043     { Bad_Opcode },
3044     { "movq2dq",{ XM, MS } },
3045     { "movq",   { EXqS, XM } },
3046     { "movdq2q",{ MX, XS } },
3047   },
3048
3049   /* PREFIX_0FE6 */
3050   {
3051     { Bad_Opcode },
3052     { "cvtdq2pd", { XM, EXq } },
3053     { "cvttpd2dq", { XM, EXx } },
3054     { "cvtpd2dq", { XM, EXx } },
3055   },
3056
3057   /* PREFIX_0FE7 */
3058   {
3059     { "movntq", { Mq, MX } },
3060     { Bad_Opcode },
3061     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3062   },
3063
3064   /* PREFIX_0FF0 */
3065   {
3066     { Bad_Opcode },
3067     { Bad_Opcode },
3068     { Bad_Opcode },
3069     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3070   },
3071
3072   /* PREFIX_0FF7 */
3073   {
3074     { "maskmovq", { MX, MS } },
3075     { Bad_Opcode },
3076     { "maskmovdqu", { XM, XS } },
3077   },
3078
3079   /* PREFIX_0F3810 */
3080   {
3081     { Bad_Opcode },
3082     { Bad_Opcode },
3083     { "pblendvb", { XM, EXx, XMM0 } },
3084   },
3085
3086   /* PREFIX_0F3814 */
3087   {
3088     { Bad_Opcode },
3089     { Bad_Opcode },
3090     { "blendvps", { XM, EXx, XMM0 } },
3091   },
3092
3093   /* PREFIX_0F3815 */
3094   {
3095     { Bad_Opcode },
3096     { Bad_Opcode },
3097     { "blendvpd", { XM, EXx, XMM0 } },
3098   },
3099
3100   /* PREFIX_0F3817 */
3101   {
3102     { Bad_Opcode },
3103     { Bad_Opcode },
3104     { "ptest",  { XM, EXx } },
3105   },
3106
3107   /* PREFIX_0F3820 */
3108   {
3109     { Bad_Opcode },
3110     { Bad_Opcode },
3111     { "pmovsxbw", { XM, EXq } },
3112   },
3113
3114   /* PREFIX_0F3821 */
3115   {
3116     { Bad_Opcode },
3117     { Bad_Opcode },
3118     { "pmovsxbd", { XM, EXd } },
3119   },
3120
3121   /* PREFIX_0F3822 */
3122   {
3123     { Bad_Opcode },
3124     { Bad_Opcode },
3125     { "pmovsxbq", { XM, EXw } },
3126   },
3127
3128   /* PREFIX_0F3823 */
3129   {
3130     { Bad_Opcode },
3131     { Bad_Opcode },
3132     { "pmovsxwd", { XM, EXq } },
3133   },
3134
3135   /* PREFIX_0F3824 */
3136   {
3137     { Bad_Opcode },
3138     { Bad_Opcode },
3139     { "pmovsxwq", { XM, EXd } },
3140   },
3141
3142   /* PREFIX_0F3825 */
3143   {
3144     { Bad_Opcode },
3145     { Bad_Opcode },
3146     { "pmovsxdq", { XM, EXq } },
3147   },
3148
3149   /* PREFIX_0F3828 */
3150   {
3151     { Bad_Opcode },
3152     { Bad_Opcode },
3153     { "pmuldq", { XM, EXx } },
3154   },
3155
3156   /* PREFIX_0F3829 */
3157   {
3158     { Bad_Opcode },
3159     { Bad_Opcode },
3160     { "pcmpeqq", { XM, EXx } },
3161   },
3162
3163   /* PREFIX_0F382A */
3164   {
3165     { Bad_Opcode },
3166     { Bad_Opcode },
3167     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3168   },
3169
3170   /* PREFIX_0F382B */
3171   {
3172     { Bad_Opcode },
3173     { Bad_Opcode },
3174     { "packusdw", { XM, EXx } },
3175   },
3176
3177   /* PREFIX_0F3830 */
3178   {
3179     { Bad_Opcode },
3180     { Bad_Opcode },
3181     { "pmovzxbw", { XM, EXq } },
3182   },
3183
3184   /* PREFIX_0F3831 */
3185   {
3186     { Bad_Opcode },
3187     { Bad_Opcode },
3188     { "pmovzxbd", { XM, EXd } },
3189   },
3190
3191   /* PREFIX_0F3832 */
3192   {
3193     { Bad_Opcode },
3194     { Bad_Opcode },
3195     { "pmovzxbq", { XM, EXw } },
3196   },
3197
3198   /* PREFIX_0F3833 */
3199   {
3200     { Bad_Opcode },
3201     { Bad_Opcode },
3202     { "pmovzxwd", { XM, EXq } },
3203   },
3204
3205   /* PREFIX_0F3834 */
3206   {
3207     { Bad_Opcode },
3208     { Bad_Opcode },
3209     { "pmovzxwq", { XM, EXd } },
3210   },
3211
3212   /* PREFIX_0F3835 */
3213   {
3214     { Bad_Opcode },
3215     { Bad_Opcode },
3216     { "pmovzxdq", { XM, EXq } },
3217   },
3218
3219   /* PREFIX_0F3837 */
3220   {
3221     { Bad_Opcode },
3222     { Bad_Opcode },
3223     { "pcmpgtq", { XM, EXx } },
3224   },
3225
3226   /* PREFIX_0F3838 */
3227   {
3228     { Bad_Opcode },
3229     { Bad_Opcode },
3230     { "pminsb", { XM, EXx } },
3231   },
3232
3233   /* PREFIX_0F3839 */
3234   {
3235     { Bad_Opcode },
3236     { Bad_Opcode },
3237     { "pminsd", { XM, EXx } },
3238   },
3239
3240   /* PREFIX_0F383A */
3241   {
3242     { Bad_Opcode },
3243     { Bad_Opcode },
3244     { "pminuw", { XM, EXx } },
3245   },
3246
3247   /* PREFIX_0F383B */
3248   {
3249     { Bad_Opcode },
3250     { Bad_Opcode },
3251     { "pminud", { XM, EXx } },
3252   },
3253
3254   /* PREFIX_0F383C */
3255   {
3256     { Bad_Opcode },
3257     { Bad_Opcode },
3258     { "pmaxsb", { XM, EXx } },
3259   },
3260
3261   /* PREFIX_0F383D */
3262   {
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { "pmaxsd", { XM, EXx } },
3266   },
3267
3268   /* PREFIX_0F383E */
3269   {
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { "pmaxuw", { XM, EXx } },
3273   },
3274
3275   /* PREFIX_0F383F */
3276   {
3277     { Bad_Opcode },
3278     { Bad_Opcode },
3279     { "pmaxud", { XM, EXx } },
3280   },
3281
3282   /* PREFIX_0F3840 */
3283   {
3284     { Bad_Opcode },
3285     { Bad_Opcode },
3286     { "pmulld", { XM, EXx } },
3287   },
3288
3289   /* PREFIX_0F3841 */
3290   {
3291     { Bad_Opcode },
3292     { Bad_Opcode },
3293     { "phminposuw", { XM, EXx } },
3294   },
3295
3296   /* PREFIX_0F3880 */
3297   {
3298     { Bad_Opcode },
3299     { Bad_Opcode },
3300     { "invept", { Gm, Mo } },
3301   },
3302
3303   /* PREFIX_0F3881 */
3304   {
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { "invvpid", { Gm, Mo } },
3308   },
3309
3310   /* PREFIX_0F38DB */
3311   {
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { "aesimc", { XM, EXx } },
3315   },
3316
3317   /* PREFIX_0F38DC */
3318   {
3319     { Bad_Opcode },
3320     { Bad_Opcode },
3321     { "aesenc", { XM, EXx } },
3322   },
3323
3324   /* PREFIX_0F38DD */
3325   {
3326     { Bad_Opcode },
3327     { Bad_Opcode },
3328     { "aesenclast", { XM, EXx } },
3329   },
3330
3331   /* PREFIX_0F38DE */
3332   {
3333     { Bad_Opcode },
3334     { Bad_Opcode },
3335     { "aesdec", { XM, EXx } },
3336   },
3337
3338   /* PREFIX_0F38DF */
3339   {
3340     { Bad_Opcode },
3341     { Bad_Opcode },
3342     { "aesdeclast", { XM, EXx } },
3343   },
3344
3345   /* PREFIX_0F38F0 */
3346   {
3347     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3348     { Bad_Opcode },
3349     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3350     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } } },
3351   },
3352
3353   /* PREFIX_0F38F1 */
3354   {
3355     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3356     { Bad_Opcode },
3357     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3358     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },
3359   },
3360
3361   /* PREFIX_0F3A08 */
3362   {
3363     { Bad_Opcode },
3364     { Bad_Opcode },
3365     { "roundps", { XM, EXx, Ib } },
3366   },
3367
3368   /* PREFIX_0F3A09 */
3369   {
3370     { Bad_Opcode },
3371     { Bad_Opcode },
3372     { "roundpd", { XM, EXx, Ib } },
3373   },
3374
3375   /* PREFIX_0F3A0A */
3376   {
3377     { Bad_Opcode },
3378     { Bad_Opcode },
3379     { "roundss", { XM, EXd, Ib } },
3380   },
3381
3382   /* PREFIX_0F3A0B */
3383   {
3384     { Bad_Opcode },
3385     { Bad_Opcode },
3386     { "roundsd", { XM, EXq, Ib } },
3387   },
3388
3389   /* PREFIX_0F3A0C */
3390   {
3391     { Bad_Opcode },
3392     { Bad_Opcode },
3393     { "blendps", { XM, EXx, Ib } },
3394   },
3395
3396   /* PREFIX_0F3A0D */
3397   {
3398     { Bad_Opcode },
3399     { Bad_Opcode },
3400     { "blendpd", { XM, EXx, Ib } },
3401   },
3402
3403   /* PREFIX_0F3A0E */
3404   {
3405     { Bad_Opcode },
3406     { Bad_Opcode },
3407     { "pblendw", { XM, EXx, Ib } },
3408   },
3409
3410   /* PREFIX_0F3A14 */
3411   {
3412     { Bad_Opcode },
3413     { Bad_Opcode },
3414     { "pextrb", { Edqb, XM, Ib } },
3415   },
3416
3417   /* PREFIX_0F3A15 */
3418   {
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { "pextrw", { Edqw, XM, Ib } },
3422   },
3423
3424   /* PREFIX_0F3A16 */
3425   {
3426     { Bad_Opcode },
3427     { Bad_Opcode },
3428     { "pextrK", { Edq, XM, Ib } },
3429   },
3430
3431   /* PREFIX_0F3A17 */
3432   {
3433     { Bad_Opcode },
3434     { Bad_Opcode },
3435     { "extractps", { Edqd, XM, Ib } },
3436   },
3437
3438   /* PREFIX_0F3A20 */
3439   {
3440     { Bad_Opcode },
3441     { Bad_Opcode },
3442     { "pinsrb", { XM, Edqb, Ib } },
3443   },
3444
3445   /* PREFIX_0F3A21 */
3446   {
3447     { Bad_Opcode },
3448     { Bad_Opcode },
3449     { "insertps", { XM, EXd, Ib } },
3450   },
3451
3452   /* PREFIX_0F3A22 */
3453   {
3454     { Bad_Opcode },
3455     { Bad_Opcode },
3456     { "pinsrK", { XM, Edq, Ib } },
3457   },
3458
3459   /* PREFIX_0F3A40 */
3460   {
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { "dpps",   { XM, EXx, Ib } },
3464   },
3465
3466   /* PREFIX_0F3A41 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { "dppd",   { XM, EXx, Ib } },
3471   },
3472
3473   /* PREFIX_0F3A42 */
3474   {
3475     { Bad_Opcode },
3476     { Bad_Opcode },
3477     { "mpsadbw", { XM, EXx, Ib } },
3478   },
3479
3480   /* PREFIX_0F3A44 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { "pclmulqdq", { XM, EXx, PCLMUL } },
3485   },
3486
3487   /* PREFIX_0F3A60 */
3488   {
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { "pcmpestrm", { XM, EXx, Ib } },
3492   },
3493
3494   /* PREFIX_0F3A61 */
3495   {
3496     { Bad_Opcode },
3497     { Bad_Opcode },
3498     { "pcmpestri", { XM, EXx, Ib } },
3499   },
3500
3501   /* PREFIX_0F3A62 */
3502   {
3503     { Bad_Opcode },
3504     { Bad_Opcode },
3505     { "pcmpistrm", { XM, EXx, Ib } },
3506   },
3507
3508   /* PREFIX_0F3A63 */
3509   {
3510     { Bad_Opcode },
3511     { Bad_Opcode },
3512     { "pcmpistri", { XM, EXx, Ib } },
3513   },
3514
3515   /* PREFIX_0F3ADF */
3516   {
3517     { Bad_Opcode },
3518     { Bad_Opcode },
3519     { "aeskeygenassist", { XM, EXx, Ib } },
3520   },
3521
3522   /* PREFIX_VEX_10 */
3523   {
3524     { VEX_W_TABLE (VEX_W_10_P_0) },
3525     { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3526     { VEX_W_TABLE (VEX_W_10_P_2) },
3527     { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3528   },
3529
3530   /* PREFIX_VEX_11 */
3531   {
3532     { VEX_W_TABLE (VEX_W_11_P_0) },
3533     { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3534     { VEX_W_TABLE (VEX_W_11_P_2) },
3535     { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3536   },
3537
3538   /* PREFIX_VEX_12 */
3539   {
3540     { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3541     { VEX_W_TABLE (VEX_W_12_P_1) },
3542     { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3543     { VEX_W_TABLE (VEX_W_12_P_3) },
3544   },
3545
3546   /* PREFIX_VEX_16 */
3547   {
3548     { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3549     { VEX_W_TABLE (VEX_W_16_P_1) },
3550     { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3551   },
3552
3553   /* PREFIX_VEX_2A */
3554   {
3555     { Bad_Opcode },
3556     { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3557     { Bad_Opcode },
3558     { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3559   },
3560
3561   /* PREFIX_VEX_2C */
3562   {
3563     { Bad_Opcode },
3564     { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3565     { Bad_Opcode },
3566     { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3567   },
3568
3569   /* PREFIX_VEX_2D */
3570   {
3571     { Bad_Opcode },
3572     { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3573     { Bad_Opcode },
3574     { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3575   },
3576
3577   /* PREFIX_VEX_2E */
3578   {
3579     { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3580     { Bad_Opcode },
3581     { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3582   },
3583
3584   /* PREFIX_VEX_2F */
3585   {
3586     { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3587     { Bad_Opcode },
3588     { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3589   },
3590
3591   /* PREFIX_VEX_51 */
3592   {
3593     { VEX_W_TABLE (VEX_W_51_P_0) },
3594     { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3595     { VEX_W_TABLE (VEX_W_51_P_2) },
3596     { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3597   },
3598
3599   /* PREFIX_VEX_52 */
3600   {
3601     { VEX_W_TABLE (VEX_W_52_P_0) },
3602     { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3603   },
3604
3605   /* PREFIX_VEX_53 */
3606   {
3607     { VEX_W_TABLE (VEX_W_53_P_0) },
3608     { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3609   },
3610
3611   /* PREFIX_VEX_58 */
3612   {
3613     { VEX_W_TABLE (VEX_W_58_P_0) },
3614     { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3615     { VEX_W_TABLE (VEX_W_58_P_2) },
3616     { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3617   },
3618
3619   /* PREFIX_VEX_59 */
3620   {
3621     { VEX_W_TABLE (VEX_W_59_P_0) },
3622     { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3623     { VEX_W_TABLE (VEX_W_59_P_2) },
3624     { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3625   },
3626
3627   /* PREFIX_VEX_5A */
3628   {
3629     { VEX_W_TABLE (VEX_W_5A_P_0) },
3630     { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3631     { "vcvtpd2ps%XY", { XMM, EXx } },
3632     { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3633   },
3634
3635   /* PREFIX_VEX_5B */
3636   {
3637     { VEX_W_TABLE (VEX_W_5B_P_0) },
3638     { VEX_W_TABLE (VEX_W_5B_P_1) },
3639     { VEX_W_TABLE (VEX_W_5B_P_2) },
3640   },
3641
3642   /* PREFIX_VEX_5C */
3643   {
3644     { VEX_W_TABLE (VEX_W_5C_P_0) },
3645     { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3646     { VEX_W_TABLE (VEX_W_5C_P_2) },
3647     { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3648   },
3649
3650   /* PREFIX_VEX_5D */
3651   {
3652     { VEX_W_TABLE (VEX_W_5D_P_0) },
3653     { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3654     { VEX_W_TABLE (VEX_W_5D_P_2) },
3655     { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3656   },
3657
3658   /* PREFIX_VEX_5E */
3659   {
3660     { VEX_W_TABLE (VEX_W_5E_P_0) },
3661     { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3662     { VEX_W_TABLE (VEX_W_5E_P_2) },
3663     { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3664   },
3665
3666   /* PREFIX_VEX_5F */
3667   {
3668     { VEX_W_TABLE (VEX_W_5F_P_0) },
3669     { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3670     { VEX_W_TABLE (VEX_W_5F_P_2) },
3671     { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3672   },
3673
3674   /* PREFIX_VEX_60 */
3675   {
3676     { Bad_Opcode },
3677     { Bad_Opcode },
3678     { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3679   },
3680
3681   /* PREFIX_VEX_61 */
3682   {
3683     { Bad_Opcode },
3684     { Bad_Opcode },
3685     { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3686   },
3687
3688   /* PREFIX_VEX_62 */
3689   {
3690     { Bad_Opcode },
3691     { Bad_Opcode },
3692     { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3693   },
3694
3695   /* PREFIX_VEX_63 */
3696   {
3697     { Bad_Opcode },
3698     { Bad_Opcode },
3699     { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3700   },
3701
3702   /* PREFIX_VEX_64 */
3703   {
3704     { Bad_Opcode },
3705     { Bad_Opcode },
3706     { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3707   },
3708
3709   /* PREFIX_VEX_65 */
3710   {
3711     { Bad_Opcode },
3712     { Bad_Opcode },
3713     { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3714   },
3715
3716   /* PREFIX_VEX_66 */
3717   {
3718     { Bad_Opcode },
3719     { Bad_Opcode },
3720     { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3721   },
3722
3723   /* PREFIX_VEX_67 */
3724   {
3725     { Bad_Opcode },
3726     { Bad_Opcode },
3727     { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3728   },
3729
3730   /* PREFIX_VEX_68 */
3731   {
3732     { Bad_Opcode },
3733     { Bad_Opcode },
3734     { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3735   },
3736
3737   /* PREFIX_VEX_69 */
3738   {
3739     { Bad_Opcode },
3740     { Bad_Opcode },
3741     { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3742   },
3743
3744   /* PREFIX_VEX_6A */
3745   {
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3749   },
3750
3751   /* PREFIX_VEX_6B */
3752   {
3753     { Bad_Opcode },
3754     { Bad_Opcode },
3755     { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3756   },
3757
3758   /* PREFIX_VEX_6C */
3759   {
3760     { Bad_Opcode },
3761     { Bad_Opcode },
3762     { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3763   },
3764
3765   /* PREFIX_VEX_6D */
3766   {
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3770   },
3771
3772   /* PREFIX_VEX_6E */
3773   {
3774     { Bad_Opcode },
3775     { Bad_Opcode },
3776     { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3777   },
3778
3779   /* PREFIX_VEX_6F */
3780   {
3781     { Bad_Opcode },
3782     { VEX_W_TABLE (VEX_W_6F_P_1) },
3783     { VEX_W_TABLE (VEX_W_6F_P_2) },
3784   },
3785
3786   /* PREFIX_VEX_70 */
3787   {
3788     { Bad_Opcode },
3789     { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3790     { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3791     { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3792   },
3793
3794   /* PREFIX_VEX_71_REG_2 */
3795   {
3796     { Bad_Opcode },
3797     { Bad_Opcode },
3798     { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3799   },
3800
3801   /* PREFIX_VEX_71_REG_4 */
3802   {
3803     { Bad_Opcode },
3804     { Bad_Opcode },
3805     { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3806   },
3807
3808   /* PREFIX_VEX_71_REG_6 */
3809   {
3810     { Bad_Opcode },
3811     { Bad_Opcode },
3812     { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3813   },
3814
3815   /* PREFIX_VEX_72_REG_2 */
3816   {
3817     { Bad_Opcode },
3818     { Bad_Opcode },
3819     { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3820   },
3821
3822   /* PREFIX_VEX_72_REG_4 */
3823   {
3824     { Bad_Opcode },
3825     { Bad_Opcode },
3826     { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3827   },
3828
3829   /* PREFIX_VEX_72_REG_6 */
3830   {
3831     { Bad_Opcode },
3832     { Bad_Opcode },
3833     { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3834   },
3835
3836   /* PREFIX_VEX_73_REG_2 */
3837   {
3838     { Bad_Opcode },
3839     { Bad_Opcode },
3840     { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3841   },
3842
3843   /* PREFIX_VEX_73_REG_3 */
3844   {
3845     { Bad_Opcode },
3846     { Bad_Opcode },
3847     { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3848   },
3849
3850   /* PREFIX_VEX_73_REG_6 */
3851   {
3852     { Bad_Opcode },
3853     { Bad_Opcode },
3854     { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3855   },
3856
3857   /* PREFIX_VEX_73_REG_7 */
3858   {
3859     { Bad_Opcode },
3860     { Bad_Opcode },
3861     { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3862   },
3863
3864   /* PREFIX_VEX_74 */
3865   {
3866     { Bad_Opcode },
3867     { Bad_Opcode },
3868     { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3869   },
3870
3871   /* PREFIX_VEX_75 */
3872   {
3873     { Bad_Opcode },
3874     { Bad_Opcode },
3875     { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3876   },
3877
3878   /* PREFIX_VEX_76 */
3879   {
3880     { Bad_Opcode },
3881     { Bad_Opcode },
3882     { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3883   },
3884
3885   /* PREFIX_VEX_77 */
3886   {
3887     { VEX_W_TABLE (VEX_W_77_P_0) },
3888   },
3889
3890   /* PREFIX_VEX_7C */
3891   {
3892     { Bad_Opcode },
3893     { Bad_Opcode },
3894     { VEX_W_TABLE (VEX_W_7C_P_2) },
3895     { VEX_W_TABLE (VEX_W_7C_P_3) },
3896   },
3897
3898   /* PREFIX_VEX_7D */
3899   {
3900     { Bad_Opcode },
3901     { Bad_Opcode },
3902     { VEX_W_TABLE (VEX_W_7D_P_2) },
3903     { VEX_W_TABLE (VEX_W_7D_P_3) },
3904   },
3905
3906   /* PREFIX_VEX_7E */
3907   {
3908     { Bad_Opcode },
3909     { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3910     { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3911   },
3912
3913   /* PREFIX_VEX_7F */
3914   {
3915     { Bad_Opcode },
3916     { VEX_W_TABLE (VEX_W_7F_P_1) },
3917     { VEX_W_TABLE (VEX_W_7F_P_2) },
3918   },
3919
3920   /* PREFIX_VEX_C2 */
3921   {
3922     { VEX_W_TABLE (VEX_W_C2_P_0) },
3923     { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3924     { VEX_W_TABLE (VEX_W_C2_P_2) },
3925     { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3926   },
3927
3928   /* PREFIX_VEX_C4 */
3929   {
3930     { Bad_Opcode },
3931     { Bad_Opcode },
3932     { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3933   },
3934
3935   /* PREFIX_VEX_C5 */
3936   {
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3940   },
3941
3942   /* PREFIX_VEX_D0 */
3943   {
3944     { Bad_Opcode },
3945     { Bad_Opcode },
3946     { VEX_W_TABLE (VEX_W_D0_P_2) },
3947     { VEX_W_TABLE (VEX_W_D0_P_3) },
3948   },
3949
3950   /* PREFIX_VEX_D1 */
3951   {
3952     { Bad_Opcode },
3953     { Bad_Opcode },
3954     { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3955   },
3956
3957   /* PREFIX_VEX_D2 */
3958   {
3959     { Bad_Opcode },
3960     { Bad_Opcode },
3961     { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3962   },
3963
3964   /* PREFIX_VEX_D3 */
3965   {
3966     { Bad_Opcode },
3967     { Bad_Opcode },
3968     { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3969   },
3970
3971   /* PREFIX_VEX_D4 */
3972   {
3973     { Bad_Opcode },
3974     { Bad_Opcode },
3975     { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3976   },
3977
3978   /* PREFIX_VEX_D5 */
3979   {
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3983   },
3984
3985   /* PREFIX_VEX_D6 */
3986   {
3987     { Bad_Opcode },
3988     { Bad_Opcode },
3989     { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3990   },
3991
3992   /* PREFIX_VEX_D7 */
3993   {
3994     { Bad_Opcode },
3995     { Bad_Opcode },
3996     { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3997   },
3998
3999   /* PREFIX_VEX_D8 */
4000   {
4001     { Bad_Opcode },
4002     { Bad_Opcode },
4003     { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
4004   },
4005
4006   /* PREFIX_VEX_D9 */
4007   {
4008     { Bad_Opcode },
4009     { Bad_Opcode },
4010     { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
4011   },
4012
4013   /* PREFIX_VEX_DA */
4014   {
4015     { Bad_Opcode },
4016     { Bad_Opcode },
4017     { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
4018   },
4019
4020   /* PREFIX_VEX_DB */
4021   {
4022     { Bad_Opcode },
4023     { Bad_Opcode },
4024     { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
4025   },
4026
4027   /* PREFIX_VEX_DC */
4028   {
4029     { Bad_Opcode },
4030     { Bad_Opcode },
4031     { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
4032   },
4033
4034   /* PREFIX_VEX_DD */
4035   {
4036     { Bad_Opcode },
4037     { Bad_Opcode },
4038     { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
4039   },
4040
4041   /* PREFIX_VEX_DE */
4042   {
4043     { Bad_Opcode },
4044     { Bad_Opcode },
4045     { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
4046   },
4047
4048   /* PREFIX_VEX_DF */
4049   {
4050     { Bad_Opcode },
4051     { Bad_Opcode },
4052     { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
4053   },
4054
4055   /* PREFIX_VEX_E0 */
4056   {
4057     { Bad_Opcode },
4058     { Bad_Opcode },
4059     { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
4060   },
4061
4062   /* PREFIX_VEX_E1 */
4063   {
4064     { Bad_Opcode },
4065     { Bad_Opcode },
4066     { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
4067   },
4068
4069   /* PREFIX_VEX_E2 */
4070   {
4071     { Bad_Opcode },
4072     { Bad_Opcode },
4073     { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
4074   },
4075
4076   /* PREFIX_VEX_E3 */
4077   {
4078     { Bad_Opcode },
4079     { Bad_Opcode },
4080     { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
4081   },
4082
4083   /* PREFIX_VEX_E4 */
4084   {
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
4088   },
4089
4090   /* PREFIX_VEX_E5 */
4091   {
4092     { Bad_Opcode },
4093     { Bad_Opcode },
4094     { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
4095   },
4096
4097   /* PREFIX_VEX_E6 */
4098   {
4099     { Bad_Opcode },
4100     { VEX_W_TABLE (VEX_W_E6_P_1) },
4101     { VEX_W_TABLE (VEX_W_E6_P_2) },
4102     { VEX_W_TABLE (VEX_W_E6_P_3) },
4103   },
4104
4105   /* PREFIX_VEX_E7 */
4106   {
4107     { Bad_Opcode },
4108     { Bad_Opcode },
4109     { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
4110   },
4111
4112   /* PREFIX_VEX_E8 */
4113   {
4114     { Bad_Opcode },
4115     { Bad_Opcode },
4116     { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
4117   },
4118
4119   /* PREFIX_VEX_E9 */
4120   {
4121     { Bad_Opcode },
4122     { Bad_Opcode },
4123     { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
4124   },
4125
4126   /* PREFIX_VEX_EA */
4127   {
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
4131   },
4132
4133   /* PREFIX_VEX_EB */
4134   {
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
4138   },
4139
4140   /* PREFIX_VEX_EC */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
4145   },
4146
4147   /* PREFIX_VEX_ED */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4152   },
4153
4154   /* PREFIX_VEX_EE */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4159   },
4160
4161   /* PREFIX_VEX_EF */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4166   },
4167
4168   /* PREFIX_VEX_F0 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { Bad_Opcode },
4173     { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4174   },
4175
4176   /* PREFIX_VEX_F1 */
4177   {
4178     { Bad_Opcode },
4179     { Bad_Opcode },
4180     { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4181   },
4182
4183   /* PREFIX_VEX_F2 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4188   },
4189
4190   /* PREFIX_VEX_F3 */
4191   {
4192     { Bad_Opcode },
4193     { Bad_Opcode },
4194     { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4195   },
4196
4197   /* PREFIX_VEX_F4 */
4198   {
4199     { Bad_Opcode },
4200     { Bad_Opcode },
4201     { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4202   },
4203
4204   /* PREFIX_VEX_F5 */
4205   {
4206     { Bad_Opcode },
4207     { Bad_Opcode },
4208     { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4209   },
4210
4211   /* PREFIX_VEX_F6 */
4212   {
4213     { Bad_Opcode },
4214     { Bad_Opcode },
4215     { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4216   },
4217
4218   /* PREFIX_VEX_F7 */
4219   {
4220     { Bad_Opcode },
4221     { Bad_Opcode },
4222     { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4223   },
4224
4225   /* PREFIX_VEX_F8 */
4226   {
4227     { Bad_Opcode },
4228     { Bad_Opcode },
4229     { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4230   },
4231
4232   /* PREFIX_VEX_F9 */
4233   {
4234     { Bad_Opcode },
4235     { Bad_Opcode },
4236     { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4237   },
4238
4239   /* PREFIX_VEX_FA */
4240   {
4241     { Bad_Opcode },
4242     { Bad_Opcode },
4243     { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4244   },
4245
4246   /* PREFIX_VEX_FB */
4247   {
4248     { Bad_Opcode },
4249     { Bad_Opcode },
4250     { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4251   },
4252
4253   /* PREFIX_VEX_FC */
4254   {
4255     { Bad_Opcode },
4256     { Bad_Opcode },
4257     { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4258   },
4259
4260   /* PREFIX_VEX_FD */
4261   {
4262     { Bad_Opcode },
4263     { Bad_Opcode },
4264     { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4265   },
4266
4267   /* PREFIX_VEX_FE */
4268   {
4269     { Bad_Opcode },
4270     { Bad_Opcode },
4271     { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4272   },
4273
4274   /* PREFIX_VEX_3800 */
4275   {
4276     { Bad_Opcode },
4277     { Bad_Opcode },
4278     { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4279   },
4280
4281   /* PREFIX_VEX_3801 */
4282   {
4283     { Bad_Opcode },
4284     { Bad_Opcode },
4285     { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4286   },
4287
4288   /* PREFIX_VEX_3802 */
4289   {
4290     { Bad_Opcode },
4291     { Bad_Opcode },
4292     { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4293   },
4294
4295   /* PREFIX_VEX_3803 */
4296   {
4297     { Bad_Opcode },
4298     { Bad_Opcode },
4299     { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4300   },
4301
4302   /* PREFIX_VEX_3804 */
4303   {
4304     { Bad_Opcode },
4305     { Bad_Opcode },
4306     { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4307   },
4308
4309   /* PREFIX_VEX_3805 */
4310   {
4311     { Bad_Opcode },
4312     { Bad_Opcode },
4313     { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4314   },
4315
4316   /* PREFIX_VEX_3806 */
4317   {
4318     { Bad_Opcode },
4319     { Bad_Opcode },
4320     { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4321   },
4322
4323   /* PREFIX_VEX_3807 */
4324   {
4325     { Bad_Opcode },
4326     { Bad_Opcode },
4327     { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4328   },
4329
4330   /* PREFIX_VEX_3808 */
4331   {
4332     { Bad_Opcode },
4333     { Bad_Opcode },
4334     { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4335   },
4336
4337   /* PREFIX_VEX_3809 */
4338   {
4339     { Bad_Opcode },
4340     { Bad_Opcode },
4341     { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4342   },
4343
4344   /* PREFIX_VEX_380A */
4345   {
4346     { Bad_Opcode },
4347     { Bad_Opcode },
4348     { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4349   },
4350
4351   /* PREFIX_VEX_380B */
4352   {
4353     { Bad_Opcode },
4354     { Bad_Opcode },
4355     { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4356   },
4357
4358   /* PREFIX_VEX_380C */
4359   {
4360     { Bad_Opcode },
4361     { Bad_Opcode },
4362     { VEX_W_TABLE (VEX_W_380C_P_2) },
4363   },
4364
4365   /* PREFIX_VEX_380D */
4366   {
4367     { Bad_Opcode },
4368     { Bad_Opcode },
4369     { VEX_W_TABLE (VEX_W_380D_P_2) },
4370   },
4371
4372   /* PREFIX_VEX_380E */
4373   {
4374     { Bad_Opcode },
4375     { Bad_Opcode },
4376     { VEX_W_TABLE (VEX_W_380E_P_2) },
4377   },
4378
4379   /* PREFIX_VEX_380F */
4380   {
4381     { Bad_Opcode },
4382     { Bad_Opcode },
4383     { VEX_W_TABLE (VEX_W_380F_P_2) },
4384   },
4385
4386   /* PREFIX_VEX_3817 */
4387   {
4388     { Bad_Opcode },
4389     { Bad_Opcode },
4390     { VEX_W_TABLE (VEX_W_3817_P_2) },
4391   },
4392
4393   /* PREFIX_VEX_3818 */
4394   {
4395     { Bad_Opcode },
4396     { Bad_Opcode },
4397     { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4398   },
4399
4400   /* PREFIX_VEX_3819 */
4401   {
4402     { Bad_Opcode },
4403     { Bad_Opcode },
4404     { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4405   },
4406
4407   /* PREFIX_VEX_381A */
4408   {
4409     { Bad_Opcode },
4410     { Bad_Opcode },
4411     { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4412   },
4413
4414   /* PREFIX_VEX_381C */
4415   {
4416     { Bad_Opcode },
4417     { Bad_Opcode },
4418     { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4419   },
4420
4421   /* PREFIX_VEX_381D */
4422   {
4423     { Bad_Opcode },
4424     { Bad_Opcode },
4425     { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4426   },
4427
4428   /* PREFIX_VEX_381E */
4429   {
4430     { Bad_Opcode },
4431     { Bad_Opcode },
4432     { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4433   },
4434
4435   /* PREFIX_VEX_3820 */
4436   {
4437     { Bad_Opcode },
4438     { Bad_Opcode },
4439     { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4440     { Bad_Opcode },
4441   },
4442
4443   /* PREFIX_VEX_3821 */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4448   },
4449
4450   /* PREFIX_VEX_3822 */
4451   {
4452     { Bad_Opcode },
4453     { Bad_Opcode },
4454     { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4455   },
4456
4457   /* PREFIX_VEX_3823 */
4458   {
4459     { Bad_Opcode },
4460     { Bad_Opcode },
4461     { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4462   },
4463
4464   /* PREFIX_VEX_3824 */
4465   {
4466     { Bad_Opcode },
4467     { Bad_Opcode },
4468     { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4469   },
4470
4471   /* PREFIX_VEX_3825 */
4472   {
4473     { Bad_Opcode },
4474     { Bad_Opcode },
4475     { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4476   },
4477
4478   /* PREFIX_VEX_3828 */
4479   {
4480     { Bad_Opcode },
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4483   },
4484
4485   /* PREFIX_VEX_3829 */
4486   {
4487     { Bad_Opcode },
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4490   },
4491
4492   /* PREFIX_VEX_382A */
4493   {
4494     { Bad_Opcode },
4495     { Bad_Opcode },
4496     { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4497   },
4498
4499   /* PREFIX_VEX_382B */
4500   {
4501     { Bad_Opcode },
4502     { Bad_Opcode },
4503     { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4504   },
4505
4506   /* PREFIX_VEX_382C */
4507   {
4508     { Bad_Opcode },
4509     { Bad_Opcode },
4510      { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4511   },
4512
4513   /* PREFIX_VEX_382D */
4514   {
4515     { Bad_Opcode },
4516     { Bad_Opcode },
4517      { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4518   },
4519
4520   /* PREFIX_VEX_382E */
4521   {
4522     { Bad_Opcode },
4523     { Bad_Opcode },
4524      { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4525   },
4526
4527   /* PREFIX_VEX_382F */
4528   {
4529     { Bad_Opcode },
4530     { Bad_Opcode },
4531      { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4532   },
4533
4534   /* PREFIX_VEX_3830 */
4535   {
4536     { Bad_Opcode },
4537     { Bad_Opcode },
4538     { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4539   },
4540
4541   /* PREFIX_VEX_3831 */
4542   {
4543     { Bad_Opcode },
4544     { Bad_Opcode },
4545     { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4546   },
4547
4548   /* PREFIX_VEX_3832 */
4549   {
4550     { Bad_Opcode },
4551     { Bad_Opcode },
4552     { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4553   },
4554
4555   /* PREFIX_VEX_3833 */
4556   {
4557     { Bad_Opcode },
4558     { Bad_Opcode },
4559     { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4560   },
4561
4562   /* PREFIX_VEX_3834 */
4563   {
4564     { Bad_Opcode },
4565     { Bad_Opcode },
4566     { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4567   },
4568
4569   /* PREFIX_VEX_3835 */
4570   {
4571     { Bad_Opcode },
4572     { Bad_Opcode },
4573     { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4574   },
4575
4576   /* PREFIX_VEX_3837 */
4577   {
4578     { Bad_Opcode },
4579     { Bad_Opcode },
4580     { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4581   },
4582
4583   /* PREFIX_VEX_3838 */
4584   {
4585     { Bad_Opcode },
4586     { Bad_Opcode },
4587     { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4588   },
4589
4590   /* PREFIX_VEX_3839 */
4591   {
4592     { Bad_Opcode },
4593     { Bad_Opcode },
4594     { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4595   },
4596
4597   /* PREFIX_VEX_383A */
4598   {
4599     { Bad_Opcode },
4600     { Bad_Opcode },
4601     { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4602   },
4603
4604   /* PREFIX_VEX_383B */
4605   {
4606     { Bad_Opcode },
4607     { Bad_Opcode },
4608     { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4609   },
4610
4611   /* PREFIX_VEX_383C */
4612   {
4613     { Bad_Opcode },
4614     { Bad_Opcode },
4615     { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4616   },
4617
4618   /* PREFIX_VEX_383D */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4623   },
4624
4625   /* PREFIX_VEX_383E */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4630   },
4631
4632   /* PREFIX_VEX_383F */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4637   },
4638
4639   /* PREFIX_VEX_3840 */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4644   },
4645
4646   /* PREFIX_VEX_3841 */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4651   },
4652
4653   /* PREFIX_VEX_3896 */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4658   },
4659
4660   /* PREFIX_VEX_3897 */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4665   },
4666
4667   /* PREFIX_VEX_3898 */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "vfmadd132p%XW", { XM, Vex, EXx } },
4672   },
4673
4674   /* PREFIX_VEX_3899 */
4675   {
4676     { Bad_Opcode },
4677     { Bad_Opcode },
4678     { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },
4679   },
4680
4681   /* PREFIX_VEX_389A */
4682   {
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { "vfmsub132p%XW", { XM, Vex, EXx } },
4686   },
4687
4688   /* PREFIX_VEX_389B */
4689   {
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },
4693   },
4694
4695   /* PREFIX_VEX_389C */
4696   {
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { "vfnmadd132p%XW", { XM, Vex, EXx } },
4700   },
4701
4702   /* PREFIX_VEX_389D */
4703   {
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },
4707   },
4708
4709   /* PREFIX_VEX_389E */
4710   {
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { "vfnmsub132p%XW", { XM, Vex, EXx } },
4714   },
4715
4716   /* PREFIX_VEX_389F */
4717   {
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },
4721   },
4722
4723   /* PREFIX_VEX_38A6 */
4724   {
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4728     { Bad_Opcode },
4729   },
4730
4731   /* PREFIX_VEX_38A7 */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4736   },
4737
4738   /* PREFIX_VEX_38A8 */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "vfmadd213p%XW", { XM, Vex, EXx } },
4743   },
4744
4745   /* PREFIX_VEX_38A9 */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },
4750   },
4751
4752   /* PREFIX_VEX_38AA */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "vfmsub213p%XW", { XM, Vex, EXx } },
4757   },
4758
4759   /* PREFIX_VEX_38AB */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },
4764   },
4765
4766   /* PREFIX_VEX_38AC */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "vfnmadd213p%XW", { XM, Vex, EXx } },
4771   },
4772
4773   /* PREFIX_VEX_38AD */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },
4778   },
4779
4780   /* PREFIX_VEX_38AE */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "vfnmsub213p%XW", { XM, Vex, EXx } },
4785   },
4786
4787   /* PREFIX_VEX_38AF */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },
4792   },
4793
4794   /* PREFIX_VEX_38B6 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "vfmaddsub231p%XW", { XM, Vex, EXx } },
4799   },
4800
4801   /* PREFIX_VEX_38B7 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "vfmsubadd231p%XW", { XM, Vex, EXx } },
4806   },
4807
4808   /* PREFIX_VEX_38B8 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "vfmadd231p%XW", { XM, Vex, EXx } },
4813   },
4814
4815   /* PREFIX_VEX_38B9 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },
4820   },
4821
4822   /* PREFIX_VEX_38BA */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "vfmsub231p%XW", { XM, Vex, EXx } },
4827   },
4828
4829   /* PREFIX_VEX_38BB */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },
4834   },
4835
4836   /* PREFIX_VEX_38BC */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "vfnmadd231p%XW", { XM, Vex, EXx } },
4841   },
4842
4843   /* PREFIX_VEX_38BD */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },
4848   },
4849
4850   /* PREFIX_VEX_38BE */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "vfnmsub231p%XW", { XM, Vex, EXx } },
4855   },
4856
4857   /* PREFIX_VEX_38BF */
4858   {
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },
4862   },
4863
4864   /* PREFIX_VEX_38DB */
4865   {
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4869   },
4870
4871   /* PREFIX_VEX_38DC */
4872   {
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4876   },
4877
4878   /* PREFIX_VEX_38DD */
4879   {
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4883   },
4884
4885   /* PREFIX_VEX_38DE */
4886   {
4887     { Bad_Opcode },
4888     { Bad_Opcode },
4889     { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4890   },
4891
4892   /* PREFIX_VEX_38DF */
4893   {
4894     { Bad_Opcode },
4895     { Bad_Opcode },
4896     { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4897   },
4898
4899   /* PREFIX_VEX_3A04 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_3A04_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_3A05 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_3A05_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_3A06 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_3A08 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_3A08_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_3A09 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_3A09_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_3A0A */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_3A0B */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_3A0C */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_3A0C_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_3A0D */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_3A0D_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_3A0E */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_3A0F */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_3A14 */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_3A15 */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_3A16 */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_3A17 */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_3A18 */
5005   {
5006     { Bad_Opcode },
5007     { Bad_Opcode },
5008     { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_3A19 */
5012   {
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
5016   },
5017
5018   /* PREFIX_VEX_3A20 */
5019   {
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
5023   },
5024
5025   /* PREFIX_VEX_3A21 */
5026   {
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
5030   },
5031
5032   /* PREFIX_VEX_3A22 */
5033   {
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
5037   },
5038
5039   /* PREFIX_VEX_3A40 */
5040   {
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { VEX_W_TABLE (VEX_W_3A40_P_2) },
5044   },
5045
5046   /* PREFIX_VEX_3A41 */
5047   {
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
5051   },
5052
5053   /* PREFIX_VEX_3A42 */
5054   {
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
5058   },
5059
5060   /* PREFIX_VEX_3A44 */
5061   {
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },
5065   },
5066
5067   /* PREFIX_VEX_3A4A */
5068   {
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { VEX_W_TABLE (VEX_W_3A4A_P_2) },
5072   },
5073
5074   /* PREFIX_VEX_3A4B */
5075   {
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { VEX_W_TABLE (VEX_W_3A4B_P_2) },
5079   },
5080
5081   /* PREFIX_VEX_3A4C */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
5086   },
5087
5088   /* PREFIX_VEX_3A5C */
5089   {
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5093   },
5094
5095   /* PREFIX_VEX_3A5D */
5096   {
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5100   },
5101
5102   /* PREFIX_VEX_3A5E */
5103   {
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5107   },
5108
5109   /* PREFIX_VEX_3A5F */
5110   {
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5114   },
5115
5116   /* PREFIX_VEX_3A60 */
5117   {
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
5121     { Bad_Opcode },
5122   },
5123
5124   /* PREFIX_VEX_3A61 */
5125   {
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
5129   },
5130
5131   /* PREFIX_VEX_3A62 */
5132   {
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_3A63 */
5139   {
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_3A68 */
5146   {
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5150   },
5151
5152   /* PREFIX_VEX_3A69 */
5153   {
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5157   },
5158
5159   /* PREFIX_VEX_3A6A */
5160   {
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
5164   },
5165
5166   /* PREFIX_VEX_3A6B */
5167   {
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
5171   },
5172
5173   /* PREFIX_VEX_3A6C */
5174   {
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5178   },
5179
5180   /* PREFIX_VEX_3A6D */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5185   },
5186
5187   /* PREFIX_VEX_3A6E */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_3A6F */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
5199   },
5200
5201   /* PREFIX_VEX_3A78 */
5202   {
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5206   },
5207
5208   /* PREFIX_VEX_3A79 */
5209   {
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5213   },
5214
5215   /* PREFIX_VEX_3A7A */
5216   {
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
5220   },
5221
5222   /* PREFIX_VEX_3A7B */
5223   {
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
5227   },
5228
5229   /* PREFIX_VEX_3A7C */
5230   {
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5234     { Bad_Opcode },
5235   },
5236
5237   /* PREFIX_VEX_3A7D */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5242   },
5243
5244   /* PREFIX_VEX_3A7E */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5249   },
5250
5251   /* PREFIX_VEX_3A7F */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5256   },
5257
5258   /* PREFIX_VEX_3ADF */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5263   },
5264 };
5265
5266 static const struct dis386 x86_64_table[][2] = {
5267   /* X86_64_06 */
5268   {
5269     { "push{T|}", { es } },
5270   },
5271
5272   /* X86_64_07 */
5273   {
5274     { "pop{T|}", { es } },
5275   },
5276
5277   /* X86_64_0D */
5278   {
5279     { "push{T|}", { cs } },
5280   },
5281
5282   /* X86_64_16 */
5283   {
5284     { "push{T|}", { ss } },
5285   },
5286
5287   /* X86_64_17 */
5288   {
5289     { "pop{T|}", { ss } },
5290   },
5291
5292   /* X86_64_1E */
5293   {
5294     { "push{T|}", { ds } },
5295   },
5296
5297   /* X86_64_1F */
5298   {
5299     { "pop{T|}", { ds } },
5300   },
5301
5302   /* X86_64_27 */
5303   {
5304     { "daa", { XX } },
5305   },
5306
5307   /* X86_64_2F */
5308   {
5309     { "das", { XX } },
5310   },
5311
5312   /* X86_64_37 */
5313   {
5314     { "aaa", { XX } },
5315   },
5316
5317   /* X86_64_3F */
5318   {
5319     { "aas", { XX } },
5320   },
5321
5322   /* X86_64_60 */
5323   {
5324     { "pusha{P|}", { XX } },
5325   },
5326
5327   /* X86_64_61 */
5328   {
5329     { "popa{P|}", { XX } },
5330   },
5331
5332   /* X86_64_62 */
5333   {
5334     { MOD_TABLE (MOD_62_32BIT) },
5335   },
5336
5337   /* X86_64_63 */
5338   {
5339     { "arpl", { Ew, Gw } },
5340     { "movs{lq|xd}", { Gv, Ed } },
5341   },
5342
5343   /* X86_64_6D */
5344   {
5345     { "ins{R|}", { Yzr, indirDX } },
5346     { "ins{G|}", { Yzr, indirDX } },
5347   },
5348
5349   /* X86_64_6F */
5350   {
5351     { "outs{R|}", { indirDXr, Xz } },
5352     { "outs{G|}", { indirDXr, Xz } },
5353   },
5354
5355   /* X86_64_9A */
5356   {
5357     { "Jcall{T|}", { Ap } },
5358   },
5359
5360   /* X86_64_C4 */
5361   {
5362     { MOD_TABLE (MOD_C4_32BIT) },
5363     { VEX_C4_TABLE (VEX_0F) },
5364   },
5365
5366   /* X86_64_C5 */
5367   {
5368     { MOD_TABLE (MOD_C5_32BIT) },
5369     { VEX_C5_TABLE (VEX_0F) },
5370   },
5371
5372   /* X86_64_CE */
5373   {
5374     { "into", { XX } },
5375   },
5376
5377   /* X86_64_D4 */
5378   {
5379     { "aam", { sIb } },
5380   },
5381
5382   /* X86_64_D5 */
5383   {
5384     { "aad", { sIb } },
5385   },
5386
5387   /* X86_64_EA */
5388   {
5389     { "Jjmp{T|}", { Ap } },
5390   },
5391
5392   /* X86_64_0F01_REG_0 */
5393   {
5394     { "sgdt{Q|IQ}", { M } },
5395     { "sgdt", { M } },
5396   },
5397
5398   /* X86_64_0F01_REG_1 */
5399   {
5400     { "sidt{Q|IQ}", { M } },
5401     { "sidt", { M } },
5402   },
5403
5404   /* X86_64_0F01_REG_2 */
5405   {
5406     { "lgdt{Q|Q}", { M } },
5407     { "lgdt", { M } },
5408   },
5409
5410   /* X86_64_0F01_REG_3 */
5411   {
5412     { "lidt{Q|Q}", { M } },
5413     { "lidt", { M } },
5414   },
5415 };
5416
5417 static const struct dis386 three_byte_table[][256] = {
5418
5419   /* THREE_BYTE_0F38 */
5420   {
5421     /* 00 */
5422     { "pshufb",         { MX, EM } },
5423     { "phaddw",         { MX, EM } },
5424     { "phaddd",         { MX, EM } },
5425     { "phaddsw",        { MX, EM } },
5426     { "pmaddubsw",      { MX, EM } },
5427     { "phsubw",         { MX, EM } },
5428     { "phsubd",         { MX, EM } },
5429     { "phsubsw",        { MX, EM } },
5430     /* 08 */
5431     { "psignb",         { MX, EM } },
5432     { "psignw",         { MX, EM } },
5433     { "psignd",         { MX, EM } },
5434     { "pmulhrsw",       { MX, EM } },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     /* 10 */
5440     { PREFIX_TABLE (PREFIX_0F3810) },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { PREFIX_TABLE (PREFIX_0F3814) },
5445     { PREFIX_TABLE (PREFIX_0F3815) },
5446     { Bad_Opcode },
5447     { PREFIX_TABLE (PREFIX_0F3817) },
5448     /* 18 */
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "pabsb",          { MX, EM } },
5454     { "pabsw",          { MX, EM } },
5455     { "pabsd",          { MX, EM } },
5456     { Bad_Opcode },
5457     /* 20 */
5458     { PREFIX_TABLE (PREFIX_0F3820) },
5459     { PREFIX_TABLE (PREFIX_0F3821) },
5460     { PREFIX_TABLE (PREFIX_0F3822) },
5461     { PREFIX_TABLE (PREFIX_0F3823) },
5462     { PREFIX_TABLE (PREFIX_0F3824) },
5463     { PREFIX_TABLE (PREFIX_0F3825) },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     /* 28 */
5467     { PREFIX_TABLE (PREFIX_0F3828) },
5468     { PREFIX_TABLE (PREFIX_0F3829) },
5469     { PREFIX_TABLE (PREFIX_0F382A) },
5470     { PREFIX_TABLE (PREFIX_0F382B) },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     /* 30 */
5476     { PREFIX_TABLE (PREFIX_0F3830) },
5477     { PREFIX_TABLE (PREFIX_0F3831) },
5478     { PREFIX_TABLE (PREFIX_0F3832) },
5479     { PREFIX_TABLE (PREFIX_0F3833) },
5480     { PREFIX_TABLE (PREFIX_0F3834) },
5481     { PREFIX_TABLE (PREFIX_0F3835) },
5482     { Bad_Opcode },
5483     { PREFIX_TABLE (PREFIX_0F3837) },
5484     /* 38 */
5485     { PREFIX_TABLE (PREFIX_0F3838) },
5486     { PREFIX_TABLE (PREFIX_0F3839) },
5487     { PREFIX_TABLE (PREFIX_0F383A) },
5488     { PREFIX_TABLE (PREFIX_0F383B) },
5489     { PREFIX_TABLE (PREFIX_0F383C) },
5490     { PREFIX_TABLE (PREFIX_0F383D) },
5491     { PREFIX_TABLE (PREFIX_0F383E) },
5492     { PREFIX_TABLE (PREFIX_0F383F) },
5493     /* 40 */
5494     { PREFIX_TABLE (PREFIX_0F3840) },
5495     { PREFIX_TABLE (PREFIX_0F3841) },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     /* 48 */
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     /* 50 */
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     /* 58 */
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     /* 60 */
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     /* 68 */
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     /* 70 */
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     /* 78 */
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     /* 80 */
5566     { PREFIX_TABLE (PREFIX_0F3880) },
5567     { PREFIX_TABLE (PREFIX_0F3881) },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     /* 88 */
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     /* 90 */
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     /* 98 */
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     /* a0 */
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     /* a8 */
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     /* b0 */
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     /* b8 */
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     /* c0 */
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     /* c8 */
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { Bad_Opcode },
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     /* d0 */
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     /* d8 */
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { PREFIX_TABLE (PREFIX_0F38DB) },
5669     { PREFIX_TABLE (PREFIX_0F38DC) },
5670     { PREFIX_TABLE (PREFIX_0F38DD) },
5671     { PREFIX_TABLE (PREFIX_0F38DE) },
5672     { PREFIX_TABLE (PREFIX_0F38DF) },
5673     /* e0 */
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     /* e8 */
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     /* f0 */
5692     { PREFIX_TABLE (PREFIX_0F38F0) },
5693     { PREFIX_TABLE (PREFIX_0F38F1) },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     { Bad_Opcode },
5700     /* f8 */
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709   },
5710   /* THREE_BYTE_0F3A */
5711   {
5712     /* 00 */
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     /* 08 */
5722     { PREFIX_TABLE (PREFIX_0F3A08) },
5723     { PREFIX_TABLE (PREFIX_0F3A09) },
5724     { PREFIX_TABLE (PREFIX_0F3A0A) },
5725     { PREFIX_TABLE (PREFIX_0F3A0B) },
5726     { PREFIX_TABLE (PREFIX_0F3A0C) },
5727     { PREFIX_TABLE (PREFIX_0F3A0D) },
5728     { PREFIX_TABLE (PREFIX_0F3A0E) },
5729     { "palignr",        { MX, EM, Ib } },
5730     /* 10 */
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     { PREFIX_TABLE (PREFIX_0F3A14) },
5736     { PREFIX_TABLE (PREFIX_0F3A15) },
5737     { PREFIX_TABLE (PREFIX_0F3A16) },
5738     { PREFIX_TABLE (PREFIX_0F3A17) },
5739     /* 18 */
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     /* 20 */
5749     { PREFIX_TABLE (PREFIX_0F3A20) },
5750     { PREFIX_TABLE (PREFIX_0F3A21) },
5751     { PREFIX_TABLE (PREFIX_0F3A22) },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     /* 28 */
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     /* 30 */
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     /* 38 */
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     /* 40 */
5785     { PREFIX_TABLE (PREFIX_0F3A40) },
5786     { PREFIX_TABLE (PREFIX_0F3A41) },
5787     { PREFIX_TABLE (PREFIX_0F3A42) },
5788     { Bad_Opcode },
5789     { PREFIX_TABLE (PREFIX_0F3A44) },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     /* 48 */
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     /* 50 */
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     /* 58 */
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     /* 60 */
5821     { PREFIX_TABLE (PREFIX_0F3A60) },
5822     { PREFIX_TABLE (PREFIX_0F3A61) },
5823     { PREFIX_TABLE (PREFIX_0F3A62) },
5824     { PREFIX_TABLE (PREFIX_0F3A63) },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     /* 68 */
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     /* 70 */
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     /* 78 */
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     /* 80 */
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     /* 88 */
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     /* 90 */
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     /* 98 */
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     /* a0 */
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     /* a8 */
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     /* b0 */
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     /* b8 */
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     /* c0 */
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     /* c8 */
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     /* d0 */
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     /* d8 */
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { PREFIX_TABLE (PREFIX_0F3ADF) },
5964     /* e0 */
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     /* e8 */
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     /* f0 */
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     /* f8 */
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000   },
6001
6002   /* THREE_BYTE_0F7A */
6003   {
6004     /* 00 */
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     /* 08 */
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     /* 10 */
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     /* 18 */
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     /* 20 */
6041     { "ptest",          { XX } },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     /* 28 */
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     /* 30 */
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { Bad_Opcode },
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { Bad_Opcode },
6067     /* 38 */
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     /* 40 */
6077     { Bad_Opcode },
6078     { "phaddbw",        { XM, EXq } },
6079     { "phaddbd",        { XM, EXq } },
6080     { "phaddbq",        { XM, EXq } },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "phaddwd",        { XM, EXq } },
6084     { "phaddwq",        { XM, EXq } },
6085     /* 48 */
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { "phadddq",        { XM, EXq } },
6090     { Bad_Opcode },
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { Bad_Opcode },
6094     /* 50 */
6095     { Bad_Opcode },
6096     { "phaddubw",       { XM, EXq } },
6097     { "phaddubd",       { XM, EXq } },
6098     { "phaddubq",       { XM, EXq } },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { "phadduwd",       { XM, EXq } },
6102     { "phadduwq",       { XM, EXq } },
6103     /* 58 */
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "phaddudq",       { XM, EXq } },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     /* 60 */
6113     { Bad_Opcode },
6114     { "phsubbw",        { XM, EXq } },
6115     { "phsubbd",        { XM, EXq } },
6116     { "phsubbq",        { XM, EXq } },
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { Bad_Opcode },
6120     { Bad_Opcode },
6121     /* 68 */
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     /* 70 */
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     /* 78 */
6140     { Bad_Opcode },
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { Bad_Opcode },
6148     /* 80 */
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     /* 88 */
6158     { Bad_Opcode },
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { Bad_Opcode },
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     /* 90 */
6167     { Bad_Opcode },
6168     { Bad_Opcode },
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     /* 98 */
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { Bad_Opcode },
6183     { Bad_Opcode },
6184     /* a0 */
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { Bad_Opcode },
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     /* a8 */
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { Bad_Opcode },
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { Bad_Opcode },
6202     /* b0 */
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { Bad_Opcode },
6211     /* b8 */
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     /* c0 */
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     /* c8 */
6230     { Bad_Opcode },
6231     { Bad_Opcode },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     /* d0 */
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     /* d8 */
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     /* e0 */
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { Bad_Opcode },
6265     /* e8 */
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     /* f0 */
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     /* f8 */
6284     { Bad_Opcode },
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { Bad_Opcode },
6288     { Bad_Opcode },
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292   },
6293 };
6294
6295 static const struct dis386 xop_table[][256] = {
6296   /* XOP_08 */
6297   {
6298     /* 00 */
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     { Bad_Opcode },
6303     { Bad_Opcode },
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     /* 08 */
6308     { Bad_Opcode },
6309     { Bad_Opcode },
6310     { Bad_Opcode },
6311     { Bad_Opcode },
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { Bad_Opcode },
6315     { Bad_Opcode },
6316     /* 10 */
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { Bad_Opcode },
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { Bad_Opcode },
6325     /* 18 */
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { Bad_Opcode },
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { Bad_Opcode },
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     /* 20 */
6335     { Bad_Opcode },
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { Bad_Opcode },
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { Bad_Opcode },
6343     /* 28 */
6344     { Bad_Opcode },
6345     { Bad_Opcode },
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { Bad_Opcode },
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     /* 30 */
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { Bad_Opcode },
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { Bad_Opcode },
6360     { Bad_Opcode },
6361     /* 38 */
6362     { Bad_Opcode },
6363     { Bad_Opcode },
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { Bad_Opcode },
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     /* 40 */
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { Bad_Opcode },
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { Bad_Opcode },
6379     /* 48 */
6380     { Bad_Opcode },
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { Bad_Opcode },
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { Bad_Opcode },
6388     /* 50 */
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { Bad_Opcode },
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { Bad_Opcode },
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     /* 58 */
6398     { Bad_Opcode },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { Bad_Opcode },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { Bad_Opcode },
6406     /* 60 */
6407     { Bad_Opcode },
6408     { Bad_Opcode },
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { Bad_Opcode },
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     /* 68 */
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { Bad_Opcode },
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { Bad_Opcode },
6423     { Bad_Opcode },
6424     /* 70 */
6425     { Bad_Opcode },
6426     { Bad_Opcode },
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { Bad_Opcode },
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     /* 78 */
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { Bad_Opcode },
6441     { Bad_Opcode },
6442     /* 80 */
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6449     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6450     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6451     /* 88 */
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6459     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6460     /* 90 */
6461     { Bad_Opcode },
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { Bad_Opcode },
6465     { Bad_Opcode },
6466     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6467     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6468     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6469     /* 98 */
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6477     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6478     /* a0 */
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6482     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6486     { Bad_Opcode },
6487     /* a8 */
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     /* b0 */
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6504     { Bad_Opcode },
6505     /* b8 */
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     /* c0 */
6515     { "vprotb",         { XM, Vex_2src_1, Ib } },
6516     { "vprotw",         { XM, Vex_2src_1, Ib } },
6517     { "vprotd",         { XM, Vex_2src_1, Ib } },
6518     { "vprotq",         { XM, Vex_2src_1, Ib } },
6519     { Bad_Opcode },
6520     { Bad_Opcode },
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     /* c8 */
6524     { Bad_Opcode },
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { "vpcomb",         { XM, Vex128, EXx, Ib } },
6529     { "vpcomw",         { XM, Vex128, EXx, Ib } },
6530     { "vpcomd",         { XM, Vex128, EXx, Ib } },
6531     { "vpcomq",         { XM, Vex128, EXx, Ib } },
6532     /* d0 */
6533     { Bad_Opcode },
6534     { Bad_Opcode },
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     /* d8 */
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { Bad_Opcode },
6549     { Bad_Opcode },
6550     /* e0 */
6551     { Bad_Opcode },
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { Bad_Opcode },
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     /* e8 */
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { Bad_Opcode },
6563     { Bad_Opcode },
6564     { "vpcomub",        { XM, Vex128, EXx, Ib } },
6565     { "vpcomuw",        { XM, Vex128, EXx, Ib } },
6566     { "vpcomud",        { XM, Vex128, EXx, Ib } },
6567     { "vpcomuq",        { XM, Vex128, EXx, Ib } },
6568     /* f0 */
6569     { Bad_Opcode },
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     /* f8 */
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586   },
6587   /* XOP_09 */
6588   {
6589     /* 00 */
6590     { Bad_Opcode },
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     /* 08 */
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     /* 10 */
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { REG_TABLE (REG_XOP_LWPCB) },
6611     { Bad_Opcode },
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { Bad_Opcode },
6616     /* 18 */
6617     { Bad_Opcode },
6618     { Bad_Opcode },
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     /* 20 */
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { Bad_Opcode },
6633     { Bad_Opcode },
6634     /* 28 */
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     /* 30 */
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { Bad_Opcode },
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     /* 38 */
6653     { Bad_Opcode },
6654     { Bad_Opcode },
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     /* 40 */
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     /* 48 */
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { Bad_Opcode },
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     /* 50 */
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { Bad_Opcode },
6688     /* 58 */
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     /* 60 */
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     /* 68 */
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     /* 70 */
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     /* 78 */
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { Bad_Opcode },
6732     { Bad_Opcode },
6733     /* 80 */
6734     { VEX_LEN_TABLE (VEX_LEN_XOP_09_80) },
6735     { VEX_LEN_TABLE (VEX_LEN_XOP_09_81) },
6736     { "vfrczss",        { XM, EXd } },
6737     { "vfrczsd",        { XM, EXq } },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     /* 88 */
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     /* 90 */
6752     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 } },
6753     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 } },
6754     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 } },
6755     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 } },
6756     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 } },
6757     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 } },
6758     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 } },
6759     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 } },
6760     /* 98 */
6761     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 } },
6762     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 } },
6763     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 } },
6764     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 } },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { Bad_Opcode },
6768     { Bad_Opcode },
6769     /* a0 */
6770     { Bad_Opcode },
6771     { Bad_Opcode },
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     /* a8 */
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { Bad_Opcode },
6786     { Bad_Opcode },
6787     /* b0 */
6788     { Bad_Opcode },
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     /* b8 */
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     /* c0 */
6806     { Bad_Opcode },
6807     { "vphaddbw",       { XM, EXxmm } },
6808     { "vphaddbd",       { XM, EXxmm } },
6809     { "vphaddbq",       { XM, EXxmm } },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { "vphaddwd",       { XM, EXxmm } },
6813     { "vphaddwq",       { XM, EXxmm } },
6814     /* c8 */
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { "vphadddq",       { XM, EXxmm } },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     /* d0 */
6824     { Bad_Opcode },
6825     { "vphaddubw",      { XM, EXxmm } },
6826     { "vphaddubd",      { XM, EXxmm } },
6827     { "vphaddubq",      { XM, EXxmm } },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { "vphadduwd",      { XM, EXxmm } },
6831     { "vphadduwq",      { XM, EXxmm } },
6832     /* d8 */
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { "vphaddudq",      { XM, EXxmm } },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     /* e0 */
6842     { Bad_Opcode },
6843     { "vphsubbw",       { XM, EXxmm } },
6844     { "vphsubwd",       { XM, EXxmm } },
6845     { "vphsubdq",       { XM, EXxmm } },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     /* e8 */
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     /* f0 */
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     /* f8 */
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877   },
6878   /* XOP_0A */
6879   {
6880     /* 00 */
6881     { Bad_Opcode },
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     /* 08 */
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     /* 10 */
6899     { Bad_Opcode },
6900     { Bad_Opcode },
6901     { REG_TABLE (REG_XOP_LWP) },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     /* 18 */
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     /* 20 */
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     /* 28 */
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     /* 30 */
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { Bad_Opcode },
6941     { Bad_Opcode },
6942     { Bad_Opcode },
6943     /* 38 */
6944     { Bad_Opcode },
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { Bad_Opcode },
6948     { Bad_Opcode },
6949     { Bad_Opcode },
6950     { Bad_Opcode },
6951     { Bad_Opcode },
6952     /* 40 */
6953     { Bad_Opcode },
6954     { Bad_Opcode },
6955     { Bad_Opcode },
6956     { Bad_Opcode },
6957     { Bad_Opcode },
6958     { Bad_Opcode },
6959     { Bad_Opcode },
6960     { Bad_Opcode },
6961     /* 48 */
6962     { Bad_Opcode },
6963     { Bad_Opcode },
6964     { Bad_Opcode },
6965     { Bad_Opcode },
6966     { Bad_Opcode },
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { Bad_Opcode },
6970     /* 50 */
6971     { Bad_Opcode },
6972     { Bad_Opcode },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     { Bad_Opcode },
6978     { Bad_Opcode },
6979     /* 58 */
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { Bad_Opcode },
6984     { Bad_Opcode },
6985     { Bad_Opcode },
6986     { Bad_Opcode },
6987     { Bad_Opcode },
6988     /* 60 */
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     { Bad_Opcode },
6993     { Bad_Opcode },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     /* 68 */
6998     { Bad_Opcode },
6999     { Bad_Opcode },
7000     { Bad_Opcode },
7001     { Bad_Opcode },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 70 */
7007     { Bad_Opcode },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     { Bad_Opcode },
7014     { Bad_Opcode },
7015     /* 78 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { Bad_Opcode },
7021     { Bad_Opcode },
7022     { Bad_Opcode },
7023     { Bad_Opcode },
7024     /* 80 */
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     { Bad_Opcode },
7029     { Bad_Opcode },
7030     { Bad_Opcode },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 88 */
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 90 */
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     /* 98 */
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     /* a0 */
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* a8 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* b0 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* b8 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* c0 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* c8 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* d0 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* d8 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* e0 */
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* e8 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* f0 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* f8 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168   },
7169 };
7170
7171 static const struct dis386 vex_table[][256] = {
7172   /* VEX_0F */
7173   {
7174     /* 00 */
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     /* 08 */
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     /* 10 */
7193     { PREFIX_TABLE (PREFIX_VEX_10) },
7194     { PREFIX_TABLE (PREFIX_VEX_11) },
7195     { PREFIX_TABLE (PREFIX_VEX_12) },
7196     { MOD_TABLE (MOD_VEX_13) },
7197     { VEX_W_TABLE (VEX_W_14) },
7198     { VEX_W_TABLE (VEX_W_15) },
7199     { PREFIX_TABLE (PREFIX_VEX_16) },
7200     { MOD_TABLE (MOD_VEX_17) },
7201     /* 18 */
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     /* 20 */
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     /* 28 */
7220     { VEX_W_TABLE (VEX_W_28) },
7221     { VEX_W_TABLE (VEX_W_29) },
7222     { PREFIX_TABLE (PREFIX_VEX_2A) },
7223     { MOD_TABLE (MOD_VEX_2B) },
7224     { PREFIX_TABLE (PREFIX_VEX_2C) },
7225     { PREFIX_TABLE (PREFIX_VEX_2D) },
7226     { PREFIX_TABLE (PREFIX_VEX_2E) },
7227     { PREFIX_TABLE (PREFIX_VEX_2F) },
7228     /* 30 */
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { Bad_Opcode },
7236     { Bad_Opcode },
7237     /* 38 */
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     /* 40 */
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     /* 48 */
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     /* 50 */
7265     { MOD_TABLE (MOD_VEX_50) },
7266     { PREFIX_TABLE (PREFIX_VEX_51) },
7267     { PREFIX_TABLE (PREFIX_VEX_52) },
7268     { PREFIX_TABLE (PREFIX_VEX_53) },
7269     { "vandpX",         { XM, Vex, EXx } },
7270     { "vandnpX",        { XM, Vex, EXx } },
7271     { "vorpX",          { XM, Vex, EXx } },
7272     { "vxorpX",         { XM, Vex, EXx } },
7273     /* 58 */
7274     { PREFIX_TABLE (PREFIX_VEX_58) },
7275     { PREFIX_TABLE (PREFIX_VEX_59) },
7276     { PREFIX_TABLE (PREFIX_VEX_5A) },
7277     { PREFIX_TABLE (PREFIX_VEX_5B) },
7278     { PREFIX_TABLE (PREFIX_VEX_5C) },
7279     { PREFIX_TABLE (PREFIX_VEX_5D) },
7280     { PREFIX_TABLE (PREFIX_VEX_5E) },
7281     { PREFIX_TABLE (PREFIX_VEX_5F) },
7282     /* 60 */
7283     { PREFIX_TABLE (PREFIX_VEX_60) },
7284     { PREFIX_TABLE (PREFIX_VEX_61) },
7285     { PREFIX_TABLE (PREFIX_VEX_62) },
7286     { PREFIX_TABLE (PREFIX_VEX_63) },
7287     { PREFIX_TABLE (PREFIX_VEX_64) },
7288     { PREFIX_TABLE (PREFIX_VEX_65) },
7289     { PREFIX_TABLE (PREFIX_VEX_66) },
7290     { PREFIX_TABLE (PREFIX_VEX_67) },
7291     /* 68 */
7292     { PREFIX_TABLE (PREFIX_VEX_68) },
7293     { PREFIX_TABLE (PREFIX_VEX_69) },
7294     { PREFIX_TABLE (PREFIX_VEX_6A) },
7295     { PREFIX_TABLE (PREFIX_VEX_6B) },
7296     { PREFIX_TABLE (PREFIX_VEX_6C) },
7297     { PREFIX_TABLE (PREFIX_VEX_6D) },
7298     { PREFIX_TABLE (PREFIX_VEX_6E) },
7299     { PREFIX_TABLE (PREFIX_VEX_6F) },
7300     /* 70 */
7301     { PREFIX_TABLE (PREFIX_VEX_70) },
7302     { REG_TABLE (REG_VEX_71) },
7303     { REG_TABLE (REG_VEX_72) },
7304     { REG_TABLE (REG_VEX_73) },
7305     { PREFIX_TABLE (PREFIX_VEX_74) },
7306     { PREFIX_TABLE (PREFIX_VEX_75) },
7307     { PREFIX_TABLE (PREFIX_VEX_76) },
7308     { PREFIX_TABLE (PREFIX_VEX_77) },
7309     /* 78 */
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { PREFIX_TABLE (PREFIX_VEX_7C) },
7315     { PREFIX_TABLE (PREFIX_VEX_7D) },
7316     { PREFIX_TABLE (PREFIX_VEX_7E) },
7317     { PREFIX_TABLE (PREFIX_VEX_7F) },
7318     /* 80 */
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     /* 88 */
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     /* 90 */
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     /* 98 */
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     /* a0 */
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     /* a8 */
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { REG_TABLE (REG_VEX_AE) },
7371     { Bad_Opcode },
7372     /* b0 */
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     /* b8 */
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     /* c0 */
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { PREFIX_TABLE (PREFIX_VEX_C2) },
7394     { Bad_Opcode },
7395     { PREFIX_TABLE (PREFIX_VEX_C4) },
7396     { PREFIX_TABLE (PREFIX_VEX_C5) },
7397     { "vshufpX",        { XM, Vex, EXx, Ib } },
7398     { Bad_Opcode },
7399     /* c8 */
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     /* d0 */
7409     { PREFIX_TABLE (PREFIX_VEX_D0) },
7410     { PREFIX_TABLE (PREFIX_VEX_D1) },
7411     { PREFIX_TABLE (PREFIX_VEX_D2) },
7412     { PREFIX_TABLE (PREFIX_VEX_D3) },
7413     { PREFIX_TABLE (PREFIX_VEX_D4) },
7414     { PREFIX_TABLE (PREFIX_VEX_D5) },
7415     { PREFIX_TABLE (PREFIX_VEX_D6) },
7416     { PREFIX_TABLE (PREFIX_VEX_D7) },
7417     /* d8 */
7418     { PREFIX_TABLE (PREFIX_VEX_D8) },
7419     { PREFIX_TABLE (PREFIX_VEX_D9) },
7420     { PREFIX_TABLE (PREFIX_VEX_DA) },
7421     { PREFIX_TABLE (PREFIX_VEX_DB) },
7422     { PREFIX_TABLE (PREFIX_VEX_DC) },
7423     { PREFIX_TABLE (PREFIX_VEX_DD) },
7424     { PREFIX_TABLE (PREFIX_VEX_DE) },
7425     { PREFIX_TABLE (PREFIX_VEX_DF) },
7426     /* e0 */
7427     { PREFIX_TABLE (PREFIX_VEX_E0) },
7428     { PREFIX_TABLE (PREFIX_VEX_E1) },
7429     { PREFIX_TABLE (PREFIX_VEX_E2) },
7430     { PREFIX_TABLE (PREFIX_VEX_E3) },
7431     { PREFIX_TABLE (PREFIX_VEX_E4) },
7432     { PREFIX_TABLE (PREFIX_VEX_E5) },
7433     { PREFIX_TABLE (PREFIX_VEX_E6) },
7434     { PREFIX_TABLE (PREFIX_VEX_E7) },
7435     /* e8 */
7436     { PREFIX_TABLE (PREFIX_VEX_E8) },
7437     { PREFIX_TABLE (PREFIX_VEX_E9) },
7438     { PREFIX_TABLE (PREFIX_VEX_EA) },
7439     { PREFIX_TABLE (PREFIX_VEX_EB) },
7440     { PREFIX_TABLE (PREFIX_VEX_EC) },
7441     { PREFIX_TABLE (PREFIX_VEX_ED) },
7442     { PREFIX_TABLE (PREFIX_VEX_EE) },
7443     { PREFIX_TABLE (PREFIX_VEX_EF) },
7444     /* f0 */
7445     { PREFIX_TABLE (PREFIX_VEX_F0) },
7446     { PREFIX_TABLE (PREFIX_VEX_F1) },
7447     { PREFIX_TABLE (PREFIX_VEX_F2) },
7448     { PREFIX_TABLE (PREFIX_VEX_F3) },
7449     { PREFIX_TABLE (PREFIX_VEX_F4) },
7450     { PREFIX_TABLE (PREFIX_VEX_F5) },
7451     { PREFIX_TABLE (PREFIX_VEX_F6) },
7452     { PREFIX_TABLE (PREFIX_VEX_F7) },
7453     /* f8 */
7454     { PREFIX_TABLE (PREFIX_VEX_F8) },
7455     { PREFIX_TABLE (PREFIX_VEX_F9) },
7456     { PREFIX_TABLE (PREFIX_VEX_FA) },
7457     { PREFIX_TABLE (PREFIX_VEX_FB) },
7458     { PREFIX_TABLE (PREFIX_VEX_FC) },
7459     { PREFIX_TABLE (PREFIX_VEX_FD) },
7460     { PREFIX_TABLE (PREFIX_VEX_FE) },
7461     { Bad_Opcode },
7462   },
7463   /* VEX_0F38 */
7464   {
7465     /* 00 */
7466     { PREFIX_TABLE (PREFIX_VEX_3800) },
7467     { PREFIX_TABLE (PREFIX_VEX_3801) },
7468     { PREFIX_TABLE (PREFIX_VEX_3802) },
7469     { PREFIX_TABLE (PREFIX_VEX_3803) },
7470     { PREFIX_TABLE (PREFIX_VEX_3804) },
7471     { PREFIX_TABLE (PREFIX_VEX_3805) },
7472     { PREFIX_TABLE (PREFIX_VEX_3806) },
7473     { PREFIX_TABLE (PREFIX_VEX_3807) },
7474     /* 08 */
7475     { PREFIX_TABLE (PREFIX_VEX_3808) },
7476     { PREFIX_TABLE (PREFIX_VEX_3809) },
7477     { PREFIX_TABLE (PREFIX_VEX_380A) },
7478     { PREFIX_TABLE (PREFIX_VEX_380B) },
7479     { PREFIX_TABLE (PREFIX_VEX_380C) },
7480     { PREFIX_TABLE (PREFIX_VEX_380D) },
7481     { PREFIX_TABLE (PREFIX_VEX_380E) },
7482     { PREFIX_TABLE (PREFIX_VEX_380F) },
7483     /* 10 */
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { PREFIX_TABLE (PREFIX_VEX_3817) },
7492     /* 18 */
7493     { PREFIX_TABLE (PREFIX_VEX_3818) },
7494     { PREFIX_TABLE (PREFIX_VEX_3819) },
7495     { PREFIX_TABLE (PREFIX_VEX_381A) },
7496     { Bad_Opcode },
7497     { PREFIX_TABLE (PREFIX_VEX_381C) },
7498     { PREFIX_TABLE (PREFIX_VEX_381D) },
7499     { PREFIX_TABLE (PREFIX_VEX_381E) },
7500     { Bad_Opcode },
7501     /* 20 */
7502     { PREFIX_TABLE (PREFIX_VEX_3820) },
7503     { PREFIX_TABLE (PREFIX_VEX_3821) },
7504     { PREFIX_TABLE (PREFIX_VEX_3822) },
7505     { PREFIX_TABLE (PREFIX_VEX_3823) },
7506     { PREFIX_TABLE (PREFIX_VEX_3824) },
7507     { PREFIX_TABLE (PREFIX_VEX_3825) },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     /* 28 */
7511     { PREFIX_TABLE (PREFIX_VEX_3828) },
7512     { PREFIX_TABLE (PREFIX_VEX_3829) },
7513     { PREFIX_TABLE (PREFIX_VEX_382A) },
7514     { PREFIX_TABLE (PREFIX_VEX_382B) },
7515     { PREFIX_TABLE (PREFIX_VEX_382C) },
7516     { PREFIX_TABLE (PREFIX_VEX_382D) },
7517     { PREFIX_TABLE (PREFIX_VEX_382E) },
7518     { PREFIX_TABLE (PREFIX_VEX_382F) },
7519     /* 30 */
7520     { PREFIX_TABLE (PREFIX_VEX_3830) },
7521     { PREFIX_TABLE (PREFIX_VEX_3831) },
7522     { PREFIX_TABLE (PREFIX_VEX_3832) },
7523     { PREFIX_TABLE (PREFIX_VEX_3833) },
7524     { PREFIX_TABLE (PREFIX_VEX_3834) },
7525     { PREFIX_TABLE (PREFIX_VEX_3835) },
7526     { Bad_Opcode },
7527     { PREFIX_TABLE (PREFIX_VEX_3837) },
7528     /* 38 */
7529     { PREFIX_TABLE (PREFIX_VEX_3838) },
7530     { PREFIX_TABLE (PREFIX_VEX_3839) },
7531     { PREFIX_TABLE (PREFIX_VEX_383A) },
7532     { PREFIX_TABLE (PREFIX_VEX_383B) },
7533     { PREFIX_TABLE (PREFIX_VEX_383C) },
7534     { PREFIX_TABLE (PREFIX_VEX_383D) },
7535     { PREFIX_TABLE (PREFIX_VEX_383E) },
7536     { PREFIX_TABLE (PREFIX_VEX_383F) },
7537     /* 40 */
7538     { PREFIX_TABLE (PREFIX_VEX_3840) },
7539     { PREFIX_TABLE (PREFIX_VEX_3841) },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     /* 48 */
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     /* 50 */
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     /* 58 */
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     /* 60 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 68 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 70 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 78 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 80 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 88 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 90 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { PREFIX_TABLE (PREFIX_VEX_3896) },
7635     { PREFIX_TABLE (PREFIX_VEX_3897) },
7636     /* 98 */
7637     { PREFIX_TABLE (PREFIX_VEX_3898) },
7638     { PREFIX_TABLE (PREFIX_VEX_3899) },
7639     { PREFIX_TABLE (PREFIX_VEX_389A) },
7640     { PREFIX_TABLE (PREFIX_VEX_389B) },
7641     { PREFIX_TABLE (PREFIX_VEX_389C) },
7642     { PREFIX_TABLE (PREFIX_VEX_389D) },
7643     { PREFIX_TABLE (PREFIX_VEX_389E) },
7644     { PREFIX_TABLE (PREFIX_VEX_389F) },
7645     /* a0 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { PREFIX_TABLE (PREFIX_VEX_38A6) },
7653     { PREFIX_TABLE (PREFIX_VEX_38A7) },
7654     /* a8 */
7655     { PREFIX_TABLE (PREFIX_VEX_38A8) },
7656     { PREFIX_TABLE (PREFIX_VEX_38A9) },
7657     { PREFIX_TABLE (PREFIX_VEX_38AA) },
7658     { PREFIX_TABLE (PREFIX_VEX_38AB) },
7659     { PREFIX_TABLE (PREFIX_VEX_38AC) },
7660     { PREFIX_TABLE (PREFIX_VEX_38AD) },
7661     { PREFIX_TABLE (PREFIX_VEX_38AE) },
7662     { PREFIX_TABLE (PREFIX_VEX_38AF) },
7663     /* b0 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { PREFIX_TABLE (PREFIX_VEX_38B6) },
7671     { PREFIX_TABLE (PREFIX_VEX_38B7) },
7672     /* b8 */
7673     { PREFIX_TABLE (PREFIX_VEX_38B8) },
7674     { PREFIX_TABLE (PREFIX_VEX_38B9) },
7675     { PREFIX_TABLE (PREFIX_VEX_38BA) },
7676     { PREFIX_TABLE (PREFIX_VEX_38BB) },
7677     { PREFIX_TABLE (PREFIX_VEX_38BC) },
7678     { PREFIX_TABLE (PREFIX_VEX_38BD) },
7679     { PREFIX_TABLE (PREFIX_VEX_38BE) },
7680     { PREFIX_TABLE (PREFIX_VEX_38BF) },
7681     /* c0 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* c8 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* d0 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* d8 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { PREFIX_TABLE (PREFIX_VEX_38DB) },
7713     { PREFIX_TABLE (PREFIX_VEX_38DC) },
7714     { PREFIX_TABLE (PREFIX_VEX_38DD) },
7715     { PREFIX_TABLE (PREFIX_VEX_38DE) },
7716     { PREFIX_TABLE (PREFIX_VEX_38DF) },
7717     /* e0 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     /* e8 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     /* f0 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     /* f8 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753   },
7754   /* VEX_0F3A */
7755   {
7756     /* 00 */
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { PREFIX_TABLE (PREFIX_VEX_3A04) },
7762     { PREFIX_TABLE (PREFIX_VEX_3A05) },
7763     { PREFIX_TABLE (PREFIX_VEX_3A06) },
7764     { Bad_Opcode },
7765     /* 08 */
7766     { PREFIX_TABLE (PREFIX_VEX_3A08) },
7767     { PREFIX_TABLE (PREFIX_VEX_3A09) },
7768     { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7769     { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7770     { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7771     { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7772     { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7773     { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7774     /* 10 */
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { PREFIX_TABLE (PREFIX_VEX_3A14) },
7780     { PREFIX_TABLE (PREFIX_VEX_3A15) },
7781     { PREFIX_TABLE (PREFIX_VEX_3A16) },
7782     { PREFIX_TABLE (PREFIX_VEX_3A17) },
7783     /* 18 */
7784     { PREFIX_TABLE (PREFIX_VEX_3A18) },
7785     { PREFIX_TABLE (PREFIX_VEX_3A19) },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     /* 20 */
7793     { PREFIX_TABLE (PREFIX_VEX_3A20) },
7794     { PREFIX_TABLE (PREFIX_VEX_3A21) },
7795     { PREFIX_TABLE (PREFIX_VEX_3A22) },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     /* 28 */
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     /* 30 */
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     /* 38 */
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     /* 40 */
7829     { PREFIX_TABLE (PREFIX_VEX_3A40) },
7830     { PREFIX_TABLE (PREFIX_VEX_3A41) },
7831     { PREFIX_TABLE (PREFIX_VEX_3A42) },
7832     { Bad_Opcode },
7833     { PREFIX_TABLE (PREFIX_VEX_3A44) },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     /* 48 */
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7841     { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7842     { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     /* 50 */
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     /* 58 */
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7861     { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7862     { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7863     { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7864     /* 60 */
7865     { PREFIX_TABLE (PREFIX_VEX_3A60) },
7866     { PREFIX_TABLE (PREFIX_VEX_3A61) },
7867     { PREFIX_TABLE (PREFIX_VEX_3A62) },
7868     { PREFIX_TABLE (PREFIX_VEX_3A63) },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 68 */
7874     { PREFIX_TABLE (PREFIX_VEX_3A68) },
7875     { PREFIX_TABLE (PREFIX_VEX_3A69) },
7876     { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7877     { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7878     { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7879     { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7880     { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7881     { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7882     /* 70 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 78 */
7892     { PREFIX_TABLE (PREFIX_VEX_3A78) },
7893     { PREFIX_TABLE (PREFIX_VEX_3A79) },
7894     { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7895     { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7896     { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7897     { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7898     { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7899     { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7900     /* 80 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 88 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 90 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 98 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* a0 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* a8 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* b0 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* b8 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* c0 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* c8 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* d0 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* d8 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { PREFIX_TABLE (PREFIX_VEX_3ADF) },
8008     /* e0 */
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* e8 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* f0 */
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     /* f8 */
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044   },
8045 };
8046
8047 static const struct dis386 vex_len_table[][2] = {
8048   /* VEX_LEN_10_P_1 */
8049   {
8050     { VEX_W_TABLE (VEX_W_10_P_1) },
8051   },
8052
8053   /* VEX_LEN_10_P_3 */
8054   {
8055     { VEX_W_TABLE (VEX_W_10_P_3) },
8056   },
8057
8058   /* VEX_LEN_11_P_1 */
8059   {
8060     { VEX_W_TABLE (VEX_W_11_P_1) },
8061   },
8062
8063   /* VEX_LEN_11_P_3 */
8064   {
8065     { VEX_W_TABLE (VEX_W_11_P_3) },
8066   },
8067
8068   /* VEX_LEN_12_P_0_M_0 */
8069   {
8070     { VEX_W_TABLE (VEX_W_12_P_0_M_0) },
8071   },
8072
8073   /* VEX_LEN_12_P_0_M_1 */
8074   {
8075     { VEX_W_TABLE (VEX_W_12_P_0_M_1) },
8076   },
8077
8078   /* VEX_LEN_12_P_2 */
8079   {
8080     { VEX_W_TABLE (VEX_W_12_P_2) },
8081   },
8082
8083   /* VEX_LEN_13_M_0 */
8084   {
8085     { VEX_W_TABLE (VEX_W_13_M_0) },
8086   },
8087
8088   /* VEX_LEN_16_P_0_M_0 */
8089   {
8090     { VEX_W_TABLE (VEX_W_16_P_0_M_0) },
8091   },
8092
8093   /* VEX_LEN_16_P_0_M_1 */
8094   {
8095     { VEX_W_TABLE (VEX_W_16_P_0_M_1) },
8096   },
8097
8098   /* VEX_LEN_16_P_2 */
8099   {
8100     { VEX_W_TABLE (VEX_W_16_P_2) },
8101   },
8102
8103   /* VEX_LEN_17_M_0 */
8104   {
8105     { VEX_W_TABLE (VEX_W_17_M_0) },
8106   },
8107
8108   /* VEX_LEN_2A_P_1 */
8109   {
8110     { "vcvtsi2ss%LQ",   { XM, Vex128, Ev } },
8111   },
8112
8113   /* VEX_LEN_2A_P_3 */
8114   {
8115     { "vcvtsi2sd%LQ",   { XM, Vex128, Ev } },
8116   },
8117
8118   /* VEX_LEN_2C_P_1 */
8119   {
8120     { "vcvttss2siY",    { Gv, EXd } },
8121   },
8122
8123   /* VEX_LEN_2C_P_3 */
8124   {
8125     { "vcvttsd2siY",    { Gv, EXq } },
8126   },
8127
8128   /* VEX_LEN_2D_P_1 */
8129   {
8130     { "vcvtss2siY",     { Gv, EXd } },
8131   },
8132
8133   /* VEX_LEN_2D_P_3 */
8134   {
8135     { "vcvtsd2siY",     { Gv, EXq } },
8136   },
8137
8138   /* VEX_LEN_2E_P_0 */
8139   {
8140     { VEX_W_TABLE (VEX_W_2E_P_0) },
8141   },
8142
8143   /* VEX_LEN_2E_P_2 */
8144   {
8145     { VEX_W_TABLE (VEX_W_2E_P_2) },
8146   },
8147
8148   /* VEX_LEN_2F_P_0 */
8149   {
8150     { VEX_W_TABLE (VEX_W_2F_P_0) },
8151   },
8152
8153   /* VEX_LEN_2F_P_2 */
8154   {
8155     { VEX_W_TABLE (VEX_W_2F_P_2) },
8156   },
8157
8158   /* VEX_LEN_51_P_1 */
8159   {
8160     { VEX_W_TABLE (VEX_W_51_P_1) },
8161   },
8162
8163   /* VEX_LEN_51_P_3 */
8164   {
8165     { VEX_W_TABLE (VEX_W_51_P_3) },
8166   },
8167
8168   /* VEX_LEN_52_P_1 */
8169   {
8170     { VEX_W_TABLE (VEX_W_52_P_1) },
8171   },
8172
8173   /* VEX_LEN_53_P_1 */
8174   {
8175     { VEX_W_TABLE (VEX_W_53_P_1) },
8176   },
8177
8178   /* VEX_LEN_58_P_1 */
8179   {
8180     { VEX_W_TABLE (VEX_W_58_P_1) },
8181   },
8182
8183   /* VEX_LEN_58_P_3 */
8184   {
8185     { VEX_W_TABLE (VEX_W_58_P_3) },
8186   },
8187
8188   /* VEX_LEN_59_P_1 */
8189   {
8190     { VEX_W_TABLE (VEX_W_59_P_1) },
8191   },
8192
8193   /* VEX_LEN_59_P_3 */
8194   {
8195     { VEX_W_TABLE (VEX_W_59_P_3) },
8196   },
8197
8198   /* VEX_LEN_5A_P_1 */
8199   {
8200     { VEX_W_TABLE (VEX_W_5A_P_1) },
8201   },
8202
8203   /* VEX_LEN_5A_P_3 */
8204   {
8205     { VEX_W_TABLE (VEX_W_5A_P_3) },
8206   },
8207
8208   /* VEX_LEN_5C_P_1 */
8209   {
8210     { VEX_W_TABLE (VEX_W_5C_P_1) },
8211   },
8212
8213   /* VEX_LEN_5C_P_3 */
8214   {
8215     { VEX_W_TABLE (VEX_W_5C_P_3) },
8216   },
8217
8218   /* VEX_LEN_5D_P_1 */
8219   {
8220     { VEX_W_TABLE (VEX_W_5D_P_1) },
8221   },
8222
8223   /* VEX_LEN_5D_P_3 */
8224   {
8225     { VEX_W_TABLE (VEX_W_5D_P_3) },
8226   },
8227
8228   /* VEX_LEN_5E_P_1 */
8229   {
8230     { VEX_W_TABLE (VEX_W_5E_P_1) },
8231   },
8232
8233   /* VEX_LEN_5E_P_3 */
8234   {
8235     { VEX_W_TABLE (VEX_W_5E_P_3) },
8236   },
8237
8238   /* VEX_LEN_5F_P_1 */
8239   {
8240     { VEX_W_TABLE (VEX_W_5F_P_1) },
8241   },
8242
8243   /* VEX_LEN_5F_P_3 */
8244   {
8245     { VEX_W_TABLE (VEX_W_5F_P_3) },
8246   },
8247
8248   /* VEX_LEN_60_P_2 */
8249   {
8250     { VEX_W_TABLE (VEX_W_60_P_2) },
8251   },
8252
8253   /* VEX_LEN_61_P_2 */
8254   {
8255     { VEX_W_TABLE (VEX_W_61_P_2) },
8256   },
8257
8258   /* VEX_LEN_62_P_2 */
8259   {
8260     { VEX_W_TABLE (VEX_W_62_P_2) },
8261   },
8262
8263   /* VEX_LEN_63_P_2 */
8264   {
8265     { VEX_W_TABLE (VEX_W_63_P_2) },
8266   },
8267
8268   /* VEX_LEN_64_P_2 */
8269   {
8270     { VEX_W_TABLE (VEX_W_64_P_2) },
8271   },
8272
8273   /* VEX_LEN_65_P_2 */
8274   {
8275     { VEX_W_TABLE (VEX_W_65_P_2) },
8276   },
8277
8278   /* VEX_LEN_66_P_2 */
8279   {
8280     { VEX_W_TABLE (VEX_W_66_P_2) },
8281   },
8282
8283   /* VEX_LEN_67_P_2 */
8284   {
8285     { VEX_W_TABLE (VEX_W_67_P_2) },
8286   },
8287
8288   /* VEX_LEN_68_P_2 */
8289   {
8290     { VEX_W_TABLE (VEX_W_68_P_2) },
8291   },
8292
8293   /* VEX_LEN_69_P_2 */
8294   {
8295     { VEX_W_TABLE (VEX_W_69_P_2) },
8296   },
8297
8298   /* VEX_LEN_6A_P_2 */
8299   {
8300     { VEX_W_TABLE (VEX_W_6A_P_2) },
8301   },
8302
8303   /* VEX_LEN_6B_P_2 */
8304   {
8305     { VEX_W_TABLE (VEX_W_6B_P_2) },
8306   },
8307
8308   /* VEX_LEN_6C_P_2 */
8309   {
8310     { VEX_W_TABLE (VEX_W_6C_P_2) },
8311   },
8312
8313   /* VEX_LEN_6D_P_2 */
8314   {
8315     { VEX_W_TABLE (VEX_W_6D_P_2) },
8316   },
8317
8318   /* VEX_LEN_6E_P_2 */
8319   {
8320     { "vmovK",          { XM, Edq } },
8321   },
8322
8323   /* VEX_LEN_70_P_1 */
8324   {
8325     { VEX_W_TABLE (VEX_W_70_P_1) },
8326   },
8327
8328   /* VEX_LEN_70_P_2 */
8329   {
8330     { VEX_W_TABLE (VEX_W_70_P_2) },
8331   },
8332
8333   /* VEX_LEN_70_P_3 */
8334   {
8335     { VEX_W_TABLE (VEX_W_70_P_3) },
8336   },
8337
8338   /* VEX_LEN_71_R_2_P_2 */
8339   {
8340     { VEX_W_TABLE (VEX_W_71_R_2_P_2) },
8341   },
8342
8343   /* VEX_LEN_71_R_4_P_2 */
8344   {
8345     { VEX_W_TABLE (VEX_W_71_R_4_P_2) },
8346   },
8347
8348   /* VEX_LEN_71_R_6_P_2 */
8349   {
8350     { VEX_W_TABLE (VEX_W_71_R_6_P_2) },
8351   },
8352
8353   /* VEX_LEN_72_R_2_P_2 */
8354   {
8355     { VEX_W_TABLE (VEX_W_72_R_2_P_2) },
8356   },
8357
8358   /* VEX_LEN_72_R_4_P_2 */
8359   {
8360     { VEX_W_TABLE (VEX_W_72_R_4_P_2) },
8361   },
8362
8363   /* VEX_LEN_72_R_6_P_2 */
8364   {
8365     { VEX_W_TABLE (VEX_W_72_R_6_P_2) },
8366   },
8367
8368   /* VEX_LEN_73_R_2_P_2 */
8369   {
8370     { VEX_W_TABLE (VEX_W_73_R_2_P_2) },
8371   },
8372
8373   /* VEX_LEN_73_R_3_P_2 */
8374   {
8375     { VEX_W_TABLE (VEX_W_73_R_3_P_2) },
8376   },
8377
8378   /* VEX_LEN_73_R_6_P_2 */
8379   {
8380     { VEX_W_TABLE (VEX_W_73_R_6_P_2) },
8381   },
8382
8383   /* VEX_LEN_73_R_7_P_2 */
8384   {
8385     { VEX_W_TABLE (VEX_W_73_R_7_P_2) },
8386   },
8387
8388   /* VEX_LEN_74_P_2 */
8389   {
8390     { VEX_W_TABLE (VEX_W_74_P_2) },
8391   },
8392
8393   /* VEX_LEN_75_P_2 */
8394   {
8395     { VEX_W_TABLE (VEX_W_75_P_2) },
8396   },
8397
8398   /* VEX_LEN_76_P_2 */
8399   {
8400     { VEX_W_TABLE (VEX_W_76_P_2) },
8401   },
8402
8403   /* VEX_LEN_7E_P_1 */
8404   {
8405     { VEX_W_TABLE (VEX_W_7E_P_1) },
8406   },
8407
8408   /* VEX_LEN_7E_P_2 */
8409   {
8410     { "vmovK",          { Edq, XM } },
8411   },
8412
8413   /* VEX_LEN_AE_R_2_M_0 */
8414   {
8415     { VEX_W_TABLE (VEX_W_AE_R_2_M_0) },
8416   },
8417
8418   /* VEX_LEN_AE_R_3_M_0 */
8419   {
8420     { VEX_W_TABLE (VEX_W_AE_R_3_M_0) },
8421   },
8422
8423   /* VEX_LEN_C2_P_1 */
8424   {
8425     { VEX_W_TABLE (VEX_W_C2_P_1) },
8426   },
8427
8428   /* VEX_LEN_C2_P_3 */
8429   {
8430     { VEX_W_TABLE (VEX_W_C2_P_3) },
8431   },
8432
8433   /* VEX_LEN_C4_P_2 */
8434   {
8435     { VEX_W_TABLE (VEX_W_C4_P_2) },
8436   },
8437
8438   /* VEX_LEN_C5_P_2 */
8439   {
8440     { VEX_W_TABLE (VEX_W_C5_P_2) },
8441   },
8442
8443   /* VEX_LEN_D1_P_2 */
8444   {
8445     { VEX_W_TABLE (VEX_W_D1_P_2) },
8446   },
8447
8448   /* VEX_LEN_D2_P_2 */
8449   {
8450     { VEX_W_TABLE (VEX_W_D2_P_2) },
8451   },
8452
8453   /* VEX_LEN_D3_P_2 */
8454   {
8455     { VEX_W_TABLE (VEX_W_D3_P_2) },
8456   },
8457
8458   /* VEX_LEN_D4_P_2 */
8459   {
8460     { VEX_W_TABLE (VEX_W_D4_P_2) },
8461   },
8462
8463   /* VEX_LEN_D5_P_2 */
8464   {
8465     { VEX_W_TABLE (VEX_W_D5_P_2) },
8466   },
8467
8468   /* VEX_LEN_D6_P_2 */
8469   {
8470     { VEX_W_TABLE (VEX_W_D6_P_2) },
8471   },
8472
8473   /* VEX_LEN_D7_P_2_M_1 */
8474   {
8475     { VEX_W_TABLE (VEX_W_D7_P_2_M_1) },
8476   },
8477
8478   /* VEX_LEN_D8_P_2 */
8479   {
8480     { VEX_W_TABLE (VEX_W_D8_P_2) },
8481   },
8482
8483   /* VEX_LEN_D9_P_2 */
8484   {
8485     { VEX_W_TABLE (VEX_W_D9_P_2) },
8486   },
8487
8488   /* VEX_LEN_DA_P_2 */
8489   {
8490     { VEX_W_TABLE (VEX_W_DA_P_2) },
8491   },
8492
8493   /* VEX_LEN_DB_P_2 */
8494   {
8495     { VEX_W_TABLE (VEX_W_DB_P_2) },
8496   },
8497
8498   /* VEX_LEN_DC_P_2 */
8499   {
8500     { VEX_W_TABLE (VEX_W_DC_P_2) },
8501   },
8502
8503   /* VEX_LEN_DD_P_2 */
8504   {
8505     { VEX_W_TABLE (VEX_W_DD_P_2) },
8506   },
8507
8508   /* VEX_LEN_DE_P_2 */
8509   {
8510     { VEX_W_TABLE (VEX_W_DE_P_2) },
8511   },
8512
8513   /* VEX_LEN_DF_P_2 */
8514   {
8515     { VEX_W_TABLE (VEX_W_DF_P_2) },
8516   },
8517
8518   /* VEX_LEN_E0_P_2 */
8519   {
8520     { VEX_W_TABLE (VEX_W_E0_P_2) },
8521   },
8522
8523   /* VEX_LEN_E1_P_2 */
8524   {
8525     { VEX_W_TABLE (VEX_W_E1_P_2) },
8526   },
8527
8528   /* VEX_LEN_E2_P_2 */
8529   {
8530     { VEX_W_TABLE (VEX_W_E2_P_2) },
8531   },
8532
8533   /* VEX_LEN_E3_P_2 */
8534   {
8535     { VEX_W_TABLE (VEX_W_E3_P_2) },
8536   },
8537
8538   /* VEX_LEN_E4_P_2 */
8539   {
8540     { VEX_W_TABLE (VEX_W_E4_P_2) },
8541   },
8542
8543   /* VEX_LEN_E5_P_2 */
8544   {
8545     { VEX_W_TABLE (VEX_W_E5_P_2) },
8546   },
8547
8548   /* VEX_LEN_E8_P_2 */
8549   {
8550     { VEX_W_TABLE (VEX_W_E8_P_2) },
8551   },
8552
8553   /* VEX_LEN_E9_P_2 */
8554   {
8555     { VEX_W_TABLE (VEX_W_E9_P_2) },
8556   },
8557
8558   /* VEX_LEN_EA_P_2 */
8559   {
8560     { VEX_W_TABLE (VEX_W_EA_P_2) },
8561   },
8562
8563   /* VEX_LEN_EB_P_2 */
8564   {
8565     { VEX_W_TABLE (VEX_W_EB_P_2) },
8566   },
8567
8568   /* VEX_LEN_EC_P_2 */
8569   {
8570     { VEX_W_TABLE (VEX_W_EC_P_2) },
8571   },
8572
8573   /* VEX_LEN_ED_P_2 */
8574   {
8575     { VEX_W_TABLE (VEX_W_ED_P_2) },
8576   },
8577
8578   /* VEX_LEN_EE_P_2 */
8579   {
8580     { VEX_W_TABLE (VEX_W_EE_P_2) },
8581   },
8582
8583   /* VEX_LEN_EF_P_2 */
8584   {
8585     { VEX_W_TABLE (VEX_W_EF_P_2) },
8586   },
8587
8588   /* VEX_LEN_F1_P_2 */
8589   {
8590     { VEX_W_TABLE (VEX_W_F1_P_2) },
8591   },
8592
8593   /* VEX_LEN_F2_P_2 */
8594   {
8595     { VEX_W_TABLE (VEX_W_F2_P_2) },
8596     { Bad_Opcode },
8597   },
8598
8599   /* VEX_LEN_F3_P_2 */
8600   {
8601     { VEX_W_TABLE (VEX_W_F3_P_2) },
8602   },
8603
8604   /* VEX_LEN_F4_P_2 */
8605   {
8606     { VEX_W_TABLE (VEX_W_F4_P_2) },
8607   },
8608
8609   /* VEX_LEN_F5_P_2 */
8610   {
8611     { VEX_W_TABLE (VEX_W_F5_P_2) },
8612   },
8613
8614   /* VEX_LEN_F6_P_2 */
8615   {
8616     { VEX_W_TABLE (VEX_W_F6_P_2) },
8617   },
8618
8619   /* VEX_LEN_F7_P_2 */
8620   {
8621     { VEX_W_TABLE (VEX_W_F7_P_2) },
8622   },
8623
8624   /* VEX_LEN_F8_P_2 */
8625   {
8626     { VEX_W_TABLE (VEX_W_F8_P_2) },
8627   },
8628
8629   /* VEX_LEN_F9_P_2 */
8630   {
8631     { VEX_W_TABLE (VEX_W_F9_P_2) },
8632   },
8633
8634   /* VEX_LEN_FA_P_2 */
8635   {
8636     { VEX_W_TABLE (VEX_W_FA_P_2) },
8637   },
8638
8639   /* VEX_LEN_FB_P_2 */
8640   {
8641     { VEX_W_TABLE (VEX_W_FB_P_2) },
8642   },
8643
8644   /* VEX_LEN_FC_P_2 */
8645   {
8646     { VEX_W_TABLE (VEX_W_FC_P_2) },
8647   },
8648
8649   /* VEX_LEN_FD_P_2 */
8650   {
8651     { VEX_W_TABLE (VEX_W_FD_P_2) },
8652   },
8653
8654   /* VEX_LEN_FE_P_2 */
8655   {
8656     { VEX_W_TABLE (VEX_W_FE_P_2) },
8657   },
8658
8659   /* VEX_LEN_3800_P_2 */
8660   {
8661     { VEX_W_TABLE (VEX_W_3800_P_2) },
8662   },
8663
8664   /* VEX_LEN_3801_P_2 */
8665   {
8666     { VEX_W_TABLE (VEX_W_3801_P_2) },
8667   },
8668
8669   /* VEX_LEN_3802_P_2 */
8670   {
8671     { VEX_W_TABLE (VEX_W_3802_P_2) },
8672   },
8673
8674   /* VEX_LEN_3803_P_2 */
8675   {
8676     { VEX_W_TABLE (VEX_W_3803_P_2) },
8677   },
8678
8679   /* VEX_LEN_3804_P_2 */
8680   {
8681     { VEX_W_TABLE (VEX_W_3804_P_2) },
8682   },
8683
8684   /* VEX_LEN_3805_P_2 */
8685   {
8686     { VEX_W_TABLE (VEX_W_3805_P_2) },
8687   },
8688
8689   /* VEX_LEN_3806_P_2 */
8690   {
8691     { VEX_W_TABLE (VEX_W_3806_P_2) },
8692   },
8693
8694   /* VEX_LEN_3807_P_2 */
8695   {
8696     { VEX_W_TABLE (VEX_W_3807_P_2) },
8697   },
8698
8699   /* VEX_LEN_3808_P_2 */
8700   {
8701     { VEX_W_TABLE (VEX_W_3808_P_2) },
8702   },
8703
8704   /* VEX_LEN_3809_P_2 */
8705   {
8706     { VEX_W_TABLE (VEX_W_3809_P_2) },
8707   },
8708
8709   /* VEX_LEN_380A_P_2 */
8710   {
8711     { VEX_W_TABLE (VEX_W_380A_P_2) },
8712   },
8713
8714   /* VEX_LEN_380B_P_2 */
8715   {
8716     { VEX_W_TABLE (VEX_W_380B_P_2) },
8717   },
8718
8719   /* VEX_LEN_3819_P_2_M_0 */
8720   {
8721     { Bad_Opcode },
8722     { VEX_W_TABLE (VEX_W_3819_P_2_M_0) },
8723   },
8724
8725   /* VEX_LEN_381A_P_2_M_0 */
8726   {
8727     { Bad_Opcode },
8728     { VEX_W_TABLE (VEX_W_381A_P_2_M_0) },
8729   },
8730
8731   /* VEX_LEN_381C_P_2 */
8732   {
8733     { VEX_W_TABLE (VEX_W_381C_P_2) },
8734   },
8735
8736   /* VEX_LEN_381D_P_2 */
8737   {
8738     { VEX_W_TABLE (VEX_W_381D_P_2) },
8739   },
8740
8741   /* VEX_LEN_381E_P_2 */
8742   {
8743     { VEX_W_TABLE (VEX_W_381E_P_2) },
8744   },
8745
8746   /* VEX_LEN_3820_P_2 */
8747   {
8748     { VEX_W_TABLE (VEX_W_3820_P_2) },
8749   },
8750
8751   /* VEX_LEN_3821_P_2 */
8752   {
8753     { VEX_W_TABLE (VEX_W_3821_P_2) },
8754   },
8755
8756   /* VEX_LEN_3822_P_2 */
8757   {
8758     { VEX_W_TABLE (VEX_W_3822_P_2) },
8759   },
8760
8761   /* VEX_LEN_3823_P_2 */
8762   {
8763     { VEX_W_TABLE (VEX_W_3823_P_2) },
8764   },
8765
8766   /* VEX_LEN_3824_P_2 */
8767   {
8768     { VEX_W_TABLE (VEX_W_3824_P_2) },
8769   },
8770
8771   /* VEX_LEN_3825_P_2 */
8772   {
8773     { VEX_W_TABLE (VEX_W_3825_P_2) },
8774   },
8775
8776   /* VEX_LEN_3828_P_2 */
8777   {
8778     { VEX_W_TABLE (VEX_W_3828_P_2) },
8779   },
8780
8781   /* VEX_LEN_3829_P_2 */
8782   {
8783     { VEX_W_TABLE (VEX_W_3829_P_2) },
8784   },
8785
8786   /* VEX_LEN_382A_P_2_M_0 */
8787   {
8788     { VEX_W_TABLE (VEX_W_382A_P_2_M_0) },
8789   },
8790
8791   /* VEX_LEN_382B_P_2 */
8792   {
8793     { VEX_W_TABLE (VEX_W_382B_P_2) },
8794   },
8795
8796   /* VEX_LEN_3830_P_2 */
8797   {
8798     { VEX_W_TABLE (VEX_W_3830_P_2) },
8799   },
8800
8801   /* VEX_LEN_3831_P_2 */
8802   {
8803     { VEX_W_TABLE (VEX_W_3831_P_2) },
8804   },
8805
8806   /* VEX_LEN_3832_P_2 */
8807   {
8808     { VEX_W_TABLE (VEX_W_3832_P_2) },
8809   },
8810
8811   /* VEX_LEN_3833_P_2 */
8812   {
8813     { VEX_W_TABLE (VEX_W_3833_P_2) },
8814   },
8815
8816   /* VEX_LEN_3834_P_2 */
8817   {
8818     { VEX_W_TABLE (VEX_W_3834_P_2) },
8819   },
8820
8821   /* VEX_LEN_3835_P_2 */
8822   {
8823     { VEX_W_TABLE (VEX_W_3835_P_2) },
8824   },
8825
8826   /* VEX_LEN_3837_P_2 */
8827   {
8828     { VEX_W_TABLE (VEX_W_3837_P_2) },
8829   },
8830
8831   /* VEX_LEN_3838_P_2 */
8832   {
8833     { VEX_W_TABLE (VEX_W_3838_P_2) },
8834   },
8835
8836   /* VEX_LEN_3839_P_2 */
8837   {
8838     { VEX_W_TABLE (VEX_W_3839_P_2) },
8839   },
8840
8841   /* VEX_LEN_383A_P_2 */
8842   {
8843     { VEX_W_TABLE (VEX_W_383A_P_2) },
8844   },
8845
8846   /* VEX_LEN_383B_P_2 */
8847   {
8848     { VEX_W_TABLE (VEX_W_383B_P_2) },
8849   },
8850
8851   /* VEX_LEN_383C_P_2 */
8852   {
8853     { VEX_W_TABLE (VEX_W_383C_P_2) },
8854   },
8855
8856   /* VEX_LEN_383D_P_2 */
8857   {
8858     { VEX_W_TABLE (VEX_W_383D_P_2) },
8859   },
8860
8861   /* VEX_LEN_383E_P_2 */
8862   {
8863     { VEX_W_TABLE (VEX_W_383E_P_2) },
8864   },
8865
8866   /* VEX_LEN_383F_P_2 */
8867   {
8868     { VEX_W_TABLE (VEX_W_383F_P_2) },
8869   },
8870
8871   /* VEX_LEN_3840_P_2 */
8872   {
8873     { VEX_W_TABLE (VEX_W_3840_P_2) },
8874   },
8875
8876   /* VEX_LEN_3841_P_2 */
8877   {
8878     { VEX_W_TABLE (VEX_W_3841_P_2) },
8879   },
8880
8881   /* VEX_LEN_38DB_P_2 */
8882   {
8883     { VEX_W_TABLE (VEX_W_38DB_P_2) },
8884   },
8885
8886   /* VEX_LEN_38DC_P_2 */
8887   {
8888     { VEX_W_TABLE (VEX_W_38DC_P_2) },
8889   },
8890
8891   /* VEX_LEN_38DD_P_2 */
8892   {
8893     { VEX_W_TABLE (VEX_W_38DD_P_2) },
8894   },
8895
8896   /* VEX_LEN_38DE_P_2 */
8897   {
8898     { VEX_W_TABLE (VEX_W_38DE_P_2) },
8899   },
8900
8901   /* VEX_LEN_38DF_P_2 */
8902   {
8903     { VEX_W_TABLE (VEX_W_38DF_P_2) },
8904   },
8905
8906   /* VEX_LEN_3A06_P_2 */
8907   {
8908     { Bad_Opcode },
8909     { VEX_W_TABLE (VEX_W_3A06_P_2) },
8910   },
8911
8912   /* VEX_LEN_3A0A_P_2 */
8913   {
8914     { VEX_W_TABLE (VEX_W_3A0A_P_2) },
8915   },
8916
8917   /* VEX_LEN_3A0B_P_2 */
8918   {
8919     { VEX_W_TABLE (VEX_W_3A0B_P_2) },
8920   },
8921
8922   /* VEX_LEN_3A0E_P_2 */
8923   {
8924     { VEX_W_TABLE (VEX_W_3A0E_P_2) },
8925   },
8926
8927   /* VEX_LEN_3A0F_P_2 */
8928   {
8929     { VEX_W_TABLE (VEX_W_3A0F_P_2) },
8930   },
8931
8932   /* VEX_LEN_3A14_P_2 */
8933   {
8934     { VEX_W_TABLE (VEX_W_3A14_P_2) },
8935   },
8936
8937   /* VEX_LEN_3A15_P_2 */
8938   {
8939     { VEX_W_TABLE (VEX_W_3A15_P_2) },
8940   },
8941
8942   /* VEX_LEN_3A16_P_2  */
8943   {
8944     { "vpextrK",        { Edq, XM, Ib } },
8945   },
8946
8947   /* VEX_LEN_3A17_P_2 */
8948   {
8949     { "vextractps",     { Edqd, XM, Ib } },
8950   },
8951
8952   /* VEX_LEN_3A18_P_2 */
8953   {
8954     { Bad_Opcode },
8955     { VEX_W_TABLE (VEX_W_3A18_P_2) },
8956   },
8957
8958   /* VEX_LEN_3A19_P_2 */
8959   {
8960     { Bad_Opcode },
8961     { VEX_W_TABLE (VEX_W_3A19_P_2) },
8962   },
8963
8964   /* VEX_LEN_3A20_P_2 */
8965   {
8966     { VEX_W_TABLE (VEX_W_3A20_P_2) },
8967   },
8968
8969   /* VEX_LEN_3A21_P_2 */
8970   {
8971     { VEX_W_TABLE (VEX_W_3A21_P_2) },
8972   },
8973
8974   /* VEX_LEN_3A22_P_2 */
8975   {
8976     { "vpinsrK",        { XM, Vex128, Edq, Ib } },
8977   },
8978
8979   /* VEX_LEN_3A41_P_2 */
8980   {
8981     { VEX_W_TABLE (VEX_W_3A41_P_2) },
8982   },
8983
8984   /* VEX_LEN_3A42_P_2 */
8985   {
8986     { VEX_W_TABLE (VEX_W_3A42_P_2) },
8987   },
8988
8989   /* VEX_LEN_3A44_P_2 */
8990   {
8991     { VEX_W_TABLE (VEX_W_3A44_P_2) },
8992   },
8993
8994   /* VEX_LEN_3A4C_P_2 */
8995   {
8996     { VEX_W_TABLE (VEX_W_3A4C_P_2) },
8997   },
8998
8999   /* VEX_LEN_3A60_P_2 */
9000   {
9001     { VEX_W_TABLE (VEX_W_3A60_P_2) },
9002   },
9003
9004   /* VEX_LEN_3A61_P_2 */
9005   {
9006     { VEX_W_TABLE (VEX_W_3A61_P_2) },
9007   },
9008
9009   /* VEX_LEN_3A62_P_2 */
9010   {
9011     { VEX_W_TABLE (VEX_W_3A62_P_2) },
9012   },
9013
9014   /* VEX_LEN_3A63_P_2 */
9015   {
9016     { VEX_W_TABLE (VEX_W_3A63_P_2) },
9017   },
9018
9019   /* VEX_LEN_3A6A_P_2 */
9020   {
9021     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9022   },
9023
9024   /* VEX_LEN_3A6B_P_2 */
9025   {
9026     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9027   },
9028
9029   /* VEX_LEN_3A6E_P_2 */
9030   {
9031     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9032   },
9033
9034   /* VEX_LEN_3A6F_P_2 */
9035   {
9036     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9037   },
9038
9039   /* VEX_LEN_3A7A_P_2 */
9040   {
9041     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9042   },
9043
9044   /* VEX_LEN_3A7B_P_2 */
9045   {
9046     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9047   },
9048
9049   /* VEX_LEN_3A7E_P_2 */
9050   {
9051     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
9052   },
9053
9054   /* VEX_LEN_3A7F_P_2 */
9055   {
9056     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9057   },
9058
9059   /* VEX_LEN_3ADF_P_2 */
9060   {
9061     { VEX_W_TABLE (VEX_W_3ADF_P_2) },
9062   },
9063
9064   /* VEX_LEN_XOP_09_80 */
9065   {
9066     { "vfrczps",        { XM, EXxmm } },
9067     { "vfrczps",        { XM, EXymmq } },
9068   },
9069
9070   /* VEX_LEN_XOP_09_81 */
9071   {
9072     { "vfrczpd",        { XM, EXxmm } },
9073     { "vfrczpd",        { XM, EXymmq } },
9074   },
9075 };
9076
9077 static const struct dis386 vex_w_table[][2] = {
9078   {
9079     /* VEX_W_10_P_0 */
9080     { "vmovups",        { XM, EXx } },
9081   },
9082   {
9083     /* VEX_W_10_P_1 */
9084     { "vmovss",         { XMVex, Vex128, EXd } },
9085   },
9086   {
9087     /* VEX_W_10_P_2 */
9088     { "vmovupd",        { XM, EXx } },
9089   },
9090   {
9091     /* VEX_W_10_P_3 */
9092     { "vmovsd",         { XMVex, Vex128, EXq } },
9093   },
9094   {
9095     /* VEX_W_11_P_0 */
9096     { "vmovups",        { EXxS, XM } },
9097   },
9098   {
9099     /* VEX_W_11_P_1 */
9100     { "vmovss",         { EXdVexS, Vex128, XM } },
9101   },
9102   {
9103     /* VEX_W_11_P_2 */
9104     { "vmovupd",        { EXxS, XM } },
9105   },
9106   {
9107     /* VEX_W_11_P_3 */
9108     { "vmovsd",         { EXqVexS, Vex128, XM } },
9109   },
9110   {
9111     /* VEX_W_12_P_0_M_0 */
9112     { "vmovlps",        { XM, Vex128, EXq } },
9113   },
9114   {
9115     /* VEX_W_12_P_0_M_1 */
9116     { "vmovhlps",       { XM, Vex128, EXq } },
9117   },
9118   {
9119     /* VEX_W_12_P_1 */
9120     { "vmovsldup",      { XM, EXx } },
9121   },
9122   {
9123     /* VEX_W_12_P_2 */
9124     { "vmovlpd",        { XM, Vex128, EXq } },
9125   },
9126   {
9127     /* VEX_W_12_P_3 */
9128     { "vmovddup",       { XM, EXymmq } },
9129   },
9130   {
9131     /* VEX_W_13_M_0 */
9132     { "vmovlpX",        { EXq, XM } },
9133   },
9134   {
9135     /* VEX_W_14 */
9136     { "vunpcklpX",      { XM, Vex, EXx } },
9137   },
9138   {
9139     /* VEX_W_15 */
9140     { "vunpckhpX",      { XM, Vex, EXx } },
9141   },
9142   {
9143     /* VEX_W_16_P_0_M_0 */
9144     { "vmovhps",        { XM, Vex128, EXq } },
9145   },
9146   {
9147     /* VEX_W_16_P_0_M_1 */
9148     { "vmovlhps",       { XM, Vex128, EXq } },
9149   },
9150   {
9151     /* VEX_W_16_P_1 */
9152     { "vmovshdup",      { XM, EXx } },
9153   },
9154   {
9155     /* VEX_W_16_P_2 */
9156     { "vmovhpd",        { XM, Vex128, EXq } },
9157   },
9158   {
9159     /* VEX_W_17_M_0 */
9160     { "vmovhpX",        { EXq, XM } },
9161   },
9162   {
9163     /* VEX_W_28 */
9164     { "vmovapX",        { XM, EXx } },
9165   },
9166   {
9167     /* VEX_W_29 */
9168     { "vmovapX",        { EXxS, XM } },
9169   },
9170   {
9171     /* VEX_W_2B_M_0 */
9172     { "vmovntpX",       { Mx, XM } },
9173   },
9174   {
9175     /* VEX_W_2E_P_0 */
9176     { "vucomiss",       { XM, EXd } },
9177   },
9178   {
9179     /* VEX_W_2E_P_2 */
9180     { "vucomisd",       { XM, EXq } },
9181   },
9182   {
9183     /* VEX_W_2F_P_0 */
9184     { "vcomiss",        { XM, EXd } },
9185   },
9186   {
9187     /* VEX_W_2F_P_2 */
9188     { "vcomisd",        { XM, EXq } },
9189   },
9190   {
9191     /* VEX_W_50_M_0 */
9192     { "vmovmskpX",      { Gdq, XS } },
9193   },
9194   {
9195     /* VEX_W_51_P_0 */
9196     { "vsqrtps",        { XM, EXx } },
9197   },
9198   {
9199     /* VEX_W_51_P_1 */
9200     { "vsqrtss",        { XM, Vex128, EXd } },
9201   },
9202   {
9203     /* VEX_W_51_P_2  */
9204     { "vsqrtpd",        { XM, EXx } },
9205   },
9206   {
9207     /* VEX_W_51_P_3 */
9208     { "vsqrtsd",        { XM, Vex128, EXq } },
9209   },
9210   {
9211     /* VEX_W_52_P_0 */
9212     { "vrsqrtps",       { XM, EXx } },
9213   },
9214   {
9215     /* VEX_W_52_P_1 */
9216     { "vrsqrtss",       { XM, Vex128, EXd } },
9217   },
9218   {
9219     /* VEX_W_53_P_0  */
9220     { "vrcpps",         { XM, EXx } },
9221   },
9222   {
9223     /* VEX_W_53_P_1  */
9224     { "vrcpss",         { XM, Vex128, EXd } },
9225   },
9226   {
9227     /* VEX_W_58_P_0  */
9228     { "vaddps",         { XM, Vex, EXx } },
9229   },
9230   {
9231     /* VEX_W_58_P_1  */
9232     { "vaddss",         { XM, Vex128, EXd } },
9233   },
9234   {
9235     /* VEX_W_58_P_2  */
9236     { "vaddpd",         { XM, Vex, EXx } },
9237   },
9238   {
9239     /* VEX_W_58_P_3  */
9240     { "vaddsd",         { XM, Vex128, EXq } },
9241   },
9242   {
9243     /* VEX_W_59_P_0  */
9244     { "vmulps",         { XM, Vex, EXx } },
9245   },
9246   {
9247     /* VEX_W_59_P_1  */
9248     { "vmulss",         { XM, Vex128, EXd } },
9249   },
9250   {
9251     /* VEX_W_59_P_2  */
9252     { "vmulpd",         { XM, Vex, EXx } },
9253   },
9254   {
9255     /* VEX_W_59_P_3  */
9256     { "vmulsd",         { XM, Vex128, EXq } },
9257   },
9258   {
9259     /* VEX_W_5A_P_0  */
9260     { "vcvtps2pd",      { XM, EXxmmq } },
9261   },
9262   {
9263     /* VEX_W_5A_P_1  */
9264     { "vcvtss2sd",      { XM, Vex128, EXd } },
9265   },
9266   {
9267     /* VEX_W_5A_P_3  */
9268     { "vcvtsd2ss",      { XM, Vex128, EXq } },
9269   },
9270   {
9271     /* VEX_W_5B_P_0  */
9272     { "vcvtdq2ps",      { XM, EXx } },
9273   },
9274   {
9275     /* VEX_W_5B_P_1  */
9276     { "vcvttps2dq",     { XM, EXx } },
9277   },
9278   {
9279     /* VEX_W_5B_P_2  */
9280     { "vcvtps2dq",      { XM, EXx } },
9281   },
9282   {
9283     /* VEX_W_5C_P_0  */
9284     { "vsubps",         { XM, Vex, EXx } },
9285   },
9286   {
9287     /* VEX_W_5C_P_1  */
9288     { "vsubss",         { XM, Vex128, EXd } },
9289   },
9290   {
9291     /* VEX_W_5C_P_2  */
9292     { "vsubpd",         { XM, Vex, EXx } },
9293   },
9294   {
9295     /* VEX_W_5C_P_3  */
9296     { "vsubsd",         { XM, Vex128, EXq } },
9297   },
9298   {
9299     /* VEX_W_5D_P_0  */
9300     { "vminps",         { XM, Vex, EXx } },
9301   },
9302   {
9303     /* VEX_W_5D_P_1  */
9304     { "vminss",         { XM, Vex128, EXd } },
9305   },
9306   {
9307     /* VEX_W_5D_P_2  */
9308     { "vminpd",         { XM, Vex, EXx } },
9309   },
9310   {
9311     /* VEX_W_5D_P_3  */
9312     { "vminsd",         { XM, Vex128, EXq } },
9313   },
9314   {
9315     /* VEX_W_5E_P_0  */
9316     { "vdivps",         { XM, Vex, EXx } },
9317   },
9318   {
9319     /* VEX_W_5E_P_1  */
9320     { "vdivss",         { XM, Vex128, EXd } },
9321   },
9322   {
9323     /* VEX_W_5E_P_2  */
9324     { "vdivpd",         { XM, Vex, EXx } },
9325   },
9326   {
9327     /* VEX_W_5E_P_3  */
9328     { "vdivsd",         { XM, Vex128, EXq } },
9329   },
9330   {
9331     /* VEX_W_5F_P_0  */
9332     { "vmaxps",         { XM, Vex, EXx } },
9333   },
9334   {
9335     /* VEX_W_5F_P_1  */
9336     { "vmaxss",         { XM, Vex128, EXd } },
9337   },
9338   {
9339     /* VEX_W_5F_P_2  */
9340     { "vmaxpd",         { XM, Vex, EXx } },
9341   },
9342   {
9343     /* VEX_W_5F_P_3  */
9344     { "vmaxsd",         { XM, Vex128, EXq } },
9345   },
9346   {
9347     /* VEX_W_60_P_2  */
9348     { "vpunpcklbw",     { XM, Vex128, EXx } },
9349   },
9350   {
9351     /* VEX_W_61_P_2  */
9352     { "vpunpcklwd",     { XM, Vex128, EXx } },
9353   },
9354   {
9355     /* VEX_W_62_P_2  */
9356     { "vpunpckldq",     { XM, Vex128, EXx } },
9357   },
9358   {
9359     /* VEX_W_63_P_2  */
9360     { "vpacksswb",      { XM, Vex128, EXx } },
9361   },
9362   {
9363     /* VEX_W_64_P_2  */
9364     { "vpcmpgtb",       { XM, Vex128, EXx } },
9365   },
9366   {
9367     /* VEX_W_65_P_2  */
9368     { "vpcmpgtw",       { XM, Vex128, EXx } },
9369   },
9370   {
9371     /* VEX_W_66_P_2  */
9372     { "vpcmpgtd",       { XM, Vex128, EXx } },
9373   },
9374   {
9375     /* VEX_W_67_P_2  */
9376     { "vpackuswb",      { XM, Vex128, EXx } },
9377   },
9378   {
9379     /* VEX_W_68_P_2  */
9380     { "vpunpckhbw",     { XM, Vex128, EXx } },
9381   },
9382   {
9383     /* VEX_W_69_P_2  */
9384     { "vpunpckhwd",     { XM, Vex128, EXx } },
9385   },
9386   {
9387     /* VEX_W_6A_P_2  */
9388     { "vpunpckhdq",     { XM, Vex128, EXx } },
9389   },
9390   {
9391     /* VEX_W_6B_P_2  */
9392     { "vpackssdw",      { XM, Vex128, EXx } },
9393   },
9394   {
9395     /* VEX_W_6C_P_2  */
9396     { "vpunpcklqdq",    { XM, Vex128, EXx } },
9397   },
9398   {
9399     /* VEX_W_6D_P_2  */
9400     { "vpunpckhqdq",    { XM, Vex128, EXx } },
9401   },
9402   {
9403     /* VEX_W_6F_P_1  */
9404     { "vmovdqu",        { XM, EXx } },
9405   },
9406   {
9407     /* VEX_W_6F_P_2  */
9408     { "vmovdqa",        { XM, EXx } },
9409   },
9410   {
9411     /* VEX_W_70_P_1 */
9412     { "vpshufhw",       { XM, EXx, Ib } },
9413   },
9414   {
9415     /* VEX_W_70_P_2 */
9416     { "vpshufd",        { XM, EXx, Ib } },
9417   },
9418   {
9419     /* VEX_W_70_P_3 */
9420     { "vpshuflw",       { XM, EXx, Ib } },
9421   },
9422   {
9423     /* VEX_W_71_R_2_P_2  */
9424     { "vpsrlw",         { Vex128, XS, Ib } },
9425   },
9426   {
9427     /* VEX_W_71_R_4_P_2  */
9428     { "vpsraw",         { Vex128, XS, Ib } },
9429   },
9430   {
9431     /* VEX_W_71_R_6_P_2  */
9432     { "vpsllw",         { Vex128, XS, Ib } },
9433   },
9434   {
9435     /* VEX_W_72_R_2_P_2  */
9436     { "vpsrld",         { Vex128, XS, Ib } },
9437   },
9438   {
9439     /* VEX_W_72_R_4_P_2  */
9440     { "vpsrad",         { Vex128, XS, Ib } },
9441   },
9442   {
9443     /* VEX_W_72_R_6_P_2  */
9444     { "vpslld",         { Vex128, XS, Ib } },
9445   },
9446   {
9447     /* VEX_W_73_R_2_P_2  */
9448     { "vpsrlq",         { Vex128, XS, Ib } },
9449   },
9450   {
9451     /* VEX_W_73_R_3_P_2  */
9452     { "vpsrldq",        { Vex128, XS, Ib } },
9453   },
9454   {
9455     /* VEX_W_73_R_6_P_2  */
9456     { "vpsllq",         { Vex128, XS, Ib } },
9457   },
9458   {
9459     /* VEX_W_73_R_7_P_2  */
9460     { "vpslldq",        { Vex128, XS, Ib } },
9461   },
9462   {
9463     /* VEX_W_74_P_2 */
9464     { "vpcmpeqb",       { XM, Vex128, EXx } },
9465   },
9466   {
9467     /* VEX_W_75_P_2 */
9468     { "vpcmpeqw",       { XM, Vex128, EXx } },
9469   },
9470   {
9471     /* VEX_W_76_P_2 */
9472     { "vpcmpeqd",       { XM, Vex128, EXx } },
9473   },
9474   {
9475     /* VEX_W_77_P_0 */
9476     { "",               { VZERO } },
9477   },
9478   {
9479     /* VEX_W_7C_P_2 */
9480     { "vhaddpd",        { XM, Vex, EXx } },
9481   },
9482   {
9483     /* VEX_W_7C_P_3 */
9484     { "vhaddps",        { XM, Vex, EXx } },
9485   },
9486   {
9487     /* VEX_W_7D_P_2 */
9488     { "vhsubpd",        { XM, Vex, EXx } },
9489   },
9490   {
9491     /* VEX_W_7D_P_3 */
9492     { "vhsubps",        { XM, Vex, EXx } },
9493   },
9494   {
9495     /* VEX_W_7E_P_1 */
9496     { "vmovq",          { XM, EXq } },
9497   },
9498   {
9499     /* VEX_W_7F_P_1 */
9500     { "vmovdqu",        { EXxS, XM } },
9501   },
9502   {
9503     /* VEX_W_7F_P_2 */
9504     { "vmovdqa",        { EXxS, XM } },
9505   },
9506   {
9507     /* VEX_W_AE_R_2_M_0 */
9508     { "vldmxcsr",       { Md } },
9509   },
9510   {
9511     /* VEX_W_AE_R_3_M_0 */
9512     { "vstmxcsr",       { Md } },
9513   },
9514   {
9515     /* VEX_W_C2_P_0 */
9516     { "vcmpps",         { XM, Vex, EXx, VCMP } },
9517   },
9518   {
9519     /* VEX_W_C2_P_1 */
9520     { "vcmpss",         { XM, Vex128, EXd, VCMP } },
9521   },
9522   {
9523     /* VEX_W_C2_P_2 */
9524     { "vcmppd",         { XM, Vex, EXx, VCMP } },
9525   },
9526   {
9527     /* VEX_W_C2_P_3 */
9528     { "vcmpsd",         { XM, Vex128, EXq, VCMP } },
9529   },
9530   {
9531     /* VEX_W_C4_P_2 */
9532     { "vpinsrw",        { XM, Vex128, Edqw, Ib } },
9533   },
9534   {
9535     /* VEX_W_C5_P_2 */
9536     { "vpextrw",        { Gdq, XS, Ib } },
9537   },
9538   {
9539     /* VEX_W_D0_P_2 */
9540     { "vaddsubpd",      { XM, Vex, EXx } },
9541   },
9542   {
9543     /* VEX_W_D0_P_3 */
9544     { "vaddsubps",      { XM, Vex, EXx } },
9545   },
9546   {
9547     /* VEX_W_D1_P_2 */
9548     { "vpsrlw",         { XM, Vex128, EXx } },
9549   },
9550   {
9551     /* VEX_W_D2_P_2 */
9552     { "vpsrld",         { XM, Vex128, EXx } },
9553   },
9554   {
9555     /* VEX_W_D3_P_2 */
9556     { "vpsrlq",         { XM, Vex128, EXx } },
9557   },
9558   {
9559     /* VEX_W_D4_P_2 */
9560     { "vpaddq",         { XM, Vex128, EXx } },
9561   },
9562   {
9563     /* VEX_W_D5_P_2 */
9564     { "vpmullw",        { XM, Vex128, EXx } },
9565   },
9566   {
9567     /* VEX_W_D6_P_2 */
9568     { "vmovq",          { EXqS, XM } },
9569   },
9570   {
9571     /* VEX_W_D7_P_2_M_1 */
9572     { "vpmovmskb",      { Gdq, XS } },
9573   },
9574   {
9575     /* VEX_W_D8_P_2 */
9576     { "vpsubusb",       { XM, Vex128, EXx } },
9577   },
9578   {
9579     /* VEX_W_D9_P_2 */
9580     { "vpsubusw",       { XM, Vex128, EXx } },
9581   },
9582   {
9583     /* VEX_W_DA_P_2 */
9584     { "vpminub",        { XM, Vex128, EXx } },
9585   },
9586   {
9587     /* VEX_W_DB_P_2 */
9588     { "vpand",          { XM, Vex128, EXx } },
9589   },
9590   {
9591     /* VEX_W_DC_P_2 */
9592     { "vpaddusb",       { XM, Vex128, EXx } },
9593   },
9594   {
9595     /* VEX_W_DD_P_2 */
9596     { "vpaddusw",       { XM, Vex128, EXx } },
9597   },
9598   {
9599     /* VEX_W_DE_P_2 */
9600     { "vpmaxub",        { XM, Vex128, EXx } },
9601   },
9602   {
9603     /* VEX_W_DF_P_2 */
9604     { "vpandn",         { XM, Vex128, EXx } },
9605   },
9606   {
9607     /* VEX_W_E0_P_2  */
9608     { "vpavgb",         { XM, Vex128, EXx } },
9609   },
9610   {
9611     /* VEX_W_E1_P_2  */
9612     { "vpsraw",         { XM, Vex128, EXx } },
9613   },
9614   {
9615     /* VEX_W_E2_P_2  */
9616     { "vpsrad",         { XM, Vex128, EXx } },
9617   },
9618   {
9619     /* VEX_W_E3_P_2  */
9620     { "vpavgw",         { XM, Vex128, EXx } },
9621   },
9622   {
9623     /* VEX_W_E4_P_2  */
9624     { "vpmulhuw",       { XM, Vex128, EXx } },
9625   },
9626   {
9627     /* VEX_W_E5_P_2  */
9628     { "vpmulhw",        { XM, Vex128, EXx } },
9629   },
9630   {
9631     /* VEX_W_E6_P_1  */
9632     { "vcvtdq2pd",      { XM, EXxmmq } },
9633   },
9634   {
9635     /* VEX_W_E6_P_2  */
9636     { "vcvttpd2dq%XY",  { XMM, EXx } },
9637   },
9638   {
9639     /* VEX_W_E6_P_3  */
9640     { "vcvtpd2dq%XY",   { XMM, EXx } },
9641   },
9642   {
9643     /* VEX_W_E7_P_2_M_0 */
9644     { "vmovntdq",       { Mx, XM } },
9645   },
9646   {
9647     /* VEX_W_E8_P_2  */
9648     { "vpsubsb",        { XM, Vex128, EXx } },
9649   },
9650   {
9651     /* VEX_W_E9_P_2  */
9652     { "vpsubsw",        { XM, Vex128, EXx } },
9653   },
9654   {
9655     /* VEX_W_EA_P_2  */
9656     { "vpminsw",        { XM, Vex128, EXx } },
9657   },
9658   {
9659     /* VEX_W_EB_P_2  */
9660     { "vpor",           { XM, Vex128, EXx } },
9661   },
9662   {
9663     /* VEX_W_EC_P_2  */
9664     { "vpaddsb",        { XM, Vex128, EXx } },
9665   },
9666   {
9667     /* VEX_W_ED_P_2  */
9668     { "vpaddsw",        { XM, Vex128, EXx } },
9669   },
9670   {
9671     /* VEX_W_EE_P_2  */
9672     { "vpmaxsw",        { XM, Vex128, EXx } },
9673   },
9674   {
9675     /* VEX_W_EF_P_2  */
9676     { "vpxor",          { XM, Vex128, EXx } },
9677   },
9678   {
9679     /* VEX_W_F0_P_3_M_0 */
9680     { "vlddqu",         { XM, M } },
9681   },
9682   {
9683     /* VEX_W_F1_P_2 */
9684     { "vpsllw",         { XM, Vex128, EXx } },
9685   },
9686   {
9687     /* VEX_W_F2_P_2 */
9688     { "vpslld",         { XM, Vex128, EXx } },
9689   },
9690   {
9691     /* VEX_W_F3_P_2 */
9692     { "vpsllq",         { XM, Vex128, EXx } },
9693   },
9694   {
9695     /* VEX_W_F4_P_2 */
9696     { "vpmuludq",       { XM, Vex128, EXx } },
9697   },
9698   {
9699     /* VEX_W_F5_P_2 */
9700     { "vpmaddwd",       { XM, Vex128, EXx } },
9701   },
9702   {
9703     /* VEX_W_F6_P_2 */
9704     { "vpsadbw",        { XM, Vex128, EXx } },
9705   },
9706   {
9707     /* VEX_W_F7_P_2 */
9708     { "vmaskmovdqu",    { XM, XS } },
9709   },
9710   {
9711     /* VEX_W_F8_P_2 */
9712     { "vpsubb",         { XM, Vex128, EXx } },
9713   },
9714   {
9715     /* VEX_W_F9_P_2 */
9716     { "vpsubw",         { XM, Vex128, EXx } },
9717   },
9718   {
9719     /* VEX_W_FA_P_2 */
9720     { "vpsubd",         { XM, Vex128, EXx } },
9721   },
9722   {
9723     /* VEX_W_FB_P_2 */
9724     { "vpsubq",         { XM, Vex128, EXx } },
9725   },
9726   {
9727     /* VEX_W_FC_P_2 */
9728     { "vpaddb",         { XM, Vex128, EXx } },
9729   },
9730   {
9731     /* VEX_W_FD_P_2 */
9732     { "vpaddw",         { XM, Vex128, EXx } },
9733   },
9734   {
9735     /* VEX_W_FE_P_2 */
9736     { "vpaddd",         { XM, Vex128, EXx } },
9737   },
9738   {
9739     /* VEX_W_3800_P_2  */
9740     { "vpshufb",        { XM, Vex128, EXx } },
9741   },
9742   {
9743     /* VEX_W_3801_P_2  */
9744     { "vphaddw",        { XM, Vex128, EXx } },
9745   },
9746   {
9747     /* VEX_W_3802_P_2  */
9748     { "vphaddd",        { XM, Vex128, EXx } },
9749   },
9750   {
9751     /* VEX_W_3803_P_2  */
9752     { "vphaddsw",       { XM, Vex128, EXx } },
9753   },
9754   {
9755     /* VEX_W_3804_P_2  */
9756     { "vpmaddubsw",     { XM, Vex128, EXx } },
9757   },
9758   {
9759     /* VEX_W_3805_P_2  */
9760     { "vphsubw",        { XM, Vex128, EXx } },
9761   },
9762   {
9763     /* VEX_W_3806_P_2  */
9764     { "vphsubd",        { XM, Vex128, EXx } },
9765   },
9766   {
9767     /* VEX_W_3807_P_2  */
9768     { "vphsubsw",       { XM, Vex128, EXx } },
9769   },
9770   {
9771     /* VEX_W_3808_P_2  */
9772     { "vpsignb",        { XM, Vex128, EXx } },
9773   },
9774   {
9775     /* VEX_W_3809_P_2  */
9776     { "vpsignw",        { XM, Vex128, EXx } },
9777   },
9778   {
9779     /* VEX_W_380A_P_2  */
9780     { "vpsignd",        { XM, Vex128, EXx } },
9781   },
9782   {
9783     /* VEX_W_380B_P_2  */
9784     { "vpmulhrsw",      { XM, Vex128, EXx } },
9785   },
9786   {
9787     /* VEX_W_380C_P_2  */
9788     { "vpermilps",      { XM, Vex, EXx } },
9789   },
9790   {
9791     /* VEX_W_380D_P_2  */
9792     { "vpermilpd",      { XM, Vex, EXx } },
9793   },
9794   {
9795     /* VEX_W_380E_P_2  */
9796     { "vtestps",        { XM, EXx } },
9797   },
9798   {
9799     /* VEX_W_380F_P_2  */
9800     { "vtestpd",        { XM, EXx } },
9801   },
9802   {
9803     /* VEX_W_3817_P_2 */
9804     { "vptest",         { XM, EXx } },
9805   },
9806   {
9807     /* VEX_W_3818_P_2_M_0 */
9808     { "vbroadcastss",   { XM, Md } },
9809   },
9810   {
9811     /* VEX_W_3819_P_2_M_0 */
9812     { "vbroadcastsd",   { XM, Mq } },
9813   },
9814   {
9815     /* VEX_W_381A_P_2_M_0 */
9816     { "vbroadcastf128", { XM, Mxmm } },
9817   },
9818   {
9819     /* VEX_W_381C_P_2 */
9820     { "vpabsb",         { XM, EXx } },
9821   },
9822   {
9823     /* VEX_W_381D_P_2 */
9824     { "vpabsw",         { XM, EXx } },
9825   },
9826   {
9827     /* VEX_W_381E_P_2 */
9828     { "vpabsd",         { XM, EXx } },
9829   },
9830   {
9831     /* VEX_W_3820_P_2 */
9832     { "vpmovsxbw",      { XM, EXq } },
9833   },
9834   {
9835     /* VEX_W_3821_P_2 */
9836     { "vpmovsxbd",      { XM, EXd } },
9837   },
9838   {
9839     /* VEX_W_3822_P_2 */
9840     { "vpmovsxbq",      { XM, EXw } },
9841   },
9842   {
9843     /* VEX_W_3823_P_2 */
9844     { "vpmovsxwd",      { XM, EXq } },
9845   },
9846   {
9847     /* VEX_W_3824_P_2 */
9848     { "vpmovsxwq",      { XM, EXd } },
9849   },
9850   {
9851     /* VEX_W_3825_P_2 */
9852     { "vpmovsxdq",      { XM, EXq } },
9853   },
9854   {
9855     /* VEX_W_3828_P_2 */
9856     { "vpmuldq",        { XM, Vex128, EXx } },
9857   },
9858   {
9859     /* VEX_W_3829_P_2 */
9860     { "vpcmpeqq",       { XM, Vex128, EXx } },
9861   },
9862   {
9863     /* VEX_W_382A_P_2_M_0 */
9864     { "vmovntdqa",      { XM, Mx } },
9865   },
9866   {
9867     /* VEX_W_382B_P_2 */
9868     { "vpackusdw",      { XM, Vex128, EXx } },
9869   },
9870   {
9871     /* VEX_W_382C_P_2_M_0 */
9872     { "vmaskmovps",     { XM, Vex, Mx } },
9873   },
9874   {
9875     /* VEX_W_382D_P_2_M_0 */
9876     { "vmaskmovpd",     { XM, Vex, Mx } },
9877   },
9878   {
9879     /* VEX_W_382E_P_2_M_0 */
9880     { "vmaskmovps",     { Mx, Vex, XM } },
9881   },
9882   {
9883     /* VEX_W_382F_P_2_M_0 */
9884     { "vmaskmovpd",     { Mx, Vex, XM } },
9885   },
9886   {
9887     /* VEX_W_3830_P_2 */
9888     { "vpmovzxbw",      { XM, EXq } },
9889   },
9890   {
9891     /* VEX_W_3831_P_2 */
9892     { "vpmovzxbd",      { XM, EXd } },
9893   },
9894   {
9895     /* VEX_W_3832_P_2 */
9896     { "vpmovzxbq",      { XM, EXw } },
9897   },
9898   {
9899     /* VEX_W_3833_P_2 */
9900     { "vpmovzxwd",      { XM, EXq } },
9901   },
9902   {
9903     /* VEX_W_3834_P_2 */
9904     { "vpmovzxwq",      { XM, EXd } },
9905   },
9906   {
9907     /* VEX_W_3835_P_2 */
9908     { "vpmovzxdq",      { XM, EXq } },
9909   },
9910   {
9911     /* VEX_W_3837_P_2 */
9912     { "vpcmpgtq",       { XM, Vex128, EXx } },
9913   },
9914   {
9915     /* VEX_W_3838_P_2 */
9916     { "vpminsb",        { XM, Vex128, EXx } },
9917   },
9918   {
9919     /* VEX_W_3839_P_2 */
9920     { "vpminsd",        { XM, Vex128, EXx } },
9921   },
9922   {
9923     /* VEX_W_383A_P_2 */
9924     { "vpminuw",        { XM, Vex128, EXx } },
9925   },
9926   {
9927     /* VEX_W_383B_P_2 */
9928     { "vpminud",        { XM, Vex128, EXx } },
9929   },
9930   {
9931     /* VEX_W_383C_P_2 */
9932     { "vpmaxsb",        { XM, Vex128, EXx } },
9933   },
9934   {
9935     /* VEX_W_383D_P_2 */
9936     { "vpmaxsd",        { XM, Vex128, EXx } },
9937   },
9938   {
9939     /* VEX_W_383E_P_2 */
9940     { "vpmaxuw",        { XM, Vex128, EXx } },
9941   },
9942   {
9943     /* VEX_W_383F_P_2 */
9944     { "vpmaxud",        { XM, Vex128, EXx } },
9945   },
9946   {
9947     /* VEX_W_3840_P_2 */
9948     { "vpmulld",        { XM, Vex128, EXx } },
9949   },
9950   {
9951     /* VEX_W_3841_P_2 */
9952     { "vphminposuw",    { XM, EXx } },
9953   },
9954   {
9955     /* VEX_W_38DB_P_2 */
9956     { "vaesimc",        { XM, EXx } },
9957   },
9958   {
9959     /* VEX_W_38DC_P_2 */
9960     { "vaesenc",        { XM, Vex128, EXx } },
9961   },
9962   {
9963     /* VEX_W_38DD_P_2 */
9964     { "vaesenclast",    { XM, Vex128, EXx } },
9965   },
9966   {
9967     /* VEX_W_38DE_P_2 */
9968     { "vaesdec",        { XM, Vex128, EXx } },
9969   },
9970   {
9971     /* VEX_W_38DF_P_2 */
9972     { "vaesdeclast",    { XM, Vex128, EXx } },
9973   },
9974   {
9975     /* VEX_W_3A04_P_2 */
9976     { "vpermilps",      { XM, EXx, Ib } },
9977   },
9978   {
9979     /* VEX_W_3A05_P_2 */
9980     { "vpermilpd",      { XM, EXx, Ib } },
9981   },
9982   {
9983     /* VEX_W_3A06_P_2 */
9984     { "vperm2f128",     { XM, Vex256, EXx, Ib } },
9985   },
9986   {
9987     /* VEX_W_3A08_P_2 */
9988     { "vroundps",       { XM, EXx, Ib } },
9989   },
9990   {
9991     /* VEX_W_3A09_P_2 */
9992     { "vroundpd",       { XM, EXx, Ib } },
9993   },
9994   {
9995     /* VEX_W_3A0A_P_2 */
9996     { "vroundss",       { XM, Vex128, EXd, Ib } },
9997   },
9998   {
9999     /* VEX_W_3A0B_P_2 */
10000     { "vroundsd",       { XM, Vex128, EXq, Ib } },
10001   },
10002   {
10003     /* VEX_W_3A0C_P_2 */
10004     { "vblendps",       { XM, Vex, EXx, Ib } },
10005   },
10006   {
10007     /* VEX_W_3A0D_P_2 */
10008     { "vblendpd",       { XM, Vex, EXx, Ib } },
10009   },
10010   {
10011     /* VEX_W_3A0E_P_2 */
10012     { "vpblendw",       { XM, Vex128, EXx, Ib } },
10013   },
10014   {
10015     /* VEX_W_3A0F_P_2 */
10016     { "vpalignr",       { XM, Vex128, EXx, Ib } },
10017   },
10018   {
10019     /* VEX_W_3A14_P_2 */
10020     { "vpextrb",        { Edqb, XM, Ib } },
10021   },
10022   {
10023     /* VEX_W_3A15_P_2 */
10024     { "vpextrw",        { Edqw, XM, Ib } },
10025   },
10026   {
10027     /* VEX_W_3A18_P_2 */
10028     { "vinsertf128",    { XM, Vex256, EXxmm, Ib } },
10029   },
10030   {
10031     /* VEX_W_3A19_P_2 */
10032     { "vextractf128",   { EXxmm, XM, Ib } },
10033   },
10034   {
10035     /* VEX_W_3A20_P_2 */
10036     { "vpinsrb",        { XM, Vex128, Edqb, Ib } },
10037   },
10038   {
10039     /* VEX_W_3A21_P_2 */
10040     { "vinsertps",      { XM, Vex128, EXd, Ib } },
10041   },
10042   {
10043     /* VEX_W_3A40_P_2 */
10044     { "vdpps",          { XM, Vex, EXx, Ib } },
10045   },
10046   {
10047     /* VEX_W_3A41_P_2 */
10048     { "vdppd",          { XM, Vex128, EXx, Ib } },
10049   },
10050   {
10051     /* VEX_W_3A42_P_2 */
10052     { "vmpsadbw",       { XM, Vex128, EXx, Ib } },
10053   },
10054   {
10055     /* VEX_W_3A44_P_2 */
10056     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL } },
10057   },
10058   {
10059     /* VEX_W_3A4A_P_2 */
10060     { "vblendvps",      { XM, Vex, EXx, XMVexI4 } },
10061   },
10062   {
10063     /* VEX_W_3A4B_P_2 */
10064     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 } },
10065   },
10066   {
10067     /* VEX_W_3A4C_P_2 */
10068     { "vpblendvb",      { XM, Vex128, EXx, XMVexI4 } },
10069   },
10070   {
10071     /* VEX_W_3A60_P_2 */
10072     { "vpcmpestrm",     { XM, EXx, Ib } },
10073   },
10074   {
10075     /* VEX_W_3A61_P_2 */
10076     { "vpcmpestri",     { XM, EXx, Ib } },
10077   },
10078   {
10079     /* VEX_W_3A62_P_2 */
10080     { "vpcmpistrm",     { XM, EXx, Ib } },
10081   },
10082   {
10083     /* VEX_W_3A63_P_2 */
10084     { "vpcmpistri",     { XM, EXx, Ib } },
10085   },
10086   {
10087     /* VEX_W_3ADF_P_2 */
10088     { "vaeskeygenassist", { XM, EXx, Ib } },
10089   },
10090 };
10091
10092 static const struct dis386 mod_table[][2] = {
10093   {
10094     /* MOD_8D */
10095     { "leaS",           { Gv, M } },
10096   },
10097   {
10098     /* MOD_0F01_REG_0 */
10099     { X86_64_TABLE (X86_64_0F01_REG_0) },
10100     { RM_TABLE (RM_0F01_REG_0) },
10101   },
10102   {
10103     /* MOD_0F01_REG_1 */
10104     { X86_64_TABLE (X86_64_0F01_REG_1) },
10105     { RM_TABLE (RM_0F01_REG_1) },
10106   },
10107   {
10108     /* MOD_0F01_REG_2 */
10109     { X86_64_TABLE (X86_64_0F01_REG_2) },
10110     { RM_TABLE (RM_0F01_REG_2) },
10111   },
10112   {
10113     /* MOD_0F01_REG_3 */
10114     { X86_64_TABLE (X86_64_0F01_REG_3) },
10115     { RM_TABLE (RM_0F01_REG_3) },
10116   },
10117   {
10118     /* MOD_0F01_REG_7 */
10119     { "invlpg",         { Mb } },
10120     { RM_TABLE (RM_0F01_REG_7) },
10121   },
10122   {
10123     /* MOD_0F12_PREFIX_0 */
10124     { "movlps",         { XM, EXq } },
10125     { "movhlps",        { XM, EXq } },
10126   },
10127   {
10128     /* MOD_0F13 */
10129     { "movlpX",         { EXq, XM } },
10130   },
10131   {
10132     /* MOD_0F16_PREFIX_0 */
10133     { "movhps",         { XM, EXq } },
10134     { "movlhps",        { XM, EXq } },
10135   },
10136   {
10137     /* MOD_0F17 */
10138     { "movhpX",         { EXq, XM } },
10139   },
10140   {
10141     /* MOD_0F18_REG_0 */
10142     { "prefetchnta",    { Mb } },
10143   },
10144   {
10145     /* MOD_0F18_REG_1 */
10146     { "prefetcht0",     { Mb } },
10147   },
10148   {
10149     /* MOD_0F18_REG_2 */
10150     { "prefetcht1",     { Mb } },
10151   },
10152   {
10153     /* MOD_0F18_REG_3 */
10154     { "prefetcht2",     { Mb } },
10155   },
10156   {
10157     /* MOD_0F20 */
10158     { Bad_Opcode },
10159     { "movZ",           { Rm, Cm } },
10160   },
10161   {
10162     /* MOD_0F21 */
10163     { Bad_Opcode },
10164     { "movZ",           { Rm, Dm } },
10165   },
10166   {
10167     /* MOD_0F22 */
10168     { Bad_Opcode },
10169     { "movZ",           { Cm, Rm } },
10170   },
10171   {
10172     /* MOD_0F23 */
10173     { Bad_Opcode },
10174     { "movZ",           { Dm, Rm } },
10175   },
10176   {
10177     /* MOD_0F24 */
10178     { Bad_Opcode },
10179     { "movL",           { Rd, Td } },
10180   },
10181   {
10182     /* MOD_0F26 */
10183     { Bad_Opcode },
10184     { "movL",           { Td, Rd } },
10185   },
10186   {
10187     /* MOD_0F2B_PREFIX_0 */
10188     {"movntps",         { Mx, XM } },
10189   },
10190   {
10191     /* MOD_0F2B_PREFIX_1 */
10192     {"movntss",         { Md, XM } },
10193   },
10194   {
10195     /* MOD_0F2B_PREFIX_2 */
10196     {"movntpd",         { Mx, XM } },
10197   },
10198   {
10199     /* MOD_0F2B_PREFIX_3 */
10200     {"movntsd",         { Mq, XM } },
10201   },
10202   {
10203     /* MOD_0F51 */
10204     { Bad_Opcode },
10205     { "movmskpX",       { Gdq, XS } },
10206   },
10207   {
10208     /* MOD_0F71_REG_2 */
10209     { Bad_Opcode },
10210     { "psrlw",          { MS, Ib } },
10211   },
10212   {
10213     /* MOD_0F71_REG_4 */
10214     { Bad_Opcode },
10215     { "psraw",          { MS, Ib } },
10216   },
10217   {
10218     /* MOD_0F71_REG_6 */
10219     { Bad_Opcode },
10220     { "psllw",          { MS, Ib } },
10221   },
10222   {
10223     /* MOD_0F72_REG_2 */
10224     { Bad_Opcode },
10225     { "psrld",          { MS, Ib } },
10226   },
10227   {
10228     /* MOD_0F72_REG_4 */
10229     { Bad_Opcode },
10230     { "psrad",          { MS, Ib } },
10231   },
10232   {
10233     /* MOD_0F72_REG_6 */
10234     { Bad_Opcode },
10235     { "pslld",          { MS, Ib } },
10236   },
10237   {
10238     /* MOD_0F73_REG_2 */
10239     { Bad_Opcode },
10240     { "psrlq",          { MS, Ib } },
10241   },
10242   {
10243     /* MOD_0F73_REG_3 */
10244     { Bad_Opcode },
10245     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10246   },
10247   {
10248     /* MOD_0F73_REG_6 */
10249     { Bad_Opcode },
10250     { "psllq",          { MS, Ib } },
10251   },
10252   {
10253     /* MOD_0F73_REG_7 */
10254     { Bad_Opcode },
10255     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10256   },
10257   {
10258     /* MOD_0FAE_REG_0 */
10259     { "fxsave",         { FXSAVE } },
10260   },
10261   {
10262     /* MOD_0FAE_REG_1 */
10263     { "fxrstor",        { FXSAVE } },
10264   },
10265   {
10266     /* MOD_0FAE_REG_2 */
10267     { "ldmxcsr",        { Md } },
10268   },
10269   {
10270     /* MOD_0FAE_REG_3 */
10271     { "stmxcsr",        { Md } },
10272   },
10273   {
10274     /* MOD_0FAE_REG_4 */
10275     { "xsave",          { FXSAVE } },
10276   },
10277   {
10278     /* MOD_0FAE_REG_5 */
10279     { "xrstor",         { FXSAVE } },
10280     { RM_TABLE (RM_0FAE_REG_5) },
10281   },
10282   {
10283     /* MOD_0FAE_REG_6 */
10284     { Bad_Opcode },
10285     { RM_TABLE (RM_0FAE_REG_6) },
10286   },
10287   {
10288     /* MOD_0FAE_REG_7 */
10289     { "clflush",        { Mb } },
10290     { RM_TABLE (RM_0FAE_REG_7) },
10291   },
10292   {
10293     /* MOD_0FB2 */
10294     { "lssS",           { Gv, Mp } },
10295   },
10296   {
10297     /* MOD_0FB4 */
10298     { "lfsS",           { Gv, Mp } },
10299   },
10300   {
10301     /* MOD_0FB5 */
10302     { "lgsS",           { Gv, Mp } },
10303   },
10304   {
10305     /* MOD_0FC7_REG_6 */
10306     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10307   },
10308   {
10309     /* MOD_0FC7_REG_7 */
10310     { "vmptrst",        { Mq } },
10311   },
10312   {
10313     /* MOD_0FD7 */
10314     { Bad_Opcode },
10315     { "pmovmskb",       { Gdq, MS } },
10316   },
10317   {
10318     /* MOD_0FE7_PREFIX_2 */
10319     { "movntdq",        { Mx, XM } },
10320   },
10321   {
10322     /* MOD_0FF0_PREFIX_3 */
10323     { "lddqu",          { XM, M } },
10324   },
10325   {
10326     /* MOD_0F382A_PREFIX_2 */
10327     { "movntdqa",       { XM, Mx } },
10328   },
10329   {
10330     /* MOD_62_32BIT */
10331     { "bound{S|}",      { Gv, Ma } },
10332   },
10333   {
10334     /* MOD_C4_32BIT */
10335     { "lesS",           { Gv, Mp } },
10336     { VEX_C4_TABLE (VEX_0F) },
10337   },
10338   {
10339     /* MOD_C5_32BIT */
10340     { "ldsS",           { Gv, Mp } },
10341     { VEX_C5_TABLE (VEX_0F) },
10342   },
10343   {
10344     /* MOD_VEX_12_PREFIX_0 */
10345     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
10346     { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
10347   },
10348   {
10349     /* MOD_VEX_13 */
10350     { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
10351   },
10352   {
10353     /* MOD_VEX_16_PREFIX_0 */
10354     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
10355     { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
10356   },
10357   {
10358     /* MOD_VEX_17 */
10359     { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
10360   },
10361   {
10362     /* MOD_VEX_2B */
10363     { VEX_W_TABLE (VEX_W_2B_M_0) },
10364   },
10365   {
10366     /* MOD_VEX_50 */
10367     { Bad_Opcode },
10368     { VEX_W_TABLE (VEX_W_50_M_0) },
10369   },
10370   {
10371     /* MOD_VEX_71_REG_2 */
10372     { Bad_Opcode },
10373     { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
10374   },
10375   {
10376     /* MOD_VEX_71_REG_4 */
10377     { Bad_Opcode },
10378     { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
10379   },
10380   {
10381     /* MOD_VEX_71_REG_6 */
10382     { Bad_Opcode },
10383     { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
10384   },
10385   {
10386     /* MOD_VEX_72_REG_2 */
10387     { Bad_Opcode },
10388     { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
10389   },
10390   {
10391     /* MOD_VEX_72_REG_4 */
10392     { Bad_Opcode },
10393     { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
10394   },
10395   {
10396     /* MOD_VEX_72_REG_6 */
10397     { Bad_Opcode },
10398     { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
10399   },
10400   {
10401     /* MOD_VEX_73_REG_2 */
10402     { Bad_Opcode },
10403     { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
10404   },
10405   {
10406     /* MOD_VEX_73_REG_3 */
10407     { Bad_Opcode },
10408     { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
10409   },
10410   {
10411     /* MOD_VEX_73_REG_6 */
10412     { Bad_Opcode },
10413     { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
10414   },
10415   {
10416     /* MOD_VEX_73_REG_7 */
10417     { Bad_Opcode },
10418     { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
10419   },
10420   {
10421     /* MOD_VEX_AE_REG_2 */
10422     { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
10423   },
10424   {
10425     /* MOD_VEX_AE_REG_3 */
10426     { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
10427   },
10428   {
10429     /* MOD_VEX_D7_PREFIX_2 */
10430     { Bad_Opcode },
10431     { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
10432   },
10433   {
10434     /* MOD_VEX_E7_PREFIX_2 */
10435     { VEX_W_TABLE (VEX_W_E7_P_2_M_0) },
10436   },
10437   {
10438     /* MOD_VEX_F0_PREFIX_3 */
10439     { VEX_W_TABLE (VEX_W_F0_P_3_M_0) },
10440   },
10441   {
10442     /* MOD_VEX_3818_PREFIX_2 */
10443     { VEX_W_TABLE (VEX_W_3818_P_2_M_0) },
10444   },
10445   {
10446     /* MOD_VEX_3819_PREFIX_2 */
10447     { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
10448   },
10449   {
10450     /* MOD_VEX_381A_PREFIX_2 */
10451     { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
10452   },
10453   {
10454     /* MOD_VEX_382A_PREFIX_2 */
10455     { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
10456   },
10457   {
10458     /* MOD_VEX_382C_PREFIX_2 */
10459     { VEX_W_TABLE (VEX_W_382C_P_2_M_0) },
10460   },
10461   {
10462     /* MOD_VEX_382D_PREFIX_2 */
10463     { VEX_W_TABLE (VEX_W_382D_P_2_M_0) },
10464   },
10465   {
10466     /* MOD_VEX_382E_PREFIX_2 */
10467     { VEX_W_TABLE (VEX_W_382E_P_2_M_0) },
10468   },
10469   {
10470     /* MOD_VEX_382F_PREFIX_2 */
10471     { VEX_W_TABLE (VEX_W_382F_P_2_M_0) },
10472   },
10473 };
10474
10475 static const struct dis386 rm_table[][8] = {
10476   {
10477     /* RM_0F01_REG_0 */
10478     { Bad_Opcode },
10479     { "vmcall",         { Skip_MODRM } },
10480     { "vmlaunch",       { Skip_MODRM } },
10481     { "vmresume",       { Skip_MODRM } },
10482     { "vmxoff",         { Skip_MODRM } },
10483   },
10484   {
10485     /* RM_0F01_REG_1 */
10486     { "monitor",        { { OP_Monitor, 0 } } },
10487     { "mwait",          { { OP_Mwait, 0 } } },
10488   },
10489   {
10490     /* RM_0F01_REG_2 */
10491     { "xgetbv",         { Skip_MODRM } },
10492     { "xsetbv",         { Skip_MODRM } },
10493   },
10494   {
10495     /* RM_0F01_REG_3 */
10496     { "vmrun",          { Skip_MODRM } },
10497     { "vmmcall",        { Skip_MODRM } },
10498     { "vmload",         { Skip_MODRM } },
10499     { "vmsave",         { Skip_MODRM } },
10500     { "stgi",           { Skip_MODRM } },
10501     { "clgi",           { Skip_MODRM } },
10502     { "skinit",         { Skip_MODRM } },
10503     { "invlpga",        { Skip_MODRM } },
10504   },
10505   {
10506     /* RM_0F01_REG_7 */
10507     { "swapgs",         { Skip_MODRM } },
10508     { "rdtscp",         { Skip_MODRM } },
10509   },
10510   {
10511     /* RM_0FAE_REG_5 */
10512     { "lfence",         { Skip_MODRM } },
10513   },
10514   {
10515     /* RM_0FAE_REG_6 */
10516     { "mfence",         { Skip_MODRM } },
10517   },
10518   {
10519     /* RM_0FAE_REG_7 */
10520     { "sfence",         { Skip_MODRM } },
10521   },
10522 };
10523
10524 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10525
10526 /* We use the high bit to indicate different name for the same
10527    prefix.  */
10528 #define ADDR16_PREFIX   (0x67 | 0x100)
10529 #define ADDR32_PREFIX   (0x67 | 0x200)
10530 #define DATA16_PREFIX   (0x66 | 0x100)
10531 #define DATA32_PREFIX   (0x66 | 0x200)
10532 #define REP_PREFIX      (0xf3 | 0x100)
10533
10534 static int
10535 ckprefix (void)
10536 {
10537   int newrex, i, length;
10538   rex = 0;
10539   rex_ignored = 0;
10540   prefixes = 0;
10541   used_prefixes = 0;
10542   rex_used = 0;
10543   last_lock_prefix = -1;
10544   last_repz_prefix = -1;
10545   last_repnz_prefix = -1;
10546   last_data_prefix = -1;
10547   last_addr_prefix = -1;
10548   last_rex_prefix = -1;
10549   last_seg_prefix = -1;
10550   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10551     all_prefixes[i] = 0;
10552   i = 0;
10553   length = 0;
10554   /* The maximum instruction length is 15bytes.  */
10555   while (length < MAX_CODE_LENGTH - 1)
10556     {
10557       FETCH_DATA (the_info, codep + 1);
10558       newrex = 0;
10559       switch (*codep)
10560         {
10561         /* REX prefixes family.  */
10562         case 0x40:
10563         case 0x41:
10564         case 0x42:
10565         case 0x43:
10566         case 0x44:
10567         case 0x45:
10568         case 0x46:
10569         case 0x47:
10570         case 0x48:
10571         case 0x49:
10572         case 0x4a:
10573         case 0x4b:
10574         case 0x4c:
10575         case 0x4d:
10576         case 0x4e:
10577         case 0x4f:
10578           if (address_mode == mode_64bit)
10579             newrex = *codep;
10580           else
10581             return 1;
10582           last_rex_prefix = i;
10583           break;
10584         case 0xf3:
10585           prefixes |= PREFIX_REPZ;
10586           last_repz_prefix = i;
10587           break;
10588         case 0xf2:
10589           prefixes |= PREFIX_REPNZ;
10590           last_repnz_prefix = i;
10591           break;
10592         case 0xf0:
10593           prefixes |= PREFIX_LOCK;
10594           last_lock_prefix = i;
10595           break;
10596         case 0x2e:
10597           prefixes |= PREFIX_CS;
10598           last_seg_prefix = i;
10599           break;
10600         case 0x36:
10601           prefixes |= PREFIX_SS;
10602           last_seg_prefix = i;
10603           break;
10604         case 0x3e:
10605           prefixes |= PREFIX_DS;
10606           last_seg_prefix = i;
10607           break;
10608         case 0x26:
10609           prefixes |= PREFIX_ES;
10610           last_seg_prefix = i;
10611           break;
10612         case 0x64:
10613           prefixes |= PREFIX_FS;
10614           last_seg_prefix = i;
10615           break;
10616         case 0x65:
10617           prefixes |= PREFIX_GS;
10618           last_seg_prefix = i;
10619           break;
10620         case 0x66:
10621           prefixes |= PREFIX_DATA;
10622           last_data_prefix = i;
10623           break;
10624         case 0x67:
10625           prefixes |= PREFIX_ADDR;
10626           last_addr_prefix = i;
10627           break;
10628         case FWAIT_OPCODE:
10629           /* fwait is really an instruction.  If there are prefixes
10630              before the fwait, they belong to the fwait, *not* to the
10631              following instruction.  */
10632           if (prefixes || rex)
10633             {
10634               prefixes |= PREFIX_FWAIT;
10635               codep++;
10636               return 1;
10637             }
10638           prefixes = PREFIX_FWAIT;
10639           break;
10640         default:
10641           return 1;
10642         }
10643       /* Rex is ignored when followed by another prefix.  */
10644       if (rex)
10645         {
10646           rex_used = rex;
10647           return 1;
10648         }
10649       if (*codep != FWAIT_OPCODE)
10650         all_prefixes[i++] = *codep;
10651       rex = newrex;
10652       codep++;
10653       length++;
10654     }
10655   return 0;
10656 }
10657
10658 static int
10659 seg_prefix (int pref)
10660 {
10661   switch (pref)
10662     {
10663     case 0x2e:
10664       return PREFIX_CS;
10665     case 0x36:
10666       return PREFIX_SS;
10667     case 0x3e:
10668       return PREFIX_DS;
10669     case 0x26:
10670       return PREFIX_ES;
10671     case 0x64:
10672       return PREFIX_FS;
10673     case 0x65:
10674       return PREFIX_GS;
10675     default:
10676       return 0;
10677     }
10678 }
10679
10680 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10681    prefix byte.  */
10682
10683 static const char *
10684 prefix_name (int pref, int sizeflag)
10685 {
10686   static const char *rexes [16] =
10687     {
10688       "rex",            /* 0x40 */
10689       "rex.B",          /* 0x41 */
10690       "rex.X",          /* 0x42 */
10691       "rex.XB",         /* 0x43 */
10692       "rex.R",          /* 0x44 */
10693       "rex.RB",         /* 0x45 */
10694       "rex.RX",         /* 0x46 */
10695       "rex.RXB",        /* 0x47 */
10696       "rex.W",          /* 0x48 */
10697       "rex.WB",         /* 0x49 */
10698       "rex.WX",         /* 0x4a */
10699       "rex.WXB",        /* 0x4b */
10700       "rex.WR",         /* 0x4c */
10701       "rex.WRB",        /* 0x4d */
10702       "rex.WRX",        /* 0x4e */
10703       "rex.WRXB",       /* 0x4f */
10704     };
10705
10706   switch (pref)
10707     {
10708     /* REX prefixes family.  */
10709     case 0x40:
10710     case 0x41:
10711     case 0x42:
10712     case 0x43:
10713     case 0x44:
10714     case 0x45:
10715     case 0x46:
10716     case 0x47:
10717     case 0x48:
10718     case 0x49:
10719     case 0x4a:
10720     case 0x4b:
10721     case 0x4c:
10722     case 0x4d:
10723     case 0x4e:
10724     case 0x4f:
10725       return rexes [pref - 0x40];
10726     case 0xf3:
10727       return "repz";
10728     case 0xf2:
10729       return "repnz";
10730     case 0xf0:
10731       return "lock";
10732     case 0x2e:
10733       return "cs";
10734     case 0x36:
10735       return "ss";
10736     case 0x3e:
10737       return "ds";
10738     case 0x26:
10739       return "es";
10740     case 0x64:
10741       return "fs";
10742     case 0x65:
10743       return "gs";
10744     case 0x66:
10745       return (sizeflag & DFLAG) ? "data16" : "data32";
10746     case 0x67:
10747       if (address_mode == mode_64bit)
10748         return (sizeflag & AFLAG) ? "addr32" : "addr64";
10749       else
10750         return (sizeflag & AFLAG) ? "addr16" : "addr32";
10751     case FWAIT_OPCODE:
10752       return "fwait";
10753     case ADDR16_PREFIX:
10754       return "addr16";
10755     case ADDR32_PREFIX:
10756       return "addr32";
10757     case DATA16_PREFIX:
10758       return "data16";
10759     case DATA32_PREFIX:
10760       return "data32";
10761     case REP_PREFIX:
10762       return "rep";
10763     default:
10764       return NULL;
10765     }
10766 }
10767
10768 static char op_out[MAX_OPERANDS][100];
10769 static int op_ad, op_index[MAX_OPERANDS];
10770 static int two_source_ops;
10771 static bfd_vma op_address[MAX_OPERANDS];
10772 static bfd_vma op_riprel[MAX_OPERANDS];
10773 static bfd_vma start_pc;
10774
10775 /*
10776  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10777  *   (see topic "Redundant prefixes" in the "Differences from 8086"
10778  *   section of the "Virtual 8086 Mode" chapter.)
10779  * 'pc' should be the address of this instruction, it will
10780  *   be used to print the target address if this is a relative jump or call
10781  * The function returns the length of this instruction in bytes.
10782  */
10783
10784 static char intel_syntax;
10785 static char intel_mnemonic = !SYSV386_COMPAT;
10786 static char open_char;
10787 static char close_char;
10788 static char separator_char;
10789 static char scale_char;
10790
10791 /* Here for backwards compatibility.  When gdb stops using
10792    print_insn_i386_att and print_insn_i386_intel these functions can
10793    disappear, and print_insn_i386 be merged into print_insn.  */
10794 int
10795 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10796 {
10797   intel_syntax = 0;
10798
10799   return print_insn (pc, info);
10800 }
10801
10802 int
10803 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10804 {
10805   intel_syntax = 1;
10806
10807   return print_insn (pc, info);
10808 }
10809
10810 int
10811 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10812 {
10813   intel_syntax = -1;
10814
10815   return print_insn (pc, info);
10816 }
10817
10818 void
10819 print_i386_disassembler_options (FILE *stream)
10820 {
10821   fprintf (stream, _("\n\
10822 The following i386/x86-64 specific disassembler options are supported for use\n\
10823 with the -M switch (multiple options should be separated by commas):\n"));
10824
10825   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
10826   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
10827   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
10828   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
10829   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
10830   fprintf (stream, _("  att-mnemonic\n"
10831                      "              Display instruction in AT&T mnemonic\n"));
10832   fprintf (stream, _("  intel-mnemonic\n"
10833                      "              Display instruction in Intel mnemonic\n"));
10834   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
10835   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
10836   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
10837   fprintf (stream, _("  data32      Assume 32bit data size\n"));
10838   fprintf (stream, _("  data16      Assume 16bit data size\n"));
10839   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
10840 }
10841
10842 /* Bad opcode.  */
10843 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10844
10845 /* Get a pointer to struct dis386 with a valid name.  */
10846
10847 static const struct dis386 *
10848 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10849 {
10850   int vindex, vex_table_index;
10851
10852   if (dp->name != NULL)
10853     return dp;
10854
10855   switch (dp->op[0].bytemode)
10856     {
10857     case USE_REG_TABLE:
10858       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
10859       break;
10860
10861     case USE_MOD_TABLE:
10862       vindex = modrm.mod == 0x3 ? 1 : 0;
10863       dp = &mod_table[dp->op[1].bytemode][vindex];
10864       break;
10865
10866     case USE_RM_TABLE:
10867       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10868       break;
10869
10870     case USE_PREFIX_TABLE:
10871       if (need_vex)
10872         {
10873           /* The prefix in VEX is implicit.  */
10874           switch (vex.prefix)
10875             {
10876             case 0:
10877               vindex = 0;
10878               break;
10879             case REPE_PREFIX_OPCODE:
10880               vindex = 1;
10881               break;
10882             case DATA_PREFIX_OPCODE:
10883               vindex = 2;
10884               break;
10885             case REPNE_PREFIX_OPCODE:
10886               vindex = 3;
10887               break;
10888             default:
10889               abort ();
10890               break;
10891             }
10892         }
10893       else
10894         {
10895           vindex = 0;
10896           used_prefixes |= (prefixes & PREFIX_REPZ);
10897           if (prefixes & PREFIX_REPZ)
10898             {
10899               vindex = 1;
10900               all_prefixes[last_repz_prefix] = 0;
10901             }
10902           else
10903             {
10904               /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10905                  PREFIX_DATA.  */
10906               used_prefixes |= (prefixes & PREFIX_REPNZ);
10907               if (prefixes & PREFIX_REPNZ)
10908                 {
10909                   vindex = 3;
10910                   all_prefixes[last_repnz_prefix] = 0;
10911                 }
10912               else
10913                 {
10914                   used_prefixes |= (prefixes & PREFIX_DATA);
10915                   if (prefixes & PREFIX_DATA)
10916                     {
10917                       vindex = 2;
10918                       all_prefixes[last_data_prefix] = 0;
10919                     }
10920                 }
10921             }
10922         }
10923       dp = &prefix_table[dp->op[1].bytemode][vindex];
10924       break;
10925
10926     case USE_X86_64_TABLE:
10927       vindex = address_mode == mode_64bit ? 1 : 0;
10928       dp = &x86_64_table[dp->op[1].bytemode][vindex];
10929       break;
10930
10931     case USE_3BYTE_TABLE:
10932       FETCH_DATA (info, codep + 2);
10933       vindex = *codep++;
10934       dp = &three_byte_table[dp->op[1].bytemode][vindex];
10935       modrm.mod = (*codep >> 6) & 3;
10936       modrm.reg = (*codep >> 3) & 7;
10937       modrm.rm = *codep & 7;
10938       break;
10939
10940     case USE_VEX_LEN_TABLE:
10941       if (!need_vex)
10942         abort ();
10943
10944       switch (vex.length)
10945         {
10946         case 128:
10947           vindex = 0;
10948           break;
10949         case 256:
10950           vindex = 1;
10951           break;
10952         default:
10953           abort ();
10954           break;
10955         }
10956
10957       dp = &vex_len_table[dp->op[1].bytemode][vindex];
10958       break;
10959
10960     case USE_XOP_8F_TABLE:
10961       FETCH_DATA (info, codep + 3);
10962       /* All bits in the REX prefix are ignored.  */
10963       rex_ignored = rex;
10964       rex = ~(*codep >> 5) & 0x7;
10965
10966       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
10967       switch ((*codep & 0x1f))
10968         {
10969         default:
10970           BadOp ();
10971         case 0x8:
10972           vex_table_index = XOP_08;
10973           break;
10974         case 0x9:
10975           vex_table_index = XOP_09;
10976           break;
10977         case 0xa:
10978           vex_table_index = XOP_0A;
10979           break;
10980         }
10981       codep++;
10982       vex.w = *codep & 0x80;
10983       if (vex.w && address_mode == mode_64bit)
10984         rex |= REX_W;
10985
10986       vex.register_specifier = (~(*codep >> 3)) & 0xf;
10987       if (address_mode != mode_64bit
10988           && vex.register_specifier > 0x7)
10989         BadOp ();
10990
10991       vex.length = (*codep & 0x4) ? 256 : 128;
10992       switch ((*codep & 0x3))
10993         {
10994         case 0:
10995           vex.prefix = 0;
10996           break;
10997         case 1:
10998           vex.prefix = DATA_PREFIX_OPCODE;
10999           break;
11000         case 2:
11001           vex.prefix = REPE_PREFIX_OPCODE;
11002           break;
11003         case 3:
11004           vex.prefix = REPNE_PREFIX_OPCODE;
11005           break;
11006         }
11007       need_vex = 1;
11008       need_vex_reg = 1;
11009       codep++;
11010       vindex = *codep++;
11011       dp = &xop_table[vex_table_index][vindex];
11012
11013       FETCH_DATA (info, codep + 1);
11014       modrm.mod = (*codep >> 6) & 3;
11015       modrm.reg = (*codep >> 3) & 7;
11016       modrm.rm = *codep & 7;
11017       break;
11018
11019     case USE_VEX_C4_TABLE:
11020       FETCH_DATA (info, codep + 3);
11021       /* All bits in the REX prefix are ignored.  */
11022       rex_ignored = rex;
11023       rex = ~(*codep >> 5) & 0x7;
11024       switch ((*codep & 0x1f))
11025         {
11026         default:
11027           BadOp ();
11028         case 0x1:
11029           vex_table_index = VEX_0F;
11030           break;
11031         case 0x2:
11032           vex_table_index = VEX_0F38;
11033           break;
11034         case 0x3:
11035           vex_table_index = VEX_0F3A;
11036           break;
11037         }
11038       codep++;
11039       vex.w = *codep & 0x80;
11040       if (vex.w && address_mode == mode_64bit)
11041         rex |= REX_W;
11042
11043       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11044       if (address_mode != mode_64bit
11045           && vex.register_specifier > 0x7)
11046         BadOp ();
11047
11048       vex.length = (*codep & 0x4) ? 256 : 128;
11049       switch ((*codep & 0x3))
11050         {
11051         case 0:
11052           vex.prefix = 0;
11053           break;
11054         case 1:
11055           vex.prefix = DATA_PREFIX_OPCODE;
11056           break;
11057         case 2:
11058           vex.prefix = REPE_PREFIX_OPCODE;
11059           break;
11060         case 3:
11061           vex.prefix = REPNE_PREFIX_OPCODE;
11062           break;
11063         }
11064       need_vex = 1;
11065       need_vex_reg = 1;
11066       codep++;
11067       vindex = *codep++;
11068       dp = &vex_table[vex_table_index][vindex];
11069       /* There is no MODRM byte for VEX [82|77].  */
11070       if (vindex != 0x77 && vindex != 0x82)
11071         {
11072           FETCH_DATA (info, codep + 1);
11073           modrm.mod = (*codep >> 6) & 3;
11074           modrm.reg = (*codep >> 3) & 7;
11075           modrm.rm = *codep & 7;
11076         }
11077       break;
11078
11079     case USE_VEX_C5_TABLE:
11080       FETCH_DATA (info, codep + 2);
11081       /* All bits in the REX prefix are ignored.  */
11082       rex_ignored = rex;
11083       rex = (*codep & 0x80) ? 0 : REX_R;
11084
11085       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11086       if (address_mode != mode_64bit
11087           && vex.register_specifier > 0x7)
11088         BadOp ();
11089
11090       vex.w = 0;
11091
11092       vex.length = (*codep & 0x4) ? 256 : 128;
11093       switch ((*codep & 0x3))
11094         {
11095         case 0:
11096           vex.prefix = 0;
11097           break;
11098         case 1:
11099           vex.prefix = DATA_PREFIX_OPCODE;
11100           break;
11101         case 2:
11102           vex.prefix = REPE_PREFIX_OPCODE;
11103           break;
11104         case 3:
11105           vex.prefix = REPNE_PREFIX_OPCODE;
11106           break;
11107         }
11108       need_vex = 1;
11109       need_vex_reg = 1;
11110       codep++;
11111       vindex = *codep++;
11112       dp = &vex_table[dp->op[1].bytemode][vindex];
11113       /* There is no MODRM byte for VEX [82|77].  */
11114       if (vindex != 0x77 && vindex != 0x82)
11115         {
11116           FETCH_DATA (info, codep + 1);
11117           modrm.mod = (*codep >> 6) & 3;
11118           modrm.reg = (*codep >> 3) & 7;
11119           modrm.rm = *codep & 7;
11120         }
11121       break;
11122
11123     case USE_VEX_W_TABLE:
11124       if (!need_vex)
11125         abort ();
11126
11127       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11128       break;
11129
11130     case 0:
11131       dp = &bad_opcode;
11132       break;
11133
11134     default:
11135       abort ();
11136     }
11137
11138   if (dp->name != NULL)
11139     return dp;
11140   else
11141     return get_valid_dis386 (dp, info);
11142 }
11143
11144 static int
11145 print_insn (bfd_vma pc, disassemble_info *info)
11146 {
11147   const struct dis386 *dp;
11148   int i;
11149   char *op_txt[MAX_OPERANDS];
11150   int needcomma;
11151   int sizeflag;
11152   const char *p;
11153   struct dis_private priv;
11154   unsigned char op;
11155   int prefix_length;
11156   int default_prefixes;
11157
11158   if (info->mach == bfd_mach_x86_64_intel_syntax
11159       || info->mach == bfd_mach_x86_64
11160       || info->mach == bfd_mach_l1om
11161       || info->mach == bfd_mach_l1om_intel_syntax)
11162     address_mode = mode_64bit;
11163   else
11164     address_mode = mode_32bit;
11165
11166   if (intel_syntax == (char) -1)
11167     intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
11168                     || info->mach == bfd_mach_x86_64_intel_syntax
11169                     || info->mach == bfd_mach_l1om_intel_syntax);
11170
11171   if (info->mach == bfd_mach_i386_i386
11172       || info->mach == bfd_mach_x86_64
11173       || info->mach == bfd_mach_l1om
11174       || info->mach == bfd_mach_i386_i386_intel_syntax
11175       || info->mach == bfd_mach_x86_64_intel_syntax
11176       || info->mach == bfd_mach_l1om_intel_syntax)
11177     priv.orig_sizeflag = AFLAG | DFLAG;
11178   else if (info->mach == bfd_mach_i386_i8086)
11179     priv.orig_sizeflag = 0;
11180   else
11181     abort ();
11182
11183   for (p = info->disassembler_options; p != NULL; )
11184     {
11185       if (CONST_STRNEQ (p, "x86-64"))
11186         {
11187           address_mode = mode_64bit;
11188           priv.orig_sizeflag = AFLAG | DFLAG;
11189         }
11190       else if (CONST_STRNEQ (p, "i386"))
11191         {
11192           address_mode = mode_32bit;
11193           priv.orig_sizeflag = AFLAG | DFLAG;
11194         }
11195       else if (CONST_STRNEQ (p, "i8086"))
11196         {
11197           address_mode = mode_16bit;
11198           priv.orig_sizeflag = 0;
11199         }
11200       else if (CONST_STRNEQ (p, "intel"))
11201         {
11202           intel_syntax = 1;
11203           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11204             intel_mnemonic = 1;
11205         }
11206       else if (CONST_STRNEQ (p, "att"))
11207         {
11208           intel_syntax = 0;
11209           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11210             intel_mnemonic = 0;
11211         }
11212       else if (CONST_STRNEQ (p, "addr"))
11213         {
11214           if (address_mode == mode_64bit)
11215             {
11216               if (p[4] == '3' && p[5] == '2')
11217                 priv.orig_sizeflag &= ~AFLAG;
11218               else if (p[4] == '6' && p[5] == '4')
11219                 priv.orig_sizeflag |= AFLAG;
11220             }
11221           else
11222             {
11223               if (p[4] == '1' && p[5] == '6')
11224                 priv.orig_sizeflag &= ~AFLAG;
11225               else if (p[4] == '3' && p[5] == '2')
11226                 priv.orig_sizeflag |= AFLAG;
11227             }
11228         }
11229       else if (CONST_STRNEQ (p, "data"))
11230         {
11231           if (p[4] == '1' && p[5] == '6')
11232             priv.orig_sizeflag &= ~DFLAG;
11233           else if (p[4] == '3' && p[5] == '2')
11234             priv.orig_sizeflag |= DFLAG;
11235         }
11236       else if (CONST_STRNEQ (p, "suffix"))
11237         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11238
11239       p = strchr (p, ',');
11240       if (p != NULL)
11241         p++;
11242     }
11243
11244   if (intel_syntax)
11245     {
11246       names64 = intel_names64;
11247       names32 = intel_names32;
11248       names16 = intel_names16;
11249       names8 = intel_names8;
11250       names8rex = intel_names8rex;
11251       names_seg = intel_names_seg;
11252       names_mm = intel_names_mm;
11253       names_xmm = intel_names_xmm;
11254       names_ymm = intel_names_ymm;
11255       index64 = intel_index64;
11256       index32 = intel_index32;
11257       index16 = intel_index16;
11258       open_char = '[';
11259       close_char = ']';
11260       separator_char = '+';
11261       scale_char = '*';
11262     }
11263   else
11264     {
11265       names64 = att_names64;
11266       names32 = att_names32;
11267       names16 = att_names16;
11268       names8 = att_names8;
11269       names8rex = att_names8rex;
11270       names_seg = att_names_seg;
11271       names_mm = att_names_mm;
11272       names_xmm = att_names_xmm;
11273       names_ymm = att_names_ymm;
11274       index64 = att_index64;
11275       index32 = att_index32;
11276       index16 = att_index16;
11277       open_char = '(';
11278       close_char =  ')';
11279       separator_char = ',';
11280       scale_char = ',';
11281     }
11282
11283   /* The output looks better if we put 7 bytes on a line, since that
11284      puts most long word instructions on a single line.  Use 8 bytes
11285      for Intel L1OM.  */
11286   if (info->mach == bfd_mach_l1om
11287       || info->mach == bfd_mach_l1om_intel_syntax)
11288     info->bytes_per_line = 8;
11289   else
11290     info->bytes_per_line = 7;
11291
11292   info->private_data = &priv;
11293   priv.max_fetched = priv.the_buffer;
11294   priv.insn_start = pc;
11295
11296   obuf[0] = 0;
11297   for (i = 0; i < MAX_OPERANDS; ++i)
11298     {
11299       op_out[i][0] = 0;
11300       op_index[i] = -1;
11301     }
11302
11303   the_info = info;
11304   start_pc = pc;
11305   start_codep = priv.the_buffer;
11306   codep = priv.the_buffer;
11307
11308   if (setjmp (priv.bailout) != 0)
11309     {
11310       const char *name;
11311
11312       /* Getting here means we tried for data but didn't get it.  That
11313          means we have an incomplete instruction of some sort.  Just
11314          print the first byte as a prefix or a .byte pseudo-op.  */
11315       if (codep > priv.the_buffer)
11316         {
11317           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11318           if (name != NULL)
11319             (*info->fprintf_func) (info->stream, "%s", name);
11320           else
11321             {
11322               /* Just print the first byte as a .byte instruction.  */
11323               (*info->fprintf_func) (info->stream, ".byte 0x%x",
11324                                      (unsigned int) priv.the_buffer[0]);
11325             }
11326
11327           return 1;
11328         }
11329
11330       return -1;
11331     }
11332
11333   obufp = obuf;
11334   sizeflag = priv.orig_sizeflag;
11335
11336   if (!ckprefix () || rex_used)
11337     {
11338       /* Too many prefixes or unused REX prefixes.  */
11339       for (i = 0;
11340            all_prefixes[i] && i < (int) ARRAY_SIZE (all_prefixes);
11341            i++)
11342         (*info->fprintf_func) (info->stream, "%s",
11343                                prefix_name (all_prefixes[i], sizeflag));
11344       return 1;
11345     }
11346
11347   insn_codep = codep;
11348
11349   FETCH_DATA (info, codep + 1);
11350   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11351
11352   if (((prefixes & PREFIX_FWAIT)
11353        && ((*codep < 0xd8) || (*codep > 0xdf))))
11354     {
11355       (*info->fprintf_func) (info->stream, "fwait");
11356       return 1;
11357     }
11358
11359   op = 0;
11360
11361   if (*codep == 0x0f)
11362     {
11363       unsigned char threebyte;
11364       FETCH_DATA (info, codep + 2);
11365       threebyte = *++codep;
11366       dp = &dis386_twobyte[threebyte];
11367       need_modrm = twobyte_has_modrm[*codep];
11368       codep++;
11369     }
11370   else
11371     {
11372       dp = &dis386[*codep];
11373       need_modrm = onebyte_has_modrm[*codep];
11374       codep++;
11375     }
11376
11377   if ((prefixes & PREFIX_REPZ))
11378     used_prefixes |= PREFIX_REPZ;
11379   if ((prefixes & PREFIX_REPNZ))
11380     used_prefixes |= PREFIX_REPNZ;
11381   if ((prefixes & PREFIX_LOCK))
11382     used_prefixes |= PREFIX_LOCK;
11383
11384   default_prefixes = 0;
11385   if (prefixes & PREFIX_ADDR)
11386     {
11387       sizeflag ^= AFLAG;
11388       if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11389         {
11390           if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11391             all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11392           else
11393             all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11394           default_prefixes |= PREFIX_ADDR;
11395         }
11396     }
11397
11398   if ((prefixes & PREFIX_DATA))
11399     {
11400       sizeflag ^= DFLAG;
11401       if (dp->op[2].bytemode == cond_jump_mode
11402           && dp->op[0].bytemode == v_mode
11403           && !intel_syntax)
11404         {
11405           if (sizeflag & DFLAG)
11406             all_prefixes[last_data_prefix] = DATA32_PREFIX;
11407           else
11408             all_prefixes[last_data_prefix] = DATA16_PREFIX;
11409           default_prefixes |= PREFIX_DATA;
11410         }
11411       else if (rex & REX_W)
11412         {
11413           /* REX_W will override PREFIX_DATA.  */
11414           default_prefixes |= PREFIX_DATA;
11415         }
11416     }
11417
11418   if (need_modrm)
11419     {
11420       FETCH_DATA (info, codep + 1);
11421       modrm.mod = (*codep >> 6) & 3;
11422       modrm.reg = (*codep >> 3) & 7;
11423       modrm.rm = *codep & 7;
11424     }
11425
11426    need_vex = 0;
11427    need_vex_reg = 0;
11428    vex_w_done = 0;
11429
11430   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11431     {
11432       dofloat (sizeflag);
11433     }
11434   else
11435     {
11436       dp = get_valid_dis386 (dp, info);
11437       if (dp != NULL && putop (dp->name, sizeflag) == 0)
11438         {
11439           for (i = 0; i < MAX_OPERANDS; ++i)
11440             {
11441               obufp = op_out[i];
11442               op_ad = MAX_OPERANDS - 1 - i;
11443               if (dp->op[i].rtn)
11444                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11445             }
11446         }
11447     }
11448
11449   /* See if any prefixes were not used.  If so, print the first one
11450      separately.  If we don't do this, we'll wind up printing an
11451      instruction stream which does not precisely correspond to the
11452      bytes we are disassembling.  */
11453   if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11454     {
11455       for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11456         if (all_prefixes[i])
11457           {
11458             const char *name;
11459             name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11460             if (name == NULL)
11461               name = INTERNAL_DISASSEMBLER_ERROR;
11462             (*info->fprintf_func) (info->stream, "%s", name);
11463             return 1;
11464           }
11465     }
11466
11467   /* Check if the REX prefix is used.  */
11468   if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11469     all_prefixes[last_rex_prefix] = 0;
11470
11471   /* Check if the SEG prefix is used.  */
11472   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11473                    | PREFIX_FS | PREFIX_GS)) != 0
11474       && (used_prefixes
11475           & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11476     all_prefixes[last_seg_prefix] = 0;
11477
11478   /* Check if the ADDR prefix is used.  */
11479   if ((prefixes & PREFIX_ADDR) != 0
11480       && (used_prefixes & PREFIX_ADDR) != 0)
11481     all_prefixes[last_addr_prefix] = 0;
11482
11483   /* Check if the DATA prefix is used.  */
11484   if ((prefixes & PREFIX_DATA) != 0
11485       && (used_prefixes & PREFIX_DATA) != 0)
11486     all_prefixes[last_data_prefix] = 0;
11487
11488   prefix_length = 0;
11489   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11490     if (all_prefixes[i])
11491       {
11492         const char *name;
11493         name = prefix_name (all_prefixes[i], sizeflag);
11494         if (name == NULL)
11495           abort ();
11496         prefix_length += strlen (name) + 1;
11497         (*info->fprintf_func) (info->stream, "%s ", name);
11498       }
11499
11500   /* Check maximum code length.  */
11501   if ((codep - start_codep) > MAX_CODE_LENGTH)
11502     {
11503       (*info->fprintf_func) (info->stream, "(bad)");
11504       return MAX_CODE_LENGTH;
11505     }
11506
11507   obufp = mnemonicendp;
11508   for (i = strlen (obuf) + prefix_length; i < 6; i++)
11509     oappend (" ");
11510   oappend (" ");
11511   (*info->fprintf_func) (info->stream, "%s", obuf);
11512
11513   /* The enter and bound instructions are printed with operands in the same
11514      order as the intel book; everything else is printed in reverse order.  */
11515   if (intel_syntax || two_source_ops)
11516     {
11517       bfd_vma riprel;
11518
11519       for (i = 0; i < MAX_OPERANDS; ++i)
11520         op_txt[i] = op_out[i];
11521
11522       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11523         {
11524           op_ad = op_index[i];
11525           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11526           op_index[MAX_OPERANDS - 1 - i] = op_ad;
11527           riprel = op_riprel[i];
11528           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11529           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11530         }
11531     }
11532   else
11533     {
11534       for (i = 0; i < MAX_OPERANDS; ++i)
11535         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11536     }
11537
11538   needcomma = 0;
11539   for (i = 0; i < MAX_OPERANDS; ++i)
11540     if (*op_txt[i])
11541       {
11542         if (needcomma)
11543           (*info->fprintf_func) (info->stream, ",");
11544         if (op_index[i] != -1 && !op_riprel[i])
11545           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11546         else
11547           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11548         needcomma = 1;
11549       }
11550
11551   for (i = 0; i < MAX_OPERANDS; i++)
11552     if (op_index[i] != -1 && op_riprel[i])
11553       {
11554         (*info->fprintf_func) (info->stream, "        # ");
11555         (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11556                                                 + op_address[op_index[i]]), info);
11557         break;
11558       }
11559   return codep - priv.the_buffer;
11560 }
11561
11562 static const char *float_mem[] = {
11563   /* d8 */
11564   "fadd{s|}",
11565   "fmul{s|}",
11566   "fcom{s|}",
11567   "fcomp{s|}",
11568   "fsub{s|}",
11569   "fsubr{s|}",
11570   "fdiv{s|}",
11571   "fdivr{s|}",
11572   /* d9 */
11573   "fld{s|}",
11574   "(bad)",
11575   "fst{s|}",
11576   "fstp{s|}",
11577   "fldenvIC",
11578   "fldcw",
11579   "fNstenvIC",
11580   "fNstcw",
11581   /* da */
11582   "fiadd{l|}",
11583   "fimul{l|}",
11584   "ficom{l|}",
11585   "ficomp{l|}",
11586   "fisub{l|}",
11587   "fisubr{l|}",
11588   "fidiv{l|}",
11589   "fidivr{l|}",
11590   /* db */
11591   "fild{l|}",
11592   "fisttp{l|}",
11593   "fist{l|}",
11594   "fistp{l|}",
11595   "(bad)",
11596   "fld{t||t|}",
11597   "(bad)",
11598   "fstp{t||t|}",
11599   /* dc */
11600   "fadd{l|}",
11601   "fmul{l|}",
11602   "fcom{l|}",
11603   "fcomp{l|}",
11604   "fsub{l|}",
11605   "fsubr{l|}",
11606   "fdiv{l|}",
11607   "fdivr{l|}",
11608   /* dd */
11609   "fld{l|}",
11610   "fisttp{ll|}",
11611   "fst{l||}",
11612   "fstp{l|}",
11613   "frstorIC",
11614   "(bad)",
11615   "fNsaveIC",
11616   "fNstsw",
11617   /* de */
11618   "fiadd",
11619   "fimul",
11620   "ficom",
11621   "ficomp",
11622   "fisub",
11623   "fisubr",
11624   "fidiv",
11625   "fidivr",
11626   /* df */
11627   "fild",
11628   "fisttp",
11629   "fist",
11630   "fistp",
11631   "fbld",
11632   "fild{ll|}",
11633   "fbstp",
11634   "fistp{ll|}",
11635 };
11636
11637 static const unsigned char float_mem_mode[] = {
11638   /* d8 */
11639   d_mode,
11640   d_mode,
11641   d_mode,
11642   d_mode,
11643   d_mode,
11644   d_mode,
11645   d_mode,
11646   d_mode,
11647   /* d9 */
11648   d_mode,
11649   0,
11650   d_mode,
11651   d_mode,
11652   0,
11653   w_mode,
11654   0,
11655   w_mode,
11656   /* da */
11657   d_mode,
11658   d_mode,
11659   d_mode,
11660   d_mode,
11661   d_mode,
11662   d_mode,
11663   d_mode,
11664   d_mode,
11665   /* db */
11666   d_mode,
11667   d_mode,
11668   d_mode,
11669   d_mode,
11670   0,
11671   t_mode,
11672   0,
11673   t_mode,
11674   /* dc */
11675   q_mode,
11676   q_mode,
11677   q_mode,
11678   q_mode,
11679   q_mode,
11680   q_mode,
11681   q_mode,
11682   q_mode,
11683   /* dd */
11684   q_mode,
11685   q_mode,
11686   q_mode,
11687   q_mode,
11688   0,
11689   0,
11690   0,
11691   w_mode,
11692   /* de */
11693   w_mode,
11694   w_mode,
11695   w_mode,
11696   w_mode,
11697   w_mode,
11698   w_mode,
11699   w_mode,
11700   w_mode,
11701   /* df */
11702   w_mode,
11703   w_mode,
11704   w_mode,
11705   w_mode,
11706   t_mode,
11707   q_mode,
11708   t_mode,
11709   q_mode
11710 };
11711
11712 #define ST { OP_ST, 0 }
11713 #define STi { OP_STi, 0 }
11714
11715 #define FGRPd9_2 NULL, { { NULL, 0 } }
11716 #define FGRPd9_4 NULL, { { NULL, 1 } }
11717 #define FGRPd9_5 NULL, { { NULL, 2 } }
11718 #define FGRPd9_6 NULL, { { NULL, 3 } }
11719 #define FGRPd9_7 NULL, { { NULL, 4 } }
11720 #define FGRPda_5 NULL, { { NULL, 5 } }
11721 #define FGRPdb_4 NULL, { { NULL, 6 } }
11722 #define FGRPde_3 NULL, { { NULL, 7 } }
11723 #define FGRPdf_4 NULL, { { NULL, 8 } }
11724
11725 static const struct dis386 float_reg[][8] = {
11726   /* d8 */
11727   {
11728     { "fadd",   { ST, STi } },
11729     { "fmul",   { ST, STi } },
11730     { "fcom",   { STi } },
11731     { "fcomp",  { STi } },
11732     { "fsub",   { ST, STi } },
11733     { "fsubr",  { ST, STi } },
11734     { "fdiv",   { ST, STi } },
11735     { "fdivr",  { ST, STi } },
11736   },
11737   /* d9 */
11738   {
11739     { "fld",    { STi } },
11740     { "fxch",   { STi } },
11741     { FGRPd9_2 },
11742     { Bad_Opcode },
11743     { FGRPd9_4 },
11744     { FGRPd9_5 },
11745     { FGRPd9_6 },
11746     { FGRPd9_7 },
11747   },
11748   /* da */
11749   {
11750     { "fcmovb", { ST, STi } },
11751     { "fcmove", { ST, STi } },
11752     { "fcmovbe",{ ST, STi } },
11753     { "fcmovu", { ST, STi } },
11754     { Bad_Opcode },
11755     { FGRPda_5 },
11756     { Bad_Opcode },
11757     { Bad_Opcode },
11758   },
11759   /* db */
11760   {
11761     { "fcmovnb",{ ST, STi } },
11762     { "fcmovne",{ ST, STi } },
11763     { "fcmovnbe",{ ST, STi } },
11764     { "fcmovnu",{ ST, STi } },
11765     { FGRPdb_4 },
11766     { "fucomi", { ST, STi } },
11767     { "fcomi",  { ST, STi } },
11768     { Bad_Opcode },
11769   },
11770   /* dc */
11771   {
11772     { "fadd",   { STi, ST } },
11773     { "fmul",   { STi, ST } },
11774     { Bad_Opcode },
11775     { Bad_Opcode },
11776     { "fsub!M", { STi, ST } },
11777     { "fsubM",  { STi, ST } },
11778     { "fdiv!M", { STi, ST } },
11779     { "fdivM",  { STi, ST } },
11780   },
11781   /* dd */
11782   {
11783     { "ffree",  { STi } },
11784     { Bad_Opcode },
11785     { "fst",    { STi } },
11786     { "fstp",   { STi } },
11787     { "fucom",  { STi } },
11788     { "fucomp", { STi } },
11789     { Bad_Opcode },
11790     { Bad_Opcode },
11791   },
11792   /* de */
11793   {
11794     { "faddp",  { STi, ST } },
11795     { "fmulp",  { STi, ST } },
11796     { Bad_Opcode },
11797     { FGRPde_3 },
11798     { "fsub!Mp", { STi, ST } },
11799     { "fsubMp", { STi, ST } },
11800     { "fdiv!Mp", { STi, ST } },
11801     { "fdivMp", { STi, ST } },
11802   },
11803   /* df */
11804   {
11805     { "ffreep", { STi } },
11806     { Bad_Opcode },
11807     { Bad_Opcode },
11808     { Bad_Opcode },
11809     { FGRPdf_4 },
11810     { "fucomip", { ST, STi } },
11811     { "fcomip", { ST, STi } },
11812     { Bad_Opcode },
11813   },
11814 };
11815
11816 static char *fgrps[][8] = {
11817   /* d9_2  0 */
11818   {
11819     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11820   },
11821
11822   /* d9_4  1 */
11823   {
11824     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11825   },
11826
11827   /* d9_5  2 */
11828   {
11829     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11830   },
11831
11832   /* d9_6  3 */
11833   {
11834     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11835   },
11836
11837   /* d9_7  4 */
11838   {
11839     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11840   },
11841
11842   /* da_5  5 */
11843   {
11844     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11845   },
11846
11847   /* db_4  6 */
11848   {
11849     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11850     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11851   },
11852
11853   /* de_3  7 */
11854   {
11855     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11856   },
11857
11858   /* df_4  8 */
11859   {
11860     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11861   },
11862 };
11863
11864 static void
11865 swap_operand (void)
11866 {
11867   mnemonicendp[0] = '.';
11868   mnemonicendp[1] = 's';
11869   mnemonicendp += 2;
11870 }
11871
11872 static void
11873 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11874                int sizeflag ATTRIBUTE_UNUSED)
11875 {
11876   /* Skip mod/rm byte.  */
11877   MODRM_CHECK;
11878   codep++;
11879 }
11880
11881 static void
11882 dofloat (int sizeflag)
11883 {
11884   const struct dis386 *dp;
11885   unsigned char floatop;
11886
11887   floatop = codep[-1];
11888
11889   if (modrm.mod != 3)
11890     {
11891       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11892
11893       putop (float_mem[fp_indx], sizeflag);
11894       obufp = op_out[0];
11895       op_ad = 2;
11896       OP_E (float_mem_mode[fp_indx], sizeflag);
11897       return;
11898     }
11899   /* Skip mod/rm byte.  */
11900   MODRM_CHECK;
11901   codep++;
11902
11903   dp = &float_reg[floatop - 0xd8][modrm.reg];
11904   if (dp->name == NULL)
11905     {
11906       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11907
11908       /* Instruction fnstsw is only one with strange arg.  */
11909       if (floatop == 0xdf && codep[-1] == 0xe0)
11910         strcpy (op_out[0], names16[0]);
11911     }
11912   else
11913     {
11914       putop (dp->name, sizeflag);
11915
11916       obufp = op_out[0];
11917       op_ad = 2;
11918       if (dp->op[0].rtn)
11919         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11920
11921       obufp = op_out[1];
11922       op_ad = 1;
11923       if (dp->op[1].rtn)
11924         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11925     }
11926 }
11927
11928 static void
11929 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11930 {
11931   oappend ("%st" + intel_syntax);
11932 }
11933
11934 static void
11935 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11936 {
11937   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
11938   oappend (scratchbuf + intel_syntax);
11939 }
11940
11941 /* Capital letters in template are macros.  */
11942 static int
11943 putop (const char *in_template, int sizeflag)
11944 {
11945   const char *p;
11946   int alt = 0;
11947   int cond = 1;
11948   unsigned int l = 0, len = 1;
11949   char last[4];
11950
11951 #define SAVE_LAST(c)                    \
11952   if (l < len && l < sizeof (last))     \
11953     last[l++] = c;                      \
11954   else                                  \
11955     abort ();
11956
11957   for (p = in_template; *p; p++)
11958     {
11959       switch (*p)
11960         {
11961         default:
11962           *obufp++ = *p;
11963           break;
11964         case '%':
11965           len++;
11966           break;
11967         case '!':
11968           cond = 0;
11969           break;
11970         case '{':
11971           alt = 0;
11972           if (intel_syntax)
11973             {
11974               while (*++p != '|')
11975                 if (*p == '}' || *p == '\0')
11976                   abort ();
11977             }
11978           /* Fall through.  */
11979         case 'I':
11980           alt = 1;
11981           continue;
11982         case '|':
11983           while (*++p != '}')
11984             {
11985               if (*p == '\0')
11986                 abort ();
11987             }
11988           break;
11989         case '}':
11990           break;
11991         case 'A':
11992           if (intel_syntax)
11993             break;
11994           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11995             *obufp++ = 'b';
11996           break;
11997         case 'B':
11998           if (l == 0 && len == 1)
11999             {
12000 case_B:
12001               if (intel_syntax)
12002                 break;
12003               if (sizeflag & SUFFIX_ALWAYS)
12004                 *obufp++ = 'b';
12005             }
12006           else
12007             {
12008               if (l != 1
12009                   || len != 2
12010                   || last[0] != 'L')
12011                 {
12012                   SAVE_LAST (*p);
12013                   break;
12014                 }
12015
12016               if (address_mode == mode_64bit
12017                   && !(prefixes & PREFIX_ADDR))
12018                 {
12019                   *obufp++ = 'a';
12020                   *obufp++ = 'b';
12021                   *obufp++ = 's';
12022                 }
12023
12024               goto case_B;
12025             }
12026           break;
12027         case 'C':
12028           if (intel_syntax && !alt)
12029             break;
12030           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12031             {
12032               if (sizeflag & DFLAG)
12033                 *obufp++ = intel_syntax ? 'd' : 'l';
12034               else
12035                 *obufp++ = intel_syntax ? 'w' : 's';
12036               used_prefixes |= (prefixes & PREFIX_DATA);
12037             }
12038           break;
12039         case 'D':
12040           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12041             break;
12042           USED_REX (REX_W);
12043           if (modrm.mod == 3)
12044             {
12045               if (rex & REX_W)
12046                 *obufp++ = 'q';
12047               else
12048                 {
12049                   if (sizeflag & DFLAG)
12050                     *obufp++ = intel_syntax ? 'd' : 'l';
12051                   else
12052                     *obufp++ = 'w';
12053                   used_prefixes |= (prefixes & PREFIX_DATA);
12054                 }
12055             }
12056           else
12057             *obufp++ = 'w';
12058           break;
12059         case 'E':               /* For jcxz/jecxz */
12060           if (address_mode == mode_64bit)
12061             {
12062               if (sizeflag & AFLAG)
12063                 *obufp++ = 'r';
12064               else
12065                 *obufp++ = 'e';
12066             }
12067           else
12068             if (sizeflag & AFLAG)
12069               *obufp++ = 'e';
12070           used_prefixes |= (prefixes & PREFIX_ADDR);
12071           break;
12072         case 'F':
12073           if (intel_syntax)
12074             break;
12075           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12076             {
12077               if (sizeflag & AFLAG)
12078                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12079               else
12080                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12081               used_prefixes |= (prefixes & PREFIX_ADDR);
12082             }
12083           break;
12084         case 'G':
12085           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12086             break;
12087           if ((rex & REX_W) || (sizeflag & DFLAG))
12088             *obufp++ = 'l';
12089           else
12090             *obufp++ = 'w';
12091           if (!(rex & REX_W))
12092             used_prefixes |= (prefixes & PREFIX_DATA);
12093           break;
12094         case 'H':
12095           if (intel_syntax)
12096             break;
12097           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12098               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12099             {
12100               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12101               *obufp++ = ',';
12102               *obufp++ = 'p';
12103               if (prefixes & PREFIX_DS)
12104                 *obufp++ = 't';
12105               else
12106                 *obufp++ = 'n';
12107             }
12108           break;
12109         case 'J':
12110           if (intel_syntax)
12111             break;
12112           *obufp++ = 'l';
12113           break;
12114         case 'K':
12115           USED_REX (REX_W);
12116           if (rex & REX_W)
12117             *obufp++ = 'q';
12118           else
12119             *obufp++ = 'd';
12120           break;
12121         case 'Z':
12122           if (intel_syntax)
12123             break;
12124           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12125             {
12126               *obufp++ = 'q';
12127               break;
12128             }
12129           /* Fall through.  */
12130           goto case_L;
12131         case 'L':
12132           if (l != 0 || len != 1)
12133             {
12134               SAVE_LAST (*p);
12135               break;
12136             }
12137 case_L:
12138           if (intel_syntax)
12139             break;
12140           if (sizeflag & SUFFIX_ALWAYS)
12141             *obufp++ = 'l';
12142           break;
12143         case 'M':
12144           if (intel_mnemonic != cond)
12145             *obufp++ = 'r';
12146           break;
12147         case 'N':
12148           if ((prefixes & PREFIX_FWAIT) == 0)
12149             *obufp++ = 'n';
12150           else
12151             used_prefixes |= PREFIX_FWAIT;
12152           break;
12153         case 'O':
12154           USED_REX (REX_W);
12155           if (rex & REX_W)
12156             *obufp++ = 'o';
12157           else if (intel_syntax && (sizeflag & DFLAG))
12158             *obufp++ = 'q';
12159           else
12160             *obufp++ = 'd';
12161           if (!(rex & REX_W))
12162             used_prefixes |= (prefixes & PREFIX_DATA);
12163           break;
12164         case 'T':
12165           if (intel_syntax)
12166             break;
12167           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12168             {
12169               *obufp++ = 'q';
12170               break;
12171             }
12172           /* Fall through.  */
12173         case 'P':
12174           if (intel_syntax)
12175             break;
12176           if ((prefixes & PREFIX_DATA)
12177               || (rex & REX_W)
12178               || (sizeflag & SUFFIX_ALWAYS))
12179             {
12180               USED_REX (REX_W);
12181               if (rex & REX_W)
12182                 *obufp++ = 'q';
12183               else
12184                 {
12185                    if (sizeflag & DFLAG)
12186                       *obufp++ = 'l';
12187                    else
12188                      *obufp++ = 'w';
12189                    used_prefixes |= (prefixes & PREFIX_DATA);
12190                 }
12191             }
12192           break;
12193         case 'U':
12194           if (intel_syntax)
12195             break;
12196           if (address_mode == mode_64bit && (sizeflag & DFLAG))
12197             {
12198               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12199                 *obufp++ = 'q';
12200               break;
12201             }
12202           /* Fall through.  */
12203           goto case_Q;
12204         case 'Q':
12205           if (l == 0 && len == 1)
12206             {
12207 case_Q:
12208               if (intel_syntax && !alt)
12209                 break;
12210               USED_REX (REX_W);
12211               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12212                 {
12213                   if (rex & REX_W)
12214                     *obufp++ = 'q';
12215                   else
12216                     {
12217                       if (sizeflag & DFLAG)
12218                         *obufp++ = intel_syntax ? 'd' : 'l';
12219                       else
12220                         *obufp++ = 'w';
12221                       used_prefixes |= (prefixes & PREFIX_DATA);
12222                     }
12223                 }
12224             }
12225           else
12226             {
12227               if (l != 1 || len != 2 || last[0] != 'L')
12228                 {
12229                   SAVE_LAST (*p);
12230                   break;
12231                 }
12232               if (intel_syntax
12233                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12234                 break;
12235               if ((rex & REX_W))
12236                 {
12237                   USED_REX (REX_W);
12238                   *obufp++ = 'q';
12239                 }
12240               else
12241                 *obufp++ = 'l';
12242             }
12243           break;
12244         case 'R':
12245           USED_REX (REX_W);
12246           if (rex & REX_W)
12247             *obufp++ = 'q';
12248           else if (sizeflag & DFLAG)
12249             {
12250               if (intel_syntax)
12251                   *obufp++ = 'd';
12252               else
12253                   *obufp++ = 'l';
12254             }
12255           else
12256             *obufp++ = 'w';
12257           if (intel_syntax && !p[1]
12258               && ((rex & REX_W) || (sizeflag & DFLAG)))
12259             *obufp++ = 'e';
12260           if (!(rex & REX_W))
12261             used_prefixes |= (prefixes & PREFIX_DATA);
12262           break;
12263         case 'V':
12264           if (l == 0 && len == 1)
12265             {
12266               if (intel_syntax)
12267                 break;
12268               if (address_mode == mode_64bit && (sizeflag & DFLAG))
12269                 {
12270                   if (sizeflag & SUFFIX_ALWAYS)
12271                     *obufp++ = 'q';
12272                   break;
12273                 }
12274             }
12275           else
12276             {
12277               if (l != 1
12278                   || len != 2
12279                   || last[0] != 'L')
12280                 {
12281                   SAVE_LAST (*p);
12282                   break;
12283                 }
12284
12285               if (rex & REX_W)
12286                 {
12287                   *obufp++ = 'a';
12288                   *obufp++ = 'b';
12289                   *obufp++ = 's';
12290                 }
12291             }
12292           /* Fall through.  */
12293           goto case_S;
12294         case 'S':
12295           if (l == 0 && len == 1)
12296             {
12297 case_S:
12298               if (intel_syntax)
12299                 break;
12300               if (sizeflag & SUFFIX_ALWAYS)
12301                 {
12302                   if (rex & REX_W)
12303                     *obufp++ = 'q';
12304                   else
12305                     {
12306                       if (sizeflag & DFLAG)
12307                         *obufp++ = 'l';
12308                       else
12309                         *obufp++ = 'w';
12310                       used_prefixes |= (prefixes & PREFIX_DATA);
12311                     }
12312                 }
12313             }
12314           else
12315             {
12316               if (l != 1
12317                   || len != 2
12318                   || last[0] != 'L')
12319                 {
12320                   SAVE_LAST (*p);
12321                   break;
12322                 }
12323
12324               if (address_mode == mode_64bit
12325                   && !(prefixes & PREFIX_ADDR))
12326                 {
12327                   *obufp++ = 'a';
12328                   *obufp++ = 'b';
12329                   *obufp++ = 's';
12330                 }
12331
12332               goto case_S;
12333             }
12334           break;
12335         case 'X':
12336           if (l != 0 || len != 1)
12337             {
12338               SAVE_LAST (*p);
12339               break;
12340             }
12341           if (need_vex && vex.prefix)
12342             {
12343               if (vex.prefix == DATA_PREFIX_OPCODE)
12344                 *obufp++ = 'd';
12345               else
12346                 *obufp++ = 's';
12347             }
12348           else
12349             {
12350               if (prefixes & PREFIX_DATA)
12351                 *obufp++ = 'd';
12352               else
12353                 *obufp++ = 's';
12354               used_prefixes |= (prefixes & PREFIX_DATA);
12355             }
12356           break;
12357         case 'Y':
12358           if (l == 0 && len == 1)
12359             {
12360               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12361                 break;
12362               if (rex & REX_W)
12363                 {
12364                   USED_REX (REX_W);
12365                   *obufp++ = 'q';
12366                 }
12367               break;
12368             }
12369           else
12370             {
12371               if (l != 1 || len != 2 || last[0] != 'X')
12372                 {
12373                   SAVE_LAST (*p);
12374                   break;
12375                 }
12376               if (!need_vex)
12377                 abort ();
12378               if (intel_syntax
12379                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12380                 break;
12381               switch (vex.length)
12382                 {
12383                 case 128:
12384                   *obufp++ = 'x';
12385                   break;
12386                 case 256:
12387                   *obufp++ = 'y';
12388                   break;
12389                 default:
12390                   abort ();
12391                 }
12392             }
12393           break;
12394         case 'W':
12395           if (l == 0 && len == 1)
12396             {
12397               /* operand size flag for cwtl, cbtw */
12398               USED_REX (REX_W);
12399               if (rex & REX_W)
12400                 {
12401                   if (intel_syntax)
12402                     *obufp++ = 'd';
12403                   else
12404                     *obufp++ = 'l';
12405                 }
12406               else if (sizeflag & DFLAG)
12407                 *obufp++ = 'w';
12408               else
12409                 *obufp++ = 'b';
12410               if (!(rex & REX_W))
12411                 used_prefixes |= (prefixes & PREFIX_DATA);
12412             }
12413           else
12414             {
12415               if (l != 1 || len != 2 || last[0] != 'X')
12416                 {
12417                   SAVE_LAST (*p);
12418                   break;
12419                 }
12420               if (!need_vex)
12421                 abort ();
12422               *obufp++ = vex.w ? 'd': 's';
12423             }
12424           break;
12425         }
12426       alt = 0;
12427     }
12428   *obufp = 0;
12429   mnemonicendp = obufp;
12430   return 0;
12431 }
12432
12433 static void
12434 oappend (const char *s)
12435 {
12436   obufp = stpcpy (obufp, s);
12437 }
12438
12439 static void
12440 append_seg (void)
12441 {
12442   if (prefixes & PREFIX_CS)
12443     {
12444       used_prefixes |= PREFIX_CS;
12445       oappend ("%cs:" + intel_syntax);
12446     }
12447   if (prefixes & PREFIX_DS)
12448     {
12449       used_prefixes |= PREFIX_DS;
12450       oappend ("%ds:" + intel_syntax);
12451     }
12452   if (prefixes & PREFIX_SS)
12453     {
12454       used_prefixes |= PREFIX_SS;
12455       oappend ("%ss:" + intel_syntax);
12456     }
12457   if (prefixes & PREFIX_ES)
12458     {
12459       used_prefixes |= PREFIX_ES;
12460       oappend ("%es:" + intel_syntax);
12461     }
12462   if (prefixes & PREFIX_FS)
12463     {
12464       used_prefixes |= PREFIX_FS;
12465       oappend ("%fs:" + intel_syntax);
12466     }
12467   if (prefixes & PREFIX_GS)
12468     {
12469       used_prefixes |= PREFIX_GS;
12470       oappend ("%gs:" + intel_syntax);
12471     }
12472 }
12473
12474 static void
12475 OP_indirE (int bytemode, int sizeflag)
12476 {
12477   if (!intel_syntax)
12478     oappend ("*");
12479   OP_E (bytemode, sizeflag);
12480 }
12481
12482 static void
12483 print_operand_value (char *buf, int hex, bfd_vma disp)
12484 {
12485   if (address_mode == mode_64bit)
12486     {
12487       if (hex)
12488         {
12489           char tmp[30];
12490           int i;
12491           buf[0] = '0';
12492           buf[1] = 'x';
12493           sprintf_vma (tmp, disp);
12494           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12495           strcpy (buf + 2, tmp + i);
12496         }
12497       else
12498         {
12499           bfd_signed_vma v = disp;
12500           char tmp[30];
12501           int i;
12502           if (v < 0)
12503             {
12504               *(buf++) = '-';
12505               v = -disp;
12506               /* Check for possible overflow on 0x8000000000000000.  */
12507               if (v < 0)
12508                 {
12509                   strcpy (buf, "9223372036854775808");
12510                   return;
12511                 }
12512             }
12513           if (!v)
12514             {
12515               strcpy (buf, "0");
12516               return;
12517             }
12518
12519           i = 0;
12520           tmp[29] = 0;
12521           while (v)
12522             {
12523               tmp[28 - i] = (v % 10) + '0';
12524               v /= 10;
12525               i++;
12526             }
12527           strcpy (buf, tmp + 29 - i);
12528         }
12529     }
12530   else
12531     {
12532       if (hex)
12533         sprintf (buf, "0x%x", (unsigned int) disp);
12534       else
12535         sprintf (buf, "%d", (int) disp);
12536     }
12537 }
12538
12539 /* Put DISP in BUF as signed hex number.  */
12540
12541 static void
12542 print_displacement (char *buf, bfd_vma disp)
12543 {
12544   bfd_signed_vma val = disp;
12545   char tmp[30];
12546   int i, j = 0;
12547
12548   if (val < 0)
12549     {
12550       buf[j++] = '-';
12551       val = -disp;
12552
12553       /* Check for possible overflow.  */
12554       if (val < 0)
12555         {
12556           switch (address_mode)
12557             {
12558             case mode_64bit:
12559               strcpy (buf + j, "0x8000000000000000");
12560               break;
12561             case mode_32bit:
12562               strcpy (buf + j, "0x80000000");
12563               break;
12564             case mode_16bit:
12565               strcpy (buf + j, "0x8000");
12566               break;
12567             }
12568           return;
12569         }
12570     }
12571
12572   buf[j++] = '0';
12573   buf[j++] = 'x';
12574
12575   sprintf_vma (tmp, (bfd_vma) val);
12576   for (i = 0; tmp[i] == '0'; i++)
12577     continue;
12578   if (tmp[i] == '\0')
12579     i--;
12580   strcpy (buf + j, tmp + i);
12581 }
12582
12583 static void
12584 intel_operand_size (int bytemode, int sizeflag)
12585 {
12586   switch (bytemode)
12587     {
12588     case b_mode:
12589     case b_swap_mode:
12590     case dqb_mode:
12591       oappend ("BYTE PTR ");
12592       break;
12593     case w_mode:
12594     case dqw_mode:
12595       oappend ("WORD PTR ");
12596       break;
12597     case stack_v_mode:
12598       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12599         {
12600           oappend ("QWORD PTR ");
12601           break;
12602         }
12603       /* FALLTHRU */
12604     case v_mode:
12605     case v_swap_mode:
12606     case dq_mode:
12607       USED_REX (REX_W);
12608       if (rex & REX_W)
12609         oappend ("QWORD PTR ");
12610       else
12611         {
12612           if ((sizeflag & DFLAG) || bytemode == dq_mode)
12613             oappend ("DWORD PTR ");
12614           else
12615             oappend ("WORD PTR ");
12616           used_prefixes |= (prefixes & PREFIX_DATA);
12617         }
12618       break;
12619     case z_mode:
12620       if ((rex & REX_W) || (sizeflag & DFLAG))
12621         *obufp++ = 'D';
12622       oappend ("WORD PTR ");
12623       if (!(rex & REX_W))
12624         used_prefixes |= (prefixes & PREFIX_DATA);
12625       break;
12626     case a_mode:
12627       if (sizeflag & DFLAG)
12628         oappend ("QWORD PTR ");
12629       else
12630         oappend ("DWORD PTR ");
12631       used_prefixes |= (prefixes & PREFIX_DATA);
12632       break;
12633     case d_mode:
12634     case d_swap_mode:
12635     case dqd_mode:
12636       oappend ("DWORD PTR ");
12637       break;
12638     case q_mode:
12639     case q_swap_mode:
12640       oappend ("QWORD PTR ");
12641       break;
12642     case m_mode:
12643       if (address_mode == mode_64bit)
12644         oappend ("QWORD PTR ");
12645       else
12646         oappend ("DWORD PTR ");
12647       break;
12648     case f_mode:
12649       if (sizeflag & DFLAG)
12650         oappend ("FWORD PTR ");
12651       else
12652         oappend ("DWORD PTR ");
12653       used_prefixes |= (prefixes & PREFIX_DATA);
12654       break;
12655     case t_mode:
12656       oappend ("TBYTE PTR ");
12657       break;
12658     case x_mode:
12659     case x_swap_mode:
12660       if (need_vex)
12661         {
12662           switch (vex.length)
12663             {
12664             case 128:
12665               oappend ("XMMWORD PTR ");
12666               break;
12667             case 256:
12668               oappend ("YMMWORD PTR ");
12669               break;
12670             default:
12671               abort ();
12672             }
12673         }
12674       else
12675         oappend ("XMMWORD PTR ");
12676       break;
12677     case xmm_mode:
12678       oappend ("XMMWORD PTR ");
12679       break;
12680     case xmmq_mode:
12681       if (!need_vex)
12682         abort ();
12683
12684       switch (vex.length)
12685         {
12686         case 128:
12687           oappend ("QWORD PTR ");
12688           break;
12689         case 256:
12690           oappend ("XMMWORD PTR ");
12691           break;
12692         default:
12693           abort ();
12694         }
12695       break;
12696     case ymmq_mode:
12697       if (!need_vex)
12698         abort ();
12699
12700       switch (vex.length)
12701         {
12702         case 128:
12703           oappend ("QWORD PTR ");
12704           break;
12705         case 256:
12706           oappend ("YMMWORD PTR ");
12707           break;
12708         default:
12709           abort ();
12710         }
12711       break;
12712     case o_mode:
12713       oappend ("OWORD PTR ");
12714       break;
12715     case vex_w_dq_mode:
12716       if (!need_vex)
12717         abort ();
12718
12719       if (vex.w)
12720         oappend ("QWORD PTR ");
12721       else
12722         oappend ("DWORD PTR ");
12723       break;
12724     default:
12725       break;
12726     }
12727 }
12728
12729 static void
12730 OP_E_register (int bytemode, int sizeflag)
12731 {
12732   int reg = modrm.rm;
12733   const char **names;
12734
12735   USED_REX (REX_B);
12736   if ((rex & REX_B))
12737     reg += 8;
12738
12739   if ((sizeflag & SUFFIX_ALWAYS)
12740       && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12741     swap_operand ();
12742
12743   switch (bytemode)
12744     {
12745     case b_mode:
12746     case b_swap_mode:
12747       USED_REX (0);
12748       if (rex)
12749         names = names8rex;
12750       else
12751         names = names8;
12752       break;
12753     case w_mode:
12754       names = names16;
12755       break;
12756     case d_mode:
12757       names = names32;
12758       break;
12759     case q_mode:
12760       names = names64;
12761       break;
12762     case m_mode:
12763       names = address_mode == mode_64bit ? names64 : names32;
12764       break;
12765     case stack_v_mode:
12766       if (address_mode == mode_64bit && (sizeflag & DFLAG))
12767         {
12768           names = names64;
12769           break;
12770         }
12771       bytemode = v_mode;
12772       /* FALLTHRU */
12773     case v_mode:
12774     case v_swap_mode:
12775     case dq_mode:
12776     case dqb_mode:
12777     case dqd_mode:
12778     case dqw_mode:
12779       USED_REX (REX_W);
12780       if (rex & REX_W)
12781         names = names64;
12782       else
12783         {
12784           if ((sizeflag & DFLAG)
12785               || (bytemode != v_mode
12786                   && bytemode != v_swap_mode))
12787             names = names32;
12788           else
12789             names = names16;
12790           used_prefixes |= (prefixes & PREFIX_DATA);
12791         }
12792       break;
12793     case 0:
12794       return;
12795     default:
12796       oappend (INTERNAL_DISASSEMBLER_ERROR);
12797       return;
12798     }
12799   oappend (names[reg]);
12800 }
12801
12802 static void
12803 OP_E_memory (int bytemode, int sizeflag)
12804 {
12805   bfd_vma disp = 0;
12806   int add = (rex & REX_B) ? 8 : 0;
12807   int riprel = 0;
12808
12809   USED_REX (REX_B);
12810   if (intel_syntax)
12811     intel_operand_size (bytemode, sizeflag);
12812   append_seg ();
12813
12814   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12815     {
12816       /* 32/64 bit address mode */
12817       int havedisp;
12818       int havesib;
12819       int havebase;
12820       int haveindex;
12821       int needindex;
12822       int base, rbase;
12823       int vindex = 0;
12824       int scale = 0;
12825
12826       havesib = 0;
12827       havebase = 1;
12828       haveindex = 0;
12829       base = modrm.rm;
12830
12831       if (base == 4)
12832         {
12833           havesib = 1;
12834           FETCH_DATA (the_info, codep + 1);
12835           vindex = (*codep >> 3) & 7;
12836           scale = (*codep >> 6) & 3;
12837           base = *codep & 7;
12838           USED_REX (REX_X);
12839           if (rex & REX_X)
12840             vindex += 8;
12841           haveindex = vindex != 4;
12842           codep++;
12843         }
12844       rbase = base + add;
12845
12846       switch (modrm.mod)
12847         {
12848         case 0:
12849           if (base == 5)
12850             {
12851               havebase = 0;
12852               if (address_mode == mode_64bit && !havesib)
12853                 riprel = 1;
12854               disp = get32s ();
12855             }
12856           break;
12857         case 1:
12858           FETCH_DATA (the_info, codep + 1);
12859           disp = *codep++;
12860           if ((disp & 0x80) != 0)
12861             disp -= 0x100;
12862           break;
12863         case 2:
12864           disp = get32s ();
12865           break;
12866         }
12867
12868       /* In 32bit mode, we need index register to tell [offset] from
12869          [eiz*1 + offset].  */
12870       needindex = (havesib
12871                    && !havebase
12872                    && !haveindex
12873                    && address_mode == mode_32bit);
12874       havedisp = (havebase
12875                   || needindex
12876                   || (havesib && (haveindex || scale != 0)));
12877
12878       if (!intel_syntax)
12879         if (modrm.mod != 0 || base == 5)
12880           {
12881             if (havedisp || riprel)
12882               print_displacement (scratchbuf, disp);
12883             else
12884               print_operand_value (scratchbuf, 1, disp);
12885             oappend (scratchbuf);
12886             if (riprel)
12887               {
12888                 set_op (disp, 1);
12889                 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
12890               }
12891           }
12892
12893       if (havebase || haveindex || riprel)
12894         used_prefixes |= PREFIX_ADDR;
12895
12896       if (havedisp || (intel_syntax && riprel))
12897         {
12898           *obufp++ = open_char;
12899           if (intel_syntax && riprel)
12900             {
12901               set_op (disp, 1);
12902               oappend (sizeflag & AFLAG ? "rip" : "eip");
12903             }
12904           *obufp = '\0';
12905           if (havebase)
12906             oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
12907                      ? names64[rbase] : names32[rbase]);
12908           if (havesib)
12909             {
12910               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
12911                  print index to tell base + index from base.  */
12912               if (scale != 0
12913                   || needindex
12914                   || haveindex
12915                   || (havebase && base != ESP_REG_NUM))
12916                 {
12917                   if (!intel_syntax || havebase)
12918                     {
12919                       *obufp++ = separator_char;
12920                       *obufp = '\0';
12921                     }
12922                   if (haveindex)
12923                     oappend (address_mode == mode_64bit
12924                              && (sizeflag & AFLAG)
12925                              ? names64[vindex] : names32[vindex]);
12926                   else
12927                     oappend (address_mode == mode_64bit
12928                              && (sizeflag & AFLAG)
12929                              ? index64 : index32);
12930
12931                   *obufp++ = scale_char;
12932                   *obufp = '\0';
12933                   sprintf (scratchbuf, "%d", 1 << scale);
12934                   oappend (scratchbuf);
12935                 }
12936             }
12937           if (intel_syntax
12938               && (disp || modrm.mod != 0 || base == 5))
12939             {
12940               if (!havedisp || (bfd_signed_vma) disp >= 0)
12941                 {
12942                   *obufp++ = '+';
12943                   *obufp = '\0';
12944                 }
12945               else if (modrm.mod != 1 && disp != -disp)
12946                 {
12947                   *obufp++ = '-';
12948                   *obufp = '\0';
12949                   disp = - (bfd_signed_vma) disp;
12950                 }
12951
12952               if (havedisp)
12953                 print_displacement (scratchbuf, disp);
12954               else
12955                 print_operand_value (scratchbuf, 1, disp);
12956               oappend (scratchbuf);
12957             }
12958
12959           *obufp++ = close_char;
12960           *obufp = '\0';
12961         }
12962       else if (intel_syntax)
12963         {
12964           if (modrm.mod != 0 || base == 5)
12965             {
12966               if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12967                               | PREFIX_ES | PREFIX_FS | PREFIX_GS))
12968                 ;
12969               else
12970                 {
12971                   oappend (names_seg[ds_reg - es_reg]);
12972                   oappend (":");
12973                 }
12974               print_operand_value (scratchbuf, 1, disp);
12975               oappend (scratchbuf);
12976             }
12977         }
12978     }
12979   else
12980     {
12981       /* 16 bit address mode */
12982       used_prefixes |= prefixes & PREFIX_ADDR;
12983       switch (modrm.mod)
12984         {
12985         case 0:
12986           if (modrm.rm == 6)
12987             {
12988               disp = get16 ();
12989               if ((disp & 0x8000) != 0)
12990                 disp -= 0x10000;
12991             }
12992           break;
12993         case 1:
12994           FETCH_DATA (the_info, codep + 1);
12995           disp = *codep++;
12996           if ((disp & 0x80) != 0)
12997             disp -= 0x100;
12998           break;
12999         case 2:
13000           disp = get16 ();
13001           if ((disp & 0x8000) != 0)
13002             disp -= 0x10000;
13003           break;
13004         }
13005
13006       if (!intel_syntax)
13007         if (modrm.mod != 0 || modrm.rm == 6)
13008           {
13009             print_displacement (scratchbuf, disp);
13010             oappend (scratchbuf);
13011           }
13012
13013       if (modrm.mod != 0 || modrm.rm != 6)
13014         {
13015           *obufp++ = open_char;
13016           *obufp = '\0';
13017           oappend (index16[modrm.rm]);
13018           if (intel_syntax
13019               && (disp || modrm.mod != 0 || modrm.rm == 6))
13020             {
13021               if ((bfd_signed_vma) disp >= 0)
13022                 {
13023                   *obufp++ = '+';
13024                   *obufp = '\0';
13025                 }
13026               else if (modrm.mod != 1)
13027                 {
13028                   *obufp++ = '-';
13029                   *obufp = '\0';
13030                   disp = - (bfd_signed_vma) disp;
13031                 }
13032
13033               print_displacement (scratchbuf, disp);
13034               oappend (scratchbuf);
13035             }
13036
13037           *obufp++ = close_char;
13038           *obufp = '\0';
13039         }
13040       else if (intel_syntax)
13041         {
13042           if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13043                           | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13044             ;
13045           else
13046             {
13047               oappend (names_seg[ds_reg - es_reg]);
13048               oappend (":");
13049             }
13050           print_operand_value (scratchbuf, 1, disp & 0xffff);
13051           oappend (scratchbuf);
13052         }
13053     }
13054 }
13055
13056 static void
13057 OP_E (int bytemode, int sizeflag)
13058 {
13059   /* Skip mod/rm byte.  */
13060   MODRM_CHECK;
13061   codep++;
13062
13063   if (modrm.mod == 3)
13064     OP_E_register (bytemode, sizeflag);
13065   else
13066     OP_E_memory (bytemode, sizeflag);
13067 }
13068
13069 static void
13070 OP_G (int bytemode, int sizeflag)
13071 {
13072   int add = 0;
13073   USED_REX (REX_R);
13074   if (rex & REX_R)
13075     add += 8;
13076   switch (bytemode)
13077     {
13078     case b_mode:
13079       USED_REX (0);
13080       if (rex)
13081         oappend (names8rex[modrm.reg + add]);
13082       else
13083         oappend (names8[modrm.reg + add]);
13084       break;
13085     case w_mode:
13086       oappend (names16[modrm.reg + add]);
13087       break;
13088     case d_mode:
13089       oappend (names32[modrm.reg + add]);
13090       break;
13091     case q_mode:
13092       oappend (names64[modrm.reg + add]);
13093       break;
13094     case v_mode:
13095     case dq_mode:
13096     case dqb_mode:
13097     case dqd_mode:
13098     case dqw_mode:
13099       USED_REX (REX_W);
13100       if (rex & REX_W)
13101         oappend (names64[modrm.reg + add]);
13102       else
13103         {
13104           if ((sizeflag & DFLAG) || bytemode != v_mode)
13105             oappend (names32[modrm.reg + add]);
13106           else
13107             oappend (names16[modrm.reg + add]);
13108           used_prefixes |= (prefixes & PREFIX_DATA);
13109         }
13110       break;
13111     case m_mode:
13112       if (address_mode == mode_64bit)
13113         oappend (names64[modrm.reg + add]);
13114       else
13115         oappend (names32[modrm.reg + add]);
13116       break;
13117     default:
13118       oappend (INTERNAL_DISASSEMBLER_ERROR);
13119       break;
13120     }
13121 }
13122
13123 static bfd_vma
13124 get64 (void)
13125 {
13126   bfd_vma x;
13127 #ifdef BFD64
13128   unsigned int a;
13129   unsigned int b;
13130
13131   FETCH_DATA (the_info, codep + 8);
13132   a = *codep++ & 0xff;
13133   a |= (*codep++ & 0xff) << 8;
13134   a |= (*codep++ & 0xff) << 16;
13135   a |= (*codep++ & 0xff) << 24;
13136   b = *codep++ & 0xff;
13137   b |= (*codep++ & 0xff) << 8;
13138   b |= (*codep++ & 0xff) << 16;
13139   b |= (*codep++ & 0xff) << 24;
13140   x = a + ((bfd_vma) b << 32);
13141 #else
13142   abort ();
13143   x = 0;
13144 #endif
13145   return x;
13146 }
13147
13148 static bfd_signed_vma
13149 get32 (void)
13150 {
13151   bfd_signed_vma x = 0;
13152
13153   FETCH_DATA (the_info, codep + 4);
13154   x = *codep++ & (bfd_signed_vma) 0xff;
13155   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13156   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13157   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13158   return x;
13159 }
13160
13161 static bfd_signed_vma
13162 get32s (void)
13163 {
13164   bfd_signed_vma x = 0;
13165
13166   FETCH_DATA (the_info, codep + 4);
13167   x = *codep++ & (bfd_signed_vma) 0xff;
13168   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13169   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13170   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13171
13172   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13173
13174   return x;
13175 }
13176
13177 static int
13178 get16 (void)
13179 {
13180   int x = 0;
13181
13182   FETCH_DATA (the_info, codep + 2);
13183   x = *codep++ & 0xff;
13184   x |= (*codep++ & 0xff) << 8;
13185   return x;
13186 }
13187
13188 static void
13189 set_op (bfd_vma op, int riprel)
13190 {
13191   op_index[op_ad] = op_ad;
13192   if (address_mode == mode_64bit)
13193     {
13194       op_address[op_ad] = op;
13195       op_riprel[op_ad] = riprel;
13196     }
13197   else
13198     {
13199       /* Mask to get a 32-bit address.  */
13200       op_address[op_ad] = op & 0xffffffff;
13201       op_riprel[op_ad] = riprel & 0xffffffff;
13202     }
13203 }
13204
13205 static void
13206 OP_REG (int code, int sizeflag)
13207 {
13208   const char *s;
13209   int add;
13210   USED_REX (REX_B);
13211   if (rex & REX_B)
13212     add = 8;
13213   else
13214     add = 0;
13215
13216   switch (code)
13217     {
13218     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13219     case sp_reg: case bp_reg: case si_reg: case di_reg:
13220       s = names16[code - ax_reg + add];
13221       break;
13222     case es_reg: case ss_reg: case cs_reg:
13223     case ds_reg: case fs_reg: case gs_reg:
13224       s = names_seg[code - es_reg + add];
13225       break;
13226     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13227     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13228       USED_REX (0);
13229       if (rex)
13230         s = names8rex[code - al_reg + add];
13231       else
13232         s = names8[code - al_reg];
13233       break;
13234     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13235     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13236       if (address_mode == mode_64bit && (sizeflag & DFLAG))
13237         {
13238           s = names64[code - rAX_reg + add];
13239           break;
13240         }
13241       code += eAX_reg - rAX_reg;
13242       /* Fall through.  */
13243     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13244     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13245       USED_REX (REX_W);
13246       if (rex & REX_W)
13247         s = names64[code - eAX_reg + add];
13248       else
13249         {
13250           if (sizeflag & DFLAG)
13251             s = names32[code - eAX_reg + add];
13252           else
13253             s = names16[code - eAX_reg + add];
13254           used_prefixes |= (prefixes & PREFIX_DATA);
13255         }
13256       break;
13257     default:
13258       s = INTERNAL_DISASSEMBLER_ERROR;
13259       break;
13260     }
13261   oappend (s);
13262 }
13263
13264 static void
13265 OP_IMREG (int code, int sizeflag)
13266 {
13267   const char *s;
13268
13269   switch (code)
13270     {
13271     case indir_dx_reg:
13272       if (intel_syntax)
13273         s = "dx";
13274       else
13275         s = "(%dx)";
13276       break;
13277     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13278     case sp_reg: case bp_reg: case si_reg: case di_reg:
13279       s = names16[code - ax_reg];
13280       break;
13281     case es_reg: case ss_reg: case cs_reg:
13282     case ds_reg: case fs_reg: case gs_reg:
13283       s = names_seg[code - es_reg];
13284       break;
13285     case al_reg: case ah_reg: case cl_reg: case ch_reg:
13286     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13287       USED_REX (0);
13288       if (rex)
13289         s = names8rex[code - al_reg];
13290       else
13291         s = names8[code - al_reg];
13292       break;
13293     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13294     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13295       USED_REX (REX_W);
13296       if (rex & REX_W)
13297         s = names64[code - eAX_reg];
13298       else
13299         {
13300           if (sizeflag & DFLAG)
13301             s = names32[code - eAX_reg];
13302           else
13303             s = names16[code - eAX_reg];
13304           used_prefixes |= (prefixes & PREFIX_DATA);
13305         }
13306       break;
13307     case z_mode_ax_reg:
13308       if ((rex & REX_W) || (sizeflag & DFLAG))
13309         s = *names32;
13310       else
13311         s = *names16;
13312       if (!(rex & REX_W))
13313         used_prefixes |= (prefixes & PREFIX_DATA);
13314       break;
13315     default:
13316       s = INTERNAL_DISASSEMBLER_ERROR;
13317       break;
13318     }
13319   oappend (s);
13320 }
13321
13322 static void
13323 OP_I (int bytemode, int sizeflag)
13324 {
13325   bfd_signed_vma op;
13326   bfd_signed_vma mask = -1;
13327
13328   switch (bytemode)
13329     {
13330     case b_mode:
13331       FETCH_DATA (the_info, codep + 1);
13332       op = *codep++;
13333       mask = 0xff;
13334       break;
13335     case q_mode:
13336       if (address_mode == mode_64bit)
13337         {
13338           op = get32s ();
13339           break;
13340         }
13341       /* Fall through.  */
13342     case v_mode:
13343       USED_REX (REX_W);
13344       if (rex & REX_W)
13345         op = get32s ();
13346       else
13347         {
13348           if (sizeflag & DFLAG)
13349             {
13350               op = get32 ();
13351               mask = 0xffffffff;
13352             }
13353           else
13354             {
13355               op = get16 ();
13356               mask = 0xfffff;
13357             }
13358           used_prefixes |= (prefixes & PREFIX_DATA);
13359         }
13360       break;
13361     case w_mode:
13362       mask = 0xfffff;
13363       op = get16 ();
13364       break;
13365     case const_1_mode:
13366       if (intel_syntax)
13367         oappend ("1");
13368       return;
13369     default:
13370       oappend (INTERNAL_DISASSEMBLER_ERROR);
13371       return;
13372     }
13373
13374   op &= mask;
13375   scratchbuf[0] = '$';
13376   print_operand_value (scratchbuf + 1, 1, op);
13377   oappend (scratchbuf + intel_syntax);
13378   scratchbuf[0] = '\0';
13379 }
13380
13381 static void
13382 OP_I64 (int bytemode, int sizeflag)
13383 {
13384   bfd_signed_vma op;
13385   bfd_signed_vma mask = -1;
13386
13387   if (address_mode != mode_64bit)
13388     {
13389       OP_I (bytemode, sizeflag);
13390       return;
13391     }
13392
13393   switch (bytemode)
13394     {
13395     case b_mode:
13396       FETCH_DATA (the_info, codep + 1);
13397       op = *codep++;
13398       mask = 0xff;
13399       break;
13400     case v_mode:
13401       USED_REX (REX_W);
13402       if (rex & REX_W)
13403         op = get64 ();
13404       else
13405         {
13406           if (sizeflag & DFLAG)
13407             {
13408               op = get32 ();
13409               mask = 0xffffffff;
13410             }
13411           else
13412             {
13413               op = get16 ();
13414               mask = 0xfffff;
13415             }
13416           used_prefixes |= (prefixes & PREFIX_DATA);
13417         }
13418       break;
13419     case w_mode:
13420       mask = 0xfffff;
13421       op = get16 ();
13422       break;
13423     default:
13424       oappend (INTERNAL_DISASSEMBLER_ERROR);
13425       return;
13426     }
13427
13428   op &= mask;
13429   scratchbuf[0] = '$';
13430   print_operand_value (scratchbuf + 1, 1, op);
13431   oappend (scratchbuf + intel_syntax);
13432   scratchbuf[0] = '\0';
13433 }
13434
13435 static void
13436 OP_sI (int bytemode, int sizeflag)
13437 {
13438   bfd_signed_vma op;
13439   bfd_signed_vma mask = -1;
13440
13441   switch (bytemode)
13442     {
13443     case b_mode:
13444       FETCH_DATA (the_info, codep + 1);
13445       op = *codep++;
13446       if ((op & 0x80) != 0)
13447         op -= 0x100;
13448       mask = 0xffffffff;
13449       break;
13450     case v_mode:
13451       USED_REX (REX_W);
13452       if (rex & REX_W)
13453         op = get32s ();
13454       else
13455         {
13456           if (sizeflag & DFLAG)
13457             {
13458               op = get32s ();
13459               mask = 0xffffffff;
13460             }
13461           else
13462             {
13463               mask = 0xffffffff;
13464               op = get16 ();
13465               if ((op & 0x8000) != 0)
13466                 op -= 0x10000;
13467             }
13468           used_prefixes |= (prefixes & PREFIX_DATA);
13469         }
13470       break;
13471     case w_mode:
13472       op = get16 ();
13473       mask = 0xffffffff;
13474       if ((op & 0x8000) != 0)
13475         op -= 0x10000;
13476       break;
13477     default:
13478       oappend (INTERNAL_DISASSEMBLER_ERROR);
13479       return;
13480     }
13481
13482   scratchbuf[0] = '$';
13483   print_operand_value (scratchbuf + 1, 1, op);
13484   oappend (scratchbuf + intel_syntax);
13485 }
13486
13487 static void
13488 OP_J (int bytemode, int sizeflag)
13489 {
13490   bfd_vma disp;
13491   bfd_vma mask = -1;
13492   bfd_vma segment = 0;
13493
13494   switch (bytemode)
13495     {
13496     case b_mode:
13497       FETCH_DATA (the_info, codep + 1);
13498       disp = *codep++;
13499       if ((disp & 0x80) != 0)
13500         disp -= 0x100;
13501       break;
13502     case v_mode:
13503       USED_REX (REX_W);
13504       if ((sizeflag & DFLAG) || (rex & REX_W))
13505         disp = get32s ();
13506       else
13507         {
13508           disp = get16 ();
13509           if ((disp & 0x8000) != 0)
13510             disp -= 0x10000;
13511           /* In 16bit mode, address is wrapped around at 64k within
13512              the same segment.  Otherwise, a data16 prefix on a jump
13513              instruction means that the pc is masked to 16 bits after
13514              the displacement is added!  */
13515           mask = 0xffff;
13516           if ((prefixes & PREFIX_DATA) == 0)
13517             segment = ((start_pc + codep - start_codep)
13518                        & ~((bfd_vma) 0xffff));
13519         }
13520       if (!(rex & REX_W))
13521         used_prefixes |= (prefixes & PREFIX_DATA);
13522       break;
13523     default:
13524       oappend (INTERNAL_DISASSEMBLER_ERROR);
13525       return;
13526     }
13527   disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
13528   set_op (disp, 0);
13529   print_operand_value (scratchbuf, 1, disp);
13530   oappend (scratchbuf);
13531 }
13532
13533 static void
13534 OP_SEG (int bytemode, int sizeflag)
13535 {
13536   if (bytemode == w_mode)
13537     oappend (names_seg[modrm.reg]);
13538   else
13539     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13540 }
13541
13542 static void
13543 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13544 {
13545   int seg, offset;
13546
13547   if (sizeflag & DFLAG)
13548     {
13549       offset = get32 ();
13550       seg = get16 ();
13551     }
13552   else
13553     {
13554       offset = get16 ();
13555       seg = get16 ();
13556     }
13557   used_prefixes |= (prefixes & PREFIX_DATA);
13558   if (intel_syntax)
13559     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13560   else
13561     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13562   oappend (scratchbuf);
13563 }
13564
13565 static void
13566 OP_OFF (int bytemode, int sizeflag)
13567 {
13568   bfd_vma off;
13569
13570   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13571     intel_operand_size (bytemode, sizeflag);
13572   append_seg ();
13573
13574   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13575     off = get32 ();
13576   else
13577     off = get16 ();
13578
13579   if (intel_syntax)
13580     {
13581       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13582                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13583         {
13584           oappend (names_seg[ds_reg - es_reg]);
13585           oappend (":");
13586         }
13587     }
13588   print_operand_value (scratchbuf, 1, off);
13589   oappend (scratchbuf);
13590 }
13591
13592 static void
13593 OP_OFF64 (int bytemode, int sizeflag)
13594 {
13595   bfd_vma off;
13596
13597   if (address_mode != mode_64bit
13598       || (prefixes & PREFIX_ADDR))
13599     {
13600       OP_OFF (bytemode, sizeflag);
13601       return;
13602     }
13603
13604   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13605     intel_operand_size (bytemode, sizeflag);
13606   append_seg ();
13607
13608   off = get64 ();
13609
13610   if (intel_syntax)
13611     {
13612       if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13613                         | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13614         {
13615           oappend (names_seg[ds_reg - es_reg]);
13616           oappend (":");
13617         }
13618     }
13619   print_operand_value (scratchbuf, 1, off);
13620   oappend (scratchbuf);
13621 }
13622
13623 static void
13624 ptr_reg (int code, int sizeflag)
13625 {
13626   const char *s;
13627
13628   *obufp++ = open_char;
13629   used_prefixes |= (prefixes & PREFIX_ADDR);
13630   if (address_mode == mode_64bit)
13631     {
13632       if (!(sizeflag & AFLAG))
13633         s = names32[code - eAX_reg];
13634       else
13635         s = names64[code - eAX_reg];
13636     }
13637   else if (sizeflag & AFLAG)
13638     s = names32[code - eAX_reg];
13639   else
13640     s = names16[code - eAX_reg];
13641   oappend (s);
13642   *obufp++ = close_char;
13643   *obufp = 0;
13644 }
13645
13646 static void
13647 OP_ESreg (int code, int sizeflag)
13648 {
13649   if (intel_syntax)
13650     {
13651       switch (codep[-1])
13652         {
13653         case 0x6d:      /* insw/insl */
13654           intel_operand_size (z_mode, sizeflag);
13655           break;
13656         case 0xa5:      /* movsw/movsl/movsq */
13657         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13658         case 0xab:      /* stosw/stosl */
13659         case 0xaf:      /* scasw/scasl */
13660           intel_operand_size (v_mode, sizeflag);
13661           break;
13662         default:
13663           intel_operand_size (b_mode, sizeflag);
13664         }
13665     }
13666   oappend ("%es:" + intel_syntax);
13667   ptr_reg (code, sizeflag);
13668 }
13669
13670 static void
13671 OP_DSreg (int code, int sizeflag)
13672 {
13673   if (intel_syntax)
13674     {
13675       switch (codep[-1])
13676         {
13677         case 0x6f:      /* outsw/outsl */
13678           intel_operand_size (z_mode, sizeflag);
13679           break;
13680         case 0xa5:      /* movsw/movsl/movsq */
13681         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
13682         case 0xad:      /* lodsw/lodsl/lodsq */
13683           intel_operand_size (v_mode, sizeflag);
13684           break;
13685         default:
13686           intel_operand_size (b_mode, sizeflag);
13687         }
13688     }
13689   if ((prefixes
13690        & (PREFIX_CS
13691           | PREFIX_DS
13692           | PREFIX_SS
13693           | PREFIX_ES
13694           | PREFIX_FS
13695           | PREFIX_GS)) == 0)
13696     prefixes |= PREFIX_DS;
13697   append_seg ();
13698   ptr_reg (code, sizeflag);
13699 }
13700
13701 static void
13702 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13703 {
13704   int add;
13705   if (rex & REX_R)
13706     {
13707       USED_REX (REX_R);
13708       add = 8;
13709     }
13710   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13711     {
13712       all_prefixes[last_lock_prefix] = 0;
13713       used_prefixes |= PREFIX_LOCK;
13714       add = 8;
13715     }
13716   else
13717     add = 0;
13718   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13719   oappend (scratchbuf + intel_syntax);
13720 }
13721
13722 static void
13723 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13724 {
13725   int add;
13726   USED_REX (REX_R);
13727   if (rex & REX_R)
13728     add = 8;
13729   else
13730     add = 0;
13731   if (intel_syntax)
13732     sprintf (scratchbuf, "db%d", modrm.reg + add);
13733   else
13734     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13735   oappend (scratchbuf);
13736 }
13737
13738 static void
13739 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13740 {
13741   sprintf (scratchbuf, "%%tr%d", modrm.reg);
13742   oappend (scratchbuf + intel_syntax);
13743 }
13744
13745 static void
13746 OP_R (int bytemode, int sizeflag)
13747 {
13748   if (modrm.mod == 3)
13749     OP_E (bytemode, sizeflag);
13750   else
13751     BadOp ();
13752 }
13753
13754 static void
13755 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13756 {
13757   int reg = modrm.reg;
13758   const char **names;
13759
13760   used_prefixes |= (prefixes & PREFIX_DATA);
13761   if (prefixes & PREFIX_DATA)
13762     {
13763       names = names_xmm;
13764       USED_REX (REX_R);
13765       if (rex & REX_R)
13766         reg += 8;
13767     }
13768   else
13769     names = names_mm;
13770   oappend (names[reg]);
13771 }
13772
13773 static void
13774 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13775 {
13776   int reg = modrm.reg;
13777   const char **names;
13778
13779   USED_REX (REX_R);
13780   if (rex & REX_R)
13781     reg += 8;
13782   if (need_vex && bytemode != xmm_mode)
13783     {
13784       switch (vex.length)
13785         {
13786         case 128:
13787           names = names_xmm;
13788           break;
13789         case 256:
13790           names = names_ymm;
13791           break;
13792         default:
13793           abort ();
13794         }
13795     }
13796   else
13797     names = names_xmm;
13798   oappend (names[reg]);
13799 }
13800
13801 static void
13802 OP_EM (int bytemode, int sizeflag)
13803 {
13804   int reg;
13805   const char **names;
13806
13807   if (modrm.mod != 3)
13808     {
13809       if (intel_syntax
13810           && (bytemode == v_mode || bytemode == v_swap_mode))
13811         {
13812           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13813           used_prefixes |= (prefixes & PREFIX_DATA);
13814         }
13815       OP_E (bytemode, sizeflag);
13816       return;
13817     }
13818
13819   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
13820     swap_operand ();
13821
13822   /* Skip mod/rm byte.  */
13823   MODRM_CHECK;
13824   codep++;
13825   used_prefixes |= (prefixes & PREFIX_DATA);
13826   reg = modrm.rm;
13827   if (prefixes & PREFIX_DATA)
13828     {
13829       names = names_xmm;
13830       USED_REX (REX_B);
13831       if (rex & REX_B)
13832         reg += 8;
13833     }
13834   else
13835     names = names_mm;
13836   oappend (names[reg]);
13837 }
13838
13839 /* cvt* are the only instructions in sse2 which have
13840    both SSE and MMX operands and also have 0x66 prefix
13841    in their opcode. 0x66 was originally used to differentiate
13842    between SSE and MMX instruction(operands). So we have to handle the
13843    cvt* separately using OP_EMC and OP_MXC */
13844 static void
13845 OP_EMC (int bytemode, int sizeflag)
13846 {
13847   if (modrm.mod != 3)
13848     {
13849       if (intel_syntax && bytemode == v_mode)
13850         {
13851           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
13852           used_prefixes |= (prefixes & PREFIX_DATA);
13853         }
13854       OP_E (bytemode, sizeflag);
13855       return;
13856     }
13857
13858   /* Skip mod/rm byte.  */
13859   MODRM_CHECK;
13860   codep++;
13861   used_prefixes |= (prefixes & PREFIX_DATA);
13862   oappend (names_mm[modrm.rm]);
13863 }
13864
13865 static void
13866 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13867 {
13868   used_prefixes |= (prefixes & PREFIX_DATA);
13869   oappend (names_mm[modrm.reg]);
13870 }
13871
13872 static void
13873 OP_EX (int bytemode, int sizeflag)
13874 {
13875   int reg;
13876   const char **names;
13877
13878   /* Skip mod/rm byte.  */
13879   MODRM_CHECK;
13880   codep++;
13881
13882   if (modrm.mod != 3)
13883     {
13884       OP_E_memory (bytemode, sizeflag);
13885       return;
13886     }
13887
13888   reg = modrm.rm;
13889   USED_REX (REX_B);
13890   if (rex & REX_B)
13891     reg += 8;
13892
13893   if ((sizeflag & SUFFIX_ALWAYS)
13894       && (bytemode == x_swap_mode
13895           || bytemode == d_swap_mode
13896           || bytemode == q_swap_mode))
13897     swap_operand ();
13898
13899   if (need_vex
13900       && bytemode != xmm_mode
13901       && bytemode != xmmq_mode)
13902     {
13903       switch (vex.length)
13904         {
13905         case 128:
13906           names = names_xmm;
13907           break;
13908         case 256:
13909           names = names_ymm;
13910           break;
13911         default:
13912           abort ();
13913         }
13914     }
13915   else
13916     names = names_xmm;
13917   oappend (names[reg]);
13918 }
13919
13920 static void
13921 OP_MS (int bytemode, int sizeflag)
13922 {
13923   if (modrm.mod == 3)
13924     OP_EM (bytemode, sizeflag);
13925   else
13926     BadOp ();
13927 }
13928
13929 static void
13930 OP_XS (int bytemode, int sizeflag)
13931 {
13932   if (modrm.mod == 3)
13933     OP_EX (bytemode, sizeflag);
13934   else
13935     BadOp ();
13936 }
13937
13938 static void
13939 OP_M (int bytemode, int sizeflag)
13940 {
13941   if (modrm.mod == 3)
13942     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13943     BadOp ();
13944   else
13945     OP_E (bytemode, sizeflag);
13946 }
13947
13948 static void
13949 OP_0f07 (int bytemode, int sizeflag)
13950 {
13951   if (modrm.mod != 3 || modrm.rm != 0)
13952     BadOp ();
13953   else
13954     OP_E (bytemode, sizeflag);
13955 }
13956
13957 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13958    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13959
13960 static void
13961 NOP_Fixup1 (int bytemode, int sizeflag)
13962 {
13963   if ((prefixes & PREFIX_DATA) != 0
13964       || (rex != 0
13965           && rex != 0x48
13966           && address_mode == mode_64bit))
13967     OP_REG (bytemode, sizeflag);
13968   else
13969     strcpy (obuf, "nop");
13970 }
13971
13972 static void
13973 NOP_Fixup2 (int bytemode, int sizeflag)
13974 {
13975   if ((prefixes & PREFIX_DATA) != 0
13976       || (rex != 0
13977           && rex != 0x48
13978           && address_mode == mode_64bit))
13979     OP_IMREG (bytemode, sizeflag);
13980 }
13981
13982 static const char *const Suffix3DNow[] = {
13983 /* 00 */        NULL,           NULL,           NULL,           NULL,
13984 /* 04 */        NULL,           NULL,           NULL,           NULL,
13985 /* 08 */        NULL,           NULL,           NULL,           NULL,
13986 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13987 /* 10 */        NULL,           NULL,           NULL,           NULL,
13988 /* 14 */        NULL,           NULL,           NULL,           NULL,
13989 /* 18 */        NULL,           NULL,           NULL,           NULL,
13990 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13991 /* 20 */        NULL,           NULL,           NULL,           NULL,
13992 /* 24 */        NULL,           NULL,           NULL,           NULL,
13993 /* 28 */        NULL,           NULL,           NULL,           NULL,
13994 /* 2C */        NULL,           NULL,           NULL,           NULL,
13995 /* 30 */        NULL,           NULL,           NULL,           NULL,
13996 /* 34 */        NULL,           NULL,           NULL,           NULL,
13997 /* 38 */        NULL,           NULL,           NULL,           NULL,
13998 /* 3C */        NULL,           NULL,           NULL,           NULL,
13999 /* 40 */        NULL,           NULL,           NULL,           NULL,
14000 /* 44 */        NULL,           NULL,           NULL,           NULL,
14001 /* 48 */        NULL,           NULL,           NULL,           NULL,
14002 /* 4C */        NULL,           NULL,           NULL,           NULL,
14003 /* 50 */        NULL,           NULL,           NULL,           NULL,
14004 /* 54 */        NULL,           NULL,           NULL,           NULL,
14005 /* 58 */        NULL,           NULL,           NULL,           NULL,
14006 /* 5C */        NULL,           NULL,           NULL,           NULL,
14007 /* 60 */        NULL,           NULL,           NULL,           NULL,
14008 /* 64 */        NULL,           NULL,           NULL,           NULL,
14009 /* 68 */        NULL,           NULL,           NULL,           NULL,
14010 /* 6C */        NULL,           NULL,           NULL,           NULL,
14011 /* 70 */        NULL,           NULL,           NULL,           NULL,
14012 /* 74 */        NULL,           NULL,           NULL,           NULL,
14013 /* 78 */        NULL,           NULL,           NULL,           NULL,
14014 /* 7C */        NULL,           NULL,           NULL,           NULL,
14015 /* 80 */        NULL,           NULL,           NULL,           NULL,
14016 /* 84 */        NULL,           NULL,           NULL,           NULL,
14017 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
14018 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
14019 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
14020 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
14021 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
14022 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
14023 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
14024 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
14025 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
14026 /* AC */        NULL,           NULL,           "pfacc",        NULL,
14027 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
14028 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
14029 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
14030 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
14031 /* C0 */        NULL,           NULL,           NULL,           NULL,
14032 /* C4 */        NULL,           NULL,           NULL,           NULL,
14033 /* C8 */        NULL,           NULL,           NULL,           NULL,
14034 /* CC */        NULL,           NULL,           NULL,           NULL,
14035 /* D0 */        NULL,           NULL,           NULL,           NULL,
14036 /* D4 */        NULL,           NULL,           NULL,           NULL,
14037 /* D8 */        NULL,           NULL,           NULL,           NULL,
14038 /* DC */        NULL,           NULL,           NULL,           NULL,
14039 /* E0 */        NULL,           NULL,           NULL,           NULL,
14040 /* E4 */        NULL,           NULL,           NULL,           NULL,
14041 /* E8 */        NULL,           NULL,           NULL,           NULL,
14042 /* EC */        NULL,           NULL,           NULL,           NULL,
14043 /* F0 */        NULL,           NULL,           NULL,           NULL,
14044 /* F4 */        NULL,           NULL,           NULL,           NULL,
14045 /* F8 */        NULL,           NULL,           NULL,           NULL,
14046 /* FC */        NULL,           NULL,           NULL,           NULL,
14047 };
14048
14049 static void
14050 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14051 {
14052   const char *mnemonic;
14053
14054   FETCH_DATA (the_info, codep + 1);
14055   /* AMD 3DNow! instructions are specified by an opcode suffix in the
14056      place where an 8-bit immediate would normally go.  ie. the last
14057      byte of the instruction.  */
14058   obufp = mnemonicendp;
14059   mnemonic = Suffix3DNow[*codep++ & 0xff];
14060   if (mnemonic)
14061     oappend (mnemonic);
14062   else
14063     {
14064       /* Since a variable sized modrm/sib chunk is between the start
14065          of the opcode (0x0f0f) and the opcode suffix, we need to do
14066          all the modrm processing first, and don't know until now that
14067          we have a bad opcode.  This necessitates some cleaning up.  */
14068       op_out[0][0] = '\0';
14069       op_out[1][0] = '\0';
14070       BadOp ();
14071     }
14072   mnemonicendp = obufp;
14073 }
14074
14075 static struct op simd_cmp_op[] =
14076 {
14077   { STRING_COMMA_LEN ("eq") },
14078   { STRING_COMMA_LEN ("lt") },
14079   { STRING_COMMA_LEN ("le") },
14080   { STRING_COMMA_LEN ("unord") },
14081   { STRING_COMMA_LEN ("neq") },
14082   { STRING_COMMA_LEN ("nlt") },
14083   { STRING_COMMA_LEN ("nle") },
14084   { STRING_COMMA_LEN ("ord") }
14085 };
14086
14087 static void
14088 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14089 {
14090   unsigned int cmp_type;
14091
14092   FETCH_DATA (the_info, codep + 1);
14093   cmp_type = *codep++ & 0xff;
14094   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14095     {
14096       char suffix [3];
14097       char *p = mnemonicendp - 2;
14098       suffix[0] = p[0];
14099       suffix[1] = p[1];
14100       suffix[2] = '\0';
14101       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14102       mnemonicendp += simd_cmp_op[cmp_type].len;
14103     }
14104   else
14105     {
14106       /* We have a reserved extension byte.  Output it directly.  */
14107       scratchbuf[0] = '$';
14108       print_operand_value (scratchbuf + 1, 1, cmp_type);
14109       oappend (scratchbuf + intel_syntax);
14110       scratchbuf[0] = '\0';
14111     }
14112 }
14113
14114 static void
14115 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14116           int sizeflag ATTRIBUTE_UNUSED)
14117 {
14118   /* mwait %eax,%ecx  */
14119   if (!intel_syntax)
14120     {
14121       const char **names = (address_mode == mode_64bit
14122                             ? names64 : names32);
14123       strcpy (op_out[0], names[0]);
14124       strcpy (op_out[1], names[1]);
14125       two_source_ops = 1;
14126     }
14127   /* Skip mod/rm byte.  */
14128   MODRM_CHECK;
14129   codep++;
14130 }
14131
14132 static void
14133 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14134             int sizeflag ATTRIBUTE_UNUSED)
14135 {
14136   /* monitor %eax,%ecx,%edx"  */
14137   if (!intel_syntax)
14138     {
14139       const char **op1_names;
14140       const char **names = (address_mode == mode_64bit
14141                             ? names64 : names32);
14142
14143       if (!(prefixes & PREFIX_ADDR))
14144         op1_names = (address_mode == mode_16bit
14145                      ? names16 : names);
14146       else
14147         {
14148           /* Remove "addr16/addr32".  */
14149           all_prefixes[last_addr_prefix] = 0;
14150           op1_names = (address_mode != mode_32bit
14151                        ? names32 : names16);
14152           used_prefixes |= PREFIX_ADDR;
14153         }
14154       strcpy (op_out[0], op1_names[0]);
14155       strcpy (op_out[1], names[1]);
14156       strcpy (op_out[2], names[2]);
14157       two_source_ops = 1;
14158     }
14159   /* Skip mod/rm byte.  */
14160   MODRM_CHECK;
14161   codep++;
14162 }
14163
14164 static void
14165 BadOp (void)
14166 {
14167   /* Throw away prefixes and 1st. opcode byte.  */
14168   codep = insn_codep + 1;
14169   oappend ("(bad)");
14170 }
14171
14172 static void
14173 REP_Fixup (int bytemode, int sizeflag)
14174 {
14175   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14176      lods and stos.  */
14177   if (prefixes & PREFIX_REPZ)
14178     all_prefixes[last_repz_prefix] = REP_PREFIX;
14179
14180   switch (bytemode)
14181     {
14182     case al_reg:
14183     case eAX_reg:
14184     case indir_dx_reg:
14185       OP_IMREG (bytemode, sizeflag);
14186       break;
14187     case eDI_reg:
14188       OP_ESreg (bytemode, sizeflag);
14189       break;
14190     case eSI_reg:
14191       OP_DSreg (bytemode, sizeflag);
14192       break;
14193     default:
14194       abort ();
14195       break;
14196     }
14197 }
14198
14199 static void
14200 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14201 {
14202   USED_REX (REX_W);
14203   if (rex & REX_W)
14204     {
14205       /* Change cmpxchg8b to cmpxchg16b.  */
14206       char *p = mnemonicendp - 2;
14207       mnemonicendp = stpcpy (p, "16b");
14208       bytemode = o_mode;
14209     }
14210   OP_M (bytemode, sizeflag);
14211 }
14212
14213 static void
14214 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14215 {
14216   const char **names;
14217
14218   if (need_vex)
14219     {
14220       switch (vex.length)
14221         {
14222         case 128:
14223           names = names_xmm;
14224           break;
14225         case 256:
14226           names = names_ymm;
14227           break;
14228         default:
14229           abort ();
14230         }
14231     }
14232   else
14233     names = names_xmm;
14234   oappend (names[reg]);
14235 }
14236
14237 static void
14238 CRC32_Fixup (int bytemode, int sizeflag)
14239 {
14240   /* Add proper suffix to "crc32".  */
14241   char *p = mnemonicendp;
14242
14243   switch (bytemode)
14244     {
14245     case b_mode:
14246       if (intel_syntax)
14247         goto skip;
14248
14249       *p++ = 'b';
14250       break;
14251     case v_mode:
14252       if (intel_syntax)
14253         goto skip;
14254
14255       USED_REX (REX_W);
14256       if (rex & REX_W)
14257         *p++ = 'q';
14258       else
14259         {
14260           if (sizeflag & DFLAG)
14261             *p++ = 'l';
14262           else
14263             *p++ = 'w';
14264           used_prefixes |= (prefixes & PREFIX_DATA);
14265         }
14266       break;
14267     default:
14268       oappend (INTERNAL_DISASSEMBLER_ERROR);
14269       break;
14270     }
14271   mnemonicendp = p;
14272   *p = '\0';
14273
14274 skip:
14275   if (modrm.mod == 3)
14276     {
14277       int add;
14278
14279       /* Skip mod/rm byte.  */
14280       MODRM_CHECK;
14281       codep++;
14282
14283       USED_REX (REX_B);
14284       add = (rex & REX_B) ? 8 : 0;
14285       if (bytemode == b_mode)
14286         {
14287           USED_REX (0);
14288           if (rex)
14289             oappend (names8rex[modrm.rm + add]);
14290           else
14291             oappend (names8[modrm.rm + add]);
14292         }
14293       else
14294         {
14295           USED_REX (REX_W);
14296           if (rex & REX_W)
14297             oappend (names64[modrm.rm + add]);
14298           else if ((prefixes & PREFIX_DATA))
14299             oappend (names16[modrm.rm + add]);
14300           else
14301             oappend (names32[modrm.rm + add]);
14302         }
14303     }
14304   else
14305     OP_E (bytemode, sizeflag);
14306 }
14307
14308 static void
14309 FXSAVE_Fixup (int bytemode, int sizeflag)
14310 {
14311   /* Add proper suffix to "fxsave" and "fxrstor".  */
14312   USED_REX (REX_W);
14313   if (rex & REX_W)
14314     {
14315       char *p = mnemonicendp;
14316       *p++ = '6';
14317       *p++ = '4';
14318       *p = '\0';
14319       mnemonicendp = p;
14320     }
14321   OP_M (bytemode, sizeflag);
14322 }
14323
14324 /* Display the destination register operand for instructions with
14325    VEX. */
14326
14327 static void
14328 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14329 {
14330   const char **names;
14331
14332   if (!need_vex)
14333     abort ();
14334
14335   if (!need_vex_reg)
14336     return;
14337
14338   switch (vex.length)
14339     {
14340     case 128:
14341       switch (bytemode)
14342         {
14343         case vex_mode:
14344         case vex128_mode:
14345           break;
14346         default:
14347           abort ();
14348           return;
14349         }
14350
14351       names = names_xmm;
14352       break;
14353     case 256:
14354       switch (bytemode)
14355         {
14356         case vex_mode:
14357         case vex256_mode:
14358           break;
14359         default:
14360           abort ();
14361           return;
14362         }
14363
14364       names = names_ymm;
14365       break;
14366     default:
14367       abort ();
14368       break;
14369     }
14370   oappend (names[vex.register_specifier]);
14371 }
14372
14373 /* Get the VEX immediate byte without moving codep.  */
14374
14375 static unsigned char
14376 get_vex_imm8 (int sizeflag, int opnum)
14377 {
14378   int bytes_before_imm = 0;
14379
14380   if (modrm.mod != 3)
14381     {
14382       /* There are SIB/displacement bytes.  */
14383       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14384         {
14385           /* 32/64 bit address mode */
14386           int base = modrm.rm;
14387
14388           /* Check SIB byte.  */
14389           if (base == 4)
14390             {
14391               FETCH_DATA (the_info, codep + 1);
14392               base = *codep & 7;
14393               /* When decoding the third source, don't increase
14394                  bytes_before_imm as this has already been incremented
14395                  by one in OP_E_memory while decoding the second
14396                  source operand.  */
14397               if (opnum == 0)
14398                 bytes_before_imm++;
14399             }
14400
14401           /* Don't increase bytes_before_imm when decoding the third source,
14402              it has already been incremented by OP_E_memory while decoding
14403              the second source operand.  */
14404           if (opnum == 0)
14405             {
14406               switch (modrm.mod)
14407                 {
14408                   case 0:
14409                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
14410                        SIB == 5, there is a 4 byte displacement.  */
14411                     if (base != 5)
14412                       /* No displacement. */
14413                       break;
14414                   case 2:
14415                     /* 4 byte displacement.  */
14416                     bytes_before_imm += 4;
14417                     break;
14418                   case 1:
14419                     /* 1 byte displacement.  */
14420                     bytes_before_imm++;
14421                     break;
14422                 }
14423             }
14424         }
14425       else
14426         {
14427           /* 16 bit address mode */
14428           /* Don't increase bytes_before_imm when decoding the third source,
14429              it has already been incremented by OP_E_memory while decoding
14430              the second source operand.  */
14431           if (opnum == 0)
14432             {
14433               switch (modrm.mod)
14434                 {
14435                 case 0:
14436                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
14437                   if (modrm.rm != 6)
14438                     /* No displacement. */
14439                     break;
14440                 case 2:
14441                   /* 2 byte displacement.  */
14442                   bytes_before_imm += 2;
14443                   break;
14444                 case 1:
14445                   /* 1 byte displacement: when decoding the third source,
14446                      don't increase bytes_before_imm as this has already
14447                      been incremented by one in OP_E_memory while decoding
14448                      the second source operand.  */
14449                   if (opnum == 0)
14450                     bytes_before_imm++;
14451
14452                   break;
14453                 }
14454             }
14455         }
14456     }
14457
14458   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14459   return codep [bytes_before_imm];
14460 }
14461
14462 static void
14463 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14464 {
14465   const char **names;
14466
14467   if (reg == -1 && modrm.mod != 3)
14468     {
14469       OP_E_memory (bytemode, sizeflag);
14470       return;
14471     }
14472   else
14473     {
14474       if (reg == -1)
14475         {
14476           reg = modrm.rm;
14477           USED_REX (REX_B);
14478           if (rex & REX_B)
14479             reg += 8;
14480         }
14481       else if (reg > 7 && address_mode != mode_64bit)
14482         BadOp ();
14483     }
14484
14485   switch (vex.length)
14486     {
14487     case 128:
14488       names = names_xmm;
14489       break;
14490     case 256:
14491       names = names_ymm;
14492       break;
14493     default:
14494       abort ();
14495     }
14496   oappend (names[reg]);
14497 }
14498
14499 static void
14500 OP_Vex_2src (int bytemode, int sizeflag)
14501 {
14502   if (modrm.mod == 3)
14503     {
14504       int reg = modrm.rm;
14505       USED_REX (REX_B);
14506       if (rex & REX_B)
14507         reg += 8;
14508       oappend (names_xmm[reg]);
14509     }
14510   else
14511     {
14512       if (intel_syntax
14513           && (bytemode == v_mode || bytemode == v_swap_mode))
14514         {
14515           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14516           used_prefixes |= (prefixes & PREFIX_DATA);
14517         }
14518       OP_E (bytemode, sizeflag);
14519     }
14520 }
14521
14522 static void
14523 OP_Vex_2src_1 (int bytemode, int sizeflag)
14524 {
14525   if (modrm.mod == 3)
14526     {
14527       /* Skip mod/rm byte.   */
14528       MODRM_CHECK;
14529       codep++;
14530     }
14531
14532   if (vex.w)
14533     oappend (names_xmm[vex.register_specifier]);
14534   else
14535     OP_Vex_2src (bytemode, sizeflag);
14536 }
14537
14538 static void
14539 OP_Vex_2src_2 (int bytemode, int sizeflag)
14540 {
14541   if (vex.w)
14542     OP_Vex_2src (bytemode, sizeflag);
14543   else
14544     oappend (names_xmm[vex.register_specifier]);
14545 }
14546
14547 static void
14548 OP_EX_VexW (int bytemode, int sizeflag)
14549 {
14550   int reg = -1;
14551
14552   if (!vex_w_done)
14553     {
14554       vex_w_done = 1;
14555
14556       /* Skip mod/rm byte.  */
14557       MODRM_CHECK;
14558       codep++;
14559
14560       if (vex.w)
14561         reg = get_vex_imm8 (sizeflag, 0) >> 4;
14562     }
14563   else
14564     {
14565       if (!vex.w)
14566         reg = get_vex_imm8 (sizeflag, 1) >> 4;
14567     }
14568
14569   OP_EX_VexReg (bytemode, sizeflag, reg);
14570 }
14571
14572 static void
14573 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14574              int sizeflag ATTRIBUTE_UNUSED)
14575 {
14576   /* Skip the immediate byte and check for invalid bits.  */
14577   FETCH_DATA (the_info, codep + 1);
14578   if (*codep++ & 0xf)
14579     BadOp ();
14580 }
14581
14582 static void
14583 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14584 {
14585   int reg;
14586   const char **names;
14587
14588   FETCH_DATA (the_info, codep + 1);
14589   reg = *codep++;
14590
14591   if (bytemode != x_mode)
14592     abort ();
14593
14594   if (reg & 0xf)
14595       BadOp ();
14596
14597   reg >>= 4;
14598   if (reg > 7 && address_mode != mode_64bit)
14599     BadOp ();
14600
14601   switch (vex.length)
14602     {
14603     case 128:
14604       names = names_xmm;
14605       break;
14606     case 256:
14607       names = names_ymm;
14608       break;
14609     default:
14610       abort ();
14611     }
14612   oappend (names[reg]);
14613 }
14614
14615 static void
14616 OP_XMM_VexW (int bytemode, int sizeflag)
14617 {
14618   /* Turn off the REX.W bit since it is used for swapping operands
14619      now.  */
14620   rex &= ~REX_W;
14621   OP_XMM (bytemode, sizeflag);
14622 }
14623
14624 static void
14625 OP_EX_Vex (int bytemode, int sizeflag)
14626 {
14627   if (modrm.mod != 3)
14628     {
14629       if (vex.register_specifier != 0)
14630         BadOp ();
14631       need_vex_reg = 0;
14632     }
14633   OP_EX (bytemode, sizeflag);
14634 }
14635
14636 static void
14637 OP_XMM_Vex (int bytemode, int sizeflag)
14638 {
14639   if (modrm.mod != 3)
14640     {
14641       if (vex.register_specifier != 0)
14642         BadOp ();
14643       need_vex_reg = 0;
14644     }
14645   OP_XMM (bytemode, sizeflag);
14646 }
14647
14648 static void
14649 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14650 {
14651   switch (vex.length)
14652     {
14653     case 128:
14654       mnemonicendp = stpcpy (obuf, "vzeroupper");
14655       break;
14656     case 256:
14657       mnemonicendp = stpcpy (obuf, "vzeroall");
14658       break;
14659     default:
14660       abort ();
14661     }
14662 }
14663
14664 static struct op vex_cmp_op[] =
14665 {
14666   { STRING_COMMA_LEN ("eq") },
14667   { STRING_COMMA_LEN ("lt") },
14668   { STRING_COMMA_LEN ("le") },
14669   { STRING_COMMA_LEN ("unord") },
14670   { STRING_COMMA_LEN ("neq") },
14671   { STRING_COMMA_LEN ("nlt") },
14672   { STRING_COMMA_LEN ("nle") },
14673   { STRING_COMMA_LEN ("ord") },
14674   { STRING_COMMA_LEN ("eq_uq") },
14675   { STRING_COMMA_LEN ("nge") },
14676   { STRING_COMMA_LEN ("ngt") },
14677   { STRING_COMMA_LEN ("false") },
14678   { STRING_COMMA_LEN ("neq_oq") },
14679   { STRING_COMMA_LEN ("ge") },
14680   { STRING_COMMA_LEN ("gt") },
14681   { STRING_COMMA_LEN ("true") },
14682   { STRING_COMMA_LEN ("eq_os") },
14683   { STRING_COMMA_LEN ("lt_oq") },
14684   { STRING_COMMA_LEN ("le_oq") },
14685   { STRING_COMMA_LEN ("unord_s") },
14686   { STRING_COMMA_LEN ("neq_us") },
14687   { STRING_COMMA_LEN ("nlt_uq") },
14688   { STRING_COMMA_LEN ("nle_uq") },
14689   { STRING_COMMA_LEN ("ord_s") },
14690   { STRING_COMMA_LEN ("eq_us") },
14691   { STRING_COMMA_LEN ("nge_uq") },
14692   { STRING_COMMA_LEN ("ngt_uq") },
14693   { STRING_COMMA_LEN ("false_os") },
14694   { STRING_COMMA_LEN ("neq_os") },
14695   { STRING_COMMA_LEN ("ge_oq") },
14696   { STRING_COMMA_LEN ("gt_oq") },
14697   { STRING_COMMA_LEN ("true_us") },
14698 };
14699
14700 static void
14701 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14702 {
14703   unsigned int cmp_type;
14704
14705   FETCH_DATA (the_info, codep + 1);
14706   cmp_type = *codep++ & 0xff;
14707   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
14708     {
14709       char suffix [3];
14710       char *p = mnemonicendp - 2;
14711       suffix[0] = p[0];
14712       suffix[1] = p[1];
14713       suffix[2] = '\0';
14714       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
14715       mnemonicendp += vex_cmp_op[cmp_type].len;
14716     }
14717   else
14718     {
14719       /* We have a reserved extension byte.  Output it directly.  */
14720       scratchbuf[0] = '$';
14721       print_operand_value (scratchbuf + 1, 1, cmp_type);
14722       oappend (scratchbuf + intel_syntax);
14723       scratchbuf[0] = '\0';
14724     }
14725 }
14726
14727 static const struct op pclmul_op[] =
14728 {
14729   { STRING_COMMA_LEN ("lql") },
14730   { STRING_COMMA_LEN ("hql") },
14731   { STRING_COMMA_LEN ("lqh") },
14732   { STRING_COMMA_LEN ("hqh") }
14733 };
14734
14735 static void
14736 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
14737               int sizeflag ATTRIBUTE_UNUSED)
14738 {
14739   unsigned int pclmul_type;
14740
14741   FETCH_DATA (the_info, codep + 1);
14742   pclmul_type = *codep++ & 0xff;
14743   switch (pclmul_type)
14744     {
14745     case 0x10:
14746       pclmul_type = 2;
14747       break;
14748     case 0x11:
14749       pclmul_type = 3;
14750       break;
14751     default:
14752       break;
14753     }
14754   if (pclmul_type < ARRAY_SIZE (pclmul_op))
14755     {
14756       char suffix [4];
14757       char *p = mnemonicendp - 3;
14758       suffix[0] = p[0];
14759       suffix[1] = p[1];
14760       suffix[2] = p[2];
14761       suffix[3] = '\0';
14762       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
14763       mnemonicendp += pclmul_op[pclmul_type].len;
14764     }
14765   else
14766     {
14767       /* We have a reserved extension byte.  Output it directly.  */
14768       scratchbuf[0] = '$';
14769       print_operand_value (scratchbuf + 1, 1, pclmul_type);
14770       oappend (scratchbuf + intel_syntax);
14771       scratchbuf[0] = '\0';
14772     }
14773 }
14774
14775 static void
14776 MOVBE_Fixup (int bytemode, int sizeflag)
14777 {
14778   /* Add proper suffix to "movbe".  */
14779   char *p = mnemonicendp;
14780
14781   switch (bytemode)
14782     {
14783     case v_mode:
14784       if (intel_syntax)
14785         goto skip;
14786
14787       USED_REX (REX_W);
14788       if (sizeflag & SUFFIX_ALWAYS)
14789         {
14790           if (rex & REX_W)
14791             *p++ = 'q';
14792           else
14793             {
14794               if (sizeflag & DFLAG)
14795                 *p++ = 'l';
14796               else
14797                 *p++ = 'w';
14798               used_prefixes |= (prefixes & PREFIX_DATA);
14799             }
14800         }
14801       break;
14802     default:
14803       oappend (INTERNAL_DISASSEMBLER_ERROR);
14804       break;
14805     }
14806   mnemonicendp = p;
14807   *p = '\0';
14808
14809 skip:
14810   OP_M (bytemode, sizeflag);
14811 }
14812
14813 static void
14814 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14815 {
14816   int reg;
14817   const char **names;
14818
14819   /* Skip mod/rm byte.  */
14820   MODRM_CHECK;
14821   codep++;
14822
14823   if (vex.w)
14824     names = names64;
14825   else if (vex.length == 256)
14826     names = names32;
14827   else
14828     names = names16;
14829
14830   reg = modrm.rm;
14831   USED_REX (REX_B);
14832   if (rex & REX_B)
14833     reg += 8;
14834
14835   oappend (names[reg]);
14836 }
14837
14838 static void
14839 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14840 {
14841   const char **names;
14842
14843   if (vex.w)
14844     names = names64;
14845   else if (vex.length == 256)
14846     names = names32;
14847   else
14848     names = names16;
14849
14850   oappend (names[vex.register_specifier]);
14851 }
14852
14853 static void
14854 OP_LWP_I (int bytemode ATTRIBUTE_UNUSED, int sizeflag)
14855 {
14856   if (vex.w || vex.length == 256)
14857     OP_I (q_mode, sizeflag);
14858   else
14859     OP_I (w_mode, sizeflag);
14860 }
14861