1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
134 OPCODES_SIGJMP_BUF bailout
;
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode
,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode
,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode
,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode
,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
800 MOD_VEX_0F12_PREFIX_0
,
802 MOD_VEX_0F16_PREFIX_0
,
818 MOD_VEX_0FD7_PREFIX_2
,
819 MOD_VEX_0FE7_PREFIX_2
,
820 MOD_VEX_0FF0_PREFIX_3
,
821 MOD_VEX_0F381A_PREFIX_2
,
822 MOD_VEX_0F382A_PREFIX_2
,
823 MOD_VEX_0F382C_PREFIX_2
,
824 MOD_VEX_0F382D_PREFIX_2
,
825 MOD_VEX_0F382E_PREFIX_2
,
826 MOD_VEX_0F382F_PREFIX_2
,
827 MOD_VEX_0F385A_PREFIX_2
,
828 MOD_VEX_0F388C_PREFIX_2
,
829 MOD_VEX_0F388E_PREFIX_2
,
831 MOD_EVEX_0F10_PREFIX_1
,
832 MOD_EVEX_0F10_PREFIX_3
,
833 MOD_EVEX_0F11_PREFIX_1
,
834 MOD_EVEX_0F11_PREFIX_3
,
835 MOD_EVEX_0F12_PREFIX_0
,
836 MOD_EVEX_0F16_PREFIX_0
,
837 MOD_EVEX_0F38C6_REG_1
,
838 MOD_EVEX_0F38C6_REG_2
,
839 MOD_EVEX_0F38C6_REG_5
,
840 MOD_EVEX_0F38C6_REG_6
,
841 MOD_EVEX_0F38C7_REG_1
,
842 MOD_EVEX_0F38C7_REG_2
,
843 MOD_EVEX_0F38C7_REG_5
,
844 MOD_EVEX_0F38C7_REG_6
1036 PREFIX_VEX_0F71_REG_2
,
1037 PREFIX_VEX_0F71_REG_4
,
1038 PREFIX_VEX_0F71_REG_6
,
1039 PREFIX_VEX_0F72_REG_2
,
1040 PREFIX_VEX_0F72_REG_4
,
1041 PREFIX_VEX_0F72_REG_6
,
1042 PREFIX_VEX_0F73_REG_2
,
1043 PREFIX_VEX_0F73_REG_3
,
1044 PREFIX_VEX_0F73_REG_6
,
1045 PREFIX_VEX_0F73_REG_7
,
1217 PREFIX_VEX_0F38F3_REG_1
,
1218 PREFIX_VEX_0F38F3_REG_2
,
1219 PREFIX_VEX_0F38F3_REG_3
,
1336 PREFIX_EVEX_0F71_REG_2
,
1337 PREFIX_EVEX_0F71_REG_4
,
1338 PREFIX_EVEX_0F71_REG_6
,
1339 PREFIX_EVEX_0F72_REG_0
,
1340 PREFIX_EVEX_0F72_REG_1
,
1341 PREFIX_EVEX_0F72_REG_2
,
1342 PREFIX_EVEX_0F72_REG_4
,
1343 PREFIX_EVEX_0F72_REG_6
,
1344 PREFIX_EVEX_0F73_REG_2
,
1345 PREFIX_EVEX_0F73_REG_3
,
1346 PREFIX_EVEX_0F73_REG_6
,
1347 PREFIX_EVEX_0F73_REG_7
,
1527 PREFIX_EVEX_0F38C6_REG_1
,
1528 PREFIX_EVEX_0F38C6_REG_2
,
1529 PREFIX_EVEX_0F38C6_REG_5
,
1530 PREFIX_EVEX_0F38C6_REG_6
,
1531 PREFIX_EVEX_0F38C7_REG_1
,
1532 PREFIX_EVEX_0F38C7_REG_2
,
1533 PREFIX_EVEX_0F38C7_REG_5
,
1534 PREFIX_EVEX_0F38C7_REG_6
,
1621 THREE_BYTE_0F38
= 0,
1649 VEX_LEN_0F10_P_1
= 0,
1653 VEX_LEN_0F12_P_0_M_0
,
1654 VEX_LEN_0F12_P_0_M_1
,
1657 VEX_LEN_0F16_P_0_M_0
,
1658 VEX_LEN_0F16_P_0_M_1
,
1722 VEX_LEN_0FAE_R_2_M_0
,
1723 VEX_LEN_0FAE_R_3_M_0
,
1732 VEX_LEN_0F381A_P_2_M_0
,
1735 VEX_LEN_0F385A_P_2_M_0
,
1742 VEX_LEN_0F38F3_R_1_P_0
,
1743 VEX_LEN_0F38F3_R_2_P_0
,
1744 VEX_LEN_0F38F3_R_3_P_0
,
1790 VEX_LEN_0FXOP_08_CC
,
1791 VEX_LEN_0FXOP_08_CD
,
1792 VEX_LEN_0FXOP_08_CE
,
1793 VEX_LEN_0FXOP_08_CF
,
1794 VEX_LEN_0FXOP_08_EC
,
1795 VEX_LEN_0FXOP_08_ED
,
1796 VEX_LEN_0FXOP_08_EE
,
1797 VEX_LEN_0FXOP_08_EF
,
1798 VEX_LEN_0FXOP_09_80
,
1832 VEX_W_0F41_P_0_LEN_1
,
1833 VEX_W_0F41_P_2_LEN_1
,
1834 VEX_W_0F42_P_0_LEN_1
,
1835 VEX_W_0F42_P_2_LEN_1
,
1836 VEX_W_0F44_P_0_LEN_0
,
1837 VEX_W_0F44_P_2_LEN_0
,
1838 VEX_W_0F45_P_0_LEN_1
,
1839 VEX_W_0F45_P_2_LEN_1
,
1840 VEX_W_0F46_P_0_LEN_1
,
1841 VEX_W_0F46_P_2_LEN_1
,
1842 VEX_W_0F47_P_0_LEN_1
,
1843 VEX_W_0F47_P_2_LEN_1
,
1844 VEX_W_0F4A_P_0_LEN_1
,
1845 VEX_W_0F4A_P_2_LEN_1
,
1846 VEX_W_0F4B_P_0_LEN_1
,
1847 VEX_W_0F4B_P_2_LEN_1
,
1927 VEX_W_0F90_P_0_LEN_0
,
1928 VEX_W_0F90_P_2_LEN_0
,
1929 VEX_W_0F91_P_0_LEN_0
,
1930 VEX_W_0F91_P_2_LEN_0
,
1931 VEX_W_0F92_P_0_LEN_0
,
1932 VEX_W_0F92_P_2_LEN_0
,
1933 VEX_W_0F92_P_3_LEN_0
,
1934 VEX_W_0F93_P_0_LEN_0
,
1935 VEX_W_0F93_P_2_LEN_0
,
1936 VEX_W_0F93_P_3_LEN_0
,
1937 VEX_W_0F98_P_0_LEN_0
,
1938 VEX_W_0F98_P_2_LEN_0
,
1939 VEX_W_0F99_P_0_LEN_0
,
1940 VEX_W_0F99_P_2_LEN_0
,
2019 VEX_W_0F381A_P_2_M_0
,
2031 VEX_W_0F382A_P_2_M_0
,
2033 VEX_W_0F382C_P_2_M_0
,
2034 VEX_W_0F382D_P_2_M_0
,
2035 VEX_W_0F382E_P_2_M_0
,
2036 VEX_W_0F382F_P_2_M_0
,
2058 VEX_W_0F385A_P_2_M_0
,
2086 VEX_W_0F3A30_P_2_LEN_0
,
2087 VEX_W_0F3A31_P_2_LEN_0
,
2088 VEX_W_0F3A32_P_2_LEN_0
,
2089 VEX_W_0F3A33_P_2_LEN_0
,
2109 EVEX_W_0F10_P_1_M_0
,
2110 EVEX_W_0F10_P_1_M_1
,
2112 EVEX_W_0F10_P_3_M_0
,
2113 EVEX_W_0F10_P_3_M_1
,
2115 EVEX_W_0F11_P_1_M_0
,
2116 EVEX_W_0F11_P_1_M_1
,
2118 EVEX_W_0F11_P_3_M_0
,
2119 EVEX_W_0F11_P_3_M_1
,
2120 EVEX_W_0F12_P_0_M_0
,
2121 EVEX_W_0F12_P_0_M_1
,
2131 EVEX_W_0F16_P_0_M_0
,
2132 EVEX_W_0F16_P_0_M_1
,
2203 EVEX_W_0F72_R_2_P_2
,
2204 EVEX_W_0F72_R_6_P_2
,
2205 EVEX_W_0F73_R_2_P_2
,
2206 EVEX_W_0F73_R_6_P_2
,
2305 EVEX_W_0F38C7_R_1_P_2
,
2306 EVEX_W_0F38C7_R_2_P_2
,
2307 EVEX_W_0F38C7_R_5_P_2
,
2308 EVEX_W_0F38C7_R_6_P_2
,
2343 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2354 /* Upper case letters in the instruction names here are macros.
2355 'A' => print 'b' if no register operands or suffix_always is true
2356 'B' => print 'b' if suffix_always is true
2357 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2359 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2360 suffix_always is true
2361 'E' => print 'e' if 32-bit form of jcxz
2362 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2363 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2364 'H' => print ",pt" or ",pn" branch hint
2365 'I' => honor following macro letter even in Intel mode (implemented only
2366 for some of the macro letters)
2368 'K' => print 'd' or 'q' if rex prefix is present.
2369 'L' => print 'l' if suffix_always is true
2370 'M' => print 'r' if intel_mnemonic is false.
2371 'N' => print 'n' if instruction has no wait "prefix"
2372 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2373 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2374 or suffix_always is true. print 'q' if rex prefix is present.
2375 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2377 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2378 'S' => print 'w', 'l' or 'q' if suffix_always is true
2379 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2380 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2381 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2382 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2383 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2384 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2385 suffix_always is true.
2386 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2387 '!' => change condition from true to false or from false to true.
2388 '%' => add 1 upper case letter to the macro.
2390 2 upper case letter macros:
2391 "XY" => print 'x' or 'y' if no register operands or suffix_always
2393 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2394 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2395 or suffix_always is true
2396 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2397 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2398 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2399 "LW" => print 'd', 'q' depending on the VEX.W bit
2400 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2401 an operand size prefix, or suffix_always is true. print
2402 'q' if rex prefix is present.
2404 Many of the above letters print nothing in Intel mode. See "putop"
2407 Braces '{' and '}', and vertical bars '|', indicate alternative
2408 mnemonic strings for AT&T and Intel. */
2410 static const struct dis386 dis386
[] = {
2412 { "addB", { Ebh1
, Gb
} },
2413 { "addS", { Evh1
, Gv
} },
2414 { "addB", { Gb
, EbS
} },
2415 { "addS", { Gv
, EvS
} },
2416 { "addB", { AL
, Ib
} },
2417 { "addS", { eAX
, Iv
} },
2418 { X86_64_TABLE (X86_64_06
) },
2419 { X86_64_TABLE (X86_64_07
) },
2421 { "orB", { Ebh1
, Gb
} },
2422 { "orS", { Evh1
, Gv
} },
2423 { "orB", { Gb
, EbS
} },
2424 { "orS", { Gv
, EvS
} },
2425 { "orB", { AL
, Ib
} },
2426 { "orS", { eAX
, Iv
} },
2427 { X86_64_TABLE (X86_64_0D
) },
2428 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2430 { "adcB", { Ebh1
, Gb
} },
2431 { "adcS", { Evh1
, Gv
} },
2432 { "adcB", { Gb
, EbS
} },
2433 { "adcS", { Gv
, EvS
} },
2434 { "adcB", { AL
, Ib
} },
2435 { "adcS", { eAX
, Iv
} },
2436 { X86_64_TABLE (X86_64_16
) },
2437 { X86_64_TABLE (X86_64_17
) },
2439 { "sbbB", { Ebh1
, Gb
} },
2440 { "sbbS", { Evh1
, Gv
} },
2441 { "sbbB", { Gb
, EbS
} },
2442 { "sbbS", { Gv
, EvS
} },
2443 { "sbbB", { AL
, Ib
} },
2444 { "sbbS", { eAX
, Iv
} },
2445 { X86_64_TABLE (X86_64_1E
) },
2446 { X86_64_TABLE (X86_64_1F
) },
2448 { "andB", { Ebh1
, Gb
} },
2449 { "andS", { Evh1
, Gv
} },
2450 { "andB", { Gb
, EbS
} },
2451 { "andS", { Gv
, EvS
} },
2452 { "andB", { AL
, Ib
} },
2453 { "andS", { eAX
, Iv
} },
2454 { Bad_Opcode
}, /* SEG ES prefix */
2455 { X86_64_TABLE (X86_64_27
) },
2457 { "subB", { Ebh1
, Gb
} },
2458 { "subS", { Evh1
, Gv
} },
2459 { "subB", { Gb
, EbS
} },
2460 { "subS", { Gv
, EvS
} },
2461 { "subB", { AL
, Ib
} },
2462 { "subS", { eAX
, Iv
} },
2463 { Bad_Opcode
}, /* SEG CS prefix */
2464 { X86_64_TABLE (X86_64_2F
) },
2466 { "xorB", { Ebh1
, Gb
} },
2467 { "xorS", { Evh1
, Gv
} },
2468 { "xorB", { Gb
, EbS
} },
2469 { "xorS", { Gv
, EvS
} },
2470 { "xorB", { AL
, Ib
} },
2471 { "xorS", { eAX
, Iv
} },
2472 { Bad_Opcode
}, /* SEG SS prefix */
2473 { X86_64_TABLE (X86_64_37
) },
2475 { "cmpB", { Eb
, Gb
} },
2476 { "cmpS", { Ev
, Gv
} },
2477 { "cmpB", { Gb
, EbS
} },
2478 { "cmpS", { Gv
, EvS
} },
2479 { "cmpB", { AL
, Ib
} },
2480 { "cmpS", { eAX
, Iv
} },
2481 { Bad_Opcode
}, /* SEG DS prefix */
2482 { X86_64_TABLE (X86_64_3F
) },
2484 { "inc{S|}", { RMeAX
} },
2485 { "inc{S|}", { RMeCX
} },
2486 { "inc{S|}", { RMeDX
} },
2487 { "inc{S|}", { RMeBX
} },
2488 { "inc{S|}", { RMeSP
} },
2489 { "inc{S|}", { RMeBP
} },
2490 { "inc{S|}", { RMeSI
} },
2491 { "inc{S|}", { RMeDI
} },
2493 { "dec{S|}", { RMeAX
} },
2494 { "dec{S|}", { RMeCX
} },
2495 { "dec{S|}", { RMeDX
} },
2496 { "dec{S|}", { RMeBX
} },
2497 { "dec{S|}", { RMeSP
} },
2498 { "dec{S|}", { RMeBP
} },
2499 { "dec{S|}", { RMeSI
} },
2500 { "dec{S|}", { RMeDI
} },
2502 { "pushV", { RMrAX
} },
2503 { "pushV", { RMrCX
} },
2504 { "pushV", { RMrDX
} },
2505 { "pushV", { RMrBX
} },
2506 { "pushV", { RMrSP
} },
2507 { "pushV", { RMrBP
} },
2508 { "pushV", { RMrSI
} },
2509 { "pushV", { RMrDI
} },
2511 { "popV", { RMrAX
} },
2512 { "popV", { RMrCX
} },
2513 { "popV", { RMrDX
} },
2514 { "popV", { RMrBX
} },
2515 { "popV", { RMrSP
} },
2516 { "popV", { RMrBP
} },
2517 { "popV", { RMrSI
} },
2518 { "popV", { RMrDI
} },
2520 { X86_64_TABLE (X86_64_60
) },
2521 { X86_64_TABLE (X86_64_61
) },
2522 { X86_64_TABLE (X86_64_62
) },
2523 { X86_64_TABLE (X86_64_63
) },
2524 { Bad_Opcode
}, /* seg fs */
2525 { Bad_Opcode
}, /* seg gs */
2526 { Bad_Opcode
}, /* op size prefix */
2527 { Bad_Opcode
}, /* adr size prefix */
2529 { "pushT", { sIv
} },
2530 { "imulS", { Gv
, Ev
, Iv
} },
2531 { "pushT", { sIbT
} },
2532 { "imulS", { Gv
, Ev
, sIb
} },
2533 { "ins{b|}", { Ybr
, indirDX
} },
2534 { X86_64_TABLE (X86_64_6D
) },
2535 { "outs{b|}", { indirDXr
, Xb
} },
2536 { X86_64_TABLE (X86_64_6F
) },
2538 { "joH", { Jb
, BND
, cond_jump_flag
} },
2539 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2540 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2541 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2542 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2543 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2544 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2545 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2547 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2548 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2549 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2550 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2551 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2552 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2553 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2554 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2556 { REG_TABLE (REG_80
) },
2557 { REG_TABLE (REG_81
) },
2559 { REG_TABLE (REG_82
) },
2560 { "testB", { Eb
, Gb
} },
2561 { "testS", { Ev
, Gv
} },
2562 { "xchgB", { Ebh2
, Gb
} },
2563 { "xchgS", { Evh2
, Gv
} },
2565 { "movB", { Ebh3
, Gb
} },
2566 { "movS", { Evh3
, Gv
} },
2567 { "movB", { Gb
, EbS
} },
2568 { "movS", { Gv
, EvS
} },
2569 { "movD", { Sv
, Sw
} },
2570 { MOD_TABLE (MOD_8D
) },
2571 { "movD", { Sw
, Sv
} },
2572 { REG_TABLE (REG_8F
) },
2574 { PREFIX_TABLE (PREFIX_90
) },
2575 { "xchgS", { RMeCX
, eAX
} },
2576 { "xchgS", { RMeDX
, eAX
} },
2577 { "xchgS", { RMeBX
, eAX
} },
2578 { "xchgS", { RMeSP
, eAX
} },
2579 { "xchgS", { RMeBP
, eAX
} },
2580 { "xchgS", { RMeSI
, eAX
} },
2581 { "xchgS", { RMeDI
, eAX
} },
2583 { "cW{t|}R", { XX
} },
2584 { "cR{t|}O", { XX
} },
2585 { X86_64_TABLE (X86_64_9A
) },
2586 { Bad_Opcode
}, /* fwait */
2587 { "pushfT", { XX
} },
2588 { "popfT", { XX
} },
2592 { "mov%LB", { AL
, Ob
} },
2593 { "mov%LS", { eAX
, Ov
} },
2594 { "mov%LB", { Ob
, AL
} },
2595 { "mov%LS", { Ov
, eAX
} },
2596 { "movs{b|}", { Ybr
, Xb
} },
2597 { "movs{R|}", { Yvr
, Xv
} },
2598 { "cmps{b|}", { Xb
, Yb
} },
2599 { "cmps{R|}", { Xv
, Yv
} },
2601 { "testB", { AL
, Ib
} },
2602 { "testS", { eAX
, Iv
} },
2603 { "stosB", { Ybr
, AL
} },
2604 { "stosS", { Yvr
, eAX
} },
2605 { "lodsB", { ALr
, Xb
} },
2606 { "lodsS", { eAXr
, Xv
} },
2607 { "scasB", { AL
, Yb
} },
2608 { "scasS", { eAX
, Yv
} },
2610 { "movB", { RMAL
, Ib
} },
2611 { "movB", { RMCL
, Ib
} },
2612 { "movB", { RMDL
, Ib
} },
2613 { "movB", { RMBL
, Ib
} },
2614 { "movB", { RMAH
, Ib
} },
2615 { "movB", { RMCH
, Ib
} },
2616 { "movB", { RMDH
, Ib
} },
2617 { "movB", { RMBH
, Ib
} },
2619 { "mov%LV", { RMeAX
, Iv64
} },
2620 { "mov%LV", { RMeCX
, Iv64
} },
2621 { "mov%LV", { RMeDX
, Iv64
} },
2622 { "mov%LV", { RMeBX
, Iv64
} },
2623 { "mov%LV", { RMeSP
, Iv64
} },
2624 { "mov%LV", { RMeBP
, Iv64
} },
2625 { "mov%LV", { RMeSI
, Iv64
} },
2626 { "mov%LV", { RMeDI
, Iv64
} },
2628 { REG_TABLE (REG_C0
) },
2629 { REG_TABLE (REG_C1
) },
2630 { "retT", { Iw
, BND
} },
2631 { "retT", { BND
} },
2632 { X86_64_TABLE (X86_64_C4
) },
2633 { X86_64_TABLE (X86_64_C5
) },
2634 { REG_TABLE (REG_C6
) },
2635 { REG_TABLE (REG_C7
) },
2637 { "enterT", { Iw
, Ib
} },
2638 { "leaveT", { XX
} },
2639 { "Jret{|f}P", { Iw
} },
2640 { "Jret{|f}P", { XX
} },
2643 { X86_64_TABLE (X86_64_CE
) },
2644 { "iret%LP", { XX
} },
2646 { REG_TABLE (REG_D0
) },
2647 { REG_TABLE (REG_D1
) },
2648 { REG_TABLE (REG_D2
) },
2649 { REG_TABLE (REG_D3
) },
2650 { X86_64_TABLE (X86_64_D4
) },
2651 { X86_64_TABLE (X86_64_D5
) },
2653 { "xlat", { DSBX
} },
2664 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2665 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2666 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2667 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2668 { "inB", { AL
, Ib
} },
2669 { "inG", { zAX
, Ib
} },
2670 { "outB", { Ib
, AL
} },
2671 { "outG", { Ib
, zAX
} },
2673 { "callT", { Jv
, BND
} },
2674 { "jmpT", { Jv
, BND
} },
2675 { X86_64_TABLE (X86_64_EA
) },
2676 { "jmp", { Jb
, BND
} },
2677 { "inB", { AL
, indirDX
} },
2678 { "inG", { zAX
, indirDX
} },
2679 { "outB", { indirDX
, AL
} },
2680 { "outG", { indirDX
, zAX
} },
2682 { Bad_Opcode
}, /* lock prefix */
2683 { "icebp", { XX
} },
2684 { Bad_Opcode
}, /* repne */
2685 { Bad_Opcode
}, /* repz */
2688 { REG_TABLE (REG_F6
) },
2689 { REG_TABLE (REG_F7
) },
2697 { REG_TABLE (REG_FE
) },
2698 { REG_TABLE (REG_FF
) },
2701 static const struct dis386 dis386_twobyte
[] = {
2703 { REG_TABLE (REG_0F00
) },
2704 { REG_TABLE (REG_0F01
) },
2705 { "larS", { Gv
, Ew
} },
2706 { "lslS", { Gv
, Ew
} },
2708 { "syscall", { XX
} },
2710 { "sysret%LP", { XX
} },
2713 { "wbinvd", { XX
} },
2717 { REG_TABLE (REG_0F0D
) },
2718 { "femms", { XX
} },
2719 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2721 { PREFIX_TABLE (PREFIX_0F10
) },
2722 { PREFIX_TABLE (PREFIX_0F11
) },
2723 { PREFIX_TABLE (PREFIX_0F12
) },
2724 { MOD_TABLE (MOD_0F13
) },
2725 { "unpcklpX", { XM
, EXx
} },
2726 { "unpckhpX", { XM
, EXx
} },
2727 { PREFIX_TABLE (PREFIX_0F16
) },
2728 { MOD_TABLE (MOD_0F17
) },
2730 { REG_TABLE (REG_0F18
) },
2732 { PREFIX_TABLE (PREFIX_0F1A
) },
2733 { PREFIX_TABLE (PREFIX_0F1B
) },
2739 { MOD_TABLE (MOD_0F20
) },
2740 { MOD_TABLE (MOD_0F21
) },
2741 { MOD_TABLE (MOD_0F22
) },
2742 { MOD_TABLE (MOD_0F23
) },
2743 { MOD_TABLE (MOD_0F24
) },
2745 { MOD_TABLE (MOD_0F26
) },
2748 { "movapX", { XM
, EXx
} },
2749 { "movapX", { EXxS
, XM
} },
2750 { PREFIX_TABLE (PREFIX_0F2A
) },
2751 { PREFIX_TABLE (PREFIX_0F2B
) },
2752 { PREFIX_TABLE (PREFIX_0F2C
) },
2753 { PREFIX_TABLE (PREFIX_0F2D
) },
2754 { PREFIX_TABLE (PREFIX_0F2E
) },
2755 { PREFIX_TABLE (PREFIX_0F2F
) },
2757 { "wrmsr", { XX
} },
2758 { "rdtsc", { XX
} },
2759 { "rdmsr", { XX
} },
2760 { "rdpmc", { XX
} },
2761 { "sysenter", { XX
} },
2762 { "sysexit", { XX
} },
2764 { "getsec", { XX
} },
2766 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2768 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2775 { "cmovoS", { Gv
, Ev
} },
2776 { "cmovnoS", { Gv
, Ev
} },
2777 { "cmovbS", { Gv
, Ev
} },
2778 { "cmovaeS", { Gv
, Ev
} },
2779 { "cmoveS", { Gv
, Ev
} },
2780 { "cmovneS", { Gv
, Ev
} },
2781 { "cmovbeS", { Gv
, Ev
} },
2782 { "cmovaS", { Gv
, Ev
} },
2784 { "cmovsS", { Gv
, Ev
} },
2785 { "cmovnsS", { Gv
, Ev
} },
2786 { "cmovpS", { Gv
, Ev
} },
2787 { "cmovnpS", { Gv
, Ev
} },
2788 { "cmovlS", { Gv
, Ev
} },
2789 { "cmovgeS", { Gv
, Ev
} },
2790 { "cmovleS", { Gv
, Ev
} },
2791 { "cmovgS", { Gv
, Ev
} },
2793 { MOD_TABLE (MOD_0F51
) },
2794 { PREFIX_TABLE (PREFIX_0F51
) },
2795 { PREFIX_TABLE (PREFIX_0F52
) },
2796 { PREFIX_TABLE (PREFIX_0F53
) },
2797 { "andpX", { XM
, EXx
} },
2798 { "andnpX", { XM
, EXx
} },
2799 { "orpX", { XM
, EXx
} },
2800 { "xorpX", { XM
, EXx
} },
2802 { PREFIX_TABLE (PREFIX_0F58
) },
2803 { PREFIX_TABLE (PREFIX_0F59
) },
2804 { PREFIX_TABLE (PREFIX_0F5A
) },
2805 { PREFIX_TABLE (PREFIX_0F5B
) },
2806 { PREFIX_TABLE (PREFIX_0F5C
) },
2807 { PREFIX_TABLE (PREFIX_0F5D
) },
2808 { PREFIX_TABLE (PREFIX_0F5E
) },
2809 { PREFIX_TABLE (PREFIX_0F5F
) },
2811 { PREFIX_TABLE (PREFIX_0F60
) },
2812 { PREFIX_TABLE (PREFIX_0F61
) },
2813 { PREFIX_TABLE (PREFIX_0F62
) },
2814 { "packsswb", { MX
, EM
} },
2815 { "pcmpgtb", { MX
, EM
} },
2816 { "pcmpgtw", { MX
, EM
} },
2817 { "pcmpgtd", { MX
, EM
} },
2818 { "packuswb", { MX
, EM
} },
2820 { "punpckhbw", { MX
, EM
} },
2821 { "punpckhwd", { MX
, EM
} },
2822 { "punpckhdq", { MX
, EM
} },
2823 { "packssdw", { MX
, EM
} },
2824 { PREFIX_TABLE (PREFIX_0F6C
) },
2825 { PREFIX_TABLE (PREFIX_0F6D
) },
2826 { "movK", { MX
, Edq
} },
2827 { PREFIX_TABLE (PREFIX_0F6F
) },
2829 { PREFIX_TABLE (PREFIX_0F70
) },
2830 { REG_TABLE (REG_0F71
) },
2831 { REG_TABLE (REG_0F72
) },
2832 { REG_TABLE (REG_0F73
) },
2833 { "pcmpeqb", { MX
, EM
} },
2834 { "pcmpeqw", { MX
, EM
} },
2835 { "pcmpeqd", { MX
, EM
} },
2838 { PREFIX_TABLE (PREFIX_0F78
) },
2839 { PREFIX_TABLE (PREFIX_0F79
) },
2840 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2842 { PREFIX_TABLE (PREFIX_0F7C
) },
2843 { PREFIX_TABLE (PREFIX_0F7D
) },
2844 { PREFIX_TABLE (PREFIX_0F7E
) },
2845 { PREFIX_TABLE (PREFIX_0F7F
) },
2847 { "joH", { Jv
, BND
, cond_jump_flag
} },
2848 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2849 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2850 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2851 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2852 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2853 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2854 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2856 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2857 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2858 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2859 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2860 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2861 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2862 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2863 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2866 { "setno", { Eb
} },
2868 { "setae", { Eb
} },
2870 { "setne", { Eb
} },
2871 { "setbe", { Eb
} },
2875 { "setns", { Eb
} },
2877 { "setnp", { Eb
} },
2879 { "setge", { Eb
} },
2880 { "setle", { Eb
} },
2883 { "pushT", { fs
} },
2885 { "cpuid", { XX
} },
2886 { "btS", { Ev
, Gv
} },
2887 { "shldS", { Ev
, Gv
, Ib
} },
2888 { "shldS", { Ev
, Gv
, CL
} },
2889 { REG_TABLE (REG_0FA6
) },
2890 { REG_TABLE (REG_0FA7
) },
2892 { "pushT", { gs
} },
2895 { "btsS", { Evh1
, Gv
} },
2896 { "shrdS", { Ev
, Gv
, Ib
} },
2897 { "shrdS", { Ev
, Gv
, CL
} },
2898 { REG_TABLE (REG_0FAE
) },
2899 { "imulS", { Gv
, Ev
} },
2901 { "cmpxchgB", { Ebh1
, Gb
} },
2902 { "cmpxchgS", { Evh1
, Gv
} },
2903 { MOD_TABLE (MOD_0FB2
) },
2904 { "btrS", { Evh1
, Gv
} },
2905 { MOD_TABLE (MOD_0FB4
) },
2906 { MOD_TABLE (MOD_0FB5
) },
2907 { "movz{bR|x}", { Gv
, Eb
} },
2908 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2910 { PREFIX_TABLE (PREFIX_0FB8
) },
2912 { REG_TABLE (REG_0FBA
) },
2913 { "btcS", { Evh1
, Gv
} },
2914 { PREFIX_TABLE (PREFIX_0FBC
) },
2915 { PREFIX_TABLE (PREFIX_0FBD
) },
2916 { "movs{bR|x}", { Gv
, Eb
} },
2917 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2919 { "xaddB", { Ebh1
, Gb
} },
2920 { "xaddS", { Evh1
, Gv
} },
2921 { PREFIX_TABLE (PREFIX_0FC2
) },
2922 { PREFIX_TABLE (PREFIX_0FC3
) },
2923 { "pinsrw", { MX
, Edqw
, Ib
} },
2924 { "pextrw", { Gdq
, MS
, Ib
} },
2925 { "shufpX", { XM
, EXx
, Ib
} },
2926 { REG_TABLE (REG_0FC7
) },
2928 { "bswap", { RMeAX
} },
2929 { "bswap", { RMeCX
} },
2930 { "bswap", { RMeDX
} },
2931 { "bswap", { RMeBX
} },
2932 { "bswap", { RMeSP
} },
2933 { "bswap", { RMeBP
} },
2934 { "bswap", { RMeSI
} },
2935 { "bswap", { RMeDI
} },
2937 { PREFIX_TABLE (PREFIX_0FD0
) },
2938 { "psrlw", { MX
, EM
} },
2939 { "psrld", { MX
, EM
} },
2940 { "psrlq", { MX
, EM
} },
2941 { "paddq", { MX
, EM
} },
2942 { "pmullw", { MX
, EM
} },
2943 { PREFIX_TABLE (PREFIX_0FD6
) },
2944 { MOD_TABLE (MOD_0FD7
) },
2946 { "psubusb", { MX
, EM
} },
2947 { "psubusw", { MX
, EM
} },
2948 { "pminub", { MX
, EM
} },
2949 { "pand", { MX
, EM
} },
2950 { "paddusb", { MX
, EM
} },
2951 { "paddusw", { MX
, EM
} },
2952 { "pmaxub", { MX
, EM
} },
2953 { "pandn", { MX
, EM
} },
2955 { "pavgb", { MX
, EM
} },
2956 { "psraw", { MX
, EM
} },
2957 { "psrad", { MX
, EM
} },
2958 { "pavgw", { MX
, EM
} },
2959 { "pmulhuw", { MX
, EM
} },
2960 { "pmulhw", { MX
, EM
} },
2961 { PREFIX_TABLE (PREFIX_0FE6
) },
2962 { PREFIX_TABLE (PREFIX_0FE7
) },
2964 { "psubsb", { MX
, EM
} },
2965 { "psubsw", { MX
, EM
} },
2966 { "pminsw", { MX
, EM
} },
2967 { "por", { MX
, EM
} },
2968 { "paddsb", { MX
, EM
} },
2969 { "paddsw", { MX
, EM
} },
2970 { "pmaxsw", { MX
, EM
} },
2971 { "pxor", { MX
, EM
} },
2973 { PREFIX_TABLE (PREFIX_0FF0
) },
2974 { "psllw", { MX
, EM
} },
2975 { "pslld", { MX
, EM
} },
2976 { "psllq", { MX
, EM
} },
2977 { "pmuludq", { MX
, EM
} },
2978 { "pmaddwd", { MX
, EM
} },
2979 { "psadbw", { MX
, EM
} },
2980 { PREFIX_TABLE (PREFIX_0FF7
) },
2982 { "psubb", { MX
, EM
} },
2983 { "psubw", { MX
, EM
} },
2984 { "psubd", { MX
, EM
} },
2985 { "psubq", { MX
, EM
} },
2986 { "paddb", { MX
, EM
} },
2987 { "paddw", { MX
, EM
} },
2988 { "paddd", { MX
, EM
} },
2992 static const unsigned char onebyte_has_modrm
[256] = {
2993 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2994 /* ------------------------------- */
2995 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2996 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2997 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2998 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2999 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3000 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3001 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3002 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3003 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3004 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3005 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3006 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3007 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3008 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3009 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3010 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3011 /* ------------------------------- */
3012 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3015 static const unsigned char twobyte_has_modrm
[256] = {
3016 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3017 /* ------------------------------- */
3018 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3019 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3020 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3021 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3022 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3023 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3024 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3025 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3026 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3027 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3028 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3029 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3030 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3031 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3032 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3033 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3034 /* ------------------------------- */
3035 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3038 static const unsigned char twobyte_has_mandatory_prefix
[256] = {
3039 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3040 /* ------------------------------- */
3041 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3042 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3043 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3044 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3045 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3046 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3047 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3048 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3049 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3050 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3051 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3052 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3053 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3054 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3055 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3056 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3057 /* ------------------------------- */
3058 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3061 static char obuf
[100];
3063 static char *mnemonicendp
;
3064 static char scratchbuf
[100];
3065 static unsigned char *start_codep
;
3066 static unsigned char *insn_codep
;
3067 static unsigned char *codep
;
3068 static unsigned char *end_codep
;
3069 static int last_lock_prefix
;
3070 static int last_repz_prefix
;
3071 static int last_repnz_prefix
;
3072 static int last_data_prefix
;
3073 static int last_addr_prefix
;
3074 static int last_rex_prefix
;
3075 static int last_seg_prefix
;
3076 static int fwait_prefix
;
3077 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3078 static int mandatory_prefix
;
3079 /* The active segment register prefix. */
3080 static int active_seg_prefix
;
3081 #define MAX_CODE_LENGTH 15
3082 /* We can up to 14 prefixes since the maximum instruction length is
3084 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3085 static disassemble_info
*the_info
;
3093 static unsigned char need_modrm
;
3103 int register_specifier
;
3110 int mask_register_specifier
;
3116 static unsigned char need_vex
;
3117 static unsigned char need_vex_reg
;
3118 static unsigned char vex_w_done
;
3126 /* If we are accessing mod/rm/reg without need_modrm set, then the
3127 values are stale. Hitting this abort likely indicates that you
3128 need to update onebyte_has_modrm or twobyte_has_modrm. */
3129 #define MODRM_CHECK if (!need_modrm) abort ()
3131 static const char **names64
;
3132 static const char **names32
;
3133 static const char **names16
;
3134 static const char **names8
;
3135 static const char **names8rex
;
3136 static const char **names_seg
;
3137 static const char *index64
;
3138 static const char *index32
;
3139 static const char **index16
;
3140 static const char **names_bnd
;
3142 static const char *intel_names64
[] = {
3143 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3146 static const char *intel_names32
[] = {
3147 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3148 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3150 static const char *intel_names16
[] = {
3151 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3152 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3154 static const char *intel_names8
[] = {
3155 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3157 static const char *intel_names8rex
[] = {
3158 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3159 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3161 static const char *intel_names_seg
[] = {
3162 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3164 static const char *intel_index64
= "riz";
3165 static const char *intel_index32
= "eiz";
3166 static const char *intel_index16
[] = {
3167 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3170 static const char *att_names64
[] = {
3171 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3172 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3174 static const char *att_names32
[] = {
3175 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3176 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3178 static const char *att_names16
[] = {
3179 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3180 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3182 static const char *att_names8
[] = {
3183 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3185 static const char *att_names8rex
[] = {
3186 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3187 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3189 static const char *att_names_seg
[] = {
3190 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3192 static const char *att_index64
= "%riz";
3193 static const char *att_index32
= "%eiz";
3194 static const char *att_index16
[] = {
3195 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3198 static const char **names_mm
;
3199 static const char *intel_names_mm
[] = {
3200 "mm0", "mm1", "mm2", "mm3",
3201 "mm4", "mm5", "mm6", "mm7"
3203 static const char *att_names_mm
[] = {
3204 "%mm0", "%mm1", "%mm2", "%mm3",
3205 "%mm4", "%mm5", "%mm6", "%mm7"
3208 static const char *intel_names_bnd
[] = {
3209 "bnd0", "bnd1", "bnd2", "bnd3"
3212 static const char *att_names_bnd
[] = {
3213 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3216 static const char **names_xmm
;
3217 static const char *intel_names_xmm
[] = {
3218 "xmm0", "xmm1", "xmm2", "xmm3",
3219 "xmm4", "xmm5", "xmm6", "xmm7",
3220 "xmm8", "xmm9", "xmm10", "xmm11",
3221 "xmm12", "xmm13", "xmm14", "xmm15",
3222 "xmm16", "xmm17", "xmm18", "xmm19",
3223 "xmm20", "xmm21", "xmm22", "xmm23",
3224 "xmm24", "xmm25", "xmm26", "xmm27",
3225 "xmm28", "xmm29", "xmm30", "xmm31"
3227 static const char *att_names_xmm
[] = {
3228 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3229 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3230 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3231 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3232 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3233 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3234 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3235 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3238 static const char **names_ymm
;
3239 static const char *intel_names_ymm
[] = {
3240 "ymm0", "ymm1", "ymm2", "ymm3",
3241 "ymm4", "ymm5", "ymm6", "ymm7",
3242 "ymm8", "ymm9", "ymm10", "ymm11",
3243 "ymm12", "ymm13", "ymm14", "ymm15",
3244 "ymm16", "ymm17", "ymm18", "ymm19",
3245 "ymm20", "ymm21", "ymm22", "ymm23",
3246 "ymm24", "ymm25", "ymm26", "ymm27",
3247 "ymm28", "ymm29", "ymm30", "ymm31"
3249 static const char *att_names_ymm
[] = {
3250 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3251 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3252 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3253 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3254 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3255 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3256 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3257 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3260 static const char **names_zmm
;
3261 static const char *intel_names_zmm
[] = {
3262 "zmm0", "zmm1", "zmm2", "zmm3",
3263 "zmm4", "zmm5", "zmm6", "zmm7",
3264 "zmm8", "zmm9", "zmm10", "zmm11",
3265 "zmm12", "zmm13", "zmm14", "zmm15",
3266 "zmm16", "zmm17", "zmm18", "zmm19",
3267 "zmm20", "zmm21", "zmm22", "zmm23",
3268 "zmm24", "zmm25", "zmm26", "zmm27",
3269 "zmm28", "zmm29", "zmm30", "zmm31"
3271 static const char *att_names_zmm
[] = {
3272 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3273 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3274 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3275 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3276 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3277 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3278 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3279 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3282 static const char **names_mask
;
3283 static const char *intel_names_mask
[] = {
3284 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3286 static const char *att_names_mask
[] = {
3287 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3290 static const char *names_rounding
[] =
3298 static const struct dis386 reg_table
[][8] = {
3301 { "addA", { Ebh1
, Ib
} },
3302 { "orA", { Ebh1
, Ib
} },
3303 { "adcA", { Ebh1
, Ib
} },
3304 { "sbbA", { Ebh1
, Ib
} },
3305 { "andA", { Ebh1
, Ib
} },
3306 { "subA", { Ebh1
, Ib
} },
3307 { "xorA", { Ebh1
, Ib
} },
3308 { "cmpA", { Eb
, Ib
} },
3312 { "addQ", { Evh1
, Iv
} },
3313 { "orQ", { Evh1
, Iv
} },
3314 { "adcQ", { Evh1
, Iv
} },
3315 { "sbbQ", { Evh1
, Iv
} },
3316 { "andQ", { Evh1
, Iv
} },
3317 { "subQ", { Evh1
, Iv
} },
3318 { "xorQ", { Evh1
, Iv
} },
3319 { "cmpQ", { Ev
, Iv
} },
3323 { "addQ", { Evh1
, sIb
} },
3324 { "orQ", { Evh1
, sIb
} },
3325 { "adcQ", { Evh1
, sIb
} },
3326 { "sbbQ", { Evh1
, sIb
} },
3327 { "andQ", { Evh1
, sIb
} },
3328 { "subQ", { Evh1
, sIb
} },
3329 { "xorQ", { Evh1
, sIb
} },
3330 { "cmpQ", { Ev
, sIb
} },
3334 { "popU", { stackEv
} },
3335 { XOP_8F_TABLE (XOP_09
) },
3339 { XOP_8F_TABLE (XOP_09
) },
3343 { "rolA", { Eb
, Ib
} },
3344 { "rorA", { Eb
, Ib
} },
3345 { "rclA", { Eb
, Ib
} },
3346 { "rcrA", { Eb
, Ib
} },
3347 { "shlA", { Eb
, Ib
} },
3348 { "shrA", { Eb
, Ib
} },
3350 { "sarA", { Eb
, Ib
} },
3354 { "rolQ", { Ev
, Ib
} },
3355 { "rorQ", { Ev
, Ib
} },
3356 { "rclQ", { Ev
, Ib
} },
3357 { "rcrQ", { Ev
, Ib
} },
3358 { "shlQ", { Ev
, Ib
} },
3359 { "shrQ", { Ev
, Ib
} },
3361 { "sarQ", { Ev
, Ib
} },
3365 { "movA", { Ebh3
, Ib
} },
3372 { MOD_TABLE (MOD_C6_REG_7
) },
3376 { "movQ", { Evh3
, Iv
} },
3383 { MOD_TABLE (MOD_C7_REG_7
) },
3387 { "rolA", { Eb
, I1
} },
3388 { "rorA", { Eb
, I1
} },
3389 { "rclA", { Eb
, I1
} },
3390 { "rcrA", { Eb
, I1
} },
3391 { "shlA", { Eb
, I1
} },
3392 { "shrA", { Eb
, I1
} },
3394 { "sarA", { Eb
, I1
} },
3398 { "rolQ", { Ev
, I1
} },
3399 { "rorQ", { Ev
, I1
} },
3400 { "rclQ", { Ev
, I1
} },
3401 { "rcrQ", { Ev
, I1
} },
3402 { "shlQ", { Ev
, I1
} },
3403 { "shrQ", { Ev
, I1
} },
3405 { "sarQ", { Ev
, I1
} },
3409 { "rolA", { Eb
, CL
} },
3410 { "rorA", { Eb
, CL
} },
3411 { "rclA", { Eb
, CL
} },
3412 { "rcrA", { Eb
, CL
} },
3413 { "shlA", { Eb
, CL
} },
3414 { "shrA", { Eb
, CL
} },
3416 { "sarA", { Eb
, CL
} },
3420 { "rolQ", { Ev
, CL
} },
3421 { "rorQ", { Ev
, CL
} },
3422 { "rclQ", { Ev
, CL
} },
3423 { "rcrQ", { Ev
, CL
} },
3424 { "shlQ", { Ev
, CL
} },
3425 { "shrQ", { Ev
, CL
} },
3427 { "sarQ", { Ev
, CL
} },
3431 { "testA", { Eb
, Ib
} },
3433 { "notA", { Ebh1
} },
3434 { "negA", { Ebh1
} },
3435 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3436 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3437 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3438 { "idivA", { Eb
} }, /* and idiv for consistency. */
3442 { "testQ", { Ev
, Iv
} },
3444 { "notQ", { Evh1
} },
3445 { "negQ", { Evh1
} },
3446 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3447 { "imulQ", { Ev
} },
3449 { "idivQ", { Ev
} },
3453 { "incA", { Ebh1
} },
3454 { "decA", { Ebh1
} },
3458 { "incQ", { Evh1
} },
3459 { "decQ", { Evh1
} },
3460 { "call{T|}", { indirEv
, BND
} },
3461 { MOD_TABLE (MOD_FF_REG_3
) },
3462 { "jmp{T|}", { indirEv
, BND
} },
3463 { MOD_TABLE (MOD_FF_REG_5
) },
3464 { "pushU", { stackEv
} },
3469 { "sldtD", { Sv
} },
3480 { MOD_TABLE (MOD_0F01_REG_0
) },
3481 { MOD_TABLE (MOD_0F01_REG_1
) },
3482 { MOD_TABLE (MOD_0F01_REG_2
) },
3483 { MOD_TABLE (MOD_0F01_REG_3
) },
3484 { "smswD", { Sv
} },
3487 { MOD_TABLE (MOD_0F01_REG_7
) },
3491 { "prefetch", { Mb
} },
3492 { "prefetchw", { Mb
} },
3493 { "prefetchwt1", { Mb
} },
3494 { "prefetch", { Mb
} },
3495 { "prefetch", { Mb
} },
3496 { "prefetch", { Mb
} },
3497 { "prefetch", { Mb
} },
3498 { "prefetch", { Mb
} },
3502 { MOD_TABLE (MOD_0F18_REG_0
) },
3503 { MOD_TABLE (MOD_0F18_REG_1
) },
3504 { MOD_TABLE (MOD_0F18_REG_2
) },
3505 { MOD_TABLE (MOD_0F18_REG_3
) },
3506 { MOD_TABLE (MOD_0F18_REG_4
) },
3507 { MOD_TABLE (MOD_0F18_REG_5
) },
3508 { MOD_TABLE (MOD_0F18_REG_6
) },
3509 { MOD_TABLE (MOD_0F18_REG_7
) },
3515 { MOD_TABLE (MOD_0F71_REG_2
) },
3517 { MOD_TABLE (MOD_0F71_REG_4
) },
3519 { MOD_TABLE (MOD_0F71_REG_6
) },
3525 { MOD_TABLE (MOD_0F72_REG_2
) },
3527 { MOD_TABLE (MOD_0F72_REG_4
) },
3529 { MOD_TABLE (MOD_0F72_REG_6
) },
3535 { MOD_TABLE (MOD_0F73_REG_2
) },
3536 { MOD_TABLE (MOD_0F73_REG_3
) },
3539 { MOD_TABLE (MOD_0F73_REG_6
) },
3540 { MOD_TABLE (MOD_0F73_REG_7
) },
3544 { "montmul", { { OP_0f07
, 0 } } },
3545 { "xsha1", { { OP_0f07
, 0 } } },
3546 { "xsha256", { { OP_0f07
, 0 } } },
3550 { "xstore-rng", { { OP_0f07
, 0 } } },
3551 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3552 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3553 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3554 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3555 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3559 { MOD_TABLE (MOD_0FAE_REG_0
) },
3560 { MOD_TABLE (MOD_0FAE_REG_1
) },
3561 { MOD_TABLE (MOD_0FAE_REG_2
) },
3562 { MOD_TABLE (MOD_0FAE_REG_3
) },
3563 { MOD_TABLE (MOD_0FAE_REG_4
) },
3564 { MOD_TABLE (MOD_0FAE_REG_5
) },
3565 { MOD_TABLE (MOD_0FAE_REG_6
) },
3566 { MOD_TABLE (MOD_0FAE_REG_7
) },
3574 { "btQ", { Ev
, Ib
} },
3575 { "btsQ", { Evh1
, Ib
} },
3576 { "btrQ", { Evh1
, Ib
} },
3577 { "btcQ", { Evh1
, Ib
} },
3582 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3584 { MOD_TABLE (MOD_0FC7_REG_3
) },
3585 { MOD_TABLE (MOD_0FC7_REG_4
) },
3586 { MOD_TABLE (MOD_0FC7_REG_5
) },
3587 { MOD_TABLE (MOD_0FC7_REG_6
) },
3588 { MOD_TABLE (MOD_0FC7_REG_7
) },
3594 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3596 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3598 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3604 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3606 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3608 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3614 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3615 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3618 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3619 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3625 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3626 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3628 /* REG_VEX_0F38F3 */
3631 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3632 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3633 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3637 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3638 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3642 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3643 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3645 /* REG_XOP_TBM_01 */
3648 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3649 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3650 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3651 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3652 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3653 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3654 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3656 /* REG_XOP_TBM_02 */
3659 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3664 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3666 #define NEED_REG_TABLE
3667 #include "i386-dis-evex.h"
3668 #undef NEED_REG_TABLE
3671 static const struct dis386 prefix_table
[][4] = {
3674 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3675 { "pause", { XX
} },
3676 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3681 { "movups", { XM
, EXx
} },
3682 { "movss", { XM
, EXd
} },
3683 { "movupd", { XM
, EXx
} },
3684 { "movsd", { XM
, EXq
} },
3689 { "movups", { EXxS
, XM
} },
3690 { "movss", { EXdS
, XM
} },
3691 { "movupd", { EXxS
, XM
} },
3692 { "movsd", { EXqS
, XM
} },
3697 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3698 { "movsldup", { XM
, EXx
} },
3699 { "movlpd", { XM
, EXq
} },
3700 { "movddup", { XM
, EXq
} },
3705 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3706 { "movshdup", { XM
, EXx
} },
3707 { "movhpd", { XM
, EXq
} },
3712 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3713 { "bndcl", { Gbnd
, Ev_bnd
} },
3714 { "bndmov", { Gbnd
, Ebnd
} },
3715 { "bndcu", { Gbnd
, Ev_bnd
} },
3720 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3721 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3722 { "bndmov", { Ebnd
, Gbnd
} },
3723 { "bndcn", { Gbnd
, Ev_bnd
} },
3728 { "cvtpi2ps", { XM
, EMCq
} },
3729 { "cvtsi2ss%LQ", { XM
, Ev
} },
3730 { "cvtpi2pd", { XM
, EMCq
} },
3731 { "cvtsi2sd%LQ", { XM
, Ev
} },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3744 { "cvttps2pi", { MXC
, EXq
} },
3745 { "cvttss2siY", { Gv
, EXd
} },
3746 { "cvttpd2pi", { MXC
, EXx
} },
3747 { "cvttsd2siY", { Gv
, EXq
} },
3752 { "cvtps2pi", { MXC
, EXq
} },
3753 { "cvtss2siY", { Gv
, EXd
} },
3754 { "cvtpd2pi", { MXC
, EXx
} },
3755 { "cvtsd2siY", { Gv
, EXq
} },
3760 { "ucomiss",{ XM
, EXd
} },
3762 { "ucomisd",{ XM
, EXq
} },
3767 { "comiss", { XM
, EXd
} },
3769 { "comisd", { XM
, EXq
} },
3774 { "sqrtps", { XM
, EXx
} },
3775 { "sqrtss", { XM
, EXd
} },
3776 { "sqrtpd", { XM
, EXx
} },
3777 { "sqrtsd", { XM
, EXq
} },
3782 { "rsqrtps",{ XM
, EXx
} },
3783 { "rsqrtss",{ XM
, EXd
} },
3788 { "rcpps", { XM
, EXx
} },
3789 { "rcpss", { XM
, EXd
} },
3794 { "addps", { XM
, EXx
} },
3795 { "addss", { XM
, EXd
} },
3796 { "addpd", { XM
, EXx
} },
3797 { "addsd", { XM
, EXq
} },
3802 { "mulps", { XM
, EXx
} },
3803 { "mulss", { XM
, EXd
} },
3804 { "mulpd", { XM
, EXx
} },
3805 { "mulsd", { XM
, EXq
} },
3810 { "cvtps2pd", { XM
, EXq
} },
3811 { "cvtss2sd", { XM
, EXd
} },
3812 { "cvtpd2ps", { XM
, EXx
} },
3813 { "cvtsd2ss", { XM
, EXq
} },
3818 { "cvtdq2ps", { XM
, EXx
} },
3819 { "cvttps2dq", { XM
, EXx
} },
3820 { "cvtps2dq", { XM
, EXx
} },
3825 { "subps", { XM
, EXx
} },
3826 { "subss", { XM
, EXd
} },
3827 { "subpd", { XM
, EXx
} },
3828 { "subsd", { XM
, EXq
} },
3833 { "minps", { XM
, EXx
} },
3834 { "minss", { XM
, EXd
} },
3835 { "minpd", { XM
, EXx
} },
3836 { "minsd", { XM
, EXq
} },
3841 { "divps", { XM
, EXx
} },
3842 { "divss", { XM
, EXd
} },
3843 { "divpd", { XM
, EXx
} },
3844 { "divsd", { XM
, EXq
} },
3849 { "maxps", { XM
, EXx
} },
3850 { "maxss", { XM
, EXd
} },
3851 { "maxpd", { XM
, EXx
} },
3852 { "maxsd", { XM
, EXq
} },
3857 { "punpcklbw",{ MX
, EMd
} },
3859 { "punpcklbw",{ MX
, EMx
} },
3864 { "punpcklwd",{ MX
, EMd
} },
3866 { "punpcklwd",{ MX
, EMx
} },
3871 { "punpckldq",{ MX
, EMd
} },
3873 { "punpckldq",{ MX
, EMx
} },
3880 { "punpcklqdq", { XM
, EXx
} },
3887 { "punpckhqdq", { XM
, EXx
} },
3892 { "movq", { MX
, EM
} },
3893 { "movdqu", { XM
, EXx
} },
3894 { "movdqa", { XM
, EXx
} },
3899 { "pshufw", { MX
, EM
, Ib
} },
3900 { "pshufhw",{ XM
, EXx
, Ib
} },
3901 { "pshufd", { XM
, EXx
, Ib
} },
3902 { "pshuflw",{ XM
, EXx
, Ib
} },
3905 /* PREFIX_0F73_REG_3 */
3909 { "psrldq", { XS
, Ib
} },
3912 /* PREFIX_0F73_REG_7 */
3916 { "pslldq", { XS
, Ib
} },
3921 {"vmread", { Em
, Gm
} },
3923 {"extrq", { XS
, Ib
, Ib
} },
3924 {"insertq", { XM
, XS
, Ib
, Ib
} },
3929 {"vmwrite", { Gm
, Em
} },
3931 {"extrq", { XM
, XS
} },
3932 {"insertq", { XM
, XS
} },
3939 { "haddpd", { XM
, EXx
} },
3940 { "haddps", { XM
, EXx
} },
3947 { "hsubpd", { XM
, EXx
} },
3948 { "hsubps", { XM
, EXx
} },
3953 { "movK", { Edq
, MX
} },
3954 { "movq", { XM
, EXq
} },
3955 { "movK", { Edq
, XM
} },
3960 { "movq", { EMS
, MX
} },
3961 { "movdqu", { EXxS
, XM
} },
3962 { "movdqa", { EXxS
, XM
} },
3965 /* PREFIX_0FAE_REG_0 */
3968 { "rdfsbase", { Ev
} },
3971 /* PREFIX_0FAE_REG_1 */
3974 { "rdgsbase", { Ev
} },
3977 /* PREFIX_0FAE_REG_2 */
3980 { "wrfsbase", { Ev
} },
3983 /* PREFIX_0FAE_REG_3 */
3986 { "wrgsbase", { Ev
} },
3989 /* PREFIX_0FAE_REG_7 */
3991 { "clflush", { Mb
} },
3993 { "clflushopt", { Mb
} },
3999 { "popcntS", { Gv
, Ev
} },
4004 { "bsfS", { Gv
, Ev
} },
4005 { "tzcntS", { Gv
, Ev
} },
4006 { "bsfS", { Gv
, Ev
} },
4011 { "bsrS", { Gv
, Ev
} },
4012 { "lzcntS", { Gv
, Ev
} },
4013 { "bsrS", { Gv
, Ev
} },
4018 { "cmpps", { XM
, EXx
, CMP
} },
4019 { "cmpss", { XM
, EXd
, CMP
} },
4020 { "cmppd", { XM
, EXx
, CMP
} },
4021 { "cmpsd", { XM
, EXq
, CMP
} },
4026 { "movntiS", { Ma
, Gv
} },
4029 /* PREFIX_0FC7_REG_6 */
4031 { "vmptrld",{ Mq
} },
4032 { "vmxon", { Mq
} },
4033 { "vmclear",{ Mq
} },
4040 { "addsubpd", { XM
, EXx
} },
4041 { "addsubps", { XM
, EXx
} },
4047 { "movq2dq",{ XM
, MS
} },
4048 { "movq", { EXqS
, XM
} },
4049 { "movdq2q",{ MX
, XS
} },
4055 { "cvtdq2pd", { XM
, EXq
} },
4056 { "cvttpd2dq", { XM
, EXx
} },
4057 { "cvtpd2dq", { XM
, EXx
} },
4062 { "movntq", { Mq
, MX
} },
4064 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4072 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4077 { "maskmovq", { MX
, MS
} },
4079 { "maskmovdqu", { XM
, XS
} },
4086 { "pblendvb", { XM
, EXx
, XMM0
} },
4093 { "blendvps", { XM
, EXx
, XMM0
} },
4100 { "blendvpd", { XM
, EXx
, XMM0
} },
4107 { "ptest", { XM
, EXx
} },
4114 { "pmovsxbw", { XM
, EXq
} },
4121 { "pmovsxbd", { XM
, EXd
} },
4128 { "pmovsxbq", { XM
, EXw
} },
4135 { "pmovsxwd", { XM
, EXq
} },
4142 { "pmovsxwq", { XM
, EXd
} },
4149 { "pmovsxdq", { XM
, EXq
} },
4156 { "pmuldq", { XM
, EXx
} },
4163 { "pcmpeqq", { XM
, EXx
} },
4170 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4177 { "packusdw", { XM
, EXx
} },
4184 { "pmovzxbw", { XM
, EXq
} },
4191 { "pmovzxbd", { XM
, EXd
} },
4198 { "pmovzxbq", { XM
, EXw
} },
4205 { "pmovzxwd", { XM
, EXq
} },
4212 { "pmovzxwq", { XM
, EXd
} },
4219 { "pmovzxdq", { XM
, EXq
} },
4226 { "pcmpgtq", { XM
, EXx
} },
4233 { "pminsb", { XM
, EXx
} },
4240 { "pminsd", { XM
, EXx
} },
4247 { "pminuw", { XM
, EXx
} },
4254 { "pminud", { XM
, EXx
} },
4261 { "pmaxsb", { XM
, EXx
} },
4268 { "pmaxsd", { XM
, EXx
} },
4275 { "pmaxuw", { XM
, EXx
} },
4282 { "pmaxud", { XM
, EXx
} },
4289 { "pmulld", { XM
, EXx
} },
4296 { "phminposuw", { XM
, EXx
} },
4303 { "invept", { Gm
, Mo
} },
4310 { "invvpid", { Gm
, Mo
} },
4317 { "invpcid", { Gm
, M
} },
4322 { "sha1nexte", { XM
, EXxmm
} },
4327 { "sha1msg1", { XM
, EXxmm
} },
4332 { "sha1msg2", { XM
, EXxmm
} },
4337 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4342 { "sha256msg1", { XM
, EXxmm
} },
4347 { "sha256msg2", { XM
, EXxmm
} },
4354 { "aesimc", { XM
, EXx
} },
4361 { "aesenc", { XM
, EXx
} },
4368 { "aesenclast", { XM
, EXx
} },
4375 { "aesdec", { XM
, EXx
} },
4382 { "aesdeclast", { XM
, EXx
} },
4387 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4389 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4390 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4395 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4397 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4398 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4404 { "adoxS", { Gdq
, Edq
} },
4405 { "adcxS", { Gdq
, Edq
} },
4413 { "roundps", { XM
, EXx
, Ib
} },
4420 { "roundpd", { XM
, EXx
, Ib
} },
4427 { "roundss", { XM
, EXd
, Ib
} },
4434 { "roundsd", { XM
, EXq
, Ib
} },
4441 { "blendps", { XM
, EXx
, Ib
} },
4448 { "blendpd", { XM
, EXx
, Ib
} },
4455 { "pblendw", { XM
, EXx
, Ib
} },
4462 { "pextrb", { Edqb
, XM
, Ib
} },
4469 { "pextrw", { Edqw
, XM
, Ib
} },
4476 { "pextrK", { Edq
, XM
, Ib
} },
4483 { "extractps", { Edqd
, XM
, Ib
} },
4490 { "pinsrb", { XM
, Edqb
, Ib
} },
4497 { "insertps", { XM
, EXd
, Ib
} },
4504 { "pinsrK", { XM
, Edq
, Ib
} },
4511 { "dpps", { XM
, EXx
, Ib
} },
4518 { "dppd", { XM
, EXx
, Ib
} },
4525 { "mpsadbw", { XM
, EXx
, Ib
} },
4532 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4539 { "pcmpestrm", { XM
, EXx
, Ib
} },
4546 { "pcmpestri", { XM
, EXx
, Ib
} },
4553 { "pcmpistrm", { XM
, EXx
, Ib
} },
4560 { "pcmpistri", { XM
, EXx
, Ib
} },
4565 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4572 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4575 /* PREFIX_VEX_0F10 */
4577 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4578 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4579 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4580 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4583 /* PREFIX_VEX_0F11 */
4585 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4586 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4587 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4588 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4591 /* PREFIX_VEX_0F12 */
4593 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4594 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4595 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4596 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4599 /* PREFIX_VEX_0F16 */
4601 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4602 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4603 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4606 /* PREFIX_VEX_0F2A */
4609 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4611 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4614 /* PREFIX_VEX_0F2C */
4617 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4619 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4622 /* PREFIX_VEX_0F2D */
4625 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4627 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4630 /* PREFIX_VEX_0F2E */
4632 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4634 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4637 /* PREFIX_VEX_0F2F */
4639 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4641 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4644 /* PREFIX_VEX_0F41 */
4646 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4648 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4651 /* PREFIX_VEX_0F42 */
4653 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4655 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4658 /* PREFIX_VEX_0F44 */
4660 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4662 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4665 /* PREFIX_VEX_0F45 */
4667 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4669 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4672 /* PREFIX_VEX_0F46 */
4674 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4676 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4679 /* PREFIX_VEX_0F47 */
4681 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4683 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4686 /* PREFIX_VEX_0F4A */
4688 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4690 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4693 /* PREFIX_VEX_0F4B */
4695 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4697 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4700 /* PREFIX_VEX_0F51 */
4702 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4703 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4704 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4705 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4708 /* PREFIX_VEX_0F52 */
4710 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4711 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4714 /* PREFIX_VEX_0F53 */
4716 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4717 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4720 /* PREFIX_VEX_0F58 */
4722 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4723 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4724 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4725 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4728 /* PREFIX_VEX_0F59 */
4730 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4731 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4732 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4736 /* PREFIX_VEX_0F5A */
4738 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4740 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4741 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4744 /* PREFIX_VEX_0F5B */
4746 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4747 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4748 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4751 /* PREFIX_VEX_0F5C */
4753 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4754 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4755 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4756 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4759 /* PREFIX_VEX_0F5D */
4761 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4763 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4764 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4767 /* PREFIX_VEX_0F5E */
4769 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4771 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4775 /* PREFIX_VEX_0F5F */
4777 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4779 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4780 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4783 /* PREFIX_VEX_0F60 */
4787 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4790 /* PREFIX_VEX_0F61 */
4794 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4797 /* PREFIX_VEX_0F62 */
4801 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4804 /* PREFIX_VEX_0F63 */
4808 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4811 /* PREFIX_VEX_0F64 */
4815 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4818 /* PREFIX_VEX_0F65 */
4822 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4825 /* PREFIX_VEX_0F66 */
4829 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4832 /* PREFIX_VEX_0F67 */
4836 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4839 /* PREFIX_VEX_0F68 */
4843 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4846 /* PREFIX_VEX_0F69 */
4850 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4853 /* PREFIX_VEX_0F6A */
4857 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4860 /* PREFIX_VEX_0F6B */
4864 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4867 /* PREFIX_VEX_0F6C */
4871 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4874 /* PREFIX_VEX_0F6D */
4878 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4881 /* PREFIX_VEX_0F6E */
4885 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4888 /* PREFIX_VEX_0F6F */
4891 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4892 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4895 /* PREFIX_VEX_0F70 */
4898 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4899 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4900 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4903 /* PREFIX_VEX_0F71_REG_2 */
4907 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4910 /* PREFIX_VEX_0F71_REG_4 */
4914 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4917 /* PREFIX_VEX_0F71_REG_6 */
4921 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4924 /* PREFIX_VEX_0F72_REG_2 */
4928 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4931 /* PREFIX_VEX_0F72_REG_4 */
4935 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4938 /* PREFIX_VEX_0F72_REG_6 */
4942 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4945 /* PREFIX_VEX_0F73_REG_2 */
4949 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4952 /* PREFIX_VEX_0F73_REG_3 */
4956 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4959 /* PREFIX_VEX_0F73_REG_6 */
4963 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4966 /* PREFIX_VEX_0F73_REG_7 */
4970 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4973 /* PREFIX_VEX_0F74 */
4977 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4980 /* PREFIX_VEX_0F75 */
4984 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4987 /* PREFIX_VEX_0F76 */
4991 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4994 /* PREFIX_VEX_0F77 */
4996 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4999 /* PREFIX_VEX_0F7C */
5003 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5004 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5007 /* PREFIX_VEX_0F7D */
5011 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5012 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5015 /* PREFIX_VEX_0F7E */
5018 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5022 /* PREFIX_VEX_0F7F */
5025 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5026 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5029 /* PREFIX_VEX_0F90 */
5031 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5033 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5036 /* PREFIX_VEX_0F91 */
5038 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5040 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5043 /* PREFIX_VEX_0F92 */
5045 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5047 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5048 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5051 /* PREFIX_VEX_0F93 */
5053 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5055 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5056 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5059 /* PREFIX_VEX_0F98 */
5061 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5063 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5066 /* PREFIX_VEX_0F99 */
5068 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5070 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5073 /* PREFIX_VEX_0FC2 */
5075 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5076 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5077 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5078 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5081 /* PREFIX_VEX_0FC4 */
5085 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5088 /* PREFIX_VEX_0FC5 */
5092 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5095 /* PREFIX_VEX_0FD0 */
5099 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5100 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5103 /* PREFIX_VEX_0FD1 */
5107 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5110 /* PREFIX_VEX_0FD2 */
5114 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5117 /* PREFIX_VEX_0FD3 */
5121 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5124 /* PREFIX_VEX_0FD4 */
5128 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5131 /* PREFIX_VEX_0FD5 */
5135 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5138 /* PREFIX_VEX_0FD6 */
5142 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5145 /* PREFIX_VEX_0FD7 */
5149 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5152 /* PREFIX_VEX_0FD8 */
5156 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5159 /* PREFIX_VEX_0FD9 */
5163 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5166 /* PREFIX_VEX_0FDA */
5170 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5173 /* PREFIX_VEX_0FDB */
5177 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5180 /* PREFIX_VEX_0FDC */
5184 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5187 /* PREFIX_VEX_0FDD */
5191 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5194 /* PREFIX_VEX_0FDE */
5198 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5201 /* PREFIX_VEX_0FDF */
5205 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5208 /* PREFIX_VEX_0FE0 */
5212 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5215 /* PREFIX_VEX_0FE1 */
5219 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5222 /* PREFIX_VEX_0FE2 */
5226 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5229 /* PREFIX_VEX_0FE3 */
5233 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5236 /* PREFIX_VEX_0FE4 */
5240 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5243 /* PREFIX_VEX_0FE5 */
5247 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5250 /* PREFIX_VEX_0FE6 */
5253 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5254 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5255 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5258 /* PREFIX_VEX_0FE7 */
5262 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5265 /* PREFIX_VEX_0FE8 */
5269 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5272 /* PREFIX_VEX_0FE9 */
5276 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5279 /* PREFIX_VEX_0FEA */
5283 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5286 /* PREFIX_VEX_0FEB */
5290 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5293 /* PREFIX_VEX_0FEC */
5297 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5300 /* PREFIX_VEX_0FED */
5304 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5307 /* PREFIX_VEX_0FEE */
5311 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5314 /* PREFIX_VEX_0FEF */
5318 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5321 /* PREFIX_VEX_0FF0 */
5326 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5329 /* PREFIX_VEX_0FF1 */
5333 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5336 /* PREFIX_VEX_0FF2 */
5340 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5343 /* PREFIX_VEX_0FF3 */
5347 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5350 /* PREFIX_VEX_0FF4 */
5354 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5357 /* PREFIX_VEX_0FF5 */
5361 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5364 /* PREFIX_VEX_0FF6 */
5368 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5371 /* PREFIX_VEX_0FF7 */
5375 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5378 /* PREFIX_VEX_0FF8 */
5382 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5385 /* PREFIX_VEX_0FF9 */
5389 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5392 /* PREFIX_VEX_0FFA */
5396 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5399 /* PREFIX_VEX_0FFB */
5403 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5406 /* PREFIX_VEX_0FFC */
5410 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5413 /* PREFIX_VEX_0FFD */
5417 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5420 /* PREFIX_VEX_0FFE */
5424 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5427 /* PREFIX_VEX_0F3800 */
5431 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5434 /* PREFIX_VEX_0F3801 */
5438 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5441 /* PREFIX_VEX_0F3802 */
5445 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5448 /* PREFIX_VEX_0F3803 */
5452 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5455 /* PREFIX_VEX_0F3804 */
5459 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5462 /* PREFIX_VEX_0F3805 */
5466 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5469 /* PREFIX_VEX_0F3806 */
5473 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5476 /* PREFIX_VEX_0F3807 */
5480 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5483 /* PREFIX_VEX_0F3808 */
5487 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5490 /* PREFIX_VEX_0F3809 */
5494 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5497 /* PREFIX_VEX_0F380A */
5501 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5504 /* PREFIX_VEX_0F380B */
5508 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5511 /* PREFIX_VEX_0F380C */
5515 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5518 /* PREFIX_VEX_0F380D */
5522 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5525 /* PREFIX_VEX_0F380E */
5529 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5532 /* PREFIX_VEX_0F380F */
5536 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5539 /* PREFIX_VEX_0F3813 */
5543 { "vcvtph2ps", { XM
, EXxmmq
} },
5546 /* PREFIX_VEX_0F3816 */
5550 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5553 /* PREFIX_VEX_0F3817 */
5557 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5560 /* PREFIX_VEX_0F3818 */
5564 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5567 /* PREFIX_VEX_0F3819 */
5571 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5574 /* PREFIX_VEX_0F381A */
5578 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5581 /* PREFIX_VEX_0F381C */
5585 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5588 /* PREFIX_VEX_0F381D */
5592 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5595 /* PREFIX_VEX_0F381E */
5599 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5602 /* PREFIX_VEX_0F3820 */
5606 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5609 /* PREFIX_VEX_0F3821 */
5613 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5616 /* PREFIX_VEX_0F3822 */
5620 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5623 /* PREFIX_VEX_0F3823 */
5627 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5630 /* PREFIX_VEX_0F3824 */
5634 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5637 /* PREFIX_VEX_0F3825 */
5641 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5644 /* PREFIX_VEX_0F3828 */
5648 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5651 /* PREFIX_VEX_0F3829 */
5655 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5658 /* PREFIX_VEX_0F382A */
5662 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5665 /* PREFIX_VEX_0F382B */
5669 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5672 /* PREFIX_VEX_0F382C */
5676 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5679 /* PREFIX_VEX_0F382D */
5683 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5686 /* PREFIX_VEX_0F382E */
5690 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5693 /* PREFIX_VEX_0F382F */
5697 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5700 /* PREFIX_VEX_0F3830 */
5704 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5707 /* PREFIX_VEX_0F3831 */
5711 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5714 /* PREFIX_VEX_0F3832 */
5718 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5721 /* PREFIX_VEX_0F3833 */
5725 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5728 /* PREFIX_VEX_0F3834 */
5732 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5735 /* PREFIX_VEX_0F3835 */
5739 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5742 /* PREFIX_VEX_0F3836 */
5746 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5749 /* PREFIX_VEX_0F3837 */
5753 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5756 /* PREFIX_VEX_0F3838 */
5760 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5763 /* PREFIX_VEX_0F3839 */
5767 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5770 /* PREFIX_VEX_0F383A */
5774 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5777 /* PREFIX_VEX_0F383B */
5781 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5784 /* PREFIX_VEX_0F383C */
5788 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5791 /* PREFIX_VEX_0F383D */
5795 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5798 /* PREFIX_VEX_0F383E */
5802 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5805 /* PREFIX_VEX_0F383F */
5809 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5812 /* PREFIX_VEX_0F3840 */
5816 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5819 /* PREFIX_VEX_0F3841 */
5823 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5826 /* PREFIX_VEX_0F3845 */
5830 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5833 /* PREFIX_VEX_0F3846 */
5837 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5840 /* PREFIX_VEX_0F3847 */
5844 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5847 /* PREFIX_VEX_0F3858 */
5851 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5854 /* PREFIX_VEX_0F3859 */
5858 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5861 /* PREFIX_VEX_0F385A */
5865 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5868 /* PREFIX_VEX_0F3878 */
5872 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5875 /* PREFIX_VEX_0F3879 */
5879 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5882 /* PREFIX_VEX_0F388C */
5886 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5889 /* PREFIX_VEX_0F388E */
5893 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5896 /* PREFIX_VEX_0F3890 */
5900 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5903 /* PREFIX_VEX_0F3891 */
5907 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5910 /* PREFIX_VEX_0F3892 */
5914 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5917 /* PREFIX_VEX_0F3893 */
5921 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5924 /* PREFIX_VEX_0F3896 */
5928 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5931 /* PREFIX_VEX_0F3897 */
5935 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5938 /* PREFIX_VEX_0F3898 */
5942 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5945 /* PREFIX_VEX_0F3899 */
5949 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5952 /* PREFIX_VEX_0F389A */
5956 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5959 /* PREFIX_VEX_0F389B */
5963 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5966 /* PREFIX_VEX_0F389C */
5970 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5973 /* PREFIX_VEX_0F389D */
5977 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5980 /* PREFIX_VEX_0F389E */
5984 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
5987 /* PREFIX_VEX_0F389F */
5991 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5994 /* PREFIX_VEX_0F38A6 */
5998 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
6002 /* PREFIX_VEX_0F38A7 */
6006 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
6009 /* PREFIX_VEX_0F38A8 */
6013 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
6016 /* PREFIX_VEX_0F38A9 */
6020 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6023 /* PREFIX_VEX_0F38AA */
6027 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
6030 /* PREFIX_VEX_0F38AB */
6034 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6037 /* PREFIX_VEX_0F38AC */
6041 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
6044 /* PREFIX_VEX_0F38AD */
6048 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6051 /* PREFIX_VEX_0F38AE */
6055 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
6058 /* PREFIX_VEX_0F38AF */
6062 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6065 /* PREFIX_VEX_0F38B6 */
6069 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
6072 /* PREFIX_VEX_0F38B7 */
6076 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
6079 /* PREFIX_VEX_0F38B8 */
6083 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
6086 /* PREFIX_VEX_0F38B9 */
6090 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6093 /* PREFIX_VEX_0F38BA */
6097 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
6100 /* PREFIX_VEX_0F38BB */
6104 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6107 /* PREFIX_VEX_0F38BC */
6111 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
6114 /* PREFIX_VEX_0F38BD */
6118 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6121 /* PREFIX_VEX_0F38BE */
6125 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
6128 /* PREFIX_VEX_0F38BF */
6132 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
6135 /* PREFIX_VEX_0F38DB */
6139 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6142 /* PREFIX_VEX_0F38DC */
6146 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
6149 /* PREFIX_VEX_0F38DD */
6153 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
6156 /* PREFIX_VEX_0F38DE */
6160 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
6163 /* PREFIX_VEX_0F38DF */
6167 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
6170 /* PREFIX_VEX_0F38F2 */
6172 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6175 /* PREFIX_VEX_0F38F3_REG_1 */
6177 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6180 /* PREFIX_VEX_0F38F3_REG_2 */
6182 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6185 /* PREFIX_VEX_0F38F3_REG_3 */
6187 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6190 /* PREFIX_VEX_0F38F5 */
6192 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6193 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6195 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6198 /* PREFIX_VEX_0F38F6 */
6203 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6206 /* PREFIX_VEX_0F38F7 */
6208 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6209 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6210 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6211 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6214 /* PREFIX_VEX_0F3A00 */
6218 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6221 /* PREFIX_VEX_0F3A01 */
6225 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6228 /* PREFIX_VEX_0F3A02 */
6232 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6235 /* PREFIX_VEX_0F3A04 */
6239 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6242 /* PREFIX_VEX_0F3A05 */
6246 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6249 /* PREFIX_VEX_0F3A06 */
6253 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6256 /* PREFIX_VEX_0F3A08 */
6260 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6263 /* PREFIX_VEX_0F3A09 */
6267 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6270 /* PREFIX_VEX_0F3A0A */
6274 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6277 /* PREFIX_VEX_0F3A0B */
6281 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6284 /* PREFIX_VEX_0F3A0C */
6288 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6291 /* PREFIX_VEX_0F3A0D */
6295 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6298 /* PREFIX_VEX_0F3A0E */
6302 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6305 /* PREFIX_VEX_0F3A0F */
6309 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6312 /* PREFIX_VEX_0F3A14 */
6316 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6319 /* PREFIX_VEX_0F3A15 */
6323 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6326 /* PREFIX_VEX_0F3A16 */
6330 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6333 /* PREFIX_VEX_0F3A17 */
6337 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6340 /* PREFIX_VEX_0F3A18 */
6344 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6347 /* PREFIX_VEX_0F3A19 */
6351 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6354 /* PREFIX_VEX_0F3A1D */
6358 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6361 /* PREFIX_VEX_0F3A20 */
6365 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6368 /* PREFIX_VEX_0F3A21 */
6372 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6375 /* PREFIX_VEX_0F3A22 */
6379 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6382 /* PREFIX_VEX_0F3A30 */
6386 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6389 /* PREFIX_VEX_0F3A31 */
6393 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6396 /* PREFIX_VEX_0F3A32 */
6400 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6403 /* PREFIX_VEX_0F3A33 */
6407 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6410 /* PREFIX_VEX_0F3A38 */
6414 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6417 /* PREFIX_VEX_0F3A39 */
6421 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6424 /* PREFIX_VEX_0F3A40 */
6428 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6431 /* PREFIX_VEX_0F3A41 */
6435 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6438 /* PREFIX_VEX_0F3A42 */
6442 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6445 /* PREFIX_VEX_0F3A44 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6452 /* PREFIX_VEX_0F3A46 */
6456 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6459 /* PREFIX_VEX_0F3A48 */
6463 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6466 /* PREFIX_VEX_0F3A49 */
6470 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6473 /* PREFIX_VEX_0F3A4A */
6477 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6480 /* PREFIX_VEX_0F3A4B */
6484 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6487 /* PREFIX_VEX_0F3A4C */
6491 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6494 /* PREFIX_VEX_0F3A5C */
6498 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6501 /* PREFIX_VEX_0F3A5D */
6505 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6508 /* PREFIX_VEX_0F3A5E */
6512 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6515 /* PREFIX_VEX_0F3A5F */
6519 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6522 /* PREFIX_VEX_0F3A60 */
6526 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6530 /* PREFIX_VEX_0F3A61 */
6534 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6537 /* PREFIX_VEX_0F3A62 */
6541 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6544 /* PREFIX_VEX_0F3A63 */
6548 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6551 /* PREFIX_VEX_0F3A68 */
6555 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6558 /* PREFIX_VEX_0F3A69 */
6562 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6565 /* PREFIX_VEX_0F3A6A */
6569 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6572 /* PREFIX_VEX_0F3A6B */
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6579 /* PREFIX_VEX_0F3A6C */
6583 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6586 /* PREFIX_VEX_0F3A6D */
6590 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6593 /* PREFIX_VEX_0F3A6E */
6597 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6600 /* PREFIX_VEX_0F3A6F */
6604 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6607 /* PREFIX_VEX_0F3A78 */
6611 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6614 /* PREFIX_VEX_0F3A79 */
6618 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6621 /* PREFIX_VEX_0F3A7A */
6625 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6628 /* PREFIX_VEX_0F3A7B */
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6635 /* PREFIX_VEX_0F3A7C */
6639 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6643 /* PREFIX_VEX_0F3A7D */
6647 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6650 /* PREFIX_VEX_0F3A7E */
6654 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6657 /* PREFIX_VEX_0F3A7F */
6661 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6664 /* PREFIX_VEX_0F3ADF */
6668 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6671 /* PREFIX_VEX_0F3AF0 */
6676 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6679 #define NEED_PREFIX_TABLE
6680 #include "i386-dis-evex.h"
6681 #undef NEED_PREFIX_TABLE
6684 static const struct dis386 x86_64_table
[][2] = {
6687 { "pushP", { es
} },
6697 { "pushP", { cs
} },
6702 { "pushP", { ss
} },
6712 { "pushP", { ds
} },
6742 { "pushaP", { XX
} },
6747 { "popaP", { XX
} },
6752 { MOD_TABLE (MOD_62_32BIT
) },
6753 { EVEX_TABLE (EVEX_0F
) },
6758 { "arpl", { Ew
, Gw
} },
6759 { "movs{lq|xd}", { Gv
, Ed
} },
6764 { "ins{R|}", { Yzr
, indirDX
} },
6765 { "ins{G|}", { Yzr
, indirDX
} },
6770 { "outs{R|}", { indirDXr
, Xz
} },
6771 { "outs{G|}", { indirDXr
, Xz
} },
6776 { "Jcall{T|}", { Ap
} },
6781 { MOD_TABLE (MOD_C4_32BIT
) },
6782 { VEX_C4_TABLE (VEX_0F
) },
6787 { MOD_TABLE (MOD_C5_32BIT
) },
6788 { VEX_C5_TABLE (VEX_0F
) },
6808 { "Jjmp{T|}", { Ap
} },
6811 /* X86_64_0F01_REG_0 */
6813 { "sgdt{Q|IQ}", { M
} },
6817 /* X86_64_0F01_REG_1 */
6819 { "sidt{Q|IQ}", { M
} },
6823 /* X86_64_0F01_REG_2 */
6825 { "lgdt{Q|Q}", { M
} },
6829 /* X86_64_0F01_REG_3 */
6831 { "lidt{Q|Q}", { M
} },
6836 static const struct dis386 three_byte_table
[][256] = {
6838 /* THREE_BYTE_0F38 */
6841 { "pshufb", { MX
, EM
} },
6842 { "phaddw", { MX
, EM
} },
6843 { "phaddd", { MX
, EM
} },
6844 { "phaddsw", { MX
, EM
} },
6845 { "pmaddubsw", { MX
, EM
} },
6846 { "phsubw", { MX
, EM
} },
6847 { "phsubd", { MX
, EM
} },
6848 { "phsubsw", { MX
, EM
} },
6850 { "psignb", { MX
, EM
} },
6851 { "psignw", { MX
, EM
} },
6852 { "psignd", { MX
, EM
} },
6853 { "pmulhrsw", { MX
, EM
} },
6859 { PREFIX_TABLE (PREFIX_0F3810
) },
6863 { PREFIX_TABLE (PREFIX_0F3814
) },
6864 { PREFIX_TABLE (PREFIX_0F3815
) },
6866 { PREFIX_TABLE (PREFIX_0F3817
) },
6872 { "pabsb", { MX
, EM
} },
6873 { "pabsw", { MX
, EM
} },
6874 { "pabsd", { MX
, EM
} },
6877 { PREFIX_TABLE (PREFIX_0F3820
) },
6878 { PREFIX_TABLE (PREFIX_0F3821
) },
6879 { PREFIX_TABLE (PREFIX_0F3822
) },
6880 { PREFIX_TABLE (PREFIX_0F3823
) },
6881 { PREFIX_TABLE (PREFIX_0F3824
) },
6882 { PREFIX_TABLE (PREFIX_0F3825
) },
6886 { PREFIX_TABLE (PREFIX_0F3828
) },
6887 { PREFIX_TABLE (PREFIX_0F3829
) },
6888 { PREFIX_TABLE (PREFIX_0F382A
) },
6889 { PREFIX_TABLE (PREFIX_0F382B
) },
6895 { PREFIX_TABLE (PREFIX_0F3830
) },
6896 { PREFIX_TABLE (PREFIX_0F3831
) },
6897 { PREFIX_TABLE (PREFIX_0F3832
) },
6898 { PREFIX_TABLE (PREFIX_0F3833
) },
6899 { PREFIX_TABLE (PREFIX_0F3834
) },
6900 { PREFIX_TABLE (PREFIX_0F3835
) },
6902 { PREFIX_TABLE (PREFIX_0F3837
) },
6904 { PREFIX_TABLE (PREFIX_0F3838
) },
6905 { PREFIX_TABLE (PREFIX_0F3839
) },
6906 { PREFIX_TABLE (PREFIX_0F383A
) },
6907 { PREFIX_TABLE (PREFIX_0F383B
) },
6908 { PREFIX_TABLE (PREFIX_0F383C
) },
6909 { PREFIX_TABLE (PREFIX_0F383D
) },
6910 { PREFIX_TABLE (PREFIX_0F383E
) },
6911 { PREFIX_TABLE (PREFIX_0F383F
) },
6913 { PREFIX_TABLE (PREFIX_0F3840
) },
6914 { PREFIX_TABLE (PREFIX_0F3841
) },
6985 { PREFIX_TABLE (PREFIX_0F3880
) },
6986 { PREFIX_TABLE (PREFIX_0F3881
) },
6987 { PREFIX_TABLE (PREFIX_0F3882
) },
7066 { PREFIX_TABLE (PREFIX_0F38C8
) },
7067 { PREFIX_TABLE (PREFIX_0F38C9
) },
7068 { PREFIX_TABLE (PREFIX_0F38CA
) },
7069 { PREFIX_TABLE (PREFIX_0F38CB
) },
7070 { PREFIX_TABLE (PREFIX_0F38CC
) },
7071 { PREFIX_TABLE (PREFIX_0F38CD
) },
7087 { PREFIX_TABLE (PREFIX_0F38DB
) },
7088 { PREFIX_TABLE (PREFIX_0F38DC
) },
7089 { PREFIX_TABLE (PREFIX_0F38DD
) },
7090 { PREFIX_TABLE (PREFIX_0F38DE
) },
7091 { PREFIX_TABLE (PREFIX_0F38DF
) },
7111 { PREFIX_TABLE (PREFIX_0F38F0
) },
7112 { PREFIX_TABLE (PREFIX_0F38F1
) },
7117 { PREFIX_TABLE (PREFIX_0F38F6
) },
7129 /* THREE_BYTE_0F3A */
7141 { PREFIX_TABLE (PREFIX_0F3A08
) },
7142 { PREFIX_TABLE (PREFIX_0F3A09
) },
7143 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7144 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7145 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7146 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7147 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7148 { "palignr", { MX
, EM
, Ib
} },
7154 { PREFIX_TABLE (PREFIX_0F3A14
) },
7155 { PREFIX_TABLE (PREFIX_0F3A15
) },
7156 { PREFIX_TABLE (PREFIX_0F3A16
) },
7157 { PREFIX_TABLE (PREFIX_0F3A17
) },
7168 { PREFIX_TABLE (PREFIX_0F3A20
) },
7169 { PREFIX_TABLE (PREFIX_0F3A21
) },
7170 { PREFIX_TABLE (PREFIX_0F3A22
) },
7204 { PREFIX_TABLE (PREFIX_0F3A40
) },
7205 { PREFIX_TABLE (PREFIX_0F3A41
) },
7206 { PREFIX_TABLE (PREFIX_0F3A42
) },
7208 { PREFIX_TABLE (PREFIX_0F3A44
) },
7240 { PREFIX_TABLE (PREFIX_0F3A60
) },
7241 { PREFIX_TABLE (PREFIX_0F3A61
) },
7242 { PREFIX_TABLE (PREFIX_0F3A62
) },
7243 { PREFIX_TABLE (PREFIX_0F3A63
) },
7361 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7382 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7421 /* THREE_BYTE_0F7A */
7460 { "ptest", { XX
} },
7497 { "phaddbw", { XM
, EXq
} },
7498 { "phaddbd", { XM
, EXq
} },
7499 { "phaddbq", { XM
, EXq
} },
7502 { "phaddwd", { XM
, EXq
} },
7503 { "phaddwq", { XM
, EXq
} },
7508 { "phadddq", { XM
, EXq
} },
7515 { "phaddubw", { XM
, EXq
} },
7516 { "phaddubd", { XM
, EXq
} },
7517 { "phaddubq", { XM
, EXq
} },
7520 { "phadduwd", { XM
, EXq
} },
7521 { "phadduwq", { XM
, EXq
} },
7526 { "phaddudq", { XM
, EXq
} },
7533 { "phsubbw", { XM
, EXq
} },
7534 { "phsubbd", { XM
, EXq
} },
7535 { "phsubbq", { XM
, EXq
} },
7714 static const struct dis386 xop_table
[][256] = {
7867 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7868 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7869 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7877 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7878 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7885 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7886 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7887 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7895 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7896 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7900 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7901 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7904 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7922 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7934 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7935 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7936 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7937 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7947 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7948 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7949 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7950 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7983 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7984 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7985 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7986 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8010 { REG_TABLE (REG_XOP_TBM_01
) },
8011 { REG_TABLE (REG_XOP_TBM_02
) },
8029 { REG_TABLE (REG_XOP_LWPCB
) },
8153 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8154 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8155 { "vfrczss", { XM
, EXd
} },
8156 { "vfrczsd", { XM
, EXq
} },
8171 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8172 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8173 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
8174 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8175 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
8176 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8177 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
8178 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8180 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
8181 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
8182 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
8183 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
8226 { "vphaddbw", { XM
, EXxmm
} },
8227 { "vphaddbd", { XM
, EXxmm
} },
8228 { "vphaddbq", { XM
, EXxmm
} },
8231 { "vphaddwd", { XM
, EXxmm
} },
8232 { "vphaddwq", { XM
, EXxmm
} },
8237 { "vphadddq", { XM
, EXxmm
} },
8244 { "vphaddubw", { XM
, EXxmm
} },
8245 { "vphaddubd", { XM
, EXxmm
} },
8246 { "vphaddubq", { XM
, EXxmm
} },
8249 { "vphadduwd", { XM
, EXxmm
} },
8250 { "vphadduwq", { XM
, EXxmm
} },
8255 { "vphaddudq", { XM
, EXxmm
} },
8262 { "vphsubbw", { XM
, EXxmm
} },
8263 { "vphsubwd", { XM
, EXxmm
} },
8264 { "vphsubdq", { XM
, EXxmm
} },
8318 { "bextr", { Gv
, Ev
, Iq
} },
8320 { REG_TABLE (REG_XOP_LWP
) },
8590 static const struct dis386 vex_table
[][256] = {
8612 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8615 { MOD_TABLE (MOD_VEX_0F13
) },
8616 { VEX_W_TABLE (VEX_W_0F14
) },
8617 { VEX_W_TABLE (VEX_W_0F15
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8619 { MOD_TABLE (MOD_VEX_0F17
) },
8639 { VEX_W_TABLE (VEX_W_0F28
) },
8640 { VEX_W_TABLE (VEX_W_0F29
) },
8641 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8642 { MOD_TABLE (MOD_VEX_0F2B
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8684 { MOD_TABLE (MOD_VEX_0F50
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8688 { "vandpX", { XM
, Vex
, EXx
} },
8689 { "vandnpX", { XM
, Vex
, EXx
} },
8690 { "vorpX", { XM
, Vex
, EXx
} },
8691 { "vxorpX", { XM
, Vex
, EXx
} },
8693 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8721 { REG_TABLE (REG_VEX_0F71
) },
8722 { REG_TABLE (REG_VEX_0F72
) },
8723 { REG_TABLE (REG_VEX_0F73
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8789 { REG_TABLE (REG_VEX_0FAE
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8816 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8828 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8963 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8985 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9158 { REG_TABLE (REG_VEX_0F38F3
) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9181 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9212 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9213 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9231 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9293 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9294 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9426 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9446 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9466 #define NEED_OPCODE_TABLE
9467 #include "i386-dis-evex.h"
9468 #undef NEED_OPCODE_TABLE
9469 static const struct dis386 vex_len_table
[][2] = {
9470 /* VEX_LEN_0F10_P_1 */
9472 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9473 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9476 /* VEX_LEN_0F10_P_3 */
9478 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9479 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9482 /* VEX_LEN_0F11_P_1 */
9484 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9485 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9488 /* VEX_LEN_0F11_P_3 */
9490 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9491 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9494 /* VEX_LEN_0F12_P_0_M_0 */
9496 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9499 /* VEX_LEN_0F12_P_0_M_1 */
9501 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9504 /* VEX_LEN_0F12_P_2 */
9506 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9509 /* VEX_LEN_0F13_M_0 */
9511 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9514 /* VEX_LEN_0F16_P_0_M_0 */
9516 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9519 /* VEX_LEN_0F16_P_0_M_1 */
9521 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9524 /* VEX_LEN_0F16_P_2 */
9526 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9529 /* VEX_LEN_0F17_M_0 */
9531 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9534 /* VEX_LEN_0F2A_P_1 */
9536 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9537 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9540 /* VEX_LEN_0F2A_P_3 */
9542 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9543 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9546 /* VEX_LEN_0F2C_P_1 */
9548 { "vcvttss2siY", { Gv
, EXdScalar
} },
9549 { "vcvttss2siY", { Gv
, EXdScalar
} },
9552 /* VEX_LEN_0F2C_P_3 */
9554 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9555 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9558 /* VEX_LEN_0F2D_P_1 */
9560 { "vcvtss2siY", { Gv
, EXdScalar
} },
9561 { "vcvtss2siY", { Gv
, EXdScalar
} },
9564 /* VEX_LEN_0F2D_P_3 */
9566 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9567 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9570 /* VEX_LEN_0F2E_P_0 */
9572 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9573 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9576 /* VEX_LEN_0F2E_P_2 */
9578 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9579 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9582 /* VEX_LEN_0F2F_P_0 */
9584 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9585 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9588 /* VEX_LEN_0F2F_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9591 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9594 /* VEX_LEN_0F41_P_0 */
9597 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9599 /* VEX_LEN_0F41_P_2 */
9602 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9604 /* VEX_LEN_0F42_P_0 */
9607 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9609 /* VEX_LEN_0F42_P_2 */
9612 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9614 /* VEX_LEN_0F44_P_0 */
9616 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9618 /* VEX_LEN_0F44_P_2 */
9620 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9622 /* VEX_LEN_0F45_P_0 */
9625 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9627 /* VEX_LEN_0F45_P_2 */
9630 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9632 /* VEX_LEN_0F46_P_0 */
9635 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9637 /* VEX_LEN_0F46_P_2 */
9640 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9642 /* VEX_LEN_0F47_P_0 */
9645 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9647 /* VEX_LEN_0F47_P_2 */
9650 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9652 /* VEX_LEN_0F4A_P_0 */
9655 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9657 /* VEX_LEN_0F4A_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9662 /* VEX_LEN_0F4B_P_0 */
9665 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9667 /* VEX_LEN_0F4B_P_2 */
9670 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9673 /* VEX_LEN_0F51_P_1 */
9675 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9676 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9679 /* VEX_LEN_0F51_P_3 */
9681 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9682 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9685 /* VEX_LEN_0F52_P_1 */
9687 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9688 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9691 /* VEX_LEN_0F53_P_1 */
9693 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9694 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9697 /* VEX_LEN_0F58_P_1 */
9699 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9700 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9703 /* VEX_LEN_0F58_P_3 */
9705 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9706 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9709 /* VEX_LEN_0F59_P_1 */
9711 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9712 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9715 /* VEX_LEN_0F59_P_3 */
9717 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9718 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9721 /* VEX_LEN_0F5A_P_1 */
9723 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9724 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9727 /* VEX_LEN_0F5A_P_3 */
9729 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9730 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9733 /* VEX_LEN_0F5C_P_1 */
9735 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9736 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9739 /* VEX_LEN_0F5C_P_3 */
9741 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9742 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9745 /* VEX_LEN_0F5D_P_1 */
9747 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9748 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9751 /* VEX_LEN_0F5D_P_3 */
9753 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9754 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9757 /* VEX_LEN_0F5E_P_1 */
9759 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9760 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9763 /* VEX_LEN_0F5E_P_3 */
9765 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9766 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9769 /* VEX_LEN_0F5F_P_1 */
9771 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9772 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9775 /* VEX_LEN_0F5F_P_3 */
9777 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9778 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9781 /* VEX_LEN_0F6E_P_2 */
9783 { "vmovK", { XMScalar
, Edq
} },
9784 { "vmovK", { XMScalar
, Edq
} },
9787 /* VEX_LEN_0F7E_P_1 */
9789 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9790 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9793 /* VEX_LEN_0F7E_P_2 */
9795 { "vmovK", { Edq
, XMScalar
} },
9796 { "vmovK", { Edq
, XMScalar
} },
9799 /* VEX_LEN_0F90_P_0 */
9801 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9804 /* VEX_LEN_0F90_P_2 */
9806 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9809 /* VEX_LEN_0F91_P_0 */
9811 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9814 /* VEX_LEN_0F91_P_2 */
9816 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9819 /* VEX_LEN_0F92_P_0 */
9821 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9824 /* VEX_LEN_0F92_P_2 */
9826 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9829 /* VEX_LEN_0F92_P_3 */
9831 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9834 /* VEX_LEN_0F93_P_0 */
9836 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9839 /* VEX_LEN_0F93_P_2 */
9841 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9844 /* VEX_LEN_0F93_P_3 */
9846 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9849 /* VEX_LEN_0F98_P_0 */
9851 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9854 /* VEX_LEN_0F98_P_2 */
9856 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9859 /* VEX_LEN_0F99_P_0 */
9861 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9864 /* VEX_LEN_0F99_P_2 */
9866 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9869 /* VEX_LEN_0FAE_R_2_M_0 */
9871 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9874 /* VEX_LEN_0FAE_R_3_M_0 */
9876 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9879 /* VEX_LEN_0FC2_P_1 */
9881 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9882 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9885 /* VEX_LEN_0FC2_P_3 */
9887 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9888 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9891 /* VEX_LEN_0FC4_P_2 */
9893 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9896 /* VEX_LEN_0FC5_P_2 */
9898 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9901 /* VEX_LEN_0FD6_P_2 */
9903 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9904 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9907 /* VEX_LEN_0FF7_P_2 */
9909 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9912 /* VEX_LEN_0F3816_P_2 */
9915 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9918 /* VEX_LEN_0F3819_P_2 */
9921 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9924 /* VEX_LEN_0F381A_P_2_M_0 */
9927 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9930 /* VEX_LEN_0F3836_P_2 */
9933 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9936 /* VEX_LEN_0F3841_P_2 */
9938 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9941 /* VEX_LEN_0F385A_P_2_M_0 */
9944 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9947 /* VEX_LEN_0F38DB_P_2 */
9949 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9952 /* VEX_LEN_0F38DC_P_2 */
9954 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9957 /* VEX_LEN_0F38DD_P_2 */
9959 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9962 /* VEX_LEN_0F38DE_P_2 */
9964 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9967 /* VEX_LEN_0F38DF_P_2 */
9969 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9972 /* VEX_LEN_0F38F2_P_0 */
9974 { "andnS", { Gdq
, VexGdq
, Edq
} },
9977 /* VEX_LEN_0F38F3_R_1_P_0 */
9979 { "blsrS", { VexGdq
, Edq
} },
9982 /* VEX_LEN_0F38F3_R_2_P_0 */
9984 { "blsmskS", { VexGdq
, Edq
} },
9987 /* VEX_LEN_0F38F3_R_3_P_0 */
9989 { "blsiS", { VexGdq
, Edq
} },
9992 /* VEX_LEN_0F38F5_P_0 */
9994 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
9997 /* VEX_LEN_0F38F5_P_1 */
9999 { "pextS", { Gdq
, VexGdq
, Edq
} },
10002 /* VEX_LEN_0F38F5_P_3 */
10004 { "pdepS", { Gdq
, VexGdq
, Edq
} },
10007 /* VEX_LEN_0F38F6_P_3 */
10009 { "mulxS", { Gdq
, VexGdq
, Edq
} },
10012 /* VEX_LEN_0F38F7_P_0 */
10014 { "bextrS", { Gdq
, Edq
, VexGdq
} },
10017 /* VEX_LEN_0F38F7_P_1 */
10019 { "sarxS", { Gdq
, Edq
, VexGdq
} },
10022 /* VEX_LEN_0F38F7_P_2 */
10024 { "shlxS", { Gdq
, Edq
, VexGdq
} },
10027 /* VEX_LEN_0F38F7_P_3 */
10029 { "shrxS", { Gdq
, Edq
, VexGdq
} },
10032 /* VEX_LEN_0F3A00_P_2 */
10035 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10038 /* VEX_LEN_0F3A01_P_2 */
10041 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10044 /* VEX_LEN_0F3A06_P_2 */
10047 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10050 /* VEX_LEN_0F3A0A_P_2 */
10052 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10053 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10056 /* VEX_LEN_0F3A0B_P_2 */
10058 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10059 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10062 /* VEX_LEN_0F3A14_P_2 */
10064 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10067 /* VEX_LEN_0F3A15_P_2 */
10069 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10072 /* VEX_LEN_0F3A16_P_2 */
10074 { "vpextrK", { Edq
, XM
, Ib
} },
10077 /* VEX_LEN_0F3A17_P_2 */
10079 { "vextractps", { Edqd
, XM
, Ib
} },
10082 /* VEX_LEN_0F3A18_P_2 */
10085 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10088 /* VEX_LEN_0F3A19_P_2 */
10091 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10094 /* VEX_LEN_0F3A20_P_2 */
10096 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10099 /* VEX_LEN_0F3A21_P_2 */
10101 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10104 /* VEX_LEN_0F3A22_P_2 */
10106 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
10109 /* VEX_LEN_0F3A30_P_2 */
10111 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10114 /* VEX_LEN_0F3A31_P_2 */
10116 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10119 /* VEX_LEN_0F3A32_P_2 */
10121 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10124 /* VEX_LEN_0F3A33_P_2 */
10126 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10129 /* VEX_LEN_0F3A38_P_2 */
10132 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10135 /* VEX_LEN_0F3A39_P_2 */
10138 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10141 /* VEX_LEN_0F3A41_P_2 */
10143 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10146 /* VEX_LEN_0F3A44_P_2 */
10148 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
10151 /* VEX_LEN_0F3A46_P_2 */
10154 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10157 /* VEX_LEN_0F3A60_P_2 */
10159 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
10162 /* VEX_LEN_0F3A61_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
10167 /* VEX_LEN_0F3A62_P_2 */
10169 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10172 /* VEX_LEN_0F3A63_P_2 */
10174 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10177 /* VEX_LEN_0F3A6A_P_2 */
10179 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10182 /* VEX_LEN_0F3A6B_P_2 */
10184 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10187 /* VEX_LEN_0F3A6E_P_2 */
10189 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10192 /* VEX_LEN_0F3A6F_P_2 */
10194 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10197 /* VEX_LEN_0F3A7A_P_2 */
10199 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10202 /* VEX_LEN_0F3A7B_P_2 */
10204 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10207 /* VEX_LEN_0F3A7E_P_2 */
10209 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
10212 /* VEX_LEN_0F3A7F_P_2 */
10214 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
10217 /* VEX_LEN_0F3ADF_P_2 */
10219 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10222 /* VEX_LEN_0F3AF0_P_3 */
10224 { "rorxS", { Gdq
, Edq
, Ib
} },
10227 /* VEX_LEN_0FXOP_08_CC */
10229 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
10232 /* VEX_LEN_0FXOP_08_CD */
10234 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
10237 /* VEX_LEN_0FXOP_08_CE */
10239 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
10242 /* VEX_LEN_0FXOP_08_CF */
10244 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
10247 /* VEX_LEN_0FXOP_08_EC */
10249 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
10252 /* VEX_LEN_0FXOP_08_ED */
10254 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
10257 /* VEX_LEN_0FXOP_08_EE */
10259 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
10262 /* VEX_LEN_0FXOP_08_EF */
10264 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
10267 /* VEX_LEN_0FXOP_09_80 */
10269 { "vfrczps", { XM
, EXxmm
} },
10270 { "vfrczps", { XM
, EXymmq
} },
10273 /* VEX_LEN_0FXOP_09_81 */
10275 { "vfrczpd", { XM
, EXxmm
} },
10276 { "vfrczpd", { XM
, EXymmq
} },
10280 static const struct dis386 vex_w_table
[][2] = {
10282 /* VEX_W_0F10_P_0 */
10283 { "vmovups", { XM
, EXx
} },
10286 /* VEX_W_0F10_P_1 */
10287 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
10290 /* VEX_W_0F10_P_2 */
10291 { "vmovupd", { XM
, EXx
} },
10294 /* VEX_W_0F10_P_3 */
10295 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
10298 /* VEX_W_0F11_P_0 */
10299 { "vmovups", { EXxS
, XM
} },
10302 /* VEX_W_0F11_P_1 */
10303 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
10306 /* VEX_W_0F11_P_2 */
10307 { "vmovupd", { EXxS
, XM
} },
10310 /* VEX_W_0F11_P_3 */
10311 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
10314 /* VEX_W_0F12_P_0_M_0 */
10315 { "vmovlps", { XM
, Vex128
, EXq
} },
10318 /* VEX_W_0F12_P_0_M_1 */
10319 { "vmovhlps", { XM
, Vex128
, EXq
} },
10322 /* VEX_W_0F12_P_1 */
10323 { "vmovsldup", { XM
, EXx
} },
10326 /* VEX_W_0F12_P_2 */
10327 { "vmovlpd", { XM
, Vex128
, EXq
} },
10330 /* VEX_W_0F12_P_3 */
10331 { "vmovddup", { XM
, EXymmq
} },
10334 /* VEX_W_0F13_M_0 */
10335 { "vmovlpX", { EXq
, XM
} },
10339 { "vunpcklpX", { XM
, Vex
, EXx
} },
10343 { "vunpckhpX", { XM
, Vex
, EXx
} },
10346 /* VEX_W_0F16_P_0_M_0 */
10347 { "vmovhps", { XM
, Vex128
, EXq
} },
10350 /* VEX_W_0F16_P_0_M_1 */
10351 { "vmovlhps", { XM
, Vex128
, EXq
} },
10354 /* VEX_W_0F16_P_1 */
10355 { "vmovshdup", { XM
, EXx
} },
10358 /* VEX_W_0F16_P_2 */
10359 { "vmovhpd", { XM
, Vex128
, EXq
} },
10362 /* VEX_W_0F17_M_0 */
10363 { "vmovhpX", { EXq
, XM
} },
10367 { "vmovapX", { XM
, EXx
} },
10371 { "vmovapX", { EXxS
, XM
} },
10374 /* VEX_W_0F2B_M_0 */
10375 { "vmovntpX", { Mx
, XM
} },
10378 /* VEX_W_0F2E_P_0 */
10379 { "vucomiss", { XMScalar
, EXdScalar
} },
10382 /* VEX_W_0F2E_P_2 */
10383 { "vucomisd", { XMScalar
, EXqScalar
} },
10386 /* VEX_W_0F2F_P_0 */
10387 { "vcomiss", { XMScalar
, EXdScalar
} },
10390 /* VEX_W_0F2F_P_2 */
10391 { "vcomisd", { XMScalar
, EXqScalar
} },
10394 /* VEX_W_0F41_P_0_LEN_1 */
10395 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10396 { "kandq", { MaskG
, MaskVex
, MaskR
} },
10399 /* VEX_W_0F41_P_2_LEN_1 */
10400 { "kandb", { MaskG
, MaskVex
, MaskR
} },
10401 { "kandd", { MaskG
, MaskVex
, MaskR
} },
10404 /* VEX_W_0F42_P_0_LEN_1 */
10405 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10406 { "kandnq", { MaskG
, MaskVex
, MaskR
} },
10409 /* VEX_W_0F42_P_2_LEN_1 */
10410 { "kandnb", { MaskG
, MaskVex
, MaskR
} },
10411 { "kandnd", { MaskG
, MaskVex
, MaskR
} },
10414 /* VEX_W_0F44_P_0_LEN_0 */
10415 { "knotw", { MaskG
, MaskR
} },
10416 { "knotq", { MaskG
, MaskR
} },
10419 /* VEX_W_0F44_P_2_LEN_0 */
10420 { "knotb", { MaskG
, MaskR
} },
10421 { "knotd", { MaskG
, MaskR
} },
10424 /* VEX_W_0F45_P_0_LEN_1 */
10425 { "korw", { MaskG
, MaskVex
, MaskR
} },
10426 { "korq", { MaskG
, MaskVex
, MaskR
} },
10429 /* VEX_W_0F45_P_2_LEN_1 */
10430 { "korb", { MaskG
, MaskVex
, MaskR
} },
10431 { "kord", { MaskG
, MaskVex
, MaskR
} },
10434 /* VEX_W_0F46_P_0_LEN_1 */
10435 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10436 { "kxnorq", { MaskG
, MaskVex
, MaskR
} },
10439 /* VEX_W_0F46_P_2_LEN_1 */
10440 { "kxnorb", { MaskG
, MaskVex
, MaskR
} },
10441 { "kxnord", { MaskG
, MaskVex
, MaskR
} },
10444 /* VEX_W_0F47_P_0_LEN_1 */
10445 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10446 { "kxorq", { MaskG
, MaskVex
, MaskR
} },
10449 /* VEX_W_0F47_P_2_LEN_1 */
10450 { "kxorb", { MaskG
, MaskVex
, MaskR
} },
10451 { "kxord", { MaskG
, MaskVex
, MaskR
} },
10454 /* VEX_W_0F4A_P_0_LEN_1 */
10455 { "kaddw", { MaskG
, MaskVex
, MaskR
} },
10456 { "kaddq", { MaskG
, MaskVex
, MaskR
} },
10459 /* VEX_W_0F4A_P_2_LEN_1 */
10460 { "kaddb", { MaskG
, MaskVex
, MaskR
} },
10461 { "kaddd", { MaskG
, MaskVex
, MaskR
} },
10464 /* VEX_W_0F4B_P_0_LEN_1 */
10465 { "kunpckwd", { MaskG
, MaskVex
, MaskR
} },
10466 { "kunpckdq", { MaskG
, MaskVex
, MaskR
} },
10469 /* VEX_W_0F4B_P_2_LEN_1 */
10470 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10473 /* VEX_W_0F50_M_0 */
10474 { "vmovmskpX", { Gdq
, XS
} },
10477 /* VEX_W_0F51_P_0 */
10478 { "vsqrtps", { XM
, EXx
} },
10481 /* VEX_W_0F51_P_1 */
10482 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10485 /* VEX_W_0F51_P_2 */
10486 { "vsqrtpd", { XM
, EXx
} },
10489 /* VEX_W_0F51_P_3 */
10490 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10493 /* VEX_W_0F52_P_0 */
10494 { "vrsqrtps", { XM
, EXx
} },
10497 /* VEX_W_0F52_P_1 */
10498 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10501 /* VEX_W_0F53_P_0 */
10502 { "vrcpps", { XM
, EXx
} },
10505 /* VEX_W_0F53_P_1 */
10506 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10509 /* VEX_W_0F58_P_0 */
10510 { "vaddps", { XM
, Vex
, EXx
} },
10513 /* VEX_W_0F58_P_1 */
10514 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10517 /* VEX_W_0F58_P_2 */
10518 { "vaddpd", { XM
, Vex
, EXx
} },
10521 /* VEX_W_0F58_P_3 */
10522 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10525 /* VEX_W_0F59_P_0 */
10526 { "vmulps", { XM
, Vex
, EXx
} },
10529 /* VEX_W_0F59_P_1 */
10530 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10533 /* VEX_W_0F59_P_2 */
10534 { "vmulpd", { XM
, Vex
, EXx
} },
10537 /* VEX_W_0F59_P_3 */
10538 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10541 /* VEX_W_0F5A_P_0 */
10542 { "vcvtps2pd", { XM
, EXxmmq
} },
10545 /* VEX_W_0F5A_P_1 */
10546 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10549 /* VEX_W_0F5A_P_3 */
10550 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10553 /* VEX_W_0F5B_P_0 */
10554 { "vcvtdq2ps", { XM
, EXx
} },
10557 /* VEX_W_0F5B_P_1 */
10558 { "vcvttps2dq", { XM
, EXx
} },
10561 /* VEX_W_0F5B_P_2 */
10562 { "vcvtps2dq", { XM
, EXx
} },
10565 /* VEX_W_0F5C_P_0 */
10566 { "vsubps", { XM
, Vex
, EXx
} },
10569 /* VEX_W_0F5C_P_1 */
10570 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10573 /* VEX_W_0F5C_P_2 */
10574 { "vsubpd", { XM
, Vex
, EXx
} },
10577 /* VEX_W_0F5C_P_3 */
10578 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10581 /* VEX_W_0F5D_P_0 */
10582 { "vminps", { XM
, Vex
, EXx
} },
10585 /* VEX_W_0F5D_P_1 */
10586 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10589 /* VEX_W_0F5D_P_2 */
10590 { "vminpd", { XM
, Vex
, EXx
} },
10593 /* VEX_W_0F5D_P_3 */
10594 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10597 /* VEX_W_0F5E_P_0 */
10598 { "vdivps", { XM
, Vex
, EXx
} },
10601 /* VEX_W_0F5E_P_1 */
10602 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10605 /* VEX_W_0F5E_P_2 */
10606 { "vdivpd", { XM
, Vex
, EXx
} },
10609 /* VEX_W_0F5E_P_3 */
10610 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10613 /* VEX_W_0F5F_P_0 */
10614 { "vmaxps", { XM
, Vex
, EXx
} },
10617 /* VEX_W_0F5F_P_1 */
10618 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10621 /* VEX_W_0F5F_P_2 */
10622 { "vmaxpd", { XM
, Vex
, EXx
} },
10625 /* VEX_W_0F5F_P_3 */
10626 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10629 /* VEX_W_0F60_P_2 */
10630 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10633 /* VEX_W_0F61_P_2 */
10634 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10637 /* VEX_W_0F62_P_2 */
10638 { "vpunpckldq", { XM
, Vex
, EXx
} },
10641 /* VEX_W_0F63_P_2 */
10642 { "vpacksswb", { XM
, Vex
, EXx
} },
10645 /* VEX_W_0F64_P_2 */
10646 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10649 /* VEX_W_0F65_P_2 */
10650 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10653 /* VEX_W_0F66_P_2 */
10654 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10657 /* VEX_W_0F67_P_2 */
10658 { "vpackuswb", { XM
, Vex
, EXx
} },
10661 /* VEX_W_0F68_P_2 */
10662 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10665 /* VEX_W_0F69_P_2 */
10666 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10669 /* VEX_W_0F6A_P_2 */
10670 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10673 /* VEX_W_0F6B_P_2 */
10674 { "vpackssdw", { XM
, Vex
, EXx
} },
10677 /* VEX_W_0F6C_P_2 */
10678 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10681 /* VEX_W_0F6D_P_2 */
10682 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10685 /* VEX_W_0F6F_P_1 */
10686 { "vmovdqu", { XM
, EXx
} },
10689 /* VEX_W_0F6F_P_2 */
10690 { "vmovdqa", { XM
, EXx
} },
10693 /* VEX_W_0F70_P_1 */
10694 { "vpshufhw", { XM
, EXx
, Ib
} },
10697 /* VEX_W_0F70_P_2 */
10698 { "vpshufd", { XM
, EXx
, Ib
} },
10701 /* VEX_W_0F70_P_3 */
10702 { "vpshuflw", { XM
, EXx
, Ib
} },
10705 /* VEX_W_0F71_R_2_P_2 */
10706 { "vpsrlw", { Vex
, XS
, Ib
} },
10709 /* VEX_W_0F71_R_4_P_2 */
10710 { "vpsraw", { Vex
, XS
, Ib
} },
10713 /* VEX_W_0F71_R_6_P_2 */
10714 { "vpsllw", { Vex
, XS
, Ib
} },
10717 /* VEX_W_0F72_R_2_P_2 */
10718 { "vpsrld", { Vex
, XS
, Ib
} },
10721 /* VEX_W_0F72_R_4_P_2 */
10722 { "vpsrad", { Vex
, XS
, Ib
} },
10725 /* VEX_W_0F72_R_6_P_2 */
10726 { "vpslld", { Vex
, XS
, Ib
} },
10729 /* VEX_W_0F73_R_2_P_2 */
10730 { "vpsrlq", { Vex
, XS
, Ib
} },
10733 /* VEX_W_0F73_R_3_P_2 */
10734 { "vpsrldq", { Vex
, XS
, Ib
} },
10737 /* VEX_W_0F73_R_6_P_2 */
10738 { "vpsllq", { Vex
, XS
, Ib
} },
10741 /* VEX_W_0F73_R_7_P_2 */
10742 { "vpslldq", { Vex
, XS
, Ib
} },
10745 /* VEX_W_0F74_P_2 */
10746 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10749 /* VEX_W_0F75_P_2 */
10750 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10753 /* VEX_W_0F76_P_2 */
10754 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10757 /* VEX_W_0F77_P_0 */
10761 /* VEX_W_0F7C_P_2 */
10762 { "vhaddpd", { XM
, Vex
, EXx
} },
10765 /* VEX_W_0F7C_P_3 */
10766 { "vhaddps", { XM
, Vex
, EXx
} },
10769 /* VEX_W_0F7D_P_2 */
10770 { "vhsubpd", { XM
, Vex
, EXx
} },
10773 /* VEX_W_0F7D_P_3 */
10774 { "vhsubps", { XM
, Vex
, EXx
} },
10777 /* VEX_W_0F7E_P_1 */
10778 { "vmovq", { XMScalar
, EXqScalar
} },
10781 /* VEX_W_0F7F_P_1 */
10782 { "vmovdqu", { EXxS
, XM
} },
10785 /* VEX_W_0F7F_P_2 */
10786 { "vmovdqa", { EXxS
, XM
} },
10789 /* VEX_W_0F90_P_0_LEN_0 */
10790 { "kmovw", { MaskG
, MaskE
} },
10791 { "kmovq", { MaskG
, MaskE
} },
10794 /* VEX_W_0F90_P_2_LEN_0 */
10795 { "kmovb", { MaskG
, MaskBDE
} },
10796 { "kmovd", { MaskG
, MaskBDE
} },
10799 /* VEX_W_0F91_P_0_LEN_0 */
10800 { "kmovw", { Ew
, MaskG
} },
10801 { "kmovq", { Eq
, MaskG
} },
10804 /* VEX_W_0F91_P_2_LEN_0 */
10805 { "kmovb", { Eb
, MaskG
} },
10806 { "kmovd", { Ed
, MaskG
} },
10809 /* VEX_W_0F92_P_0_LEN_0 */
10810 { "kmovw", { MaskG
, Rdq
} },
10813 /* VEX_W_0F92_P_2_LEN_0 */
10814 { "kmovb", { MaskG
, Rdq
} },
10817 /* VEX_W_0F92_P_3_LEN_0 */
10818 { "kmovd", { MaskG
, Rdq
} },
10819 { "kmovq", { MaskG
, Rdq
} },
10822 /* VEX_W_0F93_P_0_LEN_0 */
10823 { "kmovw", { Gdq
, MaskR
} },
10826 /* VEX_W_0F93_P_2_LEN_0 */
10827 { "kmovb", { Gdq
, MaskR
} },
10830 /* VEX_W_0F93_P_3_LEN_0 */
10831 { "kmovd", { Gdq
, MaskR
} },
10832 { "kmovq", { Gdq
, MaskR
} },
10835 /* VEX_W_0F98_P_0_LEN_0 */
10836 { "kortestw", { MaskG
, MaskR
} },
10837 { "kortestq", { MaskG
, MaskR
} },
10840 /* VEX_W_0F98_P_2_LEN_0 */
10841 { "kortestb", { MaskG
, MaskR
} },
10842 { "kortestd", { MaskG
, MaskR
} },
10845 /* VEX_W_0F99_P_0_LEN_0 */
10846 { "ktestw", { MaskG
, MaskR
} },
10847 { "ktestq", { MaskG
, MaskR
} },
10850 /* VEX_W_0F99_P_2_LEN_0 */
10851 { "ktestb", { MaskG
, MaskR
} },
10852 { "ktestd", { MaskG
, MaskR
} },
10855 /* VEX_W_0FAE_R_2_M_0 */
10856 { "vldmxcsr", { Md
} },
10859 /* VEX_W_0FAE_R_3_M_0 */
10860 { "vstmxcsr", { Md
} },
10863 /* VEX_W_0FC2_P_0 */
10864 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10867 /* VEX_W_0FC2_P_1 */
10868 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10871 /* VEX_W_0FC2_P_2 */
10872 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10875 /* VEX_W_0FC2_P_3 */
10876 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10879 /* VEX_W_0FC4_P_2 */
10880 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10883 /* VEX_W_0FC5_P_2 */
10884 { "vpextrw", { Gdq
, XS
, Ib
} },
10887 /* VEX_W_0FD0_P_2 */
10888 { "vaddsubpd", { XM
, Vex
, EXx
} },
10891 /* VEX_W_0FD0_P_3 */
10892 { "vaddsubps", { XM
, Vex
, EXx
} },
10895 /* VEX_W_0FD1_P_2 */
10896 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10899 /* VEX_W_0FD2_P_2 */
10900 { "vpsrld", { XM
, Vex
, EXxmm
} },
10903 /* VEX_W_0FD3_P_2 */
10904 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10907 /* VEX_W_0FD4_P_2 */
10908 { "vpaddq", { XM
, Vex
, EXx
} },
10911 /* VEX_W_0FD5_P_2 */
10912 { "vpmullw", { XM
, Vex
, EXx
} },
10915 /* VEX_W_0FD6_P_2 */
10916 { "vmovq", { EXqScalarS
, XMScalar
} },
10919 /* VEX_W_0FD7_P_2_M_1 */
10920 { "vpmovmskb", { Gdq
, XS
} },
10923 /* VEX_W_0FD8_P_2 */
10924 { "vpsubusb", { XM
, Vex
, EXx
} },
10927 /* VEX_W_0FD9_P_2 */
10928 { "vpsubusw", { XM
, Vex
, EXx
} },
10931 /* VEX_W_0FDA_P_2 */
10932 { "vpminub", { XM
, Vex
, EXx
} },
10935 /* VEX_W_0FDB_P_2 */
10936 { "vpand", { XM
, Vex
, EXx
} },
10939 /* VEX_W_0FDC_P_2 */
10940 { "vpaddusb", { XM
, Vex
, EXx
} },
10943 /* VEX_W_0FDD_P_2 */
10944 { "vpaddusw", { XM
, Vex
, EXx
} },
10947 /* VEX_W_0FDE_P_2 */
10948 { "vpmaxub", { XM
, Vex
, EXx
} },
10951 /* VEX_W_0FDF_P_2 */
10952 { "vpandn", { XM
, Vex
, EXx
} },
10955 /* VEX_W_0FE0_P_2 */
10956 { "vpavgb", { XM
, Vex
, EXx
} },
10959 /* VEX_W_0FE1_P_2 */
10960 { "vpsraw", { XM
, Vex
, EXxmm
} },
10963 /* VEX_W_0FE2_P_2 */
10964 { "vpsrad", { XM
, Vex
, EXxmm
} },
10967 /* VEX_W_0FE3_P_2 */
10968 { "vpavgw", { XM
, Vex
, EXx
} },
10971 /* VEX_W_0FE4_P_2 */
10972 { "vpmulhuw", { XM
, Vex
, EXx
} },
10975 /* VEX_W_0FE5_P_2 */
10976 { "vpmulhw", { XM
, Vex
, EXx
} },
10979 /* VEX_W_0FE6_P_1 */
10980 { "vcvtdq2pd", { XM
, EXxmmq
} },
10983 /* VEX_W_0FE6_P_2 */
10984 { "vcvttpd2dq%XY", { XMM
, EXx
} },
10987 /* VEX_W_0FE6_P_3 */
10988 { "vcvtpd2dq%XY", { XMM
, EXx
} },
10991 /* VEX_W_0FE7_P_2_M_0 */
10992 { "vmovntdq", { Mx
, XM
} },
10995 /* VEX_W_0FE8_P_2 */
10996 { "vpsubsb", { XM
, Vex
, EXx
} },
10999 /* VEX_W_0FE9_P_2 */
11000 { "vpsubsw", { XM
, Vex
, EXx
} },
11003 /* VEX_W_0FEA_P_2 */
11004 { "vpminsw", { XM
, Vex
, EXx
} },
11007 /* VEX_W_0FEB_P_2 */
11008 { "vpor", { XM
, Vex
, EXx
} },
11011 /* VEX_W_0FEC_P_2 */
11012 { "vpaddsb", { XM
, Vex
, EXx
} },
11015 /* VEX_W_0FED_P_2 */
11016 { "vpaddsw", { XM
, Vex
, EXx
} },
11019 /* VEX_W_0FEE_P_2 */
11020 { "vpmaxsw", { XM
, Vex
, EXx
} },
11023 /* VEX_W_0FEF_P_2 */
11024 { "vpxor", { XM
, Vex
, EXx
} },
11027 /* VEX_W_0FF0_P_3_M_0 */
11028 { "vlddqu", { XM
, M
} },
11031 /* VEX_W_0FF1_P_2 */
11032 { "vpsllw", { XM
, Vex
, EXxmm
} },
11035 /* VEX_W_0FF2_P_2 */
11036 { "vpslld", { XM
, Vex
, EXxmm
} },
11039 /* VEX_W_0FF3_P_2 */
11040 { "vpsllq", { XM
, Vex
, EXxmm
} },
11043 /* VEX_W_0FF4_P_2 */
11044 { "vpmuludq", { XM
, Vex
, EXx
} },
11047 /* VEX_W_0FF5_P_2 */
11048 { "vpmaddwd", { XM
, Vex
, EXx
} },
11051 /* VEX_W_0FF6_P_2 */
11052 { "vpsadbw", { XM
, Vex
, EXx
} },
11055 /* VEX_W_0FF7_P_2 */
11056 { "vmaskmovdqu", { XM
, XS
} },
11059 /* VEX_W_0FF8_P_2 */
11060 { "vpsubb", { XM
, Vex
, EXx
} },
11063 /* VEX_W_0FF9_P_2 */
11064 { "vpsubw", { XM
, Vex
, EXx
} },
11067 /* VEX_W_0FFA_P_2 */
11068 { "vpsubd", { XM
, Vex
, EXx
} },
11071 /* VEX_W_0FFB_P_2 */
11072 { "vpsubq", { XM
, Vex
, EXx
} },
11075 /* VEX_W_0FFC_P_2 */
11076 { "vpaddb", { XM
, Vex
, EXx
} },
11079 /* VEX_W_0FFD_P_2 */
11080 { "vpaddw", { XM
, Vex
, EXx
} },
11083 /* VEX_W_0FFE_P_2 */
11084 { "vpaddd", { XM
, Vex
, EXx
} },
11087 /* VEX_W_0F3800_P_2 */
11088 { "vpshufb", { XM
, Vex
, EXx
} },
11091 /* VEX_W_0F3801_P_2 */
11092 { "vphaddw", { XM
, Vex
, EXx
} },
11095 /* VEX_W_0F3802_P_2 */
11096 { "vphaddd", { XM
, Vex
, EXx
} },
11099 /* VEX_W_0F3803_P_2 */
11100 { "vphaddsw", { XM
, Vex
, EXx
} },
11103 /* VEX_W_0F3804_P_2 */
11104 { "vpmaddubsw", { XM
, Vex
, EXx
} },
11107 /* VEX_W_0F3805_P_2 */
11108 { "vphsubw", { XM
, Vex
, EXx
} },
11111 /* VEX_W_0F3806_P_2 */
11112 { "vphsubd", { XM
, Vex
, EXx
} },
11115 /* VEX_W_0F3807_P_2 */
11116 { "vphsubsw", { XM
, Vex
, EXx
} },
11119 /* VEX_W_0F3808_P_2 */
11120 { "vpsignb", { XM
, Vex
, EXx
} },
11123 /* VEX_W_0F3809_P_2 */
11124 { "vpsignw", { XM
, Vex
, EXx
} },
11127 /* VEX_W_0F380A_P_2 */
11128 { "vpsignd", { XM
, Vex
, EXx
} },
11131 /* VEX_W_0F380B_P_2 */
11132 { "vpmulhrsw", { XM
, Vex
, EXx
} },
11135 /* VEX_W_0F380C_P_2 */
11136 { "vpermilps", { XM
, Vex
, EXx
} },
11139 /* VEX_W_0F380D_P_2 */
11140 { "vpermilpd", { XM
, Vex
, EXx
} },
11143 /* VEX_W_0F380E_P_2 */
11144 { "vtestps", { XM
, EXx
} },
11147 /* VEX_W_0F380F_P_2 */
11148 { "vtestpd", { XM
, EXx
} },
11151 /* VEX_W_0F3816_P_2 */
11152 { "vpermps", { XM
, Vex
, EXx
} },
11155 /* VEX_W_0F3817_P_2 */
11156 { "vptest", { XM
, EXx
} },
11159 /* VEX_W_0F3818_P_2 */
11160 { "vbroadcastss", { XM
, EXxmm_md
} },
11163 /* VEX_W_0F3819_P_2 */
11164 { "vbroadcastsd", { XM
, EXxmm_mq
} },
11167 /* VEX_W_0F381A_P_2_M_0 */
11168 { "vbroadcastf128", { XM
, Mxmm
} },
11171 /* VEX_W_0F381C_P_2 */
11172 { "vpabsb", { XM
, EXx
} },
11175 /* VEX_W_0F381D_P_2 */
11176 { "vpabsw", { XM
, EXx
} },
11179 /* VEX_W_0F381E_P_2 */
11180 { "vpabsd", { XM
, EXx
} },
11183 /* VEX_W_0F3820_P_2 */
11184 { "vpmovsxbw", { XM
, EXxmmq
} },
11187 /* VEX_W_0F3821_P_2 */
11188 { "vpmovsxbd", { XM
, EXxmmqd
} },
11191 /* VEX_W_0F3822_P_2 */
11192 { "vpmovsxbq", { XM
, EXxmmdw
} },
11195 /* VEX_W_0F3823_P_2 */
11196 { "vpmovsxwd", { XM
, EXxmmq
} },
11199 /* VEX_W_0F3824_P_2 */
11200 { "vpmovsxwq", { XM
, EXxmmqd
} },
11203 /* VEX_W_0F3825_P_2 */
11204 { "vpmovsxdq", { XM
, EXxmmq
} },
11207 /* VEX_W_0F3828_P_2 */
11208 { "vpmuldq", { XM
, Vex
, EXx
} },
11211 /* VEX_W_0F3829_P_2 */
11212 { "vpcmpeqq", { XM
, Vex
, EXx
} },
11215 /* VEX_W_0F382A_P_2_M_0 */
11216 { "vmovntdqa", { XM
, Mx
} },
11219 /* VEX_W_0F382B_P_2 */
11220 { "vpackusdw", { XM
, Vex
, EXx
} },
11223 /* VEX_W_0F382C_P_2_M_0 */
11224 { "vmaskmovps", { XM
, Vex
, Mx
} },
11227 /* VEX_W_0F382D_P_2_M_0 */
11228 { "vmaskmovpd", { XM
, Vex
, Mx
} },
11231 /* VEX_W_0F382E_P_2_M_0 */
11232 { "vmaskmovps", { Mx
, Vex
, XM
} },
11235 /* VEX_W_0F382F_P_2_M_0 */
11236 { "vmaskmovpd", { Mx
, Vex
, XM
} },
11239 /* VEX_W_0F3830_P_2 */
11240 { "vpmovzxbw", { XM
, EXxmmq
} },
11243 /* VEX_W_0F3831_P_2 */
11244 { "vpmovzxbd", { XM
, EXxmmqd
} },
11247 /* VEX_W_0F3832_P_2 */
11248 { "vpmovzxbq", { XM
, EXxmmdw
} },
11251 /* VEX_W_0F3833_P_2 */
11252 { "vpmovzxwd", { XM
, EXxmmq
} },
11255 /* VEX_W_0F3834_P_2 */
11256 { "vpmovzxwq", { XM
, EXxmmqd
} },
11259 /* VEX_W_0F3835_P_2 */
11260 { "vpmovzxdq", { XM
, EXxmmq
} },
11263 /* VEX_W_0F3836_P_2 */
11264 { "vpermd", { XM
, Vex
, EXx
} },
11267 /* VEX_W_0F3837_P_2 */
11268 { "vpcmpgtq", { XM
, Vex
, EXx
} },
11271 /* VEX_W_0F3838_P_2 */
11272 { "vpminsb", { XM
, Vex
, EXx
} },
11275 /* VEX_W_0F3839_P_2 */
11276 { "vpminsd", { XM
, Vex
, EXx
} },
11279 /* VEX_W_0F383A_P_2 */
11280 { "vpminuw", { XM
, Vex
, EXx
} },
11283 /* VEX_W_0F383B_P_2 */
11284 { "vpminud", { XM
, Vex
, EXx
} },
11287 /* VEX_W_0F383C_P_2 */
11288 { "vpmaxsb", { XM
, Vex
, EXx
} },
11291 /* VEX_W_0F383D_P_2 */
11292 { "vpmaxsd", { XM
, Vex
, EXx
} },
11295 /* VEX_W_0F383E_P_2 */
11296 { "vpmaxuw", { XM
, Vex
, EXx
} },
11299 /* VEX_W_0F383F_P_2 */
11300 { "vpmaxud", { XM
, Vex
, EXx
} },
11303 /* VEX_W_0F3840_P_2 */
11304 { "vpmulld", { XM
, Vex
, EXx
} },
11307 /* VEX_W_0F3841_P_2 */
11308 { "vphminposuw", { XM
, EXx
} },
11311 /* VEX_W_0F3846_P_2 */
11312 { "vpsravd", { XM
, Vex
, EXx
} },
11315 /* VEX_W_0F3858_P_2 */
11316 { "vpbroadcastd", { XM
, EXxmm_md
} },
11319 /* VEX_W_0F3859_P_2 */
11320 { "vpbroadcastq", { XM
, EXxmm_mq
} },
11323 /* VEX_W_0F385A_P_2_M_0 */
11324 { "vbroadcasti128", { XM
, Mxmm
} },
11327 /* VEX_W_0F3878_P_2 */
11328 { "vpbroadcastb", { XM
, EXxmm_mb
} },
11331 /* VEX_W_0F3879_P_2 */
11332 { "vpbroadcastw", { XM
, EXxmm_mw
} },
11335 /* VEX_W_0F38DB_P_2 */
11336 { "vaesimc", { XM
, EXx
} },
11339 /* VEX_W_0F38DC_P_2 */
11340 { "vaesenc", { XM
, Vex128
, EXx
} },
11343 /* VEX_W_0F38DD_P_2 */
11344 { "vaesenclast", { XM
, Vex128
, EXx
} },
11347 /* VEX_W_0F38DE_P_2 */
11348 { "vaesdec", { XM
, Vex128
, EXx
} },
11351 /* VEX_W_0F38DF_P_2 */
11352 { "vaesdeclast", { XM
, Vex128
, EXx
} },
11355 /* VEX_W_0F3A00_P_2 */
11357 { "vpermq", { XM
, EXx
, Ib
} },
11360 /* VEX_W_0F3A01_P_2 */
11362 { "vpermpd", { XM
, EXx
, Ib
} },
11365 /* VEX_W_0F3A02_P_2 */
11366 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
11369 /* VEX_W_0F3A04_P_2 */
11370 { "vpermilps", { XM
, EXx
, Ib
} },
11373 /* VEX_W_0F3A05_P_2 */
11374 { "vpermilpd", { XM
, EXx
, Ib
} },
11377 /* VEX_W_0F3A06_P_2 */
11378 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
11381 /* VEX_W_0F3A08_P_2 */
11382 { "vroundps", { XM
, EXx
, Ib
} },
11385 /* VEX_W_0F3A09_P_2 */
11386 { "vroundpd", { XM
, EXx
, Ib
} },
11389 /* VEX_W_0F3A0A_P_2 */
11390 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
11393 /* VEX_W_0F3A0B_P_2 */
11394 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
11397 /* VEX_W_0F3A0C_P_2 */
11398 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
11401 /* VEX_W_0F3A0D_P_2 */
11402 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
11405 /* VEX_W_0F3A0E_P_2 */
11406 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
11409 /* VEX_W_0F3A0F_P_2 */
11410 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
11413 /* VEX_W_0F3A14_P_2 */
11414 { "vpextrb", { Edqb
, XM
, Ib
} },
11417 /* VEX_W_0F3A15_P_2 */
11418 { "vpextrw", { Edqw
, XM
, Ib
} },
11421 /* VEX_W_0F3A18_P_2 */
11422 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
11425 /* VEX_W_0F3A19_P_2 */
11426 { "vextractf128", { EXxmm
, XM
, Ib
} },
11429 /* VEX_W_0F3A20_P_2 */
11430 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
11433 /* VEX_W_0F3A21_P_2 */
11434 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
11437 /* VEX_W_0F3A30_P_2_LEN_0 */
11438 { "kshiftrb", { MaskG
, MaskR
, Ib
} },
11439 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
11442 /* VEX_W_0F3A31_P_2_LEN_0 */
11443 { "kshiftrd", { MaskG
, MaskR
, Ib
} },
11444 { "kshiftrq", { MaskG
, MaskR
, Ib
} },
11447 /* VEX_W_0F3A32_P_2_LEN_0 */
11448 { "kshiftlb", { MaskG
, MaskR
, Ib
} },
11449 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
11452 /* VEX_W_0F3A33_P_2_LEN_0 */
11453 { "kshiftld", { MaskG
, MaskR
, Ib
} },
11454 { "kshiftlq", { MaskG
, MaskR
, Ib
} },
11457 /* VEX_W_0F3A38_P_2 */
11458 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
11461 /* VEX_W_0F3A39_P_2 */
11462 { "vextracti128", { EXxmm
, XM
, Ib
} },
11465 /* VEX_W_0F3A40_P_2 */
11466 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
11469 /* VEX_W_0F3A41_P_2 */
11470 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
11473 /* VEX_W_0F3A42_P_2 */
11474 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
11477 /* VEX_W_0F3A44_P_2 */
11478 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11481 /* VEX_W_0F3A46_P_2 */
11482 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11485 /* VEX_W_0F3A48_P_2 */
11486 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11487 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11490 /* VEX_W_0F3A49_P_2 */
11491 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11492 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11495 /* VEX_W_0F3A4A_P_2 */
11496 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11499 /* VEX_W_0F3A4B_P_2 */
11500 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11503 /* VEX_W_0F3A4C_P_2 */
11504 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11507 /* VEX_W_0F3A60_P_2 */
11508 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11511 /* VEX_W_0F3A61_P_2 */
11512 { "vpcmpestri", { XM
, EXx
, Ib
} },
11515 /* VEX_W_0F3A62_P_2 */
11516 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11519 /* VEX_W_0F3A63_P_2 */
11520 { "vpcmpistri", { XM
, EXx
, Ib
} },
11523 /* VEX_W_0F3ADF_P_2 */
11524 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11526 #define NEED_VEX_W_TABLE
11527 #include "i386-dis-evex.h"
11528 #undef NEED_VEX_W_TABLE
11531 static const struct dis386 mod_table
[][2] = {
11534 { "leaS", { Gv
, M
} },
11539 { RM_TABLE (RM_C6_REG_7
) },
11544 { RM_TABLE (RM_C7_REG_7
) },
11548 { "Jcall{T|}", { indirEp
} },
11552 { "Jjmp{T|}", { indirEp
} },
11555 /* MOD_0F01_REG_0 */
11556 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11557 { RM_TABLE (RM_0F01_REG_0
) },
11560 /* MOD_0F01_REG_1 */
11561 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11562 { RM_TABLE (RM_0F01_REG_1
) },
11565 /* MOD_0F01_REG_2 */
11566 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11567 { RM_TABLE (RM_0F01_REG_2
) },
11570 /* MOD_0F01_REG_3 */
11571 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11572 { RM_TABLE (RM_0F01_REG_3
) },
11575 /* MOD_0F01_REG_7 */
11576 { "invlpg", { Mb
} },
11577 { RM_TABLE (RM_0F01_REG_7
) },
11580 /* MOD_0F12_PREFIX_0 */
11581 { "movlps", { XM
, EXq
} },
11582 { "movhlps", { XM
, EXq
} },
11586 { "movlpX", { EXq
, XM
} },
11589 /* MOD_0F16_PREFIX_0 */
11590 { "movhps", { XM
, EXq
} },
11591 { "movlhps", { XM
, EXq
} },
11595 { "movhpX", { EXq
, XM
} },
11598 /* MOD_0F18_REG_0 */
11599 { "prefetchnta", { Mb
} },
11602 /* MOD_0F18_REG_1 */
11603 { "prefetcht0", { Mb
} },
11606 /* MOD_0F18_REG_2 */
11607 { "prefetcht1", { Mb
} },
11610 /* MOD_0F18_REG_3 */
11611 { "prefetcht2", { Mb
} },
11614 /* MOD_0F18_REG_4 */
11615 { "nop/reserved", { Mb
} },
11618 /* MOD_0F18_REG_5 */
11619 { "nop/reserved", { Mb
} },
11622 /* MOD_0F18_REG_6 */
11623 { "nop/reserved", { Mb
} },
11626 /* MOD_0F18_REG_7 */
11627 { "nop/reserved", { Mb
} },
11630 /* MOD_0F1A_PREFIX_0 */
11631 { "bndldx", { Gbnd
, Ev_bnd
} },
11632 { "nopQ", { Ev
} },
11635 /* MOD_0F1B_PREFIX_0 */
11636 { "bndstx", { Ev_bnd
, Gbnd
} },
11637 { "nopQ", { Ev
} },
11640 /* MOD_0F1B_PREFIX_1 */
11641 { "bndmk", { Gbnd
, Ev_bnd
} },
11642 { "nopQ", { Ev
} },
11647 { "movZ", { Rm
, Cm
} },
11652 { "movZ", { Rm
, Dm
} },
11657 { "movZ", { Cm
, Rm
} },
11662 { "movZ", { Dm
, Rm
} },
11667 { "movL", { Rd
, Td
} },
11672 { "movL", { Td
, Rd
} },
11675 /* MOD_0F2B_PREFIX_0 */
11676 {"movntps", { Mx
, XM
} },
11679 /* MOD_0F2B_PREFIX_1 */
11680 {"movntss", { Md
, XM
} },
11683 /* MOD_0F2B_PREFIX_2 */
11684 {"movntpd", { Mx
, XM
} },
11687 /* MOD_0F2B_PREFIX_3 */
11688 {"movntsd", { Mq
, XM
} },
11693 { "movmskpX", { Gdq
, XS
} },
11696 /* MOD_0F71_REG_2 */
11698 { "psrlw", { MS
, Ib
} },
11701 /* MOD_0F71_REG_4 */
11703 { "psraw", { MS
, Ib
} },
11706 /* MOD_0F71_REG_6 */
11708 { "psllw", { MS
, Ib
} },
11711 /* MOD_0F72_REG_2 */
11713 { "psrld", { MS
, Ib
} },
11716 /* MOD_0F72_REG_4 */
11718 { "psrad", { MS
, Ib
} },
11721 /* MOD_0F72_REG_6 */
11723 { "pslld", { MS
, Ib
} },
11726 /* MOD_0F73_REG_2 */
11728 { "psrlq", { MS
, Ib
} },
11731 /* MOD_0F73_REG_3 */
11733 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11736 /* MOD_0F73_REG_6 */
11738 { "psllq", { MS
, Ib
} },
11741 /* MOD_0F73_REG_7 */
11743 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11746 /* MOD_0FAE_REG_0 */
11747 { "fxsave", { FXSAVE
} },
11748 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11751 /* MOD_0FAE_REG_1 */
11752 { "fxrstor", { FXSAVE
} },
11753 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11756 /* MOD_0FAE_REG_2 */
11757 { "ldmxcsr", { Md
} },
11758 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11761 /* MOD_0FAE_REG_3 */
11762 { "stmxcsr", { Md
} },
11763 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11766 /* MOD_0FAE_REG_4 */
11767 { "xsave", { FXSAVE
} },
11770 /* MOD_0FAE_REG_5 */
11771 { "xrstor", { FXSAVE
} },
11772 { RM_TABLE (RM_0FAE_REG_5
) },
11775 /* MOD_0FAE_REG_6 */
11776 { "xsaveopt", { FXSAVE
} },
11777 { RM_TABLE (RM_0FAE_REG_6
) },
11780 /* MOD_0FAE_REG_7 */
11781 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11782 { RM_TABLE (RM_0FAE_REG_7
) },
11786 { "lssS", { Gv
, Mp
} },
11790 { "lfsS", { Gv
, Mp
} },
11794 { "lgsS", { Gv
, Mp
} },
11797 /* MOD_0FC7_REG_3 */
11798 { "xrstors", { FXSAVE
} },
11801 /* MOD_0FC7_REG_4 */
11802 { "xsavec", { FXSAVE
} },
11805 /* MOD_0FC7_REG_5 */
11806 { "xsaves", { FXSAVE
} },
11809 /* MOD_0FC7_REG_6 */
11810 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11811 { "rdrand", { Ev
} },
11814 /* MOD_0FC7_REG_7 */
11815 { "vmptrst", { Mq
} },
11816 { "rdseed", { Ev
} },
11821 { "pmovmskb", { Gdq
, MS
} },
11824 /* MOD_0FE7_PREFIX_2 */
11825 { "movntdq", { Mx
, XM
} },
11828 /* MOD_0FF0_PREFIX_3 */
11829 { "lddqu", { XM
, M
} },
11832 /* MOD_0F382A_PREFIX_2 */
11833 { "movntdqa", { XM
, Mx
} },
11837 { "bound{S|}", { Gv
, Ma
} },
11838 { EVEX_TABLE (EVEX_0F
) },
11842 { "lesS", { Gv
, Mp
} },
11843 { VEX_C4_TABLE (VEX_0F
) },
11847 { "ldsS", { Gv
, Mp
} },
11848 { VEX_C5_TABLE (VEX_0F
) },
11851 /* MOD_VEX_0F12_PREFIX_0 */
11852 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11853 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11857 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11860 /* MOD_VEX_0F16_PREFIX_0 */
11861 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11862 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11866 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11870 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11875 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11878 /* MOD_VEX_0F71_REG_2 */
11880 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11883 /* MOD_VEX_0F71_REG_4 */
11885 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11888 /* MOD_VEX_0F71_REG_6 */
11890 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11893 /* MOD_VEX_0F72_REG_2 */
11895 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11898 /* MOD_VEX_0F72_REG_4 */
11900 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11903 /* MOD_VEX_0F72_REG_6 */
11905 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11908 /* MOD_VEX_0F73_REG_2 */
11910 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11913 /* MOD_VEX_0F73_REG_3 */
11915 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11918 /* MOD_VEX_0F73_REG_6 */
11920 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11923 /* MOD_VEX_0F73_REG_7 */
11925 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11928 /* MOD_VEX_0FAE_REG_2 */
11929 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11932 /* MOD_VEX_0FAE_REG_3 */
11933 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11936 /* MOD_VEX_0FD7_PREFIX_2 */
11938 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11941 /* MOD_VEX_0FE7_PREFIX_2 */
11942 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11945 /* MOD_VEX_0FF0_PREFIX_3 */
11946 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11949 /* MOD_VEX_0F381A_PREFIX_2 */
11950 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11953 /* MOD_VEX_0F382A_PREFIX_2 */
11954 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11957 /* MOD_VEX_0F382C_PREFIX_2 */
11958 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11961 /* MOD_VEX_0F382D_PREFIX_2 */
11962 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11965 /* MOD_VEX_0F382E_PREFIX_2 */
11966 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11969 /* MOD_VEX_0F382F_PREFIX_2 */
11970 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11973 /* MOD_VEX_0F385A_PREFIX_2 */
11974 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11977 /* MOD_VEX_0F388C_PREFIX_2 */
11978 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11981 /* MOD_VEX_0F388E_PREFIX_2 */
11982 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11984 #define NEED_MOD_TABLE
11985 #include "i386-dis-evex.h"
11986 #undef NEED_MOD_TABLE
11989 static const struct dis386 rm_table
[][8] = {
11992 { "xabort", { Skip_MODRM
, Ib
} },
11996 { "xbeginT", { Skip_MODRM
, Jv
} },
11999 /* RM_0F01_REG_0 */
12001 { "vmcall", { Skip_MODRM
} },
12002 { "vmlaunch", { Skip_MODRM
} },
12003 { "vmresume", { Skip_MODRM
} },
12004 { "vmxoff", { Skip_MODRM
} },
12007 /* RM_0F01_REG_1 */
12008 { "monitor", { { OP_Monitor
, 0 } } },
12009 { "mwait", { { OP_Mwait
, 0 } } },
12010 { "clac", { Skip_MODRM
} },
12011 { "stac", { Skip_MODRM
} },
12015 { "encls", { Skip_MODRM
} },
12018 /* RM_0F01_REG_2 */
12019 { "xgetbv", { Skip_MODRM
} },
12020 { "xsetbv", { Skip_MODRM
} },
12023 { "vmfunc", { Skip_MODRM
} },
12024 { "xend", { Skip_MODRM
} },
12025 { "xtest", { Skip_MODRM
} },
12026 { "enclu", { Skip_MODRM
} },
12029 /* RM_0F01_REG_3 */
12030 { "vmrun", { Skip_MODRM
} },
12031 { "vmmcall", { Skip_MODRM
} },
12032 { "vmload", { Skip_MODRM
} },
12033 { "vmsave", { Skip_MODRM
} },
12034 { "stgi", { Skip_MODRM
} },
12035 { "clgi", { Skip_MODRM
} },
12036 { "skinit", { Skip_MODRM
} },
12037 { "invlpga", { Skip_MODRM
} },
12040 /* RM_0F01_REG_7 */
12041 { "swapgs", { Skip_MODRM
} },
12042 { "rdtscp", { Skip_MODRM
} },
12045 /* RM_0FAE_REG_5 */
12046 { "lfence", { Skip_MODRM
} },
12049 /* RM_0FAE_REG_6 */
12050 { "mfence", { Skip_MODRM
} },
12053 /* RM_0FAE_REG_7 */
12054 { "sfence", { Skip_MODRM
} },
12058 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12060 /* We use the high bit to indicate different name for the same
12062 #define REP_PREFIX (0xf3 | 0x100)
12063 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12064 #define XRELEASE_PREFIX (0xf3 | 0x400)
12065 #define BND_PREFIX (0xf2 | 0x400)
12070 int newrex
, i
, length
;
12076 last_lock_prefix
= -1;
12077 last_repz_prefix
= -1;
12078 last_repnz_prefix
= -1;
12079 last_data_prefix
= -1;
12080 last_addr_prefix
= -1;
12081 last_rex_prefix
= -1;
12082 last_seg_prefix
= -1;
12084 active_seg_prefix
= 0;
12085 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12086 all_prefixes
[i
] = 0;
12089 /* The maximum instruction length is 15bytes. */
12090 while (length
< MAX_CODE_LENGTH
- 1)
12092 FETCH_DATA (the_info
, codep
+ 1);
12096 /* REX prefixes family. */
12113 if (address_mode
== mode_64bit
)
12117 last_rex_prefix
= i
;
12120 prefixes
|= PREFIX_REPZ
;
12121 last_repz_prefix
= i
;
12124 prefixes
|= PREFIX_REPNZ
;
12125 last_repnz_prefix
= i
;
12128 prefixes
|= PREFIX_LOCK
;
12129 last_lock_prefix
= i
;
12132 prefixes
|= PREFIX_CS
;
12133 last_seg_prefix
= i
;
12134 active_seg_prefix
= PREFIX_CS
;
12137 prefixes
|= PREFIX_SS
;
12138 last_seg_prefix
= i
;
12139 active_seg_prefix
= PREFIX_SS
;
12142 prefixes
|= PREFIX_DS
;
12143 last_seg_prefix
= i
;
12144 active_seg_prefix
= PREFIX_DS
;
12147 prefixes
|= PREFIX_ES
;
12148 last_seg_prefix
= i
;
12149 active_seg_prefix
= PREFIX_ES
;
12152 prefixes
|= PREFIX_FS
;
12153 last_seg_prefix
= i
;
12154 active_seg_prefix
= PREFIX_FS
;
12157 prefixes
|= PREFIX_GS
;
12158 last_seg_prefix
= i
;
12159 active_seg_prefix
= PREFIX_GS
;
12162 prefixes
|= PREFIX_DATA
;
12163 last_data_prefix
= i
;
12166 prefixes
|= PREFIX_ADDR
;
12167 last_addr_prefix
= i
;
12170 /* fwait is really an instruction. If there are prefixes
12171 before the fwait, they belong to the fwait, *not* to the
12172 following instruction. */
12174 if (prefixes
|| rex
)
12176 prefixes
|= PREFIX_FWAIT
;
12178 /* This ensures that the previous REX prefixes are noticed
12179 as unused prefixes, as in the return case below. */
12183 prefixes
= PREFIX_FWAIT
;
12188 /* Rex is ignored when followed by another prefix. */
12194 if (*codep
!= FWAIT_OPCODE
)
12195 all_prefixes
[i
++] = *codep
;
12203 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12206 static const char *
12207 prefix_name (int pref
, int sizeflag
)
12209 static const char *rexes
[16] =
12212 "rex.B", /* 0x41 */
12213 "rex.X", /* 0x42 */
12214 "rex.XB", /* 0x43 */
12215 "rex.R", /* 0x44 */
12216 "rex.RB", /* 0x45 */
12217 "rex.RX", /* 0x46 */
12218 "rex.RXB", /* 0x47 */
12219 "rex.W", /* 0x48 */
12220 "rex.WB", /* 0x49 */
12221 "rex.WX", /* 0x4a */
12222 "rex.WXB", /* 0x4b */
12223 "rex.WR", /* 0x4c */
12224 "rex.WRB", /* 0x4d */
12225 "rex.WRX", /* 0x4e */
12226 "rex.WRXB", /* 0x4f */
12231 /* REX prefixes family. */
12248 return rexes
[pref
- 0x40];
12268 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12270 if (address_mode
== mode_64bit
)
12271 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12273 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12278 case XACQUIRE_PREFIX
:
12280 case XRELEASE_PREFIX
:
12289 static char op_out
[MAX_OPERANDS
][100];
12290 static int op_ad
, op_index
[MAX_OPERANDS
];
12291 static int two_source_ops
;
12292 static bfd_vma op_address
[MAX_OPERANDS
];
12293 static bfd_vma op_riprel
[MAX_OPERANDS
];
12294 static bfd_vma start_pc
;
12297 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12298 * (see topic "Redundant prefixes" in the "Differences from 8086"
12299 * section of the "Virtual 8086 Mode" chapter.)
12300 * 'pc' should be the address of this instruction, it will
12301 * be used to print the target address if this is a relative jump or call
12302 * The function returns the length of this instruction in bytes.
12305 static char intel_syntax
;
12306 static char intel_mnemonic
= !SYSV386_COMPAT
;
12307 static char open_char
;
12308 static char close_char
;
12309 static char separator_char
;
12310 static char scale_char
;
12312 /* Here for backwards compatibility. When gdb stops using
12313 print_insn_i386_att and print_insn_i386_intel these functions can
12314 disappear, and print_insn_i386 be merged into print_insn. */
12316 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12320 return print_insn (pc
, info
);
12324 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12328 return print_insn (pc
, info
);
12332 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12336 return print_insn (pc
, info
);
12340 print_i386_disassembler_options (FILE *stream
)
12342 fprintf (stream
, _("\n\
12343 The following i386/x86-64 specific disassembler options are supported for use\n\
12344 with the -M switch (multiple options should be separated by commas):\n"));
12346 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12347 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12348 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12349 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12350 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12351 fprintf (stream
, _(" att-mnemonic\n"
12352 " Display instruction in AT&T mnemonic\n"));
12353 fprintf (stream
, _(" intel-mnemonic\n"
12354 " Display instruction in Intel mnemonic\n"));
12355 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12356 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12357 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12358 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12359 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12360 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12364 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
12366 /* Get a pointer to struct dis386 with a valid name. */
12368 static const struct dis386
*
12369 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12371 int vindex
, vex_table_index
;
12373 if (dp
->name
!= NULL
)
12376 switch (dp
->op
[0].bytemode
)
12378 case USE_REG_TABLE
:
12379 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12382 case USE_MOD_TABLE
:
12383 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12384 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12388 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12391 case USE_PREFIX_TABLE
:
12394 /* The prefix in VEX is implicit. */
12395 switch (vex
.prefix
)
12400 case REPE_PREFIX_OPCODE
:
12403 case DATA_PREFIX_OPCODE
:
12406 case REPNE_PREFIX_OPCODE
:
12416 int last_prefix
= -1;
12419 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12420 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12422 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12424 if (last_repz_prefix
> last_repnz_prefix
)
12427 prefix
= PREFIX_REPZ
;
12428 last_prefix
= last_repz_prefix
;
12433 prefix
= PREFIX_REPNZ
;
12434 last_prefix
= last_repnz_prefix
;
12437 /* Ignore the invalid index if it isn't mandatory. */
12438 if (!mandatory_prefix
12439 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].name
12441 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].op
[0].bytemode
12446 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12449 prefix
= PREFIX_DATA
;
12450 last_prefix
= last_data_prefix
;
12455 used_prefixes
|= prefix
;
12456 all_prefixes
[last_prefix
] = 0;
12459 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12462 case USE_X86_64_TABLE
:
12463 vindex
= address_mode
== mode_64bit
? 1 : 0;
12464 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12467 case USE_3BYTE_TABLE
:
12468 FETCH_DATA (info
, codep
+ 2);
12470 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12472 modrm
.mod
= (*codep
>> 6) & 3;
12473 modrm
.reg
= (*codep
>> 3) & 7;
12474 modrm
.rm
= *codep
& 7;
12477 case USE_VEX_LEN_TABLE
:
12481 switch (vex
.length
)
12494 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12497 case USE_XOP_8F_TABLE
:
12498 FETCH_DATA (info
, codep
+ 3);
12499 /* All bits in the REX prefix are ignored. */
12501 rex
= ~(*codep
>> 5) & 0x7;
12503 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12504 switch ((*codep
& 0x1f))
12510 vex_table_index
= XOP_08
;
12513 vex_table_index
= XOP_09
;
12516 vex_table_index
= XOP_0A
;
12520 vex
.w
= *codep
& 0x80;
12521 if (vex
.w
&& address_mode
== mode_64bit
)
12524 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12525 if (address_mode
!= mode_64bit
12526 && vex
.register_specifier
> 0x7)
12532 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12533 switch ((*codep
& 0x3))
12539 vex
.prefix
= DATA_PREFIX_OPCODE
;
12542 vex
.prefix
= REPE_PREFIX_OPCODE
;
12545 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12552 dp
= &xop_table
[vex_table_index
][vindex
];
12555 FETCH_DATA (info
, codep
+ 1);
12556 modrm
.mod
= (*codep
>> 6) & 3;
12557 modrm
.reg
= (*codep
>> 3) & 7;
12558 modrm
.rm
= *codep
& 7;
12561 case USE_VEX_C4_TABLE
:
12563 FETCH_DATA (info
, codep
+ 3);
12564 /* All bits in the REX prefix are ignored. */
12566 rex
= ~(*codep
>> 5) & 0x7;
12567 switch ((*codep
& 0x1f))
12573 vex_table_index
= VEX_0F
;
12576 vex_table_index
= VEX_0F38
;
12579 vex_table_index
= VEX_0F3A
;
12583 vex
.w
= *codep
& 0x80;
12584 if (vex
.w
&& address_mode
== mode_64bit
)
12587 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12588 if (address_mode
!= mode_64bit
12589 && vex
.register_specifier
> 0x7)
12595 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12596 switch ((*codep
& 0x3))
12602 vex
.prefix
= DATA_PREFIX_OPCODE
;
12605 vex
.prefix
= REPE_PREFIX_OPCODE
;
12608 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12615 dp
= &vex_table
[vex_table_index
][vindex
];
12617 /* There is no MODRM byte for VEX [82|77]. */
12618 if (vindex
!= 0x77 && vindex
!= 0x82)
12620 FETCH_DATA (info
, codep
+ 1);
12621 modrm
.mod
= (*codep
>> 6) & 3;
12622 modrm
.reg
= (*codep
>> 3) & 7;
12623 modrm
.rm
= *codep
& 7;
12627 case USE_VEX_C5_TABLE
:
12629 FETCH_DATA (info
, codep
+ 2);
12630 /* All bits in the REX prefix are ignored. */
12632 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12634 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12635 if (address_mode
!= mode_64bit
12636 && vex
.register_specifier
> 0x7)
12644 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12645 switch ((*codep
& 0x3))
12651 vex
.prefix
= DATA_PREFIX_OPCODE
;
12654 vex
.prefix
= REPE_PREFIX_OPCODE
;
12657 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12664 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12666 /* There is no MODRM byte for VEX [82|77]. */
12667 if (vindex
!= 0x77 && vindex
!= 0x82)
12669 FETCH_DATA (info
, codep
+ 1);
12670 modrm
.mod
= (*codep
>> 6) & 3;
12671 modrm
.reg
= (*codep
>> 3) & 7;
12672 modrm
.rm
= *codep
& 7;
12676 case USE_VEX_W_TABLE
:
12680 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12683 case USE_EVEX_TABLE
:
12684 two_source_ops
= 0;
12687 FETCH_DATA (info
, codep
+ 4);
12688 /* All bits in the REX prefix are ignored. */
12690 /* The first byte after 0x62. */
12691 rex
= ~(*codep
>> 5) & 0x7;
12692 vex
.r
= *codep
& 0x10;
12693 switch ((*codep
& 0xf))
12696 return &bad_opcode
;
12698 vex_table_index
= EVEX_0F
;
12701 vex_table_index
= EVEX_0F38
;
12704 vex_table_index
= EVEX_0F3A
;
12708 /* The second byte after 0x62. */
12710 vex
.w
= *codep
& 0x80;
12711 if (vex
.w
&& address_mode
== mode_64bit
)
12714 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12715 if (address_mode
!= mode_64bit
)
12717 /* In 16/32-bit mode silently ignore following bits. */
12721 vex
.register_specifier
&= 0x7;
12725 if (!(*codep
& 0x4))
12726 return &bad_opcode
;
12728 switch ((*codep
& 0x3))
12734 vex
.prefix
= DATA_PREFIX_OPCODE
;
12737 vex
.prefix
= REPE_PREFIX_OPCODE
;
12740 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12744 /* The third byte after 0x62. */
12747 /* Remember the static rounding bits. */
12748 vex
.ll
= (*codep
>> 5) & 3;
12749 vex
.b
= (*codep
& 0x10) != 0;
12751 vex
.v
= *codep
& 0x8;
12752 vex
.mask_register_specifier
= *codep
& 0x7;
12753 vex
.zeroing
= *codep
& 0x80;
12759 dp
= &evex_table
[vex_table_index
][vindex
];
12761 FETCH_DATA (info
, codep
+ 1);
12762 modrm
.mod
= (*codep
>> 6) & 3;
12763 modrm
.reg
= (*codep
>> 3) & 7;
12764 modrm
.rm
= *codep
& 7;
12766 /* Set vector length. */
12767 if (modrm
.mod
== 3 && vex
.b
)
12783 return &bad_opcode
;
12796 if (dp
->name
!= NULL
)
12799 return get_valid_dis386 (dp
, info
);
12803 get_sib (disassemble_info
*info
, int sizeflag
)
12805 /* If modrm.mod == 3, operand must be register. */
12807 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12811 FETCH_DATA (info
, codep
+ 2);
12812 sib
.index
= (codep
[1] >> 3) & 7;
12813 sib
.scale
= (codep
[1] >> 6) & 3;
12814 sib
.base
= codep
[1] & 7;
12819 print_insn (bfd_vma pc
, disassemble_info
*info
)
12821 const struct dis386
*dp
;
12823 char *op_txt
[MAX_OPERANDS
];
12825 int sizeflag
, orig_sizeflag
;
12827 struct dis_private priv
;
12830 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12831 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12832 address_mode
= mode_32bit
;
12833 else if (info
->mach
== bfd_mach_i386_i8086
)
12835 address_mode
= mode_16bit
;
12836 priv
.orig_sizeflag
= 0;
12839 address_mode
= mode_64bit
;
12841 if (intel_syntax
== (char) -1)
12842 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12844 for (p
= info
->disassembler_options
; p
!= NULL
; )
12846 if (CONST_STRNEQ (p
, "x86-64"))
12848 address_mode
= mode_64bit
;
12849 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12851 else if (CONST_STRNEQ (p
, "i386"))
12853 address_mode
= mode_32bit
;
12854 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12856 else if (CONST_STRNEQ (p
, "i8086"))
12858 address_mode
= mode_16bit
;
12859 priv
.orig_sizeflag
= 0;
12861 else if (CONST_STRNEQ (p
, "intel"))
12864 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12865 intel_mnemonic
= 1;
12867 else if (CONST_STRNEQ (p
, "att"))
12870 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12871 intel_mnemonic
= 0;
12873 else if (CONST_STRNEQ (p
, "addr"))
12875 if (address_mode
== mode_64bit
)
12877 if (p
[4] == '3' && p
[5] == '2')
12878 priv
.orig_sizeflag
&= ~AFLAG
;
12879 else if (p
[4] == '6' && p
[5] == '4')
12880 priv
.orig_sizeflag
|= AFLAG
;
12884 if (p
[4] == '1' && p
[5] == '6')
12885 priv
.orig_sizeflag
&= ~AFLAG
;
12886 else if (p
[4] == '3' && p
[5] == '2')
12887 priv
.orig_sizeflag
|= AFLAG
;
12890 else if (CONST_STRNEQ (p
, "data"))
12892 if (p
[4] == '1' && p
[5] == '6')
12893 priv
.orig_sizeflag
&= ~DFLAG
;
12894 else if (p
[4] == '3' && p
[5] == '2')
12895 priv
.orig_sizeflag
|= DFLAG
;
12897 else if (CONST_STRNEQ (p
, "suffix"))
12898 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12900 p
= strchr (p
, ',');
12907 names64
= intel_names64
;
12908 names32
= intel_names32
;
12909 names16
= intel_names16
;
12910 names8
= intel_names8
;
12911 names8rex
= intel_names8rex
;
12912 names_seg
= intel_names_seg
;
12913 names_mm
= intel_names_mm
;
12914 names_bnd
= intel_names_bnd
;
12915 names_xmm
= intel_names_xmm
;
12916 names_ymm
= intel_names_ymm
;
12917 names_zmm
= intel_names_zmm
;
12918 index64
= intel_index64
;
12919 index32
= intel_index32
;
12920 names_mask
= intel_names_mask
;
12921 index16
= intel_index16
;
12924 separator_char
= '+';
12929 names64
= att_names64
;
12930 names32
= att_names32
;
12931 names16
= att_names16
;
12932 names8
= att_names8
;
12933 names8rex
= att_names8rex
;
12934 names_seg
= att_names_seg
;
12935 names_mm
= att_names_mm
;
12936 names_bnd
= att_names_bnd
;
12937 names_xmm
= att_names_xmm
;
12938 names_ymm
= att_names_ymm
;
12939 names_zmm
= att_names_zmm
;
12940 index64
= att_index64
;
12941 index32
= att_index32
;
12942 names_mask
= att_names_mask
;
12943 index16
= att_index16
;
12946 separator_char
= ',';
12950 /* The output looks better if we put 7 bytes on a line, since that
12951 puts most long word instructions on a single line. Use 8 bytes
12953 if ((info
->mach
& bfd_mach_l1om
) != 0)
12954 info
->bytes_per_line
= 8;
12956 info
->bytes_per_line
= 7;
12958 info
->private_data
= &priv
;
12959 priv
.max_fetched
= priv
.the_buffer
;
12960 priv
.insn_start
= pc
;
12963 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12971 start_codep
= priv
.the_buffer
;
12972 codep
= priv
.the_buffer
;
12974 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12978 /* Getting here means we tried for data but didn't get it. That
12979 means we have an incomplete instruction of some sort. Just
12980 print the first byte as a prefix or a .byte pseudo-op. */
12981 if (codep
> priv
.the_buffer
)
12983 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12985 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12988 /* Just print the first byte as a .byte instruction. */
12989 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12990 (unsigned int) priv
.the_buffer
[0]);
13000 sizeflag
= priv
.orig_sizeflag
;
13002 if (!ckprefix () || rex_used
)
13004 /* Too many prefixes or unused REX prefixes. */
13006 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13008 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13010 prefix_name (all_prefixes
[i
], sizeflag
));
13014 insn_codep
= codep
;
13016 FETCH_DATA (info
, codep
+ 1);
13017 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13019 if (((prefixes
& PREFIX_FWAIT
)
13020 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13022 /* Handle prefixes before fwait. */
13023 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13025 (*info
->fprintf_func
) (info
->stream
, "%s ",
13026 prefix_name (all_prefixes
[i
], sizeflag
));
13027 (*info
->fprintf_func
) (info
->stream
, "fwait");
13031 if (*codep
== 0x0f)
13033 unsigned char threebyte
;
13034 FETCH_DATA (info
, codep
+ 2);
13035 threebyte
= *++codep
;
13036 dp
= &dis386_twobyte
[threebyte
];
13037 need_modrm
= twobyte_has_modrm
[*codep
];
13038 mandatory_prefix
= twobyte_has_mandatory_prefix
[*codep
];
13043 dp
= &dis386
[*codep
];
13044 need_modrm
= onebyte_has_modrm
[*codep
];
13045 mandatory_prefix
= 0;
13049 /* Save sizeflag for printing the extra prefixes later before updating
13050 it for mnemonic and operand processing. The prefix names depend
13051 only on the address mode. */
13052 orig_sizeflag
= sizeflag
;
13053 if (prefixes
& PREFIX_ADDR
)
13055 if ((prefixes
& PREFIX_DATA
))
13061 FETCH_DATA (info
, codep
+ 1);
13062 modrm
.mod
= (*codep
>> 6) & 3;
13063 modrm
.reg
= (*codep
>> 3) & 7;
13064 modrm
.rm
= *codep
& 7;
13072 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13074 get_sib (info
, sizeflag
);
13075 dofloat (sizeflag
);
13079 dp
= get_valid_dis386 (dp
, info
);
13080 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13082 get_sib (info
, sizeflag
);
13083 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13086 op_ad
= MAX_OPERANDS
- 1 - i
;
13088 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13089 /* For EVEX instruction after the last operand masking
13090 should be printed. */
13091 if (i
== 0 && vex
.evex
)
13093 /* Don't print {%k0}. */
13094 if (vex
.mask_register_specifier
)
13097 oappend (names_mask
[vex
.mask_register_specifier
]);
13107 /* Check if the REX prefix is used. */
13108 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13109 all_prefixes
[last_rex_prefix
] = 0;
13111 /* Check if the SEG prefix is used. */
13112 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13113 | PREFIX_FS
| PREFIX_GS
)) != 0
13114 && (used_prefixes
& active_seg_prefix
) != 0)
13115 all_prefixes
[last_seg_prefix
] = 0;
13117 /* Check if the ADDR prefix is used. */
13118 if ((prefixes
& PREFIX_ADDR
) != 0
13119 && (used_prefixes
& PREFIX_ADDR
) != 0)
13120 all_prefixes
[last_addr_prefix
] = 0;
13122 /* Check if the DATA prefix is used. */
13123 if ((prefixes
& PREFIX_DATA
) != 0
13124 && (used_prefixes
& PREFIX_DATA
) != 0)
13125 all_prefixes
[last_data_prefix
] = 0;
13127 /* Print the extra prefixes. */
13129 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13130 if (all_prefixes
[i
])
13133 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13136 prefix_length
+= strlen (name
) + 1;
13137 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13140 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13141 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13142 used by putop and MMX/SSE operand and may be overriden by the
13143 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13145 if (mandatory_prefix
13146 && dp
!= &bad_opcode
13148 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13150 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13152 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13154 && (used_prefixes
& PREFIX_DATA
) == 0))))
13156 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13157 return end_codep
- priv
.the_buffer
;
13160 /* Check maximum code length. */
13161 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13163 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13164 return MAX_CODE_LENGTH
;
13167 obufp
= mnemonicendp
;
13168 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13171 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13173 /* The enter and bound instructions are printed with operands in the same
13174 order as the intel book; everything else is printed in reverse order. */
13175 if (intel_syntax
|| two_source_ops
)
13179 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13180 op_txt
[i
] = op_out
[i
];
13182 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13184 op_ad
= op_index
[i
];
13185 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13186 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13187 riprel
= op_riprel
[i
];
13188 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13189 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13194 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13195 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13199 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13203 (*info
->fprintf_func
) (info
->stream
, ",");
13204 if (op_index
[i
] != -1 && !op_riprel
[i
])
13205 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13207 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13211 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13212 if (op_index
[i
] != -1 && op_riprel
[i
])
13214 (*info
->fprintf_func
) (info
->stream
, " # ");
13215 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
13216 + op_address
[op_index
[i
]]), info
);
13219 return codep
- priv
.the_buffer
;
13222 static const char *float_mem
[] = {
13297 static const unsigned char float_mem_mode
[] = {
13372 #define ST { OP_ST, 0 }
13373 #define STi { OP_STi, 0 }
13375 #define FGRPd9_2 NULL, { { NULL, 0 } }
13376 #define FGRPd9_4 NULL, { { NULL, 1 } }
13377 #define FGRPd9_5 NULL, { { NULL, 2 } }
13378 #define FGRPd9_6 NULL, { { NULL, 3 } }
13379 #define FGRPd9_7 NULL, { { NULL, 4 } }
13380 #define FGRPda_5 NULL, { { NULL, 5 } }
13381 #define FGRPdb_4 NULL, { { NULL, 6 } }
13382 #define FGRPde_3 NULL, { { NULL, 7 } }
13383 #define FGRPdf_4 NULL, { { NULL, 8 } }
13385 static const struct dis386 float_reg
[][8] = {
13388 { "fadd", { ST
, STi
} },
13389 { "fmul", { ST
, STi
} },
13390 { "fcom", { STi
} },
13391 { "fcomp", { STi
} },
13392 { "fsub", { ST
, STi
} },
13393 { "fsubr", { ST
, STi
} },
13394 { "fdiv", { ST
, STi
} },
13395 { "fdivr", { ST
, STi
} },
13399 { "fld", { STi
} },
13400 { "fxch", { STi
} },
13410 { "fcmovb", { ST
, STi
} },
13411 { "fcmove", { ST
, STi
} },
13412 { "fcmovbe",{ ST
, STi
} },
13413 { "fcmovu", { ST
, STi
} },
13421 { "fcmovnb",{ ST
, STi
} },
13422 { "fcmovne",{ ST
, STi
} },
13423 { "fcmovnbe",{ ST
, STi
} },
13424 { "fcmovnu",{ ST
, STi
} },
13426 { "fucomi", { ST
, STi
} },
13427 { "fcomi", { ST
, STi
} },
13432 { "fadd", { STi
, ST
} },
13433 { "fmul", { STi
, ST
} },
13436 { "fsub!M", { STi
, ST
} },
13437 { "fsubM", { STi
, ST
} },
13438 { "fdiv!M", { STi
, ST
} },
13439 { "fdivM", { STi
, ST
} },
13443 { "ffree", { STi
} },
13445 { "fst", { STi
} },
13446 { "fstp", { STi
} },
13447 { "fucom", { STi
} },
13448 { "fucomp", { STi
} },
13454 { "faddp", { STi
, ST
} },
13455 { "fmulp", { STi
, ST
} },
13458 { "fsub!Mp", { STi
, ST
} },
13459 { "fsubMp", { STi
, ST
} },
13460 { "fdiv!Mp", { STi
, ST
} },
13461 { "fdivMp", { STi
, ST
} },
13465 { "ffreep", { STi
} },
13470 { "fucomip", { ST
, STi
} },
13471 { "fcomip", { ST
, STi
} },
13476 static char *fgrps
[][8] = {
13479 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13484 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13489 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13494 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13499 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13504 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13509 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13510 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13515 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13520 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13525 swap_operand (void)
13527 mnemonicendp
[0] = '.';
13528 mnemonicendp
[1] = 's';
13533 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13534 int sizeflag ATTRIBUTE_UNUSED
)
13536 /* Skip mod/rm byte. */
13542 dofloat (int sizeflag
)
13544 const struct dis386
*dp
;
13545 unsigned char floatop
;
13547 floatop
= codep
[-1];
13549 if (modrm
.mod
!= 3)
13551 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13553 putop (float_mem
[fp_indx
], sizeflag
);
13556 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13559 /* Skip mod/rm byte. */
13563 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13564 if (dp
->name
== NULL
)
13566 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13568 /* Instruction fnstsw is only one with strange arg. */
13569 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13570 strcpy (op_out
[0], names16
[0]);
13574 putop (dp
->name
, sizeflag
);
13579 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13584 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13588 /* Like oappend (below), but S is a string starting with '%'.
13589 In Intel syntax, the '%' is elided. */
13591 oappend_maybe_intel (const char *s
)
13593 oappend (s
+ intel_syntax
);
13597 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13599 oappend_maybe_intel ("%st");
13603 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13605 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13606 oappend_maybe_intel (scratchbuf
);
13609 /* Capital letters in template are macros. */
13611 putop (const char *in_template
, int sizeflag
)
13616 unsigned int l
= 0, len
= 1;
13619 #define SAVE_LAST(c) \
13620 if (l < len && l < sizeof (last)) \
13625 for (p
= in_template
; *p
; p
++)
13642 while (*++p
!= '|')
13643 if (*p
== '}' || *p
== '\0')
13646 /* Fall through. */
13651 while (*++p
!= '}')
13662 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13666 if (l
== 0 && len
== 1)
13671 if (sizeflag
& SUFFIX_ALWAYS
)
13684 if (address_mode
== mode_64bit
13685 && !(prefixes
& PREFIX_ADDR
))
13696 if (intel_syntax
&& !alt
)
13698 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13700 if (sizeflag
& DFLAG
)
13701 *obufp
++ = intel_syntax
? 'd' : 'l';
13703 *obufp
++ = intel_syntax
? 'w' : 's';
13704 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13708 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13711 if (modrm
.mod
== 3)
13717 if (sizeflag
& DFLAG
)
13718 *obufp
++ = intel_syntax
? 'd' : 'l';
13721 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13727 case 'E': /* For jcxz/jecxz */
13728 if (address_mode
== mode_64bit
)
13730 if (sizeflag
& AFLAG
)
13736 if (sizeflag
& AFLAG
)
13738 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13743 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13745 if (sizeflag
& AFLAG
)
13746 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13748 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13749 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13753 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13755 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13759 if (!(rex
& REX_W
))
13760 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13765 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13766 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13768 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13771 if (prefixes
& PREFIX_DS
)
13792 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13797 /* Fall through. */
13800 if (l
!= 0 || len
!= 1)
13808 if (sizeflag
& SUFFIX_ALWAYS
)
13812 if (intel_mnemonic
!= cond
)
13816 if ((prefixes
& PREFIX_FWAIT
) == 0)
13819 used_prefixes
|= PREFIX_FWAIT
;
13825 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13829 if (!(rex
& REX_W
))
13830 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13834 && address_mode
== mode_64bit
13835 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13840 /* Fall through. */
13843 if (l
== 0 && len
== 1)
13848 if ((rex
& REX_W
) == 0
13849 && (prefixes
& PREFIX_DATA
))
13851 if ((sizeflag
& DFLAG
) == 0)
13853 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13857 if ((prefixes
& PREFIX_DATA
)
13859 || (sizeflag
& SUFFIX_ALWAYS
))
13866 if (sizeflag
& DFLAG
)
13870 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13876 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13882 if ((prefixes
& PREFIX_DATA
)
13884 || (sizeflag
& SUFFIX_ALWAYS
))
13891 if (sizeflag
& DFLAG
)
13892 *obufp
++ = intel_syntax
? 'd' : 'l';
13895 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13903 if (address_mode
== mode_64bit
13904 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13906 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13910 /* Fall through. */
13913 if (l
== 0 && len
== 1)
13916 if (intel_syntax
&& !alt
)
13919 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13925 if (sizeflag
& DFLAG
)
13926 *obufp
++ = intel_syntax
? 'd' : 'l';
13929 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13935 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13941 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13956 else if (sizeflag
& DFLAG
)
13965 if (intel_syntax
&& !p
[1]
13966 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13968 if (!(rex
& REX_W
))
13969 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13972 if (l
== 0 && len
== 1)
13976 if (address_mode
== mode_64bit
13977 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13979 if (sizeflag
& SUFFIX_ALWAYS
)
14001 /* Fall through. */
14004 if (l
== 0 && len
== 1)
14009 if (sizeflag
& SUFFIX_ALWAYS
)
14015 if (sizeflag
& DFLAG
)
14019 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14033 if (address_mode
== mode_64bit
14034 && !(prefixes
& PREFIX_ADDR
))
14045 if (l
!= 0 || len
!= 1)
14050 if (need_vex
&& vex
.prefix
)
14052 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14059 if (prefixes
& PREFIX_DATA
)
14063 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14067 if (l
== 0 && len
== 1)
14069 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14080 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14088 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14090 switch (vex
.length
)
14104 if (l
== 0 && len
== 1)
14106 /* operand size flag for cwtl, cbtw */
14115 else if (sizeflag
& DFLAG
)
14119 if (!(rex
& REX_W
))
14120 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14127 && last
[0] != 'L'))
14134 if (last
[0] == 'X')
14135 *obufp
++ = vex
.w
? 'd': 's';
14137 *obufp
++ = vex
.w
? 'q': 'd';
14144 mnemonicendp
= obufp
;
14149 oappend (const char *s
)
14151 obufp
= stpcpy (obufp
, s
);
14157 /* Only print the active segment register. */
14158 if (!active_seg_prefix
)
14161 used_prefixes
|= active_seg_prefix
;
14162 switch (active_seg_prefix
)
14165 oappend_maybe_intel ("%cs:");
14168 oappend_maybe_intel ("%ds:");
14171 oappend_maybe_intel ("%ss:");
14174 oappend_maybe_intel ("%es:");
14177 oappend_maybe_intel ("%fs:");
14180 oappend_maybe_intel ("%gs:");
14188 OP_indirE (int bytemode
, int sizeflag
)
14192 OP_E (bytemode
, sizeflag
);
14196 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14198 if (address_mode
== mode_64bit
)
14206 sprintf_vma (tmp
, disp
);
14207 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14208 strcpy (buf
+ 2, tmp
+ i
);
14212 bfd_signed_vma v
= disp
;
14219 /* Check for possible overflow on 0x8000000000000000. */
14222 strcpy (buf
, "9223372036854775808");
14236 tmp
[28 - i
] = (v
% 10) + '0';
14240 strcpy (buf
, tmp
+ 29 - i
);
14246 sprintf (buf
, "0x%x", (unsigned int) disp
);
14248 sprintf (buf
, "%d", (int) disp
);
14252 /* Put DISP in BUF as signed hex number. */
14255 print_displacement (char *buf
, bfd_vma disp
)
14257 bfd_signed_vma val
= disp
;
14266 /* Check for possible overflow. */
14269 switch (address_mode
)
14272 strcpy (buf
+ j
, "0x8000000000000000");
14275 strcpy (buf
+ j
, "0x80000000");
14278 strcpy (buf
+ j
, "0x8000");
14288 sprintf_vma (tmp
, (bfd_vma
) val
);
14289 for (i
= 0; tmp
[i
] == '0'; i
++)
14291 if (tmp
[i
] == '\0')
14293 strcpy (buf
+ j
, tmp
+ i
);
14297 intel_operand_size (int bytemode
, int sizeflag
)
14301 && (bytemode
== x_mode
14302 || bytemode
== evex_half_bcst_xmmq_mode
))
14305 oappend ("QWORD PTR ");
14307 oappend ("DWORD PTR ");
14316 oappend ("BYTE PTR ");
14321 case dqw_swap_mode
:
14322 oappend ("WORD PTR ");
14325 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14327 oappend ("QWORD PTR ");
14336 oappend ("QWORD PTR ");
14339 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14340 oappend ("DWORD PTR ");
14342 oappend ("WORD PTR ");
14343 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14347 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14349 oappend ("WORD PTR ");
14350 if (!(rex
& REX_W
))
14351 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14354 if (sizeflag
& DFLAG
)
14355 oappend ("QWORD PTR ");
14357 oappend ("DWORD PTR ");
14358 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14361 case d_scalar_mode
:
14362 case d_scalar_swap_mode
:
14365 oappend ("DWORD PTR ");
14368 case q_scalar_mode
:
14369 case q_scalar_swap_mode
:
14371 oappend ("QWORD PTR ");
14374 if (address_mode
== mode_64bit
)
14375 oappend ("QWORD PTR ");
14377 oappend ("DWORD PTR ");
14380 if (sizeflag
& DFLAG
)
14381 oappend ("FWORD PTR ");
14383 oappend ("DWORD PTR ");
14384 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14387 oappend ("TBYTE PTR ");
14391 case evex_x_gscat_mode
:
14392 case evex_x_nobcst_mode
:
14395 switch (vex
.length
)
14398 oappend ("XMMWORD PTR ");
14401 oappend ("YMMWORD PTR ");
14404 oappend ("ZMMWORD PTR ");
14411 oappend ("XMMWORD PTR ");
14414 oappend ("XMMWORD PTR ");
14417 oappend ("YMMWORD PTR ");
14420 case evex_half_bcst_xmmq_mode
:
14424 switch (vex
.length
)
14427 oappend ("QWORD PTR ");
14430 oappend ("XMMWORD PTR ");
14433 oappend ("YMMWORD PTR ");
14443 switch (vex
.length
)
14448 oappend ("BYTE PTR ");
14458 switch (vex
.length
)
14463 oappend ("WORD PTR ");
14473 switch (vex
.length
)
14478 oappend ("DWORD PTR ");
14488 switch (vex
.length
)
14493 oappend ("QWORD PTR ");
14503 switch (vex
.length
)
14506 oappend ("WORD PTR ");
14509 oappend ("DWORD PTR ");
14512 oappend ("QWORD PTR ");
14522 switch (vex
.length
)
14525 oappend ("DWORD PTR ");
14528 oappend ("QWORD PTR ");
14531 oappend ("XMMWORD PTR ");
14541 switch (vex
.length
)
14544 oappend ("QWORD PTR ");
14547 oappend ("YMMWORD PTR ");
14550 oappend ("ZMMWORD PTR ");
14560 switch (vex
.length
)
14564 oappend ("XMMWORD PTR ");
14571 oappend ("OWORD PTR ");
14574 case vex_w_dq_mode
:
14575 case vex_scalar_w_dq_mode
:
14580 oappend ("QWORD PTR ");
14582 oappend ("DWORD PTR ");
14584 case vex_vsib_d_w_dq_mode
:
14585 case vex_vsib_q_w_dq_mode
:
14592 oappend ("QWORD PTR ");
14594 oappend ("DWORD PTR ");
14598 switch (vex
.length
)
14601 oappend ("XMMWORD PTR ");
14604 oappend ("YMMWORD PTR ");
14607 oappend ("ZMMWORD PTR ");
14614 case vex_vsib_q_w_d_mode
:
14615 case vex_vsib_d_w_d_mode
:
14616 if (!need_vex
|| !vex
.evex
)
14619 switch (vex
.length
)
14622 oappend ("QWORD PTR ");
14625 oappend ("XMMWORD PTR ");
14628 oappend ("YMMWORD PTR ");
14636 if (!need_vex
|| vex
.length
!= 128)
14639 oappend ("DWORD PTR ");
14641 oappend ("BYTE PTR ");
14647 oappend ("QWORD PTR ");
14649 oappend ("WORD PTR ");
14658 OP_E_register (int bytemode
, int sizeflag
)
14660 int reg
= modrm
.rm
;
14661 const char **names
;
14667 if ((sizeflag
& SUFFIX_ALWAYS
)
14668 && (bytemode
== b_swap_mode
14669 || bytemode
== v_swap_mode
14670 || bytemode
== dqw_swap_mode
))
14696 names
= address_mode
== mode_64bit
? names64
: names32
;
14702 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14715 case dqw_swap_mode
:
14721 if ((sizeflag
& DFLAG
)
14722 || (bytemode
!= v_mode
14723 && bytemode
!= v_swap_mode
))
14727 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14732 names
= names_mask
;
14737 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14740 oappend (names
[reg
]);
14744 OP_E_memory (int bytemode
, int sizeflag
)
14747 int add
= (rex
& REX_B
) ? 8 : 0;
14753 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14755 && bytemode
!= x_mode
14756 && bytemode
!= xmmq_mode
14757 && bytemode
!= evex_half_bcst_xmmq_mode
)
14766 case dqw_swap_mode
:
14773 case vex_vsib_d_w_dq_mode
:
14774 case vex_vsib_d_w_d_mode
:
14775 case vex_vsib_q_w_dq_mode
:
14776 case vex_vsib_q_w_d_mode
:
14777 case evex_x_gscat_mode
:
14779 shift
= vex
.w
? 3 : 2;
14782 case evex_half_bcst_xmmq_mode
:
14786 shift
= vex
.w
? 3 : 2;
14789 /* Fall through if vex.b == 0. */
14793 case evex_x_nobcst_mode
:
14795 switch (vex
.length
)
14818 case q_scalar_mode
:
14820 case q_scalar_swap_mode
:
14826 case d_scalar_mode
:
14828 case d_scalar_swap_mode
:
14840 /* Make necessary corrections to shift for modes that need it.
14841 For these modes we currently have shift 4, 5 or 6 depending on
14842 vex.length (it corresponds to xmmword, ymmword or zmmword
14843 operand). We might want to make it 3, 4 or 5 (e.g. for
14844 xmmq_mode). In case of broadcast enabled the corrections
14845 aren't needed, as element size is always 32 or 64 bits. */
14847 && (bytemode
== xmmq_mode
14848 || bytemode
== evex_half_bcst_xmmq_mode
))
14850 else if (bytemode
== xmmqd_mode
)
14852 else if (bytemode
== xmmdw_mode
)
14854 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14862 intel_operand_size (bytemode
, sizeflag
);
14865 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14867 /* 32/64 bit address mode */
14876 int addr32flag
= !((sizeflag
& AFLAG
)
14877 || bytemode
== v_bnd_mode
14878 || bytemode
== bnd_mode
);
14879 const char **indexes64
= names64
;
14880 const char **indexes32
= names32
;
14890 vindex
= sib
.index
;
14896 case vex_vsib_d_w_dq_mode
:
14897 case vex_vsib_d_w_d_mode
:
14898 case vex_vsib_q_w_dq_mode
:
14899 case vex_vsib_q_w_d_mode
:
14909 switch (vex
.length
)
14912 indexes64
= indexes32
= names_xmm
;
14916 || bytemode
== vex_vsib_q_w_dq_mode
14917 || bytemode
== vex_vsib_q_w_d_mode
)
14918 indexes64
= indexes32
= names_ymm
;
14920 indexes64
= indexes32
= names_xmm
;
14924 || bytemode
== vex_vsib_q_w_dq_mode
14925 || bytemode
== vex_vsib_q_w_d_mode
)
14926 indexes64
= indexes32
= names_zmm
;
14928 indexes64
= indexes32
= names_ymm
;
14935 haveindex
= vindex
!= 4;
14942 rbase
= base
+ add
;
14950 if (address_mode
== mode_64bit
&& !havesib
)
14956 FETCH_DATA (the_info
, codep
+ 1);
14958 if ((disp
& 0x80) != 0)
14960 if (vex
.evex
&& shift
> 0)
14968 /* In 32bit mode, we need index register to tell [offset] from
14969 [eiz*1 + offset]. */
14970 needindex
= (havesib
14973 && address_mode
== mode_32bit
);
14974 havedisp
= (havebase
14976 || (havesib
&& (haveindex
|| scale
!= 0)));
14979 if (modrm
.mod
!= 0 || base
== 5)
14981 if (havedisp
|| riprel
)
14982 print_displacement (scratchbuf
, disp
);
14984 print_operand_value (scratchbuf
, 1, disp
);
14985 oappend (scratchbuf
);
14989 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14993 if ((havebase
|| haveindex
|| riprel
)
14994 && (bytemode
!= v_bnd_mode
)
14995 && (bytemode
!= bnd_mode
))
14996 used_prefixes
|= PREFIX_ADDR
;
14998 if (havedisp
|| (intel_syntax
&& riprel
))
15000 *obufp
++ = open_char
;
15001 if (intel_syntax
&& riprel
)
15004 oappend (sizeflag
& AFLAG
? "rip" : "eip");
15008 oappend (address_mode
== mode_64bit
&& !addr32flag
15009 ? names64
[rbase
] : names32
[rbase
]);
15012 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15013 print index to tell base + index from base. */
15017 || (havebase
&& base
!= ESP_REG_NUM
))
15019 if (!intel_syntax
|| havebase
)
15021 *obufp
++ = separator_char
;
15025 oappend (address_mode
== mode_64bit
&& !addr32flag
15026 ? indexes64
[vindex
] : indexes32
[vindex
]);
15028 oappend (address_mode
== mode_64bit
&& !addr32flag
15029 ? index64
: index32
);
15031 *obufp
++ = scale_char
;
15033 sprintf (scratchbuf
, "%d", 1 << scale
);
15034 oappend (scratchbuf
);
15038 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15040 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15045 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15049 disp
= - (bfd_signed_vma
) disp
;
15053 print_displacement (scratchbuf
, disp
);
15055 print_operand_value (scratchbuf
, 1, disp
);
15056 oappend (scratchbuf
);
15059 *obufp
++ = close_char
;
15062 else if (intel_syntax
)
15064 if (modrm
.mod
!= 0 || base
== 5)
15066 if (!active_seg_prefix
)
15068 oappend (names_seg
[ds_reg
- es_reg
]);
15071 print_operand_value (scratchbuf
, 1, disp
);
15072 oappend (scratchbuf
);
15078 /* 16 bit address mode */
15079 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15086 if ((disp
& 0x8000) != 0)
15091 FETCH_DATA (the_info
, codep
+ 1);
15093 if ((disp
& 0x80) != 0)
15098 if ((disp
& 0x8000) != 0)
15104 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15106 print_displacement (scratchbuf
, disp
);
15107 oappend (scratchbuf
);
15110 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15112 *obufp
++ = open_char
;
15114 oappend (index16
[modrm
.rm
]);
15116 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15118 if ((bfd_signed_vma
) disp
>= 0)
15123 else if (modrm
.mod
!= 1)
15127 disp
= - (bfd_signed_vma
) disp
;
15130 print_displacement (scratchbuf
, disp
);
15131 oappend (scratchbuf
);
15134 *obufp
++ = close_char
;
15137 else if (intel_syntax
)
15139 if (!active_seg_prefix
)
15141 oappend (names_seg
[ds_reg
- es_reg
]);
15144 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15145 oappend (scratchbuf
);
15148 if (vex
.evex
&& vex
.b
15149 && (bytemode
== x_mode
15150 || bytemode
== xmmq_mode
15151 || bytemode
== evex_half_bcst_xmmq_mode
))
15154 || bytemode
== xmmq_mode
15155 || bytemode
== evex_half_bcst_xmmq_mode
)
15157 switch (vex
.length
)
15160 oappend ("{1to2}");
15163 oappend ("{1to4}");
15166 oappend ("{1to8}");
15174 switch (vex
.length
)
15177 oappend ("{1to4}");
15180 oappend ("{1to8}");
15183 oappend ("{1to16}");
15193 OP_E (int bytemode
, int sizeflag
)
15195 /* Skip mod/rm byte. */
15199 if (modrm
.mod
== 3)
15200 OP_E_register (bytemode
, sizeflag
);
15202 OP_E_memory (bytemode
, sizeflag
);
15206 OP_G (int bytemode
, int sizeflag
)
15217 oappend (names8rex
[modrm
.reg
+ add
]);
15219 oappend (names8
[modrm
.reg
+ add
]);
15222 oappend (names16
[modrm
.reg
+ add
]);
15227 oappend (names32
[modrm
.reg
+ add
]);
15230 oappend (names64
[modrm
.reg
+ add
]);
15233 oappend (names_bnd
[modrm
.reg
]);
15240 case dqw_swap_mode
:
15243 oappend (names64
[modrm
.reg
+ add
]);
15246 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15247 oappend (names32
[modrm
.reg
+ add
]);
15249 oappend (names16
[modrm
.reg
+ add
]);
15250 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15254 if (address_mode
== mode_64bit
)
15255 oappend (names64
[modrm
.reg
+ add
]);
15257 oappend (names32
[modrm
.reg
+ add
]);
15261 oappend (names_mask
[modrm
.reg
+ add
]);
15264 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15277 FETCH_DATA (the_info
, codep
+ 8);
15278 a
= *codep
++ & 0xff;
15279 a
|= (*codep
++ & 0xff) << 8;
15280 a
|= (*codep
++ & 0xff) << 16;
15281 a
|= (*codep
++ & 0xff) << 24;
15282 b
= *codep
++ & 0xff;
15283 b
|= (*codep
++ & 0xff) << 8;
15284 b
|= (*codep
++ & 0xff) << 16;
15285 b
|= (*codep
++ & 0xff) << 24;
15286 x
= a
+ ((bfd_vma
) b
<< 32);
15294 static bfd_signed_vma
15297 bfd_signed_vma x
= 0;
15299 FETCH_DATA (the_info
, codep
+ 4);
15300 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15301 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15302 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15303 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15307 static bfd_signed_vma
15310 bfd_signed_vma x
= 0;
15312 FETCH_DATA (the_info
, codep
+ 4);
15313 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15314 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15315 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15316 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15318 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15328 FETCH_DATA (the_info
, codep
+ 2);
15329 x
= *codep
++ & 0xff;
15330 x
|= (*codep
++ & 0xff) << 8;
15335 set_op (bfd_vma op
, int riprel
)
15337 op_index
[op_ad
] = op_ad
;
15338 if (address_mode
== mode_64bit
)
15340 op_address
[op_ad
] = op
;
15341 op_riprel
[op_ad
] = riprel
;
15345 /* Mask to get a 32-bit address. */
15346 op_address
[op_ad
] = op
& 0xffffffff;
15347 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15352 OP_REG (int code
, int sizeflag
)
15359 case es_reg
: case ss_reg
: case cs_reg
:
15360 case ds_reg
: case fs_reg
: case gs_reg
:
15361 oappend (names_seg
[code
- es_reg
]);
15373 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15374 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15375 s
= names16
[code
- ax_reg
+ add
];
15377 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15378 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15381 s
= names8rex
[code
- al_reg
+ add
];
15383 s
= names8
[code
- al_reg
];
15385 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15386 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15387 if (address_mode
== mode_64bit
15388 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15390 s
= names64
[code
- rAX_reg
+ add
];
15393 code
+= eAX_reg
- rAX_reg
;
15394 /* Fall through. */
15395 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15396 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15399 s
= names64
[code
- eAX_reg
+ add
];
15402 if (sizeflag
& DFLAG
)
15403 s
= names32
[code
- eAX_reg
+ add
];
15405 s
= names16
[code
- eAX_reg
+ add
];
15406 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15410 s
= INTERNAL_DISASSEMBLER_ERROR
;
15417 OP_IMREG (int code
, int sizeflag
)
15429 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15430 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15431 s
= names16
[code
- ax_reg
];
15433 case es_reg
: case ss_reg
: case cs_reg
:
15434 case ds_reg
: case fs_reg
: case gs_reg
:
15435 s
= names_seg
[code
- es_reg
];
15437 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15438 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15441 s
= names8rex
[code
- al_reg
];
15443 s
= names8
[code
- al_reg
];
15445 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15446 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15449 s
= names64
[code
- eAX_reg
];
15452 if (sizeflag
& DFLAG
)
15453 s
= names32
[code
- eAX_reg
];
15455 s
= names16
[code
- eAX_reg
];
15456 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15459 case z_mode_ax_reg
:
15460 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15464 if (!(rex
& REX_W
))
15465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15468 s
= INTERNAL_DISASSEMBLER_ERROR
;
15475 OP_I (int bytemode
, int sizeflag
)
15478 bfd_signed_vma mask
= -1;
15483 FETCH_DATA (the_info
, codep
+ 1);
15488 if (address_mode
== mode_64bit
)
15493 /* Fall through. */
15500 if (sizeflag
& DFLAG
)
15510 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15522 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15527 scratchbuf
[0] = '$';
15528 print_operand_value (scratchbuf
+ 1, 1, op
);
15529 oappend_maybe_intel (scratchbuf
);
15530 scratchbuf
[0] = '\0';
15534 OP_I64 (int bytemode
, int sizeflag
)
15537 bfd_signed_vma mask
= -1;
15539 if (address_mode
!= mode_64bit
)
15541 OP_I (bytemode
, sizeflag
);
15548 FETCH_DATA (the_info
, codep
+ 1);
15558 if (sizeflag
& DFLAG
)
15568 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15576 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15581 scratchbuf
[0] = '$';
15582 print_operand_value (scratchbuf
+ 1, 1, op
);
15583 oappend_maybe_intel (scratchbuf
);
15584 scratchbuf
[0] = '\0';
15588 OP_sI (int bytemode
, int sizeflag
)
15596 FETCH_DATA (the_info
, codep
+ 1);
15598 if ((op
& 0x80) != 0)
15600 if (bytemode
== b_T_mode
)
15602 if (address_mode
!= mode_64bit
15603 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15605 /* The operand-size prefix is overridden by a REX prefix. */
15606 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15614 if (!(rex
& REX_W
))
15616 if (sizeflag
& DFLAG
)
15624 /* The operand-size prefix is overridden by a REX prefix. */
15625 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15631 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15635 scratchbuf
[0] = '$';
15636 print_operand_value (scratchbuf
+ 1, 1, op
);
15637 oappend_maybe_intel (scratchbuf
);
15641 OP_J (int bytemode
, int sizeflag
)
15645 bfd_vma segment
= 0;
15650 FETCH_DATA (the_info
, codep
+ 1);
15652 if ((disp
& 0x80) != 0)
15657 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15662 if ((disp
& 0x8000) != 0)
15664 /* In 16bit mode, address is wrapped around at 64k within
15665 the same segment. Otherwise, a data16 prefix on a jump
15666 instruction means that the pc is masked to 16 bits after
15667 the displacement is added! */
15669 if ((prefixes
& PREFIX_DATA
) == 0)
15670 segment
= ((start_pc
+ codep
- start_codep
)
15671 & ~((bfd_vma
) 0xffff));
15673 if (!(rex
& REX_W
))
15674 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15677 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15680 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15682 print_operand_value (scratchbuf
, 1, disp
);
15683 oappend (scratchbuf
);
15687 OP_SEG (int bytemode
, int sizeflag
)
15689 if (bytemode
== w_mode
)
15690 oappend (names_seg
[modrm
.reg
]);
15692 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15696 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15700 if (sizeflag
& DFLAG
)
15710 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15712 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15714 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15715 oappend (scratchbuf
);
15719 OP_OFF (int bytemode
, int sizeflag
)
15723 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15724 intel_operand_size (bytemode
, sizeflag
);
15727 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15734 if (!active_seg_prefix
)
15736 oappend (names_seg
[ds_reg
- es_reg
]);
15740 print_operand_value (scratchbuf
, 1, off
);
15741 oappend (scratchbuf
);
15745 OP_OFF64 (int bytemode
, int sizeflag
)
15749 if (address_mode
!= mode_64bit
15750 || (prefixes
& PREFIX_ADDR
))
15752 OP_OFF (bytemode
, sizeflag
);
15756 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15757 intel_operand_size (bytemode
, sizeflag
);
15764 if (!active_seg_prefix
)
15766 oappend (names_seg
[ds_reg
- es_reg
]);
15770 print_operand_value (scratchbuf
, 1, off
);
15771 oappend (scratchbuf
);
15775 ptr_reg (int code
, int sizeflag
)
15779 *obufp
++ = open_char
;
15780 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15781 if (address_mode
== mode_64bit
)
15783 if (!(sizeflag
& AFLAG
))
15784 s
= names32
[code
- eAX_reg
];
15786 s
= names64
[code
- eAX_reg
];
15788 else if (sizeflag
& AFLAG
)
15789 s
= names32
[code
- eAX_reg
];
15791 s
= names16
[code
- eAX_reg
];
15793 *obufp
++ = close_char
;
15798 OP_ESreg (int code
, int sizeflag
)
15804 case 0x6d: /* insw/insl */
15805 intel_operand_size (z_mode
, sizeflag
);
15807 case 0xa5: /* movsw/movsl/movsq */
15808 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15809 case 0xab: /* stosw/stosl */
15810 case 0xaf: /* scasw/scasl */
15811 intel_operand_size (v_mode
, sizeflag
);
15814 intel_operand_size (b_mode
, sizeflag
);
15817 oappend_maybe_intel ("%es:");
15818 ptr_reg (code
, sizeflag
);
15822 OP_DSreg (int code
, int sizeflag
)
15828 case 0x6f: /* outsw/outsl */
15829 intel_operand_size (z_mode
, sizeflag
);
15831 case 0xa5: /* movsw/movsl/movsq */
15832 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15833 case 0xad: /* lodsw/lodsl/lodsq */
15834 intel_operand_size (v_mode
, sizeflag
);
15837 intel_operand_size (b_mode
, sizeflag
);
15840 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15841 default segment register DS is printed. */
15842 if (!active_seg_prefix
)
15843 active_seg_prefix
= PREFIX_DS
;
15845 ptr_reg (code
, sizeflag
);
15849 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15857 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15859 all_prefixes
[last_lock_prefix
] = 0;
15860 used_prefixes
|= PREFIX_LOCK
;
15865 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15866 oappend_maybe_intel (scratchbuf
);
15870 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15879 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15881 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15882 oappend (scratchbuf
);
15886 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15888 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15889 oappend_maybe_intel (scratchbuf
);
15893 OP_R (int bytemode
, int sizeflag
)
15895 if (modrm
.mod
== 3)
15896 OP_E (bytemode
, sizeflag
);
15902 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15904 int reg
= modrm
.reg
;
15905 const char **names
;
15907 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15908 if (prefixes
& PREFIX_DATA
)
15917 oappend (names
[reg
]);
15921 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15923 int reg
= modrm
.reg
;
15924 const char **names
;
15936 && bytemode
!= xmm_mode
15937 && bytemode
!= xmmq_mode
15938 && bytemode
!= evex_half_bcst_xmmq_mode
15939 && bytemode
!= ymm_mode
15940 && bytemode
!= scalar_mode
)
15942 switch (vex
.length
)
15949 || (bytemode
!= vex_vsib_q_w_dq_mode
15950 && bytemode
!= vex_vsib_q_w_d_mode
))
15962 else if (bytemode
== xmmq_mode
15963 || bytemode
== evex_half_bcst_xmmq_mode
)
15965 switch (vex
.length
)
15978 else if (bytemode
== ymm_mode
)
15982 oappend (names
[reg
]);
15986 OP_EM (int bytemode
, int sizeflag
)
15989 const char **names
;
15991 if (modrm
.mod
!= 3)
15994 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15996 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15997 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15999 OP_E (bytemode
, sizeflag
);
16003 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16006 /* Skip mod/rm byte. */
16009 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16011 if (prefixes
& PREFIX_DATA
)
16020 oappend (names
[reg
]);
16023 /* cvt* are the only instructions in sse2 which have
16024 both SSE and MMX operands and also have 0x66 prefix
16025 in their opcode. 0x66 was originally used to differentiate
16026 between SSE and MMX instruction(operands). So we have to handle the
16027 cvt* separately using OP_EMC and OP_MXC */
16029 OP_EMC (int bytemode
, int sizeflag
)
16031 if (modrm
.mod
!= 3)
16033 if (intel_syntax
&& bytemode
== v_mode
)
16035 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16036 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16038 OP_E (bytemode
, sizeflag
);
16042 /* Skip mod/rm byte. */
16045 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16046 oappend (names_mm
[modrm
.rm
]);
16050 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16052 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16053 oappend (names_mm
[modrm
.reg
]);
16057 OP_EX (int bytemode
, int sizeflag
)
16060 const char **names
;
16062 /* Skip mod/rm byte. */
16066 if (modrm
.mod
!= 3)
16068 OP_E_memory (bytemode
, sizeflag
);
16083 if ((sizeflag
& SUFFIX_ALWAYS
)
16084 && (bytemode
== x_swap_mode
16085 || bytemode
== d_swap_mode
16086 || bytemode
== dqw_swap_mode
16087 || bytemode
== d_scalar_swap_mode
16088 || bytemode
== q_swap_mode
16089 || bytemode
== q_scalar_swap_mode
))
16093 && bytemode
!= xmm_mode
16094 && bytemode
!= xmmdw_mode
16095 && bytemode
!= xmmqd_mode
16096 && bytemode
!= xmm_mb_mode
16097 && bytemode
!= xmm_mw_mode
16098 && bytemode
!= xmm_md_mode
16099 && bytemode
!= xmm_mq_mode
16100 && bytemode
!= xmm_mdq_mode
16101 && bytemode
!= xmmq_mode
16102 && bytemode
!= evex_half_bcst_xmmq_mode
16103 && bytemode
!= ymm_mode
16104 && bytemode
!= d_scalar_mode
16105 && bytemode
!= d_scalar_swap_mode
16106 && bytemode
!= q_scalar_mode
16107 && bytemode
!= q_scalar_swap_mode
16108 && bytemode
!= vex_scalar_w_dq_mode
)
16110 switch (vex
.length
)
16125 else if (bytemode
== xmmq_mode
16126 || bytemode
== evex_half_bcst_xmmq_mode
)
16128 switch (vex
.length
)
16141 else if (bytemode
== ymm_mode
)
16145 oappend (names
[reg
]);
16149 OP_MS (int bytemode
, int sizeflag
)
16151 if (modrm
.mod
== 3)
16152 OP_EM (bytemode
, sizeflag
);
16158 OP_XS (int bytemode
, int sizeflag
)
16160 if (modrm
.mod
== 3)
16161 OP_EX (bytemode
, sizeflag
);
16167 OP_M (int bytemode
, int sizeflag
)
16169 if (modrm
.mod
== 3)
16170 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16173 OP_E (bytemode
, sizeflag
);
16177 OP_0f07 (int bytemode
, int sizeflag
)
16179 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16182 OP_E (bytemode
, sizeflag
);
16185 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16186 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16189 NOP_Fixup1 (int bytemode
, int sizeflag
)
16191 if ((prefixes
& PREFIX_DATA
) != 0
16194 && address_mode
== mode_64bit
))
16195 OP_REG (bytemode
, sizeflag
);
16197 strcpy (obuf
, "nop");
16201 NOP_Fixup2 (int bytemode
, int sizeflag
)
16203 if ((prefixes
& PREFIX_DATA
) != 0
16206 && address_mode
== mode_64bit
))
16207 OP_IMREG (bytemode
, sizeflag
);
16210 static const char *const Suffix3DNow
[] = {
16211 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16212 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16213 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16214 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16215 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16216 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16217 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16218 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16219 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16220 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16221 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16222 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16223 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16224 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16225 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16226 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16227 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16228 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16229 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16230 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16231 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16232 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16233 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16234 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16235 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16236 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16237 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16238 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16239 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16240 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16241 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16242 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16243 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16244 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16245 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16246 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16247 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16248 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16249 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16250 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16251 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16252 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16253 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16254 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16255 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16256 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16257 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16258 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16259 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16260 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16261 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16262 /* CC */ NULL
, NULL
, NULL
, NULL
,
16263 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16264 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16265 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16266 /* DC */ NULL
, NULL
, NULL
, NULL
,
16267 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16268 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16269 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16270 /* EC */ NULL
, NULL
, NULL
, NULL
,
16271 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16272 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16273 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16274 /* FC */ NULL
, NULL
, NULL
, NULL
,
16278 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16280 const char *mnemonic
;
16282 FETCH_DATA (the_info
, codep
+ 1);
16283 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16284 place where an 8-bit immediate would normally go. ie. the last
16285 byte of the instruction. */
16286 obufp
= mnemonicendp
;
16287 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16289 oappend (mnemonic
);
16292 /* Since a variable sized modrm/sib chunk is between the start
16293 of the opcode (0x0f0f) and the opcode suffix, we need to do
16294 all the modrm processing first, and don't know until now that
16295 we have a bad opcode. This necessitates some cleaning up. */
16296 op_out
[0][0] = '\0';
16297 op_out
[1][0] = '\0';
16300 mnemonicendp
= obufp
;
16303 static struct op simd_cmp_op
[] =
16305 { STRING_COMMA_LEN ("eq") },
16306 { STRING_COMMA_LEN ("lt") },
16307 { STRING_COMMA_LEN ("le") },
16308 { STRING_COMMA_LEN ("unord") },
16309 { STRING_COMMA_LEN ("neq") },
16310 { STRING_COMMA_LEN ("nlt") },
16311 { STRING_COMMA_LEN ("nle") },
16312 { STRING_COMMA_LEN ("ord") }
16316 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16318 unsigned int cmp_type
;
16320 FETCH_DATA (the_info
, codep
+ 1);
16321 cmp_type
= *codep
++ & 0xff;
16322 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16325 char *p
= mnemonicendp
- 2;
16329 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16330 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16334 /* We have a reserved extension byte. Output it directly. */
16335 scratchbuf
[0] = '$';
16336 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16337 oappend_maybe_intel (scratchbuf
);
16338 scratchbuf
[0] = '\0';
16343 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16344 int sizeflag ATTRIBUTE_UNUSED
)
16346 /* mwait %eax,%ecx */
16349 const char **names
= (address_mode
== mode_64bit
16350 ? names64
: names32
);
16351 strcpy (op_out
[0], names
[0]);
16352 strcpy (op_out
[1], names
[1]);
16353 two_source_ops
= 1;
16355 /* Skip mod/rm byte. */
16361 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16362 int sizeflag ATTRIBUTE_UNUSED
)
16364 /* monitor %eax,%ecx,%edx" */
16367 const char **op1_names
;
16368 const char **names
= (address_mode
== mode_64bit
16369 ? names64
: names32
);
16371 if (!(prefixes
& PREFIX_ADDR
))
16372 op1_names
= (address_mode
== mode_16bit
16373 ? names16
: names
);
16376 /* Remove "addr16/addr32". */
16377 all_prefixes
[last_addr_prefix
] = 0;
16378 op1_names
= (address_mode
!= mode_32bit
16379 ? names32
: names16
);
16380 used_prefixes
|= PREFIX_ADDR
;
16382 strcpy (op_out
[0], op1_names
[0]);
16383 strcpy (op_out
[1], names
[1]);
16384 strcpy (op_out
[2], names
[2]);
16385 two_source_ops
= 1;
16387 /* Skip mod/rm byte. */
16395 /* Throw away prefixes and 1st. opcode byte. */
16396 codep
= insn_codep
+ 1;
16401 REP_Fixup (int bytemode
, int sizeflag
)
16403 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16405 if (prefixes
& PREFIX_REPZ
)
16406 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16413 OP_IMREG (bytemode
, sizeflag
);
16416 OP_ESreg (bytemode
, sizeflag
);
16419 OP_DSreg (bytemode
, sizeflag
);
16427 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16431 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16433 if (prefixes
& PREFIX_REPNZ
)
16434 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16437 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16438 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16442 HLE_Fixup1 (int bytemode
, int sizeflag
)
16445 && (prefixes
& PREFIX_LOCK
) != 0)
16447 if (prefixes
& PREFIX_REPZ
)
16448 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16449 if (prefixes
& PREFIX_REPNZ
)
16450 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16453 OP_E (bytemode
, sizeflag
);
16456 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16457 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16461 HLE_Fixup2 (int bytemode
, int sizeflag
)
16463 if (modrm
.mod
!= 3)
16465 if (prefixes
& PREFIX_REPZ
)
16466 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16467 if (prefixes
& PREFIX_REPNZ
)
16468 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16471 OP_E (bytemode
, sizeflag
);
16474 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16475 "xrelease" for memory operand. No check for LOCK prefix. */
16478 HLE_Fixup3 (int bytemode
, int sizeflag
)
16481 && last_repz_prefix
> last_repnz_prefix
16482 && (prefixes
& PREFIX_REPZ
) != 0)
16483 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16485 OP_E (bytemode
, sizeflag
);
16489 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16494 /* Change cmpxchg8b to cmpxchg16b. */
16495 char *p
= mnemonicendp
- 2;
16496 mnemonicendp
= stpcpy (p
, "16b");
16499 else if ((prefixes
& PREFIX_LOCK
) != 0)
16501 if (prefixes
& PREFIX_REPZ
)
16502 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16503 if (prefixes
& PREFIX_REPNZ
)
16504 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16507 OP_M (bytemode
, sizeflag
);
16511 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16513 const char **names
;
16517 switch (vex
.length
)
16531 oappend (names
[reg
]);
16535 CRC32_Fixup (int bytemode
, int sizeflag
)
16537 /* Add proper suffix to "crc32". */
16538 char *p
= mnemonicendp
;
16557 if (sizeflag
& DFLAG
)
16561 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16565 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16572 if (modrm
.mod
== 3)
16576 /* Skip mod/rm byte. */
16581 add
= (rex
& REX_B
) ? 8 : 0;
16582 if (bytemode
== b_mode
)
16586 oappend (names8rex
[modrm
.rm
+ add
]);
16588 oappend (names8
[modrm
.rm
+ add
]);
16594 oappend (names64
[modrm
.rm
+ add
]);
16595 else if ((prefixes
& PREFIX_DATA
))
16596 oappend (names16
[modrm
.rm
+ add
]);
16598 oappend (names32
[modrm
.rm
+ add
]);
16602 OP_E (bytemode
, sizeflag
);
16606 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16608 /* Add proper suffix to "fxsave" and "fxrstor". */
16612 char *p
= mnemonicendp
;
16618 OP_M (bytemode
, sizeflag
);
16621 /* Display the destination register operand for instructions with
16625 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16628 const char **names
;
16636 reg
= vex
.register_specifier
;
16643 if (bytemode
== vex_scalar_mode
)
16645 oappend (names_xmm
[reg
]);
16649 switch (vex
.length
)
16656 case vex_vsib_q_w_dq_mode
:
16657 case vex_vsib_q_w_d_mode
:
16668 names
= names_mask
;
16682 case vex_vsib_q_w_dq_mode
:
16683 case vex_vsib_q_w_d_mode
:
16684 names
= vex
.w
? names_ymm
: names_xmm
;
16688 names
= names_mask
;
16702 oappend (names
[reg
]);
16705 /* Get the VEX immediate byte without moving codep. */
16707 static unsigned char
16708 get_vex_imm8 (int sizeflag
, int opnum
)
16710 int bytes_before_imm
= 0;
16712 if (modrm
.mod
!= 3)
16714 /* There are SIB/displacement bytes. */
16715 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16717 /* 32/64 bit address mode */
16718 int base
= modrm
.rm
;
16720 /* Check SIB byte. */
16723 FETCH_DATA (the_info
, codep
+ 1);
16725 /* When decoding the third source, don't increase
16726 bytes_before_imm as this has already been incremented
16727 by one in OP_E_memory while decoding the second
16730 bytes_before_imm
++;
16733 /* Don't increase bytes_before_imm when decoding the third source,
16734 it has already been incremented by OP_E_memory while decoding
16735 the second source operand. */
16741 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16742 SIB == 5, there is a 4 byte displacement. */
16744 /* No displacement. */
16747 /* 4 byte displacement. */
16748 bytes_before_imm
+= 4;
16751 /* 1 byte displacement. */
16752 bytes_before_imm
++;
16759 /* 16 bit address mode */
16760 /* Don't increase bytes_before_imm when decoding the third source,
16761 it has already been incremented by OP_E_memory while decoding
16762 the second source operand. */
16768 /* When modrm.rm == 6, there is a 2 byte displacement. */
16770 /* No displacement. */
16773 /* 2 byte displacement. */
16774 bytes_before_imm
+= 2;
16777 /* 1 byte displacement: when decoding the third source,
16778 don't increase bytes_before_imm as this has already
16779 been incremented by one in OP_E_memory while decoding
16780 the second source operand. */
16782 bytes_before_imm
++;
16790 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16791 return codep
[bytes_before_imm
];
16795 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16797 const char **names
;
16799 if (reg
== -1 && modrm
.mod
!= 3)
16801 OP_E_memory (bytemode
, sizeflag
);
16813 else if (reg
> 7 && address_mode
!= mode_64bit
)
16817 switch (vex
.length
)
16828 oappend (names
[reg
]);
16832 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16835 static unsigned char vex_imm8
;
16837 if (vex_w_done
== 0)
16841 /* Skip mod/rm byte. */
16845 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16848 reg
= vex_imm8
>> 4;
16850 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16852 else if (vex_w_done
== 1)
16857 reg
= vex_imm8
>> 4;
16859 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16863 /* Output the imm8 directly. */
16864 scratchbuf
[0] = '$';
16865 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16866 oappend_maybe_intel (scratchbuf
);
16867 scratchbuf
[0] = '\0';
16873 OP_Vex_2src (int bytemode
, int sizeflag
)
16875 if (modrm
.mod
== 3)
16877 int reg
= modrm
.rm
;
16881 oappend (names_xmm
[reg
]);
16886 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16888 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16889 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16891 OP_E (bytemode
, sizeflag
);
16896 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16898 if (modrm
.mod
== 3)
16900 /* Skip mod/rm byte. */
16906 oappend (names_xmm
[vex
.register_specifier
]);
16908 OP_Vex_2src (bytemode
, sizeflag
);
16912 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16915 OP_Vex_2src (bytemode
, sizeflag
);
16917 oappend (names_xmm
[vex
.register_specifier
]);
16921 OP_EX_VexW (int bytemode
, int sizeflag
)
16929 /* Skip mod/rm byte. */
16934 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16939 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16942 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16946 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16947 int sizeflag ATTRIBUTE_UNUSED
)
16949 /* Skip the immediate byte and check for invalid bits. */
16950 FETCH_DATA (the_info
, codep
+ 1);
16951 if (*codep
++ & 0xf)
16956 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16959 const char **names
;
16961 FETCH_DATA (the_info
, codep
+ 1);
16964 if (bytemode
!= x_mode
)
16971 if (reg
> 7 && address_mode
!= mode_64bit
)
16974 switch (vex
.length
)
16985 oappend (names
[reg
]);
16989 OP_XMM_VexW (int bytemode
, int sizeflag
)
16991 /* Turn off the REX.W bit since it is used for swapping operands
16994 OP_XMM (bytemode
, sizeflag
);
16998 OP_EX_Vex (int bytemode
, int sizeflag
)
17000 if (modrm
.mod
!= 3)
17002 if (vex
.register_specifier
!= 0)
17006 OP_EX (bytemode
, sizeflag
);
17010 OP_XMM_Vex (int bytemode
, int sizeflag
)
17012 if (modrm
.mod
!= 3)
17014 if (vex
.register_specifier
!= 0)
17018 OP_XMM (bytemode
, sizeflag
);
17022 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17024 switch (vex
.length
)
17027 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17030 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17037 static struct op vex_cmp_op
[] =
17039 { STRING_COMMA_LEN ("eq") },
17040 { STRING_COMMA_LEN ("lt") },
17041 { STRING_COMMA_LEN ("le") },
17042 { STRING_COMMA_LEN ("unord") },
17043 { STRING_COMMA_LEN ("neq") },
17044 { STRING_COMMA_LEN ("nlt") },
17045 { STRING_COMMA_LEN ("nle") },
17046 { STRING_COMMA_LEN ("ord") },
17047 { STRING_COMMA_LEN ("eq_uq") },
17048 { STRING_COMMA_LEN ("nge") },
17049 { STRING_COMMA_LEN ("ngt") },
17050 { STRING_COMMA_LEN ("false") },
17051 { STRING_COMMA_LEN ("neq_oq") },
17052 { STRING_COMMA_LEN ("ge") },
17053 { STRING_COMMA_LEN ("gt") },
17054 { STRING_COMMA_LEN ("true") },
17055 { STRING_COMMA_LEN ("eq_os") },
17056 { STRING_COMMA_LEN ("lt_oq") },
17057 { STRING_COMMA_LEN ("le_oq") },
17058 { STRING_COMMA_LEN ("unord_s") },
17059 { STRING_COMMA_LEN ("neq_us") },
17060 { STRING_COMMA_LEN ("nlt_uq") },
17061 { STRING_COMMA_LEN ("nle_uq") },
17062 { STRING_COMMA_LEN ("ord_s") },
17063 { STRING_COMMA_LEN ("eq_us") },
17064 { STRING_COMMA_LEN ("nge_uq") },
17065 { STRING_COMMA_LEN ("ngt_uq") },
17066 { STRING_COMMA_LEN ("false_os") },
17067 { STRING_COMMA_LEN ("neq_os") },
17068 { STRING_COMMA_LEN ("ge_oq") },
17069 { STRING_COMMA_LEN ("gt_oq") },
17070 { STRING_COMMA_LEN ("true_us") },
17074 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17076 unsigned int cmp_type
;
17078 FETCH_DATA (the_info
, codep
+ 1);
17079 cmp_type
= *codep
++ & 0xff;
17080 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17083 char *p
= mnemonicendp
- 2;
17087 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17088 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17092 /* We have a reserved extension byte. Output it directly. */
17093 scratchbuf
[0] = '$';
17094 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17095 oappend_maybe_intel (scratchbuf
);
17096 scratchbuf
[0] = '\0';
17101 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17102 int sizeflag ATTRIBUTE_UNUSED
)
17104 unsigned int cmp_type
;
17109 FETCH_DATA (the_info
, codep
+ 1);
17110 cmp_type
= *codep
++ & 0xff;
17111 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17112 If it's the case, print suffix, otherwise - print the immediate. */
17113 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17118 char *p
= mnemonicendp
- 2;
17120 /* vpcmp* can have both one- and two-lettered suffix. */
17134 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17135 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17139 /* We have a reserved extension byte. Output it directly. */
17140 scratchbuf
[0] = '$';
17141 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17142 oappend_maybe_intel (scratchbuf
);
17143 scratchbuf
[0] = '\0';
17147 static const struct op pclmul_op
[] =
17149 { STRING_COMMA_LEN ("lql") },
17150 { STRING_COMMA_LEN ("hql") },
17151 { STRING_COMMA_LEN ("lqh") },
17152 { STRING_COMMA_LEN ("hqh") }
17156 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17157 int sizeflag ATTRIBUTE_UNUSED
)
17159 unsigned int pclmul_type
;
17161 FETCH_DATA (the_info
, codep
+ 1);
17162 pclmul_type
= *codep
++ & 0xff;
17163 switch (pclmul_type
)
17174 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17177 char *p
= mnemonicendp
- 3;
17182 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17183 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17187 /* We have a reserved extension byte. Output it directly. */
17188 scratchbuf
[0] = '$';
17189 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17190 oappend_maybe_intel (scratchbuf
);
17191 scratchbuf
[0] = '\0';
17196 MOVBE_Fixup (int bytemode
, int sizeflag
)
17198 /* Add proper suffix to "movbe". */
17199 char *p
= mnemonicendp
;
17208 if (sizeflag
& SUFFIX_ALWAYS
)
17214 if (sizeflag
& DFLAG
)
17218 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17223 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17230 OP_M (bytemode
, sizeflag
);
17234 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17237 const char **names
;
17239 /* Skip mod/rm byte. */
17253 oappend (names
[reg
]);
17257 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17259 const char **names
;
17266 oappend (names
[vex
.register_specifier
]);
17270 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17273 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17277 if ((rex
& REX_R
) != 0 || !vex
.r
)
17283 oappend (names_mask
[modrm
.reg
]);
17287 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17290 || (bytemode
!= evex_rounding_mode
17291 && bytemode
!= evex_sae_mode
))
17293 if (modrm
.mod
== 3 && vex
.b
)
17296 case evex_rounding_mode
:
17297 oappend (names_rounding
[vex
.ll
]);
17299 case evex_sae_mode
: