opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "dis-asm.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VEXI4_Fixup (int, int);
  99 static void VZERO_Fixup (int, int);
 100 static void VCMP_Fixup (int, int);
 101 static void VPCMP_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void OP_LWPCB_E (int, int);
 121 static void OP_LWP_E (int, int);
 122 static void OP_Vex_2src_1 (int, int);
 123 static void OP_Vex_2src_2 (int, int);
 124
 125 static void MOVBE_Fixup (int, int);
 126
 127 static void OP_Mask (int, int);
 128
 129 struct dis_private {
 130   /* Points to first byte not fetched.  */
 131   bfd_byte *max_fetched;
 132   bfd_byte the_buffer[MAX_MNEM_SIZE];
 133   bfd_vma insn_start;
 134   int orig_sizeflag;
 135   OPCODES_SIGJMP_BUF bailout;
 136 };
 137
 138 enum address_mode
 139 {
 140   mode_16bit,
 141   mode_32bit,
 142   mode_64bit
 143 };
 144
 145 enum address_mode address_mode;
 146
 147 /* Flags for the prefixes for the current instruction.  See below.  */
 148 static int prefixes;
 149
 150 /* REX prefix the current instruction.  See below.  */
 151 static int rex;
 152 /* Bits of REX we've already used.  */
 153 static int rex_used;
 154 /* REX bits in original REX prefix ignored.  */
 155 static int rex_ignored;
 156 /* Mark parts used in the REX prefix.  When we are testing for
 157    empty prefix (for 8bit register REX extension), just mask it
 158    out.  Otherwise test for REX bit is excuse for existence of REX
 159    only in case value is nonzero.  */
 160 #define USED_REX(value)                                 \
 161   {                                                     \
 162     if (value)                                          \
 163       {                                                 \
 164         if ((rex & value))                              \
 165           rex_used |= (value) | REX_OPCODE;             \
 166       }                                                 \
 167     else                                                \
 168       rex_used |= REX_OPCODE;                           \
 169   }
 170
 171 /* Flags for prefixes which we somehow handled when printing the
 172    current instruction.  */
 173 static int used_prefixes;
 174
 175 /* Flags stored in PREFIXES.  */
 176 #define PREFIX_REPZ 1
 177 #define PREFIX_REPNZ 2
 178 #define PREFIX_LOCK 4
 179 #define PREFIX_CS 8
 180 #define PREFIX_SS 0x10
 181 #define PREFIX_DS 0x20
 182 #define PREFIX_ES 0x40
 183 #define PREFIX_FS 0x80
 184 #define PREFIX_GS 0x100
 185 #define PREFIX_DATA 0x200
 186 #define PREFIX_ADDR 0x400
 187 #define PREFIX_FWAIT 0x800
 188
 189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 190    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 191    on error.  */
 192 #define FETCH_DATA(info, addr) \
 193   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 194    ? 1 : fetch_data ((info), (addr)))
 195
 196 static int
 197 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 198 {
 199   int status;
 200   struct dis_private *priv = (struct dis_private *) info->private_data;
 201   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 202
 203   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 204     status = (*info->read_memory_func) (start,
 205                                         priv->max_fetched,
 206                                         addr - priv->max_fetched,
 207                                         info);
 208   else
 209     status = -1;
 210   if (status != 0)
 211     {
 212       /* If we did manage to read at least one byte, then
 213          print_insn_i386 will do something sensible.  Otherwise, print
 214          an error.  We do that here because this is where we know
 215          STATUS.  */
 216       if (priv->max_fetched == priv->the_buffer)
 217         (*info->memory_error_func) (status, start, info);
 218       OPCODES_SIGLONGJMP (priv->bailout, 1);
 219     }
 220   else
 221     priv->max_fetched = addr;
 222   return 1;
 223 }
 224
 225 /* Possible values for prefix requirement.  */
 226 #define PREFIX_IGNORED_SHIFT    16
 227 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 228 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 232
 233 /* Opcode prefixes.  */
 234 #define PREFIX_OPCODE           (PREFIX_REPZ \
 235                                  | PREFIX_REPNZ \
 236                                  | PREFIX_DATA)
 237
 238 /* Prefixes ignored.  */
 239 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 240                                  | PREFIX_IGNORED_REPNZ \
 241                                  | PREFIX_IGNORED_DATA)
 242
 243 #define XX { NULL, 0 }
 244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 245
 246 #define Eb { OP_E, b_mode }
 247 #define Ebnd { OP_E, bnd_mode }
 248 #define EbS { OP_E, b_swap_mode }
 249 #define Ev { OP_E, v_mode }
 250 #define Ev_bnd { OP_E, v_bnd_mode }
 251 #define EvS { OP_E, v_swap_mode }
 252 #define Ed { OP_E, d_mode }
 253 #define Edq { OP_E, dq_mode }
 254 #define Edqw { OP_E, dqw_mode }
 255 #define Edqb { OP_E, dqb_mode }
 256 #define Edb { OP_E, db_mode }
 257 #define Edw { OP_E, dw_mode }
 258 #define Edqd { OP_E, dqd_mode }
 259 #define Eq { OP_E, q_mode }
 260 #define indirEv { OP_indirE, indir_v_mode }
 261 #define indirEp { OP_indirE, f_mode }
 262 #define stackEv { OP_E, stack_v_mode }
 263 #define Em { OP_E, m_mode }
 264 #define Ew { OP_E, w_mode }
 265 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 266 #define Ma { OP_M, a_mode }
 267 #define Mb { OP_M, b_mode }
 268 #define Md { OP_M, d_mode }
 269 #define Mo { OP_M, o_mode }
 270 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 271 #define Mq { OP_M, q_mode }
 272 #define Mx { OP_M, x_mode }
 273 #define Mxmm { OP_M, xmm_mode }
 274 #define Gb { OP_G, b_mode }
 275 #define Gbnd { OP_G, bnd_mode }
 276 #define Gv { OP_G, v_mode }
 277 #define Gd { OP_G, d_mode }
 278 #define Gdq { OP_G, dq_mode }
 279 #define Gm { OP_G, m_mode }
 280 #define Gw { OP_G, w_mode }
 281 #define Rd { OP_R, d_mode }
 282 #define Rdq { OP_R, dq_mode }
 283 #define Rm { OP_R, m_mode }
 284 #define Ib { OP_I, b_mode }
 285 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 286 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 287 #define Iv { OP_I, v_mode }
 288 #define sIv { OP_sI, v_mode }
 289 #define Iq { OP_I, q_mode }
 290 #define Iv64 { OP_I64, v_mode }
 291 #define Iw { OP_I, w_mode }
 292 #define I1 { OP_I, const_1_mode }
 293 #define Jb { OP_J, b_mode }
 294 #define Jv { OP_J, v_mode }
 295 #define Cm { OP_C, m_mode }
 296 #define Dm { OP_D, m_mode }
 297 #define Td { OP_T, d_mode }
 298 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 299
 300 #define RMeAX { OP_REG, eAX_reg }
 301 #define RMeBX { OP_REG, eBX_reg }
 302 #define RMeCX { OP_REG, eCX_reg }
 303 #define RMeDX { OP_REG, eDX_reg }
 304 #define RMeSP { OP_REG, eSP_reg }
 305 #define RMeBP { OP_REG, eBP_reg }
 306 #define RMeSI { OP_REG, eSI_reg }
 307 #define RMeDI { OP_REG, eDI_reg }
 308 #define RMrAX { OP_REG, rAX_reg }
 309 #define RMrBX { OP_REG, rBX_reg }
 310 #define RMrCX { OP_REG, rCX_reg }
 311 #define RMrDX { OP_REG, rDX_reg }
 312 #define RMrSP { OP_REG, rSP_reg }
 313 #define RMrBP { OP_REG, rBP_reg }
 314 #define RMrSI { OP_REG, rSI_reg }
 315 #define RMrDI { OP_REG, rDI_reg }
 316 #define RMAL { OP_REG, al_reg }
 317 #define RMCL { OP_REG, cl_reg }
 318 #define RMDL { OP_REG, dl_reg }
 319 #define RMBL { OP_REG, bl_reg }
 320 #define RMAH { OP_REG, ah_reg }
 321 #define RMCH { OP_REG, ch_reg }
 322 #define RMDH { OP_REG, dh_reg }
 323 #define RMBH { OP_REG, bh_reg }
 324 #define RMAX { OP_REG, ax_reg }
 325 #define RMDX { OP_REG, dx_reg }
 326
 327 #define eAX { OP_IMREG, eAX_reg }
 328 #define eBX { OP_IMREG, eBX_reg }
 329 #define eCX { OP_IMREG, eCX_reg }
 330 #define eDX { OP_IMREG, eDX_reg }
 331 #define eSP { OP_IMREG, eSP_reg }
 332 #define eBP { OP_IMREG, eBP_reg }
 333 #define eSI { OP_IMREG, eSI_reg }
 334 #define eDI { OP_IMREG, eDI_reg }
 335 #define AL { OP_IMREG, al_reg }
 336 #define CL { OP_IMREG, cl_reg }
 337 #define DL { OP_IMREG, dl_reg }
 338 #define BL { OP_IMREG, bl_reg }
 339 #define AH { OP_IMREG, ah_reg }
 340 #define CH { OP_IMREG, ch_reg }
 341 #define DH { OP_IMREG, dh_reg }
 342 #define BH { OP_IMREG, bh_reg }
 343 #define AX { OP_IMREG, ax_reg }
 344 #define DX { OP_IMREG, dx_reg }
 345 #define zAX { OP_IMREG, z_mode_ax_reg }
 346 #define indirDX { OP_IMREG, indir_dx_reg }
 347
 348 #define Sw { OP_SEG, w_mode }
 349 #define Sv { OP_SEG, v_mode }
 350 #define Ap { OP_DIR, 0 }
 351 #define Ob { OP_OFF64, b_mode }
 352 #define Ov { OP_OFF64, v_mode }
 353 #define Xb { OP_DSreg, eSI_reg }
 354 #define Xv { OP_DSreg, eSI_reg }
 355 #define Xz { OP_DSreg, eSI_reg }
 356 #define Yb { OP_ESreg, eDI_reg }
 357 #define Yv { OP_ESreg, eDI_reg }
 358 #define DSBX { OP_DSreg, eBX_reg }
 359
 360 #define es { OP_REG, es_reg }
 361 #define ss { OP_REG, ss_reg }
 362 #define cs { OP_REG, cs_reg }
 363 #define ds { OP_REG, ds_reg }
 364 #define fs { OP_REG, fs_reg }
 365 #define gs { OP_REG, gs_reg }
 366
 367 #define MX { OP_MMX, 0 }
 368 #define XM { OP_XMM, 0 }
 369 #define XMScalar { OP_XMM, scalar_mode }
 370 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 371 #define XMM { OP_XMM, xmm_mode }
 372 #define XMxmmq { OP_XMM, xmmq_mode }
 373 #define EM { OP_EM, v_mode }
 374 #define EMS { OP_EM, v_swap_mode }
 375 #define EMd { OP_EM, d_mode }
 376 #define EMx { OP_EM, x_mode }
 377 #define EXw { OP_EX, w_mode }
 378 #define EXd { OP_EX, d_mode }
 379 #define EXdScalar { OP_EX, d_scalar_mode }
 380 #define EXdS { OP_EX, d_swap_mode }
 381 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 382 #define EXq { OP_EX, q_mode }
 383 #define EXqScalar { OP_EX, q_scalar_mode }
 384 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 385 #define EXqS { OP_EX, q_swap_mode }
 386 #define EXx { OP_EX, x_mode }
 387 #define EXxS { OP_EX, x_swap_mode }
 388 #define EXxmm { OP_EX, xmm_mode }
 389 #define EXymm { OP_EX, ymm_mode }
 390 #define EXxmmq { OP_EX, xmmq_mode }
 391 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 392 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 393 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 394 #define EXxmm_md { OP_EX, xmm_md_mode }
 395 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 396 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 397 #define EXxmmdw { OP_EX, xmmdw_mode }
 398 #define EXxmmqd { OP_EX, xmmqd_mode }
 399 #define EXymmq { OP_EX, ymmq_mode }
 400 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 401 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 402 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 403 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 404 #define MS { OP_MS, v_mode }
 405 #define XS { OP_XS, v_mode }
 406 #define EMCq { OP_EMC, q_mode }
 407 #define MXC { OP_MXC, 0 }
 408 #define OPSUF { OP_3DNowSuffix, 0 }
 409 #define CMP { CMP_Fixup, 0 }
 410 #define XMM0 { XMM_Fixup, 0 }
 411 #define FXSAVE { FXSAVE_Fixup, 0 }
 412 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 413 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 414
 415 #define Vex { OP_VEX, vex_mode }
 416 #define VexScalar { OP_VEX, vex_scalar_mode }
 417 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 418 #define Vex128 { OP_VEX, vex128_mode }
 419 #define Vex256 { OP_VEX, vex256_mode }
 420 #define VexGdq { OP_VEX, dq_mode }
 421 #define VexI4 { VEXI4_Fixup, 0}
 422 #define EXdVex { OP_EX_Vex, d_mode }
 423 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 424 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 425 #define EXqVex { OP_EX_Vex, q_mode }
 426 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 428 #define EXVexW { OP_EX_VexW, x_mode }
 429 #define EXdVexW { OP_EX_VexW, d_mode }
 430 #define EXqVexW { OP_EX_VexW, q_mode }
 431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 432 #define XMVex { OP_XMM_Vex, 0 }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VZERO { VZERO_Fixup, 0 }
 438 #define VCMP { VCMP_Fixup, 0 }
 439 #define VPCMP { VPCMP_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 443
 444 #define XMask { OP_Mask, mask_mode }
 445 #define MaskG { OP_G, mask_mode }
 446 #define MaskE { OP_E, mask_mode }
 447 #define MaskBDE { OP_E, mask_bd_mode }
 448 #define MaskR { OP_R, mask_mode }
 449 #define MaskVex { OP_VEX, mask_mode }
 450
 451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 455
 456 /* Used handle "rep" prefix for string instructions.  */
 457 #define Xbr { REP_Fixup, eSI_reg }
 458 #define Xvr { REP_Fixup, eSI_reg }
 459 #define Ybr { REP_Fixup, eDI_reg }
 460 #define Yvr { REP_Fixup, eDI_reg }
 461 #define Yzr { REP_Fixup, eDI_reg }
 462 #define indirDXr { REP_Fixup, indir_dx_reg }
 463 #define ALr { REP_Fixup, al_reg }
 464 #define eAXr { REP_Fixup, eAX_reg }
 465
 466 /* Used handle HLE prefix for lockable instructions.  */
 467 #define Ebh1 { HLE_Fixup1, b_mode }
 468 #define Evh1 { HLE_Fixup1, v_mode }
 469 #define Ebh2 { HLE_Fixup2, b_mode }
 470 #define Evh2 { HLE_Fixup2, v_mode }
 471 #define Ebh3 { HLE_Fixup3, b_mode }
 472 #define Evh3 { HLE_Fixup3, v_mode }
 473
 474 #define BND { BND_Fixup, 0 }
 475
 476 #define cond_jump_flag { NULL, cond_jump_mode }
 477 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 478
 479 /* bits in sizeflag */
 480 #define SUFFIX_ALWAYS 4
 481 #define AFLAG 2
 482 #define DFLAG 1
 483
 484 enum
 485 {
 486   /* byte operand */
 487   b_mode = 1,
 488   /* byte operand with operand swapped */
 489   b_swap_mode,
 490   /* byte operand, sign extend like 'T' suffix */
 491   b_T_mode,
 492   /* operand size depends on prefixes */
 493   v_mode,
 494   /* operand size depends on prefixes with operand swapped */
 495   v_swap_mode,
 496   /* word operand */
 497   w_mode,
 498   /* double word operand  */
 499   d_mode,
 500   /* double word operand with operand swapped */
 501   d_swap_mode,
 502   /* quad word operand */
 503   q_mode,
 504   /* quad word operand with operand swapped */
 505   q_swap_mode,
 506   /* ten-byte operand */
 507   t_mode,
 508   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 509      broadcast enabled.  */
 510   x_mode,
 511   /* Similar to x_mode, but with different EVEX mem shifts.  */
 512   evex_x_gscat_mode,
 513   /* Similar to x_mode, but with disabled broadcast.  */
 514   evex_x_nobcst_mode,
 515   /* Similar to x_mode, but with operands swapped and disabled broadcast
 516      in EVEX.  */
 517   x_swap_mode,
 518   /* 16-byte XMM operand */
 519   xmm_mode,
 520   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 521      memory operand (depending on vector length).  Broadcast isn't
 522      allowed.  */
 523   xmmq_mode,
 524   /* Same as xmmq_mode, but broadcast is allowed.  */
 525   evex_half_bcst_xmmq_mode,
 526   /* XMM register or byte memory operand */
 527   xmm_mb_mode,
 528   /* XMM register or word memory operand */
 529   xmm_mw_mode,
 530   /* XMM register or double word memory operand */
 531   xmm_md_mode,
 532   /* XMM register or quad word memory operand */
 533   xmm_mq_mode,
 534   /* XMM register or double/quad word memory operand, depending on
 535      VEX.W.  */
 536   xmm_mdq_mode,
 537   /* 16-byte XMM, word, double word or quad word operand.  */
 538   xmmdw_mode,
 539   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 540   xmmqd_mode,
 541   /* 32-byte YMM operand */
 542   ymm_mode,
 543   /* quad word, ymmword or zmmword memory operand.  */
 544   ymmq_mode,
 545   /* 32-byte YMM or 16-byte word operand */
 546   ymmxmm_mode,
 547   /* d_mode in 32bit, q_mode in 64bit mode.  */
 548   m_mode,
 549   /* pair of v_mode operands */
 550   a_mode,
 551   cond_jump_mode,
 552   loop_jcxz_mode,
 553   v_bnd_mode,
 554   /* operand size depends on REX prefixes.  */
 555   dq_mode,
 556   /* registers like dq_mode, memory like w_mode.  */
 557   dqw_mode,
 558   bnd_mode,
 559   /* 4- or 6-byte pointer operand */
 560   f_mode,
 561   const_1_mode,
 562   /* v_mode for indirect branch opcodes.  */
 563   indir_v_mode,
 564   /* v_mode for stack-related opcodes.  */
 565   stack_v_mode,
 566   /* non-quad operand size depends on prefixes */
 567   z_mode,
 568   /* 16-byte operand */
 569   o_mode,
 570   /* registers like dq_mode, memory like b_mode.  */
 571   dqb_mode,
 572   /* registers like d_mode, memory like b_mode.  */
 573   db_mode,
 574   /* registers like d_mode, memory like w_mode.  */
 575   dw_mode,
 576   /* registers like dq_mode, memory like d_mode.  */
 577   dqd_mode,
 578   /* normal vex mode */
 579   vex_mode,
 580   /* 128bit vex mode */
 581   vex128_mode,
 582   /* 256bit vex mode */
 583   vex256_mode,
 584   /* operand size depends on the VEX.W bit.  */
 585   vex_w_dq_mode,
 586
 587   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 588   vex_vsib_d_w_dq_mode,
 589   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 590   vex_vsib_d_w_d_mode,
 591   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 592   vex_vsib_q_w_dq_mode,
 593   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 594   vex_vsib_q_w_d_mode,
 595
 596   /* scalar, ignore vector length.  */
 597   scalar_mode,
 598   /* like d_mode, ignore vector length.  */
 599   d_scalar_mode,
 600   /* like d_swap_mode, ignore vector length.  */
 601   d_scalar_swap_mode,
 602   /* like q_mode, ignore vector length.  */
 603   q_scalar_mode,
 604   /* like q_swap_mode, ignore vector length.  */
 605   q_scalar_swap_mode,
 606   /* like vex_mode, ignore vector length.  */
 607   vex_scalar_mode,
 608   /* like vex_w_dq_mode, ignore vector length.  */
 609   vex_scalar_w_dq_mode,
 610
 611   /* Static rounding.  */
 612   evex_rounding_mode,
 613   /* Supress all exceptions.  */
 614   evex_sae_mode,
 615
 616   /* Mask register operand.  */
 617   mask_mode,
 618   /* Mask register operand.  */
 619   mask_bd_mode,
 620
 621   es_reg,
 622   cs_reg,
 623   ss_reg,
 624   ds_reg,
 625   fs_reg,
 626   gs_reg,
 627
 628   eAX_reg,
 629   eCX_reg,
 630   eDX_reg,
 631   eBX_reg,
 632   eSP_reg,
 633   eBP_reg,
 634   eSI_reg,
 635   eDI_reg,
 636
 637   al_reg,
 638   cl_reg,
 639   dl_reg,
 640   bl_reg,
 641   ah_reg,
 642   ch_reg,
 643   dh_reg,
 644   bh_reg,
 645
 646   ax_reg,
 647   cx_reg,
 648   dx_reg,
 649   bx_reg,
 650   sp_reg,
 651   bp_reg,
 652   si_reg,
 653   di_reg,
 654
 655   rAX_reg,
 656   rCX_reg,
 657   rDX_reg,
 658   rBX_reg,
 659   rSP_reg,
 660   rBP_reg,
 661   rSI_reg,
 662   rDI_reg,
 663
 664   z_mode_ax_reg,
 665   indir_dx_reg
 666 };
 667
 668 enum
 669 {
 670   FLOATCODE = 1,
 671   USE_REG_TABLE,
 672   USE_MOD_TABLE,
 673   USE_RM_TABLE,
 674   USE_PREFIX_TABLE,
 675   USE_X86_64_TABLE,
 676   USE_3BYTE_TABLE,
 677   USE_XOP_8F_TABLE,
 678   USE_VEX_C4_TABLE,
 679   USE_VEX_C5_TABLE,
 680   USE_VEX_LEN_TABLE,
 681   USE_VEX_W_TABLE,
 682   USE_EVEX_TABLE
 683 };
 684
 685 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 686
 687 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 688 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 689 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 690 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 691 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 692 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 693 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 694 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 695 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 696 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 697 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 698 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 699 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 700 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 701 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 702
 703 enum
 704 {
 705   REG_80 = 0,
 706   REG_81,
 707   REG_83,
 708   REG_8F,
 709   REG_C0,
 710   REG_C1,
 711   REG_C6,
 712   REG_C7,
 713   REG_D0,
 714   REG_D1,
 715   REG_D2,
 716   REG_D3,
 717   REG_F6,
 718   REG_F7,
 719   REG_FE,
 720   REG_FF,
 721   REG_0F00,
 722   REG_0F01,
 723   REG_0F0D,
 724   REG_0F18,
 725   REG_0F71,
 726   REG_0F72,
 727   REG_0F73,
 728   REG_0FA6,
 729   REG_0FA7,
 730   REG_0FAE,
 731   REG_0FBA,
 732   REG_0FC7,
 733   REG_VEX_0F71,
 734   REG_VEX_0F72,
 735   REG_VEX_0F73,
 736   REG_VEX_0FAE,
 737   REG_VEX_0F38F3,
 738   REG_XOP_LWPCB,
 739   REG_XOP_LWP,
 740   REG_XOP_TBM_01,
 741   REG_XOP_TBM_02,
 742
 743   REG_EVEX_0F71,
 744   REG_EVEX_0F72,
 745   REG_EVEX_0F73,
 746   REG_EVEX_0F38C6,
 747   REG_EVEX_0F38C7
 748 };
 749
 750 enum
 751 {
 752   MOD_8D = 0,
 753   MOD_C6_REG_7,
 754   MOD_C7_REG_7,
 755   MOD_FF_REG_3,
 756   MOD_FF_REG_5,
 757   MOD_0F01_REG_0,
 758   MOD_0F01_REG_1,
 759   MOD_0F01_REG_2,
 760   MOD_0F01_REG_3,
 761   MOD_0F01_REG_5,
 762   MOD_0F01_REG_7,
 763   MOD_0F12_PREFIX_0,
 764   MOD_0F13,
 765   MOD_0F16_PREFIX_0,
 766   MOD_0F17,
 767   MOD_0F18_REG_0,
 768   MOD_0F18_REG_1,
 769   MOD_0F18_REG_2,
 770   MOD_0F18_REG_3,
 771   MOD_0F18_REG_4,
 772   MOD_0F18_REG_5,
 773   MOD_0F18_REG_6,
 774   MOD_0F18_REG_7,
 775   MOD_0F1A_PREFIX_0,
 776   MOD_0F1B_PREFIX_0,
 777   MOD_0F1B_PREFIX_1,
 778   MOD_0F24,
 779   MOD_0F26,
 780   MOD_0F2B_PREFIX_0,
 781   MOD_0F2B_PREFIX_1,
 782   MOD_0F2B_PREFIX_2,
 783   MOD_0F2B_PREFIX_3,
 784   MOD_0F51,
 785   MOD_0F71_REG_2,
 786   MOD_0F71_REG_4,
 787   MOD_0F71_REG_6,
 788   MOD_0F72_REG_2,
 789   MOD_0F72_REG_4,
 790   MOD_0F72_REG_6,
 791   MOD_0F73_REG_2,
 792   MOD_0F73_REG_3,
 793   MOD_0F73_REG_6,
 794   MOD_0F73_REG_7,
 795   MOD_0FAE_REG_0,
 796   MOD_0FAE_REG_1,
 797   MOD_0FAE_REG_2,
 798   MOD_0FAE_REG_3,
 799   MOD_0FAE_REG_4,
 800   MOD_0FAE_REG_5,
 801   MOD_0FAE_REG_6,
 802   MOD_0FAE_REG_7,
 803   MOD_0FB2,
 804   MOD_0FB4,
 805   MOD_0FB5,
 806   MOD_0FC3,
 807   MOD_0FC7_REG_3,
 808   MOD_0FC7_REG_4,
 809   MOD_0FC7_REG_5,
 810   MOD_0FC7_REG_6,
 811   MOD_0FC7_REG_7,
 812   MOD_0FD7,
 813   MOD_0FE7_PREFIX_2,
 814   MOD_0FF0_PREFIX_3,
 815   MOD_0F382A_PREFIX_2,
 816   MOD_62_32BIT,
 817   MOD_C4_32BIT,
 818   MOD_C5_32BIT,
 819   MOD_VEX_0F12_PREFIX_0,
 820   MOD_VEX_0F13,
 821   MOD_VEX_0F16_PREFIX_0,
 822   MOD_VEX_0F17,
 823   MOD_VEX_0F2B,
 824   MOD_VEX_W_0_0F41_P_0_LEN_1,
 825   MOD_VEX_W_1_0F41_P_0_LEN_1,
 826   MOD_VEX_W_0_0F41_P_2_LEN_1,
 827   MOD_VEX_W_1_0F41_P_2_LEN_1,
 828   MOD_VEX_W_0_0F42_P_0_LEN_1,
 829   MOD_VEX_W_1_0F42_P_0_LEN_1,
 830   MOD_VEX_W_0_0F42_P_2_LEN_1,
 831   MOD_VEX_W_1_0F42_P_2_LEN_1,
 832   MOD_VEX_W_0_0F44_P_0_LEN_1,
 833   MOD_VEX_W_1_0F44_P_0_LEN_1,
 834   MOD_VEX_W_0_0F44_P_2_LEN_1,
 835   MOD_VEX_W_1_0F44_P_2_LEN_1,
 836   MOD_VEX_W_0_0F45_P_0_LEN_1,
 837   MOD_VEX_W_1_0F45_P_0_LEN_1,
 838   MOD_VEX_W_0_0F45_P_2_LEN_1,
 839   MOD_VEX_W_1_0F45_P_2_LEN_1,
 840   MOD_VEX_W_0_0F46_P_0_LEN_1,
 841   MOD_VEX_W_1_0F46_P_0_LEN_1,
 842   MOD_VEX_W_0_0F46_P_2_LEN_1,
 843   MOD_VEX_W_1_0F46_P_2_LEN_1,
 844   MOD_VEX_W_0_0F47_P_0_LEN_1,
 845   MOD_VEX_W_1_0F47_P_0_LEN_1,
 846   MOD_VEX_W_0_0F47_P_2_LEN_1,
 847   MOD_VEX_W_1_0F47_P_2_LEN_1,
 848   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 849   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 850   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 851   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 852   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 853   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 854   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 855   MOD_VEX_0F50,
 856   MOD_VEX_0F71_REG_2,
 857   MOD_VEX_0F71_REG_4,
 858   MOD_VEX_0F71_REG_6,
 859   MOD_VEX_0F72_REG_2,
 860   MOD_VEX_0F72_REG_4,
 861   MOD_VEX_0F72_REG_6,
 862   MOD_VEX_0F73_REG_2,
 863   MOD_VEX_0F73_REG_3,
 864   MOD_VEX_0F73_REG_6,
 865   MOD_VEX_0F73_REG_7,
 866   MOD_VEX_W_0_0F91_P_0_LEN_0,
 867   MOD_VEX_W_1_0F91_P_0_LEN_0,
 868   MOD_VEX_W_0_0F91_P_2_LEN_0,
 869   MOD_VEX_W_1_0F91_P_2_LEN_0,
 870   MOD_VEX_W_0_0F92_P_0_LEN_0,
 871   MOD_VEX_W_0_0F92_P_2_LEN_0,
 872   MOD_VEX_W_0_0F92_P_3_LEN_0,
 873   MOD_VEX_W_1_0F92_P_3_LEN_0,
 874   MOD_VEX_W_0_0F93_P_0_LEN_0,
 875   MOD_VEX_W_0_0F93_P_2_LEN_0,
 876   MOD_VEX_W_0_0F93_P_3_LEN_0,
 877   MOD_VEX_W_1_0F93_P_3_LEN_0,
 878   MOD_VEX_W_0_0F98_P_0_LEN_0,
 879   MOD_VEX_W_1_0F98_P_0_LEN_0,
 880   MOD_VEX_W_0_0F98_P_2_LEN_0,
 881   MOD_VEX_W_1_0F98_P_2_LEN_0,
 882   MOD_VEX_W_0_0F99_P_0_LEN_0,
 883   MOD_VEX_W_1_0F99_P_0_LEN_0,
 884   MOD_VEX_W_0_0F99_P_2_LEN_0,
 885   MOD_VEX_W_1_0F99_P_2_LEN_0,
 886   MOD_VEX_0FAE_REG_2,
 887   MOD_VEX_0FAE_REG_3,
 888   MOD_VEX_0FD7_PREFIX_2,
 889   MOD_VEX_0FE7_PREFIX_2,
 890   MOD_VEX_0FF0_PREFIX_3,
 891   MOD_VEX_0F381A_PREFIX_2,
 892   MOD_VEX_0F382A_PREFIX_2,
 893   MOD_VEX_0F382C_PREFIX_2,
 894   MOD_VEX_0F382D_PREFIX_2,
 895   MOD_VEX_0F382E_PREFIX_2,
 896   MOD_VEX_0F382F_PREFIX_2,
 897   MOD_VEX_0F385A_PREFIX_2,
 898   MOD_VEX_0F388C_PREFIX_2,
 899   MOD_VEX_0F388E_PREFIX_2,
 900   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 901   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 902   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 903   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 904   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 905   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 906   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 907   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 908
 909   MOD_EVEX_0F10_PREFIX_1,
 910   MOD_EVEX_0F10_PREFIX_3,
 911   MOD_EVEX_0F11_PREFIX_1,
 912   MOD_EVEX_0F11_PREFIX_3,
 913   MOD_EVEX_0F12_PREFIX_0,
 914   MOD_EVEX_0F16_PREFIX_0,
 915   MOD_EVEX_0F38C6_REG_1,
 916   MOD_EVEX_0F38C6_REG_2,
 917   MOD_EVEX_0F38C6_REG_5,
 918   MOD_EVEX_0F38C6_REG_6,
 919   MOD_EVEX_0F38C7_REG_1,
 920   MOD_EVEX_0F38C7_REG_2,
 921   MOD_EVEX_0F38C7_REG_5,
 922   MOD_EVEX_0F38C7_REG_6
 923 };
 924
 925 enum
 926 {
 927   RM_C6_REG_7 = 0,
 928   RM_C7_REG_7,
 929   RM_0F01_REG_0,
 930   RM_0F01_REG_1,
 931   RM_0F01_REG_2,
 932   RM_0F01_REG_3,
 933   RM_0F01_REG_5,
 934   RM_0F01_REG_7,
 935   RM_0FAE_REG_5,
 936   RM_0FAE_REG_6,
 937   RM_0FAE_REG_7
 938 };
 939
 940 enum
 941 {
 942   PREFIX_90 = 0,
 943   PREFIX_0F10,
 944   PREFIX_0F11,
 945   PREFIX_0F12,
 946   PREFIX_0F16,
 947   PREFIX_0F1A,
 948   PREFIX_0F1B,
 949   PREFIX_0F2A,
 950   PREFIX_0F2B,
 951   PREFIX_0F2C,
 952   PREFIX_0F2D,
 953   PREFIX_0F2E,
 954   PREFIX_0F2F,
 955   PREFIX_0F51,
 956   PREFIX_0F52,
 957   PREFIX_0F53,
 958   PREFIX_0F58,
 959   PREFIX_0F59,
 960   PREFIX_0F5A,
 961   PREFIX_0F5B,
 962   PREFIX_0F5C,
 963   PREFIX_0F5D,
 964   PREFIX_0F5E,
 965   PREFIX_0F5F,
 966   PREFIX_0F60,
 967   PREFIX_0F61,
 968   PREFIX_0F62,
 969   PREFIX_0F6C,
 970   PREFIX_0F6D,
 971   PREFIX_0F6F,
 972   PREFIX_0F70,
 973   PREFIX_0F73_REG_3,
 974   PREFIX_0F73_REG_7,
 975   PREFIX_0F78,
 976   PREFIX_0F79,
 977   PREFIX_0F7C,
 978   PREFIX_0F7D,
 979   PREFIX_0F7E,
 980   PREFIX_0F7F,
 981   PREFIX_0FAE_REG_0,
 982   PREFIX_0FAE_REG_1,
 983   PREFIX_0FAE_REG_2,
 984   PREFIX_0FAE_REG_3,
 985   PREFIX_MOD_0_0FAE_REG_4,
 986   PREFIX_MOD_3_0FAE_REG_4,
 987   PREFIX_0FAE_REG_6,
 988   PREFIX_0FAE_REG_7,
 989   PREFIX_0FB8,
 990   PREFIX_0FBC,
 991   PREFIX_0FBD,
 992   PREFIX_0FC2,
 993   PREFIX_MOD_0_0FC3,
 994   PREFIX_MOD_0_0FC7_REG_6,
 995   PREFIX_MOD_3_0FC7_REG_6,
 996   PREFIX_MOD_3_0FC7_REG_7,
 997   PREFIX_0FD0,
 998   PREFIX_0FD6,
 999   PREFIX_0FE6,
1000   PREFIX_0FE7,
1001   PREFIX_0FF0,
1002   PREFIX_0FF7,
1003   PREFIX_0F3810,
1004   PREFIX_0F3814,
1005   PREFIX_0F3815,
1006   PREFIX_0F3817,
1007   PREFIX_0F3820,
1008   PREFIX_0F3821,
1009   PREFIX_0F3822,
1010   PREFIX_0F3823,
1011   PREFIX_0F3824,
1012   PREFIX_0F3825,
1013   PREFIX_0F3828,
1014   PREFIX_0F3829,
1015   PREFIX_0F382A,
1016   PREFIX_0F382B,
1017   PREFIX_0F3830,
1018   PREFIX_0F3831,
1019   PREFIX_0F3832,
1020   PREFIX_0F3833,
1021   PREFIX_0F3834,
1022   PREFIX_0F3835,
1023   PREFIX_0F3837,
1024   PREFIX_0F3838,
1025   PREFIX_0F3839,
1026   PREFIX_0F383A,
1027   PREFIX_0F383B,
1028   PREFIX_0F383C,
1029   PREFIX_0F383D,
1030   PREFIX_0F383E,
1031   PREFIX_0F383F,
1032   PREFIX_0F3840,
1033   PREFIX_0F3841,
1034   PREFIX_0F3880,
1035   PREFIX_0F3881,
1036   PREFIX_0F3882,
1037   PREFIX_0F38C8,
1038   PREFIX_0F38C9,
1039   PREFIX_0F38CA,
1040   PREFIX_0F38CB,
1041   PREFIX_0F38CC,
1042   PREFIX_0F38CD,
1043   PREFIX_0F38DB,
1044   PREFIX_0F38DC,
1045   PREFIX_0F38DD,
1046   PREFIX_0F38DE,
1047   PREFIX_0F38DF,
1048   PREFIX_0F38F0,
1049   PREFIX_0F38F1,
1050   PREFIX_0F38F6,
1051   PREFIX_0F3A08,
1052   PREFIX_0F3A09,
1053   PREFIX_0F3A0A,
1054   PREFIX_0F3A0B,
1055   PREFIX_0F3A0C,
1056   PREFIX_0F3A0D,
1057   PREFIX_0F3A0E,
1058   PREFIX_0F3A14,
1059   PREFIX_0F3A15,
1060   PREFIX_0F3A16,
1061   PREFIX_0F3A17,
1062   PREFIX_0F3A20,
1063   PREFIX_0F3A21,
1064   PREFIX_0F3A22,
1065   PREFIX_0F3A40,
1066   PREFIX_0F3A41,
1067   PREFIX_0F3A42,
1068   PREFIX_0F3A44,
1069   PREFIX_0F3A60,
1070   PREFIX_0F3A61,
1071   PREFIX_0F3A62,
1072   PREFIX_0F3A63,
1073   PREFIX_0F3ACC,
1074   PREFIX_0F3ADF,
1075   PREFIX_VEX_0F10,
1076   PREFIX_VEX_0F11,
1077   PREFIX_VEX_0F12,
1078   PREFIX_VEX_0F16,
1079   PREFIX_VEX_0F2A,
1080   PREFIX_VEX_0F2C,
1081   PREFIX_VEX_0F2D,
1082   PREFIX_VEX_0F2E,
1083   PREFIX_VEX_0F2F,
1084   PREFIX_VEX_0F41,
1085   PREFIX_VEX_0F42,
1086   PREFIX_VEX_0F44,
1087   PREFIX_VEX_0F45,
1088   PREFIX_VEX_0F46,
1089   PREFIX_VEX_0F47,
1090   PREFIX_VEX_0F4A,
1091   PREFIX_VEX_0F4B,
1092   PREFIX_VEX_0F51,
1093   PREFIX_VEX_0F52,
1094   PREFIX_VEX_0F53,
1095   PREFIX_VEX_0F58,
1096   PREFIX_VEX_0F59,
1097   PREFIX_VEX_0F5A,
1098   PREFIX_VEX_0F5B,
1099   PREFIX_VEX_0F5C,
1100   PREFIX_VEX_0F5D,
1101   PREFIX_VEX_0F5E,
1102   PREFIX_VEX_0F5F,
1103   PREFIX_VEX_0F60,
1104   PREFIX_VEX_0F61,
1105   PREFIX_VEX_0F62,
1106   PREFIX_VEX_0F63,
1107   PREFIX_VEX_0F64,
1108   PREFIX_VEX_0F65,
1109   PREFIX_VEX_0F66,
1110   PREFIX_VEX_0F67,
1111   PREFIX_VEX_0F68,
1112   PREFIX_VEX_0F69,
1113   PREFIX_VEX_0F6A,
1114   PREFIX_VEX_0F6B,
1115   PREFIX_VEX_0F6C,
1116   PREFIX_VEX_0F6D,
1117   PREFIX_VEX_0F6E,
1118   PREFIX_VEX_0F6F,
1119   PREFIX_VEX_0F70,
1120   PREFIX_VEX_0F71_REG_2,
1121   PREFIX_VEX_0F71_REG_4,
1122   PREFIX_VEX_0F71_REG_6,
1123   PREFIX_VEX_0F72_REG_2,
1124   PREFIX_VEX_0F72_REG_4,
1125   PREFIX_VEX_0F72_REG_6,
1126   PREFIX_VEX_0F73_REG_2,
1127   PREFIX_VEX_0F73_REG_3,
1128   PREFIX_VEX_0F73_REG_6,
1129   PREFIX_VEX_0F73_REG_7,
1130   PREFIX_VEX_0F74,
1131   PREFIX_VEX_0F75,
1132   PREFIX_VEX_0F76,
1133   PREFIX_VEX_0F77,
1134   PREFIX_VEX_0F7C,
1135   PREFIX_VEX_0F7D,
1136   PREFIX_VEX_0F7E,
1137   PREFIX_VEX_0F7F,
1138   PREFIX_VEX_0F90,
1139   PREFIX_VEX_0F91,
1140   PREFIX_VEX_0F92,
1141   PREFIX_VEX_0F93,
1142   PREFIX_VEX_0F98,
1143   PREFIX_VEX_0F99,
1144   PREFIX_VEX_0FC2,
1145   PREFIX_VEX_0FC4,
1146   PREFIX_VEX_0FC5,
1147   PREFIX_VEX_0FD0,
1148   PREFIX_VEX_0FD1,
1149   PREFIX_VEX_0FD2,
1150   PREFIX_VEX_0FD3,
1151   PREFIX_VEX_0FD4,
1152   PREFIX_VEX_0FD5,
1153   PREFIX_VEX_0FD6,
1154   PREFIX_VEX_0FD7,
1155   PREFIX_VEX_0FD8,
1156   PREFIX_VEX_0FD9,
1157   PREFIX_VEX_0FDA,
1158   PREFIX_VEX_0FDB,
1159   PREFIX_VEX_0FDC,
1160   PREFIX_VEX_0FDD,
1161   PREFIX_VEX_0FDE,
1162   PREFIX_VEX_0FDF,
1163   PREFIX_VEX_0FE0,
1164   PREFIX_VEX_0FE1,
1165   PREFIX_VEX_0FE2,
1166   PREFIX_VEX_0FE3,
1167   PREFIX_VEX_0FE4,
1168   PREFIX_VEX_0FE5,
1169   PREFIX_VEX_0FE6,
1170   PREFIX_VEX_0FE7,
1171   PREFIX_VEX_0FE8,
1172   PREFIX_VEX_0FE9,
1173   PREFIX_VEX_0FEA,
1174   PREFIX_VEX_0FEB,
1175   PREFIX_VEX_0FEC,
1176   PREFIX_VEX_0FED,
1177   PREFIX_VEX_0FEE,
1178   PREFIX_VEX_0FEF,
1179   PREFIX_VEX_0FF0,
1180   PREFIX_VEX_0FF1,
1181   PREFIX_VEX_0FF2,
1182   PREFIX_VEX_0FF3,
1183   PREFIX_VEX_0FF4,
1184   PREFIX_VEX_0FF5,
1185   PREFIX_VEX_0FF6,
1186   PREFIX_VEX_0FF7,
1187   PREFIX_VEX_0FF8,
1188   PREFIX_VEX_0FF9,
1189   PREFIX_VEX_0FFA,
1190   PREFIX_VEX_0FFB,
1191   PREFIX_VEX_0FFC,
1192   PREFIX_VEX_0FFD,
1193   PREFIX_VEX_0FFE,
1194   PREFIX_VEX_0F3800,
1195   PREFIX_VEX_0F3801,
1196   PREFIX_VEX_0F3802,
1197   PREFIX_VEX_0F3803,
1198   PREFIX_VEX_0F3804,
1199   PREFIX_VEX_0F3805,
1200   PREFIX_VEX_0F3806,
1201   PREFIX_VEX_0F3807,
1202   PREFIX_VEX_0F3808,
1203   PREFIX_VEX_0F3809,
1204   PREFIX_VEX_0F380A,
1205   PREFIX_VEX_0F380B,
1206   PREFIX_VEX_0F380C,
1207   PREFIX_VEX_0F380D,
1208   PREFIX_VEX_0F380E,
1209   PREFIX_VEX_0F380F,
1210   PREFIX_VEX_0F3813,
1211   PREFIX_VEX_0F3816,
1212   PREFIX_VEX_0F3817,
1213   PREFIX_VEX_0F3818,
1214   PREFIX_VEX_0F3819,
1215   PREFIX_VEX_0F381A,
1216   PREFIX_VEX_0F381C,
1217   PREFIX_VEX_0F381D,
1218   PREFIX_VEX_0F381E,
1219   PREFIX_VEX_0F3820,
1220   PREFIX_VEX_0F3821,
1221   PREFIX_VEX_0F3822,
1222   PREFIX_VEX_0F3823,
1223   PREFIX_VEX_0F3824,
1224   PREFIX_VEX_0F3825,
1225   PREFIX_VEX_0F3828,
1226   PREFIX_VEX_0F3829,
1227   PREFIX_VEX_0F382A,
1228   PREFIX_VEX_0F382B,
1229   PREFIX_VEX_0F382C,
1230   PREFIX_VEX_0F382D,
1231   PREFIX_VEX_0F382E,
1232   PREFIX_VEX_0F382F,
1233   PREFIX_VEX_0F3830,
1234   PREFIX_VEX_0F3831,
1235   PREFIX_VEX_0F3832,
1236   PREFIX_VEX_0F3833,
1237   PREFIX_VEX_0F3834,
1238   PREFIX_VEX_0F3835,
1239   PREFIX_VEX_0F3836,
1240   PREFIX_VEX_0F3837,
1241   PREFIX_VEX_0F3838,
1242   PREFIX_VEX_0F3839,
1243   PREFIX_VEX_0F383A,
1244   PREFIX_VEX_0F383B,
1245   PREFIX_VEX_0F383C,
1246   PREFIX_VEX_0F383D,
1247   PREFIX_VEX_0F383E,
1248   PREFIX_VEX_0F383F,
1249   PREFIX_VEX_0F3840,
1250   PREFIX_VEX_0F3841,
1251   PREFIX_VEX_0F3845,
1252   PREFIX_VEX_0F3846,
1253   PREFIX_VEX_0F3847,
1254   PREFIX_VEX_0F3858,
1255   PREFIX_VEX_0F3859,
1256   PREFIX_VEX_0F385A,
1257   PREFIX_VEX_0F3878,
1258   PREFIX_VEX_0F3879,
1259   PREFIX_VEX_0F388C,
1260   PREFIX_VEX_0F388E,
1261   PREFIX_VEX_0F3890,
1262   PREFIX_VEX_0F3891,
1263   PREFIX_VEX_0F3892,
1264   PREFIX_VEX_0F3893,
1265   PREFIX_VEX_0F3896,
1266   PREFIX_VEX_0F3897,
1267   PREFIX_VEX_0F3898,
1268   PREFIX_VEX_0F3899,
1269   PREFIX_VEX_0F389A,
1270   PREFIX_VEX_0F389B,
1271   PREFIX_VEX_0F389C,
1272   PREFIX_VEX_0F389D,
1273   PREFIX_VEX_0F389E,
1274   PREFIX_VEX_0F389F,
1275   PREFIX_VEX_0F38A6,
1276   PREFIX_VEX_0F38A7,
1277   PREFIX_VEX_0F38A8,
1278   PREFIX_VEX_0F38A9,
1279   PREFIX_VEX_0F38AA,
1280   PREFIX_VEX_0F38AB,
1281   PREFIX_VEX_0F38AC,
1282   PREFIX_VEX_0F38AD,
1283   PREFIX_VEX_0F38AE,
1284   PREFIX_VEX_0F38AF,
1285   PREFIX_VEX_0F38B6,
1286   PREFIX_VEX_0F38B7,
1287   PREFIX_VEX_0F38B8,
1288   PREFIX_VEX_0F38B9,
1289   PREFIX_VEX_0F38BA,
1290   PREFIX_VEX_0F38BB,
1291   PREFIX_VEX_0F38BC,
1292   PREFIX_VEX_0F38BD,
1293   PREFIX_VEX_0F38BE,
1294   PREFIX_VEX_0F38BF,
1295   PREFIX_VEX_0F38DB,
1296   PREFIX_VEX_0F38DC,
1297   PREFIX_VEX_0F38DD,
1298   PREFIX_VEX_0F38DE,
1299   PREFIX_VEX_0F38DF,
1300   PREFIX_VEX_0F38F2,
1301   PREFIX_VEX_0F38F3_REG_1,
1302   PREFIX_VEX_0F38F3_REG_2,
1303   PREFIX_VEX_0F38F3_REG_3,
1304   PREFIX_VEX_0F38F5,
1305   PREFIX_VEX_0F38F6,
1306   PREFIX_VEX_0F38F7,
1307   PREFIX_VEX_0F3A00,
1308   PREFIX_VEX_0F3A01,
1309   PREFIX_VEX_0F3A02,
1310   PREFIX_VEX_0F3A04,
1311   PREFIX_VEX_0F3A05,
1312   PREFIX_VEX_0F3A06,
1313   PREFIX_VEX_0F3A08,
1314   PREFIX_VEX_0F3A09,
1315   PREFIX_VEX_0F3A0A,
1316   PREFIX_VEX_0F3A0B,
1317   PREFIX_VEX_0F3A0C,
1318   PREFIX_VEX_0F3A0D,
1319   PREFIX_VEX_0F3A0E,
1320   PREFIX_VEX_0F3A0F,
1321   PREFIX_VEX_0F3A14,
1322   PREFIX_VEX_0F3A15,
1323   PREFIX_VEX_0F3A16,
1324   PREFIX_VEX_0F3A17,
1325   PREFIX_VEX_0F3A18,
1326   PREFIX_VEX_0F3A19,
1327   PREFIX_VEX_0F3A1D,
1328   PREFIX_VEX_0F3A20,
1329   PREFIX_VEX_0F3A21,
1330   PREFIX_VEX_0F3A22,
1331   PREFIX_VEX_0F3A30,
1332   PREFIX_VEX_0F3A31,
1333   PREFIX_VEX_0F3A32,
1334   PREFIX_VEX_0F3A33,
1335   PREFIX_VEX_0F3A38,
1336   PREFIX_VEX_0F3A39,
1337   PREFIX_VEX_0F3A40,
1338   PREFIX_VEX_0F3A41,
1339   PREFIX_VEX_0F3A42,
1340   PREFIX_VEX_0F3A44,
1341   PREFIX_VEX_0F3A46,
1342   PREFIX_VEX_0F3A48,
1343   PREFIX_VEX_0F3A49,
1344   PREFIX_VEX_0F3A4A,
1345   PREFIX_VEX_0F3A4B,
1346   PREFIX_VEX_0F3A4C,
1347   PREFIX_VEX_0F3A5C,
1348   PREFIX_VEX_0F3A5D,
1349   PREFIX_VEX_0F3A5E,
1350   PREFIX_VEX_0F3A5F,
1351   PREFIX_VEX_0F3A60,
1352   PREFIX_VEX_0F3A61,
1353   PREFIX_VEX_0F3A62,
1354   PREFIX_VEX_0F3A63,
1355   PREFIX_VEX_0F3A68,
1356   PREFIX_VEX_0F3A69,
1357   PREFIX_VEX_0F3A6A,
1358   PREFIX_VEX_0F3A6B,
1359   PREFIX_VEX_0F3A6C,
1360   PREFIX_VEX_0F3A6D,
1361   PREFIX_VEX_0F3A6E,
1362   PREFIX_VEX_0F3A6F,
1363   PREFIX_VEX_0F3A78,
1364   PREFIX_VEX_0F3A79,
1365   PREFIX_VEX_0F3A7A,
1366   PREFIX_VEX_0F3A7B,
1367   PREFIX_VEX_0F3A7C,
1368   PREFIX_VEX_0F3A7D,
1369   PREFIX_VEX_0F3A7E,
1370   PREFIX_VEX_0F3A7F,
1371   PREFIX_VEX_0F3ADF,
1372   PREFIX_VEX_0F3AF0,
1373
1374   PREFIX_EVEX_0F10,
1375   PREFIX_EVEX_0F11,
1376   PREFIX_EVEX_0F12,
1377   PREFIX_EVEX_0F13,
1378   PREFIX_EVEX_0F14,
1379   PREFIX_EVEX_0F15,
1380   PREFIX_EVEX_0F16,
1381   PREFIX_EVEX_0F17,
1382   PREFIX_EVEX_0F28,
1383   PREFIX_EVEX_0F29,
1384   PREFIX_EVEX_0F2A,
1385   PREFIX_EVEX_0F2B,
1386   PREFIX_EVEX_0F2C,
1387   PREFIX_EVEX_0F2D,
1388   PREFIX_EVEX_0F2E,
1389   PREFIX_EVEX_0F2F,
1390   PREFIX_EVEX_0F51,
1391   PREFIX_EVEX_0F54,
1392   PREFIX_EVEX_0F55,
1393   PREFIX_EVEX_0F56,
1394   PREFIX_EVEX_0F57,
1395   PREFIX_EVEX_0F58,
1396   PREFIX_EVEX_0F59,
1397   PREFIX_EVEX_0F5A,
1398   PREFIX_EVEX_0F5B,
1399   PREFIX_EVEX_0F5C,
1400   PREFIX_EVEX_0F5D,
1401   PREFIX_EVEX_0F5E,
1402   PREFIX_EVEX_0F5F,
1403   PREFIX_EVEX_0F60,
1404   PREFIX_EVEX_0F61,
1405   PREFIX_EVEX_0F62,
1406   PREFIX_EVEX_0F63,
1407   PREFIX_EVEX_0F64,
1408   PREFIX_EVEX_0F65,
1409   PREFIX_EVEX_0F66,
1410   PREFIX_EVEX_0F67,
1411   PREFIX_EVEX_0F68,
1412   PREFIX_EVEX_0F69,
1413   PREFIX_EVEX_0F6A,
1414   PREFIX_EVEX_0F6B,
1415   PREFIX_EVEX_0F6C,
1416   PREFIX_EVEX_0F6D,
1417   PREFIX_EVEX_0F6E,
1418   PREFIX_EVEX_0F6F,
1419   PREFIX_EVEX_0F70,
1420   PREFIX_EVEX_0F71_REG_2,
1421   PREFIX_EVEX_0F71_REG_4,
1422   PREFIX_EVEX_0F71_REG_6,
1423   PREFIX_EVEX_0F72_REG_0,
1424   PREFIX_EVEX_0F72_REG_1,
1425   PREFIX_EVEX_0F72_REG_2,
1426   PREFIX_EVEX_0F72_REG_4,
1427   PREFIX_EVEX_0F72_REG_6,
1428   PREFIX_EVEX_0F73_REG_2,
1429   PREFIX_EVEX_0F73_REG_3,
1430   PREFIX_EVEX_0F73_REG_6,
1431   PREFIX_EVEX_0F73_REG_7,
1432   PREFIX_EVEX_0F74,
1433   PREFIX_EVEX_0F75,
1434   PREFIX_EVEX_0F76,
1435   PREFIX_EVEX_0F78,
1436   PREFIX_EVEX_0F79,
1437   PREFIX_EVEX_0F7A,
1438   PREFIX_EVEX_0F7B,
1439   PREFIX_EVEX_0F7E,
1440   PREFIX_EVEX_0F7F,
1441   PREFIX_EVEX_0FC2,
1442   PREFIX_EVEX_0FC4,
1443   PREFIX_EVEX_0FC5,
1444   PREFIX_EVEX_0FC6,
1445   PREFIX_EVEX_0FD1,
1446   PREFIX_EVEX_0FD2,
1447   PREFIX_EVEX_0FD3,
1448   PREFIX_EVEX_0FD4,
1449   PREFIX_EVEX_0FD5,
1450   PREFIX_EVEX_0FD6,
1451   PREFIX_EVEX_0FD8,
1452   PREFIX_EVEX_0FD9,
1453   PREFIX_EVEX_0FDA,
1454   PREFIX_EVEX_0FDB,
1455   PREFIX_EVEX_0FDC,
1456   PREFIX_EVEX_0FDD,
1457   PREFIX_EVEX_0FDE,
1458   PREFIX_EVEX_0FDF,
1459   PREFIX_EVEX_0FE0,
1460   PREFIX_EVEX_0FE1,
1461   PREFIX_EVEX_0FE2,
1462   PREFIX_EVEX_0FE3,
1463   PREFIX_EVEX_0FE4,
1464   PREFIX_EVEX_0FE5,
1465   PREFIX_EVEX_0FE6,
1466   PREFIX_EVEX_0FE7,
1467   PREFIX_EVEX_0FE8,
1468   PREFIX_EVEX_0FE9,
1469   PREFIX_EVEX_0FEA,
1470   PREFIX_EVEX_0FEB,
1471   PREFIX_EVEX_0FEC,
1472   PREFIX_EVEX_0FED,
1473   PREFIX_EVEX_0FEE,
1474   PREFIX_EVEX_0FEF,
1475   PREFIX_EVEX_0FF1,
1476   PREFIX_EVEX_0FF2,
1477   PREFIX_EVEX_0FF3,
1478   PREFIX_EVEX_0FF4,
1479   PREFIX_EVEX_0FF5,
1480   PREFIX_EVEX_0FF6,
1481   PREFIX_EVEX_0FF8,
1482   PREFIX_EVEX_0FF9,
1483   PREFIX_EVEX_0FFA,
1484   PREFIX_EVEX_0FFB,
1485   PREFIX_EVEX_0FFC,
1486   PREFIX_EVEX_0FFD,
1487   PREFIX_EVEX_0FFE,
1488   PREFIX_EVEX_0F3800,
1489   PREFIX_EVEX_0F3804,
1490   PREFIX_EVEX_0F380B,
1491   PREFIX_EVEX_0F380C,
1492   PREFIX_EVEX_0F380D,
1493   PREFIX_EVEX_0F3810,
1494   PREFIX_EVEX_0F3811,
1495   PREFIX_EVEX_0F3812,
1496   PREFIX_EVEX_0F3813,
1497   PREFIX_EVEX_0F3814,
1498   PREFIX_EVEX_0F3815,
1499   PREFIX_EVEX_0F3816,
1500   PREFIX_EVEX_0F3818,
1501   PREFIX_EVEX_0F3819,
1502   PREFIX_EVEX_0F381A,
1503   PREFIX_EVEX_0F381B,
1504   PREFIX_EVEX_0F381C,
1505   PREFIX_EVEX_0F381D,
1506   PREFIX_EVEX_0F381E,
1507   PREFIX_EVEX_0F381F,
1508   PREFIX_EVEX_0F3820,
1509   PREFIX_EVEX_0F3821,
1510   PREFIX_EVEX_0F3822,
1511   PREFIX_EVEX_0F3823,
1512   PREFIX_EVEX_0F3824,
1513   PREFIX_EVEX_0F3825,
1514   PREFIX_EVEX_0F3826,
1515   PREFIX_EVEX_0F3827,
1516   PREFIX_EVEX_0F3828,
1517   PREFIX_EVEX_0F3829,
1518   PREFIX_EVEX_0F382A,
1519   PREFIX_EVEX_0F382B,
1520   PREFIX_EVEX_0F382C,
1521   PREFIX_EVEX_0F382D,
1522   PREFIX_EVEX_0F3830,
1523   PREFIX_EVEX_0F3831,
1524   PREFIX_EVEX_0F3832,
1525   PREFIX_EVEX_0F3833,
1526   PREFIX_EVEX_0F3834,
1527   PREFIX_EVEX_0F3835,
1528   PREFIX_EVEX_0F3836,
1529   PREFIX_EVEX_0F3837,
1530   PREFIX_EVEX_0F3838,
1531   PREFIX_EVEX_0F3839,
1532   PREFIX_EVEX_0F383A,
1533   PREFIX_EVEX_0F383B,
1534   PREFIX_EVEX_0F383C,
1535   PREFIX_EVEX_0F383D,
1536   PREFIX_EVEX_0F383E,
1537   PREFIX_EVEX_0F383F,
1538   PREFIX_EVEX_0F3840,
1539   PREFIX_EVEX_0F3842,
1540   PREFIX_EVEX_0F3843,
1541   PREFIX_EVEX_0F3844,
1542   PREFIX_EVEX_0F3845,
1543   PREFIX_EVEX_0F3846,
1544   PREFIX_EVEX_0F3847,
1545   PREFIX_EVEX_0F384C,
1546   PREFIX_EVEX_0F384D,
1547   PREFIX_EVEX_0F384E,
1548   PREFIX_EVEX_0F384F,
1549   PREFIX_EVEX_0F3852,
1550   PREFIX_EVEX_0F3853,
1551   PREFIX_EVEX_0F3855,
1552   PREFIX_EVEX_0F3858,
1553   PREFIX_EVEX_0F3859,
1554   PREFIX_EVEX_0F385A,
1555   PREFIX_EVEX_0F385B,
1556   PREFIX_EVEX_0F3864,
1557   PREFIX_EVEX_0F3865,
1558   PREFIX_EVEX_0F3866,
1559   PREFIX_EVEX_0F3875,
1560   PREFIX_EVEX_0F3876,
1561   PREFIX_EVEX_0F3877,
1562   PREFIX_EVEX_0F3878,
1563   PREFIX_EVEX_0F3879,
1564   PREFIX_EVEX_0F387A,
1565   PREFIX_EVEX_0F387B,
1566   PREFIX_EVEX_0F387C,
1567   PREFIX_EVEX_0F387D,
1568   PREFIX_EVEX_0F387E,
1569   PREFIX_EVEX_0F387F,
1570   PREFIX_EVEX_0F3883,
1571   PREFIX_EVEX_0F3888,
1572   PREFIX_EVEX_0F3889,
1573   PREFIX_EVEX_0F388A,
1574   PREFIX_EVEX_0F388B,
1575   PREFIX_EVEX_0F388D,
1576   PREFIX_EVEX_0F3890,
1577   PREFIX_EVEX_0F3891,
1578   PREFIX_EVEX_0F3892,
1579   PREFIX_EVEX_0F3893,
1580   PREFIX_EVEX_0F3896,
1581   PREFIX_EVEX_0F3897,
1582   PREFIX_EVEX_0F3898,
1583   PREFIX_EVEX_0F3899,
1584   PREFIX_EVEX_0F389A,
1585   PREFIX_EVEX_0F389B,
1586   PREFIX_EVEX_0F389C,
1587   PREFIX_EVEX_0F389D,
1588   PREFIX_EVEX_0F389E,
1589   PREFIX_EVEX_0F389F,
1590   PREFIX_EVEX_0F38A0,
1591   PREFIX_EVEX_0F38A1,
1592   PREFIX_EVEX_0F38A2,
1593   PREFIX_EVEX_0F38A3,
1594   PREFIX_EVEX_0F38A6,
1595   PREFIX_EVEX_0F38A7,
1596   PREFIX_EVEX_0F38A8,
1597   PREFIX_EVEX_0F38A9,
1598   PREFIX_EVEX_0F38AA,
1599   PREFIX_EVEX_0F38AB,
1600   PREFIX_EVEX_0F38AC,
1601   PREFIX_EVEX_0F38AD,
1602   PREFIX_EVEX_0F38AE,
1603   PREFIX_EVEX_0F38AF,
1604   PREFIX_EVEX_0F38B4,
1605   PREFIX_EVEX_0F38B5,
1606   PREFIX_EVEX_0F38B6,
1607   PREFIX_EVEX_0F38B7,
1608   PREFIX_EVEX_0F38B8,
1609   PREFIX_EVEX_0F38B9,
1610   PREFIX_EVEX_0F38BA,
1611   PREFIX_EVEX_0F38BB,
1612   PREFIX_EVEX_0F38BC,
1613   PREFIX_EVEX_0F38BD,
1614   PREFIX_EVEX_0F38BE,
1615   PREFIX_EVEX_0F38BF,
1616   PREFIX_EVEX_0F38C4,
1617   PREFIX_EVEX_0F38C6_REG_1,
1618   PREFIX_EVEX_0F38C6_REG_2,
1619   PREFIX_EVEX_0F38C6_REG_5,
1620   PREFIX_EVEX_0F38C6_REG_6,
1621   PREFIX_EVEX_0F38C7_REG_1,
1622   PREFIX_EVEX_0F38C7_REG_2,
1623   PREFIX_EVEX_0F38C7_REG_5,
1624   PREFIX_EVEX_0F38C7_REG_6,
1625   PREFIX_EVEX_0F38C8,
1626   PREFIX_EVEX_0F38CA,
1627   PREFIX_EVEX_0F38CB,
1628   PREFIX_EVEX_0F38CC,
1629   PREFIX_EVEX_0F38CD,
1630
1631   PREFIX_EVEX_0F3A00,
1632   PREFIX_EVEX_0F3A01,
1633   PREFIX_EVEX_0F3A03,
1634   PREFIX_EVEX_0F3A04,
1635   PREFIX_EVEX_0F3A05,
1636   PREFIX_EVEX_0F3A08,
1637   PREFIX_EVEX_0F3A09,
1638   PREFIX_EVEX_0F3A0A,
1639   PREFIX_EVEX_0F3A0B,
1640   PREFIX_EVEX_0F3A0F,
1641   PREFIX_EVEX_0F3A14,
1642   PREFIX_EVEX_0F3A15,
1643   PREFIX_EVEX_0F3A16,
1644   PREFIX_EVEX_0F3A17,
1645   PREFIX_EVEX_0F3A18,
1646   PREFIX_EVEX_0F3A19,
1647   PREFIX_EVEX_0F3A1A,
1648   PREFIX_EVEX_0F3A1B,
1649   PREFIX_EVEX_0F3A1D,
1650   PREFIX_EVEX_0F3A1E,
1651   PREFIX_EVEX_0F3A1F,
1652   PREFIX_EVEX_0F3A20,
1653   PREFIX_EVEX_0F3A21,
1654   PREFIX_EVEX_0F3A22,
1655   PREFIX_EVEX_0F3A23,
1656   PREFIX_EVEX_0F3A25,
1657   PREFIX_EVEX_0F3A26,
1658   PREFIX_EVEX_0F3A27,
1659   PREFIX_EVEX_0F3A38,
1660   PREFIX_EVEX_0F3A39,
1661   PREFIX_EVEX_0F3A3A,
1662   PREFIX_EVEX_0F3A3B,
1663   PREFIX_EVEX_0F3A3E,
1664   PREFIX_EVEX_0F3A3F,
1665   PREFIX_EVEX_0F3A42,
1666   PREFIX_EVEX_0F3A43,
1667   PREFIX_EVEX_0F3A50,
1668   PREFIX_EVEX_0F3A51,
1669   PREFIX_EVEX_0F3A54,
1670   PREFIX_EVEX_0F3A55,
1671   PREFIX_EVEX_0F3A56,
1672   PREFIX_EVEX_0F3A57,
1673   PREFIX_EVEX_0F3A66,
1674   PREFIX_EVEX_0F3A67
1675 };
1676
1677 enum
1678 {
1679   X86_64_06 = 0,
1680   X86_64_07,
1681   X86_64_0D,
1682   X86_64_16,
1683   X86_64_17,
1684   X86_64_1E,
1685   X86_64_1F,
1686   X86_64_27,
1687   X86_64_2F,
1688   X86_64_37,
1689   X86_64_3F,
1690   X86_64_60,
1691   X86_64_61,
1692   X86_64_62,
1693   X86_64_63,
1694   X86_64_6D,
1695   X86_64_6F,
1696   X86_64_82,
1697   X86_64_9A,
1698   X86_64_C4,
1699   X86_64_C5,
1700   X86_64_CE,
1701   X86_64_D4,
1702   X86_64_D5,
1703   X86_64_E8,
1704   X86_64_E9,
1705   X86_64_EA,
1706   X86_64_0F01_REG_0,
1707   X86_64_0F01_REG_1,
1708   X86_64_0F01_REG_2,
1709   X86_64_0F01_REG_3
1710 };
1711
1712 enum
1713 {
1714   THREE_BYTE_0F38 = 0,
1715   THREE_BYTE_0F3A
1716 };
1717
1718 enum
1719 {
1720   XOP_08 = 0,
1721   XOP_09,
1722   XOP_0A
1723 };
1724
1725 enum
1726 {
1727   VEX_0F = 0,
1728   VEX_0F38,
1729   VEX_0F3A
1730 };
1731
1732 enum
1733 {
1734   EVEX_0F = 0,
1735   EVEX_0F38,
1736   EVEX_0F3A
1737 };
1738
1739 enum
1740 {
1741   VEX_LEN_0F10_P_1 = 0,
1742   VEX_LEN_0F10_P_3,
1743   VEX_LEN_0F11_P_1,
1744   VEX_LEN_0F11_P_3,
1745   VEX_LEN_0F12_P_0_M_0,
1746   VEX_LEN_0F12_P_0_M_1,
1747   VEX_LEN_0F12_P_2,
1748   VEX_LEN_0F13_M_0,
1749   VEX_LEN_0F16_P_0_M_0,
1750   VEX_LEN_0F16_P_0_M_1,
1751   VEX_LEN_0F16_P_2,
1752   VEX_LEN_0F17_M_0,
1753   VEX_LEN_0F2A_P_1,
1754   VEX_LEN_0F2A_P_3,
1755   VEX_LEN_0F2C_P_1,
1756   VEX_LEN_0F2C_P_3,
1757   VEX_LEN_0F2D_P_1,
1758   VEX_LEN_0F2D_P_3,
1759   VEX_LEN_0F2E_P_0,
1760   VEX_LEN_0F2E_P_2,
1761   VEX_LEN_0F2F_P_0,
1762   VEX_LEN_0F2F_P_2,
1763   VEX_LEN_0F41_P_0,
1764   VEX_LEN_0F41_P_2,
1765   VEX_LEN_0F42_P_0,
1766   VEX_LEN_0F42_P_2,
1767   VEX_LEN_0F44_P_0,
1768   VEX_LEN_0F44_P_2,
1769   VEX_LEN_0F45_P_0,
1770   VEX_LEN_0F45_P_2,
1771   VEX_LEN_0F46_P_0,
1772   VEX_LEN_0F46_P_2,
1773   VEX_LEN_0F47_P_0,
1774   VEX_LEN_0F47_P_2,
1775   VEX_LEN_0F4A_P_0,
1776   VEX_LEN_0F4A_P_2,
1777   VEX_LEN_0F4B_P_0,
1778   VEX_LEN_0F4B_P_2,
1779   VEX_LEN_0F51_P_1,
1780   VEX_LEN_0F51_P_3,
1781   VEX_LEN_0F52_P_1,
1782   VEX_LEN_0F53_P_1,
1783   VEX_LEN_0F58_P_1,
1784   VEX_LEN_0F58_P_3,
1785   VEX_LEN_0F59_P_1,
1786   VEX_LEN_0F59_P_3,
1787   VEX_LEN_0F5A_P_1,
1788   VEX_LEN_0F5A_P_3,
1789   VEX_LEN_0F5C_P_1,
1790   VEX_LEN_0F5C_P_3,
1791   VEX_LEN_0F5D_P_1,
1792   VEX_LEN_0F5D_P_3,
1793   VEX_LEN_0F5E_P_1,
1794   VEX_LEN_0F5E_P_3,
1795   VEX_LEN_0F5F_P_1,
1796   VEX_LEN_0F5F_P_3,
1797   VEX_LEN_0F6E_P_2,
1798   VEX_LEN_0F7E_P_1,
1799   VEX_LEN_0F7E_P_2,
1800   VEX_LEN_0F90_P_0,
1801   VEX_LEN_0F90_P_2,
1802   VEX_LEN_0F91_P_0,
1803   VEX_LEN_0F91_P_2,
1804   VEX_LEN_0F92_P_0,
1805   VEX_LEN_0F92_P_2,
1806   VEX_LEN_0F92_P_3,
1807   VEX_LEN_0F93_P_0,
1808   VEX_LEN_0F93_P_2,
1809   VEX_LEN_0F93_P_3,
1810   VEX_LEN_0F98_P_0,
1811   VEX_LEN_0F98_P_2,
1812   VEX_LEN_0F99_P_0,
1813   VEX_LEN_0F99_P_2,
1814   VEX_LEN_0FAE_R_2_M_0,
1815   VEX_LEN_0FAE_R_3_M_0,
1816   VEX_LEN_0FC2_P_1,
1817   VEX_LEN_0FC2_P_3,
1818   VEX_LEN_0FC4_P_2,
1819   VEX_LEN_0FC5_P_2,
1820   VEX_LEN_0FD6_P_2,
1821   VEX_LEN_0FF7_P_2,
1822   VEX_LEN_0F3816_P_2,
1823   VEX_LEN_0F3819_P_2,
1824   VEX_LEN_0F381A_P_2_M_0,
1825   VEX_LEN_0F3836_P_2,
1826   VEX_LEN_0F3841_P_2,
1827   VEX_LEN_0F385A_P_2_M_0,
1828   VEX_LEN_0F38DB_P_2,
1829   VEX_LEN_0F38DC_P_2,
1830   VEX_LEN_0F38DD_P_2,
1831   VEX_LEN_0F38DE_P_2,
1832   VEX_LEN_0F38DF_P_2,
1833   VEX_LEN_0F38F2_P_0,
1834   VEX_LEN_0F38F3_R_1_P_0,
1835   VEX_LEN_0F38F3_R_2_P_0,
1836   VEX_LEN_0F38F3_R_3_P_0,
1837   VEX_LEN_0F38F5_P_0,
1838   VEX_LEN_0F38F5_P_1,
1839   VEX_LEN_0F38F5_P_3,
1840   VEX_LEN_0F38F6_P_3,
1841   VEX_LEN_0F38F7_P_0,
1842   VEX_LEN_0F38F7_P_1,
1843   VEX_LEN_0F38F7_P_2,
1844   VEX_LEN_0F38F7_P_3,
1845   VEX_LEN_0F3A00_P_2,
1846   VEX_LEN_0F3A01_P_2,
1847   VEX_LEN_0F3A06_P_2,
1848   VEX_LEN_0F3A0A_P_2,
1849   VEX_LEN_0F3A0B_P_2,
1850   VEX_LEN_0F3A14_P_2,
1851   VEX_LEN_0F3A15_P_2,
1852   VEX_LEN_0F3A16_P_2,
1853   VEX_LEN_0F3A17_P_2,
1854   VEX_LEN_0F3A18_P_2,
1855   VEX_LEN_0F3A19_P_2,
1856   VEX_LEN_0F3A20_P_2,
1857   VEX_LEN_0F3A21_P_2,
1858   VEX_LEN_0F3A22_P_2,
1859   VEX_LEN_0F3A30_P_2,
1860   VEX_LEN_0F3A31_P_2,
1861   VEX_LEN_0F3A32_P_2,
1862   VEX_LEN_0F3A33_P_2,
1863   VEX_LEN_0F3A38_P_2,
1864   VEX_LEN_0F3A39_P_2,
1865   VEX_LEN_0F3A41_P_2,
1866   VEX_LEN_0F3A44_P_2,
1867   VEX_LEN_0F3A46_P_2,
1868   VEX_LEN_0F3A60_P_2,
1869   VEX_LEN_0F3A61_P_2,
1870   VEX_LEN_0F3A62_P_2,
1871   VEX_LEN_0F3A63_P_2,
1872   VEX_LEN_0F3A6A_P_2,
1873   VEX_LEN_0F3A6B_P_2,
1874   VEX_LEN_0F3A6E_P_2,
1875   VEX_LEN_0F3A6F_P_2,
1876   VEX_LEN_0F3A7A_P_2,
1877   VEX_LEN_0F3A7B_P_2,
1878   VEX_LEN_0F3A7E_P_2,
1879   VEX_LEN_0F3A7F_P_2,
1880   VEX_LEN_0F3ADF_P_2,
1881   VEX_LEN_0F3AF0_P_3,
1882   VEX_LEN_0FXOP_08_CC,
1883   VEX_LEN_0FXOP_08_CD,
1884   VEX_LEN_0FXOP_08_CE,
1885   VEX_LEN_0FXOP_08_CF,
1886   VEX_LEN_0FXOP_08_EC,
1887   VEX_LEN_0FXOP_08_ED,
1888   VEX_LEN_0FXOP_08_EE,
1889   VEX_LEN_0FXOP_08_EF,
1890   VEX_LEN_0FXOP_09_80,
1891   VEX_LEN_0FXOP_09_81
1892 };
1893
1894 enum
1895 {
1896   VEX_W_0F10_P_0 = 0,
1897   VEX_W_0F10_P_1,
1898   VEX_W_0F10_P_2,
1899   VEX_W_0F10_P_3,
1900   VEX_W_0F11_P_0,
1901   VEX_W_0F11_P_1,
1902   VEX_W_0F11_P_2,
1903   VEX_W_0F11_P_3,
1904   VEX_W_0F12_P_0_M_0,
1905   VEX_W_0F12_P_0_M_1,
1906   VEX_W_0F12_P_1,
1907   VEX_W_0F12_P_2,
1908   VEX_W_0F12_P_3,
1909   VEX_W_0F13_M_0,
1910   VEX_W_0F14,
1911   VEX_W_0F15,
1912   VEX_W_0F16_P_0_M_0,
1913   VEX_W_0F16_P_0_M_1,
1914   VEX_W_0F16_P_1,
1915   VEX_W_0F16_P_2,
1916   VEX_W_0F17_M_0,
1917   VEX_W_0F28,
1918   VEX_W_0F29,
1919   VEX_W_0F2B_M_0,
1920   VEX_W_0F2E_P_0,
1921   VEX_W_0F2E_P_2,
1922   VEX_W_0F2F_P_0,
1923   VEX_W_0F2F_P_2,
1924   VEX_W_0F41_P_0_LEN_1,
1925   VEX_W_0F41_P_2_LEN_1,
1926   VEX_W_0F42_P_0_LEN_1,
1927   VEX_W_0F42_P_2_LEN_1,
1928   VEX_W_0F44_P_0_LEN_0,
1929   VEX_W_0F44_P_2_LEN_0,
1930   VEX_W_0F45_P_0_LEN_1,
1931   VEX_W_0F45_P_2_LEN_1,
1932   VEX_W_0F46_P_0_LEN_1,
1933   VEX_W_0F46_P_2_LEN_1,
1934   VEX_W_0F47_P_0_LEN_1,
1935   VEX_W_0F47_P_2_LEN_1,
1936   VEX_W_0F4A_P_0_LEN_1,
1937   VEX_W_0F4A_P_2_LEN_1,
1938   VEX_W_0F4B_P_0_LEN_1,
1939   VEX_W_0F4B_P_2_LEN_1,
1940   VEX_W_0F50_M_0,
1941   VEX_W_0F51_P_0,
1942   VEX_W_0F51_P_1,
1943   VEX_W_0F51_P_2,
1944   VEX_W_0F51_P_3,
1945   VEX_W_0F52_P_0,
1946   VEX_W_0F52_P_1,
1947   VEX_W_0F53_P_0,
1948   VEX_W_0F53_P_1,
1949   VEX_W_0F58_P_0,
1950   VEX_W_0F58_P_1,
1951   VEX_W_0F58_P_2,
1952   VEX_W_0F58_P_3,
1953   VEX_W_0F59_P_0,
1954   VEX_W_0F59_P_1,
1955   VEX_W_0F59_P_2,
1956   VEX_W_0F59_P_3,
1957   VEX_W_0F5A_P_0,
1958   VEX_W_0F5A_P_1,
1959   VEX_W_0F5A_P_3,
1960   VEX_W_0F5B_P_0,
1961   VEX_W_0F5B_P_1,
1962   VEX_W_0F5B_P_2,
1963   VEX_W_0F5C_P_0,
1964   VEX_W_0F5C_P_1,
1965   VEX_W_0F5C_P_2,
1966   VEX_W_0F5C_P_3,
1967   VEX_W_0F5D_P_0,
1968   VEX_W_0F5D_P_1,
1969   VEX_W_0F5D_P_2,
1970   VEX_W_0F5D_P_3,
1971   VEX_W_0F5E_P_0,
1972   VEX_W_0F5E_P_1,
1973   VEX_W_0F5E_P_2,
1974   VEX_W_0F5E_P_3,
1975   VEX_W_0F5F_P_0,
1976   VEX_W_0F5F_P_1,
1977   VEX_W_0F5F_P_2,
1978   VEX_W_0F5F_P_3,
1979   VEX_W_0F60_P_2,
1980   VEX_W_0F61_P_2,
1981   VEX_W_0F62_P_2,
1982   VEX_W_0F63_P_2,
1983   VEX_W_0F64_P_2,
1984   VEX_W_0F65_P_2,
1985   VEX_W_0F66_P_2,
1986   VEX_W_0F67_P_2,
1987   VEX_W_0F68_P_2,
1988   VEX_W_0F69_P_2,
1989   VEX_W_0F6A_P_2,
1990   VEX_W_0F6B_P_2,
1991   VEX_W_0F6C_P_2,
1992   VEX_W_0F6D_P_2,
1993   VEX_W_0F6F_P_1,
1994   VEX_W_0F6F_P_2,
1995   VEX_W_0F70_P_1,
1996   VEX_W_0F70_P_2,
1997   VEX_W_0F70_P_3,
1998   VEX_W_0F71_R_2_P_2,
1999   VEX_W_0F71_R_4_P_2,
2000   VEX_W_0F71_R_6_P_2,
2001   VEX_W_0F72_R_2_P_2,
2002   VEX_W_0F72_R_4_P_2,
2003   VEX_W_0F72_R_6_P_2,
2004   VEX_W_0F73_R_2_P_2,
2005   VEX_W_0F73_R_3_P_2,
2006   VEX_W_0F73_R_6_P_2,
2007   VEX_W_0F73_R_7_P_2,
2008   VEX_W_0F74_P_2,
2009   VEX_W_0F75_P_2,
2010   VEX_W_0F76_P_2,
2011   VEX_W_0F77_P_0,
2012   VEX_W_0F7C_P_2,
2013   VEX_W_0F7C_P_3,
2014   VEX_W_0F7D_P_2,
2015   VEX_W_0F7D_P_3,
2016   VEX_W_0F7E_P_1,
2017   VEX_W_0F7F_P_1,
2018   VEX_W_0F7F_P_2,
2019   VEX_W_0F90_P_0_LEN_0,
2020   VEX_W_0F90_P_2_LEN_0,
2021   VEX_W_0F91_P_0_LEN_0,
2022   VEX_W_0F91_P_2_LEN_0,
2023   VEX_W_0F92_P_0_LEN_0,
2024   VEX_W_0F92_P_2_LEN_0,
2025   VEX_W_0F92_P_3_LEN_0,
2026   VEX_W_0F93_P_0_LEN_0,
2027   VEX_W_0F93_P_2_LEN_0,
2028   VEX_W_0F93_P_3_LEN_0,
2029   VEX_W_0F98_P_0_LEN_0,
2030   VEX_W_0F98_P_2_LEN_0,
2031   VEX_W_0F99_P_0_LEN_0,
2032   VEX_W_0F99_P_2_LEN_0,
2033   VEX_W_0FAE_R_2_M_0,
2034   VEX_W_0FAE_R_3_M_0,
2035   VEX_W_0FC2_P_0,
2036   VEX_W_0FC2_P_1,
2037   VEX_W_0FC2_P_2,
2038   VEX_W_0FC2_P_3,
2039   VEX_W_0FC4_P_2,
2040   VEX_W_0FC5_P_2,
2041   VEX_W_0FD0_P_2,
2042   VEX_W_0FD0_P_3,
2043   VEX_W_0FD1_P_2,
2044   VEX_W_0FD2_P_2,
2045   VEX_W_0FD3_P_2,
2046   VEX_W_0FD4_P_2,
2047   VEX_W_0FD5_P_2,
2048   VEX_W_0FD6_P_2,
2049   VEX_W_0FD7_P_2_M_1,
2050   VEX_W_0FD8_P_2,
2051   VEX_W_0FD9_P_2,
2052   VEX_W_0FDA_P_2,
2053   VEX_W_0FDB_P_2,
2054   VEX_W_0FDC_P_2,
2055   VEX_W_0FDD_P_2,
2056   VEX_W_0FDE_P_2,
2057   VEX_W_0FDF_P_2,
2058   VEX_W_0FE0_P_2,
2059   VEX_W_0FE1_P_2,
2060   VEX_W_0FE2_P_2,
2061   VEX_W_0FE3_P_2,
2062   VEX_W_0FE4_P_2,
2063   VEX_W_0FE5_P_2,
2064   VEX_W_0FE6_P_1,
2065   VEX_W_0FE6_P_2,
2066   VEX_W_0FE6_P_3,
2067   VEX_W_0FE7_P_2_M_0,
2068   VEX_W_0FE8_P_2,
2069   VEX_W_0FE9_P_2,
2070   VEX_W_0FEA_P_2,
2071   VEX_W_0FEB_P_2,
2072   VEX_W_0FEC_P_2,
2073   VEX_W_0FED_P_2,
2074   VEX_W_0FEE_P_2,
2075   VEX_W_0FEF_P_2,
2076   VEX_W_0FF0_P_3_M_0,
2077   VEX_W_0FF1_P_2,
2078   VEX_W_0FF2_P_2,
2079   VEX_W_0FF3_P_2,
2080   VEX_W_0FF4_P_2,
2081   VEX_W_0FF5_P_2,
2082   VEX_W_0FF6_P_2,
2083   VEX_W_0FF7_P_2,
2084   VEX_W_0FF8_P_2,
2085   VEX_W_0FF9_P_2,
2086   VEX_W_0FFA_P_2,
2087   VEX_W_0FFB_P_2,
2088   VEX_W_0FFC_P_2,
2089   VEX_W_0FFD_P_2,
2090   VEX_W_0FFE_P_2,
2091   VEX_W_0F3800_P_2,
2092   VEX_W_0F3801_P_2,
2093   VEX_W_0F3802_P_2,
2094   VEX_W_0F3803_P_2,
2095   VEX_W_0F3804_P_2,
2096   VEX_W_0F3805_P_2,
2097   VEX_W_0F3806_P_2,
2098   VEX_W_0F3807_P_2,
2099   VEX_W_0F3808_P_2,
2100   VEX_W_0F3809_P_2,
2101   VEX_W_0F380A_P_2,
2102   VEX_W_0F380B_P_2,
2103   VEX_W_0F380C_P_2,
2104   VEX_W_0F380D_P_2,
2105   VEX_W_0F380E_P_2,
2106   VEX_W_0F380F_P_2,
2107   VEX_W_0F3816_P_2,
2108   VEX_W_0F3817_P_2,
2109   VEX_W_0F3818_P_2,
2110   VEX_W_0F3819_P_2,
2111   VEX_W_0F381A_P_2_M_0,
2112   VEX_W_0F381C_P_2,
2113   VEX_W_0F381D_P_2,
2114   VEX_W_0F381E_P_2,
2115   VEX_W_0F3820_P_2,
2116   VEX_W_0F3821_P_2,
2117   VEX_W_0F3822_P_2,
2118   VEX_W_0F3823_P_2,
2119   VEX_W_0F3824_P_2,
2120   VEX_W_0F3825_P_2,
2121   VEX_W_0F3828_P_2,
2122   VEX_W_0F3829_P_2,
2123   VEX_W_0F382A_P_2_M_0,
2124   VEX_W_0F382B_P_2,
2125   VEX_W_0F382C_P_2_M_0,
2126   VEX_W_0F382D_P_2_M_0,
2127   VEX_W_0F382E_P_2_M_0,
2128   VEX_W_0F382F_P_2_M_0,
2129   VEX_W_0F3830_P_2,
2130   VEX_W_0F3831_P_2,
2131   VEX_W_0F3832_P_2,
2132   VEX_W_0F3833_P_2,
2133   VEX_W_0F3834_P_2,
2134   VEX_W_0F3835_P_2,
2135   VEX_W_0F3836_P_2,
2136   VEX_W_0F3837_P_2,
2137   VEX_W_0F3838_P_2,
2138   VEX_W_0F3839_P_2,
2139   VEX_W_0F383A_P_2,
2140   VEX_W_0F383B_P_2,
2141   VEX_W_0F383C_P_2,
2142   VEX_W_0F383D_P_2,
2143   VEX_W_0F383E_P_2,
2144   VEX_W_0F383F_P_2,
2145   VEX_W_0F3840_P_2,
2146   VEX_W_0F3841_P_2,
2147   VEX_W_0F3846_P_2,
2148   VEX_W_0F3858_P_2,
2149   VEX_W_0F3859_P_2,
2150   VEX_W_0F385A_P_2_M_0,
2151   VEX_W_0F3878_P_2,
2152   VEX_W_0F3879_P_2,
2153   VEX_W_0F38DB_P_2,
2154   VEX_W_0F38DC_P_2,
2155   VEX_W_0F38DD_P_2,
2156   VEX_W_0F38DE_P_2,
2157   VEX_W_0F38DF_P_2,
2158   VEX_W_0F3A00_P_2,
2159   VEX_W_0F3A01_P_2,
2160   VEX_W_0F3A02_P_2,
2161   VEX_W_0F3A04_P_2,
2162   VEX_W_0F3A05_P_2,
2163   VEX_W_0F3A06_P_2,
2164   VEX_W_0F3A08_P_2,
2165   VEX_W_0F3A09_P_2,
2166   VEX_W_0F3A0A_P_2,
2167   VEX_W_0F3A0B_P_2,
2168   VEX_W_0F3A0C_P_2,
2169   VEX_W_0F3A0D_P_2,
2170   VEX_W_0F3A0E_P_2,
2171   VEX_W_0F3A0F_P_2,
2172   VEX_W_0F3A14_P_2,
2173   VEX_W_0F3A15_P_2,
2174   VEX_W_0F3A18_P_2,
2175   VEX_W_0F3A19_P_2,
2176   VEX_W_0F3A20_P_2,
2177   VEX_W_0F3A21_P_2,
2178   VEX_W_0F3A30_P_2_LEN_0,
2179   VEX_W_0F3A31_P_2_LEN_0,
2180   VEX_W_0F3A32_P_2_LEN_0,
2181   VEX_W_0F3A33_P_2_LEN_0,
2182   VEX_W_0F3A38_P_2,
2183   VEX_W_0F3A39_P_2,
2184   VEX_W_0F3A40_P_2,
2185   VEX_W_0F3A41_P_2,
2186   VEX_W_0F3A42_P_2,
2187   VEX_W_0F3A44_P_2,
2188   VEX_W_0F3A46_P_2,
2189   VEX_W_0F3A48_P_2,
2190   VEX_W_0F3A49_P_2,
2191   VEX_W_0F3A4A_P_2,
2192   VEX_W_0F3A4B_P_2,
2193   VEX_W_0F3A4C_P_2,
2194   VEX_W_0F3A60_P_2,
2195   VEX_W_0F3A61_P_2,
2196   VEX_W_0F3A62_P_2,
2197   VEX_W_0F3A63_P_2,
2198   VEX_W_0F3ADF_P_2,
2199
2200   EVEX_W_0F10_P_0,
2201   EVEX_W_0F10_P_1_M_0,
2202   EVEX_W_0F10_P_1_M_1,
2203   EVEX_W_0F10_P_2,
2204   EVEX_W_0F10_P_3_M_0,
2205   EVEX_W_0F10_P_3_M_1,
2206   EVEX_W_0F11_P_0,
2207   EVEX_W_0F11_P_1_M_0,
2208   EVEX_W_0F11_P_1_M_1,
2209   EVEX_W_0F11_P_2,
2210   EVEX_W_0F11_P_3_M_0,
2211   EVEX_W_0F11_P_3_M_1,
2212   EVEX_W_0F12_P_0_M_0,
2213   EVEX_W_0F12_P_0_M_1,
2214   EVEX_W_0F12_P_1,
2215   EVEX_W_0F12_P_2,
2216   EVEX_W_0F12_P_3,
2217   EVEX_W_0F13_P_0,
2218   EVEX_W_0F13_P_2,
2219   EVEX_W_0F14_P_0,
2220   EVEX_W_0F14_P_2,
2221   EVEX_W_0F15_P_0,
2222   EVEX_W_0F15_P_2,
2223   EVEX_W_0F16_P_0_M_0,
2224   EVEX_W_0F16_P_0_M_1,
2225   EVEX_W_0F16_P_1,
2226   EVEX_W_0F16_P_2,
2227   EVEX_W_0F17_P_0,
2228   EVEX_W_0F17_P_2,
2229   EVEX_W_0F28_P_0,
2230   EVEX_W_0F28_P_2,
2231   EVEX_W_0F29_P_0,
2232   EVEX_W_0F29_P_2,
2233   EVEX_W_0F2A_P_1,
2234   EVEX_W_0F2A_P_3,
2235   EVEX_W_0F2B_P_0,
2236   EVEX_W_0F2B_P_2,
2237   EVEX_W_0F2E_P_0,
2238   EVEX_W_0F2E_P_2,
2239   EVEX_W_0F2F_P_0,
2240   EVEX_W_0F2F_P_2,
2241   EVEX_W_0F51_P_0,
2242   EVEX_W_0F51_P_1,
2243   EVEX_W_0F51_P_2,
2244   EVEX_W_0F51_P_3,
2245   EVEX_W_0F54_P_0,
2246   EVEX_W_0F54_P_2,
2247   EVEX_W_0F55_P_0,
2248   EVEX_W_0F55_P_2,
2249   EVEX_W_0F56_P_0,
2250   EVEX_W_0F56_P_2,
2251   EVEX_W_0F57_P_0,
2252   EVEX_W_0F57_P_2,
2253   EVEX_W_0F58_P_0,
2254   EVEX_W_0F58_P_1,
2255   EVEX_W_0F58_P_2,
2256   EVEX_W_0F58_P_3,
2257   EVEX_W_0F59_P_0,
2258   EVEX_W_0F59_P_1,
2259   EVEX_W_0F59_P_2,
2260   EVEX_W_0F59_P_3,
2261   EVEX_W_0F5A_P_0,
2262   EVEX_W_0F5A_P_1,
2263   EVEX_W_0F5A_P_2,
2264   EVEX_W_0F5A_P_3,
2265   EVEX_W_0F5B_P_0,
2266   EVEX_W_0F5B_P_1,
2267   EVEX_W_0F5B_P_2,
2268   EVEX_W_0F5C_P_0,
2269   EVEX_W_0F5C_P_1,
2270   EVEX_W_0F5C_P_2,
2271   EVEX_W_0F5C_P_3,
2272   EVEX_W_0F5D_P_0,
2273   EVEX_W_0F5D_P_1,
2274   EVEX_W_0F5D_P_2,
2275   EVEX_W_0F5D_P_3,
2276   EVEX_W_0F5E_P_0,
2277   EVEX_W_0F5E_P_1,
2278   EVEX_W_0F5E_P_2,
2279   EVEX_W_0F5E_P_3,
2280   EVEX_W_0F5F_P_0,
2281   EVEX_W_0F5F_P_1,
2282   EVEX_W_0F5F_P_2,
2283   EVEX_W_0F5F_P_3,
2284   EVEX_W_0F62_P_2,
2285   EVEX_W_0F66_P_2,
2286   EVEX_W_0F6A_P_2,
2287   EVEX_W_0F6B_P_2,
2288   EVEX_W_0F6C_P_2,
2289   EVEX_W_0F6D_P_2,
2290   EVEX_W_0F6E_P_2,
2291   EVEX_W_0F6F_P_1,
2292   EVEX_W_0F6F_P_2,
2293   EVEX_W_0F6F_P_3,
2294   EVEX_W_0F70_P_2,
2295   EVEX_W_0F72_R_2_P_2,
2296   EVEX_W_0F72_R_6_P_2,
2297   EVEX_W_0F73_R_2_P_2,
2298   EVEX_W_0F73_R_6_P_2,
2299   EVEX_W_0F76_P_2,
2300   EVEX_W_0F78_P_0,
2301   EVEX_W_0F78_P_2,
2302   EVEX_W_0F79_P_0,
2303   EVEX_W_0F79_P_2,
2304   EVEX_W_0F7A_P_1,
2305   EVEX_W_0F7A_P_2,
2306   EVEX_W_0F7A_P_3,
2307   EVEX_W_0F7B_P_1,
2308   EVEX_W_0F7B_P_2,
2309   EVEX_W_0F7B_P_3,
2310   EVEX_W_0F7E_P_1,
2311   EVEX_W_0F7E_P_2,
2312   EVEX_W_0F7F_P_1,
2313   EVEX_W_0F7F_P_2,
2314   EVEX_W_0F7F_P_3,
2315   EVEX_W_0FC2_P_0,
2316   EVEX_W_0FC2_P_1,
2317   EVEX_W_0FC2_P_2,
2318   EVEX_W_0FC2_P_3,
2319   EVEX_W_0FC6_P_0,
2320   EVEX_W_0FC6_P_2,
2321   EVEX_W_0FD2_P_2,
2322   EVEX_W_0FD3_P_2,
2323   EVEX_W_0FD4_P_2,
2324   EVEX_W_0FD6_P_2,
2325   EVEX_W_0FE6_P_1,
2326   EVEX_W_0FE6_P_2,
2327   EVEX_W_0FE6_P_3,
2328   EVEX_W_0FE7_P_2,
2329   EVEX_W_0FF2_P_2,
2330   EVEX_W_0FF3_P_2,
2331   EVEX_W_0FF4_P_2,
2332   EVEX_W_0FFA_P_2,
2333   EVEX_W_0FFB_P_2,
2334   EVEX_W_0FFE_P_2,
2335   EVEX_W_0F380C_P_2,
2336   EVEX_W_0F380D_P_2,
2337   EVEX_W_0F3810_P_1,
2338   EVEX_W_0F3810_P_2,
2339   EVEX_W_0F3811_P_1,
2340   EVEX_W_0F3811_P_2,
2341   EVEX_W_0F3812_P_1,
2342   EVEX_W_0F3812_P_2,
2343   EVEX_W_0F3813_P_1,
2344   EVEX_W_0F3813_P_2,
2345   EVEX_W_0F3814_P_1,
2346   EVEX_W_0F3815_P_1,
2347   EVEX_W_0F3818_P_2,
2348   EVEX_W_0F3819_P_2,
2349   EVEX_W_0F381A_P_2,
2350   EVEX_W_0F381B_P_2,
2351   EVEX_W_0F381E_P_2,
2352   EVEX_W_0F381F_P_2,
2353   EVEX_W_0F3820_P_1,
2354   EVEX_W_0F3821_P_1,
2355   EVEX_W_0F3822_P_1,
2356   EVEX_W_0F3823_P_1,
2357   EVEX_W_0F3824_P_1,
2358   EVEX_W_0F3825_P_1,
2359   EVEX_W_0F3825_P_2,
2360   EVEX_W_0F3826_P_1,
2361   EVEX_W_0F3826_P_2,
2362   EVEX_W_0F3828_P_1,
2363   EVEX_W_0F3828_P_2,
2364   EVEX_W_0F3829_P_1,
2365   EVEX_W_0F3829_P_2,
2366   EVEX_W_0F382A_P_1,
2367   EVEX_W_0F382A_P_2,
2368   EVEX_W_0F382B_P_2,
2369   EVEX_W_0F3830_P_1,
2370   EVEX_W_0F3831_P_1,
2371   EVEX_W_0F3832_P_1,
2372   EVEX_W_0F3833_P_1,
2373   EVEX_W_0F3834_P_1,
2374   EVEX_W_0F3835_P_1,
2375   EVEX_W_0F3835_P_2,
2376   EVEX_W_0F3837_P_2,
2377   EVEX_W_0F3838_P_1,
2378   EVEX_W_0F3839_P_1,
2379   EVEX_W_0F383A_P_1,
2380   EVEX_W_0F3840_P_2,
2381   EVEX_W_0F3855_P_2,
2382   EVEX_W_0F3858_P_2,
2383   EVEX_W_0F3859_P_2,
2384   EVEX_W_0F385A_P_2,
2385   EVEX_W_0F385B_P_2,
2386   EVEX_W_0F3866_P_2,
2387   EVEX_W_0F3875_P_2,
2388   EVEX_W_0F3878_P_2,
2389   EVEX_W_0F3879_P_2,
2390   EVEX_W_0F387A_P_2,
2391   EVEX_W_0F387B_P_2,
2392   EVEX_W_0F387D_P_2,
2393   EVEX_W_0F3883_P_2,
2394   EVEX_W_0F388D_P_2,
2395   EVEX_W_0F3891_P_2,
2396   EVEX_W_0F3893_P_2,
2397   EVEX_W_0F38A1_P_2,
2398   EVEX_W_0F38A3_P_2,
2399   EVEX_W_0F38C7_R_1_P_2,
2400   EVEX_W_0F38C7_R_2_P_2,
2401   EVEX_W_0F38C7_R_5_P_2,
2402   EVEX_W_0F38C7_R_6_P_2,
2403
2404   EVEX_W_0F3A00_P_2,
2405   EVEX_W_0F3A01_P_2,
2406   EVEX_W_0F3A04_P_2,
2407   EVEX_W_0F3A05_P_2,
2408   EVEX_W_0F3A08_P_2,
2409   EVEX_W_0F3A09_P_2,
2410   EVEX_W_0F3A0A_P_2,
2411   EVEX_W_0F3A0B_P_2,
2412   EVEX_W_0F3A16_P_2,
2413   EVEX_W_0F3A18_P_2,
2414   EVEX_W_0F3A19_P_2,
2415   EVEX_W_0F3A1A_P_2,
2416   EVEX_W_0F3A1B_P_2,
2417   EVEX_W_0F3A1D_P_2,
2418   EVEX_W_0F3A21_P_2,
2419   EVEX_W_0F3A22_P_2,
2420   EVEX_W_0F3A23_P_2,
2421   EVEX_W_0F3A38_P_2,
2422   EVEX_W_0F3A39_P_2,
2423   EVEX_W_0F3A3A_P_2,
2424   EVEX_W_0F3A3B_P_2,
2425   EVEX_W_0F3A3E_P_2,
2426   EVEX_W_0F3A3F_P_2,
2427   EVEX_W_0F3A42_P_2,
2428   EVEX_W_0F3A43_P_2,
2429   EVEX_W_0F3A50_P_2,
2430   EVEX_W_0F3A51_P_2,
2431   EVEX_W_0F3A56_P_2,
2432   EVEX_W_0F3A57_P_2,
2433   EVEX_W_0F3A66_P_2,
2434   EVEX_W_0F3A67_P_2
2435 };
2436
2437 typedef void (*op_rtn) (int bytemode, int sizeflag);
2438
2439 struct dis386 {
2440   const char *name;
2441   struct
2442     {
2443       op_rtn rtn;
2444       int bytemode;
2445     } op[MAX_OPERANDS];
2446   unsigned int prefix_requirement;
2447 };
2448
2449 /* Upper case letters in the instruction names here are macros.
2450    'A' => print 'b' if no register operands or suffix_always is true
2451    'B' => print 'b' if suffix_always is true
2452    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2453           size prefix
2454    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2455           suffix_always is true
2456    'E' => print 'e' if 32-bit form of jcxz
2457    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2458    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2459    'H' => print ",pt" or ",pn" branch hint
2460    'I' => honor following macro letter even in Intel mode (implemented only
2461           for some of the macro letters)
2462    'J' => print 'l'
2463    'K' => print 'd' or 'q' if rex prefix is present.
2464    'L' => print 'l' if suffix_always is true
2465    'M' => print 'r' if intel_mnemonic is false.
2466    'N' => print 'n' if instruction has no wait "prefix"
2467    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2468    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2469           or suffix_always is true.  print 'q' if rex prefix is present.
2470    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2471           is true
2472    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2473    'S' => print 'w', 'l' or 'q' if suffix_always is true
2474    'T' => print 'q' in 64bit mode if instruction has no operand size
2475           prefix and behave as 'P' otherwise
2476    'U' => print 'q' in 64bit mode if instruction has no operand size
2477           prefix and behave as 'Q' otherwise
2478    'V' => print 'q' in 64bit mode if instruction has no operand size
2479           prefix and behave as 'S' otherwise
2480    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2481    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2482    'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2483           suffix_always is true.
2484    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2485    '!' => change condition from true to false or from false to true.
2486    '%' => add 1 upper case letter to the macro.
2487    '^' => print 'w' or 'l' depending on operand size prefix or
2488           suffix_always is true (lcall/ljmp).
2489    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2490           on operand size prefix.
2491    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2492           has no operand size prefix for AMD64 ISA, behave as 'P'
2493           otherwise
2494
2495    2 upper case letter macros:
2496    "XY" => print 'x' or 'y' if suffix_always is true or no register
2497            operands and no broadcast.
2498    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2499            register operands and no broadcast.
2500    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2501    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2502            or suffix_always is true
2503    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2504    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2505    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2506    "LW" => print 'd', 'q' depending on the VEX.W bit
2507    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2508            an operand size prefix, or suffix_always is true.  print
2509            'q' if rex prefix is present.
2510
2511    Many of the above letters print nothing in Intel mode.  See "putop"
2512    for the details.
2513
2514    Braces '{' and '}', and vertical bars '|', indicate alternative
2515    mnemonic strings for AT&T and Intel.  */
2516
2517 static const struct dis386 dis386[] = {
2518   /* 00 */
2519   { "addB",             { Ebh1, Gb }, 0 },
2520   { "addS",             { Evh1, Gv }, 0 },
2521   { "addB",             { Gb, EbS }, 0 },
2522   { "addS",             { Gv, EvS }, 0 },
2523   { "addB",             { AL, Ib }, 0 },
2524   { "addS",             { eAX, Iv }, 0 },
2525   { X86_64_TABLE (X86_64_06) },
2526   { X86_64_TABLE (X86_64_07) },
2527   /* 08 */
2528   { "orB",              { Ebh1, Gb }, 0 },
2529   { "orS",              { Evh1, Gv }, 0 },
2530   { "orB",              { Gb, EbS }, 0 },
2531   { "orS",              { Gv, EvS }, 0 },
2532   { "orB",              { AL, Ib }, 0 },
2533   { "orS",              { eAX, Iv }, 0 },
2534   { X86_64_TABLE (X86_64_0D) },
2535   { Bad_Opcode },       /* 0x0f extended opcode escape */
2536   /* 10 */
2537   { "adcB",             { Ebh1, Gb }, 0 },
2538   { "adcS",             { Evh1, Gv }, 0 },
2539   { "adcB",             { Gb, EbS }, 0 },
2540   { "adcS",             { Gv, EvS }, 0 },
2541   { "adcB",             { AL, Ib }, 0 },
2542   { "adcS",             { eAX, Iv }, 0 },
2543   { X86_64_TABLE (X86_64_16) },
2544   { X86_64_TABLE (X86_64_17) },
2545   /* 18 */
2546   { "sbbB",             { Ebh1, Gb }, 0 },
2547   { "sbbS",             { Evh1, Gv }, 0 },
2548   { "sbbB",             { Gb, EbS }, 0 },
2549   { "sbbS",             { Gv, EvS }, 0 },
2550   { "sbbB",             { AL, Ib }, 0 },
2551   { "sbbS",             { eAX, Iv }, 0 },
2552   { X86_64_TABLE (X86_64_1E) },
2553   { X86_64_TABLE (X86_64_1F) },
2554   /* 20 */
2555   { "andB",             { Ebh1, Gb }, 0 },
2556   { "andS",             { Evh1, Gv }, 0 },
2557   { "andB",             { Gb, EbS }, 0 },
2558   { "andS",             { Gv, EvS }, 0 },
2559   { "andB",             { AL, Ib }, 0 },
2560   { "andS",             { eAX, Iv }, 0 },
2561   { Bad_Opcode },       /* SEG ES prefix */
2562   { X86_64_TABLE (X86_64_27) },
2563   /* 28 */
2564   { "subB",             { Ebh1, Gb }, 0 },
2565   { "subS",             { Evh1, Gv }, 0 },
2566   { "subB",             { Gb, EbS }, 0 },
2567   { "subS",             { Gv, EvS }, 0 },
2568   { "subB",             { AL, Ib }, 0 },
2569   { "subS",             { eAX, Iv }, 0 },
2570   { Bad_Opcode },       /* SEG CS prefix */
2571   { X86_64_TABLE (X86_64_2F) },
2572   /* 30 */
2573   { "xorB",             { Ebh1, Gb }, 0 },
2574   { "xorS",             { Evh1, Gv }, 0 },
2575   { "xorB",             { Gb, EbS }, 0 },
2576   { "xorS",             { Gv, EvS }, 0 },
2577   { "xorB",             { AL, Ib }, 0 },
2578   { "xorS",             { eAX, Iv }, 0 },
2579   { Bad_Opcode },       /* SEG SS prefix */
2580   { X86_64_TABLE (X86_64_37) },
2581   /* 38 */
2582   { "cmpB",             { Eb, Gb }, 0 },
2583   { "cmpS",             { Ev, Gv }, 0 },
2584   { "cmpB",             { Gb, EbS }, 0 },
2585   { "cmpS",             { Gv, EvS }, 0 },
2586   { "cmpB",             { AL, Ib }, 0 },
2587   { "cmpS",             { eAX, Iv }, 0 },
2588   { Bad_Opcode },       /* SEG DS prefix */
2589   { X86_64_TABLE (X86_64_3F) },
2590   /* 40 */
2591   { "inc{S|}",          { RMeAX }, 0 },
2592   { "inc{S|}",          { RMeCX }, 0 },
2593   { "inc{S|}",          { RMeDX }, 0 },
2594   { "inc{S|}",          { RMeBX }, 0 },
2595   { "inc{S|}",          { RMeSP }, 0 },
2596   { "inc{S|}",          { RMeBP }, 0 },
2597   { "inc{S|}",          { RMeSI }, 0 },
2598   { "inc{S|}",          { RMeDI }, 0 },
2599   /* 48 */
2600   { "dec{S|}",          { RMeAX }, 0 },
2601   { "dec{S|}",          { RMeCX }, 0 },
2602   { "dec{S|}",          { RMeDX }, 0 },
2603   { "dec{S|}",          { RMeBX }, 0 },
2604   { "dec{S|}",          { RMeSP }, 0 },
2605   { "dec{S|}",          { RMeBP }, 0 },
2606   { "dec{S|}",          { RMeSI }, 0 },
2607   { "dec{S|}",          { RMeDI }, 0 },
2608   /* 50 */
2609   { "pushV",            { RMrAX }, 0 },
2610   { "pushV",            { RMrCX }, 0 },
2611   { "pushV",            { RMrDX }, 0 },
2612   { "pushV",            { RMrBX }, 0 },
2613   { "pushV",            { RMrSP }, 0 },
2614   { "pushV",            { RMrBP }, 0 },
2615   { "pushV",            { RMrSI }, 0 },
2616   { "pushV",            { RMrDI }, 0 },
2617   /* 58 */
2618   { "popV",             { RMrAX }, 0 },
2619   { "popV",             { RMrCX }, 0 },
2620   { "popV",             { RMrDX }, 0 },
2621   { "popV",             { RMrBX }, 0 },
2622   { "popV",             { RMrSP }, 0 },
2623   { "popV",             { RMrBP }, 0 },
2624   { "popV",             { RMrSI }, 0 },
2625   { "popV",             { RMrDI }, 0 },
2626   /* 60 */
2627   { X86_64_TABLE (X86_64_60) },
2628   { X86_64_TABLE (X86_64_61) },
2629   { X86_64_TABLE (X86_64_62) },
2630   { X86_64_TABLE (X86_64_63) },
2631   { Bad_Opcode },       /* seg fs */
2632   { Bad_Opcode },       /* seg gs */
2633   { Bad_Opcode },       /* op size prefix */
2634   { Bad_Opcode },       /* adr size prefix */
2635   /* 68 */
2636   { "pushT",            { sIv }, 0 },
2637   { "imulS",            { Gv, Ev, Iv }, 0 },
2638   { "pushT",            { sIbT }, 0 },
2639   { "imulS",            { Gv, Ev, sIb }, 0 },
2640   { "ins{b|}",          { Ybr, indirDX }, 0 },
2641   { X86_64_TABLE (X86_64_6D) },
2642   { "outs{b|}",         { indirDXr, Xb }, 0 },
2643   { X86_64_TABLE (X86_64_6F) },
2644   /* 70 */
2645   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2646   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2647   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2648   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2649   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2650   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2651   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2652   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2653   /* 78 */
2654   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2655   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2656   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2657   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2658   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2659   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2660   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2661   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2662   /* 80 */
2663   { REG_TABLE (REG_80) },
2664   { REG_TABLE (REG_81) },
2665   { X86_64_TABLE (X86_64_82) },
2666   { REG_TABLE (REG_83) },
2667   { "testB",            { Eb, Gb }, 0 },
2668   { "testS",            { Ev, Gv }, 0 },
2669   { "xchgB",            { Ebh2, Gb }, 0 },
2670   { "xchgS",            { Evh2, Gv }, 0 },
2671   /* 88 */
2672   { "movB",             { Ebh3, Gb }, 0 },
2673   { "movS",             { Evh3, Gv }, 0 },
2674   { "movB",             { Gb, EbS }, 0 },
2675   { "movS",             { Gv, EvS }, 0 },
2676   { "movD",             { Sv, Sw }, 0 },
2677   { MOD_TABLE (MOD_8D) },
2678   { "movD",             { Sw, Sv }, 0 },
2679   { REG_TABLE (REG_8F) },
2680   /* 90 */
2681   { PREFIX_TABLE (PREFIX_90) },
2682   { "xchgS",            { RMeCX, eAX }, 0 },
2683   { "xchgS",            { RMeDX, eAX }, 0 },
2684   { "xchgS",            { RMeBX, eAX }, 0 },
2685   { "xchgS",            { RMeSP, eAX }, 0 },
2686   { "xchgS",            { RMeBP, eAX }, 0 },
2687   { "xchgS",            { RMeSI, eAX }, 0 },
2688   { "xchgS",            { RMeDI, eAX }, 0 },
2689   /* 98 */
2690   { "cW{t|}R",          { XX }, 0 },
2691   { "cR{t|}O",          { XX }, 0 },
2692   { X86_64_TABLE (X86_64_9A) },
2693   { Bad_Opcode },       /* fwait */
2694   { "pushfT",           { XX }, 0 },
2695   { "popfT",            { XX }, 0 },
2696   { "sahf",             { XX }, 0 },
2697   { "lahf",             { XX }, 0 },
2698   /* a0 */
2699   { "mov%LB",           { AL, Ob }, 0 },
2700   { "mov%LS",           { eAX, Ov }, 0 },
2701   { "mov%LB",           { Ob, AL }, 0 },
2702   { "mov%LS",           { Ov, eAX }, 0 },
2703   { "movs{b|}",         { Ybr, Xb }, 0 },
2704   { "movs{R|}",         { Yvr, Xv }, 0 },
2705   { "cmps{b|}",         { Xb, Yb }, 0 },
2706   { "cmps{R|}",         { Xv, Yv }, 0 },
2707   /* a8 */
2708   { "testB",            { AL, Ib }, 0 },
2709   { "testS",            { eAX, Iv }, 0 },
2710   { "stosB",            { Ybr, AL }, 0 },
2711   { "stosS",            { Yvr, eAX }, 0 },
2712   { "lodsB",            { ALr, Xb }, 0 },
2713   { "lodsS",            { eAXr, Xv }, 0 },
2714   { "scasB",            { AL, Yb }, 0 },
2715   { "scasS",            { eAX, Yv }, 0 },
2716   /* b0 */
2717   { "movB",             { RMAL, Ib }, 0 },
2718   { "movB",             { RMCL, Ib }, 0 },
2719   { "movB",             { RMDL, Ib }, 0 },
2720   { "movB",             { RMBL, Ib }, 0 },
2721   { "movB",             { RMAH, Ib }, 0 },
2722   { "movB",             { RMCH, Ib }, 0 },
2723   { "movB",             { RMDH, Ib }, 0 },
2724   { "movB",             { RMBH, Ib }, 0 },
2725   /* b8 */
2726   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2727   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2728   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2729   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2730   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2731   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2732   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2733   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2734   /* c0 */
2735   { REG_TABLE (REG_C0) },
2736   { REG_TABLE (REG_C1) },
2737   { "retT",             { Iw, BND }, 0 },
2738   { "retT",             { BND }, 0 },
2739   { X86_64_TABLE (X86_64_C4) },
2740   { X86_64_TABLE (X86_64_C5) },
2741   { REG_TABLE (REG_C6) },
2742   { REG_TABLE (REG_C7) },
2743   /* c8 */
2744   { "enterT",           { Iw, Ib }, 0 },
2745   { "leaveT",           { XX }, 0 },
2746   { "Jret{|f}P",        { Iw }, 0 },
2747   { "Jret{|f}P",        { XX }, 0 },
2748   { "int3",             { XX }, 0 },
2749   { "int",              { Ib }, 0 },
2750   { X86_64_TABLE (X86_64_CE) },
2751   { "iret%LP",          { XX }, 0 },
2752   /* d0 */
2753   { REG_TABLE (REG_D0) },
2754   { REG_TABLE (REG_D1) },
2755   { REG_TABLE (REG_D2) },
2756   { REG_TABLE (REG_D3) },
2757   { X86_64_TABLE (X86_64_D4) },
2758   { X86_64_TABLE (X86_64_D5) },
2759   { Bad_Opcode },
2760   { "xlat",             { DSBX }, 0 },
2761   /* d8 */
2762   { FLOAT },
2763   { FLOAT },
2764   { FLOAT },
2765   { FLOAT },
2766   { FLOAT },
2767   { FLOAT },
2768   { FLOAT },
2769   { FLOAT },
2770   /* e0 */
2771   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2772   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2773   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2774   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2775   { "inB",              { AL, Ib }, 0 },
2776   { "inG",              { zAX, Ib }, 0 },
2777   { "outB",             { Ib, AL }, 0 },
2778   { "outG",             { Ib, zAX }, 0 },
2779   /* e8 */
2780   { X86_64_TABLE (X86_64_E8) },
2781   { X86_64_TABLE (X86_64_E9) },
2782   { X86_64_TABLE (X86_64_EA) },
2783   { "jmp",              { Jb, BND }, 0 },
2784   { "inB",              { AL, indirDX }, 0 },
2785   { "inG",              { zAX, indirDX }, 0 },
2786   { "outB",             { indirDX, AL }, 0 },
2787   { "outG",             { indirDX, zAX }, 0 },
2788   /* f0 */
2789   { Bad_Opcode },       /* lock prefix */
2790   { "icebp",            { XX }, 0 },
2791   { Bad_Opcode },       /* repne */
2792   { Bad_Opcode },       /* repz */
2793   { "hlt",              { XX }, 0 },
2794   { "cmc",              { XX }, 0 },
2795   { REG_TABLE (REG_F6) },
2796   { REG_TABLE (REG_F7) },
2797   /* f8 */
2798   { "clc",              { XX }, 0 },
2799   { "stc",              { XX }, 0 },
2800   { "cli",              { XX }, 0 },
2801   { "sti",              { XX }, 0 },
2802   { "cld",              { XX }, 0 },
2803   { "std",              { XX }, 0 },
2804   { REG_TABLE (REG_FE) },
2805   { REG_TABLE (REG_FF) },
2806 };
2807
2808 static const struct dis386 dis386_twobyte[] = {
2809   /* 00 */
2810   { REG_TABLE (REG_0F00 ) },
2811   { REG_TABLE (REG_0F01 ) },
2812   { "larS",             { Gv, Ew }, 0 },
2813   { "lslS",             { Gv, Ew }, 0 },
2814   { Bad_Opcode },
2815   { "syscall",          { XX }, 0 },
2816   { "clts",             { XX }, 0 },
2817   { "sysret%LP",                { XX }, 0 },
2818   /* 08 */
2819   { "invd",             { XX }, 0 },
2820   { "wbinvd",           { XX }, 0 },
2821   { Bad_Opcode },
2822   { "ud2",              { XX }, 0 },
2823   { Bad_Opcode },
2824   { REG_TABLE (REG_0F0D) },
2825   { "femms",            { XX }, 0 },
2826   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2827   /* 10 */
2828   { PREFIX_TABLE (PREFIX_0F10) },
2829   { PREFIX_TABLE (PREFIX_0F11) },
2830   { PREFIX_TABLE (PREFIX_0F12) },
2831   { MOD_TABLE (MOD_0F13) },
2832   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2833   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2834   { PREFIX_TABLE (PREFIX_0F16) },
2835   { MOD_TABLE (MOD_0F17) },
2836   /* 18 */
2837   { REG_TABLE (REG_0F18) },
2838   { "nopQ",             { Ev }, 0 },
2839   { PREFIX_TABLE (PREFIX_0F1A) },
2840   { PREFIX_TABLE (PREFIX_0F1B) },
2841   { "nopQ",             { Ev }, 0 },
2842   { "nopQ",             { Ev }, 0 },
2843   { "nopQ",             { Ev }, 0 },
2844   { "nopQ",             { Ev }, 0 },
2845   /* 20 */
2846   { "movZ",             { Rm, Cm }, 0 },
2847   { "movZ",             { Rm, Dm }, 0 },
2848   { "movZ",             { Cm, Rm }, 0 },
2849   { "movZ",             { Dm, Rm }, 0 },
2850   { MOD_TABLE (MOD_0F24) },
2851   { Bad_Opcode },
2852   { MOD_TABLE (MOD_0F26) },
2853   { Bad_Opcode },
2854   /* 28 */
2855   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2856   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2857   { PREFIX_TABLE (PREFIX_0F2A) },
2858   { PREFIX_TABLE (PREFIX_0F2B) },
2859   { PREFIX_TABLE (PREFIX_0F2C) },
2860   { PREFIX_TABLE (PREFIX_0F2D) },
2861   { PREFIX_TABLE (PREFIX_0F2E) },
2862   { PREFIX_TABLE (PREFIX_0F2F) },
2863   /* 30 */
2864   { "wrmsr",            { XX }, 0 },
2865   { "rdtsc",            { XX }, 0 },
2866   { "rdmsr",            { XX }, 0 },
2867   { "rdpmc",            { XX }, 0 },
2868   { "sysenter",         { XX }, 0 },
2869   { "sysexit",          { XX }, 0 },
2870   { Bad_Opcode },
2871   { "getsec",           { XX }, 0 },
2872   /* 38 */
2873   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2874   { Bad_Opcode },
2875   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2876   { Bad_Opcode },
2877   { Bad_Opcode },
2878   { Bad_Opcode },
2879   { Bad_Opcode },
2880   { Bad_Opcode },
2881   /* 40 */
2882   { "cmovoS",           { Gv, Ev }, 0 },
2883   { "cmovnoS",          { Gv, Ev }, 0 },
2884   { "cmovbS",           { Gv, Ev }, 0 },
2885   { "cmovaeS",          { Gv, Ev }, 0 },
2886   { "cmoveS",           { Gv, Ev }, 0 },
2887   { "cmovneS",          { Gv, Ev }, 0 },
2888   { "cmovbeS",          { Gv, Ev }, 0 },
2889   { "cmovaS",           { Gv, Ev }, 0 },
2890   /* 48 */
2891   { "cmovsS",           { Gv, Ev }, 0 },
2892   { "cmovnsS",          { Gv, Ev }, 0 },
2893   { "cmovpS",           { Gv, Ev }, 0 },
2894   { "cmovnpS",          { Gv, Ev }, 0 },
2895   { "cmovlS",           { Gv, Ev }, 0 },
2896   { "cmovgeS",          { Gv, Ev }, 0 },
2897   { "cmovleS",          { Gv, Ev }, 0 },
2898   { "cmovgS",           { Gv, Ev }, 0 },
2899   /* 50 */
2900   { MOD_TABLE (MOD_0F51) },
2901   { PREFIX_TABLE (PREFIX_0F51) },
2902   { PREFIX_TABLE (PREFIX_0F52) },
2903   { PREFIX_TABLE (PREFIX_0F53) },
2904   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2905   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2906   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2907   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2908   /* 58 */
2909   { PREFIX_TABLE (PREFIX_0F58) },
2910   { PREFIX_TABLE (PREFIX_0F59) },
2911   { PREFIX_TABLE (PREFIX_0F5A) },
2912   { PREFIX_TABLE (PREFIX_0F5B) },
2913   { PREFIX_TABLE (PREFIX_0F5C) },
2914   { PREFIX_TABLE (PREFIX_0F5D) },
2915   { PREFIX_TABLE (PREFIX_0F5E) },
2916   { PREFIX_TABLE (PREFIX_0F5F) },
2917   /* 60 */
2918   { PREFIX_TABLE (PREFIX_0F60) },
2919   { PREFIX_TABLE (PREFIX_0F61) },
2920   { PREFIX_TABLE (PREFIX_0F62) },
2921   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2922   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2923   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2924   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2925   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2926   /* 68 */
2927   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2928   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2929   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2930   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2931   { PREFIX_TABLE (PREFIX_0F6C) },
2932   { PREFIX_TABLE (PREFIX_0F6D) },
2933   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2934   { PREFIX_TABLE (PREFIX_0F6F) },
2935   /* 70 */
2936   { PREFIX_TABLE (PREFIX_0F70) },
2937   { REG_TABLE (REG_0F71) },
2938   { REG_TABLE (REG_0F72) },
2939   { REG_TABLE (REG_0F73) },
2940   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2941   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2942   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2943   { "emms",             { XX }, PREFIX_OPCODE },
2944   /* 78 */
2945   { PREFIX_TABLE (PREFIX_0F78) },
2946   { PREFIX_TABLE (PREFIX_0F79) },
2947   { Bad_Opcode },
2948   { Bad_Opcode },
2949   { PREFIX_TABLE (PREFIX_0F7C) },
2950   { PREFIX_TABLE (PREFIX_0F7D) },
2951   { PREFIX_TABLE (PREFIX_0F7E) },
2952   { PREFIX_TABLE (PREFIX_0F7F) },
2953   /* 80 */
2954   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2955   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2956   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2957   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2958   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2959   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2960   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2961   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2962   /* 88 */
2963   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2964   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2965   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2966   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2967   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2968   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2969   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2970   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2971   /* 90 */
2972   { "seto",             { Eb }, 0 },
2973   { "setno",            { Eb }, 0 },
2974   { "setb",             { Eb }, 0 },
2975   { "setae",            { Eb }, 0 },
2976   { "sete",             { Eb }, 0 },
2977   { "setne",            { Eb }, 0 },
2978   { "setbe",            { Eb }, 0 },
2979   { "seta",             { Eb }, 0 },
2980   /* 98 */
2981   { "sets",             { Eb }, 0 },
2982   { "setns",            { Eb }, 0 },
2983   { "setp",             { Eb }, 0 },
2984   { "setnp",            { Eb }, 0 },
2985   { "setl",             { Eb }, 0 },
2986   { "setge",            { Eb }, 0 },
2987   { "setle",            { Eb }, 0 },
2988   { "setg",             { Eb }, 0 },
2989   /* a0 */
2990   { "pushT",            { fs }, 0 },
2991   { "popT",             { fs }, 0 },
2992   { "cpuid",            { XX }, 0 },
2993   { "btS",              { Ev, Gv }, 0 },
2994   { "shldS",            { Ev, Gv, Ib }, 0 },
2995   { "shldS",            { Ev, Gv, CL }, 0 },
2996   { REG_TABLE (REG_0FA6) },
2997   { REG_TABLE (REG_0FA7) },
2998   /* a8 */
2999   { "pushT",            { gs }, 0 },
3000   { "popT",             { gs }, 0 },
3001   { "rsm",              { XX }, 0 },
3002   { "btsS",             { Evh1, Gv }, 0 },
3003   { "shrdS",            { Ev, Gv, Ib }, 0 },
3004   { "shrdS",            { Ev, Gv, CL }, 0 },
3005   { REG_TABLE (REG_0FAE) },
3006   { "imulS",            { Gv, Ev }, 0 },
3007   /* b0 */
3008   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3009   { "cmpxchgS",         { Evh1, Gv }, 0 },
3010   { MOD_TABLE (MOD_0FB2) },
3011   { "btrS",             { Evh1, Gv }, 0 },
3012   { MOD_TABLE (MOD_0FB4) },
3013   { MOD_TABLE (MOD_0FB5) },
3014   { "movz{bR|x}",       { Gv, Eb }, 0 },
3015   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3016   /* b8 */
3017   { PREFIX_TABLE (PREFIX_0FB8) },
3018   { "ud1",              { XX }, 0 },
3019   { REG_TABLE (REG_0FBA) },
3020   { "btcS",             { Evh1, Gv }, 0 },
3021   { PREFIX_TABLE (PREFIX_0FBC) },
3022   { PREFIX_TABLE (PREFIX_0FBD) },
3023   { "movs{bR|x}",       { Gv, Eb }, 0 },
3024   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3025   /* c0 */
3026   { "xaddB",            { Ebh1, Gb }, 0 },
3027   { "xaddS",            { Evh1, Gv }, 0 },
3028   { PREFIX_TABLE (PREFIX_0FC2) },
3029   { MOD_TABLE (MOD_0FC3) },
3030   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3031   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3032   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3033   { REG_TABLE (REG_0FC7) },
3034   /* c8 */
3035   { "bswap",            { RMeAX }, 0 },
3036   { "bswap",            { RMeCX }, 0 },
3037   { "bswap",            { RMeDX }, 0 },
3038   { "bswap",            { RMeBX }, 0 },
3039   { "bswap",            { RMeSP }, 0 },
3040   { "bswap",            { RMeBP }, 0 },
3041   { "bswap",            { RMeSI }, 0 },
3042   { "bswap",            { RMeDI }, 0 },
3043   /* d0 */
3044   { PREFIX_TABLE (PREFIX_0FD0) },
3045   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3046   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3047   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3048   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3049   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3050   { PREFIX_TABLE (PREFIX_0FD6) },
3051   { MOD_TABLE (MOD_0FD7) },
3052   /* d8 */
3053   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3054   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3055   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3056   { "pand",             { MX, EM }, PREFIX_OPCODE },
3057   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3058   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3059   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3060   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3061   /* e0 */
3062   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3063   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3064   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3065   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3066   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3067   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3068   { PREFIX_TABLE (PREFIX_0FE6) },
3069   { PREFIX_TABLE (PREFIX_0FE7) },
3070   /* e8 */
3071   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3072   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3073   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3074   { "por",              { MX, EM }, PREFIX_OPCODE },
3075   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3076   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3077   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3078   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3079   /* f0 */
3080   { PREFIX_TABLE (PREFIX_0FF0) },
3081   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3082   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3083   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3084   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3085   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3086   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3087   { PREFIX_TABLE (PREFIX_0FF7) },
3088   /* f8 */
3089   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3090   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3091   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3092   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3093   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3094   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3095   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3096   { Bad_Opcode },
3097 };
3098
3099 static const unsigned char onebyte_has_modrm[256] = {
3100   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3101   /*       -------------------------------        */
3102   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3103   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3104   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3105   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3106   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3107   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3108   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3109   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3110   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3111   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3112   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3113   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3114   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3115   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3116   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3117   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3118   /*       -------------------------------        */
3119   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3120 };
3121
3122 static const unsigned char twobyte_has_modrm[256] = {
3123   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3124   /*       -------------------------------        */
3125   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3126   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3127   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3128   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3129   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3130   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3131   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3132   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3133   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3134   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3135   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3136   /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3137   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3138   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3139   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3140   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3141   /*       -------------------------------        */
3142   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3143 };
3144
3145 static char obuf[100];
3146 static char *obufp;
3147 static char *mnemonicendp;
3148 static char scratchbuf[100];
3149 static unsigned char *start_codep;
3150 static unsigned char *insn_codep;
3151 static unsigned char *codep;
3152 static unsigned char *end_codep;
3153 static int last_lock_prefix;
3154 static int last_repz_prefix;
3155 static int last_repnz_prefix;
3156 static int last_data_prefix;
3157 static int last_addr_prefix;
3158 static int last_rex_prefix;
3159 static int last_seg_prefix;
3160 static int fwait_prefix;
3161 /* The active segment register prefix.  */
3162 static int active_seg_prefix;
3163 #define MAX_CODE_LENGTH 15
3164 /* We can up to 14 prefixes since the maximum instruction length is
3165    15bytes.  */
3166 static int all_prefixes[MAX_CODE_LENGTH - 1];
3167 static disassemble_info *the_info;
3168 static struct
3169   {
3170     int mod;
3171     int reg;
3172     int rm;
3173   }
3174 modrm;
3175 static unsigned char need_modrm;
3176 static struct
3177   {
3178     int scale;
3179     int index;
3180     int base;
3181   }
3182 sib;
3183 static struct
3184   {
3185     int register_specifier;
3186     int length;
3187     int prefix;
3188     int w;
3189     int evex;
3190     int r;
3191     int v;
3192     int mask_register_specifier;
3193     int zeroing;
3194     int ll;
3195     int b;
3196   }
3197 vex;
3198 static unsigned char need_vex;
3199 static unsigned char need_vex_reg;
3200 static unsigned char vex_w_done;
3201
3202 struct op
3203   {
3204     const char *name;
3205     unsigned int len;
3206   };
3207
3208 /* If we are accessing mod/rm/reg without need_modrm set, then the
3209    values are stale.  Hitting this abort likely indicates that you
3210    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3211 #define MODRM_CHECK  if (!need_modrm) abort ()
3212
3213 static const char **names64;
3214 static const char **names32;
3215 static const char **names16;
3216 static const char **names8;
3217 static const char **names8rex;
3218 static const char **names_seg;
3219 static const char *index64;
3220 static const char *index32;
3221 static const char **index16;
3222 static const char **names_bnd;
3223
3224 static const char *intel_names64[] = {
3225   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3226   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3227 };
3228 static const char *intel_names32[] = {
3229   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3230   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3231 };
3232 static const char *intel_names16[] = {
3233   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3234   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3235 };
3236 static const char *intel_names8[] = {
3237   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3238 };
3239 static const char *intel_names8rex[] = {
3240   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3241   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3242 };
3243 static const char *intel_names_seg[] = {
3244   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3245 };
3246 static const char *intel_index64 = "riz";
3247 static const char *intel_index32 = "eiz";
3248 static const char *intel_index16[] = {
3249   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3250 };
3251
3252 static const char *att_names64[] = {
3253   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3254   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3255 };
3256 static const char *att_names32[] = {
3257   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3258   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3259 };
3260 static const char *att_names16[] = {
3261   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3262   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3263 };
3264 static const char *att_names8[] = {
3265   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3266 };
3267 static const char *att_names8rex[] = {
3268   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3269   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3270 };
3271 static const char *att_names_seg[] = {
3272   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3273 };
3274 static const char *att_index64 = "%riz";
3275 static const char *att_index32 = "%eiz";
3276 static const char *att_index16[] = {
3277   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3278 };
3279
3280 static const char **names_mm;
3281 static const char *intel_names_mm[] = {
3282   "mm0", "mm1", "mm2", "mm3",
3283   "mm4", "mm5", "mm6", "mm7"
3284 };
3285 static const char *att_names_mm[] = {
3286   "%mm0", "%mm1", "%mm2", "%mm3",
3287   "%mm4", "%mm5", "%mm6", "%mm7"
3288 };
3289
3290 static const char *intel_names_bnd[] = {
3291   "bnd0", "bnd1", "bnd2", "bnd3"
3292 };
3293
3294 static const char *att_names_bnd[] = {
3295   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3296 };
3297
3298 static const char **names_xmm;
3299 static const char *intel_names_xmm[] = {
3300   "xmm0", "xmm1", "xmm2", "xmm3",
3301   "xmm4", "xmm5", "xmm6", "xmm7",
3302   "xmm8", "xmm9", "xmm10", "xmm11",
3303   "xmm12", "xmm13", "xmm14", "xmm15",
3304   "xmm16", "xmm17", "xmm18", "xmm19",
3305   "xmm20", "xmm21", "xmm22", "xmm23",
3306   "xmm24", "xmm25", "xmm26", "xmm27",
3307   "xmm28", "xmm29", "xmm30", "xmm31"
3308 };
3309 static const char *att_names_xmm[] = {
3310   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3311   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3312   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3313   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3314   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3315   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3316   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3317   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3318 };
3319
3320 static const char **names_ymm;
3321 static const char *intel_names_ymm[] = {
3322   "ymm0", "ymm1", "ymm2", "ymm3",
3323   "ymm4", "ymm5", "ymm6", "ymm7",
3324   "ymm8", "ymm9", "ymm10", "ymm11",
3325   "ymm12", "ymm13", "ymm14", "ymm15",
3326   "ymm16", "ymm17", "ymm18", "ymm19",
3327   "ymm20", "ymm21", "ymm22", "ymm23",
3328   "ymm24", "ymm25", "ymm26", "ymm27",
3329   "ymm28", "ymm29", "ymm30", "ymm31"
3330 };
3331 static const char *att_names_ymm[] = {
3332   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3333   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3334   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3335   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3336   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3337   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3338   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3339   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3340 };
3341
3342 static const char **names_zmm;
3343 static const char *intel_names_zmm[] = {
3344   "zmm0", "zmm1", "zmm2", "zmm3",
3345   "zmm4", "zmm5", "zmm6", "zmm7",
3346   "zmm8", "zmm9", "zmm10", "zmm11",
3347   "zmm12", "zmm13", "zmm14", "zmm15",
3348   "zmm16", "zmm17", "zmm18", "zmm19",
3349   "zmm20", "zmm21", "zmm22", "zmm23",
3350   "zmm24", "zmm25", "zmm26", "zmm27",
3351   "zmm28", "zmm29", "zmm30", "zmm31"
3352 };
3353 static const char *att_names_zmm[] = {
3354   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3355   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3356   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3357   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3358   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3359   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3360   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3361   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3362 };
3363
3364 static const char **names_mask;
3365 static const char *intel_names_mask[] = {
3366   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3367 };
3368 static const char *att_names_mask[] = {
3369   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3370 };
3371
3372 static const char *names_rounding[] =
3373 {
3374   "{rn-sae}",
3375   "{rd-sae}",
3376   "{ru-sae}",
3377   "{rz-sae}"
3378 };
3379
3380 static const struct dis386 reg_table[][8] = {
3381   /* REG_80 */
3382   {
3383     { "addA",   { Ebh1, Ib }, 0 },
3384     { "orA",    { Ebh1, Ib }, 0 },
3385     { "adcA",   { Ebh1, Ib }, 0 },
3386     { "sbbA",   { Ebh1, Ib }, 0 },
3387     { "andA",   { Ebh1, Ib }, 0 },
3388     { "subA",   { Ebh1, Ib }, 0 },
3389     { "xorA",   { Ebh1, Ib }, 0 },
3390     { "cmpA",   { Eb, Ib }, 0 },
3391   },
3392   /* REG_81 */
3393   {
3394     { "addQ",   { Evh1, Iv }, 0 },
3395     { "orQ",    { Evh1, Iv }, 0 },
3396     { "adcQ",   { Evh1, Iv }, 0 },
3397     { "sbbQ",   { Evh1, Iv }, 0 },
3398     { "andQ",   { Evh1, Iv }, 0 },
3399     { "subQ",   { Evh1, Iv }, 0 },
3400     { "xorQ",   { Evh1, Iv }, 0 },
3401     { "cmpQ",   { Ev, Iv }, 0 },
3402   },
3403   /* REG_83 */
3404   {
3405     { "addQ",   { Evh1, sIb }, 0 },
3406     { "orQ",    { Evh1, sIb }, 0 },
3407     { "adcQ",   { Evh1, sIb }, 0 },
3408     { "sbbQ",   { Evh1, sIb }, 0 },
3409     { "andQ",   { Evh1, sIb }, 0 },
3410     { "subQ",   { Evh1, sIb }, 0 },
3411     { "xorQ",   { Evh1, sIb }, 0 },
3412     { "cmpQ",   { Ev, sIb }, 0 },
3413   },
3414   /* REG_8F */
3415   {
3416     { "popU",   { stackEv }, 0 },
3417     { XOP_8F_TABLE (XOP_09) },
3418     { Bad_Opcode },
3419     { Bad_Opcode },
3420     { Bad_Opcode },
3421     { XOP_8F_TABLE (XOP_09) },
3422   },
3423   /* REG_C0 */
3424   {
3425     { "rolA",   { Eb, Ib }, 0 },
3426     { "rorA",   { Eb, Ib }, 0 },
3427     { "rclA",   { Eb, Ib }, 0 },
3428     { "rcrA",   { Eb, Ib }, 0 },
3429     { "shlA",   { Eb, Ib }, 0 },
3430     { "shrA",   { Eb, Ib }, 0 },
3431     { Bad_Opcode },
3432     { "sarA",   { Eb, Ib }, 0 },
3433   },
3434   /* REG_C1 */
3435   {
3436     { "rolQ",   { Ev, Ib }, 0 },
3437     { "rorQ",   { Ev, Ib }, 0 },
3438     { "rclQ",   { Ev, Ib }, 0 },
3439     { "rcrQ",   { Ev, Ib }, 0 },
3440     { "shlQ",   { Ev, Ib }, 0 },
3441     { "shrQ",   { Ev, Ib }, 0 },
3442     { Bad_Opcode },
3443     { "sarQ",   { Ev, Ib }, 0 },
3444   },
3445   /* REG_C6 */
3446   {
3447     { "movA",   { Ebh3, Ib }, 0 },
3448     { Bad_Opcode },
3449     { Bad_Opcode },
3450     { Bad_Opcode },
3451     { Bad_Opcode },
3452     { Bad_Opcode },
3453     { Bad_Opcode },
3454     { MOD_TABLE (MOD_C6_REG_7) },
3455   },
3456   /* REG_C7 */
3457   {
3458     { "movQ",   { Evh3, Iv }, 0 },
3459     { Bad_Opcode },
3460     { Bad_Opcode },
3461     { Bad_Opcode },
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { Bad_Opcode },
3465     { MOD_TABLE (MOD_C7_REG_7) },
3466   },
3467   /* REG_D0 */
3468   {
3469     { "rolA",   { Eb, I1 }, 0 },
3470     { "rorA",   { Eb, I1 }, 0 },
3471     { "rclA",   { Eb, I1 }, 0 },
3472     { "rcrA",   { Eb, I1 }, 0 },
3473     { "shlA",   { Eb, I1 }, 0 },
3474     { "shrA",   { Eb, I1 }, 0 },
3475     { Bad_Opcode },
3476     { "sarA",   { Eb, I1 }, 0 },
3477   },
3478   /* REG_D1 */
3479   {
3480     { "rolQ",   { Ev, I1 }, 0 },
3481     { "rorQ",   { Ev, I1 }, 0 },
3482     { "rclQ",   { Ev, I1 }, 0 },
3483     { "rcrQ",   { Ev, I1 }, 0 },
3484     { "shlQ",   { Ev, I1 }, 0 },
3485     { "shrQ",   { Ev, I1 }, 0 },
3486     { Bad_Opcode },
3487     { "sarQ",   { Ev, I1 }, 0 },
3488   },
3489   /* REG_D2 */
3490   {
3491     { "rolA",   { Eb, CL }, 0 },
3492     { "rorA",   { Eb, CL }, 0 },
3493     { "rclA",   { Eb, CL }, 0 },
3494     { "rcrA",   { Eb, CL }, 0 },
3495     { "shlA",   { Eb, CL }, 0 },
3496     { "shrA",   { Eb, CL }, 0 },
3497     { Bad_Opcode },
3498     { "sarA",   { Eb, CL }, 0 },
3499   },
3500   /* REG_D3 */
3501   {
3502     { "rolQ",   { Ev, CL }, 0 },
3503     { "rorQ",   { Ev, CL }, 0 },
3504     { "rclQ",   { Ev, CL }, 0 },
3505     { "rcrQ",   { Ev, CL }, 0 },
3506     { "shlQ",   { Ev, CL }, 0 },
3507     { "shrQ",   { Ev, CL }, 0 },
3508     { Bad_Opcode },
3509     { "sarQ",   { Ev, CL }, 0 },
3510   },
3511   /* REG_F6 */
3512   {
3513     { "testA",  { Eb, Ib }, 0 },
3514     { Bad_Opcode },
3515     { "notA",   { Ebh1 }, 0 },
3516     { "negA",   { Ebh1 }, 0 },
3517     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3518     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3519     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3520     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3521   },
3522   /* REG_F7 */
3523   {
3524     { "testQ",  { Ev, Iv }, 0 },
3525     { Bad_Opcode },
3526     { "notQ",   { Evh1 }, 0 },
3527     { "negQ",   { Evh1 }, 0 },
3528     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3529     { "imulQ",  { Ev }, 0 },
3530     { "divQ",   { Ev }, 0 },
3531     { "idivQ",  { Ev }, 0 },
3532   },
3533   /* REG_FE */
3534   {
3535     { "incA",   { Ebh1 }, 0 },
3536     { "decA",   { Ebh1 }, 0 },
3537   },
3538   /* REG_FF */
3539   {
3540     { "incQ",   { Evh1 }, 0 },
3541     { "decQ",   { Evh1 }, 0 },
3542     { "call{&|}", { indirEv, BND }, 0 },
3543     { MOD_TABLE (MOD_FF_REG_3) },
3544     { "jmp{&|}", { indirEv, BND }, 0 },
3545     { MOD_TABLE (MOD_FF_REG_5) },
3546     { "pushU",  { stackEv }, 0 },
3547     { Bad_Opcode },
3548   },
3549   /* REG_0F00 */
3550   {
3551     { "sldtD",  { Sv }, 0 },
3552     { "strD",   { Sv }, 0 },
3553     { "lldt",   { Ew }, 0 },
3554     { "ltr",    { Ew }, 0 },
3555     { "verr",   { Ew }, 0 },
3556     { "verw",   { Ew }, 0 },
3557     { Bad_Opcode },
3558     { Bad_Opcode },
3559   },
3560   /* REG_0F01 */
3561   {
3562     { MOD_TABLE (MOD_0F01_REG_0) },
3563     { MOD_TABLE (MOD_0F01_REG_1) },
3564     { MOD_TABLE (MOD_0F01_REG_2) },
3565     { MOD_TABLE (MOD_0F01_REG_3) },
3566     { "smswD",  { Sv }, 0 },
3567     { MOD_TABLE (MOD_0F01_REG_5) },
3568     { "lmsw",   { Ew }, 0 },
3569     { MOD_TABLE (MOD_0F01_REG_7) },
3570   },
3571   /* REG_0F0D */
3572   {
3573     { "prefetch",       { Mb }, 0 },
3574     { "prefetchw",      { Mb }, 0 },
3575     { "prefetchwt1",    { Mb }, 0 },
3576     { "prefetch",       { Mb }, 0 },
3577     { "prefetch",       { Mb }, 0 },
3578     { "prefetch",       { Mb }, 0 },
3579     { "prefetch",       { Mb }, 0 },
3580     { "prefetch",       { Mb }, 0 },
3581   },
3582   /* REG_0F18 */
3583   {
3584     { MOD_TABLE (MOD_0F18_REG_0) },
3585     { MOD_TABLE (MOD_0F18_REG_1) },
3586     { MOD_TABLE (MOD_0F18_REG_2) },
3587     { MOD_TABLE (MOD_0F18_REG_3) },
3588     { MOD_TABLE (MOD_0F18_REG_4) },
3589     { MOD_TABLE (MOD_0F18_REG_5) },
3590     { MOD_TABLE (MOD_0F18_REG_6) },
3591     { MOD_TABLE (MOD_0F18_REG_7) },
3592   },
3593   /* REG_0F71 */
3594   {
3595     { Bad_Opcode },
3596     { Bad_Opcode },
3597     { MOD_TABLE (MOD_0F71_REG_2) },
3598     { Bad_Opcode },
3599     { MOD_TABLE (MOD_0F71_REG_4) },
3600     { Bad_Opcode },
3601     { MOD_TABLE (MOD_0F71_REG_6) },
3602   },
3603   /* REG_0F72 */
3604   {
3605     { Bad_Opcode },
3606     { Bad_Opcode },
3607     { MOD_TABLE (MOD_0F72_REG_2) },
3608     { Bad_Opcode },
3609     { MOD_TABLE (MOD_0F72_REG_4) },
3610     { Bad_Opcode },
3611     { MOD_TABLE (MOD_0F72_REG_6) },
3612   },
3613   /* REG_0F73 */
3614   {
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { MOD_TABLE (MOD_0F73_REG_2) },
3618     { MOD_TABLE (MOD_0F73_REG_3) },
3619     { Bad_Opcode },
3620     { Bad_Opcode },
3621     { MOD_TABLE (MOD_0F73_REG_6) },
3622     { MOD_TABLE (MOD_0F73_REG_7) },
3623   },
3624   /* REG_0FA6 */
3625   {
3626     { "montmul",        { { OP_0f07, 0 } }, 0 },
3627     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3628     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3629   },
3630   /* REG_0FA7 */
3631   {
3632     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3633     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3634     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3635     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3636     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3637     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3638   },
3639   /* REG_0FAE */
3640   {
3641     { MOD_TABLE (MOD_0FAE_REG_0) },
3642     { MOD_TABLE (MOD_0FAE_REG_1) },
3643     { MOD_TABLE (MOD_0FAE_REG_2) },
3644     { MOD_TABLE (MOD_0FAE_REG_3) },
3645     { MOD_TABLE (MOD_0FAE_REG_4) },
3646     { MOD_TABLE (MOD_0FAE_REG_5) },
3647     { MOD_TABLE (MOD_0FAE_REG_6) },
3648     { MOD_TABLE (MOD_0FAE_REG_7) },
3649   },
3650   /* REG_0FBA */
3651   {
3652     { Bad_Opcode },
3653     { Bad_Opcode },
3654     { Bad_Opcode },
3655     { Bad_Opcode },
3656     { "btQ",    { Ev, Ib }, 0 },
3657     { "btsQ",   { Evh1, Ib }, 0 },
3658     { "btrQ",   { Evh1, Ib }, 0 },
3659     { "btcQ",   { Evh1, Ib }, 0 },
3660   },
3661   /* REG_0FC7 */
3662   {
3663     { Bad_Opcode },
3664     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3665     { Bad_Opcode },
3666     { MOD_TABLE (MOD_0FC7_REG_3) },
3667     { MOD_TABLE (MOD_0FC7_REG_4) },
3668     { MOD_TABLE (MOD_0FC7_REG_5) },
3669     { MOD_TABLE (MOD_0FC7_REG_6) },
3670     { MOD_TABLE (MOD_0FC7_REG_7) },
3671   },
3672   /* REG_VEX_0F71 */
3673   {
3674     { Bad_Opcode },
3675     { Bad_Opcode },
3676     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3677     { Bad_Opcode },
3678     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3679     { Bad_Opcode },
3680     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3681   },
3682   /* REG_VEX_0F72 */
3683   {
3684     { Bad_Opcode },
3685     { Bad_Opcode },
3686     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3687     { Bad_Opcode },
3688     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3689     { Bad_Opcode },
3690     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3691   },
3692   /* REG_VEX_0F73 */
3693   {
3694     { Bad_Opcode },
3695     { Bad_Opcode },
3696     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3697     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3698     { Bad_Opcode },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3701     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3702   },
3703   /* REG_VEX_0FAE */
3704   {
3705     { Bad_Opcode },
3706     { Bad_Opcode },
3707     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3708     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3709   },
3710   /* REG_VEX_0F38F3 */
3711   {
3712     { Bad_Opcode },
3713     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3714     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3715     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3716   },
3717   /* REG_XOP_LWPCB */
3718   {
3719     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3720     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3721   },
3722   /* REG_XOP_LWP */
3723   {
3724     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3725     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3726   },
3727   /* REG_XOP_TBM_01 */
3728   {
3729     { Bad_Opcode },
3730     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3731     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3732     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3733     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3734     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3735     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3736     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3737   },
3738   /* REG_XOP_TBM_02 */
3739   {
3740     { Bad_Opcode },
3741     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3742     { Bad_Opcode },
3743     { Bad_Opcode },
3744     { Bad_Opcode },
3745     { Bad_Opcode },
3746     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3747   },
3748 #define NEED_REG_TABLE
3749 #include "i386-dis-evex.h"
3750 #undef NEED_REG_TABLE
3751 };
3752
3753 static const struct dis386 prefix_table[][4] = {
3754   /* PREFIX_90 */
3755   {
3756     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3757     { "pause", { XX }, 0 },
3758     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3759     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3760   },
3761
3762   /* PREFIX_0F10 */
3763   {
3764     { "movups", { XM, EXx }, PREFIX_OPCODE },
3765     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3766     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3767     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3768   },
3769
3770   /* PREFIX_0F11 */
3771   {
3772     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3773     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3774     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3775     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3776   },
3777
3778   /* PREFIX_0F12 */
3779   {
3780     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3781     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3782     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3783     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3784   },
3785
3786   /* PREFIX_0F16 */
3787   {
3788     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3789     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3790     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3791   },
3792
3793   /* PREFIX_0F1A */
3794   {
3795     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3796     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3797     { "bndmov", { Gbnd, Ebnd }, 0 },
3798     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3799   },
3800
3801   /* PREFIX_0F1B */
3802   {
3803     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3804     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3805     { "bndmov", { Ebnd, Gbnd }, 0 },
3806     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3807   },
3808
3809   /* PREFIX_0F2A */
3810   {
3811     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3812     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3813     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3814     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3815   },
3816
3817   /* PREFIX_0F2B */
3818   {
3819     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3820     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3821     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3822     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3823   },
3824
3825   /* PREFIX_0F2C */
3826   {
3827     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3828     { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3829     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3830     { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3831   },
3832
3833   /* PREFIX_0F2D */
3834   {
3835     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3836     { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3837     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3838     { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3839   },
3840
3841   /* PREFIX_0F2E */
3842   {
3843     { "ucomiss",{ XM, EXd }, 0 },
3844     { Bad_Opcode },
3845     { "ucomisd",{ XM, EXq }, 0 },
3846   },
3847
3848   /* PREFIX_0F2F */
3849   {
3850     { "comiss", { XM, EXd }, 0 },
3851     { Bad_Opcode },
3852     { "comisd", { XM, EXq }, 0 },
3853   },
3854
3855   /* PREFIX_0F51 */
3856   {
3857     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3858     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3859     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3860     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3861   },
3862
3863   /* PREFIX_0F52 */
3864   {
3865     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3866     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3867   },
3868
3869   /* PREFIX_0F53 */
3870   {
3871     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3872     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3873   },
3874
3875   /* PREFIX_0F58 */
3876   {
3877     { "addps", { XM, EXx }, PREFIX_OPCODE },
3878     { "addss", { XM, EXd }, PREFIX_OPCODE },
3879     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3880     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3881   },
3882
3883   /* PREFIX_0F59 */
3884   {
3885     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3886     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3887     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3888     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3889   },
3890
3891   /* PREFIX_0F5A */
3892   {
3893     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3894     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3895     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3896     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3897   },
3898
3899   /* PREFIX_0F5B */
3900   {
3901     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3902     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3903     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3904   },
3905
3906   /* PREFIX_0F5C */
3907   {
3908     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3909     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3910     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3911     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3912   },
3913
3914   /* PREFIX_0F5D */
3915   {
3916     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3917     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3918     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3919     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3920   },
3921
3922   /* PREFIX_0F5E */
3923   {
3924     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3925     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3926     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3927     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3928   },
3929
3930   /* PREFIX_0F5F */
3931   {
3932     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3933     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3934     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3935     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3936   },
3937
3938   /* PREFIX_0F60 */
3939   {
3940     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3941     { Bad_Opcode },
3942     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3943   },
3944
3945   /* PREFIX_0F61 */
3946   {
3947     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3948     { Bad_Opcode },
3949     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3950   },
3951
3952   /* PREFIX_0F62 */
3953   {
3954     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3955     { Bad_Opcode },
3956     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3957   },
3958
3959   /* PREFIX_0F6C */
3960   {
3961     { Bad_Opcode },
3962     { Bad_Opcode },
3963     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0F6D */
3967   {
3968     { Bad_Opcode },
3969     { Bad_Opcode },
3970     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3971   },
3972
3973   /* PREFIX_0F6F */
3974   {
3975     { "movq",   { MX, EM }, PREFIX_OPCODE },
3976     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3977     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3978   },
3979
3980   /* PREFIX_0F70 */
3981   {
3982     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3983     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3984     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3985     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3986   },
3987
3988   /* PREFIX_0F73_REG_3 */
3989   {
3990     { Bad_Opcode },
3991     { Bad_Opcode },
3992     { "psrldq", { XS, Ib }, 0 },
3993   },
3994
3995   /* PREFIX_0F73_REG_7 */
3996   {
3997     { Bad_Opcode },
3998     { Bad_Opcode },
3999     { "pslldq", { XS, Ib }, 0 },
4000   },
4001
4002   /* PREFIX_0F78 */
4003   {
4004     {"vmread",  { Em, Gm }, 0 },
4005     { Bad_Opcode },
4006     {"extrq",   { XS, Ib, Ib }, 0 },
4007     {"insertq", { XM, XS, Ib, Ib }, 0 },
4008   },
4009
4010   /* PREFIX_0F79 */
4011   {
4012     {"vmwrite", { Gm, Em }, 0 },
4013     { Bad_Opcode },
4014     {"extrq",   { XM, XS }, 0 },
4015     {"insertq", { XM, XS }, 0 },
4016   },
4017
4018   /* PREFIX_0F7C */
4019   {
4020     { Bad_Opcode },
4021     { Bad_Opcode },
4022     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4023     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4024   },
4025
4026   /* PREFIX_0F7D */
4027   {
4028     { Bad_Opcode },
4029     { Bad_Opcode },
4030     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4031     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4032   },
4033
4034   /* PREFIX_0F7E */
4035   {
4036     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4037     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4038     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4039   },
4040
4041   /* PREFIX_0F7F */
4042   {
4043     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4044     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4045     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4046   },
4047
4048   /* PREFIX_0FAE_REG_0 */
4049   {
4050     { Bad_Opcode },
4051     { "rdfsbase", { Ev }, 0 },
4052   },
4053
4054   /* PREFIX_0FAE_REG_1 */
4055   {
4056     { Bad_Opcode },
4057     { "rdgsbase", { Ev }, 0 },
4058   },
4059
4060   /* PREFIX_0FAE_REG_2 */
4061   {
4062     { Bad_Opcode },
4063     { "wrfsbase", { Ev }, 0 },
4064   },
4065
4066   /* PREFIX_0FAE_REG_3 */
4067   {
4068     { Bad_Opcode },
4069     { "wrgsbase", { Ev }, 0 },
4070   },
4071
4072   /* PREFIX_MOD_0_0FAE_REG_4 */
4073   {
4074     { "xsave",  { FXSAVE }, 0 },
4075     { "ptwrite%LQ", { Edq }, 0 },
4076   },
4077
4078   /* PREFIX_MOD_3_0FAE_REG_4 */
4079   {
4080     { Bad_Opcode },
4081     { "ptwrite%LQ", { Edq }, 0 },
4082   },
4083
4084   /* PREFIX_0FAE_REG_6 */
4085   {
4086     { "xsaveopt",      { FXSAVE }, 0 },
4087     { Bad_Opcode },
4088     { "clwb",   { Mb }, 0 },
4089   },
4090
4091   /* PREFIX_0FAE_REG_7 */
4092   {
4093     { "clflush",        { Mb }, 0 },
4094     { Bad_Opcode },
4095     { "clflushopt",     { Mb }, 0 },
4096   },
4097
4098   /* PREFIX_0FB8 */
4099   {
4100     { Bad_Opcode },
4101     { "popcntS", { Gv, Ev }, 0 },
4102   },
4103
4104   /* PREFIX_0FBC */
4105   {
4106     { "bsfS",   { Gv, Ev }, 0 },
4107     { "tzcntS", { Gv, Ev }, 0 },
4108     { "bsfS",   { Gv, Ev }, 0 },
4109   },
4110
4111   /* PREFIX_0FBD */
4112   {
4113     { "bsrS",   { Gv, Ev }, 0 },
4114     { "lzcntS", { Gv, Ev }, 0 },
4115     { "bsrS",   { Gv, Ev }, 0 },
4116   },
4117
4118   /* PREFIX_0FC2 */
4119   {
4120     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4121     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4122     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4123     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4124   },
4125
4126   /* PREFIX_MOD_0_0FC3 */
4127   {
4128     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4129   },
4130
4131   /* PREFIX_MOD_0_0FC7_REG_6 */
4132   {
4133     { "vmptrld",{ Mq }, 0 },
4134     { "vmxon",  { Mq }, 0 },
4135     { "vmclear",{ Mq }, 0 },
4136   },
4137
4138   /* PREFIX_MOD_3_0FC7_REG_6 */
4139   {
4140     { "rdrand", { Ev }, 0 },
4141     { Bad_Opcode },
4142     { "rdrand", { Ev }, 0 }
4143   },
4144
4145   /* PREFIX_MOD_3_0FC7_REG_7 */
4146   {
4147     { "rdseed", { Ev }, 0 },
4148     { "rdpid",  { Em }, 0 },
4149     { "rdseed", { Ev }, 0 },
4150   },
4151
4152   /* PREFIX_0FD0 */
4153   {
4154     { Bad_Opcode },
4155     { Bad_Opcode },
4156     { "addsubpd", { XM, EXx }, 0 },
4157     { "addsubps", { XM, EXx }, 0 },
4158   },
4159
4160   /* PREFIX_0FD6 */
4161   {
4162     { Bad_Opcode },
4163     { "movq2dq",{ XM, MS }, 0 },
4164     { "movq",   { EXqS, XM }, 0 },
4165     { "movdq2q",{ MX, XS }, 0 },
4166   },
4167
4168   /* PREFIX_0FE6 */
4169   {
4170     { Bad_Opcode },
4171     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4172     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4173     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4174   },
4175
4176   /* PREFIX_0FE7 */
4177   {
4178     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4179     { Bad_Opcode },
4180     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4181   },
4182
4183   /* PREFIX_0FF0 */
4184   {
4185     { Bad_Opcode },
4186     { Bad_Opcode },
4187     { Bad_Opcode },
4188     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4189   },
4190
4191   /* PREFIX_0FF7 */
4192   {
4193     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4194     { Bad_Opcode },
4195     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4196   },
4197
4198   /* PREFIX_0F3810 */
4199   {
4200     { Bad_Opcode },
4201     { Bad_Opcode },
4202     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4203   },
4204
4205   /* PREFIX_0F3814 */
4206   {
4207     { Bad_Opcode },
4208     { Bad_Opcode },
4209     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4210   },
4211
4212   /* PREFIX_0F3815 */
4213   {
4214     { Bad_Opcode },
4215     { Bad_Opcode },
4216     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4217   },
4218
4219   /* PREFIX_0F3817 */
4220   {
4221     { Bad_Opcode },
4222     { Bad_Opcode },
4223     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4224   },
4225
4226   /* PREFIX_0F3820 */
4227   {
4228     { Bad_Opcode },
4229     { Bad_Opcode },
4230     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4231   },
4232
4233   /* PREFIX_0F3821 */
4234   {
4235     { Bad_Opcode },
4236     { Bad_Opcode },
4237     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4238   },
4239
4240   /* PREFIX_0F3822 */
4241   {
4242     { Bad_Opcode },
4243     { Bad_Opcode },
4244     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4245   },
4246
4247   /* PREFIX_0F3823 */
4248   {
4249     { Bad_Opcode },
4250     { Bad_Opcode },
4251     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4252   },
4253
4254   /* PREFIX_0F3824 */
4255   {
4256     { Bad_Opcode },
4257     { Bad_Opcode },
4258     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4259   },
4260
4261   /* PREFIX_0F3825 */
4262   {
4263     { Bad_Opcode },
4264     { Bad_Opcode },
4265     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4266   },
4267
4268   /* PREFIX_0F3828 */
4269   {
4270     { Bad_Opcode },
4271     { Bad_Opcode },
4272     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4273   },
4274
4275   /* PREFIX_0F3829 */
4276   {
4277     { Bad_Opcode },
4278     { Bad_Opcode },
4279     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4280   },
4281
4282   /* PREFIX_0F382A */
4283   {
4284     { Bad_Opcode },
4285     { Bad_Opcode },
4286     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4287   },
4288
4289   /* PREFIX_0F382B */
4290   {
4291     { Bad_Opcode },
4292     { Bad_Opcode },
4293     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4294   },
4295
4296   /* PREFIX_0F3830 */
4297   {
4298     { Bad_Opcode },
4299     { Bad_Opcode },
4300     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4301   },
4302
4303   /* PREFIX_0F3831 */
4304   {
4305     { Bad_Opcode },
4306     { Bad_Opcode },
4307     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4308   },
4309
4310   /* PREFIX_0F3832 */
4311   {
4312     { Bad_Opcode },
4313     { Bad_Opcode },
4314     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4315   },
4316
4317   /* PREFIX_0F3833 */
4318   {
4319     { Bad_Opcode },
4320     { Bad_Opcode },
4321     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4322   },
4323
4324   /* PREFIX_0F3834 */
4325   {
4326     { Bad_Opcode },
4327     { Bad_Opcode },
4328     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4329   },
4330
4331   /* PREFIX_0F3835 */
4332   {
4333     { Bad_Opcode },
4334     { Bad_Opcode },
4335     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4336   },
4337
4338   /* PREFIX_0F3837 */
4339   {
4340     { Bad_Opcode },
4341     { Bad_Opcode },
4342     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4343   },
4344
4345   /* PREFIX_0F3838 */
4346   {
4347     { Bad_Opcode },
4348     { Bad_Opcode },
4349     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4350   },
4351
4352   /* PREFIX_0F3839 */
4353   {
4354     { Bad_Opcode },
4355     { Bad_Opcode },
4356     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4357   },
4358
4359   /* PREFIX_0F383A */
4360   {
4361     { Bad_Opcode },
4362     { Bad_Opcode },
4363     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F383B */
4367   {
4368     { Bad_Opcode },
4369     { Bad_Opcode },
4370     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4371   },
4372
4373   /* PREFIX_0F383C */
4374   {
4375     { Bad_Opcode },
4376     { Bad_Opcode },
4377     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4378   },
4379
4380   /* PREFIX_0F383D */
4381   {
4382     { Bad_Opcode },
4383     { Bad_Opcode },
4384     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4385   },
4386
4387   /* PREFIX_0F383E */
4388   {
4389     { Bad_Opcode },
4390     { Bad_Opcode },
4391     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4392   },
4393
4394   /* PREFIX_0F383F */
4395   {
4396     { Bad_Opcode },
4397     { Bad_Opcode },
4398     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4399   },
4400
4401   /* PREFIX_0F3840 */
4402   {
4403     { Bad_Opcode },
4404     { Bad_Opcode },
4405     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F3841 */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F3880 */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F3881 */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F3882 */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F38C8 */
4437   {
4438     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38C9 */
4442   {
4443     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4444   },
4445
4446   /* PREFIX_0F38CA */
4447   {
4448     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4449   },
4450
4451   /* PREFIX_0F38CB */
4452   {
4453     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4454   },
4455
4456   /* PREFIX_0F38CC */
4457   {
4458     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4459   },
4460
4461   /* PREFIX_0F38CD */
4462   {
4463     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F38DB */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4471   },
4472
4473   /* PREFIX_0F38DC */
4474   {
4475     { Bad_Opcode },
4476     { Bad_Opcode },
4477     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4478   },
4479
4480   /* PREFIX_0F38DD */
4481   {
4482     { Bad_Opcode },
4483     { Bad_Opcode },
4484     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4485   },
4486
4487   /* PREFIX_0F38DE */
4488   {
4489     { Bad_Opcode },
4490     { Bad_Opcode },
4491     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4492   },
4493
4494   /* PREFIX_0F38DF */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F38F0 */
4502   {
4503     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4504     { Bad_Opcode },
4505     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4506     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4507   },
4508
4509   /* PREFIX_0F38F1 */
4510   {
4511     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4512     { Bad_Opcode },
4513     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4514     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4515   },
4516
4517   /* PREFIX_0F38F6 */
4518   {
4519     { Bad_Opcode },
4520     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4521     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4522     { Bad_Opcode },
4523   },
4524
4525   /* PREFIX_0F3A08 */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F3A09 */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F3A0A */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F3A0B */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3A0C */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3A0D */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3A0E */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3A14 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3A15 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F3A16 */
4589   {
4590     { Bad_Opcode },
4591     { Bad_Opcode },
4592     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4593   },
4594
4595   /* PREFIX_0F3A17 */
4596   {
4597     { Bad_Opcode },
4598     { Bad_Opcode },
4599     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4600   },
4601
4602   /* PREFIX_0F3A20 */
4603   {
4604     { Bad_Opcode },
4605     { Bad_Opcode },
4606     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4607   },
4608
4609   /* PREFIX_0F3A21 */
4610   {
4611     { Bad_Opcode },
4612     { Bad_Opcode },
4613     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4614   },
4615
4616   /* PREFIX_0F3A22 */
4617   {
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4621   },
4622
4623   /* PREFIX_0F3A40 */
4624   {
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4628   },
4629
4630   /* PREFIX_0F3A41 */
4631   {
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4635   },
4636
4637   /* PREFIX_0F3A42 */
4638   {
4639     { Bad_Opcode },
4640     { Bad_Opcode },
4641     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4642   },
4643
4644   /* PREFIX_0F3A44 */
4645   {
4646     { Bad_Opcode },
4647     { Bad_Opcode },
4648     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4649   },
4650
4651   /* PREFIX_0F3A60 */
4652   {
4653     { Bad_Opcode },
4654     { Bad_Opcode },
4655     { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4656   },
4657
4658   /* PREFIX_0F3A61 */
4659   {
4660     { Bad_Opcode },
4661     { Bad_Opcode },
4662     { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE },
4663   },
4664
4665   /* PREFIX_0F3A62 */
4666   {
4667     { Bad_Opcode },
4668     { Bad_Opcode },
4669     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4670   },
4671
4672   /* PREFIX_0F3A63 */
4673   {
4674     { Bad_Opcode },
4675     { Bad_Opcode },
4676     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4677   },
4678
4679   /* PREFIX_0F3ACC */
4680   {
4681     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4682   },
4683
4684   /* PREFIX_0F3ADF */
4685   {
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4689   },
4690
4691   /* PREFIX_VEX_0F10 */
4692   {
4693     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4694     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4695     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4696     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4697   },
4698
4699   /* PREFIX_VEX_0F11 */
4700   {
4701     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4702     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4703     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4704     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4705   },
4706
4707   /* PREFIX_VEX_0F12 */
4708   {
4709     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4710     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4711     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4712     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4713   },
4714
4715   /* PREFIX_VEX_0F16 */
4716   {
4717     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4718     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4719     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4720   },
4721
4722   /* PREFIX_VEX_0F2A */
4723   {
4724     { Bad_Opcode },
4725     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4726     { Bad_Opcode },
4727     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4728   },
4729
4730   /* PREFIX_VEX_0F2C */
4731   {
4732     { Bad_Opcode },
4733     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4734     { Bad_Opcode },
4735     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4736   },
4737
4738   /* PREFIX_VEX_0F2D */
4739   {
4740     { Bad_Opcode },
4741     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4742     { Bad_Opcode },
4743     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4744   },
4745
4746   /* PREFIX_VEX_0F2E */
4747   {
4748     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4749     { Bad_Opcode },
4750     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4751   },
4752
4753   /* PREFIX_VEX_0F2F */
4754   {
4755     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4756     { Bad_Opcode },
4757     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4758   },
4759
4760   /* PREFIX_VEX_0F41 */
4761   {
4762     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4763     { Bad_Opcode },
4764     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4765   },
4766
4767   /* PREFIX_VEX_0F42 */
4768   {
4769     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4770     { Bad_Opcode },
4771     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4772   },
4773
4774   /* PREFIX_VEX_0F44 */
4775   {
4776     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4777     { Bad_Opcode },
4778     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4779   },
4780
4781   /* PREFIX_VEX_0F45 */
4782   {
4783     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4784     { Bad_Opcode },
4785     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4786   },
4787
4788   /* PREFIX_VEX_0F46 */
4789   {
4790     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4791     { Bad_Opcode },
4792     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4793   },
4794
4795   /* PREFIX_VEX_0F47 */
4796   {
4797     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4798     { Bad_Opcode },
4799     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4800   },
4801
4802   /* PREFIX_VEX_0F4A */
4803   {
4804     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4805     { Bad_Opcode },
4806     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4807   },
4808
4809   /* PREFIX_VEX_0F4B */
4810   {
4811     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4812     { Bad_Opcode },
4813     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4814   },
4815
4816   /* PREFIX_VEX_0F51 */
4817   {
4818     { VEX_W_TABLE (VEX_W_0F51_P_0) },
4819     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4820     { VEX_W_TABLE (VEX_W_0F51_P_2) },
4821     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4822   },
4823
4824   /* PREFIX_VEX_0F52 */
4825   {
4826     { VEX_W_TABLE (VEX_W_0F52_P_0) },
4827     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4828   },
4829
4830   /* PREFIX_VEX_0F53 */
4831   {
4832     { VEX_W_TABLE (VEX_W_0F53_P_0) },
4833     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4834   },
4835
4836   /* PREFIX_VEX_0F58 */
4837   {
4838     { VEX_W_TABLE (VEX_W_0F58_P_0) },
4839     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4840     { VEX_W_TABLE (VEX_W_0F58_P_2) },
4841     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4842   },
4843
4844   /* PREFIX_VEX_0F59 */
4845   {
4846     { VEX_W_TABLE (VEX_W_0F59_P_0) },
4847     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4848     { VEX_W_TABLE (VEX_W_0F59_P_2) },
4849     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4850   },
4851
4852   /* PREFIX_VEX_0F5A */
4853   {
4854     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4855     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4856     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4857     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4858   },
4859
4860   /* PREFIX_VEX_0F5B */
4861   {
4862     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4863     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4864     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4865   },
4866
4867   /* PREFIX_VEX_0F5C */
4868   {
4869     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4870     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4871     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4872     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4873   },
4874
4875   /* PREFIX_VEX_0F5D */
4876   {
4877     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4878     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4879     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4880     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4881   },
4882
4883   /* PREFIX_VEX_0F5E */
4884   {
4885     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4887     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4888     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4889   },
4890
4891   /* PREFIX_VEX_0F5F */
4892   {
4893     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4895     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4896     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4897   },
4898
4899   /* PREFIX_VEX_0F60 */
4900   {
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { VEX_W_TABLE (VEX_W_0F60_P_2) },
4904   },
4905
4906   /* PREFIX_VEX_0F61 */
4907   {
4908     { Bad_Opcode },
4909     { Bad_Opcode },
4910     { VEX_W_TABLE (VEX_W_0F61_P_2) },
4911   },
4912
4913   /* PREFIX_VEX_0F62 */
4914   {
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { VEX_W_TABLE (VEX_W_0F62_P_2) },
4918   },
4919
4920   /* PREFIX_VEX_0F63 */
4921   {
4922     { Bad_Opcode },
4923     { Bad_Opcode },
4924     { VEX_W_TABLE (VEX_W_0F63_P_2) },
4925   },
4926
4927   /* PREFIX_VEX_0F64 */
4928   {
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { VEX_W_TABLE (VEX_W_0F64_P_2) },
4932   },
4933
4934   /* PREFIX_VEX_0F65 */
4935   {
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { VEX_W_TABLE (VEX_W_0F65_P_2) },
4939   },
4940
4941   /* PREFIX_VEX_0F66 */
4942   {
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { VEX_W_TABLE (VEX_W_0F66_P_2) },
4946   },
4947
4948   /* PREFIX_VEX_0F67 */
4949   {
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { VEX_W_TABLE (VEX_W_0F67_P_2) },
4953   },
4954
4955   /* PREFIX_VEX_0F68 */
4956   {
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { VEX_W_TABLE (VEX_W_0F68_P_2) },
4960   },
4961
4962   /* PREFIX_VEX_0F69 */
4963   {
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { VEX_W_TABLE (VEX_W_0F69_P_2) },
4967   },
4968
4969   /* PREFIX_VEX_0F6A */
4970   {
4971     { Bad_Opcode },
4972     { Bad_Opcode },
4973     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4974   },
4975
4976   /* PREFIX_VEX_0F6B */
4977   {
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4981   },
4982
4983   /* PREFIX_VEX_0F6C */
4984   {
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4988   },
4989
4990   /* PREFIX_VEX_0F6D */
4991   {
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4995   },
4996
4997   /* PREFIX_VEX_0F6E */
4998   {
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5002   },
5003
5004   /* PREFIX_VEX_0F6F */
5005   {
5006     { Bad_Opcode },
5007     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5008     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5009   },
5010
5011   /* PREFIX_VEX_0F70 */
5012   {
5013     { Bad_Opcode },
5014     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5015     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5016     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5017   },
5018
5019   /* PREFIX_VEX_0F71_REG_2 */
5020   {
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5024   },
5025
5026   /* PREFIX_VEX_0F71_REG_4 */
5027   {
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5031   },
5032
5033   /* PREFIX_VEX_0F71_REG_6 */
5034   {
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5038   },
5039
5040   /* PREFIX_VEX_0F72_REG_2 */
5041   {
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5045   },
5046
5047   /* PREFIX_VEX_0F72_REG_4 */
5048   {
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5052   },
5053
5054   /* PREFIX_VEX_0F72_REG_6 */
5055   {
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5059   },
5060
5061   /* PREFIX_VEX_0F73_REG_2 */
5062   {
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5066   },
5067
5068   /* PREFIX_VEX_0F73_REG_3 */
5069   {
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5073   },
5074
5075   /* PREFIX_VEX_0F73_REG_6 */
5076   {
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5080   },
5081
5082   /* PREFIX_VEX_0F73_REG_7 */
5083   {
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5087   },
5088
5089   /* PREFIX_VEX_0F74 */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5094   },
5095
5096   /* PREFIX_VEX_0F75 */
5097   {
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5101   },
5102
5103   /* PREFIX_VEX_0F76 */
5104   {
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5108   },
5109
5110   /* PREFIX_VEX_0F77 */
5111   {
5112     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5113   },
5114
5115   /* PREFIX_VEX_0F7C */
5116   {
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5120     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5121   },
5122
5123   /* PREFIX_VEX_0F7D */
5124   {
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5128     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5129   },
5130
5131   /* PREFIX_VEX_0F7E */
5132   {
5133     { Bad_Opcode },
5134     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5135     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5136   },
5137
5138   /* PREFIX_VEX_0F7F */
5139   {
5140     { Bad_Opcode },
5141     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5142     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5143   },
5144
5145   /* PREFIX_VEX_0F90 */
5146   {
5147     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5148     { Bad_Opcode },
5149     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5150   },
5151
5152   /* PREFIX_VEX_0F91 */
5153   {
5154     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5155     { Bad_Opcode },
5156     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5157   },
5158
5159   /* PREFIX_VEX_0F92 */
5160   {
5161     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5162     { Bad_Opcode },
5163     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5164     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5165   },
5166
5167   /* PREFIX_VEX_0F93 */
5168   {
5169     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5170     { Bad_Opcode },
5171     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5172     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5173   },
5174
5175   /* PREFIX_VEX_0F98 */
5176   {
5177     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5178     { Bad_Opcode },
5179     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F99 */
5183   {
5184     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5185     { Bad_Opcode },
5186     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0FC2 */
5190   {
5191     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5192     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5193     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5194     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5195   },
5196
5197   /* PREFIX_VEX_0FC4 */
5198   {
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5202   },
5203
5204   /* PREFIX_VEX_0FC5 */
5205   {
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5209   },
5210
5211   /* PREFIX_VEX_0FD0 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5216     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5217   },
5218
5219   /* PREFIX_VEX_0FD1 */
5220   {
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5224   },
5225
5226   /* PREFIX_VEX_0FD2 */
5227   {
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5231   },
5232
5233   /* PREFIX_VEX_0FD3 */
5234   {
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5238   },
5239
5240   /* PREFIX_VEX_0FD4 */
5241   {
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5245   },
5246
5247   /* PREFIX_VEX_0FD5 */
5248   {
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5252   },
5253
5254   /* PREFIX_VEX_0FD6 */
5255   {
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5259   },
5260
5261   /* PREFIX_VEX_0FD7 */
5262   {
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5266   },
5267
5268   /* PREFIX_VEX_0FD8 */
5269   {
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5273   },
5274
5275   /* PREFIX_VEX_0FD9 */
5276   {
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5280   },
5281
5282   /* PREFIX_VEX_0FDA */
5283   {
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5287   },
5288
5289   /* PREFIX_VEX_0FDB */
5290   {
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5294   },
5295
5296   /* PREFIX_VEX_0FDC */
5297   {
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5301   },
5302
5303   /* PREFIX_VEX_0FDD */
5304   {
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5308   },
5309
5310   /* PREFIX_VEX_0FDE */
5311   {
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5315   },
5316
5317   /* PREFIX_VEX_0FDF */
5318   {
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5322   },
5323
5324   /* PREFIX_VEX_0FE0 */
5325   {
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5329   },
5330
5331   /* PREFIX_VEX_0FE1 */
5332   {
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5336   },
5337
5338   /* PREFIX_VEX_0FE2 */
5339   {
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5343   },
5344
5345   /* PREFIX_VEX_0FE3 */
5346   {
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5350   },
5351
5352   /* PREFIX_VEX_0FE4 */
5353   {
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5357   },
5358
5359   /* PREFIX_VEX_0FE5 */
5360   {
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5364   },
5365
5366   /* PREFIX_VEX_0FE6 */
5367   {
5368     { Bad_Opcode },
5369     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5370     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5371     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5372   },
5373
5374   /* PREFIX_VEX_0FE7 */
5375   {
5376     { Bad_Opcode },
5377     { Bad_Opcode },
5378     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5379   },
5380
5381   /* PREFIX_VEX_0FE8 */
5382   {
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5386   },
5387
5388   /* PREFIX_VEX_0FE9 */
5389   {
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5393   },
5394
5395   /* PREFIX_VEX_0FEA */
5396   {
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5400   },
5401
5402   /* PREFIX_VEX_0FEB */
5403   {
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5407   },
5408
5409   /* PREFIX_VEX_0FEC */
5410   {
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5414   },
5415
5416   /* PREFIX_VEX_0FED */
5417   {
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5421   },
5422
5423   /* PREFIX_VEX_0FEE */
5424   {
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5428   },
5429
5430   /* PREFIX_VEX_0FEF */
5431   {
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5435   },
5436
5437   /* PREFIX_VEX_0FF0 */
5438   {
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5443   },
5444
5445   /* PREFIX_VEX_0FF1 */
5446   {
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5450   },
5451
5452   /* PREFIX_VEX_0FF2 */
5453   {
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5457   },
5458
5459   /* PREFIX_VEX_0FF3 */
5460   {
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5464   },
5465
5466   /* PREFIX_VEX_0FF4 */
5467   {
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5471   },
5472
5473   /* PREFIX_VEX_0FF5 */
5474   {
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5478   },
5479
5480   /* PREFIX_VEX_0FF6 */
5481   {
5482     { Bad_Opcode },
5483     { Bad_Opcode },
5484     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5485   },
5486
5487   /* PREFIX_VEX_0FF7 */
5488   {
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5492   },
5493
5494   /* PREFIX_VEX_0FF8 */
5495   {
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5499   },
5500
5501   /* PREFIX_VEX_0FF9 */
5502   {
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5506   },
5507
5508   /* PREFIX_VEX_0FFA */
5509   {
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5513   },
5514
5515   /* PREFIX_VEX_0FFB */
5516   {
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5520   },
5521
5522   /* PREFIX_VEX_0FFC */
5523   {
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5527   },
5528
5529   /* PREFIX_VEX_0FFD */
5530   {
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5534   },
5535
5536   /* PREFIX_VEX_0FFE */
5537   {
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5541   },
5542
5543   /* PREFIX_VEX_0F3800 */
5544   {
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5548   },
5549
5550   /* PREFIX_VEX_0F3801 */
5551   {
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5555   },
5556
5557   /* PREFIX_VEX_0F3802 */
5558   {
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5562   },
5563
5564   /* PREFIX_VEX_0F3803 */
5565   {
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5569   },
5570
5571   /* PREFIX_VEX_0F3804 */
5572   {
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5576   },
5577
5578   /* PREFIX_VEX_0F3805 */
5579   {
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5583   },
5584
5585   /* PREFIX_VEX_0F3806 */
5586   {
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5590   },
5591
5592   /* PREFIX_VEX_0F3807 */
5593   {
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5597   },
5598
5599   /* PREFIX_VEX_0F3808 */
5600   {
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5604   },
5605
5606   /* PREFIX_VEX_0F3809 */
5607   {
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5611   },
5612
5613   /* PREFIX_VEX_0F380A */
5614   {
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5618   },
5619
5620   /* PREFIX_VEX_0F380B */
5621   {
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5625   },
5626
5627   /* PREFIX_VEX_0F380C */
5628   {
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5632   },
5633
5634   /* PREFIX_VEX_0F380D */
5635   {
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5639   },
5640
5641   /* PREFIX_VEX_0F380E */
5642   {
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5646   },
5647
5648   /* PREFIX_VEX_0F380F */
5649   {
5650     { Bad_Opcode },
5651     { Bad_Opcode },
5652     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5653   },
5654
5655   /* PREFIX_VEX_0F3813 */
5656   {
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5660   },
5661
5662   /* PREFIX_VEX_0F3816 */
5663   {
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5667   },
5668
5669   /* PREFIX_VEX_0F3817 */
5670   {
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5674   },
5675
5676   /* PREFIX_VEX_0F3818 */
5677   {
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5681   },
5682
5683   /* PREFIX_VEX_0F3819 */
5684   {
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5688   },
5689
5690   /* PREFIX_VEX_0F381A */
5691   {
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5695   },
5696
5697   /* PREFIX_VEX_0F381C */
5698   {
5699     { Bad_Opcode },
5700     { Bad_Opcode },
5701     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5702   },
5703
5704   /* PREFIX_VEX_0F381D */
5705   {
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5709   },
5710
5711   /* PREFIX_VEX_0F381E */
5712   {
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5716   },
5717
5718   /* PREFIX_VEX_0F3820 */
5719   {
5720     { Bad_Opcode },
5721     { Bad_Opcode },
5722     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5723   },
5724
5725   /* PREFIX_VEX_0F3821 */
5726   {
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5730   },
5731
5732   /* PREFIX_VEX_0F3822 */
5733   {
5734     { Bad_Opcode },
5735     { Bad_Opcode },
5736     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5737   },
5738
5739   /* PREFIX_VEX_0F3823 */
5740   {
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5744   },
5745
5746   /* PREFIX_VEX_0F3824 */
5747   {
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5751   },
5752
5753   /* PREFIX_VEX_0F3825 */
5754   {
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5758   },
5759
5760   /* PREFIX_VEX_0F3828 */
5761   {
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5765   },
5766
5767   /* PREFIX_VEX_0F3829 */
5768   {
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5772   },
5773
5774   /* PREFIX_VEX_0F382A */
5775   {
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5779   },
5780
5781   /* PREFIX_VEX_0F382B */
5782   {
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5786   },
5787
5788   /* PREFIX_VEX_0F382C */
5789   {
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5793   },
5794
5795   /* PREFIX_VEX_0F382D */
5796   {
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5800   },
5801
5802   /* PREFIX_VEX_0F382E */
5803   {
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5807   },
5808
5809   /* PREFIX_VEX_0F382F */
5810   {
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5814   },
5815
5816   /* PREFIX_VEX_0F3830 */
5817   {
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5821   },
5822
5823   /* PREFIX_VEX_0F3831 */
5824   {
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5828   },
5829
5830   /* PREFIX_VEX_0F3832 */
5831   {
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5835   },
5836
5837   /* PREFIX_VEX_0F3833 */
5838   {
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5842   },
5843
5844   /* PREFIX_VEX_0F3834 */
5845   {
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5849   },
5850
5851   /* PREFIX_VEX_0F3835 */
5852   {
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5856   },
5857
5858   /* PREFIX_VEX_0F3836 */
5859   {
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5863   },
5864
5865   /* PREFIX_VEX_0F3837 */
5866   {
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5870   },
5871
5872   /* PREFIX_VEX_0F3838 */
5873   {
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5877   },
5878
5879   /* PREFIX_VEX_0F3839 */
5880   {
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5884   },
5885
5886   /* PREFIX_VEX_0F383A */
5887   {
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5891   },
5892
5893   /* PREFIX_VEX_0F383B */
5894   {
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5898   },
5899
5900   /* PREFIX_VEX_0F383C */
5901   {
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5905   },
5906
5907   /* PREFIX_VEX_0F383D */
5908   {
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5912   },
5913
5914   /* PREFIX_VEX_0F383E */
5915   {
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5919   },
5920
5921   /* PREFIX_VEX_0F383F */
5922   {
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5926   },
5927
5928   /* PREFIX_VEX_0F3840 */
5929   {
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5933   },
5934
5935   /* PREFIX_VEX_0F3841 */
5936   {
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5940   },
5941
5942   /* PREFIX_VEX_0F3845 */
5943   {
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5947   },
5948
5949   /* PREFIX_VEX_0F3846 */
5950   {
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5954   },
5955
5956   /* PREFIX_VEX_0F3847 */
5957   {
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5961   },
5962
5963   /* PREFIX_VEX_0F3858 */
5964   {
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5968   },
5969
5970   /* PREFIX_VEX_0F3859 */
5971   {
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5975   },
5976
5977   /* PREFIX_VEX_0F385A */
5978   {
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5982   },
5983
5984   /* PREFIX_VEX_0F3878 */
5985   {
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5989   },
5990
5991   /* PREFIX_VEX_0F3879 */
5992   {
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5996   },
5997
5998   /* PREFIX_VEX_0F388C */
5999   {
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6003   },
6004
6005   /* PREFIX_VEX_0F388E */
6006   {
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6010   },
6011
6012   /* PREFIX_VEX_0F3890 */
6013   {
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6017   },
6018
6019   /* PREFIX_VEX_0F3891 */
6020   {
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6024   },
6025
6026   /* PREFIX_VEX_0F3892 */
6027   {
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6031   },
6032
6033   /* PREFIX_VEX_0F3893 */
6034   {
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6038   },
6039
6040   /* PREFIX_VEX_0F3896 */
6041   {
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6045   },
6046
6047   /* PREFIX_VEX_0F3897 */
6048   {
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6052   },
6053
6054   /* PREFIX_VEX_0F3898 */
6055   {
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6059   },
6060
6061   /* PREFIX_VEX_0F3899 */
6062   {
6063     { Bad_Opcode },
6064     { Bad_Opcode },
6065     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6066   },
6067
6068   /* PREFIX_VEX_0F389A */
6069   {
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6073   },
6074
6075   /* PREFIX_VEX_0F389B */
6076   {
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6080   },
6081
6082   /* PREFIX_VEX_0F389C */
6083   {
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6087   },
6088
6089   /* PREFIX_VEX_0F389D */
6090   {
6091     { Bad_Opcode },
6092     { Bad_Opcode },
6093     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6094   },
6095
6096   /* PREFIX_VEX_0F389E */
6097   {
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6101   },
6102
6103   /* PREFIX_VEX_0F389F */
6104   {
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6108   },
6109
6110   /* PREFIX_VEX_0F38A6 */
6111   {
6112     { Bad_Opcode },
6113     { Bad_Opcode },
6114     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6115     { Bad_Opcode },
6116   },
6117
6118   /* PREFIX_VEX_0F38A7 */
6119   {
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6123   },
6124
6125   /* PREFIX_VEX_0F38A8 */
6126   {
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6130   },
6131
6132   /* PREFIX_VEX_0F38A9 */
6133   {
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6137   },
6138
6139   /* PREFIX_VEX_0F38AA */
6140   {
6141     { Bad_Opcode },
6142     { Bad_Opcode },
6143     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6144   },
6145
6146   /* PREFIX_VEX_0F38AB */
6147   {
6148     { Bad_Opcode },
6149     { Bad_Opcode },
6150     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6151   },
6152
6153   /* PREFIX_VEX_0F38AC */
6154   {
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6158   },
6159
6160   /* PREFIX_VEX_0F38AD */
6161   {
6162     { Bad_Opcode },
6163     { Bad_Opcode },
6164     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6165   },
6166
6167   /* PREFIX_VEX_0F38AE */
6168   {
6169     { Bad_Opcode },
6170     { Bad_Opcode },
6171     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6172   },
6173
6174   /* PREFIX_VEX_0F38AF */
6175   {
6176     { Bad_Opcode },
6177     { Bad_Opcode },
6178     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6179   },
6180
6181   /* PREFIX_VEX_0F38B6 */
6182   {
6183     { Bad_Opcode },
6184     { Bad_Opcode },
6185     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6186   },
6187
6188   /* PREFIX_VEX_0F38B7 */
6189   {
6190     { Bad_Opcode },
6191     { Bad_Opcode },
6192     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6193   },
6194
6195   /* PREFIX_VEX_0F38B8 */
6196   {
6197     { Bad_Opcode },
6198     { Bad_Opcode },
6199     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6200   },
6201
6202   /* PREFIX_VEX_0F38B9 */
6203   {
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6207   },
6208
6209   /* PREFIX_VEX_0F38BA */
6210   {
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6214   },
6215
6216   /* PREFIX_VEX_0F38BB */
6217   {
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6221   },
6222
6223   /* PREFIX_VEX_0F38BC */
6224   {
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6228   },
6229
6230   /* PREFIX_VEX_0F38BD */
6231   {
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6235   },
6236
6237   /* PREFIX_VEX_0F38BE */
6238   {
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6242   },
6243
6244   /* PREFIX_VEX_0F38BF */
6245   {
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6249   },
6250
6251   /* PREFIX_VEX_0F38DB */
6252   {
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6256   },
6257
6258   /* PREFIX_VEX_0F38DC */
6259   {
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6263   },
6264
6265   /* PREFIX_VEX_0F38DD */
6266   {
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6270   },
6271
6272   /* PREFIX_VEX_0F38DE */
6273   {
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6277   },
6278
6279   /* PREFIX_VEX_0F38DF */
6280   {
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F2 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F3_REG_1 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6294   },
6295
6296   /* PREFIX_VEX_0F38F3_REG_2 */
6297   {
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6299   },
6300
6301   /* PREFIX_VEX_0F38F3_REG_3 */
6302   {
6303     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6304   },
6305
6306   /* PREFIX_VEX_0F38F5 */
6307   {
6308     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6310     { Bad_Opcode },
6311     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6312   },
6313
6314   /* PREFIX_VEX_0F38F6 */
6315   {
6316     { Bad_Opcode },
6317     { Bad_Opcode },
6318     { Bad_Opcode },
6319     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6320   },
6321
6322   /* PREFIX_VEX_0F38F7 */
6323   {
6324     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6325     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6326     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6327     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6328   },
6329
6330   /* PREFIX_VEX_0F3A00 */
6331   {
6332     { Bad_Opcode },
6333     { Bad_Opcode },
6334     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6335   },
6336
6337   /* PREFIX_VEX_0F3A01 */
6338   {
6339     { Bad_Opcode },
6340     { Bad_Opcode },
6341     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6342   },
6343
6344   /* PREFIX_VEX_0F3A02 */
6345   {
6346     { Bad_Opcode },
6347     { Bad_Opcode },
6348     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6349   },
6350
6351   /* PREFIX_VEX_0F3A04 */
6352   {
6353     { Bad_Opcode },
6354     { Bad_Opcode },
6355     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6356   },
6357
6358   /* PREFIX_VEX_0F3A05 */
6359   {
6360     { Bad_Opcode },
6361     { Bad_Opcode },
6362     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6363   },
6364
6365   /* PREFIX_VEX_0F3A06 */
6366   {
6367     { Bad_Opcode },
6368     { Bad_Opcode },
6369     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6370   },
6371
6372   /* PREFIX_VEX_0F3A08 */
6373   {
6374     { Bad_Opcode },
6375     { Bad_Opcode },
6376     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6377   },
6378
6379   /* PREFIX_VEX_0F3A09 */
6380   {
6381     { Bad_Opcode },
6382     { Bad_Opcode },
6383     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6384   },
6385
6386   /* PREFIX_VEX_0F3A0A */
6387   {
6388     { Bad_Opcode },
6389     { Bad_Opcode },
6390     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6391   },
6392
6393   /* PREFIX_VEX_0F3A0B */
6394   {
6395     { Bad_Opcode },
6396     { Bad_Opcode },
6397     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6398   },
6399
6400   /* PREFIX_VEX_0F3A0C */
6401   {
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6405   },
6406
6407   /* PREFIX_VEX_0F3A0D */
6408   {
6409     { Bad_Opcode },
6410     { Bad_Opcode },
6411     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6412   },
6413
6414   /* PREFIX_VEX_0F3A0E */
6415   {
6416     { Bad_Opcode },
6417     { Bad_Opcode },
6418     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6419   },
6420
6421   /* PREFIX_VEX_0F3A0F */
6422   {
6423     { Bad_Opcode },
6424     { Bad_Opcode },
6425     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6426   },
6427
6428   /* PREFIX_VEX_0F3A14 */
6429   {
6430     { Bad_Opcode },
6431     { Bad_Opcode },
6432     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6433   },
6434
6435   /* PREFIX_VEX_0F3A15 */
6436   {
6437     { Bad_Opcode },
6438     { Bad_Opcode },
6439     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6440   },
6441
6442   /* PREFIX_VEX_0F3A16 */
6443   {
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6447   },
6448
6449   /* PREFIX_VEX_0F3A17 */
6450   {
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6454   },
6455
6456   /* PREFIX_VEX_0F3A18 */
6457   {
6458     { Bad_Opcode },
6459     { Bad_Opcode },
6460     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6461   },
6462
6463   /* PREFIX_VEX_0F3A19 */
6464   {
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6468   },
6469
6470   /* PREFIX_VEX_0F3A1D */
6471   {
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6475   },
6476
6477   /* PREFIX_VEX_0F3A20 */
6478   {
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6482   },
6483
6484   /* PREFIX_VEX_0F3A21 */
6485   {
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6489   },
6490
6491   /* PREFIX_VEX_0F3A22 */
6492   {
6493     { Bad_Opcode },
6494     { Bad_Opcode },
6495     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6496   },
6497
6498   /* PREFIX_VEX_0F3A30 */
6499   {
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6503   },
6504
6505   /* PREFIX_VEX_0F3A31 */
6506   {
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6510   },
6511
6512   /* PREFIX_VEX_0F3A32 */
6513   {
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6517   },
6518
6519   /* PREFIX_VEX_0F3A33 */
6520   {
6521     { Bad_Opcode },
6522     { Bad_Opcode },
6523     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6524   },
6525
6526   /* PREFIX_VEX_0F3A38 */
6527   {
6528     { Bad_Opcode },
6529     { Bad_Opcode },
6530     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6531   },
6532
6533   /* PREFIX_VEX_0F3A39 */
6534   {
6535     { Bad_Opcode },
6536     { Bad_Opcode },
6537     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6538   },
6539
6540   /* PREFIX_VEX_0F3A40 */
6541   {
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6545   },
6546
6547   /* PREFIX_VEX_0F3A41 */
6548   {
6549     { Bad_Opcode },
6550     { Bad_Opcode },
6551     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6552   },
6553
6554   /* PREFIX_VEX_0F3A42 */
6555   {
6556     { Bad_Opcode },
6557     { Bad_Opcode },
6558     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6559   },
6560
6561   /* PREFIX_VEX_0F3A44 */
6562   {
6563     { Bad_Opcode },
6564     { Bad_Opcode },
6565     { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6566   },
6567
6568   /* PREFIX_VEX_0F3A46 */
6569   {
6570     { Bad_Opcode },
6571     { Bad_Opcode },
6572     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6573   },
6574
6575   /* PREFIX_VEX_0F3A48 */
6576   {
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6580   },
6581
6582   /* PREFIX_VEX_0F3A49 */
6583   {
6584     { Bad_Opcode },
6585     { Bad_Opcode },
6586     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6587   },
6588
6589   /* PREFIX_VEX_0F3A4A */
6590   {
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6594   },
6595
6596   /* PREFIX_VEX_0F3A4B */
6597   {
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6601   },
6602
6603   /* PREFIX_VEX_0F3A4C */
6604   {
6605     { Bad_Opcode },
6606     { Bad_Opcode },
6607     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6608   },
6609
6610   /* PREFIX_VEX_0F3A5C */
6611   {
6612     { Bad_Opcode },
6613     { Bad_Opcode },
6614     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6615   },
6616
6617   /* PREFIX_VEX_0F3A5D */
6618   {
6619     { Bad_Opcode },
6620     { Bad_Opcode },
6621     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6622   },
6623
6624   /* PREFIX_VEX_0F3A5E */
6625   {
6626     { Bad_Opcode },
6627     { Bad_Opcode },
6628     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6629   },
6630
6631   /* PREFIX_VEX_0F3A5F */
6632   {
6633     { Bad_Opcode },
6634     { Bad_Opcode },
6635     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6636   },
6637
6638   /* PREFIX_VEX_0F3A60 */
6639   {
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6643     { Bad_Opcode },
6644   },
6645
6646   /* PREFIX_VEX_0F3A61 */
6647   {
6648     { Bad_Opcode },
6649     { Bad_Opcode },
6650     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6651   },
6652
6653   /* PREFIX_VEX_0F3A62 */
6654   {
6655     { Bad_Opcode },
6656     { Bad_Opcode },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6658   },
6659
6660   /* PREFIX_VEX_0F3A63 */
6661   {
6662     { Bad_Opcode },
6663     { Bad_Opcode },
6664     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6665   },
6666
6667   /* PREFIX_VEX_0F3A68 */
6668   {
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6672   },
6673
6674   /* PREFIX_VEX_0F3A69 */
6675   {
6676     { Bad_Opcode },
6677     { Bad_Opcode },
6678     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6679   },
6680
6681   /* PREFIX_VEX_0F3A6A */
6682   {
6683     { Bad_Opcode },
6684     { Bad_Opcode },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6686   },
6687
6688   /* PREFIX_VEX_0F3A6B */
6689   {
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6693   },
6694
6695   /* PREFIX_VEX_0F3A6C */
6696   {
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6700   },
6701
6702   /* PREFIX_VEX_0F3A6D */
6703   {
6704     { Bad_Opcode },
6705     { Bad_Opcode },
6706     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6707   },
6708
6709   /* PREFIX_VEX_0F3A6E */
6710   {
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6714   },
6715
6716   /* PREFIX_VEX_0F3A6F */
6717   {
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6721   },
6722
6723   /* PREFIX_VEX_0F3A78 */
6724   {
6725     { Bad_Opcode },
6726     { Bad_Opcode },
6727     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6728   },
6729
6730   /* PREFIX_VEX_0F3A79 */
6731   {
6732     { Bad_Opcode },
6733     { Bad_Opcode },
6734     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6735   },
6736
6737   /* PREFIX_VEX_0F3A7A */
6738   {
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6742   },
6743
6744   /* PREFIX_VEX_0F3A7B */
6745   {
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6749   },
6750
6751   /* PREFIX_VEX_0F3A7C */
6752   {
6753     { Bad_Opcode },
6754     { Bad_Opcode },
6755     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6756     { Bad_Opcode },
6757   },
6758
6759   /* PREFIX_VEX_0F3A7D */
6760   {
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6764   },
6765
6766   /* PREFIX_VEX_0F3A7E */
6767   {
6768     { Bad_Opcode },
6769     { Bad_Opcode },
6770     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6771   },
6772
6773   /* PREFIX_VEX_0F3A7F */
6774   {
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6778   },
6779
6780   /* PREFIX_VEX_0F3ADF */
6781   {
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6785   },
6786
6787   /* PREFIX_VEX_0F3AF0 */
6788   {
6789     { Bad_Opcode },
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6793   },
6794
6795 #define NEED_PREFIX_TABLE
6796 #include "i386-dis-evex.h"
6797 #undef NEED_PREFIX_TABLE
6798 };
6799
6800 static const struct dis386 x86_64_table[][2] = {
6801   /* X86_64_06 */
6802   {
6803     { "pushP", { es }, 0 },
6804   },
6805
6806   /* X86_64_07 */
6807   {
6808     { "popP", { es }, 0 },
6809   },
6810
6811   /* X86_64_0D */
6812   {
6813     { "pushP", { cs }, 0 },
6814   },
6815
6816   /* X86_64_16 */
6817   {
6818     { "pushP", { ss }, 0 },
6819   },
6820
6821   /* X86_64_17 */
6822   {
6823     { "popP", { ss }, 0 },
6824   },
6825
6826   /* X86_64_1E */
6827   {
6828     { "pushP", { ds }, 0 },
6829   },
6830
6831   /* X86_64_1F */
6832   {
6833     { "popP", { ds }, 0 },
6834   },
6835
6836   /* X86_64_27 */
6837   {
6838     { "daa", { XX }, 0 },
6839   },
6840
6841   /* X86_64_2F */
6842   {
6843     { "das", { XX }, 0 },
6844   },
6845
6846   /* X86_64_37 */
6847   {
6848     { "aaa", { XX }, 0 },
6849   },
6850
6851   /* X86_64_3F */
6852   {
6853     { "aas", { XX }, 0 },
6854   },
6855
6856   /* X86_64_60 */
6857   {
6858     { "pushaP", { XX }, 0 },
6859   },
6860
6861   /* X86_64_61 */
6862   {
6863     { "popaP", { XX }, 0 },
6864   },
6865
6866   /* X86_64_62 */
6867   {
6868     { MOD_TABLE (MOD_62_32BIT) },
6869     { EVEX_TABLE (EVEX_0F) },
6870   },
6871
6872   /* X86_64_63 */
6873   {
6874     { "arpl", { Ew, Gw }, 0 },
6875     { "movs{lq|xd}", { Gv, Ed }, 0 },
6876   },
6877
6878   /* X86_64_6D */
6879   {
6880     { "ins{R|}", { Yzr, indirDX }, 0 },
6881     { "ins{G|}", { Yzr, indirDX }, 0 },
6882   },
6883
6884   /* X86_64_6F */
6885   {
6886     { "outs{R|}", { indirDXr, Xz }, 0 },
6887     { "outs{G|}", { indirDXr, Xz }, 0 },
6888   },
6889
6890   /* X86_64_82 */
6891   {
6892     /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode.  */
6893     { REG_TABLE (REG_80) },
6894   },
6895
6896   /* X86_64_9A */
6897   {
6898     { "Jcall{T|}", { Ap }, 0 },
6899   },
6900
6901   /* X86_64_C4 */
6902   {
6903     { MOD_TABLE (MOD_C4_32BIT) },
6904     { VEX_C4_TABLE (VEX_0F) },
6905   },
6906
6907   /* X86_64_C5 */
6908   {
6909     { MOD_TABLE (MOD_C5_32BIT) },
6910     { VEX_C5_TABLE (VEX_0F) },
6911   },
6912
6913   /* X86_64_CE */
6914   {
6915     { "into", { XX }, 0 },
6916   },
6917
6918   /* X86_64_D4 */
6919   {
6920     { "aam", { Ib }, 0 },
6921   },
6922
6923   /* X86_64_D5 */
6924   {
6925     { "aad", { Ib }, 0 },
6926   },
6927
6928   /* X86_64_E8 */
6929   {
6930     { "callP",          { Jv, BND }, 0 },
6931     { "call@",          { Jv, BND }, 0 }
6932   },
6933
6934   /* X86_64_E9 */
6935   {
6936     { "jmpP",           { Jv, BND }, 0 },
6937     { "jmp@",           { Jv, BND }, 0 }
6938   },
6939
6940   /* X86_64_EA */
6941   {
6942     { "Jjmp{T|}", { Ap }, 0 },
6943   },
6944
6945   /* X86_64_0F01_REG_0 */
6946   {
6947     { "sgdt{Q|IQ}", { M }, 0 },
6948     { "sgdt", { M }, 0 },
6949   },
6950
6951   /* X86_64_0F01_REG_1 */
6952   {
6953     { "sidt{Q|IQ}", { M }, 0 },
6954     { "sidt", { M }, 0 },
6955   },
6956
6957   /* X86_64_0F01_REG_2 */
6958   {
6959     { "lgdt{Q|Q}", { M }, 0 },
6960     { "lgdt", { M }, 0 },
6961   },
6962
6963   /* X86_64_0F01_REG_3 */
6964   {
6965     { "lidt{Q|Q}", { M }, 0 },
6966     { "lidt", { M }, 0 },
6967   },
6968 };
6969
6970 static const struct dis386 three_byte_table[][256] = {
6971
6972   /* THREE_BYTE_0F38 */
6973   {
6974     /* 00 */
6975     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6976     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6977     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6978     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6979     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6980     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6981     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6982     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6983     /* 08 */
6984     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6985     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6986     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6987     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { Bad_Opcode },
6992     /* 10 */
6993     { PREFIX_TABLE (PREFIX_0F3810) },
6994     { Bad_Opcode },
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { PREFIX_TABLE (PREFIX_0F3814) },
6998     { PREFIX_TABLE (PREFIX_0F3815) },
6999     { Bad_Opcode },
7000     { PREFIX_TABLE (PREFIX_0F3817) },
7001     /* 18 */
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7007     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7008     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7009     { Bad_Opcode },
7010     /* 20 */
7011     { PREFIX_TABLE (PREFIX_0F3820) },
7012     { PREFIX_TABLE (PREFIX_0F3821) },
7013     { PREFIX_TABLE (PREFIX_0F3822) },
7014     { PREFIX_TABLE (PREFIX_0F3823) },
7015     { PREFIX_TABLE (PREFIX_0F3824) },
7016     { PREFIX_TABLE (PREFIX_0F3825) },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     /* 28 */
7020     { PREFIX_TABLE (PREFIX_0F3828) },
7021     { PREFIX_TABLE (PREFIX_0F3829) },
7022     { PREFIX_TABLE (PREFIX_0F382A) },
7023     { PREFIX_TABLE (PREFIX_0F382B) },
7024     { Bad_Opcode },
7025     { Bad_Opcode },
7026     { Bad_Opcode },
7027     { Bad_Opcode },
7028     /* 30 */
7029     { PREFIX_TABLE (PREFIX_0F3830) },
7030     { PREFIX_TABLE (PREFIX_0F3831) },
7031     { PREFIX_TABLE (PREFIX_0F3832) },
7032     { PREFIX_TABLE (PREFIX_0F3833) },
7033     { PREFIX_TABLE (PREFIX_0F3834) },
7034     { PREFIX_TABLE (PREFIX_0F3835) },
7035     { Bad_Opcode },
7036     { PREFIX_TABLE (PREFIX_0F3837) },
7037     /* 38 */
7038     { PREFIX_TABLE (PREFIX_0F3838) },
7039     { PREFIX_TABLE (PREFIX_0F3839) },
7040     { PREFIX_TABLE (PREFIX_0F383A) },
7041     { PREFIX_TABLE (PREFIX_0F383B) },
7042     { PREFIX_TABLE (PREFIX_0F383C) },
7043     { PREFIX_TABLE (PREFIX_0F383D) },
7044     { PREFIX_TABLE (PREFIX_0F383E) },
7045     { PREFIX_TABLE (PREFIX_0F383F) },
7046     /* 40 */
7047     { PREFIX_TABLE (PREFIX_0F3840) },
7048     { PREFIX_TABLE (PREFIX_0F3841) },
7049     { Bad_Opcode },
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     /* 48 */
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     { Bad_Opcode },
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     /* 50 */
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     /* 58 */
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     /* 60 */
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     /* 68 */
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     /* 70 */
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     { Bad_Opcode },
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     /* 78 */
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     /* 80 */
7119     { PREFIX_TABLE (PREFIX_0F3880) },
7120     { PREFIX_TABLE (PREFIX_0F3881) },
7121     { PREFIX_TABLE (PREFIX_0F3882) },
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     /* 88 */
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     /* 90 */
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     /* 98 */
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     /* a0 */
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     /* a8 */
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     /* b0 */
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     /* b8 */
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     { Bad_Opcode },
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     /* c0 */
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     /* c8 */
7200     { PREFIX_TABLE (PREFIX_0F38C8) },
7201     { PREFIX_TABLE (PREFIX_0F38C9) },
7202     { PREFIX_TABLE (PREFIX_0F38CA) },
7203     { PREFIX_TABLE (PREFIX_0F38CB) },
7204     { PREFIX_TABLE (PREFIX_0F38CC) },
7205     { PREFIX_TABLE (PREFIX_0F38CD) },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     /* d0 */
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     /* d8 */
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F38DB) },
7222     { PREFIX_TABLE (PREFIX_0F38DC) },
7223     { PREFIX_TABLE (PREFIX_0F38DD) },
7224     { PREFIX_TABLE (PREFIX_0F38DE) },
7225     { PREFIX_TABLE (PREFIX_0F38DF) },
7226     /* e0 */
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     /* e8 */
7236     { Bad_Opcode },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     /* f0 */
7245     { PREFIX_TABLE (PREFIX_0F38F0) },
7246     { PREFIX_TABLE (PREFIX_0F38F1) },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     { Bad_Opcode },
7250     { Bad_Opcode },
7251     { PREFIX_TABLE (PREFIX_0F38F6) },
7252     { Bad_Opcode },
7253     /* f8 */
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     { Bad_Opcode },
7260     { Bad_Opcode },
7261     { Bad_Opcode },
7262   },
7263   /* THREE_BYTE_0F3A */
7264   {
7265     /* 00 */
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     { Bad_Opcode },
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     /* 08 */
7275     { PREFIX_TABLE (PREFIX_0F3A08) },
7276     { PREFIX_TABLE (PREFIX_0F3A09) },
7277     { PREFIX_TABLE (PREFIX_0F3A0A) },
7278     { PREFIX_TABLE (PREFIX_0F3A0B) },
7279     { PREFIX_TABLE (PREFIX_0F3A0C) },
7280     { PREFIX_TABLE (PREFIX_0F3A0D) },
7281     { PREFIX_TABLE (PREFIX_0F3A0E) },
7282     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7283     /* 10 */
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     { PREFIX_TABLE (PREFIX_0F3A14) },
7289     { PREFIX_TABLE (PREFIX_0F3A15) },
7290     { PREFIX_TABLE (PREFIX_0F3A16) },
7291     { PREFIX_TABLE (PREFIX_0F3A17) },
7292     /* 18 */
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     { Bad_Opcode },
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     /* 20 */
7302     { PREFIX_TABLE (PREFIX_0F3A20) },
7303     { PREFIX_TABLE (PREFIX_0F3A21) },
7304     { PREFIX_TABLE (PREFIX_0F3A22) },
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     /* 28 */
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     /* 30 */
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     /* 38 */
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     /* 40 */
7338     { PREFIX_TABLE (PREFIX_0F3A40) },
7339     { PREFIX_TABLE (PREFIX_0F3A41) },
7340     { PREFIX_TABLE (PREFIX_0F3A42) },
7341     { Bad_Opcode },
7342     { PREFIX_TABLE (PREFIX_0F3A44) },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     /* 48 */
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     /* 50 */
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     /* 58 */
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     /* 60 */
7374     { PREFIX_TABLE (PREFIX_0F3A60) },
7375     { PREFIX_TABLE (PREFIX_0F3A61) },
7376     { PREFIX_TABLE (PREFIX_0F3A62) },
7377     { PREFIX_TABLE (PREFIX_0F3A63) },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     /* 68 */
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     /* 70 */
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     /* 78 */
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     /* 80 */
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     /* 88 */
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     /* 90 */
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     /* 98 */
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     /* a0 */
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     /* a8 */
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     /* b0 */
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     /* b8 */
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     /* c0 */
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     /* c8 */
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     { PREFIX_TABLE (PREFIX_0F3ACC) },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     /* d0 */
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     /* d8 */
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { PREFIX_TABLE (PREFIX_0F3ADF) },
7517     /* e0 */
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     /* e8 */
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     /* f0 */
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     /* f8 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553   },
7554 };
7555
7556 static const struct dis386 xop_table[][256] = {
7557   /* XOP_08 */
7558   {
7559     /* 00 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 08 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 10 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 18 */
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 20 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* 28 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* 30 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* 38 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* 40 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* 48 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* 50 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* 58 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* 60 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* 68 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* 70 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* 78 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* 80 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7710     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7711     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7712     /* 88 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7720     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7721     /* 90 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7728     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7729     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7730     /* 98 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7738     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7739     /* a0 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7743     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7747     { Bad_Opcode },
7748     /* a8 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* b0 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7765     { Bad_Opcode },
7766     /* b8 */
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     /* c0 */
7776     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7777     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7778     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7779     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     /* c8 */
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7790     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7791     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7792     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7793     /* d0 */
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     /* d8 */
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     /* e0 */
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     /* e8 */
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7826     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7827     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7828     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7829     /* f0 */
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     /* f8 */
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847   },
7848   /* XOP_09 */
7849   {
7850     /* 00 */
7851     { Bad_Opcode },
7852     { REG_TABLE (REG_XOP_TBM_01) },
7853     { REG_TABLE (REG_XOP_TBM_02) },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     /* 08 */
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     { Bad_Opcode },
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     /* 10 */
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { REG_TABLE (REG_XOP_LWPCB) },
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     /* 18 */
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     /* 20 */
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     /* 28 */
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     /* 30 */
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     /* 38 */
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     /* 40 */
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     /* 48 */
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     /* 50 */
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     /* 58 */
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     /* 60 */
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     /* 68 */
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     /* 70 */
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     /* 78 */
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     /* 80 */
7995     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7996     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7997     { "vfrczss",        { XM, EXd }, 0 },
7998     { "vfrczsd",        { XM, EXq }, 0 },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     /* 88 */
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     /* 90 */
8013     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021     /* 98 */
8022     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     /* a0 */
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     { Bad_Opcode },
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     /* a8 */
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     /* b0 */
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     /* b8 */
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     /* c0 */
8067     { Bad_Opcode },
8068     { "vphaddbw",       { XM, EXxmm }, 0 },
8069     { "vphaddbd",       { XM, EXxmm }, 0 },
8070     { "vphaddbq",       { XM, EXxmm }, 0 },
8071     { Bad_Opcode },
8072     { Bad_Opcode },
8073     { "vphaddwd",       { XM, EXxmm }, 0 },
8074     { "vphaddwq",       { XM, EXxmm }, 0 },
8075     /* c8 */
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { "vphadddq",       { XM, EXxmm }, 0 },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     /* d0 */
8085     { Bad_Opcode },
8086     { "vphaddubw",      { XM, EXxmm }, 0 },
8087     { "vphaddubd",      { XM, EXxmm }, 0 },
8088     { "vphaddubq",      { XM, EXxmm }, 0 },
8089     { Bad_Opcode },
8090     { Bad_Opcode },
8091     { "vphadduwd",      { XM, EXxmm }, 0 },
8092     { "vphadduwq",      { XM, EXxmm }, 0 },
8093     /* d8 */
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { "vphaddudq",      { XM, EXxmm }, 0 },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     /* e0 */
8103     { Bad_Opcode },
8104     { "vphsubbw",       { XM, EXxmm }, 0 },
8105     { "vphsubwd",       { XM, EXxmm }, 0 },
8106     { "vphsubdq",       { XM, EXxmm }, 0 },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     /* e8 */
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     /* f0 */
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     /* f8 */
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138   },
8139   /* XOP_0A */
8140   {
8141     /* 00 */
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     /* 08 */
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     { Bad_Opcode },
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     /* 10 */
8160     { "bextr",  { Gv, Ev, Iq }, 0 },
8161     { Bad_Opcode },
8162     { REG_TABLE (REG_XOP_LWP) },
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     /* 18 */
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     /* 20 */
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     /* 28 */
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     /* 30 */
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     /* 38 */
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     /* 40 */
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     /* 48 */
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     /* 50 */
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     /* 58 */
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     /* 60 */
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     /* 68 */
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     /* 70 */
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     /* 78 */
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     /* 80 */
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     /* 88 */
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     /* 90 */
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     /* 98 */
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     /* a0 */
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     /* a8 */
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     /* b0 */
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     /* b8 */
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     /* c0 */
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     /* c8 */
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     /* d0 */
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     /* d8 */
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     /* e0 */
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     /* e8 */
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     /* f0 */
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     /* f8 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429   },
8430 };
8431
8432 static const struct dis386 vex_table[][256] = {
8433   /* VEX_0F */
8434   {
8435     /* 00 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 08 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 10 */
8454     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8455     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8456     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8457     { MOD_TABLE (MOD_VEX_0F13) },
8458     { VEX_W_TABLE (VEX_W_0F14) },
8459     { VEX_W_TABLE (VEX_W_0F15) },
8460     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8461     { MOD_TABLE (MOD_VEX_0F17) },
8462     /* 18 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 20 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* 28 */
8481     { VEX_W_TABLE (VEX_W_0F28) },
8482     { VEX_W_TABLE (VEX_W_0F29) },
8483     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8484     { MOD_TABLE (MOD_VEX_0F2B) },
8485     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8486     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8487     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8488     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8489     /* 30 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* 38 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* 40 */
8508     { Bad_Opcode },
8509     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8510     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8511     { Bad_Opcode },
8512     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8515     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8516     /* 48 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8520     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* 50 */
8526     { MOD_TABLE (MOD_VEX_0F50) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8530     { "vandpX",         { XM, Vex, EXx }, 0 },
8531     { "vandnpX",        { XM, Vex, EXx }, 0 },
8532     { "vorpX",          { XM, Vex, EXx }, 0 },
8533     { "vxorpX",         { XM, Vex, EXx }, 0 },
8534     /* 58 */
8535     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8537     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8538     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8543     /* 60 */
8544     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8546     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8547     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8548     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8549     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8552     /* 68 */
8553     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8557     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8558     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8561     /* 70 */
8562     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8563     { REG_TABLE (REG_VEX_0F71) },
8564     { REG_TABLE (REG_VEX_0F72) },
8565     { REG_TABLE (REG_VEX_0F73) },
8566     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8567     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8570     /* 78 */
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8576     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8577     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8578     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8579     /* 80 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     /* 88 */
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     /* 90 */
8598     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8599     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8600     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8601     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     /* 98 */
8607     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8608     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* a0 */
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     /* a8 */
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { REG_TABLE (REG_VEX_0FAE) },
8632     { Bad_Opcode },
8633     /* b0 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     /* b8 */
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { Bad_Opcode },
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     /* c0 */
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8655     { Bad_Opcode },
8656     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8658     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8659     { Bad_Opcode },
8660     /* c8 */
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { Bad_Opcode },
8669     /* d0 */
8670     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8672     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8673     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8678     /* d8 */
8679     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8681     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8682     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8687     /* e0 */
8688     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8696     /* e8 */
8697     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8705     /* f0 */
8706     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8710     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8711     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8714     /* f8 */
8715     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8719     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8720     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8722     { Bad_Opcode },
8723   },
8724   /* VEX_0F38 */
8725   {
8726     /* 00 */
8727     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8729     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8730     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8731     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8732     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8734     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8735     /* 08 */
8736     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8738     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8739     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8744     /* 10 */
8745     { Bad_Opcode },
8746     { Bad_Opcode },
8747     { Bad_Opcode },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8749     { Bad_Opcode },
8750     { Bad_Opcode },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8753     /* 18 */
8754     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8757     { Bad_Opcode },
8758     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8761     { Bad_Opcode },
8762     /* 20 */
8763     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8769     { Bad_Opcode },
8770     { Bad_Opcode },
8771     /* 28 */
8772     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8775     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8780     /* 30 */
8781     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8783     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8784     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8786     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8789     /* 38 */
8790     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8794     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8795     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8798     /* 40 */
8799     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8801     { Bad_Opcode },
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8807     /* 48 */
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     { Bad_Opcode },
8811     { Bad_Opcode },
8812     { Bad_Opcode },
8813     { Bad_Opcode },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     /* 50 */
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     { Bad_Opcode },
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     /* 58 */
8826     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8827     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8828     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     /* 60 */
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     /* 68 */
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     /* 70 */
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     /* 78 */
8862     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8863     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     /* 80 */
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     /* 88 */
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8885     { Bad_Opcode },
8886     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8887     { Bad_Opcode },
8888     /* 90 */
8889     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8891     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8892     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8896     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8897     /* 98 */
8898     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8900     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8901     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8906     /* a0 */
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { Bad_Opcode },
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8915     /* a8 */
8916     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8924     /* b0 */
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { Bad_Opcode },
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8933     /* b8 */
8934     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8938     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8939     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8940     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8942     /* c0 */
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { Bad_Opcode },
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     /* c8 */
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     { Bad_Opcode },
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     /* d0 */
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     /* d8 */
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8974     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8975     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8976     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8978     /* e0 */
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     /* e8 */
8988     { Bad_Opcode },
8989     { Bad_Opcode },
8990     { Bad_Opcode },
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     /* f0 */
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9000     { REG_TABLE (REG_VEX_0F38F3) },
9001     { Bad_Opcode },
9002     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9003     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9005     /* f8 */
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     { Bad_Opcode },
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { Bad_Opcode },
9014   },
9015   /* VEX_0F3A */
9016   {
9017     /* 00 */
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9020     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9021     { Bad_Opcode },
9022     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9023     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9024     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9025     { Bad_Opcode },
9026     /* 08 */
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9029     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9035     /* 10 */
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     { Bad_Opcode },
9039     { Bad_Opcode },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9044     /* 18 */
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9047     { Bad_Opcode },
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     /* 20 */
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     /* 28 */
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     /* 30 */
9072     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9073     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9074     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9076     { Bad_Opcode },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     /* 38 */
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9082     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     /* 40 */
9090     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9091     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9092     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9093     { Bad_Opcode },
9094     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9095     { Bad_Opcode },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9097     { Bad_Opcode },
9098     /* 48 */
9099     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9100     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9101     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9102     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { Bad_Opcode },
9107     /* 50 */
9108     { Bad_Opcode },
9109     { Bad_Opcode },
9110     { Bad_Opcode },
9111     { Bad_Opcode },
9112     { Bad_Opcode },
9113     { Bad_Opcode },
9114     { Bad_Opcode },
9115     { Bad_Opcode },
9116     /* 58 */
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9125     /* 60 */
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9128     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9129     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     /* 68 */
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9143     /* 70 */
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     /* 78 */
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9157     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9158     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9159     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9160     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9161     /* 80 */
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     /* 88 */
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     { Bad_Opcode },
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     /* 90 */
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     /* 98 */
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     /* a0 */
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     /* a8 */
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     /* b0 */
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     /* b8 */
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     /* c0 */
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     /* c8 */
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     /* d0 */
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     /* d8 */
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { Bad_Opcode },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9269     /* e0 */
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     /* e8 */
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     /* f0 */
9288     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     /* f8 */
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     { Bad_Opcode },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305   },
9306 };
9307
9308 #define NEED_OPCODE_TABLE
9309 #include "i386-dis-evex.h"
9310 #undef NEED_OPCODE_TABLE
9311 static const struct dis386 vex_len_table[][2] = {
9312   /* VEX_LEN_0F10_P_1 */
9313   {
9314     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9315     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9316   },
9317
9318   /* VEX_LEN_0F10_P_3 */
9319   {
9320     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9321     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9322   },
9323
9324   /* VEX_LEN_0F11_P_1 */
9325   {
9326     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9327     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9328   },
9329
9330   /* VEX_LEN_0F11_P_3 */
9331   {
9332     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9333     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9334   },
9335
9336   /* VEX_LEN_0F12_P_0_M_0 */
9337   {
9338     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9339   },
9340
9341   /* VEX_LEN_0F12_P_0_M_1 */
9342   {
9343     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9344   },
9345
9346   /* VEX_LEN_0F12_P_2 */
9347   {
9348     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9349   },
9350
9351   /* VEX_LEN_0F13_M_0 */
9352   {
9353     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9354   },
9355
9356   /* VEX_LEN_0F16_P_0_M_0 */
9357   {
9358     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9359   },
9360
9361   /* VEX_LEN_0F16_P_0_M_1 */
9362   {
9363     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9364   },
9365
9366   /* VEX_LEN_0F16_P_2 */
9367   {
9368     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9369   },
9370
9371   /* VEX_LEN_0F17_M_0 */
9372   {
9373     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9374   },
9375
9376   /* VEX_LEN_0F2A_P_1 */
9377   {
9378     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9379     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9380   },
9381
9382   /* VEX_LEN_0F2A_P_3 */
9383   {
9384     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9385     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9386   },
9387
9388   /* VEX_LEN_0F2C_P_1 */
9389   {
9390     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9391     { "vcvttss2siY",    { Gv, EXdScalar }, 0 },
9392   },
9393
9394   /* VEX_LEN_0F2C_P_3 */
9395   {
9396     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9397     { "vcvttsd2siY",    { Gv, EXqScalar }, 0 },
9398   },
9399
9400   /* VEX_LEN_0F2D_P_1 */
9401   {
9402     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9403     { "vcvtss2siY",     { Gv, EXdScalar }, 0 },
9404   },
9405
9406   /* VEX_LEN_0F2D_P_3 */
9407   {
9408     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9409     { "vcvtsd2siY",     { Gv, EXqScalar }, 0 },
9410   },
9411
9412   /* VEX_LEN_0F2E_P_0 */
9413   {
9414     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9415     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9416   },
9417
9418   /* VEX_LEN_0F2E_P_2 */
9419   {
9420     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9421     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9422   },
9423
9424   /* VEX_LEN_0F2F_P_0 */
9425   {
9426     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9427     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9428   },
9429
9430   /* VEX_LEN_0F2F_P_2 */
9431   {
9432     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9433     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9434   },
9435
9436   /* VEX_LEN_0F41_P_0 */
9437   {
9438     { Bad_Opcode },
9439     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9440   },
9441   /* VEX_LEN_0F41_P_2 */
9442   {
9443     { Bad_Opcode },
9444     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9445   },
9446   /* VEX_LEN_0F42_P_0 */
9447   {
9448     { Bad_Opcode },
9449     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9450   },
9451   /* VEX_LEN_0F42_P_2 */
9452   {
9453     { Bad_Opcode },
9454     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9455   },
9456   /* VEX_LEN_0F44_P_0 */
9457   {
9458     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9459   },
9460   /* VEX_LEN_0F44_P_2 */
9461   {
9462     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9463   },
9464   /* VEX_LEN_0F45_P_0 */
9465   {
9466     { Bad_Opcode },
9467     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9468   },
9469   /* VEX_LEN_0F45_P_2 */
9470   {
9471     { Bad_Opcode },
9472     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9473   },
9474   /* VEX_LEN_0F46_P_0 */
9475   {
9476     { Bad_Opcode },
9477     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9478   },
9479   /* VEX_LEN_0F46_P_2 */
9480   {
9481     { Bad_Opcode },
9482     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9483   },
9484   /* VEX_LEN_0F47_P_0 */
9485   {
9486     { Bad_Opcode },
9487     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9488   },
9489   /* VEX_LEN_0F47_P_2 */
9490   {
9491     { Bad_Opcode },
9492     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9493   },
9494   /* VEX_LEN_0F4A_P_0 */
9495   {
9496     { Bad_Opcode },
9497     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9498   },
9499   /* VEX_LEN_0F4A_P_2 */
9500   {
9501     { Bad_Opcode },
9502     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9503   },
9504   /* VEX_LEN_0F4B_P_0 */
9505   {
9506     { Bad_Opcode },
9507     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9508   },
9509   /* VEX_LEN_0F4B_P_2 */
9510   {
9511     { Bad_Opcode },
9512     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9513   },
9514
9515   /* VEX_LEN_0F51_P_1 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9518     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9519   },
9520
9521   /* VEX_LEN_0F51_P_3 */
9522   {
9523     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9524     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9525   },
9526
9527   /* VEX_LEN_0F52_P_1 */
9528   {
9529     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9530     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9531   },
9532
9533   /* VEX_LEN_0F53_P_1 */
9534   {
9535     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9536     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9537   },
9538
9539   /* VEX_LEN_0F58_P_1 */
9540   {
9541     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9542     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9543   },
9544
9545   /* VEX_LEN_0F58_P_3 */
9546   {
9547     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9548     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9549   },
9550
9551   /* VEX_LEN_0F59_P_1 */
9552   {
9553     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9554     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9555   },
9556
9557   /* VEX_LEN_0F59_P_3 */
9558   {
9559     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9560     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9561   },
9562
9563   /* VEX_LEN_0F5A_P_1 */
9564   {
9565     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9566     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9567   },
9568
9569   /* VEX_LEN_0F5A_P_3 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9572     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9573   },
9574
9575   /* VEX_LEN_0F5C_P_1 */
9576   {
9577     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9578     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9579   },
9580
9581   /* VEX_LEN_0F5C_P_3 */
9582   {
9583     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9584     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9585   },
9586
9587   /* VEX_LEN_0F5D_P_1 */
9588   {
9589     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9590     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9591   },
9592
9593   /* VEX_LEN_0F5D_P_3 */
9594   {
9595     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9596     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9597   },
9598
9599   /* VEX_LEN_0F5E_P_1 */
9600   {
9601     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9602     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9603   },
9604
9605   /* VEX_LEN_0F5E_P_3 */
9606   {
9607     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9608     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9609   },
9610
9611   /* VEX_LEN_0F5F_P_1 */
9612   {
9613     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9614     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9615   },
9616
9617   /* VEX_LEN_0F5F_P_3 */
9618   {
9619     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9620     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9621   },
9622
9623   /* VEX_LEN_0F6E_P_2 */
9624   {
9625     { "vmovK",          { XMScalar, Edq }, 0 },
9626     { "vmovK",          { XMScalar, Edq }, 0 },
9627   },
9628
9629   /* VEX_LEN_0F7E_P_1 */
9630   {
9631     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9632     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9633   },
9634
9635   /* VEX_LEN_0F7E_P_2 */
9636   {
9637     { "vmovK",          { Edq, XMScalar }, 0 },
9638     { "vmovK",          { Edq, XMScalar }, 0 },
9639   },
9640
9641   /* VEX_LEN_0F90_P_0 */
9642   {
9643     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9644   },
9645
9646   /* VEX_LEN_0F90_P_2 */
9647   {
9648     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9649   },
9650
9651   /* VEX_LEN_0F91_P_0 */
9652   {
9653     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9654   },
9655
9656   /* VEX_LEN_0F91_P_2 */
9657   {
9658     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9659   },
9660
9661   /* VEX_LEN_0F92_P_0 */
9662   {
9663     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9664   },
9665
9666   /* VEX_LEN_0F92_P_2 */
9667   {
9668     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9669   },
9670
9671   /* VEX_LEN_0F92_P_3 */
9672   {
9673     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9674   },
9675
9676   /* VEX_LEN_0F93_P_0 */
9677   {
9678     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9679   },
9680
9681   /* VEX_LEN_0F93_P_2 */
9682   {
9683     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9684   },
9685
9686   /* VEX_LEN_0F93_P_3 */
9687   {
9688     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9689   },
9690
9691   /* VEX_LEN_0F98_P_0 */
9692   {
9693     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9694   },
9695
9696   /* VEX_LEN_0F98_P_2 */
9697   {
9698     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9699   },
9700
9701   /* VEX_LEN_0F99_P_0 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9704   },
9705
9706   /* VEX_LEN_0F99_P_2 */
9707   {
9708     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9709   },
9710
9711   /* VEX_LEN_0FAE_R_2_M_0 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9714   },
9715
9716   /* VEX_LEN_0FAE_R_3_M_0 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9719   },
9720
9721   /* VEX_LEN_0FC2_P_1 */
9722   {
9723     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9724     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9725   },
9726
9727   /* VEX_LEN_0FC2_P_3 */
9728   {
9729     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9730     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9731   },
9732
9733   /* VEX_LEN_0FC4_P_2 */
9734   {
9735     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9736   },
9737
9738   /* VEX_LEN_0FC5_P_2 */
9739   {
9740     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9741   },
9742
9743   /* VEX_LEN_0FD6_P_2 */
9744   {
9745     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9746     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9747   },
9748
9749   /* VEX_LEN_0FF7_P_2 */
9750   {
9751     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9752   },
9753
9754   /* VEX_LEN_0F3816_P_2 */
9755   {
9756     { Bad_Opcode },
9757     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9758   },
9759
9760   /* VEX_LEN_0F3819_P_2 */
9761   {
9762     { Bad_Opcode },
9763     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9764   },
9765
9766   /* VEX_LEN_0F381A_P_2_M_0 */
9767   {
9768     { Bad_Opcode },
9769     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9770   },
9771
9772   /* VEX_LEN_0F3836_P_2 */
9773   {
9774     { Bad_Opcode },
9775     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9776   },
9777
9778   /* VEX_LEN_0F3841_P_2 */
9779   {
9780     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9781   },
9782
9783   /* VEX_LEN_0F385A_P_2_M_0 */
9784   {
9785     { Bad_Opcode },
9786     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9787   },
9788
9789   /* VEX_LEN_0F38DB_P_2 */
9790   {
9791     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9792   },
9793
9794   /* VEX_LEN_0F38DC_P_2 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9797   },
9798
9799   /* VEX_LEN_0F38DD_P_2 */
9800   {
9801     { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9802   },
9803
9804   /* VEX_LEN_0F38DE_P_2 */
9805   {
9806     { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9807   },
9808
9809   /* VEX_LEN_0F38DF_P_2 */
9810   {
9811     { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9812   },
9813
9814   /* VEX_LEN_0F38F2_P_0 */
9815   {
9816     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9817   },
9818
9819   /* VEX_LEN_0F38F3_R_1_P_0 */
9820   {
9821     { "blsrS",          { VexGdq, Edq }, 0 },
9822   },
9823
9824   /* VEX_LEN_0F38F3_R_2_P_0 */
9825   {
9826     { "blsmskS",        { VexGdq, Edq }, 0 },
9827   },
9828
9829   /* VEX_LEN_0F38F3_R_3_P_0 */
9830   {
9831     { "blsiS",          { VexGdq, Edq }, 0 },
9832   },
9833
9834   /* VEX_LEN_0F38F5_P_0 */
9835   {
9836     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9837   },
9838
9839   /* VEX_LEN_0F38F5_P_1 */
9840   {
9841     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9842   },
9843
9844   /* VEX_LEN_0F38F5_P_3 */
9845   {
9846     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9847   },
9848
9849   /* VEX_LEN_0F38F6_P_3 */
9850   {
9851     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9852   },
9853
9854   /* VEX_LEN_0F38F7_P_0 */
9855   {
9856     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9857   },
9858
9859   /* VEX_LEN_0F38F7_P_1 */
9860   {
9861     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9862   },
9863
9864   /* VEX_LEN_0F38F7_P_2 */
9865   {
9866     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9867   },
9868
9869   /* VEX_LEN_0F38F7_P_3 */
9870   {
9871     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9872   },
9873
9874   /* VEX_LEN_0F3A00_P_2 */
9875   {
9876     { Bad_Opcode },
9877     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9878   },
9879
9880   /* VEX_LEN_0F3A01_P_2 */
9881   {
9882     { Bad_Opcode },
9883     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9884   },
9885
9886   /* VEX_LEN_0F3A06_P_2 */
9887   {
9888     { Bad_Opcode },
9889     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9890   },
9891
9892   /* VEX_LEN_0F3A0A_P_2 */
9893   {
9894     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9895     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
9896   },
9897
9898   /* VEX_LEN_0F3A0B_P_2 */
9899   {
9900     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9901     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
9902   },
9903
9904   /* VEX_LEN_0F3A14_P_2 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
9907   },
9908
9909   /* VEX_LEN_0F3A15_P_2 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
9912   },
9913
9914   /* VEX_LEN_0F3A16_P_2  */
9915   {
9916     { "vpextrK",        { Edq, XM, Ib }, 0 },
9917   },
9918
9919   /* VEX_LEN_0F3A17_P_2 */
9920   {
9921     { "vextractps",     { Edqd, XM, Ib }, 0 },
9922   },
9923
9924   /* VEX_LEN_0F3A18_P_2 */
9925   {
9926     { Bad_Opcode },
9927     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9928   },
9929
9930   /* VEX_LEN_0F3A19_P_2 */
9931   {
9932     { Bad_Opcode },
9933     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9934   },
9935
9936   /* VEX_LEN_0F3A20_P_2 */
9937   {
9938     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
9939   },
9940
9941   /* VEX_LEN_0F3A21_P_2 */
9942   {
9943     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
9944   },
9945
9946   /* VEX_LEN_0F3A22_P_2 */
9947   {
9948     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9949   },
9950
9951   /* VEX_LEN_0F3A30_P_2 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9954   },
9955
9956   /* VEX_LEN_0F3A31_P_2 */
9957   {
9958     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9959   },
9960
9961   /* VEX_LEN_0F3A32_P_2 */
9962   {
9963     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9964   },
9965
9966   /* VEX_LEN_0F3A33_P_2 */
9967   {
9968     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9969   },
9970
9971   /* VEX_LEN_0F3A38_P_2 */
9972   {
9973     { Bad_Opcode },
9974     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9975   },
9976
9977   /* VEX_LEN_0F3A39_P_2 */
9978   {
9979     { Bad_Opcode },
9980     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9981   },
9982
9983   /* VEX_LEN_0F3A41_P_2 */
9984   {
9985     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
9986   },
9987
9988   /* VEX_LEN_0F3A44_P_2 */
9989   {
9990     { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
9991   },
9992
9993   /* VEX_LEN_0F3A46_P_2 */
9994   {
9995     { Bad_Opcode },
9996     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9997   },
9998
9999   /* VEX_LEN_0F3A60_P_2 */
10000   {
10001     { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10002   },
10003
10004   /* VEX_LEN_0F3A61_P_2 */
10005   {
10006     { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10007   },
10008
10009   /* VEX_LEN_0F3A62_P_2 */
10010   {
10011     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10012   },
10013
10014   /* VEX_LEN_0F3A63_P_2 */
10015   {
10016     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10017   },
10018
10019   /* VEX_LEN_0F3A6A_P_2 */
10020   {
10021     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10022   },
10023
10024   /* VEX_LEN_0F3A6B_P_2 */
10025   {
10026     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10027   },
10028
10029   /* VEX_LEN_0F3A6E_P_2 */
10030   {
10031     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10032   },
10033
10034   /* VEX_LEN_0F3A6F_P_2 */
10035   {
10036     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10037   },
10038
10039   /* VEX_LEN_0F3A7A_P_2 */
10040   {
10041     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10042   },
10043
10044   /* VEX_LEN_0F3A7B_P_2 */
10045   {
10046     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10047   },
10048
10049   /* VEX_LEN_0F3A7E_P_2 */
10050   {
10051     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10052   },
10053
10054   /* VEX_LEN_0F3A7F_P_2 */
10055   {
10056     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10057   },
10058
10059   /* VEX_LEN_0F3ADF_P_2 */
10060   {
10061     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10062   },
10063
10064   /* VEX_LEN_0F3AF0_P_3 */
10065   {
10066     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10067   },
10068
10069   /* VEX_LEN_0FXOP_08_CC */
10070   {
10071      { "vpcomb",        { XM, Vex128, EXx, Ib }, 0 },
10072   },
10073
10074   /* VEX_LEN_0FXOP_08_CD */
10075   {
10076      { "vpcomw",        { XM, Vex128, EXx, Ib }, 0 },
10077   },
10078
10079   /* VEX_LEN_0FXOP_08_CE */
10080   {
10081      { "vpcomd",        { XM, Vex128, EXx, Ib }, 0 },
10082   },
10083
10084   /* VEX_LEN_0FXOP_08_CF */
10085   {
10086      { "vpcomq",        { XM, Vex128, EXx, Ib }, 0 },
10087   },
10088
10089   /* VEX_LEN_0FXOP_08_EC */
10090   {
10091      { "vpcomub",       { XM, Vex128, EXx, Ib }, 0 },
10092   },
10093
10094   /* VEX_LEN_0FXOP_08_ED */
10095   {
10096      { "vpcomuw",       { XM, Vex128, EXx, Ib }, 0 },
10097   },
10098
10099   /* VEX_LEN_0FXOP_08_EE */
10100   {
10101      { "vpcomud",       { XM, Vex128, EXx, Ib }, 0 },
10102   },
10103
10104   /* VEX_LEN_0FXOP_08_EF */
10105   {
10106      { "vpcomuq",       { XM, Vex128, EXx, Ib }, 0 },
10107   },
10108
10109   /* VEX_LEN_0FXOP_09_80 */
10110   {
10111     { "vfrczps",        { XM, EXxmm }, 0 },
10112     { "vfrczps",        { XM, EXymmq }, 0 },
10113   },
10114
10115   /* VEX_LEN_0FXOP_09_81 */
10116   {
10117     { "vfrczpd",        { XM, EXxmm }, 0 },
10118     { "vfrczpd",        { XM, EXymmq }, 0 },
10119   },
10120 };
10121
10122 static const struct dis386 vex_w_table[][2] = {
10123   {
10124     /* VEX_W_0F10_P_0 */
10125     { "vmovups",        { XM, EXx }, 0 },
10126   },
10127   {
10128     /* VEX_W_0F10_P_1 */
10129     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10130   },
10131   {
10132     /* VEX_W_0F10_P_2 */
10133     { "vmovupd",        { XM, EXx }, 0 },
10134   },
10135   {
10136     /* VEX_W_0F10_P_3 */
10137     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10138   },
10139   {
10140     /* VEX_W_0F11_P_0 */
10141     { "vmovups",        { EXxS, XM }, 0 },
10142   },
10143   {
10144     /* VEX_W_0F11_P_1 */
10145     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10146   },
10147   {
10148     /* VEX_W_0F11_P_2 */
10149     { "vmovupd",        { EXxS, XM }, 0 },
10150   },
10151   {
10152     /* VEX_W_0F11_P_3 */
10153     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10154   },
10155   {
10156     /* VEX_W_0F12_P_0_M_0 */
10157     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10158   },
10159   {
10160     /* VEX_W_0F12_P_0_M_1 */
10161     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10162   },
10163   {
10164     /* VEX_W_0F12_P_1 */
10165     { "vmovsldup",      { XM, EXx }, 0 },
10166   },
10167   {
10168     /* VEX_W_0F12_P_2 */
10169     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10170   },
10171   {
10172     /* VEX_W_0F12_P_3 */
10173     { "vmovddup",       { XM, EXymmq }, 0 },
10174   },
10175   {
10176     /* VEX_W_0F13_M_0 */
10177     { "vmovlpX",        { EXq, XM }, 0 },
10178   },
10179   {
10180     /* VEX_W_0F14 */
10181     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10182   },
10183   {
10184     /* VEX_W_0F15 */
10185     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10186   },
10187   {
10188     /* VEX_W_0F16_P_0_M_0 */
10189     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10190   },
10191   {
10192     /* VEX_W_0F16_P_0_M_1 */
10193     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10194   },
10195   {
10196     /* VEX_W_0F16_P_1 */
10197     { "vmovshdup",      { XM, EXx }, 0 },
10198   },
10199   {
10200     /* VEX_W_0F16_P_2 */
10201     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10202   },
10203   {
10204     /* VEX_W_0F17_M_0 */
10205     { "vmovhpX",        { EXq, XM }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F28 */
10209     { "vmovapX",        { XM, EXx }, 0 },
10210   },
10211   {
10212     /* VEX_W_0F29 */
10213     { "vmovapX",        { EXxS, XM }, 0 },
10214   },
10215   {
10216     /* VEX_W_0F2B_M_0 */
10217     { "vmovntpX",       { Mx, XM }, 0 },
10218   },
10219   {
10220     /* VEX_W_0F2E_P_0 */
10221     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10222   },
10223   {
10224     /* VEX_W_0F2E_P_2 */
10225     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10226   },
10227   {
10228     /* VEX_W_0F2F_P_0 */
10229     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10230   },
10231   {
10232     /* VEX_W_0F2F_P_2 */
10233     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10234   },
10235   {
10236     /* VEX_W_0F41_P_0_LEN_1 */
10237     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10238     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10239   },
10240   {
10241     /* VEX_W_0F41_P_2_LEN_1 */
10242     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10243     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10244   },
10245   {
10246     /* VEX_W_0F42_P_0_LEN_1 */
10247     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10248     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10249   },
10250   {
10251     /* VEX_W_0F42_P_2_LEN_1 */
10252     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10253     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10254   },
10255   {
10256     /* VEX_W_0F44_P_0_LEN_0 */
10257     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10258     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10259   },
10260   {
10261     /* VEX_W_0F44_P_2_LEN_0 */
10262     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10263     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10264   },
10265   {
10266     /* VEX_W_0F45_P_0_LEN_1 */
10267     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10268     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10269   },
10270   {
10271     /* VEX_W_0F45_P_2_LEN_1 */
10272     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10273     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10274   },
10275   {
10276     /* VEX_W_0F46_P_0_LEN_1 */
10277     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10278     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10279   },
10280   {
10281     /* VEX_W_0F46_P_2_LEN_1 */
10282     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10283     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10284   },
10285   {
10286     /* VEX_W_0F47_P_0_LEN_1 */
10287     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10288     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10289   },
10290   {
10291     /* VEX_W_0F47_P_2_LEN_1 */
10292     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10293     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10294   },
10295   {
10296     /* VEX_W_0F4A_P_0_LEN_1 */
10297     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10298     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10299   },
10300   {
10301     /* VEX_W_0F4A_P_2_LEN_1 */
10302     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10303     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10304   },
10305   {
10306     /* VEX_W_0F4B_P_0_LEN_1 */
10307     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10308     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10309   },
10310   {
10311     /* VEX_W_0F4B_P_2_LEN_1 */
10312     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10313   },
10314   {
10315     /* VEX_W_0F50_M_0 */
10316     { "vmovmskpX",      { Gdq, XS }, 0 },
10317   },
10318   {
10319     /* VEX_W_0F51_P_0 */
10320     { "vsqrtps",        { XM, EXx }, 0 },
10321   },
10322   {
10323     /* VEX_W_0F51_P_1 */
10324     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10325   },
10326   {
10327     /* VEX_W_0F51_P_2  */
10328     { "vsqrtpd",        { XM, EXx }, 0 },
10329   },
10330   {
10331     /* VEX_W_0F51_P_3 */
10332     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10333   },
10334   {
10335     /* VEX_W_0F52_P_0 */
10336     { "vrsqrtps",       { XM, EXx }, 0 },
10337   },
10338   {
10339     /* VEX_W_0F52_P_1 */
10340     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10341   },
10342   {
10343     /* VEX_W_0F53_P_0  */
10344     { "vrcpps",         { XM, EXx }, 0 },
10345   },
10346   {
10347     /* VEX_W_0F53_P_1  */
10348     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10349   },
10350   {
10351     /* VEX_W_0F58_P_0  */
10352     { "vaddps",         { XM, Vex, EXx }, 0 },
10353   },
10354   {
10355     /* VEX_W_0F58_P_1  */
10356     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10357   },
10358   {
10359     /* VEX_W_0F58_P_2  */
10360     { "vaddpd",         { XM, Vex, EXx }, 0 },
10361   },
10362   {
10363     /* VEX_W_0F58_P_3  */
10364     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10365   },
10366   {
10367     /* VEX_W_0F59_P_0  */
10368     { "vmulps",         { XM, Vex, EXx }, 0 },
10369   },
10370   {
10371     /* VEX_W_0F59_P_1  */
10372     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10373   },
10374   {
10375     /* VEX_W_0F59_P_2  */
10376     { "vmulpd",         { XM, Vex, EXx }, 0 },
10377   },
10378   {
10379     /* VEX_W_0F59_P_3  */
10380     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10381   },
10382   {
10383     /* VEX_W_0F5A_P_0  */
10384     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10385   },
10386   {
10387     /* VEX_W_0F5A_P_1  */
10388     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10389   },
10390   {
10391     /* VEX_W_0F5A_P_3  */
10392     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10393   },
10394   {
10395     /* VEX_W_0F5B_P_0  */
10396     { "vcvtdq2ps",      { XM, EXx }, 0 },
10397   },
10398   {
10399     /* VEX_W_0F5B_P_1  */
10400     { "vcvttps2dq",     { XM, EXx }, 0 },
10401   },
10402   {
10403     /* VEX_W_0F5B_P_2  */
10404     { "vcvtps2dq",      { XM, EXx }, 0 },
10405   },
10406   {
10407     /* VEX_W_0F5C_P_0  */
10408     { "vsubps",         { XM, Vex, EXx }, 0 },
10409   },
10410   {
10411     /* VEX_W_0F5C_P_1  */
10412     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10413   },
10414   {
10415     /* VEX_W_0F5C_P_2  */
10416     { "vsubpd",         { XM, Vex, EXx }, 0 },
10417   },
10418   {
10419     /* VEX_W_0F5C_P_3  */
10420     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10421   },
10422   {
10423     /* VEX_W_0F5D_P_0  */
10424     { "vminps",         { XM, Vex, EXx }, 0 },
10425   },
10426   {
10427     /* VEX_W_0F5D_P_1  */
10428     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10429   },
10430   {
10431     /* VEX_W_0F5D_P_2  */
10432     { "vminpd",         { XM, Vex, EXx }, 0 },
10433   },
10434   {
10435     /* VEX_W_0F5D_P_3  */
10436     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10437   },
10438   {
10439     /* VEX_W_0F5E_P_0  */
10440     { "vdivps",         { XM, Vex, EXx }, 0 },
10441   },
10442   {
10443     /* VEX_W_0F5E_P_1  */
10444     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10445   },
10446   {
10447     /* VEX_W_0F5E_P_2  */
10448     { "vdivpd",         { XM, Vex, EXx }, 0 },
10449   },
10450   {
10451     /* VEX_W_0F5E_P_3  */
10452     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10453   },
10454   {
10455     /* VEX_W_0F5F_P_0  */
10456     { "vmaxps",         { XM, Vex, EXx }, 0 },
10457   },
10458   {
10459     /* VEX_W_0F5F_P_1  */
10460     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10461   },
10462   {
10463     /* VEX_W_0F5F_P_2  */
10464     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10465   },
10466   {
10467     /* VEX_W_0F5F_P_3  */
10468     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10469   },
10470   {
10471     /* VEX_W_0F60_P_2  */
10472     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10473   },
10474   {
10475     /* VEX_W_0F61_P_2  */
10476     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10477   },
10478   {
10479     /* VEX_W_0F62_P_2  */
10480     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10481   },
10482   {
10483     /* VEX_W_0F63_P_2  */
10484     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10485   },
10486   {
10487     /* VEX_W_0F64_P_2  */
10488     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10489   },
10490   {
10491     /* VEX_W_0F65_P_2  */
10492     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10493   },
10494   {
10495     /* VEX_W_0F66_P_2  */
10496     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10497   },
10498   {
10499     /* VEX_W_0F67_P_2  */
10500     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10501   },
10502   {
10503     /* VEX_W_0F68_P_2  */
10504     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F69_P_2  */
10508     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F6A_P_2  */
10512     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F6B_P_2  */
10516     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F6C_P_2  */
10520     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F6D_P_2  */
10524     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F6F_P_1  */
10528     { "vmovdqu",        { XM, EXx }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F6F_P_2  */
10532     { "vmovdqa",        { XM, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F70_P_1 */
10536     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F70_P_2 */
10540     { "vpshufd",        { XM, EXx, Ib }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F70_P_3 */
10544     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F71_R_2_P_2  */
10548     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F71_R_4_P_2  */
10552     { "vpsraw",         { Vex, XS, Ib }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F71_R_6_P_2  */
10556     { "vpsllw",         { Vex, XS, Ib }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F72_R_2_P_2  */
10560     { "vpsrld",         { Vex, XS, Ib }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F72_R_4_P_2  */
10564     { "vpsrad",         { Vex, XS, Ib }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F72_R_6_P_2  */
10568     { "vpslld",         { Vex, XS, Ib }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F73_R_2_P_2  */
10572     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F73_R_3_P_2  */
10576     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F73_R_6_P_2  */
10580     { "vpsllq",         { Vex, XS, Ib }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F73_R_7_P_2  */
10584     { "vpslldq",        { Vex, XS, Ib }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F74_P_2 */
10588     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F75_P_2 */
10592     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F76_P_2 */
10596     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F77_P_0 */
10600     { "",               { VZERO }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F7C_P_2 */
10604     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F7C_P_3 */
10608     { "vhaddps",        { XM, Vex, EXx }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F7D_P_2 */
10612     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F7D_P_3 */
10616     { "vhsubps",        { XM, Vex, EXx }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F7E_P_1 */
10620     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F7F_P_1 */
10624     { "vmovdqu",        { EXxS, XM }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F7F_P_2 */
10628     { "vmovdqa",        { EXxS, XM }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F90_P_0_LEN_0 */
10632     { "kmovw",          { MaskG, MaskE }, 0 },
10633     { "kmovq",          { MaskG, MaskE }, 0 },
10634   },
10635   {
10636     /* VEX_W_0F90_P_2_LEN_0 */
10637     { "kmovb",          { MaskG, MaskBDE }, 0 },
10638     { "kmovd",          { MaskG, MaskBDE }, 0 },
10639   },
10640   {
10641     /* VEX_W_0F91_P_0_LEN_0 */
10642     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10643     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10644   },
10645   {
10646     /* VEX_W_0F91_P_2_LEN_0 */
10647     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10648     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10649   },
10650   {
10651     /* VEX_W_0F92_P_0_LEN_0 */
10652     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10653   },
10654   {
10655     /* VEX_W_0F92_P_2_LEN_0 */
10656     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10657   },
10658   {
10659     /* VEX_W_0F92_P_3_LEN_0 */
10660     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10661     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10662   },
10663   {
10664     /* VEX_W_0F93_P_0_LEN_0 */
10665     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10666   },
10667   {
10668     /* VEX_W_0F93_P_2_LEN_0 */
10669     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10670   },
10671   {
10672     /* VEX_W_0F93_P_3_LEN_0 */
10673     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10674     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10675   },
10676   {
10677     /* VEX_W_0F98_P_0_LEN_0 */
10678     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10679     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10680   },
10681   {
10682     /* VEX_W_0F98_P_2_LEN_0 */
10683     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10684     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10685   },
10686   {
10687     /* VEX_W_0F99_P_0_LEN_0 */
10688     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10689     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10690   },
10691   {
10692     /* VEX_W_0F99_P_2_LEN_0 */
10693     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10694     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10695   },
10696   {
10697     /* VEX_W_0FAE_R_2_M_0 */
10698     { "vldmxcsr",       { Md }, 0 },
10699   },
10700   {
10701     /* VEX_W_0FAE_R_3_M_0 */
10702     { "vstmxcsr",       { Md }, 0 },
10703   },
10704   {
10705     /* VEX_W_0FC2_P_0 */
10706     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10707   },
10708   {
10709     /* VEX_W_0FC2_P_1 */
10710     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10711   },
10712   {
10713     /* VEX_W_0FC2_P_2 */
10714     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10715   },
10716   {
10717     /* VEX_W_0FC2_P_3 */
10718     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10719   },
10720   {
10721     /* VEX_W_0FC4_P_2 */
10722     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10723   },
10724   {
10725     /* VEX_W_0FC5_P_2 */
10726     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10727   },
10728   {
10729     /* VEX_W_0FD0_P_2 */
10730     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10731   },
10732   {
10733     /* VEX_W_0FD0_P_3 */
10734     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10735   },
10736   {
10737     /* VEX_W_0FD1_P_2 */
10738     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10739   },
10740   {
10741     /* VEX_W_0FD2_P_2 */
10742     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10743   },
10744   {
10745     /* VEX_W_0FD3_P_2 */
10746     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10747   },
10748   {
10749     /* VEX_W_0FD4_P_2 */
10750     { "vpaddq",         { XM, Vex, EXx }, 0 },
10751   },
10752   {
10753     /* VEX_W_0FD5_P_2 */
10754     { "vpmullw",        { XM, Vex, EXx }, 0 },
10755   },
10756   {
10757     /* VEX_W_0FD6_P_2 */
10758     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10759   },
10760   {
10761     /* VEX_W_0FD7_P_2_M_1 */
10762     { "vpmovmskb",      { Gdq, XS }, 0 },
10763   },
10764   {
10765     /* VEX_W_0FD8_P_2 */
10766     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10767   },
10768   {
10769     /* VEX_W_0FD9_P_2 */
10770     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10771   },
10772   {
10773     /* VEX_W_0FDA_P_2 */
10774     { "vpminub",        { XM, Vex, EXx }, 0 },
10775   },
10776   {
10777     /* VEX_W_0FDB_P_2 */
10778     { "vpand",          { XM, Vex, EXx }, 0 },
10779   },
10780   {
10781     /* VEX_W_0FDC_P_2 */
10782     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10783   },
10784   {
10785     /* VEX_W_0FDD_P_2 */
10786     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10787   },
10788   {
10789     /* VEX_W_0FDE_P_2 */
10790     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10791   },
10792   {
10793     /* VEX_W_0FDF_P_2 */
10794     { "vpandn",         { XM, Vex, EXx }, 0 },
10795   },
10796   {
10797     /* VEX_W_0FE0_P_2  */
10798     { "vpavgb",         { XM, Vex, EXx }, 0 },
10799   },
10800   {
10801     /* VEX_W_0FE1_P_2  */
10802     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10803   },
10804   {
10805     /* VEX_W_0FE2_P_2  */
10806     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10807   },
10808   {
10809     /* VEX_W_0FE3_P_2  */
10810     { "vpavgw",         { XM, Vex, EXx }, 0 },
10811   },
10812   {
10813     /* VEX_W_0FE4_P_2  */
10814     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
10815   },
10816   {
10817     /* VEX_W_0FE5_P_2  */
10818     { "vpmulhw",        { XM, Vex, EXx }, 0 },
10819   },
10820   {
10821     /* VEX_W_0FE6_P_1  */
10822     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
10823   },
10824   {
10825     /* VEX_W_0FE6_P_2  */
10826     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
10827   },
10828   {
10829     /* VEX_W_0FE6_P_3  */
10830     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
10831   },
10832   {
10833     /* VEX_W_0FE7_P_2_M_0 */
10834     { "vmovntdq",       { Mx, XM }, 0 },
10835   },
10836   {
10837     /* VEX_W_0FE8_P_2  */
10838     { "vpsubsb",        { XM, Vex, EXx }, 0 },
10839   },
10840   {
10841     /* VEX_W_0FE9_P_2  */
10842     { "vpsubsw",        { XM, Vex, EXx }, 0 },
10843   },
10844   {
10845     /* VEX_W_0FEA_P_2  */
10846     { "vpminsw",        { XM, Vex, EXx }, 0 },
10847   },
10848   {
10849     /* VEX_W_0FEB_P_2  */
10850     { "vpor",           { XM, Vex, EXx }, 0 },
10851   },
10852   {
10853     /* VEX_W_0FEC_P_2  */
10854     { "vpaddsb",        { XM, Vex, EXx }, 0 },
10855   },
10856   {
10857     /* VEX_W_0FED_P_2  */
10858     { "vpaddsw",        { XM, Vex, EXx }, 0 },
10859   },
10860   {
10861     /* VEX_W_0FEE_P_2  */
10862     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
10863   },
10864   {
10865     /* VEX_W_0FEF_P_2  */
10866     { "vpxor",          { XM, Vex, EXx }, 0 },
10867   },
10868   {
10869     /* VEX_W_0FF0_P_3_M_0 */
10870     { "vlddqu",         { XM, M }, 0 },
10871   },
10872   {
10873     /* VEX_W_0FF1_P_2 */
10874     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
10875   },
10876   {
10877     /* VEX_W_0FF2_P_2 */
10878     { "vpslld",         { XM, Vex, EXxmm }, 0 },
10879   },
10880   {
10881     /* VEX_W_0FF3_P_2 */
10882     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
10883   },
10884   {
10885     /* VEX_W_0FF4_P_2 */
10886     { "vpmuludq",       { XM, Vex, EXx }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FF5_P_2 */
10890     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FF6_P_2 */
10894     { "vpsadbw",        { XM, Vex, EXx }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FF7_P_2 */
10898     { "vmaskmovdqu",    { XM, XS }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FF8_P_2 */
10902     { "vpsubb",         { XM, Vex, EXx }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FF9_P_2 */
10906     { "vpsubw",         { XM, Vex, EXx }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FFA_P_2 */
10910     { "vpsubd",         { XM, Vex, EXx }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FFB_P_2 */
10914     { "vpsubq",         { XM, Vex, EXx }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FFC_P_2 */
10918     { "vpaddb",         { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FFD_P_2 */
10922     { "vpaddw",         { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FFE_P_2 */
10926     { "vpaddd",         { XM, Vex, EXx }, 0 },
10927   },
10928   {
10929     /* VEX_W_0F3800_P_2  */
10930     { "vpshufb",        { XM, Vex, EXx }, 0 },
10931   },
10932   {
10933     /* VEX_W_0F3801_P_2  */
10934     { "vphaddw",        { XM, Vex, EXx }, 0 },
10935   },
10936   {
10937     /* VEX_W_0F3802_P_2  */
10938     { "vphaddd",        { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0F3803_P_2  */
10942     { "vphaddsw",       { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0F3804_P_2  */
10946     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
10947   },
10948   {
10949     /* VEX_W_0F3805_P_2  */
10950     { "vphsubw",        { XM, Vex, EXx }, 0 },
10951   },
10952   {
10953     /* VEX_W_0F3806_P_2  */
10954     { "vphsubd",        { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0F3807_P_2  */
10958     { "vphsubsw",       { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0F3808_P_2  */
10962     { "vpsignb",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0F3809_P_2  */
10966     { "vpsignw",        { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0F380A_P_2  */
10970     { "vpsignd",        { XM, Vex, EXx }, 0 },
10971   },
10972   {
10973     /* VEX_W_0F380B_P_2  */
10974     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0F380C_P_2  */
10978     { "vpermilps",      { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0F380D_P_2  */
10982     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0F380E_P_2  */
10986     { "vtestps",        { XM, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0F380F_P_2  */
10990     { "vtestpd",        { XM, EXx }, 0 },
10991   },
10992   {
10993     /* VEX_W_0F3816_P_2  */
10994     { "vpermps",        { XM, Vex, EXx }, 0 },
10995   },
10996   {
10997     /* VEX_W_0F3817_P_2 */
10998     { "vptest",         { XM, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0F3818_P_2 */
11002     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11003   },
11004   {
11005     /* VEX_W_0F3819_P_2 */
11006     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11007   },
11008   {
11009     /* VEX_W_0F381A_P_2_M_0 */
11010     { "vbroadcastf128", { XM, Mxmm }, 0 },
11011   },
11012   {
11013     /* VEX_W_0F381C_P_2 */
11014     { "vpabsb",         { XM, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0F381D_P_2 */
11018     { "vpabsw",         { XM, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0F381E_P_2 */
11022     { "vpabsd",         { XM, EXx }, 0 },
11023   },
11024   {
11025     /* VEX_W_0F3820_P_2 */
11026     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11027   },
11028   {
11029     /* VEX_W_0F3821_P_2 */
11030     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11031   },
11032   {
11033     /* VEX_W_0F3822_P_2 */
11034     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11035   },
11036   {
11037     /* VEX_W_0F3823_P_2 */
11038     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11039   },
11040   {
11041     /* VEX_W_0F3824_P_2 */
11042     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11043   },
11044   {
11045     /* VEX_W_0F3825_P_2 */
11046     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11047   },
11048   {
11049     /* VEX_W_0F3828_P_2 */
11050     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0F3829_P_2 */
11054     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0F382A_P_2_M_0 */
11058     { "vmovntdqa",      { XM, Mx }, 0 },
11059   },
11060   {
11061     /* VEX_W_0F382B_P_2 */
11062     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11063   },
11064   {
11065     /* VEX_W_0F382C_P_2_M_0 */
11066     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11067   },
11068   {
11069     /* VEX_W_0F382D_P_2_M_0 */
11070     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11071   },
11072   {
11073     /* VEX_W_0F382E_P_2_M_0 */
11074     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11075   },
11076   {
11077     /* VEX_W_0F382F_P_2_M_0 */
11078     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11079   },
11080   {
11081     /* VEX_W_0F3830_P_2 */
11082     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11083   },
11084   {
11085     /* VEX_W_0F3831_P_2 */
11086     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11087   },
11088   {
11089     /* VEX_W_0F3832_P_2 */
11090     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11091   },
11092   {
11093     /* VEX_W_0F3833_P_2 */
11094     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11095   },
11096   {
11097     /* VEX_W_0F3834_P_2 */
11098     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11099   },
11100   {
11101     /* VEX_W_0F3835_P_2 */
11102     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11103   },
11104   {
11105     /* VEX_W_0F3836_P_2  */
11106     { "vpermd",         { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0F3837_P_2 */
11110     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0F3838_P_2 */
11114     { "vpminsb",        { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F3839_P_2 */
11118     { "vpminsd",        { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F383A_P_2 */
11122     { "vpminuw",        { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F383B_P_2 */
11126     { "vpminud",        { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F383C_P_2 */
11130     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F383D_P_2 */
11134     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F383E_P_2 */
11138     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F383F_P_2 */
11142     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F3840_P_2 */
11146     { "vpmulld",        { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3841_P_2 */
11150     { "vphminposuw",    { XM, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3846_P_2 */
11154     { "vpsravd",        { XM, Vex, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F3858_P_2 */
11158     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F3859_P_2 */
11162     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F385A_P_2_M_0 */
11166     { "vbroadcasti128", { XM, Mxmm }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F3878_P_2 */
11170     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F3879_P_2 */
11174     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F38DB_P_2 */
11178     { "vaesimc",        { XM, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F38DC_P_2 */
11182     { "vaesenc",        { XM, Vex128, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F38DD_P_2 */
11186     { "vaesenclast",    { XM, Vex128, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F38DE_P_2 */
11190     { "vaesdec",        { XM, Vex128, EXx }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F38DF_P_2 */
11194     { "vaesdeclast",    { XM, Vex128, EXx }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F3A00_P_2 */
11198     { Bad_Opcode },
11199     { "vpermq",         { XM, EXx, Ib }, 0 },
11200   },
11201   {
11202     /* VEX_W_0F3A01_P_2 */
11203     { Bad_Opcode },
11204     { "vpermpd",        { XM, EXx, Ib }, 0 },
11205   },
11206   {
11207     /* VEX_W_0F3A02_P_2 */
11208     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11209   },
11210   {
11211     /* VEX_W_0F3A04_P_2 */
11212     { "vpermilps",      { XM, EXx, Ib }, 0 },
11213   },
11214   {
11215     /* VEX_W_0F3A05_P_2 */
11216     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11217   },
11218   {
11219     /* VEX_W_0F3A06_P_2 */
11220     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11221   },
11222   {
11223     /* VEX_W_0F3A08_P_2 */
11224     { "vroundps",       { XM, EXx, Ib }, 0 },
11225   },
11226   {
11227     /* VEX_W_0F3A09_P_2 */
11228     { "vroundpd",       { XM, EXx, Ib }, 0 },
11229   },
11230   {
11231     /* VEX_W_0F3A0A_P_2 */
11232     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11233   },
11234   {
11235     /* VEX_W_0F3A0B_P_2 */
11236     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11237   },
11238   {
11239     /* VEX_W_0F3A0C_P_2 */
11240     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11241   },
11242   {
11243     /* VEX_W_0F3A0D_P_2 */
11244     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11245   },
11246   {
11247     /* VEX_W_0F3A0E_P_2 */
11248     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11249   },
11250   {
11251     /* VEX_W_0F3A0F_P_2 */
11252     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11253   },
11254   {
11255     /* VEX_W_0F3A14_P_2 */
11256     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11257   },
11258   {
11259     /* VEX_W_0F3A15_P_2 */
11260     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11261   },
11262   {
11263     /* VEX_W_0F3A18_P_2 */
11264     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11265   },
11266   {
11267     /* VEX_W_0F3A19_P_2 */
11268     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11269   },
11270   {
11271     /* VEX_W_0F3A20_P_2 */
11272     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11273   },
11274   {
11275     /* VEX_W_0F3A21_P_2 */
11276     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11277   },
11278   {
11279     /* VEX_W_0F3A30_P_2_LEN_0 */
11280     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11281     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11282   },
11283   {
11284     /* VEX_W_0F3A31_P_2_LEN_0 */
11285     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11286     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11287   },
11288   {
11289     /* VEX_W_0F3A32_P_2_LEN_0 */
11290     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11291     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11292   },
11293   {
11294     /* VEX_W_0F3A33_P_2_LEN_0 */
11295     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11296     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11297   },
11298   {
11299     /* VEX_W_0F3A38_P_2 */
11300     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11301   },
11302   {
11303     /* VEX_W_0F3A39_P_2 */
11304     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11305   },
11306   {
11307     /* VEX_W_0F3A40_P_2 */
11308     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11309   },
11310   {
11311     /* VEX_W_0F3A41_P_2 */
11312     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11313   },
11314   {
11315     /* VEX_W_0F3A42_P_2 */
11316     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11317   },
11318   {
11319     /* VEX_W_0F3A44_P_2 */
11320     { "vpclmulqdq",     { XM, Vex128, EXx, PCLMUL }, 0 },
11321   },
11322   {
11323     /* VEX_W_0F3A46_P_2 */
11324     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11325   },
11326   {
11327     /* VEX_W_0F3A48_P_2 */
11328     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11329     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11330   },
11331   {
11332     /* VEX_W_0F3A49_P_2 */
11333     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11334     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3A4A_P_2 */
11338     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3A4B_P_2 */
11342     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F3A4C_P_2 */
11346     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F3A60_P_2 */
11350     { "vpcmpestrm",     { XM, EXx, Ib }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F3A61_P_2 */
11354     { "vpcmpestri",     { XM, EXx, Ib }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3A62_P_2 */
11358     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3A63_P_2 */
11362     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F3ADF_P_2 */
11366     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11367   },
11368 #define NEED_VEX_W_TABLE
11369 #include "i386-dis-evex.h"
11370 #undef NEED_VEX_W_TABLE
11371 };
11372
11373 static const struct dis386 mod_table[][2] = {
11374   {
11375     /* MOD_8D */
11376     { "leaS",           { Gv, M }, 0 },
11377   },
11378   {
11379     /* MOD_C6_REG_7 */
11380     { Bad_Opcode },
11381     { RM_TABLE (RM_C6_REG_7) },
11382   },
11383   {
11384     /* MOD_C7_REG_7 */
11385     { Bad_Opcode },
11386     { RM_TABLE (RM_C7_REG_7) },
11387   },
11388   {
11389     /* MOD_FF_REG_3 */
11390     { "Jcall^", { indirEp }, 0 },
11391   },
11392   {
11393     /* MOD_FF_REG_5 */
11394     { "Jjmp^", { indirEp }, 0 },
11395   },
11396   {
11397     /* MOD_0F01_REG_0 */
11398     { X86_64_TABLE (X86_64_0F01_REG_0) },
11399     { RM_TABLE (RM_0F01_REG_0) },
11400   },
11401   {
11402     /* MOD_0F01_REG_1 */
11403     { X86_64_TABLE (X86_64_0F01_REG_1) },
11404     { RM_TABLE (RM_0F01_REG_1) },
11405   },
11406   {
11407     /* MOD_0F01_REG_2 */
11408     { X86_64_TABLE (X86_64_0F01_REG_2) },
11409     { RM_TABLE (RM_0F01_REG_2) },
11410   },
11411   {
11412     /* MOD_0F01_REG_3 */
11413     { X86_64_TABLE (X86_64_0F01_REG_3) },
11414     { RM_TABLE (RM_0F01_REG_3) },
11415   },
11416   {
11417     /* MOD_0F01_REG_5 */
11418     { Bad_Opcode },
11419     { RM_TABLE (RM_0F01_REG_5) },
11420   },
11421   {
11422     /* MOD_0F01_REG_7 */
11423     { "invlpg",         { Mb }, 0 },
11424     { RM_TABLE (RM_0F01_REG_7) },
11425   },
11426   {
11427     /* MOD_0F12_PREFIX_0 */
11428     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11429     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11430   },
11431   {
11432     /* MOD_0F13 */
11433     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11434   },
11435   {
11436     /* MOD_0F16_PREFIX_0 */
11437     { "movhps",         { XM, EXq }, 0 },
11438     { "movlhps",        { XM, EXq }, 0 },
11439   },
11440   {
11441     /* MOD_0F17 */
11442     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11443   },
11444   {
11445     /* MOD_0F18_REG_0 */
11446     { "prefetchnta",    { Mb }, 0 },
11447   },
11448   {
11449     /* MOD_0F18_REG_1 */
11450     { "prefetcht0",     { Mb }, 0 },
11451   },
11452   {
11453     /* MOD_0F18_REG_2 */
11454     { "prefetcht1",     { Mb }, 0 },
11455   },
11456   {
11457     /* MOD_0F18_REG_3 */
11458     { "prefetcht2",     { Mb }, 0 },
11459   },
11460   {
11461     /* MOD_0F18_REG_4 */
11462     { "nop/reserved",   { Mb }, 0 },
11463   },
11464   {
11465     /* MOD_0F18_REG_5 */
11466     { "nop/reserved",   { Mb }, 0 },
11467   },
11468   {
11469     /* MOD_0F18_REG_6 */
11470     { "nop/reserved",   { Mb }, 0 },
11471   },
11472   {
11473     /* MOD_0F18_REG_7 */
11474     { "nop/reserved",   { Mb }, 0 },
11475   },
11476   {
11477     /* MOD_0F1A_PREFIX_0 */
11478     { "bndldx",         { Gbnd, Ev_bnd }, 0 },
11479     { "nopQ",           { Ev }, 0 },
11480   },
11481   {
11482     /* MOD_0F1B_PREFIX_0 */
11483     { "bndstx",         { Ev_bnd, Gbnd }, 0 },
11484     { "nopQ",           { Ev }, 0 },
11485   },
11486   {
11487     /* MOD_0F1B_PREFIX_1 */
11488     { "bndmk",          { Gbnd, Ev_bnd }, 0 },
11489     { "nopQ",           { Ev }, 0 },
11490   },
11491   {
11492     /* MOD_0F24 */
11493     { Bad_Opcode },
11494     { "movL",           { Rd, Td }, 0 },
11495   },
11496   {
11497     /* MOD_0F26 */
11498     { Bad_Opcode },
11499     { "movL",           { Td, Rd }, 0 },
11500   },
11501   {
11502     /* MOD_0F2B_PREFIX_0 */
11503     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11504   },
11505   {
11506     /* MOD_0F2B_PREFIX_1 */
11507     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11508   },
11509   {
11510     /* MOD_0F2B_PREFIX_2 */
11511     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11512   },
11513   {
11514     /* MOD_0F2B_PREFIX_3 */
11515     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11516   },
11517   {
11518     /* MOD_0F51 */
11519     { Bad_Opcode },
11520     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11521   },
11522   {
11523     /* MOD_0F71_REG_2 */
11524     { Bad_Opcode },
11525     { "psrlw",          { MS, Ib }, 0 },
11526   },
11527   {
11528     /* MOD_0F71_REG_4 */
11529     { Bad_Opcode },
11530     { "psraw",          { MS, Ib }, 0 },
11531   },
11532   {
11533     /* MOD_0F71_REG_6 */
11534     { Bad_Opcode },
11535     { "psllw",          { MS, Ib }, 0 },
11536   },
11537   {
11538     /* MOD_0F72_REG_2 */
11539     { Bad_Opcode },
11540     { "psrld",          { MS, Ib }, 0 },
11541   },
11542   {
11543     /* MOD_0F72_REG_4 */
11544     { Bad_Opcode },
11545     { "psrad",          { MS, Ib }, 0 },
11546   },
11547   {
11548     /* MOD_0F72_REG_6 */
11549     { Bad_Opcode },
11550     { "pslld",          { MS, Ib }, 0 },
11551   },
11552   {
11553     /* MOD_0F73_REG_2 */
11554     { Bad_Opcode },
11555     { "psrlq",          { MS, Ib }, 0 },
11556   },
11557   {
11558     /* MOD_0F73_REG_3 */
11559     { Bad_Opcode },
11560     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11561   },
11562   {
11563     /* MOD_0F73_REG_6 */
11564     { Bad_Opcode },
11565     { "psllq",          { MS, Ib }, 0 },
11566   },
11567   {
11568     /* MOD_0F73_REG_7 */
11569     { Bad_Opcode },
11570     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11571   },
11572   {
11573     /* MOD_0FAE_REG_0 */
11574     { "fxsave",         { FXSAVE }, 0 },
11575     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11576   },
11577   {
11578     /* MOD_0FAE_REG_1 */
11579     { "fxrstor",        { FXSAVE }, 0 },
11580     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11581   },
11582   {
11583     /* MOD_0FAE_REG_2 */
11584     { "ldmxcsr",        { Md }, 0 },
11585     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11586   },
11587   {
11588     /* MOD_0FAE_REG_3 */
11589     { "stmxcsr",        { Md }, 0 },
11590     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11591   },
11592   {
11593     /* MOD_0FAE_REG_4 */
11594     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11595     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11596   },
11597   {
11598     /* MOD_0FAE_REG_5 */
11599     { "xrstor",         { FXSAVE }, 0 },
11600     { RM_TABLE (RM_0FAE_REG_5) },
11601   },
11602   {
11603     /* MOD_0FAE_REG_6 */
11604     { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11605     { RM_TABLE (RM_0FAE_REG_6) },
11606   },
11607   {
11608     /* MOD_0FAE_REG_7 */
11609     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11610     { RM_TABLE (RM_0FAE_REG_7) },
11611   },
11612   {
11613     /* MOD_0FB2 */
11614     { "lssS",           { Gv, Mp }, 0 },
11615   },
11616   {
11617     /* MOD_0FB4 */
11618     { "lfsS",           { Gv, Mp }, 0 },
11619   },
11620   {
11621     /* MOD_0FB5 */
11622     { "lgsS",           { Gv, Mp }, 0 },
11623   },
11624   {
11625     /* MOD_0FC3 */
11626     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11627   },
11628   {
11629     /* MOD_0FC7_REG_3 */
11630     { "xrstors",        { FXSAVE }, 0 },
11631   },
11632   {
11633     /* MOD_0FC7_REG_4 */
11634     { "xsavec",         { FXSAVE }, 0 },
11635   },
11636   {
11637     /* MOD_0FC7_REG_5 */
11638     { "xsaves",         { FXSAVE }, 0 },
11639   },
11640   {
11641     /* MOD_0FC7_REG_6 */
11642     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11643     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11644   },
11645   {
11646     /* MOD_0FC7_REG_7 */
11647     { "vmptrst",        { Mq }, 0 },
11648     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11649   },
11650   {
11651     /* MOD_0FD7 */
11652     { Bad_Opcode },
11653     { "pmovmskb",       { Gdq, MS }, 0 },
11654   },
11655   {
11656     /* MOD_0FE7_PREFIX_2 */
11657     { "movntdq",        { Mx, XM }, 0 },
11658   },
11659   {
11660     /* MOD_0FF0_PREFIX_3 */
11661     { "lddqu",          { XM, M }, 0 },
11662   },
11663   {
11664     /* MOD_0F382A_PREFIX_2 */
11665     { "movntdqa",       { XM, Mx }, 0 },
11666   },
11667   {
11668     /* MOD_62_32BIT */
11669     { "bound{S|}",      { Gv, Ma }, 0 },
11670     { EVEX_TABLE (EVEX_0F) },
11671   },
11672   {
11673     /* MOD_C4_32BIT */
11674     { "lesS",           { Gv, Mp }, 0 },
11675     { VEX_C4_TABLE (VEX_0F) },
11676   },
11677   {
11678     /* MOD_C5_32BIT */
11679     { "ldsS",           { Gv, Mp }, 0 },
11680     { VEX_C5_TABLE (VEX_0F) },
11681   },
11682   {
11683     /* MOD_VEX_0F12_PREFIX_0 */
11684     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11685     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11686   },
11687   {
11688     /* MOD_VEX_0F13 */
11689     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11690   },
11691   {
11692     /* MOD_VEX_0F16_PREFIX_0 */
11693     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11694     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11695   },
11696   {
11697     /* MOD_VEX_0F17 */
11698     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11699   },
11700   {
11701     /* MOD_VEX_0F2B */
11702     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11703   },
11704   {
11705     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11706     { Bad_Opcode },
11707     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11708   },
11709   {
11710     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11711     { Bad_Opcode },
11712     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11713   },
11714   {
11715     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11716     { Bad_Opcode },
11717     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11718   },
11719   {
11720     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11721     { Bad_Opcode },
11722     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11723   },
11724   {
11725     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11726     { Bad_Opcode },
11727     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11728   },
11729   {
11730     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11731     { Bad_Opcode },
11732     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11733   },
11734   {
11735     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11736     { Bad_Opcode },
11737     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11738   },
11739   {
11740     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11741     { Bad_Opcode },
11742     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11743   },
11744   {
11745     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11746     { Bad_Opcode },
11747     { "knotw",          { MaskG, MaskR }, 0 },
11748   },
11749   {
11750     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11751     { Bad_Opcode },
11752     { "knotq",          { MaskG, MaskR }, 0 },
11753   },
11754   {
11755     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11756     { Bad_Opcode },
11757     { "knotb",          { MaskG, MaskR }, 0 },
11758   },
11759   {
11760     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11761     { Bad_Opcode },
11762     { "knotd",          { MaskG, MaskR }, 0 },
11763   },
11764   {
11765     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11766     { Bad_Opcode },
11767     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11768   },
11769   {
11770     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11771     { Bad_Opcode },
11772     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11773   },
11774   {
11775     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11776     { Bad_Opcode },
11777     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11778   },
11779   {
11780     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11781     { Bad_Opcode },
11782     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11783   },
11784  {
11785     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11786     { Bad_Opcode },
11787     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11788   },
11789   {
11790     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11791     { Bad_Opcode },
11792     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11793   },
11794   {
11795     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11796     { Bad_Opcode },
11797     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11798   },
11799   {
11800     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11801     { Bad_Opcode },
11802     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
11803   },
11804   {
11805     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11806     { Bad_Opcode },
11807     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
11808   },
11809   {
11810     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11811     { Bad_Opcode },
11812     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
11813   },
11814   {
11815     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11816     { Bad_Opcode },
11817     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
11818   },
11819   {
11820     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11821     { Bad_Opcode },
11822     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
11823   },
11824   {
11825     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11826     { Bad_Opcode },
11827     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
11828   },
11829   {
11830     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11831     { Bad_Opcode },
11832     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
11833   },
11834   {
11835     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11836     { Bad_Opcode },
11837     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
11838   },
11839   {
11840     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11841     { Bad_Opcode },
11842     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
11843   },
11844   {
11845     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11846     { Bad_Opcode },
11847     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
11848   },
11849   {
11850     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11851     { Bad_Opcode },
11852     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
11853   },
11854   {
11855     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11856     { Bad_Opcode },
11857     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
11858   },
11859   {
11860     /* MOD_VEX_0F50 */
11861     { Bad_Opcode },
11862     { VEX_W_TABLE (VEX_W_0F50_M_0) },
11863   },
11864   {
11865     /* MOD_VEX_0F71_REG_2 */
11866     { Bad_Opcode },
11867     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11868   },
11869   {
11870     /* MOD_VEX_0F71_REG_4 */
11871     { Bad_Opcode },
11872     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11873   },
11874   {
11875     /* MOD_VEX_0F71_REG_6 */
11876     { Bad_Opcode },
11877     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11878   },
11879   {
11880     /* MOD_VEX_0F72_REG_2 */
11881     { Bad_Opcode },
11882     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11883   },
11884   {
11885     /* MOD_VEX_0F72_REG_4 */
11886     { Bad_Opcode },
11887     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11888   },
11889   {
11890     /* MOD_VEX_0F72_REG_6 */
11891     { Bad_Opcode },
11892     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11893   },
11894   {
11895     /* MOD_VEX_0F73_REG_2 */
11896     { Bad_Opcode },
11897     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11898   },
11899   {
11900     /* MOD_VEX_0F73_REG_3 */
11901     { Bad_Opcode },
11902     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11903   },
11904   {
11905     /* MOD_VEX_0F73_REG_6 */
11906     { Bad_Opcode },
11907     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11908   },
11909   {
11910     /* MOD_VEX_0F73_REG_7 */
11911     { Bad_Opcode },
11912     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11913   },
11914   {
11915     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11916     { "kmovw",          { Ew, MaskG }, 0 },
11917     { Bad_Opcode },
11918   },
11919   {
11920     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
11921     { "kmovq",          { Eq, MaskG }, 0 },
11922     { Bad_Opcode },
11923   },
11924   {
11925     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11926     { "kmovb",          { Eb, MaskG }, 0 },
11927     { Bad_Opcode },
11928   },
11929   {
11930     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
11931     { "kmovd",          { Ed, MaskG }, 0 },
11932     { Bad_Opcode },
11933   },
11934   {
11935     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
11936     { Bad_Opcode },
11937     { "kmovw",          { MaskG, Rdq }, 0 },
11938   },
11939   {
11940     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
11941     { Bad_Opcode },
11942     { "kmovb",          { MaskG, Rdq }, 0 },
11943   },
11944   {
11945     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
11946     { Bad_Opcode },
11947     { "kmovd",          { MaskG, Rdq }, 0 },
11948   },
11949   {
11950     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
11951     { Bad_Opcode },
11952     { "kmovq",          { MaskG, Rdq }, 0 },
11953   },
11954   {
11955     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
11956     { Bad_Opcode },
11957     { "kmovw",          { Gdq, MaskR }, 0 },
11958   },
11959   {
11960     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
11961     { Bad_Opcode },
11962     { "kmovb",          { Gdq, MaskR }, 0 },
11963   },
11964   {
11965     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
11966     { Bad_Opcode },
11967     { "kmovd",          { Gdq, MaskR }, 0 },
11968   },
11969   {
11970     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
11971     { Bad_Opcode },
11972     { "kmovq",          { Gdq, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
11976     { Bad_Opcode },
11977     { "kortestw", { MaskG, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
11981     { Bad_Opcode },
11982     { "kortestq", { MaskG, MaskR }, 0 },
11983   },
11984   {
11985     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
11986     { Bad_Opcode },
11987     { "kortestb", { MaskG, MaskR }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
11991     { Bad_Opcode },
11992     { "kortestd", { MaskG, MaskR }, 0 },
11993   },
11994   {
11995     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
11996     { Bad_Opcode },
11997     { "ktestw", { MaskG, MaskR }, 0 },
11998   },
11999   {
12000     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12001     { Bad_Opcode },
12002     { "ktestq", { MaskG, MaskR }, 0 },
12003   },
12004   {
12005     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12006     { Bad_Opcode },
12007     { "ktestb", { MaskG, MaskR }, 0 },
12008   },
12009   {
12010     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12011     { Bad_Opcode },
12012     { "ktestd", { MaskG, MaskR }, 0 },
12013   },
12014   {
12015     /* MOD_VEX_0FAE_REG_2 */
12016     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12017   },
12018   {
12019     /* MOD_VEX_0FAE_REG_3 */
12020     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12021   },
12022   {
12023     /* MOD_VEX_0FD7_PREFIX_2 */
12024     { Bad_Opcode },
12025     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12026   },
12027   {
12028     /* MOD_VEX_0FE7_PREFIX_2 */
12029     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12030   },
12031   {
12032     /* MOD_VEX_0FF0_PREFIX_3 */
12033     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12034   },
12035   {
12036     /* MOD_VEX_0F381A_PREFIX_2 */
12037     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12038   },
12039   {
12040     /* MOD_VEX_0F382A_PREFIX_2 */
12041     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12042   },
12043   {
12044     /* MOD_VEX_0F382C_PREFIX_2 */
12045     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12046   },
12047   {
12048     /* MOD_VEX_0F382D_PREFIX_2 */
12049     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12050   },
12051   {
12052     /* MOD_VEX_0F382E_PREFIX_2 */
12053     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12054   },
12055   {
12056     /* MOD_VEX_0F382F_PREFIX_2 */
12057     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12058   },
12059   {
12060     /* MOD_VEX_0F385A_PREFIX_2 */
12061     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12062   },
12063   {
12064     /* MOD_VEX_0F388C_PREFIX_2 */
12065     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12066   },
12067   {
12068     /* MOD_VEX_0F388E_PREFIX_2 */
12069     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12070   },
12071   {
12072     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12073     { Bad_Opcode },
12074     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12075   },
12076   {
12077     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12078     { Bad_Opcode },
12079     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12080   },
12081   {
12082     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12083     { Bad_Opcode },
12084     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12085   },
12086   {
12087     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12088     { Bad_Opcode },
12089     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12090   },
12091   {
12092     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12093     { Bad_Opcode },
12094     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12095   },
12096   {
12097     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12098     { Bad_Opcode },
12099     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12100   },
12101   {
12102     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12103     { Bad_Opcode },
12104     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12105   },
12106   {
12107     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12108     { Bad_Opcode },
12109     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12110   },
12111 #define NEED_MOD_TABLE
12112 #include "i386-dis-evex.h"
12113 #undef NEED_MOD_TABLE
12114 };
12115
12116 static const struct dis386 rm_table[][8] = {
12117   {
12118     /* RM_C6_REG_7 */
12119     { "xabort",         { Skip_MODRM, Ib }, 0 },
12120   },
12121   {
12122     /* RM_C7_REG_7 */
12123     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12124   },
12125   {
12126     /* RM_0F01_REG_0 */
12127     { Bad_Opcode },
12128     { "vmcall",         { Skip_MODRM }, 0 },
12129     { "vmlaunch",       { Skip_MODRM }, 0 },
12130     { "vmresume",       { Skip_MODRM }, 0 },
12131     { "vmxoff",         { Skip_MODRM }, 0 },
12132   },
12133   {
12134     /* RM_0F01_REG_1 */
12135     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12136     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12137     { "clac",           { Skip_MODRM }, 0 },
12138     { "stac",           { Skip_MODRM }, 0 },
12139     { Bad_Opcode },
12140     { Bad_Opcode },
12141     { Bad_Opcode },
12142     { "encls",          { Skip_MODRM }, 0 },
12143   },
12144   {
12145     /* RM_0F01_REG_2 */
12146     { "xgetbv",         { Skip_MODRM }, 0 },
12147     { "xsetbv",         { Skip_MODRM }, 0 },
12148     { Bad_Opcode },
12149     { Bad_Opcode },
12150     { "vmfunc",         { Skip_MODRM }, 0 },
12151     { "xend",           { Skip_MODRM }, 0 },
12152     { "xtest",          { Skip_MODRM }, 0 },
12153     { "enclu",          { Skip_MODRM }, 0 },
12154   },
12155   {
12156     /* RM_0F01_REG_3 */
12157     { "vmrun",          { Skip_MODRM }, 0 },
12158     { "vmmcall",        { Skip_MODRM }, 0 },
12159     { "vmload",         { Skip_MODRM }, 0 },
12160     { "vmsave",         { Skip_MODRM }, 0 },
12161     { "stgi",           { Skip_MODRM }, 0 },
12162     { "clgi",           { Skip_MODRM }, 0 },
12163     { "skinit",         { Skip_MODRM }, 0 },
12164     { "invlpga",        { Skip_MODRM }, 0 },
12165   },
12166   {
12167     /* RM_0F01_REG_5 */
12168     { Bad_Opcode },
12169     { Bad_Opcode },
12170     { Bad_Opcode },
12171     { Bad_Opcode },
12172     { Bad_Opcode },
12173     { Bad_Opcode },
12174     { "rdpkru",         { Skip_MODRM }, 0 },
12175     { "wrpkru",         { Skip_MODRM }, 0 },
12176   },
12177   {
12178     /* RM_0F01_REG_7 */
12179     { "swapgs",         { Skip_MODRM }, 0  },
12180     { "rdtscp",         { Skip_MODRM }, 0  },
12181     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12182     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12183     { "clzero",         { Skip_MODRM }, 0  },
12184   },
12185   {
12186     /* RM_0FAE_REG_5 */
12187     { "lfence",         { Skip_MODRM }, 0 },
12188   },
12189   {
12190     /* RM_0FAE_REG_6 */
12191     { "mfence",         { Skip_MODRM }, 0 },
12192   },
12193   {
12194     /* RM_0FAE_REG_7 */
12195     { "sfence",         { Skip_MODRM }, 0 },
12196
12197   },
12198 };
12199
12200 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12201
12202 /* We use the high bit to indicate different name for the same
12203    prefix.  */
12204 #define REP_PREFIX      (0xf3 | 0x100)
12205 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12206 #define XRELEASE_PREFIX (0xf3 | 0x400)
12207 #define BND_PREFIX      (0xf2 | 0x400)
12208
12209 static int
12210 ckprefix (void)
12211 {
12212   int newrex, i, length;
12213   rex = 0;
12214   rex_ignored = 0;
12215   prefixes = 0;
12216   used_prefixes = 0;
12217   rex_used = 0;
12218   last_lock_prefix = -1;
12219   last_repz_prefix = -1;
12220   last_repnz_prefix = -1;
12221   last_data_prefix = -1;
12222   last_addr_prefix = -1;
12223   last_rex_prefix = -1;
12224   last_seg_prefix = -1;
12225   fwait_prefix = -1;
12226   active_seg_prefix = 0;
12227   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12228     all_prefixes[i] = 0;
12229   i = 0;
12230   length = 0;
12231   /* The maximum instruction length is 15bytes.  */
12232   while (length < MAX_CODE_LENGTH - 1)
12233     {
12234       FETCH_DATA (the_info, codep + 1);
12235       newrex = 0;
12236       switch (*codep)
12237         {
12238         /* REX prefixes family.  */
12239         case 0x40:
12240         case 0x41:
12241         case 0x42:
12242         case 0x43:
12243         case 0x44:
12244         case 0x45:
12245         case 0x46:
12246         case 0x47:
12247         case 0x48:
12248         case 0x49:
12249         case 0x4a:
12250         case 0x4b:
12251         case 0x4c:
12252         case 0x4d:
12253         case 0x4e:
12254         case 0x4f:
12255           if (address_mode == mode_64bit)
12256             newrex = *codep;
12257           else
12258             return 1;
12259           last_rex_prefix = i;
12260           break;
12261         case 0xf3:
12262           prefixes |= PREFIX_REPZ;
12263           last_repz_prefix = i;
12264           break;
12265         case 0xf2:
12266           prefixes |= PREFIX_REPNZ;
12267           last_repnz_prefix = i;
12268           break;
12269         case 0xf0:
12270           prefixes |= PREFIX_LOCK;
12271           last_lock_prefix = i;
12272           break;
12273         case 0x2e:
12274           prefixes |= PREFIX_CS;
12275           last_seg_prefix = i;
12276           active_seg_prefix = PREFIX_CS;
12277           break;
12278         case 0x36:
12279           prefixes |= PREFIX_SS;
12280           last_seg_prefix = i;
12281           active_seg_prefix = PREFIX_SS;
12282           break;
12283         case 0x3e:
12284           prefixes |= PREFIX_DS;
12285           last_seg_prefix = i;
12286           active_seg_prefix = PREFIX_DS;
12287           break;
12288         case 0x26:
12289           prefixes |= PREFIX_ES;
12290           last_seg_prefix = i;
12291           active_seg_prefix = PREFIX_ES;
12292           break;
12293         case 0x64:
12294           prefixes |= PREFIX_FS;
12295           last_seg_prefix = i;
12296           active_seg_prefix = PREFIX_FS;
12297           break;
12298         case 0x65:
12299           prefixes |= PREFIX_GS;
12300           last_seg_prefix = i;
12301           active_seg_prefix = PREFIX_GS;
12302           break;
12303         case 0x66:
12304           prefixes |= PREFIX_DATA;
12305           last_data_prefix = i;
12306           break;
12307         case 0x67:
12308           prefixes |= PREFIX_ADDR;
12309           last_addr_prefix = i;
12310           break;
12311         case FWAIT_OPCODE:
12312           /* fwait is really an instruction.  If there are prefixes
12313              before the fwait, they belong to the fwait, *not* to the
12314              following instruction.  */
12315           fwait_prefix = i;
12316           if (prefixes || rex)
12317             {
12318               prefixes |= PREFIX_FWAIT;
12319               codep++;
12320               /* This ensures that the previous REX prefixes are noticed
12321                  as unused prefixes, as in the return case below.  */
12322               rex_used = rex;
12323               return 1;
12324             }
12325           prefixes = PREFIX_FWAIT;
12326           break;
12327         default:
12328           return 1;
12329         }
12330       /* Rex is ignored when followed by another prefix.  */
12331       if (rex)
12332         {
12333           rex_used = rex;
12334           return 1;
12335         }
12336       if (*codep != FWAIT_OPCODE)
12337         all_prefixes[i++] = *codep;
12338       rex = newrex;
12339       codep++;
12340       length++;
12341     }
12342   return 0;
12343 }
12344
12345 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12346    prefix byte.  */
12347
12348 static const char *
12349 prefix_name (int pref, int sizeflag)
12350 {
12351   static const char *rexes [16] =
12352     {
12353       "rex",            /* 0x40 */
12354       "rex.B",          /* 0x41 */
12355       "rex.X",          /* 0x42 */
12356       "rex.XB",         /* 0x43 */
12357       "rex.R",          /* 0x44 */
12358       "rex.RB",         /* 0x45 */
12359       "rex.RX",         /* 0x46 */
12360       "rex.RXB",        /* 0x47 */
12361       "rex.W",          /* 0x48 */
12362       "rex.WB",         /* 0x49 */
12363       "rex.WX",         /* 0x4a */
12364       "rex.WXB",        /* 0x4b */
12365       "rex.WR",         /* 0x4c */
12366       "rex.WRB",        /* 0x4d */
12367       "rex.WRX",        /* 0x4e */
12368       "rex.WRXB",       /* 0x4f */
12369     };
12370
12371   switch (pref)
12372     {
12373     /* REX prefixes family.  */
12374     case 0x40:
12375     case 0x41:
12376     case 0x42:
12377     case 0x43:
12378     case 0x44:
12379     case 0x45:
12380     case 0x46:
12381     case 0x47:
12382     case 0x48:
12383     case 0x49:
12384     case 0x4a:
12385     case 0x4b:
12386     case 0x4c:
12387     case 0x4d:
12388     case 0x4e:
12389     case 0x4f:
12390       return rexes [pref - 0x40];
12391     case 0xf3:
12392       return "repz";
12393     case 0xf2:
12394       return "repnz";
12395     case 0xf0:
12396       return "lock";
12397     case 0x2e:
12398       return "cs";
12399     case 0x36:
12400       return "ss";
12401     case 0x3e:
12402       return "ds";
12403     case 0x26:
12404       return "es";
12405     case 0x64:
12406       return "fs";
12407     case 0x65:
12408       return "gs";
12409     case 0x66:
12410       return (sizeflag & DFLAG) ? "data16" : "data32";
12411     case 0x67:
12412       if (address_mode == mode_64bit)
12413         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12414       else
12415         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12416     case FWAIT_OPCODE:
12417       return "fwait";
12418     case REP_PREFIX:
12419       return "rep";
12420     case XACQUIRE_PREFIX:
12421       return "xacquire";
12422     case XRELEASE_PREFIX:
12423       return "xrelease";
12424     case BND_PREFIX:
12425       return "bnd";
12426     default:
12427       return NULL;
12428     }
12429 }
12430
12431 static char op_out[MAX_OPERANDS][100];
12432 static int op_ad, op_index[MAX_OPERANDS];
12433 static int two_source_ops;
12434 static bfd_vma op_address[MAX_OPERANDS];
12435 static bfd_vma op_riprel[MAX_OPERANDS];
12436 static bfd_vma start_pc;
12437
12438 /*
12439  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12440  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12441  *   section of the "Virtual 8086 Mode" chapter.)
12442  * 'pc' should be the address of this instruction, it will
12443  *   be used to print the target address if this is a relative jump or call
12444  * The function returns the length of this instruction in bytes.
12445  */
12446
12447 static char intel_syntax;
12448 static char intel_mnemonic = !SYSV386_COMPAT;
12449 static char open_char;
12450 static char close_char;
12451 static char separator_char;
12452 static char scale_char;
12453
12454 enum x86_64_isa
12455 {
12456   amd64 = 0,
12457   intel64
12458 };
12459
12460 static enum x86_64_isa isa64;
12461
12462 /* Here for backwards compatibility.  When gdb stops using
12463    print_insn_i386_att and print_insn_i386_intel these functions can
12464    disappear, and print_insn_i386 be merged into print_insn.  */
12465 int
12466 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12467 {
12468   intel_syntax = 0;
12469
12470   return print_insn (pc, info);
12471 }
12472
12473 int
12474 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12475 {
12476   intel_syntax = 1;
12477
12478   return print_insn (pc, info);
12479 }
12480
12481 int
12482 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12483 {
12484   intel_syntax = -1;
12485
12486   return print_insn (pc, info);
12487 }
12488
12489 void
12490 print_i386_disassembler_options (FILE *stream)
12491 {
12492   fprintf (stream, _("\n\
12493 The following i386/x86-64 specific disassembler options are supported for use\n\
12494 with the -M switch (multiple options should be separated by commas):\n"));
12495
12496   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12497   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12498   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12499   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12500   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12501   fprintf (stream, _("  att-mnemonic\n"
12502                      "              Display instruction in AT&T mnemonic\n"));
12503   fprintf (stream, _("  intel-mnemonic\n"
12504                      "              Display instruction in Intel mnemonic\n"));
12505   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12506   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12507   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12508   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12509   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12510   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12511   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12512   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12513 }
12514
12515 /* Bad opcode.  */
12516 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12517
12518 /* Get a pointer to struct dis386 with a valid name.  */
12519
12520 static const struct dis386 *
12521 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12522 {
12523   int vindex, vex_table_index;
12524
12525   if (dp->name != NULL)
12526     return dp;
12527
12528   switch (dp->op[0].bytemode)
12529     {
12530     case USE_REG_TABLE:
12531       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12532       break;
12533
12534     case USE_MOD_TABLE:
12535       vindex = modrm.mod == 0x3 ? 1 : 0;
12536       dp = &mod_table[dp->op[1].bytemode][vindex];
12537       break;
12538
12539     case USE_RM_TABLE:
12540       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12541       break;
12542
12543     case USE_PREFIX_TABLE:
12544       if (need_vex)
12545         {
12546           /* The prefix in VEX is implicit.  */
12547           switch (vex.prefix)
12548             {
12549             case 0:
12550               vindex = 0;
12551               break;
12552             case REPE_PREFIX_OPCODE:
12553               vindex = 1;
12554               break;
12555             case DATA_PREFIX_OPCODE:
12556               vindex = 2;
12557               break;
12558             case REPNE_PREFIX_OPCODE:
12559               vindex = 3;
12560               break;
12561             default:
12562               abort ();
12563               break;
12564             }
12565         }
12566       else
12567         {
12568           int last_prefix = -1;
12569           int prefix = 0;
12570           vindex = 0;
12571           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12572              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12573              last one wins.  */
12574           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12575             {
12576               if (last_repz_prefix > last_repnz_prefix)
12577                 {
12578                   vindex = 1;
12579                   prefix = PREFIX_REPZ;
12580                   last_prefix = last_repz_prefix;
12581                 }
12582               else
12583                 {
12584                   vindex = 3;
12585                   prefix = PREFIX_REPNZ;
12586                   last_prefix = last_repnz_prefix;
12587                 }
12588
12589               /* Check if prefix should be ignored.  */
12590               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12591                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12592                    & prefix) != 0)
12593                 vindex = 0;
12594             }
12595
12596           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12597             {
12598               vindex = 2;
12599               prefix = PREFIX_DATA;
12600               last_prefix = last_data_prefix;
12601             }
12602
12603           if (vindex != 0)
12604             {
12605               used_prefixes |= prefix;
12606               all_prefixes[last_prefix] = 0;
12607             }
12608         }
12609       dp = &prefix_table[dp->op[1].bytemode][vindex];
12610       break;
12611
12612     case USE_X86_64_TABLE:
12613       vindex = address_mode == mode_64bit ? 1 : 0;
12614       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12615       break;
12616
12617     case USE_3BYTE_TABLE:
12618       FETCH_DATA (info, codep + 2);
12619       vindex = *codep++;
12620       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12621       end_codep = codep;
12622       modrm.mod = (*codep >> 6) & 3;
12623       modrm.reg = (*codep >> 3) & 7;
12624       modrm.rm = *codep & 7;
12625       break;
12626
12627     case USE_VEX_LEN_TABLE:
12628       if (!need_vex)
12629         abort ();
12630
12631       switch (vex.length)
12632         {
12633         case 128:
12634           vindex = 0;
12635           break;
12636         case 256:
12637           vindex = 1;
12638           break;
12639         default:
12640           abort ();
12641           break;
12642         }
12643
12644       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12645       break;
12646
12647     case USE_XOP_8F_TABLE:
12648       FETCH_DATA (info, codep + 3);
12649       /* All bits in the REX prefix are ignored.  */
12650       rex_ignored = rex;
12651       rex = ~(*codep >> 5) & 0x7;
12652
12653       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12654       switch ((*codep & 0x1f))
12655         {
12656         default:
12657           dp = &bad_opcode;
12658           return dp;
12659         case 0x8:
12660           vex_table_index = XOP_08;
12661           break;
12662         case 0x9:
12663           vex_table_index = XOP_09;
12664           break;
12665         case 0xa:
12666           vex_table_index = XOP_0A;
12667           break;
12668         }
12669       codep++;
12670       vex.w = *codep & 0x80;
12671       if (vex.w && address_mode == mode_64bit)
12672         rex |= REX_W;
12673
12674       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12675       if (address_mode != mode_64bit)
12676         {
12677           /* In 16/32-bit mode REX_B is silently ignored.  */
12678           rex &= ~REX_B;
12679           if (vex.register_specifier > 0x7)
12680             {
12681               dp = &bad_opcode;
12682               return dp;
12683             }
12684         }
12685
12686       vex.length = (*codep & 0x4) ? 256 : 128;
12687       switch ((*codep & 0x3))
12688         {
12689         case 0:
12690           vex.prefix = 0;
12691           break;
12692         case 1:
12693           vex.prefix = DATA_PREFIX_OPCODE;
12694           break;
12695         case 2:
12696           vex.prefix = REPE_PREFIX_OPCODE;
12697           break;
12698         case 3:
12699           vex.prefix = REPNE_PREFIX_OPCODE;
12700           break;
12701         }
12702       need_vex = 1;
12703       need_vex_reg = 1;
12704       codep++;
12705       vindex = *codep++;
12706       dp = &xop_table[vex_table_index][vindex];
12707
12708       end_codep = codep;
12709       FETCH_DATA (info, codep + 1);
12710       modrm.mod = (*codep >> 6) & 3;
12711       modrm.reg = (*codep >> 3) & 7;
12712       modrm.rm = *codep & 7;
12713       break;
12714
12715     case USE_VEX_C4_TABLE:
12716       /* VEX prefix.  */
12717       FETCH_DATA (info, codep + 3);
12718       /* All bits in the REX prefix are ignored.  */
12719       rex_ignored = rex;
12720       rex = ~(*codep >> 5) & 0x7;
12721       switch ((*codep & 0x1f))
12722         {
12723         default:
12724           dp = &bad_opcode;
12725           return dp;
12726         case 0x1:
12727           vex_table_index = VEX_0F;
12728           break;
12729         case 0x2:
12730           vex_table_index = VEX_0F38;
12731           break;
12732         case 0x3:
12733           vex_table_index = VEX_0F3A;
12734           break;
12735         }
12736       codep++;
12737       vex.w = *codep & 0x80;
12738       if (address_mode == mode_64bit)
12739         {
12740           if (vex.w)
12741             rex |= REX_W;
12742           vex.register_specifier = (~(*codep >> 3)) & 0xf;
12743         }
12744       else
12745         {
12746           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12747              is ignored, other REX bits are 0 and the highest bit in
12748              VEX.vvvv is also ignored.  */
12749           rex = 0;
12750           vex.register_specifier = (~(*codep >> 3)) & 0x7;
12751         }
12752       vex.length = (*codep & 0x4) ? 256 : 128;
12753       switch ((*codep & 0x3))
12754         {
12755         case 0:
12756           vex.prefix = 0;
12757           break;
12758         case 1:
12759           vex.prefix = DATA_PREFIX_OPCODE;
12760           break;
12761         case 2:
12762           vex.prefix = REPE_PREFIX_OPCODE;
12763           break;
12764         case 3:
12765           vex.prefix = REPNE_PREFIX_OPCODE;
12766           break;
12767         }
12768       need_vex = 1;
12769       need_vex_reg = 1;
12770       codep++;
12771       vindex = *codep++;
12772       dp = &vex_table[vex_table_index][vindex];
12773       end_codep = codep;
12774       /* There is no MODRM byte for VEX [82|77].  */
12775       if (vindex != 0x77 && vindex != 0x82)
12776         {
12777           FETCH_DATA (info, codep + 1);
12778           modrm.mod = (*codep >> 6) & 3;
12779           modrm.reg = (*codep >> 3) & 7;
12780           modrm.rm = *codep & 7;
12781         }
12782       break;
12783
12784     case USE_VEX_C5_TABLE:
12785       /* VEX prefix.  */
12786       FETCH_DATA (info, codep + 2);
12787       /* All bits in the REX prefix are ignored.  */
12788       rex_ignored = rex;
12789       rex = (*codep & 0x80) ? 0 : REX_R;
12790
12791       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12792          VEX.vvvv is 1.  */
12793       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12794       vex.w = 0;
12795       vex.length = (*codep & 0x4) ? 256 : 128;
12796       switch ((*codep & 0x3))
12797         {
12798         case 0:
12799           vex.prefix = 0;
12800           break;
12801         case 1:
12802           vex.prefix = DATA_PREFIX_OPCODE;
12803           break;
12804         case 2:
12805           vex.prefix = REPE_PREFIX_OPCODE;
12806           break;
12807         case 3:
12808           vex.prefix = REPNE_PREFIX_OPCODE;
12809           break;
12810         }
12811       need_vex = 1;
12812       need_vex_reg = 1;
12813       codep++;
12814       vindex = *codep++;
12815       dp = &vex_table[dp->op[1].bytemode][vindex];
12816       end_codep = codep;
12817       /* There is no MODRM byte for VEX [82|77].  */
12818       if (vindex != 0x77 && vindex != 0x82)
12819         {
12820           FETCH_DATA (info, codep + 1);
12821           modrm.mod = (*codep >> 6) & 3;
12822           modrm.reg = (*codep >> 3) & 7;
12823           modrm.rm = *codep & 7;
12824         }
12825       break;
12826
12827     case USE_VEX_W_TABLE:
12828       if (!need_vex)
12829         abort ();
12830
12831       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12832       break;
12833
12834     case USE_EVEX_TABLE:
12835       two_source_ops = 0;
12836       /* EVEX prefix.  */
12837       vex.evex = 1;
12838       FETCH_DATA (info, codep + 4);
12839       /* All bits in the REX prefix are ignored.  */
12840       rex_ignored = rex;
12841       /* The first byte after 0x62.  */
12842       rex = ~(*codep >> 5) & 0x7;
12843       vex.r = *codep & 0x10;
12844       switch ((*codep & 0xf))
12845         {
12846         default:
12847           return &bad_opcode;
12848         case 0x1:
12849           vex_table_index = EVEX_0F;
12850           break;
12851         case 0x2:
12852           vex_table_index = EVEX_0F38;
12853           break;
12854         case 0x3:
12855           vex_table_index = EVEX_0F3A;
12856           break;
12857         }
12858
12859       /* The second byte after 0x62.  */
12860       codep++;
12861       vex.w = *codep & 0x80;
12862       if (vex.w && address_mode == mode_64bit)
12863         rex |= REX_W;
12864
12865       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12866       if (address_mode != mode_64bit)
12867         {
12868           /* In 16/32-bit mode silently ignore following bits.  */
12869           rex &= ~REX_B;
12870           vex.r = 1;
12871           vex.v = 1;
12872           vex.register_specifier &= 0x7;
12873         }
12874
12875       /* The U bit.  */
12876       if (!(*codep & 0x4))
12877         return &bad_opcode;
12878
12879       switch ((*codep & 0x3))
12880         {
12881         case 0:
12882           vex.prefix = 0;
12883           break;
12884         case 1:
12885           vex.prefix = DATA_PREFIX_OPCODE;
12886           break;
12887         case 2:
12888           vex.prefix = REPE_PREFIX_OPCODE;
12889           break;
12890         case 3:
12891           vex.prefix = REPNE_PREFIX_OPCODE;
12892           break;
12893         }
12894
12895       /* The third byte after 0x62.  */
12896       codep++;
12897
12898       /* Remember the static rounding bits.  */
12899       vex.ll = (*codep >> 5) & 3;
12900       vex.b = (*codep & 0x10) != 0;
12901
12902       vex.v = *codep & 0x8;
12903       vex.mask_register_specifier = *codep & 0x7;
12904       vex.zeroing = *codep & 0x80;
12905
12906       need_vex = 1;
12907       need_vex_reg = 1;
12908       codep++;
12909       vindex = *codep++;
12910       dp = &evex_table[vex_table_index][vindex];
12911       end_codep = codep;
12912       FETCH_DATA (info, codep + 1);
12913       modrm.mod = (*codep >> 6) & 3;
12914       modrm.reg = (*codep >> 3) & 7;
12915       modrm.rm = *codep & 7;
12916
12917       /* Set vector length.  */
12918       if (modrm.mod == 3 && vex.b)
12919         vex.length = 512;
12920       else
12921         {
12922           switch (vex.ll)
12923             {
12924             case 0x0:
12925               vex.length = 128;
12926               break;
12927             case 0x1:
12928               vex.length = 256;
12929               break;
12930             case 0x2:
12931               vex.length = 512;
12932               break;
12933             default:
12934               return &bad_opcode;
12935             }
12936         }
12937       break;
12938
12939     case 0:
12940       dp = &bad_opcode;
12941       break;
12942
12943     default:
12944       abort ();
12945     }
12946
12947   if (dp->name != NULL)
12948     return dp;
12949   else
12950     return get_valid_dis386 (dp, info);
12951 }
12952
12953 static void
12954 get_sib (disassemble_info *info, int sizeflag)
12955 {
12956   /* If modrm.mod == 3, operand must be register.  */
12957   if (need_modrm
12958       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12959       && modrm.mod != 3
12960       && modrm.rm == 4)
12961     {
12962       FETCH_DATA (info, codep + 2);
12963       sib.index = (codep [1] >> 3) & 7;
12964       sib.scale = (codep [1] >> 6) & 3;
12965       sib.base = codep [1] & 7;
12966     }
12967 }
12968
12969 static int
12970 print_insn (bfd_vma pc, disassemble_info *info)
12971 {
12972   const struct dis386 *dp;
12973   int i;
12974   char *op_txt[MAX_OPERANDS];
12975   int needcomma;
12976   int sizeflag, orig_sizeflag;
12977   const char *p;
12978   struct dis_private priv;
12979   int prefix_length;
12980
12981   priv.orig_sizeflag = AFLAG | DFLAG;
12982   if ((info->mach & bfd_mach_i386_i386) != 0)
12983     address_mode = mode_32bit;
12984   else if (info->mach == bfd_mach_i386_i8086)
12985     {
12986       address_mode = mode_16bit;
12987       priv.orig_sizeflag = 0;
12988     }
12989   else
12990     address_mode = mode_64bit;
12991
12992   if (intel_syntax == (char) -1)
12993     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12994
12995   for (p = info->disassembler_options; p != NULL; )
12996     {
12997       if (CONST_STRNEQ (p, "amd64"))
12998         isa64 = amd64;
12999       else if (CONST_STRNEQ (p, "intel64"))
13000         isa64 = intel64;
13001       else if (CONST_STRNEQ (p, "x86-64"))
13002         {
13003           address_mode = mode_64bit;
13004           priv.orig_sizeflag = AFLAG | DFLAG;
13005         }
13006       else if (CONST_STRNEQ (p, "i386"))
13007         {
13008           address_mode = mode_32bit;
13009           priv.orig_sizeflag = AFLAG | DFLAG;
13010         }
13011       else if (CONST_STRNEQ (p, "i8086"))
13012         {
13013           address_mode = mode_16bit;
13014           priv.orig_sizeflag = 0;
13015         }
13016       else if (CONST_STRNEQ (p, "intel"))
13017         {
13018           intel_syntax = 1;
13019           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13020             intel_mnemonic = 1;
13021         }
13022       else if (CONST_STRNEQ (p, "att"))
13023         {
13024           intel_syntax = 0;
13025           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13026             intel_mnemonic = 0;
13027         }
13028       else if (CONST_STRNEQ (p, "addr"))
13029         {
13030           if (address_mode == mode_64bit)
13031             {
13032               if (p[4] == '3' && p[5] == '2')
13033                 priv.orig_sizeflag &= ~AFLAG;
13034               else if (p[4] == '6' && p[5] == '4')
13035                 priv.orig_sizeflag |= AFLAG;
13036             }
13037           else
13038             {
13039               if (p[4] == '1' && p[5] == '6')
13040                 priv.orig_sizeflag &= ~AFLAG;
13041               else if (p[4] == '3' && p[5] == '2')
13042                 priv.orig_sizeflag |= AFLAG;
13043             }
13044         }
13045       else if (CONST_STRNEQ (p, "data"))
13046         {
13047           if (p[4] == '1' && p[5] == '6')
13048             priv.orig_sizeflag &= ~DFLAG;
13049           else if (p[4] == '3' && p[5] == '2')
13050             priv.orig_sizeflag |= DFLAG;
13051         }
13052       else if (CONST_STRNEQ (p, "suffix"))
13053         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13054
13055       p = strchr (p, ',');
13056       if (p != NULL)
13057         p++;
13058     }
13059
13060   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13061     {
13062       (*info->fprintf_func) (info->stream,
13063                              _("64-bit address is disabled"));
13064       return -1;
13065     }
13066
13067   if (intel_syntax)
13068     {
13069       names64 = intel_names64;
13070       names32 = intel_names32;
13071       names16 = intel_names16;
13072       names8 = intel_names8;
13073       names8rex = intel_names8rex;
13074       names_seg = intel_names_seg;
13075       names_mm = intel_names_mm;
13076       names_bnd = intel_names_bnd;
13077       names_xmm = intel_names_xmm;
13078       names_ymm = intel_names_ymm;
13079       names_zmm = intel_names_zmm;
13080       index64 = intel_index64;
13081       index32 = intel_index32;
13082       names_mask = intel_names_mask;
13083       index16 = intel_index16;
13084       open_char = '[';
13085       close_char = ']';
13086       separator_char = '+';
13087       scale_char = '*';
13088     }
13089   else
13090     {
13091       names64 = att_names64;
13092       names32 = att_names32;
13093       names16 = att_names16;
13094       names8 = att_names8;
13095       names8rex = att_names8rex;
13096       names_seg = att_names_seg;
13097       names_mm = att_names_mm;
13098       names_bnd = att_names_bnd;
13099       names_xmm = att_names_xmm;
13100       names_ymm = att_names_ymm;
13101       names_zmm = att_names_zmm;
13102       index64 = att_index64;
13103       index32 = att_index32;
13104       names_mask = att_names_mask;
13105       index16 = att_index16;
13106       open_char = '(';
13107       close_char =  ')';
13108       separator_char = ',';
13109       scale_char = ',';
13110     }
13111
13112   /* The output looks better if we put 7 bytes on a line, since that
13113      puts most long word instructions on a single line.  Use 8 bytes
13114      for Intel L1OM.  */
13115   if ((info->mach & bfd_mach_l1om) != 0)
13116     info->bytes_per_line = 8;
13117   else
13118     info->bytes_per_line = 7;
13119
13120   info->private_data = &priv;
13121   priv.max_fetched = priv.the_buffer;
13122   priv.insn_start = pc;
13123
13124   obuf[0] = 0;
13125   for (i = 0; i < MAX_OPERANDS; ++i)
13126     {
13127       op_out[i][0] = 0;
13128       op_index[i] = -1;
13129     }
13130
13131   the_info = info;
13132   start_pc = pc;
13133   start_codep = priv.the_buffer;
13134   codep = priv.the_buffer;
13135
13136   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13137     {
13138       const char *name;
13139
13140       /* Getting here means we tried for data but didn't get it.  That
13141          means we have an incomplete instruction of some sort.  Just
13142          print the first byte as a prefix or a .byte pseudo-op.  */
13143       if (codep > priv.the_buffer)
13144         {
13145           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13146           if (name != NULL)
13147             (*info->fprintf_func) (info->stream, "%s", name);
13148           else
13149             {
13150               /* Just print the first byte as a .byte instruction.  */
13151               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13152                                      (unsigned int) priv.the_buffer[0]);
13153             }
13154
13155           return 1;
13156         }
13157
13158       return -1;
13159     }
13160
13161   obufp = obuf;
13162   sizeflag = priv.orig_sizeflag;
13163
13164   if (!ckprefix () || rex_used)
13165     {
13166       /* Too many prefixes or unused REX prefixes.  */
13167       for (i = 0;
13168            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13169            i++)
13170         (*info->fprintf_func) (info->stream, "%s%s",
13171                                i == 0 ? "" : " ",
13172                                prefix_name (all_prefixes[i], sizeflag));
13173       return i;
13174     }
13175
13176   insn_codep = codep;
13177
13178   FETCH_DATA (info, codep + 1);
13179   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13180
13181   if (((prefixes & PREFIX_FWAIT)
13182        && ((*codep < 0xd8) || (*codep > 0xdf))))
13183     {
13184       /* Handle prefixes before fwait.  */
13185       for (i = 0; i < fwait_prefix && all_prefixes[i];
13186            i++)
13187         (*info->fprintf_func) (info->stream, "%s ",
13188                                prefix_name (all_prefixes[i], sizeflag));
13189       (*info->fprintf_func) (info->stream, "fwait");
13190       return i + 1;
13191     }
13192
13193   if (*codep == 0x0f)
13194     {
13195       unsigned char threebyte;
13196
13197       codep++;
13198       FETCH_DATA (info, codep + 1);
13199       threebyte = *codep;
13200       dp = &dis386_twobyte[threebyte];
13201       need_modrm = twobyte_has_modrm[*codep];
13202       codep++;
13203     }
13204   else
13205     {
13206       dp = &dis386[*codep];
13207       need_modrm = onebyte_has_modrm[*codep];
13208       codep++;
13209     }
13210
13211   /* Save sizeflag for printing the extra prefixes later before updating
13212      it for mnemonic and operand processing.  The prefix names depend
13213      only on the address mode.  */
13214   orig_sizeflag = sizeflag;
13215   if (prefixes & PREFIX_ADDR)
13216     sizeflag ^= AFLAG;
13217   if ((prefixes & PREFIX_DATA))
13218     sizeflag ^= DFLAG;
13219
13220   end_codep = codep;
13221   if (need_modrm)
13222     {
13223       FETCH_DATA (info, codep + 1);
13224       modrm.mod = (*codep >> 6) & 3;
13225       modrm.reg = (*codep >> 3) & 7;
13226       modrm.rm = *codep & 7;
13227     }
13228
13229   need_vex = 0;
13230   need_vex_reg = 0;
13231   vex_w_done = 0;
13232   vex.evex = 0;
13233
13234   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13235     {
13236       get_sib (info, sizeflag);
13237       dofloat (sizeflag);
13238     }
13239   else
13240     {
13241       dp = get_valid_dis386 (dp, info);
13242       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13243         {
13244           get_sib (info, sizeflag);
13245           for (i = 0; i < MAX_OPERANDS; ++i)
13246             {
13247               obufp = op_out[i];
13248               op_ad = MAX_OPERANDS - 1 - i;
13249               if (dp->op[i].rtn)
13250                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13251               /* For EVEX instruction after the last operand masking
13252                  should be printed.  */
13253               if (i == 0 && vex.evex)
13254                 {
13255                   /* Don't print {%k0}.  */
13256                   if (vex.mask_register_specifier)
13257                     {
13258                       oappend ("{");
13259                       oappend (names_mask[vex.mask_register_specifier]);
13260                       oappend ("}");
13261                     }
13262                   if (vex.zeroing)
13263                     oappend ("{z}");
13264                 }
13265             }
13266         }
13267     }
13268
13269   /* Check if the REX prefix is used.  */
13270   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13271     all_prefixes[last_rex_prefix] = 0;
13272
13273   /* Check if the SEG prefix is used.  */
13274   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13275                    | PREFIX_FS | PREFIX_GS)) != 0
13276       && (used_prefixes & active_seg_prefix) != 0)
13277     all_prefixes[last_seg_prefix] = 0;
13278
13279   /* Check if the ADDR prefix is used.  */
13280   if ((prefixes & PREFIX_ADDR) != 0
13281       && (used_prefixes & PREFIX_ADDR) != 0)
13282     all_prefixes[last_addr_prefix] = 0;
13283
13284   /* Check if the DATA prefix is used.  */
13285   if ((prefixes & PREFIX_DATA) != 0
13286       && (used_prefixes & PREFIX_DATA) != 0)
13287     all_prefixes[last_data_prefix] = 0;
13288
13289   /* Print the extra prefixes.  */
13290   prefix_length = 0;
13291   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13292     if (all_prefixes[i])
13293       {
13294         const char *name;
13295         name = prefix_name (all_prefixes[i], orig_sizeflag);
13296         if (name == NULL)
13297           abort ();
13298         prefix_length += strlen (name) + 1;
13299         (*info->fprintf_func) (info->stream, "%s ", name);
13300       }
13301
13302   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13303      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13304      used by putop and MMX/SSE operand and may be overriden by the
13305      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13306      separately.  */
13307   if (dp->prefix_requirement == PREFIX_OPCODE
13308       && dp != &bad_opcode
13309       && (((prefixes
13310             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13311            && (used_prefixes
13312                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13313           || ((((prefixes
13314                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13315                 == PREFIX_DATA)
13316                && (used_prefixes & PREFIX_DATA) == 0))))
13317     {
13318       (*info->fprintf_func) (info->stream, "(bad)");
13319       return end_codep - priv.the_buffer;
13320     }
13321
13322   /* Check maximum code length.  */
13323   if ((codep - start_codep) > MAX_CODE_LENGTH)
13324     {
13325       (*info->fprintf_func) (info->stream, "(bad)");
13326       return MAX_CODE_LENGTH;
13327     }
13328
13329   obufp = mnemonicendp;
13330   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13331     oappend (" ");
13332   oappend (" ");
13333   (*info->fprintf_func) (info->stream, "%s", obuf);
13334
13335   /* The enter and bound instructions are printed with operands in the same
13336      order as the intel book; everything else is printed in reverse order.  */
13337   if (intel_syntax || two_source_ops)
13338     {
13339       bfd_vma riprel;
13340
13341       for (i = 0; i < MAX_OPERANDS; ++i)
13342         op_txt[i] = op_out[i];
13343
13344       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13345           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13346         {
13347           op_txt[2] = op_out[3];
13348           op_txt[3] = op_out[2];
13349         }
13350
13351       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13352         {
13353           op_ad = op_index[i];
13354           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13355           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13356           riprel = op_riprel[i];
13357           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13358           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13359         }
13360     }
13361   else
13362     {
13363       for (i = 0; i < MAX_OPERANDS; ++i)
13364         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13365     }
13366
13367   needcomma = 0;
13368   for (i = 0; i < MAX_OPERANDS; ++i)
13369     if (*op_txt[i])
13370       {
13371         if (needcomma)
13372           (*info->fprintf_func) (info->stream, ",");
13373         if (op_index[i] != -1 && !op_riprel[i])
13374           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13375         else
13376           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13377         needcomma = 1;
13378       }
13379
13380   for (i = 0; i < MAX_OPERANDS; i++)
13381     if (op_index[i] != -1 && op_riprel[i])
13382       {
13383         (*info->fprintf_func) (info->stream, "        # ");
13384         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13385                                                 + op_address[op_index[i]]), info);
13386         break;
13387       }
13388   return codep - priv.the_buffer;
13389 }
13390
13391 static const char *float_mem[] = {
13392   /* d8 */
13393   "fadd{s|}",
13394   "fmul{s|}",
13395   "fcom{s|}",
13396   "fcomp{s|}",
13397   "fsub{s|}",
13398   "fsubr{s|}",
13399   "fdiv{s|}",
13400   "fdivr{s|}",
13401   /* d9 */
13402   "fld{s|}",
13403   "(bad)",
13404   "fst{s|}",
13405   "fstp{s|}",
13406   "fldenvIC",
13407   "fldcw",
13408   "fNstenvIC",
13409   "fNstcw",
13410   /* da */
13411   "fiadd{l|}",
13412   "fimul{l|}",
13413   "ficom{l|}",
13414   "ficomp{l|}",
13415   "fisub{l|}",
13416   "fisubr{l|}",
13417   "fidiv{l|}",
13418   "fidivr{l|}",
13419   /* db */
13420   "fild{l|}",
13421   "fisttp{l|}",
13422   "fist{l|}",
13423   "fistp{l|}",
13424   "(bad)",
13425   "fld{t||t|}",
13426   "(bad)",
13427   "fstp{t||t|}",
13428   /* dc */
13429   "fadd{l|}",
13430   "fmul{l|}",
13431   "fcom{l|}",
13432   "fcomp{l|}",
13433   "fsub{l|}",
13434   "fsubr{l|}",
13435   "fdiv{l|}",
13436   "fdivr{l|}",
13437   /* dd */
13438   "fld{l|}",
13439   "fisttp{ll|}",
13440   "fst{l||}",
13441   "fstp{l|}",
13442   "frstorIC",
13443   "(bad)",
13444   "fNsaveIC",
13445   "fNstsw",
13446   /* de */
13447   "fiadd",
13448   "fimul",
13449   "ficom",
13450   "ficomp",
13451   "fisub",
13452   "fisubr",
13453   "fidiv",
13454   "fidivr",
13455   /* df */
13456   "fild",
13457   "fisttp",
13458   "fist",
13459   "fistp",
13460   "fbld",
13461   "fild{ll|}",
13462   "fbstp",
13463   "fistp{ll|}",
13464 };
13465
13466 static const unsigned char float_mem_mode[] = {
13467   /* d8 */
13468   d_mode,
13469   d_mode,
13470   d_mode,
13471   d_mode,
13472   d_mode,
13473   d_mode,
13474   d_mode,
13475   d_mode,
13476   /* d9 */
13477   d_mode,
13478   0,
13479   d_mode,
13480   d_mode,
13481   0,
13482   w_mode,
13483   0,
13484   w_mode,
13485   /* da */
13486   d_mode,
13487   d_mode,
13488   d_mode,
13489   d_mode,
13490   d_mode,
13491   d_mode,
13492   d_mode,
13493   d_mode,
13494   /* db */
13495   d_mode,
13496   d_mode,
13497   d_mode,
13498   d_mode,
13499   0,
13500   t_mode,
13501   0,
13502   t_mode,
13503   /* dc */
13504   q_mode,
13505   q_mode,
13506   q_mode,
13507   q_mode,
13508   q_mode,
13509   q_mode,
13510   q_mode,
13511   q_mode,
13512   /* dd */
13513   q_mode,
13514   q_mode,
13515   q_mode,
13516   q_mode,
13517   0,
13518   0,
13519   0,
13520   w_mode,
13521   /* de */
13522   w_mode,
13523   w_mode,
13524   w_mode,
13525   w_mode,
13526   w_mode,
13527   w_mode,
13528   w_mode,
13529   w_mode,
13530   /* df */
13531   w_mode,
13532   w_mode,
13533   w_mode,
13534   w_mode,
13535   t_mode,
13536   q_mode,
13537   t_mode,
13538   q_mode
13539 };
13540
13541 #define ST { OP_ST, 0 }
13542 #define STi { OP_STi, 0 }
13543
13544 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13545 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13546 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13547 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13548 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13549 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13550 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13551 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13552 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13553
13554 static const struct dis386 float_reg[][8] = {
13555   /* d8 */
13556   {
13557     { "fadd",   { ST, STi }, 0 },
13558     { "fmul",   { ST, STi }, 0 },
13559     { "fcom",   { STi }, 0 },
13560     { "fcomp",  { STi }, 0 },
13561     { "fsub",   { ST, STi }, 0 },
13562     { "fsubr",  { ST, STi }, 0 },
13563     { "fdiv",   { ST, STi }, 0 },
13564     { "fdivr",  { ST, STi }, 0 },
13565   },
13566   /* d9 */
13567   {
13568     { "fld",    { STi }, 0 },
13569     { "fxch",   { STi }, 0 },
13570     { FGRPd9_2 },
13571     { Bad_Opcode },
13572     { FGRPd9_4 },
13573     { FGRPd9_5 },
13574     { FGRPd9_6 },
13575     { FGRPd9_7 },
13576   },
13577   /* da */
13578   {
13579     { "fcmovb", { ST, STi }, 0 },
13580     { "fcmove", { ST, STi }, 0 },
13581     { "fcmovbe",{ ST, STi }, 0 },
13582     { "fcmovu", { ST, STi }, 0 },
13583     { Bad_Opcode },
13584     { FGRPda_5 },
13585     { Bad_Opcode },
13586     { Bad_Opcode },
13587   },
13588   /* db */
13589   {
13590     { "fcmovnb",{ ST, STi }, 0 },
13591     { "fcmovne",{ ST, STi }, 0 },
13592     { "fcmovnbe",{ ST, STi }, 0 },
13593     { "fcmovnu",{ ST, STi }, 0 },
13594     { FGRPdb_4 },
13595     { "fucomi", { ST, STi }, 0 },
13596     { "fcomi",  { ST, STi }, 0 },
13597     { Bad_Opcode },
13598   },
13599   /* dc */
13600   {
13601     { "fadd",   { STi, ST }, 0 },
13602     { "fmul",   { STi, ST }, 0 },
13603     { Bad_Opcode },
13604     { Bad_Opcode },
13605     { "fsub!M", { STi, ST }, 0 },
13606     { "fsubM",  { STi, ST }, 0 },
13607     { "fdiv!M", { STi, ST }, 0 },
13608     { "fdivM",  { STi, ST }, 0 },
13609   },
13610   /* dd */
13611   {
13612     { "ffree",  { STi }, 0 },
13613     { Bad_Opcode },
13614     { "fst",    { STi }, 0 },
13615     { "fstp",   { STi }, 0 },
13616     { "fucom",  { STi }, 0 },
13617     { "fucomp", { STi }, 0 },
13618     { Bad_Opcode },
13619     { Bad_Opcode },
13620   },
13621   /* de */
13622   {
13623     { "faddp",  { STi, ST }, 0 },
13624     { "fmulp",  { STi, ST }, 0 },
13625     { Bad_Opcode },
13626     { FGRPde_3 },
13627     { "fsub!Mp", { STi, ST }, 0 },
13628     { "fsubMp", { STi, ST }, 0 },
13629     { "fdiv!Mp", { STi, ST }, 0 },
13630     { "fdivMp", { STi, ST }, 0 },
13631   },
13632   /* df */
13633   {
13634     { "ffreep", { STi }, 0 },
13635     { Bad_Opcode },
13636     { Bad_Opcode },
13637     { Bad_Opcode },
13638     { FGRPdf_4 },
13639     { "fucomip", { ST, STi }, 0 },
13640     { "fcomip", { ST, STi }, 0 },
13641     { Bad_Opcode },
13642   },
13643 };
13644
13645 static char *fgrps[][8] = {
13646   /* Bad opcode 0 */
13647   {
13648     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13649   },
13650
13651   /* d9_2  1 */
13652   {
13653     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13654   },
13655
13656   /* d9_4  2 */
13657   {
13658     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13659   },
13660
13661   /* d9_5  3 */
13662   {
13663     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13664   },
13665
13666   /* d9_6  4 */
13667   {
13668     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13669   },
13670
13671   /* d9_7  5 */
13672   {
13673     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13674   },
13675
13676   /* da_5  6 */
13677   {
13678     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13679   },
13680
13681   /* db_4  7 */
13682   {
13683     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13684     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13685   },
13686
13687   /* de_3  8 */
13688   {
13689     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13690   },
13691
13692   /* df_4  9 */
13693   {
13694     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13695   },
13696 };
13697
13698 static void
13699 swap_operand (void)
13700 {
13701   mnemonicendp[0] = '.';
13702   mnemonicendp[1] = 's';
13703   mnemonicendp += 2;
13704 }
13705
13706 static void
13707 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13708                int sizeflag ATTRIBUTE_UNUSED)
13709 {
13710   /* Skip mod/rm byte.  */
13711   MODRM_CHECK;
13712   codep++;
13713 }
13714
13715 static void
13716 dofloat (int sizeflag)
13717 {
13718   const struct dis386 *dp;
13719   unsigned char floatop;
13720
13721   floatop = codep[-1];
13722
13723   if (modrm.mod != 3)
13724     {
13725       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13726
13727       putop (float_mem[fp_indx], sizeflag);
13728       obufp = op_out[0];
13729       op_ad = 2;
13730       OP_E (float_mem_mode[fp_indx], sizeflag);
13731       return;
13732     }
13733   /* Skip mod/rm byte.  */
13734   MODRM_CHECK;
13735   codep++;
13736
13737   dp = &float_reg[floatop - 0xd8][modrm.reg];
13738   if (dp->name == NULL)
13739     {
13740       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13741
13742       /* Instruction fnstsw is only one with strange arg.  */
13743       if (floatop == 0xdf && codep[-1] == 0xe0)
13744         strcpy (op_out[0], names16[0]);
13745     }
13746   else
13747     {
13748       putop (dp->name, sizeflag);
13749
13750       obufp = op_out[0];
13751       op_ad = 2;
13752       if (dp->op[0].rtn)
13753         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13754
13755       obufp = op_out[1];
13756       op_ad = 1;
13757       if (dp->op[1].rtn)
13758         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13759     }
13760 }
13761
13762 /* Like oappend (below), but S is a string starting with '%'.
13763    In Intel syntax, the '%' is elided.  */
13764 static void
13765 oappend_maybe_intel (const char *s)
13766 {
13767   oappend (s + intel_syntax);
13768 }
13769
13770 static void
13771 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13772 {
13773   oappend_maybe_intel ("%st");
13774 }
13775
13776 static void
13777 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13778 {
13779   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13780   oappend_maybe_intel (scratchbuf);
13781 }
13782
13783 /* Capital letters in template are macros.  */
13784 static int
13785 putop (const char *in_template, int sizeflag)
13786 {
13787   const char *p;
13788   int alt = 0;
13789   int cond = 1;
13790   unsigned int l = 0, len = 1;
13791   char last[4];
13792
13793 #define SAVE_LAST(c)                    \
13794   if (l < len && l < sizeof (last))     \
13795     last[l++] = c;                      \
13796   else                                  \
13797     abort ();
13798
13799   for (p = in_template; *p; p++)
13800     {
13801       switch (*p)
13802         {
13803         default:
13804           *obufp++ = *p;
13805           break;
13806         case '%':
13807           len++;
13808           break;
13809         case '!':
13810           cond = 0;
13811           break;
13812         case '{':
13813           if (intel_syntax)
13814             {
13815               while (*++p != '|')
13816                 if (*p == '}' || *p == '\0')
13817                   abort ();
13818             }
13819           /* Fall through.  */
13820         case 'I':
13821           alt = 1;
13822           continue;
13823         case '|':
13824           while (*++p != '}')
13825             {
13826               if (*p == '\0')
13827                 abort ();
13828             }
13829           break;
13830         case '}':
13831           break;
13832         case 'A':
13833           if (intel_syntax)
13834             break;
13835           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13836             *obufp++ = 'b';
13837           break;
13838         case 'B':
13839           if (l == 0 && len == 1)
13840             {
13841 case_B:
13842               if (intel_syntax)
13843                 break;
13844               if (sizeflag & SUFFIX_ALWAYS)
13845                 *obufp++ = 'b';
13846             }
13847           else
13848             {
13849               if (l != 1
13850                   || len != 2
13851                   || last[0] != 'L')
13852                 {
13853                   SAVE_LAST (*p);
13854                   break;
13855                 }
13856
13857               if (address_mode == mode_64bit
13858                   && !(prefixes & PREFIX_ADDR))
13859                 {
13860                   *obufp++ = 'a';
13861                   *obufp++ = 'b';
13862                   *obufp++ = 's';
13863                 }
13864
13865               goto case_B;
13866             }
13867           break;
13868         case 'C':
13869           if (intel_syntax && !alt)
13870             break;
13871           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13872             {
13873               if (sizeflag & DFLAG)
13874                 *obufp++ = intel_syntax ? 'd' : 'l';
13875               else
13876                 *obufp++ = intel_syntax ? 'w' : 's';
13877               used_prefixes |= (prefixes & PREFIX_DATA);
13878             }
13879           break;
13880         case 'D':
13881           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13882             break;
13883           USED_REX (REX_W);
13884           if (modrm.mod == 3)
13885             {
13886               if (rex & REX_W)
13887                 *obufp++ = 'q';
13888               else
13889                 {
13890                   if (sizeflag & DFLAG)
13891                     *obufp++ = intel_syntax ? 'd' : 'l';
13892                   else
13893                     *obufp++ = 'w';
13894                   used_prefixes |= (prefixes & PREFIX_DATA);
13895                 }
13896             }
13897           else
13898             *obufp++ = 'w';
13899           break;
13900         case 'E':               /* For jcxz/jecxz */
13901           if (address_mode == mode_64bit)
13902             {
13903               if (sizeflag & AFLAG)
13904                 *obufp++ = 'r';
13905               else
13906                 *obufp++ = 'e';
13907             }
13908           else
13909             if (sizeflag & AFLAG)
13910               *obufp++ = 'e';
13911           used_prefixes |= (prefixes & PREFIX_ADDR);
13912           break;
13913         case 'F':
13914           if (intel_syntax)
13915             break;
13916           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13917             {
13918               if (sizeflag & AFLAG)
13919                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13920               else
13921                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13922               used_prefixes |= (prefixes & PREFIX_ADDR);
13923             }
13924           break;
13925         case 'G':
13926           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13927             break;
13928           if ((rex & REX_W) || (sizeflag & DFLAG))
13929             *obufp++ = 'l';
13930           else
13931             *obufp++ = 'w';
13932           if (!(rex & REX_W))
13933             used_prefixes |= (prefixes & PREFIX_DATA);
13934           break;
13935         case 'H':
13936           if (intel_syntax)
13937             break;
13938           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13939               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13940             {
13941               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13942               *obufp++ = ',';
13943               *obufp++ = 'p';
13944               if (prefixes & PREFIX_DS)
13945                 *obufp++ = 't';
13946               else
13947                 *obufp++ = 'n';
13948             }
13949           break;
13950         case 'J':
13951           if (intel_syntax)
13952             break;
13953           *obufp++ = 'l';
13954           break;
13955         case 'K':
13956           USED_REX (REX_W);
13957           if (rex & REX_W)
13958             *obufp++ = 'q';
13959           else
13960             *obufp++ = 'd';
13961           break;
13962         case 'Z':
13963           if (l != 0 || len != 1)
13964             {
13965               if (l != 1 || len != 2 || last[0] != 'X')
13966                 {
13967                   SAVE_LAST (*p);
13968                   break;
13969                 }
13970               if (!need_vex || !vex.evex)
13971                 abort ();
13972               if (intel_syntax
13973                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13974                 break;
13975               switch (vex.length)
13976                 {
13977                 case 128:
13978                   *obufp++ = 'x';
13979                   break;
13980                 case 256:
13981                   *obufp++ = 'y';
13982                   break;
13983                 case 512:
13984                   *obufp++ = 'z';
13985                   break;
13986                 default:
13987                   abort ();
13988                 }
13989               break;
13990             }
13991           if (intel_syntax)
13992             break;
13993           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13994             {
13995               *obufp++ = 'q';
13996               break;
13997             }
13998           /* Fall through.  */
13999           goto case_L;
14000         case 'L':
14001           if (l != 0 || len != 1)
14002             {
14003               SAVE_LAST (*p);
14004               break;
14005             }
14006 case_L:
14007           if (intel_syntax)
14008             break;
14009           if (sizeflag & SUFFIX_ALWAYS)
14010             *obufp++ = 'l';
14011           break;
14012         case 'M':
14013           if (intel_mnemonic != cond)
14014             *obufp++ = 'r';
14015           break;
14016         case 'N':
14017           if ((prefixes & PREFIX_FWAIT) == 0)
14018             *obufp++ = 'n';
14019           else
14020             used_prefixes |= PREFIX_FWAIT;
14021           break;
14022         case 'O':
14023           USED_REX (REX_W);
14024           if (rex & REX_W)
14025             *obufp++ = 'o';
14026           else if (intel_syntax && (sizeflag & DFLAG))
14027             *obufp++ = 'q';
14028           else
14029             *obufp++ = 'd';
14030           if (!(rex & REX_W))
14031             used_prefixes |= (prefixes & PREFIX_DATA);
14032           break;
14033         case '&':
14034           if (!intel_syntax
14035               && address_mode == mode_64bit
14036               && isa64 == intel64)
14037             {
14038               *obufp++ = 'q';
14039               break;
14040             }
14041           /* Fall through.  */
14042         case 'T':
14043           if (!intel_syntax
14044               && address_mode == mode_64bit
14045               && ((sizeflag & DFLAG) || (rex & REX_W)))
14046             {
14047               *obufp++ = 'q';
14048               break;
14049             }
14050           /* Fall through.  */
14051           goto case_P;
14052         case 'P':
14053           if (l == 0 && len == 1)
14054             {
14055 case_P:
14056               if (intel_syntax)
14057                 {
14058                   if ((rex & REX_W) == 0
14059                       && (prefixes & PREFIX_DATA))
14060                     {
14061                       if ((sizeflag & DFLAG) == 0)
14062                         *obufp++ = 'w';
14063                       used_prefixes |= (prefixes & PREFIX_DATA);
14064                     }
14065                   break;
14066                 }
14067               if ((prefixes & PREFIX_DATA)
14068                   || (rex & REX_W)
14069                   || (sizeflag & SUFFIX_ALWAYS))
14070                 {
14071                   USED_REX (REX_W);
14072                   if (rex & REX_W)
14073                     *obufp++ = 'q';
14074                   else
14075                     {
14076                       if (sizeflag & DFLAG)
14077                         *obufp++ = 'l';
14078                       else
14079                         *obufp++ = 'w';
14080                       used_prefixes |= (prefixes & PREFIX_DATA);
14081                     }
14082                 }
14083             }
14084           else
14085             {
14086               if (l != 1 || len != 2 || last[0] != 'L')
14087                 {
14088                   SAVE_LAST (*p);
14089                   break;
14090                 }
14091
14092               if ((prefixes & PREFIX_DATA)
14093                   || (rex & REX_W)
14094                   || (sizeflag & SUFFIX_ALWAYS))
14095                 {
14096                   USED_REX (REX_W);
14097                   if (rex & REX_W)
14098                     *obufp++ = 'q';
14099                   else
14100                     {
14101                       if (sizeflag & DFLAG)
14102                         *obufp++ = intel_syntax ? 'd' : 'l';
14103                       else
14104                         *obufp++ = 'w';
14105                       used_prefixes |= (prefixes & PREFIX_DATA);
14106                     }
14107                 }
14108             }
14109           break;
14110         case 'U':
14111           if (intel_syntax)
14112             break;
14113           if (address_mode == mode_64bit
14114               && ((sizeflag & DFLAG) || (rex & REX_W)))
14115             {
14116               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14117                 *obufp++ = 'q';
14118               break;
14119             }
14120           /* Fall through.  */
14121           goto case_Q;
14122         case 'Q':
14123           if (l == 0 && len == 1)
14124             {
14125 case_Q:
14126               if (intel_syntax && !alt)
14127                 break;
14128               USED_REX (REX_W);
14129               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14130                 {
14131                   if (rex & REX_W)
14132                     *obufp++ = 'q';
14133                   else
14134                     {
14135                       if (sizeflag & DFLAG)
14136                         *obufp++ = intel_syntax ? 'd' : 'l';
14137                       else
14138                         *obufp++ = 'w';
14139                       used_prefixes |= (prefixes & PREFIX_DATA);
14140                     }
14141                 }
14142             }
14143           else
14144             {
14145               if (l != 1 || len != 2 || last[0] != 'L')
14146                 {
14147                   SAVE_LAST (*p);
14148                   break;
14149                 }
14150               if (intel_syntax
14151                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14152                 break;
14153               if ((rex & REX_W))
14154                 {
14155                   USED_REX (REX_W);
14156                   *obufp++ = 'q';
14157                 }
14158               else
14159                 *obufp++ = 'l';
14160             }
14161           break;
14162         case 'R':
14163           USED_REX (REX_W);
14164           if (rex & REX_W)
14165             *obufp++ = 'q';
14166           else if (sizeflag & DFLAG)
14167             {
14168               if (intel_syntax)
14169                   *obufp++ = 'd';
14170               else
14171                   *obufp++ = 'l';
14172             }
14173           else
14174             *obufp++ = 'w';
14175           if (intel_syntax && !p[1]
14176               && ((rex & REX_W) || (sizeflag & DFLAG)))
14177             *obufp++ = 'e';
14178           if (!(rex & REX_W))
14179             used_prefixes |= (prefixes & PREFIX_DATA);
14180           break;
14181         case 'V':
14182           if (l == 0 && len == 1)
14183             {
14184               if (intel_syntax)
14185                 break;
14186               if (address_mode == mode_64bit
14187                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14188                 {
14189                   if (sizeflag & SUFFIX_ALWAYS)
14190                     *obufp++ = 'q';
14191                   break;
14192                 }
14193             }
14194           else
14195             {
14196               if (l != 1
14197                   || len != 2
14198                   || last[0] != 'L')
14199                 {
14200                   SAVE_LAST (*p);
14201                   break;
14202                 }
14203
14204               if (rex & REX_W)
14205                 {
14206                   *obufp++ = 'a';
14207                   *obufp++ = 'b';
14208                   *obufp++ = 's';
14209                 }
14210             }
14211           /* Fall through.  */
14212           goto case_S;
14213         case 'S':
14214           if (l == 0 && len == 1)
14215             {
14216 case_S:
14217               if (intel_syntax)
14218                 break;
14219               if (sizeflag & SUFFIX_ALWAYS)
14220                 {
14221                   if (rex & REX_W)
14222                     *obufp++ = 'q';
14223                   else
14224                     {
14225                       if (sizeflag & DFLAG)
14226                         *obufp++ = 'l';
14227                       else
14228                         *obufp++ = 'w';
14229                       used_prefixes |= (prefixes & PREFIX_DATA);
14230                     }
14231                 }
14232             }
14233           else
14234             {
14235               if (l != 1
14236                   || len != 2
14237                   || last[0] != 'L')
14238                 {
14239                   SAVE_LAST (*p);
14240                   break;
14241                 }
14242
14243               if (address_mode == mode_64bit
14244                   && !(prefixes & PREFIX_ADDR))
14245                 {
14246                   *obufp++ = 'a';
14247                   *obufp++ = 'b';
14248                   *obufp++ = 's';
14249                 }
14250
14251               goto case_S;
14252             }
14253           break;
14254         case 'X':
14255           if (l != 0 || len != 1)
14256             {
14257               SAVE_LAST (*p);
14258               break;
14259             }
14260           if (need_vex && vex.prefix)
14261             {
14262               if (vex.prefix == DATA_PREFIX_OPCODE)
14263                 *obufp++ = 'd';
14264               else
14265                 *obufp++ = 's';
14266             }
14267           else
14268             {
14269               if (prefixes & PREFIX_DATA)
14270                 *obufp++ = 'd';
14271               else
14272                 *obufp++ = 's';
14273               used_prefixes |= (prefixes & PREFIX_DATA);
14274             }
14275           break;
14276         case 'Y':
14277           if (l == 0 && len == 1)
14278             {
14279               if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14280                 break;
14281               if (rex & REX_W)
14282                 {
14283                   USED_REX (REX_W);
14284                   *obufp++ = 'q';
14285                 }
14286               break;
14287             }
14288           else
14289             {
14290               if (l != 1 || len != 2 || last[0] != 'X')
14291                 {
14292                   SAVE_LAST (*p);
14293                   break;
14294                 }
14295               if (!need_vex)
14296                 abort ();
14297               if (intel_syntax
14298                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14299                 break;
14300               switch (vex.length)
14301                 {
14302                 case 128:
14303                   *obufp++ = 'x';
14304                   break;
14305                 case 256:
14306                   *obufp++ = 'y';
14307                   break;
14308                 case 512:
14309                   if (!vex.evex)
14310                 default:
14311                     abort ();
14312                 }
14313             }
14314           break;
14315         case 'W':
14316           if (l == 0 && len == 1)
14317             {
14318               /* operand size flag for cwtl, cbtw */
14319               USED_REX (REX_W);
14320               if (rex & REX_W)
14321                 {
14322                   if (intel_syntax)
14323                     *obufp++ = 'd';
14324                   else
14325                     *obufp++ = 'l';
14326                 }
14327               else if (sizeflag & DFLAG)
14328                 *obufp++ = 'w';
14329               else
14330                 *obufp++ = 'b';
14331               if (!(rex & REX_W))
14332                 used_prefixes |= (prefixes & PREFIX_DATA);
14333             }
14334           else
14335             {
14336               if (l != 1
14337                   || len != 2
14338                   || (last[0] != 'X'
14339                       && last[0] != 'L'))
14340                 {
14341                   SAVE_LAST (*p);
14342                   break;
14343                 }
14344               if (!need_vex)
14345                 abort ();
14346               if (last[0] == 'X')
14347                 *obufp++ = vex.w ? 'd': 's';
14348               else
14349                 *obufp++ = vex.w ? 'q': 'd';
14350             }
14351           break;
14352         case '^':
14353           if (intel_syntax)
14354             break;
14355           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14356             {
14357               if (sizeflag & DFLAG)
14358                 *obufp++ = 'l';
14359               else
14360                 *obufp++ = 'w';
14361               used_prefixes |= (prefixes & PREFIX_DATA);
14362             }
14363           break;
14364         case '@':
14365           if (intel_syntax)
14366             break;
14367           if (address_mode == mode_64bit
14368               && (isa64 == intel64
14369                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14370               *obufp++ = 'q';
14371           else if ((prefixes & PREFIX_DATA))
14372             {
14373               if (!(sizeflag & DFLAG))
14374                 *obufp++ = 'w';
14375               used_prefixes |= (prefixes & PREFIX_DATA);
14376             }
14377           break;
14378         }
14379       alt = 0;
14380     }
14381   *obufp = 0;
14382   mnemonicendp = obufp;
14383   return 0;
14384 }
14385
14386 static void
14387 oappend (const char *s)
14388 {
14389   obufp = stpcpy (obufp, s);
14390 }
14391
14392 static void
14393 append_seg (void)
14394 {
14395   /* Only print the active segment register.  */
14396   if (!active_seg_prefix)
14397     return;
14398
14399   used_prefixes |= active_seg_prefix;
14400   switch (active_seg_prefix)
14401     {
14402     case PREFIX_CS:
14403       oappend_maybe_intel ("%cs:");
14404       break;
14405     case PREFIX_DS:
14406       oappend_maybe_intel ("%ds:");
14407       break;
14408     case PREFIX_SS:
14409       oappend_maybe_intel ("%ss:");
14410       break;
14411     case PREFIX_ES:
14412       oappend_maybe_intel ("%es:");
14413       break;
14414     case PREFIX_FS:
14415       oappend_maybe_intel ("%fs:");
14416       break;
14417     case PREFIX_GS:
14418       oappend_maybe_intel ("%gs:");
14419       break;
14420     default:
14421       break;
14422     }
14423 }
14424
14425 static void
14426 OP_indirE (int bytemode, int sizeflag)
14427 {
14428   if (!intel_syntax)
14429     oappend ("*");
14430   OP_E (bytemode, sizeflag);
14431 }
14432
14433 static void
14434 print_operand_value (char *buf, int hex, bfd_vma disp)
14435 {
14436   if (address_mode == mode_64bit)
14437     {
14438       if (hex)
14439         {
14440           char tmp[30];
14441           int i;
14442           buf[0] = '0';
14443           buf[1] = 'x';
14444           sprintf_vma (tmp, disp);
14445           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14446           strcpy (buf + 2, tmp + i);
14447         }
14448       else
14449         {
14450           bfd_signed_vma v = disp;
14451           char tmp[30];
14452           int i;
14453           if (v < 0)
14454             {
14455               *(buf++) = '-';
14456               v = -disp;
14457               /* Check for possible overflow on 0x8000000000000000.  */
14458               if (v < 0)
14459                 {
14460                   strcpy (buf, "9223372036854775808");
14461                   return;
14462                 }
14463             }
14464           if (!v)
14465             {
14466               strcpy (buf, "0");
14467               return;
14468             }
14469
14470           i = 0;
14471           tmp[29] = 0;
14472           while (v)
14473             {
14474               tmp[28 - i] = (v % 10) + '0';
14475               v /= 10;
14476               i++;
14477             }
14478           strcpy (buf, tmp + 29 - i);
14479         }
14480     }
14481   else
14482     {
14483       if (hex)
14484         sprintf (buf, "0x%x", (unsigned int) disp);
14485       else
14486         sprintf (buf, "%d", (int) disp);
14487     }
14488 }
14489
14490 /* Put DISP in BUF as signed hex number.  */
14491
14492 static void
14493 print_displacement (char *buf, bfd_vma disp)
14494 {
14495   bfd_signed_vma val = disp;
14496   char tmp[30];
14497   int i, j = 0;
14498
14499   if (val < 0)
14500     {
14501       buf[j++] = '-';
14502       val = -disp;
14503
14504       /* Check for possible overflow.  */
14505       if (val < 0)
14506         {
14507           switch (address_mode)
14508             {
14509             case mode_64bit:
14510               strcpy (buf + j, "0x8000000000000000");
14511               break;
14512             case mode_32bit:
14513               strcpy (buf + j, "0x80000000");
14514               break;
14515             case mode_16bit:
14516               strcpy (buf + j, "0x8000");
14517               break;
14518             }
14519           return;
14520         }
14521     }
14522
14523   buf[j++] = '0';
14524   buf[j++] = 'x';
14525
14526   sprintf_vma (tmp, (bfd_vma) val);
14527   for (i = 0; tmp[i] == '0'; i++)
14528     continue;
14529   if (tmp[i] == '\0')
14530     i--;
14531   strcpy (buf + j, tmp + i);
14532 }
14533
14534 static void
14535 intel_operand_size (int bytemode, int sizeflag)
14536 {
14537   if (vex.evex
14538       && vex.b
14539       && (bytemode == x_mode
14540           || bytemode == evex_half_bcst_xmmq_mode))
14541     {
14542       if (vex.w)
14543         oappend ("QWORD PTR ");
14544       else
14545         oappend ("DWORD PTR ");
14546       return;
14547     }
14548   switch (bytemode)
14549     {
14550     case b_mode:
14551     case b_swap_mode:
14552     case dqb_mode:
14553     case db_mode:
14554       oappend ("BYTE PTR ");
14555       break;
14556     case w_mode:
14557     case dw_mode:
14558     case dqw_mode:
14559       oappend ("WORD PTR ");
14560       break;
14561     case indir_v_mode:
14562       if (address_mode == mode_64bit && isa64 == intel64)
14563         {
14564           oappend ("QWORD PTR ");
14565           break;
14566         }
14567       /* Fall through.  */
14568     case stack_v_mode:
14569       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14570         {
14571           oappend ("QWORD PTR ");
14572           break;
14573         }
14574       /* Fall through.  */
14575     case v_mode:
14576     case v_swap_mode:
14577     case dq_mode:
14578       USED_REX (REX_W);
14579       if (rex & REX_W)
14580         oappend ("QWORD PTR ");
14581       else
14582         {
14583           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14584             oappend ("DWORD PTR ");
14585           else
14586             oappend ("WORD PTR ");
14587           used_prefixes |= (prefixes & PREFIX_DATA);
14588         }
14589       break;
14590     case z_mode:
14591       if ((rex & REX_W) || (sizeflag & DFLAG))
14592         *obufp++ = 'D';
14593       oappend ("WORD PTR ");
14594       if (!(rex & REX_W))
14595         used_prefixes |= (prefixes & PREFIX_DATA);
14596       break;
14597     case a_mode:
14598       if (sizeflag & DFLAG)
14599         oappend ("QWORD PTR ");
14600       else
14601         oappend ("DWORD PTR ");
14602       used_prefixes |= (prefixes & PREFIX_DATA);
14603       break;
14604     case d_mode:
14605     case d_scalar_mode:
14606     case d_scalar_swap_mode:
14607     case d_swap_mode:
14608     case dqd_mode:
14609       oappend ("DWORD PTR ");
14610       break;
14611     case q_mode:
14612     case q_scalar_mode:
14613     case q_scalar_swap_mode:
14614     case q_swap_mode:
14615       oappend ("QWORD PTR ");
14616       break;
14617     case m_mode:
14618       if (address_mode == mode_64bit)
14619         oappend ("QWORD PTR ");
14620       else
14621         oappend ("DWORD PTR ");
14622       break;
14623     case f_mode:
14624       if (sizeflag & DFLAG)
14625         oappend ("FWORD PTR ");
14626       else
14627         oappend ("DWORD PTR ");
14628       used_prefixes |= (prefixes & PREFIX_DATA);
14629       break;
14630     case t_mode:
14631       oappend ("TBYTE PTR ");
14632       break;
14633     case x_mode:
14634     case x_swap_mode:
14635     case evex_x_gscat_mode:
14636     case evex_x_nobcst_mode:
14637       if (need_vex)
14638         {
14639           switch (vex.length)
14640             {
14641             case 128:
14642               oappend ("XMMWORD PTR ");
14643               break;
14644             case 256:
14645               oappend ("YMMWORD PTR ");
14646               break;
14647             case 512:
14648               oappend ("ZMMWORD PTR ");
14649               break;
14650             default:
14651               abort ();
14652             }
14653         }
14654       else
14655         oappend ("XMMWORD PTR ");
14656       break;
14657     case xmm_mode:
14658       oappend ("XMMWORD PTR ");
14659       break;
14660     case ymm_mode:
14661       oappend ("YMMWORD PTR ");
14662       break;
14663     case xmmq_mode:
14664     case evex_half_bcst_xmmq_mode:
14665       if (!need_vex)
14666         abort ();
14667
14668       switch (vex.length)
14669         {
14670         case 128:
14671           oappend ("QWORD PTR ");
14672           break;
14673         case 256:
14674           oappend ("XMMWORD PTR ");
14675           break;
14676         case 512:
14677           oappend ("YMMWORD PTR ");
14678           break;
14679         default:
14680           abort ();
14681         }
14682       break;
14683     case xmm_mb_mode:
14684       if (!need_vex)
14685         abort ();
14686
14687       switch (vex.length)
14688         {
14689         case 128:
14690         case 256:
14691         case 512:
14692           oappend ("BYTE PTR ");
14693           break;
14694         default:
14695           abort ();
14696         }
14697       break;
14698     case xmm_mw_mode:
14699       if (!need_vex)
14700         abort ();
14701
14702       switch (vex.length)
14703         {
14704         case 128:
14705         case 256:
14706         case 512:
14707           oappend ("WORD PTR ");
14708           break;
14709         default:
14710           abort ();
14711         }
14712       break;
14713     case xmm_md_mode:
14714       if (!need_vex)
14715         abort ();
14716
14717       switch (vex.length)
14718         {
14719         case 128:
14720         case 256:
14721         case 512:
14722           oappend ("DWORD PTR ");
14723           break;
14724         default:
14725           abort ();
14726         }
14727       break;
14728     case xmm_mq_mode:
14729       if (!need_vex)
14730         abort ();
14731
14732       switch (vex.length)
14733         {
14734         case 128:
14735         case 256:
14736         case 512:
14737           oappend ("QWORD PTR ");
14738           break;
14739         default:
14740           abort ();
14741         }
14742       break;
14743     case xmmdw_mode:
14744       if (!need_vex)
14745         abort ();
14746
14747       switch (vex.length)
14748         {
14749         case 128:
14750           oappend ("WORD PTR ");
14751           break;
14752         case 256:
14753           oappend ("DWORD PTR ");
14754           break;
14755         case 512:
14756           oappend ("QWORD PTR ");
14757           break;
14758         default:
14759           abort ();
14760         }
14761       break;
14762     case xmmqd_mode:
14763       if (!need_vex)
14764         abort ();
14765
14766       switch (vex.length)
14767         {
14768         case 128:
14769           oappend ("DWORD PTR ");
14770           break;
14771         case 256:
14772           oappend ("QWORD PTR ");
14773           break;
14774         case 512:
14775           oappend ("XMMWORD PTR ");
14776           break;
14777         default:
14778           abort ();
14779         }
14780       break;
14781     case ymmq_mode:
14782       if (!need_vex)
14783         abort ();
14784
14785       switch (vex.length)
14786         {
14787         case 128:
14788           oappend ("QWORD PTR ");
14789           break;
14790         case 256:
14791           oappend ("YMMWORD PTR ");
14792           break;
14793         case 512:
14794           oappend ("ZMMWORD PTR ");
14795           break;
14796         default:
14797           abort ();
14798         }
14799       break;
14800     case ymmxmm_mode:
14801       if (!need_vex)
14802         abort ();
14803
14804       switch (vex.length)
14805         {
14806         case 128:
14807         case 256:
14808           oappend ("XMMWORD PTR ");
14809           break;
14810         default:
14811           abort ();
14812         }
14813       break;
14814     case o_mode:
14815       oappend ("OWORD PTR ");
14816       break;
14817     case xmm_mdq_mode:
14818     case vex_w_dq_mode:
14819     case vex_scalar_w_dq_mode:
14820       if (!need_vex)
14821         abort ();
14822
14823       if (vex.w)
14824         oappend ("QWORD PTR ");
14825       else
14826         oappend ("DWORD PTR ");
14827       break;
14828     case vex_vsib_d_w_dq_mode:
14829     case vex_vsib_q_w_dq_mode:
14830       if (!need_vex)
14831         abort ();
14832
14833       if (!vex.evex)
14834         {
14835           if (vex.w)
14836             oappend ("QWORD PTR ");
14837           else
14838             oappend ("DWORD PTR ");
14839         }
14840       else
14841         {
14842           switch (vex.length)
14843             {
14844             case 128:
14845               oappend ("XMMWORD PTR ");
14846               break;
14847             case 256:
14848               oappend ("YMMWORD PTR ");
14849               break;
14850             case 512:
14851               oappend ("ZMMWORD PTR ");
14852               break;
14853             default:
14854               abort ();
14855             }
14856         }
14857       break;
14858     case vex_vsib_q_w_d_mode:
14859     case vex_vsib_d_w_d_mode:
14860       if (!need_vex || !vex.evex)
14861         abort ();
14862
14863       switch (vex.length)
14864         {
14865         case 128:
14866           oappend ("QWORD PTR ");
14867           break;
14868         case 256:
14869           oappend ("XMMWORD PTR ");
14870           break;
14871         case 512:
14872           oappend ("YMMWORD PTR ");
14873           break;
14874         default:
14875           abort ();
14876         }
14877
14878       break;
14879     case mask_bd_mode:
14880       if (!need_vex || vex.length != 128)
14881         abort ();
14882       if (vex.w)
14883         oappend ("DWORD PTR ");
14884       else
14885         oappend ("BYTE PTR ");
14886       break;
14887     case mask_mode:
14888       if (!need_vex)
14889         abort ();
14890       if (vex.w)
14891         oappend ("QWORD PTR ");
14892       else
14893         oappend ("WORD PTR ");
14894       break;
14895     case v_bnd_mode:
14896     default:
14897       break;
14898     }
14899 }
14900
14901 static void
14902 OP_E_register (int bytemode, int sizeflag)
14903 {
14904   int reg = modrm.rm;
14905   const char **names;
14906
14907   USED_REX (REX_B);
14908   if ((rex & REX_B))
14909     reg += 8;
14910
14911   if ((sizeflag & SUFFIX_ALWAYS)
14912       && (bytemode == b_swap_mode
14913           || bytemode == v_swap_mode))
14914     swap_operand ();
14915
14916   switch (bytemode)
14917     {
14918     case b_mode:
14919     case b_swap_mode:
14920       USED_REX (0);
14921       if (rex)
14922         names = names8rex;
14923       else
14924         names = names8;
14925       break;
14926     case w_mode:
14927       names = names16;
14928       break;
14929     case d_mode:
14930     case dw_mode:
14931     case db_mode:
14932       names = names32;
14933       break;
14934     case q_mode:
14935       names = names64;
14936       break;
14937     case m_mode:
14938     case v_bnd_mode:
14939       names = address_mode == mode_64bit ? names64 : names32;
14940       break;
14941     case bnd_mode:
14942       names = names_bnd;
14943       break;
14944     case indir_v_mode:
14945       if (address_mode == mode_64bit && isa64 == intel64)
14946         {
14947           names = names64;
14948           break;
14949         }
14950       /* Fall through.  */
14951     case stack_v_mode:
14952       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14953         {
14954           names = names64;
14955           break;
14956         }
14957       bytemode = v_mode;
14958       /* Fall through.  */
14959     case v_mode:
14960     case v_swap_mode:
14961     case dq_mode:
14962     case dqb_mode:
14963     case dqd_mode:
14964     case dqw_mode:
14965       USED_REX (REX_W);
14966       if (rex & REX_W)
14967         names = names64;
14968       else
14969         {
14970           if ((sizeflag & DFLAG)
14971               || (bytemode != v_mode
14972                   && bytemode != v_swap_mode))
14973             names = names32;
14974           else
14975             names = names16;
14976           used_prefixes |= (prefixes & PREFIX_DATA);
14977         }
14978       break;
14979     case mask_bd_mode:
14980     case mask_mode:
14981       if (reg > 0x7)
14982         {
14983           oappend ("(bad)");
14984           return;
14985         }
14986       names = names_mask;
14987       break;
14988     case 0:
14989       return;
14990     default:
14991       oappend (INTERNAL_DISASSEMBLER_ERROR);
14992       return;
14993     }
14994   oappend (names[reg]);
14995 }
14996
14997 static void
14998 OP_E_memory (int bytemode, int sizeflag)
14999 {
15000   bfd_vma disp = 0;
15001   int add = (rex & REX_B) ? 8 : 0;
15002   int riprel = 0;
15003   int shift;
15004
15005   if (vex.evex)
15006     {
15007       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15008       if (vex.b
15009           && bytemode != x_mode
15010           && bytemode != xmmq_mode
15011           && bytemode != evex_half_bcst_xmmq_mode)
15012         {
15013           BadOp ();
15014           return;
15015         }
15016       switch (bytemode)
15017         {
15018         case dqw_mode:
15019         case dw_mode:
15020           shift = 1;
15021           break;
15022         case dqb_mode:
15023         case db_mode:
15024           shift = 0;
15025           break;
15026         case vex_vsib_d_w_dq_mode:
15027         case vex_vsib_d_w_d_mode:
15028         case vex_vsib_q_w_dq_mode:
15029         case vex_vsib_q_w_d_mode:
15030         case evex_x_gscat_mode:
15031         case xmm_mdq_mode:
15032           shift = vex.w ? 3 : 2;
15033           break;
15034         case x_mode:
15035         case evex_half_bcst_xmmq_mode:
15036         case xmmq_mode:
15037           if (vex.b)
15038             {
15039               shift = vex.w ? 3 : 2;
15040               break;
15041             }
15042           /* Fall through.  */
15043         case xmmqd_mode:
15044         case xmmdw_mode:
15045         case ymmq_mode:
15046         case evex_x_nobcst_mode:
15047         case x_swap_mode:
15048           switch (vex.length)
15049             {
15050             case 128:
15051               shift = 4;
15052               break;
15053             case 256:
15054               shift = 5;
15055               break;
15056             case 512:
15057               shift = 6;
15058               break;
15059             default:
15060               abort ();
15061             }
15062           break;
15063         case ymm_mode:
15064           shift = 5;
15065           break;
15066         case xmm_mode:
15067           shift = 4;
15068           break;
15069         case xmm_mq_mode:
15070         case q_mode:
15071         case q_scalar_mode:
15072         case q_swap_mode:
15073         case q_scalar_swap_mode:
15074           shift = 3;
15075           break;
15076         case dqd_mode:
15077         case xmm_md_mode:
15078         case d_mode:
15079         case d_scalar_mode:
15080         case d_swap_mode:
15081         case d_scalar_swap_mode:
15082           shift = 2;
15083           break;
15084         case xmm_mw_mode:
15085           shift = 1;
15086           break;
15087         case xmm_mb_mode:
15088           shift = 0;
15089           break;
15090         default:
15091           abort ();
15092         }
15093       /* Make necessary corrections to shift for modes that need it.
15094          For these modes we currently have shift 4, 5 or 6 depending on
15095          vex.length (it corresponds to xmmword, ymmword or zmmword
15096          operand).  We might want to make it 3, 4 or 5 (e.g. for
15097          xmmq_mode).  In case of broadcast enabled the corrections
15098          aren't needed, as element size is always 32 or 64 bits.  */
15099       if (!vex.b
15100           && (bytemode == xmmq_mode
15101               || bytemode == evex_half_bcst_xmmq_mode))
15102         shift -= 1;
15103       else if (bytemode == xmmqd_mode)
15104         shift -= 2;
15105       else if (bytemode == xmmdw_mode)
15106         shift -= 3;
15107       else if (bytemode == ymmq_mode && vex.length == 128)
15108         shift -= 1;
15109     }
15110   else
15111     shift = 0;
15112
15113   USED_REX (REX_B);
15114   if (intel_syntax)
15115     intel_operand_size (bytemode, sizeflag);
15116   append_seg ();
15117
15118   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15119     {
15120       /* 32/64 bit address mode */
15121       int havedisp;
15122       int havesib;
15123       int havebase;
15124       int haveindex;
15125       int needindex;
15126       int base, rbase;
15127       int vindex = 0;
15128       int scale = 0;
15129       int addr32flag = !((sizeflag & AFLAG)
15130                          || bytemode == v_bnd_mode
15131                          || bytemode == bnd_mode);
15132       const char **indexes64 = names64;
15133       const char **indexes32 = names32;
15134
15135       havesib = 0;
15136       havebase = 1;
15137       haveindex = 0;
15138       base = modrm.rm;
15139
15140       if (base == 4)
15141         {
15142           havesib = 1;
15143           vindex = sib.index;
15144           USED_REX (REX_X);
15145           if (rex & REX_X)
15146             vindex += 8;
15147           switch (bytemode)
15148             {
15149             case vex_vsib_d_w_dq_mode:
15150             case vex_vsib_d_w_d_mode:
15151             case vex_vsib_q_w_dq_mode:
15152             case vex_vsib_q_w_d_mode:
15153               if (!need_vex)
15154                 abort ();
15155               if (vex.evex)
15156                 {
15157                   if (!vex.v)
15158                     vindex += 16;
15159                 }
15160
15161               haveindex = 1;
15162               switch (vex.length)
15163                 {
15164                 case 128:
15165                   indexes64 = indexes32 = names_xmm;
15166                   break;
15167                 case 256:
15168                   if (!vex.w
15169                       || bytemode == vex_vsib_q_w_dq_mode
15170                       || bytemode == vex_vsib_q_w_d_mode)
15171                     indexes64 = indexes32 = names_ymm;
15172                   else
15173                     indexes64 = indexes32 = names_xmm;
15174                   break;
15175                 case 512:
15176                   if (!vex.w
15177                       || bytemode == vex_vsib_q_w_dq_mode
15178                       || bytemode == vex_vsib_q_w_d_mode)
15179                     indexes64 = indexes32 = names_zmm;
15180                   else
15181                     indexes64 = indexes32 = names_ymm;
15182                   break;
15183                 default:
15184                   abort ();
15185                 }
15186               break;
15187             default:
15188               haveindex = vindex != 4;
15189               break;
15190             }
15191           scale = sib.scale;
15192           base = sib.base;
15193           codep++;
15194         }
15195       rbase = base + add;
15196
15197       switch (modrm.mod)
15198         {
15199         case 0:
15200           if (base == 5)
15201             {
15202               havebase = 0;
15203               if (address_mode == mode_64bit && !havesib)
15204                 riprel = 1;
15205               disp = get32s ();
15206             }
15207           break;
15208         case 1:
15209           FETCH_DATA (the_info, codep + 1);
15210           disp = *codep++;
15211           if ((disp & 0x80) != 0)
15212             disp -= 0x100;
15213           if (vex.evex && shift > 0)
15214             disp <<= shift;
15215           break;
15216         case 2:
15217           disp = get32s ();
15218           break;
15219         }
15220
15221       /* In 32bit mode, we need index register to tell [offset] from
15222          [eiz*1 + offset].  */
15223       needindex = (havesib
15224                    && !havebase
15225                    && !haveindex
15226                    && address_mode == mode_32bit);
15227       havedisp = (havebase
15228                   || needindex
15229                   || (havesib && (haveindex || scale != 0)));
15230
15231       if (!intel_syntax)
15232         if (modrm.mod != 0 || base == 5)
15233           {
15234             if (havedisp || riprel)
15235               print_displacement (scratchbuf, disp);
15236             else
15237               print_operand_value (scratchbuf, 1, disp);
15238             oappend (scratchbuf);
15239             if (riprel)
15240               {
15241                 set_op (disp, 1);
15242                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15243               }
15244           }
15245
15246       if ((havebase || haveindex || riprel)
15247           && (bytemode != v_bnd_mode)
15248           && (bytemode != bnd_mode))
15249         used_prefixes |= PREFIX_ADDR;
15250
15251       if (havedisp || (intel_syntax && riprel))
15252         {
15253           *obufp++ = open_char;
15254           if (intel_syntax && riprel)
15255             {
15256               set_op (disp, 1);
15257               oappend (!addr32flag ? "rip" : "eip");
15258             }
15259           *obufp = '\0';
15260           if (havebase)
15261             oappend (address_mode == mode_64bit && !addr32flag
15262                      ? names64[rbase] : names32[rbase]);
15263           if (havesib)
15264             {
15265               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15266                  print index to tell base + index from base.  */
15267               if (scale != 0
15268                   || needindex
15269                   || haveindex
15270                   || (havebase && base != ESP_REG_NUM))
15271                 {
15272                   if (!intel_syntax || havebase)
15273                     {
15274                       *obufp++ = separator_char;
15275                       *obufp = '\0';
15276                     }
15277                   if (haveindex)
15278                     oappend (address_mode == mode_64bit && !addr32flag
15279                              ? indexes64[vindex] : indexes32[vindex]);
15280                   else
15281                     oappend (address_mode == mode_64bit && !addr32flag
15282                              ? index64 : index32);
15283
15284                   *obufp++ = scale_char;
15285                   *obufp = '\0';
15286                   sprintf (scratchbuf, "%d", 1 << scale);
15287                   oappend (scratchbuf);
15288                 }
15289             }
15290           if (intel_syntax
15291               && (disp || modrm.mod != 0 || base == 5))
15292             {
15293               if (!havedisp || (bfd_signed_vma) disp >= 0)
15294                 {
15295                   *obufp++ = '+';
15296                   *obufp = '\0';
15297                 }
15298               else if (modrm.mod != 1 && disp != -disp)
15299                 {
15300                   *obufp++ = '-';
15301                   *obufp = '\0';
15302                   disp = - (bfd_signed_vma) disp;
15303                 }
15304
15305               if (havedisp)
15306                 print_displacement (scratchbuf, disp);
15307               else
15308                 print_operand_value (scratchbuf, 1, disp);
15309               oappend (scratchbuf);
15310             }
15311
15312           *obufp++ = close_char;
15313           *obufp = '\0';
15314         }
15315       else if (intel_syntax)
15316         {
15317           if (modrm.mod != 0 || base == 5)
15318             {
15319               if (!active_seg_prefix)
15320                 {
15321                   oappend (names_seg[ds_reg - es_reg]);
15322                   oappend (":");
15323                 }
15324               print_operand_value (scratchbuf, 1, disp);
15325               oappend (scratchbuf);
15326             }
15327         }
15328     }
15329   else
15330     {
15331       /* 16 bit address mode */
15332       used_prefixes |= prefixes & PREFIX_ADDR;
15333       switch (modrm.mod)
15334         {
15335         case 0:
15336           if (modrm.rm == 6)
15337             {
15338               disp = get16 ();
15339               if ((disp & 0x8000) != 0)
15340                 disp -= 0x10000;
15341             }
15342           break;
15343         case 1:
15344           FETCH_DATA (the_info, codep + 1);
15345           disp = *codep++;
15346           if ((disp & 0x80) != 0)
15347             disp -= 0x100;
15348           break;
15349         case 2:
15350           disp = get16 ();
15351           if ((disp & 0x8000) != 0)
15352             disp -= 0x10000;
15353           break;
15354         }
15355
15356       if (!intel_syntax)
15357         if (modrm.mod != 0 || modrm.rm == 6)
15358           {
15359             print_displacement (scratchbuf, disp);
15360             oappend (scratchbuf);
15361           }
15362
15363       if (modrm.mod != 0 || modrm.rm != 6)
15364         {
15365           *obufp++ = open_char;
15366           *obufp = '\0';
15367           oappend (index16[modrm.rm]);
15368           if (intel_syntax
15369               && (disp || modrm.mod != 0 || modrm.rm == 6))
15370             {
15371               if ((bfd_signed_vma) disp >= 0)
15372                 {
15373                   *obufp++ = '+';
15374                   *obufp = '\0';
15375                 }
15376               else if (modrm.mod != 1)
15377                 {
15378                   *obufp++ = '-';
15379                   *obufp = '\0';
15380                   disp = - (bfd_signed_vma) disp;
15381                 }
15382
15383               print_displacement (scratchbuf, disp);
15384               oappend (scratchbuf);
15385             }
15386
15387           *obufp++ = close_char;
15388           *obufp = '\0';
15389         }
15390       else if (intel_syntax)
15391         {
15392           if (!active_seg_prefix)
15393             {
15394               oappend (names_seg[ds_reg - es_reg]);
15395               oappend (":");
15396             }
15397           print_operand_value (scratchbuf, 1, disp & 0xffff);
15398           oappend (scratchbuf);
15399         }
15400     }
15401   if (vex.evex && vex.b
15402       && (bytemode == x_mode
15403           || bytemode == xmmq_mode
15404           || bytemode == evex_half_bcst_xmmq_mode))
15405     {
15406       if (vex.w
15407           || bytemode == xmmq_mode
15408           || bytemode == evex_half_bcst_xmmq_mode)
15409         {
15410           switch (vex.length)
15411             {
15412             case 128:
15413               oappend ("{1to2}");
15414               break;
15415             case 256:
15416               oappend ("{1to4}");
15417               break;
15418             case 512:
15419               oappend ("{1to8}");
15420               break;
15421             default:
15422               abort ();
15423             }
15424         }
15425       else
15426         {
15427           switch (vex.length)
15428             {
15429             case 128:
15430               oappend ("{1to4}");
15431               break;
15432             case 256:
15433               oappend ("{1to8}");
15434               break;
15435             case 512:
15436               oappend ("{1to16}");
15437               break;
15438             default:
15439               abort ();
15440             }
15441         }
15442     }
15443 }
15444
15445 static void
15446 OP_E (int bytemode, int sizeflag)
15447 {
15448   /* Skip mod/rm byte.  */
15449   MODRM_CHECK;
15450   codep++;
15451
15452   if (modrm.mod == 3)
15453     OP_E_register (bytemode, sizeflag);
15454   else
15455     OP_E_memory (bytemode, sizeflag);
15456 }
15457
15458 static void
15459 OP_G (int bytemode, int sizeflag)
15460 {
15461   int add = 0;
15462   USED_REX (REX_R);
15463   if (rex & REX_R)
15464     add += 8;
15465   switch (bytemode)
15466     {
15467     case b_mode:
15468       USED_REX (0);
15469       if (rex)
15470         oappend (names8rex[modrm.reg + add]);
15471       else
15472         oappend (names8[modrm.reg + add]);
15473       break;
15474     case w_mode:
15475       oappend (names16[modrm.reg + add]);
15476       break;
15477     case d_mode:
15478     case db_mode:
15479     case dw_mode:
15480       oappend (names32[modrm.reg + add]);
15481       break;
15482     case q_mode:
15483       oappend (names64[modrm.reg + add]);
15484       break;
15485     case bnd_mode:
15486       oappend (names_bnd[modrm.reg]);
15487       break;
15488     case v_mode:
15489     case dq_mode:
15490     case dqb_mode:
15491     case dqd_mode:
15492     case dqw_mode:
15493       USED_REX (REX_W);
15494       if (rex & REX_W)
15495         oappend (names64[modrm.reg + add]);
15496       else
15497         {
15498           if ((sizeflag & DFLAG) || bytemode != v_mode)
15499             oappend (names32[modrm.reg + add]);
15500           else
15501             oappend (names16[modrm.reg + add]);
15502           used_prefixes |= (prefixes & PREFIX_DATA);
15503         }
15504       break;
15505     case m_mode:
15506       if (address_mode == mode_64bit)
15507         oappend (names64[modrm.reg + add]);
15508       else
15509         oappend (names32[modrm.reg + add]);
15510       break;
15511     case mask_bd_mode:
15512     case mask_mode:
15513       if ((modrm.reg + add) > 0x7)
15514         {
15515           oappend ("(bad)");
15516           return;
15517         }
15518       oappend (names_mask[modrm.reg + add]);
15519       break;
15520     default:
15521       oappend (INTERNAL_DISASSEMBLER_ERROR);
15522       break;
15523     }
15524 }
15525
15526 static bfd_vma
15527 get64 (void)
15528 {
15529   bfd_vma x;
15530 #ifdef BFD64
15531   unsigned int a;
15532   unsigned int b;
15533
15534   FETCH_DATA (the_info, codep + 8);
15535   a = *codep++ & 0xff;
15536   a |= (*codep++ & 0xff) << 8;
15537   a |= (*codep++ & 0xff) << 16;
15538   a |= (*codep++ & 0xffu) << 24;
15539   b = *codep++ & 0xff;
15540   b |= (*codep++ & 0xff) << 8;
15541   b |= (*codep++ & 0xff) << 16;
15542   b |= (*codep++ & 0xffu) << 24;
15543   x = a + ((bfd_vma) b << 32);
15544 #else
15545   abort ();
15546   x = 0;
15547 #endif
15548   return x;
15549 }
15550
15551 static bfd_signed_vma
15552 get32 (void)
15553 {
15554   bfd_signed_vma x = 0;
15555
15556   FETCH_DATA (the_info, codep + 4);
15557   x = *codep++ & (bfd_signed_vma) 0xff;
15558   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15559   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15560   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15561   return x;
15562 }
15563
15564 static bfd_signed_vma
15565 get32s (void)
15566 {
15567   bfd_signed_vma x = 0;
15568
15569   FETCH_DATA (the_info, codep + 4);
15570   x = *codep++ & (bfd_signed_vma) 0xff;
15571   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15572   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15573   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15574
15575   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15576
15577   return x;
15578 }
15579
15580 static int
15581 get16 (void)
15582 {
15583   int x = 0;
15584
15585   FETCH_DATA (the_info, codep + 2);
15586   x = *codep++ & 0xff;
15587   x |= (*codep++ & 0xff) << 8;
15588   return x;
15589 }
15590
15591 static void
15592 set_op (bfd_vma op, int riprel)
15593 {
15594   op_index[op_ad] = op_ad;
15595   if (address_mode == mode_64bit)
15596     {
15597       op_address[op_ad] = op;
15598       op_riprel[op_ad] = riprel;
15599     }
15600   else
15601     {
15602       /* Mask to get a 32-bit address.  */
15603       op_address[op_ad] = op & 0xffffffff;
15604       op_riprel[op_ad] = riprel & 0xffffffff;
15605     }
15606 }
15607
15608 static void
15609 OP_REG (int code, int sizeflag)
15610 {
15611   const char *s;
15612   int add;
15613
15614   switch (code)
15615     {
15616     case es_reg: case ss_reg: case cs_reg:
15617     case ds_reg: case fs_reg: case gs_reg:
15618       oappend (names_seg[code - es_reg]);
15619       return;
15620     }
15621
15622   USED_REX (REX_B);
15623   if (rex & REX_B)
15624     add = 8;
15625   else
15626     add = 0;
15627
15628   switch (code)
15629     {
15630     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15631     case sp_reg: case bp_reg: case si_reg: case di_reg:
15632       s = names16[code - ax_reg + add];
15633       break;
15634     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15635     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15636       USED_REX (0);
15637       if (rex)
15638         s = names8rex[code - al_reg + add];
15639       else
15640         s = names8[code - al_reg];
15641       break;
15642     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15643     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15644       if (address_mode == mode_64bit
15645           && ((sizeflag & DFLAG) || (rex & REX_W)))
15646         {
15647           s = names64[code - rAX_reg + add];
15648           break;
15649         }
15650       code += eAX_reg - rAX_reg;
15651       /* Fall through.  */
15652     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15653     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15654       USED_REX (REX_W);
15655       if (rex & REX_W)
15656         s = names64[code - eAX_reg + add];
15657       else
15658         {
15659           if (sizeflag & DFLAG)
15660             s = names32[code - eAX_reg + add];
15661           else
15662             s = names16[code - eAX_reg + add];
15663           used_prefixes |= (prefixes & PREFIX_DATA);
15664         }
15665       break;
15666     default:
15667       s = INTERNAL_DISASSEMBLER_ERROR;
15668       break;
15669     }
15670   oappend (s);
15671 }
15672
15673 static void
15674 OP_IMREG (int code, int sizeflag)
15675 {
15676   const char *s;
15677
15678   switch (code)
15679     {
15680     case indir_dx_reg:
15681       if (intel_syntax)
15682         s = "dx";
15683       else
15684         s = "(%dx)";
15685       break;
15686     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15687     case sp_reg: case bp_reg: case si_reg: case di_reg:
15688       s = names16[code - ax_reg];
15689       break;
15690     case es_reg: case ss_reg: case cs_reg:
15691     case ds_reg: case fs_reg: case gs_reg:
15692       s = names_seg[code - es_reg];
15693       break;
15694     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15695     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15696       USED_REX (0);
15697       if (rex)
15698         s = names8rex[code - al_reg];
15699       else
15700         s = names8[code - al_reg];
15701       break;
15702     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15703     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15704       USED_REX (REX_W);
15705       if (rex & REX_W)
15706         s = names64[code - eAX_reg];
15707       else
15708         {
15709           if (sizeflag & DFLAG)
15710             s = names32[code - eAX_reg];
15711           else
15712             s = names16[code - eAX_reg];
15713           used_prefixes |= (prefixes & PREFIX_DATA);
15714         }
15715       break;
15716     case z_mode_ax_reg:
15717       if ((rex & REX_W) || (sizeflag & DFLAG))
15718         s = *names32;
15719       else
15720         s = *names16;
15721       if (!(rex & REX_W))
15722         used_prefixes |= (prefixes & PREFIX_DATA);
15723       break;
15724     default:
15725       s = INTERNAL_DISASSEMBLER_ERROR;
15726       break;
15727     }
15728   oappend (s);
15729 }
15730
15731 static void
15732 OP_I (int bytemode, int sizeflag)
15733 {
15734   bfd_signed_vma op;
15735   bfd_signed_vma mask = -1;
15736
15737   switch (bytemode)
15738     {
15739     case b_mode:
15740       FETCH_DATA (the_info, codep + 1);
15741       op = *codep++;
15742       mask = 0xff;
15743       break;
15744     case q_mode:
15745       if (address_mode == mode_64bit)
15746         {
15747           op = get32s ();
15748           break;
15749         }
15750       /* Fall through.  */
15751     case v_mode:
15752       USED_REX (REX_W);
15753       if (rex & REX_W)
15754         op = get32s ();
15755       else
15756         {
15757           if (sizeflag & DFLAG)
15758             {
15759               op = get32 ();
15760               mask = 0xffffffff;
15761             }
15762           else
15763             {
15764               op = get16 ();
15765               mask = 0xfffff;
15766             }
15767           used_prefixes |= (prefixes & PREFIX_DATA);
15768         }
15769       break;
15770     case w_mode:
15771       mask = 0xfffff;
15772       op = get16 ();
15773       break;
15774     case const_1_mode:
15775       if (intel_syntax)
15776         oappend ("1");
15777       return;
15778     default:
15779       oappend (INTERNAL_DISASSEMBLER_ERROR);
15780       return;
15781     }
15782
15783   op &= mask;
15784   scratchbuf[0] = '$';
15785   print_operand_value (scratchbuf + 1, 1, op);
15786   oappend_maybe_intel (scratchbuf);
15787   scratchbuf[0] = '\0';
15788 }
15789
15790 static void
15791 OP_I64 (int bytemode, int sizeflag)
15792 {
15793   bfd_signed_vma op;
15794   bfd_signed_vma mask = -1;
15795
15796   if (address_mode != mode_64bit)
15797     {
15798       OP_I (bytemode, sizeflag);
15799       return;
15800     }
15801
15802   switch (bytemode)
15803     {
15804     case b_mode:
15805       FETCH_DATA (the_info, codep + 1);
15806       op = *codep++;
15807       mask = 0xff;
15808       break;
15809     case v_mode:
15810       USED_REX (REX_W);
15811       if (rex & REX_W)
15812         op = get64 ();
15813       else
15814         {
15815           if (sizeflag & DFLAG)
15816             {
15817               op = get32 ();
15818               mask = 0xffffffff;
15819             }
15820           else
15821             {
15822               op = get16 ();
15823               mask = 0xfffff;
15824             }
15825           used_prefixes |= (prefixes & PREFIX_DATA);
15826         }
15827       break;
15828     case w_mode:
15829       mask = 0xfffff;
15830       op = get16 ();
15831       break;
15832     default:
15833       oappend (INTERNAL_DISASSEMBLER_ERROR);
15834       return;
15835     }
15836
15837   op &= mask;
15838   scratchbuf[0] = '$';
15839   print_operand_value (scratchbuf + 1, 1, op);
15840   oappend_maybe_intel (scratchbuf);
15841   scratchbuf[0] = '\0';
15842 }
15843
15844 static void
15845 OP_sI (int bytemode, int sizeflag)
15846 {
15847   bfd_signed_vma op;
15848
15849   switch (bytemode)
15850     {
15851     case b_mode:
15852     case b_T_mode:
15853       FETCH_DATA (the_info, codep + 1);
15854       op = *codep++;
15855       if ((op & 0x80) != 0)
15856         op -= 0x100;
15857       if (bytemode == b_T_mode)
15858         {
15859           if (address_mode != mode_64bit
15860               || !((sizeflag & DFLAG) || (rex & REX_W)))
15861             {
15862               /* The operand-size prefix is overridden by a REX prefix.  */
15863               if ((sizeflag & DFLAG) || (rex & REX_W))
15864                 op &= 0xffffffff;
15865               else
15866                 op &= 0xffff;
15867           }
15868         }
15869       else
15870         {
15871           if (!(rex & REX_W))
15872             {
15873               if (sizeflag & DFLAG)
15874                 op &= 0xffffffff;
15875               else
15876                 op &= 0xffff;
15877             }
15878         }
15879       break;
15880     case v_mode:
15881       /* The operand-size prefix is overridden by a REX prefix.  */
15882       if ((sizeflag & DFLAG) || (rex & REX_W))
15883         op = get32s ();
15884       else
15885         op = get16 ();
15886       break;
15887     default:
15888       oappend (INTERNAL_DISASSEMBLER_ERROR);
15889       return;
15890     }
15891
15892   scratchbuf[0] = '$';
15893   print_operand_value (scratchbuf + 1, 1, op);
15894   oappend_maybe_intel (scratchbuf);
15895 }
15896
15897 static void
15898 OP_J (int bytemode, int sizeflag)
15899 {
15900   bfd_vma disp;
15901   bfd_vma mask = -1;
15902   bfd_vma segment = 0;
15903
15904   switch (bytemode)
15905     {
15906     case b_mode:
15907       FETCH_DATA (the_info, codep + 1);
15908       disp = *codep++;
15909       if ((disp & 0x80) != 0)
15910         disp -= 0x100;
15911       break;
15912     case v_mode:
15913       if (isa64 == amd64)
15914         USED_REX (REX_W);
15915       if ((sizeflag & DFLAG)
15916           || (address_mode == mode_64bit
15917               && (isa64 != amd64 || (rex & REX_W))))
15918         disp = get32s ();
15919       else
15920         {
15921           disp = get16 ();
15922           if ((disp & 0x8000) != 0)
15923             disp -= 0x10000;
15924           /* In 16bit mode, address is wrapped around at 64k within
15925              the same segment.  Otherwise, a data16 prefix on a jump
15926              instruction means that the pc is masked to 16 bits after
15927              the displacement is added!  */
15928           mask = 0xffff;
15929           if ((prefixes & PREFIX_DATA) == 0)
15930             segment = ((start_pc + (codep - start_codep))
15931                        & ~((bfd_vma) 0xffff));
15932         }
15933       if (address_mode != mode_64bit
15934           || (isa64 == amd64 && !(rex & REX_W)))
15935         used_prefixes |= (prefixes & PREFIX_DATA);
15936       break;
15937     default:
15938       oappend (INTERNAL_DISASSEMBLER_ERROR);
15939       return;
15940     }
15941   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15942   set_op (disp, 0);
15943   print_operand_value (scratchbuf, 1, disp);
15944   oappend (scratchbuf);
15945 }
15946
15947 static void
15948 OP_SEG (int bytemode, int sizeflag)
15949 {
15950   if (bytemode == w_mode)
15951     oappend (names_seg[modrm.reg]);
15952   else
15953     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15954 }
15955
15956 static void
15957 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15958 {
15959   int seg, offset;
15960
15961   if (sizeflag & DFLAG)
15962     {
15963       offset = get32 ();
15964       seg = get16 ();
15965     }
15966   else
15967     {
15968       offset = get16 ();
15969       seg = get16 ();
15970     }
15971   used_prefixes |= (prefixes & PREFIX_DATA);
15972   if (intel_syntax)
15973     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15974   else
15975     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15976   oappend (scratchbuf);
15977 }
15978
15979 static void
15980 OP_OFF (int bytemode, int sizeflag)
15981 {
15982   bfd_vma off;
15983
15984   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15985     intel_operand_size (bytemode, sizeflag);
15986   append_seg ();
15987
15988   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15989     off = get32 ();
15990   else
15991     off = get16 ();
15992
15993   if (intel_syntax)
15994     {
15995       if (!active_seg_prefix)
15996         {
15997           oappend (names_seg[ds_reg - es_reg]);
15998           oappend (":");
15999         }
16000     }
16001   print_operand_value (scratchbuf, 1, off);
16002   oappend (scratchbuf);
16003 }
16004
16005 static void
16006 OP_OFF64 (int bytemode, int sizeflag)
16007 {
16008   bfd_vma off;
16009
16010   if (address_mode != mode_64bit
16011       || (prefixes & PREFIX_ADDR))
16012     {
16013       OP_OFF (bytemode, sizeflag);
16014       return;
16015     }
16016
16017   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16018     intel_operand_size (bytemode, sizeflag);
16019   append_seg ();
16020
16021   off = get64 ();
16022
16023   if (intel_syntax)
16024     {
16025       if (!active_seg_prefix)
16026         {
16027           oappend (names_seg[ds_reg - es_reg]);
16028           oappend (":");
16029         }
16030     }
16031   print_operand_value (scratchbuf, 1, off);
16032   oappend (scratchbuf);
16033 }
16034
16035 static void
16036 ptr_reg (int code, int sizeflag)
16037 {
16038   const char *s;
16039
16040   *obufp++ = open_char;
16041   used_prefixes |= (prefixes & PREFIX_ADDR);
16042   if (address_mode == mode_64bit)
16043     {
16044       if (!(sizeflag & AFLAG))
16045         s = names32[code - eAX_reg];
16046       else
16047         s = names64[code - eAX_reg];
16048     }
16049   else if (sizeflag & AFLAG)
16050     s = names32[code - eAX_reg];
16051   else
16052     s = names16[code - eAX_reg];
16053   oappend (s);
16054   *obufp++ = close_char;
16055   *obufp = 0;
16056 }
16057
16058 static void
16059 OP_ESreg (int code, int sizeflag)
16060 {
16061   if (intel_syntax)
16062     {
16063       switch (codep[-1])
16064         {
16065         case 0x6d:      /* insw/insl */
16066           intel_operand_size (z_mode, sizeflag);
16067           break;
16068         case 0xa5:      /* movsw/movsl/movsq */
16069         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16070         case 0xab:      /* stosw/stosl */
16071         case 0xaf:      /* scasw/scasl */
16072           intel_operand_size (v_mode, sizeflag);
16073           break;
16074         default:
16075           intel_operand_size (b_mode, sizeflag);
16076         }
16077     }
16078   oappend_maybe_intel ("%es:");
16079   ptr_reg (code, sizeflag);
16080 }
16081
16082 static void
16083 OP_DSreg (int code, int sizeflag)
16084 {
16085   if (intel_syntax)
16086     {
16087       switch (codep[-1])
16088         {
16089         case 0x6f:      /* outsw/outsl */
16090           intel_operand_size (z_mode, sizeflag);
16091           break;
16092         case 0xa5:      /* movsw/movsl/movsq */
16093         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16094         case 0xad:      /* lodsw/lodsl/lodsq */
16095           intel_operand_size (v_mode, sizeflag);
16096           break;
16097         default:
16098           intel_operand_size (b_mode, sizeflag);
16099         }
16100     }
16101   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16102      default segment register DS is printed.  */
16103   if (!active_seg_prefix)
16104     active_seg_prefix = PREFIX_DS;
16105   append_seg ();
16106   ptr_reg (code, sizeflag);
16107 }
16108
16109 static void
16110 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16111 {
16112   int add;
16113   if (rex & REX_R)
16114     {
16115       USED_REX (REX_R);
16116       add = 8;
16117     }
16118   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16119     {
16120       all_prefixes[last_lock_prefix] = 0;
16121       used_prefixes |= PREFIX_LOCK;
16122       add = 8;
16123     }
16124   else
16125     add = 0;
16126   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16127   oappend_maybe_intel (scratchbuf);
16128 }
16129
16130 static void
16131 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16132 {
16133   int add;
16134   USED_REX (REX_R);
16135   if (rex & REX_R)
16136     add = 8;
16137   else
16138     add = 0;
16139   if (intel_syntax)
16140     sprintf (scratchbuf, "db%d", modrm.reg + add);
16141   else
16142     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16143   oappend (scratchbuf);
16144 }
16145
16146 static void
16147 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16148 {
16149   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16150   oappend_maybe_intel (scratchbuf);
16151 }
16152
16153 static void
16154 OP_R (int bytemode, int sizeflag)
16155 {
16156   /* Skip mod/rm byte.  */
16157   MODRM_CHECK;
16158   codep++;
16159   OP_E_register (bytemode, sizeflag);
16160 }
16161
16162 static void
16163 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16164 {
16165   int reg = modrm.reg;
16166   const char **names;
16167
16168   used_prefixes |= (prefixes & PREFIX_DATA);
16169   if (prefixes & PREFIX_DATA)
16170     {
16171       names = names_xmm;
16172       USED_REX (REX_R);
16173       if (rex & REX_R)
16174         reg += 8;
16175     }
16176   else
16177     names = names_mm;
16178   oappend (names[reg]);
16179 }
16180
16181 static void
16182 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16183 {
16184   int reg = modrm.reg;
16185   const char **names;
16186
16187   USED_REX (REX_R);
16188   if (rex & REX_R)
16189     reg += 8;
16190   if (vex.evex)
16191     {
16192       if (!vex.r)
16193         reg += 16;
16194     }
16195
16196   if (need_vex
16197       && bytemode != xmm_mode
16198       && bytemode != xmmq_mode
16199       && bytemode != evex_half_bcst_xmmq_mode
16200       && bytemode != ymm_mode
16201       && bytemode != scalar_mode)
16202     {
16203       switch (vex.length)
16204         {
16205         case 128:
16206           names = names_xmm;
16207           break;
16208         case 256:
16209           if (vex.w
16210               || (bytemode != vex_vsib_q_w_dq_mode
16211                   && bytemode != vex_vsib_q_w_d_mode))
16212             names = names_ymm;
16213           else
16214             names = names_xmm;
16215           break;
16216         case 512:
16217           names = names_zmm;
16218           break;
16219         default:
16220           abort ();
16221         }
16222     }
16223   else if (bytemode == xmmq_mode
16224            || bytemode == evex_half_bcst_xmmq_mode)
16225     {
16226       switch (vex.length)
16227         {
16228         case 128:
16229         case 256:
16230           names = names_xmm;
16231           break;
16232         case 512:
16233           names = names_ymm;
16234           break;
16235         default:
16236           abort ();
16237         }
16238     }
16239   else if (bytemode == ymm_mode)
16240     names = names_ymm;
16241   else
16242     names = names_xmm;
16243   oappend (names[reg]);
16244 }
16245
16246 static void
16247 OP_EM (int bytemode, int sizeflag)
16248 {
16249   int reg;
16250   const char **names;
16251
16252   if (modrm.mod != 3)
16253     {
16254       if (intel_syntax
16255           && (bytemode == v_mode || bytemode == v_swap_mode))
16256         {
16257           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16258           used_prefixes |= (prefixes & PREFIX_DATA);
16259         }
16260       OP_E (bytemode, sizeflag);
16261       return;
16262     }
16263
16264   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16265     swap_operand ();
16266
16267   /* Skip mod/rm byte.  */
16268   MODRM_CHECK;
16269   codep++;
16270   used_prefixes |= (prefixes & PREFIX_DATA);
16271   reg = modrm.rm;
16272   if (prefixes & PREFIX_DATA)
16273     {
16274       names = names_xmm;
16275       USED_REX (REX_B);
16276       if (rex & REX_B)
16277         reg += 8;
16278     }
16279   else
16280     names = names_mm;
16281   oappend (names[reg]);
16282 }
16283
16284 /* cvt* are the only instructions in sse2 which have
16285    both SSE and MMX operands and also have 0x66 prefix
16286    in their opcode. 0x66 was originally used to differentiate
16287    between SSE and MMX instruction(operands). So we have to handle the
16288    cvt* separately using OP_EMC and OP_MXC */
16289 static void
16290 OP_EMC (int bytemode, int sizeflag)
16291 {
16292   if (modrm.mod != 3)
16293     {
16294       if (intel_syntax && bytemode == v_mode)
16295         {
16296           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16297           used_prefixes |= (prefixes & PREFIX_DATA);
16298         }
16299       OP_E (bytemode, sizeflag);
16300       return;
16301     }
16302
16303   /* Skip mod/rm byte.  */
16304   MODRM_CHECK;
16305   codep++;
16306   used_prefixes |= (prefixes & PREFIX_DATA);
16307   oappend (names_mm[modrm.rm]);
16308 }
16309
16310 static void
16311 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16312 {
16313   used_prefixes |= (prefixes & PREFIX_DATA);
16314   oappend (names_mm[modrm.reg]);
16315 }
16316
16317 static void
16318 OP_EX (int bytemode, int sizeflag)
16319 {
16320   int reg;
16321   const char **names;
16322
16323   /* Skip mod/rm byte.  */
16324   MODRM_CHECK;
16325   codep++;
16326
16327   if (modrm.mod != 3)
16328     {
16329       OP_E_memory (bytemode, sizeflag);
16330       return;
16331     }
16332
16333   reg = modrm.rm;
16334   USED_REX (REX_B);
16335   if (rex & REX_B)
16336     reg += 8;
16337   if (vex.evex)
16338     {
16339       USED_REX (REX_X);
16340       if ((rex & REX_X))
16341         reg += 16;
16342     }
16343
16344   if ((sizeflag & SUFFIX_ALWAYS)
16345       && (bytemode == x_swap_mode
16346           || bytemode == d_swap_mode
16347           || bytemode == d_scalar_swap_mode
16348           || bytemode == q_swap_mode
16349           || bytemode == q_scalar_swap_mode))
16350     swap_operand ();
16351
16352   if (need_vex
16353       && bytemode != xmm_mode
16354       && bytemode != xmmdw_mode
16355       && bytemode != xmmqd_mode
16356       && bytemode != xmm_mb_mode
16357       && bytemode != xmm_mw_mode
16358       && bytemode != xmm_md_mode
16359       && bytemode != xmm_mq_mode
16360       && bytemode != xmm_mdq_mode
16361       && bytemode != xmmq_mode
16362       && bytemode != evex_half_bcst_xmmq_mode
16363       && bytemode != ymm_mode
16364       && bytemode != d_scalar_mode
16365       && bytemode != d_scalar_swap_mode
16366       && bytemode != q_scalar_mode
16367       && bytemode != q_scalar_swap_mode
16368       && bytemode != vex_scalar_w_dq_mode)
16369     {
16370       switch (vex.length)
16371         {
16372         case 128:
16373           names = names_xmm;
16374           break;
16375         case 256:
16376           names = names_ymm;
16377           break;
16378         case 512:
16379           names = names_zmm;
16380           break;
16381         default:
16382           abort ();
16383         }
16384     }
16385   else if (bytemode == xmmq_mode
16386            || bytemode == evex_half_bcst_xmmq_mode)
16387     {
16388       switch (vex.length)
16389         {
16390         case 128:
16391         case 256:
16392           names = names_xmm;
16393           break;
16394         case 512:
16395           names = names_ymm;
16396           break;
16397         default:
16398           abort ();
16399         }
16400     }
16401   else if (bytemode == ymm_mode)
16402     names = names_ymm;
16403   else
16404     names = names_xmm;
16405   oappend (names[reg]);
16406 }
16407
16408 static void
16409 OP_MS (int bytemode, int sizeflag)
16410 {
16411   if (modrm.mod == 3)
16412     OP_EM (bytemode, sizeflag);
16413   else
16414     BadOp ();
16415 }
16416
16417 static void
16418 OP_XS (int bytemode, int sizeflag)
16419 {
16420   if (modrm.mod == 3)
16421     OP_EX (bytemode, sizeflag);
16422   else
16423     BadOp ();
16424 }
16425
16426 static void
16427 OP_M (int bytemode, int sizeflag)
16428 {
16429   if (modrm.mod == 3)
16430     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16431     BadOp ();
16432   else
16433     OP_E (bytemode, sizeflag);
16434 }
16435
16436 static void
16437 OP_0f07 (int bytemode, int sizeflag)
16438 {
16439   if (modrm.mod != 3 || modrm.rm != 0)
16440     BadOp ();
16441   else
16442     OP_E (bytemode, sizeflag);
16443 }
16444
16445 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16446    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16447
16448 static void
16449 NOP_Fixup1 (int bytemode, int sizeflag)
16450 {
16451   if ((prefixes & PREFIX_DATA) != 0
16452       || (rex != 0
16453           && rex != 0x48
16454           && address_mode == mode_64bit))
16455     OP_REG (bytemode, sizeflag);
16456   else
16457     strcpy (obuf, "nop");
16458 }
16459
16460 static void
16461 NOP_Fixup2 (int bytemode, int sizeflag)
16462 {
16463   if ((prefixes & PREFIX_DATA) != 0
16464       || (rex != 0
16465           && rex != 0x48
16466           && address_mode == mode_64bit))
16467     OP_IMREG (bytemode, sizeflag);
16468 }
16469
16470 static const char *const Suffix3DNow[] = {
16471 /* 00 */        NULL,           NULL,           NULL,           NULL,
16472 /* 04 */        NULL,           NULL,           NULL,           NULL,
16473 /* 08 */        NULL,           NULL,           NULL,           NULL,
16474 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16475 /* 10 */        NULL,           NULL,           NULL,           NULL,
16476 /* 14 */        NULL,           NULL,           NULL,           NULL,
16477 /* 18 */        NULL,           NULL,           NULL,           NULL,
16478 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16479 /* 20 */        NULL,           NULL,           NULL,           NULL,
16480 /* 24 */        NULL,           NULL,           NULL,           NULL,
16481 /* 28 */        NULL,           NULL,           NULL,           NULL,
16482 /* 2C */        NULL,           NULL,           NULL,           NULL,
16483 /* 30 */        NULL,           NULL,           NULL,           NULL,
16484 /* 34 */        NULL,           NULL,           NULL,           NULL,
16485 /* 38 */        NULL,           NULL,           NULL,           NULL,
16486 /* 3C */        NULL,           NULL,           NULL,           NULL,
16487 /* 40 */        NULL,           NULL,           NULL,           NULL,
16488 /* 44 */        NULL,           NULL,           NULL,           NULL,
16489 /* 48 */        NULL,           NULL,           NULL,           NULL,
16490 /* 4C */        NULL,           NULL,           NULL,           NULL,
16491 /* 50 */        NULL,           NULL,           NULL,           NULL,
16492 /* 54 */        NULL,           NULL,           NULL,           NULL,
16493 /* 58 */        NULL,           NULL,           NULL,           NULL,
16494 /* 5C */        NULL,           NULL,           NULL,           NULL,
16495 /* 60 */        NULL,           NULL,           NULL,           NULL,
16496 /* 64 */        NULL,           NULL,           NULL,           NULL,
16497 /* 68 */        NULL,           NULL,           NULL,           NULL,
16498 /* 6C */        NULL,           NULL,           NULL,           NULL,
16499 /* 70 */        NULL,           NULL,           NULL,           NULL,
16500 /* 74 */        NULL,           NULL,           NULL,           NULL,
16501 /* 78 */        NULL,           NULL,           NULL,           NULL,
16502 /* 7C */        NULL,           NULL,           NULL,           NULL,
16503 /* 80 */        NULL,           NULL,           NULL,           NULL,
16504 /* 84 */        NULL,           NULL,           NULL,           NULL,
16505 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16506 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16507 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16508 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16509 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16510 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16511 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16512 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16513 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16514 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16515 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16516 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16517 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16518 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16519 /* C0 */        NULL,           NULL,           NULL,           NULL,
16520 /* C4 */        NULL,           NULL,           NULL,           NULL,
16521 /* C8 */        NULL,           NULL,           NULL,           NULL,
16522 /* CC */        NULL,           NULL,           NULL,           NULL,
16523 /* D0 */        NULL,           NULL,           NULL,           NULL,
16524 /* D4 */        NULL,           NULL,           NULL,           NULL,
16525 /* D8 */        NULL,           NULL,           NULL,           NULL,
16526 /* DC */        NULL,           NULL,           NULL,           NULL,
16527 /* E0 */        NULL,           NULL,           NULL,           NULL,
16528 /* E4 */        NULL,           NULL,           NULL,           NULL,
16529 /* E8 */        NULL,           NULL,           NULL,           NULL,
16530 /* EC */        NULL,           NULL,           NULL,           NULL,
16531 /* F0 */        NULL,           NULL,           NULL,           NULL,
16532 /* F4 */        NULL,           NULL,           NULL,           NULL,
16533 /* F8 */        NULL,           NULL,           NULL,           NULL,
16534 /* FC */        NULL,           NULL,           NULL,           NULL,
16535 };
16536
16537 static void
16538 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16539 {
16540   const char *mnemonic;
16541
16542   FETCH_DATA (the_info, codep + 1);
16543   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16544      place where an 8-bit immediate would normally go.  ie. the last
16545      byte of the instruction.  */
16546   obufp = mnemonicendp;
16547   mnemonic = Suffix3DNow[*codep++ & 0xff];
16548   if (mnemonic)
16549     oappend (mnemonic);
16550   else
16551     {
16552       /* Since a variable sized modrm/sib chunk is between the start
16553          of the opcode (0x0f0f) and the opcode suffix, we need to do
16554          all the modrm processing first, and don't know until now that
16555          we have a bad opcode.  This necessitates some cleaning up.  */
16556       op_out[0][0] = '\0';
16557       op_out[1][0] = '\0';
16558       BadOp ();
16559     }
16560   mnemonicendp = obufp;
16561 }
16562
16563 static struct op simd_cmp_op[] =
16564 {
16565   { STRING_COMMA_LEN ("eq") },
16566   { STRING_COMMA_LEN ("lt") },
16567   { STRING_COMMA_LEN ("le") },
16568   { STRING_COMMA_LEN ("unord") },
16569   { STRING_COMMA_LEN ("neq") },
16570   { STRING_COMMA_LEN ("nlt") },
16571   { STRING_COMMA_LEN ("nle") },
16572   { STRING_COMMA_LEN ("ord") }
16573 };
16574
16575 static void
16576 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16577 {
16578   unsigned int cmp_type;
16579
16580   FETCH_DATA (the_info, codep + 1);
16581   cmp_type = *codep++ & 0xff;
16582   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16583     {
16584       char suffix [3];
16585       char *p = mnemonicendp - 2;
16586       suffix[0] = p[0];
16587       suffix[1] = p[1];
16588       suffix[2] = '\0';
16589       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16590       mnemonicendp += simd_cmp_op[cmp_type].len;
16591     }
16592   else
16593     {
16594       /* We have a reserved extension byte.  Output it directly.  */
16595       scratchbuf[0] = '$';
16596       print_operand_value (scratchbuf + 1, 1, cmp_type);
16597       oappend_maybe_intel (scratchbuf);
16598       scratchbuf[0] = '\0';
16599     }
16600 }
16601
16602 static void
16603 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16604           int sizeflag ATTRIBUTE_UNUSED)
16605 {
16606   /* mwaitx %eax,%ecx,%ebx */
16607   if (!intel_syntax)
16608     {
16609       const char **names = (address_mode == mode_64bit
16610                             ? names64 : names32);
16611       strcpy (op_out[0], names[0]);
16612       strcpy (op_out[1], names[1]);
16613       strcpy (op_out[2], names[3]);
16614       two_source_ops = 1;
16615     }
16616   /* Skip mod/rm byte.  */
16617   MODRM_CHECK;
16618   codep++;
16619 }
16620
16621 static void
16622 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16623           int sizeflag ATTRIBUTE_UNUSED)
16624 {
16625   /* mwait %eax,%ecx  */
16626   if (!intel_syntax)
16627     {
16628       const char **names = (address_mode == mode_64bit
16629                             ? names64 : names32);
16630       strcpy (op_out[0], names[0]);
16631       strcpy (op_out[1], names[1]);
16632       two_source_ops = 1;
16633     }
16634   /* Skip mod/rm byte.  */
16635   MODRM_CHECK;
16636   codep++;
16637 }
16638
16639 static void
16640 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16641             int sizeflag ATTRIBUTE_UNUSED)
16642 {
16643   /* monitor %eax,%ecx,%edx"  */
16644   if (!intel_syntax)
16645     {
16646       const char **op1_names;
16647       const char **names = (address_mode == mode_64bit
16648                             ? names64 : names32);
16649
16650       if (!(prefixes & PREFIX_ADDR))
16651         op1_names = (address_mode == mode_16bit
16652                      ? names16 : names);
16653       else
16654         {
16655           /* Remove "addr16/addr32".  */
16656           all_prefixes[last_addr_prefix] = 0;
16657           op1_names = (address_mode != mode_32bit
16658                        ? names32 : names16);
16659           used_prefixes |= PREFIX_ADDR;
16660         }
16661       strcpy (op_out[0], op1_names[0]);
16662       strcpy (op_out[1], names[1]);
16663       strcpy (op_out[2], names[2]);
16664       two_source_ops = 1;
16665     }
16666   /* Skip mod/rm byte.  */
16667   MODRM_CHECK;
16668   codep++;
16669 }
16670
16671 static void
16672 BadOp (void)
16673 {
16674   /* Throw away prefixes and 1st. opcode byte.  */
16675   codep = insn_codep + 1;
16676   oappend ("(bad)");
16677 }
16678
16679 static void
16680 REP_Fixup (int bytemode, int sizeflag)
16681 {
16682   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16683      lods and stos.  */
16684   if (prefixes & PREFIX_REPZ)
16685     all_prefixes[last_repz_prefix] = REP_PREFIX;
16686
16687   switch (bytemode)
16688     {
16689     case al_reg:
16690     case eAX_reg:
16691     case indir_dx_reg:
16692       OP_IMREG (bytemode, sizeflag);
16693       break;
16694     case eDI_reg:
16695       OP_ESreg (bytemode, sizeflag);
16696       break;
16697     case eSI_reg:
16698       OP_DSreg (bytemode, sizeflag);
16699       break;
16700     default:
16701       abort ();
16702       break;
16703     }
16704 }
16705
16706 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16707    "bnd".  */
16708
16709 static void
16710 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16711 {
16712   if (prefixes & PREFIX_REPNZ)
16713     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16714 }
16715
16716 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16717    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16718  */
16719
16720 static void
16721 HLE_Fixup1 (int bytemode, int sizeflag)
16722 {
16723   if (modrm.mod != 3
16724       && (prefixes & PREFIX_LOCK) != 0)
16725     {
16726       if (prefixes & PREFIX_REPZ)
16727         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16728       if (prefixes & PREFIX_REPNZ)
16729         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16730     }
16731
16732   OP_E (bytemode, sizeflag);
16733 }
16734
16735 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16736    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16737  */
16738
16739 static void
16740 HLE_Fixup2 (int bytemode, int sizeflag)
16741 {
16742   if (modrm.mod != 3)
16743     {
16744       if (prefixes & PREFIX_REPZ)
16745         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16746       if (prefixes & PREFIX_REPNZ)
16747         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16748     }
16749
16750   OP_E (bytemode, sizeflag);
16751 }
16752
16753 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16754    "xrelease" for memory operand.  No check for LOCK prefix.   */
16755
16756 static void
16757 HLE_Fixup3 (int bytemode, int sizeflag)
16758 {
16759   if (modrm.mod != 3
16760       && last_repz_prefix > last_repnz_prefix
16761       && (prefixes & PREFIX_REPZ) != 0)
16762     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16763
16764   OP_E (bytemode, sizeflag);
16765 }
16766
16767 static void
16768 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16769 {
16770   USED_REX (REX_W);
16771   if (rex & REX_W)
16772     {
16773       /* Change cmpxchg8b to cmpxchg16b.  */
16774       char *p = mnemonicendp - 2;
16775       mnemonicendp = stpcpy (p, "16b");
16776       bytemode = o_mode;
16777     }
16778   else if ((prefixes & PREFIX_LOCK) != 0)
16779     {
16780       if (prefixes & PREFIX_REPZ)
16781         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16782       if (prefixes & PREFIX_REPNZ)
16783         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16784     }
16785
16786   OP_M (bytemode, sizeflag);
16787 }
16788
16789 static void
16790 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16791 {
16792   const char **names;
16793
16794   if (need_vex)
16795     {
16796       switch (vex.length)
16797         {
16798         case 128:
16799           names = names_xmm;
16800           break;
16801         case 256:
16802           names = names_ymm;
16803           break;
16804         default:
16805           abort ();
16806         }
16807     }
16808   else
16809     names = names_xmm;
16810   oappend (names[reg]);
16811 }
16812
16813 static void
16814 CRC32_Fixup (int bytemode, int sizeflag)
16815 {
16816   /* Add proper suffix to "crc32".  */
16817   char *p = mnemonicendp;
16818
16819   switch (bytemode)
16820     {
16821     case b_mode:
16822       if (intel_syntax)
16823         goto skip;
16824
16825       *p++ = 'b';
16826       break;
16827     case v_mode:
16828       if (intel_syntax)
16829         goto skip;
16830
16831       USED_REX (REX_W);
16832       if (rex & REX_W)
16833         *p++ = 'q';
16834       else
16835         {
16836           if (sizeflag & DFLAG)
16837             *p++ = 'l';
16838           else
16839             *p++ = 'w';
16840           used_prefixes |= (prefixes & PREFIX_DATA);
16841         }
16842       break;
16843     default:
16844       oappend (INTERNAL_DISASSEMBLER_ERROR);
16845       break;
16846     }
16847   mnemonicendp = p;
16848   *p = '\0';
16849
16850 skip:
16851   if (modrm.mod == 3)
16852     {
16853       int add;
16854
16855       /* Skip mod/rm byte.  */
16856       MODRM_CHECK;
16857       codep++;
16858
16859       USED_REX (REX_B);
16860       add = (rex & REX_B) ? 8 : 0;
16861       if (bytemode == b_mode)
16862         {
16863           USED_REX (0);
16864           if (rex)
16865             oappend (names8rex[modrm.rm + add]);
16866           else
16867             oappend (names8[modrm.rm + add]);
16868         }
16869       else
16870         {
16871           USED_REX (REX_W);
16872           if (rex & REX_W)
16873             oappend (names64[modrm.rm + add]);
16874           else if ((prefixes & PREFIX_DATA))
16875             oappend (names16[modrm.rm + add]);
16876           else
16877             oappend (names32[modrm.rm + add]);
16878         }
16879     }
16880   else
16881     OP_E (bytemode, sizeflag);
16882 }
16883
16884 static void
16885 FXSAVE_Fixup (int bytemode, int sizeflag)
16886 {
16887   /* Add proper suffix to "fxsave" and "fxrstor".  */
16888   USED_REX (REX_W);
16889   if (rex & REX_W)
16890     {
16891       char *p = mnemonicendp;
16892       *p++ = '6';
16893       *p++ = '4';
16894       *p = '\0';
16895       mnemonicendp = p;
16896     }
16897   OP_M (bytemode, sizeflag);
16898 }
16899
16900 /* Display the destination register operand for instructions with
16901    VEX. */
16902
16903 static void
16904 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16905 {
16906   int reg;
16907   const char **names;
16908
16909   if (!need_vex)
16910     abort ();
16911
16912   if (!need_vex_reg)
16913     return;
16914
16915   reg = vex.register_specifier;
16916   if (vex.evex)
16917     {
16918       if (!vex.v)
16919         reg += 16;
16920     }
16921
16922   if (bytemode == vex_scalar_mode)
16923     {
16924       oappend (names_xmm[reg]);
16925       return;
16926     }
16927
16928   switch (vex.length)
16929     {
16930     case 128:
16931       switch (bytemode)
16932         {
16933         case vex_mode:
16934         case vex128_mode:
16935         case vex_vsib_q_w_dq_mode:
16936         case vex_vsib_q_w_d_mode:
16937           names = names_xmm;
16938           break;
16939         case dq_mode:
16940           if (vex.w)
16941             names = names64;
16942           else
16943             names = names32;
16944           break;
16945         case mask_bd_mode:
16946         case mask_mode:
16947           if (reg > 0x7)
16948             {
16949               oappend ("(bad)");
16950               return;
16951             }
16952           names = names_mask;
16953           break;
16954         default:
16955           abort ();
16956           return;
16957         }
16958       break;
16959     case 256:
16960       switch (bytemode)
16961         {
16962         case vex_mode:
16963         case vex256_mode:
16964           names = names_ymm;
16965           break;
16966         case vex_vsib_q_w_dq_mode:
16967         case vex_vsib_q_w_d_mode:
16968           names = vex.w ? names_ymm : names_xmm;
16969           break;
16970         case mask_bd_mode:
16971         case mask_mode:
16972           if (reg > 0x7)
16973             {
16974               oappend ("(bad)");
16975               return;
16976             }
16977           names = names_mask;
16978           break;
16979         default:
16980           /* See PR binutils/20893 for a reproducer.  */
16981           oappend ("(bad)");
16982           return;
16983         }
16984       break;
16985     case 512:
16986       names = names_zmm;
16987       break;
16988     default:
16989       abort ();
16990       break;
16991     }
16992   oappend (names[reg]);
16993 }
16994
16995 /* Get the VEX immediate byte without moving codep.  */
16996
16997 static unsigned char
16998 get_vex_imm8 (int sizeflag, int opnum)
16999 {
17000   int bytes_before_imm = 0;
17001
17002   if (modrm.mod != 3)
17003     {
17004       /* There are SIB/displacement bytes.  */
17005       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17006         {
17007           /* 32/64 bit address mode */
17008           int base = modrm.rm;
17009
17010           /* Check SIB byte.  */
17011           if (base == 4)
17012             {
17013               FETCH_DATA (the_info, codep + 1);
17014               base = *codep & 7;
17015               /* When decoding the third source, don't increase
17016                  bytes_before_imm as this has already been incremented
17017                  by one in OP_E_memory while decoding the second
17018                  source operand.  */
17019               if (opnum == 0)
17020                 bytes_before_imm++;
17021             }
17022
17023           /* Don't increase bytes_before_imm when decoding the third source,
17024              it has already been incremented by OP_E_memory while decoding
17025              the second source operand.  */
17026           if (opnum == 0)
17027             {
17028               switch (modrm.mod)
17029                 {
17030                   case 0:
17031                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17032                        SIB == 5, there is a 4 byte displacement.  */
17033                     if (base != 5)
17034                       /* No displacement. */
17035                       break;
17036                     /* Fall through.  */
17037                   case 2:
17038                     /* 4 byte displacement.  */
17039                     bytes_before_imm += 4;
17040                     break;
17041                   case 1:
17042                     /* 1 byte displacement.  */
17043                     bytes_before_imm++;
17044                     break;
17045                 }
17046             }
17047         }
17048       else
17049         {
17050           /* 16 bit address mode */
17051           /* Don't increase bytes_before_imm when decoding the third source,
17052              it has already been incremented by OP_E_memory while decoding
17053              the second source operand.  */
17054           if (opnum == 0)
17055             {
17056               switch (modrm.mod)
17057                 {
17058                 case 0:
17059                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17060                   if (modrm.rm != 6)
17061                     /* No displacement. */
17062                     break;
17063                   /* Fall through.  */
17064                 case 2:
17065                   /* 2 byte displacement.  */
17066                   bytes_before_imm += 2;
17067                   break;
17068                 case 1:
17069                   /* 1 byte displacement: when decoding the third source,
17070                      don't increase bytes_before_imm as this has already
17071                      been incremented by one in OP_E_memory while decoding
17072                      the second source operand.  */
17073                   if (opnum == 0)
17074                     bytes_before_imm++;
17075
17076                   break;
17077                 }
17078             }
17079         }
17080     }
17081
17082   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17083   return codep [bytes_before_imm];
17084 }
17085
17086 static void
17087 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17088 {
17089   const char **names;
17090
17091   if (reg == -1 && modrm.mod != 3)
17092     {
17093       OP_E_memory (bytemode, sizeflag);
17094       return;
17095     }
17096   else
17097     {
17098       if (reg == -1)
17099         {
17100           reg = modrm.rm;
17101           USED_REX (REX_B);
17102           if (rex & REX_B)
17103             reg += 8;
17104         }
17105       else if (reg > 7 && address_mode != mode_64bit)
17106         BadOp ();
17107     }
17108
17109   switch (vex.length)
17110     {
17111     case 128:
17112       names = names_xmm;
17113       break;
17114     case 256:
17115       names = names_ymm;
17116       break;
17117     default:
17118       abort ();
17119     }
17120   oappend (names[reg]);
17121 }
17122
17123 static void
17124 OP_EX_VexImmW (int bytemode, int sizeflag)
17125 {
17126   int reg = -1;
17127   static unsigned char vex_imm8;
17128
17129   if (vex_w_done == 0)
17130     {
17131       vex_w_done = 1;
17132
17133       /* Skip mod/rm byte.  */
17134       MODRM_CHECK;
17135       codep++;
17136
17137       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17138
17139       if (vex.w)
17140           reg = vex_imm8 >> 4;
17141
17142       OP_EX_VexReg (bytemode, sizeflag, reg);
17143     }
17144   else if (vex_w_done == 1)
17145     {
17146       vex_w_done = 2;
17147
17148       if (!vex.w)
17149           reg = vex_imm8 >> 4;
17150
17151       OP_EX_VexReg (bytemode, sizeflag, reg);
17152     }
17153   else
17154     {
17155       /* Output the imm8 directly.  */
17156       scratchbuf[0] = '$';
17157       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17158       oappend_maybe_intel (scratchbuf);
17159       scratchbuf[0] = '\0';
17160       codep++;
17161     }
17162 }
17163
17164 static void
17165 OP_Vex_2src (int bytemode, int sizeflag)
17166 {
17167   if (modrm.mod == 3)
17168     {
17169       int reg = modrm.rm;
17170       USED_REX (REX_B);
17171       if (rex & REX_B)
17172         reg += 8;
17173       oappend (names_xmm[reg]);
17174     }
17175   else
17176     {
17177       if (intel_syntax
17178           && (bytemode == v_mode || bytemode == v_swap_mode))
17179         {
17180           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17181           used_prefixes |= (prefixes & PREFIX_DATA);
17182         }
17183       OP_E (bytemode, sizeflag);
17184     }
17185 }
17186
17187 static void
17188 OP_Vex_2src_1 (int bytemode, int sizeflag)
17189 {
17190   if (modrm.mod == 3)
17191     {
17192       /* Skip mod/rm byte.   */
17193       MODRM_CHECK;
17194       codep++;
17195     }
17196
17197   if (vex.w)
17198     oappend (names_xmm[vex.register_specifier]);
17199   else
17200     OP_Vex_2src (bytemode, sizeflag);
17201 }
17202
17203 static void
17204 OP_Vex_2src_2 (int bytemode, int sizeflag)
17205 {
17206   if (vex.w)
17207     OP_Vex_2src (bytemode, sizeflag);
17208   else
17209     oappend (names_xmm[vex.register_specifier]);
17210 }
17211
17212 static void
17213 OP_EX_VexW (int bytemode, int sizeflag)
17214 {
17215   int reg = -1;
17216
17217   if (!vex_w_done)
17218     {
17219       vex_w_done = 1;
17220
17221       /* Skip mod/rm byte.  */
17222       MODRM_CHECK;
17223       codep++;
17224
17225       if (vex.w)
17226         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17227     }
17228   else
17229     {
17230       if (!vex.w)
17231         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17232     }
17233
17234   OP_EX_VexReg (bytemode, sizeflag, reg);
17235 }
17236
17237 static void
17238 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17239              int sizeflag ATTRIBUTE_UNUSED)
17240 {
17241   /* Skip the immediate byte and check for invalid bits.  */
17242   FETCH_DATA (the_info, codep + 1);
17243   if (*codep++ & 0xf)
17244     BadOp ();
17245 }
17246
17247 static void
17248 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17249 {
17250   int reg;
17251   const char **names;
17252
17253   FETCH_DATA (the_info, codep + 1);
17254   reg = *codep++;
17255
17256   if (bytemode != x_mode)
17257     abort ();
17258
17259   if (reg & 0xf)
17260       BadOp ();
17261
17262   reg >>= 4;
17263   if (reg > 7 && address_mode != mode_64bit)
17264     BadOp ();
17265
17266   switch (vex.length)
17267     {
17268     case 128:
17269       names = names_xmm;
17270       break;
17271     case 256:
17272       names = names_ymm;
17273       break;
17274     default:
17275       abort ();
17276     }
17277   oappend (names[reg]);
17278 }
17279
17280 static void
17281 OP_XMM_VexW (int bytemode, int sizeflag)
17282 {
17283   /* Turn off the REX.W bit since it is used for swapping operands
17284      now.  */
17285   rex &= ~REX_W;
17286   OP_XMM (bytemode, sizeflag);
17287 }
17288
17289 static void
17290 OP_EX_Vex (int bytemode, int sizeflag)
17291 {
17292   if (modrm.mod != 3)
17293     {
17294       if (vex.register_specifier != 0)
17295         BadOp ();
17296       need_vex_reg = 0;
17297     }
17298   OP_EX (bytemode, sizeflag);
17299 }
17300
17301 static void
17302 OP_XMM_Vex (int bytemode, int sizeflag)
17303 {
17304   if (modrm.mod != 3)
17305     {
17306       if (vex.register_specifier != 0)
17307         BadOp ();
17308       need_vex_reg = 0;
17309     }
17310   OP_XMM (bytemode, sizeflag);
17311 }
17312
17313 static void
17314 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17315 {
17316   switch (vex.length)
17317     {
17318     case 128:
17319       mnemonicendp = stpcpy (obuf, "vzeroupper");
17320       break;
17321     case 256:
17322       mnemonicendp = stpcpy (obuf, "vzeroall");
17323       break;
17324     default:
17325       abort ();
17326     }
17327 }
17328
17329 static struct op vex_cmp_op[] =
17330 {
17331   { STRING_COMMA_LEN ("eq") },
17332   { STRING_COMMA_LEN ("lt") },
17333   { STRING_COMMA_LEN ("le") },
17334   { STRING_COMMA_LEN ("unord") },
17335   { STRING_COMMA_LEN ("neq") },
17336   { STRING_COMMA_LEN ("nlt") },
17337   { STRING_COMMA_LEN ("nle") },
17338   { STRING_COMMA_LEN ("ord") },
17339   { STRING_COMMA_LEN ("eq_uq") },
17340   { STRING_COMMA_LEN ("nge") },
17341   { STRING_COMMA_LEN ("ngt") },
17342   { STRING_COMMA_LEN ("false") },
17343   { STRING_COMMA_LEN ("neq_oq") },
17344   { STRING_COMMA_LEN ("ge") },
17345   { STRING_COMMA_LEN ("gt") },
17346   { STRING_COMMA_LEN ("true") },
17347   { STRING_COMMA_LEN ("eq_os") },
17348   { STRING_COMMA_LEN ("lt_oq") },
17349   { STRING_COMMA_LEN ("le_oq") },
17350   { STRING_COMMA_LEN ("unord_s") },
17351   { STRING_COMMA_LEN ("neq_us") },
17352   { STRING_COMMA_LEN ("nlt_uq") },
17353   { STRING_COMMA_LEN ("nle_uq") },
17354   { STRING_COMMA_LEN ("ord_s") },
17355   { STRING_COMMA_LEN ("eq_us") },
17356   { STRING_COMMA_LEN ("nge_uq") },
17357   { STRING_COMMA_LEN ("ngt_uq") },
17358   { STRING_COMMA_LEN ("false_os") },
17359   { STRING_COMMA_LEN ("neq_os") },
17360   { STRING_COMMA_LEN ("ge_oq") },
17361   { STRING_COMMA_LEN ("gt_oq") },
17362   { STRING_COMMA_LEN ("true_us") },
17363 };
17364
17365 static void
17366 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17367 {
17368   unsigned int cmp_type;
17369
17370   FETCH_DATA (the_info, codep + 1);
17371   cmp_type = *codep++ & 0xff;
17372   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17373     {
17374       char suffix [3];
17375       char *p = mnemonicendp - 2;
17376       suffix[0] = p[0];
17377       suffix[1] = p[1];
17378       suffix[2] = '\0';
17379       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17380       mnemonicendp += vex_cmp_op[cmp_type].len;
17381     }
17382   else
17383     {
17384       /* We have a reserved extension byte.  Output it directly.  */
17385       scratchbuf[0] = '$';
17386       print_operand_value (scratchbuf + 1, 1, cmp_type);
17387       oappend_maybe_intel (scratchbuf);
17388       scratchbuf[0] = '\0';
17389     }
17390 }
17391
17392 static void
17393 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17394              int sizeflag ATTRIBUTE_UNUSED)
17395 {
17396   unsigned int cmp_type;
17397
17398   if (!vex.evex)
17399     abort ();
17400
17401   FETCH_DATA (the_info, codep + 1);
17402   cmp_type = *codep++ & 0xff;
17403   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17404      If it's the case, print suffix, otherwise - print the immediate.  */
17405   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17406       && cmp_type != 3
17407       && cmp_type != 7)
17408     {
17409       char suffix [3];
17410       char *p = mnemonicendp - 2;
17411
17412       /* vpcmp* can have both one- and two-lettered suffix.  */
17413       if (p[0] == 'p')
17414         {
17415           p++;
17416           suffix[0] = p[0];
17417           suffix[1] = '\0';
17418         }
17419       else
17420         {
17421           suffix[0] = p[0];
17422           suffix[1] = p[1];
17423           suffix[2] = '\0';
17424         }
17425
17426       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17427       mnemonicendp += simd_cmp_op[cmp_type].len;
17428     }
17429   else
17430     {
17431       /* We have a reserved extension byte.  Output it directly.  */
17432       scratchbuf[0] = '$';
17433       print_operand_value (scratchbuf + 1, 1, cmp_type);
17434       oappend_maybe_intel (scratchbuf);
17435       scratchbuf[0] = '\0';
17436     }
17437 }
17438
17439 static const struct op pclmul_op[] =
17440 {
17441   { STRING_COMMA_LEN ("lql") },
17442   { STRING_COMMA_LEN ("hql") },
17443   { STRING_COMMA_LEN ("lqh") },
17444   { STRING_COMMA_LEN ("hqh") }
17445 };
17446
17447 static void
17448 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17449               int sizeflag ATTRIBUTE_UNUSED)
17450 {
17451   unsigned int pclmul_type;
17452
17453   FETCH_DATA (the_info, codep + 1);
17454   pclmul_type = *codep++ & 0xff;
17455   switch (pclmul_type)
17456     {
17457     case 0x10:
17458       pclmul_type = 2;
17459       break;
17460     case 0x11:
17461       pclmul_type = 3;
17462       break;
17463     default:
17464       break;
17465     }
17466   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17467     {
17468       char suffix [4];
17469       char *p = mnemonicendp - 3;
17470       suffix[0] = p[0];
17471       suffix[1] = p[1];
17472       suffix[2] = p[2];
17473       suffix[3] = '\0';
17474       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17475       mnemonicendp += pclmul_op[pclmul_type].len;
17476     }
17477   else
17478     {
17479       /* We have a reserved extension byte.  Output it directly.  */
17480       scratchbuf[0] = '$';
17481       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17482       oappend_maybe_intel (scratchbuf);
17483       scratchbuf[0] = '\0';
17484     }
17485 }
17486
17487 static void
17488 MOVBE_Fixup (int bytemode, int sizeflag)
17489 {
17490   /* Add proper suffix to "movbe".  */
17491   char *p = mnemonicendp;
17492
17493   switch (bytemode)
17494     {
17495     case v_mode:
17496       if (intel_syntax)
17497         goto skip;
17498
17499       USED_REX (REX_W);
17500       if (sizeflag & SUFFIX_ALWAYS)
17501         {
17502           if (rex & REX_W)
17503             *p++ = 'q';
17504           else
17505             {
17506               if (sizeflag & DFLAG)
17507                 *p++ = 'l';
17508               else
17509                 *p++ = 'w';
17510               used_prefixes |= (prefixes & PREFIX_DATA);
17511             }
17512         }
17513       break;
17514     default:
17515       oappend (INTERNAL_DISASSEMBLER_ERROR);
17516       break;
17517     }
17518   mnemonicendp = p;
17519   *p = '\0';
17520
17521 skip:
17522   OP_M (bytemode, sizeflag);
17523 }
17524
17525 static void
17526 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17527 {
17528   int reg;
17529   const char **names;
17530
17531   /* Skip mod/rm byte.  */
17532   MODRM_CHECK;
17533   codep++;
17534
17535   if (vex.w)
17536     names = names64;
17537   else
17538     names = names32;
17539
17540   reg = modrm.rm;
17541   USED_REX (REX_B);
17542   if (rex & REX_B)
17543     reg += 8;
17544
17545   oappend (names[reg]);
17546 }
17547
17548 static void
17549 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17550 {
17551   const char **names;
17552
17553   if (vex.w)
17554     names = names64;
17555   else
17556     names = names32;
17557
17558   oappend (names[vex.register_specifier]);
17559 }
17560
17561 static void
17562 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17563 {
17564   if (!vex.evex
17565       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17566     abort ();
17567
17568   USED_REX (REX_R);
17569   if ((rex & REX_R) != 0 || !vex.r)
17570     {
17571       BadOp ();
17572       return;
17573     }
17574
17575   oappend (names_mask [modrm.reg]);
17576 }
17577
17578 static void
17579 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17580 {
17581   if (!vex.evex
17582       || (bytemode != evex_rounding_mode
17583           && bytemode != evex_sae_mode))
17584     abort ();
17585   if (modrm.mod == 3 && vex.b)
17586     switch (bytemode)
17587       {
17588       case evex_rounding_mode:
17589         oappend (names_rounding[vex.ll]);
17590         break;
17591       case evex_sae_mode:
17592         oappend ("{sae}");
17593         break;
17594       default:
17595         break;
17596       }
17597 }