1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void NOP_Fixup1 (int, int);
105 static void NOP_Fixup2 (int, int);
106 static void OP_3DNowSuffix (int, int);
107 static void CMP_Fixup (int, int);
108 static void BadOp (void);
109 static void REP_Fixup (int, int);
110 static void BND_Fixup (int, int);
111 static void NOTRACK_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void PCMPESTR_Fixup (int, int);
120 static void OP_LWPCB_E (int, int);
121 static void OP_LWP_E (int, int);
122 static void OP_Vex_2src_1 (int, int);
123 static void OP_Vex_2src_2 (int, int);
125 static void MOVBE_Fixup (int, int);
127 static void OP_Mask (int, int);
130 /* Points to first byte not fetched. */
131 bfd_byte
*max_fetched
;
132 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
135 OPCODES_SIGJMP_BUF bailout
;
145 enum address_mode address_mode
;
147 /* Flags for the prefixes for the current instruction. See below. */
150 /* REX prefix the current instruction. See below. */
152 /* Bits of REX we've already used. */
154 /* REX bits in original REX prefix ignored. */
155 static int rex_ignored
;
156 /* Mark parts used in the REX prefix. When we are testing for
157 empty prefix (for 8bit register REX extension), just mask it
158 out. Otherwise test for REX bit is excuse for existence of REX
159 only in case value is nonzero. */
160 #define USED_REX(value) \
165 rex_used |= (value) | REX_OPCODE; \
168 rex_used |= REX_OPCODE; \
171 /* Flags for prefixes which we somehow handled when printing the
172 current instruction. */
173 static int used_prefixes
;
175 /* Flags stored in PREFIXES. */
176 #define PREFIX_REPZ 1
177 #define PREFIX_REPNZ 2
178 #define PREFIX_LOCK 4
180 #define PREFIX_SS 0x10
181 #define PREFIX_DS 0x20
182 #define PREFIX_ES 0x40
183 #define PREFIX_FS 0x80
184 #define PREFIX_GS 0x100
185 #define PREFIX_DATA 0x200
186 #define PREFIX_ADDR 0x400
187 #define PREFIX_FWAIT 0x800
189 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
190 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
192 #define FETCH_DATA(info, addr) \
193 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
194 ? 1 : fetch_data ((info), (addr)))
197 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
200 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
201 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
203 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
204 status
= (*info
->read_memory_func
) (start
,
206 addr
- priv
->max_fetched
,
212 /* If we did manage to read at least one byte, then
213 print_insn_i386 will do something sensible. Otherwise, print
214 an error. We do that here because this is where we know
216 if (priv
->max_fetched
== priv
->the_buffer
)
217 (*info
->memory_error_func
) (status
, start
, info
);
218 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
221 priv
->max_fetched
= addr
;
225 /* Possible values for prefix requirement. */
226 #define PREFIX_IGNORED_SHIFT 16
227 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
228 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
233 /* Opcode prefixes. */
234 #define PREFIX_OPCODE (PREFIX_REPZ \
238 /* Prefixes ignored. */
239 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
240 | PREFIX_IGNORED_REPNZ \
241 | PREFIX_IGNORED_DATA)
243 #define XX { NULL, 0 }
244 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
246 #define Eb { OP_E, b_mode }
247 #define Ebnd { OP_E, bnd_mode }
248 #define EbS { OP_E, b_swap_mode }
249 #define EbndS { OP_E, bnd_swap_mode }
250 #define Ev { OP_E, v_mode }
251 #define Eva { OP_E, va_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mv_bnd { OP_M, v_bndmk_mode }
275 #define Mx { OP_M, x_mode }
276 #define Mxmm { OP_M, xmm_mode }
277 #define Gb { OP_G, b_mode }
278 #define Gbnd { OP_G, bnd_mode }
279 #define Gv { OP_G, v_mode }
280 #define Gd { OP_G, d_mode }
281 #define Gdq { OP_G, dq_mode }
282 #define Gm { OP_G, m_mode }
283 #define Gva { OP_G, va_mode }
284 #define Gw { OP_G, w_mode }
285 #define Rd { OP_R, d_mode }
286 #define Rdq { OP_R, dq_mode }
287 #define Rm { OP_R, m_mode }
288 #define Ib { OP_I, b_mode }
289 #define sIb { OP_sI, b_mode } /* sign extened byte */
290 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
291 #define Iv { OP_I, v_mode }
292 #define sIv { OP_sI, v_mode }
293 #define Iv64 { OP_I64, v_mode }
294 #define Id { OP_I, d_mode }
295 #define Iw { OP_I, w_mode }
296 #define I1 { OP_I, const_1_mode }
297 #define Jb { OP_J, b_mode }
298 #define Jv { OP_J, v_mode }
299 #define Cm { OP_C, m_mode }
300 #define Dm { OP_D, m_mode }
301 #define Td { OP_T, d_mode }
302 #define Skip_MODRM { OP_Skip_MODRM, 0 }
304 #define RMeAX { OP_REG, eAX_reg }
305 #define RMeBX { OP_REG, eBX_reg }
306 #define RMeCX { OP_REG, eCX_reg }
307 #define RMeDX { OP_REG, eDX_reg }
308 #define RMeSP { OP_REG, eSP_reg }
309 #define RMeBP { OP_REG, eBP_reg }
310 #define RMeSI { OP_REG, eSI_reg }
311 #define RMeDI { OP_REG, eDI_reg }
312 #define RMrAX { OP_REG, rAX_reg }
313 #define RMrBX { OP_REG, rBX_reg }
314 #define RMrCX { OP_REG, rCX_reg }
315 #define RMrDX { OP_REG, rDX_reg }
316 #define RMrSP { OP_REG, rSP_reg }
317 #define RMrBP { OP_REG, rBP_reg }
318 #define RMrSI { OP_REG, rSI_reg }
319 #define RMrDI { OP_REG, rDI_reg }
320 #define RMAL { OP_REG, al_reg }
321 #define RMCL { OP_REG, cl_reg }
322 #define RMDL { OP_REG, dl_reg }
323 #define RMBL { OP_REG, bl_reg }
324 #define RMAH { OP_REG, ah_reg }
325 #define RMCH { OP_REG, ch_reg }
326 #define RMDH { OP_REG, dh_reg }
327 #define RMBH { OP_REG, bh_reg }
328 #define RMAX { OP_REG, ax_reg }
329 #define RMDX { OP_REG, dx_reg }
331 #define eAX { OP_IMREG, eAX_reg }
332 #define eBX { OP_IMREG, eBX_reg }
333 #define eCX { OP_IMREG, eCX_reg }
334 #define eDX { OP_IMREG, eDX_reg }
335 #define eSP { OP_IMREG, eSP_reg }
336 #define eBP { OP_IMREG, eBP_reg }
337 #define eSI { OP_IMREG, eSI_reg }
338 #define eDI { OP_IMREG, eDI_reg }
339 #define AL { OP_IMREG, al_reg }
340 #define CL { OP_IMREG, cl_reg }
341 #define DL { OP_IMREG, dl_reg }
342 #define BL { OP_IMREG, bl_reg }
343 #define AH { OP_IMREG, ah_reg }
344 #define CH { OP_IMREG, ch_reg }
345 #define DH { OP_IMREG, dh_reg }
346 #define BH { OP_IMREG, bh_reg }
347 #define AX { OP_IMREG, ax_reg }
348 #define DX { OP_IMREG, dx_reg }
349 #define zAX { OP_IMREG, z_mode_ax_reg }
350 #define indirDX { OP_IMREG, indir_dx_reg }
352 #define Sw { OP_SEG, w_mode }
353 #define Sv { OP_SEG, v_mode }
354 #define Ap { OP_DIR, 0 }
355 #define Ob { OP_OFF64, b_mode }
356 #define Ov { OP_OFF64, v_mode }
357 #define Xb { OP_DSreg, eSI_reg }
358 #define Xv { OP_DSreg, eSI_reg }
359 #define Xz { OP_DSreg, eSI_reg }
360 #define Yb { OP_ESreg, eDI_reg }
361 #define Yv { OP_ESreg, eDI_reg }
362 #define DSBX { OP_DSreg, eBX_reg }
364 #define es { OP_REG, es_reg }
365 #define ss { OP_REG, ss_reg }
366 #define cs { OP_REG, cs_reg }
367 #define ds { OP_REG, ds_reg }
368 #define fs { OP_REG, fs_reg }
369 #define gs { OP_REG, gs_reg }
371 #define MX { OP_MMX, 0 }
372 #define XM { OP_XMM, 0 }
373 #define XMScalar { OP_XMM, scalar_mode }
374 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
375 #define XMM { OP_XMM, xmm_mode }
376 #define XMxmmq { OP_XMM, xmmq_mode }
377 #define EM { OP_EM, v_mode }
378 #define EMS { OP_EM, v_swap_mode }
379 #define EMd { OP_EM, d_mode }
380 #define EMx { OP_EM, x_mode }
381 #define EXbScalar { OP_EX, b_scalar_mode }
382 #define EXw { OP_EX, w_mode }
383 #define EXwScalar { OP_EX, w_scalar_mode }
384 #define EXd { OP_EX, d_mode }
385 #define EXdScalar { OP_EX, d_scalar_mode }
386 #define EXdS { OP_EX, d_swap_mode }
387 #define EXq { OP_EX, q_mode }
388 #define EXqScalar { OP_EX, q_scalar_mode }
389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
390 #define EXqS { OP_EX, q_swap_mode }
391 #define EXx { OP_EX, x_mode }
392 #define EXxS { OP_EX, x_swap_mode }
393 #define EXxmm { OP_EX, xmm_mode }
394 #define EXymm { OP_EX, ymm_mode }
395 #define EXxmmq { OP_EX, xmmq_mode }
396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
399 #define EXxmm_md { OP_EX, xmm_md_mode }
400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
402 #define EXxmmdw { OP_EX, xmmdw_mode }
403 #define EXxmmqd { OP_EX, xmmqd_mode }
404 #define EXymmq { OP_EX, ymmq_mode }
405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
409 #define MS { OP_MS, v_mode }
410 #define XS { OP_XS, v_mode }
411 #define EMCq { OP_EMC, q_mode }
412 #define MXC { OP_MXC, 0 }
413 #define OPSUF { OP_3DNowSuffix, 0 }
414 #define CMP { CMP_Fixup, 0 }
415 #define XMM0 { XMM_Fixup, 0 }
416 #define FXSAVE { FXSAVE_Fixup, 0 }
417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
420 #define Vex { OP_VEX, vex_mode }
421 #define VexScalar { OP_VEX, vex_scalar_mode }
422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
423 #define Vex128 { OP_VEX, vex128_mode }
424 #define Vex256 { OP_VEX, vex256_mode }
425 #define VexGdq { OP_VEX, dq_mode }
426 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
427 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
428 #define EXVexW { OP_EX_VexW, x_mode }
429 #define EXdVexW { OP_EX_VexW, d_mode }
430 #define EXqVexW { OP_EX_VexW, q_mode }
431 #define EXVexImmW { OP_EX_VexImmW, x_mode }
432 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
433 #define XMVexW { OP_XMM_VexW, 0 }
434 #define XMVexI4 { OP_REG_VexI4, x_mode }
435 #define PCLMUL { PCLMUL_Fixup, 0 }
436 #define VCMP { VCMP_Fixup, 0 }
437 #define VPCMP { VPCMP_Fixup, 0 }
438 #define VPCOM { VPCOM_Fixup, 0 }
440 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
441 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
442 #define EXxEVexS { OP_Rounding, evex_sae_mode }
444 #define XMask { OP_Mask, mask_mode }
445 #define MaskG { OP_G, mask_mode }
446 #define MaskE { OP_E, mask_mode }
447 #define MaskBDE { OP_E, mask_bd_mode }
448 #define MaskR { OP_R, mask_mode }
449 #define MaskVex { OP_VEX, mask_mode }
451 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
452 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
453 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
454 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
456 /* Used handle "rep" prefix for string instructions. */
457 #define Xbr { REP_Fixup, eSI_reg }
458 #define Xvr { REP_Fixup, eSI_reg }
459 #define Ybr { REP_Fixup, eDI_reg }
460 #define Yvr { REP_Fixup, eDI_reg }
461 #define Yzr { REP_Fixup, eDI_reg }
462 #define indirDXr { REP_Fixup, indir_dx_reg }
463 #define ALr { REP_Fixup, al_reg }
464 #define eAXr { REP_Fixup, eAX_reg }
466 /* Used handle HLE prefix for lockable instructions. */
467 #define Ebh1 { HLE_Fixup1, b_mode }
468 #define Evh1 { HLE_Fixup1, v_mode }
469 #define Ebh2 { HLE_Fixup2, b_mode }
470 #define Evh2 { HLE_Fixup2, v_mode }
471 #define Ebh3 { HLE_Fixup3, b_mode }
472 #define Evh3 { HLE_Fixup3, v_mode }
474 #define BND { BND_Fixup, 0 }
475 #define NOTRACK { NOTRACK_Fixup, 0 }
477 #define cond_jump_flag { NULL, cond_jump_mode }
478 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
480 /* bits in sizeflag */
481 #define SUFFIX_ALWAYS 4
489 /* byte operand with operand swapped */
491 /* byte operand, sign extend like 'T' suffix */
493 /* operand size depends on prefixes */
495 /* operand size depends on prefixes with operand swapped */
497 /* operand size depends on address prefix */
501 /* double word operand */
503 /* double word operand with operand swapped */
505 /* quad word operand */
507 /* quad word operand with operand swapped */
509 /* ten-byte operand */
511 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
512 broadcast enabled. */
514 /* Similar to x_mode, but with different EVEX mem shifts. */
516 /* Similar to x_mode, but with disabled broadcast. */
518 /* Similar to x_mode, but with operands swapped and disabled broadcast
521 /* 16-byte XMM operand */
523 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
524 memory operand (depending on vector length). Broadcast isn't
527 /* Same as xmmq_mode, but broadcast is allowed. */
528 evex_half_bcst_xmmq_mode
,
529 /* XMM register or byte memory operand */
531 /* XMM register or word memory operand */
533 /* XMM register or double word memory operand */
535 /* XMM register or quad word memory operand */
537 /* XMM register or double/quad word memory operand, depending on
540 /* 16-byte XMM, word, double word or quad word operand. */
542 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
544 /* 32-byte YMM operand */
546 /* quad word, ymmword or zmmword memory operand. */
548 /* 32-byte YMM or 16-byte word operand */
550 /* d_mode in 32bit, q_mode in 64bit mode. */
552 /* pair of v_mode operands */
557 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode. */
565 /* bounds operand with operand swapped */
567 /* 4- or 6-byte pointer operand */
570 /* v_mode for indirect branch opcodes. */
572 /* v_mode for stack-related opcodes. */
574 /* non-quad operand size depends on prefixes */
576 /* 16-byte operand */
578 /* registers like dq_mode, memory like b_mode. */
580 /* registers like d_mode, memory like b_mode. */
582 /* registers like d_mode, memory like w_mode. */
584 /* registers like dq_mode, memory like d_mode. */
586 /* normal vex mode */
588 /* 128bit vex mode */
590 /* 256bit vex mode */
592 /* operand size depends on the VEX.W bit. */
595 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
596 vex_vsib_d_w_dq_mode
,
597 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
599 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
600 vex_vsib_q_w_dq_mode
,
601 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
604 /* scalar, ignore vector length. */
606 /* like b_mode, ignore vector length. */
608 /* like w_mode, ignore vector length. */
610 /* like d_mode, ignore vector length. */
612 /* like d_swap_mode, ignore vector length. */
614 /* like q_mode, ignore vector length. */
616 /* like q_swap_mode, ignore vector length. */
618 /* like vex_mode, ignore vector length. */
620 /* like vex_w_dq_mode, ignore vector length. */
621 vex_scalar_w_dq_mode
,
623 /* Static rounding. */
625 /* Static rounding, 64-bit mode only. */
626 evex_rounding_64_mode
,
627 /* Supress all exceptions. */
630 /* Mask register operand. */
632 /* Mask register operand. */
700 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
702 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
703 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
704 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
705 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
706 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
707 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
708 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
709 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
710 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
711 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
712 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
713 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
714 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
715 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
716 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
717 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
845 MOD_VEX_0F12_PREFIX_0
,
847 MOD_VEX_0F16_PREFIX_0
,
850 MOD_VEX_W_0_0F41_P_0_LEN_1
,
851 MOD_VEX_W_1_0F41_P_0_LEN_1
,
852 MOD_VEX_W_0_0F41_P_2_LEN_1
,
853 MOD_VEX_W_1_0F41_P_2_LEN_1
,
854 MOD_VEX_W_0_0F42_P_0_LEN_1
,
855 MOD_VEX_W_1_0F42_P_0_LEN_1
,
856 MOD_VEX_W_0_0F42_P_2_LEN_1
,
857 MOD_VEX_W_1_0F42_P_2_LEN_1
,
858 MOD_VEX_W_0_0F44_P_0_LEN_1
,
859 MOD_VEX_W_1_0F44_P_0_LEN_1
,
860 MOD_VEX_W_0_0F44_P_2_LEN_1
,
861 MOD_VEX_W_1_0F44_P_2_LEN_1
,
862 MOD_VEX_W_0_0F45_P_0_LEN_1
,
863 MOD_VEX_W_1_0F45_P_0_LEN_1
,
864 MOD_VEX_W_0_0F45_P_2_LEN_1
,
865 MOD_VEX_W_1_0F45_P_2_LEN_1
,
866 MOD_VEX_W_0_0F46_P_0_LEN_1
,
867 MOD_VEX_W_1_0F46_P_0_LEN_1
,
868 MOD_VEX_W_0_0F46_P_2_LEN_1
,
869 MOD_VEX_W_1_0F46_P_2_LEN_1
,
870 MOD_VEX_W_0_0F47_P_0_LEN_1
,
871 MOD_VEX_W_1_0F47_P_0_LEN_1
,
872 MOD_VEX_W_0_0F47_P_2_LEN_1
,
873 MOD_VEX_W_1_0F47_P_2_LEN_1
,
874 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
875 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
876 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
877 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
878 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
879 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
880 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
892 MOD_VEX_W_0_0F91_P_0_LEN_0
,
893 MOD_VEX_W_1_0F91_P_0_LEN_0
,
894 MOD_VEX_W_0_0F91_P_2_LEN_0
,
895 MOD_VEX_W_1_0F91_P_2_LEN_0
,
896 MOD_VEX_W_0_0F92_P_0_LEN_0
,
897 MOD_VEX_W_0_0F92_P_2_LEN_0
,
898 MOD_VEX_0F92_P_3_LEN_0
,
899 MOD_VEX_W_0_0F93_P_0_LEN_0
,
900 MOD_VEX_W_0_0F93_P_2_LEN_0
,
901 MOD_VEX_0F93_P_3_LEN_0
,
902 MOD_VEX_W_0_0F98_P_0_LEN_0
,
903 MOD_VEX_W_1_0F98_P_0_LEN_0
,
904 MOD_VEX_W_0_0F98_P_2_LEN_0
,
905 MOD_VEX_W_1_0F98_P_2_LEN_0
,
906 MOD_VEX_W_0_0F99_P_0_LEN_0
,
907 MOD_VEX_W_1_0F99_P_0_LEN_0
,
908 MOD_VEX_W_0_0F99_P_2_LEN_0
,
909 MOD_VEX_W_1_0F99_P_2_LEN_0
,
912 MOD_VEX_0FD7_PREFIX_2
,
913 MOD_VEX_0FE7_PREFIX_2
,
914 MOD_VEX_0FF0_PREFIX_3
,
915 MOD_VEX_0F381A_PREFIX_2
,
916 MOD_VEX_0F382A_PREFIX_2
,
917 MOD_VEX_0F382C_PREFIX_2
,
918 MOD_VEX_0F382D_PREFIX_2
,
919 MOD_VEX_0F382E_PREFIX_2
,
920 MOD_VEX_0F382F_PREFIX_2
,
921 MOD_VEX_0F385A_PREFIX_2
,
922 MOD_VEX_0F388C_PREFIX_2
,
923 MOD_VEX_0F388E_PREFIX_2
,
924 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
925 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
926 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
927 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
928 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
929 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
930 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
931 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
933 MOD_EVEX_0F12_PREFIX_0
,
934 MOD_EVEX_0F16_PREFIX_0
,
935 MOD_EVEX_0F38C6_REG_1
,
936 MOD_EVEX_0F38C6_REG_2
,
937 MOD_EVEX_0F38C6_REG_5
,
938 MOD_EVEX_0F38C6_REG_6
,
939 MOD_EVEX_0F38C7_REG_1
,
940 MOD_EVEX_0F38C7_REG_2
,
941 MOD_EVEX_0F38C7_REG_5
,
942 MOD_EVEX_0F38C7_REG_6
955 RM_0F1E_P_1_MOD_3_REG_7
,
956 RM_0FAE_REG_6_MOD_3_P_0
,
963 PREFIX_0F01_REG_5_MOD_0
,
964 PREFIX_0F01_REG_5_MOD_3_RM_0
,
965 PREFIX_0F01_REG_5_MOD_3_RM_2
,
966 PREFIX_0F01_REG_7_MOD_3_RM_2
,
967 PREFIX_0F01_REG_7_MOD_3_RM_3
,
1009 PREFIX_0FAE_REG_0_MOD_3
,
1010 PREFIX_0FAE_REG_1_MOD_3
,
1011 PREFIX_0FAE_REG_2_MOD_3
,
1012 PREFIX_0FAE_REG_3_MOD_3
,
1013 PREFIX_0FAE_REG_4_MOD_0
,
1014 PREFIX_0FAE_REG_4_MOD_3
,
1015 PREFIX_0FAE_REG_5_MOD_0
,
1016 PREFIX_0FAE_REG_5_MOD_3
,
1017 PREFIX_0FAE_REG_6_MOD_0
,
1018 PREFIX_0FAE_REG_6_MOD_3
,
1019 PREFIX_0FAE_REG_7_MOD_0
,
1025 PREFIX_0FC7_REG_6_MOD_0
,
1026 PREFIX_0FC7_REG_6_MOD_3
,
1027 PREFIX_0FC7_REG_7_MOD_3
,
1157 PREFIX_VEX_0F71_REG_2
,
1158 PREFIX_VEX_0F71_REG_4
,
1159 PREFIX_VEX_0F71_REG_6
,
1160 PREFIX_VEX_0F72_REG_2
,
1161 PREFIX_VEX_0F72_REG_4
,
1162 PREFIX_VEX_0F72_REG_6
,
1163 PREFIX_VEX_0F73_REG_2
,
1164 PREFIX_VEX_0F73_REG_3
,
1165 PREFIX_VEX_0F73_REG_6
,
1166 PREFIX_VEX_0F73_REG_7
,
1339 PREFIX_VEX_0F38F3_REG_1
,
1340 PREFIX_VEX_0F38F3_REG_2
,
1341 PREFIX_VEX_0F38F3_REG_3
,
1460 PREFIX_EVEX_0F71_REG_2
,
1461 PREFIX_EVEX_0F71_REG_4
,
1462 PREFIX_EVEX_0F71_REG_6
,
1463 PREFIX_EVEX_0F72_REG_0
,
1464 PREFIX_EVEX_0F72_REG_1
,
1465 PREFIX_EVEX_0F72_REG_2
,
1466 PREFIX_EVEX_0F72_REG_4
,
1467 PREFIX_EVEX_0F72_REG_6
,
1468 PREFIX_EVEX_0F73_REG_2
,
1469 PREFIX_EVEX_0F73_REG_3
,
1470 PREFIX_EVEX_0F73_REG_6
,
1471 PREFIX_EVEX_0F73_REG_7
,
1668 PREFIX_EVEX_0F38C6_REG_1
,
1669 PREFIX_EVEX_0F38C6_REG_2
,
1670 PREFIX_EVEX_0F38C6_REG_5
,
1671 PREFIX_EVEX_0F38C6_REG_6
,
1672 PREFIX_EVEX_0F38C7_REG_1
,
1673 PREFIX_EVEX_0F38C7_REG_2
,
1674 PREFIX_EVEX_0F38C7_REG_5
,
1675 PREFIX_EVEX_0F38C7_REG_6
,
1777 THREE_BYTE_0F38
= 0,
1804 VEX_LEN_0F12_P_0_M_0
= 0,
1805 VEX_LEN_0F12_P_0_M_1
,
1808 VEX_LEN_0F16_P_0_M_0
,
1809 VEX_LEN_0F16_P_0_M_1
,
1846 VEX_LEN_0FAE_R_2_M_0
,
1847 VEX_LEN_0FAE_R_3_M_0
,
1854 VEX_LEN_0F381A_P_2_M_0
,
1857 VEX_LEN_0F385A_P_2_M_0
,
1860 VEX_LEN_0F38F3_R_1_P_0
,
1861 VEX_LEN_0F38F3_R_2_P_0
,
1862 VEX_LEN_0F38F3_R_3_P_0
,
1905 VEX_LEN_0FXOP_08_CC
,
1906 VEX_LEN_0FXOP_08_CD
,
1907 VEX_LEN_0FXOP_08_CE
,
1908 VEX_LEN_0FXOP_08_CF
,
1909 VEX_LEN_0FXOP_08_EC
,
1910 VEX_LEN_0FXOP_08_ED
,
1911 VEX_LEN_0FXOP_08_EE
,
1912 VEX_LEN_0FXOP_08_EF
,
1913 VEX_LEN_0FXOP_09_80
,
1919 EVEX_LEN_0F6E_P_2
= 0,
1923 EVEX_LEN_0F3819_P_2_W_0
,
1924 EVEX_LEN_0F3819_P_2_W_1
,
1925 EVEX_LEN_0F381A_P_2_W_0
,
1926 EVEX_LEN_0F381A_P_2_W_1
,
1927 EVEX_LEN_0F381B_P_2_W_0
,
1928 EVEX_LEN_0F381B_P_2_W_1
,
1929 EVEX_LEN_0F385A_P_2_W_0
,
1930 EVEX_LEN_0F385A_P_2_W_1
,
1931 EVEX_LEN_0F385B_P_2_W_0
,
1932 EVEX_LEN_0F385B_P_2_W_1
,
1933 EVEX_LEN_0F38C6_REG_1_PREFIX_2
,
1934 EVEX_LEN_0F38C6_REG_2_PREFIX_2
,
1935 EVEX_LEN_0F38C6_REG_5_PREFIX_2
,
1936 EVEX_LEN_0F38C6_REG_6_PREFIX_2
,
1937 EVEX_LEN_0F38C7_R_1_P_2_W_0
,
1938 EVEX_LEN_0F38C7_R_1_P_2_W_1
,
1939 EVEX_LEN_0F38C7_R_2_P_2_W_0
,
1940 EVEX_LEN_0F38C7_R_2_P_2_W_1
,
1941 EVEX_LEN_0F38C7_R_5_P_2_W_0
,
1942 EVEX_LEN_0F38C7_R_5_P_2_W_1
,
1943 EVEX_LEN_0F38C7_R_6_P_2_W_0
,
1944 EVEX_LEN_0F38C7_R_6_P_2_W_1
,
1945 EVEX_LEN_0F3A18_P_2_W_0
,
1946 EVEX_LEN_0F3A18_P_2_W_1
,
1947 EVEX_LEN_0F3A19_P_2_W_0
,
1948 EVEX_LEN_0F3A19_P_2_W_1
,
1949 EVEX_LEN_0F3A1A_P_2_W_0
,
1950 EVEX_LEN_0F3A1A_P_2_W_1
,
1951 EVEX_LEN_0F3A1B_P_2_W_0
,
1952 EVEX_LEN_0F3A1B_P_2_W_1
,
1953 EVEX_LEN_0F3A23_P_2_W_0
,
1954 EVEX_LEN_0F3A23_P_2_W_1
,
1955 EVEX_LEN_0F3A38_P_2_W_0
,
1956 EVEX_LEN_0F3A38_P_2_W_1
,
1957 EVEX_LEN_0F3A39_P_2_W_0
,
1958 EVEX_LEN_0F3A39_P_2_W_1
,
1959 EVEX_LEN_0F3A3A_P_2_W_0
,
1960 EVEX_LEN_0F3A3A_P_2_W_1
,
1961 EVEX_LEN_0F3A3B_P_2_W_0
,
1962 EVEX_LEN_0F3A3B_P_2_W_1
,
1963 EVEX_LEN_0F3A43_P_2_W_0
,
1964 EVEX_LEN_0F3A43_P_2_W_1
1969 VEX_W_0F41_P_0_LEN_1
= 0,
1970 VEX_W_0F41_P_2_LEN_1
,
1971 VEX_W_0F42_P_0_LEN_1
,
1972 VEX_W_0F42_P_2_LEN_1
,
1973 VEX_W_0F44_P_0_LEN_0
,
1974 VEX_W_0F44_P_2_LEN_0
,
1975 VEX_W_0F45_P_0_LEN_1
,
1976 VEX_W_0F45_P_2_LEN_1
,
1977 VEX_W_0F46_P_0_LEN_1
,
1978 VEX_W_0F46_P_2_LEN_1
,
1979 VEX_W_0F47_P_0_LEN_1
,
1980 VEX_W_0F47_P_2_LEN_1
,
1981 VEX_W_0F4A_P_0_LEN_1
,
1982 VEX_W_0F4A_P_2_LEN_1
,
1983 VEX_W_0F4B_P_0_LEN_1
,
1984 VEX_W_0F4B_P_2_LEN_1
,
1985 VEX_W_0F90_P_0_LEN_0
,
1986 VEX_W_0F90_P_2_LEN_0
,
1987 VEX_W_0F91_P_0_LEN_0
,
1988 VEX_W_0F91_P_2_LEN_0
,
1989 VEX_W_0F92_P_0_LEN_0
,
1990 VEX_W_0F92_P_2_LEN_0
,
1991 VEX_W_0F93_P_0_LEN_0
,
1992 VEX_W_0F93_P_2_LEN_0
,
1993 VEX_W_0F98_P_0_LEN_0
,
1994 VEX_W_0F98_P_2_LEN_0
,
1995 VEX_W_0F99_P_0_LEN_0
,
1996 VEX_W_0F99_P_2_LEN_0
,
2004 VEX_W_0F381A_P_2_M_0
,
2005 VEX_W_0F382C_P_2_M_0
,
2006 VEX_W_0F382D_P_2_M_0
,
2007 VEX_W_0F382E_P_2_M_0
,
2008 VEX_W_0F382F_P_2_M_0
,
2013 VEX_W_0F385A_P_2_M_0
,
2025 VEX_W_0F3A30_P_2_LEN_0
,
2026 VEX_W_0F3A31_P_2_LEN_0
,
2027 VEX_W_0F3A32_P_2_LEN_0
,
2028 VEX_W_0F3A33_P_2_LEN_0
,
2048 EVEX_W_0F12_P_0_M_0
,
2049 EVEX_W_0F12_P_0_M_1
,
2059 EVEX_W_0F16_P_0_M_0
,
2060 EVEX_W_0F16_P_0_M_1
,
2129 EVEX_W_0F72_R_2_P_2
,
2130 EVEX_W_0F72_R_6_P_2
,
2131 EVEX_W_0F73_R_2_P_2
,
2132 EVEX_W_0F73_R_6_P_2
,
2242 EVEX_W_0F38C7_R_1_P_2
,
2243 EVEX_W_0F38C7_R_2_P_2
,
2244 EVEX_W_0F38C7_R_5_P_2
,
2245 EVEX_W_0F38C7_R_6_P_2
,
2284 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2293 unsigned int prefix_requirement
;
2296 /* Upper case letters in the instruction names here are macros.
2297 'A' => print 'b' if no register operands or suffix_always is true
2298 'B' => print 'b' if suffix_always is true
2299 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2301 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2302 suffix_always is true
2303 'E' => print 'e' if 32-bit form of jcxz
2304 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2305 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2306 'H' => print ",pt" or ",pn" branch hint
2307 'I' => honor following macro letter even in Intel mode (implemented only
2308 for some of the macro letters)
2310 'K' => print 'd' or 'q' if rex prefix is present.
2311 'L' => print 'l' if suffix_always is true
2312 'M' => print 'r' if intel_mnemonic is false.
2313 'N' => print 'n' if instruction has no wait "prefix"
2314 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2315 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2316 or suffix_always is true. print 'q' if rex prefix is present.
2317 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2319 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2320 'S' => print 'w', 'l' or 'q' if suffix_always is true
2321 'T' => print 'q' in 64bit mode if instruction has no operand size
2322 prefix and behave as 'P' otherwise
2323 'U' => print 'q' in 64bit mode if instruction has no operand size
2324 prefix and behave as 'Q' otherwise
2325 'V' => print 'q' in 64bit mode if instruction has no operand size
2326 prefix and behave as 'S' otherwise
2327 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2328 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2330 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2331 '!' => change condition from true to false or from false to true.
2332 '%' => add 1 upper case letter to the macro.
2333 '^' => print 'w' or 'l' depending on operand size prefix or
2334 suffix_always is true (lcall/ljmp).
2335 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2336 on operand size prefix.
2337 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2338 has no operand size prefix for AMD64 ISA, behave as 'P'
2341 2 upper case letter macros:
2342 "XY" => print 'x' or 'y' if suffix_always is true or no register
2343 operands and no broadcast.
2344 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2345 register operands and no broadcast.
2346 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2347 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2348 or suffix_always is true
2349 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2350 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2351 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2352 "LW" => print 'd', 'q' depending on the VEX.W bit
2353 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2354 an operand size prefix, or suffix_always is true. print
2355 'q' if rex prefix is present.
2357 Many of the above letters print nothing in Intel mode. See "putop"
2360 Braces '{' and '}', and vertical bars '|', indicate alternative
2361 mnemonic strings for AT&T and Intel. */
2363 static const struct dis386 dis386
[] = {
2365 { "addB", { Ebh1
, Gb
}, 0 },
2366 { "addS", { Evh1
, Gv
}, 0 },
2367 { "addB", { Gb
, EbS
}, 0 },
2368 { "addS", { Gv
, EvS
}, 0 },
2369 { "addB", { AL
, Ib
}, 0 },
2370 { "addS", { eAX
, Iv
}, 0 },
2371 { X86_64_TABLE (X86_64_06
) },
2372 { X86_64_TABLE (X86_64_07
) },
2374 { "orB", { Ebh1
, Gb
}, 0 },
2375 { "orS", { Evh1
, Gv
}, 0 },
2376 { "orB", { Gb
, EbS
}, 0 },
2377 { "orS", { Gv
, EvS
}, 0 },
2378 { "orB", { AL
, Ib
}, 0 },
2379 { "orS", { eAX
, Iv
}, 0 },
2380 { X86_64_TABLE (X86_64_0D
) },
2381 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2383 { "adcB", { Ebh1
, Gb
}, 0 },
2384 { "adcS", { Evh1
, Gv
}, 0 },
2385 { "adcB", { Gb
, EbS
}, 0 },
2386 { "adcS", { Gv
, EvS
}, 0 },
2387 { "adcB", { AL
, Ib
}, 0 },
2388 { "adcS", { eAX
, Iv
}, 0 },
2389 { X86_64_TABLE (X86_64_16
) },
2390 { X86_64_TABLE (X86_64_17
) },
2392 { "sbbB", { Ebh1
, Gb
}, 0 },
2393 { "sbbS", { Evh1
, Gv
}, 0 },
2394 { "sbbB", { Gb
, EbS
}, 0 },
2395 { "sbbS", { Gv
, EvS
}, 0 },
2396 { "sbbB", { AL
, Ib
}, 0 },
2397 { "sbbS", { eAX
, Iv
}, 0 },
2398 { X86_64_TABLE (X86_64_1E
) },
2399 { X86_64_TABLE (X86_64_1F
) },
2401 { "andB", { Ebh1
, Gb
}, 0 },
2402 { "andS", { Evh1
, Gv
}, 0 },
2403 { "andB", { Gb
, EbS
}, 0 },
2404 { "andS", { Gv
, EvS
}, 0 },
2405 { "andB", { AL
, Ib
}, 0 },
2406 { "andS", { eAX
, Iv
}, 0 },
2407 { Bad_Opcode
}, /* SEG ES prefix */
2408 { X86_64_TABLE (X86_64_27
) },
2410 { "subB", { Ebh1
, Gb
}, 0 },
2411 { "subS", { Evh1
, Gv
}, 0 },
2412 { "subB", { Gb
, EbS
}, 0 },
2413 { "subS", { Gv
, EvS
}, 0 },
2414 { "subB", { AL
, Ib
}, 0 },
2415 { "subS", { eAX
, Iv
}, 0 },
2416 { Bad_Opcode
}, /* SEG CS prefix */
2417 { X86_64_TABLE (X86_64_2F
) },
2419 { "xorB", { Ebh1
, Gb
}, 0 },
2420 { "xorS", { Evh1
, Gv
}, 0 },
2421 { "xorB", { Gb
, EbS
}, 0 },
2422 { "xorS", { Gv
, EvS
}, 0 },
2423 { "xorB", { AL
, Ib
}, 0 },
2424 { "xorS", { eAX
, Iv
}, 0 },
2425 { Bad_Opcode
}, /* SEG SS prefix */
2426 { X86_64_TABLE (X86_64_37
) },
2428 { "cmpB", { Eb
, Gb
}, 0 },
2429 { "cmpS", { Ev
, Gv
}, 0 },
2430 { "cmpB", { Gb
, EbS
}, 0 },
2431 { "cmpS", { Gv
, EvS
}, 0 },
2432 { "cmpB", { AL
, Ib
}, 0 },
2433 { "cmpS", { eAX
, Iv
}, 0 },
2434 { Bad_Opcode
}, /* SEG DS prefix */
2435 { X86_64_TABLE (X86_64_3F
) },
2437 { "inc{S|}", { RMeAX
}, 0 },
2438 { "inc{S|}", { RMeCX
}, 0 },
2439 { "inc{S|}", { RMeDX
}, 0 },
2440 { "inc{S|}", { RMeBX
}, 0 },
2441 { "inc{S|}", { RMeSP
}, 0 },
2442 { "inc{S|}", { RMeBP
}, 0 },
2443 { "inc{S|}", { RMeSI
}, 0 },
2444 { "inc{S|}", { RMeDI
}, 0 },
2446 { "dec{S|}", { RMeAX
}, 0 },
2447 { "dec{S|}", { RMeCX
}, 0 },
2448 { "dec{S|}", { RMeDX
}, 0 },
2449 { "dec{S|}", { RMeBX
}, 0 },
2450 { "dec{S|}", { RMeSP
}, 0 },
2451 { "dec{S|}", { RMeBP
}, 0 },
2452 { "dec{S|}", { RMeSI
}, 0 },
2453 { "dec{S|}", { RMeDI
}, 0 },
2455 { "pushV", { RMrAX
}, 0 },
2456 { "pushV", { RMrCX
}, 0 },
2457 { "pushV", { RMrDX
}, 0 },
2458 { "pushV", { RMrBX
}, 0 },
2459 { "pushV", { RMrSP
}, 0 },
2460 { "pushV", { RMrBP
}, 0 },
2461 { "pushV", { RMrSI
}, 0 },
2462 { "pushV", { RMrDI
}, 0 },
2464 { "popV", { RMrAX
}, 0 },
2465 { "popV", { RMrCX
}, 0 },
2466 { "popV", { RMrDX
}, 0 },
2467 { "popV", { RMrBX
}, 0 },
2468 { "popV", { RMrSP
}, 0 },
2469 { "popV", { RMrBP
}, 0 },
2470 { "popV", { RMrSI
}, 0 },
2471 { "popV", { RMrDI
}, 0 },
2473 { X86_64_TABLE (X86_64_60
) },
2474 { X86_64_TABLE (X86_64_61
) },
2475 { X86_64_TABLE (X86_64_62
) },
2476 { X86_64_TABLE (X86_64_63
) },
2477 { Bad_Opcode
}, /* seg fs */
2478 { Bad_Opcode
}, /* seg gs */
2479 { Bad_Opcode
}, /* op size prefix */
2480 { Bad_Opcode
}, /* adr size prefix */
2482 { "pushT", { sIv
}, 0 },
2483 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2484 { "pushT", { sIbT
}, 0 },
2485 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2486 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2487 { X86_64_TABLE (X86_64_6D
) },
2488 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2489 { X86_64_TABLE (X86_64_6F
) },
2491 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2492 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2493 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2494 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2495 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2496 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2497 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2498 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2500 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2501 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2502 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2503 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2504 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2505 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2506 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2507 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2509 { REG_TABLE (REG_80
) },
2510 { REG_TABLE (REG_81
) },
2511 { X86_64_TABLE (X86_64_82
) },
2512 { REG_TABLE (REG_83
) },
2513 { "testB", { Eb
, Gb
}, 0 },
2514 { "testS", { Ev
, Gv
}, 0 },
2515 { "xchgB", { Ebh2
, Gb
}, 0 },
2516 { "xchgS", { Evh2
, Gv
}, 0 },
2518 { "movB", { Ebh3
, Gb
}, 0 },
2519 { "movS", { Evh3
, Gv
}, 0 },
2520 { "movB", { Gb
, EbS
}, 0 },
2521 { "movS", { Gv
, EvS
}, 0 },
2522 { "movD", { Sv
, Sw
}, 0 },
2523 { MOD_TABLE (MOD_8D
) },
2524 { "movD", { Sw
, Sv
}, 0 },
2525 { REG_TABLE (REG_8F
) },
2527 { PREFIX_TABLE (PREFIX_90
) },
2528 { "xchgS", { RMeCX
, eAX
}, 0 },
2529 { "xchgS", { RMeDX
, eAX
}, 0 },
2530 { "xchgS", { RMeBX
, eAX
}, 0 },
2531 { "xchgS", { RMeSP
, eAX
}, 0 },
2532 { "xchgS", { RMeBP
, eAX
}, 0 },
2533 { "xchgS", { RMeSI
, eAX
}, 0 },
2534 { "xchgS", { RMeDI
, eAX
}, 0 },
2536 { "cW{t|}R", { XX
}, 0 },
2537 { "cR{t|}O", { XX
}, 0 },
2538 { X86_64_TABLE (X86_64_9A
) },
2539 { Bad_Opcode
}, /* fwait */
2540 { "pushfT", { XX
}, 0 },
2541 { "popfT", { XX
}, 0 },
2542 { "sahf", { XX
}, 0 },
2543 { "lahf", { XX
}, 0 },
2545 { "mov%LB", { AL
, Ob
}, 0 },
2546 { "mov%LS", { eAX
, Ov
}, 0 },
2547 { "mov%LB", { Ob
, AL
}, 0 },
2548 { "mov%LS", { Ov
, eAX
}, 0 },
2549 { "movs{b|}", { Ybr
, Xb
}, 0 },
2550 { "movs{R|}", { Yvr
, Xv
}, 0 },
2551 { "cmps{b|}", { Xb
, Yb
}, 0 },
2552 { "cmps{R|}", { Xv
, Yv
}, 0 },
2554 { "testB", { AL
, Ib
}, 0 },
2555 { "testS", { eAX
, Iv
}, 0 },
2556 { "stosB", { Ybr
, AL
}, 0 },
2557 { "stosS", { Yvr
, eAX
}, 0 },
2558 { "lodsB", { ALr
, Xb
}, 0 },
2559 { "lodsS", { eAXr
, Xv
}, 0 },
2560 { "scasB", { AL
, Yb
}, 0 },
2561 { "scasS", { eAX
, Yv
}, 0 },
2563 { "movB", { RMAL
, Ib
}, 0 },
2564 { "movB", { RMCL
, Ib
}, 0 },
2565 { "movB", { RMDL
, Ib
}, 0 },
2566 { "movB", { RMBL
, Ib
}, 0 },
2567 { "movB", { RMAH
, Ib
}, 0 },
2568 { "movB", { RMCH
, Ib
}, 0 },
2569 { "movB", { RMDH
, Ib
}, 0 },
2570 { "movB", { RMBH
, Ib
}, 0 },
2572 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2573 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2574 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2575 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2576 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2577 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2578 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2579 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2581 { REG_TABLE (REG_C0
) },
2582 { REG_TABLE (REG_C1
) },
2583 { "retT", { Iw
, BND
}, 0 },
2584 { "retT", { BND
}, 0 },
2585 { X86_64_TABLE (X86_64_C4
) },
2586 { X86_64_TABLE (X86_64_C5
) },
2587 { REG_TABLE (REG_C6
) },
2588 { REG_TABLE (REG_C7
) },
2590 { "enterT", { Iw
, Ib
}, 0 },
2591 { "leaveT", { XX
}, 0 },
2592 { "Jret{|f}P", { Iw
}, 0 },
2593 { "Jret{|f}P", { XX
}, 0 },
2594 { "int3", { XX
}, 0 },
2595 { "int", { Ib
}, 0 },
2596 { X86_64_TABLE (X86_64_CE
) },
2597 { "iret%LP", { XX
}, 0 },
2599 { REG_TABLE (REG_D0
) },
2600 { REG_TABLE (REG_D1
) },
2601 { REG_TABLE (REG_D2
) },
2602 { REG_TABLE (REG_D3
) },
2603 { X86_64_TABLE (X86_64_D4
) },
2604 { X86_64_TABLE (X86_64_D5
) },
2606 { "xlat", { DSBX
}, 0 },
2617 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2618 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2619 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2620 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2621 { "inB", { AL
, Ib
}, 0 },
2622 { "inG", { zAX
, Ib
}, 0 },
2623 { "outB", { Ib
, AL
}, 0 },
2624 { "outG", { Ib
, zAX
}, 0 },
2626 { X86_64_TABLE (X86_64_E8
) },
2627 { X86_64_TABLE (X86_64_E9
) },
2628 { X86_64_TABLE (X86_64_EA
) },
2629 { "jmp", { Jb
, BND
}, 0 },
2630 { "inB", { AL
, indirDX
}, 0 },
2631 { "inG", { zAX
, indirDX
}, 0 },
2632 { "outB", { indirDX
, AL
}, 0 },
2633 { "outG", { indirDX
, zAX
}, 0 },
2635 { Bad_Opcode
}, /* lock prefix */
2636 { "icebp", { XX
}, 0 },
2637 { Bad_Opcode
}, /* repne */
2638 { Bad_Opcode
}, /* repz */
2639 { "hlt", { XX
}, 0 },
2640 { "cmc", { XX
}, 0 },
2641 { REG_TABLE (REG_F6
) },
2642 { REG_TABLE (REG_F7
) },
2644 { "clc", { XX
}, 0 },
2645 { "stc", { XX
}, 0 },
2646 { "cli", { XX
}, 0 },
2647 { "sti", { XX
}, 0 },
2648 { "cld", { XX
}, 0 },
2649 { "std", { XX
}, 0 },
2650 { REG_TABLE (REG_FE
) },
2651 { REG_TABLE (REG_FF
) },
2654 static const struct dis386 dis386_twobyte
[] = {
2656 { REG_TABLE (REG_0F00
) },
2657 { REG_TABLE (REG_0F01
) },
2658 { "larS", { Gv
, Ew
}, 0 },
2659 { "lslS", { Gv
, Ew
}, 0 },
2661 { "syscall", { XX
}, 0 },
2662 { "clts", { XX
}, 0 },
2663 { "sysret%LP", { XX
}, 0 },
2665 { "invd", { XX
}, 0 },
2666 { PREFIX_TABLE (PREFIX_0F09
) },
2668 { "ud2", { XX
}, 0 },
2670 { REG_TABLE (REG_0F0D
) },
2671 { "femms", { XX
}, 0 },
2672 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2674 { PREFIX_TABLE (PREFIX_0F10
) },
2675 { PREFIX_TABLE (PREFIX_0F11
) },
2676 { PREFIX_TABLE (PREFIX_0F12
) },
2677 { MOD_TABLE (MOD_0F13
) },
2678 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2679 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2680 { PREFIX_TABLE (PREFIX_0F16
) },
2681 { MOD_TABLE (MOD_0F17
) },
2683 { REG_TABLE (REG_0F18
) },
2684 { "nopQ", { Ev
}, 0 },
2685 { PREFIX_TABLE (PREFIX_0F1A
) },
2686 { PREFIX_TABLE (PREFIX_0F1B
) },
2687 { PREFIX_TABLE (PREFIX_0F1C
) },
2688 { "nopQ", { Ev
}, 0 },
2689 { PREFIX_TABLE (PREFIX_0F1E
) },
2690 { "nopQ", { Ev
}, 0 },
2692 { "movZ", { Rm
, Cm
}, 0 },
2693 { "movZ", { Rm
, Dm
}, 0 },
2694 { "movZ", { Cm
, Rm
}, 0 },
2695 { "movZ", { Dm
, Rm
}, 0 },
2696 { MOD_TABLE (MOD_0F24
) },
2698 { MOD_TABLE (MOD_0F26
) },
2701 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2702 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2703 { PREFIX_TABLE (PREFIX_0F2A
) },
2704 { PREFIX_TABLE (PREFIX_0F2B
) },
2705 { PREFIX_TABLE (PREFIX_0F2C
) },
2706 { PREFIX_TABLE (PREFIX_0F2D
) },
2707 { PREFIX_TABLE (PREFIX_0F2E
) },
2708 { PREFIX_TABLE (PREFIX_0F2F
) },
2710 { "wrmsr", { XX
}, 0 },
2711 { "rdtsc", { XX
}, 0 },
2712 { "rdmsr", { XX
}, 0 },
2713 { "rdpmc", { XX
}, 0 },
2714 { "sysenter", { XX
}, 0 },
2715 { "sysexit", { XX
}, 0 },
2717 { "getsec", { XX
}, 0 },
2719 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2721 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2728 { "cmovoS", { Gv
, Ev
}, 0 },
2729 { "cmovnoS", { Gv
, Ev
}, 0 },
2730 { "cmovbS", { Gv
, Ev
}, 0 },
2731 { "cmovaeS", { Gv
, Ev
}, 0 },
2732 { "cmoveS", { Gv
, Ev
}, 0 },
2733 { "cmovneS", { Gv
, Ev
}, 0 },
2734 { "cmovbeS", { Gv
, Ev
}, 0 },
2735 { "cmovaS", { Gv
, Ev
}, 0 },
2737 { "cmovsS", { Gv
, Ev
}, 0 },
2738 { "cmovnsS", { Gv
, Ev
}, 0 },
2739 { "cmovpS", { Gv
, Ev
}, 0 },
2740 { "cmovnpS", { Gv
, Ev
}, 0 },
2741 { "cmovlS", { Gv
, Ev
}, 0 },
2742 { "cmovgeS", { Gv
, Ev
}, 0 },
2743 { "cmovleS", { Gv
, Ev
}, 0 },
2744 { "cmovgS", { Gv
, Ev
}, 0 },
2746 { MOD_TABLE (MOD_0F51
) },
2747 { PREFIX_TABLE (PREFIX_0F51
) },
2748 { PREFIX_TABLE (PREFIX_0F52
) },
2749 { PREFIX_TABLE (PREFIX_0F53
) },
2750 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2751 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2752 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2753 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2755 { PREFIX_TABLE (PREFIX_0F58
) },
2756 { PREFIX_TABLE (PREFIX_0F59
) },
2757 { PREFIX_TABLE (PREFIX_0F5A
) },
2758 { PREFIX_TABLE (PREFIX_0F5B
) },
2759 { PREFIX_TABLE (PREFIX_0F5C
) },
2760 { PREFIX_TABLE (PREFIX_0F5D
) },
2761 { PREFIX_TABLE (PREFIX_0F5E
) },
2762 { PREFIX_TABLE (PREFIX_0F5F
) },
2764 { PREFIX_TABLE (PREFIX_0F60
) },
2765 { PREFIX_TABLE (PREFIX_0F61
) },
2766 { PREFIX_TABLE (PREFIX_0F62
) },
2767 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2768 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2769 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2770 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2771 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2773 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2774 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2775 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2776 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2777 { PREFIX_TABLE (PREFIX_0F6C
) },
2778 { PREFIX_TABLE (PREFIX_0F6D
) },
2779 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2780 { PREFIX_TABLE (PREFIX_0F6F
) },
2782 { PREFIX_TABLE (PREFIX_0F70
) },
2783 { REG_TABLE (REG_0F71
) },
2784 { REG_TABLE (REG_0F72
) },
2785 { REG_TABLE (REG_0F73
) },
2786 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2787 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2788 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
2789 { "emms", { XX
}, PREFIX_OPCODE
},
2791 { PREFIX_TABLE (PREFIX_0F78
) },
2792 { PREFIX_TABLE (PREFIX_0F79
) },
2795 { PREFIX_TABLE (PREFIX_0F7C
) },
2796 { PREFIX_TABLE (PREFIX_0F7D
) },
2797 { PREFIX_TABLE (PREFIX_0F7E
) },
2798 { PREFIX_TABLE (PREFIX_0F7F
) },
2800 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
2801 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
2802 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
2803 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2804 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2805 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
2806 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2807 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
2809 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2810 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
2811 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2812 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
2813 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
2814 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
2815 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
2816 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
2818 { "seto", { Eb
}, 0 },
2819 { "setno", { Eb
}, 0 },
2820 { "setb", { Eb
}, 0 },
2821 { "setae", { Eb
}, 0 },
2822 { "sete", { Eb
}, 0 },
2823 { "setne", { Eb
}, 0 },
2824 { "setbe", { Eb
}, 0 },
2825 { "seta", { Eb
}, 0 },
2827 { "sets", { Eb
}, 0 },
2828 { "setns", { Eb
}, 0 },
2829 { "setp", { Eb
}, 0 },
2830 { "setnp", { Eb
}, 0 },
2831 { "setl", { Eb
}, 0 },
2832 { "setge", { Eb
}, 0 },
2833 { "setle", { Eb
}, 0 },
2834 { "setg", { Eb
}, 0 },
2836 { "pushT", { fs
}, 0 },
2837 { "popT", { fs
}, 0 },
2838 { "cpuid", { XX
}, 0 },
2839 { "btS", { Ev
, Gv
}, 0 },
2840 { "shldS", { Ev
, Gv
, Ib
}, 0 },
2841 { "shldS", { Ev
, Gv
, CL
}, 0 },
2842 { REG_TABLE (REG_0FA6
) },
2843 { REG_TABLE (REG_0FA7
) },
2845 { "pushT", { gs
}, 0 },
2846 { "popT", { gs
}, 0 },
2847 { "rsm", { XX
}, 0 },
2848 { "btsS", { Evh1
, Gv
}, 0 },
2849 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
2850 { "shrdS", { Ev
, Gv
, CL
}, 0 },
2851 { REG_TABLE (REG_0FAE
) },
2852 { "imulS", { Gv
, Ev
}, 0 },
2854 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
2855 { "cmpxchgS", { Evh1
, Gv
}, 0 },
2856 { MOD_TABLE (MOD_0FB2
) },
2857 { "btrS", { Evh1
, Gv
}, 0 },
2858 { MOD_TABLE (MOD_0FB4
) },
2859 { MOD_TABLE (MOD_0FB5
) },
2860 { "movz{bR|x}", { Gv
, Eb
}, 0 },
2861 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
2863 { PREFIX_TABLE (PREFIX_0FB8
) },
2864 { "ud1S", { Gv
, Ev
}, 0 },
2865 { REG_TABLE (REG_0FBA
) },
2866 { "btcS", { Evh1
, Gv
}, 0 },
2867 { PREFIX_TABLE (PREFIX_0FBC
) },
2868 { PREFIX_TABLE (PREFIX_0FBD
) },
2869 { "movs{bR|x}", { Gv
, Eb
}, 0 },
2870 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
2872 { "xaddB", { Ebh1
, Gb
}, 0 },
2873 { "xaddS", { Evh1
, Gv
}, 0 },
2874 { PREFIX_TABLE (PREFIX_0FC2
) },
2875 { MOD_TABLE (MOD_0FC3
) },
2876 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
2877 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
2878 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
2879 { REG_TABLE (REG_0FC7
) },
2881 { "bswap", { RMeAX
}, 0 },
2882 { "bswap", { RMeCX
}, 0 },
2883 { "bswap", { RMeDX
}, 0 },
2884 { "bswap", { RMeBX
}, 0 },
2885 { "bswap", { RMeSP
}, 0 },
2886 { "bswap", { RMeBP
}, 0 },
2887 { "bswap", { RMeSI
}, 0 },
2888 { "bswap", { RMeDI
}, 0 },
2890 { PREFIX_TABLE (PREFIX_0FD0
) },
2891 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
2892 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
2893 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
2894 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
2895 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
2896 { PREFIX_TABLE (PREFIX_0FD6
) },
2897 { MOD_TABLE (MOD_0FD7
) },
2899 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
2900 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
2901 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
2902 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
2903 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
2904 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
2905 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
2906 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
2908 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
2909 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
2910 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
2911 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
2912 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
2913 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
2914 { PREFIX_TABLE (PREFIX_0FE6
) },
2915 { PREFIX_TABLE (PREFIX_0FE7
) },
2917 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
2918 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
2919 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
2920 { "por", { MX
, EM
}, PREFIX_OPCODE
},
2921 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
2922 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
2923 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
2924 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
2926 { PREFIX_TABLE (PREFIX_0FF0
) },
2927 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
2928 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
2929 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
2930 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
2931 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
2932 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
2933 { PREFIX_TABLE (PREFIX_0FF7
) },
2935 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
2936 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
2937 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
2938 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
2939 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
2940 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
2941 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
2942 { "ud0S", { Gv
, Ev
}, 0 },
2945 static const unsigned char onebyte_has_modrm
[256] = {
2946 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2947 /* ------------------------------- */
2948 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2949 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2950 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2951 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2952 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2953 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2954 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2955 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2956 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2957 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2958 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2959 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2960 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2961 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2962 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2963 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2964 /* ------------------------------- */
2965 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2968 static const unsigned char twobyte_has_modrm
[256] = {
2969 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2970 /* ------------------------------- */
2971 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2972 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2973 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2974 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2975 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2976 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2977 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2978 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2979 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2980 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2981 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2982 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2983 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2984 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2985 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2986 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2987 /* ------------------------------- */
2988 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2991 static char obuf
[100];
2993 static char *mnemonicendp
;
2994 static char scratchbuf
[100];
2995 static unsigned char *start_codep
;
2996 static unsigned char *insn_codep
;
2997 static unsigned char *codep
;
2998 static unsigned char *end_codep
;
2999 static int last_lock_prefix
;
3000 static int last_repz_prefix
;
3001 static int last_repnz_prefix
;
3002 static int last_data_prefix
;
3003 static int last_addr_prefix
;
3004 static int last_rex_prefix
;
3005 static int last_seg_prefix
;
3006 static int fwait_prefix
;
3007 /* The active segment register prefix. */
3008 static int active_seg_prefix
;
3009 #define MAX_CODE_LENGTH 15
3010 /* We can up to 14 prefixes since the maximum instruction length is
3012 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3013 static disassemble_info
*the_info
;
3021 static unsigned char need_modrm
;
3031 int register_specifier
;
3038 int mask_register_specifier
;
3044 static unsigned char need_vex
;
3045 static unsigned char need_vex_reg
;
3046 static unsigned char vex_w_done
;
3054 /* If we are accessing mod/rm/reg without need_modrm set, then the
3055 values are stale. Hitting this abort likely indicates that you
3056 need to update onebyte_has_modrm or twobyte_has_modrm. */
3057 #define MODRM_CHECK if (!need_modrm) abort ()
3059 static const char **names64
;
3060 static const char **names32
;
3061 static const char **names16
;
3062 static const char **names8
;
3063 static const char **names8rex
;
3064 static const char **names_seg
;
3065 static const char *index64
;
3066 static const char *index32
;
3067 static const char **index16
;
3068 static const char **names_bnd
;
3070 static const char *intel_names64
[] = {
3071 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3072 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3074 static const char *intel_names32
[] = {
3075 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3076 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3078 static const char *intel_names16
[] = {
3079 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3080 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3082 static const char *intel_names8
[] = {
3083 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3085 static const char *intel_names8rex
[] = {
3086 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3087 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3089 static const char *intel_names_seg
[] = {
3090 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3092 static const char *intel_index64
= "riz";
3093 static const char *intel_index32
= "eiz";
3094 static const char *intel_index16
[] = {
3095 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3098 static const char *att_names64
[] = {
3099 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3100 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3102 static const char *att_names32
[] = {
3103 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3104 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3106 static const char *att_names16
[] = {
3107 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3108 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3110 static const char *att_names8
[] = {
3111 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3113 static const char *att_names8rex
[] = {
3114 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3115 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3117 static const char *att_names_seg
[] = {
3118 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3120 static const char *att_index64
= "%riz";
3121 static const char *att_index32
= "%eiz";
3122 static const char *att_index16
[] = {
3123 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3126 static const char **names_mm
;
3127 static const char *intel_names_mm
[] = {
3128 "mm0", "mm1", "mm2", "mm3",
3129 "mm4", "mm5", "mm6", "mm7"
3131 static const char *att_names_mm
[] = {
3132 "%mm0", "%mm1", "%mm2", "%mm3",
3133 "%mm4", "%mm5", "%mm6", "%mm7"
3136 static const char *intel_names_bnd
[] = {
3137 "bnd0", "bnd1", "bnd2", "bnd3"
3140 static const char *att_names_bnd
[] = {
3141 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3144 static const char **names_xmm
;
3145 static const char *intel_names_xmm
[] = {
3146 "xmm0", "xmm1", "xmm2", "xmm3",
3147 "xmm4", "xmm5", "xmm6", "xmm7",
3148 "xmm8", "xmm9", "xmm10", "xmm11",
3149 "xmm12", "xmm13", "xmm14", "xmm15",
3150 "xmm16", "xmm17", "xmm18", "xmm19",
3151 "xmm20", "xmm21", "xmm22", "xmm23",
3152 "xmm24", "xmm25", "xmm26", "xmm27",
3153 "xmm28", "xmm29", "xmm30", "xmm31"
3155 static const char *att_names_xmm
[] = {
3156 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3157 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3158 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3159 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3160 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3161 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3162 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3163 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3166 static const char **names_ymm
;
3167 static const char *intel_names_ymm
[] = {
3168 "ymm0", "ymm1", "ymm2", "ymm3",
3169 "ymm4", "ymm5", "ymm6", "ymm7",
3170 "ymm8", "ymm9", "ymm10", "ymm11",
3171 "ymm12", "ymm13", "ymm14", "ymm15",
3172 "ymm16", "ymm17", "ymm18", "ymm19",
3173 "ymm20", "ymm21", "ymm22", "ymm23",
3174 "ymm24", "ymm25", "ymm26", "ymm27",
3175 "ymm28", "ymm29", "ymm30", "ymm31"
3177 static const char *att_names_ymm
[] = {
3178 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3179 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3180 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3181 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3182 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3183 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3184 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3185 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3188 static const char **names_zmm
;
3189 static const char *intel_names_zmm
[] = {
3190 "zmm0", "zmm1", "zmm2", "zmm3",
3191 "zmm4", "zmm5", "zmm6", "zmm7",
3192 "zmm8", "zmm9", "zmm10", "zmm11",
3193 "zmm12", "zmm13", "zmm14", "zmm15",
3194 "zmm16", "zmm17", "zmm18", "zmm19",
3195 "zmm20", "zmm21", "zmm22", "zmm23",
3196 "zmm24", "zmm25", "zmm26", "zmm27",
3197 "zmm28", "zmm29", "zmm30", "zmm31"
3199 static const char *att_names_zmm
[] = {
3200 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3201 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3202 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3203 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3204 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3205 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3206 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3207 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3210 static const char **names_mask
;
3211 static const char *intel_names_mask
[] = {
3212 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3214 static const char *att_names_mask
[] = {
3215 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3218 static const char *names_rounding
[] =
3226 static const struct dis386 reg_table
[][8] = {
3229 { "addA", { Ebh1
, Ib
}, 0 },
3230 { "orA", { Ebh1
, Ib
}, 0 },
3231 { "adcA", { Ebh1
, Ib
}, 0 },
3232 { "sbbA", { Ebh1
, Ib
}, 0 },
3233 { "andA", { Ebh1
, Ib
}, 0 },
3234 { "subA", { Ebh1
, Ib
}, 0 },
3235 { "xorA", { Ebh1
, Ib
}, 0 },
3236 { "cmpA", { Eb
, Ib
}, 0 },
3240 { "addQ", { Evh1
, Iv
}, 0 },
3241 { "orQ", { Evh1
, Iv
}, 0 },
3242 { "adcQ", { Evh1
, Iv
}, 0 },
3243 { "sbbQ", { Evh1
, Iv
}, 0 },
3244 { "andQ", { Evh1
, Iv
}, 0 },
3245 { "subQ", { Evh1
, Iv
}, 0 },
3246 { "xorQ", { Evh1
, Iv
}, 0 },
3247 { "cmpQ", { Ev
, Iv
}, 0 },
3251 { "addQ", { Evh1
, sIb
}, 0 },
3252 { "orQ", { Evh1
, sIb
}, 0 },
3253 { "adcQ", { Evh1
, sIb
}, 0 },
3254 { "sbbQ", { Evh1
, sIb
}, 0 },
3255 { "andQ", { Evh1
, sIb
}, 0 },
3256 { "subQ", { Evh1
, sIb
}, 0 },
3257 { "xorQ", { Evh1
, sIb
}, 0 },
3258 { "cmpQ", { Ev
, sIb
}, 0 },
3262 { "popU", { stackEv
}, 0 },
3263 { XOP_8F_TABLE (XOP_09
) },
3267 { XOP_8F_TABLE (XOP_09
) },
3271 { "rolA", { Eb
, Ib
}, 0 },
3272 { "rorA", { Eb
, Ib
}, 0 },
3273 { "rclA", { Eb
, Ib
}, 0 },
3274 { "rcrA", { Eb
, Ib
}, 0 },
3275 { "shlA", { Eb
, Ib
}, 0 },
3276 { "shrA", { Eb
, Ib
}, 0 },
3277 { "shlA", { Eb
, Ib
}, 0 },
3278 { "sarA", { Eb
, Ib
}, 0 },
3282 { "rolQ", { Ev
, Ib
}, 0 },
3283 { "rorQ", { Ev
, Ib
}, 0 },
3284 { "rclQ", { Ev
, Ib
}, 0 },
3285 { "rcrQ", { Ev
, Ib
}, 0 },
3286 { "shlQ", { Ev
, Ib
}, 0 },
3287 { "shrQ", { Ev
, Ib
}, 0 },
3288 { "shlQ", { Ev
, Ib
}, 0 },
3289 { "sarQ", { Ev
, Ib
}, 0 },
3293 { "movA", { Ebh3
, Ib
}, 0 },
3300 { MOD_TABLE (MOD_C6_REG_7
) },
3304 { "movQ", { Evh3
, Iv
}, 0 },
3311 { MOD_TABLE (MOD_C7_REG_7
) },
3315 { "rolA", { Eb
, I1
}, 0 },
3316 { "rorA", { Eb
, I1
}, 0 },
3317 { "rclA", { Eb
, I1
}, 0 },
3318 { "rcrA", { Eb
, I1
}, 0 },
3319 { "shlA", { Eb
, I1
}, 0 },
3320 { "shrA", { Eb
, I1
}, 0 },
3321 { "shlA", { Eb
, I1
}, 0 },
3322 { "sarA", { Eb
, I1
}, 0 },
3326 { "rolQ", { Ev
, I1
}, 0 },
3327 { "rorQ", { Ev
, I1
}, 0 },
3328 { "rclQ", { Ev
, I1
}, 0 },
3329 { "rcrQ", { Ev
, I1
}, 0 },
3330 { "shlQ", { Ev
, I1
}, 0 },
3331 { "shrQ", { Ev
, I1
}, 0 },
3332 { "shlQ", { Ev
, I1
}, 0 },
3333 { "sarQ", { Ev
, I1
}, 0 },
3337 { "rolA", { Eb
, CL
}, 0 },
3338 { "rorA", { Eb
, CL
}, 0 },
3339 { "rclA", { Eb
, CL
}, 0 },
3340 { "rcrA", { Eb
, CL
}, 0 },
3341 { "shlA", { Eb
, CL
}, 0 },
3342 { "shrA", { Eb
, CL
}, 0 },
3343 { "shlA", { Eb
, CL
}, 0 },
3344 { "sarA", { Eb
, CL
}, 0 },
3348 { "rolQ", { Ev
, CL
}, 0 },
3349 { "rorQ", { Ev
, CL
}, 0 },
3350 { "rclQ", { Ev
, CL
}, 0 },
3351 { "rcrQ", { Ev
, CL
}, 0 },
3352 { "shlQ", { Ev
, CL
}, 0 },
3353 { "shrQ", { Ev
, CL
}, 0 },
3354 { "shlQ", { Ev
, CL
}, 0 },
3355 { "sarQ", { Ev
, CL
}, 0 },
3359 { "testA", { Eb
, Ib
}, 0 },
3360 { "testA", { Eb
, Ib
}, 0 },
3361 { "notA", { Ebh1
}, 0 },
3362 { "negA", { Ebh1
}, 0 },
3363 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3364 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3365 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3366 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3370 { "testQ", { Ev
, Iv
}, 0 },
3371 { "testQ", { Ev
, Iv
}, 0 },
3372 { "notQ", { Evh1
}, 0 },
3373 { "negQ", { Evh1
}, 0 },
3374 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3375 { "imulQ", { Ev
}, 0 },
3376 { "divQ", { Ev
}, 0 },
3377 { "idivQ", { Ev
}, 0 },
3381 { "incA", { Ebh1
}, 0 },
3382 { "decA", { Ebh1
}, 0 },
3386 { "incQ", { Evh1
}, 0 },
3387 { "decQ", { Evh1
}, 0 },
3388 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3389 { MOD_TABLE (MOD_FF_REG_3
) },
3390 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3391 { MOD_TABLE (MOD_FF_REG_5
) },
3392 { "pushU", { stackEv
}, 0 },
3397 { "sldtD", { Sv
}, 0 },
3398 { "strD", { Sv
}, 0 },
3399 { "lldt", { Ew
}, 0 },
3400 { "ltr", { Ew
}, 0 },
3401 { "verr", { Ew
}, 0 },
3402 { "verw", { Ew
}, 0 },
3408 { MOD_TABLE (MOD_0F01_REG_0
) },
3409 { MOD_TABLE (MOD_0F01_REG_1
) },
3410 { MOD_TABLE (MOD_0F01_REG_2
) },
3411 { MOD_TABLE (MOD_0F01_REG_3
) },
3412 { "smswD", { Sv
}, 0 },
3413 { MOD_TABLE (MOD_0F01_REG_5
) },
3414 { "lmsw", { Ew
}, 0 },
3415 { MOD_TABLE (MOD_0F01_REG_7
) },
3419 { "prefetch", { Mb
}, 0 },
3420 { "prefetchw", { Mb
}, 0 },
3421 { "prefetchwt1", { Mb
}, 0 },
3422 { "prefetch", { Mb
}, 0 },
3423 { "prefetch", { Mb
}, 0 },
3424 { "prefetch", { Mb
}, 0 },
3425 { "prefetch", { Mb
}, 0 },
3426 { "prefetch", { Mb
}, 0 },
3430 { MOD_TABLE (MOD_0F18_REG_0
) },
3431 { MOD_TABLE (MOD_0F18_REG_1
) },
3432 { MOD_TABLE (MOD_0F18_REG_2
) },
3433 { MOD_TABLE (MOD_0F18_REG_3
) },
3434 { MOD_TABLE (MOD_0F18_REG_4
) },
3435 { MOD_TABLE (MOD_0F18_REG_5
) },
3436 { MOD_TABLE (MOD_0F18_REG_6
) },
3437 { MOD_TABLE (MOD_0F18_REG_7
) },
3439 /* REG_0F1C_P_0_MOD_0 */
3441 { "cldemote", { Mb
}, 0 },
3442 { "nopQ", { Ev
}, 0 },
3443 { "nopQ", { Ev
}, 0 },
3444 { "nopQ", { Ev
}, 0 },
3445 { "nopQ", { Ev
}, 0 },
3446 { "nopQ", { Ev
}, 0 },
3447 { "nopQ", { Ev
}, 0 },
3448 { "nopQ", { Ev
}, 0 },
3450 /* REG_0F1E_P_1_MOD_3 */
3452 { "nopQ", { Ev
}, 0 },
3453 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3454 { "nopQ", { Ev
}, 0 },
3455 { "nopQ", { Ev
}, 0 },
3456 { "nopQ", { Ev
}, 0 },
3457 { "nopQ", { Ev
}, 0 },
3458 { "nopQ", { Ev
}, 0 },
3459 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7
) },
3465 { MOD_TABLE (MOD_0F71_REG_2
) },
3467 { MOD_TABLE (MOD_0F71_REG_4
) },
3469 { MOD_TABLE (MOD_0F71_REG_6
) },
3475 { MOD_TABLE (MOD_0F72_REG_2
) },
3477 { MOD_TABLE (MOD_0F72_REG_4
) },
3479 { MOD_TABLE (MOD_0F72_REG_6
) },
3485 { MOD_TABLE (MOD_0F73_REG_2
) },
3486 { MOD_TABLE (MOD_0F73_REG_3
) },
3489 { MOD_TABLE (MOD_0F73_REG_6
) },
3490 { MOD_TABLE (MOD_0F73_REG_7
) },
3494 { "montmul", { { OP_0f07
, 0 } }, 0 },
3495 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3496 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3500 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3501 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3502 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3503 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3504 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3505 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3509 { MOD_TABLE (MOD_0FAE_REG_0
) },
3510 { MOD_TABLE (MOD_0FAE_REG_1
) },
3511 { MOD_TABLE (MOD_0FAE_REG_2
) },
3512 { MOD_TABLE (MOD_0FAE_REG_3
) },
3513 { MOD_TABLE (MOD_0FAE_REG_4
) },
3514 { MOD_TABLE (MOD_0FAE_REG_5
) },
3515 { MOD_TABLE (MOD_0FAE_REG_6
) },
3516 { MOD_TABLE (MOD_0FAE_REG_7
) },
3524 { "btQ", { Ev
, Ib
}, 0 },
3525 { "btsQ", { Evh1
, Ib
}, 0 },
3526 { "btrQ", { Evh1
, Ib
}, 0 },
3527 { "btcQ", { Evh1
, Ib
}, 0 },
3532 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3534 { MOD_TABLE (MOD_0FC7_REG_3
) },
3535 { MOD_TABLE (MOD_0FC7_REG_4
) },
3536 { MOD_TABLE (MOD_0FC7_REG_5
) },
3537 { MOD_TABLE (MOD_0FC7_REG_6
) },
3538 { MOD_TABLE (MOD_0FC7_REG_7
) },
3544 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3546 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3548 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3554 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3556 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3558 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3564 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3565 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3568 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3569 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3575 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3576 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3578 /* REG_VEX_0F38F3 */
3581 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3582 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3583 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3587 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3588 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3592 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3593 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Id
}, 0 },
3595 /* REG_XOP_TBM_01 */
3598 { "blcfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3599 { "blsfill", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3600 { "blcs", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3601 { "tzmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3602 { "blcic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3603 { "blsic", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3604 { "t1mskc", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3606 /* REG_XOP_TBM_02 */
3609 { "blcmsk", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3614 { "blci", { { OP_LWP_E
, 0 }, Edq
}, 0 },
3617 #include "i386-dis-evex-reg.h"
3620 static const struct dis386 prefix_table
[][4] = {
3623 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3624 { "pause", { XX
}, 0 },
3625 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3626 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3629 /* PREFIX_0F01_REG_5_MOD_0 */
3632 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3635 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3638 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3641 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3644 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3647 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3649 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
3652 /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3654 { "mwaitx", { { OP_Mwait
, eBX_reg
} }, 0 },
3659 { "wbinvd", { XX
}, 0 },
3660 { "wbnoinvd", { XX
}, 0 },
3665 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3666 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3667 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3668 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3673 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3674 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3675 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3676 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3681 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3682 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3683 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3684 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3689 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3690 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3691 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3696 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3697 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3698 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3699 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3704 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3705 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3706 { "bndmov", { EbndS
, Gbnd
}, 0 },
3707 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3712 { MOD_TABLE (MOD_0F1C_PREFIX_0
) },
3713 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3714 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3715 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3720 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3721 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3722 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3723 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3728 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3729 { "cvtsi2ss%LQ", { XM
, Edq
}, PREFIX_OPCODE
},
3730 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3731 { "cvtsi2sd%LQ", { XM
, Edq
}, 0 },
3736 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3737 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3744 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3745 { "cvttss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3746 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3747 { "cvttsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3752 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3753 { "cvtss2si", { Gdq
, EXd
}, PREFIX_OPCODE
},
3754 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3755 { "cvtsd2si", { Gdq
, EXq
}, PREFIX_OPCODE
},
3760 { "ucomiss",{ XM
, EXd
}, 0 },
3762 { "ucomisd",{ XM
, EXq
}, 0 },
3767 { "comiss", { XM
, EXd
}, 0 },
3769 { "comisd", { XM
, EXq
}, 0 },
3774 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3775 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3776 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3777 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3782 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3783 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3788 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3789 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3794 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3795 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3796 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3797 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3802 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3803 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3804 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3805 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3810 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3811 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3812 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3813 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
3818 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3819 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3820 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
3825 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
3826 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
3827 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
3828 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
3833 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
3834 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
3835 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
3836 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
3841 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
3842 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
3843 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
3844 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
3849 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
3850 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
3851 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
3852 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
3857 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
3859 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
3864 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
3866 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
3871 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
3873 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
3880 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3887 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
3892 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
3893 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
3894 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
3899 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
3900 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3901 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3902 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3905 /* PREFIX_0F73_REG_3 */
3909 { "psrldq", { XS
, Ib
}, 0 },
3912 /* PREFIX_0F73_REG_7 */
3916 { "pslldq", { XS
, Ib
}, 0 },
3921 {"vmread", { Em
, Gm
}, 0 },
3923 {"extrq", { XS
, Ib
, Ib
}, 0 },
3924 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
3929 {"vmwrite", { Gm
, Em
}, 0 },
3931 {"extrq", { XM
, XS
}, 0 },
3932 {"insertq", { XM
, XS
}, 0 },
3939 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
3940 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
3947 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
3948 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
3953 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
3954 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
3955 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
3960 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
3961 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
3962 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
3965 /* PREFIX_0FAE_REG_0_MOD_3 */
3968 { "rdfsbase", { Ev
}, 0 },
3971 /* PREFIX_0FAE_REG_1_MOD_3 */
3974 { "rdgsbase", { Ev
}, 0 },
3977 /* PREFIX_0FAE_REG_2_MOD_3 */
3980 { "wrfsbase", { Ev
}, 0 },
3983 /* PREFIX_0FAE_REG_3_MOD_3 */
3986 { "wrgsbase", { Ev
}, 0 },
3989 /* PREFIX_0FAE_REG_4_MOD_0 */
3991 { "xsave", { FXSAVE
}, 0 },
3992 { "ptwrite%LQ", { Edq
}, 0 },
3995 /* PREFIX_0FAE_REG_4_MOD_3 */
3998 { "ptwrite%LQ", { Edq
}, 0 },
4001 /* PREFIX_0FAE_REG_5_MOD_0 */
4003 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4006 /* PREFIX_0FAE_REG_5_MOD_3 */
4008 { "lfence", { Skip_MODRM
}, 0 },
4009 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4012 /* PREFIX_0FAE_REG_6_MOD_0 */
4014 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4015 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4016 { "clwb", { Mb
}, PREFIX_OPCODE
},
4019 /* PREFIX_0FAE_REG_6_MOD_3 */
4021 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0
) },
4022 { "umonitor", { Eva
}, PREFIX_OPCODE
},
4023 { "tpause", { Edq
}, PREFIX_OPCODE
},
4024 { "umwait", { Edq
}, PREFIX_OPCODE
},
4027 /* PREFIX_0FAE_REG_7_MOD_0 */
4029 { "clflush", { Mb
}, 0 },
4031 { "clflushopt", { Mb
}, 0 },
4037 { "popcntS", { Gv
, Ev
}, 0 },
4042 { "bsfS", { Gv
, Ev
}, 0 },
4043 { "tzcntS", { Gv
, Ev
}, 0 },
4044 { "bsfS", { Gv
, Ev
}, 0 },
4049 { "bsrS", { Gv
, Ev
}, 0 },
4050 { "lzcntS", { Gv
, Ev
}, 0 },
4051 { "bsrS", { Gv
, Ev
}, 0 },
4056 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4057 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4058 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4059 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4062 /* PREFIX_0FC3_MOD_0 */
4064 { "movntiS", { Edq
, Gdq
}, PREFIX_OPCODE
},
4067 /* PREFIX_0FC7_REG_6_MOD_0 */
4069 { "vmptrld",{ Mq
}, 0 },
4070 { "vmxon", { Mq
}, 0 },
4071 { "vmclear",{ Mq
}, 0 },
4074 /* PREFIX_0FC7_REG_6_MOD_3 */
4076 { "rdrand", { Ev
}, 0 },
4078 { "rdrand", { Ev
}, 0 }
4081 /* PREFIX_0FC7_REG_7_MOD_3 */
4083 { "rdseed", { Ev
}, 0 },
4084 { "rdpid", { Em
}, 0 },
4085 { "rdseed", { Ev
}, 0 },
4092 { "addsubpd", { XM
, EXx
}, 0 },
4093 { "addsubps", { XM
, EXx
}, 0 },
4099 { "movq2dq",{ XM
, MS
}, 0 },
4100 { "movq", { EXqS
, XM
}, 0 },
4101 { "movdq2q",{ MX
, XS
}, 0 },
4107 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4108 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4109 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4114 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4116 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4124 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4129 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4131 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4138 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4145 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4152 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4159 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4166 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4173 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4180 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4187 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4194 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4201 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4208 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4215 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4222 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4229 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4236 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4243 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4250 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4257 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4264 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4271 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4278 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4285 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4292 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4299 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4306 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4313 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4320 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4327 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4334 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4341 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4348 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4355 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4362 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4369 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4374 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4379 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4384 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4389 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4394 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4399 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4406 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4413 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4420 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4427 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4434 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4441 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4446 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4448 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4449 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4454 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4456 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4457 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4464 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4469 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4470 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4471 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4478 { MOD_TABLE (MOD_0F38F8_PREFIX_1
) },
4479 { MOD_TABLE (MOD_0F38F8_PREFIX_2
) },
4480 { MOD_TABLE (MOD_0F38F8_PREFIX_3
) },
4485 { MOD_TABLE (MOD_0F38F9_PREFIX_0
) },
4492 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4499 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4506 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4513 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4520 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4527 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4534 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4541 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4548 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4555 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4562 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4569 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4576 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4583 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4590 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4597 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4604 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4611 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4618 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4625 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4632 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4639 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4644 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4651 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4658 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4665 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4668 /* PREFIX_VEX_0F10 */
4670 { "vmovups", { XM
, EXx
}, 0 },
4671 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
4672 { "vmovupd", { XM
, EXx
}, 0 },
4673 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
4676 /* PREFIX_VEX_0F11 */
4678 { "vmovups", { EXxS
, XM
}, 0 },
4679 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
4680 { "vmovupd", { EXxS
, XM
}, 0 },
4681 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
4684 /* PREFIX_VEX_0F12 */
4686 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4687 { "vmovsldup", { XM
, EXx
}, 0 },
4688 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4689 { "vmovddup", { XM
, EXymmq
}, 0 },
4692 /* PREFIX_VEX_0F16 */
4694 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4695 { "vmovshdup", { XM
, EXx
}, 0 },
4696 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4699 /* PREFIX_VEX_0F2A */
4702 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4704 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Edq
}, 0 },
4707 /* PREFIX_VEX_0F2C */
4710 { "vcvttss2si", { Gdq
, EXdScalar
}, 0 },
4712 { "vcvttsd2si", { Gdq
, EXqScalar
}, 0 },
4715 /* PREFIX_VEX_0F2D */
4718 { "vcvtss2si", { Gdq
, EXdScalar
}, 0 },
4720 { "vcvtsd2si", { Gdq
, EXqScalar
}, 0 },
4723 /* PREFIX_VEX_0F2E */
4725 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
4727 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
4730 /* PREFIX_VEX_0F2F */
4732 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
4734 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
4737 /* PREFIX_VEX_0F41 */
4739 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4744 /* PREFIX_VEX_0F42 */
4746 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4748 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4751 /* PREFIX_VEX_0F44 */
4753 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4758 /* PREFIX_VEX_0F45 */
4760 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4762 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4765 /* PREFIX_VEX_0F46 */
4767 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4769 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4772 /* PREFIX_VEX_0F47 */
4774 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4776 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4779 /* PREFIX_VEX_0F4A */
4781 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4783 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4786 /* PREFIX_VEX_0F4B */
4788 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4790 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4793 /* PREFIX_VEX_0F51 */
4795 { "vsqrtps", { XM
, EXx
}, 0 },
4796 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4797 { "vsqrtpd", { XM
, EXx
}, 0 },
4798 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4801 /* PREFIX_VEX_0F52 */
4803 { "vrsqrtps", { XM
, EXx
}, 0 },
4804 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4807 /* PREFIX_VEX_0F53 */
4809 { "vrcpps", { XM
, EXx
}, 0 },
4810 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4813 /* PREFIX_VEX_0F58 */
4815 { "vaddps", { XM
, Vex
, EXx
}, 0 },
4816 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4817 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
4818 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4821 /* PREFIX_VEX_0F59 */
4823 { "vmulps", { XM
, Vex
, EXx
}, 0 },
4824 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4825 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
4826 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4829 /* PREFIX_VEX_0F5A */
4831 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
4832 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4833 { "vcvtpd2ps%XY",{ XMM
, EXx
}, 0 },
4834 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4837 /* PREFIX_VEX_0F5B */
4839 { "vcvtdq2ps", { XM
, EXx
}, 0 },
4840 { "vcvttps2dq", { XM
, EXx
}, 0 },
4841 { "vcvtps2dq", { XM
, EXx
}, 0 },
4844 /* PREFIX_VEX_0F5C */
4846 { "vsubps", { XM
, Vex
, EXx
}, 0 },
4847 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4848 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
4849 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4852 /* PREFIX_VEX_0F5D */
4854 { "vminps", { XM
, Vex
, EXx
}, 0 },
4855 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4856 { "vminpd", { XM
, Vex
, EXx
}, 0 },
4857 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4860 /* PREFIX_VEX_0F5E */
4862 { "vdivps", { XM
, Vex
, EXx
}, 0 },
4863 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4864 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
4865 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4868 /* PREFIX_VEX_0F5F */
4870 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
4871 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
4872 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
4873 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
4876 /* PREFIX_VEX_0F60 */
4880 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
4883 /* PREFIX_VEX_0F61 */
4887 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
4890 /* PREFIX_VEX_0F62 */
4894 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
4897 /* PREFIX_VEX_0F63 */
4901 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
4904 /* PREFIX_VEX_0F64 */
4908 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
4911 /* PREFIX_VEX_0F65 */
4915 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
4918 /* PREFIX_VEX_0F66 */
4922 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
4925 /* PREFIX_VEX_0F67 */
4929 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
4932 /* PREFIX_VEX_0F68 */
4936 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
4939 /* PREFIX_VEX_0F69 */
4943 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
4946 /* PREFIX_VEX_0F6A */
4950 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
4953 /* PREFIX_VEX_0F6B */
4957 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
4960 /* PREFIX_VEX_0F6C */
4964 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
4967 /* PREFIX_VEX_0F6D */
4971 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
4974 /* PREFIX_VEX_0F6E */
4978 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4981 /* PREFIX_VEX_0F6F */
4984 { "vmovdqu", { XM
, EXx
}, 0 },
4985 { "vmovdqa", { XM
, EXx
}, 0 },
4988 /* PREFIX_VEX_0F70 */
4991 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
4992 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
4993 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
4996 /* PREFIX_VEX_0F71_REG_2 */
5000 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
5003 /* PREFIX_VEX_0F71_REG_4 */
5007 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
5010 /* PREFIX_VEX_0F71_REG_6 */
5014 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
5017 /* PREFIX_VEX_0F72_REG_2 */
5021 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
5024 /* PREFIX_VEX_0F72_REG_4 */
5028 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
5031 /* PREFIX_VEX_0F72_REG_6 */
5035 { "vpslld", { Vex
, XS
, Ib
}, 0 },
5038 /* PREFIX_VEX_0F73_REG_2 */
5042 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
5045 /* PREFIX_VEX_0F73_REG_3 */
5049 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
5052 /* PREFIX_VEX_0F73_REG_6 */
5056 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
5059 /* PREFIX_VEX_0F73_REG_7 */
5063 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
5066 /* PREFIX_VEX_0F74 */
5070 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
5073 /* PREFIX_VEX_0F75 */
5077 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
5080 /* PREFIX_VEX_0F76 */
5084 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
5087 /* PREFIX_VEX_0F77 */
5089 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0
) },
5092 /* PREFIX_VEX_0F7C */
5096 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
5097 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
5100 /* PREFIX_VEX_0F7D */
5104 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
5105 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
5108 /* PREFIX_VEX_0F7E */
5111 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5112 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5115 /* PREFIX_VEX_0F7F */
5118 { "vmovdqu", { EXxS
, XM
}, 0 },
5119 { "vmovdqa", { EXxS
, XM
}, 0 },
5122 /* PREFIX_VEX_0F90 */
5124 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5126 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5129 /* PREFIX_VEX_0F91 */
5131 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5133 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5136 /* PREFIX_VEX_0F92 */
5138 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5140 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5141 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5144 /* PREFIX_VEX_0F93 */
5146 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5148 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5149 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5152 /* PREFIX_VEX_0F98 */
5154 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5156 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5159 /* PREFIX_VEX_0F99 */
5161 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5163 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5166 /* PREFIX_VEX_0FC2 */
5168 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
5169 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
5170 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
5171 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
5174 /* PREFIX_VEX_0FC4 */
5178 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5181 /* PREFIX_VEX_0FC5 */
5185 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5188 /* PREFIX_VEX_0FD0 */
5192 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
5193 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
5196 /* PREFIX_VEX_0FD1 */
5200 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
5203 /* PREFIX_VEX_0FD2 */
5207 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
5210 /* PREFIX_VEX_0FD3 */
5214 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
5217 /* PREFIX_VEX_0FD4 */
5221 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
5224 /* PREFIX_VEX_0FD5 */
5228 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
5231 /* PREFIX_VEX_0FD6 */
5235 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5238 /* PREFIX_VEX_0FD7 */
5242 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5245 /* PREFIX_VEX_0FD8 */
5249 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
5252 /* PREFIX_VEX_0FD9 */
5256 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
5259 /* PREFIX_VEX_0FDA */
5263 { "vpminub", { XM
, Vex
, EXx
}, 0 },
5266 /* PREFIX_VEX_0FDB */
5270 { "vpand", { XM
, Vex
, EXx
}, 0 },
5273 /* PREFIX_VEX_0FDC */
5277 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
5280 /* PREFIX_VEX_0FDD */
5284 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
5287 /* PREFIX_VEX_0FDE */
5291 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
5294 /* PREFIX_VEX_0FDF */
5298 { "vpandn", { XM
, Vex
, EXx
}, 0 },
5301 /* PREFIX_VEX_0FE0 */
5305 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
5308 /* PREFIX_VEX_0FE1 */
5312 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
5315 /* PREFIX_VEX_0FE2 */
5319 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
5322 /* PREFIX_VEX_0FE3 */
5326 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
5329 /* PREFIX_VEX_0FE4 */
5333 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
5336 /* PREFIX_VEX_0FE5 */
5340 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
5343 /* PREFIX_VEX_0FE6 */
5346 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
5347 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
5348 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
5351 /* PREFIX_VEX_0FE7 */
5355 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5358 /* PREFIX_VEX_0FE8 */
5362 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
5365 /* PREFIX_VEX_0FE9 */
5369 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
5372 /* PREFIX_VEX_0FEA */
5376 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
5379 /* PREFIX_VEX_0FEB */
5383 { "vpor", { XM
, Vex
, EXx
}, 0 },
5386 /* PREFIX_VEX_0FEC */
5390 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
5393 /* PREFIX_VEX_0FED */
5397 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
5400 /* PREFIX_VEX_0FEE */
5404 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
5407 /* PREFIX_VEX_0FEF */
5411 { "vpxor", { XM
, Vex
, EXx
}, 0 },
5414 /* PREFIX_VEX_0FF0 */
5419 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5422 /* PREFIX_VEX_0FF1 */
5426 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
5429 /* PREFIX_VEX_0FF2 */
5433 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
5436 /* PREFIX_VEX_0FF3 */
5440 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
5443 /* PREFIX_VEX_0FF4 */
5447 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
5450 /* PREFIX_VEX_0FF5 */
5454 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
5457 /* PREFIX_VEX_0FF6 */
5461 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
5464 /* PREFIX_VEX_0FF7 */
5468 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5471 /* PREFIX_VEX_0FF8 */
5475 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
5478 /* PREFIX_VEX_0FF9 */
5482 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
5485 /* PREFIX_VEX_0FFA */
5489 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
5492 /* PREFIX_VEX_0FFB */
5496 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
5499 /* PREFIX_VEX_0FFC */
5503 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
5506 /* PREFIX_VEX_0FFD */
5510 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
5513 /* PREFIX_VEX_0FFE */
5517 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
5520 /* PREFIX_VEX_0F3800 */
5524 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
5527 /* PREFIX_VEX_0F3801 */
5531 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
5534 /* PREFIX_VEX_0F3802 */
5538 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
5541 /* PREFIX_VEX_0F3803 */
5545 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
5548 /* PREFIX_VEX_0F3804 */
5552 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
5555 /* PREFIX_VEX_0F3805 */
5559 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
5562 /* PREFIX_VEX_0F3806 */
5566 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
5569 /* PREFIX_VEX_0F3807 */
5573 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
5576 /* PREFIX_VEX_0F3808 */
5580 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
5583 /* PREFIX_VEX_0F3809 */
5587 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
5590 /* PREFIX_VEX_0F380A */
5594 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
5597 /* PREFIX_VEX_0F380B */
5601 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
5604 /* PREFIX_VEX_0F380C */
5608 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5611 /* PREFIX_VEX_0F380D */
5615 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5618 /* PREFIX_VEX_0F380E */
5622 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5625 /* PREFIX_VEX_0F380F */
5629 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5632 /* PREFIX_VEX_0F3813 */
5636 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5639 /* PREFIX_VEX_0F3816 */
5643 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5646 /* PREFIX_VEX_0F3817 */
5650 { "vptest", { XM
, EXx
}, 0 },
5653 /* PREFIX_VEX_0F3818 */
5657 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5660 /* PREFIX_VEX_0F3819 */
5664 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5667 /* PREFIX_VEX_0F381A */
5671 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5674 /* PREFIX_VEX_0F381C */
5678 { "vpabsb", { XM
, EXx
}, 0 },
5681 /* PREFIX_VEX_0F381D */
5685 { "vpabsw", { XM
, EXx
}, 0 },
5688 /* PREFIX_VEX_0F381E */
5692 { "vpabsd", { XM
, EXx
}, 0 },
5695 /* PREFIX_VEX_0F3820 */
5699 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
5702 /* PREFIX_VEX_0F3821 */
5706 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
5709 /* PREFIX_VEX_0F3822 */
5713 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
5716 /* PREFIX_VEX_0F3823 */
5720 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
5723 /* PREFIX_VEX_0F3824 */
5727 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
5730 /* PREFIX_VEX_0F3825 */
5734 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
5737 /* PREFIX_VEX_0F3828 */
5741 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
5744 /* PREFIX_VEX_0F3829 */
5748 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
5751 /* PREFIX_VEX_0F382A */
5755 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5758 /* PREFIX_VEX_0F382B */
5762 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
5765 /* PREFIX_VEX_0F382C */
5769 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5772 /* PREFIX_VEX_0F382D */
5776 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5779 /* PREFIX_VEX_0F382E */
5783 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5786 /* PREFIX_VEX_0F382F */
5790 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5793 /* PREFIX_VEX_0F3830 */
5797 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
5800 /* PREFIX_VEX_0F3831 */
5804 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
5807 /* PREFIX_VEX_0F3832 */
5811 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
5814 /* PREFIX_VEX_0F3833 */
5818 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
5821 /* PREFIX_VEX_0F3834 */
5825 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
5828 /* PREFIX_VEX_0F3835 */
5832 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
5835 /* PREFIX_VEX_0F3836 */
5839 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5842 /* PREFIX_VEX_0F3837 */
5846 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
5849 /* PREFIX_VEX_0F3838 */
5853 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
5856 /* PREFIX_VEX_0F3839 */
5860 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
5863 /* PREFIX_VEX_0F383A */
5867 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
5870 /* PREFIX_VEX_0F383B */
5874 { "vpminud", { XM
, Vex
, EXx
}, 0 },
5877 /* PREFIX_VEX_0F383C */
5881 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
5884 /* PREFIX_VEX_0F383D */
5888 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
5891 /* PREFIX_VEX_0F383E */
5895 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
5898 /* PREFIX_VEX_0F383F */
5902 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
5905 /* PREFIX_VEX_0F3840 */
5909 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
5912 /* PREFIX_VEX_0F3841 */
5916 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5919 /* PREFIX_VEX_0F3845 */
5923 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
5926 /* PREFIX_VEX_0F3846 */
5930 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5933 /* PREFIX_VEX_0F3847 */
5937 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
5940 /* PREFIX_VEX_0F3858 */
5944 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5947 /* PREFIX_VEX_0F3859 */
5951 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5954 /* PREFIX_VEX_0F385A */
5958 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5961 /* PREFIX_VEX_0F3878 */
5965 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5968 /* PREFIX_VEX_0F3879 */
5972 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5975 /* PREFIX_VEX_0F388C */
5979 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5982 /* PREFIX_VEX_0F388E */
5986 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5989 /* PREFIX_VEX_0F3890 */
5993 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
5996 /* PREFIX_VEX_0F3891 */
6000 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6003 /* PREFIX_VEX_0F3892 */
6007 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6010 /* PREFIX_VEX_0F3893 */
6014 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6017 /* PREFIX_VEX_0F3896 */
6021 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6024 /* PREFIX_VEX_0F3897 */
6028 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6031 /* PREFIX_VEX_0F3898 */
6035 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6038 /* PREFIX_VEX_0F3899 */
6042 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6045 /* PREFIX_VEX_0F389A */
6049 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6052 /* PREFIX_VEX_0F389B */
6056 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6059 /* PREFIX_VEX_0F389C */
6063 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6066 /* PREFIX_VEX_0F389D */
6070 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6073 /* PREFIX_VEX_0F389E */
6077 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6080 /* PREFIX_VEX_0F389F */
6084 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6087 /* PREFIX_VEX_0F38A6 */
6091 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6095 /* PREFIX_VEX_0F38A7 */
6099 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F38A8 */
6106 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6109 /* PREFIX_VEX_0F38A9 */
6113 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6116 /* PREFIX_VEX_0F38AA */
6120 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6123 /* PREFIX_VEX_0F38AB */
6127 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6130 /* PREFIX_VEX_0F38AC */
6134 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6137 /* PREFIX_VEX_0F38AD */
6141 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6144 /* PREFIX_VEX_0F38AE */
6148 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6151 /* PREFIX_VEX_0F38AF */
6155 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6158 /* PREFIX_VEX_0F38B6 */
6162 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6165 /* PREFIX_VEX_0F38B7 */
6169 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6172 /* PREFIX_VEX_0F38B8 */
6176 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6179 /* PREFIX_VEX_0F38B9 */
6183 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6186 /* PREFIX_VEX_0F38BA */
6190 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6193 /* PREFIX_VEX_0F38BB */
6197 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6200 /* PREFIX_VEX_0F38BC */
6204 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6207 /* PREFIX_VEX_0F38BD */
6211 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6214 /* PREFIX_VEX_0F38BE */
6218 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6221 /* PREFIX_VEX_0F38BF */
6225 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6228 /* PREFIX_VEX_0F38CF */
6232 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6235 /* PREFIX_VEX_0F38DB */
6239 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6242 /* PREFIX_VEX_0F38DC */
6246 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6249 /* PREFIX_VEX_0F38DD */
6253 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6256 /* PREFIX_VEX_0F38DE */
6260 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6263 /* PREFIX_VEX_0F38DF */
6267 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6270 /* PREFIX_VEX_0F38F2 */
6272 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6275 /* PREFIX_VEX_0F38F3_REG_1 */
6277 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6280 /* PREFIX_VEX_0F38F3_REG_2 */
6282 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6285 /* PREFIX_VEX_0F38F3_REG_3 */
6287 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6290 /* PREFIX_VEX_0F38F5 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6293 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6298 /* PREFIX_VEX_0F38F6 */
6303 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6306 /* PREFIX_VEX_0F38F7 */
6308 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6309 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6310 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6314 /* PREFIX_VEX_0F3A00 */
6318 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6321 /* PREFIX_VEX_0F3A01 */
6325 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6328 /* PREFIX_VEX_0F3A02 */
6332 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6335 /* PREFIX_VEX_0F3A04 */
6339 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6342 /* PREFIX_VEX_0F3A05 */
6346 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6349 /* PREFIX_VEX_0F3A06 */
6353 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6356 /* PREFIX_VEX_0F3A08 */
6360 { "vroundps", { XM
, EXx
, Ib
}, 0 },
6363 /* PREFIX_VEX_0F3A09 */
6367 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
6370 /* PREFIX_VEX_0F3A0A */
6374 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
6377 /* PREFIX_VEX_0F3A0B */
6381 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
6384 /* PREFIX_VEX_0F3A0C */
6388 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
6391 /* PREFIX_VEX_0F3A0D */
6395 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
6398 /* PREFIX_VEX_0F3A0E */
6402 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
6405 /* PREFIX_VEX_0F3A0F */
6409 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
6412 /* PREFIX_VEX_0F3A14 */
6416 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6419 /* PREFIX_VEX_0F3A15 */
6423 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6426 /* PREFIX_VEX_0F3A16 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6433 /* PREFIX_VEX_0F3A17 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6440 /* PREFIX_VEX_0F3A18 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6447 /* PREFIX_VEX_0F3A19 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6454 /* PREFIX_VEX_0F3A1D */
6458 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6461 /* PREFIX_VEX_0F3A20 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6468 /* PREFIX_VEX_0F3A21 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6475 /* PREFIX_VEX_0F3A22 */
6479 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6482 /* PREFIX_VEX_0F3A30 */
6486 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6489 /* PREFIX_VEX_0F3A31 */
6493 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6496 /* PREFIX_VEX_0F3A32 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6503 /* PREFIX_VEX_0F3A33 */
6507 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6510 /* PREFIX_VEX_0F3A38 */
6514 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6517 /* PREFIX_VEX_0F3A39 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6524 /* PREFIX_VEX_0F3A40 */
6528 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
6531 /* PREFIX_VEX_0F3A41 */
6535 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6538 /* PREFIX_VEX_0F3A42 */
6542 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
6545 /* PREFIX_VEX_0F3A44 */
6549 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6552 /* PREFIX_VEX_0F3A46 */
6556 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6559 /* PREFIX_VEX_0F3A48 */
6563 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6566 /* PREFIX_VEX_0F3A49 */
6570 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6573 /* PREFIX_VEX_0F3A4A */
6577 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6580 /* PREFIX_VEX_0F3A4B */
6584 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6587 /* PREFIX_VEX_0F3A4C */
6591 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6594 /* PREFIX_VEX_0F3A5C */
6598 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6601 /* PREFIX_VEX_0F3A5D */
6605 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6608 /* PREFIX_VEX_0F3A5E */
6612 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6615 /* PREFIX_VEX_0F3A5F */
6619 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6622 /* PREFIX_VEX_0F3A60 */
6626 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6630 /* PREFIX_VEX_0F3A61 */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6637 /* PREFIX_VEX_0F3A62 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6644 /* PREFIX_VEX_0F3A63 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6651 /* PREFIX_VEX_0F3A68 */
6655 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6658 /* PREFIX_VEX_0F3A69 */
6662 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6665 /* PREFIX_VEX_0F3A6A */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6672 /* PREFIX_VEX_0F3A6B */
6676 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6679 /* PREFIX_VEX_0F3A6C */
6683 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6686 /* PREFIX_VEX_0F3A6D */
6690 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6693 /* PREFIX_VEX_0F3A6E */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6700 /* PREFIX_VEX_0F3A6F */
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6707 /* PREFIX_VEX_0F3A78 */
6711 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6714 /* PREFIX_VEX_0F3A79 */
6718 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6721 /* PREFIX_VEX_0F3A7A */
6725 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6728 /* PREFIX_VEX_0F3A7B */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6735 /* PREFIX_VEX_0F3A7C */
6739 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6743 /* PREFIX_VEX_0F3A7D */
6747 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6750 /* PREFIX_VEX_0F3A7E */
6754 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6757 /* PREFIX_VEX_0F3A7F */
6761 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6764 /* PREFIX_VEX_0F3ACE */
6768 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6771 /* PREFIX_VEX_0F3ACF */
6775 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6778 /* PREFIX_VEX_0F3ADF */
6782 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6785 /* PREFIX_VEX_0F3AF0 */
6790 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6793 #include "i386-dis-evex-prefix.h"
6796 static const struct dis386 x86_64_table
[][2] = {
6799 { "pushP", { es
}, 0 },
6804 { "popP", { es
}, 0 },
6809 { "pushP", { cs
}, 0 },
6814 { "pushP", { ss
}, 0 },
6819 { "popP", { ss
}, 0 },
6824 { "pushP", { ds
}, 0 },
6829 { "popP", { ds
}, 0 },
6834 { "daa", { XX
}, 0 },
6839 { "das", { XX
}, 0 },
6844 { "aaa", { XX
}, 0 },
6849 { "aas", { XX
}, 0 },
6854 { "pushaP", { XX
}, 0 },
6859 { "popaP", { XX
}, 0 },
6864 { MOD_TABLE (MOD_62_32BIT
) },
6865 { EVEX_TABLE (EVEX_0F
) },
6870 { "arpl", { Ew
, Gw
}, 0 },
6871 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
6876 { "ins{R|}", { Yzr
, indirDX
}, 0 },
6877 { "ins{G|}", { Yzr
, indirDX
}, 0 },
6882 { "outs{R|}", { indirDXr
, Xz
}, 0 },
6883 { "outs{G|}", { indirDXr
, Xz
}, 0 },
6888 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6889 { REG_TABLE (REG_80
) },
6894 { "Jcall{T|}", { Ap
}, 0 },
6899 { MOD_TABLE (MOD_C4_32BIT
) },
6900 { VEX_C4_TABLE (VEX_0F
) },
6905 { MOD_TABLE (MOD_C5_32BIT
) },
6906 { VEX_C5_TABLE (VEX_0F
) },
6911 { "into", { XX
}, 0 },
6916 { "aam", { Ib
}, 0 },
6921 { "aad", { Ib
}, 0 },
6926 { "callP", { Jv
, BND
}, 0 },
6927 { "call@", { Jv
, BND
}, 0 }
6932 { "jmpP", { Jv
, BND
}, 0 },
6933 { "jmp@", { Jv
, BND
}, 0 }
6938 { "Jjmp{T|}", { Ap
}, 0 },
6941 /* X86_64_0F01_REG_0 */
6943 { "sgdt{Q|IQ}", { M
}, 0 },
6944 { "sgdt", { M
}, 0 },
6947 /* X86_64_0F01_REG_1 */
6949 { "sidt{Q|IQ}", { M
}, 0 },
6950 { "sidt", { M
}, 0 },
6953 /* X86_64_0F01_REG_2 */
6955 { "lgdt{Q|Q}", { M
}, 0 },
6956 { "lgdt", { M
}, 0 },
6959 /* X86_64_0F01_REG_3 */
6961 { "lidt{Q|Q}", { M
}, 0 },
6962 { "lidt", { M
}, 0 },
6966 static const struct dis386 three_byte_table
[][256] = {
6968 /* THREE_BYTE_0F38 */
6971 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
6972 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
6973 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
6974 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
6975 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
6976 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
6977 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
6978 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
6980 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
6981 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
6982 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
6983 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
6989 { PREFIX_TABLE (PREFIX_0F3810
) },
6993 { PREFIX_TABLE (PREFIX_0F3814
) },
6994 { PREFIX_TABLE (PREFIX_0F3815
) },
6996 { PREFIX_TABLE (PREFIX_0F3817
) },
7002 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7003 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7004 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7007 { PREFIX_TABLE (PREFIX_0F3820
) },
7008 { PREFIX_TABLE (PREFIX_0F3821
) },
7009 { PREFIX_TABLE (PREFIX_0F3822
) },
7010 { PREFIX_TABLE (PREFIX_0F3823
) },
7011 { PREFIX_TABLE (PREFIX_0F3824
) },
7012 { PREFIX_TABLE (PREFIX_0F3825
) },
7016 { PREFIX_TABLE (PREFIX_0F3828
) },
7017 { PREFIX_TABLE (PREFIX_0F3829
) },
7018 { PREFIX_TABLE (PREFIX_0F382A
) },
7019 { PREFIX_TABLE (PREFIX_0F382B
) },
7025 { PREFIX_TABLE (PREFIX_0F3830
) },
7026 { PREFIX_TABLE (PREFIX_0F3831
) },
7027 { PREFIX_TABLE (PREFIX_0F3832
) },
7028 { PREFIX_TABLE (PREFIX_0F3833
) },
7029 { PREFIX_TABLE (PREFIX_0F3834
) },
7030 { PREFIX_TABLE (PREFIX_0F3835
) },
7032 { PREFIX_TABLE (PREFIX_0F3837
) },
7034 { PREFIX_TABLE (PREFIX_0F3838
) },
7035 { PREFIX_TABLE (PREFIX_0F3839
) },
7036 { PREFIX_TABLE (PREFIX_0F383A
) },
7037 { PREFIX_TABLE (PREFIX_0F383B
) },
7038 { PREFIX_TABLE (PREFIX_0F383C
) },
7039 { PREFIX_TABLE (PREFIX_0F383D
) },
7040 { PREFIX_TABLE (PREFIX_0F383E
) },
7041 { PREFIX_TABLE (PREFIX_0F383F
) },
7043 { PREFIX_TABLE (PREFIX_0F3840
) },
7044 { PREFIX_TABLE (PREFIX_0F3841
) },
7115 { PREFIX_TABLE (PREFIX_0F3880
) },
7116 { PREFIX_TABLE (PREFIX_0F3881
) },
7117 { PREFIX_TABLE (PREFIX_0F3882
) },
7196 { PREFIX_TABLE (PREFIX_0F38C8
) },
7197 { PREFIX_TABLE (PREFIX_0F38C9
) },
7198 { PREFIX_TABLE (PREFIX_0F38CA
) },
7199 { PREFIX_TABLE (PREFIX_0F38CB
) },
7200 { PREFIX_TABLE (PREFIX_0F38CC
) },
7201 { PREFIX_TABLE (PREFIX_0F38CD
) },
7203 { PREFIX_TABLE (PREFIX_0F38CF
) },
7217 { PREFIX_TABLE (PREFIX_0F38DB
) },
7218 { PREFIX_TABLE (PREFIX_0F38DC
) },
7219 { PREFIX_TABLE (PREFIX_0F38DD
) },
7220 { PREFIX_TABLE (PREFIX_0F38DE
) },
7221 { PREFIX_TABLE (PREFIX_0F38DF
) },
7241 { PREFIX_TABLE (PREFIX_0F38F0
) },
7242 { PREFIX_TABLE (PREFIX_0F38F1
) },
7246 { PREFIX_TABLE (PREFIX_0F38F5
) },
7247 { PREFIX_TABLE (PREFIX_0F38F6
) },
7250 { PREFIX_TABLE (PREFIX_0F38F8
) },
7251 { PREFIX_TABLE (PREFIX_0F38F9
) },
7259 /* THREE_BYTE_0F3A */
7271 { PREFIX_TABLE (PREFIX_0F3A08
) },
7272 { PREFIX_TABLE (PREFIX_0F3A09
) },
7273 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7274 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7275 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7276 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7277 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7278 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7284 { PREFIX_TABLE (PREFIX_0F3A14
) },
7285 { PREFIX_TABLE (PREFIX_0F3A15
) },
7286 { PREFIX_TABLE (PREFIX_0F3A16
) },
7287 { PREFIX_TABLE (PREFIX_0F3A17
) },
7298 { PREFIX_TABLE (PREFIX_0F3A20
) },
7299 { PREFIX_TABLE (PREFIX_0F3A21
) },
7300 { PREFIX_TABLE (PREFIX_0F3A22
) },
7334 { PREFIX_TABLE (PREFIX_0F3A40
) },
7335 { PREFIX_TABLE (PREFIX_0F3A41
) },
7336 { PREFIX_TABLE (PREFIX_0F3A42
) },
7338 { PREFIX_TABLE (PREFIX_0F3A44
) },
7370 { PREFIX_TABLE (PREFIX_0F3A60
) },
7371 { PREFIX_TABLE (PREFIX_0F3A61
) },
7372 { PREFIX_TABLE (PREFIX_0F3A62
) },
7373 { PREFIX_TABLE (PREFIX_0F3A63
) },
7491 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7493 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7494 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7512 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7552 static const struct dis386 xop_table
[][256] = {
7705 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7706 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7707 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7715 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7716 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7723 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7724 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7725 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7733 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7734 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7738 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7739 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7742 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7760 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7772 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7773 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7774 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7775 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7785 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7786 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7787 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7821 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7822 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7823 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7848 { REG_TABLE (REG_XOP_TBM_01
) },
7849 { REG_TABLE (REG_XOP_TBM_02
) },
7867 { REG_TABLE (REG_XOP_LWPCB
) },
7991 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7992 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7993 { "vfrczss", { XM
, EXd
}, 0 },
7994 { "vfrczsd", { XM
, EXq
}, 0 },
8009 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8010 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8011 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8012 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8013 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8014 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8015 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8016 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8018 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8019 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8020 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8021 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8064 { "vphaddbw", { XM
, EXxmm
}, 0 },
8065 { "vphaddbd", { XM
, EXxmm
}, 0 },
8066 { "vphaddbq", { XM
, EXxmm
}, 0 },
8069 { "vphaddwd", { XM
, EXxmm
}, 0 },
8070 { "vphaddwq", { XM
, EXxmm
}, 0 },
8075 { "vphadddq", { XM
, EXxmm
}, 0 },
8082 { "vphaddubw", { XM
, EXxmm
}, 0 },
8083 { "vphaddubd", { XM
, EXxmm
}, 0 },
8084 { "vphaddubq", { XM
, EXxmm
}, 0 },
8087 { "vphadduwd", { XM
, EXxmm
}, 0 },
8088 { "vphadduwq", { XM
, EXxmm
}, 0 },
8093 { "vphaddudq", { XM
, EXxmm
}, 0 },
8100 { "vphsubbw", { XM
, EXxmm
}, 0 },
8101 { "vphsubwd", { XM
, EXxmm
}, 0 },
8102 { "vphsubdq", { XM
, EXxmm
}, 0 },
8156 { "bextrS", { Gdq
, Edq
, Id
}, 0 },
8158 { REG_TABLE (REG_XOP_LWP
) },
8428 static const struct dis386 vex_table
[][256] = {
8450 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8451 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8453 { MOD_TABLE (MOD_VEX_0F13
) },
8454 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
8455 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
8456 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8457 { MOD_TABLE (MOD_VEX_0F17
) },
8477 { "vmovapX", { XM
, EXx
}, 0 },
8478 { "vmovapX", { EXxS
, XM
}, 0 },
8479 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8480 { MOD_TABLE (MOD_VEX_0F2B
) },
8481 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8505 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8506 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8522 { MOD_TABLE (MOD_VEX_0F50
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8524 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8525 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8526 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8527 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8528 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8529 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8531 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8532 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8533 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8534 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8559 { REG_TABLE (REG_VEX_0F71
) },
8560 { REG_TABLE (REG_VEX_0F72
) },
8561 { REG_TABLE (REG_VEX_0F73
) },
8562 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8564 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8571 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8594 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8603 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8627 { REG_TABLE (REG_VEX_0FAE
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8654 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8666 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8748 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8822 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8996 { REG_TABLE (REG_VEX_0F38F3
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9014 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9068 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9086 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9131 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9245 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9246 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9304 #include "i386-dis-evex.h"
9306 static const struct dis386 vex_len_table
[][2] = {
9307 /* VEX_LEN_0F12_P_0_M_0 */
9309 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
9312 /* VEX_LEN_0F12_P_0_M_1 */
9314 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
9317 /* VEX_LEN_0F12_P_2 */
9319 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
9322 /* VEX_LEN_0F13_M_0 */
9324 { "vmovlpX", { EXq
, XM
}, 0 },
9327 /* VEX_LEN_0F16_P_0_M_0 */
9329 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
9332 /* VEX_LEN_0F16_P_0_M_1 */
9334 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
9337 /* VEX_LEN_0F16_P_2 */
9339 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
9342 /* VEX_LEN_0F17_M_0 */
9344 { "vmovhpX", { EXq
, XM
}, 0 },
9347 /* VEX_LEN_0F41_P_0 */
9350 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9352 /* VEX_LEN_0F41_P_2 */
9355 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9357 /* VEX_LEN_0F42_P_0 */
9360 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9362 /* VEX_LEN_0F42_P_2 */
9365 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9367 /* VEX_LEN_0F44_P_0 */
9369 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9371 /* VEX_LEN_0F44_P_2 */
9373 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9375 /* VEX_LEN_0F45_P_0 */
9378 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9380 /* VEX_LEN_0F45_P_2 */
9383 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9385 /* VEX_LEN_0F46_P_0 */
9388 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9390 /* VEX_LEN_0F46_P_2 */
9393 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9395 /* VEX_LEN_0F47_P_0 */
9398 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9400 /* VEX_LEN_0F47_P_2 */
9403 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9405 /* VEX_LEN_0F4A_P_0 */
9408 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9410 /* VEX_LEN_0F4A_P_2 */
9413 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9415 /* VEX_LEN_0F4B_P_0 */
9418 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9420 /* VEX_LEN_0F4B_P_2 */
9423 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9426 /* VEX_LEN_0F6E_P_2 */
9428 { "vmovK", { XMScalar
, Edq
}, 0 },
9431 /* VEX_LEN_0F77_P_1 */
9433 { "vzeroupper", { XX
}, 0 },
9434 { "vzeroall", { XX
}, 0 },
9437 /* VEX_LEN_0F7E_P_1 */
9439 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
9442 /* VEX_LEN_0F7E_P_2 */
9444 { "vmovK", { Edq
, XMScalar
}, 0 },
9447 /* VEX_LEN_0F90_P_0 */
9449 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9452 /* VEX_LEN_0F90_P_2 */
9454 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9457 /* VEX_LEN_0F91_P_0 */
9459 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9462 /* VEX_LEN_0F91_P_2 */
9464 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9467 /* VEX_LEN_0F92_P_0 */
9469 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9472 /* VEX_LEN_0F92_P_2 */
9474 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9477 /* VEX_LEN_0F92_P_3 */
9479 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0
) },
9482 /* VEX_LEN_0F93_P_0 */
9484 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9487 /* VEX_LEN_0F93_P_2 */
9489 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9492 /* VEX_LEN_0F93_P_3 */
9494 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0
) },
9497 /* VEX_LEN_0F98_P_0 */
9499 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9502 /* VEX_LEN_0F98_P_2 */
9504 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9507 /* VEX_LEN_0F99_P_0 */
9509 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9512 /* VEX_LEN_0F99_P_2 */
9514 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9517 /* VEX_LEN_0FAE_R_2_M_0 */
9519 { "vldmxcsr", { Md
}, 0 },
9522 /* VEX_LEN_0FAE_R_3_M_0 */
9524 { "vstmxcsr", { Md
}, 0 },
9527 /* VEX_LEN_0FC4_P_2 */
9529 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
9532 /* VEX_LEN_0FC5_P_2 */
9534 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
9537 /* VEX_LEN_0FD6_P_2 */
9539 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
9542 /* VEX_LEN_0FF7_P_2 */
9544 { "vmaskmovdqu", { XM
, XS
}, 0 },
9547 /* VEX_LEN_0F3816_P_2 */
9550 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9553 /* VEX_LEN_0F3819_P_2 */
9556 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9559 /* VEX_LEN_0F381A_P_2_M_0 */
9562 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9565 /* VEX_LEN_0F3836_P_2 */
9568 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9571 /* VEX_LEN_0F3841_P_2 */
9573 { "vphminposuw", { XM
, EXx
}, 0 },
9576 /* VEX_LEN_0F385A_P_2_M_0 */
9579 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9582 /* VEX_LEN_0F38DB_P_2 */
9584 { "vaesimc", { XM
, EXx
}, 0 },
9587 /* VEX_LEN_0F38F2_P_0 */
9589 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9592 /* VEX_LEN_0F38F3_R_1_P_0 */
9594 { "blsrS", { VexGdq
, Edq
}, 0 },
9597 /* VEX_LEN_0F38F3_R_2_P_0 */
9599 { "blsmskS", { VexGdq
, Edq
}, 0 },
9602 /* VEX_LEN_0F38F3_R_3_P_0 */
9604 { "blsiS", { VexGdq
, Edq
}, 0 },
9607 /* VEX_LEN_0F38F5_P_0 */
9609 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9612 /* VEX_LEN_0F38F5_P_1 */
9614 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9617 /* VEX_LEN_0F38F5_P_3 */
9619 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9622 /* VEX_LEN_0F38F6_P_3 */
9624 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9627 /* VEX_LEN_0F38F7_P_0 */
9629 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9632 /* VEX_LEN_0F38F7_P_1 */
9634 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
9637 /* VEX_LEN_0F38F7_P_2 */
9639 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
9642 /* VEX_LEN_0F38F7_P_3 */
9644 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
9647 /* VEX_LEN_0F3A00_P_2 */
9650 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9653 /* VEX_LEN_0F3A01_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9659 /* VEX_LEN_0F3A06_P_2 */
9662 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9665 /* VEX_LEN_0F3A14_P_2 */
9667 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
9670 /* VEX_LEN_0F3A15_P_2 */
9672 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
9675 /* VEX_LEN_0F3A16_P_2 */
9677 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
9680 /* VEX_LEN_0F3A17_P_2 */
9682 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
9685 /* VEX_LEN_0F3A18_P_2 */
9688 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9691 /* VEX_LEN_0F3A19_P_2 */
9694 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9697 /* VEX_LEN_0F3A20_P_2 */
9699 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
9702 /* VEX_LEN_0F3A21_P_2 */
9704 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
9707 /* VEX_LEN_0F3A22_P_2 */
9709 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
9712 /* VEX_LEN_0F3A30_P_2 */
9714 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9717 /* VEX_LEN_0F3A31_P_2 */
9719 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
9722 /* VEX_LEN_0F3A32_P_2 */
9724 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9727 /* VEX_LEN_0F3A33_P_2 */
9729 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
9732 /* VEX_LEN_0F3A38_P_2 */
9735 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9738 /* VEX_LEN_0F3A39_P_2 */
9741 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9744 /* VEX_LEN_0F3A41_P_2 */
9746 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
9749 /* VEX_LEN_0F3A46_P_2 */
9752 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9755 /* VEX_LEN_0F3A60_P_2 */
9757 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9760 /* VEX_LEN_0F3A61_P_2 */
9762 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
9765 /* VEX_LEN_0F3A62_P_2 */
9767 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
9770 /* VEX_LEN_0F3A63_P_2 */
9772 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
9775 /* VEX_LEN_0F3A6A_P_2 */
9777 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9780 /* VEX_LEN_0F3A6B_P_2 */
9782 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9785 /* VEX_LEN_0F3A6E_P_2 */
9787 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9790 /* VEX_LEN_0F3A6F_P_2 */
9792 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9795 /* VEX_LEN_0F3A7A_P_2 */
9797 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9800 /* VEX_LEN_0F3A7B_P_2 */
9802 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9805 /* VEX_LEN_0F3A7E_P_2 */
9807 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
9810 /* VEX_LEN_0F3A7F_P_2 */
9812 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
9815 /* VEX_LEN_0F3ADF_P_2 */
9817 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
9820 /* VEX_LEN_0F3AF0_P_3 */
9822 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
9825 /* VEX_LEN_0FXOP_08_CC */
9827 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9830 /* VEX_LEN_0FXOP_08_CD */
9832 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9835 /* VEX_LEN_0FXOP_08_CE */
9837 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9840 /* VEX_LEN_0FXOP_08_CF */
9842 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9845 /* VEX_LEN_0FXOP_08_EC */
9847 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9850 /* VEX_LEN_0FXOP_08_ED */
9852 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9855 /* VEX_LEN_0FXOP_08_EE */
9857 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9860 /* VEX_LEN_0FXOP_08_EF */
9862 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
9865 /* VEX_LEN_0FXOP_09_80 */
9867 { "vfrczps", { XM
, EXxmm
}, 0 },
9868 { "vfrczps", { XM
, EXymmq
}, 0 },
9871 /* VEX_LEN_0FXOP_09_81 */
9873 { "vfrczpd", { XM
, EXxmm
}, 0 },
9874 { "vfrczpd", { XM
, EXymmq
}, 0 },
9878 #include "i386-dis-evex-len.h"
9880 static const struct dis386 vex_w_table
[][2] = {
9882 /* VEX_W_0F41_P_0_LEN_1 */
9883 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
9884 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
9887 /* VEX_W_0F41_P_2_LEN_1 */
9888 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
9889 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
9892 /* VEX_W_0F42_P_0_LEN_1 */
9893 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
9894 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
9897 /* VEX_W_0F42_P_2_LEN_1 */
9898 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
9899 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
9902 /* VEX_W_0F44_P_0_LEN_0 */
9903 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
9904 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
9907 /* VEX_W_0F44_P_2_LEN_0 */
9908 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
9909 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
9912 /* VEX_W_0F45_P_0_LEN_1 */
9913 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
9914 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
9917 /* VEX_W_0F45_P_2_LEN_1 */
9918 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
9919 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
9922 /* VEX_W_0F46_P_0_LEN_1 */
9923 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
9924 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
9927 /* VEX_W_0F46_P_2_LEN_1 */
9928 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
9929 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
9932 /* VEX_W_0F47_P_0_LEN_1 */
9933 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
9934 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
9937 /* VEX_W_0F47_P_2_LEN_1 */
9938 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
9939 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
9942 /* VEX_W_0F4A_P_0_LEN_1 */
9943 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
9944 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
9947 /* VEX_W_0F4A_P_2_LEN_1 */
9948 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
9949 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
9952 /* VEX_W_0F4B_P_0_LEN_1 */
9953 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
9954 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
9957 /* VEX_W_0F4B_P_2_LEN_1 */
9958 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
9961 /* VEX_W_0F90_P_0_LEN_0 */
9962 { "kmovw", { MaskG
, MaskE
}, 0 },
9963 { "kmovq", { MaskG
, MaskE
}, 0 },
9966 /* VEX_W_0F90_P_2_LEN_0 */
9967 { "kmovb", { MaskG
, MaskBDE
}, 0 },
9968 { "kmovd", { MaskG
, MaskBDE
}, 0 },
9971 /* VEX_W_0F91_P_0_LEN_0 */
9972 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
9973 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
9976 /* VEX_W_0F91_P_2_LEN_0 */
9977 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
9978 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
9981 /* VEX_W_0F92_P_0_LEN_0 */
9982 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
9985 /* VEX_W_0F92_P_2_LEN_0 */
9986 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
9989 /* VEX_W_0F93_P_0_LEN_0 */
9990 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
9993 /* VEX_W_0F93_P_2_LEN_0 */
9994 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
9997 /* VEX_W_0F98_P_0_LEN_0 */
9998 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
9999 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10002 /* VEX_W_0F98_P_2_LEN_0 */
10003 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10004 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10007 /* VEX_W_0F99_P_0_LEN_0 */
10008 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10009 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10012 /* VEX_W_0F99_P_2_LEN_0 */
10013 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10014 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10017 /* VEX_W_0F380C_P_2 */
10018 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
10021 /* VEX_W_0F380D_P_2 */
10022 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
10025 /* VEX_W_0F380E_P_2 */
10026 { "vtestps", { XM
, EXx
}, 0 },
10029 /* VEX_W_0F380F_P_2 */
10030 { "vtestpd", { XM
, EXx
}, 0 },
10033 /* VEX_W_0F3816_P_2 */
10034 { "vpermps", { XM
, Vex
, EXx
}, 0 },
10037 /* VEX_W_0F3818_P_2 */
10038 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
10041 /* VEX_W_0F3819_P_2 */
10042 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
10045 /* VEX_W_0F381A_P_2_M_0 */
10046 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
10049 /* VEX_W_0F382C_P_2_M_0 */
10050 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
10053 /* VEX_W_0F382D_P_2_M_0 */
10054 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
10057 /* VEX_W_0F382E_P_2_M_0 */
10058 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
10061 /* VEX_W_0F382F_P_2_M_0 */
10062 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
10065 /* VEX_W_0F3836_P_2 */
10066 { "vpermd", { XM
, Vex
, EXx
}, 0 },
10069 /* VEX_W_0F3846_P_2 */
10070 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
10073 /* VEX_W_0F3858_P_2 */
10074 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
10077 /* VEX_W_0F3859_P_2 */
10078 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
10081 /* VEX_W_0F385A_P_2_M_0 */
10082 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
10085 /* VEX_W_0F3878_P_2 */
10086 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
10089 /* VEX_W_0F3879_P_2 */
10090 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
10093 /* VEX_W_0F38CF_P_2 */
10094 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
10097 /* VEX_W_0F3A00_P_2 */
10099 { "vpermq", { XM
, EXx
, Ib
}, 0 },
10102 /* VEX_W_0F3A01_P_2 */
10104 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
10107 /* VEX_W_0F3A02_P_2 */
10108 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
10111 /* VEX_W_0F3A04_P_2 */
10112 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
10115 /* VEX_W_0F3A05_P_2 */
10116 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
10119 /* VEX_W_0F3A06_P_2 */
10120 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10123 /* VEX_W_0F3A18_P_2 */
10124 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10127 /* VEX_W_0F3A19_P_2 */
10128 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
10131 /* VEX_W_0F3A30_P_2_LEN_0 */
10132 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
10133 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
10136 /* VEX_W_0F3A31_P_2_LEN_0 */
10137 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
10138 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
10141 /* VEX_W_0F3A32_P_2_LEN_0 */
10142 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
10143 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
10146 /* VEX_W_0F3A33_P_2_LEN_0 */
10147 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
10148 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
10151 /* VEX_W_0F3A38_P_2 */
10152 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
10155 /* VEX_W_0F3A39_P_2 */
10156 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
10159 /* VEX_W_0F3A46_P_2 */
10160 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
10163 /* VEX_W_0F3A48_P_2 */
10164 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10165 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10168 /* VEX_W_0F3A49_P_2 */
10169 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10170 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
10173 /* VEX_W_0F3A4A_P_2 */
10174 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10177 /* VEX_W_0F3A4B_P_2 */
10178 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10181 /* VEX_W_0F3A4C_P_2 */
10182 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
10185 /* VEX_W_0F3ACE_P_2 */
10187 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10190 /* VEX_W_0F3ACF_P_2 */
10192 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
10195 #include "i386-dis-evex-w.h"
10198 static const struct dis386 mod_table
[][2] = {
10201 { "leaS", { Gv
, M
}, 0 },
10206 { RM_TABLE (RM_C6_REG_7
) },
10211 { RM_TABLE (RM_C7_REG_7
) },
10215 { "Jcall^", { indirEp
}, 0 },
10219 { "Jjmp^", { indirEp
}, 0 },
10222 /* MOD_0F01_REG_0 */
10223 { X86_64_TABLE (X86_64_0F01_REG_0
) },
10224 { RM_TABLE (RM_0F01_REG_0
) },
10227 /* MOD_0F01_REG_1 */
10228 { X86_64_TABLE (X86_64_0F01_REG_1
) },
10229 { RM_TABLE (RM_0F01_REG_1
) },
10232 /* MOD_0F01_REG_2 */
10233 { X86_64_TABLE (X86_64_0F01_REG_2
) },
10234 { RM_TABLE (RM_0F01_REG_2
) },
10237 /* MOD_0F01_REG_3 */
10238 { X86_64_TABLE (X86_64_0F01_REG_3
) },
10239 { RM_TABLE (RM_0F01_REG_3
) },
10242 /* MOD_0F01_REG_5 */
10243 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0
) },
10244 { RM_TABLE (RM_0F01_REG_5_MOD_3
) },
10247 /* MOD_0F01_REG_7 */
10248 { "invlpg", { Mb
}, 0 },
10249 { RM_TABLE (RM_0F01_REG_7_MOD_3
) },
10252 /* MOD_0F12_PREFIX_0 */
10253 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
10254 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
10258 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
10261 /* MOD_0F16_PREFIX_0 */
10262 { "movhps", { XM
, EXq
}, 0 },
10263 { "movlhps", { XM
, EXq
}, 0 },
10267 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
10270 /* MOD_0F18_REG_0 */
10271 { "prefetchnta", { Mb
}, 0 },
10274 /* MOD_0F18_REG_1 */
10275 { "prefetcht0", { Mb
}, 0 },
10278 /* MOD_0F18_REG_2 */
10279 { "prefetcht1", { Mb
}, 0 },
10282 /* MOD_0F18_REG_3 */
10283 { "prefetcht2", { Mb
}, 0 },
10286 /* MOD_0F18_REG_4 */
10287 { "nop/reserved", { Mb
}, 0 },
10290 /* MOD_0F18_REG_5 */
10291 { "nop/reserved", { Mb
}, 0 },
10294 /* MOD_0F18_REG_6 */
10295 { "nop/reserved", { Mb
}, 0 },
10298 /* MOD_0F18_REG_7 */
10299 { "nop/reserved", { Mb
}, 0 },
10302 /* MOD_0F1A_PREFIX_0 */
10303 { "bndldx", { Gbnd
, Mv_bnd
}, 0 },
10304 { "nopQ", { Ev
}, 0 },
10307 /* MOD_0F1B_PREFIX_0 */
10308 { "bndstx", { Mv_bnd
, Gbnd
}, 0 },
10309 { "nopQ", { Ev
}, 0 },
10312 /* MOD_0F1B_PREFIX_1 */
10313 { "bndmk", { Gbnd
, Mv_bnd
}, 0 },
10314 { "nopQ", { Ev
}, 0 },
10317 /* MOD_0F1C_PREFIX_0 */
10318 { REG_TABLE (REG_0F1C_P_0_MOD_0
) },
10319 { "nopQ", { Ev
}, 0 },
10322 /* MOD_0F1E_PREFIX_1 */
10323 { "nopQ", { Ev
}, 0 },
10324 { REG_TABLE (REG_0F1E_P_1_MOD_3
) },
10329 { "movL", { Rd
, Td
}, 0 },
10334 { "movL", { Td
, Rd
}, 0 },
10337 /* MOD_0F2B_PREFIX_0 */
10338 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
10341 /* MOD_0F2B_PREFIX_1 */
10342 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
10345 /* MOD_0F2B_PREFIX_2 */
10346 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
10349 /* MOD_0F2B_PREFIX_3 */
10350 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
10355 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
10358 /* MOD_0F71_REG_2 */
10360 { "psrlw", { MS
, Ib
}, 0 },
10363 /* MOD_0F71_REG_4 */
10365 { "psraw", { MS
, Ib
}, 0 },
10368 /* MOD_0F71_REG_6 */
10370 { "psllw", { MS
, Ib
}, 0 },
10373 /* MOD_0F72_REG_2 */
10375 { "psrld", { MS
, Ib
}, 0 },
10378 /* MOD_0F72_REG_4 */
10380 { "psrad", { MS
, Ib
}, 0 },
10383 /* MOD_0F72_REG_6 */
10385 { "pslld", { MS
, Ib
}, 0 },
10388 /* MOD_0F73_REG_2 */
10390 { "psrlq", { MS
, Ib
}, 0 },
10393 /* MOD_0F73_REG_3 */
10395 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
10398 /* MOD_0F73_REG_6 */
10400 { "psllq", { MS
, Ib
}, 0 },
10403 /* MOD_0F73_REG_7 */
10405 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
10408 /* MOD_0FAE_REG_0 */
10409 { "fxsave", { FXSAVE
}, 0 },
10410 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3
) },
10413 /* MOD_0FAE_REG_1 */
10414 { "fxrstor", { FXSAVE
}, 0 },
10415 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3
) },
10418 /* MOD_0FAE_REG_2 */
10419 { "ldmxcsr", { Md
}, 0 },
10420 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3
) },
10423 /* MOD_0FAE_REG_3 */
10424 { "stmxcsr", { Md
}, 0 },
10425 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3
) },
10428 /* MOD_0FAE_REG_4 */
10429 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0
) },
10430 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3
) },
10433 /* MOD_0FAE_REG_5 */
10434 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0
) },
10435 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3
) },
10438 /* MOD_0FAE_REG_6 */
10439 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0
) },
10440 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3
) },
10443 /* MOD_0FAE_REG_7 */
10444 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0
) },
10445 { RM_TABLE (RM_0FAE_REG_7_MOD_3
) },
10449 { "lssS", { Gv
, Mp
}, 0 },
10453 { "lfsS", { Gv
, Mp
}, 0 },
10457 { "lgsS", { Gv
, Mp
}, 0 },
10461 { PREFIX_TABLE (PREFIX_0FC3_MOD_0
) },
10464 /* MOD_0FC7_REG_3 */
10465 { "xrstors", { FXSAVE
}, 0 },
10468 /* MOD_0FC7_REG_4 */
10469 { "xsavec", { FXSAVE
}, 0 },
10472 /* MOD_0FC7_REG_5 */
10473 { "xsaves", { FXSAVE
}, 0 },
10476 /* MOD_0FC7_REG_6 */
10477 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0
) },
10478 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3
) }
10481 /* MOD_0FC7_REG_7 */
10482 { "vmptrst", { Mq
}, 0 },
10483 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3
) }
10488 { "pmovmskb", { Gdq
, MS
}, 0 },
10491 /* MOD_0FE7_PREFIX_2 */
10492 { "movntdq", { Mx
, XM
}, 0 },
10495 /* MOD_0FF0_PREFIX_3 */
10496 { "lddqu", { XM
, M
}, 0 },
10499 /* MOD_0F382A_PREFIX_2 */
10500 { "movntdqa", { XM
, Mx
}, 0 },
10503 /* MOD_0F38F5_PREFIX_2 */
10504 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
10507 /* MOD_0F38F6_PREFIX_0 */
10508 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
10511 /* MOD_0F38F8_PREFIX_1 */
10512 { "enqcmds", { Gva
, M
}, PREFIX_OPCODE
},
10515 /* MOD_0F38F8_PREFIX_2 */
10516 { "movdir64b", { Gva
, M
}, PREFIX_OPCODE
},
10519 /* MOD_0F38F8_PREFIX_3 */
10520 { "enqcmd", { Gva
, M
}, PREFIX_OPCODE
},
10523 /* MOD_0F38F9_PREFIX_0 */
10524 { "movdiri", { Em
, Gv
}, PREFIX_OPCODE
},
10528 { "bound{S|}", { Gv
, Ma
}, 0 },
10529 { EVEX_TABLE (EVEX_0F
) },
10533 { "lesS", { Gv
, Mp
}, 0 },
10534 { VEX_C4_TABLE (VEX_0F
) },
10538 { "ldsS", { Gv
, Mp
}, 0 },
10539 { VEX_C5_TABLE (VEX_0F
) },
10542 /* MOD_VEX_0F12_PREFIX_0 */
10543 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
10544 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
10548 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
10551 /* MOD_VEX_0F16_PREFIX_0 */
10552 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
10553 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
10557 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
10561 { "vmovntpX", { Mx
, XM
}, 0 },
10564 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10566 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
10569 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10571 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
10574 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10576 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
10579 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10581 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
10584 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10586 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
10589 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10591 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
10594 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10596 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
10599 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10601 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
10604 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10606 { "knotw", { MaskG
, MaskR
}, 0 },
10609 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10611 { "knotq", { MaskG
, MaskR
}, 0 },
10614 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10616 { "knotb", { MaskG
, MaskR
}, 0 },
10619 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10621 { "knotd", { MaskG
, MaskR
}, 0 },
10624 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10626 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
10629 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10631 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
10634 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10636 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
10639 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10641 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
10644 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10646 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10649 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10651 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10654 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10656 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10659 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10661 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
10664 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10666 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
10669 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10671 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
10674 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10676 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
10679 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10681 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
10684 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10686 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
10689 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10691 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
10694 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10696 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
10699 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10701 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
10704 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10706 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
10709 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10711 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
10714 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10716 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
10721 { "vmovmskpX", { Gdq
, XS
}, 0 },
10724 /* MOD_VEX_0F71_REG_2 */
10726 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
10729 /* MOD_VEX_0F71_REG_4 */
10731 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
10734 /* MOD_VEX_0F71_REG_6 */
10736 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
10739 /* MOD_VEX_0F72_REG_2 */
10741 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
10744 /* MOD_VEX_0F72_REG_4 */
10746 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
10749 /* MOD_VEX_0F72_REG_6 */
10751 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
10754 /* MOD_VEX_0F73_REG_2 */
10756 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
10759 /* MOD_VEX_0F73_REG_3 */
10761 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
10764 /* MOD_VEX_0F73_REG_6 */
10766 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
10769 /* MOD_VEX_0F73_REG_7 */
10771 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
10774 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10775 { "kmovw", { Ew
, MaskG
}, 0 },
10779 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10780 { "kmovq", { Eq
, MaskG
}, 0 },
10784 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10785 { "kmovb", { Eb
, MaskG
}, 0 },
10789 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10790 { "kmovd", { Ed
, MaskG
}, 0 },
10794 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10796 { "kmovw", { MaskG
, Rdq
}, 0 },
10799 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10801 { "kmovb", { MaskG
, Rdq
}, 0 },
10804 /* MOD_VEX_0F92_P_3_LEN_0 */
10806 { "kmovK", { MaskG
, Rdq
}, 0 },
10809 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10811 { "kmovw", { Gdq
, MaskR
}, 0 },
10814 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10816 { "kmovb", { Gdq
, MaskR
}, 0 },
10819 /* MOD_VEX_0F93_P_3_LEN_0 */
10821 { "kmovK", { Gdq
, MaskR
}, 0 },
10824 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10826 { "kortestw", { MaskG
, MaskR
}, 0 },
10829 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10831 { "kortestq", { MaskG
, MaskR
}, 0 },
10834 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10836 { "kortestb", { MaskG
, MaskR
}, 0 },
10839 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10841 { "kortestd", { MaskG
, MaskR
}, 0 },
10844 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10846 { "ktestw", { MaskG
, MaskR
}, 0 },
10849 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10851 { "ktestq", { MaskG
, MaskR
}, 0 },
10854 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10856 { "ktestb", { MaskG
, MaskR
}, 0 },
10859 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10861 { "ktestd", { MaskG
, MaskR
}, 0 },
10864 /* MOD_VEX_0FAE_REG_2 */
10865 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
10868 /* MOD_VEX_0FAE_REG_3 */
10869 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
10872 /* MOD_VEX_0FD7_PREFIX_2 */
10874 { "vpmovmskb", { Gdq
, XS
}, 0 },
10877 /* MOD_VEX_0FE7_PREFIX_2 */
10878 { "vmovntdq", { Mx
, XM
}, 0 },
10881 /* MOD_VEX_0FF0_PREFIX_3 */
10882 { "vlddqu", { XM
, M
}, 0 },
10885 /* MOD_VEX_0F381A_PREFIX_2 */
10886 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
10889 /* MOD_VEX_0F382A_PREFIX_2 */
10890 { "vmovntdqa", { XM
, Mx
}, 0 },
10893 /* MOD_VEX_0F382C_PREFIX_2 */
10894 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
10897 /* MOD_VEX_0F382D_PREFIX_2 */
10898 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
10901 /* MOD_VEX_0F382E_PREFIX_2 */
10902 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
10905 /* MOD_VEX_0F382F_PREFIX_2 */
10906 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
10909 /* MOD_VEX_0F385A_PREFIX_2 */
10910 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
10913 /* MOD_VEX_0F388C_PREFIX_2 */
10914 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
10917 /* MOD_VEX_0F388E_PREFIX_2 */
10918 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
10921 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10923 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
10926 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10928 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
10931 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10933 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
10936 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10938 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
10941 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10943 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
10946 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10948 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
10951 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10953 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
10956 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10958 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
10961 #include "i386-dis-evex-mod.h"
10964 static const struct dis386 rm_table
[][8] = {
10967 { "xabort", { Skip_MODRM
, Ib
}, 0 },
10971 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
10974 /* RM_0F01_REG_0 */
10975 { "enclv", { Skip_MODRM
}, 0 },
10976 { "vmcall", { Skip_MODRM
}, 0 },
10977 { "vmlaunch", { Skip_MODRM
}, 0 },
10978 { "vmresume", { Skip_MODRM
}, 0 },
10979 { "vmxoff", { Skip_MODRM
}, 0 },
10980 { "pconfig", { Skip_MODRM
}, 0 },
10983 /* RM_0F01_REG_1 */
10984 { "monitor", { { OP_Monitor
, 0 } }, 0 },
10985 { "mwait", { { OP_Mwait
, 0 } }, 0 },
10986 { "clac", { Skip_MODRM
}, 0 },
10987 { "stac", { Skip_MODRM
}, 0 },
10991 { "encls", { Skip_MODRM
}, 0 },
10994 /* RM_0F01_REG_2 */
10995 { "xgetbv", { Skip_MODRM
}, 0 },
10996 { "xsetbv", { Skip_MODRM
}, 0 },
10999 { "vmfunc", { Skip_MODRM
}, 0 },
11000 { "xend", { Skip_MODRM
}, 0 },
11001 { "xtest", { Skip_MODRM
}, 0 },
11002 { "enclu", { Skip_MODRM
}, 0 },
11005 /* RM_0F01_REG_3 */
11006 { "vmrun", { Skip_MODRM
}, 0 },
11007 { "vmmcall", { Skip_MODRM
}, 0 },
11008 { "vmload", { Skip_MODRM
}, 0 },
11009 { "vmsave", { Skip_MODRM
}, 0 },
11010 { "stgi", { Skip_MODRM
}, 0 },
11011 { "clgi", { Skip_MODRM
}, 0 },
11012 { "skinit", { Skip_MODRM
}, 0 },
11013 { "invlpga", { Skip_MODRM
}, 0 },
11016 /* RM_0F01_REG_5_MOD_3 */
11017 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0
) },
11019 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2
) },
11023 { "rdpkru", { Skip_MODRM
}, 0 },
11024 { "wrpkru", { Skip_MODRM
}, 0 },
11027 /* RM_0F01_REG_7_MOD_3 */
11028 { "swapgs", { Skip_MODRM
}, 0 },
11029 { "rdtscp", { Skip_MODRM
}, 0 },
11030 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2
) },
11031 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3
) },
11032 { "clzero", { Skip_MODRM
}, 0 },
11035 /* RM_0F1E_P_1_MOD_3_REG_7 */
11036 { "nopQ", { Ev
}, 0 },
11037 { "nopQ", { Ev
}, 0 },
11038 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
11039 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
11040 { "nopQ", { Ev
}, 0 },
11041 { "nopQ", { Ev
}, 0 },
11042 { "nopQ", { Ev
}, 0 },
11043 { "nopQ", { Ev
}, 0 },
11046 /* RM_0FAE_REG_6_MOD_3 */
11047 { "mfence", { Skip_MODRM
}, 0 },
11050 /* RM_0FAE_REG_7_MOD_3 */
11051 { "sfence", { Skip_MODRM
}, 0 },
11056 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11058 /* We use the high bit to indicate different name for the same
11060 #define REP_PREFIX (0xf3 | 0x100)
11061 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11062 #define XRELEASE_PREFIX (0xf3 | 0x400)
11063 #define BND_PREFIX (0xf2 | 0x400)
11064 #define NOTRACK_PREFIX (0x3e | 0x100)
11069 int newrex
, i
, length
;
11075 last_lock_prefix
= -1;
11076 last_repz_prefix
= -1;
11077 last_repnz_prefix
= -1;
11078 last_data_prefix
= -1;
11079 last_addr_prefix
= -1;
11080 last_rex_prefix
= -1;
11081 last_seg_prefix
= -1;
11083 active_seg_prefix
= 0;
11084 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11085 all_prefixes
[i
] = 0;
11088 /* The maximum instruction length is 15bytes. */
11089 while (length
< MAX_CODE_LENGTH
- 1)
11091 FETCH_DATA (the_info
, codep
+ 1);
11095 /* REX prefixes family. */
11112 if (address_mode
== mode_64bit
)
11116 last_rex_prefix
= i
;
11119 prefixes
|= PREFIX_REPZ
;
11120 last_repz_prefix
= i
;
11123 prefixes
|= PREFIX_REPNZ
;
11124 last_repnz_prefix
= i
;
11127 prefixes
|= PREFIX_LOCK
;
11128 last_lock_prefix
= i
;
11131 prefixes
|= PREFIX_CS
;
11132 last_seg_prefix
= i
;
11133 active_seg_prefix
= PREFIX_CS
;
11136 prefixes
|= PREFIX_SS
;
11137 last_seg_prefix
= i
;
11138 active_seg_prefix
= PREFIX_SS
;
11141 prefixes
|= PREFIX_DS
;
11142 last_seg_prefix
= i
;
11143 active_seg_prefix
= PREFIX_DS
;
11146 prefixes
|= PREFIX_ES
;
11147 last_seg_prefix
= i
;
11148 active_seg_prefix
= PREFIX_ES
;
11151 prefixes
|= PREFIX_FS
;
11152 last_seg_prefix
= i
;
11153 active_seg_prefix
= PREFIX_FS
;
11156 prefixes
|= PREFIX_GS
;
11157 last_seg_prefix
= i
;
11158 active_seg_prefix
= PREFIX_GS
;
11161 prefixes
|= PREFIX_DATA
;
11162 last_data_prefix
= i
;
11165 prefixes
|= PREFIX_ADDR
;
11166 last_addr_prefix
= i
;
11169 /* fwait is really an instruction. If there are prefixes
11170 before the fwait, they belong to the fwait, *not* to the
11171 following instruction. */
11173 if (prefixes
|| rex
)
11175 prefixes
|= PREFIX_FWAIT
;
11177 /* This ensures that the previous REX prefixes are noticed
11178 as unused prefixes, as in the return case below. */
11182 prefixes
= PREFIX_FWAIT
;
11187 /* Rex is ignored when followed by another prefix. */
11193 if (*codep
!= FWAIT_OPCODE
)
11194 all_prefixes
[i
++] = *codep
;
11202 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11205 static const char *
11206 prefix_name (int pref
, int sizeflag
)
11208 static const char *rexes
[16] =
11211 "rex.B", /* 0x41 */
11212 "rex.X", /* 0x42 */
11213 "rex.XB", /* 0x43 */
11214 "rex.R", /* 0x44 */
11215 "rex.RB", /* 0x45 */
11216 "rex.RX", /* 0x46 */
11217 "rex.RXB", /* 0x47 */
11218 "rex.W", /* 0x48 */
11219 "rex.WB", /* 0x49 */
11220 "rex.WX", /* 0x4a */
11221 "rex.WXB", /* 0x4b */
11222 "rex.WR", /* 0x4c */
11223 "rex.WRB", /* 0x4d */
11224 "rex.WRX", /* 0x4e */
11225 "rex.WRXB", /* 0x4f */
11230 /* REX prefixes family. */
11247 return rexes
[pref
- 0x40];
11267 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11269 if (address_mode
== mode_64bit
)
11270 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11272 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11277 case XACQUIRE_PREFIX
:
11279 case XRELEASE_PREFIX
:
11283 case NOTRACK_PREFIX
:
11290 static char op_out
[MAX_OPERANDS
][100];
11291 static int op_ad
, op_index
[MAX_OPERANDS
];
11292 static int two_source_ops
;
11293 static bfd_vma op_address
[MAX_OPERANDS
];
11294 static bfd_vma op_riprel
[MAX_OPERANDS
];
11295 static bfd_vma start_pc
;
11298 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11299 * (see topic "Redundant prefixes" in the "Differences from 8086"
11300 * section of the "Virtual 8086 Mode" chapter.)
11301 * 'pc' should be the address of this instruction, it will
11302 * be used to print the target address if this is a relative jump or call
11303 * The function returns the length of this instruction in bytes.
11306 static char intel_syntax
;
11307 static char intel_mnemonic
= !SYSV386_COMPAT
;
11308 static char open_char
;
11309 static char close_char
;
11310 static char separator_char
;
11311 static char scale_char
;
11319 static enum x86_64_isa isa64
;
11321 /* Here for backwards compatibility. When gdb stops using
11322 print_insn_i386_att and print_insn_i386_intel these functions can
11323 disappear, and print_insn_i386 be merged into print_insn. */
11325 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11329 return print_insn (pc
, info
);
11333 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11337 return print_insn (pc
, info
);
11341 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11345 return print_insn (pc
, info
);
11349 print_i386_disassembler_options (FILE *stream
)
11351 fprintf (stream
, _("\n\
11352 The following i386/x86-64 specific disassembler options are supported for use\n\
11353 with the -M switch (multiple options should be separated by commas):\n"));
11355 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11356 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11357 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11358 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11359 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11360 fprintf (stream
, _(" att-mnemonic\n"
11361 " Display instruction in AT&T mnemonic\n"));
11362 fprintf (stream
, _(" intel-mnemonic\n"
11363 " Display instruction in Intel mnemonic\n"));
11364 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11365 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11366 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11367 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11368 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11369 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11370 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
11371 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
11375 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
11377 /* Get a pointer to struct dis386 with a valid name. */
11379 static const struct dis386
*
11380 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11382 int vindex
, vex_table_index
;
11384 if (dp
->name
!= NULL
)
11387 switch (dp
->op
[0].bytemode
)
11389 case USE_REG_TABLE
:
11390 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11393 case USE_MOD_TABLE
:
11394 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11395 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11399 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11402 case USE_PREFIX_TABLE
:
11405 /* The prefix in VEX is implicit. */
11406 switch (vex
.prefix
)
11411 case REPE_PREFIX_OPCODE
:
11414 case DATA_PREFIX_OPCODE
:
11417 case REPNE_PREFIX_OPCODE
:
11427 int last_prefix
= -1;
11430 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11431 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11433 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11435 if (last_repz_prefix
> last_repnz_prefix
)
11438 prefix
= PREFIX_REPZ
;
11439 last_prefix
= last_repz_prefix
;
11444 prefix
= PREFIX_REPNZ
;
11445 last_prefix
= last_repnz_prefix
;
11448 /* Check if prefix should be ignored. */
11449 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
11450 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
11455 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
11458 prefix
= PREFIX_DATA
;
11459 last_prefix
= last_data_prefix
;
11464 used_prefixes
|= prefix
;
11465 all_prefixes
[last_prefix
] = 0;
11468 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
11471 case USE_X86_64_TABLE
:
11472 vindex
= address_mode
== mode_64bit
? 1 : 0;
11473 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
11476 case USE_3BYTE_TABLE
:
11477 FETCH_DATA (info
, codep
+ 2);
11479 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
11481 modrm
.mod
= (*codep
>> 6) & 3;
11482 modrm
.reg
= (*codep
>> 3) & 7;
11483 modrm
.rm
= *codep
& 7;
11486 case USE_VEX_LEN_TABLE
:
11490 switch (vex
.length
)
11503 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
11506 case USE_EVEX_LEN_TABLE
:
11510 switch (vex
.length
)
11526 dp
= &evex_len_table
[dp
->op
[1].bytemode
][vindex
];
11529 case USE_XOP_8F_TABLE
:
11530 FETCH_DATA (info
, codep
+ 3);
11531 /* All bits in the REX prefix are ignored. */
11533 rex
= ~(*codep
>> 5) & 0x7;
11535 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11536 switch ((*codep
& 0x1f))
11542 vex_table_index
= XOP_08
;
11545 vex_table_index
= XOP_09
;
11548 vex_table_index
= XOP_0A
;
11552 vex
.w
= *codep
& 0x80;
11553 if (vex
.w
&& address_mode
== mode_64bit
)
11556 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11557 if (address_mode
!= mode_64bit
)
11559 /* In 16/32-bit mode REX_B is silently ignored. */
11563 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11564 switch ((*codep
& 0x3))
11569 vex
.prefix
= DATA_PREFIX_OPCODE
;
11572 vex
.prefix
= REPE_PREFIX_OPCODE
;
11575 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11582 dp
= &xop_table
[vex_table_index
][vindex
];
11585 FETCH_DATA (info
, codep
+ 1);
11586 modrm
.mod
= (*codep
>> 6) & 3;
11587 modrm
.reg
= (*codep
>> 3) & 7;
11588 modrm
.rm
= *codep
& 7;
11591 case USE_VEX_C4_TABLE
:
11593 FETCH_DATA (info
, codep
+ 3);
11594 /* All bits in the REX prefix are ignored. */
11596 rex
= ~(*codep
>> 5) & 0x7;
11597 switch ((*codep
& 0x1f))
11603 vex_table_index
= VEX_0F
;
11606 vex_table_index
= VEX_0F38
;
11609 vex_table_index
= VEX_0F3A
;
11613 vex
.w
= *codep
& 0x80;
11614 if (address_mode
== mode_64bit
)
11621 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11622 is ignored, other REX bits are 0 and the highest bit in
11623 VEX.vvvv is also ignored (but we mustn't clear it here). */
11626 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11627 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11628 switch ((*codep
& 0x3))
11633 vex
.prefix
= DATA_PREFIX_OPCODE
;
11636 vex
.prefix
= REPE_PREFIX_OPCODE
;
11639 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11646 dp
= &vex_table
[vex_table_index
][vindex
];
11648 /* There is no MODRM byte for VEX0F 77. */
11649 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
11651 FETCH_DATA (info
, codep
+ 1);
11652 modrm
.mod
= (*codep
>> 6) & 3;
11653 modrm
.reg
= (*codep
>> 3) & 7;
11654 modrm
.rm
= *codep
& 7;
11658 case USE_VEX_C5_TABLE
:
11660 FETCH_DATA (info
, codep
+ 2);
11661 /* All bits in the REX prefix are ignored. */
11663 rex
= (*codep
& 0x80) ? 0 : REX_R
;
11665 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11667 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11668 vex
.length
= (*codep
& 0x4) ? 256 : 128;
11669 switch ((*codep
& 0x3))
11674 vex
.prefix
= DATA_PREFIX_OPCODE
;
11677 vex
.prefix
= REPE_PREFIX_OPCODE
;
11680 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11687 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
11689 /* There is no MODRM byte for VEX 77. */
11690 if (vindex
!= 0x77)
11692 FETCH_DATA (info
, codep
+ 1);
11693 modrm
.mod
= (*codep
>> 6) & 3;
11694 modrm
.reg
= (*codep
>> 3) & 7;
11695 modrm
.rm
= *codep
& 7;
11699 case USE_VEX_W_TABLE
:
11703 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
11706 case USE_EVEX_TABLE
:
11707 two_source_ops
= 0;
11710 FETCH_DATA (info
, codep
+ 4);
11711 /* All bits in the REX prefix are ignored. */
11713 /* The first byte after 0x62. */
11714 rex
= ~(*codep
>> 5) & 0x7;
11715 vex
.r
= *codep
& 0x10;
11716 switch ((*codep
& 0xf))
11719 return &bad_opcode
;
11721 vex_table_index
= EVEX_0F
;
11724 vex_table_index
= EVEX_0F38
;
11727 vex_table_index
= EVEX_0F3A
;
11731 /* The second byte after 0x62. */
11733 vex
.w
= *codep
& 0x80;
11734 if (vex
.w
&& address_mode
== mode_64bit
)
11737 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
11740 if (!(*codep
& 0x4))
11741 return &bad_opcode
;
11743 switch ((*codep
& 0x3))
11748 vex
.prefix
= DATA_PREFIX_OPCODE
;
11751 vex
.prefix
= REPE_PREFIX_OPCODE
;
11754 vex
.prefix
= REPNE_PREFIX_OPCODE
;
11758 /* The third byte after 0x62. */
11761 /* Remember the static rounding bits. */
11762 vex
.ll
= (*codep
>> 5) & 3;
11763 vex
.b
= (*codep
& 0x10) != 0;
11765 vex
.v
= *codep
& 0x8;
11766 vex
.mask_register_specifier
= *codep
& 0x7;
11767 vex
.zeroing
= *codep
& 0x80;
11769 if (address_mode
!= mode_64bit
)
11771 /* In 16/32-bit mode silently ignore following bits. */
11781 dp
= &evex_table
[vex_table_index
][vindex
];
11783 FETCH_DATA (info
, codep
+ 1);
11784 modrm
.mod
= (*codep
>> 6) & 3;
11785 modrm
.reg
= (*codep
>> 3) & 7;
11786 modrm
.rm
= *codep
& 7;
11788 /* Set vector length. */
11789 if (modrm
.mod
== 3 && vex
.b
)
11805 return &bad_opcode
;
11818 if (dp
->name
!= NULL
)
11821 return get_valid_dis386 (dp
, info
);
11825 get_sib (disassemble_info
*info
, int sizeflag
)
11827 /* If modrm.mod == 3, operand must be register. */
11829 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
11833 FETCH_DATA (info
, codep
+ 2);
11834 sib
.index
= (codep
[1] >> 3) & 7;
11835 sib
.scale
= (codep
[1] >> 6) & 3;
11836 sib
.base
= codep
[1] & 7;
11841 print_insn (bfd_vma pc
, disassemble_info
*info
)
11843 const struct dis386
*dp
;
11845 char *op_txt
[MAX_OPERANDS
];
11847 int sizeflag
, orig_sizeflag
;
11849 struct dis_private priv
;
11852 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11853 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
11854 address_mode
= mode_32bit
;
11855 else if (info
->mach
== bfd_mach_i386_i8086
)
11857 address_mode
= mode_16bit
;
11858 priv
.orig_sizeflag
= 0;
11861 address_mode
= mode_64bit
;
11863 if (intel_syntax
== (char) -1)
11864 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
11866 for (p
= info
->disassembler_options
; p
!= NULL
; )
11868 if (CONST_STRNEQ (p
, "amd64"))
11870 else if (CONST_STRNEQ (p
, "intel64"))
11872 else if (CONST_STRNEQ (p
, "x86-64"))
11874 address_mode
= mode_64bit
;
11875 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11877 else if (CONST_STRNEQ (p
, "i386"))
11879 address_mode
= mode_32bit
;
11880 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
11882 else if (CONST_STRNEQ (p
, "i8086"))
11884 address_mode
= mode_16bit
;
11885 priv
.orig_sizeflag
= 0;
11887 else if (CONST_STRNEQ (p
, "intel"))
11890 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
11891 intel_mnemonic
= 1;
11893 else if (CONST_STRNEQ (p
, "att"))
11896 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
11897 intel_mnemonic
= 0;
11899 else if (CONST_STRNEQ (p
, "addr"))
11901 if (address_mode
== mode_64bit
)
11903 if (p
[4] == '3' && p
[5] == '2')
11904 priv
.orig_sizeflag
&= ~AFLAG
;
11905 else if (p
[4] == '6' && p
[5] == '4')
11906 priv
.orig_sizeflag
|= AFLAG
;
11910 if (p
[4] == '1' && p
[5] == '6')
11911 priv
.orig_sizeflag
&= ~AFLAG
;
11912 else if (p
[4] == '3' && p
[5] == '2')
11913 priv
.orig_sizeflag
|= AFLAG
;
11916 else if (CONST_STRNEQ (p
, "data"))
11918 if (p
[4] == '1' && p
[5] == '6')
11919 priv
.orig_sizeflag
&= ~DFLAG
;
11920 else if (p
[4] == '3' && p
[5] == '2')
11921 priv
.orig_sizeflag
|= DFLAG
;
11923 else if (CONST_STRNEQ (p
, "suffix"))
11924 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
11926 p
= strchr (p
, ',');
11931 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
11933 (*info
->fprintf_func
) (info
->stream
,
11934 _("64-bit address is disabled"));
11940 names64
= intel_names64
;
11941 names32
= intel_names32
;
11942 names16
= intel_names16
;
11943 names8
= intel_names8
;
11944 names8rex
= intel_names8rex
;
11945 names_seg
= intel_names_seg
;
11946 names_mm
= intel_names_mm
;
11947 names_bnd
= intel_names_bnd
;
11948 names_xmm
= intel_names_xmm
;
11949 names_ymm
= intel_names_ymm
;
11950 names_zmm
= intel_names_zmm
;
11951 index64
= intel_index64
;
11952 index32
= intel_index32
;
11953 names_mask
= intel_names_mask
;
11954 index16
= intel_index16
;
11957 separator_char
= '+';
11962 names64
= att_names64
;
11963 names32
= att_names32
;
11964 names16
= att_names16
;
11965 names8
= att_names8
;
11966 names8rex
= att_names8rex
;
11967 names_seg
= att_names_seg
;
11968 names_mm
= att_names_mm
;
11969 names_bnd
= att_names_bnd
;
11970 names_xmm
= att_names_xmm
;
11971 names_ymm
= att_names_ymm
;
11972 names_zmm
= att_names_zmm
;
11973 index64
= att_index64
;
11974 index32
= att_index32
;
11975 names_mask
= att_names_mask
;
11976 index16
= att_index16
;
11979 separator_char
= ',';
11983 /* The output looks better if we put 7 bytes on a line, since that
11984 puts most long word instructions on a single line. Use 8 bytes
11986 if ((info
->mach
& bfd_mach_l1om
) != 0)
11987 info
->bytes_per_line
= 8;
11989 info
->bytes_per_line
= 7;
11991 info
->private_data
= &priv
;
11992 priv
.max_fetched
= priv
.the_buffer
;
11993 priv
.insn_start
= pc
;
11996 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12004 start_codep
= priv
.the_buffer
;
12005 codep
= priv
.the_buffer
;
12007 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12011 /* Getting here means we tried for data but didn't get it. That
12012 means we have an incomplete instruction of some sort. Just
12013 print the first byte as a prefix or a .byte pseudo-op. */
12014 if (codep
> priv
.the_buffer
)
12016 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12018 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12021 /* Just print the first byte as a .byte instruction. */
12022 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12023 (unsigned int) priv
.the_buffer
[0]);
12033 sizeflag
= priv
.orig_sizeflag
;
12035 if (!ckprefix () || rex_used
)
12037 /* Too many prefixes or unused REX prefixes. */
12039 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12041 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12043 prefix_name (all_prefixes
[i
], sizeflag
));
12047 insn_codep
= codep
;
12049 FETCH_DATA (info
, codep
+ 1);
12050 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12052 if (((prefixes
& PREFIX_FWAIT
)
12053 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12055 /* Handle prefixes before fwait. */
12056 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12058 (*info
->fprintf_func
) (info
->stream
, "%s ",
12059 prefix_name (all_prefixes
[i
], sizeflag
));
12060 (*info
->fprintf_func
) (info
->stream
, "fwait");
12064 if (*codep
== 0x0f)
12066 unsigned char threebyte
;
12069 FETCH_DATA (info
, codep
+ 1);
12070 threebyte
= *codep
;
12071 dp
= &dis386_twobyte
[threebyte
];
12072 need_modrm
= twobyte_has_modrm
[*codep
];
12077 dp
= &dis386
[*codep
];
12078 need_modrm
= onebyte_has_modrm
[*codep
];
12082 /* Save sizeflag for printing the extra prefixes later before updating
12083 it for mnemonic and operand processing. The prefix names depend
12084 only on the address mode. */
12085 orig_sizeflag
= sizeflag
;
12086 if (prefixes
& PREFIX_ADDR
)
12088 if ((prefixes
& PREFIX_DATA
))
12094 FETCH_DATA (info
, codep
+ 1);
12095 modrm
.mod
= (*codep
>> 6) & 3;
12096 modrm
.reg
= (*codep
>> 3) & 7;
12097 modrm
.rm
= *codep
& 7;
12103 memset (&vex
, 0, sizeof (vex
));
12105 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12107 get_sib (info
, sizeflag
);
12108 dofloat (sizeflag
);
12112 dp
= get_valid_dis386 (dp
, info
);
12113 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12115 get_sib (info
, sizeflag
);
12116 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12119 op_ad
= MAX_OPERANDS
- 1 - i
;
12121 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12122 /* For EVEX instruction after the last operand masking
12123 should be printed. */
12124 if (i
== 0 && vex
.evex
)
12126 /* Don't print {%k0}. */
12127 if (vex
.mask_register_specifier
)
12130 oappend (names_mask
[vex
.mask_register_specifier
]);
12140 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12141 are all 0s in inverted form. */
12142 if (need_vex
&& vex
.register_specifier
!= 0)
12144 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12145 return end_codep
- priv
.the_buffer
;
12148 /* Check if the REX prefix is used. */
12149 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12150 all_prefixes
[last_rex_prefix
] = 0;
12152 /* Check if the SEG prefix is used. */
12153 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12154 | PREFIX_FS
| PREFIX_GS
)) != 0
12155 && (used_prefixes
& active_seg_prefix
) != 0)
12156 all_prefixes
[last_seg_prefix
] = 0;
12158 /* Check if the ADDR prefix is used. */
12159 if ((prefixes
& PREFIX_ADDR
) != 0
12160 && (used_prefixes
& PREFIX_ADDR
) != 0)
12161 all_prefixes
[last_addr_prefix
] = 0;
12163 /* Check if the DATA prefix is used. */
12164 if ((prefixes
& PREFIX_DATA
) != 0
12165 && (used_prefixes
& PREFIX_DATA
) != 0)
12166 all_prefixes
[last_data_prefix
] = 0;
12168 /* Print the extra prefixes. */
12170 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12171 if (all_prefixes
[i
])
12174 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12177 prefix_length
+= strlen (name
) + 1;
12178 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12181 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12182 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12183 used by putop and MMX/SSE operand and may be overriden by the
12184 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12186 if (dp
->prefix_requirement
== PREFIX_OPCODE
12187 && dp
!= &bad_opcode
12189 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12191 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12193 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12195 && (used_prefixes
& PREFIX_DATA
) == 0))))
12197 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12198 return end_codep
- priv
.the_buffer
;
12201 /* Check maximum code length. */
12202 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12204 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12205 return MAX_CODE_LENGTH
;
12208 obufp
= mnemonicendp
;
12209 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12212 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12214 /* The enter and bound instructions are printed with operands in the same
12215 order as the intel book; everything else is printed in reverse order. */
12216 if (intel_syntax
|| two_source_ops
)
12220 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12221 op_txt
[i
] = op_out
[i
];
12223 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
12224 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
12226 op_txt
[2] = op_out
[3];
12227 op_txt
[3] = op_out
[2];
12230 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12232 op_ad
= op_index
[i
];
12233 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12234 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12235 riprel
= op_riprel
[i
];
12236 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12237 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12242 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12243 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12247 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12251 (*info
->fprintf_func
) (info
->stream
, ",");
12252 if (op_index
[i
] != -1 && !op_riprel
[i
])
12253 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12255 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12259 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12260 if (op_index
[i
] != -1 && op_riprel
[i
])
12262 (*info
->fprintf_func
) (info
->stream
, " # ");
12263 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
12264 + op_address
[op_index
[i
]]), info
);
12267 return codep
- priv
.the_buffer
;
12270 static const char *float_mem
[] = {
12345 static const unsigned char float_mem_mode
[] = {
12420 #define ST { OP_ST, 0 }
12421 #define STi { OP_STi, 0 }
12423 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12424 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12425 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12426 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12427 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12428 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12429 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12430 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12431 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12433 static const struct dis386 float_reg
[][8] = {
12436 { "fadd", { ST
, STi
}, 0 },
12437 { "fmul", { ST
, STi
}, 0 },
12438 { "fcom", { STi
}, 0 },
12439 { "fcomp", { STi
}, 0 },
12440 { "fsub", { ST
, STi
}, 0 },
12441 { "fsubr", { ST
, STi
}, 0 },
12442 { "fdiv", { ST
, STi
}, 0 },
12443 { "fdivr", { ST
, STi
}, 0 },
12447 { "fld", { STi
}, 0 },
12448 { "fxch", { STi
}, 0 },
12458 { "fcmovb", { ST
, STi
}, 0 },
12459 { "fcmove", { ST
, STi
}, 0 },
12460 { "fcmovbe",{ ST
, STi
}, 0 },
12461 { "fcmovu", { ST
, STi
}, 0 },
12469 { "fcmovnb",{ ST
, STi
}, 0 },
12470 { "fcmovne",{ ST
, STi
}, 0 },
12471 { "fcmovnbe",{ ST
, STi
}, 0 },
12472 { "fcmovnu",{ ST
, STi
}, 0 },
12474 { "fucomi", { ST
, STi
}, 0 },
12475 { "fcomi", { ST
, STi
}, 0 },
12480 { "fadd", { STi
, ST
}, 0 },
12481 { "fmul", { STi
, ST
}, 0 },
12484 { "fsub{!M|r}", { STi
, ST
}, 0 },
12485 { "fsub{M|}", { STi
, ST
}, 0 },
12486 { "fdiv{!M|r}", { STi
, ST
}, 0 },
12487 { "fdiv{M|}", { STi
, ST
}, 0 },
12491 { "ffree", { STi
}, 0 },
12493 { "fst", { STi
}, 0 },
12494 { "fstp", { STi
}, 0 },
12495 { "fucom", { STi
}, 0 },
12496 { "fucomp", { STi
}, 0 },
12502 { "faddp", { STi
, ST
}, 0 },
12503 { "fmulp", { STi
, ST
}, 0 },
12506 { "fsub{!M|r}p", { STi
, ST
}, 0 },
12507 { "fsub{M|}p", { STi
, ST
}, 0 },
12508 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
12509 { "fdiv{M|}p", { STi
, ST
}, 0 },
12513 { "ffreep", { STi
}, 0 },
12518 { "fucomip", { ST
, STi
}, 0 },
12519 { "fcomip", { ST
, STi
}, 0 },
12524 static char *fgrps
[][8] = {
12527 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12532 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12537 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12542 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12547 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12552 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12557 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12562 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12563 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12568 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12573 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12578 swap_operand (void)
12580 mnemonicendp
[0] = '.';
12581 mnemonicendp
[1] = 's';
12586 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
12587 int sizeflag ATTRIBUTE_UNUSED
)
12589 /* Skip mod/rm byte. */
12595 dofloat (int sizeflag
)
12597 const struct dis386
*dp
;
12598 unsigned char floatop
;
12600 floatop
= codep
[-1];
12602 if (modrm
.mod
!= 3)
12604 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
12606 putop (float_mem
[fp_indx
], sizeflag
);
12609 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
12612 /* Skip mod/rm byte. */
12616 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
12617 if (dp
->name
== NULL
)
12619 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
12621 /* Instruction fnstsw is only one with strange arg. */
12622 if (floatop
== 0xdf && codep
[-1] == 0xe0)
12623 strcpy (op_out
[0], names16
[0]);
12627 putop (dp
->name
, sizeflag
);
12632 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
12637 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
12641 /* Like oappend (below), but S is a string starting with '%'.
12642 In Intel syntax, the '%' is elided. */
12644 oappend_maybe_intel (const char *s
)
12646 oappend (s
+ intel_syntax
);
12650 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12652 oappend_maybe_intel ("%st");
12656 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
12658 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
12659 oappend_maybe_intel (scratchbuf
);
12662 /* Capital letters in template are macros. */
12664 putop (const char *in_template
, int sizeflag
)
12669 unsigned int l
= 0, len
= 1;
12672 #define SAVE_LAST(c) \
12673 if (l < len && l < sizeof (last)) \
12678 for (p
= in_template
; *p
; p
++)
12694 while (*++p
!= '|')
12695 if (*p
== '}' || *p
== '\0')
12698 /* Fall through. */
12703 while (*++p
!= '}')
12714 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12718 if (l
== 0 && len
== 1)
12723 if (sizeflag
& SUFFIX_ALWAYS
)
12736 if (address_mode
== mode_64bit
12737 && !(prefixes
& PREFIX_ADDR
))
12748 if (intel_syntax
&& !alt
)
12750 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
12752 if (sizeflag
& DFLAG
)
12753 *obufp
++ = intel_syntax
? 'd' : 'l';
12755 *obufp
++ = intel_syntax
? 'w' : 's';
12756 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12760 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
12763 if (modrm
.mod
== 3)
12769 if (sizeflag
& DFLAG
)
12770 *obufp
++ = intel_syntax
? 'd' : 'l';
12773 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12779 case 'E': /* For jcxz/jecxz */
12780 if (address_mode
== mode_64bit
)
12782 if (sizeflag
& AFLAG
)
12788 if (sizeflag
& AFLAG
)
12790 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12795 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
12797 if (sizeflag
& AFLAG
)
12798 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
12800 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
12801 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
12805 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
12807 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
12811 if (!(rex
& REX_W
))
12812 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12817 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
12818 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
12820 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
12823 if (prefixes
& PREFIX_DS
)
12842 if (l
!= 0 || len
!= 1)
12844 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
12849 if (!need_vex
|| !vex
.evex
)
12852 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
12854 switch (vex
.length
)
12872 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
12877 /* Fall through. */
12880 if (l
!= 0 || len
!= 1)
12888 if (sizeflag
& SUFFIX_ALWAYS
)
12892 if (intel_mnemonic
!= cond
)
12896 if ((prefixes
& PREFIX_FWAIT
) == 0)
12899 used_prefixes
|= PREFIX_FWAIT
;
12905 else if (intel_syntax
&& (sizeflag
& DFLAG
))
12909 if (!(rex
& REX_W
))
12910 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12914 && address_mode
== mode_64bit
12915 && isa64
== intel64
)
12920 /* Fall through. */
12923 && address_mode
== mode_64bit
12924 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12929 /* Fall through. */
12932 if (l
== 0 && len
== 1)
12937 if ((rex
& REX_W
) == 0
12938 && (prefixes
& PREFIX_DATA
))
12940 if ((sizeflag
& DFLAG
) == 0)
12942 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12946 if ((prefixes
& PREFIX_DATA
)
12948 || (sizeflag
& SUFFIX_ALWAYS
))
12955 if (sizeflag
& DFLAG
)
12959 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12965 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
12971 if ((prefixes
& PREFIX_DATA
)
12973 || (sizeflag
& SUFFIX_ALWAYS
))
12980 if (sizeflag
& DFLAG
)
12981 *obufp
++ = intel_syntax
? 'd' : 'l';
12984 used_prefixes
|= (prefixes
& PREFIX_DATA
);
12992 if (address_mode
== mode_64bit
12993 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
12995 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
12999 /* Fall through. */
13002 if (l
== 0 && len
== 1)
13005 if (intel_syntax
&& !alt
)
13008 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13014 if (sizeflag
& DFLAG
)
13015 *obufp
++ = intel_syntax
? 'd' : 'l';
13018 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13024 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13030 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13045 else if (sizeflag
& DFLAG
)
13054 if (intel_syntax
&& !p
[1]
13055 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13057 if (!(rex
& REX_W
))
13058 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13061 if (l
== 0 && len
== 1)
13065 if (address_mode
== mode_64bit
13066 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13068 if (sizeflag
& SUFFIX_ALWAYS
)
13090 /* Fall through. */
13093 if (l
== 0 && len
== 1)
13098 if (sizeflag
& SUFFIX_ALWAYS
)
13104 if (sizeflag
& DFLAG
)
13108 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13122 if (address_mode
== mode_64bit
13123 && !(prefixes
& PREFIX_ADDR
))
13134 if (l
!= 0 || len
!= 1)
13139 if (need_vex
&& vex
.prefix
)
13141 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13148 if (prefixes
& PREFIX_DATA
)
13152 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13156 if (l
== 0 && len
== 1)
13160 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13168 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
13170 switch (vex
.length
)
13186 if (l
== 0 && len
== 1)
13188 /* operand size flag for cwtl, cbtw */
13197 else if (sizeflag
& DFLAG
)
13201 if (!(rex
& REX_W
))
13202 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13209 && last
[0] != 'L'))
13216 if (last
[0] == 'X')
13217 *obufp
++ = vex
.w
? 'd': 's';
13219 *obufp
++ = vex
.w
? 'q': 'd';
13225 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13227 if (sizeflag
& DFLAG
)
13231 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13237 if (address_mode
== mode_64bit
13238 && (isa64
== intel64
13239 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
13241 else if ((prefixes
& PREFIX_DATA
))
13243 if (!(sizeflag
& DFLAG
))
13245 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13252 mnemonicendp
= obufp
;
13257 oappend (const char *s
)
13259 obufp
= stpcpy (obufp
, s
);
13265 /* Only print the active segment register. */
13266 if (!active_seg_prefix
)
13269 used_prefixes
|= active_seg_prefix
;
13270 switch (active_seg_prefix
)
13273 oappend_maybe_intel ("%cs:");
13276 oappend_maybe_intel ("%ds:");
13279 oappend_maybe_intel ("%ss:");
13282 oappend_maybe_intel ("%es:");
13285 oappend_maybe_intel ("%fs:");
13288 oappend_maybe_intel ("%gs:");
13296 OP_indirE (int bytemode
, int sizeflag
)
13300 OP_E (bytemode
, sizeflag
);
13304 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13306 if (address_mode
== mode_64bit
)
13314 sprintf_vma (tmp
, disp
);
13315 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13316 strcpy (buf
+ 2, tmp
+ i
);
13320 bfd_signed_vma v
= disp
;
13327 /* Check for possible overflow on 0x8000000000000000. */
13330 strcpy (buf
, "9223372036854775808");
13344 tmp
[28 - i
] = (v
% 10) + '0';
13348 strcpy (buf
, tmp
+ 29 - i
);
13354 sprintf (buf
, "0x%x", (unsigned int) disp
);
13356 sprintf (buf
, "%d", (int) disp
);
13360 /* Put DISP in BUF as signed hex number. */
13363 print_displacement (char *buf
, bfd_vma disp
)
13365 bfd_signed_vma val
= disp
;
13374 /* Check for possible overflow. */
13377 switch (address_mode
)
13380 strcpy (buf
+ j
, "0x8000000000000000");
13383 strcpy (buf
+ j
, "0x80000000");
13386 strcpy (buf
+ j
, "0x8000");
13396 sprintf_vma (tmp
, (bfd_vma
) val
);
13397 for (i
= 0; tmp
[i
] == '0'; i
++)
13399 if (tmp
[i
] == '\0')
13401 strcpy (buf
+ j
, tmp
+ i
);
13405 intel_operand_size (int bytemode
, int sizeflag
)
13409 && (bytemode
== x_mode
13410 || bytemode
== evex_half_bcst_xmmq_mode
))
13413 oappend ("QWORD PTR ");
13415 oappend ("DWORD PTR ");
13424 oappend ("BYTE PTR ");
13429 oappend ("WORD PTR ");
13432 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13434 oappend ("QWORD PTR ");
13437 /* Fall through. */
13439 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13441 oappend ("QWORD PTR ");
13444 /* Fall through. */
13450 oappend ("QWORD PTR ");
13453 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13454 oappend ("DWORD PTR ");
13456 oappend ("WORD PTR ");
13457 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13461 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13463 oappend ("WORD PTR ");
13464 if (!(rex
& REX_W
))
13465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13468 if (sizeflag
& DFLAG
)
13469 oappend ("QWORD PTR ");
13471 oappend ("DWORD PTR ");
13472 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13475 case d_scalar_mode
:
13476 case d_scalar_swap_mode
:
13479 oappend ("DWORD PTR ");
13482 case q_scalar_mode
:
13483 case q_scalar_swap_mode
:
13485 oappend ("QWORD PTR ");
13488 if (address_mode
== mode_64bit
)
13489 oappend ("QWORD PTR ");
13491 oappend ("DWORD PTR ");
13494 if (sizeflag
& DFLAG
)
13495 oappend ("FWORD PTR ");
13497 oappend ("DWORD PTR ");
13498 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13501 oappend ("TBYTE PTR ");
13505 case evex_x_gscat_mode
:
13506 case evex_x_nobcst_mode
:
13507 case b_scalar_mode
:
13508 case w_scalar_mode
:
13511 switch (vex
.length
)
13514 oappend ("XMMWORD PTR ");
13517 oappend ("YMMWORD PTR ");
13520 oappend ("ZMMWORD PTR ");
13527 oappend ("XMMWORD PTR ");
13530 oappend ("XMMWORD PTR ");
13533 oappend ("YMMWORD PTR ");
13536 case evex_half_bcst_xmmq_mode
:
13540 switch (vex
.length
)
13543 oappend ("QWORD PTR ");
13546 oappend ("XMMWORD PTR ");
13549 oappend ("YMMWORD PTR ");
13559 switch (vex
.length
)
13564 oappend ("BYTE PTR ");
13574 switch (vex
.length
)
13579 oappend ("WORD PTR ");
13589 switch (vex
.length
)
13594 oappend ("DWORD PTR ");
13604 switch (vex
.length
)
13609 oappend ("QWORD PTR ");
13619 switch (vex
.length
)
13622 oappend ("WORD PTR ");
13625 oappend ("DWORD PTR ");
13628 oappend ("QWORD PTR ");
13638 switch (vex
.length
)
13641 oappend ("DWORD PTR ");
13644 oappend ("QWORD PTR ");
13647 oappend ("XMMWORD PTR ");
13657 switch (vex
.length
)
13660 oappend ("QWORD PTR ");
13663 oappend ("YMMWORD PTR ");
13666 oappend ("ZMMWORD PTR ");
13676 switch (vex
.length
)
13680 oappend ("XMMWORD PTR ");
13687 oappend ("OWORD PTR ");
13690 case vex_w_dq_mode
:
13691 case vex_scalar_w_dq_mode
:
13696 oappend ("QWORD PTR ");
13698 oappend ("DWORD PTR ");
13700 case vex_vsib_d_w_dq_mode
:
13701 case vex_vsib_q_w_dq_mode
:
13708 oappend ("QWORD PTR ");
13710 oappend ("DWORD PTR ");
13714 switch (vex
.length
)
13717 oappend ("XMMWORD PTR ");
13720 oappend ("YMMWORD PTR ");
13723 oappend ("ZMMWORD PTR ");
13730 case vex_vsib_q_w_d_mode
:
13731 case vex_vsib_d_w_d_mode
:
13732 if (!need_vex
|| !vex
.evex
)
13735 switch (vex
.length
)
13738 oappend ("QWORD PTR ");
13741 oappend ("XMMWORD PTR ");
13744 oappend ("YMMWORD PTR ");
13752 if (!need_vex
|| vex
.length
!= 128)
13755 oappend ("DWORD PTR ");
13757 oappend ("BYTE PTR ");
13763 oappend ("QWORD PTR ");
13765 oappend ("WORD PTR ");
13775 OP_E_register (int bytemode
, int sizeflag
)
13777 int reg
= modrm
.rm
;
13778 const char **names
;
13784 if ((sizeflag
& SUFFIX_ALWAYS
)
13785 && (bytemode
== b_swap_mode
13786 || bytemode
== bnd_swap_mode
13787 || bytemode
== v_swap_mode
))
13813 names
= address_mode
== mode_64bit
? names64
: names32
;
13816 case bnd_swap_mode
:
13825 if (address_mode
== mode_64bit
&& isa64
== intel64
)
13830 /* Fall through. */
13832 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13838 /* Fall through. */
13850 if ((sizeflag
& DFLAG
)
13851 || (bytemode
!= v_mode
13852 && bytemode
!= v_swap_mode
))
13856 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13860 names
= (address_mode
== mode_64bit
13861 ? names64
: names32
);
13862 if (!(prefixes
& PREFIX_ADDR
))
13863 names
= (address_mode
== mode_16bit
13864 ? names16
: names
);
13867 /* Remove "addr16/addr32". */
13868 all_prefixes
[last_addr_prefix
] = 0;
13869 names
= (address_mode
!= mode_32bit
13870 ? names32
: names16
);
13871 used_prefixes
|= PREFIX_ADDR
;
13881 names
= names_mask
;
13886 oappend (INTERNAL_DISASSEMBLER_ERROR
);
13889 oappend (names
[reg
]);
13893 OP_E_memory (int bytemode
, int sizeflag
)
13896 int add
= (rex
& REX_B
) ? 8 : 0;
13902 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13904 && bytemode
!= x_mode
13905 && bytemode
!= xmmq_mode
13906 && bytemode
!= evex_half_bcst_xmmq_mode
)
13922 if (address_mode
!= mode_64bit
)
13928 case vex_vsib_d_w_dq_mode
:
13929 case vex_vsib_d_w_d_mode
:
13930 case vex_vsib_q_w_dq_mode
:
13931 case vex_vsib_q_w_d_mode
:
13932 case evex_x_gscat_mode
:
13934 shift
= vex
.w
? 3 : 2;
13937 case evex_half_bcst_xmmq_mode
:
13941 shift
= vex
.w
? 3 : 2;
13944 /* Fall through. */
13948 case evex_x_nobcst_mode
:
13950 switch (vex
.length
)
13973 case q_scalar_mode
:
13975 case q_scalar_swap_mode
:
13981 case d_scalar_mode
:
13983 case d_scalar_swap_mode
:
13986 case w_scalar_mode
:
13990 case b_scalar_mode
:
13997 /* Make necessary corrections to shift for modes that need it.
13998 For these modes we currently have shift 4, 5 or 6 depending on
13999 vex.length (it corresponds to xmmword, ymmword or zmmword
14000 operand). We might want to make it 3, 4 or 5 (e.g. for
14001 xmmq_mode). In case of broadcast enabled the corrections
14002 aren't needed, as element size is always 32 or 64 bits. */
14004 && (bytemode
== xmmq_mode
14005 || bytemode
== evex_half_bcst_xmmq_mode
))
14007 else if (bytemode
== xmmqd_mode
)
14009 else if (bytemode
== xmmdw_mode
)
14011 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
14019 intel_operand_size (bytemode
, sizeflag
);
14022 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14024 /* 32/64 bit address mode */
14034 int addr32flag
= !((sizeflag
& AFLAG
)
14035 || bytemode
== v_bnd_mode
14036 || bytemode
== v_bndmk_mode
14037 || bytemode
== bnd_mode
14038 || bytemode
== bnd_swap_mode
);
14039 const char **indexes64
= names64
;
14040 const char **indexes32
= names32
;
14050 vindex
= sib
.index
;
14056 case vex_vsib_d_w_dq_mode
:
14057 case vex_vsib_d_w_d_mode
:
14058 case vex_vsib_q_w_dq_mode
:
14059 case vex_vsib_q_w_d_mode
:
14069 switch (vex
.length
)
14072 indexes64
= indexes32
= names_xmm
;
14076 || bytemode
== vex_vsib_q_w_dq_mode
14077 || bytemode
== vex_vsib_q_w_d_mode
)
14078 indexes64
= indexes32
= names_ymm
;
14080 indexes64
= indexes32
= names_xmm
;
14084 || bytemode
== vex_vsib_q_w_dq_mode
14085 || bytemode
== vex_vsib_q_w_d_mode
)
14086 indexes64
= indexes32
= names_zmm
;
14088 indexes64
= indexes32
= names_ymm
;
14095 haveindex
= vindex
!= 4;
14102 rbase
= base
+ add
;
14110 if (address_mode
== mode_64bit
&& !havesib
)
14113 if (riprel
&& bytemode
== v_bndmk_mode
)
14121 FETCH_DATA (the_info
, codep
+ 1);
14123 if ((disp
& 0x80) != 0)
14125 if (vex
.evex
&& shift
> 0)
14138 && address_mode
!= mode_16bit
)
14140 if (address_mode
== mode_64bit
)
14142 /* Display eiz instead of addr32. */
14143 needindex
= addr32flag
;
14148 /* In 32-bit mode, we need index register to tell [offset]
14149 from [eiz*1 + offset]. */
14154 havedisp
= (havebase
14156 || (havesib
&& (haveindex
|| scale
!= 0)));
14159 if (modrm
.mod
!= 0 || base
== 5)
14161 if (havedisp
|| riprel
)
14162 print_displacement (scratchbuf
, disp
);
14164 print_operand_value (scratchbuf
, 1, disp
);
14165 oappend (scratchbuf
);
14169 oappend (!addr32flag
? "(%rip)" : "(%eip)");
14173 if ((havebase
|| haveindex
|| needindex
|| needaddr32
|| riprel
)
14174 && (bytemode
!= v_bnd_mode
)
14175 && (bytemode
!= v_bndmk_mode
)
14176 && (bytemode
!= bnd_mode
)
14177 && (bytemode
!= bnd_swap_mode
))
14178 used_prefixes
|= PREFIX_ADDR
;
14180 if (havedisp
|| (intel_syntax
&& riprel
))
14182 *obufp
++ = open_char
;
14183 if (intel_syntax
&& riprel
)
14186 oappend (!addr32flag
? "rip" : "eip");
14190 oappend (address_mode
== mode_64bit
&& !addr32flag
14191 ? names64
[rbase
] : names32
[rbase
]);
14194 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14195 print index to tell base + index from base. */
14199 || (havebase
&& base
!= ESP_REG_NUM
))
14201 if (!intel_syntax
|| havebase
)
14203 *obufp
++ = separator_char
;
14207 oappend (address_mode
== mode_64bit
&& !addr32flag
14208 ? indexes64
[vindex
] : indexes32
[vindex
]);
14210 oappend (address_mode
== mode_64bit
&& !addr32flag
14211 ? index64
: index32
);
14213 *obufp
++ = scale_char
;
14215 sprintf (scratchbuf
, "%d", 1 << scale
);
14216 oappend (scratchbuf
);
14220 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14222 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14227 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14231 disp
= - (bfd_signed_vma
) disp
;
14235 print_displacement (scratchbuf
, disp
);
14237 print_operand_value (scratchbuf
, 1, disp
);
14238 oappend (scratchbuf
);
14241 *obufp
++ = close_char
;
14244 else if (intel_syntax
)
14246 if (modrm
.mod
!= 0 || base
== 5)
14248 if (!active_seg_prefix
)
14250 oappend (names_seg
[ds_reg
- es_reg
]);
14253 print_operand_value (scratchbuf
, 1, disp
);
14254 oappend (scratchbuf
);
14260 /* 16 bit address mode */
14261 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14268 if ((disp
& 0x8000) != 0)
14273 FETCH_DATA (the_info
, codep
+ 1);
14275 if ((disp
& 0x80) != 0)
14277 if (vex
.evex
&& shift
> 0)
14282 if ((disp
& 0x8000) != 0)
14288 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14290 print_displacement (scratchbuf
, disp
);
14291 oappend (scratchbuf
);
14294 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14296 *obufp
++ = open_char
;
14298 oappend (index16
[modrm
.rm
]);
14300 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14302 if ((bfd_signed_vma
) disp
>= 0)
14307 else if (modrm
.mod
!= 1)
14311 disp
= - (bfd_signed_vma
) disp
;
14314 print_displacement (scratchbuf
, disp
);
14315 oappend (scratchbuf
);
14318 *obufp
++ = close_char
;
14321 else if (intel_syntax
)
14323 if (!active_seg_prefix
)
14325 oappend (names_seg
[ds_reg
- es_reg
]);
14328 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14329 oappend (scratchbuf
);
14332 if (vex
.evex
&& vex
.b
14333 && (bytemode
== x_mode
14334 || bytemode
== xmmq_mode
14335 || bytemode
== evex_half_bcst_xmmq_mode
))
14338 || bytemode
== xmmq_mode
14339 || bytemode
== evex_half_bcst_xmmq_mode
)
14341 switch (vex
.length
)
14344 oappend ("{1to2}");
14347 oappend ("{1to4}");
14350 oappend ("{1to8}");
14358 switch (vex
.length
)
14361 oappend ("{1to4}");
14364 oappend ("{1to8}");
14367 oappend ("{1to16}");
14377 OP_E (int bytemode
, int sizeflag
)
14379 /* Skip mod/rm byte. */
14383 if (modrm
.mod
== 3)
14384 OP_E_register (bytemode
, sizeflag
);
14386 OP_E_memory (bytemode
, sizeflag
);
14390 OP_G (int bytemode
, int sizeflag
)
14393 const char **names
;
14402 oappend (names8rex
[modrm
.reg
+ add
]);
14404 oappend (names8
[modrm
.reg
+ add
]);
14407 oappend (names16
[modrm
.reg
+ add
]);
14412 oappend (names32
[modrm
.reg
+ add
]);
14415 oappend (names64
[modrm
.reg
+ add
]);
14418 if (modrm
.reg
> 0x3)
14423 oappend (names_bnd
[modrm
.reg
]);
14432 oappend (names64
[modrm
.reg
+ add
]);
14435 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14436 oappend (names32
[modrm
.reg
+ add
]);
14438 oappend (names16
[modrm
.reg
+ add
]);
14439 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14443 names
= (address_mode
== mode_64bit
14444 ? names64
: names32
);
14445 if (!(prefixes
& PREFIX_ADDR
))
14447 if (address_mode
== mode_16bit
)
14452 /* Remove "addr16/addr32". */
14453 all_prefixes
[last_addr_prefix
] = 0;
14454 names
= (address_mode
!= mode_32bit
14455 ? names32
: names16
);
14456 used_prefixes
|= PREFIX_ADDR
;
14458 oappend (names
[modrm
.reg
+ add
]);
14461 if (address_mode
== mode_64bit
)
14462 oappend (names64
[modrm
.reg
+ add
]);
14464 oappend (names32
[modrm
.reg
+ add
]);
14468 if ((modrm
.reg
+ add
) > 0x7)
14473 oappend (names_mask
[modrm
.reg
+ add
]);
14476 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14489 FETCH_DATA (the_info
, codep
+ 8);
14490 a
= *codep
++ & 0xff;
14491 a
|= (*codep
++ & 0xff) << 8;
14492 a
|= (*codep
++ & 0xff) << 16;
14493 a
|= (*codep
++ & 0xffu
) << 24;
14494 b
= *codep
++ & 0xff;
14495 b
|= (*codep
++ & 0xff) << 8;
14496 b
|= (*codep
++ & 0xff) << 16;
14497 b
|= (*codep
++ & 0xffu
) << 24;
14498 x
= a
+ ((bfd_vma
) b
<< 32);
14506 static bfd_signed_vma
14509 bfd_signed_vma x
= 0;
14511 FETCH_DATA (the_info
, codep
+ 4);
14512 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14513 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14514 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14515 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14519 static bfd_signed_vma
14522 bfd_signed_vma x
= 0;
14524 FETCH_DATA (the_info
, codep
+ 4);
14525 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14526 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14527 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14528 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14530 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14540 FETCH_DATA (the_info
, codep
+ 2);
14541 x
= *codep
++ & 0xff;
14542 x
|= (*codep
++ & 0xff) << 8;
14547 set_op (bfd_vma op
, int riprel
)
14549 op_index
[op_ad
] = op_ad
;
14550 if (address_mode
== mode_64bit
)
14552 op_address
[op_ad
] = op
;
14553 op_riprel
[op_ad
] = riprel
;
14557 /* Mask to get a 32-bit address. */
14558 op_address
[op_ad
] = op
& 0xffffffff;
14559 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14564 OP_REG (int code
, int sizeflag
)
14571 case es_reg
: case ss_reg
: case cs_reg
:
14572 case ds_reg
: case fs_reg
: case gs_reg
:
14573 oappend (names_seg
[code
- es_reg
]);
14585 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14586 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14587 s
= names16
[code
- ax_reg
+ add
];
14589 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14590 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14593 s
= names8rex
[code
- al_reg
+ add
];
14595 s
= names8
[code
- al_reg
];
14597 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14598 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14599 if (address_mode
== mode_64bit
14600 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14602 s
= names64
[code
- rAX_reg
+ add
];
14605 code
+= eAX_reg
- rAX_reg
;
14606 /* Fall through. */
14607 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14608 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14611 s
= names64
[code
- eAX_reg
+ add
];
14614 if (sizeflag
& DFLAG
)
14615 s
= names32
[code
- eAX_reg
+ add
];
14617 s
= names16
[code
- eAX_reg
+ add
];
14618 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14622 s
= INTERNAL_DISASSEMBLER_ERROR
;
14629 OP_IMREG (int code
, int sizeflag
)
14641 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14642 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14643 s
= names16
[code
- ax_reg
];
14645 case es_reg
: case ss_reg
: case cs_reg
:
14646 case ds_reg
: case fs_reg
: case gs_reg
:
14647 s
= names_seg
[code
- es_reg
];
14649 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14650 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14653 s
= names8rex
[code
- al_reg
];
14655 s
= names8
[code
- al_reg
];
14657 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14658 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14661 s
= names64
[code
- eAX_reg
];
14664 if (sizeflag
& DFLAG
)
14665 s
= names32
[code
- eAX_reg
];
14667 s
= names16
[code
- eAX_reg
];
14668 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14671 case z_mode_ax_reg
:
14672 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14676 if (!(rex
& REX_W
))
14677 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14680 s
= INTERNAL_DISASSEMBLER_ERROR
;
14687 OP_I (int bytemode
, int sizeflag
)
14690 bfd_signed_vma mask
= -1;
14695 FETCH_DATA (the_info
, codep
+ 1);
14705 if (sizeflag
& DFLAG
)
14715 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14731 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14736 scratchbuf
[0] = '$';
14737 print_operand_value (scratchbuf
+ 1, 1, op
);
14738 oappend_maybe_intel (scratchbuf
);
14739 scratchbuf
[0] = '\0';
14743 OP_I64 (int bytemode
, int sizeflag
)
14745 if (bytemode
!= v_mode
|| address_mode
!= mode_64bit
|| !(rex
& REX_W
))
14747 OP_I (bytemode
, sizeflag
);
14753 scratchbuf
[0] = '$';
14754 print_operand_value (scratchbuf
+ 1, 1, get64 ());
14755 oappend_maybe_intel (scratchbuf
);
14756 scratchbuf
[0] = '\0';
14760 OP_sI (int bytemode
, int sizeflag
)
14768 FETCH_DATA (the_info
, codep
+ 1);
14770 if ((op
& 0x80) != 0)
14772 if (bytemode
== b_T_mode
)
14774 if (address_mode
!= mode_64bit
14775 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14777 /* The operand-size prefix is overridden by a REX prefix. */
14778 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14786 if (!(rex
& REX_W
))
14788 if (sizeflag
& DFLAG
)
14796 /* The operand-size prefix is overridden by a REX prefix. */
14797 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
14803 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14807 scratchbuf
[0] = '$';
14808 print_operand_value (scratchbuf
+ 1, 1, op
);
14809 oappend_maybe_intel (scratchbuf
);
14813 OP_J (int bytemode
, int sizeflag
)
14817 bfd_vma segment
= 0;
14822 FETCH_DATA (the_info
, codep
+ 1);
14824 if ((disp
& 0x80) != 0)
14828 if (isa64
== amd64
)
14830 if ((sizeflag
& DFLAG
)
14831 || (address_mode
== mode_64bit
14832 && (isa64
!= amd64
|| (rex
& REX_W
))))
14837 if ((disp
& 0x8000) != 0)
14839 /* In 16bit mode, address is wrapped around at 64k within
14840 the same segment. Otherwise, a data16 prefix on a jump
14841 instruction means that the pc is masked to 16 bits after
14842 the displacement is added! */
14844 if ((prefixes
& PREFIX_DATA
) == 0)
14845 segment
= ((start_pc
+ (codep
- start_codep
))
14846 & ~((bfd_vma
) 0xffff));
14848 if (address_mode
!= mode_64bit
14849 || (isa64
== amd64
&& !(rex
& REX_W
)))
14850 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14853 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14856 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
14858 print_operand_value (scratchbuf
, 1, disp
);
14859 oappend (scratchbuf
);
14863 OP_SEG (int bytemode
, int sizeflag
)
14865 if (bytemode
== w_mode
)
14866 oappend (names_seg
[modrm
.reg
]);
14868 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
14872 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
14876 if (sizeflag
& DFLAG
)
14886 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14888 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
14890 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
14891 oappend (scratchbuf
);
14895 OP_OFF (int bytemode
, int sizeflag
)
14899 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14900 intel_operand_size (bytemode
, sizeflag
);
14903 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14910 if (!active_seg_prefix
)
14912 oappend (names_seg
[ds_reg
- es_reg
]);
14916 print_operand_value (scratchbuf
, 1, off
);
14917 oappend (scratchbuf
);
14921 OP_OFF64 (int bytemode
, int sizeflag
)
14925 if (address_mode
!= mode_64bit
14926 || (prefixes
& PREFIX_ADDR
))
14928 OP_OFF (bytemode
, sizeflag
);
14932 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
14933 intel_operand_size (bytemode
, sizeflag
);
14940 if (!active_seg_prefix
)
14942 oappend (names_seg
[ds_reg
- es_reg
]);
14946 print_operand_value (scratchbuf
, 1, off
);
14947 oappend (scratchbuf
);
14951 ptr_reg (int code
, int sizeflag
)
14955 *obufp
++ = open_char
;
14956 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14957 if (address_mode
== mode_64bit
)
14959 if (!(sizeflag
& AFLAG
))
14960 s
= names32
[code
- eAX_reg
];
14962 s
= names64
[code
- eAX_reg
];
14964 else if (sizeflag
& AFLAG
)
14965 s
= names32
[code
- eAX_reg
];
14967 s
= names16
[code
- eAX_reg
];
14969 *obufp
++ = close_char
;
14974 OP_ESreg (int code
, int sizeflag
)
14980 case 0x6d: /* insw/insl */
14981 intel_operand_size (z_mode
, sizeflag
);
14983 case 0xa5: /* movsw/movsl/movsq */
14984 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14985 case 0xab: /* stosw/stosl */
14986 case 0xaf: /* scasw/scasl */
14987 intel_operand_size (v_mode
, sizeflag
);
14990 intel_operand_size (b_mode
, sizeflag
);
14993 oappend_maybe_intel ("%es:");
14994 ptr_reg (code
, sizeflag
);
14998 OP_DSreg (int code
, int sizeflag
)
15004 case 0x6f: /* outsw/outsl */
15005 intel_operand_size (z_mode
, sizeflag
);
15007 case 0xa5: /* movsw/movsl/movsq */
15008 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15009 case 0xad: /* lodsw/lodsl/lodsq */
15010 intel_operand_size (v_mode
, sizeflag
);
15013 intel_operand_size (b_mode
, sizeflag
);
15016 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15017 default segment register DS is printed. */
15018 if (!active_seg_prefix
)
15019 active_seg_prefix
= PREFIX_DS
;
15021 ptr_reg (code
, sizeflag
);
15025 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15033 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15035 all_prefixes
[last_lock_prefix
] = 0;
15036 used_prefixes
|= PREFIX_LOCK
;
15041 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15042 oappend_maybe_intel (scratchbuf
);
15046 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15055 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15057 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15058 oappend (scratchbuf
);
15062 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15064 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15065 oappend_maybe_intel (scratchbuf
);
15069 OP_R (int bytemode
, int sizeflag
)
15071 /* Skip mod/rm byte. */
15074 OP_E_register (bytemode
, sizeflag
);
15078 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15080 int reg
= modrm
.reg
;
15081 const char **names
;
15083 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15084 if (prefixes
& PREFIX_DATA
)
15093 oappend (names
[reg
]);
15097 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15099 int reg
= modrm
.reg
;
15100 const char **names
;
15112 && bytemode
!= xmm_mode
15113 && bytemode
!= xmmq_mode
15114 && bytemode
!= evex_half_bcst_xmmq_mode
15115 && bytemode
!= ymm_mode
15116 && bytemode
!= scalar_mode
)
15118 switch (vex
.length
)
15125 || (bytemode
!= vex_vsib_q_w_dq_mode
15126 && bytemode
!= vex_vsib_q_w_d_mode
))
15138 else if (bytemode
== xmmq_mode
15139 || bytemode
== evex_half_bcst_xmmq_mode
)
15141 switch (vex
.length
)
15154 else if (bytemode
== ymm_mode
)
15158 oappend (names
[reg
]);
15162 OP_EM (int bytemode
, int sizeflag
)
15165 const char **names
;
15167 if (modrm
.mod
!= 3)
15170 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15172 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15173 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15175 OP_E (bytemode
, sizeflag
);
15179 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15182 /* Skip mod/rm byte. */
15185 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15187 if (prefixes
& PREFIX_DATA
)
15196 oappend (names
[reg
]);
15199 /* cvt* are the only instructions in sse2 which have
15200 both SSE and MMX operands and also have 0x66 prefix
15201 in their opcode. 0x66 was originally used to differentiate
15202 between SSE and MMX instruction(operands). So we have to handle the
15203 cvt* separately using OP_EMC and OP_MXC */
15205 OP_EMC (int bytemode
, int sizeflag
)
15207 if (modrm
.mod
!= 3)
15209 if (intel_syntax
&& bytemode
== v_mode
)
15211 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15212 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15214 OP_E (bytemode
, sizeflag
);
15218 /* Skip mod/rm byte. */
15221 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15222 oappend (names_mm
[modrm
.rm
]);
15226 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15228 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15229 oappend (names_mm
[modrm
.reg
]);
15233 OP_EX (int bytemode
, int sizeflag
)
15236 const char **names
;
15238 /* Skip mod/rm byte. */
15242 if (modrm
.mod
!= 3)
15244 OP_E_memory (bytemode
, sizeflag
);
15259 if ((sizeflag
& SUFFIX_ALWAYS
)
15260 && (bytemode
== x_swap_mode
15261 || bytemode
== d_swap_mode
15262 || bytemode
== d_scalar_swap_mode
15263 || bytemode
== q_swap_mode
15264 || bytemode
== q_scalar_swap_mode
))
15268 && bytemode
!= xmm_mode
15269 && bytemode
!= xmmdw_mode
15270 && bytemode
!= xmmqd_mode
15271 && bytemode
!= xmm_mb_mode
15272 && bytemode
!= xmm_mw_mode
15273 && bytemode
!= xmm_md_mode
15274 && bytemode
!= xmm_mq_mode
15275 && bytemode
!= xmm_mdq_mode
15276 && bytemode
!= xmmq_mode
15277 && bytemode
!= evex_half_bcst_xmmq_mode
15278 && bytemode
!= ymm_mode
15279 && bytemode
!= d_scalar_mode
15280 && bytemode
!= d_scalar_swap_mode
15281 && bytemode
!= q_scalar_mode
15282 && bytemode
!= q_scalar_swap_mode
15283 && bytemode
!= vex_scalar_w_dq_mode
)
15285 switch (vex
.length
)
15300 else if (bytemode
== xmmq_mode
15301 || bytemode
== evex_half_bcst_xmmq_mode
)
15303 switch (vex
.length
)
15316 else if (bytemode
== ymm_mode
)
15320 oappend (names
[reg
]);
15324 OP_MS (int bytemode
, int sizeflag
)
15326 if (modrm
.mod
== 3)
15327 OP_EM (bytemode
, sizeflag
);
15333 OP_XS (int bytemode
, int sizeflag
)
15335 if (modrm
.mod
== 3)
15336 OP_EX (bytemode
, sizeflag
);
15342 OP_M (int bytemode
, int sizeflag
)
15344 if (modrm
.mod
== 3)
15345 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15348 OP_E (bytemode
, sizeflag
);
15352 OP_0f07 (int bytemode
, int sizeflag
)
15354 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15357 OP_E (bytemode
, sizeflag
);
15360 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15361 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15364 NOP_Fixup1 (int bytemode
, int sizeflag
)
15366 if ((prefixes
& PREFIX_DATA
) != 0
15369 && address_mode
== mode_64bit
))
15370 OP_REG (bytemode
, sizeflag
);
15372 strcpy (obuf
, "nop");
15376 NOP_Fixup2 (int bytemode
, int sizeflag
)
15378 if ((prefixes
& PREFIX_DATA
) != 0
15381 && address_mode
== mode_64bit
))
15382 OP_IMREG (bytemode
, sizeflag
);
15385 static const char *const Suffix3DNow
[] = {
15386 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15387 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15388 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15389 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15390 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15391 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15392 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15393 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15394 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15395 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15396 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15397 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15398 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15399 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15400 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15401 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15402 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15403 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15404 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15405 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15406 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15407 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15408 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15409 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15410 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15411 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15412 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15413 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15414 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15415 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15416 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15417 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15418 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15419 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15420 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15421 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15422 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15423 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15424 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15425 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15426 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15427 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15428 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15429 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15430 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15431 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15432 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15433 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15434 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15435 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15436 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15437 /* CC */ NULL
, NULL
, NULL
, NULL
,
15438 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15439 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15440 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15441 /* DC */ NULL
, NULL
, NULL
, NULL
,
15442 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15443 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15444 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15445 /* EC */ NULL
, NULL
, NULL
, NULL
,
15446 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15447 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15448 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15449 /* FC */ NULL
, NULL
, NULL
, NULL
,
15453 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15455 const char *mnemonic
;
15457 FETCH_DATA (the_info
, codep
+ 1);
15458 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15459 place where an 8-bit immediate would normally go. ie. the last
15460 byte of the instruction. */
15461 obufp
= mnemonicendp
;
15462 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15464 oappend (mnemonic
);
15467 /* Since a variable sized modrm/sib chunk is between the start
15468 of the opcode (0x0f0f) and the opcode suffix, we need to do
15469 all the modrm processing first, and don't know until now that
15470 we have a bad opcode. This necessitates some cleaning up. */
15471 op_out
[0][0] = '\0';
15472 op_out
[1][0] = '\0';
15475 mnemonicendp
= obufp
;
15478 static struct op simd_cmp_op
[] =
15480 { STRING_COMMA_LEN ("eq") },
15481 { STRING_COMMA_LEN ("lt") },
15482 { STRING_COMMA_LEN ("le") },
15483 { STRING_COMMA_LEN ("unord") },
15484 { STRING_COMMA_LEN ("neq") },
15485 { STRING_COMMA_LEN ("nlt") },
15486 { STRING_COMMA_LEN ("nle") },
15487 { STRING_COMMA_LEN ("ord") }
15491 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15493 unsigned int cmp_type
;
15495 FETCH_DATA (the_info
, codep
+ 1);
15496 cmp_type
= *codep
++ & 0xff;
15497 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15500 char *p
= mnemonicendp
- 2;
15504 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15505 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15509 /* We have a reserved extension byte. Output it directly. */
15510 scratchbuf
[0] = '$';
15511 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15512 oappend_maybe_intel (scratchbuf
);
15513 scratchbuf
[0] = '\0';
15518 OP_Mwait (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15520 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
15523 const char **names
= (address_mode
== mode_64bit
15524 ? names64
: names32
);
15525 strcpy (op_out
[0], names
[0]);
15526 strcpy (op_out
[1], names
[1]);
15527 if (bytemode
== eBX_reg
)
15528 strcpy (op_out
[2], names
[3]);
15529 two_source_ops
= 1;
15531 /* Skip mod/rm byte. */
15537 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15538 int sizeflag ATTRIBUTE_UNUSED
)
15540 /* monitor %eax,%ecx,%edx" */
15543 const char **op1_names
;
15544 const char **names
= (address_mode
== mode_64bit
15545 ? names64
: names32
);
15547 if (!(prefixes
& PREFIX_ADDR
))
15548 op1_names
= (address_mode
== mode_16bit
15549 ? names16
: names
);
15552 /* Remove "addr16/addr32". */
15553 all_prefixes
[last_addr_prefix
] = 0;
15554 op1_names
= (address_mode
!= mode_32bit
15555 ? names32
: names16
);
15556 used_prefixes
|= PREFIX_ADDR
;
15558 strcpy (op_out
[0], op1_names
[0]);
15559 strcpy (op_out
[1], names
[1]);
15560 strcpy (op_out
[2], names
[2]);
15561 two_source_ops
= 1;
15563 /* Skip mod/rm byte. */
15571 /* Throw away prefixes and 1st. opcode byte. */
15572 codep
= insn_codep
+ 1;
15577 REP_Fixup (int bytemode
, int sizeflag
)
15579 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15581 if (prefixes
& PREFIX_REPZ
)
15582 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15589 OP_IMREG (bytemode
, sizeflag
);
15592 OP_ESreg (bytemode
, sizeflag
);
15595 OP_DSreg (bytemode
, sizeflag
);
15603 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15607 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15609 if (prefixes
& PREFIX_REPNZ
)
15610 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15613 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15617 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
15618 int sizeflag ATTRIBUTE_UNUSED
)
15620 if (active_seg_prefix
== PREFIX_DS
15621 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
15623 /* NOTRACK prefix is only valid on indirect branch instructions.
15624 NB: DATA prefix is unsupported for Intel64. */
15625 active_seg_prefix
= 0;
15626 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
15630 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15631 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15635 HLE_Fixup1 (int bytemode
, int sizeflag
)
15638 && (prefixes
& PREFIX_LOCK
) != 0)
15640 if (prefixes
& PREFIX_REPZ
)
15641 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15642 if (prefixes
& PREFIX_REPNZ
)
15643 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15646 OP_E (bytemode
, sizeflag
);
15649 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15650 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15654 HLE_Fixup2 (int bytemode
, int sizeflag
)
15656 if (modrm
.mod
!= 3)
15658 if (prefixes
& PREFIX_REPZ
)
15659 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15660 if (prefixes
& PREFIX_REPNZ
)
15661 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15664 OP_E (bytemode
, sizeflag
);
15667 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15668 "xrelease" for memory operand. No check for LOCK prefix. */
15671 HLE_Fixup3 (int bytemode
, int sizeflag
)
15674 && last_repz_prefix
> last_repnz_prefix
15675 && (prefixes
& PREFIX_REPZ
) != 0)
15676 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15678 OP_E (bytemode
, sizeflag
);
15682 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15687 /* Change cmpxchg8b to cmpxchg16b. */
15688 char *p
= mnemonicendp
- 2;
15689 mnemonicendp
= stpcpy (p
, "16b");
15692 else if ((prefixes
& PREFIX_LOCK
) != 0)
15694 if (prefixes
& PREFIX_REPZ
)
15695 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15696 if (prefixes
& PREFIX_REPNZ
)
15697 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15700 OP_M (bytemode
, sizeflag
);
15704 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15706 const char **names
;
15710 switch (vex
.length
)
15724 oappend (names
[reg
]);
15728 CRC32_Fixup (int bytemode
, int sizeflag
)
15730 /* Add proper suffix to "crc32". */
15731 char *p
= mnemonicendp
;
15750 if (sizeflag
& DFLAG
)
15754 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15758 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15765 if (modrm
.mod
== 3)
15769 /* Skip mod/rm byte. */
15774 add
= (rex
& REX_B
) ? 8 : 0;
15775 if (bytemode
== b_mode
)
15779 oappend (names8rex
[modrm
.rm
+ add
]);
15781 oappend (names8
[modrm
.rm
+ add
]);
15787 oappend (names64
[modrm
.rm
+ add
]);
15788 else if ((prefixes
& PREFIX_DATA
))
15789 oappend (names16
[modrm
.rm
+ add
]);
15791 oappend (names32
[modrm
.rm
+ add
]);
15795 OP_E (bytemode
, sizeflag
);
15799 FXSAVE_Fixup (int bytemode
, int sizeflag
)
15801 /* Add proper suffix to "fxsave" and "fxrstor". */
15805 char *p
= mnemonicendp
;
15811 OP_M (bytemode
, sizeflag
);
15815 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
15817 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15820 char *p
= mnemonicendp
;
15825 else if (sizeflag
& SUFFIX_ALWAYS
)
15832 OP_EX (bytemode
, sizeflag
);
15835 /* Display the destination register operand for instructions with
15839 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15842 const char **names
;
15850 reg
= vex
.register_specifier
;
15851 vex
.register_specifier
= 0;
15852 if (address_mode
!= mode_64bit
)
15854 else if (vex
.evex
&& !vex
.v
)
15857 if (bytemode
== vex_scalar_mode
)
15859 oappend (names_xmm
[reg
]);
15863 switch (vex
.length
)
15870 case vex_vsib_q_w_dq_mode
:
15871 case vex_vsib_q_w_d_mode
:
15887 names
= names_mask
;
15901 case vex_vsib_q_w_dq_mode
:
15902 case vex_vsib_q_w_d_mode
:
15903 names
= vex
.w
? names_ymm
: names_xmm
;
15912 names
= names_mask
;
15915 /* See PR binutils/20893 for a reproducer. */
15927 oappend (names
[reg
]);
15930 /* Get the VEX immediate byte without moving codep. */
15932 static unsigned char
15933 get_vex_imm8 (int sizeflag
, int opnum
)
15935 int bytes_before_imm
= 0;
15937 if (modrm
.mod
!= 3)
15939 /* There are SIB/displacement bytes. */
15940 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15942 /* 32/64 bit address mode */
15943 int base
= modrm
.rm
;
15945 /* Check SIB byte. */
15948 FETCH_DATA (the_info
, codep
+ 1);
15950 /* When decoding the third source, don't increase
15951 bytes_before_imm as this has already been incremented
15952 by one in OP_E_memory while decoding the second
15955 bytes_before_imm
++;
15958 /* Don't increase bytes_before_imm when decoding the third source,
15959 it has already been incremented by OP_E_memory while decoding
15960 the second source operand. */
15966 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15967 SIB == 5, there is a 4 byte displacement. */
15969 /* No displacement. */
15971 /* Fall through. */
15973 /* 4 byte displacement. */
15974 bytes_before_imm
+= 4;
15977 /* 1 byte displacement. */
15978 bytes_before_imm
++;
15985 /* 16 bit address mode */
15986 /* Don't increase bytes_before_imm when decoding the third source,
15987 it has already been incremented by OP_E_memory while decoding
15988 the second source operand. */
15994 /* When modrm.rm == 6, there is a 2 byte displacement. */
15996 /* No displacement. */
15998 /* Fall through. */
16000 /* 2 byte displacement. */
16001 bytes_before_imm
+= 2;
16004 /* 1 byte displacement: when decoding the third source,
16005 don't increase bytes_before_imm as this has already
16006 been incremented by one in OP_E_memory while decoding
16007 the second source operand. */
16009 bytes_before_imm
++;
16017 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16018 return codep
[bytes_before_imm
];
16022 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16024 const char **names
;
16026 if (reg
== -1 && modrm
.mod
!= 3)
16028 OP_E_memory (bytemode
, sizeflag
);
16040 if (address_mode
!= mode_64bit
)
16044 switch (vex
.length
)
16055 oappend (names
[reg
]);
16059 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16062 static unsigned char vex_imm8
;
16064 if (vex_w_done
== 0)
16068 /* Skip mod/rm byte. */
16072 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16075 reg
= vex_imm8
>> 4;
16077 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16079 else if (vex_w_done
== 1)
16084 reg
= vex_imm8
>> 4;
16086 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16090 /* Output the imm8 directly. */
16091 scratchbuf
[0] = '$';
16092 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16093 oappend_maybe_intel (scratchbuf
);
16094 scratchbuf
[0] = '\0';
16100 OP_Vex_2src (int bytemode
, int sizeflag
)
16102 if (modrm
.mod
== 3)
16104 int reg
= modrm
.rm
;
16108 oappend (names_xmm
[reg
]);
16113 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16115 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16116 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16118 OP_E (bytemode
, sizeflag
);
16123 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16125 if (modrm
.mod
== 3)
16127 /* Skip mod/rm byte. */
16134 unsigned int reg
= vex
.register_specifier
;
16135 vex
.register_specifier
= 0;
16137 if (address_mode
!= mode_64bit
)
16139 oappend (names_xmm
[reg
]);
16142 OP_Vex_2src (bytemode
, sizeflag
);
16146 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16149 OP_Vex_2src (bytemode
, sizeflag
);
16152 unsigned int reg
= vex
.register_specifier
;
16153 vex
.register_specifier
= 0;
16155 if (address_mode
!= mode_64bit
)
16157 oappend (names_xmm
[reg
]);
16162 OP_EX_VexW (int bytemode
, int sizeflag
)
16168 /* Skip mod/rm byte. */
16173 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16178 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16181 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16189 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16192 const char **names
;
16194 FETCH_DATA (the_info
, codep
+ 1);
16197 if (bytemode
!= x_mode
)
16201 if (address_mode
!= mode_64bit
)
16204 switch (vex
.length
)
16215 oappend (names
[reg
]);
16219 OP_XMM_VexW (int bytemode
, int sizeflag
)
16221 /* Turn off the REX.W bit since it is used for swapping operands
16224 OP_XMM (bytemode
, sizeflag
);
16228 OP_EX_Vex (int bytemode
, int sizeflag
)
16230 if (modrm
.mod
!= 3)
16232 OP_EX (bytemode
, sizeflag
);
16236 OP_XMM_Vex (int bytemode
, int sizeflag
)
16238 if (modrm
.mod
!= 3)
16240 OP_XMM (bytemode
, sizeflag
);
16243 static struct op vex_cmp_op
[] =
16245 { STRING_COMMA_LEN ("eq") },
16246 { STRING_COMMA_LEN ("lt") },
16247 { STRING_COMMA_LEN ("le") },
16248 { STRING_COMMA_LEN ("unord") },
16249 { STRING_COMMA_LEN ("neq") },
16250 { STRING_COMMA_LEN ("nlt") },
16251 { STRING_COMMA_LEN ("nle") },
16252 { STRING_COMMA_LEN ("ord") },
16253 { STRING_COMMA_LEN ("eq_uq") },
16254 { STRING_COMMA_LEN ("nge") },
16255 { STRING_COMMA_LEN ("ngt") },
16256 { STRING_COMMA_LEN ("false") },
16257 { STRING_COMMA_LEN ("neq_oq") },
16258 { STRING_COMMA_LEN ("ge") },
16259 { STRING_COMMA_LEN ("gt") },
16260 { STRING_COMMA_LEN ("true") },
16261 { STRING_COMMA_LEN ("eq_os") },
16262 { STRING_COMMA_LEN ("lt_oq") },
16263 { STRING_COMMA_LEN ("le_oq") },
16264 { STRING_COMMA_LEN ("unord_s") },
16265 { STRING_COMMA_LEN ("neq_us") },
16266 { STRING_COMMA_LEN ("nlt_uq") },
16267 { STRING_COMMA_LEN ("nle_uq") },
16268 { STRING_COMMA_LEN ("ord_s") },
16269 { STRING_COMMA_LEN ("eq_us") },
16270 { STRING_COMMA_LEN ("nge_uq") },
16271 { STRING_COMMA_LEN ("ngt_uq") },
16272 { STRING_COMMA_LEN ("false_os") },
16273 { STRING_COMMA_LEN ("neq_os") },
16274 { STRING_COMMA_LEN ("ge_oq") },
16275 { STRING_COMMA_LEN ("gt_oq") },
16276 { STRING_COMMA_LEN ("true_us") },
16280 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16282 unsigned int cmp_type
;
16284 FETCH_DATA (the_info
, codep
+ 1);
16285 cmp_type
= *codep
++ & 0xff;
16286 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16289 char *p
= mnemonicendp
- 2;
16293 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16294 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16298 /* We have a reserved extension byte. Output it directly. */
16299 scratchbuf
[0] = '$';
16300 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16301 oappend_maybe_intel (scratchbuf
);
16302 scratchbuf
[0] = '\0';
16307 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16308 int sizeflag ATTRIBUTE_UNUSED
)
16310 unsigned int cmp_type
;
16315 FETCH_DATA (the_info
, codep
+ 1);
16316 cmp_type
= *codep
++ & 0xff;
16317 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16318 If it's the case, print suffix, otherwise - print the immediate. */
16319 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16324 char *p
= mnemonicendp
- 2;
16326 /* vpcmp* can have both one- and two-lettered suffix. */
16340 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16341 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16345 /* We have a reserved extension byte. Output it directly. */
16346 scratchbuf
[0] = '$';
16347 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16348 oappend_maybe_intel (scratchbuf
);
16349 scratchbuf
[0] = '\0';
16353 static const struct op xop_cmp_op
[] =
16355 { STRING_COMMA_LEN ("lt") },
16356 { STRING_COMMA_LEN ("le") },
16357 { STRING_COMMA_LEN ("gt") },
16358 { STRING_COMMA_LEN ("ge") },
16359 { STRING_COMMA_LEN ("eq") },
16360 { STRING_COMMA_LEN ("neq") },
16361 { STRING_COMMA_LEN ("false") },
16362 { STRING_COMMA_LEN ("true") }
16366 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16367 int sizeflag ATTRIBUTE_UNUSED
)
16369 unsigned int cmp_type
;
16371 FETCH_DATA (the_info
, codep
+ 1);
16372 cmp_type
= *codep
++ & 0xff;
16373 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
16376 char *p
= mnemonicendp
- 2;
16378 /* vpcom* can have both one- and two-lettered suffix. */
16392 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
16393 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
16397 /* We have a reserved extension byte. Output it directly. */
16398 scratchbuf
[0] = '$';
16399 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16400 oappend_maybe_intel (scratchbuf
);
16401 scratchbuf
[0] = '\0';
16405 static const struct op pclmul_op
[] =
16407 { STRING_COMMA_LEN ("lql") },
16408 { STRING_COMMA_LEN ("hql") },
16409 { STRING_COMMA_LEN ("lqh") },
16410 { STRING_COMMA_LEN ("hqh") }
16414 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16415 int sizeflag ATTRIBUTE_UNUSED
)
16417 unsigned int pclmul_type
;
16419 FETCH_DATA (the_info
, codep
+ 1);
16420 pclmul_type
= *codep
++ & 0xff;
16421 switch (pclmul_type
)
16432 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16435 char *p
= mnemonicendp
- 3;
16440 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16441 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16445 /* We have a reserved extension byte. Output it directly. */
16446 scratchbuf
[0] = '$';
16447 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16448 oappend_maybe_intel (scratchbuf
);
16449 scratchbuf
[0] = '\0';
16454 MOVBE_Fixup (int bytemode
, int sizeflag
)
16456 /* Add proper suffix to "movbe". */
16457 char *p
= mnemonicendp
;
16466 if (sizeflag
& SUFFIX_ALWAYS
)
16472 if (sizeflag
& DFLAG
)
16476 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16481 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16488 OP_M (bytemode
, sizeflag
);
16492 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16495 const char **names
;
16497 /* Skip mod/rm byte. */
16511 oappend (names
[reg
]);
16515 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16517 const char **names
;
16518 unsigned int reg
= vex
.register_specifier
;
16519 vex
.register_specifier
= 0;
16526 if (address_mode
!= mode_64bit
)
16528 oappend (names
[reg
]);
16532 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16535 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
16539 if ((rex
& REX_R
) != 0 || !vex
.r
)
16545 oappend (names_mask
[modrm
.reg
]);
16549 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16552 || (bytemode
!= evex_rounding_mode
16553 && bytemode
!= evex_rounding_64_mode
16554 && bytemode
!= evex_sae_mode
))
16556 if (modrm
.mod
== 3 && vex
.b
)
16559 case evex_rounding_64_mode
:
16560 if (address_mode
!= mode_64bit
)
16565 /* Fall through. */
16566 case evex_rounding_mode
:
16567 oappend (names_rounding
[vex
.ll
]);
16569 case evex_sae_mode
: