opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void NOP_Fixup1 (int, int);
 105 static void NOP_Fixup2 (int, int);
 106 static void OP_3DNowSuffix (int, int);
 107 static void CMP_Fixup (int, int);
 108 static void BadOp (void);
 109 static void REP_Fixup (int, int);
 110 static void SEP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127 static void MOVSXD_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iv64 { OP_I64, v_mode }
 296 #define Id { OP_I, d_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Jdqw { OP_J, dqw_mode }
 302 #define Cm { OP_C, m_mode }
 303 #define Dm { OP_D, m_mode }
 304 #define Td { OP_T, d_mode }
 305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 306
 307 #define RMeAX { OP_REG, eAX_reg }
 308 #define RMeBX { OP_REG, eBX_reg }
 309 #define RMeCX { OP_REG, eCX_reg }
 310 #define RMeDX { OP_REG, eDX_reg }
 311 #define RMeSP { OP_REG, eSP_reg }
 312 #define RMeBP { OP_REG, eBP_reg }
 313 #define RMeSI { OP_REG, eSI_reg }
 314 #define RMeDI { OP_REG, eDI_reg }
 315 #define RMrAX { OP_REG, rAX_reg }
 316 #define RMrBX { OP_REG, rBX_reg }
 317 #define RMrCX { OP_REG, rCX_reg }
 318 #define RMrDX { OP_REG, rDX_reg }
 319 #define RMrSP { OP_REG, rSP_reg }
 320 #define RMrBP { OP_REG, rBP_reg }
 321 #define RMrSI { OP_REG, rSI_reg }
 322 #define RMrDI { OP_REG, rDI_reg }
 323 #define RMAL { OP_REG, al_reg }
 324 #define RMCL { OP_REG, cl_reg }
 325 #define RMDL { OP_REG, dl_reg }
 326 #define RMBL { OP_REG, bl_reg }
 327 #define RMAH { OP_REG, ah_reg }
 328 #define RMCH { OP_REG, ch_reg }
 329 #define RMDH { OP_REG, dh_reg }
 330 #define RMBH { OP_REG, bh_reg }
 331 #define RMAX { OP_REG, ax_reg }
 332 #define RMDX { OP_REG, dx_reg }
 333
 334 #define eAX { OP_IMREG, eAX_reg }
 335 #define eBX { OP_IMREG, eBX_reg }
 336 #define eCX { OP_IMREG, eCX_reg }
 337 #define eDX { OP_IMREG, eDX_reg }
 338 #define eSP { OP_IMREG, eSP_reg }
 339 #define eBP { OP_IMREG, eBP_reg }
 340 #define eSI { OP_IMREG, eSI_reg }
 341 #define eDI { OP_IMREG, eDI_reg }
 342 #define AL { OP_IMREG, al_reg }
 343 #define CL { OP_IMREG, cl_reg }
 344 #define DL { OP_IMREG, dl_reg }
 345 #define BL { OP_IMREG, bl_reg }
 346 #define AH { OP_IMREG, ah_reg }
 347 #define CH { OP_IMREG, ch_reg }
 348 #define DH { OP_IMREG, dh_reg }
 349 #define BH { OP_IMREG, bh_reg }
 350 #define AX { OP_IMREG, ax_reg }
 351 #define DX { OP_IMREG, dx_reg }
 352 #define zAX { OP_IMREG, z_mode_ax_reg }
 353 #define indirDX { OP_IMREG, indir_dx_reg }
 354
 355 #define Sw { OP_SEG, w_mode }
 356 #define Sv { OP_SEG, v_mode }
 357 #define Ap { OP_DIR, 0 }
 358 #define Ob { OP_OFF64, b_mode }
 359 #define Ov { OP_OFF64, v_mode }
 360 #define Xb { OP_DSreg, eSI_reg }
 361 #define Xv { OP_DSreg, eSI_reg }
 362 #define Xz { OP_DSreg, eSI_reg }
 363 #define Yb { OP_ESreg, eDI_reg }
 364 #define Yv { OP_ESreg, eDI_reg }
 365 #define DSBX { OP_DSreg, eBX_reg }
 366
 367 #define es { OP_REG, es_reg }
 368 #define ss { OP_REG, ss_reg }
 369 #define cs { OP_REG, cs_reg }
 370 #define ds { OP_REG, ds_reg }
 371 #define fs { OP_REG, fs_reg }
 372 #define gs { OP_REG, gs_reg }
 373
 374 #define MX { OP_MMX, 0 }
 375 #define XM { OP_XMM, 0 }
 376 #define XMScalar { OP_XMM, scalar_mode }
 377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 378 #define XMM { OP_XMM, xmm_mode }
 379 #define XMxmmq { OP_XMM, xmmq_mode }
 380 #define EM { OP_EM, v_mode }
 381 #define EMS { OP_EM, v_swap_mode }
 382 #define EMd { OP_EM, d_mode }
 383 #define EMx { OP_EM, x_mode }
 384 #define EXbScalar { OP_EX, b_scalar_mode }
 385 #define EXw { OP_EX, w_mode }
 386 #define EXwScalar { OP_EX, w_scalar_mode }
 387 #define EXd { OP_EX, d_mode }
 388 #define EXdScalar { OP_EX, d_scalar_mode }
 389 #define EXdS { OP_EX, d_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 411 #define MS { OP_MS, v_mode }
 412 #define XS { OP_XS, v_mode }
 413 #define EMCq { OP_EMC, q_mode }
 414 #define MXC { OP_MXC, 0 }
 415 #define OPSUF { OP_3DNowSuffix, 0 }
 416 #define SEP { SEP_Fixup, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 430 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 431 #define EXVexW { OP_EX_VexW, x_mode }
 432 #define EXdVexW { OP_EX_VexW, d_mode }
 433 #define EXqVexW { OP_EX_VexW, q_mode }
 434 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 435 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 436 #define XMVexW { OP_XMM_VexW, 0 }
 437 #define XMVexI4 { OP_REG_VexI4, x_mode }
 438 #define PCLMUL { PCLMUL_Fixup, 0 }
 439 #define VCMP { VCMP_Fixup, 0 }
 440 #define VPCMP { VPCMP_Fixup, 0 }
 441 #define VPCOM { VPCOM_Fixup, 0 }
 442
 443 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 444 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 445 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 446
 447 #define XMask { OP_Mask, mask_mode }
 448 #define MaskG { OP_G, mask_mode }
 449 #define MaskE { OP_E, mask_mode }
 450 #define MaskBDE { OP_E, mask_bd_mode }
 451 #define MaskR { OP_R, mask_mode }
 452 #define MaskVex { OP_VEX, mask_mode }
 453
 454 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 455 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 456 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 457 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 458
 459 /* Used handle "rep" prefix for string instructions.  */
 460 #define Xbr { REP_Fixup, eSI_reg }
 461 #define Xvr { REP_Fixup, eSI_reg }
 462 #define Ybr { REP_Fixup, eDI_reg }
 463 #define Yvr { REP_Fixup, eDI_reg }
 464 #define Yzr { REP_Fixup, eDI_reg }
 465 #define indirDXr { REP_Fixup, indir_dx_reg }
 466 #define ALr { REP_Fixup, al_reg }
 467 #define eAXr { REP_Fixup, eAX_reg }
 468
 469 /* Used handle HLE prefix for lockable instructions.  */
 470 #define Ebh1 { HLE_Fixup1, b_mode }
 471 #define Evh1 { HLE_Fixup1, v_mode }
 472 #define Ebh2 { HLE_Fixup2, b_mode }
 473 #define Evh2 { HLE_Fixup2, v_mode }
 474 #define Ebh3 { HLE_Fixup3, b_mode }
 475 #define Evh3 { HLE_Fixup3, v_mode }
 476
 477 #define BND { BND_Fixup, 0 }
 478 #define NOTRACK { NOTRACK_Fixup, 0 }
 479
 480 #define cond_jump_flag { NULL, cond_jump_mode }
 481 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 482
 483 /* bits in sizeflag */
 484 #define SUFFIX_ALWAYS 4
 485 #define AFLAG 2
 486 #define DFLAG 1
 487
 488 enum
 489 {
 490   /* byte operand */
 491   b_mode = 1,
 492   /* byte operand with operand swapped */
 493   b_swap_mode,
 494   /* byte operand, sign extend like 'T' suffix */
 495   b_T_mode,
 496   /* operand size depends on prefixes */
 497   v_mode,
 498   /* operand size depends on prefixes with operand swapped */
 499   v_swap_mode,
 500   /* operand size depends on address prefix */
 501   va_mode,
 502   /* word operand */
 503   w_mode,
 504   /* double word operand  */
 505   d_mode,
 506   /* double word operand with operand swapped */
 507   d_swap_mode,
 508   /* quad word operand */
 509   q_mode,
 510   /* quad word operand with operand swapped */
 511   q_swap_mode,
 512   /* ten-byte operand */
 513   t_mode,
 514   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 515      broadcast enabled.  */
 516   x_mode,
 517   /* Similar to x_mode, but with different EVEX mem shifts.  */
 518   evex_x_gscat_mode,
 519   /* Similar to x_mode, but with disabled broadcast.  */
 520   evex_x_nobcst_mode,
 521   /* Similar to x_mode, but with operands swapped and disabled broadcast
 522      in EVEX.  */
 523   x_swap_mode,
 524   /* 16-byte XMM operand */
 525   xmm_mode,
 526   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 527      memory operand (depending on vector length).  Broadcast isn't
 528      allowed.  */
 529   xmmq_mode,
 530   /* Same as xmmq_mode, but broadcast is allowed.  */
 531   evex_half_bcst_xmmq_mode,
 532   /* XMM register or byte memory operand */
 533   xmm_mb_mode,
 534   /* XMM register or word memory operand */
 535   xmm_mw_mode,
 536   /* XMM register or double word memory operand */
 537   xmm_md_mode,
 538   /* XMM register or quad word memory operand */
 539   xmm_mq_mode,
 540   /* XMM register or double/quad word memory operand, depending on
 541      VEX.W.  */
 542   xmm_mdq_mode,
 543   /* 16-byte XMM, word, double word or quad word operand.  */
 544   xmmdw_mode,
 545   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 546   xmmqd_mode,
 547   /* 32-byte YMM operand */
 548   ymm_mode,
 549   /* quad word, ymmword or zmmword memory operand.  */
 550   ymmq_mode,
 551   /* 32-byte YMM or 16-byte word operand */
 552   ymmxmm_mode,
 553   /* d_mode in 32bit, q_mode in 64bit mode.  */
 554   m_mode,
 555   /* pair of v_mode operands */
 556   a_mode,
 557   cond_jump_mode,
 558   loop_jcxz_mode,
 559   movsxd_mode,
 560   v_bnd_mode,
 561   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 562   v_bndmk_mode,
 563   /* operand size depends on REX prefixes.  */
 564   dq_mode,
 565   /* registers like dq_mode, memory like w_mode, displacements like
 566      v_mode without considering Intel64 ISA.  */
 567   dqw_mode,
 568   /* bounds operand */
 569   bnd_mode,
 570   /* bounds operand with operand swapped */
 571   bnd_swap_mode,
 572   /* 4- or 6-byte pointer operand */
 573   f_mode,
 574   const_1_mode,
 575   /* v_mode for indirect branch opcodes.  */
 576   indir_v_mode,
 577   /* v_mode for stack-related opcodes.  */
 578   stack_v_mode,
 579   /* non-quad operand size depends on prefixes */
 580   z_mode,
 581   /* 16-byte operand */
 582   o_mode,
 583   /* registers like dq_mode, memory like b_mode.  */
 584   dqb_mode,
 585   /* registers like d_mode, memory like b_mode.  */
 586   db_mode,
 587   /* registers like d_mode, memory like w_mode.  */
 588   dw_mode,
 589   /* registers like dq_mode, memory like d_mode.  */
 590   dqd_mode,
 591   /* normal vex mode */
 592   vex_mode,
 593   /* 128bit vex mode */
 594   vex128_mode,
 595   /* 256bit vex mode */
 596   vex256_mode,
 597
 598   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 599   vex_vsib_d_w_dq_mode,
 600   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 601   vex_vsib_d_w_d_mode,
 602   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 603   vex_vsib_q_w_dq_mode,
 604   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 605   vex_vsib_q_w_d_mode,
 606
 607   /* scalar, ignore vector length.  */
 608   scalar_mode,
 609   /* like b_mode, ignore vector length.  */
 610   b_scalar_mode,
 611   /* like w_mode, ignore vector length.  */
 612   w_scalar_mode,
 613   /* like d_mode, ignore vector length.  */
 614   d_scalar_mode,
 615   /* like d_swap_mode, ignore vector length.  */
 616   d_scalar_swap_mode,
 617   /* like q_mode, ignore vector length.  */
 618   q_scalar_mode,
 619   /* like q_swap_mode, ignore vector length.  */
 620   q_scalar_swap_mode,
 621   /* like vex_mode, ignore vector length.  */
 622   vex_scalar_mode,
 623   /* Operand size depends on the VEX.W bit, ignore vector length.  */
 624   vex_scalar_w_dq_mode,
 625
 626   /* Static rounding.  */
 627   evex_rounding_mode,
 628   /* Static rounding, 64-bit mode only.  */
 629   evex_rounding_64_mode,
 630   /* Supress all exceptions.  */
 631   evex_sae_mode,
 632
 633   /* Mask register operand.  */
 634   mask_mode,
 635   /* Mask register operand.  */
 636   mask_bd_mode,
 637
 638   es_reg,
 639   cs_reg,
 640   ss_reg,
 641   ds_reg,
 642   fs_reg,
 643   gs_reg,
 644
 645   eAX_reg,
 646   eCX_reg,
 647   eDX_reg,
 648   eBX_reg,
 649   eSP_reg,
 650   eBP_reg,
 651   eSI_reg,
 652   eDI_reg,
 653
 654   al_reg,
 655   cl_reg,
 656   dl_reg,
 657   bl_reg,
 658   ah_reg,
 659   ch_reg,
 660   dh_reg,
 661   bh_reg,
 662
 663   ax_reg,
 664   cx_reg,
 665   dx_reg,
 666   bx_reg,
 667   sp_reg,
 668   bp_reg,
 669   si_reg,
 670   di_reg,
 671
 672   rAX_reg,
 673   rCX_reg,
 674   rDX_reg,
 675   rBX_reg,
 676   rSP_reg,
 677   rBP_reg,
 678   rSI_reg,
 679   rDI_reg,
 680
 681   z_mode_ax_reg,
 682   indir_dx_reg
 683 };
 684
 685 enum
 686 {
 687   FLOATCODE = 1,
 688   USE_REG_TABLE,
 689   USE_MOD_TABLE,
 690   USE_RM_TABLE,
 691   USE_PREFIX_TABLE,
 692   USE_X86_64_TABLE,
 693   USE_3BYTE_TABLE,
 694   USE_XOP_8F_TABLE,
 695   USE_VEX_C4_TABLE,
 696   USE_VEX_C5_TABLE,
 697   USE_VEX_LEN_TABLE,
 698   USE_VEX_W_TABLE,
 699   USE_EVEX_TABLE,
 700   USE_EVEX_LEN_TABLE
 701 };
 702
 703 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 704
 705 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 706 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 707 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 708 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 709 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 710 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 711 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 712 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 713 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 714 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 715 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 716 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 717 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 718 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 719 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 720 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 721
 722 enum
 723 {
 724   REG_80 = 0,
 725   REG_81,
 726   REG_83,
 727   REG_8F,
 728   REG_C0,
 729   REG_C1,
 730   REG_C6,
 731   REG_C7,
 732   REG_D0,
 733   REG_D1,
 734   REG_D2,
 735   REG_D3,
 736   REG_F6,
 737   REG_F7,
 738   REG_FE,
 739   REG_FF,
 740   REG_0F00,
 741   REG_0F01,
 742   REG_0F0D,
 743   REG_0F18,
 744   REG_0F1C_P_0_MOD_0,
 745   REG_0F1E_P_1_MOD_3,
 746   REG_0F71,
 747   REG_0F72,
 748   REG_0F73,
 749   REG_0FA6,
 750   REG_0FA7,
 751   REG_0FAE,
 752   REG_0FBA,
 753   REG_0FC7,
 754   REG_VEX_0F71,
 755   REG_VEX_0F72,
 756   REG_VEX_0F73,
 757   REG_VEX_0FAE,
 758   REG_VEX_0F38F3,
 759   REG_XOP_LWPCB,
 760   REG_XOP_LWP,
 761   REG_XOP_TBM_01,
 762   REG_XOP_TBM_02,
 763
 764   REG_EVEX_0F71,
 765   REG_EVEX_0F72,
 766   REG_EVEX_0F73,
 767   REG_EVEX_0F38C6,
 768   REG_EVEX_0F38C7
 769 };
 770
 771 enum
 772 {
 773   MOD_8D = 0,
 774   MOD_C6_REG_7,
 775   MOD_C7_REG_7,
 776   MOD_FF_REG_3,
 777   MOD_FF_REG_5,
 778   MOD_0F01_REG_0,
 779   MOD_0F01_REG_1,
 780   MOD_0F01_REG_2,
 781   MOD_0F01_REG_3,
 782   MOD_0F01_REG_5,
 783   MOD_0F01_REG_7,
 784   MOD_0F12_PREFIX_0,
 785   MOD_0F13,
 786   MOD_0F16_PREFIX_0,
 787   MOD_0F17,
 788   MOD_0F18_REG_0,
 789   MOD_0F18_REG_1,
 790   MOD_0F18_REG_2,
 791   MOD_0F18_REG_3,
 792   MOD_0F18_REG_4,
 793   MOD_0F18_REG_5,
 794   MOD_0F18_REG_6,
 795   MOD_0F18_REG_7,
 796   MOD_0F1A_PREFIX_0,
 797   MOD_0F1B_PREFIX_0,
 798   MOD_0F1B_PREFIX_1,
 799   MOD_0F1C_PREFIX_0,
 800   MOD_0F1E_PREFIX_1,
 801   MOD_0F24,
 802   MOD_0F26,
 803   MOD_0F2B_PREFIX_0,
 804   MOD_0F2B_PREFIX_1,
 805   MOD_0F2B_PREFIX_2,
 806   MOD_0F2B_PREFIX_3,
 807   MOD_0F51,
 808   MOD_0F71_REG_2,
 809   MOD_0F71_REG_4,
 810   MOD_0F71_REG_6,
 811   MOD_0F72_REG_2,
 812   MOD_0F72_REG_4,
 813   MOD_0F72_REG_6,
 814   MOD_0F73_REG_2,
 815   MOD_0F73_REG_3,
 816   MOD_0F73_REG_6,
 817   MOD_0F73_REG_7,
 818   MOD_0FAE_REG_0,
 819   MOD_0FAE_REG_1,
 820   MOD_0FAE_REG_2,
 821   MOD_0FAE_REG_3,
 822   MOD_0FAE_REG_4,
 823   MOD_0FAE_REG_5,
 824   MOD_0FAE_REG_6,
 825   MOD_0FAE_REG_7,
 826   MOD_0FB2,
 827   MOD_0FB4,
 828   MOD_0FB5,
 829   MOD_0FC3,
 830   MOD_0FC7_REG_3,
 831   MOD_0FC7_REG_4,
 832   MOD_0FC7_REG_5,
 833   MOD_0FC7_REG_6,
 834   MOD_0FC7_REG_7,
 835   MOD_0FD7,
 836   MOD_0FE7_PREFIX_2,
 837   MOD_0FF0_PREFIX_3,
 838   MOD_0F382A_PREFIX_2,
 839   MOD_0F38F5_PREFIX_2,
 840   MOD_0F38F6_PREFIX_0,
 841   MOD_0F38F8_PREFIX_1,
 842   MOD_0F38F8_PREFIX_2,
 843   MOD_0F38F8_PREFIX_3,
 844   MOD_0F38F9_PREFIX_0,
 845   MOD_62_32BIT,
 846   MOD_C4_32BIT,
 847   MOD_C5_32BIT,
 848   MOD_VEX_0F12_PREFIX_0,
 849   MOD_VEX_0F13,
 850   MOD_VEX_0F16_PREFIX_0,
 851   MOD_VEX_0F17,
 852   MOD_VEX_0F2B,
 853   MOD_VEX_W_0_0F41_P_0_LEN_1,
 854   MOD_VEX_W_1_0F41_P_0_LEN_1,
 855   MOD_VEX_W_0_0F41_P_2_LEN_1,
 856   MOD_VEX_W_1_0F41_P_2_LEN_1,
 857   MOD_VEX_W_0_0F42_P_0_LEN_1,
 858   MOD_VEX_W_1_0F42_P_0_LEN_1,
 859   MOD_VEX_W_0_0F42_P_2_LEN_1,
 860   MOD_VEX_W_1_0F42_P_2_LEN_1,
 861   MOD_VEX_W_0_0F44_P_0_LEN_1,
 862   MOD_VEX_W_1_0F44_P_0_LEN_1,
 863   MOD_VEX_W_0_0F44_P_2_LEN_1,
 864   MOD_VEX_W_1_0F44_P_2_LEN_1,
 865   MOD_VEX_W_0_0F45_P_0_LEN_1,
 866   MOD_VEX_W_1_0F45_P_0_LEN_1,
 867   MOD_VEX_W_0_0F45_P_2_LEN_1,
 868   MOD_VEX_W_1_0F45_P_2_LEN_1,
 869   MOD_VEX_W_0_0F46_P_0_LEN_1,
 870   MOD_VEX_W_1_0F46_P_0_LEN_1,
 871   MOD_VEX_W_0_0F46_P_2_LEN_1,
 872   MOD_VEX_W_1_0F46_P_2_LEN_1,
 873   MOD_VEX_W_0_0F47_P_0_LEN_1,
 874   MOD_VEX_W_1_0F47_P_0_LEN_1,
 875   MOD_VEX_W_0_0F47_P_2_LEN_1,
 876   MOD_VEX_W_1_0F47_P_2_LEN_1,
 877   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 878   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 879   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 880   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 881   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 882   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 883   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 884   MOD_VEX_0F50,
 885   MOD_VEX_0F71_REG_2,
 886   MOD_VEX_0F71_REG_4,
 887   MOD_VEX_0F71_REG_6,
 888   MOD_VEX_0F72_REG_2,
 889   MOD_VEX_0F72_REG_4,
 890   MOD_VEX_0F72_REG_6,
 891   MOD_VEX_0F73_REG_2,
 892   MOD_VEX_0F73_REG_3,
 893   MOD_VEX_0F73_REG_6,
 894   MOD_VEX_0F73_REG_7,
 895   MOD_VEX_W_0_0F91_P_0_LEN_0,
 896   MOD_VEX_W_1_0F91_P_0_LEN_0,
 897   MOD_VEX_W_0_0F91_P_2_LEN_0,
 898   MOD_VEX_W_1_0F91_P_2_LEN_0,
 899   MOD_VEX_W_0_0F92_P_0_LEN_0,
 900   MOD_VEX_W_0_0F92_P_2_LEN_0,
 901   MOD_VEX_0F92_P_3_LEN_0,
 902   MOD_VEX_W_0_0F93_P_0_LEN_0,
 903   MOD_VEX_W_0_0F93_P_2_LEN_0,
 904   MOD_VEX_0F93_P_3_LEN_0,
 905   MOD_VEX_W_0_0F98_P_0_LEN_0,
 906   MOD_VEX_W_1_0F98_P_0_LEN_0,
 907   MOD_VEX_W_0_0F98_P_2_LEN_0,
 908   MOD_VEX_W_1_0F98_P_2_LEN_0,
 909   MOD_VEX_W_0_0F99_P_0_LEN_0,
 910   MOD_VEX_W_1_0F99_P_0_LEN_0,
 911   MOD_VEX_W_0_0F99_P_2_LEN_0,
 912   MOD_VEX_W_1_0F99_P_2_LEN_0,
 913   MOD_VEX_0FAE_REG_2,
 914   MOD_VEX_0FAE_REG_3,
 915   MOD_VEX_0FD7_PREFIX_2,
 916   MOD_VEX_0FE7_PREFIX_2,
 917   MOD_VEX_0FF0_PREFIX_3,
 918   MOD_VEX_0F381A_PREFIX_2,
 919   MOD_VEX_0F382A_PREFIX_2,
 920   MOD_VEX_0F382C_PREFIX_2,
 921   MOD_VEX_0F382D_PREFIX_2,
 922   MOD_VEX_0F382E_PREFIX_2,
 923   MOD_VEX_0F382F_PREFIX_2,
 924   MOD_VEX_0F385A_PREFIX_2,
 925   MOD_VEX_0F388C_PREFIX_2,
 926   MOD_VEX_0F388E_PREFIX_2,
 927   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 931   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 933   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 934   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 935
 936   MOD_EVEX_0F12_PREFIX_0,
 937   MOD_EVEX_0F16_PREFIX_0,
 938   MOD_EVEX_0F38C6_REG_1,
 939   MOD_EVEX_0F38C6_REG_2,
 940   MOD_EVEX_0F38C6_REG_5,
 941   MOD_EVEX_0F38C6_REG_6,
 942   MOD_EVEX_0F38C7_REG_1,
 943   MOD_EVEX_0F38C7_REG_2,
 944   MOD_EVEX_0F38C7_REG_5,
 945   MOD_EVEX_0F38C7_REG_6
 946 };
 947
 948 enum
 949 {
 950   RM_C6_REG_7 = 0,
 951   RM_C7_REG_7,
 952   RM_0F01_REG_0,
 953   RM_0F01_REG_1,
 954   RM_0F01_REG_2,
 955   RM_0F01_REG_3,
 956   RM_0F01_REG_5_MOD_3,
 957   RM_0F01_REG_7_MOD_3,
 958   RM_0F1E_P_1_MOD_3_REG_7,
 959   RM_0FAE_REG_6_MOD_3_P_0,
 960   RM_0FAE_REG_7_MOD_3,
 961 };
 962
 963 enum
 964 {
 965   PREFIX_90 = 0,
 966   PREFIX_0F01_REG_5_MOD_0,
 967   PREFIX_0F01_REG_5_MOD_3_RM_0,
 968   PREFIX_0F01_REG_5_MOD_3_RM_2,
 969   PREFIX_0F01_REG_7_MOD_3_RM_2,
 970   PREFIX_0F01_REG_7_MOD_3_RM_3,
 971   PREFIX_0F09,
 972   PREFIX_0F10,
 973   PREFIX_0F11,
 974   PREFIX_0F12,
 975   PREFIX_0F16,
 976   PREFIX_0F1A,
 977   PREFIX_0F1B,
 978   PREFIX_0F1C,
 979   PREFIX_0F1E,
 980   PREFIX_0F2A,
 981   PREFIX_0F2B,
 982   PREFIX_0F2C,
 983   PREFIX_0F2D,
 984   PREFIX_0F2E,
 985   PREFIX_0F2F,
 986   PREFIX_0F51,
 987   PREFIX_0F52,
 988   PREFIX_0F53,
 989   PREFIX_0F58,
 990   PREFIX_0F59,
 991   PREFIX_0F5A,
 992   PREFIX_0F5B,
 993   PREFIX_0F5C,
 994   PREFIX_0F5D,
 995   PREFIX_0F5E,
 996   PREFIX_0F5F,
 997   PREFIX_0F60,
 998   PREFIX_0F61,
 999   PREFIX_0F62,
1000   PREFIX_0F6C,
1001   PREFIX_0F6D,
1002   PREFIX_0F6F,
1003   PREFIX_0F70,
1004   PREFIX_0F73_REG_3,
1005   PREFIX_0F73_REG_7,
1006   PREFIX_0F78,
1007   PREFIX_0F79,
1008   PREFIX_0F7C,
1009   PREFIX_0F7D,
1010   PREFIX_0F7E,
1011   PREFIX_0F7F,
1012   PREFIX_0FAE_REG_0_MOD_3,
1013   PREFIX_0FAE_REG_1_MOD_3,
1014   PREFIX_0FAE_REG_2_MOD_3,
1015   PREFIX_0FAE_REG_3_MOD_3,
1016   PREFIX_0FAE_REG_4_MOD_0,
1017   PREFIX_0FAE_REG_4_MOD_3,
1018   PREFIX_0FAE_REG_5_MOD_0,
1019   PREFIX_0FAE_REG_5_MOD_3,
1020   PREFIX_0FAE_REG_6_MOD_0,
1021   PREFIX_0FAE_REG_6_MOD_3,
1022   PREFIX_0FAE_REG_7_MOD_0,
1023   PREFIX_0FB8,
1024   PREFIX_0FBC,
1025   PREFIX_0FBD,
1026   PREFIX_0FC2,
1027   PREFIX_0FC3_MOD_0,
1028   PREFIX_0FC7_REG_6_MOD_0,
1029   PREFIX_0FC7_REG_6_MOD_3,
1030   PREFIX_0FC7_REG_7_MOD_3,
1031   PREFIX_0FD0,
1032   PREFIX_0FD6,
1033   PREFIX_0FE6,
1034   PREFIX_0FE7,
1035   PREFIX_0FF0,
1036   PREFIX_0FF7,
1037   PREFIX_0F3810,
1038   PREFIX_0F3814,
1039   PREFIX_0F3815,
1040   PREFIX_0F3817,
1041   PREFIX_0F3820,
1042   PREFIX_0F3821,
1043   PREFIX_0F3822,
1044   PREFIX_0F3823,
1045   PREFIX_0F3824,
1046   PREFIX_0F3825,
1047   PREFIX_0F3828,
1048   PREFIX_0F3829,
1049   PREFIX_0F382A,
1050   PREFIX_0F382B,
1051   PREFIX_0F3830,
1052   PREFIX_0F3831,
1053   PREFIX_0F3832,
1054   PREFIX_0F3833,
1055   PREFIX_0F3834,
1056   PREFIX_0F3835,
1057   PREFIX_0F3837,
1058   PREFIX_0F3838,
1059   PREFIX_0F3839,
1060   PREFIX_0F383A,
1061   PREFIX_0F383B,
1062   PREFIX_0F383C,
1063   PREFIX_0F383D,
1064   PREFIX_0F383E,
1065   PREFIX_0F383F,
1066   PREFIX_0F3840,
1067   PREFIX_0F3841,
1068   PREFIX_0F3880,
1069   PREFIX_0F3881,
1070   PREFIX_0F3882,
1071   PREFIX_0F38C8,
1072   PREFIX_0F38C9,
1073   PREFIX_0F38CA,
1074   PREFIX_0F38CB,
1075   PREFIX_0F38CC,
1076   PREFIX_0F38CD,
1077   PREFIX_0F38CF,
1078   PREFIX_0F38DB,
1079   PREFIX_0F38DC,
1080   PREFIX_0F38DD,
1081   PREFIX_0F38DE,
1082   PREFIX_0F38DF,
1083   PREFIX_0F38F0,
1084   PREFIX_0F38F1,
1085   PREFIX_0F38F5,
1086   PREFIX_0F38F6,
1087   PREFIX_0F38F8,
1088   PREFIX_0F38F9,
1089   PREFIX_0F3A08,
1090   PREFIX_0F3A09,
1091   PREFIX_0F3A0A,
1092   PREFIX_0F3A0B,
1093   PREFIX_0F3A0C,
1094   PREFIX_0F3A0D,
1095   PREFIX_0F3A0E,
1096   PREFIX_0F3A14,
1097   PREFIX_0F3A15,
1098   PREFIX_0F3A16,
1099   PREFIX_0F3A17,
1100   PREFIX_0F3A20,
1101   PREFIX_0F3A21,
1102   PREFIX_0F3A22,
1103   PREFIX_0F3A40,
1104   PREFIX_0F3A41,
1105   PREFIX_0F3A42,
1106   PREFIX_0F3A44,
1107   PREFIX_0F3A60,
1108   PREFIX_0F3A61,
1109   PREFIX_0F3A62,
1110   PREFIX_0F3A63,
1111   PREFIX_0F3ACC,
1112   PREFIX_0F3ACE,
1113   PREFIX_0F3ACF,
1114   PREFIX_0F3ADF,
1115   PREFIX_VEX_0F10,
1116   PREFIX_VEX_0F11,
1117   PREFIX_VEX_0F12,
1118   PREFIX_VEX_0F16,
1119   PREFIX_VEX_0F2A,
1120   PREFIX_VEX_0F2C,
1121   PREFIX_VEX_0F2D,
1122   PREFIX_VEX_0F2E,
1123   PREFIX_VEX_0F2F,
1124   PREFIX_VEX_0F41,
1125   PREFIX_VEX_0F42,
1126   PREFIX_VEX_0F44,
1127   PREFIX_VEX_0F45,
1128   PREFIX_VEX_0F46,
1129   PREFIX_VEX_0F47,
1130   PREFIX_VEX_0F4A,
1131   PREFIX_VEX_0F4B,
1132   PREFIX_VEX_0F51,
1133   PREFIX_VEX_0F52,
1134   PREFIX_VEX_0F53,
1135   PREFIX_VEX_0F58,
1136   PREFIX_VEX_0F59,
1137   PREFIX_VEX_0F5A,
1138   PREFIX_VEX_0F5B,
1139   PREFIX_VEX_0F5C,
1140   PREFIX_VEX_0F5D,
1141   PREFIX_VEX_0F5E,
1142   PREFIX_VEX_0F5F,
1143   PREFIX_VEX_0F60,
1144   PREFIX_VEX_0F61,
1145   PREFIX_VEX_0F62,
1146   PREFIX_VEX_0F63,
1147   PREFIX_VEX_0F64,
1148   PREFIX_VEX_0F65,
1149   PREFIX_VEX_0F66,
1150   PREFIX_VEX_0F67,
1151   PREFIX_VEX_0F68,
1152   PREFIX_VEX_0F69,
1153   PREFIX_VEX_0F6A,
1154   PREFIX_VEX_0F6B,
1155   PREFIX_VEX_0F6C,
1156   PREFIX_VEX_0F6D,
1157   PREFIX_VEX_0F6E,
1158   PREFIX_VEX_0F6F,
1159   PREFIX_VEX_0F70,
1160   PREFIX_VEX_0F71_REG_2,
1161   PREFIX_VEX_0F71_REG_4,
1162   PREFIX_VEX_0F71_REG_6,
1163   PREFIX_VEX_0F72_REG_2,
1164   PREFIX_VEX_0F72_REG_4,
1165   PREFIX_VEX_0F72_REG_6,
1166   PREFIX_VEX_0F73_REG_2,
1167   PREFIX_VEX_0F73_REG_3,
1168   PREFIX_VEX_0F73_REG_6,
1169   PREFIX_VEX_0F73_REG_7,
1170   PREFIX_VEX_0F74,
1171   PREFIX_VEX_0F75,
1172   PREFIX_VEX_0F76,
1173   PREFIX_VEX_0F77,
1174   PREFIX_VEX_0F7C,
1175   PREFIX_VEX_0F7D,
1176   PREFIX_VEX_0F7E,
1177   PREFIX_VEX_0F7F,
1178   PREFIX_VEX_0F90,
1179   PREFIX_VEX_0F91,
1180   PREFIX_VEX_0F92,
1181   PREFIX_VEX_0F93,
1182   PREFIX_VEX_0F98,
1183   PREFIX_VEX_0F99,
1184   PREFIX_VEX_0FC2,
1185   PREFIX_VEX_0FC4,
1186   PREFIX_VEX_0FC5,
1187   PREFIX_VEX_0FD0,
1188   PREFIX_VEX_0FD1,
1189   PREFIX_VEX_0FD2,
1190   PREFIX_VEX_0FD3,
1191   PREFIX_VEX_0FD4,
1192   PREFIX_VEX_0FD5,
1193   PREFIX_VEX_0FD6,
1194   PREFIX_VEX_0FD7,
1195   PREFIX_VEX_0FD8,
1196   PREFIX_VEX_0FD9,
1197   PREFIX_VEX_0FDA,
1198   PREFIX_VEX_0FDB,
1199   PREFIX_VEX_0FDC,
1200   PREFIX_VEX_0FDD,
1201   PREFIX_VEX_0FDE,
1202   PREFIX_VEX_0FDF,
1203   PREFIX_VEX_0FE0,
1204   PREFIX_VEX_0FE1,
1205   PREFIX_VEX_0FE2,
1206   PREFIX_VEX_0FE3,
1207   PREFIX_VEX_0FE4,
1208   PREFIX_VEX_0FE5,
1209   PREFIX_VEX_0FE6,
1210   PREFIX_VEX_0FE7,
1211   PREFIX_VEX_0FE8,
1212   PREFIX_VEX_0FE9,
1213   PREFIX_VEX_0FEA,
1214   PREFIX_VEX_0FEB,
1215   PREFIX_VEX_0FEC,
1216   PREFIX_VEX_0FED,
1217   PREFIX_VEX_0FEE,
1218   PREFIX_VEX_0FEF,
1219   PREFIX_VEX_0FF0,
1220   PREFIX_VEX_0FF1,
1221   PREFIX_VEX_0FF2,
1222   PREFIX_VEX_0FF3,
1223   PREFIX_VEX_0FF4,
1224   PREFIX_VEX_0FF5,
1225   PREFIX_VEX_0FF6,
1226   PREFIX_VEX_0FF7,
1227   PREFIX_VEX_0FF8,
1228   PREFIX_VEX_0FF9,
1229   PREFIX_VEX_0FFA,
1230   PREFIX_VEX_0FFB,
1231   PREFIX_VEX_0FFC,
1232   PREFIX_VEX_0FFD,
1233   PREFIX_VEX_0FFE,
1234   PREFIX_VEX_0F3800,
1235   PREFIX_VEX_0F3801,
1236   PREFIX_VEX_0F3802,
1237   PREFIX_VEX_0F3803,
1238   PREFIX_VEX_0F3804,
1239   PREFIX_VEX_0F3805,
1240   PREFIX_VEX_0F3806,
1241   PREFIX_VEX_0F3807,
1242   PREFIX_VEX_0F3808,
1243   PREFIX_VEX_0F3809,
1244   PREFIX_VEX_0F380A,
1245   PREFIX_VEX_0F380B,
1246   PREFIX_VEX_0F380C,
1247   PREFIX_VEX_0F380D,
1248   PREFIX_VEX_0F380E,
1249   PREFIX_VEX_0F380F,
1250   PREFIX_VEX_0F3813,
1251   PREFIX_VEX_0F3816,
1252   PREFIX_VEX_0F3817,
1253   PREFIX_VEX_0F3818,
1254   PREFIX_VEX_0F3819,
1255   PREFIX_VEX_0F381A,
1256   PREFIX_VEX_0F381C,
1257   PREFIX_VEX_0F381D,
1258   PREFIX_VEX_0F381E,
1259   PREFIX_VEX_0F3820,
1260   PREFIX_VEX_0F3821,
1261   PREFIX_VEX_0F3822,
1262   PREFIX_VEX_0F3823,
1263   PREFIX_VEX_0F3824,
1264   PREFIX_VEX_0F3825,
1265   PREFIX_VEX_0F3828,
1266   PREFIX_VEX_0F3829,
1267   PREFIX_VEX_0F382A,
1268   PREFIX_VEX_0F382B,
1269   PREFIX_VEX_0F382C,
1270   PREFIX_VEX_0F382D,
1271   PREFIX_VEX_0F382E,
1272   PREFIX_VEX_0F382F,
1273   PREFIX_VEX_0F3830,
1274   PREFIX_VEX_0F3831,
1275   PREFIX_VEX_0F3832,
1276   PREFIX_VEX_0F3833,
1277   PREFIX_VEX_0F3834,
1278   PREFIX_VEX_0F3835,
1279   PREFIX_VEX_0F3836,
1280   PREFIX_VEX_0F3837,
1281   PREFIX_VEX_0F3838,
1282   PREFIX_VEX_0F3839,
1283   PREFIX_VEX_0F383A,
1284   PREFIX_VEX_0F383B,
1285   PREFIX_VEX_0F383C,
1286   PREFIX_VEX_0F383D,
1287   PREFIX_VEX_0F383E,
1288   PREFIX_VEX_0F383F,
1289   PREFIX_VEX_0F3840,
1290   PREFIX_VEX_0F3841,
1291   PREFIX_VEX_0F3845,
1292   PREFIX_VEX_0F3846,
1293   PREFIX_VEX_0F3847,
1294   PREFIX_VEX_0F3858,
1295   PREFIX_VEX_0F3859,
1296   PREFIX_VEX_0F385A,
1297   PREFIX_VEX_0F3878,
1298   PREFIX_VEX_0F3879,
1299   PREFIX_VEX_0F388C,
1300   PREFIX_VEX_0F388E,
1301   PREFIX_VEX_0F3890,
1302   PREFIX_VEX_0F3891,
1303   PREFIX_VEX_0F3892,
1304   PREFIX_VEX_0F3893,
1305   PREFIX_VEX_0F3896,
1306   PREFIX_VEX_0F3897,
1307   PREFIX_VEX_0F3898,
1308   PREFIX_VEX_0F3899,
1309   PREFIX_VEX_0F389A,
1310   PREFIX_VEX_0F389B,
1311   PREFIX_VEX_0F389C,
1312   PREFIX_VEX_0F389D,
1313   PREFIX_VEX_0F389E,
1314   PREFIX_VEX_0F389F,
1315   PREFIX_VEX_0F38A6,
1316   PREFIX_VEX_0F38A7,
1317   PREFIX_VEX_0F38A8,
1318   PREFIX_VEX_0F38A9,
1319   PREFIX_VEX_0F38AA,
1320   PREFIX_VEX_0F38AB,
1321   PREFIX_VEX_0F38AC,
1322   PREFIX_VEX_0F38AD,
1323   PREFIX_VEX_0F38AE,
1324   PREFIX_VEX_0F38AF,
1325   PREFIX_VEX_0F38B6,
1326   PREFIX_VEX_0F38B7,
1327   PREFIX_VEX_0F38B8,
1328   PREFIX_VEX_0F38B9,
1329   PREFIX_VEX_0F38BA,
1330   PREFIX_VEX_0F38BB,
1331   PREFIX_VEX_0F38BC,
1332   PREFIX_VEX_0F38BD,
1333   PREFIX_VEX_0F38BE,
1334   PREFIX_VEX_0F38BF,
1335   PREFIX_VEX_0F38CF,
1336   PREFIX_VEX_0F38DB,
1337   PREFIX_VEX_0F38DC,
1338   PREFIX_VEX_0F38DD,
1339   PREFIX_VEX_0F38DE,
1340   PREFIX_VEX_0F38DF,
1341   PREFIX_VEX_0F38F2,
1342   PREFIX_VEX_0F38F3_REG_1,
1343   PREFIX_VEX_0F38F3_REG_2,
1344   PREFIX_VEX_0F38F3_REG_3,
1345   PREFIX_VEX_0F38F5,
1346   PREFIX_VEX_0F38F6,
1347   PREFIX_VEX_0F38F7,
1348   PREFIX_VEX_0F3A00,
1349   PREFIX_VEX_0F3A01,
1350   PREFIX_VEX_0F3A02,
1351   PREFIX_VEX_0F3A04,
1352   PREFIX_VEX_0F3A05,
1353   PREFIX_VEX_0F3A06,
1354   PREFIX_VEX_0F3A08,
1355   PREFIX_VEX_0F3A09,
1356   PREFIX_VEX_0F3A0A,
1357   PREFIX_VEX_0F3A0B,
1358   PREFIX_VEX_0F3A0C,
1359   PREFIX_VEX_0F3A0D,
1360   PREFIX_VEX_0F3A0E,
1361   PREFIX_VEX_0F3A0F,
1362   PREFIX_VEX_0F3A14,
1363   PREFIX_VEX_0F3A15,
1364   PREFIX_VEX_0F3A16,
1365   PREFIX_VEX_0F3A17,
1366   PREFIX_VEX_0F3A18,
1367   PREFIX_VEX_0F3A19,
1368   PREFIX_VEX_0F3A1D,
1369   PREFIX_VEX_0F3A20,
1370   PREFIX_VEX_0F3A21,
1371   PREFIX_VEX_0F3A22,
1372   PREFIX_VEX_0F3A30,
1373   PREFIX_VEX_0F3A31,
1374   PREFIX_VEX_0F3A32,
1375   PREFIX_VEX_0F3A33,
1376   PREFIX_VEX_0F3A38,
1377   PREFIX_VEX_0F3A39,
1378   PREFIX_VEX_0F3A40,
1379   PREFIX_VEX_0F3A41,
1380   PREFIX_VEX_0F3A42,
1381   PREFIX_VEX_0F3A44,
1382   PREFIX_VEX_0F3A46,
1383   PREFIX_VEX_0F3A48,
1384   PREFIX_VEX_0F3A49,
1385   PREFIX_VEX_0F3A4A,
1386   PREFIX_VEX_0F3A4B,
1387   PREFIX_VEX_0F3A4C,
1388   PREFIX_VEX_0F3A5C,
1389   PREFIX_VEX_0F3A5D,
1390   PREFIX_VEX_0F3A5E,
1391   PREFIX_VEX_0F3A5F,
1392   PREFIX_VEX_0F3A60,
1393   PREFIX_VEX_0F3A61,
1394   PREFIX_VEX_0F3A62,
1395   PREFIX_VEX_0F3A63,
1396   PREFIX_VEX_0F3A68,
1397   PREFIX_VEX_0F3A69,
1398   PREFIX_VEX_0F3A6A,
1399   PREFIX_VEX_0F3A6B,
1400   PREFIX_VEX_0F3A6C,
1401   PREFIX_VEX_0F3A6D,
1402   PREFIX_VEX_0F3A6E,
1403   PREFIX_VEX_0F3A6F,
1404   PREFIX_VEX_0F3A78,
1405   PREFIX_VEX_0F3A79,
1406   PREFIX_VEX_0F3A7A,
1407   PREFIX_VEX_0F3A7B,
1408   PREFIX_VEX_0F3A7C,
1409   PREFIX_VEX_0F3A7D,
1410   PREFIX_VEX_0F3A7E,
1411   PREFIX_VEX_0F3A7F,
1412   PREFIX_VEX_0F3ACE,
1413   PREFIX_VEX_0F3ACF,
1414   PREFIX_VEX_0F3ADF,
1415   PREFIX_VEX_0F3AF0,
1416
1417   PREFIX_EVEX_0F10,
1418   PREFIX_EVEX_0F11,
1419   PREFIX_EVEX_0F12,
1420   PREFIX_EVEX_0F13,
1421   PREFIX_EVEX_0F14,
1422   PREFIX_EVEX_0F15,
1423   PREFIX_EVEX_0F16,
1424   PREFIX_EVEX_0F17,
1425   PREFIX_EVEX_0F28,
1426   PREFIX_EVEX_0F29,
1427   PREFIX_EVEX_0F2A,
1428   PREFIX_EVEX_0F2B,
1429   PREFIX_EVEX_0F2C,
1430   PREFIX_EVEX_0F2D,
1431   PREFIX_EVEX_0F2E,
1432   PREFIX_EVEX_0F2F,
1433   PREFIX_EVEX_0F51,
1434   PREFIX_EVEX_0F54,
1435   PREFIX_EVEX_0F55,
1436   PREFIX_EVEX_0F56,
1437   PREFIX_EVEX_0F57,
1438   PREFIX_EVEX_0F58,
1439   PREFIX_EVEX_0F59,
1440   PREFIX_EVEX_0F5A,
1441   PREFIX_EVEX_0F5B,
1442   PREFIX_EVEX_0F5C,
1443   PREFIX_EVEX_0F5D,
1444   PREFIX_EVEX_0F5E,
1445   PREFIX_EVEX_0F5F,
1446   PREFIX_EVEX_0F60,
1447   PREFIX_EVEX_0F61,
1448   PREFIX_EVEX_0F62,
1449   PREFIX_EVEX_0F63,
1450   PREFIX_EVEX_0F64,
1451   PREFIX_EVEX_0F65,
1452   PREFIX_EVEX_0F66,
1453   PREFIX_EVEX_0F67,
1454   PREFIX_EVEX_0F68,
1455   PREFIX_EVEX_0F69,
1456   PREFIX_EVEX_0F6A,
1457   PREFIX_EVEX_0F6B,
1458   PREFIX_EVEX_0F6C,
1459   PREFIX_EVEX_0F6D,
1460   PREFIX_EVEX_0F6E,
1461   PREFIX_EVEX_0F6F,
1462   PREFIX_EVEX_0F70,
1463   PREFIX_EVEX_0F71_REG_2,
1464   PREFIX_EVEX_0F71_REG_4,
1465   PREFIX_EVEX_0F71_REG_6,
1466   PREFIX_EVEX_0F72_REG_0,
1467   PREFIX_EVEX_0F72_REG_1,
1468   PREFIX_EVEX_0F72_REG_2,
1469   PREFIX_EVEX_0F72_REG_4,
1470   PREFIX_EVEX_0F72_REG_6,
1471   PREFIX_EVEX_0F73_REG_2,
1472   PREFIX_EVEX_0F73_REG_3,
1473   PREFIX_EVEX_0F73_REG_6,
1474   PREFIX_EVEX_0F73_REG_7,
1475   PREFIX_EVEX_0F74,
1476   PREFIX_EVEX_0F75,
1477   PREFIX_EVEX_0F76,
1478   PREFIX_EVEX_0F78,
1479   PREFIX_EVEX_0F79,
1480   PREFIX_EVEX_0F7A,
1481   PREFIX_EVEX_0F7B,
1482   PREFIX_EVEX_0F7E,
1483   PREFIX_EVEX_0F7F,
1484   PREFIX_EVEX_0FC2,
1485   PREFIX_EVEX_0FC4,
1486   PREFIX_EVEX_0FC5,
1487   PREFIX_EVEX_0FC6,
1488   PREFIX_EVEX_0FD1,
1489   PREFIX_EVEX_0FD2,
1490   PREFIX_EVEX_0FD3,
1491   PREFIX_EVEX_0FD4,
1492   PREFIX_EVEX_0FD5,
1493   PREFIX_EVEX_0FD6,
1494   PREFIX_EVEX_0FD8,
1495   PREFIX_EVEX_0FD9,
1496   PREFIX_EVEX_0FDA,
1497   PREFIX_EVEX_0FDB,
1498   PREFIX_EVEX_0FDC,
1499   PREFIX_EVEX_0FDD,
1500   PREFIX_EVEX_0FDE,
1501   PREFIX_EVEX_0FDF,
1502   PREFIX_EVEX_0FE0,
1503   PREFIX_EVEX_0FE1,
1504   PREFIX_EVEX_0FE2,
1505   PREFIX_EVEX_0FE3,
1506   PREFIX_EVEX_0FE4,
1507   PREFIX_EVEX_0FE5,
1508   PREFIX_EVEX_0FE6,
1509   PREFIX_EVEX_0FE7,
1510   PREFIX_EVEX_0FE8,
1511   PREFIX_EVEX_0FE9,
1512   PREFIX_EVEX_0FEA,
1513   PREFIX_EVEX_0FEB,
1514   PREFIX_EVEX_0FEC,
1515   PREFIX_EVEX_0FED,
1516   PREFIX_EVEX_0FEE,
1517   PREFIX_EVEX_0FEF,
1518   PREFIX_EVEX_0FF1,
1519   PREFIX_EVEX_0FF2,
1520   PREFIX_EVEX_0FF3,
1521   PREFIX_EVEX_0FF4,
1522   PREFIX_EVEX_0FF5,
1523   PREFIX_EVEX_0FF6,
1524   PREFIX_EVEX_0FF8,
1525   PREFIX_EVEX_0FF9,
1526   PREFIX_EVEX_0FFA,
1527   PREFIX_EVEX_0FFB,
1528   PREFIX_EVEX_0FFC,
1529   PREFIX_EVEX_0FFD,
1530   PREFIX_EVEX_0FFE,
1531   PREFIX_EVEX_0F3800,
1532   PREFIX_EVEX_0F3804,
1533   PREFIX_EVEX_0F380B,
1534   PREFIX_EVEX_0F380C,
1535   PREFIX_EVEX_0F380D,
1536   PREFIX_EVEX_0F3810,
1537   PREFIX_EVEX_0F3811,
1538   PREFIX_EVEX_0F3812,
1539   PREFIX_EVEX_0F3813,
1540   PREFIX_EVEX_0F3814,
1541   PREFIX_EVEX_0F3815,
1542   PREFIX_EVEX_0F3816,
1543   PREFIX_EVEX_0F3818,
1544   PREFIX_EVEX_0F3819,
1545   PREFIX_EVEX_0F381A,
1546   PREFIX_EVEX_0F381B,
1547   PREFIX_EVEX_0F381C,
1548   PREFIX_EVEX_0F381D,
1549   PREFIX_EVEX_0F381E,
1550   PREFIX_EVEX_0F381F,
1551   PREFIX_EVEX_0F3820,
1552   PREFIX_EVEX_0F3821,
1553   PREFIX_EVEX_0F3822,
1554   PREFIX_EVEX_0F3823,
1555   PREFIX_EVEX_0F3824,
1556   PREFIX_EVEX_0F3825,
1557   PREFIX_EVEX_0F3826,
1558   PREFIX_EVEX_0F3827,
1559   PREFIX_EVEX_0F3828,
1560   PREFIX_EVEX_0F3829,
1561   PREFIX_EVEX_0F382A,
1562   PREFIX_EVEX_0F382B,
1563   PREFIX_EVEX_0F382C,
1564   PREFIX_EVEX_0F382D,
1565   PREFIX_EVEX_0F3830,
1566   PREFIX_EVEX_0F3831,
1567   PREFIX_EVEX_0F3832,
1568   PREFIX_EVEX_0F3833,
1569   PREFIX_EVEX_0F3834,
1570   PREFIX_EVEX_0F3835,
1571   PREFIX_EVEX_0F3836,
1572   PREFIX_EVEX_0F3837,
1573   PREFIX_EVEX_0F3838,
1574   PREFIX_EVEX_0F3839,
1575   PREFIX_EVEX_0F383A,
1576   PREFIX_EVEX_0F383B,
1577   PREFIX_EVEX_0F383C,
1578   PREFIX_EVEX_0F383D,
1579   PREFIX_EVEX_0F383E,
1580   PREFIX_EVEX_0F383F,
1581   PREFIX_EVEX_0F3840,
1582   PREFIX_EVEX_0F3842,
1583   PREFIX_EVEX_0F3843,
1584   PREFIX_EVEX_0F3844,
1585   PREFIX_EVEX_0F3845,
1586   PREFIX_EVEX_0F3846,
1587   PREFIX_EVEX_0F3847,
1588   PREFIX_EVEX_0F384C,
1589   PREFIX_EVEX_0F384D,
1590   PREFIX_EVEX_0F384E,
1591   PREFIX_EVEX_0F384F,
1592   PREFIX_EVEX_0F3850,
1593   PREFIX_EVEX_0F3851,
1594   PREFIX_EVEX_0F3852,
1595   PREFIX_EVEX_0F3853,
1596   PREFIX_EVEX_0F3854,
1597   PREFIX_EVEX_0F3855,
1598   PREFIX_EVEX_0F3858,
1599   PREFIX_EVEX_0F3859,
1600   PREFIX_EVEX_0F385A,
1601   PREFIX_EVEX_0F385B,
1602   PREFIX_EVEX_0F3862,
1603   PREFIX_EVEX_0F3863,
1604   PREFIX_EVEX_0F3864,
1605   PREFIX_EVEX_0F3865,
1606   PREFIX_EVEX_0F3866,
1607   PREFIX_EVEX_0F3868,
1608   PREFIX_EVEX_0F3870,
1609   PREFIX_EVEX_0F3871,
1610   PREFIX_EVEX_0F3872,
1611   PREFIX_EVEX_0F3873,
1612   PREFIX_EVEX_0F3875,
1613   PREFIX_EVEX_0F3876,
1614   PREFIX_EVEX_0F3877,
1615   PREFIX_EVEX_0F3878,
1616   PREFIX_EVEX_0F3879,
1617   PREFIX_EVEX_0F387A,
1618   PREFIX_EVEX_0F387B,
1619   PREFIX_EVEX_0F387C,
1620   PREFIX_EVEX_0F387D,
1621   PREFIX_EVEX_0F387E,
1622   PREFIX_EVEX_0F387F,
1623   PREFIX_EVEX_0F3883,
1624   PREFIX_EVEX_0F3888,
1625   PREFIX_EVEX_0F3889,
1626   PREFIX_EVEX_0F388A,
1627   PREFIX_EVEX_0F388B,
1628   PREFIX_EVEX_0F388D,
1629   PREFIX_EVEX_0F388F,
1630   PREFIX_EVEX_0F3890,
1631   PREFIX_EVEX_0F3891,
1632   PREFIX_EVEX_0F3892,
1633   PREFIX_EVEX_0F3893,
1634   PREFIX_EVEX_0F3896,
1635   PREFIX_EVEX_0F3897,
1636   PREFIX_EVEX_0F3898,
1637   PREFIX_EVEX_0F3899,
1638   PREFIX_EVEX_0F389A,
1639   PREFIX_EVEX_0F389B,
1640   PREFIX_EVEX_0F389C,
1641   PREFIX_EVEX_0F389D,
1642   PREFIX_EVEX_0F389E,
1643   PREFIX_EVEX_0F389F,
1644   PREFIX_EVEX_0F38A0,
1645   PREFIX_EVEX_0F38A1,
1646   PREFIX_EVEX_0F38A2,
1647   PREFIX_EVEX_0F38A3,
1648   PREFIX_EVEX_0F38A6,
1649   PREFIX_EVEX_0F38A7,
1650   PREFIX_EVEX_0F38A8,
1651   PREFIX_EVEX_0F38A9,
1652   PREFIX_EVEX_0F38AA,
1653   PREFIX_EVEX_0F38AB,
1654   PREFIX_EVEX_0F38AC,
1655   PREFIX_EVEX_0F38AD,
1656   PREFIX_EVEX_0F38AE,
1657   PREFIX_EVEX_0F38AF,
1658   PREFIX_EVEX_0F38B4,
1659   PREFIX_EVEX_0F38B5,
1660   PREFIX_EVEX_0F38B6,
1661   PREFIX_EVEX_0F38B7,
1662   PREFIX_EVEX_0F38B8,
1663   PREFIX_EVEX_0F38B9,
1664   PREFIX_EVEX_0F38BA,
1665   PREFIX_EVEX_0F38BB,
1666   PREFIX_EVEX_0F38BC,
1667   PREFIX_EVEX_0F38BD,
1668   PREFIX_EVEX_0F38BE,
1669   PREFIX_EVEX_0F38BF,
1670   PREFIX_EVEX_0F38C4,
1671   PREFIX_EVEX_0F38C6_REG_1,
1672   PREFIX_EVEX_0F38C6_REG_2,
1673   PREFIX_EVEX_0F38C6_REG_5,
1674   PREFIX_EVEX_0F38C6_REG_6,
1675   PREFIX_EVEX_0F38C7_REG_1,
1676   PREFIX_EVEX_0F38C7_REG_2,
1677   PREFIX_EVEX_0F38C7_REG_5,
1678   PREFIX_EVEX_0F38C7_REG_6,
1679   PREFIX_EVEX_0F38C8,
1680   PREFIX_EVEX_0F38CA,
1681   PREFIX_EVEX_0F38CB,
1682   PREFIX_EVEX_0F38CC,
1683   PREFIX_EVEX_0F38CD,
1684   PREFIX_EVEX_0F38CF,
1685   PREFIX_EVEX_0F38DC,
1686   PREFIX_EVEX_0F38DD,
1687   PREFIX_EVEX_0F38DE,
1688   PREFIX_EVEX_0F38DF,
1689
1690   PREFIX_EVEX_0F3A00,
1691   PREFIX_EVEX_0F3A01,
1692   PREFIX_EVEX_0F3A03,
1693   PREFIX_EVEX_0F3A04,
1694   PREFIX_EVEX_0F3A05,
1695   PREFIX_EVEX_0F3A08,
1696   PREFIX_EVEX_0F3A09,
1697   PREFIX_EVEX_0F3A0A,
1698   PREFIX_EVEX_0F3A0B,
1699   PREFIX_EVEX_0F3A0F,
1700   PREFIX_EVEX_0F3A14,
1701   PREFIX_EVEX_0F3A15,
1702   PREFIX_EVEX_0F3A16,
1703   PREFIX_EVEX_0F3A17,
1704   PREFIX_EVEX_0F3A18,
1705   PREFIX_EVEX_0F3A19,
1706   PREFIX_EVEX_0F3A1A,
1707   PREFIX_EVEX_0F3A1B,
1708   PREFIX_EVEX_0F3A1D,
1709   PREFIX_EVEX_0F3A1E,
1710   PREFIX_EVEX_0F3A1F,
1711   PREFIX_EVEX_0F3A20,
1712   PREFIX_EVEX_0F3A21,
1713   PREFIX_EVEX_0F3A22,
1714   PREFIX_EVEX_0F3A23,
1715   PREFIX_EVEX_0F3A25,
1716   PREFIX_EVEX_0F3A26,
1717   PREFIX_EVEX_0F3A27,
1718   PREFIX_EVEX_0F3A38,
1719   PREFIX_EVEX_0F3A39,
1720   PREFIX_EVEX_0F3A3A,
1721   PREFIX_EVEX_0F3A3B,
1722   PREFIX_EVEX_0F3A3E,
1723   PREFIX_EVEX_0F3A3F,
1724   PREFIX_EVEX_0F3A42,
1725   PREFIX_EVEX_0F3A43,
1726   PREFIX_EVEX_0F3A44,
1727   PREFIX_EVEX_0F3A50,
1728   PREFIX_EVEX_0F3A51,
1729   PREFIX_EVEX_0F3A54,
1730   PREFIX_EVEX_0F3A55,
1731   PREFIX_EVEX_0F3A56,
1732   PREFIX_EVEX_0F3A57,
1733   PREFIX_EVEX_0F3A66,
1734   PREFIX_EVEX_0F3A67,
1735   PREFIX_EVEX_0F3A70,
1736   PREFIX_EVEX_0F3A71,
1737   PREFIX_EVEX_0F3A72,
1738   PREFIX_EVEX_0F3A73,
1739   PREFIX_EVEX_0F3ACE,
1740   PREFIX_EVEX_0F3ACF
1741 };
1742
1743 enum
1744 {
1745   X86_64_06 = 0,
1746   X86_64_07,
1747   X86_64_0D,
1748   X86_64_16,
1749   X86_64_17,
1750   X86_64_1E,
1751   X86_64_1F,
1752   X86_64_27,
1753   X86_64_2F,
1754   X86_64_37,
1755   X86_64_3F,
1756   X86_64_60,
1757   X86_64_61,
1758   X86_64_62,
1759   X86_64_63,
1760   X86_64_6D,
1761   X86_64_6F,
1762   X86_64_82,
1763   X86_64_9A,
1764   X86_64_C2,
1765   X86_64_C3,
1766   X86_64_C4,
1767   X86_64_C5,
1768   X86_64_CE,
1769   X86_64_D4,
1770   X86_64_D5,
1771   X86_64_E8,
1772   X86_64_E9,
1773   X86_64_EA,
1774   X86_64_0F01_REG_0,
1775   X86_64_0F01_REG_1,
1776   X86_64_0F01_REG_2,
1777   X86_64_0F01_REG_3
1778 };
1779
1780 enum
1781 {
1782   THREE_BYTE_0F38 = 0,
1783   THREE_BYTE_0F3A
1784 };
1785
1786 enum
1787 {
1788   XOP_08 = 0,
1789   XOP_09,
1790   XOP_0A
1791 };
1792
1793 enum
1794 {
1795   VEX_0F = 0,
1796   VEX_0F38,
1797   VEX_0F3A
1798 };
1799
1800 enum
1801 {
1802   EVEX_0F = 0,
1803   EVEX_0F38,
1804   EVEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   VEX_LEN_0F12_P_0_M_0 = 0,
1810   VEX_LEN_0F12_P_0_M_1,
1811   VEX_LEN_0F12_P_2,
1812   VEX_LEN_0F13_M_0,
1813   VEX_LEN_0F16_P_0_M_0,
1814   VEX_LEN_0F16_P_0_M_1,
1815   VEX_LEN_0F16_P_2,
1816   VEX_LEN_0F17_M_0,
1817   VEX_LEN_0F41_P_0,
1818   VEX_LEN_0F41_P_2,
1819   VEX_LEN_0F42_P_0,
1820   VEX_LEN_0F42_P_2,
1821   VEX_LEN_0F44_P_0,
1822   VEX_LEN_0F44_P_2,
1823   VEX_LEN_0F45_P_0,
1824   VEX_LEN_0F45_P_2,
1825   VEX_LEN_0F46_P_0,
1826   VEX_LEN_0F46_P_2,
1827   VEX_LEN_0F47_P_0,
1828   VEX_LEN_0F47_P_2,
1829   VEX_LEN_0F4A_P_0,
1830   VEX_LEN_0F4A_P_2,
1831   VEX_LEN_0F4B_P_0,
1832   VEX_LEN_0F4B_P_2,
1833   VEX_LEN_0F6E_P_2,
1834   VEX_LEN_0F77_P_0,
1835   VEX_LEN_0F7E_P_1,
1836   VEX_LEN_0F7E_P_2,
1837   VEX_LEN_0F90_P_0,
1838   VEX_LEN_0F90_P_2,
1839   VEX_LEN_0F91_P_0,
1840   VEX_LEN_0F91_P_2,
1841   VEX_LEN_0F92_P_0,
1842   VEX_LEN_0F92_P_2,
1843   VEX_LEN_0F92_P_3,
1844   VEX_LEN_0F93_P_0,
1845   VEX_LEN_0F93_P_2,
1846   VEX_LEN_0F93_P_3,
1847   VEX_LEN_0F98_P_0,
1848   VEX_LEN_0F98_P_2,
1849   VEX_LEN_0F99_P_0,
1850   VEX_LEN_0F99_P_2,
1851   VEX_LEN_0FAE_R_2_M_0,
1852   VEX_LEN_0FAE_R_3_M_0,
1853   VEX_LEN_0FC4_P_2,
1854   VEX_LEN_0FC5_P_2,
1855   VEX_LEN_0FD6_P_2,
1856   VEX_LEN_0FF7_P_2,
1857   VEX_LEN_0F3816_P_2,
1858   VEX_LEN_0F3819_P_2,
1859   VEX_LEN_0F381A_P_2_M_0,
1860   VEX_LEN_0F3836_P_2,
1861   VEX_LEN_0F3841_P_2,
1862   VEX_LEN_0F385A_P_2_M_0,
1863   VEX_LEN_0F38DB_P_2,
1864   VEX_LEN_0F38F2_P_0,
1865   VEX_LEN_0F38F3_R_1_P_0,
1866   VEX_LEN_0F38F3_R_2_P_0,
1867   VEX_LEN_0F38F3_R_3_P_0,
1868   VEX_LEN_0F38F5_P_0,
1869   VEX_LEN_0F38F5_P_1,
1870   VEX_LEN_0F38F5_P_3,
1871   VEX_LEN_0F38F6_P_3,
1872   VEX_LEN_0F38F7_P_0,
1873   VEX_LEN_0F38F7_P_1,
1874   VEX_LEN_0F38F7_P_2,
1875   VEX_LEN_0F38F7_P_3,
1876   VEX_LEN_0F3A00_P_2,
1877   VEX_LEN_0F3A01_P_2,
1878   VEX_LEN_0F3A06_P_2,
1879   VEX_LEN_0F3A14_P_2,
1880   VEX_LEN_0F3A15_P_2,
1881   VEX_LEN_0F3A16_P_2,
1882   VEX_LEN_0F3A17_P_2,
1883   VEX_LEN_0F3A18_P_2,
1884   VEX_LEN_0F3A19_P_2,
1885   VEX_LEN_0F3A20_P_2,
1886   VEX_LEN_0F3A21_P_2,
1887   VEX_LEN_0F3A22_P_2,
1888   VEX_LEN_0F3A30_P_2,
1889   VEX_LEN_0F3A31_P_2,
1890   VEX_LEN_0F3A32_P_2,
1891   VEX_LEN_0F3A33_P_2,
1892   VEX_LEN_0F3A38_P_2,
1893   VEX_LEN_0F3A39_P_2,
1894   VEX_LEN_0F3A41_P_2,
1895   VEX_LEN_0F3A46_P_2,
1896   VEX_LEN_0F3A60_P_2,
1897   VEX_LEN_0F3A61_P_2,
1898   VEX_LEN_0F3A62_P_2,
1899   VEX_LEN_0F3A63_P_2,
1900   VEX_LEN_0F3A6A_P_2,
1901   VEX_LEN_0F3A6B_P_2,
1902   VEX_LEN_0F3A6E_P_2,
1903   VEX_LEN_0F3A6F_P_2,
1904   VEX_LEN_0F3A7A_P_2,
1905   VEX_LEN_0F3A7B_P_2,
1906   VEX_LEN_0F3A7E_P_2,
1907   VEX_LEN_0F3A7F_P_2,
1908   VEX_LEN_0F3ADF_P_2,
1909   VEX_LEN_0F3AF0_P_3,
1910   VEX_LEN_0FXOP_08_CC,
1911   VEX_LEN_0FXOP_08_CD,
1912   VEX_LEN_0FXOP_08_CE,
1913   VEX_LEN_0FXOP_08_CF,
1914   VEX_LEN_0FXOP_08_EC,
1915   VEX_LEN_0FXOP_08_ED,
1916   VEX_LEN_0FXOP_08_EE,
1917   VEX_LEN_0FXOP_08_EF,
1918   VEX_LEN_0FXOP_09_80,
1919   VEX_LEN_0FXOP_09_81
1920 };
1921
1922 enum
1923 {
1924   EVEX_LEN_0F6E_P_2 = 0,
1925   EVEX_LEN_0F7E_P_1,
1926   EVEX_LEN_0F7E_P_2,
1927   EVEX_LEN_0FD6_P_2,
1928   EVEX_LEN_0F3819_P_2_W_0,
1929   EVEX_LEN_0F3819_P_2_W_1,
1930   EVEX_LEN_0F381A_P_2_W_0,
1931   EVEX_LEN_0F381A_P_2_W_1,
1932   EVEX_LEN_0F381B_P_2_W_0,
1933   EVEX_LEN_0F381B_P_2_W_1,
1934   EVEX_LEN_0F385A_P_2_W_0,
1935   EVEX_LEN_0F385A_P_2_W_1,
1936   EVEX_LEN_0F385B_P_2_W_0,
1937   EVEX_LEN_0F385B_P_2_W_1,
1938   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1939   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1940   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1941   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1942   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1943   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1944   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1945   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1946   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1947   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1948   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1949   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1950   EVEX_LEN_0F3A18_P_2_W_0,
1951   EVEX_LEN_0F3A18_P_2_W_1,
1952   EVEX_LEN_0F3A19_P_2_W_0,
1953   EVEX_LEN_0F3A19_P_2_W_1,
1954   EVEX_LEN_0F3A1A_P_2_W_0,
1955   EVEX_LEN_0F3A1A_P_2_W_1,
1956   EVEX_LEN_0F3A1B_P_2_W_0,
1957   EVEX_LEN_0F3A1B_P_2_W_1,
1958   EVEX_LEN_0F3A23_P_2_W_0,
1959   EVEX_LEN_0F3A23_P_2_W_1,
1960   EVEX_LEN_0F3A38_P_2_W_0,
1961   EVEX_LEN_0F3A38_P_2_W_1,
1962   EVEX_LEN_0F3A39_P_2_W_0,
1963   EVEX_LEN_0F3A39_P_2_W_1,
1964   EVEX_LEN_0F3A3A_P_2_W_0,
1965   EVEX_LEN_0F3A3A_P_2_W_1,
1966   EVEX_LEN_0F3A3B_P_2_W_0,
1967   EVEX_LEN_0F3A3B_P_2_W_1,
1968   EVEX_LEN_0F3A43_P_2_W_0,
1969   EVEX_LEN_0F3A43_P_2_W_1
1970 };
1971
1972 enum
1973 {
1974   VEX_W_0F41_P_0_LEN_1 = 0,
1975   VEX_W_0F41_P_2_LEN_1,
1976   VEX_W_0F42_P_0_LEN_1,
1977   VEX_W_0F42_P_2_LEN_1,
1978   VEX_W_0F44_P_0_LEN_0,
1979   VEX_W_0F44_P_2_LEN_0,
1980   VEX_W_0F45_P_0_LEN_1,
1981   VEX_W_0F45_P_2_LEN_1,
1982   VEX_W_0F46_P_0_LEN_1,
1983   VEX_W_0F46_P_2_LEN_1,
1984   VEX_W_0F47_P_0_LEN_1,
1985   VEX_W_0F47_P_2_LEN_1,
1986   VEX_W_0F4A_P_0_LEN_1,
1987   VEX_W_0F4A_P_2_LEN_1,
1988   VEX_W_0F4B_P_0_LEN_1,
1989   VEX_W_0F4B_P_2_LEN_1,
1990   VEX_W_0F90_P_0_LEN_0,
1991   VEX_W_0F90_P_2_LEN_0,
1992   VEX_W_0F91_P_0_LEN_0,
1993   VEX_W_0F91_P_2_LEN_0,
1994   VEX_W_0F92_P_0_LEN_0,
1995   VEX_W_0F92_P_2_LEN_0,
1996   VEX_W_0F93_P_0_LEN_0,
1997   VEX_W_0F93_P_2_LEN_0,
1998   VEX_W_0F98_P_0_LEN_0,
1999   VEX_W_0F98_P_2_LEN_0,
2000   VEX_W_0F99_P_0_LEN_0,
2001   VEX_W_0F99_P_2_LEN_0,
2002   VEX_W_0F380C_P_2,
2003   VEX_W_0F380D_P_2,
2004   VEX_W_0F380E_P_2,
2005   VEX_W_0F380F_P_2,
2006   VEX_W_0F3816_P_2,
2007   VEX_W_0F3818_P_2,
2008   VEX_W_0F3819_P_2,
2009   VEX_W_0F381A_P_2_M_0,
2010   VEX_W_0F382C_P_2_M_0,
2011   VEX_W_0F382D_P_2_M_0,
2012   VEX_W_0F382E_P_2_M_0,
2013   VEX_W_0F382F_P_2_M_0,
2014   VEX_W_0F3836_P_2,
2015   VEX_W_0F3846_P_2,
2016   VEX_W_0F3858_P_2,
2017   VEX_W_0F3859_P_2,
2018   VEX_W_0F385A_P_2_M_0,
2019   VEX_W_0F3878_P_2,
2020   VEX_W_0F3879_P_2,
2021   VEX_W_0F38CF_P_2,
2022   VEX_W_0F3A00_P_2,
2023   VEX_W_0F3A01_P_2,
2024   VEX_W_0F3A02_P_2,
2025   VEX_W_0F3A04_P_2,
2026   VEX_W_0F3A05_P_2,
2027   VEX_W_0F3A06_P_2,
2028   VEX_W_0F3A18_P_2,
2029   VEX_W_0F3A19_P_2,
2030   VEX_W_0F3A30_P_2_LEN_0,
2031   VEX_W_0F3A31_P_2_LEN_0,
2032   VEX_W_0F3A32_P_2_LEN_0,
2033   VEX_W_0F3A33_P_2_LEN_0,
2034   VEX_W_0F3A38_P_2,
2035   VEX_W_0F3A39_P_2,
2036   VEX_W_0F3A46_P_2,
2037   VEX_W_0F3A48_P_2,
2038   VEX_W_0F3A49_P_2,
2039   VEX_W_0F3A4A_P_2,
2040   VEX_W_0F3A4B_P_2,
2041   VEX_W_0F3A4C_P_2,
2042   VEX_W_0F3ACE_P_2,
2043   VEX_W_0F3ACF_P_2,
2044
2045   EVEX_W_0F10_P_0,
2046   EVEX_W_0F10_P_1,
2047   EVEX_W_0F10_P_2,
2048   EVEX_W_0F10_P_3,
2049   EVEX_W_0F11_P_0,
2050   EVEX_W_0F11_P_1,
2051   EVEX_W_0F11_P_2,
2052   EVEX_W_0F11_P_3,
2053   EVEX_W_0F12_P_0_M_0,
2054   EVEX_W_0F12_P_0_M_1,
2055   EVEX_W_0F12_P_1,
2056   EVEX_W_0F12_P_2,
2057   EVEX_W_0F12_P_3,
2058   EVEX_W_0F13_P_0,
2059   EVEX_W_0F13_P_2,
2060   EVEX_W_0F14_P_0,
2061   EVEX_W_0F14_P_2,
2062   EVEX_W_0F15_P_0,
2063   EVEX_W_0F15_P_2,
2064   EVEX_W_0F16_P_0_M_0,
2065   EVEX_W_0F16_P_0_M_1,
2066   EVEX_W_0F16_P_1,
2067   EVEX_W_0F16_P_2,
2068   EVEX_W_0F17_P_0,
2069   EVEX_W_0F17_P_2,
2070   EVEX_W_0F28_P_0,
2071   EVEX_W_0F28_P_2,
2072   EVEX_W_0F29_P_0,
2073   EVEX_W_0F29_P_2,
2074   EVEX_W_0F2A_P_3,
2075   EVEX_W_0F2B_P_0,
2076   EVEX_W_0F2B_P_2,
2077   EVEX_W_0F2E_P_0,
2078   EVEX_W_0F2E_P_2,
2079   EVEX_W_0F2F_P_0,
2080   EVEX_W_0F2F_P_2,
2081   EVEX_W_0F51_P_0,
2082   EVEX_W_0F51_P_1,
2083   EVEX_W_0F51_P_2,
2084   EVEX_W_0F51_P_3,
2085   EVEX_W_0F54_P_0,
2086   EVEX_W_0F54_P_2,
2087   EVEX_W_0F55_P_0,
2088   EVEX_W_0F55_P_2,
2089   EVEX_W_0F56_P_0,
2090   EVEX_W_0F56_P_2,
2091   EVEX_W_0F57_P_0,
2092   EVEX_W_0F57_P_2,
2093   EVEX_W_0F58_P_0,
2094   EVEX_W_0F58_P_1,
2095   EVEX_W_0F58_P_2,
2096   EVEX_W_0F58_P_3,
2097   EVEX_W_0F59_P_0,
2098   EVEX_W_0F59_P_1,
2099   EVEX_W_0F59_P_2,
2100   EVEX_W_0F59_P_3,
2101   EVEX_W_0F5A_P_0,
2102   EVEX_W_0F5A_P_1,
2103   EVEX_W_0F5A_P_2,
2104   EVEX_W_0F5A_P_3,
2105   EVEX_W_0F5B_P_0,
2106   EVEX_W_0F5B_P_1,
2107   EVEX_W_0F5B_P_2,
2108   EVEX_W_0F5C_P_0,
2109   EVEX_W_0F5C_P_1,
2110   EVEX_W_0F5C_P_2,
2111   EVEX_W_0F5C_P_3,
2112   EVEX_W_0F5D_P_0,
2113   EVEX_W_0F5D_P_1,
2114   EVEX_W_0F5D_P_2,
2115   EVEX_W_0F5D_P_3,
2116   EVEX_W_0F5E_P_0,
2117   EVEX_W_0F5E_P_1,
2118   EVEX_W_0F5E_P_2,
2119   EVEX_W_0F5E_P_3,
2120   EVEX_W_0F5F_P_0,
2121   EVEX_W_0F5F_P_1,
2122   EVEX_W_0F5F_P_2,
2123   EVEX_W_0F5F_P_3,
2124   EVEX_W_0F62_P_2,
2125   EVEX_W_0F66_P_2,
2126   EVEX_W_0F6A_P_2,
2127   EVEX_W_0F6B_P_2,
2128   EVEX_W_0F6C_P_2,
2129   EVEX_W_0F6D_P_2,
2130   EVEX_W_0F6F_P_1,
2131   EVEX_W_0F6F_P_2,
2132   EVEX_W_0F6F_P_3,
2133   EVEX_W_0F70_P_2,
2134   EVEX_W_0F72_R_2_P_2,
2135   EVEX_W_0F72_R_6_P_2,
2136   EVEX_W_0F73_R_2_P_2,
2137   EVEX_W_0F73_R_6_P_2,
2138   EVEX_W_0F76_P_2,
2139   EVEX_W_0F78_P_0,
2140   EVEX_W_0F78_P_2,
2141   EVEX_W_0F79_P_0,
2142   EVEX_W_0F79_P_2,
2143   EVEX_W_0F7A_P_1,
2144   EVEX_W_0F7A_P_2,
2145   EVEX_W_0F7A_P_3,
2146   EVEX_W_0F7B_P_2,
2147   EVEX_W_0F7B_P_3,
2148   EVEX_W_0F7E_P_1,
2149   EVEX_W_0F7F_P_1,
2150   EVEX_W_0F7F_P_2,
2151   EVEX_W_0F7F_P_3,
2152   EVEX_W_0FC2_P_0,
2153   EVEX_W_0FC2_P_1,
2154   EVEX_W_0FC2_P_2,
2155   EVEX_W_0FC2_P_3,
2156   EVEX_W_0FC6_P_0,
2157   EVEX_W_0FC6_P_2,
2158   EVEX_W_0FD2_P_2,
2159   EVEX_W_0FD3_P_2,
2160   EVEX_W_0FD4_P_2,
2161   EVEX_W_0FD6_P_2,
2162   EVEX_W_0FE6_P_1,
2163   EVEX_W_0FE6_P_2,
2164   EVEX_W_0FE6_P_3,
2165   EVEX_W_0FE7_P_2,
2166   EVEX_W_0FF2_P_2,
2167   EVEX_W_0FF3_P_2,
2168   EVEX_W_0FF4_P_2,
2169   EVEX_W_0FFA_P_2,
2170   EVEX_W_0FFB_P_2,
2171   EVEX_W_0FFE_P_2,
2172   EVEX_W_0F380C_P_2,
2173   EVEX_W_0F380D_P_2,
2174   EVEX_W_0F3810_P_1,
2175   EVEX_W_0F3810_P_2,
2176   EVEX_W_0F3811_P_1,
2177   EVEX_W_0F3811_P_2,
2178   EVEX_W_0F3812_P_1,
2179   EVEX_W_0F3812_P_2,
2180   EVEX_W_0F3813_P_1,
2181   EVEX_W_0F3813_P_2,
2182   EVEX_W_0F3814_P_1,
2183   EVEX_W_0F3815_P_1,
2184   EVEX_W_0F3818_P_2,
2185   EVEX_W_0F3819_P_2,
2186   EVEX_W_0F381A_P_2,
2187   EVEX_W_0F381B_P_2,
2188   EVEX_W_0F381E_P_2,
2189   EVEX_W_0F381F_P_2,
2190   EVEX_W_0F3820_P_1,
2191   EVEX_W_0F3821_P_1,
2192   EVEX_W_0F3822_P_1,
2193   EVEX_W_0F3823_P_1,
2194   EVEX_W_0F3824_P_1,
2195   EVEX_W_0F3825_P_1,
2196   EVEX_W_0F3825_P_2,
2197   EVEX_W_0F3826_P_1,
2198   EVEX_W_0F3826_P_2,
2199   EVEX_W_0F3828_P_1,
2200   EVEX_W_0F3828_P_2,
2201   EVEX_W_0F3829_P_1,
2202   EVEX_W_0F3829_P_2,
2203   EVEX_W_0F382A_P_1,
2204   EVEX_W_0F382A_P_2,
2205   EVEX_W_0F382B_P_2,
2206   EVEX_W_0F3830_P_1,
2207   EVEX_W_0F3831_P_1,
2208   EVEX_W_0F3832_P_1,
2209   EVEX_W_0F3833_P_1,
2210   EVEX_W_0F3834_P_1,
2211   EVEX_W_0F3835_P_1,
2212   EVEX_W_0F3835_P_2,
2213   EVEX_W_0F3837_P_2,
2214   EVEX_W_0F3838_P_1,
2215   EVEX_W_0F3839_P_1,
2216   EVEX_W_0F383A_P_1,
2217   EVEX_W_0F3840_P_2,
2218   EVEX_W_0F3852_P_1,
2219   EVEX_W_0F3854_P_2,
2220   EVEX_W_0F3855_P_2,
2221   EVEX_W_0F3858_P_2,
2222   EVEX_W_0F3859_P_2,
2223   EVEX_W_0F385A_P_2,
2224   EVEX_W_0F385B_P_2,
2225   EVEX_W_0F3862_P_2,
2226   EVEX_W_0F3863_P_2,
2227   EVEX_W_0F3866_P_2,
2228   EVEX_W_0F3868_P_3,
2229   EVEX_W_0F3870_P_2,
2230   EVEX_W_0F3871_P_2,
2231   EVEX_W_0F3872_P_1,
2232   EVEX_W_0F3872_P_2,
2233   EVEX_W_0F3872_P_3,
2234   EVEX_W_0F3873_P_2,
2235   EVEX_W_0F3875_P_2,
2236   EVEX_W_0F3878_P_2,
2237   EVEX_W_0F3879_P_2,
2238   EVEX_W_0F387A_P_2,
2239   EVEX_W_0F387B_P_2,
2240   EVEX_W_0F387D_P_2,
2241   EVEX_W_0F3883_P_2,
2242   EVEX_W_0F388D_P_2,
2243   EVEX_W_0F3891_P_2,
2244   EVEX_W_0F3893_P_2,
2245   EVEX_W_0F38A1_P_2,
2246   EVEX_W_0F38A3_P_2,
2247   EVEX_W_0F38C7_R_1_P_2,
2248   EVEX_W_0F38C7_R_2_P_2,
2249   EVEX_W_0F38C7_R_5_P_2,
2250   EVEX_W_0F38C7_R_6_P_2,
2251
2252   EVEX_W_0F3A00_P_2,
2253   EVEX_W_0F3A01_P_2,
2254   EVEX_W_0F3A04_P_2,
2255   EVEX_W_0F3A05_P_2,
2256   EVEX_W_0F3A08_P_2,
2257   EVEX_W_0F3A09_P_2,
2258   EVEX_W_0F3A0A_P_2,
2259   EVEX_W_0F3A0B_P_2,
2260   EVEX_W_0F3A18_P_2,
2261   EVEX_W_0F3A19_P_2,
2262   EVEX_W_0F3A1A_P_2,
2263   EVEX_W_0F3A1B_P_2,
2264   EVEX_W_0F3A1D_P_2,
2265   EVEX_W_0F3A21_P_2,
2266   EVEX_W_0F3A23_P_2,
2267   EVEX_W_0F3A38_P_2,
2268   EVEX_W_0F3A39_P_2,
2269   EVEX_W_0F3A3A_P_2,
2270   EVEX_W_0F3A3B_P_2,
2271   EVEX_W_0F3A3E_P_2,
2272   EVEX_W_0F3A3F_P_2,
2273   EVEX_W_0F3A42_P_2,
2274   EVEX_W_0F3A43_P_2,
2275   EVEX_W_0F3A50_P_2,
2276   EVEX_W_0F3A51_P_2,
2277   EVEX_W_0F3A56_P_2,
2278   EVEX_W_0F3A57_P_2,
2279   EVEX_W_0F3A66_P_2,
2280   EVEX_W_0F3A67_P_2,
2281   EVEX_W_0F3A70_P_2,
2282   EVEX_W_0F3A71_P_2,
2283   EVEX_W_0F3A72_P_2,
2284   EVEX_W_0F3A73_P_2,
2285   EVEX_W_0F3ACE_P_2,
2286   EVEX_W_0F3ACF_P_2
2287 };
2288
2289 typedef void (*op_rtn) (int bytemode, int sizeflag);
2290
2291 struct dis386 {
2292   const char *name;
2293   struct
2294     {
2295       op_rtn rtn;
2296       int bytemode;
2297     } op[MAX_OPERANDS];
2298   unsigned int prefix_requirement;
2299 };
2300
2301 /* Upper case letters in the instruction names here are macros.
2302    'A' => print 'b' if no register operands or suffix_always is true
2303    'B' => print 'b' if suffix_always is true
2304    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2305           size prefix
2306    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2307           suffix_always is true
2308    'E' => print 'e' if 32-bit form of jcxz
2309    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2310    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2311    'H' => print ",pt" or ",pn" branch hint
2312    'I' => honor following macro letter even in Intel mode (implemented only
2313           for some of the macro letters)
2314    'J' => print 'l'
2315    'K' => print 'd' or 'q' if rex prefix is present.
2316    'L' => print 'l' if suffix_always is true
2317    'M' => print 'r' if intel_mnemonic is false.
2318    'N' => print 'n' if instruction has no wait "prefix"
2319    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2320    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2321           or suffix_always is true.  print 'q' if rex prefix is present.
2322    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2323           is true
2324    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2325    'S' => print 'w', 'l' or 'q' if suffix_always is true
2326    'T' => print 'q' in 64bit mode if instruction has no operand size
2327           prefix and behave as 'P' otherwise
2328    'U' => print 'q' in 64bit mode if instruction has no operand size
2329           prefix and behave as 'Q' otherwise
2330    'V' => print 'q' in 64bit mode if instruction has no operand size
2331           prefix and behave as 'S' otherwise
2332    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2333    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2334    'Y' unused.
2335    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2336    '!' => change condition from true to false or from false to true.
2337    '%' => add 1 upper case letter to the macro.
2338    '^' => print 'w' or 'l' depending on operand size prefix or
2339           suffix_always is true (lcall/ljmp).
2340    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2341           on operand size prefix.
2342    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2343           has no operand size prefix for AMD64 ISA, behave as 'P'
2344           otherwise
2345
2346    2 upper case letter macros:
2347    "XY" => print 'x' or 'y' if suffix_always is true or no register
2348            operands and no broadcast.
2349    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2350            register operands and no broadcast.
2351    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2352    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2353            or suffix_always is true
2354    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2355    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2356    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2357    "LW" => print 'd', 'q' depending on the VEX.W bit
2358    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2359            an operand size prefix, or suffix_always is true.  print
2360            'q' if rex prefix is present.
2361
2362    Many of the above letters print nothing in Intel mode.  See "putop"
2363    for the details.
2364
2365    Braces '{' and '}', and vertical bars '|', indicate alternative
2366    mnemonic strings for AT&T and Intel.  */
2367
2368 static const struct dis386 dis386[] = {
2369   /* 00 */
2370   { "addB",             { Ebh1, Gb }, 0 },
2371   { "addS",             { Evh1, Gv }, 0 },
2372   { "addB",             { Gb, EbS }, 0 },
2373   { "addS",             { Gv, EvS }, 0 },
2374   { "addB",             { AL, Ib }, 0 },
2375   { "addS",             { eAX, Iv }, 0 },
2376   { X86_64_TABLE (X86_64_06) },
2377   { X86_64_TABLE (X86_64_07) },
2378   /* 08 */
2379   { "orB",              { Ebh1, Gb }, 0 },
2380   { "orS",              { Evh1, Gv }, 0 },
2381   { "orB",              { Gb, EbS }, 0 },
2382   { "orS",              { Gv, EvS }, 0 },
2383   { "orB",              { AL, Ib }, 0 },
2384   { "orS",              { eAX, Iv }, 0 },
2385   { X86_64_TABLE (X86_64_0D) },
2386   { Bad_Opcode },       /* 0x0f extended opcode escape */
2387   /* 10 */
2388   { "adcB",             { Ebh1, Gb }, 0 },
2389   { "adcS",             { Evh1, Gv }, 0 },
2390   { "adcB",             { Gb, EbS }, 0 },
2391   { "adcS",             { Gv, EvS }, 0 },
2392   { "adcB",             { AL, Ib }, 0 },
2393   { "adcS",             { eAX, Iv }, 0 },
2394   { X86_64_TABLE (X86_64_16) },
2395   { X86_64_TABLE (X86_64_17) },
2396   /* 18 */
2397   { "sbbB",             { Ebh1, Gb }, 0 },
2398   { "sbbS",             { Evh1, Gv }, 0 },
2399   { "sbbB",             { Gb, EbS }, 0 },
2400   { "sbbS",             { Gv, EvS }, 0 },
2401   { "sbbB",             { AL, Ib }, 0 },
2402   { "sbbS",             { eAX, Iv }, 0 },
2403   { X86_64_TABLE (X86_64_1E) },
2404   { X86_64_TABLE (X86_64_1F) },
2405   /* 20 */
2406   { "andB",             { Ebh1, Gb }, 0 },
2407   { "andS",             { Evh1, Gv }, 0 },
2408   { "andB",             { Gb, EbS }, 0 },
2409   { "andS",             { Gv, EvS }, 0 },
2410   { "andB",             { AL, Ib }, 0 },
2411   { "andS",             { eAX, Iv }, 0 },
2412   { Bad_Opcode },       /* SEG ES prefix */
2413   { X86_64_TABLE (X86_64_27) },
2414   /* 28 */
2415   { "subB",             { Ebh1, Gb }, 0 },
2416   { "subS",             { Evh1, Gv }, 0 },
2417   { "subB",             { Gb, EbS }, 0 },
2418   { "subS",             { Gv, EvS }, 0 },
2419   { "subB",             { AL, Ib }, 0 },
2420   { "subS",             { eAX, Iv }, 0 },
2421   { Bad_Opcode },       /* SEG CS prefix */
2422   { X86_64_TABLE (X86_64_2F) },
2423   /* 30 */
2424   { "xorB",             { Ebh1, Gb }, 0 },
2425   { "xorS",             { Evh1, Gv }, 0 },
2426   { "xorB",             { Gb, EbS }, 0 },
2427   { "xorS",             { Gv, EvS }, 0 },
2428   { "xorB",             { AL, Ib }, 0 },
2429   { "xorS",             { eAX, Iv }, 0 },
2430   { Bad_Opcode },       /* SEG SS prefix */
2431   { X86_64_TABLE (X86_64_37) },
2432   /* 38 */
2433   { "cmpB",             { Eb, Gb }, 0 },
2434   { "cmpS",             { Ev, Gv }, 0 },
2435   { "cmpB",             { Gb, EbS }, 0 },
2436   { "cmpS",             { Gv, EvS }, 0 },
2437   { "cmpB",             { AL, Ib }, 0 },
2438   { "cmpS",             { eAX, Iv }, 0 },
2439   { Bad_Opcode },       /* SEG DS prefix */
2440   { X86_64_TABLE (X86_64_3F) },
2441   /* 40 */
2442   { "inc{S|}",          { RMeAX }, 0 },
2443   { "inc{S|}",          { RMeCX }, 0 },
2444   { "inc{S|}",          { RMeDX }, 0 },
2445   { "inc{S|}",          { RMeBX }, 0 },
2446   { "inc{S|}",          { RMeSP }, 0 },
2447   { "inc{S|}",          { RMeBP }, 0 },
2448   { "inc{S|}",          { RMeSI }, 0 },
2449   { "inc{S|}",          { RMeDI }, 0 },
2450   /* 48 */
2451   { "dec{S|}",          { RMeAX }, 0 },
2452   { "dec{S|}",          { RMeCX }, 0 },
2453   { "dec{S|}",          { RMeDX }, 0 },
2454   { "dec{S|}",          { RMeBX }, 0 },
2455   { "dec{S|}",          { RMeSP }, 0 },
2456   { "dec{S|}",          { RMeBP }, 0 },
2457   { "dec{S|}",          { RMeSI }, 0 },
2458   { "dec{S|}",          { RMeDI }, 0 },
2459   /* 50 */
2460   { "pushV",            { RMrAX }, 0 },
2461   { "pushV",            { RMrCX }, 0 },
2462   { "pushV",            { RMrDX }, 0 },
2463   { "pushV",            { RMrBX }, 0 },
2464   { "pushV",            { RMrSP }, 0 },
2465   { "pushV",            { RMrBP }, 0 },
2466   { "pushV",            { RMrSI }, 0 },
2467   { "pushV",            { RMrDI }, 0 },
2468   /* 58 */
2469   { "popV",             { RMrAX }, 0 },
2470   { "popV",             { RMrCX }, 0 },
2471   { "popV",             { RMrDX }, 0 },
2472   { "popV",             { RMrBX }, 0 },
2473   { "popV",             { RMrSP }, 0 },
2474   { "popV",             { RMrBP }, 0 },
2475   { "popV",             { RMrSI }, 0 },
2476   { "popV",             { RMrDI }, 0 },
2477   /* 60 */
2478   { X86_64_TABLE (X86_64_60) },
2479   { X86_64_TABLE (X86_64_61) },
2480   { X86_64_TABLE (X86_64_62) },
2481   { X86_64_TABLE (X86_64_63) },
2482   { Bad_Opcode },       /* seg fs */
2483   { Bad_Opcode },       /* seg gs */
2484   { Bad_Opcode },       /* op size prefix */
2485   { Bad_Opcode },       /* adr size prefix */
2486   /* 68 */
2487   { "pushT",            { sIv }, 0 },
2488   { "imulS",            { Gv, Ev, Iv }, 0 },
2489   { "pushT",            { sIbT }, 0 },
2490   { "imulS",            { Gv, Ev, sIb }, 0 },
2491   { "ins{b|}",          { Ybr, indirDX }, 0 },
2492   { X86_64_TABLE (X86_64_6D) },
2493   { "outs{b|}",         { indirDXr, Xb }, 0 },
2494   { X86_64_TABLE (X86_64_6F) },
2495   /* 70 */
2496   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2497   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2498   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2499   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2500   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2501   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2502   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2504   /* 78 */
2505   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2506   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2507   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2508   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2509   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2510   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2511   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2512   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2513   /* 80 */
2514   { REG_TABLE (REG_80) },
2515   { REG_TABLE (REG_81) },
2516   { X86_64_TABLE (X86_64_82) },
2517   { REG_TABLE (REG_83) },
2518   { "testB",            { Eb, Gb }, 0 },
2519   { "testS",            { Ev, Gv }, 0 },
2520   { "xchgB",            { Ebh2, Gb }, 0 },
2521   { "xchgS",            { Evh2, Gv }, 0 },
2522   /* 88 */
2523   { "movB",             { Ebh3, Gb }, 0 },
2524   { "movS",             { Evh3, Gv }, 0 },
2525   { "movB",             { Gb, EbS }, 0 },
2526   { "movS",             { Gv, EvS }, 0 },
2527   { "movD",             { Sv, Sw }, 0 },
2528   { MOD_TABLE (MOD_8D) },
2529   { "movD",             { Sw, Sv }, 0 },
2530   { REG_TABLE (REG_8F) },
2531   /* 90 */
2532   { PREFIX_TABLE (PREFIX_90) },
2533   { "xchgS",            { RMeCX, eAX }, 0 },
2534   { "xchgS",            { RMeDX, eAX }, 0 },
2535   { "xchgS",            { RMeBX, eAX }, 0 },
2536   { "xchgS",            { RMeSP, eAX }, 0 },
2537   { "xchgS",            { RMeBP, eAX }, 0 },
2538   { "xchgS",            { RMeSI, eAX }, 0 },
2539   { "xchgS",            { RMeDI, eAX }, 0 },
2540   /* 98 */
2541   { "cW{t|}R",          { XX }, 0 },
2542   { "cR{t|}O",          { XX }, 0 },
2543   { X86_64_TABLE (X86_64_9A) },
2544   { Bad_Opcode },       /* fwait */
2545   { "pushfT",           { XX }, 0 },
2546   { "popfT",            { XX }, 0 },
2547   { "sahf",             { XX }, 0 },
2548   { "lahf",             { XX }, 0 },
2549   /* a0 */
2550   { "mov%LB",           { AL, Ob }, 0 },
2551   { "mov%LS",           { eAX, Ov }, 0 },
2552   { "mov%LB",           { Ob, AL }, 0 },
2553   { "mov%LS",           { Ov, eAX }, 0 },
2554   { "movs{b|}",         { Ybr, Xb }, 0 },
2555   { "movs{R|}",         { Yvr, Xv }, 0 },
2556   { "cmps{b|}",         { Xb, Yb }, 0 },
2557   { "cmps{R|}",         { Xv, Yv }, 0 },
2558   /* a8 */
2559   { "testB",            { AL, Ib }, 0 },
2560   { "testS",            { eAX, Iv }, 0 },
2561   { "stosB",            { Ybr, AL }, 0 },
2562   { "stosS",            { Yvr, eAX }, 0 },
2563   { "lodsB",            { ALr, Xb }, 0 },
2564   { "lodsS",            { eAXr, Xv }, 0 },
2565   { "scasB",            { AL, Yb }, 0 },
2566   { "scasS",            { eAX, Yv }, 0 },
2567   /* b0 */
2568   { "movB",             { RMAL, Ib }, 0 },
2569   { "movB",             { RMCL, Ib }, 0 },
2570   { "movB",             { RMDL, Ib }, 0 },
2571   { "movB",             { RMBL, Ib }, 0 },
2572   { "movB",             { RMAH, Ib }, 0 },
2573   { "movB",             { RMCH, Ib }, 0 },
2574   { "movB",             { RMDH, Ib }, 0 },
2575   { "movB",             { RMBH, Ib }, 0 },
2576   /* b8 */
2577   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2578   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2579   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2580   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2581   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2582   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2583   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2584   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2585   /* c0 */
2586   { REG_TABLE (REG_C0) },
2587   { REG_TABLE (REG_C1) },
2588   { X86_64_TABLE (X86_64_C2) },
2589   { X86_64_TABLE (X86_64_C3) },
2590   { X86_64_TABLE (X86_64_C4) },
2591   { X86_64_TABLE (X86_64_C5) },
2592   { REG_TABLE (REG_C6) },
2593   { REG_TABLE (REG_C7) },
2594   /* c8 */
2595   { "enterT",           { Iw, Ib }, 0 },
2596   { "leaveT",           { XX }, 0 },
2597   { "Jret{|f}P",        { Iw }, 0 },
2598   { "Jret{|f}P",        { XX }, 0 },
2599   { "int3",             { XX }, 0 },
2600   { "int",              { Ib }, 0 },
2601   { X86_64_TABLE (X86_64_CE) },
2602   { "iret%LP",          { XX }, 0 },
2603   /* d0 */
2604   { REG_TABLE (REG_D0) },
2605   { REG_TABLE (REG_D1) },
2606   { REG_TABLE (REG_D2) },
2607   { REG_TABLE (REG_D3) },
2608   { X86_64_TABLE (X86_64_D4) },
2609   { X86_64_TABLE (X86_64_D5) },
2610   { Bad_Opcode },
2611   { "xlat",             { DSBX }, 0 },
2612   /* d8 */
2613   { FLOAT },
2614   { FLOAT },
2615   { FLOAT },
2616   { FLOAT },
2617   { FLOAT },
2618   { FLOAT },
2619   { FLOAT },
2620   { FLOAT },
2621   /* e0 */
2622   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2623   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2624   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2625   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2626   { "inB",              { AL, Ib }, 0 },
2627   { "inG",              { zAX, Ib }, 0 },
2628   { "outB",             { Ib, AL }, 0 },
2629   { "outG",             { Ib, zAX }, 0 },
2630   /* e8 */
2631   { X86_64_TABLE (X86_64_E8) },
2632   { X86_64_TABLE (X86_64_E9) },
2633   { X86_64_TABLE (X86_64_EA) },
2634   { "jmp",              { Jb, BND }, 0 },
2635   { "inB",              { AL, indirDX }, 0 },
2636   { "inG",              { zAX, indirDX }, 0 },
2637   { "outB",             { indirDX, AL }, 0 },
2638   { "outG",             { indirDX, zAX }, 0 },
2639   /* f0 */
2640   { Bad_Opcode },       /* lock prefix */
2641   { "icebp",            { XX }, 0 },
2642   { Bad_Opcode },       /* repne */
2643   { Bad_Opcode },       /* repz */
2644   { "hlt",              { XX }, 0 },
2645   { "cmc",              { XX }, 0 },
2646   { REG_TABLE (REG_F6) },
2647   { REG_TABLE (REG_F7) },
2648   /* f8 */
2649   { "clc",              { XX }, 0 },
2650   { "stc",              { XX }, 0 },
2651   { "cli",              { XX }, 0 },
2652   { "sti",              { XX }, 0 },
2653   { "cld",              { XX }, 0 },
2654   { "std",              { XX }, 0 },
2655   { REG_TABLE (REG_FE) },
2656   { REG_TABLE (REG_FF) },
2657 };
2658
2659 static const struct dis386 dis386_twobyte[] = {
2660   /* 00 */
2661   { REG_TABLE (REG_0F00 ) },
2662   { REG_TABLE (REG_0F01 ) },
2663   { "larS",             { Gv, Ew }, 0 },
2664   { "lslS",             { Gv, Ew }, 0 },
2665   { Bad_Opcode },
2666   { "syscall",          { XX }, 0 },
2667   { "clts",             { XX }, 0 },
2668   { "sysret%LP",                { XX }, 0 },
2669   /* 08 */
2670   { "invd",             { XX }, 0 },
2671   { PREFIX_TABLE (PREFIX_0F09) },
2672   { Bad_Opcode },
2673   { "ud2",              { XX }, 0 },
2674   { Bad_Opcode },
2675   { REG_TABLE (REG_0F0D) },
2676   { "femms",            { XX }, 0 },
2677   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2678   /* 10 */
2679   { PREFIX_TABLE (PREFIX_0F10) },
2680   { PREFIX_TABLE (PREFIX_0F11) },
2681   { PREFIX_TABLE (PREFIX_0F12) },
2682   { MOD_TABLE (MOD_0F13) },
2683   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2684   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2685   { PREFIX_TABLE (PREFIX_0F16) },
2686   { MOD_TABLE (MOD_0F17) },
2687   /* 18 */
2688   { REG_TABLE (REG_0F18) },
2689   { "nopQ",             { Ev }, 0 },
2690   { PREFIX_TABLE (PREFIX_0F1A) },
2691   { PREFIX_TABLE (PREFIX_0F1B) },
2692   { PREFIX_TABLE (PREFIX_0F1C) },
2693   { "nopQ",             { Ev }, 0 },
2694   { PREFIX_TABLE (PREFIX_0F1E) },
2695   { "nopQ",             { Ev }, 0 },
2696   /* 20 */
2697   { "movZ",             { Rm, Cm }, 0 },
2698   { "movZ",             { Rm, Dm }, 0 },
2699   { "movZ",             { Cm, Rm }, 0 },
2700   { "movZ",             { Dm, Rm }, 0 },
2701   { MOD_TABLE (MOD_0F24) },
2702   { Bad_Opcode },
2703   { MOD_TABLE (MOD_0F26) },
2704   { Bad_Opcode },
2705   /* 28 */
2706   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2707   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2708   { PREFIX_TABLE (PREFIX_0F2A) },
2709   { PREFIX_TABLE (PREFIX_0F2B) },
2710   { PREFIX_TABLE (PREFIX_0F2C) },
2711   { PREFIX_TABLE (PREFIX_0F2D) },
2712   { PREFIX_TABLE (PREFIX_0F2E) },
2713   { PREFIX_TABLE (PREFIX_0F2F) },
2714   /* 30 */
2715   { "wrmsr",            { XX }, 0 },
2716   { "rdtsc",            { XX }, 0 },
2717   { "rdmsr",            { XX }, 0 },
2718   { "rdpmc",            { XX }, 0 },
2719   { "sysenter",         { SEP }, 0 },
2720   { "sysexit",          { SEP }, 0 },
2721   { Bad_Opcode },
2722   { "getsec",           { XX }, 0 },
2723   /* 38 */
2724   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2725   { Bad_Opcode },
2726   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2727   { Bad_Opcode },
2728   { Bad_Opcode },
2729   { Bad_Opcode },
2730   { Bad_Opcode },
2731   { Bad_Opcode },
2732   /* 40 */
2733   { "cmovoS",           { Gv, Ev }, 0 },
2734   { "cmovnoS",          { Gv, Ev }, 0 },
2735   { "cmovbS",           { Gv, Ev }, 0 },
2736   { "cmovaeS",          { Gv, Ev }, 0 },
2737   { "cmoveS",           { Gv, Ev }, 0 },
2738   { "cmovneS",          { Gv, Ev }, 0 },
2739   { "cmovbeS",          { Gv, Ev }, 0 },
2740   { "cmovaS",           { Gv, Ev }, 0 },
2741   /* 48 */
2742   { "cmovsS",           { Gv, Ev }, 0 },
2743   { "cmovnsS",          { Gv, Ev }, 0 },
2744   { "cmovpS",           { Gv, Ev }, 0 },
2745   { "cmovnpS",          { Gv, Ev }, 0 },
2746   { "cmovlS",           { Gv, Ev }, 0 },
2747   { "cmovgeS",          { Gv, Ev }, 0 },
2748   { "cmovleS",          { Gv, Ev }, 0 },
2749   { "cmovgS",           { Gv, Ev }, 0 },
2750   /* 50 */
2751   { MOD_TABLE (MOD_0F51) },
2752   { PREFIX_TABLE (PREFIX_0F51) },
2753   { PREFIX_TABLE (PREFIX_0F52) },
2754   { PREFIX_TABLE (PREFIX_0F53) },
2755   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2756   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2757   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2758   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2759   /* 58 */
2760   { PREFIX_TABLE (PREFIX_0F58) },
2761   { PREFIX_TABLE (PREFIX_0F59) },
2762   { PREFIX_TABLE (PREFIX_0F5A) },
2763   { PREFIX_TABLE (PREFIX_0F5B) },
2764   { PREFIX_TABLE (PREFIX_0F5C) },
2765   { PREFIX_TABLE (PREFIX_0F5D) },
2766   { PREFIX_TABLE (PREFIX_0F5E) },
2767   { PREFIX_TABLE (PREFIX_0F5F) },
2768   /* 60 */
2769   { PREFIX_TABLE (PREFIX_0F60) },
2770   { PREFIX_TABLE (PREFIX_0F61) },
2771   { PREFIX_TABLE (PREFIX_0F62) },
2772   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2773   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2774   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2775   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2776   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2777   /* 68 */
2778   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2779   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2780   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2781   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2782   { PREFIX_TABLE (PREFIX_0F6C) },
2783   { PREFIX_TABLE (PREFIX_0F6D) },
2784   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2785   { PREFIX_TABLE (PREFIX_0F6F) },
2786   /* 70 */
2787   { PREFIX_TABLE (PREFIX_0F70) },
2788   { REG_TABLE (REG_0F71) },
2789   { REG_TABLE (REG_0F72) },
2790   { REG_TABLE (REG_0F73) },
2791   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2792   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2793   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2794   { "emms",             { XX }, PREFIX_OPCODE },
2795   /* 78 */
2796   { PREFIX_TABLE (PREFIX_0F78) },
2797   { PREFIX_TABLE (PREFIX_0F79) },
2798   { Bad_Opcode },
2799   { Bad_Opcode },
2800   { PREFIX_TABLE (PREFIX_0F7C) },
2801   { PREFIX_TABLE (PREFIX_0F7D) },
2802   { PREFIX_TABLE (PREFIX_0F7E) },
2803   { PREFIX_TABLE (PREFIX_0F7F) },
2804   /* 80 */
2805   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2806   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2807   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2808   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2809   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2810   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2811   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2813   /* 88 */
2814   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2815   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2816   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2817   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2818   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2819   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2820   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2821   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2822   /* 90 */
2823   { "seto",             { Eb }, 0 },
2824   { "setno",            { Eb }, 0 },
2825   { "setb",             { Eb }, 0 },
2826   { "setae",            { Eb }, 0 },
2827   { "sete",             { Eb }, 0 },
2828   { "setne",            { Eb }, 0 },
2829   { "setbe",            { Eb }, 0 },
2830   { "seta",             { Eb }, 0 },
2831   /* 98 */
2832   { "sets",             { Eb }, 0 },
2833   { "setns",            { Eb }, 0 },
2834   { "setp",             { Eb }, 0 },
2835   { "setnp",            { Eb }, 0 },
2836   { "setl",             { Eb }, 0 },
2837   { "setge",            { Eb }, 0 },
2838   { "setle",            { Eb }, 0 },
2839   { "setg",             { Eb }, 0 },
2840   /* a0 */
2841   { "pushT",            { fs }, 0 },
2842   { "popT",             { fs }, 0 },
2843   { "cpuid",            { XX }, 0 },
2844   { "btS",              { Ev, Gv }, 0 },
2845   { "shldS",            { Ev, Gv, Ib }, 0 },
2846   { "shldS",            { Ev, Gv, CL }, 0 },
2847   { REG_TABLE (REG_0FA6) },
2848   { REG_TABLE (REG_0FA7) },
2849   /* a8 */
2850   { "pushT",            { gs }, 0 },
2851   { "popT",             { gs }, 0 },
2852   { "rsm",              { XX }, 0 },
2853   { "btsS",             { Evh1, Gv }, 0 },
2854   { "shrdS",            { Ev, Gv, Ib }, 0 },
2855   { "shrdS",            { Ev, Gv, CL }, 0 },
2856   { REG_TABLE (REG_0FAE) },
2857   { "imulS",            { Gv, Ev }, 0 },
2858   /* b0 */
2859   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2860   { "cmpxchgS",         { Evh1, Gv }, 0 },
2861   { MOD_TABLE (MOD_0FB2) },
2862   { "btrS",             { Evh1, Gv }, 0 },
2863   { MOD_TABLE (MOD_0FB4) },
2864   { MOD_TABLE (MOD_0FB5) },
2865   { "movz{bR|x}",       { Gv, Eb }, 0 },
2866   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2867   /* b8 */
2868   { PREFIX_TABLE (PREFIX_0FB8) },
2869   { "ud1S",             { Gv, Ev }, 0 },
2870   { REG_TABLE (REG_0FBA) },
2871   { "btcS",             { Evh1, Gv }, 0 },
2872   { PREFIX_TABLE (PREFIX_0FBC) },
2873   { PREFIX_TABLE (PREFIX_0FBD) },
2874   { "movs{bR|x}",       { Gv, Eb }, 0 },
2875   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2876   /* c0 */
2877   { "xaddB",            { Ebh1, Gb }, 0 },
2878   { "xaddS",            { Evh1, Gv }, 0 },
2879   { PREFIX_TABLE (PREFIX_0FC2) },
2880   { MOD_TABLE (MOD_0FC3) },
2881   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2882   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2883   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2884   { REG_TABLE (REG_0FC7) },
2885   /* c8 */
2886   { "bswap",            { RMeAX }, 0 },
2887   { "bswap",            { RMeCX }, 0 },
2888   { "bswap",            { RMeDX }, 0 },
2889   { "bswap",            { RMeBX }, 0 },
2890   { "bswap",            { RMeSP }, 0 },
2891   { "bswap",            { RMeBP }, 0 },
2892   { "bswap",            { RMeSI }, 0 },
2893   { "bswap",            { RMeDI }, 0 },
2894   /* d0 */
2895   { PREFIX_TABLE (PREFIX_0FD0) },
2896   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2897   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2898   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2899   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2900   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2901   { PREFIX_TABLE (PREFIX_0FD6) },
2902   { MOD_TABLE (MOD_0FD7) },
2903   /* d8 */
2904   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2905   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2906   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2907   { "pand",             { MX, EM }, PREFIX_OPCODE },
2908   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2909   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2910   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2911   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2912   /* e0 */
2913   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2914   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2915   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2916   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2917   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2918   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2919   { PREFIX_TABLE (PREFIX_0FE6) },
2920   { PREFIX_TABLE (PREFIX_0FE7) },
2921   /* e8 */
2922   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2923   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2924   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2925   { "por",              { MX, EM }, PREFIX_OPCODE },
2926   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2927   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2928   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2929   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2930   /* f0 */
2931   { PREFIX_TABLE (PREFIX_0FF0) },
2932   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2933   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2934   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2935   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2936   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2937   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2938   { PREFIX_TABLE (PREFIX_0FF7) },
2939   /* f8 */
2940   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2941   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2942   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2943   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2944   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2945   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2946   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2947   { "ud0S",             { Gv, Ev }, 0 },
2948 };
2949
2950 static const unsigned char onebyte_has_modrm[256] = {
2951   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2952   /*       -------------------------------        */
2953   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2954   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2955   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2956   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2957   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2958   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2959   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2960   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2961   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2962   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2963   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2964   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2965   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2966   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2967   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2968   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2969   /*       -------------------------------        */
2970   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2971 };
2972
2973 static const unsigned char twobyte_has_modrm[256] = {
2974   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2975   /*       -------------------------------        */
2976   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2977   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2978   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2979   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2980   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2981   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2982   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2983   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2984   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2985   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2986   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2987   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2988   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2989   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2990   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2991   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2992   /*       -------------------------------        */
2993   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2994 };
2995
2996 static char obuf[100];
2997 static char *obufp;
2998 static char *mnemonicendp;
2999 static char scratchbuf[100];
3000 static unsigned char *start_codep;
3001 static unsigned char *insn_codep;
3002 static unsigned char *codep;
3003 static unsigned char *end_codep;
3004 static int last_lock_prefix;
3005 static int last_repz_prefix;
3006 static int last_repnz_prefix;
3007 static int last_data_prefix;
3008 static int last_addr_prefix;
3009 static int last_rex_prefix;
3010 static int last_seg_prefix;
3011 static int fwait_prefix;
3012 /* The active segment register prefix.  */
3013 static int active_seg_prefix;
3014 #define MAX_CODE_LENGTH 15
3015 /* We can up to 14 prefixes since the maximum instruction length is
3016    15bytes.  */
3017 static int all_prefixes[MAX_CODE_LENGTH - 1];
3018 static disassemble_info *the_info;
3019 static struct
3020   {
3021     int mod;
3022     int reg;
3023     int rm;
3024   }
3025 modrm;
3026 static unsigned char need_modrm;
3027 static struct
3028   {
3029     int scale;
3030     int index;
3031     int base;
3032   }
3033 sib;
3034 static struct
3035   {
3036     int register_specifier;
3037     int length;
3038     int prefix;
3039     int w;
3040     int evex;
3041     int r;
3042     int v;
3043     int mask_register_specifier;
3044     int zeroing;
3045     int ll;
3046     int b;
3047   }
3048 vex;
3049 static unsigned char need_vex;
3050 static unsigned char need_vex_reg;
3051 static unsigned char vex_w_done;
3052
3053 struct op
3054   {
3055     const char *name;
3056     unsigned int len;
3057   };
3058
3059 /* If we are accessing mod/rm/reg without need_modrm set, then the
3060    values are stale.  Hitting this abort likely indicates that you
3061    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3062 #define MODRM_CHECK  if (!need_modrm) abort ()
3063
3064 static const char **names64;
3065 static const char **names32;
3066 static const char **names16;
3067 static const char **names8;
3068 static const char **names8rex;
3069 static const char **names_seg;
3070 static const char *index64;
3071 static const char *index32;
3072 static const char **index16;
3073 static const char **names_bnd;
3074
3075 static const char *intel_names64[] = {
3076   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3077   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3078 };
3079 static const char *intel_names32[] = {
3080   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3081   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3082 };
3083 static const char *intel_names16[] = {
3084   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3085   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3086 };
3087 static const char *intel_names8[] = {
3088   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3089 };
3090 static const char *intel_names8rex[] = {
3091   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3092   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3093 };
3094 static const char *intel_names_seg[] = {
3095   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3096 };
3097 static const char *intel_index64 = "riz";
3098 static const char *intel_index32 = "eiz";
3099 static const char *intel_index16[] = {
3100   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3101 };
3102
3103 static const char *att_names64[] = {
3104   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3105   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3106 };
3107 static const char *att_names32[] = {
3108   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3109   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3110 };
3111 static const char *att_names16[] = {
3112   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3113   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3114 };
3115 static const char *att_names8[] = {
3116   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3117 };
3118 static const char *att_names8rex[] = {
3119   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3120   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3121 };
3122 static const char *att_names_seg[] = {
3123   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3124 };
3125 static const char *att_index64 = "%riz";
3126 static const char *att_index32 = "%eiz";
3127 static const char *att_index16[] = {
3128   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3129 };
3130
3131 static const char **names_mm;
3132 static const char *intel_names_mm[] = {
3133   "mm0", "mm1", "mm2", "mm3",
3134   "mm4", "mm5", "mm6", "mm7"
3135 };
3136 static const char *att_names_mm[] = {
3137   "%mm0", "%mm1", "%mm2", "%mm3",
3138   "%mm4", "%mm5", "%mm6", "%mm7"
3139 };
3140
3141 static const char *intel_names_bnd[] = {
3142   "bnd0", "bnd1", "bnd2", "bnd3"
3143 };
3144
3145 static const char *att_names_bnd[] = {
3146   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3147 };
3148
3149 static const char **names_xmm;
3150 static const char *intel_names_xmm[] = {
3151   "xmm0", "xmm1", "xmm2", "xmm3",
3152   "xmm4", "xmm5", "xmm6", "xmm7",
3153   "xmm8", "xmm9", "xmm10", "xmm11",
3154   "xmm12", "xmm13", "xmm14", "xmm15",
3155   "xmm16", "xmm17", "xmm18", "xmm19",
3156   "xmm20", "xmm21", "xmm22", "xmm23",
3157   "xmm24", "xmm25", "xmm26", "xmm27",
3158   "xmm28", "xmm29", "xmm30", "xmm31"
3159 };
3160 static const char *att_names_xmm[] = {
3161   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3162   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3163   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3164   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3165   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3166   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3167   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3168   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3169 };
3170
3171 static const char **names_ymm;
3172 static const char *intel_names_ymm[] = {
3173   "ymm0", "ymm1", "ymm2", "ymm3",
3174   "ymm4", "ymm5", "ymm6", "ymm7",
3175   "ymm8", "ymm9", "ymm10", "ymm11",
3176   "ymm12", "ymm13", "ymm14", "ymm15",
3177   "ymm16", "ymm17", "ymm18", "ymm19",
3178   "ymm20", "ymm21", "ymm22", "ymm23",
3179   "ymm24", "ymm25", "ymm26", "ymm27",
3180   "ymm28", "ymm29", "ymm30", "ymm31"
3181 };
3182 static const char *att_names_ymm[] = {
3183   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3184   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3185   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3186   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3187   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3188   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3189   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3190   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3191 };
3192
3193 static const char **names_zmm;
3194 static const char *intel_names_zmm[] = {
3195   "zmm0", "zmm1", "zmm2", "zmm3",
3196   "zmm4", "zmm5", "zmm6", "zmm7",
3197   "zmm8", "zmm9", "zmm10", "zmm11",
3198   "zmm12", "zmm13", "zmm14", "zmm15",
3199   "zmm16", "zmm17", "zmm18", "zmm19",
3200   "zmm20", "zmm21", "zmm22", "zmm23",
3201   "zmm24", "zmm25", "zmm26", "zmm27",
3202   "zmm28", "zmm29", "zmm30", "zmm31"
3203 };
3204 static const char *att_names_zmm[] = {
3205   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3206   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3207   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3208   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3209   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3210   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3211   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3212   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3213 };
3214
3215 static const char **names_mask;
3216 static const char *intel_names_mask[] = {
3217   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3218 };
3219 static const char *att_names_mask[] = {
3220   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3221 };
3222
3223 static const char *names_rounding[] =
3224 {
3225   "{rn-sae}",
3226   "{rd-sae}",
3227   "{ru-sae}",
3228   "{rz-sae}"
3229 };
3230
3231 static const struct dis386 reg_table[][8] = {
3232   /* REG_80 */
3233   {
3234     { "addA",   { Ebh1, Ib }, 0 },
3235     { "orA",    { Ebh1, Ib }, 0 },
3236     { "adcA",   { Ebh1, Ib }, 0 },
3237     { "sbbA",   { Ebh1, Ib }, 0 },
3238     { "andA",   { Ebh1, Ib }, 0 },
3239     { "subA",   { Ebh1, Ib }, 0 },
3240     { "xorA",   { Ebh1, Ib }, 0 },
3241     { "cmpA",   { Eb, Ib }, 0 },
3242   },
3243   /* REG_81 */
3244   {
3245     { "addQ",   { Evh1, Iv }, 0 },
3246     { "orQ",    { Evh1, Iv }, 0 },
3247     { "adcQ",   { Evh1, Iv }, 0 },
3248     { "sbbQ",   { Evh1, Iv }, 0 },
3249     { "andQ",   { Evh1, Iv }, 0 },
3250     { "subQ",   { Evh1, Iv }, 0 },
3251     { "xorQ",   { Evh1, Iv }, 0 },
3252     { "cmpQ",   { Ev, Iv }, 0 },
3253   },
3254   /* REG_83 */
3255   {
3256     { "addQ",   { Evh1, sIb }, 0 },
3257     { "orQ",    { Evh1, sIb }, 0 },
3258     { "adcQ",   { Evh1, sIb }, 0 },
3259     { "sbbQ",   { Evh1, sIb }, 0 },
3260     { "andQ",   { Evh1, sIb }, 0 },
3261     { "subQ",   { Evh1, sIb }, 0 },
3262     { "xorQ",   { Evh1, sIb }, 0 },
3263     { "cmpQ",   { Ev, sIb }, 0 },
3264   },
3265   /* REG_8F */
3266   {
3267     { "popU",   { stackEv }, 0 },
3268     { XOP_8F_TABLE (XOP_09) },
3269     { Bad_Opcode },
3270     { Bad_Opcode },
3271     { Bad_Opcode },
3272     { XOP_8F_TABLE (XOP_09) },
3273   },
3274   /* REG_C0 */
3275   {
3276     { "rolA",   { Eb, Ib }, 0 },
3277     { "rorA",   { Eb, Ib }, 0 },
3278     { "rclA",   { Eb, Ib }, 0 },
3279     { "rcrA",   { Eb, Ib }, 0 },
3280     { "shlA",   { Eb, Ib }, 0 },
3281     { "shrA",   { Eb, Ib }, 0 },
3282     { "shlA",   { Eb, Ib }, 0 },
3283     { "sarA",   { Eb, Ib }, 0 },
3284   },
3285   /* REG_C1 */
3286   {
3287     { "rolQ",   { Ev, Ib }, 0 },
3288     { "rorQ",   { Ev, Ib }, 0 },
3289     { "rclQ",   { Ev, Ib }, 0 },
3290     { "rcrQ",   { Ev, Ib }, 0 },
3291     { "shlQ",   { Ev, Ib }, 0 },
3292     { "shrQ",   { Ev, Ib }, 0 },
3293     { "shlQ",   { Ev, Ib }, 0 },
3294     { "sarQ",   { Ev, Ib }, 0 },
3295   },
3296   /* REG_C6 */
3297   {
3298     { "movA",   { Ebh3, Ib }, 0 },
3299     { Bad_Opcode },
3300     { Bad_Opcode },
3301     { Bad_Opcode },
3302     { Bad_Opcode },
3303     { Bad_Opcode },
3304     { Bad_Opcode },
3305     { MOD_TABLE (MOD_C6_REG_7) },
3306   },
3307   /* REG_C7 */
3308   {
3309     { "movQ",   { Evh3, Iv }, 0 },
3310     { Bad_Opcode },
3311     { Bad_Opcode },
3312     { Bad_Opcode },
3313     { Bad_Opcode },
3314     { Bad_Opcode },
3315     { Bad_Opcode },
3316     { MOD_TABLE (MOD_C7_REG_7) },
3317   },
3318   /* REG_D0 */
3319   {
3320     { "rolA",   { Eb, I1 }, 0 },
3321     { "rorA",   { Eb, I1 }, 0 },
3322     { "rclA",   { Eb, I1 }, 0 },
3323     { "rcrA",   { Eb, I1 }, 0 },
3324     { "shlA",   { Eb, I1 }, 0 },
3325     { "shrA",   { Eb, I1 }, 0 },
3326     { "shlA",   { Eb, I1 }, 0 },
3327     { "sarA",   { Eb, I1 }, 0 },
3328   },
3329   /* REG_D1 */
3330   {
3331     { "rolQ",   { Ev, I1 }, 0 },
3332     { "rorQ",   { Ev, I1 }, 0 },
3333     { "rclQ",   { Ev, I1 }, 0 },
3334     { "rcrQ",   { Ev, I1 }, 0 },
3335     { "shlQ",   { Ev, I1 }, 0 },
3336     { "shrQ",   { Ev, I1 }, 0 },
3337     { "shlQ",   { Ev, I1 }, 0 },
3338     { "sarQ",   { Ev, I1 }, 0 },
3339   },
3340   /* REG_D2 */
3341   {
3342     { "rolA",   { Eb, CL }, 0 },
3343     { "rorA",   { Eb, CL }, 0 },
3344     { "rclA",   { Eb, CL }, 0 },
3345     { "rcrA",   { Eb, CL }, 0 },
3346     { "shlA",   { Eb, CL }, 0 },
3347     { "shrA",   { Eb, CL }, 0 },
3348     { "shlA",   { Eb, CL }, 0 },
3349     { "sarA",   { Eb, CL }, 0 },
3350   },
3351   /* REG_D3 */
3352   {
3353     { "rolQ",   { Ev, CL }, 0 },
3354     { "rorQ",   { Ev, CL }, 0 },
3355     { "rclQ",   { Ev, CL }, 0 },
3356     { "rcrQ",   { Ev, CL }, 0 },
3357     { "shlQ",   { Ev, CL }, 0 },
3358     { "shrQ",   { Ev, CL }, 0 },
3359     { "shlQ",   { Ev, CL }, 0 },
3360     { "sarQ",   { Ev, CL }, 0 },
3361   },
3362   /* REG_F6 */
3363   {
3364     { "testA",  { Eb, Ib }, 0 },
3365     { "testA",  { Eb, Ib }, 0 },
3366     { "notA",   { Ebh1 }, 0 },
3367     { "negA",   { Ebh1 }, 0 },
3368     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3369     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3370     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3371     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3372   },
3373   /* REG_F7 */
3374   {
3375     { "testQ",  { Ev, Iv }, 0 },
3376     { "testQ",  { Ev, Iv }, 0 },
3377     { "notQ",   { Evh1 }, 0 },
3378     { "negQ",   { Evh1 }, 0 },
3379     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3380     { "imulQ",  { Ev }, 0 },
3381     { "divQ",   { Ev }, 0 },
3382     { "idivQ",  { Ev }, 0 },
3383   },
3384   /* REG_FE */
3385   {
3386     { "incA",   { Ebh1 }, 0 },
3387     { "decA",   { Ebh1 }, 0 },
3388   },
3389   /* REG_FF */
3390   {
3391     { "incQ",   { Evh1 }, 0 },
3392     { "decQ",   { Evh1 }, 0 },
3393     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3394     { MOD_TABLE (MOD_FF_REG_3) },
3395     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3396     { MOD_TABLE (MOD_FF_REG_5) },
3397     { "pushU",  { stackEv }, 0 },
3398     { Bad_Opcode },
3399   },
3400   /* REG_0F00 */
3401   {
3402     { "sldtD",  { Sv }, 0 },
3403     { "strD",   { Sv }, 0 },
3404     { "lldt",   { Ew }, 0 },
3405     { "ltr",    { Ew }, 0 },
3406     { "verr",   { Ew }, 0 },
3407     { "verw",   { Ew }, 0 },
3408     { Bad_Opcode },
3409     { Bad_Opcode },
3410   },
3411   /* REG_0F01 */
3412   {
3413     { MOD_TABLE (MOD_0F01_REG_0) },
3414     { MOD_TABLE (MOD_0F01_REG_1) },
3415     { MOD_TABLE (MOD_0F01_REG_2) },
3416     { MOD_TABLE (MOD_0F01_REG_3) },
3417     { "smswD",  { Sv }, 0 },
3418     { MOD_TABLE (MOD_0F01_REG_5) },
3419     { "lmsw",   { Ew }, 0 },
3420     { MOD_TABLE (MOD_0F01_REG_7) },
3421   },
3422   /* REG_0F0D */
3423   {
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetchw",      { Mb }, 0 },
3426     { "prefetchwt1",    { Mb }, 0 },
3427     { "prefetch",       { Mb }, 0 },
3428     { "prefetch",       { Mb }, 0 },
3429     { "prefetch",       { Mb }, 0 },
3430     { "prefetch",       { Mb }, 0 },
3431     { "prefetch",       { Mb }, 0 },
3432   },
3433   /* REG_0F18 */
3434   {
3435     { MOD_TABLE (MOD_0F18_REG_0) },
3436     { MOD_TABLE (MOD_0F18_REG_1) },
3437     { MOD_TABLE (MOD_0F18_REG_2) },
3438     { MOD_TABLE (MOD_0F18_REG_3) },
3439     { MOD_TABLE (MOD_0F18_REG_4) },
3440     { MOD_TABLE (MOD_0F18_REG_5) },
3441     { MOD_TABLE (MOD_0F18_REG_6) },
3442     { MOD_TABLE (MOD_0F18_REG_7) },
3443   },
3444   /* REG_0F1C_P_0_MOD_0 */
3445   {
3446     { "cldemote",       { Mb }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448     { "nopQ",           { Ev }, 0 },
3449     { "nopQ",           { Ev }, 0 },
3450     { "nopQ",           { Ev }, 0 },
3451     { "nopQ",           { Ev }, 0 },
3452     { "nopQ",           { Ev }, 0 },
3453     { "nopQ",           { Ev }, 0 },
3454   },
3455   /* REG_0F1E_P_1_MOD_3 */
3456   {
3457     { "nopQ",           { Ev }, 0 },
3458     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3459     { "nopQ",           { Ev }, 0 },
3460     { "nopQ",           { Ev }, 0 },
3461     { "nopQ",           { Ev }, 0 },
3462     { "nopQ",           { Ev }, 0 },
3463     { "nopQ",           { Ev }, 0 },
3464     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3465   },
3466   /* REG_0F71 */
3467   {
3468     { Bad_Opcode },
3469     { Bad_Opcode },
3470     { MOD_TABLE (MOD_0F71_REG_2) },
3471     { Bad_Opcode },
3472     { MOD_TABLE (MOD_0F71_REG_4) },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0F71_REG_6) },
3475   },
3476   /* REG_0F72 */
3477   {
3478     { Bad_Opcode },
3479     { Bad_Opcode },
3480     { MOD_TABLE (MOD_0F72_REG_2) },
3481     { Bad_Opcode },
3482     { MOD_TABLE (MOD_0F72_REG_4) },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_0F72_REG_6) },
3485   },
3486   /* REG_0F73 */
3487   {
3488     { Bad_Opcode },
3489     { Bad_Opcode },
3490     { MOD_TABLE (MOD_0F73_REG_2) },
3491     { MOD_TABLE (MOD_0F73_REG_3) },
3492     { Bad_Opcode },
3493     { Bad_Opcode },
3494     { MOD_TABLE (MOD_0F73_REG_6) },
3495     { MOD_TABLE (MOD_0F73_REG_7) },
3496   },
3497   /* REG_0FA6 */
3498   {
3499     { "montmul",        { { OP_0f07, 0 } }, 0 },
3500     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3501     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3502   },
3503   /* REG_0FA7 */
3504   {
3505     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3506     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3507     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3508     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3509     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3510     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3511   },
3512   /* REG_0FAE */
3513   {
3514     { MOD_TABLE (MOD_0FAE_REG_0) },
3515     { MOD_TABLE (MOD_0FAE_REG_1) },
3516     { MOD_TABLE (MOD_0FAE_REG_2) },
3517     { MOD_TABLE (MOD_0FAE_REG_3) },
3518     { MOD_TABLE (MOD_0FAE_REG_4) },
3519     { MOD_TABLE (MOD_0FAE_REG_5) },
3520     { MOD_TABLE (MOD_0FAE_REG_6) },
3521     { MOD_TABLE (MOD_0FAE_REG_7) },
3522   },
3523   /* REG_0FBA */
3524   {
3525     { Bad_Opcode },
3526     { Bad_Opcode },
3527     { Bad_Opcode },
3528     { Bad_Opcode },
3529     { "btQ",    { Ev, Ib }, 0 },
3530     { "btsQ",   { Evh1, Ib }, 0 },
3531     { "btrQ",   { Evh1, Ib }, 0 },
3532     { "btcQ",   { Evh1, Ib }, 0 },
3533   },
3534   /* REG_0FC7 */
3535   {
3536     { Bad_Opcode },
3537     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3538     { Bad_Opcode },
3539     { MOD_TABLE (MOD_0FC7_REG_3) },
3540     { MOD_TABLE (MOD_0FC7_REG_4) },
3541     { MOD_TABLE (MOD_0FC7_REG_5) },
3542     { MOD_TABLE (MOD_0FC7_REG_6) },
3543     { MOD_TABLE (MOD_0FC7_REG_7) },
3544   },
3545   /* REG_VEX_0F71 */
3546   {
3547     { Bad_Opcode },
3548     { Bad_Opcode },
3549     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3550     { Bad_Opcode },
3551     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3554   },
3555   /* REG_VEX_0F72 */
3556   {
3557     { Bad_Opcode },
3558     { Bad_Opcode },
3559     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3560     { Bad_Opcode },
3561     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3562     { Bad_Opcode },
3563     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3564   },
3565   /* REG_VEX_0F73 */
3566   {
3567     { Bad_Opcode },
3568     { Bad_Opcode },
3569     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3570     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3571     { Bad_Opcode },
3572     { Bad_Opcode },
3573     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3574     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3575   },
3576   /* REG_VEX_0FAE */
3577   {
3578     { Bad_Opcode },
3579     { Bad_Opcode },
3580     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3581     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3582   },
3583   /* REG_VEX_0F38F3 */
3584   {
3585     { Bad_Opcode },
3586     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3587     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3588     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3589   },
3590   /* REG_XOP_LWPCB */
3591   {
3592     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3593     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3594   },
3595   /* REG_XOP_LWP */
3596   {
3597     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3598     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3599   },
3600   /* REG_XOP_TBM_01 */
3601   {
3602     { Bad_Opcode },
3603     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3604     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3605     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3606     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3607     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3608     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3609     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3610   },
3611   /* REG_XOP_TBM_02 */
3612   {
3613     { Bad_Opcode },
3614     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3615     { Bad_Opcode },
3616     { Bad_Opcode },
3617     { Bad_Opcode },
3618     { Bad_Opcode },
3619     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3620   },
3621
3622 #include "i386-dis-evex-reg.h"
3623 };
3624
3625 static const struct dis386 prefix_table[][4] = {
3626   /* PREFIX_90 */
3627   {
3628     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3629     { "pause", { XX }, 0 },
3630     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3631     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3632   },
3633
3634   /* PREFIX_0F01_REG_5_MOD_0 */
3635   {
3636     { Bad_Opcode },
3637     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3638   },
3639
3640   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3641   {
3642     { Bad_Opcode },
3643     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3647   {
3648     { Bad_Opcode },
3649     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3650   },
3651
3652   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3653   {
3654     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3655     { "mcommit",        { Skip_MODRM }, 0 },
3656   },
3657
3658   /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
3659   {
3660     { "mwaitx",         { { OP_Mwait, eBX_reg } }, 0  },
3661   },
3662
3663   /* PREFIX_0F09 */
3664   {
3665     { "wbinvd",   { XX }, 0 },
3666     { "wbnoinvd", { XX }, 0 },
3667   },
3668
3669   /* PREFIX_0F10 */
3670   {
3671     { "movups", { XM, EXx }, PREFIX_OPCODE },
3672     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3673     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3674     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3675   },
3676
3677   /* PREFIX_0F11 */
3678   {
3679     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3680     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3681     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3682     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3683   },
3684
3685   /* PREFIX_0F12 */
3686   {
3687     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3688     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3689     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3690     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3691   },
3692
3693   /* PREFIX_0F16 */
3694   {
3695     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3696     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3697     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3698   },
3699
3700   /* PREFIX_0F1A */
3701   {
3702     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3703     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3704     { "bndmov", { Gbnd, Ebnd }, 0 },
3705     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3706   },
3707
3708   /* PREFIX_0F1B */
3709   {
3710     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3711     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3712     { "bndmov", { EbndS, Gbnd }, 0 },
3713     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3714   },
3715
3716   /* PREFIX_0F1C */
3717   {
3718     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3719     { "nopQ",   { Ev }, PREFIX_OPCODE },
3720     { "nopQ",   { Ev }, PREFIX_OPCODE },
3721     { "nopQ",   { Ev }, PREFIX_OPCODE },
3722   },
3723
3724   /* PREFIX_0F1E */
3725   {
3726     { "nopQ",   { Ev }, PREFIX_OPCODE },
3727     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3728     { "nopQ",   { Ev }, PREFIX_OPCODE },
3729     { "nopQ",   { Ev }, PREFIX_OPCODE },
3730   },
3731
3732   /* PREFIX_0F2A */
3733   {
3734     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3735     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3736     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3737     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3738   },
3739
3740   /* PREFIX_0F2B */
3741   {
3742     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3743     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3744     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3745     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3746   },
3747
3748   /* PREFIX_0F2C */
3749   {
3750     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3751     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3752     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3753     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3754   },
3755
3756   /* PREFIX_0F2D */
3757   {
3758     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3759     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3760     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3761     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3762   },
3763
3764   /* PREFIX_0F2E */
3765   {
3766     { "ucomiss",{ XM, EXd }, 0 },
3767     { Bad_Opcode },
3768     { "ucomisd",{ XM, EXq }, 0 },
3769   },
3770
3771   /* PREFIX_0F2F */
3772   {
3773     { "comiss", { XM, EXd }, 0 },
3774     { Bad_Opcode },
3775     { "comisd", { XM, EXq }, 0 },
3776   },
3777
3778   /* PREFIX_0F51 */
3779   {
3780     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3781     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3782     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3783     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3784   },
3785
3786   /* PREFIX_0F52 */
3787   {
3788     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3789     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3790   },
3791
3792   /* PREFIX_0F53 */
3793   {
3794     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3795     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3796   },
3797
3798   /* PREFIX_0F58 */
3799   {
3800     { "addps", { XM, EXx }, PREFIX_OPCODE },
3801     { "addss", { XM, EXd }, PREFIX_OPCODE },
3802     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3803     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3804   },
3805
3806   /* PREFIX_0F59 */
3807   {
3808     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3809     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3810     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3811     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3812   },
3813
3814   /* PREFIX_0F5A */
3815   {
3816     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3817     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3818     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3819     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3820   },
3821
3822   /* PREFIX_0F5B */
3823   {
3824     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3825     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3826     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3827   },
3828
3829   /* PREFIX_0F5C */
3830   {
3831     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3832     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3833     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3834     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3835   },
3836
3837   /* PREFIX_0F5D */
3838   {
3839     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3840     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3841     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3842     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3843   },
3844
3845   /* PREFIX_0F5E */
3846   {
3847     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3848     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3849     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3850     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3851   },
3852
3853   /* PREFIX_0F5F */
3854   {
3855     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3856     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3857     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3858     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_0F60 */
3862   {
3863     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3864     { Bad_Opcode },
3865     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3866   },
3867
3868   /* PREFIX_0F61 */
3869   {
3870     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3871     { Bad_Opcode },
3872     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3873   },
3874
3875   /* PREFIX_0F62 */
3876   {
3877     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3878     { Bad_Opcode },
3879     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3880   },
3881
3882   /* PREFIX_0F6C */
3883   {
3884     { Bad_Opcode },
3885     { Bad_Opcode },
3886     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3887   },
3888
3889   /* PREFIX_0F6D */
3890   {
3891     { Bad_Opcode },
3892     { Bad_Opcode },
3893     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3894   },
3895
3896   /* PREFIX_0F6F */
3897   {
3898     { "movq",   { MX, EM }, PREFIX_OPCODE },
3899     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3900     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0F70 */
3904   {
3905     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3906     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3907     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3908     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3909   },
3910
3911   /* PREFIX_0F73_REG_3 */
3912   {
3913     { Bad_Opcode },
3914     { Bad_Opcode },
3915     { "psrldq", { XS, Ib }, 0 },
3916   },
3917
3918   /* PREFIX_0F73_REG_7 */
3919   {
3920     { Bad_Opcode },
3921     { Bad_Opcode },
3922     { "pslldq", { XS, Ib }, 0 },
3923   },
3924
3925   /* PREFIX_0F78 */
3926   {
3927     {"vmread",  { Em, Gm }, 0 },
3928     { Bad_Opcode },
3929     {"extrq",   { XS, Ib, Ib }, 0 },
3930     {"insertq", { XM, XS, Ib, Ib }, 0 },
3931   },
3932
3933   /* PREFIX_0F79 */
3934   {
3935     {"vmwrite", { Gm, Em }, 0 },
3936     { Bad_Opcode },
3937     {"extrq",   { XM, XS }, 0 },
3938     {"insertq", { XM, XS }, 0 },
3939   },
3940
3941   /* PREFIX_0F7C */
3942   {
3943     { Bad_Opcode },
3944     { Bad_Opcode },
3945     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3946     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3947   },
3948
3949   /* PREFIX_0F7D */
3950   {
3951     { Bad_Opcode },
3952     { Bad_Opcode },
3953     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3954     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3955   },
3956
3957   /* PREFIX_0F7E */
3958   {
3959     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3960     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3961     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3962   },
3963
3964   /* PREFIX_0F7F */
3965   {
3966     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3967     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3968     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3969   },
3970
3971   /* PREFIX_0FAE_REG_0_MOD_3 */
3972   {
3973     { Bad_Opcode },
3974     { "rdfsbase", { Ev }, 0 },
3975   },
3976
3977   /* PREFIX_0FAE_REG_1_MOD_3 */
3978   {
3979     { Bad_Opcode },
3980     { "rdgsbase", { Ev }, 0 },
3981   },
3982
3983   /* PREFIX_0FAE_REG_2_MOD_3 */
3984   {
3985     { Bad_Opcode },
3986     { "wrfsbase", { Ev }, 0 },
3987   },
3988
3989   /* PREFIX_0FAE_REG_3_MOD_3 */
3990   {
3991     { Bad_Opcode },
3992     { "wrgsbase", { Ev }, 0 },
3993   },
3994
3995   /* PREFIX_0FAE_REG_4_MOD_0 */
3996   {
3997     { "xsave",  { FXSAVE }, 0 },
3998     { "ptwrite%LQ", { Edq }, 0 },
3999   },
4000
4001   /* PREFIX_0FAE_REG_4_MOD_3 */
4002   {
4003     { Bad_Opcode },
4004     { "ptwrite%LQ", { Edq }, 0 },
4005   },
4006
4007   /* PREFIX_0FAE_REG_5_MOD_0 */
4008   {
4009     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4010   },
4011
4012   /* PREFIX_0FAE_REG_5_MOD_3 */
4013   {
4014     { "lfence",         { Skip_MODRM }, 0 },
4015     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4016   },
4017
4018   /* PREFIX_0FAE_REG_6_MOD_0 */
4019   {
4020     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4021     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4022     { "clwb",   { Mb }, PREFIX_OPCODE },
4023   },
4024
4025   /* PREFIX_0FAE_REG_6_MOD_3 */
4026   {
4027     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4028     { "umonitor",       { Eva }, PREFIX_OPCODE },
4029     { "tpause", { Edq }, PREFIX_OPCODE },
4030     { "umwait", { Edq }, PREFIX_OPCODE },
4031   },
4032
4033   /* PREFIX_0FAE_REG_7_MOD_0 */
4034   {
4035     { "clflush",        { Mb }, 0 },
4036     { Bad_Opcode },
4037     { "clflushopt",     { Mb }, 0 },
4038   },
4039
4040   /* PREFIX_0FB8 */
4041   {
4042     { Bad_Opcode },
4043     { "popcntS", { Gv, Ev }, 0 },
4044   },
4045
4046   /* PREFIX_0FBC */
4047   {
4048     { "bsfS",   { Gv, Ev }, 0 },
4049     { "tzcntS", { Gv, Ev }, 0 },
4050     { "bsfS",   { Gv, Ev }, 0 },
4051   },
4052
4053   /* PREFIX_0FBD */
4054   {
4055     { "bsrS",   { Gv, Ev }, 0 },
4056     { "lzcntS", { Gv, Ev }, 0 },
4057     { "bsrS",   { Gv, Ev }, 0 },
4058   },
4059
4060   /* PREFIX_0FC2 */
4061   {
4062     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4063     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4064     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4065     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4066   },
4067
4068   /* PREFIX_0FC3_MOD_0 */
4069   {
4070     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4071   },
4072
4073   /* PREFIX_0FC7_REG_6_MOD_0 */
4074   {
4075     { "vmptrld",{ Mq }, 0 },
4076     { "vmxon",  { Mq }, 0 },
4077     { "vmclear",{ Mq }, 0 },
4078   },
4079
4080   /* PREFIX_0FC7_REG_6_MOD_3 */
4081   {
4082     { "rdrand", { Ev }, 0 },
4083     { Bad_Opcode },
4084     { "rdrand", { Ev }, 0 }
4085   },
4086
4087   /* PREFIX_0FC7_REG_7_MOD_3 */
4088   {
4089     { "rdseed", { Ev }, 0 },
4090     { "rdpid",  { Em }, 0 },
4091     { "rdseed", { Ev }, 0 },
4092   },
4093
4094   /* PREFIX_0FD0 */
4095   {
4096     { Bad_Opcode },
4097     { Bad_Opcode },
4098     { "addsubpd", { XM, EXx }, 0 },
4099     { "addsubps", { XM, EXx }, 0 },
4100   },
4101
4102   /* PREFIX_0FD6 */
4103   {
4104     { Bad_Opcode },
4105     { "movq2dq",{ XM, MS }, 0 },
4106     { "movq",   { EXqS, XM }, 0 },
4107     { "movdq2q",{ MX, XS }, 0 },
4108   },
4109
4110   /* PREFIX_0FE6 */
4111   {
4112     { Bad_Opcode },
4113     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4114     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4115     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4116   },
4117
4118   /* PREFIX_0FE7 */
4119   {
4120     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4121     { Bad_Opcode },
4122     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4123   },
4124
4125   /* PREFIX_0FF0 */
4126   {
4127     { Bad_Opcode },
4128     { Bad_Opcode },
4129     { Bad_Opcode },
4130     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4131   },
4132
4133   /* PREFIX_0FF7 */
4134   {
4135     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4136     { Bad_Opcode },
4137     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4138   },
4139
4140   /* PREFIX_0F3810 */
4141   {
4142     { Bad_Opcode },
4143     { Bad_Opcode },
4144     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4145   },
4146
4147   /* PREFIX_0F3814 */
4148   {
4149     { Bad_Opcode },
4150     { Bad_Opcode },
4151     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4152   },
4153
4154   /* PREFIX_0F3815 */
4155   {
4156     { Bad_Opcode },
4157     { Bad_Opcode },
4158     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4159   },
4160
4161   /* PREFIX_0F3817 */
4162   {
4163     { Bad_Opcode },
4164     { Bad_Opcode },
4165     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4166   },
4167
4168   /* PREFIX_0F3820 */
4169   {
4170     { Bad_Opcode },
4171     { Bad_Opcode },
4172     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4173   },
4174
4175   /* PREFIX_0F3821 */
4176   {
4177     { Bad_Opcode },
4178     { Bad_Opcode },
4179     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4180   },
4181
4182   /* PREFIX_0F3822 */
4183   {
4184     { Bad_Opcode },
4185     { Bad_Opcode },
4186     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4187   },
4188
4189   /* PREFIX_0F3823 */
4190   {
4191     { Bad_Opcode },
4192     { Bad_Opcode },
4193     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4194   },
4195
4196   /* PREFIX_0F3824 */
4197   {
4198     { Bad_Opcode },
4199     { Bad_Opcode },
4200     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4201   },
4202
4203   /* PREFIX_0F3825 */
4204   {
4205     { Bad_Opcode },
4206     { Bad_Opcode },
4207     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4208   },
4209
4210   /* PREFIX_0F3828 */
4211   {
4212     { Bad_Opcode },
4213     { Bad_Opcode },
4214     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4215   },
4216
4217   /* PREFIX_0F3829 */
4218   {
4219     { Bad_Opcode },
4220     { Bad_Opcode },
4221     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4222   },
4223
4224   /* PREFIX_0F382A */
4225   {
4226     { Bad_Opcode },
4227     { Bad_Opcode },
4228     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4229   },
4230
4231   /* PREFIX_0F382B */
4232   {
4233     { Bad_Opcode },
4234     { Bad_Opcode },
4235     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4236   },
4237
4238   /* PREFIX_0F3830 */
4239   {
4240     { Bad_Opcode },
4241     { Bad_Opcode },
4242     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4243   },
4244
4245   /* PREFIX_0F3831 */
4246   {
4247     { Bad_Opcode },
4248     { Bad_Opcode },
4249     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4250   },
4251
4252   /* PREFIX_0F3832 */
4253   {
4254     { Bad_Opcode },
4255     { Bad_Opcode },
4256     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4257   },
4258
4259   /* PREFIX_0F3833 */
4260   {
4261     { Bad_Opcode },
4262     { Bad_Opcode },
4263     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4264   },
4265
4266   /* PREFIX_0F3834 */
4267   {
4268     { Bad_Opcode },
4269     { Bad_Opcode },
4270     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4271   },
4272
4273   /* PREFIX_0F3835 */
4274   {
4275     { Bad_Opcode },
4276     { Bad_Opcode },
4277     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4278   },
4279
4280   /* PREFIX_0F3837 */
4281   {
4282     { Bad_Opcode },
4283     { Bad_Opcode },
4284     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4285   },
4286
4287   /* PREFIX_0F3838 */
4288   {
4289     { Bad_Opcode },
4290     { Bad_Opcode },
4291     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4292   },
4293
4294   /* PREFIX_0F3839 */
4295   {
4296     { Bad_Opcode },
4297     { Bad_Opcode },
4298     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4299   },
4300
4301   /* PREFIX_0F383A */
4302   {
4303     { Bad_Opcode },
4304     { Bad_Opcode },
4305     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4306   },
4307
4308   /* PREFIX_0F383B */
4309   {
4310     { Bad_Opcode },
4311     { Bad_Opcode },
4312     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4313   },
4314
4315   /* PREFIX_0F383C */
4316   {
4317     { Bad_Opcode },
4318     { Bad_Opcode },
4319     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4320   },
4321
4322   /* PREFIX_0F383D */
4323   {
4324     { Bad_Opcode },
4325     { Bad_Opcode },
4326     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4327   },
4328
4329   /* PREFIX_0F383E */
4330   {
4331     { Bad_Opcode },
4332     { Bad_Opcode },
4333     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4334   },
4335
4336   /* PREFIX_0F383F */
4337   {
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4341   },
4342
4343   /* PREFIX_0F3840 */
4344   {
4345     { Bad_Opcode },
4346     { Bad_Opcode },
4347     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3841 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3880 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3881 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3882 */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F38C8 */
4379   {
4380     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4381   },
4382
4383   /* PREFIX_0F38C9 */
4384   {
4385     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4386   },
4387
4388   /* PREFIX_0F38CA */
4389   {
4390     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4391   },
4392
4393   /* PREFIX_0F38CB */
4394   {
4395     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38CC */
4399   {
4400     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4401   },
4402
4403   /* PREFIX_0F38CD */
4404   {
4405     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4406   },
4407
4408   /* PREFIX_0F38CF */
4409   {
4410     { Bad_Opcode },
4411     { Bad_Opcode },
4412     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4413   },
4414
4415   /* PREFIX_0F38DB */
4416   {
4417     { Bad_Opcode },
4418     { Bad_Opcode },
4419     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4420   },
4421
4422   /* PREFIX_0F38DC */
4423   {
4424     { Bad_Opcode },
4425     { Bad_Opcode },
4426     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4427   },
4428
4429   /* PREFIX_0F38DD */
4430   {
4431     { Bad_Opcode },
4432     { Bad_Opcode },
4433     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4434   },
4435
4436   /* PREFIX_0F38DE */
4437   {
4438     { Bad_Opcode },
4439     { Bad_Opcode },
4440     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4441   },
4442
4443   /* PREFIX_0F38DF */
4444   {
4445     { Bad_Opcode },
4446     { Bad_Opcode },
4447     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4448   },
4449
4450   /* PREFIX_0F38F0 */
4451   {
4452     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4453     { Bad_Opcode },
4454     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4455     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4456   },
4457
4458   /* PREFIX_0F38F1 */
4459   {
4460     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4461     { Bad_Opcode },
4462     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4463     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4464   },
4465
4466   /* PREFIX_0F38F5 */
4467   {
4468     { Bad_Opcode },
4469     { Bad_Opcode },
4470     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4471   },
4472
4473   /* PREFIX_0F38F6 */
4474   {
4475     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4476     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4477     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4478     { Bad_Opcode },
4479   },
4480
4481   /* PREFIX_0F38F8 */
4482   {
4483     { Bad_Opcode },
4484     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4485     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4486     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4487   },
4488
4489   /* PREFIX_0F38F9 */
4490   {
4491     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4492   },
4493
4494   /* PREFIX_0F3A08 */
4495   {
4496     { Bad_Opcode },
4497     { Bad_Opcode },
4498     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4499   },
4500
4501   /* PREFIX_0F3A09 */
4502   {
4503     { Bad_Opcode },
4504     { Bad_Opcode },
4505     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4506   },
4507
4508   /* PREFIX_0F3A0A */
4509   {
4510     { Bad_Opcode },
4511     { Bad_Opcode },
4512     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4513   },
4514
4515   /* PREFIX_0F3A0B */
4516   {
4517     { Bad_Opcode },
4518     { Bad_Opcode },
4519     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4520   },
4521
4522   /* PREFIX_0F3A0C */
4523   {
4524     { Bad_Opcode },
4525     { Bad_Opcode },
4526     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4527   },
4528
4529   /* PREFIX_0F3A0D */
4530   {
4531     { Bad_Opcode },
4532     { Bad_Opcode },
4533     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4534   },
4535
4536   /* PREFIX_0F3A0E */
4537   {
4538     { Bad_Opcode },
4539     { Bad_Opcode },
4540     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4541   },
4542
4543   /* PREFIX_0F3A14 */
4544   {
4545     { Bad_Opcode },
4546     { Bad_Opcode },
4547     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4548   },
4549
4550   /* PREFIX_0F3A15 */
4551   {
4552     { Bad_Opcode },
4553     { Bad_Opcode },
4554     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4555   },
4556
4557   /* PREFIX_0F3A16 */
4558   {
4559     { Bad_Opcode },
4560     { Bad_Opcode },
4561     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4562   },
4563
4564   /* PREFIX_0F3A17 */
4565   {
4566     { Bad_Opcode },
4567     { Bad_Opcode },
4568     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4569   },
4570
4571   /* PREFIX_0F3A20 */
4572   {
4573     { Bad_Opcode },
4574     { Bad_Opcode },
4575     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4576   },
4577
4578   /* PREFIX_0F3A21 */
4579   {
4580     { Bad_Opcode },
4581     { Bad_Opcode },
4582     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4583   },
4584
4585   /* PREFIX_0F3A22 */
4586   {
4587     { Bad_Opcode },
4588     { Bad_Opcode },
4589     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4590   },
4591
4592   /* PREFIX_0F3A40 */
4593   {
4594     { Bad_Opcode },
4595     { Bad_Opcode },
4596     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4597   },
4598
4599   /* PREFIX_0F3A41 */
4600   {
4601     { Bad_Opcode },
4602     { Bad_Opcode },
4603     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4604   },
4605
4606   /* PREFIX_0F3A42 */
4607   {
4608     { Bad_Opcode },
4609     { Bad_Opcode },
4610     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F3A44 */
4614   {
4615     { Bad_Opcode },
4616     { Bad_Opcode },
4617     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4618   },
4619
4620   /* PREFIX_0F3A60 */
4621   {
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4625   },
4626
4627   /* PREFIX_0F3A61 */
4628   {
4629     { Bad_Opcode },
4630     { Bad_Opcode },
4631     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4632   },
4633
4634   /* PREFIX_0F3A62 */
4635   {
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4639   },
4640
4641   /* PREFIX_0F3A63 */
4642   {
4643     { Bad_Opcode },
4644     { Bad_Opcode },
4645     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4646   },
4647
4648   /* PREFIX_0F3ACC */
4649   {
4650     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F3ACE */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F3ACF */
4661   {
4662     { Bad_Opcode },
4663     { Bad_Opcode },
4664     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4665   },
4666
4667   /* PREFIX_0F3ADF */
4668   {
4669     { Bad_Opcode },
4670     { Bad_Opcode },
4671     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4672   },
4673
4674   /* PREFIX_VEX_0F10 */
4675   {
4676     { "vmovups",        { XM, EXx }, 0 },
4677     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4678     { "vmovupd",        { XM, EXx }, 0 },
4679     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4680   },
4681
4682   /* PREFIX_VEX_0F11 */
4683   {
4684     { "vmovups",        { EXxS, XM }, 0 },
4685     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4686     { "vmovupd",        { EXxS, XM }, 0 },
4687     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4688   },
4689
4690   /* PREFIX_VEX_0F12 */
4691   {
4692     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4693     { "vmovsldup",      { XM, EXx }, 0 },
4694     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4695     { "vmovddup",       { XM, EXymmq }, 0 },
4696   },
4697
4698   /* PREFIX_VEX_0F16 */
4699   {
4700     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4701     { "vmovshdup",      { XM, EXx }, 0 },
4702     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4703   },
4704
4705   /* PREFIX_VEX_0F2A */
4706   {
4707     { Bad_Opcode },
4708     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4709     { Bad_Opcode },
4710     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4711   },
4712
4713   /* PREFIX_VEX_0F2C */
4714   {
4715     { Bad_Opcode },
4716     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4717     { Bad_Opcode },
4718     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4719   },
4720
4721   /* PREFIX_VEX_0F2D */
4722   {
4723     { Bad_Opcode },
4724     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4725     { Bad_Opcode },
4726     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4727   },
4728
4729   /* PREFIX_VEX_0F2E */
4730   {
4731     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4732     { Bad_Opcode },
4733     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4734   },
4735
4736   /* PREFIX_VEX_0F2F */
4737   {
4738     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4739     { Bad_Opcode },
4740     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4741   },
4742
4743   /* PREFIX_VEX_0F41 */
4744   {
4745     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4746     { Bad_Opcode },
4747     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4748   },
4749
4750   /* PREFIX_VEX_0F42 */
4751   {
4752     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4753     { Bad_Opcode },
4754     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4755   },
4756
4757   /* PREFIX_VEX_0F44 */
4758   {
4759     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4760     { Bad_Opcode },
4761     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4762   },
4763
4764   /* PREFIX_VEX_0F45 */
4765   {
4766     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4767     { Bad_Opcode },
4768     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4769   },
4770
4771   /* PREFIX_VEX_0F46 */
4772   {
4773     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4774     { Bad_Opcode },
4775     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4776   },
4777
4778   /* PREFIX_VEX_0F47 */
4779   {
4780     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4781     { Bad_Opcode },
4782     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4783   },
4784
4785   /* PREFIX_VEX_0F4A */
4786   {
4787     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4788     { Bad_Opcode },
4789     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4790   },
4791
4792   /* PREFIX_VEX_0F4B */
4793   {
4794     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4795     { Bad_Opcode },
4796     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4797   },
4798
4799   /* PREFIX_VEX_0F51 */
4800   {
4801     { "vsqrtps",        { XM, EXx }, 0 },
4802     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4803     { "vsqrtpd",        { XM, EXx }, 0 },
4804     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4805   },
4806
4807   /* PREFIX_VEX_0F52 */
4808   {
4809     { "vrsqrtps",       { XM, EXx }, 0 },
4810     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4811   },
4812
4813   /* PREFIX_VEX_0F53 */
4814   {
4815     { "vrcpps",         { XM, EXx }, 0 },
4816     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4817   },
4818
4819   /* PREFIX_VEX_0F58 */
4820   {
4821     { "vaddps",         { XM, Vex, EXx }, 0 },
4822     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4823     { "vaddpd",         { XM, Vex, EXx }, 0 },
4824     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4825   },
4826
4827   /* PREFIX_VEX_0F59 */
4828   {
4829     { "vmulps",         { XM, Vex, EXx }, 0 },
4830     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4831     { "vmulpd",         { XM, Vex, EXx }, 0 },
4832     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4833   },
4834
4835   /* PREFIX_VEX_0F5A */
4836   {
4837     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4838     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4839     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4840     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4841   },
4842
4843   /* PREFIX_VEX_0F5B */
4844   {
4845     { "vcvtdq2ps",      { XM, EXx }, 0 },
4846     { "vcvttps2dq",     { XM, EXx }, 0 },
4847     { "vcvtps2dq",      { XM, EXx }, 0 },
4848   },
4849
4850   /* PREFIX_VEX_0F5C */
4851   {
4852     { "vsubps",         { XM, Vex, EXx }, 0 },
4853     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4854     { "vsubpd",         { XM, Vex, EXx }, 0 },
4855     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4856   },
4857
4858   /* PREFIX_VEX_0F5D */
4859   {
4860     { "vminps",         { XM, Vex, EXx }, 0 },
4861     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4862     { "vminpd",         { XM, Vex, EXx }, 0 },
4863     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4864   },
4865
4866   /* PREFIX_VEX_0F5E */
4867   {
4868     { "vdivps",         { XM, Vex, EXx }, 0 },
4869     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4870     { "vdivpd",         { XM, Vex, EXx }, 0 },
4871     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4872   },
4873
4874   /* PREFIX_VEX_0F5F */
4875   {
4876     { "vmaxps",         { XM, Vex, EXx }, 0 },
4877     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4878     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4879     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4880   },
4881
4882   /* PREFIX_VEX_0F60 */
4883   {
4884     { Bad_Opcode },
4885     { Bad_Opcode },
4886     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4887   },
4888
4889   /* PREFIX_VEX_0F61 */
4890   {
4891     { Bad_Opcode },
4892     { Bad_Opcode },
4893     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4894   },
4895
4896   /* PREFIX_VEX_0F62 */
4897   {
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4901   },
4902
4903   /* PREFIX_VEX_0F63 */
4904   {
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4908   },
4909
4910   /* PREFIX_VEX_0F64 */
4911   {
4912     { Bad_Opcode },
4913     { Bad_Opcode },
4914     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4915   },
4916
4917   /* PREFIX_VEX_0F65 */
4918   {
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4922   },
4923
4924   /* PREFIX_VEX_0F66 */
4925   {
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4929   },
4930
4931   /* PREFIX_VEX_0F67 */
4932   {
4933     { Bad_Opcode },
4934     { Bad_Opcode },
4935     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4936   },
4937
4938   /* PREFIX_VEX_0F68 */
4939   {
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4943   },
4944
4945   /* PREFIX_VEX_0F69 */
4946   {
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4950   },
4951
4952   /* PREFIX_VEX_0F6A */
4953   {
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4957   },
4958
4959   /* PREFIX_VEX_0F6B */
4960   {
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4964   },
4965
4966   /* PREFIX_VEX_0F6C */
4967   {
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4971   },
4972
4973   /* PREFIX_VEX_0F6D */
4974   {
4975     { Bad_Opcode },
4976     { Bad_Opcode },
4977     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4978   },
4979
4980   /* PREFIX_VEX_0F6E */
4981   {
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F6F */
4988   {
4989     { Bad_Opcode },
4990     { "vmovdqu",        { XM, EXx }, 0 },
4991     { "vmovdqa",        { XM, EXx }, 0 },
4992   },
4993
4994   /* PREFIX_VEX_0F70 */
4995   {
4996     { Bad_Opcode },
4997     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4998     { "vpshufd",        { XM, EXx, Ib }, 0 },
4999     { "vpshuflw",       { XM, EXx, Ib }, 0 },
5000   },
5001
5002   /* PREFIX_VEX_0F71_REG_2 */
5003   {
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     { "vpsrlw",         { Vex, XS, Ib }, 0 },
5007   },
5008
5009   /* PREFIX_VEX_0F71_REG_4 */
5010   {
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { "vpsraw",         { Vex, XS, Ib }, 0 },
5014   },
5015
5016   /* PREFIX_VEX_0F71_REG_6 */
5017   {
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { "vpsllw",         { Vex, XS, Ib }, 0 },
5021   },
5022
5023   /* PREFIX_VEX_0F72_REG_2 */
5024   {
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { "vpsrld",         { Vex, XS, Ib }, 0 },
5028   },
5029
5030   /* PREFIX_VEX_0F72_REG_4 */
5031   {
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { "vpsrad",         { Vex, XS, Ib }, 0 },
5035   },
5036
5037   /* PREFIX_VEX_0F72_REG_6 */
5038   {
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { "vpslld",         { Vex, XS, Ib }, 0 },
5042   },
5043
5044   /* PREFIX_VEX_0F73_REG_2 */
5045   {
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5049   },
5050
5051   /* PREFIX_VEX_0F73_REG_3 */
5052   {
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5056   },
5057
5058   /* PREFIX_VEX_0F73_REG_6 */
5059   {
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { "vpsllq",         { Vex, XS, Ib }, 0 },
5063   },
5064
5065   /* PREFIX_VEX_0F73_REG_7 */
5066   {
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { "vpslldq",        { Vex, XS, Ib }, 0 },
5070   },
5071
5072   /* PREFIX_VEX_0F74 */
5073   {
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5077   },
5078
5079   /* PREFIX_VEX_0F75 */
5080   {
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5084   },
5085
5086   /* PREFIX_VEX_0F76 */
5087   {
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5091   },
5092
5093   /* PREFIX_VEX_0F77 */
5094   {
5095     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5096   },
5097
5098   /* PREFIX_VEX_0F7C */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5103     { "vhaddps",        { XM, Vex, EXx }, 0 },
5104   },
5105
5106   /* PREFIX_VEX_0F7D */
5107   {
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5111     { "vhsubps",        { XM, Vex, EXx }, 0 },
5112   },
5113
5114   /* PREFIX_VEX_0F7E */
5115   {
5116     { Bad_Opcode },
5117     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5118     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5119   },
5120
5121   /* PREFIX_VEX_0F7F */
5122   {
5123     { Bad_Opcode },
5124     { "vmovdqu",        { EXxS, XM }, 0 },
5125     { "vmovdqa",        { EXxS, XM }, 0 },
5126   },
5127
5128   /* PREFIX_VEX_0F90 */
5129   {
5130     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5131     { Bad_Opcode },
5132     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5133   },
5134
5135   /* PREFIX_VEX_0F91 */
5136   {
5137     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5138     { Bad_Opcode },
5139     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5140   },
5141
5142   /* PREFIX_VEX_0F92 */
5143   {
5144     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5145     { Bad_Opcode },
5146     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5147     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5148   },
5149
5150   /* PREFIX_VEX_0F93 */
5151   {
5152     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5153     { Bad_Opcode },
5154     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5155     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5156   },
5157
5158   /* PREFIX_VEX_0F98 */
5159   {
5160     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5161     { Bad_Opcode },
5162     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5163   },
5164
5165   /* PREFIX_VEX_0F99 */
5166   {
5167     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5168     { Bad_Opcode },
5169     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5170   },
5171
5172   /* PREFIX_VEX_0FC2 */
5173   {
5174     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5175     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5176     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5177     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5178   },
5179
5180   /* PREFIX_VEX_0FC4 */
5181   {
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5185   },
5186
5187   /* PREFIX_VEX_0FC5 */
5188   {
5189     { Bad_Opcode },
5190     { Bad_Opcode },
5191     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5192   },
5193
5194   /* PREFIX_VEX_0FD0 */
5195   {
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5199     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5200   },
5201
5202   /* PREFIX_VEX_0FD1 */
5203   {
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5207   },
5208
5209   /* PREFIX_VEX_0FD2 */
5210   {
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5214   },
5215
5216   /* PREFIX_VEX_0FD3 */
5217   {
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5221   },
5222
5223   /* PREFIX_VEX_0FD4 */
5224   {
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { "vpaddq",         { XM, Vex, EXx }, 0 },
5228   },
5229
5230   /* PREFIX_VEX_0FD5 */
5231   {
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { "vpmullw",        { XM, Vex, EXx }, 0 },
5235   },
5236
5237   /* PREFIX_VEX_0FD6 */
5238   {
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5242   },
5243
5244   /* PREFIX_VEX_0FD7 */
5245   {
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5249   },
5250
5251   /* PREFIX_VEX_0FD8 */
5252   {
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5256   },
5257
5258   /* PREFIX_VEX_0FD9 */
5259   {
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5263   },
5264
5265   /* PREFIX_VEX_0FDA */
5266   {
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { "vpminub",        { XM, Vex, EXx }, 0 },
5270   },
5271
5272   /* PREFIX_VEX_0FDB */
5273   {
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { "vpand",          { XM, Vex, EXx }, 0 },
5277   },
5278
5279   /* PREFIX_VEX_0FDC */
5280   {
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5284   },
5285
5286   /* PREFIX_VEX_0FDD */
5287   {
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5291   },
5292
5293   /* PREFIX_VEX_0FDE */
5294   {
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5298   },
5299
5300   /* PREFIX_VEX_0FDF */
5301   {
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { "vpandn",         { XM, Vex, EXx }, 0 },
5305   },
5306
5307   /* PREFIX_VEX_0FE0 */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { "vpavgb",         { XM, Vex, EXx }, 0 },
5312   },
5313
5314   /* PREFIX_VEX_0FE1 */
5315   {
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5319   },
5320
5321   /* PREFIX_VEX_0FE2 */
5322   {
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5326   },
5327
5328   /* PREFIX_VEX_0FE3 */
5329   {
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { "vpavgw",         { XM, Vex, EXx }, 0 },
5333   },
5334
5335   /* PREFIX_VEX_0FE4 */
5336   {
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5340   },
5341
5342   /* PREFIX_VEX_0FE5 */
5343   {
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5347   },
5348
5349   /* PREFIX_VEX_0FE6 */
5350   {
5351     { Bad_Opcode },
5352     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5353     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5354     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5355   },
5356
5357   /* PREFIX_VEX_0FE7 */
5358   {
5359     { Bad_Opcode },
5360     { Bad_Opcode },
5361     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5362   },
5363
5364   /* PREFIX_VEX_0FE8 */
5365   {
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5369   },
5370
5371   /* PREFIX_VEX_0FE9 */
5372   {
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5376   },
5377
5378   /* PREFIX_VEX_0FEA */
5379   {
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { "vpminsw",        { XM, Vex, EXx }, 0 },
5383   },
5384
5385   /* PREFIX_VEX_0FEB */
5386   {
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { "vpor",           { XM, Vex, EXx }, 0 },
5390   },
5391
5392   /* PREFIX_VEX_0FEC */
5393   {
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5397   },
5398
5399   /* PREFIX_VEX_0FED */
5400   {
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5404   },
5405
5406   /* PREFIX_VEX_0FEE */
5407   {
5408     { Bad_Opcode },
5409     { Bad_Opcode },
5410     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5411   },
5412
5413   /* PREFIX_VEX_0FEF */
5414   {
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { "vpxor",          { XM, Vex, EXx }, 0 },
5418   },
5419
5420   /* PREFIX_VEX_0FF0 */
5421   {
5422     { Bad_Opcode },
5423     { Bad_Opcode },
5424     { Bad_Opcode },
5425     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5426   },
5427
5428   /* PREFIX_VEX_0FF1 */
5429   {
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5433   },
5434
5435   /* PREFIX_VEX_0FF2 */
5436   {
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5440   },
5441
5442   /* PREFIX_VEX_0FF3 */
5443   {
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5447   },
5448
5449   /* PREFIX_VEX_0FF4 */
5450   {
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5454   },
5455
5456   /* PREFIX_VEX_0FF5 */
5457   {
5458     { Bad_Opcode },
5459     { Bad_Opcode },
5460     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5461   },
5462
5463   /* PREFIX_VEX_0FF6 */
5464   {
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5468   },
5469
5470   /* PREFIX_VEX_0FF7 */
5471   {
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5475   },
5476
5477   /* PREFIX_VEX_0FF8 */
5478   {
5479     { Bad_Opcode },
5480     { Bad_Opcode },
5481     { "vpsubb",         { XM, Vex, EXx }, 0 },
5482   },
5483
5484   /* PREFIX_VEX_0FF9 */
5485   {
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { "vpsubw",         { XM, Vex, EXx }, 0 },
5489   },
5490
5491   /* PREFIX_VEX_0FFA */
5492   {
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { "vpsubd",         { XM, Vex, EXx }, 0 },
5496   },
5497
5498   /* PREFIX_VEX_0FFB */
5499   {
5500     { Bad_Opcode },
5501     { Bad_Opcode },
5502     { "vpsubq",         { XM, Vex, EXx }, 0 },
5503   },
5504
5505   /* PREFIX_VEX_0FFC */
5506   {
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { "vpaddb",         { XM, Vex, EXx }, 0 },
5510   },
5511
5512   /* PREFIX_VEX_0FFD */
5513   {
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { "vpaddw",         { XM, Vex, EXx }, 0 },
5517   },
5518
5519   /* PREFIX_VEX_0FFE */
5520   {
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { "vpaddd",         { XM, Vex, EXx }, 0 },
5524   },
5525
5526   /* PREFIX_VEX_0F3800 */
5527   {
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { "vpshufb",        { XM, Vex, EXx }, 0 },
5531   },
5532
5533   /* PREFIX_VEX_0F3801 */
5534   {
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { "vphaddw",        { XM, Vex, EXx }, 0 },
5538   },
5539
5540   /* PREFIX_VEX_0F3802 */
5541   {
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { "vphaddd",        { XM, Vex, EXx }, 0 },
5545   },
5546
5547   /* PREFIX_VEX_0F3803 */
5548   {
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5552   },
5553
5554   /* PREFIX_VEX_0F3804 */
5555   {
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5559   },
5560
5561   /* PREFIX_VEX_0F3805 */
5562   {
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { "vphsubw",        { XM, Vex, EXx }, 0 },
5566   },
5567
5568   /* PREFIX_VEX_0F3806 */
5569   {
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { "vphsubd",        { XM, Vex, EXx }, 0 },
5573   },
5574
5575   /* PREFIX_VEX_0F3807 */
5576   {
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5580   },
5581
5582   /* PREFIX_VEX_0F3808 */
5583   {
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { "vpsignb",        { XM, Vex, EXx }, 0 },
5587   },
5588
5589   /* PREFIX_VEX_0F3809 */
5590   {
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { "vpsignw",        { XM, Vex, EXx }, 0 },
5594   },
5595
5596   /* PREFIX_VEX_0F380A */
5597   {
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { "vpsignd",        { XM, Vex, EXx }, 0 },
5601   },
5602
5603   /* PREFIX_VEX_0F380B */
5604   {
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5608   },
5609
5610   /* PREFIX_VEX_0F380C */
5611   {
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5615   },
5616
5617   /* PREFIX_VEX_0F380D */
5618   {
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5622   },
5623
5624   /* PREFIX_VEX_0F380E */
5625   {
5626     { Bad_Opcode },
5627     { Bad_Opcode },
5628     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5629   },
5630
5631   /* PREFIX_VEX_0F380F */
5632   {
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5636   },
5637
5638   /* PREFIX_VEX_0F3813 */
5639   {
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5643   },
5644
5645   /* PREFIX_VEX_0F3816 */
5646   {
5647     { Bad_Opcode },
5648     { Bad_Opcode },
5649     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5650   },
5651
5652   /* PREFIX_VEX_0F3817 */
5653   {
5654     { Bad_Opcode },
5655     { Bad_Opcode },
5656     { "vptest",         { XM, EXx }, 0 },
5657   },
5658
5659   /* PREFIX_VEX_0F3818 */
5660   {
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5664   },
5665
5666   /* PREFIX_VEX_0F3819 */
5667   {
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5671   },
5672
5673   /* PREFIX_VEX_0F381A */
5674   {
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5678   },
5679
5680   /* PREFIX_VEX_0F381C */
5681   {
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { "vpabsb",         { XM, EXx }, 0 },
5685   },
5686
5687   /* PREFIX_VEX_0F381D */
5688   {
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { "vpabsw",         { XM, EXx }, 0 },
5692   },
5693
5694   /* PREFIX_VEX_0F381E */
5695   {
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { "vpabsd",         { XM, EXx }, 0 },
5699   },
5700
5701   /* PREFIX_VEX_0F3820 */
5702   {
5703     { Bad_Opcode },
5704     { Bad_Opcode },
5705     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5706   },
5707
5708   /* PREFIX_VEX_0F3821 */
5709   {
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5713   },
5714
5715   /* PREFIX_VEX_0F3822 */
5716   {
5717     { Bad_Opcode },
5718     { Bad_Opcode },
5719     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5720   },
5721
5722   /* PREFIX_VEX_0F3823 */
5723   {
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5727   },
5728
5729   /* PREFIX_VEX_0F3824 */
5730   {
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5734   },
5735
5736   /* PREFIX_VEX_0F3825 */
5737   {
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5741   },
5742
5743   /* PREFIX_VEX_0F3828 */
5744   {
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5748   },
5749
5750   /* PREFIX_VEX_0F3829 */
5751   {
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5755   },
5756
5757   /* PREFIX_VEX_0F382A */
5758   {
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5762   },
5763
5764   /* PREFIX_VEX_0F382B */
5765   {
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5769   },
5770
5771   /* PREFIX_VEX_0F382C */
5772   {
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5776   },
5777
5778   /* PREFIX_VEX_0F382D */
5779   {
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5783   },
5784
5785   /* PREFIX_VEX_0F382E */
5786   {
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5790   },
5791
5792   /* PREFIX_VEX_0F382F */
5793   {
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5797   },
5798
5799   /* PREFIX_VEX_0F3830 */
5800   {
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5804   },
5805
5806   /* PREFIX_VEX_0F3831 */
5807   {
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5811   },
5812
5813   /* PREFIX_VEX_0F3832 */
5814   {
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5818   },
5819
5820   /* PREFIX_VEX_0F3833 */
5821   {
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5825   },
5826
5827   /* PREFIX_VEX_0F3834 */
5828   {
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5832   },
5833
5834   /* PREFIX_VEX_0F3835 */
5835   {
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5839   },
5840
5841   /* PREFIX_VEX_0F3836 */
5842   {
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5846   },
5847
5848   /* PREFIX_VEX_0F3837 */
5849   {
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5853   },
5854
5855   /* PREFIX_VEX_0F3838 */
5856   {
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { "vpminsb",        { XM, Vex, EXx }, 0 },
5860   },
5861
5862   /* PREFIX_VEX_0F3839 */
5863   {
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { "vpminsd",        { XM, Vex, EXx }, 0 },
5867   },
5868
5869   /* PREFIX_VEX_0F383A */
5870   {
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { "vpminuw",        { XM, Vex, EXx }, 0 },
5874   },
5875
5876   /* PREFIX_VEX_0F383B */
5877   {
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { "vpminud",        { XM, Vex, EXx }, 0 },
5881   },
5882
5883   /* PREFIX_VEX_0F383C */
5884   {
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5888   },
5889
5890   /* PREFIX_VEX_0F383D */
5891   {
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5895   },
5896
5897   /* PREFIX_VEX_0F383E */
5898   {
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5902   },
5903
5904   /* PREFIX_VEX_0F383F */
5905   {
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5909   },
5910
5911   /* PREFIX_VEX_0F3840 */
5912   {
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { "vpmulld",        { XM, Vex, EXx }, 0 },
5916   },
5917
5918   /* PREFIX_VEX_0F3841 */
5919   {
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5923   },
5924
5925   /* PREFIX_VEX_0F3845 */
5926   {
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5930   },
5931
5932   /* PREFIX_VEX_0F3846 */
5933   {
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5937   },
5938
5939   /* PREFIX_VEX_0F3847 */
5940   {
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5944   },
5945
5946   /* PREFIX_VEX_0F3858 */
5947   {
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5951   },
5952
5953   /* PREFIX_VEX_0F3859 */
5954   {
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5958   },
5959
5960   /* PREFIX_VEX_0F385A */
5961   {
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5965   },
5966
5967   /* PREFIX_VEX_0F3878 */
5968   {
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5972   },
5973
5974   /* PREFIX_VEX_0F3879 */
5975   {
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5979   },
5980
5981   /* PREFIX_VEX_0F388C */
5982   {
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5986   },
5987
5988   /* PREFIX_VEX_0F388E */
5989   {
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5993   },
5994
5995   /* PREFIX_VEX_0F3890 */
5996   {
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6000   },
6001
6002   /* PREFIX_VEX_0F3891 */
6003   {
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6007   },
6008
6009   /* PREFIX_VEX_0F3892 */
6010   {
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6014   },
6015
6016   /* PREFIX_VEX_0F3893 */
6017   {
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6021   },
6022
6023   /* PREFIX_VEX_0F3896 */
6024   {
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6028   },
6029
6030   /* PREFIX_VEX_0F3897 */
6031   {
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6035   },
6036
6037   /* PREFIX_VEX_0F3898 */
6038   {
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6042   },
6043
6044   /* PREFIX_VEX_0F3899 */
6045   {
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6049   },
6050
6051   /* PREFIX_VEX_0F389A */
6052   {
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6056   },
6057
6058   /* PREFIX_VEX_0F389B */
6059   {
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6063   },
6064
6065   /* PREFIX_VEX_0F389C */
6066   {
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6070   },
6071
6072   /* PREFIX_VEX_0F389D */
6073   {
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6077   },
6078
6079   /* PREFIX_VEX_0F389E */
6080   {
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6084   },
6085
6086   /* PREFIX_VEX_0F389F */
6087   {
6088     { Bad_Opcode },
6089     { Bad_Opcode },
6090     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6091   },
6092
6093   /* PREFIX_VEX_0F38A6 */
6094   {
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6098     { Bad_Opcode },
6099   },
6100
6101   /* PREFIX_VEX_0F38A7 */
6102   {
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6106   },
6107
6108   /* PREFIX_VEX_0F38A8 */
6109   {
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6113   },
6114
6115   /* PREFIX_VEX_0F38A9 */
6116   {
6117     { Bad_Opcode },
6118     { Bad_Opcode },
6119     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6120   },
6121
6122   /* PREFIX_VEX_0F38AA */
6123   {
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6127   },
6128
6129   /* PREFIX_VEX_0F38AB */
6130   {
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6134   },
6135
6136   /* PREFIX_VEX_0F38AC */
6137   {
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6141   },
6142
6143   /* PREFIX_VEX_0F38AD */
6144   {
6145     { Bad_Opcode },
6146     { Bad_Opcode },
6147     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6148   },
6149
6150   /* PREFIX_VEX_0F38AE */
6151   {
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6155   },
6156
6157   /* PREFIX_VEX_0F38AF */
6158   {
6159     { Bad_Opcode },
6160     { Bad_Opcode },
6161     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6162   },
6163
6164   /* PREFIX_VEX_0F38B6 */
6165   {
6166     { Bad_Opcode },
6167     { Bad_Opcode },
6168     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6169   },
6170
6171   /* PREFIX_VEX_0F38B7 */
6172   {
6173     { Bad_Opcode },
6174     { Bad_Opcode },
6175     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6176   },
6177
6178   /* PREFIX_VEX_0F38B8 */
6179   {
6180     { Bad_Opcode },
6181     { Bad_Opcode },
6182     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6183   },
6184
6185   /* PREFIX_VEX_0F38B9 */
6186   {
6187     { Bad_Opcode },
6188     { Bad_Opcode },
6189     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6190   },
6191
6192   /* PREFIX_VEX_0F38BA */
6193   {
6194     { Bad_Opcode },
6195     { Bad_Opcode },
6196     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6197   },
6198
6199   /* PREFIX_VEX_0F38BB */
6200   {
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6204   },
6205
6206   /* PREFIX_VEX_0F38BC */
6207   {
6208     { Bad_Opcode },
6209     { Bad_Opcode },
6210     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6211   },
6212
6213   /* PREFIX_VEX_0F38BD */
6214   {
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6218   },
6219
6220   /* PREFIX_VEX_0F38BE */
6221   {
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6225   },
6226
6227   /* PREFIX_VEX_0F38BF */
6228   {
6229     { Bad_Opcode },
6230     { Bad_Opcode },
6231     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6232   },
6233
6234   /* PREFIX_VEX_0F38CF */
6235   {
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6239   },
6240
6241   /* PREFIX_VEX_0F38DB */
6242   {
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6246   },
6247
6248   /* PREFIX_VEX_0F38DC */
6249   {
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { "vaesenc",        { XM, Vex, EXx }, 0 },
6253   },
6254
6255   /* PREFIX_VEX_0F38DD */
6256   {
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6260   },
6261
6262   /* PREFIX_VEX_0F38DE */
6263   {
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { "vaesdec",        { XM, Vex, EXx }, 0 },
6267   },
6268
6269   /* PREFIX_VEX_0F38DF */
6270   {
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6274   },
6275
6276   /* PREFIX_VEX_0F38F2 */
6277   {
6278     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6279   },
6280
6281   /* PREFIX_VEX_0F38F3_REG_1 */
6282   {
6283     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6284   },
6285
6286   /* PREFIX_VEX_0F38F3_REG_2 */
6287   {
6288     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6289   },
6290
6291   /* PREFIX_VEX_0F38F3_REG_3 */
6292   {
6293     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6294   },
6295
6296   /* PREFIX_VEX_0F38F5 */
6297   {
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6300     { Bad_Opcode },
6301     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6302   },
6303
6304   /* PREFIX_VEX_0F38F6 */
6305   {
6306     { Bad_Opcode },
6307     { Bad_Opcode },
6308     { Bad_Opcode },
6309     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6310   },
6311
6312   /* PREFIX_VEX_0F38F7 */
6313   {
6314     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6315     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6316     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6317     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6318   },
6319
6320   /* PREFIX_VEX_0F3A00 */
6321   {
6322     { Bad_Opcode },
6323     { Bad_Opcode },
6324     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6325   },
6326
6327   /* PREFIX_VEX_0F3A01 */
6328   {
6329     { Bad_Opcode },
6330     { Bad_Opcode },
6331     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6332   },
6333
6334   /* PREFIX_VEX_0F3A02 */
6335   {
6336     { Bad_Opcode },
6337     { Bad_Opcode },
6338     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6339   },
6340
6341   /* PREFIX_VEX_0F3A04 */
6342   {
6343     { Bad_Opcode },
6344     { Bad_Opcode },
6345     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6346   },
6347
6348   /* PREFIX_VEX_0F3A05 */
6349   {
6350     { Bad_Opcode },
6351     { Bad_Opcode },
6352     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6353   },
6354
6355   /* PREFIX_VEX_0F3A06 */
6356   {
6357     { Bad_Opcode },
6358     { Bad_Opcode },
6359     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6360   },
6361
6362   /* PREFIX_VEX_0F3A08 */
6363   {
6364     { Bad_Opcode },
6365     { Bad_Opcode },
6366     { "vroundps",       { XM, EXx, Ib }, 0 },
6367   },
6368
6369   /* PREFIX_VEX_0F3A09 */
6370   {
6371     { Bad_Opcode },
6372     { Bad_Opcode },
6373     { "vroundpd",       { XM, EXx, Ib }, 0 },
6374   },
6375
6376   /* PREFIX_VEX_0F3A0A */
6377   {
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6381   },
6382
6383   /* PREFIX_VEX_0F3A0B */
6384   {
6385     { Bad_Opcode },
6386     { Bad_Opcode },
6387     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6388   },
6389
6390   /* PREFIX_VEX_0F3A0C */
6391   {
6392     { Bad_Opcode },
6393     { Bad_Opcode },
6394     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6395   },
6396
6397   /* PREFIX_VEX_0F3A0D */
6398   {
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6402   },
6403
6404   /* PREFIX_VEX_0F3A0E */
6405   {
6406     { Bad_Opcode },
6407     { Bad_Opcode },
6408     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6409   },
6410
6411   /* PREFIX_VEX_0F3A0F */
6412   {
6413     { Bad_Opcode },
6414     { Bad_Opcode },
6415     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6416   },
6417
6418   /* PREFIX_VEX_0F3A14 */
6419   {
6420     { Bad_Opcode },
6421     { Bad_Opcode },
6422     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6423   },
6424
6425   /* PREFIX_VEX_0F3A15 */
6426   {
6427     { Bad_Opcode },
6428     { Bad_Opcode },
6429     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6430   },
6431
6432   /* PREFIX_VEX_0F3A16 */
6433   {
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6437   },
6438
6439   /* PREFIX_VEX_0F3A17 */
6440   {
6441     { Bad_Opcode },
6442     { Bad_Opcode },
6443     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6444   },
6445
6446   /* PREFIX_VEX_0F3A18 */
6447   {
6448     { Bad_Opcode },
6449     { Bad_Opcode },
6450     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6451   },
6452
6453   /* PREFIX_VEX_0F3A19 */
6454   {
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6458   },
6459
6460   /* PREFIX_VEX_0F3A1D */
6461   {
6462     { Bad_Opcode },
6463     { Bad_Opcode },
6464     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6465   },
6466
6467   /* PREFIX_VEX_0F3A20 */
6468   {
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6472   },
6473
6474   /* PREFIX_VEX_0F3A21 */
6475   {
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6479   },
6480
6481   /* PREFIX_VEX_0F3A22 */
6482   {
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6486   },
6487
6488   /* PREFIX_VEX_0F3A30 */
6489   {
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6493   },
6494
6495   /* PREFIX_VEX_0F3A31 */
6496   {
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6500   },
6501
6502   /* PREFIX_VEX_0F3A32 */
6503   {
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6507   },
6508
6509   /* PREFIX_VEX_0F3A33 */
6510   {
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6514   },
6515
6516   /* PREFIX_VEX_0F3A38 */
6517   {
6518     { Bad_Opcode },
6519     { Bad_Opcode },
6520     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6521   },
6522
6523   /* PREFIX_VEX_0F3A39 */
6524   {
6525     { Bad_Opcode },
6526     { Bad_Opcode },
6527     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6528   },
6529
6530   /* PREFIX_VEX_0F3A40 */
6531   {
6532     { Bad_Opcode },
6533     { Bad_Opcode },
6534     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6535   },
6536
6537   /* PREFIX_VEX_0F3A41 */
6538   {
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6542   },
6543
6544   /* PREFIX_VEX_0F3A42 */
6545   {
6546     { Bad_Opcode },
6547     { Bad_Opcode },
6548     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6549   },
6550
6551   /* PREFIX_VEX_0F3A44 */
6552   {
6553     { Bad_Opcode },
6554     { Bad_Opcode },
6555     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6556   },
6557
6558   /* PREFIX_VEX_0F3A46 */
6559   {
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6563   },
6564
6565   /* PREFIX_VEX_0F3A48 */
6566   {
6567     { Bad_Opcode },
6568     { Bad_Opcode },
6569     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6570   },
6571
6572   /* PREFIX_VEX_0F3A49 */
6573   {
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6577   },
6578
6579   /* PREFIX_VEX_0F3A4A */
6580   {
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6584   },
6585
6586   /* PREFIX_VEX_0F3A4B */
6587   {
6588     { Bad_Opcode },
6589     { Bad_Opcode },
6590     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6591   },
6592
6593   /* PREFIX_VEX_0F3A4C */
6594   {
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6598   },
6599
6600   /* PREFIX_VEX_0F3A5C */
6601   {
6602     { Bad_Opcode },
6603     { Bad_Opcode },
6604     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6605   },
6606
6607   /* PREFIX_VEX_0F3A5D */
6608   {
6609     { Bad_Opcode },
6610     { Bad_Opcode },
6611     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6612   },
6613
6614   /* PREFIX_VEX_0F3A5E */
6615   {
6616     { Bad_Opcode },
6617     { Bad_Opcode },
6618     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6619   },
6620
6621   /* PREFIX_VEX_0F3A5F */
6622   {
6623     { Bad_Opcode },
6624     { Bad_Opcode },
6625     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6626   },
6627
6628   /* PREFIX_VEX_0F3A60 */
6629   {
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6633     { Bad_Opcode },
6634   },
6635
6636   /* PREFIX_VEX_0F3A61 */
6637   {
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6641   },
6642
6643   /* PREFIX_VEX_0F3A62 */
6644   {
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6648   },
6649
6650   /* PREFIX_VEX_0F3A63 */
6651   {
6652     { Bad_Opcode },
6653     { Bad_Opcode },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6655   },
6656
6657   /* PREFIX_VEX_0F3A68 */
6658   {
6659     { Bad_Opcode },
6660     { Bad_Opcode },
6661     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6662   },
6663
6664   /* PREFIX_VEX_0F3A69 */
6665   {
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6669   },
6670
6671   /* PREFIX_VEX_0F3A6A */
6672   {
6673     { Bad_Opcode },
6674     { Bad_Opcode },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6676   },
6677
6678   /* PREFIX_VEX_0F3A6B */
6679   {
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6683   },
6684
6685   /* PREFIX_VEX_0F3A6C */
6686   {
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6690   },
6691
6692   /* PREFIX_VEX_0F3A6D */
6693   {
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6697   },
6698
6699   /* PREFIX_VEX_0F3A6E */
6700   {
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6704   },
6705
6706   /* PREFIX_VEX_0F3A6F */
6707   {
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6711   },
6712
6713   /* PREFIX_VEX_0F3A78 */
6714   {
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6718   },
6719
6720   /* PREFIX_VEX_0F3A79 */
6721   {
6722     { Bad_Opcode },
6723     { Bad_Opcode },
6724     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6725   },
6726
6727   /* PREFIX_VEX_0F3A7A */
6728   {
6729     { Bad_Opcode },
6730     { Bad_Opcode },
6731     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6732   },
6733
6734   /* PREFIX_VEX_0F3A7B */
6735   {
6736     { Bad_Opcode },
6737     { Bad_Opcode },
6738     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6739   },
6740
6741   /* PREFIX_VEX_0F3A7C */
6742   {
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6746     { Bad_Opcode },
6747   },
6748
6749   /* PREFIX_VEX_0F3A7D */
6750   {
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6754   },
6755
6756   /* PREFIX_VEX_0F3A7E */
6757   {
6758     { Bad_Opcode },
6759     { Bad_Opcode },
6760     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6761   },
6762
6763   /* PREFIX_VEX_0F3A7F */
6764   {
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6768   },
6769
6770   /* PREFIX_VEX_0F3ACE */
6771   {
6772     { Bad_Opcode },
6773     { Bad_Opcode },
6774     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6775   },
6776
6777   /* PREFIX_VEX_0F3ACF */
6778   {
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6782   },
6783
6784   /* PREFIX_VEX_0F3ADF */
6785   {
6786     { Bad_Opcode },
6787     { Bad_Opcode },
6788     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6789   },
6790
6791   /* PREFIX_VEX_0F3AF0 */
6792   {
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6797   },
6798
6799 #include "i386-dis-evex-prefix.h"
6800 };
6801
6802 static const struct dis386 x86_64_table[][2] = {
6803   /* X86_64_06 */
6804   {
6805     { "pushP", { es }, 0 },
6806   },
6807
6808   /* X86_64_07 */
6809   {
6810     { "popP", { es }, 0 },
6811   },
6812
6813   /* X86_64_0D */
6814   {
6815     { "pushP", { cs }, 0 },
6816   },
6817
6818   /* X86_64_16 */
6819   {
6820     { "pushP", { ss }, 0 },
6821   },
6822
6823   /* X86_64_17 */
6824   {
6825     { "popP", { ss }, 0 },
6826   },
6827
6828   /* X86_64_1E */
6829   {
6830     { "pushP", { ds }, 0 },
6831   },
6832
6833   /* X86_64_1F */
6834   {
6835     { "popP", { ds }, 0 },
6836   },
6837
6838   /* X86_64_27 */
6839   {
6840     { "daa", { XX }, 0 },
6841   },
6842
6843   /* X86_64_2F */
6844   {
6845     { "das", { XX }, 0 },
6846   },
6847
6848   /* X86_64_37 */
6849   {
6850     { "aaa", { XX }, 0 },
6851   },
6852
6853   /* X86_64_3F */
6854   {
6855     { "aas", { XX }, 0 },
6856   },
6857
6858   /* X86_64_60 */
6859   {
6860     { "pushaP", { XX }, 0 },
6861   },
6862
6863   /* X86_64_61 */
6864   {
6865     { "popaP", { XX }, 0 },
6866   },
6867
6868   /* X86_64_62 */
6869   {
6870     { MOD_TABLE (MOD_62_32BIT) },
6871     { EVEX_TABLE (EVEX_0F) },
6872   },
6873
6874   /* X86_64_63 */
6875   {
6876     { "arpl", { Ew, Gw }, 0 },
6877     { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
6878   },
6879
6880   /* X86_64_6D */
6881   {
6882     { "ins{R|}", { Yzr, indirDX }, 0 },
6883     { "ins{G|}", { Yzr, indirDX }, 0 },
6884   },
6885
6886   /* X86_64_6F */
6887   {
6888     { "outs{R|}", { indirDXr, Xz }, 0 },
6889     { "outs{G|}", { indirDXr, Xz }, 0 },
6890   },
6891
6892   /* X86_64_82 */
6893   {
6894     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6895     { REG_TABLE (REG_80) },
6896   },
6897
6898   /* X86_64_9A */
6899   {
6900     { "Jcall{T|}", { Ap }, 0 },
6901   },
6902
6903   /* X86_64_C2 */
6904   {
6905     { "retP",           { Iw, BND }, 0 },
6906     { "ret@",           { Iw, BND }, 0 },
6907   },
6908
6909   /* X86_64_C3 */
6910   {
6911     { "retP",           { BND }, 0 },
6912     { "ret@",           { BND }, 0 },
6913   },
6914
6915   /* X86_64_C4 */
6916   {
6917     { MOD_TABLE (MOD_C4_32BIT) },
6918     { VEX_C4_TABLE (VEX_0F) },
6919   },
6920
6921   /* X86_64_C5 */
6922   {
6923     { MOD_TABLE (MOD_C5_32BIT) },
6924     { VEX_C5_TABLE (VEX_0F) },
6925   },
6926
6927   /* X86_64_CE */
6928   {
6929     { "into", { XX }, 0 },
6930   },
6931
6932   /* X86_64_D4 */
6933   {
6934     { "aam", { Ib }, 0 },
6935   },
6936
6937   /* X86_64_D5 */
6938   {
6939     { "aad", { Ib }, 0 },
6940   },
6941
6942   /* X86_64_E8 */
6943   {
6944     { "callP",          { Jv, BND }, 0 },
6945     { "call@",          { Jv, BND }, 0 }
6946   },
6947
6948   /* X86_64_E9 */
6949   {
6950     { "jmpP",           { Jv, BND }, 0 },
6951     { "jmp@",           { Jv, BND }, 0 }
6952   },
6953
6954   /* X86_64_EA */
6955   {
6956     { "Jjmp{T|}", { Ap }, 0 },
6957   },
6958
6959   /* X86_64_0F01_REG_0 */
6960   {
6961     { "sgdt{Q|IQ}", { M }, 0 },
6962     { "sgdt", { M }, 0 },
6963   },
6964
6965   /* X86_64_0F01_REG_1 */
6966   {
6967     { "sidt{Q|IQ}", { M }, 0 },
6968     { "sidt", { M }, 0 },
6969   },
6970
6971   /* X86_64_0F01_REG_2 */
6972   {
6973     { "lgdt{Q|Q}", { M }, 0 },
6974     { "lgdt", { M }, 0 },
6975   },
6976
6977   /* X86_64_0F01_REG_3 */
6978   {
6979     { "lidt{Q|Q}", { M }, 0 },
6980     { "lidt", { M }, 0 },
6981   },
6982 };
6983
6984 static const struct dis386 three_byte_table[][256] = {
6985
6986   /* THREE_BYTE_0F38 */
6987   {
6988     /* 00 */
6989     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6990     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6991     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6992     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6993     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6994     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6995     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6996     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6997     /* 08 */
6998     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6999     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7000     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7001     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { Bad_Opcode },
7006     /* 10 */
7007     { PREFIX_TABLE (PREFIX_0F3810) },
7008     { Bad_Opcode },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { PREFIX_TABLE (PREFIX_0F3814) },
7012     { PREFIX_TABLE (PREFIX_0F3815) },
7013     { Bad_Opcode },
7014     { PREFIX_TABLE (PREFIX_0F3817) },
7015     /* 18 */
7016     { Bad_Opcode },
7017     { Bad_Opcode },
7018     { Bad_Opcode },
7019     { Bad_Opcode },
7020     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7021     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7022     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7023     { Bad_Opcode },
7024     /* 20 */
7025     { PREFIX_TABLE (PREFIX_0F3820) },
7026     { PREFIX_TABLE (PREFIX_0F3821) },
7027     { PREFIX_TABLE (PREFIX_0F3822) },
7028     { PREFIX_TABLE (PREFIX_0F3823) },
7029     { PREFIX_TABLE (PREFIX_0F3824) },
7030     { PREFIX_TABLE (PREFIX_0F3825) },
7031     { Bad_Opcode },
7032     { Bad_Opcode },
7033     /* 28 */
7034     { PREFIX_TABLE (PREFIX_0F3828) },
7035     { PREFIX_TABLE (PREFIX_0F3829) },
7036     { PREFIX_TABLE (PREFIX_0F382A) },
7037     { PREFIX_TABLE (PREFIX_0F382B) },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     { Bad_Opcode },
7041     { Bad_Opcode },
7042     /* 30 */
7043     { PREFIX_TABLE (PREFIX_0F3830) },
7044     { PREFIX_TABLE (PREFIX_0F3831) },
7045     { PREFIX_TABLE (PREFIX_0F3832) },
7046     { PREFIX_TABLE (PREFIX_0F3833) },
7047     { PREFIX_TABLE (PREFIX_0F3834) },
7048     { PREFIX_TABLE (PREFIX_0F3835) },
7049     { Bad_Opcode },
7050     { PREFIX_TABLE (PREFIX_0F3837) },
7051     /* 38 */
7052     { PREFIX_TABLE (PREFIX_0F3838) },
7053     { PREFIX_TABLE (PREFIX_0F3839) },
7054     { PREFIX_TABLE (PREFIX_0F383A) },
7055     { PREFIX_TABLE (PREFIX_0F383B) },
7056     { PREFIX_TABLE (PREFIX_0F383C) },
7057     { PREFIX_TABLE (PREFIX_0F383D) },
7058     { PREFIX_TABLE (PREFIX_0F383E) },
7059     { PREFIX_TABLE (PREFIX_0F383F) },
7060     /* 40 */
7061     { PREFIX_TABLE (PREFIX_0F3840) },
7062     { PREFIX_TABLE (PREFIX_0F3841) },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     { Bad_Opcode },
7068     { Bad_Opcode },
7069     /* 48 */
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     { Bad_Opcode },
7077     { Bad_Opcode },
7078     /* 50 */
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     { Bad_Opcode },
7086     { Bad_Opcode },
7087     /* 58 */
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     { Bad_Opcode },
7095     { Bad_Opcode },
7096     /* 60 */
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     { Bad_Opcode },
7104     { Bad_Opcode },
7105     /* 68 */
7106     { Bad_Opcode },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     { Bad_Opcode },
7113     { Bad_Opcode },
7114     /* 70 */
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     { Bad_Opcode },
7122     { Bad_Opcode },
7123     /* 78 */
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     { Bad_Opcode },
7131     { Bad_Opcode },
7132     /* 80 */
7133     { PREFIX_TABLE (PREFIX_0F3880) },
7134     { PREFIX_TABLE (PREFIX_0F3881) },
7135     { PREFIX_TABLE (PREFIX_0F3882) },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     { Bad_Opcode },
7140     { Bad_Opcode },
7141     /* 88 */
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     { Bad_Opcode },
7149     { Bad_Opcode },
7150     /* 90 */
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     { Bad_Opcode },
7158     { Bad_Opcode },
7159     /* 98 */
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     { Bad_Opcode },
7167     { Bad_Opcode },
7168     /* a0 */
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     { Bad_Opcode },
7176     { Bad_Opcode },
7177     /* a8 */
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     { Bad_Opcode },
7185     { Bad_Opcode },
7186     /* b0 */
7187     { Bad_Opcode },
7188     { Bad_Opcode },
7189     { Bad_Opcode },
7190     { Bad_Opcode },
7191     { Bad_Opcode },
7192     { Bad_Opcode },
7193     { Bad_Opcode },
7194     { Bad_Opcode },
7195     /* b8 */
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     /* c0 */
7205     { Bad_Opcode },
7206     { Bad_Opcode },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { Bad_Opcode },
7211     { Bad_Opcode },
7212     { Bad_Opcode },
7213     /* c8 */
7214     { PREFIX_TABLE (PREFIX_0F38C8) },
7215     { PREFIX_TABLE (PREFIX_0F38C9) },
7216     { PREFIX_TABLE (PREFIX_0F38CA) },
7217     { PREFIX_TABLE (PREFIX_0F38CB) },
7218     { PREFIX_TABLE (PREFIX_0F38CC) },
7219     { PREFIX_TABLE (PREFIX_0F38CD) },
7220     { Bad_Opcode },
7221     { PREFIX_TABLE (PREFIX_0F38CF) },
7222     /* d0 */
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     { Bad_Opcode },
7230     { Bad_Opcode },
7231     /* d8 */
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { PREFIX_TABLE (PREFIX_0F38DB) },
7236     { PREFIX_TABLE (PREFIX_0F38DC) },
7237     { PREFIX_TABLE (PREFIX_0F38DD) },
7238     { PREFIX_TABLE (PREFIX_0F38DE) },
7239     { PREFIX_TABLE (PREFIX_0F38DF) },
7240     /* e0 */
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247     { Bad_Opcode },
7248     { Bad_Opcode },
7249     /* e8 */
7250     { Bad_Opcode },
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     /* f0 */
7259     { PREFIX_TABLE (PREFIX_0F38F0) },
7260     { PREFIX_TABLE (PREFIX_0F38F1) },
7261     { Bad_Opcode },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { PREFIX_TABLE (PREFIX_0F38F5) },
7265     { PREFIX_TABLE (PREFIX_0F38F6) },
7266     { Bad_Opcode },
7267     /* f8 */
7268     { PREFIX_TABLE (PREFIX_0F38F8) },
7269     { PREFIX_TABLE (PREFIX_0F38F9) },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276   },
7277   /* THREE_BYTE_0F3A */
7278   {
7279     /* 00 */
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     { Bad_Opcode },
7287     { Bad_Opcode },
7288     /* 08 */
7289     { PREFIX_TABLE (PREFIX_0F3A08) },
7290     { PREFIX_TABLE (PREFIX_0F3A09) },
7291     { PREFIX_TABLE (PREFIX_0F3A0A) },
7292     { PREFIX_TABLE (PREFIX_0F3A0B) },
7293     { PREFIX_TABLE (PREFIX_0F3A0C) },
7294     { PREFIX_TABLE (PREFIX_0F3A0D) },
7295     { PREFIX_TABLE (PREFIX_0F3A0E) },
7296     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7297     /* 10 */
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { PREFIX_TABLE (PREFIX_0F3A14) },
7303     { PREFIX_TABLE (PREFIX_0F3A15) },
7304     { PREFIX_TABLE (PREFIX_0F3A16) },
7305     { PREFIX_TABLE (PREFIX_0F3A17) },
7306     /* 18 */
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     { Bad_Opcode },
7314     { Bad_Opcode },
7315     /* 20 */
7316     { PREFIX_TABLE (PREFIX_0F3A20) },
7317     { PREFIX_TABLE (PREFIX_0F3A21) },
7318     { PREFIX_TABLE (PREFIX_0F3A22) },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     { Bad_Opcode },
7323     { Bad_Opcode },
7324     /* 28 */
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     { Bad_Opcode },
7332     { Bad_Opcode },
7333     /* 30 */
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     { Bad_Opcode },
7341     { Bad_Opcode },
7342     /* 38 */
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     { Bad_Opcode },
7350     { Bad_Opcode },
7351     /* 40 */
7352     { PREFIX_TABLE (PREFIX_0F3A40) },
7353     { PREFIX_TABLE (PREFIX_0F3A41) },
7354     { PREFIX_TABLE (PREFIX_0F3A42) },
7355     { Bad_Opcode },
7356     { PREFIX_TABLE (PREFIX_0F3A44) },
7357     { Bad_Opcode },
7358     { Bad_Opcode },
7359     { Bad_Opcode },
7360     /* 48 */
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     { Bad_Opcode },
7368     { Bad_Opcode },
7369     /* 50 */
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     { Bad_Opcode },
7377     { Bad_Opcode },
7378     /* 58 */
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     { Bad_Opcode },
7386     { Bad_Opcode },
7387     /* 60 */
7388     { PREFIX_TABLE (PREFIX_0F3A60) },
7389     { PREFIX_TABLE (PREFIX_0F3A61) },
7390     { PREFIX_TABLE (PREFIX_0F3A62) },
7391     { PREFIX_TABLE (PREFIX_0F3A63) },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     { Bad_Opcode },
7395     { Bad_Opcode },
7396     /* 68 */
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     { Bad_Opcode },
7404     { Bad_Opcode },
7405     /* 70 */
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     { Bad_Opcode },
7413     { Bad_Opcode },
7414     /* 78 */
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     { Bad_Opcode },
7422     { Bad_Opcode },
7423     /* 80 */
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     { Bad_Opcode },
7431     { Bad_Opcode },
7432     /* 88 */
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     { Bad_Opcode },
7440     { Bad_Opcode },
7441     /* 90 */
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     { Bad_Opcode },
7449     { Bad_Opcode },
7450     /* 98 */
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     { Bad_Opcode },
7458     { Bad_Opcode },
7459     /* a0 */
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     { Bad_Opcode },
7467     { Bad_Opcode },
7468     /* a8 */
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     { Bad_Opcode },
7476     { Bad_Opcode },
7477     /* b0 */
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     /* b8 */
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     { Bad_Opcode },
7494     { Bad_Opcode },
7495     /* c0 */
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { Bad_Opcode },
7502     { Bad_Opcode },
7503     { Bad_Opcode },
7504     /* c8 */
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { PREFIX_TABLE (PREFIX_0F3ACC) },
7510     { Bad_Opcode },
7511     { PREFIX_TABLE (PREFIX_0F3ACE) },
7512     { PREFIX_TABLE (PREFIX_0F3ACF) },
7513     /* d0 */
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     /* d8 */
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { PREFIX_TABLE (PREFIX_0F3ADF) },
7531     /* e0 */
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     /* e8 */
7541     { Bad_Opcode },
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     /* f0 */
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     { Bad_Opcode },
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     /* f8 */
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567   },
7568 };
7569
7570 static const struct dis386 xop_table[][256] = {
7571   /* XOP_08 */
7572   {
7573     /* 00 */
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     /* 08 */
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     { Bad_Opcode },
7590     { Bad_Opcode },
7591     /* 10 */
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     /* 18 */
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     /* 20 */
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     /* 28 */
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     /* 30 */
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     /* 38 */
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     /* 40 */
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     /* 48 */
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     /* 50 */
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     /* 58 */
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     /* 60 */
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     /* 68 */
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { Bad_Opcode },
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     /* 70 */
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     /* 78 */
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { Bad_Opcode },
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     /* 80 */
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { Bad_Opcode },
7723     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7724     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7725     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726     /* 88 */
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7734     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7735     /* 90 */
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7743     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744     /* 98 */
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7752     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7753     /* a0 */
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7757     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7761     { Bad_Opcode },
7762     /* a8 */
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     { Bad_Opcode },
7770     { Bad_Opcode },
7771     /* b0 */
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7779     { Bad_Opcode },
7780     /* b8 */
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     /* c0 */
7790     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7791     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7792     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7793     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     /* c8 */
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7804     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7805     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7806     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7807     /* d0 */
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     /* d8 */
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     /* e0 */
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     /* e8 */
7835     { Bad_Opcode },
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7840     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7841     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7842     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7843     /* f0 */
7844     { Bad_Opcode },
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     /* f8 */
7853     { Bad_Opcode },
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861   },
7862   /* XOP_09 */
7863   {
7864     /* 00 */
7865     { Bad_Opcode },
7866     { REG_TABLE (REG_XOP_TBM_01) },
7867     { REG_TABLE (REG_XOP_TBM_02) },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     { Bad_Opcode },
7872     { Bad_Opcode },
7873     /* 08 */
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     { Bad_Opcode },
7881     { Bad_Opcode },
7882     /* 10 */
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { REG_TABLE (REG_XOP_LWPCB) },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     { Bad_Opcode },
7890     { Bad_Opcode },
7891     /* 18 */
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     { Bad_Opcode },
7899     { Bad_Opcode },
7900     /* 20 */
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     { Bad_Opcode },
7908     { Bad_Opcode },
7909     /* 28 */
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     { Bad_Opcode },
7917     { Bad_Opcode },
7918     /* 30 */
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     { Bad_Opcode },
7926     { Bad_Opcode },
7927     /* 38 */
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     { Bad_Opcode },
7935     { Bad_Opcode },
7936     /* 40 */
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     { Bad_Opcode },
7944     { Bad_Opcode },
7945     /* 48 */
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     { Bad_Opcode },
7953     { Bad_Opcode },
7954     /* 50 */
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     { Bad_Opcode },
7962     { Bad_Opcode },
7963     /* 58 */
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     { Bad_Opcode },
7971     { Bad_Opcode },
7972     /* 60 */
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     { Bad_Opcode },
7980     { Bad_Opcode },
7981     /* 68 */
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     { Bad_Opcode },
7989     { Bad_Opcode },
7990     /* 70 */
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     { Bad_Opcode },
7998     { Bad_Opcode },
7999     /* 78 */
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { Bad_Opcode },
8003     { Bad_Opcode },
8004     { Bad_Opcode },
8005     { Bad_Opcode },
8006     { Bad_Opcode },
8007     { Bad_Opcode },
8008     /* 80 */
8009     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8010     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8011     { "vfrczss",        { XM, EXd }, 0 },
8012     { "vfrczsd",        { XM, EXq }, 0 },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     { Bad_Opcode },
8016     { Bad_Opcode },
8017     /* 88 */
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     { Bad_Opcode },
8025     { Bad_Opcode },
8026     /* 90 */
8027     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8028     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8029     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8030     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8031     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8032     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8033     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8034     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8035     /* 98 */
8036     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8037     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8038     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8039     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     { Bad_Opcode },
8043     { Bad_Opcode },
8044     /* a0 */
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     { Bad_Opcode },
8052     { Bad_Opcode },
8053     /* a8 */
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060     { Bad_Opcode },
8061     { Bad_Opcode },
8062     /* b0 */
8063     { Bad_Opcode },
8064     { Bad_Opcode },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     /* b8 */
8072     { Bad_Opcode },
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     /* c0 */
8081     { Bad_Opcode },
8082     { "vphaddbw",       { XM, EXxmm }, 0 },
8083     { "vphaddbd",       { XM, EXxmm }, 0 },
8084     { "vphaddbq",       { XM, EXxmm }, 0 },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { "vphaddwd",       { XM, EXxmm }, 0 },
8088     { "vphaddwq",       { XM, EXxmm }, 0 },
8089     /* c8 */
8090     { Bad_Opcode },
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { "vphadddq",       { XM, EXxmm }, 0 },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     /* d0 */
8099     { Bad_Opcode },
8100     { "vphaddubw",      { XM, EXxmm }, 0 },
8101     { "vphaddubd",      { XM, EXxmm }, 0 },
8102     { "vphaddubq",      { XM, EXxmm }, 0 },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { "vphadduwd",      { XM, EXxmm }, 0 },
8106     { "vphadduwq",      { XM, EXxmm }, 0 },
8107     /* d8 */
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { "vphaddudq",      { XM, EXxmm }, 0 },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     /* e0 */
8117     { Bad_Opcode },
8118     { "vphsubbw",       { XM, EXxmm }, 0 },
8119     { "vphsubwd",       { XM, EXxmm }, 0 },
8120     { "vphsubdq",       { XM, EXxmm }, 0 },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     /* e8 */
8126     { Bad_Opcode },
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     /* f0 */
8135     { Bad_Opcode },
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     /* f8 */
8144     { Bad_Opcode },
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152   },
8153   /* XOP_0A */
8154   {
8155     /* 00 */
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     { Bad_Opcode },
8163     { Bad_Opcode },
8164     /* 08 */
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     { Bad_Opcode },
8172     { Bad_Opcode },
8173     /* 10 */
8174     { "bextrS", { Gdq, Edq, Id }, 0 },
8175     { Bad_Opcode },
8176     { REG_TABLE (REG_XOP_LWP) },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     { Bad_Opcode },
8181     { Bad_Opcode },
8182     /* 18 */
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     { Bad_Opcode },
8190     { Bad_Opcode },
8191     /* 20 */
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     { Bad_Opcode },
8199     { Bad_Opcode },
8200     /* 28 */
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     { Bad_Opcode },
8208     { Bad_Opcode },
8209     /* 30 */
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     { Bad_Opcode },
8217     { Bad_Opcode },
8218     /* 38 */
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     { Bad_Opcode },
8226     { Bad_Opcode },
8227     /* 40 */
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     { Bad_Opcode },
8235     { Bad_Opcode },
8236     /* 48 */
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     { Bad_Opcode },
8244     { Bad_Opcode },
8245     /* 50 */
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     { Bad_Opcode },
8253     { Bad_Opcode },
8254     /* 58 */
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     { Bad_Opcode },
8262     { Bad_Opcode },
8263     /* 60 */
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     { Bad_Opcode },
8271     { Bad_Opcode },
8272     /* 68 */
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     { Bad_Opcode },
8280     { Bad_Opcode },
8281     /* 70 */
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     { Bad_Opcode },
8289     { Bad_Opcode },
8290     /* 78 */
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     { Bad_Opcode },
8298     { Bad_Opcode },
8299     /* 80 */
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     { Bad_Opcode },
8307     { Bad_Opcode },
8308     /* 88 */
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     { Bad_Opcode },
8316     { Bad_Opcode },
8317     /* 90 */
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     { Bad_Opcode },
8325     { Bad_Opcode },
8326     /* 98 */
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     { Bad_Opcode },
8334     { Bad_Opcode },
8335     /* a0 */
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     { Bad_Opcode },
8343     { Bad_Opcode },
8344     /* a8 */
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     { Bad_Opcode },
8352     { Bad_Opcode },
8353     /* b0 */
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     /* b8 */
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     /* c0 */
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     /* c8 */
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     /* d0 */
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     /* d8 */
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     /* e0 */
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     /* e8 */
8417     { Bad_Opcode },
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     /* f0 */
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     /* f8 */
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443   },
8444 };
8445
8446 static const struct dis386 vex_table[][256] = {
8447   /* VEX_0F */
8448   {
8449     /* 00 */
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     /* 08 */
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     /* 10 */
8468     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8469     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8471     { MOD_TABLE (MOD_VEX_0F13) },
8472     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8473     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8474     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8475     { MOD_TABLE (MOD_VEX_0F17) },
8476     /* 18 */
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     /* 20 */
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     /* 28 */
8495     { "vmovapX",        { XM, EXx }, 0 },
8496     { "vmovapX",        { EXxS, XM }, 0 },
8497     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8498     { MOD_TABLE (MOD_VEX_0F2B) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8501     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8502     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8503     /* 30 */
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     /* 38 */
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     { Bad_Opcode },
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     /* 40 */
8522     { Bad_Opcode },
8523     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8525     { Bad_Opcode },
8526     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8528     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8529     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8530     /* 48 */
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     /* 50 */
8540     { MOD_TABLE (MOD_VEX_0F50) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8544     { "vandpX",         { XM, Vex, EXx }, 0 },
8545     { "vandnpX",        { XM, Vex, EXx }, 0 },
8546     { "vorpX",          { XM, Vex, EXx }, 0 },
8547     { "vxorpX",         { XM, Vex, EXx }, 0 },
8548     /* 58 */
8549     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8550     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8555     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8556     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8557     /* 60 */
8558     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8559     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8560     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8564     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8565     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8566     /* 68 */
8567     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8568     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8569     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8570     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8571     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8572     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8573     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8574     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8575     /* 70 */
8576     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8577     { REG_TABLE (REG_VEX_0F71) },
8578     { REG_TABLE (REG_VEX_0F72) },
8579     { REG_TABLE (REG_VEX_0F73) },
8580     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8581     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8582     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8583     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8584     /* 78 */
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8590     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8591     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8592     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8593     /* 80 */
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     /* 88 */
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     /* 90 */
8612     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8613     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8614     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8615     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     /* 98 */
8621     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8622     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     /* a0 */
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     /* a8 */
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642     { Bad_Opcode },
8643     { Bad_Opcode },
8644     { Bad_Opcode },
8645     { REG_TABLE (REG_VEX_0FAE) },
8646     { Bad_Opcode },
8647     /* b0 */
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     /* b8 */
8657     { Bad_Opcode },
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     /* c0 */
8666     { Bad_Opcode },
8667     { Bad_Opcode },
8668     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8669     { Bad_Opcode },
8670     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8672     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8673     { Bad_Opcode },
8674     /* c8 */
8675     { Bad_Opcode },
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     /* d0 */
8684     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8690     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8691     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8692     /* d8 */
8693     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8699     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8700     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8701     /* e0 */
8702     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8707     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8708     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8709     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8710     /* e8 */
8711     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8712     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8713     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8714     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8715     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8716     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8717     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8718     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8719     /* f0 */
8720     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8721     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8722     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8723     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8724     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8725     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8726     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8727     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8728     /* f8 */
8729     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8730     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8731     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8732     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8733     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8734     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8735     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8736     { Bad_Opcode },
8737   },
8738   /* VEX_0F38 */
8739   {
8740     /* 00 */
8741     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8743     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8746     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8747     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8748     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8749     /* 08 */
8750     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8756     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8757     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8758     /* 10 */
8759     { Bad_Opcode },
8760     { Bad_Opcode },
8761     { Bad_Opcode },
8762     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8763     { Bad_Opcode },
8764     { Bad_Opcode },
8765     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8766     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8767     /* 18 */
8768     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8771     { Bad_Opcode },
8772     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8774     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8775     { Bad_Opcode },
8776     /* 20 */
8777     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8783     { Bad_Opcode },
8784     { Bad_Opcode },
8785     /* 28 */
8786     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8787     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8788     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8792     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8793     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8794     /* 30 */
8795     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8796     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8797     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8798     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8799     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8800     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8801     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8802     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8803     /* 38 */
8804     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8805     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8806     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8807     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8808     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8809     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8810     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8811     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8812     /* 40 */
8813     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8819     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8820     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8821     /* 48 */
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     { Bad_Opcode },
8829     { Bad_Opcode },
8830     /* 50 */
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     { Bad_Opcode },
8838     { Bad_Opcode },
8839     /* 58 */
8840     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8841     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8842     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     { Bad_Opcode },
8847     { Bad_Opcode },
8848     /* 60 */
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     { Bad_Opcode },
8856     { Bad_Opcode },
8857     /* 68 */
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     { Bad_Opcode },
8865     { Bad_Opcode },
8866     /* 70 */
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { Bad_Opcode },
8870     { Bad_Opcode },
8871     { Bad_Opcode },
8872     { Bad_Opcode },
8873     { Bad_Opcode },
8874     { Bad_Opcode },
8875     /* 78 */
8876     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     { Bad_Opcode },
8883     { Bad_Opcode },
8884     /* 80 */
8885     { Bad_Opcode },
8886     { Bad_Opcode },
8887     { Bad_Opcode },
8888     { Bad_Opcode },
8889     { Bad_Opcode },
8890     { Bad_Opcode },
8891     { Bad_Opcode },
8892     { Bad_Opcode },
8893     /* 88 */
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8899     { Bad_Opcode },
8900     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8901     { Bad_Opcode },
8902     /* 90 */
8903     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8907     { Bad_Opcode },
8908     { Bad_Opcode },
8909     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8910     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8911     /* 98 */
8912     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8913     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8914     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8915     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8916     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8918     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8919     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8920     /* a0 */
8921     { Bad_Opcode },
8922     { Bad_Opcode },
8923     { Bad_Opcode },
8924     { Bad_Opcode },
8925     { Bad_Opcode },
8926     { Bad_Opcode },
8927     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8928     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8929     /* a8 */
8930     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8931     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8932     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8933     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8934     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8935     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8936     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8937     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8938     /* b0 */
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { Bad_Opcode },
8945     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8947     /* b8 */
8948     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8949     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8956     /* c0 */
8957     { Bad_Opcode },
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { Bad_Opcode },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { Bad_Opcode },
8965     /* c8 */
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     { Bad_Opcode },
8973     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8974     /* d0 */
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     { Bad_Opcode },
8982     { Bad_Opcode },
8983     /* d8 */
8984     { Bad_Opcode },
8985     { Bad_Opcode },
8986     { Bad_Opcode },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8992     /* e0 */
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999     { Bad_Opcode },
9000     { Bad_Opcode },
9001     /* e8 */
9002     { Bad_Opcode },
9003     { Bad_Opcode },
9004     { Bad_Opcode },
9005     { Bad_Opcode },
9006     { Bad_Opcode },
9007     { Bad_Opcode },
9008     { Bad_Opcode },
9009     { Bad_Opcode },
9010     /* f0 */
9011     { Bad_Opcode },
9012     { Bad_Opcode },
9013     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9014     { REG_TABLE (REG_VEX_0F38F3) },
9015     { Bad_Opcode },
9016     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9019     /* f8 */
9020     { Bad_Opcode },
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028   },
9029   /* VEX_0F3A */
9030   {
9031     /* 00 */
9032     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9033     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9034     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9035     { Bad_Opcode },
9036     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9037     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9038     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9039     { Bad_Opcode },
9040     /* 08 */
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9042     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9043     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9044     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9045     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9046     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9047     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9048     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9049     /* 10 */
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9055     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9056     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9058     /* 18 */
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9065     { Bad_Opcode },
9066     { Bad_Opcode },
9067     /* 20 */
9068     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9069     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9070     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     { Bad_Opcode },
9075     { Bad_Opcode },
9076     /* 28 */
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     { Bad_Opcode },
9084     { Bad_Opcode },
9085     /* 30 */
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9089     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     { Bad_Opcode },
9093     { Bad_Opcode },
9094     /* 38 */
9095     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9096     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     { Bad_Opcode },
9102     { Bad_Opcode },
9103     /* 40 */
9104     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9109     { Bad_Opcode },
9110     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9111     { Bad_Opcode },
9112     /* 48 */
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9118     { Bad_Opcode },
9119     { Bad_Opcode },
9120     { Bad_Opcode },
9121     /* 50 */
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { Bad_Opcode },
9127     { Bad_Opcode },
9128     { Bad_Opcode },
9129     { Bad_Opcode },
9130     /* 58 */
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9137     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9139     /* 60 */
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9144     { Bad_Opcode },
9145     { Bad_Opcode },
9146     { Bad_Opcode },
9147     { Bad_Opcode },
9148     /* 68 */
9149     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9155     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9156     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9157     /* 70 */
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     { Bad_Opcode },
9165     { Bad_Opcode },
9166     /* 78 */
9167     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9168     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9169     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9170     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9171     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9172     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9173     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9174     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9175     /* 80 */
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     { Bad_Opcode },
9183     { Bad_Opcode },
9184     /* 88 */
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     { Bad_Opcode },
9192     { Bad_Opcode },
9193     /* 90 */
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     { Bad_Opcode },
9201     { Bad_Opcode },
9202     /* 98 */
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     { Bad_Opcode },
9210     { Bad_Opcode },
9211     /* a0 */
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     { Bad_Opcode },
9219     { Bad_Opcode },
9220     /* a8 */
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     { Bad_Opcode },
9228     { Bad_Opcode },
9229     /* b0 */
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { Bad_Opcode },
9235     { Bad_Opcode },
9236     { Bad_Opcode },
9237     { Bad_Opcode },
9238     /* b8 */
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     { Bad_Opcode },
9246     { Bad_Opcode },
9247     /* c0 */
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { Bad_Opcode },
9254     { Bad_Opcode },
9255     { Bad_Opcode },
9256     /* c8 */
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9264     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9265     /* d0 */
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     /* d8 */
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9283     /* e0 */
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     /* e8 */
9293     { Bad_Opcode },
9294     { Bad_Opcode },
9295     { Bad_Opcode },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     /* f0 */
9302     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9303     { Bad_Opcode },
9304     { Bad_Opcode },
9305     { Bad_Opcode },
9306     { Bad_Opcode },
9307     { Bad_Opcode },
9308     { Bad_Opcode },
9309     { Bad_Opcode },
9310     /* f8 */
9311     { Bad_Opcode },
9312     { Bad_Opcode },
9313     { Bad_Opcode },
9314     { Bad_Opcode },
9315     { Bad_Opcode },
9316     { Bad_Opcode },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319   },
9320 };
9321
9322 #include "i386-dis-evex.h"
9323
9324 static const struct dis386 vex_len_table[][2] = {
9325   /* VEX_LEN_0F12_P_0_M_0 */
9326   {
9327     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9328   },
9329
9330   /* VEX_LEN_0F12_P_0_M_1 */
9331   {
9332     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9333   },
9334
9335   /* VEX_LEN_0F12_P_2 */
9336   {
9337     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9338   },
9339
9340   /* VEX_LEN_0F13_M_0 */
9341   {
9342     { "vmovlpX",        { EXq, XM }, 0 },
9343   },
9344
9345   /* VEX_LEN_0F16_P_0_M_0 */
9346   {
9347     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9348   },
9349
9350   /* VEX_LEN_0F16_P_0_M_1 */
9351   {
9352     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9353   },
9354
9355   /* VEX_LEN_0F16_P_2 */
9356   {
9357     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9358   },
9359
9360   /* VEX_LEN_0F17_M_0 */
9361   {
9362     { "vmovhpX",        { EXq, XM }, 0 },
9363   },
9364
9365   /* VEX_LEN_0F41_P_0 */
9366   {
9367     { Bad_Opcode },
9368     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9369   },
9370   /* VEX_LEN_0F41_P_2 */
9371   {
9372     { Bad_Opcode },
9373     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9374   },
9375   /* VEX_LEN_0F42_P_0 */
9376   {
9377     { Bad_Opcode },
9378     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9379   },
9380   /* VEX_LEN_0F42_P_2 */
9381   {
9382     { Bad_Opcode },
9383     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9384   },
9385   /* VEX_LEN_0F44_P_0 */
9386   {
9387     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9388   },
9389   /* VEX_LEN_0F44_P_2 */
9390   {
9391     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9392   },
9393   /* VEX_LEN_0F45_P_0 */
9394   {
9395     { Bad_Opcode },
9396     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9397   },
9398   /* VEX_LEN_0F45_P_2 */
9399   {
9400     { Bad_Opcode },
9401     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9402   },
9403   /* VEX_LEN_0F46_P_0 */
9404   {
9405     { Bad_Opcode },
9406     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9407   },
9408   /* VEX_LEN_0F46_P_2 */
9409   {
9410     { Bad_Opcode },
9411     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9412   },
9413   /* VEX_LEN_0F47_P_0 */
9414   {
9415     { Bad_Opcode },
9416     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9417   },
9418   /* VEX_LEN_0F47_P_2 */
9419   {
9420     { Bad_Opcode },
9421     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9422   },
9423   /* VEX_LEN_0F4A_P_0 */
9424   {
9425     { Bad_Opcode },
9426     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9427   },
9428   /* VEX_LEN_0F4A_P_2 */
9429   {
9430     { Bad_Opcode },
9431     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9432   },
9433   /* VEX_LEN_0F4B_P_0 */
9434   {
9435     { Bad_Opcode },
9436     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9437   },
9438   /* VEX_LEN_0F4B_P_2 */
9439   {
9440     { Bad_Opcode },
9441     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9442   },
9443
9444   /* VEX_LEN_0F6E_P_2 */
9445   {
9446     { "vmovK",          { XMScalar, Edq }, 0 },
9447   },
9448
9449   /* VEX_LEN_0F77_P_1 */
9450   {
9451     { "vzeroupper",     { XX }, 0 },
9452     { "vzeroall",       { XX }, 0 },
9453   },
9454
9455   /* VEX_LEN_0F7E_P_1 */
9456   {
9457     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9458   },
9459
9460   /* VEX_LEN_0F7E_P_2 */
9461   {
9462     { "vmovK",          { Edq, XMScalar }, 0 },
9463   },
9464
9465   /* VEX_LEN_0F90_P_0 */
9466   {
9467     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9468   },
9469
9470   /* VEX_LEN_0F90_P_2 */
9471   {
9472     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9473   },
9474
9475   /* VEX_LEN_0F91_P_0 */
9476   {
9477     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9478   },
9479
9480   /* VEX_LEN_0F91_P_2 */
9481   {
9482     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9483   },
9484
9485   /* VEX_LEN_0F92_P_0 */
9486   {
9487     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9488   },
9489
9490   /* VEX_LEN_0F92_P_2 */
9491   {
9492     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9493   },
9494
9495   /* VEX_LEN_0F92_P_3 */
9496   {
9497     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9498   },
9499
9500   /* VEX_LEN_0F93_P_0 */
9501   {
9502     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9503   },
9504
9505   /* VEX_LEN_0F93_P_2 */
9506   {
9507     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9508   },
9509
9510   /* VEX_LEN_0F93_P_3 */
9511   {
9512     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9513   },
9514
9515   /* VEX_LEN_0F98_P_0 */
9516   {
9517     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9518   },
9519
9520   /* VEX_LEN_0F98_P_2 */
9521   {
9522     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9523   },
9524
9525   /* VEX_LEN_0F99_P_0 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9528   },
9529
9530   /* VEX_LEN_0F99_P_2 */
9531   {
9532     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9533   },
9534
9535   /* VEX_LEN_0FAE_R_2_M_0 */
9536   {
9537     { "vldmxcsr",       { Md }, 0 },
9538   },
9539
9540   /* VEX_LEN_0FAE_R_3_M_0 */
9541   {
9542     { "vstmxcsr",       { Md }, 0 },
9543   },
9544
9545   /* VEX_LEN_0FC4_P_2 */
9546   {
9547     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9548   },
9549
9550   /* VEX_LEN_0FC5_P_2 */
9551   {
9552     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9553   },
9554
9555   /* VEX_LEN_0FD6_P_2 */
9556   {
9557     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9558   },
9559
9560   /* VEX_LEN_0FF7_P_2 */
9561   {
9562     { "vmaskmovdqu",    { XM, XS }, 0 },
9563   },
9564
9565   /* VEX_LEN_0F3816_P_2 */
9566   {
9567     { Bad_Opcode },
9568     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9569   },
9570
9571   /* VEX_LEN_0F3819_P_2 */
9572   {
9573     { Bad_Opcode },
9574     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9575   },
9576
9577   /* VEX_LEN_0F381A_P_2_M_0 */
9578   {
9579     { Bad_Opcode },
9580     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9581   },
9582
9583   /* VEX_LEN_0F3836_P_2 */
9584   {
9585     { Bad_Opcode },
9586     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9587   },
9588
9589   /* VEX_LEN_0F3841_P_2 */
9590   {
9591     { "vphminposuw",    { XM, EXx }, 0 },
9592   },
9593
9594   /* VEX_LEN_0F385A_P_2_M_0 */
9595   {
9596     { Bad_Opcode },
9597     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9598   },
9599
9600   /* VEX_LEN_0F38DB_P_2 */
9601   {
9602     { "vaesimc",        { XM, EXx }, 0 },
9603   },
9604
9605   /* VEX_LEN_0F38F2_P_0 */
9606   {
9607     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9608   },
9609
9610   /* VEX_LEN_0F38F3_R_1_P_0 */
9611   {
9612     { "blsrS",          { VexGdq, Edq }, 0 },
9613   },
9614
9615   /* VEX_LEN_0F38F3_R_2_P_0 */
9616   {
9617     { "blsmskS",        { VexGdq, Edq }, 0 },
9618   },
9619
9620   /* VEX_LEN_0F38F3_R_3_P_0 */
9621   {
9622     { "blsiS",          { VexGdq, Edq }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F38F5_P_0 */
9626   {
9627     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9628   },
9629
9630   /* VEX_LEN_0F38F5_P_1 */
9631   {
9632     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9633   },
9634
9635   /* VEX_LEN_0F38F5_P_3 */
9636   {
9637     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9638   },
9639
9640   /* VEX_LEN_0F38F6_P_3 */
9641   {
9642     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9643   },
9644
9645   /* VEX_LEN_0F38F7_P_0 */
9646   {
9647     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9648   },
9649
9650   /* VEX_LEN_0F38F7_P_1 */
9651   {
9652     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9653   },
9654
9655   /* VEX_LEN_0F38F7_P_2 */
9656   {
9657     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9658   },
9659
9660   /* VEX_LEN_0F38F7_P_3 */
9661   {
9662     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9663   },
9664
9665   /* VEX_LEN_0F3A00_P_2 */
9666   {
9667     { Bad_Opcode },
9668     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9669   },
9670
9671   /* VEX_LEN_0F3A01_P_2 */
9672   {
9673     { Bad_Opcode },
9674     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9675   },
9676
9677   /* VEX_LEN_0F3A06_P_2 */
9678   {
9679     { Bad_Opcode },
9680     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9681   },
9682
9683   /* VEX_LEN_0F3A14_P_2 */
9684   {
9685     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9686   },
9687
9688   /* VEX_LEN_0F3A15_P_2 */
9689   {
9690     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9691   },
9692
9693   /* VEX_LEN_0F3A16_P_2  */
9694   {
9695     { "vpextrK",        { Edq, XM, Ib }, 0 },
9696   },
9697
9698   /* VEX_LEN_0F3A17_P_2 */
9699   {
9700     { "vextractps",     { Edqd, XM, Ib }, 0 },
9701   },
9702
9703   /* VEX_LEN_0F3A18_P_2 */
9704   {
9705     { Bad_Opcode },
9706     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9707   },
9708
9709   /* VEX_LEN_0F3A19_P_2 */
9710   {
9711     { Bad_Opcode },
9712     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9713   },
9714
9715   /* VEX_LEN_0F3A20_P_2 */
9716   {
9717     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9718   },
9719
9720   /* VEX_LEN_0F3A21_P_2 */
9721   {
9722     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9723   },
9724
9725   /* VEX_LEN_0F3A22_P_2 */
9726   {
9727     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9728   },
9729
9730   /* VEX_LEN_0F3A30_P_2 */
9731   {
9732     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9733   },
9734
9735   /* VEX_LEN_0F3A31_P_2 */
9736   {
9737     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9738   },
9739
9740   /* VEX_LEN_0F3A32_P_2 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9743   },
9744
9745   /* VEX_LEN_0F3A33_P_2 */
9746   {
9747     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9748   },
9749
9750   /* VEX_LEN_0F3A38_P_2 */
9751   {
9752     { Bad_Opcode },
9753     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9754   },
9755
9756   /* VEX_LEN_0F3A39_P_2 */
9757   {
9758     { Bad_Opcode },
9759     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9760   },
9761
9762   /* VEX_LEN_0F3A41_P_2 */
9763   {
9764     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9765   },
9766
9767   /* VEX_LEN_0F3A46_P_2 */
9768   {
9769     { Bad_Opcode },
9770     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9771   },
9772
9773   /* VEX_LEN_0F3A60_P_2 */
9774   {
9775     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9776   },
9777
9778   /* VEX_LEN_0F3A61_P_2 */
9779   {
9780     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9781   },
9782
9783   /* VEX_LEN_0F3A62_P_2 */
9784   {
9785     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9786   },
9787
9788   /* VEX_LEN_0F3A63_P_2 */
9789   {
9790     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9791   },
9792
9793   /* VEX_LEN_0F3A6A_P_2 */
9794   {
9795     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9796   },
9797
9798   /* VEX_LEN_0F3A6B_P_2 */
9799   {
9800     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9801   },
9802
9803   /* VEX_LEN_0F3A6E_P_2 */
9804   {
9805     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9806   },
9807
9808   /* VEX_LEN_0F3A6F_P_2 */
9809   {
9810     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9811   },
9812
9813   /* VEX_LEN_0F3A7A_P_2 */
9814   {
9815     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9816   },
9817
9818   /* VEX_LEN_0F3A7B_P_2 */
9819   {
9820     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9821   },
9822
9823   /* VEX_LEN_0F3A7E_P_2 */
9824   {
9825     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9826   },
9827
9828   /* VEX_LEN_0F3A7F_P_2 */
9829   {
9830     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9831   },
9832
9833   /* VEX_LEN_0F3ADF_P_2 */
9834   {
9835     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9836   },
9837
9838   /* VEX_LEN_0F3AF0_P_3 */
9839   {
9840     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9841   },
9842
9843   /* VEX_LEN_0FXOP_08_CC */
9844   {
9845      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9846   },
9847
9848   /* VEX_LEN_0FXOP_08_CD */
9849   {
9850      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9851   },
9852
9853   /* VEX_LEN_0FXOP_08_CE */
9854   {
9855      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9856   },
9857
9858   /* VEX_LEN_0FXOP_08_CF */
9859   {
9860      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9861   },
9862
9863   /* VEX_LEN_0FXOP_08_EC */
9864   {
9865      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9866   },
9867
9868   /* VEX_LEN_0FXOP_08_ED */
9869   {
9870      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9871   },
9872
9873   /* VEX_LEN_0FXOP_08_EE */
9874   {
9875      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9876   },
9877
9878   /* VEX_LEN_0FXOP_08_EF */
9879   {
9880      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9881   },
9882
9883   /* VEX_LEN_0FXOP_09_80 */
9884   {
9885     { "vfrczps",        { XM, EXxmm }, 0 },
9886     { "vfrczps",        { XM, EXymmq }, 0 },
9887   },
9888
9889   /* VEX_LEN_0FXOP_09_81 */
9890   {
9891     { "vfrczpd",        { XM, EXxmm }, 0 },
9892     { "vfrczpd",        { XM, EXymmq }, 0 },
9893   },
9894 };
9895
9896 #include "i386-dis-evex-len.h"
9897
9898 static const struct dis386 vex_w_table[][2] = {
9899   {
9900     /* VEX_W_0F41_P_0_LEN_1 */
9901     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9902     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9903   },
9904   {
9905     /* VEX_W_0F41_P_2_LEN_1 */
9906     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9907     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9908   },
9909   {
9910     /* VEX_W_0F42_P_0_LEN_1 */
9911     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9912     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9913   },
9914   {
9915     /* VEX_W_0F42_P_2_LEN_1 */
9916     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9917     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9918   },
9919   {
9920     /* VEX_W_0F44_P_0_LEN_0 */
9921     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9922     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9923   },
9924   {
9925     /* VEX_W_0F44_P_2_LEN_0 */
9926     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9927     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9928   },
9929   {
9930     /* VEX_W_0F45_P_0_LEN_1 */
9931     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9932     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9933   },
9934   {
9935     /* VEX_W_0F45_P_2_LEN_1 */
9936     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9937     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9938   },
9939   {
9940     /* VEX_W_0F46_P_0_LEN_1 */
9941     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9942     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9943   },
9944   {
9945     /* VEX_W_0F46_P_2_LEN_1 */
9946     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9947     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F47_P_0_LEN_1 */
9951     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9952     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9953   },
9954   {
9955     /* VEX_W_0F47_P_2_LEN_1 */
9956     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9957     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9958   },
9959   {
9960     /* VEX_W_0F4A_P_0_LEN_1 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9963   },
9964   {
9965     /* VEX_W_0F4A_P_2_LEN_1 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9968   },
9969   {
9970     /* VEX_W_0F4B_P_0_LEN_1 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9972     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9973   },
9974   {
9975     /* VEX_W_0F4B_P_2_LEN_1 */
9976     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9977   },
9978   {
9979     /* VEX_W_0F90_P_0_LEN_0 */
9980     { "kmovw",          { MaskG, MaskE }, 0 },
9981     { "kmovq",          { MaskG, MaskE }, 0 },
9982   },
9983   {
9984     /* VEX_W_0F90_P_2_LEN_0 */
9985     { "kmovb",          { MaskG, MaskBDE }, 0 },
9986     { "kmovd",          { MaskG, MaskBDE }, 0 },
9987   },
9988   {
9989     /* VEX_W_0F91_P_0_LEN_0 */
9990     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9991     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9992   },
9993   {
9994     /* VEX_W_0F91_P_2_LEN_0 */
9995     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9996     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9997   },
9998   {
9999     /* VEX_W_0F92_P_0_LEN_0 */
10000     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10001   },
10002   {
10003     /* VEX_W_0F92_P_2_LEN_0 */
10004     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10005   },
10006   {
10007     /* VEX_W_0F93_P_0_LEN_0 */
10008     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10009   },
10010   {
10011     /* VEX_W_0F93_P_2_LEN_0 */
10012     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10013   },
10014   {
10015     /* VEX_W_0F98_P_0_LEN_0 */
10016     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10017     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10018   },
10019   {
10020     /* VEX_W_0F98_P_2_LEN_0 */
10021     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10022     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10023   },
10024   {
10025     /* VEX_W_0F99_P_0_LEN_0 */
10026     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10027     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10028   },
10029   {
10030     /* VEX_W_0F99_P_2_LEN_0 */
10031     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10032     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10033   },
10034   {
10035     /* VEX_W_0F380C_P_2  */
10036     { "vpermilps",      { XM, Vex, EXx }, 0 },
10037   },
10038   {
10039     /* VEX_W_0F380D_P_2  */
10040     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10041   },
10042   {
10043     /* VEX_W_0F380E_P_2  */
10044     { "vtestps",        { XM, EXx }, 0 },
10045   },
10046   {
10047     /* VEX_W_0F380F_P_2  */
10048     { "vtestpd",        { XM, EXx }, 0 },
10049   },
10050   {
10051     /* VEX_W_0F3816_P_2  */
10052     { "vpermps",        { XM, Vex, EXx }, 0 },
10053   },
10054   {
10055     /* VEX_W_0F3818_P_2 */
10056     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10057   },
10058   {
10059     /* VEX_W_0F3819_P_2 */
10060     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10061   },
10062   {
10063     /* VEX_W_0F381A_P_2_M_0 */
10064     { "vbroadcastf128", { XM, Mxmm }, 0 },
10065   },
10066   {
10067     /* VEX_W_0F382C_P_2_M_0 */
10068     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10069   },
10070   {
10071     /* VEX_W_0F382D_P_2_M_0 */
10072     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10073   },
10074   {
10075     /* VEX_W_0F382E_P_2_M_0 */
10076     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10077   },
10078   {
10079     /* VEX_W_0F382F_P_2_M_0 */
10080     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10081   },
10082   {
10083     /* VEX_W_0F3836_P_2  */
10084     { "vpermd",         { XM, Vex, EXx }, 0 },
10085   },
10086   {
10087     /* VEX_W_0F3846_P_2 */
10088     { "vpsravd",        { XM, Vex, EXx }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F3858_P_2 */
10092     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10093   },
10094   {
10095     /* VEX_W_0F3859_P_2 */
10096     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10097   },
10098   {
10099     /* VEX_W_0F385A_P_2_M_0 */
10100     { "vbroadcasti128", { XM, Mxmm }, 0 },
10101   },
10102   {
10103     /* VEX_W_0F3878_P_2 */
10104     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10105   },
10106   {
10107     /* VEX_W_0F3879_P_2 */
10108     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10109   },
10110   {
10111     /* VEX_W_0F38CF_P_2 */
10112     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10113   },
10114   {
10115     /* VEX_W_0F3A00_P_2 */
10116     { Bad_Opcode },
10117     { "vpermq",         { XM, EXx, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A01_P_2 */
10121     { Bad_Opcode },
10122     { "vpermpd",        { XM, EXx, Ib }, 0 },
10123   },
10124   {
10125     /* VEX_W_0F3A02_P_2 */
10126     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10127   },
10128   {
10129     /* VEX_W_0F3A04_P_2 */
10130     { "vpermilps",      { XM, EXx, Ib }, 0 },
10131   },
10132   {
10133     /* VEX_W_0F3A05_P_2 */
10134     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10135   },
10136   {
10137     /* VEX_W_0F3A06_P_2 */
10138     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10139   },
10140   {
10141     /* VEX_W_0F3A18_P_2 */
10142     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10143   },
10144   {
10145     /* VEX_W_0F3A19_P_2 */
10146     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10147   },
10148   {
10149     /* VEX_W_0F3A30_P_2_LEN_0 */
10150     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10151     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10152   },
10153   {
10154     /* VEX_W_0F3A31_P_2_LEN_0 */
10155     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10156     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10157   },
10158   {
10159     /* VEX_W_0F3A32_P_2_LEN_0 */
10160     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10161     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10162   },
10163   {
10164     /* VEX_W_0F3A33_P_2_LEN_0 */
10165     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10166     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10167   },
10168   {
10169     /* VEX_W_0F3A38_P_2 */
10170     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10171   },
10172   {
10173     /* VEX_W_0F3A39_P_2 */
10174     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10175   },
10176   {
10177     /* VEX_W_0F3A46_P_2 */
10178     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10179   },
10180   {
10181     /* VEX_W_0F3A48_P_2 */
10182     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10183     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10184   },
10185   {
10186     /* VEX_W_0F3A49_P_2 */
10187     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10188     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10189   },
10190   {
10191     /* VEX_W_0F3A4A_P_2 */
10192     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10193   },
10194   {
10195     /* VEX_W_0F3A4B_P_2 */
10196     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10197   },
10198   {
10199     /* VEX_W_0F3A4C_P_2 */
10200     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10201   },
10202   {
10203     /* VEX_W_0F3ACE_P_2 */
10204     { Bad_Opcode },
10205     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10206   },
10207   {
10208     /* VEX_W_0F3ACF_P_2 */
10209     { Bad_Opcode },
10210     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10211   },
10212
10213 #include "i386-dis-evex-w.h"
10214 };
10215
10216 static const struct dis386 mod_table[][2] = {
10217   {
10218     /* MOD_8D */
10219     { "leaS",           { Gv, M }, 0 },
10220   },
10221   {
10222     /* MOD_C6_REG_7 */
10223     { Bad_Opcode },
10224     { RM_TABLE (RM_C6_REG_7) },
10225   },
10226   {
10227     /* MOD_C7_REG_7 */
10228     { Bad_Opcode },
10229     { RM_TABLE (RM_C7_REG_7) },
10230   },
10231   {
10232     /* MOD_FF_REG_3 */
10233     { "Jcall^", { indirEp }, 0 },
10234   },
10235   {
10236     /* MOD_FF_REG_5 */
10237     { "Jjmp^", { indirEp }, 0 },
10238   },
10239   {
10240     /* MOD_0F01_REG_0 */
10241     { X86_64_TABLE (X86_64_0F01_REG_0) },
10242     { RM_TABLE (RM_0F01_REG_0) },
10243   },
10244   {
10245     /* MOD_0F01_REG_1 */
10246     { X86_64_TABLE (X86_64_0F01_REG_1) },
10247     { RM_TABLE (RM_0F01_REG_1) },
10248   },
10249   {
10250     /* MOD_0F01_REG_2 */
10251     { X86_64_TABLE (X86_64_0F01_REG_2) },
10252     { RM_TABLE (RM_0F01_REG_2) },
10253   },
10254   {
10255     /* MOD_0F01_REG_3 */
10256     { X86_64_TABLE (X86_64_0F01_REG_3) },
10257     { RM_TABLE (RM_0F01_REG_3) },
10258   },
10259   {
10260     /* MOD_0F01_REG_5 */
10261     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10262     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10263   },
10264   {
10265     /* MOD_0F01_REG_7 */
10266     { "invlpg",         { Mb }, 0 },
10267     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10268   },
10269   {
10270     /* MOD_0F12_PREFIX_0 */
10271     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10272     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10273   },
10274   {
10275     /* MOD_0F13 */
10276     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10277   },
10278   {
10279     /* MOD_0F16_PREFIX_0 */
10280     { "movhps",         { XM, EXq }, 0 },
10281     { "movlhps",        { XM, EXq }, 0 },
10282   },
10283   {
10284     /* MOD_0F17 */
10285     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10286   },
10287   {
10288     /* MOD_0F18_REG_0 */
10289     { "prefetchnta",    { Mb }, 0 },
10290   },
10291   {
10292     /* MOD_0F18_REG_1 */
10293     { "prefetcht0",     { Mb }, 0 },
10294   },
10295   {
10296     /* MOD_0F18_REG_2 */
10297     { "prefetcht1",     { Mb }, 0 },
10298   },
10299   {
10300     /* MOD_0F18_REG_3 */
10301     { "prefetcht2",     { Mb }, 0 },
10302   },
10303   {
10304     /* MOD_0F18_REG_4 */
10305     { "nop/reserved",   { Mb }, 0 },
10306   },
10307   {
10308     /* MOD_0F18_REG_5 */
10309     { "nop/reserved",   { Mb }, 0 },
10310   },
10311   {
10312     /* MOD_0F18_REG_6 */
10313     { "nop/reserved",   { Mb }, 0 },
10314   },
10315   {
10316     /* MOD_0F18_REG_7 */
10317     { "nop/reserved",   { Mb }, 0 },
10318   },
10319   {
10320     /* MOD_0F1A_PREFIX_0 */
10321     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10322     { "nopQ",           { Ev }, 0 },
10323   },
10324   {
10325     /* MOD_0F1B_PREFIX_0 */
10326     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10327     { "nopQ",           { Ev }, 0 },
10328   },
10329   {
10330     /* MOD_0F1B_PREFIX_1 */
10331     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10332     { "nopQ",           { Ev }, 0 },
10333   },
10334   {
10335     /* MOD_0F1C_PREFIX_0 */
10336     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10337     { "nopQ",           { Ev }, 0 },
10338   },
10339   {
10340     /* MOD_0F1E_PREFIX_1 */
10341     { "nopQ",           { Ev }, 0 },
10342     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10343   },
10344   {
10345     /* MOD_0F24 */
10346     { Bad_Opcode },
10347     { "movL",           { Rd, Td }, 0 },
10348   },
10349   {
10350     /* MOD_0F26 */
10351     { Bad_Opcode },
10352     { "movL",           { Td, Rd }, 0 },
10353   },
10354   {
10355     /* MOD_0F2B_PREFIX_0 */
10356     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10357   },
10358   {
10359     /* MOD_0F2B_PREFIX_1 */
10360     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10361   },
10362   {
10363     /* MOD_0F2B_PREFIX_2 */
10364     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10365   },
10366   {
10367     /* MOD_0F2B_PREFIX_3 */
10368     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10369   },
10370   {
10371     /* MOD_0F51 */
10372     { Bad_Opcode },
10373     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10374   },
10375   {
10376     /* MOD_0F71_REG_2 */
10377     { Bad_Opcode },
10378     { "psrlw",          { MS, Ib }, 0 },
10379   },
10380   {
10381     /* MOD_0F71_REG_4 */
10382     { Bad_Opcode },
10383     { "psraw",          { MS, Ib }, 0 },
10384   },
10385   {
10386     /* MOD_0F71_REG_6 */
10387     { Bad_Opcode },
10388     { "psllw",          { MS, Ib }, 0 },
10389   },
10390   {
10391     /* MOD_0F72_REG_2 */
10392     { Bad_Opcode },
10393     { "psrld",          { MS, Ib }, 0 },
10394   },
10395   {
10396     /* MOD_0F72_REG_4 */
10397     { Bad_Opcode },
10398     { "psrad",          { MS, Ib }, 0 },
10399   },
10400   {
10401     /* MOD_0F72_REG_6 */
10402     { Bad_Opcode },
10403     { "pslld",          { MS, Ib }, 0 },
10404   },
10405   {
10406     /* MOD_0F73_REG_2 */
10407     { Bad_Opcode },
10408     { "psrlq",          { MS, Ib }, 0 },
10409   },
10410   {
10411     /* MOD_0F73_REG_3 */
10412     { Bad_Opcode },
10413     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10414   },
10415   {
10416     /* MOD_0F73_REG_6 */
10417     { Bad_Opcode },
10418     { "psllq",          { MS, Ib }, 0 },
10419   },
10420   {
10421     /* MOD_0F73_REG_7 */
10422     { Bad_Opcode },
10423     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10424   },
10425   {
10426     /* MOD_0FAE_REG_0 */
10427     { "fxsave",         { FXSAVE }, 0 },
10428     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10429   },
10430   {
10431     /* MOD_0FAE_REG_1 */
10432     { "fxrstor",        { FXSAVE }, 0 },
10433     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10434   },
10435   {
10436     /* MOD_0FAE_REG_2 */
10437     { "ldmxcsr",        { Md }, 0 },
10438     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10439   },
10440   {
10441     /* MOD_0FAE_REG_3 */
10442     { "stmxcsr",        { Md }, 0 },
10443     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10444   },
10445   {
10446     /* MOD_0FAE_REG_4 */
10447     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10448     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10449   },
10450   {
10451     /* MOD_0FAE_REG_5 */
10452     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10453     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10454   },
10455   {
10456     /* MOD_0FAE_REG_6 */
10457     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10458     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10459   },
10460   {
10461     /* MOD_0FAE_REG_7 */
10462     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10463     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10464   },
10465   {
10466     /* MOD_0FB2 */
10467     { "lssS",           { Gv, Mp }, 0 },
10468   },
10469   {
10470     /* MOD_0FB4 */
10471     { "lfsS",           { Gv, Mp }, 0 },
10472   },
10473   {
10474     /* MOD_0FB5 */
10475     { "lgsS",           { Gv, Mp }, 0 },
10476   },
10477   {
10478     /* MOD_0FC3 */
10479     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10480   },
10481   {
10482     /* MOD_0FC7_REG_3 */
10483     { "xrstors",        { FXSAVE }, 0 },
10484   },
10485   {
10486     /* MOD_0FC7_REG_4 */
10487     { "xsavec",         { FXSAVE }, 0 },
10488   },
10489   {
10490     /* MOD_0FC7_REG_5 */
10491     { "xsaves",         { FXSAVE }, 0 },
10492   },
10493   {
10494     /* MOD_0FC7_REG_6 */
10495     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10496     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10497   },
10498   {
10499     /* MOD_0FC7_REG_7 */
10500     { "vmptrst",        { Mq }, 0 },
10501     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10502   },
10503   {
10504     /* MOD_0FD7 */
10505     { Bad_Opcode },
10506     { "pmovmskb",       { Gdq, MS }, 0 },
10507   },
10508   {
10509     /* MOD_0FE7_PREFIX_2 */
10510     { "movntdq",        { Mx, XM }, 0 },
10511   },
10512   {
10513     /* MOD_0FF0_PREFIX_3 */
10514     { "lddqu",          { XM, M }, 0 },
10515   },
10516   {
10517     /* MOD_0F382A_PREFIX_2 */
10518     { "movntdqa",       { XM, Mx }, 0 },
10519   },
10520   {
10521     /* MOD_0F38F5_PREFIX_2 */
10522     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10523   },
10524   {
10525     /* MOD_0F38F6_PREFIX_0 */
10526     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10527   },
10528   {
10529     /* MOD_0F38F8_PREFIX_1 */
10530     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10531   },
10532   {
10533     /* MOD_0F38F8_PREFIX_2 */
10534     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10535   },
10536   {
10537     /* MOD_0F38F8_PREFIX_3 */
10538     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10539   },
10540   {
10541     /* MOD_0F38F9_PREFIX_0 */
10542     { "movdiri",        { Ev, Gv }, PREFIX_OPCODE },
10543   },
10544   {
10545     /* MOD_62_32BIT */
10546     { "bound{S|}",      { Gv, Ma }, 0 },
10547     { EVEX_TABLE (EVEX_0F) },
10548   },
10549   {
10550     /* MOD_C4_32BIT */
10551     { "lesS",           { Gv, Mp }, 0 },
10552     { VEX_C4_TABLE (VEX_0F) },
10553   },
10554   {
10555     /* MOD_C5_32BIT */
10556     { "ldsS",           { Gv, Mp }, 0 },
10557     { VEX_C5_TABLE (VEX_0F) },
10558   },
10559   {
10560     /* MOD_VEX_0F12_PREFIX_0 */
10561     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10562     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10563   },
10564   {
10565     /* MOD_VEX_0F13 */
10566     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10567   },
10568   {
10569     /* MOD_VEX_0F16_PREFIX_0 */
10570     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10571     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10572   },
10573   {
10574     /* MOD_VEX_0F17 */
10575     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10576   },
10577   {
10578     /* MOD_VEX_0F2B */
10579     { "vmovntpX",       { Mx, XM }, 0 },
10580   },
10581   {
10582     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10583     { Bad_Opcode },
10584     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10585   },
10586   {
10587     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10588     { Bad_Opcode },
10589     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10590   },
10591   {
10592     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10593     { Bad_Opcode },
10594     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10595   },
10596   {
10597     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10598     { Bad_Opcode },
10599     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10600   },
10601   {
10602     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10603     { Bad_Opcode },
10604     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10605   },
10606   {
10607     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10608     { Bad_Opcode },
10609     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10610   },
10611   {
10612     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10613     { Bad_Opcode },
10614     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10615   },
10616   {
10617     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10618     { Bad_Opcode },
10619     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10620   },
10621   {
10622     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10623     { Bad_Opcode },
10624     { "knotw",          { MaskG, MaskR }, 0 },
10625   },
10626   {
10627     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10628     { Bad_Opcode },
10629     { "knotq",          { MaskG, MaskR }, 0 },
10630   },
10631   {
10632     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10633     { Bad_Opcode },
10634     { "knotb",          { MaskG, MaskR }, 0 },
10635   },
10636   {
10637     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10638     { Bad_Opcode },
10639     { "knotd",          { MaskG, MaskR }, 0 },
10640   },
10641   {
10642     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10643     { Bad_Opcode },
10644     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10645   },
10646   {
10647     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10648     { Bad_Opcode },
10649     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10650   },
10651   {
10652     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10653     { Bad_Opcode },
10654     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10655   },
10656   {
10657     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10658     { Bad_Opcode },
10659     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10660   },
10661  {
10662     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10663     { Bad_Opcode },
10664     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10665   },
10666   {
10667     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10668     { Bad_Opcode },
10669     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10670   },
10671   {
10672     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10673     { Bad_Opcode },
10674     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10675   },
10676   {
10677     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10678     { Bad_Opcode },
10679     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10680   },
10681   {
10682     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10683     { Bad_Opcode },
10684     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10685   },
10686   {
10687     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10688     { Bad_Opcode },
10689     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10690   },
10691   {
10692     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10693     { Bad_Opcode },
10694     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10695   },
10696   {
10697     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10698     { Bad_Opcode },
10699     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10700   },
10701   {
10702     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10703     { Bad_Opcode },
10704     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10705   },
10706   {
10707     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10708     { Bad_Opcode },
10709     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10710   },
10711   {
10712     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10713     { Bad_Opcode },
10714     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10715   },
10716   {
10717     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10718     { Bad_Opcode },
10719     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10720   },
10721   {
10722     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10723     { Bad_Opcode },
10724     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10725   },
10726   {
10727     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10728     { Bad_Opcode },
10729     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10730   },
10731   {
10732     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10733     { Bad_Opcode },
10734     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10735   },
10736   {
10737     /* MOD_VEX_0F50 */
10738     { Bad_Opcode },
10739     { "vmovmskpX",      { Gdq, XS }, 0 },
10740   },
10741   {
10742     /* MOD_VEX_0F71_REG_2 */
10743     { Bad_Opcode },
10744     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10745   },
10746   {
10747     /* MOD_VEX_0F71_REG_4 */
10748     { Bad_Opcode },
10749     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10750   },
10751   {
10752     /* MOD_VEX_0F71_REG_6 */
10753     { Bad_Opcode },
10754     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10755   },
10756   {
10757     /* MOD_VEX_0F72_REG_2 */
10758     { Bad_Opcode },
10759     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10760   },
10761   {
10762     /* MOD_VEX_0F72_REG_4 */
10763     { Bad_Opcode },
10764     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10765   },
10766   {
10767     /* MOD_VEX_0F72_REG_6 */
10768     { Bad_Opcode },
10769     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10770   },
10771   {
10772     /* MOD_VEX_0F73_REG_2 */
10773     { Bad_Opcode },
10774     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10775   },
10776   {
10777     /* MOD_VEX_0F73_REG_3 */
10778     { Bad_Opcode },
10779     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10780   },
10781   {
10782     /* MOD_VEX_0F73_REG_6 */
10783     { Bad_Opcode },
10784     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10785   },
10786   {
10787     /* MOD_VEX_0F73_REG_7 */
10788     { Bad_Opcode },
10789     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10790   },
10791   {
10792     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10793     { "kmovw",          { Ew, MaskG }, 0 },
10794     { Bad_Opcode },
10795   },
10796   {
10797     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10798     { "kmovq",          { Eq, MaskG }, 0 },
10799     { Bad_Opcode },
10800   },
10801   {
10802     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10803     { "kmovb",          { Eb, MaskG }, 0 },
10804     { Bad_Opcode },
10805   },
10806   {
10807     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10808     { "kmovd",          { Ed, MaskG }, 0 },
10809     { Bad_Opcode },
10810   },
10811   {
10812     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10813     { Bad_Opcode },
10814     { "kmovw",          { MaskG, Rdq }, 0 },
10815   },
10816   {
10817     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10818     { Bad_Opcode },
10819     { "kmovb",          { MaskG, Rdq }, 0 },
10820   },
10821   {
10822     /* MOD_VEX_0F92_P_3_LEN_0 */
10823     { Bad_Opcode },
10824     { "kmovK",          { MaskG, Rdq }, 0 },
10825   },
10826   {
10827     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10828     { Bad_Opcode },
10829     { "kmovw",          { Gdq, MaskR }, 0 },
10830   },
10831   {
10832     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10833     { Bad_Opcode },
10834     { "kmovb",          { Gdq, MaskR }, 0 },
10835   },
10836   {
10837     /* MOD_VEX_0F93_P_3_LEN_0 */
10838     { Bad_Opcode },
10839     { "kmovK",          { Gdq, MaskR }, 0 },
10840   },
10841   {
10842     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10843     { Bad_Opcode },
10844     { "kortestw", { MaskG, MaskR }, 0 },
10845   },
10846   {
10847     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10848     { Bad_Opcode },
10849     { "kortestq", { MaskG, MaskR }, 0 },
10850   },
10851   {
10852     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10853     { Bad_Opcode },
10854     { "kortestb", { MaskG, MaskR }, 0 },
10855   },
10856   {
10857     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10858     { Bad_Opcode },
10859     { "kortestd", { MaskG, MaskR }, 0 },
10860   },
10861   {
10862     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10863     { Bad_Opcode },
10864     { "ktestw", { MaskG, MaskR }, 0 },
10865   },
10866   {
10867     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10868     { Bad_Opcode },
10869     { "ktestq", { MaskG, MaskR }, 0 },
10870   },
10871   {
10872     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10873     { Bad_Opcode },
10874     { "ktestb", { MaskG, MaskR }, 0 },
10875   },
10876   {
10877     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10878     { Bad_Opcode },
10879     { "ktestd", { MaskG, MaskR }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0FAE_REG_2 */
10883     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10884   },
10885   {
10886     /* MOD_VEX_0FAE_REG_3 */
10887     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0FD7_PREFIX_2 */
10891     { Bad_Opcode },
10892     { "vpmovmskb",      { Gdq, XS }, 0 },
10893   },
10894   {
10895     /* MOD_VEX_0FE7_PREFIX_2 */
10896     { "vmovntdq",       { Mx, XM }, 0 },
10897   },
10898   {
10899     /* MOD_VEX_0FF0_PREFIX_3 */
10900     { "vlddqu",         { XM, M }, 0 },
10901   },
10902   {
10903     /* MOD_VEX_0F381A_PREFIX_2 */
10904     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10905   },
10906   {
10907     /* MOD_VEX_0F382A_PREFIX_2 */
10908     { "vmovntdqa",      { XM, Mx }, 0 },
10909   },
10910   {
10911     /* MOD_VEX_0F382C_PREFIX_2 */
10912     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10913   },
10914   {
10915     /* MOD_VEX_0F382D_PREFIX_2 */
10916     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10917   },
10918   {
10919     /* MOD_VEX_0F382E_PREFIX_2 */
10920     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10921   },
10922   {
10923     /* MOD_VEX_0F382F_PREFIX_2 */
10924     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10925   },
10926   {
10927     /* MOD_VEX_0F385A_PREFIX_2 */
10928     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10929   },
10930   {
10931     /* MOD_VEX_0F388C_PREFIX_2 */
10932     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10933   },
10934   {
10935     /* MOD_VEX_0F388E_PREFIX_2 */
10936     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10937   },
10938   {
10939     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10940     { Bad_Opcode },
10941     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10942   },
10943   {
10944     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10945     { Bad_Opcode },
10946     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10947   },
10948   {
10949     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10950     { Bad_Opcode },
10951     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10952   },
10953   {
10954     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10955     { Bad_Opcode },
10956     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10957   },
10958   {
10959     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10960     { Bad_Opcode },
10961     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10962   },
10963   {
10964     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10965     { Bad_Opcode },
10966     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10967   },
10968   {
10969     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10970     { Bad_Opcode },
10971     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10972   },
10973   {
10974     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10975     { Bad_Opcode },
10976     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10977   },
10978
10979 #include "i386-dis-evex-mod.h"
10980 };
10981
10982 static const struct dis386 rm_table[][8] = {
10983   {
10984     /* RM_C6_REG_7 */
10985     { "xabort",         { Skip_MODRM, Ib }, 0 },
10986   },
10987   {
10988     /* RM_C7_REG_7 */
10989     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
10990   },
10991   {
10992     /* RM_0F01_REG_0 */
10993     { "enclv",          { Skip_MODRM }, 0 },
10994     { "vmcall",         { Skip_MODRM }, 0 },
10995     { "vmlaunch",       { Skip_MODRM }, 0 },
10996     { "vmresume",       { Skip_MODRM }, 0 },
10997     { "vmxoff",         { Skip_MODRM }, 0 },
10998     { "pconfig",        { Skip_MODRM }, 0 },
10999   },
11000   {
11001     /* RM_0F01_REG_1 */
11002     { "monitor",        { { OP_Monitor, 0 } }, 0 },
11003     { "mwait",          { { OP_Mwait, 0 } }, 0 },
11004     { "clac",           { Skip_MODRM }, 0 },
11005     { "stac",           { Skip_MODRM }, 0 },
11006     { Bad_Opcode },
11007     { Bad_Opcode },
11008     { Bad_Opcode },
11009     { "encls",          { Skip_MODRM }, 0 },
11010   },
11011   {
11012     /* RM_0F01_REG_2 */
11013     { "xgetbv",         { Skip_MODRM }, 0 },
11014     { "xsetbv",         { Skip_MODRM }, 0 },
11015     { Bad_Opcode },
11016     { Bad_Opcode },
11017     { "vmfunc",         { Skip_MODRM }, 0 },
11018     { "xend",           { Skip_MODRM }, 0 },
11019     { "xtest",          { Skip_MODRM }, 0 },
11020     { "enclu",          { Skip_MODRM }, 0 },
11021   },
11022   {
11023     /* RM_0F01_REG_3 */
11024     { "vmrun",          { Skip_MODRM }, 0 },
11025     { "vmmcall",        { Skip_MODRM }, 0 },
11026     { "vmload",         { Skip_MODRM }, 0 },
11027     { "vmsave",         { Skip_MODRM }, 0 },
11028     { "stgi",           { Skip_MODRM }, 0 },
11029     { "clgi",           { Skip_MODRM }, 0 },
11030     { "skinit",         { Skip_MODRM }, 0 },
11031     { "invlpga",        { Skip_MODRM }, 0 },
11032   },
11033   {
11034     /* RM_0F01_REG_5_MOD_3 */
11035     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11036     { Bad_Opcode },
11037     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11038     { Bad_Opcode },
11039     { Bad_Opcode },
11040     { Bad_Opcode },
11041     { "rdpkru",         { Skip_MODRM }, 0 },
11042     { "wrpkru",         { Skip_MODRM }, 0 },
11043   },
11044   {
11045     /* RM_0F01_REG_7_MOD_3 */
11046     { "swapgs",         { Skip_MODRM }, 0  },
11047     { "rdtscp",         { Skip_MODRM }, 0  },
11048     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
11049     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
11050     { "clzero",         { Skip_MODRM }, 0  },
11051     { "rdpru",          { Skip_MODRM }, 0  },
11052   },
11053   {
11054     /* RM_0F1E_P_1_MOD_3_REG_7 */
11055     { "nopQ",           { Ev }, 0 },
11056     { "nopQ",           { Ev }, 0 },
11057     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11058     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11059     { "nopQ",           { Ev }, 0 },
11060     { "nopQ",           { Ev }, 0 },
11061     { "nopQ",           { Ev }, 0 },
11062     { "nopQ",           { Ev }, 0 },
11063   },
11064   {
11065     /* RM_0FAE_REG_6_MOD_3 */
11066     { "mfence",         { Skip_MODRM }, 0 },
11067   },
11068   {
11069     /* RM_0FAE_REG_7_MOD_3 */
11070     { "sfence",         { Skip_MODRM }, 0 },
11071
11072   },
11073 };
11074
11075 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11076
11077 /* We use the high bit to indicate different name for the same
11078    prefix.  */
11079 #define REP_PREFIX      (0xf3 | 0x100)
11080 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11081 #define XRELEASE_PREFIX (0xf3 | 0x400)
11082 #define BND_PREFIX      (0xf2 | 0x400)
11083 #define NOTRACK_PREFIX  (0x3e | 0x100)
11084
11085 /* Remember if the current op is a jump instruction.  */
11086 static bfd_boolean op_is_jump = FALSE;
11087
11088 static int
11089 ckprefix (void)
11090 {
11091   int newrex, i, length;
11092   rex = 0;
11093   rex_ignored = 0;
11094   prefixes = 0;
11095   used_prefixes = 0;
11096   rex_used = 0;
11097   last_lock_prefix = -1;
11098   last_repz_prefix = -1;
11099   last_repnz_prefix = -1;
11100   last_data_prefix = -1;
11101   last_addr_prefix = -1;
11102   last_rex_prefix = -1;
11103   last_seg_prefix = -1;
11104   fwait_prefix = -1;
11105   active_seg_prefix = 0;
11106   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11107     all_prefixes[i] = 0;
11108   i = 0;
11109   length = 0;
11110   /* The maximum instruction length is 15bytes.  */
11111   while (length < MAX_CODE_LENGTH - 1)
11112     {
11113       FETCH_DATA (the_info, codep + 1);
11114       newrex = 0;
11115       switch (*codep)
11116         {
11117         /* REX prefixes family.  */
11118         case 0x40:
11119         case 0x41:
11120         case 0x42:
11121         case 0x43:
11122         case 0x44:
11123         case 0x45:
11124         case 0x46:
11125         case 0x47:
11126         case 0x48:
11127         case 0x49:
11128         case 0x4a:
11129         case 0x4b:
11130         case 0x4c:
11131         case 0x4d:
11132         case 0x4e:
11133         case 0x4f:
11134           if (address_mode == mode_64bit)
11135             newrex = *codep;
11136           else
11137             return 1;
11138           last_rex_prefix = i;
11139           break;
11140         case 0xf3:
11141           prefixes |= PREFIX_REPZ;
11142           last_repz_prefix = i;
11143           break;
11144         case 0xf2:
11145           prefixes |= PREFIX_REPNZ;
11146           last_repnz_prefix = i;
11147           break;
11148         case 0xf0:
11149           prefixes |= PREFIX_LOCK;
11150           last_lock_prefix = i;
11151           break;
11152         case 0x2e:
11153           prefixes |= PREFIX_CS;
11154           last_seg_prefix = i;
11155           active_seg_prefix = PREFIX_CS;
11156           break;
11157         case 0x36:
11158           prefixes |= PREFIX_SS;
11159           last_seg_prefix = i;
11160           active_seg_prefix = PREFIX_SS;
11161           break;
11162         case 0x3e:
11163           prefixes |= PREFIX_DS;
11164           last_seg_prefix = i;
11165           active_seg_prefix = PREFIX_DS;
11166           break;
11167         case 0x26:
11168           prefixes |= PREFIX_ES;
11169           last_seg_prefix = i;
11170           active_seg_prefix = PREFIX_ES;
11171           break;
11172         case 0x64:
11173           prefixes |= PREFIX_FS;
11174           last_seg_prefix = i;
11175           active_seg_prefix = PREFIX_FS;
11176           break;
11177         case 0x65:
11178           prefixes |= PREFIX_GS;
11179           last_seg_prefix = i;
11180           active_seg_prefix = PREFIX_GS;
11181           break;
11182         case 0x66:
11183           prefixes |= PREFIX_DATA;
11184           last_data_prefix = i;
11185           break;
11186         case 0x67:
11187           prefixes |= PREFIX_ADDR;
11188           last_addr_prefix = i;
11189           break;
11190         case FWAIT_OPCODE:
11191           /* fwait is really an instruction.  If there are prefixes
11192              before the fwait, they belong to the fwait, *not* to the
11193              following instruction.  */
11194           fwait_prefix = i;
11195           if (prefixes || rex)
11196             {
11197               prefixes |= PREFIX_FWAIT;
11198               codep++;
11199               /* This ensures that the previous REX prefixes are noticed
11200                  as unused prefixes, as in the return case below.  */
11201               rex_used = rex;
11202               return 1;
11203             }
11204           prefixes = PREFIX_FWAIT;
11205           break;
11206         default:
11207           return 1;
11208         }
11209       /* Rex is ignored when followed by another prefix.  */
11210       if (rex)
11211         {
11212           rex_used = rex;
11213           return 1;
11214         }
11215       if (*codep != FWAIT_OPCODE)
11216         all_prefixes[i++] = *codep;
11217       rex = newrex;
11218       codep++;
11219       length++;
11220     }
11221   return 0;
11222 }
11223
11224 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11225    prefix byte.  */
11226
11227 static const char *
11228 prefix_name (int pref, int sizeflag)
11229 {
11230   static const char *rexes [16] =
11231     {
11232       "rex",            /* 0x40 */
11233       "rex.B",          /* 0x41 */
11234       "rex.X",          /* 0x42 */
11235       "rex.XB",         /* 0x43 */
11236       "rex.R",          /* 0x44 */
11237       "rex.RB",         /* 0x45 */
11238       "rex.RX",         /* 0x46 */
11239       "rex.RXB",        /* 0x47 */
11240       "rex.W",          /* 0x48 */
11241       "rex.WB",         /* 0x49 */
11242       "rex.WX",         /* 0x4a */
11243       "rex.WXB",        /* 0x4b */
11244       "rex.WR",         /* 0x4c */
11245       "rex.WRB",        /* 0x4d */
11246       "rex.WRX",        /* 0x4e */
11247       "rex.WRXB",       /* 0x4f */
11248     };
11249
11250   switch (pref)
11251     {
11252     /* REX prefixes family.  */
11253     case 0x40:
11254     case 0x41:
11255     case 0x42:
11256     case 0x43:
11257     case 0x44:
11258     case 0x45:
11259     case 0x46:
11260     case 0x47:
11261     case 0x48:
11262     case 0x49:
11263     case 0x4a:
11264     case 0x4b:
11265     case 0x4c:
11266     case 0x4d:
11267     case 0x4e:
11268     case 0x4f:
11269       return rexes [pref - 0x40];
11270     case 0xf3:
11271       return "repz";
11272     case 0xf2:
11273       return "repnz";
11274     case 0xf0:
11275       return "lock";
11276     case 0x2e:
11277       return "cs";
11278     case 0x36:
11279       return "ss";
11280     case 0x3e:
11281       return "ds";
11282     case 0x26:
11283       return "es";
11284     case 0x64:
11285       return "fs";
11286     case 0x65:
11287       return "gs";
11288     case 0x66:
11289       return (sizeflag & DFLAG) ? "data16" : "data32";
11290     case 0x67:
11291       if (address_mode == mode_64bit)
11292         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11293       else
11294         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11295     case FWAIT_OPCODE:
11296       return "fwait";
11297     case REP_PREFIX:
11298       return "rep";
11299     case XACQUIRE_PREFIX:
11300       return "xacquire";
11301     case XRELEASE_PREFIX:
11302       return "xrelease";
11303     case BND_PREFIX:
11304       return "bnd";
11305     case NOTRACK_PREFIX:
11306       return "notrack";
11307     default:
11308       return NULL;
11309     }
11310 }
11311
11312 static char op_out[MAX_OPERANDS][100];
11313 static int op_ad, op_index[MAX_OPERANDS];
11314 static int two_source_ops;
11315 static bfd_vma op_address[MAX_OPERANDS];
11316 static bfd_vma op_riprel[MAX_OPERANDS];
11317 static bfd_vma start_pc;
11318
11319 /*
11320  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11321  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11322  *   section of the "Virtual 8086 Mode" chapter.)
11323  * 'pc' should be the address of this instruction, it will
11324  *   be used to print the target address if this is a relative jump or call
11325  * The function returns the length of this instruction in bytes.
11326  */
11327
11328 static char intel_syntax;
11329 static char intel_mnemonic = !SYSV386_COMPAT;
11330 static char open_char;
11331 static char close_char;
11332 static char separator_char;
11333 static char scale_char;
11334
11335 enum x86_64_isa
11336 {
11337   amd64 = 1,
11338   intel64
11339 };
11340
11341 static enum x86_64_isa isa64;
11342
11343 /* Here for backwards compatibility.  When gdb stops using
11344    print_insn_i386_att and print_insn_i386_intel these functions can
11345    disappear, and print_insn_i386 be merged into print_insn.  */
11346 int
11347 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11348 {
11349   intel_syntax = 0;
11350
11351   return print_insn (pc, info);
11352 }
11353
11354 int
11355 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11356 {
11357   intel_syntax = 1;
11358
11359   return print_insn (pc, info);
11360 }
11361
11362 int
11363 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11364 {
11365   intel_syntax = -1;
11366
11367   return print_insn (pc, info);
11368 }
11369
11370 void
11371 print_i386_disassembler_options (FILE *stream)
11372 {
11373   fprintf (stream, _("\n\
11374 The following i386/x86-64 specific disassembler options are supported for use\n\
11375 with the -M switch (multiple options should be separated by commas):\n"));
11376
11377   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11378   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11379   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11380   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11381   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11382   fprintf (stream, _("  att-mnemonic\n"
11383                      "              Display instruction in AT&T mnemonic\n"));
11384   fprintf (stream, _("  intel-mnemonic\n"
11385                      "              Display instruction in Intel mnemonic\n"));
11386   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11387   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11388   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11389   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11390   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11391   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11392   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11393   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11394 }
11395
11396 /* Bad opcode.  */
11397 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11398
11399 /* Get a pointer to struct dis386 with a valid name.  */
11400
11401 static const struct dis386 *
11402 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11403 {
11404   int vindex, vex_table_index;
11405
11406   if (dp->name != NULL)
11407     return dp;
11408
11409   switch (dp->op[0].bytemode)
11410     {
11411     case USE_REG_TABLE:
11412       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11413       break;
11414
11415     case USE_MOD_TABLE:
11416       vindex = modrm.mod == 0x3 ? 1 : 0;
11417       dp = &mod_table[dp->op[1].bytemode][vindex];
11418       break;
11419
11420     case USE_RM_TABLE:
11421       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11422       break;
11423
11424     case USE_PREFIX_TABLE:
11425       if (need_vex)
11426         {
11427           /* The prefix in VEX is implicit.  */
11428           switch (vex.prefix)
11429             {
11430             case 0:
11431               vindex = 0;
11432               break;
11433             case REPE_PREFIX_OPCODE:
11434               vindex = 1;
11435               break;
11436             case DATA_PREFIX_OPCODE:
11437               vindex = 2;
11438               break;
11439             case REPNE_PREFIX_OPCODE:
11440               vindex = 3;
11441               break;
11442             default:
11443               abort ();
11444               break;
11445             }
11446         }
11447       else
11448         {
11449           int last_prefix = -1;
11450           int prefix = 0;
11451           vindex = 0;
11452           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11453              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11454              last one wins.  */
11455           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11456             {
11457               if (last_repz_prefix > last_repnz_prefix)
11458                 {
11459                   vindex = 1;
11460                   prefix = PREFIX_REPZ;
11461                   last_prefix = last_repz_prefix;
11462                 }
11463               else
11464                 {
11465                   vindex = 3;
11466                   prefix = PREFIX_REPNZ;
11467                   last_prefix = last_repnz_prefix;
11468                 }
11469
11470               /* Check if prefix should be ignored.  */
11471               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11472                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11473                    & prefix) != 0)
11474                 vindex = 0;
11475             }
11476
11477           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11478             {
11479               vindex = 2;
11480               prefix = PREFIX_DATA;
11481               last_prefix = last_data_prefix;
11482             }
11483
11484           if (vindex != 0)
11485             {
11486               used_prefixes |= prefix;
11487               all_prefixes[last_prefix] = 0;
11488             }
11489         }
11490       dp = &prefix_table[dp->op[1].bytemode][vindex];
11491       break;
11492
11493     case USE_X86_64_TABLE:
11494       vindex = address_mode == mode_64bit ? 1 : 0;
11495       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11496       break;
11497
11498     case USE_3BYTE_TABLE:
11499       FETCH_DATA (info, codep + 2);
11500       vindex = *codep++;
11501       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11502       end_codep = codep;
11503       modrm.mod = (*codep >> 6) & 3;
11504       modrm.reg = (*codep >> 3) & 7;
11505       modrm.rm = *codep & 7;
11506       break;
11507
11508     case USE_VEX_LEN_TABLE:
11509       if (!need_vex)
11510         abort ();
11511
11512       switch (vex.length)
11513         {
11514         case 128:
11515           vindex = 0;
11516           break;
11517         case 256:
11518           vindex = 1;
11519           break;
11520         default:
11521           abort ();
11522           break;
11523         }
11524
11525       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11526       break;
11527
11528     case USE_EVEX_LEN_TABLE:
11529       if (!vex.evex)
11530         abort ();
11531
11532       switch (vex.length)
11533         {
11534         case 128:
11535           vindex = 0;
11536           break;
11537         case 256:
11538           vindex = 1;
11539           break;
11540         case 512:
11541           vindex = 2;
11542           break;
11543         default:
11544           abort ();
11545           break;
11546         }
11547
11548       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11549       break;
11550
11551     case USE_XOP_8F_TABLE:
11552       FETCH_DATA (info, codep + 3);
11553       /* All bits in the REX prefix are ignored.  */
11554       rex_ignored = rex;
11555       rex = ~(*codep >> 5) & 0x7;
11556
11557       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11558       switch ((*codep & 0x1f))
11559         {
11560         default:
11561           dp = &bad_opcode;
11562           return dp;
11563         case 0x8:
11564           vex_table_index = XOP_08;
11565           break;
11566         case 0x9:
11567           vex_table_index = XOP_09;
11568           break;
11569         case 0xa:
11570           vex_table_index = XOP_0A;
11571           break;
11572         }
11573       codep++;
11574       vex.w = *codep & 0x80;
11575       if (vex.w && address_mode == mode_64bit)
11576         rex |= REX_W;
11577
11578       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11579       if (address_mode != mode_64bit)
11580         {
11581           /* In 16/32-bit mode REX_B is silently ignored.  */
11582           rex &= ~REX_B;
11583         }
11584
11585       vex.length = (*codep & 0x4) ? 256 : 128;
11586       switch ((*codep & 0x3))
11587         {
11588         case 0:
11589           break;
11590         case 1:
11591           vex.prefix = DATA_PREFIX_OPCODE;
11592           break;
11593         case 2:
11594           vex.prefix = REPE_PREFIX_OPCODE;
11595           break;
11596         case 3:
11597           vex.prefix = REPNE_PREFIX_OPCODE;
11598           break;
11599         }
11600       need_vex = 1;
11601       need_vex_reg = 1;
11602       codep++;
11603       vindex = *codep++;
11604       dp = &xop_table[vex_table_index][vindex];
11605
11606       end_codep = codep;
11607       FETCH_DATA (info, codep + 1);
11608       modrm.mod = (*codep >> 6) & 3;
11609       modrm.reg = (*codep >> 3) & 7;
11610       modrm.rm = *codep & 7;
11611       break;
11612
11613     case USE_VEX_C4_TABLE:
11614       /* VEX prefix.  */
11615       FETCH_DATA (info, codep + 3);
11616       /* All bits in the REX prefix are ignored.  */
11617       rex_ignored = rex;
11618       rex = ~(*codep >> 5) & 0x7;
11619       switch ((*codep & 0x1f))
11620         {
11621         default:
11622           dp = &bad_opcode;
11623           return dp;
11624         case 0x1:
11625           vex_table_index = VEX_0F;
11626           break;
11627         case 0x2:
11628           vex_table_index = VEX_0F38;
11629           break;
11630         case 0x3:
11631           vex_table_index = VEX_0F3A;
11632           break;
11633         }
11634       codep++;
11635       vex.w = *codep & 0x80;
11636       if (address_mode == mode_64bit)
11637         {
11638           if (vex.w)
11639             rex |= REX_W;
11640         }
11641       else
11642         {
11643           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11644              is ignored, other REX bits are 0 and the highest bit in
11645              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11646           rex = 0;
11647         }
11648       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11649       vex.length = (*codep & 0x4) ? 256 : 128;
11650       switch ((*codep & 0x3))
11651         {
11652         case 0:
11653           break;
11654         case 1:
11655           vex.prefix = DATA_PREFIX_OPCODE;
11656           break;
11657         case 2:
11658           vex.prefix = REPE_PREFIX_OPCODE;
11659           break;
11660         case 3:
11661           vex.prefix = REPNE_PREFIX_OPCODE;
11662           break;
11663         }
11664       need_vex = 1;
11665       need_vex_reg = 1;
11666       codep++;
11667       vindex = *codep++;
11668       dp = &vex_table[vex_table_index][vindex];
11669       end_codep = codep;
11670       /* There is no MODRM byte for VEX0F 77.  */
11671       if (vex_table_index != VEX_0F || vindex != 0x77)
11672         {
11673           FETCH_DATA (info, codep + 1);
11674           modrm.mod = (*codep >> 6) & 3;
11675           modrm.reg = (*codep >> 3) & 7;
11676           modrm.rm = *codep & 7;
11677         }
11678       break;
11679
11680     case USE_VEX_C5_TABLE:
11681       /* VEX prefix.  */
11682       FETCH_DATA (info, codep + 2);
11683       /* All bits in the REX prefix are ignored.  */
11684       rex_ignored = rex;
11685       rex = (*codep & 0x80) ? 0 : REX_R;
11686
11687       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11688          VEX.vvvv is 1.  */
11689       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11690       vex.length = (*codep & 0x4) ? 256 : 128;
11691       switch ((*codep & 0x3))
11692         {
11693         case 0:
11694           break;
11695         case 1:
11696           vex.prefix = DATA_PREFIX_OPCODE;
11697           break;
11698         case 2:
11699           vex.prefix = REPE_PREFIX_OPCODE;
11700           break;
11701         case 3:
11702           vex.prefix = REPNE_PREFIX_OPCODE;
11703           break;
11704         }
11705       need_vex = 1;
11706       need_vex_reg = 1;
11707       codep++;
11708       vindex = *codep++;
11709       dp = &vex_table[dp->op[1].bytemode][vindex];
11710       end_codep = codep;
11711       /* There is no MODRM byte for VEX 77.  */
11712       if (vindex != 0x77)
11713         {
11714           FETCH_DATA (info, codep + 1);
11715           modrm.mod = (*codep >> 6) & 3;
11716           modrm.reg = (*codep >> 3) & 7;
11717           modrm.rm = *codep & 7;
11718         }
11719       break;
11720
11721     case USE_VEX_W_TABLE:
11722       if (!need_vex)
11723         abort ();
11724
11725       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11726       break;
11727
11728     case USE_EVEX_TABLE:
11729       two_source_ops = 0;
11730       /* EVEX prefix.  */
11731       vex.evex = 1;
11732       FETCH_DATA (info, codep + 4);
11733       /* All bits in the REX prefix are ignored.  */
11734       rex_ignored = rex;
11735       /* The first byte after 0x62.  */
11736       rex = ~(*codep >> 5) & 0x7;
11737       vex.r = *codep & 0x10;
11738       switch ((*codep & 0xf))
11739         {
11740         default:
11741           return &bad_opcode;
11742         case 0x1:
11743           vex_table_index = EVEX_0F;
11744           break;
11745         case 0x2:
11746           vex_table_index = EVEX_0F38;
11747           break;
11748         case 0x3:
11749           vex_table_index = EVEX_0F3A;
11750           break;
11751         }
11752
11753       /* The second byte after 0x62.  */
11754       codep++;
11755       vex.w = *codep & 0x80;
11756       if (vex.w && address_mode == mode_64bit)
11757         rex |= REX_W;
11758
11759       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11760
11761       /* The U bit.  */
11762       if (!(*codep & 0x4))
11763         return &bad_opcode;
11764
11765       switch ((*codep & 0x3))
11766         {
11767         case 0:
11768           break;
11769         case 1:
11770           vex.prefix = DATA_PREFIX_OPCODE;
11771           break;
11772         case 2:
11773           vex.prefix = REPE_PREFIX_OPCODE;
11774           break;
11775         case 3:
11776           vex.prefix = REPNE_PREFIX_OPCODE;
11777           break;
11778         }
11779
11780       /* The third byte after 0x62.  */
11781       codep++;
11782
11783       /* Remember the static rounding bits.  */
11784       vex.ll = (*codep >> 5) & 3;
11785       vex.b = (*codep & 0x10) != 0;
11786
11787       vex.v = *codep & 0x8;
11788       vex.mask_register_specifier = *codep & 0x7;
11789       vex.zeroing = *codep & 0x80;
11790
11791       if (address_mode != mode_64bit)
11792         {
11793           /* In 16/32-bit mode silently ignore following bits.  */
11794           rex &= ~REX_B;
11795           vex.r = 1;
11796           vex.v = 1;
11797         }
11798
11799       need_vex = 1;
11800       need_vex_reg = 1;
11801       codep++;
11802       vindex = *codep++;
11803       dp = &evex_table[vex_table_index][vindex];
11804       end_codep = codep;
11805       FETCH_DATA (info, codep + 1);
11806       modrm.mod = (*codep >> 6) & 3;
11807       modrm.reg = (*codep >> 3) & 7;
11808       modrm.rm = *codep & 7;
11809
11810       /* Set vector length.  */
11811       if (modrm.mod == 3 && vex.b)
11812         vex.length = 512;
11813       else
11814         {
11815           switch (vex.ll)
11816             {
11817             case 0x0:
11818               vex.length = 128;
11819               break;
11820             case 0x1:
11821               vex.length = 256;
11822               break;
11823             case 0x2:
11824               vex.length = 512;
11825               break;
11826             default:
11827               return &bad_opcode;
11828             }
11829         }
11830       break;
11831
11832     case 0:
11833       dp = &bad_opcode;
11834       break;
11835
11836     default:
11837       abort ();
11838     }
11839
11840   if (dp->name != NULL)
11841     return dp;
11842   else
11843     return get_valid_dis386 (dp, info);
11844 }
11845
11846 static void
11847 get_sib (disassemble_info *info, int sizeflag)
11848 {
11849   /* If modrm.mod == 3, operand must be register.  */
11850   if (need_modrm
11851       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11852       && modrm.mod != 3
11853       && modrm.rm == 4)
11854     {
11855       FETCH_DATA (info, codep + 2);
11856       sib.index = (codep [1] >> 3) & 7;
11857       sib.scale = (codep [1] >> 6) & 3;
11858       sib.base = codep [1] & 7;
11859     }
11860 }
11861
11862 static int
11863 print_insn (bfd_vma pc, disassemble_info *info)
11864 {
11865   const struct dis386 *dp;
11866   int i;
11867   char *op_txt[MAX_OPERANDS];
11868   int needcomma;
11869   int sizeflag, orig_sizeflag;
11870   const char *p;
11871   struct dis_private priv;
11872   int prefix_length;
11873
11874   priv.orig_sizeflag = AFLAG | DFLAG;
11875   if ((info->mach & bfd_mach_i386_i386) != 0)
11876     address_mode = mode_32bit;
11877   else if (info->mach == bfd_mach_i386_i8086)
11878     {
11879       address_mode = mode_16bit;
11880       priv.orig_sizeflag = 0;
11881     }
11882   else
11883     address_mode = mode_64bit;
11884
11885   if (intel_syntax == (char) -1)
11886     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11887
11888   for (p = info->disassembler_options; p != NULL; )
11889     {
11890       if (CONST_STRNEQ (p, "amd64"))
11891         isa64 = amd64;
11892       else if (CONST_STRNEQ (p, "intel64"))
11893         isa64 = intel64;
11894       else if (CONST_STRNEQ (p, "x86-64"))
11895         {
11896           address_mode = mode_64bit;
11897           priv.orig_sizeflag = AFLAG | DFLAG;
11898         }
11899       else if (CONST_STRNEQ (p, "i386"))
11900         {
11901           address_mode = mode_32bit;
11902           priv.orig_sizeflag = AFLAG | DFLAG;
11903         }
11904       else if (CONST_STRNEQ (p, "i8086"))
11905         {
11906           address_mode = mode_16bit;
11907           priv.orig_sizeflag = 0;
11908         }
11909       else if (CONST_STRNEQ (p, "intel"))
11910         {
11911           intel_syntax = 1;
11912           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11913             intel_mnemonic = 1;
11914         }
11915       else if (CONST_STRNEQ (p, "att"))
11916         {
11917           intel_syntax = 0;
11918           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11919             intel_mnemonic = 0;
11920         }
11921       else if (CONST_STRNEQ (p, "addr"))
11922         {
11923           if (address_mode == mode_64bit)
11924             {
11925               if (p[4] == '3' && p[5] == '2')
11926                 priv.orig_sizeflag &= ~AFLAG;
11927               else if (p[4] == '6' && p[5] == '4')
11928                 priv.orig_sizeflag |= AFLAG;
11929             }
11930           else
11931             {
11932               if (p[4] == '1' && p[5] == '6')
11933                 priv.orig_sizeflag &= ~AFLAG;
11934               else if (p[4] == '3' && p[5] == '2')
11935                 priv.orig_sizeflag |= AFLAG;
11936             }
11937         }
11938       else if (CONST_STRNEQ (p, "data"))
11939         {
11940           if (p[4] == '1' && p[5] == '6')
11941             priv.orig_sizeflag &= ~DFLAG;
11942           else if (p[4] == '3' && p[5] == '2')
11943             priv.orig_sizeflag |= DFLAG;
11944         }
11945       else if (CONST_STRNEQ (p, "suffix"))
11946         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11947
11948       p = strchr (p, ',');
11949       if (p != NULL)
11950         p++;
11951     }
11952
11953   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11954     {
11955       (*info->fprintf_func) (info->stream,
11956                              _("64-bit address is disabled"));
11957       return -1;
11958     }
11959
11960   if (intel_syntax)
11961     {
11962       names64 = intel_names64;
11963       names32 = intel_names32;
11964       names16 = intel_names16;
11965       names8 = intel_names8;
11966       names8rex = intel_names8rex;
11967       names_seg = intel_names_seg;
11968       names_mm = intel_names_mm;
11969       names_bnd = intel_names_bnd;
11970       names_xmm = intel_names_xmm;
11971       names_ymm = intel_names_ymm;
11972       names_zmm = intel_names_zmm;
11973       index64 = intel_index64;
11974       index32 = intel_index32;
11975       names_mask = intel_names_mask;
11976       index16 = intel_index16;
11977       open_char = '[';
11978       close_char = ']';
11979       separator_char = '+';
11980       scale_char = '*';
11981     }
11982   else
11983     {
11984       names64 = att_names64;
11985       names32 = att_names32;
11986       names16 = att_names16;
11987       names8 = att_names8;
11988       names8rex = att_names8rex;
11989       names_seg = att_names_seg;
11990       names_mm = att_names_mm;
11991       names_bnd = att_names_bnd;
11992       names_xmm = att_names_xmm;
11993       names_ymm = att_names_ymm;
11994       names_zmm = att_names_zmm;
11995       index64 = att_index64;
11996       index32 = att_index32;
11997       names_mask = att_names_mask;
11998       index16 = att_index16;
11999       open_char = '(';
12000       close_char =  ')';
12001       separator_char = ',';
12002       scale_char = ',';
12003     }
12004
12005   /* The output looks better if we put 7 bytes on a line, since that
12006      puts most long word instructions on a single line.  Use 8 bytes
12007      for Intel L1OM.  */
12008   if ((info->mach & bfd_mach_l1om) != 0)
12009     info->bytes_per_line = 8;
12010   else
12011     info->bytes_per_line = 7;
12012
12013   info->private_data = &priv;
12014   priv.max_fetched = priv.the_buffer;
12015   priv.insn_start = pc;
12016
12017   obuf[0] = 0;
12018   for (i = 0; i < MAX_OPERANDS; ++i)
12019     {
12020       op_out[i][0] = 0;
12021       op_index[i] = -1;
12022     }
12023
12024   the_info = info;
12025   start_pc = pc;
12026   start_codep = priv.the_buffer;
12027   codep = priv.the_buffer;
12028
12029   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12030     {
12031       const char *name;
12032
12033       /* Getting here means we tried for data but didn't get it.  That
12034          means we have an incomplete instruction of some sort.  Just
12035          print the first byte as a prefix or a .byte pseudo-op.  */
12036       if (codep > priv.the_buffer)
12037         {
12038           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12039           if (name != NULL)
12040             (*info->fprintf_func) (info->stream, "%s", name);
12041           else
12042             {
12043               /* Just print the first byte as a .byte instruction.  */
12044               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12045                                      (unsigned int) priv.the_buffer[0]);
12046             }
12047
12048           return 1;
12049         }
12050
12051       return -1;
12052     }
12053
12054   obufp = obuf;
12055   sizeflag = priv.orig_sizeflag;
12056
12057   if (!ckprefix () || rex_used)
12058     {
12059       /* Too many prefixes or unused REX prefixes.  */
12060       for (i = 0;
12061            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12062            i++)
12063         (*info->fprintf_func) (info->stream, "%s%s",
12064                                i == 0 ? "" : " ",
12065                                prefix_name (all_prefixes[i], sizeflag));
12066       return i;
12067     }
12068
12069   insn_codep = codep;
12070
12071   FETCH_DATA (info, codep + 1);
12072   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12073
12074   if (((prefixes & PREFIX_FWAIT)
12075        && ((*codep < 0xd8) || (*codep > 0xdf))))
12076     {
12077       /* Handle prefixes before fwait.  */
12078       for (i = 0; i < fwait_prefix && all_prefixes[i];
12079            i++)
12080         (*info->fprintf_func) (info->stream, "%s ",
12081                                prefix_name (all_prefixes[i], sizeflag));
12082       (*info->fprintf_func) (info->stream, "fwait");
12083       return i + 1;
12084     }
12085
12086   if (*codep == 0x0f)
12087     {
12088       unsigned char threebyte;
12089
12090       codep++;
12091       FETCH_DATA (info, codep + 1);
12092       threebyte = *codep;
12093       dp = &dis386_twobyte[threebyte];
12094       need_modrm = twobyte_has_modrm[*codep];
12095       codep++;
12096     }
12097   else
12098     {
12099       dp = &dis386[*codep];
12100       need_modrm = onebyte_has_modrm[*codep];
12101       codep++;
12102     }
12103
12104   /* Save sizeflag for printing the extra prefixes later before updating
12105      it for mnemonic and operand processing.  The prefix names depend
12106      only on the address mode.  */
12107   orig_sizeflag = sizeflag;
12108   if (prefixes & PREFIX_ADDR)
12109     sizeflag ^= AFLAG;
12110   if ((prefixes & PREFIX_DATA))
12111     sizeflag ^= DFLAG;
12112
12113   end_codep = codep;
12114   if (need_modrm)
12115     {
12116       FETCH_DATA (info, codep + 1);
12117       modrm.mod = (*codep >> 6) & 3;
12118       modrm.reg = (*codep >> 3) & 7;
12119       modrm.rm = *codep & 7;
12120     }
12121
12122   need_vex = 0;
12123   need_vex_reg = 0;
12124   vex_w_done = 0;
12125   memset (&vex, 0, sizeof (vex));
12126
12127   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12128     {
12129       get_sib (info, sizeflag);
12130       dofloat (sizeflag);
12131     }
12132   else
12133     {
12134       dp = get_valid_dis386 (dp, info);
12135       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12136         {
12137           get_sib (info, sizeflag);
12138           for (i = 0; i < MAX_OPERANDS; ++i)
12139             {
12140               obufp = op_out[i];
12141               op_ad = MAX_OPERANDS - 1 - i;
12142               if (dp->op[i].rtn)
12143                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12144               /* For EVEX instruction after the last operand masking
12145                  should be printed.  */
12146               if (i == 0 && vex.evex)
12147                 {
12148                   /* Don't print {%k0}.  */
12149                   if (vex.mask_register_specifier)
12150                     {
12151                       oappend ("{");
12152                       oappend (names_mask[vex.mask_register_specifier]);
12153                       oappend ("}");
12154                     }
12155                   if (vex.zeroing)
12156                     oappend ("{z}");
12157                 }
12158             }
12159         }
12160     }
12161
12162   /* Clear instruction information.  */
12163   if (the_info)
12164     {
12165       the_info->insn_info_valid = 0;
12166       the_info->branch_delay_insns = 0;
12167       the_info->data_size = 0;
12168       the_info->insn_type = dis_noninsn;
12169       the_info->target = 0;
12170       the_info->target2 = 0;
12171     }
12172
12173   /* Reset jump operation indicator.  */
12174   op_is_jump = FALSE;
12175
12176   {
12177     int jump_detection = 0;
12178
12179     /* Extract flags.  */
12180     for (i = 0; i < MAX_OPERANDS; ++i)
12181       {
12182         if ((dp->op[i].rtn == OP_J)
12183             || (dp->op[i].rtn == OP_indirE))
12184           jump_detection |= 1;
12185         else if ((dp->op[i].rtn == BND_Fixup)
12186                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
12187           jump_detection |= 2;
12188         else if ((dp->op[i].bytemode == cond_jump_mode)
12189                  || (dp->op[i].bytemode == loop_jcxz_mode))
12190           jump_detection |= 4;
12191       }
12192
12193     /* Determine if this is a jump or branch.  */
12194     if ((jump_detection & 0x3) == 0x3)
12195       {
12196         op_is_jump = TRUE;
12197         if (jump_detection & 0x4)
12198           the_info->insn_type = dis_condbranch;
12199         else
12200           the_info->insn_type =
12201             (dp->name && !strncmp(dp->name, "call", 4))
12202             ? dis_jsr : dis_branch;
12203       }
12204   }
12205
12206   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12207      are all 0s in inverted form.  */
12208   if (need_vex && vex.register_specifier != 0)
12209     {
12210       (*info->fprintf_func) (info->stream, "(bad)");
12211       return end_codep - priv.the_buffer;
12212     }
12213
12214   /* Check if the REX prefix is used.  */
12215   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12216     all_prefixes[last_rex_prefix] = 0;
12217
12218   /* Check if the SEG prefix is used.  */
12219   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12220                    | PREFIX_FS | PREFIX_GS)) != 0
12221       && (used_prefixes & active_seg_prefix) != 0)
12222     all_prefixes[last_seg_prefix] = 0;
12223
12224   /* Check if the ADDR prefix is used.  */
12225   if ((prefixes & PREFIX_ADDR) != 0
12226       && (used_prefixes & PREFIX_ADDR) != 0)
12227     all_prefixes[last_addr_prefix] = 0;
12228
12229   /* Check if the DATA prefix is used.  */
12230   if ((prefixes & PREFIX_DATA) != 0
12231       && (used_prefixes & PREFIX_DATA) != 0)
12232     all_prefixes[last_data_prefix] = 0;
12233
12234   /* Print the extra prefixes.  */
12235   prefix_length = 0;
12236   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12237     if (all_prefixes[i])
12238       {
12239         const char *name;
12240         name = prefix_name (all_prefixes[i], orig_sizeflag);
12241         if (name == NULL)
12242           abort ();
12243         prefix_length += strlen (name) + 1;
12244         (*info->fprintf_func) (info->stream, "%s ", name);
12245       }
12246
12247   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12248      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12249      used by putop and MMX/SSE operand and may be overriden by the
12250      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12251      separately.  */
12252   if (dp->prefix_requirement == PREFIX_OPCODE
12253       && dp != &bad_opcode
12254       && (((prefixes
12255             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12256            && (used_prefixes
12257                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12258           || ((((prefixes
12259                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12260                 == PREFIX_DATA)
12261                && (used_prefixes & PREFIX_DATA) == 0))))
12262     {
12263       (*info->fprintf_func) (info->stream, "(bad)");
12264       return end_codep - priv.the_buffer;
12265     }
12266
12267   /* Check maximum code length.  */
12268   if ((codep - start_codep) > MAX_CODE_LENGTH)
12269     {
12270       (*info->fprintf_func) (info->stream, "(bad)");
12271       return MAX_CODE_LENGTH;
12272     }
12273
12274   obufp = mnemonicendp;
12275   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12276     oappend (" ");
12277   oappend (" ");
12278   (*info->fprintf_func) (info->stream, "%s", obuf);
12279
12280   /* The enter and bound instructions are printed with operands in the same
12281      order as the intel book; everything else is printed in reverse order.  */
12282   if (intel_syntax || two_source_ops)
12283     {
12284       bfd_vma riprel;
12285
12286       for (i = 0; i < MAX_OPERANDS; ++i)
12287         op_txt[i] = op_out[i];
12288
12289       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12290           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12291         {
12292           op_txt[2] = op_out[3];
12293           op_txt[3] = op_out[2];
12294         }
12295
12296       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12297         {
12298           op_ad = op_index[i];
12299           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12300           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12301           riprel = op_riprel[i];
12302           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12303           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12304         }
12305     }
12306   else
12307     {
12308       for (i = 0; i < MAX_OPERANDS; ++i)
12309         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12310     }
12311
12312   needcomma = 0;
12313   for (i = 0; i < MAX_OPERANDS; ++i)
12314     if (*op_txt[i])
12315       {
12316         if (needcomma)
12317           (*info->fprintf_func) (info->stream, ",");
12318         if (op_index[i] != -1 && !op_riprel[i])
12319           {
12320             bfd_vma target = (bfd_vma) op_address[op_index[i]];
12321
12322             if (the_info && op_is_jump)
12323               {
12324                 the_info->insn_info_valid = 1;
12325                 the_info->branch_delay_insns = 0;
12326                 the_info->data_size = 0;
12327                 the_info->target = target;
12328                 the_info->target2 = 0;
12329               }
12330             (*info->print_address_func) (target, info);
12331           }
12332         else
12333           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12334         needcomma = 1;
12335       }
12336
12337   for (i = 0; i < MAX_OPERANDS; i++)
12338     if (op_index[i] != -1 && op_riprel[i])
12339       {
12340         (*info->fprintf_func) (info->stream, "        # ");
12341         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12342                                                 + op_address[op_index[i]]), info);
12343         break;
12344       }
12345   return codep - priv.the_buffer;
12346 }
12347
12348 static const char *float_mem[] = {
12349   /* d8 */
12350   "fadd{s|}",
12351   "fmul{s|}",
12352   "fcom{s|}",
12353   "fcomp{s|}",
12354   "fsub{s|}",
12355   "fsubr{s|}",
12356   "fdiv{s|}",
12357   "fdivr{s|}",
12358   /* d9 */
12359   "fld{s|}",
12360   "(bad)",
12361   "fst{s|}",
12362   "fstp{s|}",
12363   "fldenvIC",
12364   "fldcw",
12365   "fNstenvIC",
12366   "fNstcw",
12367   /* da */
12368   "fiadd{l|}",
12369   "fimul{l|}",
12370   "ficom{l|}",
12371   "ficomp{l|}",
12372   "fisub{l|}",
12373   "fisubr{l|}",
12374   "fidiv{l|}",
12375   "fidivr{l|}",
12376   /* db */
12377   "fild{l|}",
12378   "fisttp{l|}",
12379   "fist{l|}",
12380   "fistp{l|}",
12381   "(bad)",
12382   "fld{t||t|}",
12383   "(bad)",
12384   "fstp{t||t|}",
12385   /* dc */
12386   "fadd{l|}",
12387   "fmul{l|}",
12388   "fcom{l|}",
12389   "fcomp{l|}",
12390   "fsub{l|}",
12391   "fsubr{l|}",
12392   "fdiv{l|}",
12393   "fdivr{l|}",
12394   /* dd */
12395   "fld{l|}",
12396   "fisttp{ll|}",
12397   "fst{l||}",
12398   "fstp{l|}",
12399   "frstorIC",
12400   "(bad)",
12401   "fNsaveIC",
12402   "fNstsw",
12403   /* de */
12404   "fiadd{s|}",
12405   "fimul{s|}",
12406   "ficom{s|}",
12407   "ficomp{s|}",
12408   "fisub{s|}",
12409   "fisubr{s|}",
12410   "fidiv{s|}",
12411   "fidivr{s|}",
12412   /* df */
12413   "fild{s|}",
12414   "fisttp{s|}",
12415   "fist{s|}",
12416   "fistp{s|}",
12417   "fbld",
12418   "fild{ll|}",
12419   "fbstp",
12420   "fistp{ll|}",
12421 };
12422
12423 static const unsigned char float_mem_mode[] = {
12424   /* d8 */
12425   d_mode,
12426   d_mode,
12427   d_mode,
12428   d_mode,
12429   d_mode,
12430   d_mode,
12431   d_mode,
12432   d_mode,
12433   /* d9 */
12434   d_mode,
12435   0,
12436   d_mode,
12437   d_mode,
12438   0,
12439   w_mode,
12440   0,
12441   w_mode,
12442   /* da */
12443   d_mode,
12444   d_mode,
12445   d_mode,
12446   d_mode,
12447   d_mode,
12448   d_mode,
12449   d_mode,
12450   d_mode,
12451   /* db */
12452   d_mode,
12453   d_mode,
12454   d_mode,
12455   d_mode,
12456   0,
12457   t_mode,
12458   0,
12459   t_mode,
12460   /* dc */
12461   q_mode,
12462   q_mode,
12463   q_mode,
12464   q_mode,
12465   q_mode,
12466   q_mode,
12467   q_mode,
12468   q_mode,
12469   /* dd */
12470   q_mode,
12471   q_mode,
12472   q_mode,
12473   q_mode,
12474   0,
12475   0,
12476   0,
12477   w_mode,
12478   /* de */
12479   w_mode,
12480   w_mode,
12481   w_mode,
12482   w_mode,
12483   w_mode,
12484   w_mode,
12485   w_mode,
12486   w_mode,
12487   /* df */
12488   w_mode,
12489   w_mode,
12490   w_mode,
12491   w_mode,
12492   t_mode,
12493   q_mode,
12494   t_mode,
12495   q_mode
12496 };
12497
12498 #define ST { OP_ST, 0 }
12499 #define STi { OP_STi, 0 }
12500
12501 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12502 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12503 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12504 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12505 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12506 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12507 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12508 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12509 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12510
12511 static const struct dis386 float_reg[][8] = {
12512   /* d8 */
12513   {
12514     { "fadd",   { ST, STi }, 0 },
12515     { "fmul",   { ST, STi }, 0 },
12516     { "fcom",   { STi }, 0 },
12517     { "fcomp",  { STi }, 0 },
12518     { "fsub",   { ST, STi }, 0 },
12519     { "fsubr",  { ST, STi }, 0 },
12520     { "fdiv",   { ST, STi }, 0 },
12521     { "fdivr",  { ST, STi }, 0 },
12522   },
12523   /* d9 */
12524   {
12525     { "fld",    { STi }, 0 },
12526     { "fxch",   { STi }, 0 },
12527     { FGRPd9_2 },
12528     { Bad_Opcode },
12529     { FGRPd9_4 },
12530     { FGRPd9_5 },
12531     { FGRPd9_6 },
12532     { FGRPd9_7 },
12533   },
12534   /* da */
12535   {
12536     { "fcmovb", { ST, STi }, 0 },
12537     { "fcmove", { ST, STi }, 0 },
12538     { "fcmovbe",{ ST, STi }, 0 },
12539     { "fcmovu", { ST, STi }, 0 },
12540     { Bad_Opcode },
12541     { FGRPda_5 },
12542     { Bad_Opcode },
12543     { Bad_Opcode },
12544   },
12545   /* db */
12546   {
12547     { "fcmovnb",{ ST, STi }, 0 },
12548     { "fcmovne",{ ST, STi }, 0 },
12549     { "fcmovnbe",{ ST, STi }, 0 },
12550     { "fcmovnu",{ ST, STi }, 0 },
12551     { FGRPdb_4 },
12552     { "fucomi", { ST, STi }, 0 },
12553     { "fcomi",  { ST, STi }, 0 },
12554     { Bad_Opcode },
12555   },
12556   /* dc */
12557   {
12558     { "fadd",   { STi, ST }, 0 },
12559     { "fmul",   { STi, ST }, 0 },
12560     { Bad_Opcode },
12561     { Bad_Opcode },
12562     { "fsub{!M|r}",     { STi, ST }, 0 },
12563     { "fsub{M|}",       { STi, ST }, 0 },
12564     { "fdiv{!M|r}",     { STi, ST }, 0 },
12565     { "fdiv{M|}",       { STi, ST }, 0 },
12566   },
12567   /* dd */
12568   {
12569     { "ffree",  { STi }, 0 },
12570     { Bad_Opcode },
12571     { "fst",    { STi }, 0 },
12572     { "fstp",   { STi }, 0 },
12573     { "fucom",  { STi }, 0 },
12574     { "fucomp", { STi }, 0 },
12575     { Bad_Opcode },
12576     { Bad_Opcode },
12577   },
12578   /* de */
12579   {
12580     { "faddp",  { STi, ST }, 0 },
12581     { "fmulp",  { STi, ST }, 0 },
12582     { Bad_Opcode },
12583     { FGRPde_3 },
12584     { "fsub{!M|r}p",    { STi, ST }, 0 },
12585     { "fsub{M|}p",      { STi, ST }, 0 },
12586     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12587     { "fdiv{M|}p",      { STi, ST }, 0 },
12588   },
12589   /* df */
12590   {
12591     { "ffreep", { STi }, 0 },
12592     { Bad_Opcode },
12593     { Bad_Opcode },
12594     { Bad_Opcode },
12595     { FGRPdf_4 },
12596     { "fucomip", { ST, STi }, 0 },
12597     { "fcomip", { ST, STi }, 0 },
12598     { Bad_Opcode },
12599   },
12600 };
12601
12602 static char *fgrps[][8] = {
12603   /* Bad opcode 0 */
12604   {
12605     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12606   },
12607
12608   /* d9_2  1 */
12609   {
12610     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12611   },
12612
12613   /* d9_4  2 */
12614   {
12615     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12616   },
12617
12618   /* d9_5  3 */
12619   {
12620     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12621   },
12622
12623   /* d9_6  4 */
12624   {
12625     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12626   },
12627
12628   /* d9_7  5 */
12629   {
12630     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12631   },
12632
12633   /* da_5  6 */
12634   {
12635     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12636   },
12637
12638   /* db_4  7 */
12639   {
12640     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12641     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12642   },
12643
12644   /* de_3  8 */
12645   {
12646     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12647   },
12648
12649   /* df_4  9 */
12650   {
12651     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12652   },
12653 };
12654
12655 static void
12656 swap_operand (void)
12657 {
12658   mnemonicendp[0] = '.';
12659   mnemonicendp[1] = 's';
12660   mnemonicendp += 2;
12661 }
12662
12663 static void
12664 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12665                int sizeflag ATTRIBUTE_UNUSED)
12666 {
12667   /* Skip mod/rm byte.  */
12668   MODRM_CHECK;
12669   codep++;
12670 }
12671
12672 static void
12673 dofloat (int sizeflag)
12674 {
12675   const struct dis386 *dp;
12676   unsigned char floatop;
12677
12678   floatop = codep[-1];
12679
12680   if (modrm.mod != 3)
12681     {
12682       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12683
12684       putop (float_mem[fp_indx], sizeflag);
12685       obufp = op_out[0];
12686       op_ad = 2;
12687       OP_E (float_mem_mode[fp_indx], sizeflag);
12688       return;
12689     }
12690   /* Skip mod/rm byte.  */
12691   MODRM_CHECK;
12692   codep++;
12693
12694   dp = &float_reg[floatop - 0xd8][modrm.reg];
12695   if (dp->name == NULL)
12696     {
12697       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12698
12699       /* Instruction fnstsw is only one with strange arg.  */
12700       if (floatop == 0xdf && codep[-1] == 0xe0)
12701         strcpy (op_out[0], names16[0]);
12702     }
12703   else
12704     {
12705       putop (dp->name, sizeflag);
12706
12707       obufp = op_out[0];
12708       op_ad = 2;
12709       if (dp->op[0].rtn)
12710         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12711
12712       obufp = op_out[1];
12713       op_ad = 1;
12714       if (dp->op[1].rtn)
12715         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12716     }
12717 }
12718
12719 /* Like oappend (below), but S is a string starting with '%'.
12720    In Intel syntax, the '%' is elided.  */
12721 static void
12722 oappend_maybe_intel (const char *s)
12723 {
12724   oappend (s + intel_syntax);
12725 }
12726
12727 static void
12728 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12729 {
12730   oappend_maybe_intel ("%st");
12731 }
12732
12733 static void
12734 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12735 {
12736   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12737   oappend_maybe_intel (scratchbuf);
12738 }
12739
12740 /* Capital letters in template are macros.  */
12741 static int
12742 putop (const char *in_template, int sizeflag)
12743 {
12744   const char *p;
12745   int alt = 0;
12746   int cond = 1;
12747   unsigned int l = 0, len = 1;
12748   char last[4];
12749
12750 #define SAVE_LAST(c)                    \
12751   if (l < len && l < sizeof (last))     \
12752     last[l++] = c;                      \
12753   else                                  \
12754     abort ();
12755
12756   for (p = in_template; *p; p++)
12757     {
12758       switch (*p)
12759         {
12760         default:
12761           *obufp++ = *p;
12762           break;
12763         case '%':
12764           len++;
12765           break;
12766         case '!':
12767           cond = 0;
12768           break;
12769         case '{':
12770           if (intel_syntax)
12771             {
12772               while (*++p != '|')
12773                 if (*p == '}' || *p == '\0')
12774                   abort ();
12775             }
12776           /* Fall through.  */
12777         case 'I':
12778           alt = 1;
12779           continue;
12780         case '|':
12781           while (*++p != '}')
12782             {
12783               if (*p == '\0')
12784                 abort ();
12785             }
12786           break;
12787         case '}':
12788           break;
12789         case 'A':
12790           if (intel_syntax)
12791             break;
12792           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12793             *obufp++ = 'b';
12794           break;
12795         case 'B':
12796           if (l == 0 && len == 1)
12797             {
12798 case_B:
12799               if (intel_syntax)
12800                 break;
12801               if (sizeflag & SUFFIX_ALWAYS)
12802                 *obufp++ = 'b';
12803             }
12804           else
12805             {
12806               if (l != 1
12807                   || len != 2
12808                   || last[0] != 'L')
12809                 {
12810                   SAVE_LAST (*p);
12811                   break;
12812                 }
12813
12814               if (address_mode == mode_64bit
12815                   && !(prefixes & PREFIX_ADDR))
12816                 {
12817                   *obufp++ = 'a';
12818                   *obufp++ = 'b';
12819                   *obufp++ = 's';
12820                 }
12821
12822               goto case_B;
12823             }
12824           break;
12825         case 'C':
12826           if (intel_syntax && !alt)
12827             break;
12828           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12829             {
12830               if (sizeflag & DFLAG)
12831                 *obufp++ = intel_syntax ? 'd' : 'l';
12832               else
12833                 *obufp++ = intel_syntax ? 'w' : 's';
12834               used_prefixes |= (prefixes & PREFIX_DATA);
12835             }
12836           break;
12837         case 'D':
12838           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12839             break;
12840           USED_REX (REX_W);
12841           if (modrm.mod == 3)
12842             {
12843               if (rex & REX_W)
12844                 *obufp++ = 'q';
12845               else
12846                 {
12847                   if (sizeflag & DFLAG)
12848                     *obufp++ = intel_syntax ? 'd' : 'l';
12849                   else
12850                     *obufp++ = 'w';
12851                   used_prefixes |= (prefixes & PREFIX_DATA);
12852                 }
12853             }
12854           else
12855             *obufp++ = 'w';
12856           break;
12857         case 'E':               /* For jcxz/jecxz */
12858           if (address_mode == mode_64bit)
12859             {
12860               if (sizeflag & AFLAG)
12861                 *obufp++ = 'r';
12862               else
12863                 *obufp++ = 'e';
12864             }
12865           else
12866             if (sizeflag & AFLAG)
12867               *obufp++ = 'e';
12868           used_prefixes |= (prefixes & PREFIX_ADDR);
12869           break;
12870         case 'F':
12871           if (intel_syntax)
12872             break;
12873           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12874             {
12875               if (sizeflag & AFLAG)
12876                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12877               else
12878                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12879               used_prefixes |= (prefixes & PREFIX_ADDR);
12880             }
12881           break;
12882         case 'G':
12883           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12884             break;
12885           if ((rex & REX_W) || (sizeflag & DFLAG))
12886             *obufp++ = 'l';
12887           else
12888             *obufp++ = 'w';
12889           if (!(rex & REX_W))
12890             used_prefixes |= (prefixes & PREFIX_DATA);
12891           break;
12892         case 'H':
12893           if (intel_syntax)
12894             break;
12895           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12896               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12897             {
12898               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12899               *obufp++ = ',';
12900               *obufp++ = 'p';
12901               if (prefixes & PREFIX_DS)
12902                 *obufp++ = 't';
12903               else
12904                 *obufp++ = 'n';
12905             }
12906           break;
12907         case 'J':
12908           if (intel_syntax)
12909             break;
12910           *obufp++ = 'l';
12911           break;
12912         case 'K':
12913           USED_REX (REX_W);
12914           if (rex & REX_W)
12915             *obufp++ = 'q';
12916           else
12917             *obufp++ = 'd';
12918           break;
12919         case 'Z':
12920           if (l != 0 || len != 1)
12921             {
12922               if (l != 1 || len != 2 || last[0] != 'X')
12923                 {
12924                   SAVE_LAST (*p);
12925                   break;
12926                 }
12927               if (!need_vex || !vex.evex)
12928                 abort ();
12929               if (intel_syntax
12930                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12931                 break;
12932               switch (vex.length)
12933                 {
12934                 case 128:
12935                   *obufp++ = 'x';
12936                   break;
12937                 case 256:
12938                   *obufp++ = 'y';
12939                   break;
12940                 case 512:
12941                   *obufp++ = 'z';
12942                   break;
12943                 default:
12944                   abort ();
12945                 }
12946               break;
12947             }
12948           if (intel_syntax)
12949             break;
12950           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12951             {
12952               *obufp++ = 'q';
12953               break;
12954             }
12955           /* Fall through.  */
12956           goto case_L;
12957         case 'L':
12958           if (l != 0 || len != 1)
12959             {
12960               SAVE_LAST (*p);
12961               break;
12962             }
12963 case_L:
12964           if (intel_syntax)
12965             break;
12966           if (sizeflag & SUFFIX_ALWAYS)
12967             *obufp++ = 'l';
12968           break;
12969         case 'M':
12970           if (intel_mnemonic != cond)
12971             *obufp++ = 'r';
12972           break;
12973         case 'N':
12974           if ((prefixes & PREFIX_FWAIT) == 0)
12975             *obufp++ = 'n';
12976           else
12977             used_prefixes |= PREFIX_FWAIT;
12978           break;
12979         case 'O':
12980           USED_REX (REX_W);
12981           if (rex & REX_W)
12982             *obufp++ = 'o';
12983           else if (intel_syntax && (sizeflag & DFLAG))
12984             *obufp++ = 'q';
12985           else
12986             *obufp++ = 'd';
12987           if (!(rex & REX_W))
12988             used_prefixes |= (prefixes & PREFIX_DATA);
12989           break;
12990         case '&':
12991           if (!intel_syntax
12992               && address_mode == mode_64bit
12993               && isa64 == intel64)
12994             {
12995               *obufp++ = 'q';
12996               break;
12997             }
12998           /* Fall through.  */
12999         case 'T':
13000           if (!intel_syntax
13001               && address_mode == mode_64bit
13002               && ((sizeflag & DFLAG) || (rex & REX_W)))
13003             {
13004               *obufp++ = 'q';
13005               break;
13006             }
13007           /* Fall through.  */
13008           goto case_P;
13009         case 'P':
13010           if (l == 0 && len == 1)
13011             {
13012 case_P:
13013               if (intel_syntax)
13014                 {
13015                   if ((rex & REX_W) == 0
13016                       && (prefixes & PREFIX_DATA))
13017                     {
13018                       if ((sizeflag & DFLAG) == 0)
13019                         *obufp++ = 'w';
13020                       used_prefixes |= (prefixes & PREFIX_DATA);
13021                     }
13022                   break;
13023                 }
13024               if ((prefixes & PREFIX_DATA)
13025                   || (rex & REX_W)
13026                   || (sizeflag & SUFFIX_ALWAYS))
13027                 {
13028                   USED_REX (REX_W);
13029                   if (rex & REX_W)
13030                     *obufp++ = 'q';
13031                   else
13032                     {
13033                       if (sizeflag & DFLAG)
13034                         *obufp++ = 'l';
13035                       else
13036                         *obufp++ = 'w';
13037                       used_prefixes |= (prefixes & PREFIX_DATA);
13038                     }
13039                 }
13040             }
13041           else
13042             {
13043               if (l != 1 || len != 2 || last[0] != 'L')
13044                 {
13045                   SAVE_LAST (*p);
13046                   break;
13047                 }
13048
13049               if ((prefixes & PREFIX_DATA)
13050                   || (rex & REX_W)
13051                   || (sizeflag & SUFFIX_ALWAYS))
13052                 {
13053                   USED_REX (REX_W);
13054                   if (rex & REX_W)
13055                     *obufp++ = 'q';
13056                   else
13057                     {
13058                       if (sizeflag & DFLAG)
13059                         *obufp++ = intel_syntax ? 'd' : 'l';
13060                       else
13061                         *obufp++ = 'w';
13062                       used_prefixes |= (prefixes & PREFIX_DATA);
13063                     }
13064                 }
13065             }
13066           break;
13067         case 'U':
13068           if (intel_syntax)
13069             break;
13070           if (address_mode == mode_64bit
13071               && ((sizeflag & DFLAG) || (rex & REX_W)))
13072             {
13073               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13074                 *obufp++ = 'q';
13075               break;
13076             }
13077           /* Fall through.  */
13078           goto case_Q;
13079         case 'Q':
13080           if (l == 0 && len == 1)
13081             {
13082 case_Q:
13083               if (intel_syntax && !alt)
13084                 break;
13085               USED_REX (REX_W);
13086               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13087                 {
13088                   if (rex & REX_W)
13089                     *obufp++ = 'q';
13090                   else
13091                     {
13092                       if (sizeflag & DFLAG)
13093                         *obufp++ = intel_syntax ? 'd' : 'l';
13094                       else
13095                         *obufp++ = 'w';
13096                       used_prefixes |= (prefixes & PREFIX_DATA);
13097                     }
13098                 }
13099             }
13100           else
13101             {
13102               if (l != 1 || len != 2 || last[0] != 'L')
13103                 {
13104                   SAVE_LAST (*p);
13105                   break;
13106                 }
13107               if (intel_syntax
13108                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13109                 break;
13110               if ((rex & REX_W))
13111                 {
13112                   USED_REX (REX_W);
13113                   *obufp++ = 'q';
13114                 }
13115               else
13116                 *obufp++ = 'l';
13117             }
13118           break;
13119         case 'R':
13120           USED_REX (REX_W);
13121           if (rex & REX_W)
13122             *obufp++ = 'q';
13123           else if (sizeflag & DFLAG)
13124             {
13125               if (intel_syntax)
13126                   *obufp++ = 'd';
13127               else
13128                   *obufp++ = 'l';
13129             }
13130           else
13131             *obufp++ = 'w';
13132           if (intel_syntax && !p[1]
13133               && ((rex & REX_W) || (sizeflag & DFLAG)))
13134             *obufp++ = 'e';
13135           if (!(rex & REX_W))
13136             used_prefixes |= (prefixes & PREFIX_DATA);
13137           break;
13138         case 'V':
13139           if (l == 0 && len == 1)
13140             {
13141               if (intel_syntax)
13142                 break;
13143               if (address_mode == mode_64bit
13144                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13145                 {
13146                   if (sizeflag & SUFFIX_ALWAYS)
13147                     *obufp++ = 'q';
13148                   break;
13149                 }
13150             }
13151           else
13152             {
13153               if (l != 1
13154                   || len != 2
13155                   || last[0] != 'L')
13156                 {
13157                   SAVE_LAST (*p);
13158                   break;
13159                 }
13160
13161               if (rex & REX_W)
13162                 {
13163                   *obufp++ = 'a';
13164                   *obufp++ = 'b';
13165                   *obufp++ = 's';
13166                 }
13167             }
13168           /* Fall through.  */
13169           goto case_S;
13170         case 'S':
13171           if (l == 0 && len == 1)
13172             {
13173 case_S:
13174               if (intel_syntax)
13175                 break;
13176               if (sizeflag & SUFFIX_ALWAYS)
13177                 {
13178                   if (rex & REX_W)
13179                     *obufp++ = 'q';
13180                   else
13181                     {
13182                       if (sizeflag & DFLAG)
13183                         *obufp++ = 'l';
13184                       else
13185                         *obufp++ = 'w';
13186                       used_prefixes |= (prefixes & PREFIX_DATA);
13187                     }
13188                 }
13189             }
13190           else
13191             {
13192               if (l != 1
13193                   || len != 2
13194                   || last[0] != 'L')
13195                 {
13196                   SAVE_LAST (*p);
13197                   break;
13198                 }
13199
13200               if (address_mode == mode_64bit
13201                   && !(prefixes & PREFIX_ADDR))
13202                 {
13203                   *obufp++ = 'a';
13204                   *obufp++ = 'b';
13205                   *obufp++ = 's';
13206                 }
13207
13208               goto case_S;
13209             }
13210           break;
13211         case 'X':
13212           if (l != 0 || len != 1)
13213             {
13214               SAVE_LAST (*p);
13215               break;
13216             }
13217           if (need_vex && vex.prefix)
13218             {
13219               if (vex.prefix == DATA_PREFIX_OPCODE)
13220                 *obufp++ = 'd';
13221               else
13222                 *obufp++ = 's';
13223             }
13224           else
13225             {
13226               if (prefixes & PREFIX_DATA)
13227                 *obufp++ = 'd';
13228               else
13229                 *obufp++ = 's';
13230               used_prefixes |= (prefixes & PREFIX_DATA);
13231             }
13232           break;
13233         case 'Y':
13234           if (l == 0 && len == 1)
13235             abort ();
13236           else
13237             {
13238               if (l != 1 || len != 2 || last[0] != 'X')
13239                 {
13240                   SAVE_LAST (*p);
13241                   break;
13242                 }
13243               if (!need_vex)
13244                 abort ();
13245               if (intel_syntax
13246                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13247                 break;
13248               switch (vex.length)
13249                 {
13250                 case 128:
13251                   *obufp++ = 'x';
13252                   break;
13253                 case 256:
13254                   *obufp++ = 'y';
13255                   break;
13256                 case 512:
13257                   if (!vex.evex)
13258                 default:
13259                     abort ();
13260                 }
13261             }
13262           break;
13263         case 'W':
13264           if (l == 0 && len == 1)
13265             {
13266               /* operand size flag for cwtl, cbtw */
13267               USED_REX (REX_W);
13268               if (rex & REX_W)
13269                 {
13270                   if (intel_syntax)
13271                     *obufp++ = 'd';
13272                   else
13273                     *obufp++ = 'l';
13274                 }
13275               else if (sizeflag & DFLAG)
13276                 *obufp++ = 'w';
13277               else
13278                 *obufp++ = 'b';
13279               if (!(rex & REX_W))
13280                 used_prefixes |= (prefixes & PREFIX_DATA);
13281             }
13282           else
13283             {
13284               if (l != 1
13285                   || len != 2
13286                   || (last[0] != 'X'
13287                       && last[0] != 'L'))
13288                 {
13289                   SAVE_LAST (*p);
13290                   break;
13291                 }
13292               if (!need_vex)
13293                 abort ();
13294               if (last[0] == 'X')
13295                 *obufp++ = vex.w ? 'd': 's';
13296               else
13297                 *obufp++ = vex.w ? 'q': 'd';
13298             }
13299           break;
13300         case '^':
13301           if (intel_syntax)
13302             break;
13303           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13304             {
13305               if (sizeflag & DFLAG)
13306                 *obufp++ = 'l';
13307               else
13308                 *obufp++ = 'w';
13309               used_prefixes |= (prefixes & PREFIX_DATA);
13310             }
13311           break;
13312         case '@':
13313           if (intel_syntax)
13314             break;
13315           if (address_mode == mode_64bit
13316               && (isa64 == intel64
13317                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13318               *obufp++ = 'q';
13319           else if ((prefixes & PREFIX_DATA))
13320             {
13321               if (!(sizeflag & DFLAG))
13322                 *obufp++ = 'w';
13323               used_prefixes |= (prefixes & PREFIX_DATA);
13324             }
13325           break;
13326         }
13327       alt = 0;
13328     }
13329   *obufp = 0;
13330   mnemonicendp = obufp;
13331   return 0;
13332 }
13333
13334 static void
13335 oappend (const char *s)
13336 {
13337   obufp = stpcpy (obufp, s);
13338 }
13339
13340 static void
13341 append_seg (void)
13342 {
13343   /* Only print the active segment register.  */
13344   if (!active_seg_prefix)
13345     return;
13346
13347   used_prefixes |= active_seg_prefix;
13348   switch (active_seg_prefix)
13349     {
13350     case PREFIX_CS:
13351       oappend_maybe_intel ("%cs:");
13352       break;
13353     case PREFIX_DS:
13354       oappend_maybe_intel ("%ds:");
13355       break;
13356     case PREFIX_SS:
13357       oappend_maybe_intel ("%ss:");
13358       break;
13359     case PREFIX_ES:
13360       oappend_maybe_intel ("%es:");
13361       break;
13362     case PREFIX_FS:
13363       oappend_maybe_intel ("%fs:");
13364       break;
13365     case PREFIX_GS:
13366       oappend_maybe_intel ("%gs:");
13367       break;
13368     default:
13369       break;
13370     }
13371 }
13372
13373 static void
13374 OP_indirE (int bytemode, int sizeflag)
13375 {
13376   if (!intel_syntax)
13377     oappend ("*");
13378   OP_E (bytemode, sizeflag);
13379 }
13380
13381 static void
13382 print_operand_value (char *buf, int hex, bfd_vma disp)
13383 {
13384   if (address_mode == mode_64bit)
13385     {
13386       if (hex)
13387         {
13388           char tmp[30];
13389           int i;
13390           buf[0] = '0';
13391           buf[1] = 'x';
13392           sprintf_vma (tmp, disp);
13393           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13394           strcpy (buf + 2, tmp + i);
13395         }
13396       else
13397         {
13398           bfd_signed_vma v = disp;
13399           char tmp[30];
13400           int i;
13401           if (v < 0)
13402             {
13403               *(buf++) = '-';
13404               v = -disp;
13405               /* Check for possible overflow on 0x8000000000000000.  */
13406               if (v < 0)
13407                 {
13408                   strcpy (buf, "9223372036854775808");
13409                   return;
13410                 }
13411             }
13412           if (!v)
13413             {
13414               strcpy (buf, "0");
13415               return;
13416             }
13417
13418           i = 0;
13419           tmp[29] = 0;
13420           while (v)
13421             {
13422               tmp[28 - i] = (v % 10) + '0';
13423               v /= 10;
13424               i++;
13425             }
13426           strcpy (buf, tmp + 29 - i);
13427         }
13428     }
13429   else
13430     {
13431       if (hex)
13432         sprintf (buf, "0x%x", (unsigned int) disp);
13433       else
13434         sprintf (buf, "%d", (int) disp);
13435     }
13436 }
13437
13438 /* Put DISP in BUF as signed hex number.  */
13439
13440 static void
13441 print_displacement (char *buf, bfd_vma disp)
13442 {
13443   bfd_signed_vma val = disp;
13444   char tmp[30];
13445   int i, j = 0;
13446
13447   if (val < 0)
13448     {
13449       buf[j++] = '-';
13450       val = -disp;
13451
13452       /* Check for possible overflow.  */
13453       if (val < 0)
13454         {
13455           switch (address_mode)
13456             {
13457             case mode_64bit:
13458               strcpy (buf + j, "0x8000000000000000");
13459               break;
13460             case mode_32bit:
13461               strcpy (buf + j, "0x80000000");
13462               break;
13463             case mode_16bit:
13464               strcpy (buf + j, "0x8000");
13465               break;
13466             }
13467           return;
13468         }
13469     }
13470
13471   buf[j++] = '0';
13472   buf[j++] = 'x';
13473
13474   sprintf_vma (tmp, (bfd_vma) val);
13475   for (i = 0; tmp[i] == '0'; i++)
13476     continue;
13477   if (tmp[i] == '\0')
13478     i--;
13479   strcpy (buf + j, tmp + i);
13480 }
13481
13482 static void
13483 intel_operand_size (int bytemode, int sizeflag)
13484 {
13485   if (vex.evex
13486       && vex.b
13487       && (bytemode == x_mode
13488           || bytemode == evex_half_bcst_xmmq_mode))
13489     {
13490       if (vex.w)
13491         oappend ("QWORD PTR ");
13492       else
13493         oappend ("DWORD PTR ");
13494       return;
13495     }
13496   switch (bytemode)
13497     {
13498     case b_mode:
13499     case b_swap_mode:
13500     case dqb_mode:
13501     case db_mode:
13502       oappend ("BYTE PTR ");
13503       break;
13504     case w_mode:
13505     case dw_mode:
13506     case dqw_mode:
13507       oappend ("WORD PTR ");
13508       break;
13509     case indir_v_mode:
13510       if (address_mode == mode_64bit && isa64 == intel64)
13511         {
13512           oappend ("QWORD PTR ");
13513           break;
13514         }
13515       /* Fall through.  */
13516     case stack_v_mode:
13517       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13518         {
13519           oappend ("QWORD PTR ");
13520           break;
13521         }
13522       /* Fall through.  */
13523     case v_mode:
13524     case v_swap_mode:
13525     case dq_mode:
13526       USED_REX (REX_W);
13527       if (rex & REX_W)
13528         oappend ("QWORD PTR ");
13529       else
13530         {
13531           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13532             oappend ("DWORD PTR ");
13533           else
13534             oappend ("WORD PTR ");
13535           used_prefixes |= (prefixes & PREFIX_DATA);
13536         }
13537       break;
13538     case z_mode:
13539       if ((rex & REX_W) || (sizeflag & DFLAG))
13540         *obufp++ = 'D';
13541       oappend ("WORD PTR ");
13542       if (!(rex & REX_W))
13543         used_prefixes |= (prefixes & PREFIX_DATA);
13544       break;
13545     case a_mode:
13546       if (sizeflag & DFLAG)
13547         oappend ("QWORD PTR ");
13548       else
13549         oappend ("DWORD PTR ");
13550       used_prefixes |= (prefixes & PREFIX_DATA);
13551       break;
13552     case movsxd_mode:
13553       if (!(sizeflag & DFLAG) && isa64 == intel64)
13554         oappend ("WORD PTR ");
13555       else
13556         oappend ("DWORD PTR ");
13557       used_prefixes |= (prefixes & PREFIX_DATA);
13558       break;
13559     case d_mode:
13560     case d_scalar_mode:
13561     case d_scalar_swap_mode:
13562     case d_swap_mode:
13563     case dqd_mode:
13564       oappend ("DWORD PTR ");
13565       break;
13566     case q_mode:
13567     case q_scalar_mode:
13568     case q_scalar_swap_mode:
13569     case q_swap_mode:
13570       oappend ("QWORD PTR ");
13571       break;
13572     case m_mode:
13573       if (address_mode == mode_64bit)
13574         oappend ("QWORD PTR ");
13575       else
13576         oappend ("DWORD PTR ");
13577       break;
13578     case f_mode:
13579       if (sizeflag & DFLAG)
13580         oappend ("FWORD PTR ");
13581       else
13582         oappend ("DWORD PTR ");
13583       used_prefixes |= (prefixes & PREFIX_DATA);
13584       break;
13585     case t_mode:
13586       oappend ("TBYTE PTR ");
13587       break;
13588     case x_mode:
13589     case x_swap_mode:
13590     case evex_x_gscat_mode:
13591     case evex_x_nobcst_mode:
13592     case b_scalar_mode:
13593     case w_scalar_mode:
13594       if (need_vex)
13595         {
13596           switch (vex.length)
13597             {
13598             case 128:
13599               oappend ("XMMWORD PTR ");
13600               break;
13601             case 256:
13602               oappend ("YMMWORD PTR ");
13603               break;
13604             case 512:
13605               oappend ("ZMMWORD PTR ");
13606               break;
13607             default:
13608               abort ();
13609             }
13610         }
13611       else
13612         oappend ("XMMWORD PTR ");
13613       break;
13614     case xmm_mode:
13615       oappend ("XMMWORD PTR ");
13616       break;
13617     case ymm_mode:
13618       oappend ("YMMWORD PTR ");
13619       break;
13620     case xmmq_mode:
13621     case evex_half_bcst_xmmq_mode:
13622       if (!need_vex)
13623         abort ();
13624
13625       switch (vex.length)
13626         {
13627         case 128:
13628           oappend ("QWORD PTR ");
13629           break;
13630         case 256:
13631           oappend ("XMMWORD PTR ");
13632           break;
13633         case 512:
13634           oappend ("YMMWORD PTR ");
13635           break;
13636         default:
13637           abort ();
13638         }
13639       break;
13640     case xmm_mb_mode:
13641       if (!need_vex)
13642         abort ();
13643
13644       switch (vex.length)
13645         {
13646         case 128:
13647         case 256:
13648         case 512:
13649           oappend ("BYTE PTR ");
13650           break;
13651         default:
13652           abort ();
13653         }
13654       break;
13655     case xmm_mw_mode:
13656       if (!need_vex)
13657         abort ();
13658
13659       switch (vex.length)
13660         {
13661         case 128:
13662         case 256:
13663         case 512:
13664           oappend ("WORD PTR ");
13665           break;
13666         default:
13667           abort ();
13668         }
13669       break;
13670     case xmm_md_mode:
13671       if (!need_vex)
13672         abort ();
13673
13674       switch (vex.length)
13675         {
13676         case 128:
13677         case 256:
13678         case 512:
13679           oappend ("DWORD PTR ");
13680           break;
13681         default:
13682           abort ();
13683         }
13684       break;
13685     case xmm_mq_mode:
13686       if (!need_vex)
13687         abort ();
13688
13689       switch (vex.length)
13690         {
13691         case 128:
13692         case 256:
13693         case 512:
13694           oappend ("QWORD PTR ");
13695           break;
13696         default:
13697           abort ();
13698         }
13699       break;
13700     case xmmdw_mode:
13701       if (!need_vex)
13702         abort ();
13703
13704       switch (vex.length)
13705         {
13706         case 128:
13707           oappend ("WORD PTR ");
13708           break;
13709         case 256:
13710           oappend ("DWORD PTR ");
13711           break;
13712         case 512:
13713           oappend ("QWORD PTR ");
13714           break;
13715         default:
13716           abort ();
13717         }
13718       break;
13719     case xmmqd_mode:
13720       if (!need_vex)
13721         abort ();
13722
13723       switch (vex.length)
13724         {
13725         case 128:
13726           oappend ("DWORD PTR ");
13727           break;
13728         case 256:
13729           oappend ("QWORD PTR ");
13730           break;
13731         case 512:
13732           oappend ("XMMWORD PTR ");
13733           break;
13734         default:
13735           abort ();
13736         }
13737       break;
13738     case ymmq_mode:
13739       if (!need_vex)
13740         abort ();
13741
13742       switch (vex.length)
13743         {
13744         case 128:
13745           oappend ("QWORD PTR ");
13746           break;
13747         case 256:
13748           oappend ("YMMWORD PTR ");
13749           break;
13750         case 512:
13751           oappend ("ZMMWORD PTR ");
13752           break;
13753         default:
13754           abort ();
13755         }
13756       break;
13757     case ymmxmm_mode:
13758       if (!need_vex)
13759         abort ();
13760
13761       switch (vex.length)
13762         {
13763         case 128:
13764         case 256:
13765           oappend ("XMMWORD PTR ");
13766           break;
13767         default:
13768           abort ();
13769         }
13770       break;
13771     case o_mode:
13772       oappend ("OWORD PTR ");
13773       break;
13774     case xmm_mdq_mode:
13775     case vex_scalar_w_dq_mode:
13776       if (!need_vex)
13777         abort ();
13778
13779       if (vex.w)
13780         oappend ("QWORD PTR ");
13781       else
13782         oappend ("DWORD PTR ");
13783       break;
13784     case vex_vsib_d_w_dq_mode:
13785     case vex_vsib_q_w_dq_mode:
13786       if (!need_vex)
13787         abort ();
13788
13789       if (!vex.evex)
13790         {
13791           if (vex.w)
13792             oappend ("QWORD PTR ");
13793           else
13794             oappend ("DWORD PTR ");
13795         }
13796       else
13797         {
13798           switch (vex.length)
13799             {
13800             case 128:
13801               oappend ("XMMWORD PTR ");
13802               break;
13803             case 256:
13804               oappend ("YMMWORD PTR ");
13805               break;
13806             case 512:
13807               oappend ("ZMMWORD PTR ");
13808               break;
13809             default:
13810               abort ();
13811             }
13812         }
13813       break;
13814     case vex_vsib_q_w_d_mode:
13815     case vex_vsib_d_w_d_mode:
13816       if (!need_vex || !vex.evex)
13817         abort ();
13818
13819       switch (vex.length)
13820         {
13821         case 128:
13822           oappend ("QWORD PTR ");
13823           break;
13824         case 256:
13825           oappend ("XMMWORD PTR ");
13826           break;
13827         case 512:
13828           oappend ("YMMWORD PTR ");
13829           break;
13830         default:
13831           abort ();
13832         }
13833
13834       break;
13835     case mask_bd_mode:
13836       if (!need_vex || vex.length != 128)
13837         abort ();
13838       if (vex.w)
13839         oappend ("DWORD PTR ");
13840       else
13841         oappend ("BYTE PTR ");
13842       break;
13843     case mask_mode:
13844       if (!need_vex)
13845         abort ();
13846       if (vex.w)
13847         oappend ("QWORD PTR ");
13848       else
13849         oappend ("WORD PTR ");
13850       break;
13851     case v_bnd_mode:
13852     case v_bndmk_mode:
13853     default:
13854       break;
13855     }
13856 }
13857
13858 static void
13859 OP_E_register (int bytemode, int sizeflag)
13860 {
13861   int reg = modrm.rm;
13862   const char **names;
13863
13864   USED_REX (REX_B);
13865   if ((rex & REX_B))
13866     reg += 8;
13867
13868   if ((sizeflag & SUFFIX_ALWAYS)
13869       && (bytemode == b_swap_mode
13870           || bytemode == bnd_swap_mode
13871           || bytemode == v_swap_mode))
13872     swap_operand ();
13873
13874   switch (bytemode)
13875     {
13876     case b_mode:
13877     case b_swap_mode:
13878       USED_REX (0);
13879       if (rex)
13880         names = names8rex;
13881       else
13882         names = names8;
13883       break;
13884     case w_mode:
13885       names = names16;
13886       break;
13887     case d_mode:
13888     case dw_mode:
13889     case db_mode:
13890       names = names32;
13891       break;
13892     case q_mode:
13893       names = names64;
13894       break;
13895     case m_mode:
13896     case v_bnd_mode:
13897       names = address_mode == mode_64bit ? names64 : names32;
13898       break;
13899     case bnd_mode:
13900     case bnd_swap_mode:
13901       if (reg > 0x3)
13902         {
13903           oappend ("(bad)");
13904           return;
13905         }
13906       names = names_bnd;
13907       break;
13908     case indir_v_mode:
13909       if (address_mode == mode_64bit && isa64 == intel64)
13910         {
13911           names = names64;
13912           break;
13913         }
13914       /* Fall through.  */
13915     case stack_v_mode:
13916       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13917         {
13918           names = names64;
13919           break;
13920         }
13921       bytemode = v_mode;
13922       /* Fall through.  */
13923     case v_mode:
13924     case v_swap_mode:
13925     case dq_mode:
13926     case dqb_mode:
13927     case dqd_mode:
13928     case dqw_mode:
13929       USED_REX (REX_W);
13930       if (rex & REX_W)
13931         names = names64;
13932       else
13933         {
13934           if ((sizeflag & DFLAG)
13935               || (bytemode != v_mode
13936                   && bytemode != v_swap_mode))
13937             names = names32;
13938           else
13939             names = names16;
13940           used_prefixes |= (prefixes & PREFIX_DATA);
13941         }
13942       break;
13943     case movsxd_mode:
13944       if (!(sizeflag & DFLAG) && isa64 == intel64)
13945         names = names16;
13946       else
13947         names = names32;
13948       used_prefixes |= (prefixes & PREFIX_DATA);
13949       break;
13950     case va_mode:
13951       names = (address_mode == mode_64bit
13952                ? names64 : names32);
13953       if (!(prefixes & PREFIX_ADDR))
13954         names = (address_mode == mode_16bit
13955                      ? names16 : names);
13956       else
13957         {
13958           /* Remove "addr16/addr32".  */
13959           all_prefixes[last_addr_prefix] = 0;
13960           names = (address_mode != mode_32bit
13961                        ? names32 : names16);
13962           used_prefixes |= PREFIX_ADDR;
13963         }
13964       break;
13965     case mask_bd_mode:
13966     case mask_mode:
13967       if (reg > 0x7)
13968         {
13969           oappend ("(bad)");
13970           return;
13971         }
13972       names = names_mask;
13973       break;
13974     case 0:
13975       return;
13976     default:
13977       oappend (INTERNAL_DISASSEMBLER_ERROR);
13978       return;
13979     }
13980   oappend (names[reg]);
13981 }
13982
13983 static void
13984 OP_E_memory (int bytemode, int sizeflag)
13985 {
13986   bfd_vma disp = 0;
13987   int add = (rex & REX_B) ? 8 : 0;
13988   int riprel = 0;
13989   int shift;
13990
13991   if (vex.evex)
13992     {
13993       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13994       if (vex.b
13995           && bytemode != x_mode
13996           && bytemode != xmmq_mode
13997           && bytemode != evex_half_bcst_xmmq_mode)
13998         {
13999           BadOp ();
14000           return;
14001         }
14002       switch (bytemode)
14003         {
14004         case dqw_mode:
14005         case dw_mode:
14006           shift = 1;
14007           break;
14008         case dqb_mode:
14009         case db_mode:
14010           shift = 0;
14011           break;
14012         case dq_mode:
14013           if (address_mode != mode_64bit)
14014             {
14015               shift = 2;
14016               break;
14017             }
14018             /* fall through */
14019         case vex_vsib_d_w_dq_mode:
14020         case vex_vsib_d_w_d_mode:
14021         case vex_vsib_q_w_dq_mode:
14022         case vex_vsib_q_w_d_mode:
14023         case evex_x_gscat_mode:
14024         case xmm_mdq_mode:
14025           shift = vex.w ? 3 : 2;
14026           break;
14027         case x_mode:
14028         case evex_half_bcst_xmmq_mode:
14029         case xmmq_mode:
14030           if (vex.b)
14031             {
14032               shift = vex.w ? 3 : 2;
14033               break;
14034             }
14035           /* Fall through.  */
14036         case xmmqd_mode:
14037         case xmmdw_mode:
14038         case ymmq_mode:
14039         case evex_x_nobcst_mode:
14040         case x_swap_mode:
14041           switch (vex.length)
14042             {
14043             case 128:
14044               shift = 4;
14045               break;
14046             case 256:
14047               shift = 5;
14048               break;
14049             case 512:
14050               shift = 6;
14051               break;
14052             default:
14053               abort ();
14054             }
14055           break;
14056         case ymm_mode:
14057           shift = 5;
14058           break;
14059         case xmm_mode:
14060           shift = 4;
14061           break;
14062         case xmm_mq_mode:
14063         case q_mode:
14064         case q_scalar_mode:
14065         case q_swap_mode:
14066         case q_scalar_swap_mode:
14067           shift = 3;
14068           break;
14069         case dqd_mode:
14070         case xmm_md_mode:
14071         case d_mode:
14072         case d_scalar_mode:
14073         case d_swap_mode:
14074         case d_scalar_swap_mode:
14075           shift = 2;
14076           break;
14077         case w_scalar_mode:
14078         case xmm_mw_mode:
14079           shift = 1;
14080           break;
14081         case b_scalar_mode:
14082         case xmm_mb_mode:
14083           shift = 0;
14084           break;
14085         default:
14086           abort ();
14087         }
14088       /* Make necessary corrections to shift for modes that need it.
14089          For these modes we currently have shift 4, 5 or 6 depending on
14090          vex.length (it corresponds to xmmword, ymmword or zmmword
14091          operand).  We might want to make it 3, 4 or 5 (e.g. for
14092          xmmq_mode).  In case of broadcast enabled the corrections
14093          aren't needed, as element size is always 32 or 64 bits.  */
14094       if (!vex.b
14095           && (bytemode == xmmq_mode
14096               || bytemode == evex_half_bcst_xmmq_mode))
14097         shift -= 1;
14098       else if (bytemode == xmmqd_mode)
14099         shift -= 2;
14100       else if (bytemode == xmmdw_mode)
14101         shift -= 3;
14102       else if (bytemode == ymmq_mode && vex.length == 128)
14103         shift -= 1;
14104     }
14105   else
14106     shift = 0;
14107
14108   USED_REX (REX_B);
14109   if (intel_syntax)
14110     intel_operand_size (bytemode, sizeflag);
14111   append_seg ();
14112
14113   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14114     {
14115       /* 32/64 bit address mode */
14116       int havedisp;
14117       int havesib;
14118       int havebase;
14119       int haveindex;
14120       int needindex;
14121       int needaddr32;
14122       int base, rbase;
14123       int vindex = 0;
14124       int scale = 0;
14125       int addr32flag = !((sizeflag & AFLAG)
14126                          || bytemode == v_bnd_mode
14127                          || bytemode == v_bndmk_mode
14128                          || bytemode == bnd_mode
14129                          || bytemode == bnd_swap_mode);
14130       const char **indexes64 = names64;
14131       const char **indexes32 = names32;
14132
14133       havesib = 0;
14134       havebase = 1;
14135       haveindex = 0;
14136       base = modrm.rm;
14137
14138       if (base == 4)
14139         {
14140           havesib = 1;
14141           vindex = sib.index;
14142           USED_REX (REX_X);
14143           if (rex & REX_X)
14144             vindex += 8;
14145           switch (bytemode)
14146             {
14147             case vex_vsib_d_w_dq_mode:
14148             case vex_vsib_d_w_d_mode:
14149             case vex_vsib_q_w_dq_mode:
14150             case vex_vsib_q_w_d_mode:
14151               if (!need_vex)
14152                 abort ();
14153               if (vex.evex)
14154                 {
14155                   if (!vex.v)
14156                     vindex += 16;
14157                 }
14158
14159               haveindex = 1;
14160               switch (vex.length)
14161                 {
14162                 case 128:
14163                   indexes64 = indexes32 = names_xmm;
14164                   break;
14165                 case 256:
14166                   if (!vex.w
14167                       || bytemode == vex_vsib_q_w_dq_mode
14168                       || bytemode == vex_vsib_q_w_d_mode)
14169                     indexes64 = indexes32 = names_ymm;
14170                   else
14171                     indexes64 = indexes32 = names_xmm;
14172                   break;
14173                 case 512:
14174                   if (!vex.w
14175                       || bytemode == vex_vsib_q_w_dq_mode
14176                       || bytemode == vex_vsib_q_w_d_mode)
14177                     indexes64 = indexes32 = names_zmm;
14178                   else
14179                     indexes64 = indexes32 = names_ymm;
14180                   break;
14181                 default:
14182                   abort ();
14183                 }
14184               break;
14185             default:
14186               haveindex = vindex != 4;
14187               break;
14188             }
14189           scale = sib.scale;
14190           base = sib.base;
14191           codep++;
14192         }
14193       rbase = base + add;
14194
14195       switch (modrm.mod)
14196         {
14197         case 0:
14198           if (base == 5)
14199             {
14200               havebase = 0;
14201               if (address_mode == mode_64bit && !havesib)
14202                 riprel = 1;
14203               disp = get32s ();
14204               if (riprel && bytemode == v_bndmk_mode)
14205                 {
14206                   oappend ("(bad)");
14207                   return;
14208                 }
14209             }
14210           break;
14211         case 1:
14212           FETCH_DATA (the_info, codep + 1);
14213           disp = *codep++;
14214           if ((disp & 0x80) != 0)
14215             disp -= 0x100;
14216           if (vex.evex && shift > 0)
14217             disp <<= shift;
14218           break;
14219         case 2:
14220           disp = get32s ();
14221           break;
14222         }
14223
14224       needindex = 0;
14225       needaddr32 = 0;
14226       if (havesib
14227           && !havebase
14228           && !haveindex
14229           && address_mode != mode_16bit)
14230         {
14231           if (address_mode == mode_64bit)
14232             {
14233               /* Display eiz instead of addr32.  */
14234               needindex = addr32flag;
14235               needaddr32 = 1;
14236             }
14237           else
14238             {
14239               /* In 32-bit mode, we need index register to tell [offset]
14240                  from [eiz*1 + offset].  */
14241               needindex = 1;
14242             }
14243         }
14244
14245       havedisp = (havebase
14246                   || needindex
14247                   || (havesib && (haveindex || scale != 0)));
14248
14249       if (!intel_syntax)
14250         if (modrm.mod != 0 || base == 5)
14251           {
14252             if (havedisp || riprel)
14253               print_displacement (scratchbuf, disp);
14254             else
14255               print_operand_value (scratchbuf, 1, disp);
14256             oappend (scratchbuf);
14257             if (riprel)
14258               {
14259                 set_op (disp, 1);
14260                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14261               }
14262           }
14263
14264       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14265           && (bytemode != v_bnd_mode)
14266           && (bytemode != v_bndmk_mode)
14267           && (bytemode != bnd_mode)
14268           && (bytemode != bnd_swap_mode))
14269         used_prefixes |= PREFIX_ADDR;
14270
14271       if (havedisp || (intel_syntax && riprel))
14272         {
14273           *obufp++ = open_char;
14274           if (intel_syntax && riprel)
14275             {
14276               set_op (disp, 1);
14277               oappend (!addr32flag ? "rip" : "eip");
14278             }
14279           *obufp = '\0';
14280           if (havebase)
14281             oappend (address_mode == mode_64bit && !addr32flag
14282                      ? names64[rbase] : names32[rbase]);
14283           if (havesib)
14284             {
14285               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14286                  print index to tell base + index from base.  */
14287               if (scale != 0
14288                   || needindex
14289                   || haveindex
14290                   || (havebase && base != ESP_REG_NUM))
14291                 {
14292                   if (!intel_syntax || havebase)
14293                     {
14294                       *obufp++ = separator_char;
14295                       *obufp = '\0';
14296                     }
14297                   if (haveindex)
14298                     oappend (address_mode == mode_64bit && !addr32flag
14299                              ? indexes64[vindex] : indexes32[vindex]);
14300                   else
14301                     oappend (address_mode == mode_64bit && !addr32flag
14302                              ? index64 : index32);
14303
14304                   *obufp++ = scale_char;
14305                   *obufp = '\0';
14306                   sprintf (scratchbuf, "%d", 1 << scale);
14307                   oappend (scratchbuf);
14308                 }
14309             }
14310           if (intel_syntax
14311               && (disp || modrm.mod != 0 || base == 5))
14312             {
14313               if (!havedisp || (bfd_signed_vma) disp >= 0)
14314                 {
14315                   *obufp++ = '+';
14316                   *obufp = '\0';
14317                 }
14318               else if (modrm.mod != 1 && disp != -disp)
14319                 {
14320                   *obufp++ = '-';
14321                   *obufp = '\0';
14322                   disp = - (bfd_signed_vma) disp;
14323                 }
14324
14325               if (havedisp)
14326                 print_displacement (scratchbuf, disp);
14327               else
14328                 print_operand_value (scratchbuf, 1, disp);
14329               oappend (scratchbuf);
14330             }
14331
14332           *obufp++ = close_char;
14333           *obufp = '\0';
14334         }
14335       else if (intel_syntax)
14336         {
14337           if (modrm.mod != 0 || base == 5)
14338             {
14339               if (!active_seg_prefix)
14340                 {
14341                   oappend (names_seg[ds_reg - es_reg]);
14342                   oappend (":");
14343                 }
14344               print_operand_value (scratchbuf, 1, disp);
14345               oappend (scratchbuf);
14346             }
14347         }
14348     }
14349   else
14350     {
14351       /* 16 bit address mode */
14352       used_prefixes |= prefixes & PREFIX_ADDR;
14353       switch (modrm.mod)
14354         {
14355         case 0:
14356           if (modrm.rm == 6)
14357             {
14358               disp = get16 ();
14359               if ((disp & 0x8000) != 0)
14360                 disp -= 0x10000;
14361             }
14362           break;
14363         case 1:
14364           FETCH_DATA (the_info, codep + 1);
14365           disp = *codep++;
14366           if ((disp & 0x80) != 0)
14367             disp -= 0x100;
14368           if (vex.evex && shift > 0)
14369             disp <<= shift;
14370           break;
14371         case 2:
14372           disp = get16 ();
14373           if ((disp & 0x8000) != 0)
14374             disp -= 0x10000;
14375           break;
14376         }
14377
14378       if (!intel_syntax)
14379         if (modrm.mod != 0 || modrm.rm == 6)
14380           {
14381             print_displacement (scratchbuf, disp);
14382             oappend (scratchbuf);
14383           }
14384
14385       if (modrm.mod != 0 || modrm.rm != 6)
14386         {
14387           *obufp++ = open_char;
14388           *obufp = '\0';
14389           oappend (index16[modrm.rm]);
14390           if (intel_syntax
14391               && (disp || modrm.mod != 0 || modrm.rm == 6))
14392             {
14393               if ((bfd_signed_vma) disp >= 0)
14394                 {
14395                   *obufp++ = '+';
14396                   *obufp = '\0';
14397                 }
14398               else if (modrm.mod != 1)
14399                 {
14400                   *obufp++ = '-';
14401                   *obufp = '\0';
14402                   disp = - (bfd_signed_vma) disp;
14403                 }
14404
14405               print_displacement (scratchbuf, disp);
14406               oappend (scratchbuf);
14407             }
14408
14409           *obufp++ = close_char;
14410           *obufp = '\0';
14411         }
14412       else if (intel_syntax)
14413         {
14414           if (!active_seg_prefix)
14415             {
14416               oappend (names_seg[ds_reg - es_reg]);
14417               oappend (":");
14418             }
14419           print_operand_value (scratchbuf, 1, disp & 0xffff);
14420           oappend (scratchbuf);
14421         }
14422     }
14423   if (vex.evex && vex.b
14424       && (bytemode == x_mode
14425           || bytemode == xmmq_mode
14426           || bytemode == evex_half_bcst_xmmq_mode))
14427     {
14428       if (vex.w
14429           || bytemode == xmmq_mode
14430           || bytemode == evex_half_bcst_xmmq_mode)
14431         {
14432           switch (vex.length)
14433             {
14434             case 128:
14435               oappend ("{1to2}");
14436               break;
14437             case 256:
14438               oappend ("{1to4}");
14439               break;
14440             case 512:
14441               oappend ("{1to8}");
14442               break;
14443             default:
14444               abort ();
14445             }
14446         }
14447       else
14448         {
14449           switch (vex.length)
14450             {
14451             case 128:
14452               oappend ("{1to4}");
14453               break;
14454             case 256:
14455               oappend ("{1to8}");
14456               break;
14457             case 512:
14458               oappend ("{1to16}");
14459               break;
14460             default:
14461               abort ();
14462             }
14463         }
14464     }
14465 }
14466
14467 static void
14468 OP_E (int bytemode, int sizeflag)
14469 {
14470   /* Skip mod/rm byte.  */
14471   MODRM_CHECK;
14472   codep++;
14473
14474   if (modrm.mod == 3)
14475     OP_E_register (bytemode, sizeflag);
14476   else
14477     OP_E_memory (bytemode, sizeflag);
14478 }
14479
14480 static void
14481 OP_G (int bytemode, int sizeflag)
14482 {
14483   int add = 0;
14484   const char **names;
14485   USED_REX (REX_R);
14486   if (rex & REX_R)
14487     add += 8;
14488   switch (bytemode)
14489     {
14490     case b_mode:
14491       USED_REX (0);
14492       if (rex)
14493         oappend (names8rex[modrm.reg + add]);
14494       else
14495         oappend (names8[modrm.reg + add]);
14496       break;
14497     case w_mode:
14498       oappend (names16[modrm.reg + add]);
14499       break;
14500     case d_mode:
14501     case db_mode:
14502     case dw_mode:
14503       oappend (names32[modrm.reg + add]);
14504       break;
14505     case q_mode:
14506       oappend (names64[modrm.reg + add]);
14507       break;
14508     case bnd_mode:
14509       if (modrm.reg > 0x3)
14510         {
14511           oappend ("(bad)");
14512           return;
14513         }
14514       oappend (names_bnd[modrm.reg]);
14515       break;
14516     case v_mode:
14517     case dq_mode:
14518     case dqb_mode:
14519     case dqd_mode:
14520     case dqw_mode:
14521     case movsxd_mode:
14522       USED_REX (REX_W);
14523       if (rex & REX_W)
14524         oappend (names64[modrm.reg + add]);
14525       else
14526         {
14527           if ((sizeflag & DFLAG)
14528               || (bytemode != v_mode && bytemode != movsxd_mode))
14529             oappend (names32[modrm.reg + add]);
14530           else
14531             oappend (names16[modrm.reg + add]);
14532           used_prefixes |= (prefixes & PREFIX_DATA);
14533         }
14534       break;
14535     case va_mode:
14536       names = (address_mode == mode_64bit
14537                ? names64 : names32);
14538       if (!(prefixes & PREFIX_ADDR))
14539         {
14540           if (address_mode == mode_16bit)
14541             names = names16;
14542         }
14543       else
14544         {
14545           /* Remove "addr16/addr32".  */
14546           all_prefixes[last_addr_prefix] = 0;
14547           names = (address_mode != mode_32bit
14548                        ? names32 : names16);
14549           used_prefixes |= PREFIX_ADDR;
14550         }
14551       oappend (names[modrm.reg + add]);
14552       break;
14553     case m_mode:
14554       if (address_mode == mode_64bit)
14555         oappend (names64[modrm.reg + add]);
14556       else
14557         oappend (names32[modrm.reg + add]);
14558       break;
14559     case mask_bd_mode:
14560     case mask_mode:
14561       if ((modrm.reg + add) > 0x7)
14562         {
14563           oappend ("(bad)");
14564           return;
14565         }
14566       oappend (names_mask[modrm.reg + add]);
14567       break;
14568     default:
14569       oappend (INTERNAL_DISASSEMBLER_ERROR);
14570       break;
14571     }
14572 }
14573
14574 static bfd_vma
14575 get64 (void)
14576 {
14577   bfd_vma x;
14578 #ifdef BFD64
14579   unsigned int a;
14580   unsigned int b;
14581
14582   FETCH_DATA (the_info, codep + 8);
14583   a = *codep++ & 0xff;
14584   a |= (*codep++ & 0xff) << 8;
14585   a |= (*codep++ & 0xff) << 16;
14586   a |= (*codep++ & 0xffu) << 24;
14587   b = *codep++ & 0xff;
14588   b |= (*codep++ & 0xff) << 8;
14589   b |= (*codep++ & 0xff) << 16;
14590   b |= (*codep++ & 0xffu) << 24;
14591   x = a + ((bfd_vma) b << 32);
14592 #else
14593   abort ();
14594   x = 0;
14595 #endif
14596   return x;
14597 }
14598
14599 static bfd_signed_vma
14600 get32 (void)
14601 {
14602   bfd_signed_vma x = 0;
14603
14604   FETCH_DATA (the_info, codep + 4);
14605   x = *codep++ & (bfd_signed_vma) 0xff;
14606   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14607   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14608   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14609   return x;
14610 }
14611
14612 static bfd_signed_vma
14613 get32s (void)
14614 {
14615   bfd_signed_vma x = 0;
14616
14617   FETCH_DATA (the_info, codep + 4);
14618   x = *codep++ & (bfd_signed_vma) 0xff;
14619   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14620   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14621   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14622
14623   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14624
14625   return x;
14626 }
14627
14628 static int
14629 get16 (void)
14630 {
14631   int x = 0;
14632
14633   FETCH_DATA (the_info, codep + 2);
14634   x = *codep++ & 0xff;
14635   x |= (*codep++ & 0xff) << 8;
14636   return x;
14637 }
14638
14639 static void
14640 set_op (bfd_vma op, int riprel)
14641 {
14642   op_index[op_ad] = op_ad;
14643   if (address_mode == mode_64bit)
14644     {
14645       op_address[op_ad] = op;
14646       op_riprel[op_ad] = riprel;
14647     }
14648   else
14649     {
14650       /* Mask to get a 32-bit address.  */
14651       op_address[op_ad] = op & 0xffffffff;
14652       op_riprel[op_ad] = riprel & 0xffffffff;
14653     }
14654 }
14655
14656 static void
14657 OP_REG (int code, int sizeflag)
14658 {
14659   const char *s;
14660   int add;
14661
14662   switch (code)
14663     {
14664     case es_reg: case ss_reg: case cs_reg:
14665     case ds_reg: case fs_reg: case gs_reg:
14666       oappend (names_seg[code - es_reg]);
14667       return;
14668     }
14669
14670   USED_REX (REX_B);
14671   if (rex & REX_B)
14672     add = 8;
14673   else
14674     add = 0;
14675
14676   switch (code)
14677     {
14678     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14679     case sp_reg: case bp_reg: case si_reg: case di_reg:
14680       s = names16[code - ax_reg + add];
14681       break;
14682     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14683     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14684       USED_REX (0);
14685       if (rex)
14686         s = names8rex[code - al_reg + add];
14687       else
14688         s = names8[code - al_reg];
14689       break;
14690     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14691     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14692       if (address_mode == mode_64bit
14693           && ((sizeflag & DFLAG) || (rex & REX_W)))
14694         {
14695           s = names64[code - rAX_reg + add];
14696           break;
14697         }
14698       code += eAX_reg - rAX_reg;
14699       /* Fall through.  */
14700     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14701     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14702       USED_REX (REX_W);
14703       if (rex & REX_W)
14704         s = names64[code - eAX_reg + add];
14705       else
14706         {
14707           if (sizeflag & DFLAG)
14708             s = names32[code - eAX_reg + add];
14709           else
14710             s = names16[code - eAX_reg + add];
14711           used_prefixes |= (prefixes & PREFIX_DATA);
14712         }
14713       break;
14714     default:
14715       s = INTERNAL_DISASSEMBLER_ERROR;
14716       break;
14717     }
14718   oappend (s);
14719 }
14720
14721 static void
14722 OP_IMREG (int code, int sizeflag)
14723 {
14724   const char *s;
14725
14726   switch (code)
14727     {
14728     case indir_dx_reg:
14729       if (intel_syntax)
14730         s = "dx";
14731       else
14732         s = "(%dx)";
14733       break;
14734     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14735     case sp_reg: case bp_reg: case si_reg: case di_reg:
14736       s = names16[code - ax_reg];
14737       break;
14738     case es_reg: case ss_reg: case cs_reg:
14739     case ds_reg: case fs_reg: case gs_reg:
14740       s = names_seg[code - es_reg];
14741       break;
14742     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14743     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14744       USED_REX (0);
14745       if (rex)
14746         s = names8rex[code - al_reg];
14747       else
14748         s = names8[code - al_reg];
14749       break;
14750     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14751     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14752       USED_REX (REX_W);
14753       if (rex & REX_W)
14754         s = names64[code - eAX_reg];
14755       else
14756         {
14757           if (sizeflag & DFLAG)
14758             s = names32[code - eAX_reg];
14759           else
14760             s = names16[code - eAX_reg];
14761           used_prefixes |= (prefixes & PREFIX_DATA);
14762         }
14763       break;
14764     case z_mode_ax_reg:
14765       if ((rex & REX_W) || (sizeflag & DFLAG))
14766         s = *names32;
14767       else
14768         s = *names16;
14769       if (!(rex & REX_W))
14770         used_prefixes |= (prefixes & PREFIX_DATA);
14771       break;
14772     default:
14773       s = INTERNAL_DISASSEMBLER_ERROR;
14774       break;
14775     }
14776   oappend (s);
14777 }
14778
14779 static void
14780 OP_I (int bytemode, int sizeflag)
14781 {
14782   bfd_signed_vma op;
14783   bfd_signed_vma mask = -1;
14784
14785   switch (bytemode)
14786     {
14787     case b_mode:
14788       FETCH_DATA (the_info, codep + 1);
14789       op = *codep++;
14790       mask = 0xff;
14791       break;
14792     case v_mode:
14793       USED_REX (REX_W);
14794       if (rex & REX_W)
14795         op = get32s ();
14796       else
14797         {
14798           if (sizeflag & DFLAG)
14799             {
14800               op = get32 ();
14801               mask = 0xffffffff;
14802             }
14803           else
14804             {
14805               op = get16 ();
14806               mask = 0xfffff;
14807             }
14808           used_prefixes |= (prefixes & PREFIX_DATA);
14809         }
14810       break;
14811     case d_mode:
14812       mask = 0xffffffff;
14813       op = get32 ();
14814       break;
14815     case w_mode:
14816       mask = 0xfffff;
14817       op = get16 ();
14818       break;
14819     case const_1_mode:
14820       if (intel_syntax)
14821         oappend ("1");
14822       return;
14823     default:
14824       oappend (INTERNAL_DISASSEMBLER_ERROR);
14825       return;
14826     }
14827
14828   op &= mask;
14829   scratchbuf[0] = '$';
14830   print_operand_value (scratchbuf + 1, 1, op);
14831   oappend_maybe_intel (scratchbuf);
14832   scratchbuf[0] = '\0';
14833 }
14834
14835 static void
14836 OP_I64 (int bytemode, int sizeflag)
14837 {
14838   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14839     {
14840       OP_I (bytemode, sizeflag);
14841       return;
14842     }
14843
14844   USED_REX (REX_W);
14845
14846   scratchbuf[0] = '$';
14847   print_operand_value (scratchbuf + 1, 1, get64 ());
14848   oappend_maybe_intel (scratchbuf);
14849   scratchbuf[0] = '\0';
14850 }
14851
14852 static void
14853 OP_sI (int bytemode, int sizeflag)
14854 {
14855   bfd_signed_vma op;
14856
14857   switch (bytemode)
14858     {
14859     case b_mode:
14860     case b_T_mode:
14861       FETCH_DATA (the_info, codep + 1);
14862       op = *codep++;
14863       if ((op & 0x80) != 0)
14864         op -= 0x100;
14865       if (bytemode == b_T_mode)
14866         {
14867           if (address_mode != mode_64bit
14868               || !((sizeflag & DFLAG) || (rex & REX_W)))
14869             {
14870               /* The operand-size prefix is overridden by a REX prefix.  */
14871               if ((sizeflag & DFLAG) || (rex & REX_W))
14872                 op &= 0xffffffff;
14873               else
14874                 op &= 0xffff;
14875           }
14876         }
14877       else
14878         {
14879           if (!(rex & REX_W))
14880             {
14881               if (sizeflag & DFLAG)
14882                 op &= 0xffffffff;
14883               else
14884                 op &= 0xffff;
14885             }
14886         }
14887       break;
14888     case v_mode:
14889       /* The operand-size prefix is overridden by a REX prefix.  */
14890       if ((sizeflag & DFLAG) || (rex & REX_W))
14891         op = get32s ();
14892       else
14893         op = get16 ();
14894       break;
14895     default:
14896       oappend (INTERNAL_DISASSEMBLER_ERROR);
14897       return;
14898     }
14899
14900   scratchbuf[0] = '$';
14901   print_operand_value (scratchbuf + 1, 1, op);
14902   oappend_maybe_intel (scratchbuf);
14903 }
14904
14905 static void
14906 OP_J (int bytemode, int sizeflag)
14907 {
14908   bfd_vma disp;
14909   bfd_vma mask = -1;
14910   bfd_vma segment = 0;
14911
14912   switch (bytemode)
14913     {
14914     case b_mode:
14915       FETCH_DATA (the_info, codep + 1);
14916       disp = *codep++;
14917       if ((disp & 0x80) != 0)
14918         disp -= 0x100;
14919       break;
14920     case v_mode:
14921       if (isa64 != intel64)
14922     case dqw_mode:
14923         USED_REX (REX_W);
14924       if ((sizeflag & DFLAG)
14925           || (address_mode == mode_64bit
14926               && ((isa64 == intel64 && bytemode != dqw_mode)
14927                   || (rex & REX_W))))
14928         disp = get32s ();
14929       else
14930         {
14931           disp = get16 ();
14932           if ((disp & 0x8000) != 0)
14933             disp -= 0x10000;
14934           /* In 16bit mode, address is wrapped around at 64k within
14935              the same segment.  Otherwise, a data16 prefix on a jump
14936              instruction means that the pc is masked to 16 bits after
14937              the displacement is added!  */
14938           mask = 0xffff;
14939           if ((prefixes & PREFIX_DATA) == 0)
14940             segment = ((start_pc + (codep - start_codep))
14941                        & ~((bfd_vma) 0xffff));
14942         }
14943       if (address_mode != mode_64bit
14944           || (isa64 != intel64 && !(rex & REX_W)))
14945         used_prefixes |= (prefixes & PREFIX_DATA);
14946       break;
14947     default:
14948       oappend (INTERNAL_DISASSEMBLER_ERROR);
14949       return;
14950     }
14951   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14952   set_op (disp, 0);
14953   print_operand_value (scratchbuf, 1, disp);
14954   oappend (scratchbuf);
14955 }
14956
14957 static void
14958 OP_SEG (int bytemode, int sizeflag)
14959 {
14960   if (bytemode == w_mode)
14961     oappend (names_seg[modrm.reg]);
14962   else
14963     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14964 }
14965
14966 static void
14967 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14968 {
14969   int seg, offset;
14970
14971   if (sizeflag & DFLAG)
14972     {
14973       offset = get32 ();
14974       seg = get16 ();
14975     }
14976   else
14977     {
14978       offset = get16 ();
14979       seg = get16 ();
14980     }
14981   used_prefixes |= (prefixes & PREFIX_DATA);
14982   if (intel_syntax)
14983     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14984   else
14985     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14986   oappend (scratchbuf);
14987 }
14988
14989 static void
14990 OP_OFF (int bytemode, int sizeflag)
14991 {
14992   bfd_vma off;
14993
14994   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14995     intel_operand_size (bytemode, sizeflag);
14996   append_seg ();
14997
14998   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14999     off = get32 ();
15000   else
15001     off = get16 ();
15002
15003   if (intel_syntax)
15004     {
15005       if (!active_seg_prefix)
15006         {
15007           oappend (names_seg[ds_reg - es_reg]);
15008           oappend (":");
15009         }
15010     }
15011   print_operand_value (scratchbuf, 1, off);
15012   oappend (scratchbuf);
15013 }
15014
15015 static void
15016 OP_OFF64 (int bytemode, int sizeflag)
15017 {
15018   bfd_vma off;
15019
15020   if (address_mode != mode_64bit
15021       || (prefixes & PREFIX_ADDR))
15022     {
15023       OP_OFF (bytemode, sizeflag);
15024       return;
15025     }
15026
15027   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15028     intel_operand_size (bytemode, sizeflag);
15029   append_seg ();
15030
15031   off = get64 ();
15032
15033   if (intel_syntax)
15034     {
15035       if (!active_seg_prefix)
15036         {
15037           oappend (names_seg[ds_reg - es_reg]);
15038           oappend (":");
15039         }
15040     }
15041   print_operand_value (scratchbuf, 1, off);
15042   oappend (scratchbuf);
15043 }
15044
15045 static void
15046 ptr_reg (int code, int sizeflag)
15047 {
15048   const char *s;
15049
15050   *obufp++ = open_char;
15051   used_prefixes |= (prefixes & PREFIX_ADDR);
15052   if (address_mode == mode_64bit)
15053     {
15054       if (!(sizeflag & AFLAG))
15055         s = names32[code - eAX_reg];
15056       else
15057         s = names64[code - eAX_reg];
15058     }
15059   else if (sizeflag & AFLAG)
15060     s = names32[code - eAX_reg];
15061   else
15062     s = names16[code - eAX_reg];
15063   oappend (s);
15064   *obufp++ = close_char;
15065   *obufp = 0;
15066 }
15067
15068 static void
15069 OP_ESreg (int code, int sizeflag)
15070 {
15071   if (intel_syntax)
15072     {
15073       switch (codep[-1])
15074         {
15075         case 0x6d:      /* insw/insl */
15076           intel_operand_size (z_mode, sizeflag);
15077           break;
15078         case 0xa5:      /* movsw/movsl/movsq */
15079         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15080         case 0xab:      /* stosw/stosl */
15081         case 0xaf:      /* scasw/scasl */
15082           intel_operand_size (v_mode, sizeflag);
15083           break;
15084         default:
15085           intel_operand_size (b_mode, sizeflag);
15086         }
15087     }
15088   oappend_maybe_intel ("%es:");
15089   ptr_reg (code, sizeflag);
15090 }
15091
15092 static void
15093 OP_DSreg (int code, int sizeflag)
15094 {
15095   if (intel_syntax)
15096     {
15097       switch (codep[-1])
15098         {
15099         case 0x6f:      /* outsw/outsl */
15100           intel_operand_size (z_mode, sizeflag);
15101           break;
15102         case 0xa5:      /* movsw/movsl/movsq */
15103         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
15104         case 0xad:      /* lodsw/lodsl/lodsq */
15105           intel_operand_size (v_mode, sizeflag);
15106           break;
15107         default:
15108           intel_operand_size (b_mode, sizeflag);
15109         }
15110     }
15111   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15112      default segment register DS is printed.  */
15113   if (!active_seg_prefix)
15114     active_seg_prefix = PREFIX_DS;
15115   append_seg ();
15116   ptr_reg (code, sizeflag);
15117 }
15118
15119 static void
15120 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15121 {
15122   int add;
15123   if (rex & REX_R)
15124     {
15125       USED_REX (REX_R);
15126       add = 8;
15127     }
15128   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15129     {
15130       all_prefixes[last_lock_prefix] = 0;
15131       used_prefixes |= PREFIX_LOCK;
15132       add = 8;
15133     }
15134   else
15135     add = 0;
15136   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15137   oappend_maybe_intel (scratchbuf);
15138 }
15139
15140 static void
15141 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15142 {
15143   int add;
15144   USED_REX (REX_R);
15145   if (rex & REX_R)
15146     add = 8;
15147   else
15148     add = 0;
15149   if (intel_syntax)
15150     sprintf (scratchbuf, "db%d", modrm.reg + add);
15151   else
15152     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15153   oappend (scratchbuf);
15154 }
15155
15156 static void
15157 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15158 {
15159   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15160   oappend_maybe_intel (scratchbuf);
15161 }
15162
15163 static void
15164 OP_R (int bytemode, int sizeflag)
15165 {
15166   /* Skip mod/rm byte.  */
15167   MODRM_CHECK;
15168   codep++;
15169   OP_E_register (bytemode, sizeflag);
15170 }
15171
15172 static void
15173 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15174 {
15175   int reg = modrm.reg;
15176   const char **names;
15177
15178   used_prefixes |= (prefixes & PREFIX_DATA);
15179   if (prefixes & PREFIX_DATA)
15180     {
15181       names = names_xmm;
15182       USED_REX (REX_R);
15183       if (rex & REX_R)
15184         reg += 8;
15185     }
15186   else
15187     names = names_mm;
15188   oappend (names[reg]);
15189 }
15190
15191 static void
15192 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15193 {
15194   int reg = modrm.reg;
15195   const char **names;
15196
15197   USED_REX (REX_R);
15198   if (rex & REX_R)
15199     reg += 8;
15200   if (vex.evex)
15201     {
15202       if (!vex.r)
15203         reg += 16;
15204     }
15205
15206   if (need_vex
15207       && bytemode != xmm_mode
15208       && bytemode != xmmq_mode
15209       && bytemode != evex_half_bcst_xmmq_mode
15210       && bytemode != ymm_mode
15211       && bytemode != scalar_mode)
15212     {
15213       switch (vex.length)
15214         {
15215         case 128:
15216           names = names_xmm;
15217           break;
15218         case 256:
15219           if (vex.w
15220               || (bytemode != vex_vsib_q_w_dq_mode
15221                   && bytemode != vex_vsib_q_w_d_mode))
15222             names = names_ymm;
15223           else
15224             names = names_xmm;
15225           break;
15226         case 512:
15227           names = names_zmm;
15228           break;
15229         default:
15230           abort ();
15231         }
15232     }
15233   else if (bytemode == xmmq_mode
15234            || bytemode == evex_half_bcst_xmmq_mode)
15235     {
15236       switch (vex.length)
15237         {
15238         case 128:
15239         case 256:
15240           names = names_xmm;
15241           break;
15242         case 512:
15243           names = names_ymm;
15244           break;
15245         default:
15246           abort ();
15247         }
15248     }
15249   else if (bytemode == ymm_mode)
15250     names = names_ymm;
15251   else
15252     names = names_xmm;
15253   oappend (names[reg]);
15254 }
15255
15256 static void
15257 OP_EM (int bytemode, int sizeflag)
15258 {
15259   int reg;
15260   const char **names;
15261
15262   if (modrm.mod != 3)
15263     {
15264       if (intel_syntax
15265           && (bytemode == v_mode || bytemode == v_swap_mode))
15266         {
15267           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15268           used_prefixes |= (prefixes & PREFIX_DATA);
15269         }
15270       OP_E (bytemode, sizeflag);
15271       return;
15272     }
15273
15274   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15275     swap_operand ();
15276
15277   /* Skip mod/rm byte.  */
15278   MODRM_CHECK;
15279   codep++;
15280   used_prefixes |= (prefixes & PREFIX_DATA);
15281   reg = modrm.rm;
15282   if (prefixes & PREFIX_DATA)
15283     {
15284       names = names_xmm;
15285       USED_REX (REX_B);
15286       if (rex & REX_B)
15287         reg += 8;
15288     }
15289   else
15290     names = names_mm;
15291   oappend (names[reg]);
15292 }
15293
15294 /* cvt* are the only instructions in sse2 which have
15295    both SSE and MMX operands and also have 0x66 prefix
15296    in their opcode. 0x66 was originally used to differentiate
15297    between SSE and MMX instruction(operands). So we have to handle the
15298    cvt* separately using OP_EMC and OP_MXC */
15299 static void
15300 OP_EMC (int bytemode, int sizeflag)
15301 {
15302   if (modrm.mod != 3)
15303     {
15304       if (intel_syntax && bytemode == v_mode)
15305         {
15306           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15307           used_prefixes |= (prefixes & PREFIX_DATA);
15308         }
15309       OP_E (bytemode, sizeflag);
15310       return;
15311     }
15312
15313   /* Skip mod/rm byte.  */
15314   MODRM_CHECK;
15315   codep++;
15316   used_prefixes |= (prefixes & PREFIX_DATA);
15317   oappend (names_mm[modrm.rm]);
15318 }
15319
15320 static void
15321 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15322 {
15323   used_prefixes |= (prefixes & PREFIX_DATA);
15324   oappend (names_mm[modrm.reg]);
15325 }
15326
15327 static void
15328 OP_EX (int bytemode, int sizeflag)
15329 {
15330   int reg;
15331   const char **names;
15332
15333   /* Skip mod/rm byte.  */
15334   MODRM_CHECK;
15335   codep++;
15336
15337   if (modrm.mod != 3)
15338     {
15339       OP_E_memory (bytemode, sizeflag);
15340       return;
15341     }
15342
15343   reg = modrm.rm;
15344   USED_REX (REX_B);
15345   if (rex & REX_B)
15346     reg += 8;
15347   if (vex.evex)
15348     {
15349       USED_REX (REX_X);
15350       if ((rex & REX_X))
15351         reg += 16;
15352     }
15353
15354   if ((sizeflag & SUFFIX_ALWAYS)
15355       && (bytemode == x_swap_mode
15356           || bytemode == d_swap_mode
15357           || bytemode == d_scalar_swap_mode
15358           || bytemode == q_swap_mode
15359           || bytemode == q_scalar_swap_mode))
15360     swap_operand ();
15361
15362   if (need_vex
15363       && bytemode != xmm_mode
15364       && bytemode != xmmdw_mode
15365       && bytemode != xmmqd_mode
15366       && bytemode != xmm_mb_mode
15367       && bytemode != xmm_mw_mode
15368       && bytemode != xmm_md_mode
15369       && bytemode != xmm_mq_mode
15370       && bytemode != xmm_mdq_mode
15371       && bytemode != xmmq_mode
15372       && bytemode != evex_half_bcst_xmmq_mode
15373       && bytemode != ymm_mode
15374       && bytemode != d_scalar_mode
15375       && bytemode != d_scalar_swap_mode
15376       && bytemode != q_scalar_mode
15377       && bytemode != q_scalar_swap_mode
15378       && bytemode != vex_scalar_w_dq_mode)
15379     {
15380       switch (vex.length)
15381         {
15382         case 128:
15383           names = names_xmm;
15384           break;
15385         case 256:
15386           names = names_ymm;
15387           break;
15388         case 512:
15389           names = names_zmm;
15390           break;
15391         default:
15392           abort ();
15393         }
15394     }
15395   else if (bytemode == xmmq_mode
15396            || bytemode == evex_half_bcst_xmmq_mode)
15397     {
15398       switch (vex.length)
15399         {
15400         case 128:
15401         case 256:
15402           names = names_xmm;
15403           break;
15404         case 512:
15405           names = names_ymm;
15406           break;
15407         default:
15408           abort ();
15409         }
15410     }
15411   else if (bytemode == ymm_mode)
15412     names = names_ymm;
15413   else
15414     names = names_xmm;
15415   oappend (names[reg]);
15416 }
15417
15418 static void
15419 OP_MS (int bytemode, int sizeflag)
15420 {
15421   if (modrm.mod == 3)
15422     OP_EM (bytemode, sizeflag);
15423   else
15424     BadOp ();
15425 }
15426
15427 static void
15428 OP_XS (int bytemode, int sizeflag)
15429 {
15430   if (modrm.mod == 3)
15431     OP_EX (bytemode, sizeflag);
15432   else
15433     BadOp ();
15434 }
15435
15436 static void
15437 OP_M (int bytemode, int sizeflag)
15438 {
15439   if (modrm.mod == 3)
15440     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15441     BadOp ();
15442   else
15443     OP_E (bytemode, sizeflag);
15444 }
15445
15446 static void
15447 OP_0f07 (int bytemode, int sizeflag)
15448 {
15449   if (modrm.mod != 3 || modrm.rm != 0)
15450     BadOp ();
15451   else
15452     OP_E (bytemode, sizeflag);
15453 }
15454
15455 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15456    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15457
15458 static void
15459 NOP_Fixup1 (int bytemode, int sizeflag)
15460 {
15461   if ((prefixes & PREFIX_DATA) != 0
15462       || (rex != 0
15463           && rex != 0x48
15464           && address_mode == mode_64bit))
15465     OP_REG (bytemode, sizeflag);
15466   else
15467     strcpy (obuf, "nop");
15468 }
15469
15470 static void
15471 NOP_Fixup2 (int bytemode, int sizeflag)
15472 {
15473   if ((prefixes & PREFIX_DATA) != 0
15474       || (rex != 0
15475           && rex != 0x48
15476           && address_mode == mode_64bit))
15477     OP_IMREG (bytemode, sizeflag);
15478 }
15479
15480 static const char *const Suffix3DNow[] = {
15481 /* 00 */        NULL,           NULL,           NULL,           NULL,
15482 /* 04 */        NULL,           NULL,           NULL,           NULL,
15483 /* 08 */        NULL,           NULL,           NULL,           NULL,
15484 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15485 /* 10 */        NULL,           NULL,           NULL,           NULL,
15486 /* 14 */        NULL,           NULL,           NULL,           NULL,
15487 /* 18 */        NULL,           NULL,           NULL,           NULL,
15488 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15489 /* 20 */        NULL,           NULL,           NULL,           NULL,
15490 /* 24 */        NULL,           NULL,           NULL,           NULL,
15491 /* 28 */        NULL,           NULL,           NULL,           NULL,
15492 /* 2C */        NULL,           NULL,           NULL,           NULL,
15493 /* 30 */        NULL,           NULL,           NULL,           NULL,
15494 /* 34 */        NULL,           NULL,           NULL,           NULL,
15495 /* 38 */        NULL,           NULL,           NULL,           NULL,
15496 /* 3C */        NULL,           NULL,           NULL,           NULL,
15497 /* 40 */        NULL,           NULL,           NULL,           NULL,
15498 /* 44 */        NULL,           NULL,           NULL,           NULL,
15499 /* 48 */        NULL,           NULL,           NULL,           NULL,
15500 /* 4C */        NULL,           NULL,           NULL,           NULL,
15501 /* 50 */        NULL,           NULL,           NULL,           NULL,
15502 /* 54 */        NULL,           NULL,           NULL,           NULL,
15503 /* 58 */        NULL,           NULL,           NULL,           NULL,
15504 /* 5C */        NULL,           NULL,           NULL,           NULL,
15505 /* 60 */        NULL,           NULL,           NULL,           NULL,
15506 /* 64 */        NULL,           NULL,           NULL,           NULL,
15507 /* 68 */        NULL,           NULL,           NULL,           NULL,
15508 /* 6C */        NULL,           NULL,           NULL,           NULL,
15509 /* 70 */        NULL,           NULL,           NULL,           NULL,
15510 /* 74 */        NULL,           NULL,           NULL,           NULL,
15511 /* 78 */        NULL,           NULL,           NULL,           NULL,
15512 /* 7C */        NULL,           NULL,           NULL,           NULL,
15513 /* 80 */        NULL,           NULL,           NULL,           NULL,
15514 /* 84 */        NULL,           NULL,           NULL,           NULL,
15515 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15516 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15517 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15518 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15519 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15520 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15521 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15522 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15523 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15524 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15525 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15526 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15527 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15528 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15529 /* C0 */        NULL,           NULL,           NULL,           NULL,
15530 /* C4 */        NULL,           NULL,           NULL,           NULL,
15531 /* C8 */        NULL,           NULL,           NULL,           NULL,
15532 /* CC */        NULL,           NULL,           NULL,           NULL,
15533 /* D0 */        NULL,           NULL,           NULL,           NULL,
15534 /* D4 */        NULL,           NULL,           NULL,           NULL,
15535 /* D8 */        NULL,           NULL,           NULL,           NULL,
15536 /* DC */        NULL,           NULL,           NULL,           NULL,
15537 /* E0 */        NULL,           NULL,           NULL,           NULL,
15538 /* E4 */        NULL,           NULL,           NULL,           NULL,
15539 /* E8 */        NULL,           NULL,           NULL,           NULL,
15540 /* EC */        NULL,           NULL,           NULL,           NULL,
15541 /* F0 */        NULL,           NULL,           NULL,           NULL,
15542 /* F4 */        NULL,           NULL,           NULL,           NULL,
15543 /* F8 */        NULL,           NULL,           NULL,           NULL,
15544 /* FC */        NULL,           NULL,           NULL,           NULL,
15545 };
15546
15547 static void
15548 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15549 {
15550   const char *mnemonic;
15551
15552   FETCH_DATA (the_info, codep + 1);
15553   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15554      place where an 8-bit immediate would normally go.  ie. the last
15555      byte of the instruction.  */
15556   obufp = mnemonicendp;
15557   mnemonic = Suffix3DNow[*codep++ & 0xff];
15558   if (mnemonic)
15559     oappend (mnemonic);
15560   else
15561     {
15562       /* Since a variable sized modrm/sib chunk is between the start
15563          of the opcode (0x0f0f) and the opcode suffix, we need to do
15564          all the modrm processing first, and don't know until now that
15565          we have a bad opcode.  This necessitates some cleaning up.  */
15566       op_out[0][0] = '\0';
15567       op_out[1][0] = '\0';
15568       BadOp ();
15569     }
15570   mnemonicendp = obufp;
15571 }
15572
15573 static struct op simd_cmp_op[] =
15574 {
15575   { STRING_COMMA_LEN ("eq") },
15576   { STRING_COMMA_LEN ("lt") },
15577   { STRING_COMMA_LEN ("le") },
15578   { STRING_COMMA_LEN ("unord") },
15579   { STRING_COMMA_LEN ("neq") },
15580   { STRING_COMMA_LEN ("nlt") },
15581   { STRING_COMMA_LEN ("nle") },
15582   { STRING_COMMA_LEN ("ord") }
15583 };
15584
15585 static void
15586 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15587 {
15588   unsigned int cmp_type;
15589
15590   FETCH_DATA (the_info, codep + 1);
15591   cmp_type = *codep++ & 0xff;
15592   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15593     {
15594       char suffix [3];
15595       char *p = mnemonicendp - 2;
15596       suffix[0] = p[0];
15597       suffix[1] = p[1];
15598       suffix[2] = '\0';
15599       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15600       mnemonicendp += simd_cmp_op[cmp_type].len;
15601     }
15602   else
15603     {
15604       /* We have a reserved extension byte.  Output it directly.  */
15605       scratchbuf[0] = '$';
15606       print_operand_value (scratchbuf + 1, 1, cmp_type);
15607       oappend_maybe_intel (scratchbuf);
15608       scratchbuf[0] = '\0';
15609     }
15610 }
15611
15612 static void
15613 OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15614 {
15615   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
15616   if (!intel_syntax)
15617     {
15618       strcpy (op_out[0], names32[0]);
15619       strcpy (op_out[1], names32[1]);
15620       if (bytemode == eBX_reg)
15621         strcpy (op_out[2], names32[3]);
15622       two_source_ops = 1;
15623     }
15624   /* Skip mod/rm byte.  */
15625   MODRM_CHECK;
15626   codep++;
15627 }
15628
15629 static void
15630 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15631             int sizeflag ATTRIBUTE_UNUSED)
15632 {
15633   /* monitor %{e,r,}ax,%ecx,%edx"  */
15634   if (!intel_syntax)
15635     {
15636       const char **names = (address_mode == mode_64bit
15637                             ? names64 : names32);
15638
15639       if (prefixes & PREFIX_ADDR)
15640         {
15641           /* Remove "addr16/addr32".  */
15642           all_prefixes[last_addr_prefix] = 0;
15643           names = (address_mode != mode_32bit
15644                    ? names32 : names16);
15645           used_prefixes |= PREFIX_ADDR;
15646         }
15647       else if (address_mode == mode_16bit)
15648         names = names16;
15649       strcpy (op_out[0], names[0]);
15650       strcpy (op_out[1], names32[1]);
15651       strcpy (op_out[2], names32[2]);
15652       two_source_ops = 1;
15653     }
15654   /* Skip mod/rm byte.  */
15655   MODRM_CHECK;
15656   codep++;
15657 }
15658
15659 static void
15660 BadOp (void)
15661 {
15662   /* Throw away prefixes and 1st. opcode byte.  */
15663   codep = insn_codep + 1;
15664   oappend ("(bad)");
15665 }
15666
15667 static void
15668 REP_Fixup (int bytemode, int sizeflag)
15669 {
15670   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15671      lods and stos.  */
15672   if (prefixes & PREFIX_REPZ)
15673     all_prefixes[last_repz_prefix] = REP_PREFIX;
15674
15675   switch (bytemode)
15676     {
15677     case al_reg:
15678     case eAX_reg:
15679     case indir_dx_reg:
15680       OP_IMREG (bytemode, sizeflag);
15681       break;
15682     case eDI_reg:
15683       OP_ESreg (bytemode, sizeflag);
15684       break;
15685     case eSI_reg:
15686       OP_DSreg (bytemode, sizeflag);
15687       break;
15688     default:
15689       abort ();
15690       break;
15691     }
15692 }
15693
15694 static void
15695 SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15696 {
15697   if ( isa64 != amd64 )
15698     return;
15699
15700   obufp = obuf;
15701   BadOp ();
15702   mnemonicendp = obufp;
15703   ++codep;
15704 }
15705
15706 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15707    "bnd".  */
15708
15709 static void
15710 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15711 {
15712   if (prefixes & PREFIX_REPNZ)
15713     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15714 }
15715
15716 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15717    "notrack".  */
15718
15719 static void
15720 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15721                int sizeflag ATTRIBUTE_UNUSED)
15722 {
15723   if (active_seg_prefix == PREFIX_DS
15724       && (address_mode != mode_64bit || last_data_prefix < 0))
15725     {
15726       /* NOTRACK prefix is only valid on indirect branch instructions.
15727          NB: DATA prefix is unsupported for Intel64.  */
15728       active_seg_prefix = 0;
15729       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15730     }
15731 }
15732
15733 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15734    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15735  */
15736
15737 static void
15738 HLE_Fixup1 (int bytemode, int sizeflag)
15739 {
15740   if (modrm.mod != 3
15741       && (prefixes & PREFIX_LOCK) != 0)
15742     {
15743       if (prefixes & PREFIX_REPZ)
15744         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15745       if (prefixes & PREFIX_REPNZ)
15746         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15747     }
15748
15749   OP_E (bytemode, sizeflag);
15750 }
15751
15752 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15753    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15754  */
15755
15756 static void
15757 HLE_Fixup2 (int bytemode, int sizeflag)
15758 {
15759   if (modrm.mod != 3)
15760     {
15761       if (prefixes & PREFIX_REPZ)
15762         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15763       if (prefixes & PREFIX_REPNZ)
15764         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15765     }
15766
15767   OP_E (bytemode, sizeflag);
15768 }
15769
15770 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15771    "xrelease" for memory operand.  No check for LOCK prefix.   */
15772
15773 static void
15774 HLE_Fixup3 (int bytemode, int sizeflag)
15775 {
15776   if (modrm.mod != 3
15777       && last_repz_prefix > last_repnz_prefix
15778       && (prefixes & PREFIX_REPZ) != 0)
15779     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15780
15781   OP_E (bytemode, sizeflag);
15782 }
15783
15784 static void
15785 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15786 {
15787   USED_REX (REX_W);
15788   if (rex & REX_W)
15789     {
15790       /* Change cmpxchg8b to cmpxchg16b.  */
15791       char *p = mnemonicendp - 2;
15792       mnemonicendp = stpcpy (p, "16b");
15793       bytemode = o_mode;
15794     }
15795   else if ((prefixes & PREFIX_LOCK) != 0)
15796     {
15797       if (prefixes & PREFIX_REPZ)
15798         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15799       if (prefixes & PREFIX_REPNZ)
15800         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15801     }
15802
15803   OP_M (bytemode, sizeflag);
15804 }
15805
15806 static void
15807 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15808 {
15809   const char **names;
15810
15811   if (need_vex)
15812     {
15813       switch (vex.length)
15814         {
15815         case 128:
15816           names = names_xmm;
15817           break;
15818         case 256:
15819           names = names_ymm;
15820           break;
15821         default:
15822           abort ();
15823         }
15824     }
15825   else
15826     names = names_xmm;
15827   oappend (names[reg]);
15828 }
15829
15830 static void
15831 CRC32_Fixup (int bytemode, int sizeflag)
15832 {
15833   /* Add proper suffix to "crc32".  */
15834   char *p = mnemonicendp;
15835
15836   switch (bytemode)
15837     {
15838     case b_mode:
15839       if (intel_syntax)
15840         goto skip;
15841
15842       *p++ = 'b';
15843       break;
15844     case v_mode:
15845       if (intel_syntax)
15846         goto skip;
15847
15848       USED_REX (REX_W);
15849       if (rex & REX_W)
15850         *p++ = 'q';
15851       else
15852         {
15853           if (sizeflag & DFLAG)
15854             *p++ = 'l';
15855           else
15856             *p++ = 'w';
15857           used_prefixes |= (prefixes & PREFIX_DATA);
15858         }
15859       break;
15860     default:
15861       oappend (INTERNAL_DISASSEMBLER_ERROR);
15862       break;
15863     }
15864   mnemonicendp = p;
15865   *p = '\0';
15866
15867 skip:
15868   if (modrm.mod == 3)
15869     {
15870       int add;
15871
15872       /* Skip mod/rm byte.  */
15873       MODRM_CHECK;
15874       codep++;
15875
15876       USED_REX (REX_B);
15877       add = (rex & REX_B) ? 8 : 0;
15878       if (bytemode == b_mode)
15879         {
15880           USED_REX (0);
15881           if (rex)
15882             oappend (names8rex[modrm.rm + add]);
15883           else
15884             oappend (names8[modrm.rm + add]);
15885         }
15886       else
15887         {
15888           USED_REX (REX_W);
15889           if (rex & REX_W)
15890             oappend (names64[modrm.rm + add]);
15891           else if ((prefixes & PREFIX_DATA))
15892             oappend (names16[modrm.rm + add]);
15893           else
15894             oappend (names32[modrm.rm + add]);
15895         }
15896     }
15897   else
15898     OP_E (bytemode, sizeflag);
15899 }
15900
15901 static void
15902 FXSAVE_Fixup (int bytemode, int sizeflag)
15903 {
15904   /* Add proper suffix to "fxsave" and "fxrstor".  */
15905   USED_REX (REX_W);
15906   if (rex & REX_W)
15907     {
15908       char *p = mnemonicendp;
15909       *p++ = '6';
15910       *p++ = '4';
15911       *p = '\0';
15912       mnemonicendp = p;
15913     }
15914   OP_M (bytemode, sizeflag);
15915 }
15916
15917 static void
15918 PCMPESTR_Fixup (int bytemode, int sizeflag)
15919 {
15920   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15921   if (!intel_syntax)
15922     {
15923       char *p = mnemonicendp;
15924
15925       USED_REX (REX_W);
15926       if (rex & REX_W)
15927         *p++ = 'q';
15928       else if (sizeflag & SUFFIX_ALWAYS)
15929         *p++ = 'l';
15930
15931       *p = '\0';
15932       mnemonicendp = p;
15933     }
15934
15935   OP_EX (bytemode, sizeflag);
15936 }
15937
15938 /* Display the destination register operand for instructions with
15939    VEX. */
15940
15941 static void
15942 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15943 {
15944   int reg;
15945   const char **names;
15946
15947   if (!need_vex)
15948     abort ();
15949
15950   if (!need_vex_reg)
15951     return;
15952
15953   reg = vex.register_specifier;
15954   vex.register_specifier = 0;
15955   if (address_mode != mode_64bit)
15956     reg &= 7;
15957   else if (vex.evex && !vex.v)
15958     reg += 16;
15959
15960   if (bytemode == vex_scalar_mode)
15961     {
15962       oappend (names_xmm[reg]);
15963       return;
15964     }
15965
15966   switch (vex.length)
15967     {
15968     case 128:
15969       switch (bytemode)
15970         {
15971         case vex_mode:
15972         case vex128_mode:
15973         case vex_vsib_q_w_dq_mode:
15974         case vex_vsib_q_w_d_mode:
15975           names = names_xmm;
15976           break;
15977         case dq_mode:
15978           if (rex & REX_W)
15979             names = names64;
15980           else
15981             names = names32;
15982           break;
15983         case mask_bd_mode:
15984         case mask_mode:
15985           if (reg > 0x7)
15986             {
15987               oappend ("(bad)");
15988               return;
15989             }
15990           names = names_mask;
15991           break;
15992         default:
15993           abort ();
15994           return;
15995         }
15996       break;
15997     case 256:
15998       switch (bytemode)
15999         {
16000         case vex_mode:
16001         case vex256_mode:
16002           names = names_ymm;
16003           break;
16004         case vex_vsib_q_w_dq_mode:
16005         case vex_vsib_q_w_d_mode:
16006           names = vex.w ? names_ymm : names_xmm;
16007           break;
16008         case mask_bd_mode:
16009         case mask_mode:
16010           if (reg > 0x7)
16011             {
16012               oappend ("(bad)");
16013               return;
16014             }
16015           names = names_mask;
16016           break;
16017         default:
16018           /* See PR binutils/20893 for a reproducer.  */
16019           oappend ("(bad)");
16020           return;
16021         }
16022       break;
16023     case 512:
16024       names = names_zmm;
16025       break;
16026     default:
16027       abort ();
16028       break;
16029     }
16030   oappend (names[reg]);
16031 }
16032
16033 /* Get the VEX immediate byte without moving codep.  */
16034
16035 static unsigned char
16036 get_vex_imm8 (int sizeflag, int opnum)
16037 {
16038   int bytes_before_imm = 0;
16039
16040   if (modrm.mod != 3)
16041     {
16042       /* There are SIB/displacement bytes.  */
16043       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16044         {
16045           /* 32/64 bit address mode */
16046           int base = modrm.rm;
16047
16048           /* Check SIB byte.  */
16049           if (base == 4)
16050             {
16051               FETCH_DATA (the_info, codep + 1);
16052               base = *codep & 7;
16053               /* When decoding the third source, don't increase
16054                  bytes_before_imm as this has already been incremented
16055                  by one in OP_E_memory while decoding the second
16056                  source operand.  */
16057               if (opnum == 0)
16058                 bytes_before_imm++;
16059             }
16060
16061           /* Don't increase bytes_before_imm when decoding the third source,
16062              it has already been incremented by OP_E_memory while decoding
16063              the second source operand.  */
16064           if (opnum == 0)
16065             {
16066               switch (modrm.mod)
16067                 {
16068                   case 0:
16069                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
16070                        SIB == 5, there is a 4 byte displacement.  */
16071                     if (base != 5)
16072                       /* No displacement. */
16073                       break;
16074                     /* Fall through.  */
16075                   case 2:
16076                     /* 4 byte displacement.  */
16077                     bytes_before_imm += 4;
16078                     break;
16079                   case 1:
16080                     /* 1 byte displacement.  */
16081                     bytes_before_imm++;
16082                     break;
16083                 }
16084             }
16085         }
16086       else
16087         {
16088           /* 16 bit address mode */
16089           /* Don't increase bytes_before_imm when decoding the third source,
16090              it has already been incremented by OP_E_memory while decoding
16091              the second source operand.  */
16092           if (opnum == 0)
16093             {
16094               switch (modrm.mod)
16095                 {
16096                 case 0:
16097                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16098                   if (modrm.rm != 6)
16099                     /* No displacement. */
16100                     break;
16101                   /* Fall through.  */
16102                 case 2:
16103                   /* 2 byte displacement.  */
16104                   bytes_before_imm += 2;
16105                   break;
16106                 case 1:
16107                   /* 1 byte displacement: when decoding the third source,
16108                      don't increase bytes_before_imm as this has already
16109                      been incremented by one in OP_E_memory while decoding
16110                      the second source operand.  */
16111                   if (opnum == 0)
16112                     bytes_before_imm++;
16113
16114                   break;
16115                 }
16116             }
16117         }
16118     }
16119
16120   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16121   return codep [bytes_before_imm];
16122 }
16123
16124 static void
16125 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16126 {
16127   const char **names;
16128
16129   if (reg == -1 && modrm.mod != 3)
16130     {
16131       OP_E_memory (bytemode, sizeflag);
16132       return;
16133     }
16134   else
16135     {
16136       if (reg == -1)
16137         {
16138           reg = modrm.rm;
16139           USED_REX (REX_B);
16140           if (rex & REX_B)
16141             reg += 8;
16142         }
16143       if (address_mode != mode_64bit)
16144         reg &= 7;
16145     }
16146
16147   switch (vex.length)
16148     {
16149     case 128:
16150       names = names_xmm;
16151       break;
16152     case 256:
16153       names = names_ymm;
16154       break;
16155     default:
16156       abort ();
16157     }
16158   oappend (names[reg]);
16159 }
16160
16161 static void
16162 OP_EX_VexImmW (int bytemode, int sizeflag)
16163 {
16164   int reg = -1;
16165   static unsigned char vex_imm8;
16166
16167   if (vex_w_done == 0)
16168     {
16169       vex_w_done = 1;
16170
16171       /* Skip mod/rm byte.  */
16172       MODRM_CHECK;
16173       codep++;
16174
16175       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16176
16177       if (vex.w)
16178           reg = vex_imm8 >> 4;
16179
16180       OP_EX_VexReg (bytemode, sizeflag, reg);
16181     }
16182   else if (vex_w_done == 1)
16183     {
16184       vex_w_done = 2;
16185
16186       if (!vex.w)
16187           reg = vex_imm8 >> 4;
16188
16189       OP_EX_VexReg (bytemode, sizeflag, reg);
16190     }
16191   else
16192     {
16193       /* Output the imm8 directly.  */
16194       scratchbuf[0] = '$';
16195       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16196       oappend_maybe_intel (scratchbuf);
16197       scratchbuf[0] = '\0';
16198       codep++;
16199     }
16200 }
16201
16202 static void
16203 OP_Vex_2src (int bytemode, int sizeflag)
16204 {
16205   if (modrm.mod == 3)
16206     {
16207       int reg = modrm.rm;
16208       USED_REX (REX_B);
16209       if (rex & REX_B)
16210         reg += 8;
16211       oappend (names_xmm[reg]);
16212     }
16213   else
16214     {
16215       if (intel_syntax
16216           && (bytemode == v_mode || bytemode == v_swap_mode))
16217         {
16218           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16219           used_prefixes |= (prefixes & PREFIX_DATA);
16220         }
16221       OP_E (bytemode, sizeflag);
16222     }
16223 }
16224
16225 static void
16226 OP_Vex_2src_1 (int bytemode, int sizeflag)
16227 {
16228   if (modrm.mod == 3)
16229     {
16230       /* Skip mod/rm byte.   */
16231       MODRM_CHECK;
16232       codep++;
16233     }
16234
16235   if (vex.w)
16236     {
16237       unsigned int reg = vex.register_specifier;
16238       vex.register_specifier = 0;
16239
16240       if (address_mode != mode_64bit)
16241         reg &= 7;
16242       oappend (names_xmm[reg]);
16243     }
16244   else
16245     OP_Vex_2src (bytemode, sizeflag);
16246 }
16247
16248 static void
16249 OP_Vex_2src_2 (int bytemode, int sizeflag)
16250 {
16251   if (vex.w)
16252     OP_Vex_2src (bytemode, sizeflag);
16253   else
16254     {
16255       unsigned int reg = vex.register_specifier;
16256       vex.register_specifier = 0;
16257
16258       if (address_mode != mode_64bit)
16259         reg &= 7;
16260       oappend (names_xmm[reg]);
16261     }
16262 }
16263
16264 static void
16265 OP_EX_VexW (int bytemode, int sizeflag)
16266 {
16267   int reg = -1;
16268
16269   if (!vex_w_done)
16270     {
16271       /* Skip mod/rm byte.  */
16272       MODRM_CHECK;
16273       codep++;
16274
16275       if (vex.w)
16276         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16277     }
16278   else
16279     {
16280       if (!vex.w)
16281         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16282     }
16283
16284   OP_EX_VexReg (bytemode, sizeflag, reg);
16285
16286   if (vex_w_done)
16287     codep++;
16288   vex_w_done = 1;
16289 }
16290
16291 static void
16292 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16293 {
16294   int reg;
16295   const char **names;
16296
16297   FETCH_DATA (the_info, codep + 1);
16298   reg = *codep++;
16299
16300   if (bytemode != x_mode)
16301     abort ();
16302
16303   reg >>= 4;
16304   if (address_mode != mode_64bit)
16305     reg &= 7;
16306
16307   switch (vex.length)
16308     {
16309     case 128:
16310       names = names_xmm;
16311       break;
16312     case 256:
16313       names = names_ymm;
16314       break;
16315     default:
16316       abort ();
16317     }
16318   oappend (names[reg]);
16319 }
16320
16321 static void
16322 OP_XMM_VexW (int bytemode, int sizeflag)
16323 {
16324   /* Turn off the REX.W bit since it is used for swapping operands
16325      now.  */
16326   rex &= ~REX_W;
16327   OP_XMM (bytemode, sizeflag);
16328 }
16329
16330 static void
16331 OP_EX_Vex (int bytemode, int sizeflag)
16332 {
16333   if (modrm.mod != 3)
16334     need_vex_reg = 0;
16335   OP_EX (bytemode, sizeflag);
16336 }
16337
16338 static void
16339 OP_XMM_Vex (int bytemode, int sizeflag)
16340 {
16341   if (modrm.mod != 3)
16342     need_vex_reg = 0;
16343   OP_XMM (bytemode, sizeflag);
16344 }
16345
16346 static struct op vex_cmp_op[] =
16347 {
16348   { STRING_COMMA_LEN ("eq") },
16349   { STRING_COMMA_LEN ("lt") },
16350   { STRING_COMMA_LEN ("le") },
16351   { STRING_COMMA_LEN ("unord") },
16352   { STRING_COMMA_LEN ("neq") },
16353   { STRING_COMMA_LEN ("nlt") },
16354   { STRING_COMMA_LEN ("nle") },
16355   { STRING_COMMA_LEN ("ord") },
16356   { STRING_COMMA_LEN ("eq_uq") },
16357   { STRING_COMMA_LEN ("nge") },
16358   { STRING_COMMA_LEN ("ngt") },
16359   { STRING_COMMA_LEN ("false") },
16360   { STRING_COMMA_LEN ("neq_oq") },
16361   { STRING_COMMA_LEN ("ge") },
16362   { STRING_COMMA_LEN ("gt") },
16363   { STRING_COMMA_LEN ("true") },
16364   { STRING_COMMA_LEN ("eq_os") },
16365   { STRING_COMMA_LEN ("lt_oq") },
16366   { STRING_COMMA_LEN ("le_oq") },
16367   { STRING_COMMA_LEN ("unord_s") },
16368   { STRING_COMMA_LEN ("neq_us") },
16369   { STRING_COMMA_LEN ("nlt_uq") },
16370   { STRING_COMMA_LEN ("nle_uq") },
16371   { STRING_COMMA_LEN ("ord_s") },
16372   { STRING_COMMA_LEN ("eq_us") },
16373   { STRING_COMMA_LEN ("nge_uq") },
16374   { STRING_COMMA_LEN ("ngt_uq") },
16375   { STRING_COMMA_LEN ("false_os") },
16376   { STRING_COMMA_LEN ("neq_os") },
16377   { STRING_COMMA_LEN ("ge_oq") },
16378   { STRING_COMMA_LEN ("gt_oq") },
16379   { STRING_COMMA_LEN ("true_us") },
16380 };
16381
16382 static void
16383 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16384 {
16385   unsigned int cmp_type;
16386
16387   FETCH_DATA (the_info, codep + 1);
16388   cmp_type = *codep++ & 0xff;
16389   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16390     {
16391       char suffix [3];
16392       char *p = mnemonicendp - 2;
16393       suffix[0] = p[0];
16394       suffix[1] = p[1];
16395       suffix[2] = '\0';
16396       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16397       mnemonicendp += vex_cmp_op[cmp_type].len;
16398     }
16399   else
16400     {
16401       /* We have a reserved extension byte.  Output it directly.  */
16402       scratchbuf[0] = '$';
16403       print_operand_value (scratchbuf + 1, 1, cmp_type);
16404       oappend_maybe_intel (scratchbuf);
16405       scratchbuf[0] = '\0';
16406     }
16407 }
16408
16409 static void
16410 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16411              int sizeflag ATTRIBUTE_UNUSED)
16412 {
16413   unsigned int cmp_type;
16414
16415   if (!vex.evex)
16416     abort ();
16417
16418   FETCH_DATA (the_info, codep + 1);
16419   cmp_type = *codep++ & 0xff;
16420   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16421      If it's the case, print suffix, otherwise - print the immediate.  */
16422   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16423       && cmp_type != 3
16424       && cmp_type != 7)
16425     {
16426       char suffix [3];
16427       char *p = mnemonicendp - 2;
16428
16429       /* vpcmp* can have both one- and two-lettered suffix.  */
16430       if (p[0] == 'p')
16431         {
16432           p++;
16433           suffix[0] = p[0];
16434           suffix[1] = '\0';
16435         }
16436       else
16437         {
16438           suffix[0] = p[0];
16439           suffix[1] = p[1];
16440           suffix[2] = '\0';
16441         }
16442
16443       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16444       mnemonicendp += simd_cmp_op[cmp_type].len;
16445     }
16446   else
16447     {
16448       /* We have a reserved extension byte.  Output it directly.  */
16449       scratchbuf[0] = '$';
16450       print_operand_value (scratchbuf + 1, 1, cmp_type);
16451       oappend_maybe_intel (scratchbuf);
16452       scratchbuf[0] = '\0';
16453     }
16454 }
16455
16456 static const struct op xop_cmp_op[] =
16457 {
16458   { STRING_COMMA_LEN ("lt") },
16459   { STRING_COMMA_LEN ("le") },
16460   { STRING_COMMA_LEN ("gt") },
16461   { STRING_COMMA_LEN ("ge") },
16462   { STRING_COMMA_LEN ("eq") },
16463   { STRING_COMMA_LEN ("neq") },
16464   { STRING_COMMA_LEN ("false") },
16465   { STRING_COMMA_LEN ("true") }
16466 };
16467
16468 static void
16469 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16470              int sizeflag ATTRIBUTE_UNUSED)
16471 {
16472   unsigned int cmp_type;
16473
16474   FETCH_DATA (the_info, codep + 1);
16475   cmp_type = *codep++ & 0xff;
16476   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16477     {
16478       char suffix[3];
16479       char *p = mnemonicendp - 2;
16480
16481       /* vpcom* can have both one- and two-lettered suffix.  */
16482       if (p[0] == 'm')
16483         {
16484           p++;
16485           suffix[0] = p[0];
16486           suffix[1] = '\0';
16487         }
16488       else
16489         {
16490           suffix[0] = p[0];
16491           suffix[1] = p[1];
16492           suffix[2] = '\0';
16493         }
16494
16495       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16496       mnemonicendp += xop_cmp_op[cmp_type].len;
16497     }
16498   else
16499     {
16500       /* We have a reserved extension byte.  Output it directly.  */
16501       scratchbuf[0] = '$';
16502       print_operand_value (scratchbuf + 1, 1, cmp_type);
16503       oappend_maybe_intel (scratchbuf);
16504       scratchbuf[0] = '\0';
16505     }
16506 }
16507
16508 static const struct op pclmul_op[] =
16509 {
16510   { STRING_COMMA_LEN ("lql") },
16511   { STRING_COMMA_LEN ("hql") },
16512   { STRING_COMMA_LEN ("lqh") },
16513   { STRING_COMMA_LEN ("hqh") }
16514 };
16515
16516 static void
16517 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16518               int sizeflag ATTRIBUTE_UNUSED)
16519 {
16520   unsigned int pclmul_type;
16521
16522   FETCH_DATA (the_info, codep + 1);
16523   pclmul_type = *codep++ & 0xff;
16524   switch (pclmul_type)
16525     {
16526     case 0x10:
16527       pclmul_type = 2;
16528       break;
16529     case 0x11:
16530       pclmul_type = 3;
16531       break;
16532     default:
16533       break;
16534     }
16535   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16536     {
16537       char suffix [4];
16538       char *p = mnemonicendp - 3;
16539       suffix[0] = p[0];
16540       suffix[1] = p[1];
16541       suffix[2] = p[2];
16542       suffix[3] = '\0';
16543       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16544       mnemonicendp += pclmul_op[pclmul_type].len;
16545     }
16546   else
16547     {
16548       /* We have a reserved extension byte.  Output it directly.  */
16549       scratchbuf[0] = '$';
16550       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16551       oappend_maybe_intel (scratchbuf);
16552       scratchbuf[0] = '\0';
16553     }
16554 }
16555
16556 static void
16557 MOVBE_Fixup (int bytemode, int sizeflag)
16558 {
16559   /* Add proper suffix to "movbe".  */
16560   char *p = mnemonicendp;
16561
16562   switch (bytemode)
16563     {
16564     case v_mode:
16565       if (intel_syntax)
16566         goto skip;
16567
16568       USED_REX (REX_W);
16569       if (sizeflag & SUFFIX_ALWAYS)
16570         {
16571           if (rex & REX_W)
16572             *p++ = 'q';
16573           else
16574             {
16575               if (sizeflag & DFLAG)
16576                 *p++ = 'l';
16577               else
16578                 *p++ = 'w';
16579               used_prefixes |= (prefixes & PREFIX_DATA);
16580             }
16581         }
16582       break;
16583     default:
16584       oappend (INTERNAL_DISASSEMBLER_ERROR);
16585       break;
16586     }
16587   mnemonicendp = p;
16588   *p = '\0';
16589
16590 skip:
16591   OP_M (bytemode, sizeflag);
16592 }
16593
16594 static void
16595 MOVSXD_Fixup (int bytemode, int sizeflag)
16596 {
16597   /* Add proper suffix to "movsxd".  */
16598   char *p = mnemonicendp;
16599
16600   switch (bytemode)
16601     {
16602     case movsxd_mode:
16603       if (intel_syntax)
16604         {
16605           *p++ = 'x';
16606           *p++ = 'd';
16607           goto skip;
16608         }
16609
16610       USED_REX (REX_W);
16611       if (rex & REX_W)
16612         {
16613           *p++ = 'l';
16614           *p++ = 'q';
16615         }
16616       else
16617         {
16618           *p++ = 'x';
16619           *p++ = 'd';
16620         }
16621       break;
16622     default:
16623       oappend (INTERNAL_DISASSEMBLER_ERROR);
16624       break;
16625     }
16626
16627 skip:
16628   mnemonicendp = p;
16629   *p = '\0';
16630   OP_E (bytemode, sizeflag);
16631 }
16632
16633 static void
16634 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16635 {
16636   int reg;
16637   const char **names;
16638
16639   /* Skip mod/rm byte.  */
16640   MODRM_CHECK;
16641   codep++;
16642
16643   if (rex & REX_W)
16644     names = names64;
16645   else
16646     names = names32;
16647
16648   reg = modrm.rm;
16649   USED_REX (REX_B);
16650   if (rex & REX_B)
16651     reg += 8;
16652
16653   oappend (names[reg]);
16654 }
16655
16656 static void
16657 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16658 {
16659   const char **names;
16660   unsigned int reg = vex.register_specifier;
16661   vex.register_specifier = 0;
16662
16663   if (rex & REX_W)
16664     names = names64;
16665   else
16666     names = names32;
16667
16668   if (address_mode != mode_64bit)
16669     reg &= 7;
16670   oappend (names[reg]);
16671 }
16672
16673 static void
16674 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16675 {
16676   if (!vex.evex
16677       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16678     abort ();
16679
16680   USED_REX (REX_R);
16681   if ((rex & REX_R) != 0 || !vex.r)
16682     {
16683       BadOp ();
16684       return;
16685     }
16686
16687   oappend (names_mask [modrm.reg]);
16688 }
16689
16690 static void
16691 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16692 {
16693   if (!vex.evex
16694       || (bytemode != evex_rounding_mode
16695           && bytemode != evex_rounding_64_mode
16696           && bytemode != evex_sae_mode))
16697     abort ();
16698   if (modrm.mod == 3 && vex.b)
16699     switch (bytemode)
16700       {
16701       case evex_rounding_64_mode:
16702         if (address_mode != mode_64bit)
16703           {
16704             oappend ("(bad)");
16705             break;
16706           }
16707         /* Fall through.  */
16708       case evex_rounding_mode:
16709         oappend (names_rounding[vex.ll]);
16710         break;
16711       case evex_sae_mode:
16712         oappend ("{sae}");
16713         break;
16714       default:
16715         break;
16716       }
16717 }