1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte
*max_fetched
;
134 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
137 OPCODES_SIGJMP_BUF bailout
;
147 enum address_mode address_mode
;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored
;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes
;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
202 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
203 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
205 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
206 status
= (*info
->read_memory_func
) (start
,
208 addr
- priv
->max_fetched
,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv
->max_fetched
== priv
->the_buffer
)
219 (*info
->memory_error_func
) (status
, start
, info
);
220 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
223 priv
->max_fetched
= addr
;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mx { OP_M, x_mode }
276 #define Mxmm { OP_M, xmm_mode }
277 #define Gb { OP_G, b_mode }
278 #define Gbnd { OP_G, bnd_mode }
279 #define Gv { OP_G, v_mode }
280 #define Gd { OP_G, d_mode }
281 #define Gdq { OP_G, dq_mode }
282 #define Gm { OP_G, m_mode }
283 #define Gw { OP_G, w_mode }
284 #define Rd { OP_R, d_mode }
285 #define Rdq { OP_R, dq_mode }
286 #define Rm { OP_R, m_mode }
287 #define Ib { OP_I, b_mode }
288 #define sIb { OP_sI, b_mode } /* sign extened byte */
289 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
290 #define Iv { OP_I, v_mode }
291 #define sIv { OP_sI, v_mode }
292 #define Iq { OP_I, q_mode }
293 #define Iv64 { OP_I64, v_mode }
294 #define Iw { OP_I, w_mode }
295 #define I1 { OP_I, const_1_mode }
296 #define Jb { OP_J, b_mode }
297 #define Jv { OP_J, v_mode }
298 #define Cm { OP_C, m_mode }
299 #define Dm { OP_D, m_mode }
300 #define Td { OP_T, d_mode }
301 #define Skip_MODRM { OP_Skip_MODRM, 0 }
303 #define RMeAX { OP_REG, eAX_reg }
304 #define RMeBX { OP_REG, eBX_reg }
305 #define RMeCX { OP_REG, eCX_reg }
306 #define RMeDX { OP_REG, eDX_reg }
307 #define RMeSP { OP_REG, eSP_reg }
308 #define RMeBP { OP_REG, eBP_reg }
309 #define RMeSI { OP_REG, eSI_reg }
310 #define RMeDI { OP_REG, eDI_reg }
311 #define RMrAX { OP_REG, rAX_reg }
312 #define RMrBX { OP_REG, rBX_reg }
313 #define RMrCX { OP_REG, rCX_reg }
314 #define RMrDX { OP_REG, rDX_reg }
315 #define RMrSP { OP_REG, rSP_reg }
316 #define RMrBP { OP_REG, rBP_reg }
317 #define RMrSI { OP_REG, rSI_reg }
318 #define RMrDI { OP_REG, rDI_reg }
319 #define RMAL { OP_REG, al_reg }
320 #define RMCL { OP_REG, cl_reg }
321 #define RMDL { OP_REG, dl_reg }
322 #define RMBL { OP_REG, bl_reg }
323 #define RMAH { OP_REG, ah_reg }
324 #define RMCH { OP_REG, ch_reg }
325 #define RMDH { OP_REG, dh_reg }
326 #define RMBH { OP_REG, bh_reg }
327 #define RMAX { OP_REG, ax_reg }
328 #define RMDX { OP_REG, dx_reg }
330 #define eAX { OP_IMREG, eAX_reg }
331 #define eBX { OP_IMREG, eBX_reg }
332 #define eCX { OP_IMREG, eCX_reg }
333 #define eDX { OP_IMREG, eDX_reg }
334 #define eSP { OP_IMREG, eSP_reg }
335 #define eBP { OP_IMREG, eBP_reg }
336 #define eSI { OP_IMREG, eSI_reg }
337 #define eDI { OP_IMREG, eDI_reg }
338 #define AL { OP_IMREG, al_reg }
339 #define CL { OP_IMREG, cl_reg }
340 #define DL { OP_IMREG, dl_reg }
341 #define BL { OP_IMREG, bl_reg }
342 #define AH { OP_IMREG, ah_reg }
343 #define CH { OP_IMREG, ch_reg }
344 #define DH { OP_IMREG, dh_reg }
345 #define BH { OP_IMREG, bh_reg }
346 #define AX { OP_IMREG, ax_reg }
347 #define DX { OP_IMREG, dx_reg }
348 #define zAX { OP_IMREG, z_mode_ax_reg }
349 #define indirDX { OP_IMREG, indir_dx_reg }
351 #define Sw { OP_SEG, w_mode }
352 #define Sv { OP_SEG, v_mode }
353 #define Ap { OP_DIR, 0 }
354 #define Ob { OP_OFF64, b_mode }
355 #define Ov { OP_OFF64, v_mode }
356 #define Xb { OP_DSreg, eSI_reg }
357 #define Xv { OP_DSreg, eSI_reg }
358 #define Xz { OP_DSreg, eSI_reg }
359 #define Yb { OP_ESreg, eDI_reg }
360 #define Yv { OP_ESreg, eDI_reg }
361 #define DSBX { OP_DSreg, eBX_reg }
363 #define es { OP_REG, es_reg }
364 #define ss { OP_REG, ss_reg }
365 #define cs { OP_REG, cs_reg }
366 #define ds { OP_REG, ds_reg }
367 #define fs { OP_REG, fs_reg }
368 #define gs { OP_REG, gs_reg }
370 #define MX { OP_MMX, 0 }
371 #define XM { OP_XMM, 0 }
372 #define XMScalar { OP_XMM, scalar_mode }
373 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
374 #define XMM { OP_XMM, xmm_mode }
375 #define XMxmmq { OP_XMM, xmmq_mode }
376 #define EM { OP_EM, v_mode }
377 #define EMS { OP_EM, v_swap_mode }
378 #define EMd { OP_EM, d_mode }
379 #define EMx { OP_EM, x_mode }
380 #define EXbScalar { OP_EX, b_scalar_mode }
381 #define EXw { OP_EX, w_mode }
382 #define EXwScalar { OP_EX, w_scalar_mode }
383 #define EXd { OP_EX, d_mode }
384 #define EXdScalar { OP_EX, d_scalar_mode }
385 #define EXdS { OP_EX, d_swap_mode }
386 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
387 #define EXq { OP_EX, q_mode }
388 #define EXqScalar { OP_EX, q_scalar_mode }
389 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
390 #define EXqS { OP_EX, q_swap_mode }
391 #define EXx { OP_EX, x_mode }
392 #define EXxS { OP_EX, x_swap_mode }
393 #define EXxmm { OP_EX, xmm_mode }
394 #define EXymm { OP_EX, ymm_mode }
395 #define EXxmmq { OP_EX, xmmq_mode }
396 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
397 #define EXxmm_mb { OP_EX, xmm_mb_mode }
398 #define EXxmm_mw { OP_EX, xmm_mw_mode }
399 #define EXxmm_md { OP_EX, xmm_md_mode }
400 #define EXxmm_mq { OP_EX, xmm_mq_mode }
401 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
402 #define EXxmmdw { OP_EX, xmmdw_mode }
403 #define EXxmmqd { OP_EX, xmmqd_mode }
404 #define EXymmq { OP_EX, ymmq_mode }
405 #define EXVexWdq { OP_EX, vex_w_dq_mode }
406 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
407 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
408 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
409 #define MS { OP_MS, v_mode }
410 #define XS { OP_XS, v_mode }
411 #define EMCq { OP_EMC, q_mode }
412 #define MXC { OP_MXC, 0 }
413 #define OPSUF { OP_3DNowSuffix, 0 }
414 #define CMP { CMP_Fixup, 0 }
415 #define XMM0 { XMM_Fixup, 0 }
416 #define FXSAVE { FXSAVE_Fixup, 0 }
417 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
418 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
420 #define Vex { OP_VEX, vex_mode }
421 #define VexScalar { OP_VEX, vex_scalar_mode }
422 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
423 #define Vex128 { OP_VEX, vex128_mode }
424 #define Vex256 { OP_VEX, vex256_mode }
425 #define VexGdq { OP_VEX, dq_mode }
426 #define EXdVex { OP_EX_Vex, d_mode }
427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVex { OP_EX_Vex, q_mode }
430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVex { OP_XMM_Vex, 0 }
437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
438 #define XMVexW { OP_XMM_VexW, 0 }
439 #define XMVexI4 { OP_REG_VexI4, x_mode }
440 #define PCLMUL { PCLMUL_Fixup, 0 }
441 #define VZERO { VZERO_Fixup, 0 }
442 #define VCMP { VCMP_Fixup, 0 }
443 #define VPCMP { VPCMP_Fixup, 0 }
444 #define VPCOM { VPCOM_Fixup, 0 }
446 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
447 #define EXxEVexS { OP_Rounding, evex_sae_mode }
449 #define XMask { OP_Mask, mask_mode }
450 #define MaskG { OP_G, mask_mode }
451 #define MaskE { OP_E, mask_mode }
452 #define MaskBDE { OP_E, mask_bd_mode }
453 #define MaskR { OP_R, mask_mode }
454 #define MaskVex { OP_VEX, mask_mode }
456 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
457 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
458 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
459 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
461 /* Used handle "rep" prefix for string instructions. */
462 #define Xbr { REP_Fixup, eSI_reg }
463 #define Xvr { REP_Fixup, eSI_reg }
464 #define Ybr { REP_Fixup, eDI_reg }
465 #define Yvr { REP_Fixup, eDI_reg }
466 #define Yzr { REP_Fixup, eDI_reg }
467 #define indirDXr { REP_Fixup, indir_dx_reg }
468 #define ALr { REP_Fixup, al_reg }
469 #define eAXr { REP_Fixup, eAX_reg }
471 /* Used handle HLE prefix for lockable instructions. */
472 #define Ebh1 { HLE_Fixup1, b_mode }
473 #define Evh1 { HLE_Fixup1, v_mode }
474 #define Ebh2 { HLE_Fixup2, b_mode }
475 #define Evh2 { HLE_Fixup2, v_mode }
476 #define Ebh3 { HLE_Fixup3, b_mode }
477 #define Evh3 { HLE_Fixup3, v_mode }
479 #define BND { BND_Fixup, 0 }
480 #define NOTRACK { NOTRACK_Fixup, 0 }
482 #define cond_jump_flag { NULL, cond_jump_mode }
483 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
485 /* bits in sizeflag */
486 #define SUFFIX_ALWAYS 4
494 /* byte operand with operand swapped */
496 /* byte operand, sign extend like 'T' suffix */
498 /* operand size depends on prefixes */
500 /* operand size depends on prefixes with operand swapped */
504 /* double word operand */
506 /* double word operand with operand swapped */
508 /* quad word operand */
510 /* quad word operand with operand swapped */
512 /* ten-byte operand */
514 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
515 broadcast enabled. */
517 /* Similar to x_mode, but with different EVEX mem shifts. */
519 /* Similar to x_mode, but with disabled broadcast. */
521 /* Similar to x_mode, but with operands swapped and disabled broadcast
524 /* 16-byte XMM operand */
526 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
527 memory operand (depending on vector length). Broadcast isn't
530 /* Same as xmmq_mode, but broadcast is allowed. */
531 evex_half_bcst_xmmq_mode
,
532 /* XMM register or byte memory operand */
534 /* XMM register or word memory operand */
536 /* XMM register or double word memory operand */
538 /* XMM register or quad word memory operand */
540 /* XMM register or double/quad word memory operand, depending on
543 /* 16-byte XMM, word, double word or quad word operand. */
545 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
547 /* 32-byte YMM operand */
549 /* quad word, ymmword or zmmword memory operand. */
551 /* 32-byte YMM or 16-byte word operand */
553 /* d_mode in 32bit, q_mode in 64bit mode. */
555 /* pair of v_mode operands */
560 /* operand size depends on REX prefixes. */
562 /* registers like dq_mode, memory like w_mode. */
566 /* bounds operand with operand swapped */
568 /* 4- or 6-byte pointer operand */
571 /* v_mode for indirect branch opcodes. */
573 /* v_mode for stack-related opcodes. */
575 /* non-quad operand size depends on prefixes */
577 /* 16-byte operand */
579 /* registers like dq_mode, memory like b_mode. */
581 /* registers like d_mode, memory like b_mode. */
583 /* registers like d_mode, memory like w_mode. */
585 /* registers like dq_mode, memory like d_mode. */
587 /* normal vex mode */
589 /* 128bit vex mode */
591 /* 256bit vex mode */
593 /* operand size depends on the VEX.W bit. */
596 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
597 vex_vsib_d_w_dq_mode
,
598 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
600 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
601 vex_vsib_q_w_dq_mode
,
602 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
605 /* scalar, ignore vector length. */
607 /* like b_mode, ignore vector length. */
609 /* like w_mode, ignore vector length. */
611 /* like d_mode, ignore vector length. */
613 /* like d_swap_mode, ignore vector length. */
615 /* like q_mode, ignore vector length. */
617 /* like q_swap_mode, ignore vector length. */
619 /* like vex_mode, ignore vector length. */
621 /* like vex_w_dq_mode, ignore vector length. */
622 vex_scalar_w_dq_mode
,
624 /* Static rounding. */
626 /* Supress all exceptions. */
629 /* Mask register operand. */
631 /* Mask register operand. */
698 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
700 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
701 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
702 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
703 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
704 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
705 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
706 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
707 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
708 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
709 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
710 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
711 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
712 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
713 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
714 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
836 MOD_VEX_0F12_PREFIX_0
,
838 MOD_VEX_0F16_PREFIX_0
,
841 MOD_VEX_W_0_0F41_P_0_LEN_1
,
842 MOD_VEX_W_1_0F41_P_0_LEN_1
,
843 MOD_VEX_W_0_0F41_P_2_LEN_1
,
844 MOD_VEX_W_1_0F41_P_2_LEN_1
,
845 MOD_VEX_W_0_0F42_P_0_LEN_1
,
846 MOD_VEX_W_1_0F42_P_0_LEN_1
,
847 MOD_VEX_W_0_0F42_P_2_LEN_1
,
848 MOD_VEX_W_1_0F42_P_2_LEN_1
,
849 MOD_VEX_W_0_0F44_P_0_LEN_1
,
850 MOD_VEX_W_1_0F44_P_0_LEN_1
,
851 MOD_VEX_W_0_0F44_P_2_LEN_1
,
852 MOD_VEX_W_1_0F44_P_2_LEN_1
,
853 MOD_VEX_W_0_0F45_P_0_LEN_1
,
854 MOD_VEX_W_1_0F45_P_0_LEN_1
,
855 MOD_VEX_W_0_0F45_P_2_LEN_1
,
856 MOD_VEX_W_1_0F45_P_2_LEN_1
,
857 MOD_VEX_W_0_0F46_P_0_LEN_1
,
858 MOD_VEX_W_1_0F46_P_0_LEN_1
,
859 MOD_VEX_W_0_0F46_P_2_LEN_1
,
860 MOD_VEX_W_1_0F46_P_2_LEN_1
,
861 MOD_VEX_W_0_0F47_P_0_LEN_1
,
862 MOD_VEX_W_1_0F47_P_0_LEN_1
,
863 MOD_VEX_W_0_0F47_P_2_LEN_1
,
864 MOD_VEX_W_1_0F47_P_2_LEN_1
,
865 MOD_VEX_W_0_0F4A_P_0_LEN_1
,
866 MOD_VEX_W_1_0F4A_P_0_LEN_1
,
867 MOD_VEX_W_0_0F4A_P_2_LEN_1
,
868 MOD_VEX_W_1_0F4A_P_2_LEN_1
,
869 MOD_VEX_W_0_0F4B_P_0_LEN_1
,
870 MOD_VEX_W_1_0F4B_P_0_LEN_1
,
871 MOD_VEX_W_0_0F4B_P_2_LEN_1
,
883 MOD_VEX_W_0_0F91_P_0_LEN_0
,
884 MOD_VEX_W_1_0F91_P_0_LEN_0
,
885 MOD_VEX_W_0_0F91_P_2_LEN_0
,
886 MOD_VEX_W_1_0F91_P_2_LEN_0
,
887 MOD_VEX_W_0_0F92_P_0_LEN_0
,
888 MOD_VEX_W_0_0F92_P_2_LEN_0
,
889 MOD_VEX_W_0_0F92_P_3_LEN_0
,
890 MOD_VEX_W_1_0F92_P_3_LEN_0
,
891 MOD_VEX_W_0_0F93_P_0_LEN_0
,
892 MOD_VEX_W_0_0F93_P_2_LEN_0
,
893 MOD_VEX_W_0_0F93_P_3_LEN_0
,
894 MOD_VEX_W_1_0F93_P_3_LEN_0
,
895 MOD_VEX_W_0_0F98_P_0_LEN_0
,
896 MOD_VEX_W_1_0F98_P_0_LEN_0
,
897 MOD_VEX_W_0_0F98_P_2_LEN_0
,
898 MOD_VEX_W_1_0F98_P_2_LEN_0
,
899 MOD_VEX_W_0_0F99_P_0_LEN_0
,
900 MOD_VEX_W_1_0F99_P_0_LEN_0
,
901 MOD_VEX_W_0_0F99_P_2_LEN_0
,
902 MOD_VEX_W_1_0F99_P_2_LEN_0
,
905 MOD_VEX_0FD7_PREFIX_2
,
906 MOD_VEX_0FE7_PREFIX_2
,
907 MOD_VEX_0FF0_PREFIX_3
,
908 MOD_VEX_0F381A_PREFIX_2
,
909 MOD_VEX_0F382A_PREFIX_2
,
910 MOD_VEX_0F382C_PREFIX_2
,
911 MOD_VEX_0F382D_PREFIX_2
,
912 MOD_VEX_0F382E_PREFIX_2
,
913 MOD_VEX_0F382F_PREFIX_2
,
914 MOD_VEX_0F385A_PREFIX_2
,
915 MOD_VEX_0F388C_PREFIX_2
,
916 MOD_VEX_0F388E_PREFIX_2
,
917 MOD_VEX_W_0_0F3A30_P_2_LEN_0
,
918 MOD_VEX_W_1_0F3A30_P_2_LEN_0
,
919 MOD_VEX_W_0_0F3A31_P_2_LEN_0
,
920 MOD_VEX_W_1_0F3A31_P_2_LEN_0
,
921 MOD_VEX_W_0_0F3A32_P_2_LEN_0
,
922 MOD_VEX_W_1_0F3A32_P_2_LEN_0
,
923 MOD_VEX_W_0_0F3A33_P_2_LEN_0
,
924 MOD_VEX_W_1_0F3A33_P_2_LEN_0
,
926 MOD_EVEX_0F10_PREFIX_1
,
927 MOD_EVEX_0F10_PREFIX_3
,
928 MOD_EVEX_0F11_PREFIX_1
,
929 MOD_EVEX_0F11_PREFIX_3
,
930 MOD_EVEX_0F12_PREFIX_0
,
931 MOD_EVEX_0F16_PREFIX_0
,
932 MOD_EVEX_0F38C6_REG_1
,
933 MOD_EVEX_0F38C6_REG_2
,
934 MOD_EVEX_0F38C6_REG_5
,
935 MOD_EVEX_0F38C6_REG_6
,
936 MOD_EVEX_0F38C7_REG_1
,
937 MOD_EVEX_0F38C7_REG_2
,
938 MOD_EVEX_0F38C7_REG_5
,
939 MOD_EVEX_0F38C7_REG_6
960 PREFIX_MOD_0_0F01_REG_5
,
961 PREFIX_MOD_3_0F01_REG_5_RM_0
,
962 PREFIX_MOD_3_0F01_REG_5_RM_2
,
1007 PREFIX_MOD_0_0FAE_REG_4
,
1008 PREFIX_MOD_3_0FAE_REG_4
,
1009 PREFIX_MOD_0_0FAE_REG_5
,
1010 PREFIX_MOD_3_0FAE_REG_5
,
1018 PREFIX_MOD_0_0FC7_REG_6
,
1019 PREFIX_MOD_3_0FC7_REG_6
,
1020 PREFIX_MOD_3_0FC7_REG_7
,
1148 PREFIX_VEX_0F71_REG_2
,
1149 PREFIX_VEX_0F71_REG_4
,
1150 PREFIX_VEX_0F71_REG_6
,
1151 PREFIX_VEX_0F72_REG_2
,
1152 PREFIX_VEX_0F72_REG_4
,
1153 PREFIX_VEX_0F72_REG_6
,
1154 PREFIX_VEX_0F73_REG_2
,
1155 PREFIX_VEX_0F73_REG_3
,
1156 PREFIX_VEX_0F73_REG_6
,
1157 PREFIX_VEX_0F73_REG_7
,
1330 PREFIX_VEX_0F38F3_REG_1
,
1331 PREFIX_VEX_0F38F3_REG_2
,
1332 PREFIX_VEX_0F38F3_REG_3
,
1451 PREFIX_EVEX_0F71_REG_2
,
1452 PREFIX_EVEX_0F71_REG_4
,
1453 PREFIX_EVEX_0F71_REG_6
,
1454 PREFIX_EVEX_0F72_REG_0
,
1455 PREFIX_EVEX_0F72_REG_1
,
1456 PREFIX_EVEX_0F72_REG_2
,
1457 PREFIX_EVEX_0F72_REG_4
,
1458 PREFIX_EVEX_0F72_REG_6
,
1459 PREFIX_EVEX_0F73_REG_2
,
1460 PREFIX_EVEX_0F73_REG_3
,
1461 PREFIX_EVEX_0F73_REG_6
,
1462 PREFIX_EVEX_0F73_REG_7
,
1658 PREFIX_EVEX_0F38C6_REG_1
,
1659 PREFIX_EVEX_0F38C6_REG_2
,
1660 PREFIX_EVEX_0F38C6_REG_5
,
1661 PREFIX_EVEX_0F38C6_REG_6
,
1662 PREFIX_EVEX_0F38C7_REG_1
,
1663 PREFIX_EVEX_0F38C7_REG_2
,
1664 PREFIX_EVEX_0F38C7_REG_5
,
1665 PREFIX_EVEX_0F38C7_REG_6
,
1767 THREE_BYTE_0F38
= 0,
1794 VEX_LEN_0F10_P_1
= 0,
1798 VEX_LEN_0F12_P_0_M_0
,
1799 VEX_LEN_0F12_P_0_M_1
,
1802 VEX_LEN_0F16_P_0_M_0
,
1803 VEX_LEN_0F16_P_0_M_1
,
1867 VEX_LEN_0FAE_R_2_M_0
,
1868 VEX_LEN_0FAE_R_3_M_0
,
1877 VEX_LEN_0F381A_P_2_M_0
,
1880 VEX_LEN_0F385A_P_2_M_0
,
1883 VEX_LEN_0F38F3_R_1_P_0
,
1884 VEX_LEN_0F38F3_R_2_P_0
,
1885 VEX_LEN_0F38F3_R_3_P_0
,
1930 VEX_LEN_0FXOP_08_CC
,
1931 VEX_LEN_0FXOP_08_CD
,
1932 VEX_LEN_0FXOP_08_CE
,
1933 VEX_LEN_0FXOP_08_CF
,
1934 VEX_LEN_0FXOP_08_EC
,
1935 VEX_LEN_0FXOP_08_ED
,
1936 VEX_LEN_0FXOP_08_EE
,
1937 VEX_LEN_0FXOP_08_EF
,
1938 VEX_LEN_0FXOP_09_80
,
1972 VEX_W_0F41_P_0_LEN_1
,
1973 VEX_W_0F41_P_2_LEN_1
,
1974 VEX_W_0F42_P_0_LEN_1
,
1975 VEX_W_0F42_P_2_LEN_1
,
1976 VEX_W_0F44_P_0_LEN_0
,
1977 VEX_W_0F44_P_2_LEN_0
,
1978 VEX_W_0F45_P_0_LEN_1
,
1979 VEX_W_0F45_P_2_LEN_1
,
1980 VEX_W_0F46_P_0_LEN_1
,
1981 VEX_W_0F46_P_2_LEN_1
,
1982 VEX_W_0F47_P_0_LEN_1
,
1983 VEX_W_0F47_P_2_LEN_1
,
1984 VEX_W_0F4A_P_0_LEN_1
,
1985 VEX_W_0F4A_P_2_LEN_1
,
1986 VEX_W_0F4B_P_0_LEN_1
,
1987 VEX_W_0F4B_P_2_LEN_1
,
2067 VEX_W_0F90_P_0_LEN_0
,
2068 VEX_W_0F90_P_2_LEN_0
,
2069 VEX_W_0F91_P_0_LEN_0
,
2070 VEX_W_0F91_P_2_LEN_0
,
2071 VEX_W_0F92_P_0_LEN_0
,
2072 VEX_W_0F92_P_2_LEN_0
,
2073 VEX_W_0F92_P_3_LEN_0
,
2074 VEX_W_0F93_P_0_LEN_0
,
2075 VEX_W_0F93_P_2_LEN_0
,
2076 VEX_W_0F93_P_3_LEN_0
,
2077 VEX_W_0F98_P_0_LEN_0
,
2078 VEX_W_0F98_P_2_LEN_0
,
2079 VEX_W_0F99_P_0_LEN_0
,
2080 VEX_W_0F99_P_2_LEN_0
,
2159 VEX_W_0F381A_P_2_M_0
,
2171 VEX_W_0F382A_P_2_M_0
,
2173 VEX_W_0F382C_P_2_M_0
,
2174 VEX_W_0F382D_P_2_M_0
,
2175 VEX_W_0F382E_P_2_M_0
,
2176 VEX_W_0F382F_P_2_M_0
,
2198 VEX_W_0F385A_P_2_M_0
,
2223 VEX_W_0F3A30_P_2_LEN_0
,
2224 VEX_W_0F3A31_P_2_LEN_0
,
2225 VEX_W_0F3A32_P_2_LEN_0
,
2226 VEX_W_0F3A33_P_2_LEN_0
,
2245 EVEX_W_0F10_P_1_M_0
,
2246 EVEX_W_0F10_P_1_M_1
,
2248 EVEX_W_0F10_P_3_M_0
,
2249 EVEX_W_0F10_P_3_M_1
,
2251 EVEX_W_0F11_P_1_M_0
,
2252 EVEX_W_0F11_P_1_M_1
,
2254 EVEX_W_0F11_P_3_M_0
,
2255 EVEX_W_0F11_P_3_M_1
,
2256 EVEX_W_0F12_P_0_M_0
,
2257 EVEX_W_0F12_P_0_M_1
,
2267 EVEX_W_0F16_P_0_M_0
,
2268 EVEX_W_0F16_P_0_M_1
,
2339 EVEX_W_0F72_R_2_P_2
,
2340 EVEX_W_0F72_R_6_P_2
,
2341 EVEX_W_0F73_R_2_P_2
,
2342 EVEX_W_0F73_R_6_P_2
,
2450 EVEX_W_0F38C7_R_1_P_2
,
2451 EVEX_W_0F38C7_R_2_P_2
,
2452 EVEX_W_0F38C7_R_5_P_2
,
2453 EVEX_W_0F38C7_R_6_P_2
,
2494 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2503 unsigned int prefix_requirement
;
2506 /* Upper case letters in the instruction names here are macros.
2507 'A' => print 'b' if no register operands or suffix_always is true
2508 'B' => print 'b' if suffix_always is true
2509 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2511 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2512 suffix_always is true
2513 'E' => print 'e' if 32-bit form of jcxz
2514 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2515 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2516 'H' => print ",pt" or ",pn" branch hint
2517 'I' => honor following macro letter even in Intel mode (implemented only
2518 for some of the macro letters)
2520 'K' => print 'd' or 'q' if rex prefix is present.
2521 'L' => print 'l' if suffix_always is true
2522 'M' => print 'r' if intel_mnemonic is false.
2523 'N' => print 'n' if instruction has no wait "prefix"
2524 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2525 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2526 or suffix_always is true. print 'q' if rex prefix is present.
2527 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2529 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2530 'S' => print 'w', 'l' or 'q' if suffix_always is true
2531 'T' => print 'q' in 64bit mode if instruction has no operand size
2532 prefix and behave as 'P' otherwise
2533 'U' => print 'q' in 64bit mode if instruction has no operand size
2534 prefix and behave as 'Q' otherwise
2535 'V' => print 'q' in 64bit mode if instruction has no operand size
2536 prefix and behave as 'S' otherwise
2537 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2538 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2539 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2540 suffix_always is true.
2541 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2542 '!' => change condition from true to false or from false to true.
2543 '%' => add 1 upper case letter to the macro.
2544 '^' => print 'w' or 'l' depending on operand size prefix or
2545 suffix_always is true (lcall/ljmp).
2546 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2547 on operand size prefix.
2548 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2549 has no operand size prefix for AMD64 ISA, behave as 'P'
2552 2 upper case letter macros:
2553 "XY" => print 'x' or 'y' if suffix_always is true or no register
2554 operands and no broadcast.
2555 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2556 register operands and no broadcast.
2557 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2558 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2559 or suffix_always is true
2560 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2561 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2562 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2563 "LW" => print 'd', 'q' depending on the VEX.W bit
2564 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2565 an operand size prefix, or suffix_always is true. print
2566 'q' if rex prefix is present.
2568 Many of the above letters print nothing in Intel mode. See "putop"
2571 Braces '{' and '}', and vertical bars '|', indicate alternative
2572 mnemonic strings for AT&T and Intel. */
2574 static const struct dis386 dis386
[] = {
2576 { "addB", { Ebh1
, Gb
}, 0 },
2577 { "addS", { Evh1
, Gv
}, 0 },
2578 { "addB", { Gb
, EbS
}, 0 },
2579 { "addS", { Gv
, EvS
}, 0 },
2580 { "addB", { AL
, Ib
}, 0 },
2581 { "addS", { eAX
, Iv
}, 0 },
2582 { X86_64_TABLE (X86_64_06
) },
2583 { X86_64_TABLE (X86_64_07
) },
2585 { "orB", { Ebh1
, Gb
}, 0 },
2586 { "orS", { Evh1
, Gv
}, 0 },
2587 { "orB", { Gb
, EbS
}, 0 },
2588 { "orS", { Gv
, EvS
}, 0 },
2589 { "orB", { AL
, Ib
}, 0 },
2590 { "orS", { eAX
, Iv
}, 0 },
2591 { X86_64_TABLE (X86_64_0D
) },
2592 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2594 { "adcB", { Ebh1
, Gb
}, 0 },
2595 { "adcS", { Evh1
, Gv
}, 0 },
2596 { "adcB", { Gb
, EbS
}, 0 },
2597 { "adcS", { Gv
, EvS
}, 0 },
2598 { "adcB", { AL
, Ib
}, 0 },
2599 { "adcS", { eAX
, Iv
}, 0 },
2600 { X86_64_TABLE (X86_64_16
) },
2601 { X86_64_TABLE (X86_64_17
) },
2603 { "sbbB", { Ebh1
, Gb
}, 0 },
2604 { "sbbS", { Evh1
, Gv
}, 0 },
2605 { "sbbB", { Gb
, EbS
}, 0 },
2606 { "sbbS", { Gv
, EvS
}, 0 },
2607 { "sbbB", { AL
, Ib
}, 0 },
2608 { "sbbS", { eAX
, Iv
}, 0 },
2609 { X86_64_TABLE (X86_64_1E
) },
2610 { X86_64_TABLE (X86_64_1F
) },
2612 { "andB", { Ebh1
, Gb
}, 0 },
2613 { "andS", { Evh1
, Gv
}, 0 },
2614 { "andB", { Gb
, EbS
}, 0 },
2615 { "andS", { Gv
, EvS
}, 0 },
2616 { "andB", { AL
, Ib
}, 0 },
2617 { "andS", { eAX
, Iv
}, 0 },
2618 { Bad_Opcode
}, /* SEG ES prefix */
2619 { X86_64_TABLE (X86_64_27
) },
2621 { "subB", { Ebh1
, Gb
}, 0 },
2622 { "subS", { Evh1
, Gv
}, 0 },
2623 { "subB", { Gb
, EbS
}, 0 },
2624 { "subS", { Gv
, EvS
}, 0 },
2625 { "subB", { AL
, Ib
}, 0 },
2626 { "subS", { eAX
, Iv
}, 0 },
2627 { Bad_Opcode
}, /* SEG CS prefix */
2628 { X86_64_TABLE (X86_64_2F
) },
2630 { "xorB", { Ebh1
, Gb
}, 0 },
2631 { "xorS", { Evh1
, Gv
}, 0 },
2632 { "xorB", { Gb
, EbS
}, 0 },
2633 { "xorS", { Gv
, EvS
}, 0 },
2634 { "xorB", { AL
, Ib
}, 0 },
2635 { "xorS", { eAX
, Iv
}, 0 },
2636 { Bad_Opcode
}, /* SEG SS prefix */
2637 { X86_64_TABLE (X86_64_37
) },
2639 { "cmpB", { Eb
, Gb
}, 0 },
2640 { "cmpS", { Ev
, Gv
}, 0 },
2641 { "cmpB", { Gb
, EbS
}, 0 },
2642 { "cmpS", { Gv
, EvS
}, 0 },
2643 { "cmpB", { AL
, Ib
}, 0 },
2644 { "cmpS", { eAX
, Iv
}, 0 },
2645 { Bad_Opcode
}, /* SEG DS prefix */
2646 { X86_64_TABLE (X86_64_3F
) },
2648 { "inc{S|}", { RMeAX
}, 0 },
2649 { "inc{S|}", { RMeCX
}, 0 },
2650 { "inc{S|}", { RMeDX
}, 0 },
2651 { "inc{S|}", { RMeBX
}, 0 },
2652 { "inc{S|}", { RMeSP
}, 0 },
2653 { "inc{S|}", { RMeBP
}, 0 },
2654 { "inc{S|}", { RMeSI
}, 0 },
2655 { "inc{S|}", { RMeDI
}, 0 },
2657 { "dec{S|}", { RMeAX
}, 0 },
2658 { "dec{S|}", { RMeCX
}, 0 },
2659 { "dec{S|}", { RMeDX
}, 0 },
2660 { "dec{S|}", { RMeBX
}, 0 },
2661 { "dec{S|}", { RMeSP
}, 0 },
2662 { "dec{S|}", { RMeBP
}, 0 },
2663 { "dec{S|}", { RMeSI
}, 0 },
2664 { "dec{S|}", { RMeDI
}, 0 },
2666 { "pushV", { RMrAX
}, 0 },
2667 { "pushV", { RMrCX
}, 0 },
2668 { "pushV", { RMrDX
}, 0 },
2669 { "pushV", { RMrBX
}, 0 },
2670 { "pushV", { RMrSP
}, 0 },
2671 { "pushV", { RMrBP
}, 0 },
2672 { "pushV", { RMrSI
}, 0 },
2673 { "pushV", { RMrDI
}, 0 },
2675 { "popV", { RMrAX
}, 0 },
2676 { "popV", { RMrCX
}, 0 },
2677 { "popV", { RMrDX
}, 0 },
2678 { "popV", { RMrBX
}, 0 },
2679 { "popV", { RMrSP
}, 0 },
2680 { "popV", { RMrBP
}, 0 },
2681 { "popV", { RMrSI
}, 0 },
2682 { "popV", { RMrDI
}, 0 },
2684 { X86_64_TABLE (X86_64_60
) },
2685 { X86_64_TABLE (X86_64_61
) },
2686 { X86_64_TABLE (X86_64_62
) },
2687 { X86_64_TABLE (X86_64_63
) },
2688 { Bad_Opcode
}, /* seg fs */
2689 { Bad_Opcode
}, /* seg gs */
2690 { Bad_Opcode
}, /* op size prefix */
2691 { Bad_Opcode
}, /* adr size prefix */
2693 { "pushT", { sIv
}, 0 },
2694 { "imulS", { Gv
, Ev
, Iv
}, 0 },
2695 { "pushT", { sIbT
}, 0 },
2696 { "imulS", { Gv
, Ev
, sIb
}, 0 },
2697 { "ins{b|}", { Ybr
, indirDX
}, 0 },
2698 { X86_64_TABLE (X86_64_6D
) },
2699 { "outs{b|}", { indirDXr
, Xb
}, 0 },
2700 { X86_64_TABLE (X86_64_6F
) },
2702 { "joH", { Jb
, BND
, cond_jump_flag
}, 0 },
2703 { "jnoH", { Jb
, BND
, cond_jump_flag
}, 0 },
2704 { "jbH", { Jb
, BND
, cond_jump_flag
}, 0 },
2705 { "jaeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2706 { "jeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2707 { "jneH", { Jb
, BND
, cond_jump_flag
}, 0 },
2708 { "jbeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2709 { "jaH", { Jb
, BND
, cond_jump_flag
}, 0 },
2711 { "jsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2712 { "jnsH", { Jb
, BND
, cond_jump_flag
}, 0 },
2713 { "jpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2714 { "jnpH", { Jb
, BND
, cond_jump_flag
}, 0 },
2715 { "jlH", { Jb
, BND
, cond_jump_flag
}, 0 },
2716 { "jgeH", { Jb
, BND
, cond_jump_flag
}, 0 },
2717 { "jleH", { Jb
, BND
, cond_jump_flag
}, 0 },
2718 { "jgH", { Jb
, BND
, cond_jump_flag
}, 0 },
2720 { REG_TABLE (REG_80
) },
2721 { REG_TABLE (REG_81
) },
2722 { X86_64_TABLE (X86_64_82
) },
2723 { REG_TABLE (REG_83
) },
2724 { "testB", { Eb
, Gb
}, 0 },
2725 { "testS", { Ev
, Gv
}, 0 },
2726 { "xchgB", { Ebh2
, Gb
}, 0 },
2727 { "xchgS", { Evh2
, Gv
}, 0 },
2729 { "movB", { Ebh3
, Gb
}, 0 },
2730 { "movS", { Evh3
, Gv
}, 0 },
2731 { "movB", { Gb
, EbS
}, 0 },
2732 { "movS", { Gv
, EvS
}, 0 },
2733 { "movD", { Sv
, Sw
}, 0 },
2734 { MOD_TABLE (MOD_8D
) },
2735 { "movD", { Sw
, Sv
}, 0 },
2736 { REG_TABLE (REG_8F
) },
2738 { PREFIX_TABLE (PREFIX_90
) },
2739 { "xchgS", { RMeCX
, eAX
}, 0 },
2740 { "xchgS", { RMeDX
, eAX
}, 0 },
2741 { "xchgS", { RMeBX
, eAX
}, 0 },
2742 { "xchgS", { RMeSP
, eAX
}, 0 },
2743 { "xchgS", { RMeBP
, eAX
}, 0 },
2744 { "xchgS", { RMeSI
, eAX
}, 0 },
2745 { "xchgS", { RMeDI
, eAX
}, 0 },
2747 { "cW{t|}R", { XX
}, 0 },
2748 { "cR{t|}O", { XX
}, 0 },
2749 { X86_64_TABLE (X86_64_9A
) },
2750 { Bad_Opcode
}, /* fwait */
2751 { "pushfT", { XX
}, 0 },
2752 { "popfT", { XX
}, 0 },
2753 { "sahf", { XX
}, 0 },
2754 { "lahf", { XX
}, 0 },
2756 { "mov%LB", { AL
, Ob
}, 0 },
2757 { "mov%LS", { eAX
, Ov
}, 0 },
2758 { "mov%LB", { Ob
, AL
}, 0 },
2759 { "mov%LS", { Ov
, eAX
}, 0 },
2760 { "movs{b|}", { Ybr
, Xb
}, 0 },
2761 { "movs{R|}", { Yvr
, Xv
}, 0 },
2762 { "cmps{b|}", { Xb
, Yb
}, 0 },
2763 { "cmps{R|}", { Xv
, Yv
}, 0 },
2765 { "testB", { AL
, Ib
}, 0 },
2766 { "testS", { eAX
, Iv
}, 0 },
2767 { "stosB", { Ybr
, AL
}, 0 },
2768 { "stosS", { Yvr
, eAX
}, 0 },
2769 { "lodsB", { ALr
, Xb
}, 0 },
2770 { "lodsS", { eAXr
, Xv
}, 0 },
2771 { "scasB", { AL
, Yb
}, 0 },
2772 { "scasS", { eAX
, Yv
}, 0 },
2774 { "movB", { RMAL
, Ib
}, 0 },
2775 { "movB", { RMCL
, Ib
}, 0 },
2776 { "movB", { RMDL
, Ib
}, 0 },
2777 { "movB", { RMBL
, Ib
}, 0 },
2778 { "movB", { RMAH
, Ib
}, 0 },
2779 { "movB", { RMCH
, Ib
}, 0 },
2780 { "movB", { RMDH
, Ib
}, 0 },
2781 { "movB", { RMBH
, Ib
}, 0 },
2783 { "mov%LV", { RMeAX
, Iv64
}, 0 },
2784 { "mov%LV", { RMeCX
, Iv64
}, 0 },
2785 { "mov%LV", { RMeDX
, Iv64
}, 0 },
2786 { "mov%LV", { RMeBX
, Iv64
}, 0 },
2787 { "mov%LV", { RMeSP
, Iv64
}, 0 },
2788 { "mov%LV", { RMeBP
, Iv64
}, 0 },
2789 { "mov%LV", { RMeSI
, Iv64
}, 0 },
2790 { "mov%LV", { RMeDI
, Iv64
}, 0 },
2792 { REG_TABLE (REG_C0
) },
2793 { REG_TABLE (REG_C1
) },
2794 { "retT", { Iw
, BND
}, 0 },
2795 { "retT", { BND
}, 0 },
2796 { X86_64_TABLE (X86_64_C4
) },
2797 { X86_64_TABLE (X86_64_C5
) },
2798 { REG_TABLE (REG_C6
) },
2799 { REG_TABLE (REG_C7
) },
2801 { "enterT", { Iw
, Ib
}, 0 },
2802 { "leaveT", { XX
}, 0 },
2803 { "Jret{|f}P", { Iw
}, 0 },
2804 { "Jret{|f}P", { XX
}, 0 },
2805 { "int3", { XX
}, 0 },
2806 { "int", { Ib
}, 0 },
2807 { X86_64_TABLE (X86_64_CE
) },
2808 { "iret%LP", { XX
}, 0 },
2810 { REG_TABLE (REG_D0
) },
2811 { REG_TABLE (REG_D1
) },
2812 { REG_TABLE (REG_D2
) },
2813 { REG_TABLE (REG_D3
) },
2814 { X86_64_TABLE (X86_64_D4
) },
2815 { X86_64_TABLE (X86_64_D5
) },
2817 { "xlat", { DSBX
}, 0 },
2828 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2829 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2830 { "loopFH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2831 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
}, 0 },
2832 { "inB", { AL
, Ib
}, 0 },
2833 { "inG", { zAX
, Ib
}, 0 },
2834 { "outB", { Ib
, AL
}, 0 },
2835 { "outG", { Ib
, zAX
}, 0 },
2837 { X86_64_TABLE (X86_64_E8
) },
2838 { X86_64_TABLE (X86_64_E9
) },
2839 { X86_64_TABLE (X86_64_EA
) },
2840 { "jmp", { Jb
, BND
}, 0 },
2841 { "inB", { AL
, indirDX
}, 0 },
2842 { "inG", { zAX
, indirDX
}, 0 },
2843 { "outB", { indirDX
, AL
}, 0 },
2844 { "outG", { indirDX
, zAX
}, 0 },
2846 { Bad_Opcode
}, /* lock prefix */
2847 { "icebp", { XX
}, 0 },
2848 { Bad_Opcode
}, /* repne */
2849 { Bad_Opcode
}, /* repz */
2850 { "hlt", { XX
}, 0 },
2851 { "cmc", { XX
}, 0 },
2852 { REG_TABLE (REG_F6
) },
2853 { REG_TABLE (REG_F7
) },
2855 { "clc", { XX
}, 0 },
2856 { "stc", { XX
}, 0 },
2857 { "cli", { XX
}, 0 },
2858 { "sti", { XX
}, 0 },
2859 { "cld", { XX
}, 0 },
2860 { "std", { XX
}, 0 },
2861 { REG_TABLE (REG_FE
) },
2862 { REG_TABLE (REG_FF
) },
2865 static const struct dis386 dis386_twobyte
[] = {
2867 { REG_TABLE (REG_0F00
) },
2868 { REG_TABLE (REG_0F01
) },
2869 { "larS", { Gv
, Ew
}, 0 },
2870 { "lslS", { Gv
, Ew
}, 0 },
2872 { "syscall", { XX
}, 0 },
2873 { "clts", { XX
}, 0 },
2874 { "sysret%LP", { XX
}, 0 },
2876 { "invd", { XX
}, 0 },
2877 { PREFIX_TABLE (PREFIX_0F09
) },
2879 { "ud2", { XX
}, 0 },
2881 { REG_TABLE (REG_0F0D
) },
2882 { "femms", { XX
}, 0 },
2883 { "", { MX
, EM
, OPSUF
}, 0 }, /* See OP_3DNowSuffix. */
2885 { PREFIX_TABLE (PREFIX_0F10
) },
2886 { PREFIX_TABLE (PREFIX_0F11
) },
2887 { PREFIX_TABLE (PREFIX_0F12
) },
2888 { MOD_TABLE (MOD_0F13
) },
2889 { "unpcklpX", { XM
, EXx
}, PREFIX_OPCODE
},
2890 { "unpckhpX", { XM
, EXx
}, PREFIX_OPCODE
},
2891 { PREFIX_TABLE (PREFIX_0F16
) },
2892 { MOD_TABLE (MOD_0F17
) },
2894 { REG_TABLE (REG_0F18
) },
2895 { "nopQ", { Ev
}, 0 },
2896 { PREFIX_TABLE (PREFIX_0F1A
) },
2897 { PREFIX_TABLE (PREFIX_0F1B
) },
2898 { "nopQ", { Ev
}, 0 },
2899 { "nopQ", { Ev
}, 0 },
2900 { PREFIX_TABLE (PREFIX_0F1E
) },
2901 { "nopQ", { Ev
}, 0 },
2903 { "movZ", { Rm
, Cm
}, 0 },
2904 { "movZ", { Rm
, Dm
}, 0 },
2905 { "movZ", { Cm
, Rm
}, 0 },
2906 { "movZ", { Dm
, Rm
}, 0 },
2907 { MOD_TABLE (MOD_0F24
) },
2909 { MOD_TABLE (MOD_0F26
) },
2912 { "movapX", { XM
, EXx
}, PREFIX_OPCODE
},
2913 { "movapX", { EXxS
, XM
}, PREFIX_OPCODE
},
2914 { PREFIX_TABLE (PREFIX_0F2A
) },
2915 { PREFIX_TABLE (PREFIX_0F2B
) },
2916 { PREFIX_TABLE (PREFIX_0F2C
) },
2917 { PREFIX_TABLE (PREFIX_0F2D
) },
2918 { PREFIX_TABLE (PREFIX_0F2E
) },
2919 { PREFIX_TABLE (PREFIX_0F2F
) },
2921 { "wrmsr", { XX
}, 0 },
2922 { "rdtsc", { XX
}, 0 },
2923 { "rdmsr", { XX
}, 0 },
2924 { "rdpmc", { XX
}, 0 },
2925 { "sysenter", { XX
}, 0 },
2926 { "sysexit", { XX
}, 0 },
2928 { "getsec", { XX
}, 0 },
2930 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38
, PREFIX_OPCODE
) },
2932 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A
, PREFIX_OPCODE
) },
2939 { "cmovoS", { Gv
, Ev
}, 0 },
2940 { "cmovnoS", { Gv
, Ev
}, 0 },
2941 { "cmovbS", { Gv
, Ev
}, 0 },
2942 { "cmovaeS", { Gv
, Ev
}, 0 },
2943 { "cmoveS", { Gv
, Ev
}, 0 },
2944 { "cmovneS", { Gv
, Ev
}, 0 },
2945 { "cmovbeS", { Gv
, Ev
}, 0 },
2946 { "cmovaS", { Gv
, Ev
}, 0 },
2948 { "cmovsS", { Gv
, Ev
}, 0 },
2949 { "cmovnsS", { Gv
, Ev
}, 0 },
2950 { "cmovpS", { Gv
, Ev
}, 0 },
2951 { "cmovnpS", { Gv
, Ev
}, 0 },
2952 { "cmovlS", { Gv
, Ev
}, 0 },
2953 { "cmovgeS", { Gv
, Ev
}, 0 },
2954 { "cmovleS", { Gv
, Ev
}, 0 },
2955 { "cmovgS", { Gv
, Ev
}, 0 },
2957 { MOD_TABLE (MOD_0F51
) },
2958 { PREFIX_TABLE (PREFIX_0F51
) },
2959 { PREFIX_TABLE (PREFIX_0F52
) },
2960 { PREFIX_TABLE (PREFIX_0F53
) },
2961 { "andpX", { XM
, EXx
}, PREFIX_OPCODE
},
2962 { "andnpX", { XM
, EXx
}, PREFIX_OPCODE
},
2963 { "orpX", { XM
, EXx
}, PREFIX_OPCODE
},
2964 { "xorpX", { XM
, EXx
}, PREFIX_OPCODE
},
2966 { PREFIX_TABLE (PREFIX_0F58
) },
2967 { PREFIX_TABLE (PREFIX_0F59
) },
2968 { PREFIX_TABLE (PREFIX_0F5A
) },
2969 { PREFIX_TABLE (PREFIX_0F5B
) },
2970 { PREFIX_TABLE (PREFIX_0F5C
) },
2971 { PREFIX_TABLE (PREFIX_0F5D
) },
2972 { PREFIX_TABLE (PREFIX_0F5E
) },
2973 { PREFIX_TABLE (PREFIX_0F5F
) },
2975 { PREFIX_TABLE (PREFIX_0F60
) },
2976 { PREFIX_TABLE (PREFIX_0F61
) },
2977 { PREFIX_TABLE (PREFIX_0F62
) },
2978 { "packsswb", { MX
, EM
}, PREFIX_OPCODE
},
2979 { "pcmpgtb", { MX
, EM
}, PREFIX_OPCODE
},
2980 { "pcmpgtw", { MX
, EM
}, PREFIX_OPCODE
},
2981 { "pcmpgtd", { MX
, EM
}, PREFIX_OPCODE
},
2982 { "packuswb", { MX
, EM
}, PREFIX_OPCODE
},
2984 { "punpckhbw", { MX
, EM
}, PREFIX_OPCODE
},
2985 { "punpckhwd", { MX
, EM
}, PREFIX_OPCODE
},
2986 { "punpckhdq", { MX
, EM
}, PREFIX_OPCODE
},
2987 { "packssdw", { MX
, EM
}, PREFIX_OPCODE
},
2988 { PREFIX_TABLE (PREFIX_0F6C
) },
2989 { PREFIX_TABLE (PREFIX_0F6D
) },
2990 { "movK", { MX
, Edq
}, PREFIX_OPCODE
},
2991 { PREFIX_TABLE (PREFIX_0F6F
) },
2993 { PREFIX_TABLE (PREFIX_0F70
) },
2994 { REG_TABLE (REG_0F71
) },
2995 { REG_TABLE (REG_0F72
) },
2996 { REG_TABLE (REG_0F73
) },
2997 { "pcmpeqb", { MX
, EM
}, PREFIX_OPCODE
},
2998 { "pcmpeqw", { MX
, EM
}, PREFIX_OPCODE
},
2999 { "pcmpeqd", { MX
, EM
}, PREFIX_OPCODE
},
3000 { "emms", { XX
}, PREFIX_OPCODE
},
3002 { PREFIX_TABLE (PREFIX_0F78
) },
3003 { PREFIX_TABLE (PREFIX_0F79
) },
3006 { PREFIX_TABLE (PREFIX_0F7C
) },
3007 { PREFIX_TABLE (PREFIX_0F7D
) },
3008 { PREFIX_TABLE (PREFIX_0F7E
) },
3009 { PREFIX_TABLE (PREFIX_0F7F
) },
3011 { "joH", { Jv
, BND
, cond_jump_flag
}, 0 },
3012 { "jnoH", { Jv
, BND
, cond_jump_flag
}, 0 },
3013 { "jbH", { Jv
, BND
, cond_jump_flag
}, 0 },
3014 { "jaeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3015 { "jeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3016 { "jneH", { Jv
, BND
, cond_jump_flag
}, 0 },
3017 { "jbeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3018 { "jaH", { Jv
, BND
, cond_jump_flag
}, 0 },
3020 { "jsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3021 { "jnsH", { Jv
, BND
, cond_jump_flag
}, 0 },
3022 { "jpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3023 { "jnpH", { Jv
, BND
, cond_jump_flag
}, 0 },
3024 { "jlH", { Jv
, BND
, cond_jump_flag
}, 0 },
3025 { "jgeH", { Jv
, BND
, cond_jump_flag
}, 0 },
3026 { "jleH", { Jv
, BND
, cond_jump_flag
}, 0 },
3027 { "jgH", { Jv
, BND
, cond_jump_flag
}, 0 },
3029 { "seto", { Eb
}, 0 },
3030 { "setno", { Eb
}, 0 },
3031 { "setb", { Eb
}, 0 },
3032 { "setae", { Eb
}, 0 },
3033 { "sete", { Eb
}, 0 },
3034 { "setne", { Eb
}, 0 },
3035 { "setbe", { Eb
}, 0 },
3036 { "seta", { Eb
}, 0 },
3038 { "sets", { Eb
}, 0 },
3039 { "setns", { Eb
}, 0 },
3040 { "setp", { Eb
}, 0 },
3041 { "setnp", { Eb
}, 0 },
3042 { "setl", { Eb
}, 0 },
3043 { "setge", { Eb
}, 0 },
3044 { "setle", { Eb
}, 0 },
3045 { "setg", { Eb
}, 0 },
3047 { "pushT", { fs
}, 0 },
3048 { "popT", { fs
}, 0 },
3049 { "cpuid", { XX
}, 0 },
3050 { "btS", { Ev
, Gv
}, 0 },
3051 { "shldS", { Ev
, Gv
, Ib
}, 0 },
3052 { "shldS", { Ev
, Gv
, CL
}, 0 },
3053 { REG_TABLE (REG_0FA6
) },
3054 { REG_TABLE (REG_0FA7
) },
3056 { "pushT", { gs
}, 0 },
3057 { "popT", { gs
}, 0 },
3058 { "rsm", { XX
}, 0 },
3059 { "btsS", { Evh1
, Gv
}, 0 },
3060 { "shrdS", { Ev
, Gv
, Ib
}, 0 },
3061 { "shrdS", { Ev
, Gv
, CL
}, 0 },
3062 { REG_TABLE (REG_0FAE
) },
3063 { "imulS", { Gv
, Ev
}, 0 },
3065 { "cmpxchgB", { Ebh1
, Gb
}, 0 },
3066 { "cmpxchgS", { Evh1
, Gv
}, 0 },
3067 { MOD_TABLE (MOD_0FB2
) },
3068 { "btrS", { Evh1
, Gv
}, 0 },
3069 { MOD_TABLE (MOD_0FB4
) },
3070 { MOD_TABLE (MOD_0FB5
) },
3071 { "movz{bR|x}", { Gv
, Eb
}, 0 },
3072 { "movz{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movzww ! */
3074 { PREFIX_TABLE (PREFIX_0FB8
) },
3075 { "ud1S", { Gv
, Ev
}, 0 },
3076 { REG_TABLE (REG_0FBA
) },
3077 { "btcS", { Evh1
, Gv
}, 0 },
3078 { PREFIX_TABLE (PREFIX_0FBC
) },
3079 { PREFIX_TABLE (PREFIX_0FBD
) },
3080 { "movs{bR|x}", { Gv
, Eb
}, 0 },
3081 { "movs{wR|x}", { Gv
, Ew
}, 0 }, /* yes, there really is movsww ! */
3083 { "xaddB", { Ebh1
, Gb
}, 0 },
3084 { "xaddS", { Evh1
, Gv
}, 0 },
3085 { PREFIX_TABLE (PREFIX_0FC2
) },
3086 { MOD_TABLE (MOD_0FC3
) },
3087 { "pinsrw", { MX
, Edqw
, Ib
}, PREFIX_OPCODE
},
3088 { "pextrw", { Gdq
, MS
, Ib
}, PREFIX_OPCODE
},
3089 { "shufpX", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
3090 { REG_TABLE (REG_0FC7
) },
3092 { "bswap", { RMeAX
}, 0 },
3093 { "bswap", { RMeCX
}, 0 },
3094 { "bswap", { RMeDX
}, 0 },
3095 { "bswap", { RMeBX
}, 0 },
3096 { "bswap", { RMeSP
}, 0 },
3097 { "bswap", { RMeBP
}, 0 },
3098 { "bswap", { RMeSI
}, 0 },
3099 { "bswap", { RMeDI
}, 0 },
3101 { PREFIX_TABLE (PREFIX_0FD0
) },
3102 { "psrlw", { MX
, EM
}, PREFIX_OPCODE
},
3103 { "psrld", { MX
, EM
}, PREFIX_OPCODE
},
3104 { "psrlq", { MX
, EM
}, PREFIX_OPCODE
},
3105 { "paddq", { MX
, EM
}, PREFIX_OPCODE
},
3106 { "pmullw", { MX
, EM
}, PREFIX_OPCODE
},
3107 { PREFIX_TABLE (PREFIX_0FD6
) },
3108 { MOD_TABLE (MOD_0FD7
) },
3110 { "psubusb", { MX
, EM
}, PREFIX_OPCODE
},
3111 { "psubusw", { MX
, EM
}, PREFIX_OPCODE
},
3112 { "pminub", { MX
, EM
}, PREFIX_OPCODE
},
3113 { "pand", { MX
, EM
}, PREFIX_OPCODE
},
3114 { "paddusb", { MX
, EM
}, PREFIX_OPCODE
},
3115 { "paddusw", { MX
, EM
}, PREFIX_OPCODE
},
3116 { "pmaxub", { MX
, EM
}, PREFIX_OPCODE
},
3117 { "pandn", { MX
, EM
}, PREFIX_OPCODE
},
3119 { "pavgb", { MX
, EM
}, PREFIX_OPCODE
},
3120 { "psraw", { MX
, EM
}, PREFIX_OPCODE
},
3121 { "psrad", { MX
, EM
}, PREFIX_OPCODE
},
3122 { "pavgw", { MX
, EM
}, PREFIX_OPCODE
},
3123 { "pmulhuw", { MX
, EM
}, PREFIX_OPCODE
},
3124 { "pmulhw", { MX
, EM
}, PREFIX_OPCODE
},
3125 { PREFIX_TABLE (PREFIX_0FE6
) },
3126 { PREFIX_TABLE (PREFIX_0FE7
) },
3128 { "psubsb", { MX
, EM
}, PREFIX_OPCODE
},
3129 { "psubsw", { MX
, EM
}, PREFIX_OPCODE
},
3130 { "pminsw", { MX
, EM
}, PREFIX_OPCODE
},
3131 { "por", { MX
, EM
}, PREFIX_OPCODE
},
3132 { "paddsb", { MX
, EM
}, PREFIX_OPCODE
},
3133 { "paddsw", { MX
, EM
}, PREFIX_OPCODE
},
3134 { "pmaxsw", { MX
, EM
}, PREFIX_OPCODE
},
3135 { "pxor", { MX
, EM
}, PREFIX_OPCODE
},
3137 { PREFIX_TABLE (PREFIX_0FF0
) },
3138 { "psllw", { MX
, EM
}, PREFIX_OPCODE
},
3139 { "pslld", { MX
, EM
}, PREFIX_OPCODE
},
3140 { "psllq", { MX
, EM
}, PREFIX_OPCODE
},
3141 { "pmuludq", { MX
, EM
}, PREFIX_OPCODE
},
3142 { "pmaddwd", { MX
, EM
}, PREFIX_OPCODE
},
3143 { "psadbw", { MX
, EM
}, PREFIX_OPCODE
},
3144 { PREFIX_TABLE (PREFIX_0FF7
) },
3146 { "psubb", { MX
, EM
}, PREFIX_OPCODE
},
3147 { "psubw", { MX
, EM
}, PREFIX_OPCODE
},
3148 { "psubd", { MX
, EM
}, PREFIX_OPCODE
},
3149 { "psubq", { MX
, EM
}, PREFIX_OPCODE
},
3150 { "paddb", { MX
, EM
}, PREFIX_OPCODE
},
3151 { "paddw", { MX
, EM
}, PREFIX_OPCODE
},
3152 { "paddd", { MX
, EM
}, PREFIX_OPCODE
},
3153 { "ud0S", { Gv
, Ev
}, 0 },
3156 static const unsigned char onebyte_has_modrm
[256] = {
3157 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3158 /* ------------------------------- */
3159 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3160 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3161 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3162 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3163 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3164 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3165 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3166 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3167 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3168 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3169 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3170 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3171 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3172 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3173 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3174 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3175 /* ------------------------------- */
3176 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3179 static const unsigned char twobyte_has_modrm
[256] = {
3180 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3181 /* ------------------------------- */
3182 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3183 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3184 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3185 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3186 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3187 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3188 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3189 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3190 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3191 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3192 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3193 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3194 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3195 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3196 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3197 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3198 /* ------------------------------- */
3199 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3202 static char obuf
[100];
3204 static char *mnemonicendp
;
3205 static char scratchbuf
[100];
3206 static unsigned char *start_codep
;
3207 static unsigned char *insn_codep
;
3208 static unsigned char *codep
;
3209 static unsigned char *end_codep
;
3210 static int last_lock_prefix
;
3211 static int last_repz_prefix
;
3212 static int last_repnz_prefix
;
3213 static int last_data_prefix
;
3214 static int last_addr_prefix
;
3215 static int last_rex_prefix
;
3216 static int last_seg_prefix
;
3217 static int fwait_prefix
;
3218 /* The active segment register prefix. */
3219 static int active_seg_prefix
;
3220 #define MAX_CODE_LENGTH 15
3221 /* We can up to 14 prefixes since the maximum instruction length is
3223 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
3224 static disassemble_info
*the_info
;
3232 static unsigned char need_modrm
;
3242 int register_specifier
;
3249 int mask_register_specifier
;
3255 static unsigned char need_vex
;
3256 static unsigned char need_vex_reg
;
3257 static unsigned char vex_w_done
;
3265 /* If we are accessing mod/rm/reg without need_modrm set, then the
3266 values are stale. Hitting this abort likely indicates that you
3267 need to update onebyte_has_modrm or twobyte_has_modrm. */
3268 #define MODRM_CHECK if (!need_modrm) abort ()
3270 static const char **names64
;
3271 static const char **names32
;
3272 static const char **names16
;
3273 static const char **names8
;
3274 static const char **names8rex
;
3275 static const char **names_seg
;
3276 static const char *index64
;
3277 static const char *index32
;
3278 static const char **index16
;
3279 static const char **names_bnd
;
3281 static const char *intel_names64
[] = {
3282 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3283 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3285 static const char *intel_names32
[] = {
3286 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3287 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3289 static const char *intel_names16
[] = {
3290 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3291 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3293 static const char *intel_names8
[] = {
3294 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3296 static const char *intel_names8rex
[] = {
3297 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3298 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3300 static const char *intel_names_seg
[] = {
3301 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3303 static const char *intel_index64
= "riz";
3304 static const char *intel_index32
= "eiz";
3305 static const char *intel_index16
[] = {
3306 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3309 static const char *att_names64
[] = {
3310 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3311 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3313 static const char *att_names32
[] = {
3314 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3315 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3317 static const char *att_names16
[] = {
3318 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3319 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3321 static const char *att_names8
[] = {
3322 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3324 static const char *att_names8rex
[] = {
3325 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3326 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3328 static const char *att_names_seg
[] = {
3329 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3331 static const char *att_index64
= "%riz";
3332 static const char *att_index32
= "%eiz";
3333 static const char *att_index16
[] = {
3334 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3337 static const char **names_mm
;
3338 static const char *intel_names_mm
[] = {
3339 "mm0", "mm1", "mm2", "mm3",
3340 "mm4", "mm5", "mm6", "mm7"
3342 static const char *att_names_mm
[] = {
3343 "%mm0", "%mm1", "%mm2", "%mm3",
3344 "%mm4", "%mm5", "%mm6", "%mm7"
3347 static const char *intel_names_bnd
[] = {
3348 "bnd0", "bnd1", "bnd2", "bnd3"
3351 static const char *att_names_bnd
[] = {
3352 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3355 static const char **names_xmm
;
3356 static const char *intel_names_xmm
[] = {
3357 "xmm0", "xmm1", "xmm2", "xmm3",
3358 "xmm4", "xmm5", "xmm6", "xmm7",
3359 "xmm8", "xmm9", "xmm10", "xmm11",
3360 "xmm12", "xmm13", "xmm14", "xmm15",
3361 "xmm16", "xmm17", "xmm18", "xmm19",
3362 "xmm20", "xmm21", "xmm22", "xmm23",
3363 "xmm24", "xmm25", "xmm26", "xmm27",
3364 "xmm28", "xmm29", "xmm30", "xmm31"
3366 static const char *att_names_xmm
[] = {
3367 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3368 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3369 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3370 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3371 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3372 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3373 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3374 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3377 static const char **names_ymm
;
3378 static const char *intel_names_ymm
[] = {
3379 "ymm0", "ymm1", "ymm2", "ymm3",
3380 "ymm4", "ymm5", "ymm6", "ymm7",
3381 "ymm8", "ymm9", "ymm10", "ymm11",
3382 "ymm12", "ymm13", "ymm14", "ymm15",
3383 "ymm16", "ymm17", "ymm18", "ymm19",
3384 "ymm20", "ymm21", "ymm22", "ymm23",
3385 "ymm24", "ymm25", "ymm26", "ymm27",
3386 "ymm28", "ymm29", "ymm30", "ymm31"
3388 static const char *att_names_ymm
[] = {
3389 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3390 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3391 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3392 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3393 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3394 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3395 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3396 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3399 static const char **names_zmm
;
3400 static const char *intel_names_zmm
[] = {
3401 "zmm0", "zmm1", "zmm2", "zmm3",
3402 "zmm4", "zmm5", "zmm6", "zmm7",
3403 "zmm8", "zmm9", "zmm10", "zmm11",
3404 "zmm12", "zmm13", "zmm14", "zmm15",
3405 "zmm16", "zmm17", "zmm18", "zmm19",
3406 "zmm20", "zmm21", "zmm22", "zmm23",
3407 "zmm24", "zmm25", "zmm26", "zmm27",
3408 "zmm28", "zmm29", "zmm30", "zmm31"
3410 static const char *att_names_zmm
[] = {
3411 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3412 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3413 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3414 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3415 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3416 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3417 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3418 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3421 static const char **names_mask
;
3422 static const char *intel_names_mask
[] = {
3423 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3425 static const char *att_names_mask
[] = {
3426 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3429 static const char *names_rounding
[] =
3437 static const struct dis386 reg_table
[][8] = {
3440 { "addA", { Ebh1
, Ib
}, 0 },
3441 { "orA", { Ebh1
, Ib
}, 0 },
3442 { "adcA", { Ebh1
, Ib
}, 0 },
3443 { "sbbA", { Ebh1
, Ib
}, 0 },
3444 { "andA", { Ebh1
, Ib
}, 0 },
3445 { "subA", { Ebh1
, Ib
}, 0 },
3446 { "xorA", { Ebh1
, Ib
}, 0 },
3447 { "cmpA", { Eb
, Ib
}, 0 },
3451 { "addQ", { Evh1
, Iv
}, 0 },
3452 { "orQ", { Evh1
, Iv
}, 0 },
3453 { "adcQ", { Evh1
, Iv
}, 0 },
3454 { "sbbQ", { Evh1
, Iv
}, 0 },
3455 { "andQ", { Evh1
, Iv
}, 0 },
3456 { "subQ", { Evh1
, Iv
}, 0 },
3457 { "xorQ", { Evh1
, Iv
}, 0 },
3458 { "cmpQ", { Ev
, Iv
}, 0 },
3462 { "addQ", { Evh1
, sIb
}, 0 },
3463 { "orQ", { Evh1
, sIb
}, 0 },
3464 { "adcQ", { Evh1
, sIb
}, 0 },
3465 { "sbbQ", { Evh1
, sIb
}, 0 },
3466 { "andQ", { Evh1
, sIb
}, 0 },
3467 { "subQ", { Evh1
, sIb
}, 0 },
3468 { "xorQ", { Evh1
, sIb
}, 0 },
3469 { "cmpQ", { Ev
, sIb
}, 0 },
3473 { "popU", { stackEv
}, 0 },
3474 { XOP_8F_TABLE (XOP_09
) },
3478 { XOP_8F_TABLE (XOP_09
) },
3482 { "rolA", { Eb
, Ib
}, 0 },
3483 { "rorA", { Eb
, Ib
}, 0 },
3484 { "rclA", { Eb
, Ib
}, 0 },
3485 { "rcrA", { Eb
, Ib
}, 0 },
3486 { "shlA", { Eb
, Ib
}, 0 },
3487 { "shrA", { Eb
, Ib
}, 0 },
3488 { "shlA", { Eb
, Ib
}, 0 },
3489 { "sarA", { Eb
, Ib
}, 0 },
3493 { "rolQ", { Ev
, Ib
}, 0 },
3494 { "rorQ", { Ev
, Ib
}, 0 },
3495 { "rclQ", { Ev
, Ib
}, 0 },
3496 { "rcrQ", { Ev
, Ib
}, 0 },
3497 { "shlQ", { Ev
, Ib
}, 0 },
3498 { "shrQ", { Ev
, Ib
}, 0 },
3499 { "shlQ", { Ev
, Ib
}, 0 },
3500 { "sarQ", { Ev
, Ib
}, 0 },
3504 { "movA", { Ebh3
, Ib
}, 0 },
3511 { MOD_TABLE (MOD_C6_REG_7
) },
3515 { "movQ", { Evh3
, Iv
}, 0 },
3522 { MOD_TABLE (MOD_C7_REG_7
) },
3526 { "rolA", { Eb
, I1
}, 0 },
3527 { "rorA", { Eb
, I1
}, 0 },
3528 { "rclA", { Eb
, I1
}, 0 },
3529 { "rcrA", { Eb
, I1
}, 0 },
3530 { "shlA", { Eb
, I1
}, 0 },
3531 { "shrA", { Eb
, I1
}, 0 },
3532 { "shlA", { Eb
, I1
}, 0 },
3533 { "sarA", { Eb
, I1
}, 0 },
3537 { "rolQ", { Ev
, I1
}, 0 },
3538 { "rorQ", { Ev
, I1
}, 0 },
3539 { "rclQ", { Ev
, I1
}, 0 },
3540 { "rcrQ", { Ev
, I1
}, 0 },
3541 { "shlQ", { Ev
, I1
}, 0 },
3542 { "shrQ", { Ev
, I1
}, 0 },
3543 { "shlQ", { Ev
, I1
}, 0 },
3544 { "sarQ", { Ev
, I1
}, 0 },
3548 { "rolA", { Eb
, CL
}, 0 },
3549 { "rorA", { Eb
, CL
}, 0 },
3550 { "rclA", { Eb
, CL
}, 0 },
3551 { "rcrA", { Eb
, CL
}, 0 },
3552 { "shlA", { Eb
, CL
}, 0 },
3553 { "shrA", { Eb
, CL
}, 0 },
3554 { "shlA", { Eb
, CL
}, 0 },
3555 { "sarA", { Eb
, CL
}, 0 },
3559 { "rolQ", { Ev
, CL
}, 0 },
3560 { "rorQ", { Ev
, CL
}, 0 },
3561 { "rclQ", { Ev
, CL
}, 0 },
3562 { "rcrQ", { Ev
, CL
}, 0 },
3563 { "shlQ", { Ev
, CL
}, 0 },
3564 { "shrQ", { Ev
, CL
}, 0 },
3565 { "shlQ", { Ev
, CL
}, 0 },
3566 { "sarQ", { Ev
, CL
}, 0 },
3570 { "testA", { Eb
, Ib
}, 0 },
3571 { "testA", { Eb
, Ib
}, 0 },
3572 { "notA", { Ebh1
}, 0 },
3573 { "negA", { Ebh1
}, 0 },
3574 { "mulA", { Eb
}, 0 }, /* Don't print the implicit %al register, */
3575 { "imulA", { Eb
}, 0 }, /* to distinguish these opcodes from other */
3576 { "divA", { Eb
}, 0 }, /* mul/imul opcodes. Do the same for div */
3577 { "idivA", { Eb
}, 0 }, /* and idiv for consistency. */
3581 { "testQ", { Ev
, Iv
}, 0 },
3582 { "testQ", { Ev
, Iv
}, 0 },
3583 { "notQ", { Evh1
}, 0 },
3584 { "negQ", { Evh1
}, 0 },
3585 { "mulQ", { Ev
}, 0 }, /* Don't print the implicit register. */
3586 { "imulQ", { Ev
}, 0 },
3587 { "divQ", { Ev
}, 0 },
3588 { "idivQ", { Ev
}, 0 },
3592 { "incA", { Ebh1
}, 0 },
3593 { "decA", { Ebh1
}, 0 },
3597 { "incQ", { Evh1
}, 0 },
3598 { "decQ", { Evh1
}, 0 },
3599 { "call{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3600 { MOD_TABLE (MOD_FF_REG_3
) },
3601 { "jmp{&|}", { NOTRACK
, indirEv
, BND
}, 0 },
3602 { MOD_TABLE (MOD_FF_REG_5
) },
3603 { "pushU", { stackEv
}, 0 },
3608 { "sldtD", { Sv
}, 0 },
3609 { "strD", { Sv
}, 0 },
3610 { "lldt", { Ew
}, 0 },
3611 { "ltr", { Ew
}, 0 },
3612 { "verr", { Ew
}, 0 },
3613 { "verw", { Ew
}, 0 },
3619 { MOD_TABLE (MOD_0F01_REG_0
) },
3620 { MOD_TABLE (MOD_0F01_REG_1
) },
3621 { MOD_TABLE (MOD_0F01_REG_2
) },
3622 { MOD_TABLE (MOD_0F01_REG_3
) },
3623 { "smswD", { Sv
}, 0 },
3624 { MOD_TABLE (MOD_0F01_REG_5
) },
3625 { "lmsw", { Ew
}, 0 },
3626 { MOD_TABLE (MOD_0F01_REG_7
) },
3630 { "prefetch", { Mb
}, 0 },
3631 { "prefetchw", { Mb
}, 0 },
3632 { "prefetchwt1", { Mb
}, 0 },
3633 { "prefetch", { Mb
}, 0 },
3634 { "prefetch", { Mb
}, 0 },
3635 { "prefetch", { Mb
}, 0 },
3636 { "prefetch", { Mb
}, 0 },
3637 { "prefetch", { Mb
}, 0 },
3641 { MOD_TABLE (MOD_0F18_REG_0
) },
3642 { MOD_TABLE (MOD_0F18_REG_1
) },
3643 { MOD_TABLE (MOD_0F18_REG_2
) },
3644 { MOD_TABLE (MOD_0F18_REG_3
) },
3645 { MOD_TABLE (MOD_0F18_REG_4
) },
3646 { MOD_TABLE (MOD_0F18_REG_5
) },
3647 { MOD_TABLE (MOD_0F18_REG_6
) },
3648 { MOD_TABLE (MOD_0F18_REG_7
) },
3650 /* REG_0F1E_MOD_3 */
3652 { "nopQ", { Ev
}, 0 },
3653 { "rdsspK", { Rdq
}, PREFIX_OPCODE
},
3654 { "nopQ", { Ev
}, 0 },
3655 { "nopQ", { Ev
}, 0 },
3656 { "nopQ", { Ev
}, 0 },
3657 { "nopQ", { Ev
}, 0 },
3658 { "nopQ", { Ev
}, 0 },
3659 { RM_TABLE (RM_0F1E_MOD_3_REG_7
) },
3665 { MOD_TABLE (MOD_0F71_REG_2
) },
3667 { MOD_TABLE (MOD_0F71_REG_4
) },
3669 { MOD_TABLE (MOD_0F71_REG_6
) },
3675 { MOD_TABLE (MOD_0F72_REG_2
) },
3677 { MOD_TABLE (MOD_0F72_REG_4
) },
3679 { MOD_TABLE (MOD_0F72_REG_6
) },
3685 { MOD_TABLE (MOD_0F73_REG_2
) },
3686 { MOD_TABLE (MOD_0F73_REG_3
) },
3689 { MOD_TABLE (MOD_0F73_REG_6
) },
3690 { MOD_TABLE (MOD_0F73_REG_7
) },
3694 { "montmul", { { OP_0f07
, 0 } }, 0 },
3695 { "xsha1", { { OP_0f07
, 0 } }, 0 },
3696 { "xsha256", { { OP_0f07
, 0 } }, 0 },
3700 { "xstore-rng", { { OP_0f07
, 0 } }, 0 },
3701 { "xcrypt-ecb", { { OP_0f07
, 0 } }, 0 },
3702 { "xcrypt-cbc", { { OP_0f07
, 0 } }, 0 },
3703 { "xcrypt-ctr", { { OP_0f07
, 0 } }, 0 },
3704 { "xcrypt-cfb", { { OP_0f07
, 0 } }, 0 },
3705 { "xcrypt-ofb", { { OP_0f07
, 0 } }, 0 },
3709 { MOD_TABLE (MOD_0FAE_REG_0
) },
3710 { MOD_TABLE (MOD_0FAE_REG_1
) },
3711 { MOD_TABLE (MOD_0FAE_REG_2
) },
3712 { MOD_TABLE (MOD_0FAE_REG_3
) },
3713 { MOD_TABLE (MOD_0FAE_REG_4
) },
3714 { MOD_TABLE (MOD_0FAE_REG_5
) },
3715 { MOD_TABLE (MOD_0FAE_REG_6
) },
3716 { MOD_TABLE (MOD_0FAE_REG_7
) },
3724 { "btQ", { Ev
, Ib
}, 0 },
3725 { "btsQ", { Evh1
, Ib
}, 0 },
3726 { "btrQ", { Evh1
, Ib
}, 0 },
3727 { "btcQ", { Evh1
, Ib
}, 0 },
3732 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} }, 0 },
3734 { MOD_TABLE (MOD_0FC7_REG_3
) },
3735 { MOD_TABLE (MOD_0FC7_REG_4
) },
3736 { MOD_TABLE (MOD_0FC7_REG_5
) },
3737 { MOD_TABLE (MOD_0FC7_REG_6
) },
3738 { MOD_TABLE (MOD_0FC7_REG_7
) },
3744 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3746 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3748 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3754 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3756 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3758 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3764 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3765 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3768 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3769 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3775 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3776 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3778 /* REG_VEX_0F38F3 */
3781 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3782 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3783 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3787 { "llwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3788 { "slwpcb", { { OP_LWPCB_E
, 0 } }, 0 },
3792 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3793 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
}, 0 },
3795 /* REG_XOP_TBM_01 */
3798 { "blcfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3799 { "blsfill", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3800 { "blcs", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3801 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3802 { "blcic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3803 { "blsic", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3804 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3806 /* REG_XOP_TBM_02 */
3809 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3814 { "blci", { { OP_LWP_E
, 0 }, Ev
}, 0 },
3816 #define NEED_REG_TABLE
3817 #include "i386-dis-evex.h"
3818 #undef NEED_REG_TABLE
3821 static const struct dis386 prefix_table
[][4] = {
3824 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3825 { "pause", { XX
}, 0 },
3826 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} }, 0 },
3827 { NULL
, { { NULL
, 0 } }, PREFIX_IGNORED
}
3830 /* PREFIX_MOD_0_0F01_REG_5 */
3833 { "rstorssp", { Mq
}, PREFIX_OPCODE
},
3836 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3839 { "setssbsy", { Skip_MODRM
}, PREFIX_OPCODE
},
3842 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3845 { "saveprevssp", { Skip_MODRM
}, PREFIX_OPCODE
},
3850 { "wbinvd", { XX
}, 0 },
3851 { "wbnoinvd", { XX
}, 0 },
3856 { "movups", { XM
, EXx
}, PREFIX_OPCODE
},
3857 { "movss", { XM
, EXd
}, PREFIX_OPCODE
},
3858 { "movupd", { XM
, EXx
}, PREFIX_OPCODE
},
3859 { "movsd", { XM
, EXq
}, PREFIX_OPCODE
},
3864 { "movups", { EXxS
, XM
}, PREFIX_OPCODE
},
3865 { "movss", { EXdS
, XM
}, PREFIX_OPCODE
},
3866 { "movupd", { EXxS
, XM
}, PREFIX_OPCODE
},
3867 { "movsd", { EXqS
, XM
}, PREFIX_OPCODE
},
3872 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3873 { "movsldup", { XM
, EXx
}, PREFIX_OPCODE
},
3874 { "movlpd", { XM
, EXq
}, PREFIX_OPCODE
},
3875 { "movddup", { XM
, EXq
}, PREFIX_OPCODE
},
3880 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3881 { "movshdup", { XM
, EXx
}, PREFIX_OPCODE
},
3882 { "movhpd", { XM
, EXq
}, PREFIX_OPCODE
},
3887 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3888 { "bndcl", { Gbnd
, Ev_bnd
}, 0 },
3889 { "bndmov", { Gbnd
, Ebnd
}, 0 },
3890 { "bndcu", { Gbnd
, Ev_bnd
}, 0 },
3895 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3896 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3897 { "bndmov", { EbndS
, Gbnd
}, 0 },
3898 { "bndcn", { Gbnd
, Ev_bnd
}, 0 },
3903 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3904 { MOD_TABLE (MOD_0F1E_PREFIX_1
) },
3905 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3906 { "nopQ", { Ev
}, PREFIX_OPCODE
},
3911 { "cvtpi2ps", { XM
, EMCq
}, PREFIX_OPCODE
},
3912 { "cvtsi2ss%LQ", { XM
, Ev
}, PREFIX_OPCODE
},
3913 { "cvtpi2pd", { XM
, EMCq
}, PREFIX_OPCODE
},
3914 { "cvtsi2sd%LQ", { XM
, Ev
}, 0 },
3919 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3920 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3921 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3922 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3927 { "cvttps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3928 { "cvttss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3929 { "cvttpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3930 { "cvttsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3935 { "cvtps2pi", { MXC
, EXq
}, PREFIX_OPCODE
},
3936 { "cvtss2siY", { Gv
, EXd
}, PREFIX_OPCODE
},
3937 { "cvtpd2pi", { MXC
, EXx
}, PREFIX_OPCODE
},
3938 { "cvtsd2siY", { Gv
, EXq
}, PREFIX_OPCODE
},
3943 { "ucomiss",{ XM
, EXd
}, 0 },
3945 { "ucomisd",{ XM
, EXq
}, 0 },
3950 { "comiss", { XM
, EXd
}, 0 },
3952 { "comisd", { XM
, EXq
}, 0 },
3957 { "sqrtps", { XM
, EXx
}, PREFIX_OPCODE
},
3958 { "sqrtss", { XM
, EXd
}, PREFIX_OPCODE
},
3959 { "sqrtpd", { XM
, EXx
}, PREFIX_OPCODE
},
3960 { "sqrtsd", { XM
, EXq
}, PREFIX_OPCODE
},
3965 { "rsqrtps",{ XM
, EXx
}, PREFIX_OPCODE
},
3966 { "rsqrtss",{ XM
, EXd
}, PREFIX_OPCODE
},
3971 { "rcpps", { XM
, EXx
}, PREFIX_OPCODE
},
3972 { "rcpss", { XM
, EXd
}, PREFIX_OPCODE
},
3977 { "addps", { XM
, EXx
}, PREFIX_OPCODE
},
3978 { "addss", { XM
, EXd
}, PREFIX_OPCODE
},
3979 { "addpd", { XM
, EXx
}, PREFIX_OPCODE
},
3980 { "addsd", { XM
, EXq
}, PREFIX_OPCODE
},
3985 { "mulps", { XM
, EXx
}, PREFIX_OPCODE
},
3986 { "mulss", { XM
, EXd
}, PREFIX_OPCODE
},
3987 { "mulpd", { XM
, EXx
}, PREFIX_OPCODE
},
3988 { "mulsd", { XM
, EXq
}, PREFIX_OPCODE
},
3993 { "cvtps2pd", { XM
, EXq
}, PREFIX_OPCODE
},
3994 { "cvtss2sd", { XM
, EXd
}, PREFIX_OPCODE
},
3995 { "cvtpd2ps", { XM
, EXx
}, PREFIX_OPCODE
},
3996 { "cvtsd2ss", { XM
, EXq
}, PREFIX_OPCODE
},
4001 { "cvtdq2ps", { XM
, EXx
}, PREFIX_OPCODE
},
4002 { "cvttps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4003 { "cvtps2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4008 { "subps", { XM
, EXx
}, PREFIX_OPCODE
},
4009 { "subss", { XM
, EXd
}, PREFIX_OPCODE
},
4010 { "subpd", { XM
, EXx
}, PREFIX_OPCODE
},
4011 { "subsd", { XM
, EXq
}, PREFIX_OPCODE
},
4016 { "minps", { XM
, EXx
}, PREFIX_OPCODE
},
4017 { "minss", { XM
, EXd
}, PREFIX_OPCODE
},
4018 { "minpd", { XM
, EXx
}, PREFIX_OPCODE
},
4019 { "minsd", { XM
, EXq
}, PREFIX_OPCODE
},
4024 { "divps", { XM
, EXx
}, PREFIX_OPCODE
},
4025 { "divss", { XM
, EXd
}, PREFIX_OPCODE
},
4026 { "divpd", { XM
, EXx
}, PREFIX_OPCODE
},
4027 { "divsd", { XM
, EXq
}, PREFIX_OPCODE
},
4032 { "maxps", { XM
, EXx
}, PREFIX_OPCODE
},
4033 { "maxss", { XM
, EXd
}, PREFIX_OPCODE
},
4034 { "maxpd", { XM
, EXx
}, PREFIX_OPCODE
},
4035 { "maxsd", { XM
, EXq
}, PREFIX_OPCODE
},
4040 { "punpcklbw",{ MX
, EMd
}, PREFIX_OPCODE
},
4042 { "punpcklbw",{ MX
, EMx
}, PREFIX_OPCODE
},
4047 { "punpcklwd",{ MX
, EMd
}, PREFIX_OPCODE
},
4049 { "punpcklwd",{ MX
, EMx
}, PREFIX_OPCODE
},
4054 { "punpckldq",{ MX
, EMd
}, PREFIX_OPCODE
},
4056 { "punpckldq",{ MX
, EMx
}, PREFIX_OPCODE
},
4063 { "punpcklqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4070 { "punpckhqdq", { XM
, EXx
}, PREFIX_OPCODE
},
4075 { "movq", { MX
, EM
}, PREFIX_OPCODE
},
4076 { "movdqu", { XM
, EXx
}, PREFIX_OPCODE
},
4077 { "movdqa", { XM
, EXx
}, PREFIX_OPCODE
},
4082 { "pshufw", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
4083 { "pshufhw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4084 { "pshufd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4085 { "pshuflw",{ XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4088 /* PREFIX_0F73_REG_3 */
4092 { "psrldq", { XS
, Ib
}, 0 },
4095 /* PREFIX_0F73_REG_7 */
4099 { "pslldq", { XS
, Ib
}, 0 },
4104 {"vmread", { Em
, Gm
}, 0 },
4106 {"extrq", { XS
, Ib
, Ib
}, 0 },
4107 {"insertq", { XM
, XS
, Ib
, Ib
}, 0 },
4112 {"vmwrite", { Gm
, Em
}, 0 },
4114 {"extrq", { XM
, XS
}, 0 },
4115 {"insertq", { XM
, XS
}, 0 },
4122 { "haddpd", { XM
, EXx
}, PREFIX_OPCODE
},
4123 { "haddps", { XM
, EXx
}, PREFIX_OPCODE
},
4130 { "hsubpd", { XM
, EXx
}, PREFIX_OPCODE
},
4131 { "hsubps", { XM
, EXx
}, PREFIX_OPCODE
},
4136 { "movK", { Edq
, MX
}, PREFIX_OPCODE
},
4137 { "movq", { XM
, EXq
}, PREFIX_OPCODE
},
4138 { "movK", { Edq
, XM
}, PREFIX_OPCODE
},
4143 { "movq", { EMS
, MX
}, PREFIX_OPCODE
},
4144 { "movdqu", { EXxS
, XM
}, PREFIX_OPCODE
},
4145 { "movdqa", { EXxS
, XM
}, PREFIX_OPCODE
},
4148 /* PREFIX_0FAE_REG_0 */
4151 { "rdfsbase", { Ev
}, 0 },
4154 /* PREFIX_0FAE_REG_1 */
4157 { "rdgsbase", { Ev
}, 0 },
4160 /* PREFIX_0FAE_REG_2 */
4163 { "wrfsbase", { Ev
}, 0 },
4166 /* PREFIX_0FAE_REG_3 */
4169 { "wrgsbase", { Ev
}, 0 },
4172 /* PREFIX_MOD_0_0FAE_REG_4 */
4174 { "xsave", { FXSAVE
}, 0 },
4175 { "ptwrite%LQ", { Edq
}, 0 },
4178 /* PREFIX_MOD_3_0FAE_REG_4 */
4181 { "ptwrite%LQ", { Edq
}, 0 },
4184 /* PREFIX_MOD_0_0FAE_REG_5 */
4186 { "xrstor", { FXSAVE
}, PREFIX_OPCODE
},
4189 /* PREFIX_MOD_3_0FAE_REG_5 */
4191 { "lfence", { Skip_MODRM
}, 0 },
4192 { "incsspK", { Rdq
}, PREFIX_OPCODE
},
4195 /* PREFIX_0FAE_REG_6 */
4197 { "xsaveopt", { FXSAVE
}, PREFIX_OPCODE
},
4198 { "clrssbsy", { Mq
}, PREFIX_OPCODE
},
4199 { "clwb", { Mb
}, PREFIX_OPCODE
},
4202 /* PREFIX_0FAE_REG_7 */
4204 { "clflush", { Mb
}, 0 },
4206 { "clflushopt", { Mb
}, 0 },
4212 { "popcntS", { Gv
, Ev
}, 0 },
4217 { "bsfS", { Gv
, Ev
}, 0 },
4218 { "tzcntS", { Gv
, Ev
}, 0 },
4219 { "bsfS", { Gv
, Ev
}, 0 },
4224 { "bsrS", { Gv
, Ev
}, 0 },
4225 { "lzcntS", { Gv
, Ev
}, 0 },
4226 { "bsrS", { Gv
, Ev
}, 0 },
4231 { "cmpps", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4232 { "cmpss", { XM
, EXd
, CMP
}, PREFIX_OPCODE
},
4233 { "cmppd", { XM
, EXx
, CMP
}, PREFIX_OPCODE
},
4234 { "cmpsd", { XM
, EXq
, CMP
}, PREFIX_OPCODE
},
4237 /* PREFIX_MOD_0_0FC3 */
4239 { "movntiS", { Ev
, Gv
}, PREFIX_OPCODE
},
4242 /* PREFIX_MOD_0_0FC7_REG_6 */
4244 { "vmptrld",{ Mq
}, 0 },
4245 { "vmxon", { Mq
}, 0 },
4246 { "vmclear",{ Mq
}, 0 },
4249 /* PREFIX_MOD_3_0FC7_REG_6 */
4251 { "rdrand", { Ev
}, 0 },
4253 { "rdrand", { Ev
}, 0 }
4256 /* PREFIX_MOD_3_0FC7_REG_7 */
4258 { "rdseed", { Ev
}, 0 },
4259 { "rdpid", { Em
}, 0 },
4260 { "rdseed", { Ev
}, 0 },
4267 { "addsubpd", { XM
, EXx
}, 0 },
4268 { "addsubps", { XM
, EXx
}, 0 },
4274 { "movq2dq",{ XM
, MS
}, 0 },
4275 { "movq", { EXqS
, XM
}, 0 },
4276 { "movdq2q",{ MX
, XS
}, 0 },
4282 { "cvtdq2pd", { XM
, EXq
}, PREFIX_OPCODE
},
4283 { "cvttpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4284 { "cvtpd2dq", { XM
, EXx
}, PREFIX_OPCODE
},
4289 { "movntq", { Mq
, MX
}, PREFIX_OPCODE
},
4291 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
4299 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
4304 { "maskmovq", { MX
, MS
}, PREFIX_OPCODE
},
4306 { "maskmovdqu", { XM
, XS
}, PREFIX_OPCODE
},
4313 { "pblendvb", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4320 { "blendvps", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4327 { "blendvpd", { XM
, EXx
, XMM0
}, PREFIX_OPCODE
},
4334 { "ptest", { XM
, EXx
}, PREFIX_OPCODE
},
4341 { "pmovsxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4348 { "pmovsxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4355 { "pmovsxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4362 { "pmovsxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4369 { "pmovsxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4376 { "pmovsxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4383 { "pmuldq", { XM
, EXx
}, PREFIX_OPCODE
},
4390 { "pcmpeqq", { XM
, EXx
}, PREFIX_OPCODE
},
4397 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
4404 { "packusdw", { XM
, EXx
}, PREFIX_OPCODE
},
4411 { "pmovzxbw", { XM
, EXq
}, PREFIX_OPCODE
},
4418 { "pmovzxbd", { XM
, EXd
}, PREFIX_OPCODE
},
4425 { "pmovzxbq", { XM
, EXw
}, PREFIX_OPCODE
},
4432 { "pmovzxwd", { XM
, EXq
}, PREFIX_OPCODE
},
4439 { "pmovzxwq", { XM
, EXd
}, PREFIX_OPCODE
},
4446 { "pmovzxdq", { XM
, EXq
}, PREFIX_OPCODE
},
4453 { "pcmpgtq", { XM
, EXx
}, PREFIX_OPCODE
},
4460 { "pminsb", { XM
, EXx
}, PREFIX_OPCODE
},
4467 { "pminsd", { XM
, EXx
}, PREFIX_OPCODE
},
4474 { "pminuw", { XM
, EXx
}, PREFIX_OPCODE
},
4481 { "pminud", { XM
, EXx
}, PREFIX_OPCODE
},
4488 { "pmaxsb", { XM
, EXx
}, PREFIX_OPCODE
},
4495 { "pmaxsd", { XM
, EXx
}, PREFIX_OPCODE
},
4502 { "pmaxuw", { XM
, EXx
}, PREFIX_OPCODE
},
4509 { "pmaxud", { XM
, EXx
}, PREFIX_OPCODE
},
4516 { "pmulld", { XM
, EXx
}, PREFIX_OPCODE
},
4523 { "phminposuw", { XM
, EXx
}, PREFIX_OPCODE
},
4530 { "invept", { Gm
, Mo
}, PREFIX_OPCODE
},
4537 { "invvpid", { Gm
, Mo
}, PREFIX_OPCODE
},
4544 { "invpcid", { Gm
, M
}, PREFIX_OPCODE
},
4549 { "sha1nexte", { XM
, EXxmm
}, PREFIX_OPCODE
},
4554 { "sha1msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4559 { "sha1msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4564 { "sha256rnds2", { XM
, EXxmm
, XMM0
}, PREFIX_OPCODE
},
4569 { "sha256msg1", { XM
, EXxmm
}, PREFIX_OPCODE
},
4574 { "sha256msg2", { XM
, EXxmm
}, PREFIX_OPCODE
},
4581 { "gf2p8mulb", { XM
, EXxmm
}, PREFIX_OPCODE
},
4588 { "aesimc", { XM
, EXx
}, PREFIX_OPCODE
},
4595 { "aesenc", { XM
, EXx
}, PREFIX_OPCODE
},
4602 { "aesenclast", { XM
, EXx
}, PREFIX_OPCODE
},
4609 { "aesdec", { XM
, EXx
}, PREFIX_OPCODE
},
4616 { "aesdeclast", { XM
, EXx
}, PREFIX_OPCODE
},
4621 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4623 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4624 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} }, PREFIX_OPCODE
},
4629 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4631 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
}, PREFIX_OPCODE
},
4632 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} }, PREFIX_OPCODE
},
4639 { MOD_TABLE (MOD_0F38F5_PREFIX_2
) },
4644 { MOD_TABLE (MOD_0F38F6_PREFIX_0
) },
4645 { "adoxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4646 { "adcxS", { Gdq
, Edq
}, PREFIX_OPCODE
},
4654 { "roundps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4661 { "roundpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4668 { "roundss", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4675 { "roundsd", { XM
, EXq
, Ib
}, PREFIX_OPCODE
},
4682 { "blendps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4689 { "blendpd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4696 { "pblendw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4703 { "pextrb", { Edqb
, XM
, Ib
}, PREFIX_OPCODE
},
4710 { "pextrw", { Edqw
, XM
, Ib
}, PREFIX_OPCODE
},
4717 { "pextrK", { Edq
, XM
, Ib
}, PREFIX_OPCODE
},
4724 { "extractps", { Edqd
, XM
, Ib
}, PREFIX_OPCODE
},
4731 { "pinsrb", { XM
, Edqb
, Ib
}, PREFIX_OPCODE
},
4738 { "insertps", { XM
, EXd
, Ib
}, PREFIX_OPCODE
},
4745 { "pinsrK", { XM
, Edq
, Ib
}, PREFIX_OPCODE
},
4752 { "dpps", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4759 { "dppd", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4766 { "mpsadbw", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4773 { "pclmulqdq", { XM
, EXx
, PCLMUL
}, PREFIX_OPCODE
},
4780 { "pcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4787 { "pcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, PREFIX_OPCODE
},
4794 { "pcmpistrm", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4801 { "pcmpistri", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4806 { "sha1rnds4", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4813 { "gf2p8affineqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4820 { "gf2p8affineinvqb", { XM
, EXxmm
, Ib
}, PREFIX_OPCODE
},
4827 { "aeskeygenassist", { XM
, EXx
, Ib
}, PREFIX_OPCODE
},
4830 /* PREFIX_VEX_0F10 */
4832 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4833 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4834 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4835 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4838 /* PREFIX_VEX_0F11 */
4840 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4841 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4842 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4843 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4846 /* PREFIX_VEX_0F12 */
4848 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4849 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4850 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4851 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4854 /* PREFIX_VEX_0F16 */
4856 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4857 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4858 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4861 /* PREFIX_VEX_0F2A */
4864 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4866 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4869 /* PREFIX_VEX_0F2C */
4872 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4874 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4877 /* PREFIX_VEX_0F2D */
4880 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4882 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4885 /* PREFIX_VEX_0F2E */
4887 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4889 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4892 /* PREFIX_VEX_0F2F */
4894 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4896 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4899 /* PREFIX_VEX_0F41 */
4901 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4903 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2
) },
4906 /* PREFIX_VEX_0F42 */
4908 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4910 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2
) },
4913 /* PREFIX_VEX_0F44 */
4915 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4917 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2
) },
4920 /* PREFIX_VEX_0F45 */
4922 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4924 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2
) },
4927 /* PREFIX_VEX_0F46 */
4929 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4931 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2
) },
4934 /* PREFIX_VEX_0F47 */
4936 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4938 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2
) },
4941 /* PREFIX_VEX_0F4A */
4943 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0
) },
4945 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2
) },
4948 /* PREFIX_VEX_0F4B */
4950 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0
) },
4952 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4955 /* PREFIX_VEX_0F51 */
4957 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4958 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4959 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4960 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4963 /* PREFIX_VEX_0F52 */
4965 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4966 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4969 /* PREFIX_VEX_0F53 */
4971 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4972 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4975 /* PREFIX_VEX_0F58 */
4977 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4978 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4979 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4980 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4983 /* PREFIX_VEX_0F59 */
4985 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4986 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4987 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4988 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4991 /* PREFIX_VEX_0F5A */
4993 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4994 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4995 { "vcvtpd2ps%XY", { XMM
, EXx
}, 0 },
4996 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4999 /* PREFIX_VEX_0F5B */
5001 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
5002 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
5003 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
5006 /* PREFIX_VEX_0F5C */
5008 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
5009 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
5010 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
5014 /* PREFIX_VEX_0F5D */
5016 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
5017 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
5018 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
5022 /* PREFIX_VEX_0F5E */
5024 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
5025 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
5026 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
5027 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
5030 /* PREFIX_VEX_0F5F */
5032 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
5033 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
5034 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
5035 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
5038 /* PREFIX_VEX_0F60 */
5042 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
5045 /* PREFIX_VEX_0F61 */
5049 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
5052 /* PREFIX_VEX_0F62 */
5056 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
5059 /* PREFIX_VEX_0F63 */
5063 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
5066 /* PREFIX_VEX_0F64 */
5070 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
5073 /* PREFIX_VEX_0F65 */
5077 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
5080 /* PREFIX_VEX_0F66 */
5084 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
5087 /* PREFIX_VEX_0F67 */
5091 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
5094 /* PREFIX_VEX_0F68 */
5098 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
5101 /* PREFIX_VEX_0F69 */
5105 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
5108 /* PREFIX_VEX_0F6A */
5112 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
5115 /* PREFIX_VEX_0F6B */
5119 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
5122 /* PREFIX_VEX_0F6C */
5126 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
5129 /* PREFIX_VEX_0F6D */
5133 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
5136 /* PREFIX_VEX_0F6E */
5140 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
5143 /* PREFIX_VEX_0F6F */
5146 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
5147 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
5150 /* PREFIX_VEX_0F70 */
5153 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
5154 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
5155 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
5158 /* PREFIX_VEX_0F71_REG_2 */
5162 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
5165 /* PREFIX_VEX_0F71_REG_4 */
5169 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
5172 /* PREFIX_VEX_0F71_REG_6 */
5176 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
5179 /* PREFIX_VEX_0F72_REG_2 */
5183 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
5186 /* PREFIX_VEX_0F72_REG_4 */
5190 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
5193 /* PREFIX_VEX_0F72_REG_6 */
5197 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
5200 /* PREFIX_VEX_0F73_REG_2 */
5204 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
5207 /* PREFIX_VEX_0F73_REG_3 */
5211 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
5214 /* PREFIX_VEX_0F73_REG_6 */
5218 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
5221 /* PREFIX_VEX_0F73_REG_7 */
5225 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
5228 /* PREFIX_VEX_0F74 */
5232 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
5235 /* PREFIX_VEX_0F75 */
5239 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
5242 /* PREFIX_VEX_0F76 */
5246 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
5249 /* PREFIX_VEX_0F77 */
5251 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
5254 /* PREFIX_VEX_0F7C */
5258 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
5259 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
5262 /* PREFIX_VEX_0F7D */
5266 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
5267 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
5270 /* PREFIX_VEX_0F7E */
5273 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
5274 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
5277 /* PREFIX_VEX_0F7F */
5280 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
5281 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
5284 /* PREFIX_VEX_0F90 */
5286 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
5288 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2
) },
5291 /* PREFIX_VEX_0F91 */
5293 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
5295 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2
) },
5298 /* PREFIX_VEX_0F92 */
5300 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
5302 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2
) },
5303 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3
) },
5306 /* PREFIX_VEX_0F93 */
5308 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
5310 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2
) },
5311 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3
) },
5314 /* PREFIX_VEX_0F98 */
5316 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
5318 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2
) },
5321 /* PREFIX_VEX_0F99 */
5323 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0
) },
5325 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2
) },
5328 /* PREFIX_VEX_0FC2 */
5330 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
5331 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
5332 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
5333 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
5336 /* PREFIX_VEX_0FC4 */
5340 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
5343 /* PREFIX_VEX_0FC5 */
5347 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
5350 /* PREFIX_VEX_0FD0 */
5354 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
5355 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
5358 /* PREFIX_VEX_0FD1 */
5362 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
5365 /* PREFIX_VEX_0FD2 */
5369 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
5372 /* PREFIX_VEX_0FD3 */
5376 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
5379 /* PREFIX_VEX_0FD4 */
5383 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
5386 /* PREFIX_VEX_0FD5 */
5390 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
5393 /* PREFIX_VEX_0FD6 */
5397 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
5400 /* PREFIX_VEX_0FD7 */
5404 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
5407 /* PREFIX_VEX_0FD8 */
5411 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
5414 /* PREFIX_VEX_0FD9 */
5418 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
5421 /* PREFIX_VEX_0FDA */
5425 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
5428 /* PREFIX_VEX_0FDB */
5432 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
5435 /* PREFIX_VEX_0FDC */
5439 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
5442 /* PREFIX_VEX_0FDD */
5446 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
5449 /* PREFIX_VEX_0FDE */
5453 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
5456 /* PREFIX_VEX_0FDF */
5460 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
5463 /* PREFIX_VEX_0FE0 */
5467 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
5470 /* PREFIX_VEX_0FE1 */
5474 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
5477 /* PREFIX_VEX_0FE2 */
5481 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5484 /* PREFIX_VEX_0FE3 */
5488 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5491 /* PREFIX_VEX_0FE4 */
5495 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5498 /* PREFIX_VEX_0FE5 */
5502 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5505 /* PREFIX_VEX_0FE6 */
5508 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5509 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5510 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5513 /* PREFIX_VEX_0FE7 */
5517 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5520 /* PREFIX_VEX_0FE8 */
5524 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5527 /* PREFIX_VEX_0FE9 */
5531 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5534 /* PREFIX_VEX_0FEA */
5538 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5541 /* PREFIX_VEX_0FEB */
5545 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5548 /* PREFIX_VEX_0FEC */
5552 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5555 /* PREFIX_VEX_0FED */
5559 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5562 /* PREFIX_VEX_0FEE */
5566 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5569 /* PREFIX_VEX_0FEF */
5573 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5576 /* PREFIX_VEX_0FF0 */
5581 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5584 /* PREFIX_VEX_0FF1 */
5588 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5591 /* PREFIX_VEX_0FF2 */
5595 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5598 /* PREFIX_VEX_0FF3 */
5602 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5605 /* PREFIX_VEX_0FF4 */
5609 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5612 /* PREFIX_VEX_0FF5 */
5616 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5619 /* PREFIX_VEX_0FF6 */
5623 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5626 /* PREFIX_VEX_0FF7 */
5630 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5633 /* PREFIX_VEX_0FF8 */
5637 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5640 /* PREFIX_VEX_0FF9 */
5644 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5647 /* PREFIX_VEX_0FFA */
5651 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5654 /* PREFIX_VEX_0FFB */
5658 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5661 /* PREFIX_VEX_0FFC */
5665 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5668 /* PREFIX_VEX_0FFD */
5672 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5675 /* PREFIX_VEX_0FFE */
5679 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5682 /* PREFIX_VEX_0F3800 */
5686 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5689 /* PREFIX_VEX_0F3801 */
5693 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5696 /* PREFIX_VEX_0F3802 */
5700 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5703 /* PREFIX_VEX_0F3803 */
5707 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5710 /* PREFIX_VEX_0F3804 */
5714 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5717 /* PREFIX_VEX_0F3805 */
5721 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5724 /* PREFIX_VEX_0F3806 */
5728 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5731 /* PREFIX_VEX_0F3807 */
5735 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5738 /* PREFIX_VEX_0F3808 */
5742 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5745 /* PREFIX_VEX_0F3809 */
5749 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5752 /* PREFIX_VEX_0F380A */
5756 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5759 /* PREFIX_VEX_0F380B */
5763 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5766 /* PREFIX_VEX_0F380C */
5770 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5773 /* PREFIX_VEX_0F380D */
5777 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5780 /* PREFIX_VEX_0F380E */
5784 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5787 /* PREFIX_VEX_0F380F */
5791 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5794 /* PREFIX_VEX_0F3813 */
5798 { "vcvtph2ps", { XM
, EXxmmq
}, 0 },
5801 /* PREFIX_VEX_0F3816 */
5805 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5808 /* PREFIX_VEX_0F3817 */
5812 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5815 /* PREFIX_VEX_0F3818 */
5819 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5822 /* PREFIX_VEX_0F3819 */
5826 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5829 /* PREFIX_VEX_0F381A */
5833 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5836 /* PREFIX_VEX_0F381C */
5840 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5843 /* PREFIX_VEX_0F381D */
5847 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5850 /* PREFIX_VEX_0F381E */
5854 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5857 /* PREFIX_VEX_0F3820 */
5861 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5864 /* PREFIX_VEX_0F3821 */
5868 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5871 /* PREFIX_VEX_0F3822 */
5875 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5878 /* PREFIX_VEX_0F3823 */
5882 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5885 /* PREFIX_VEX_0F3824 */
5889 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5892 /* PREFIX_VEX_0F3825 */
5896 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5899 /* PREFIX_VEX_0F3828 */
5903 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5906 /* PREFIX_VEX_0F3829 */
5910 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5913 /* PREFIX_VEX_0F382A */
5917 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5920 /* PREFIX_VEX_0F382B */
5924 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5927 /* PREFIX_VEX_0F382C */
5931 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5934 /* PREFIX_VEX_0F382D */
5938 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5941 /* PREFIX_VEX_0F382E */
5945 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5948 /* PREFIX_VEX_0F382F */
5952 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5955 /* PREFIX_VEX_0F3830 */
5959 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5962 /* PREFIX_VEX_0F3831 */
5966 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5969 /* PREFIX_VEX_0F3832 */
5973 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5976 /* PREFIX_VEX_0F3833 */
5980 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5983 /* PREFIX_VEX_0F3834 */
5987 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5990 /* PREFIX_VEX_0F3835 */
5994 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5997 /* PREFIX_VEX_0F3836 */
6001 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
6004 /* PREFIX_VEX_0F3837 */
6008 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
6011 /* PREFIX_VEX_0F3838 */
6015 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
6018 /* PREFIX_VEX_0F3839 */
6022 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
6025 /* PREFIX_VEX_0F383A */
6029 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
6032 /* PREFIX_VEX_0F383B */
6036 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
6039 /* PREFIX_VEX_0F383C */
6043 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
6046 /* PREFIX_VEX_0F383D */
6050 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
6053 /* PREFIX_VEX_0F383E */
6057 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
6060 /* PREFIX_VEX_0F383F */
6064 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
6067 /* PREFIX_VEX_0F3840 */
6071 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
6074 /* PREFIX_VEX_0F3841 */
6078 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
6081 /* PREFIX_VEX_0F3845 */
6085 { "vpsrlv%LW", { XM
, Vex
, EXx
}, 0 },
6088 /* PREFIX_VEX_0F3846 */
6092 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
6095 /* PREFIX_VEX_0F3847 */
6099 { "vpsllv%LW", { XM
, Vex
, EXx
}, 0 },
6102 /* PREFIX_VEX_0F3858 */
6106 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
6109 /* PREFIX_VEX_0F3859 */
6113 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
6116 /* PREFIX_VEX_0F385A */
6120 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
6123 /* PREFIX_VEX_0F3878 */
6127 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
6130 /* PREFIX_VEX_0F3879 */
6134 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
6137 /* PREFIX_VEX_0F388C */
6141 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
6144 /* PREFIX_VEX_0F388E */
6148 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
6151 /* PREFIX_VEX_0F3890 */
6155 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6158 /* PREFIX_VEX_0F3891 */
6162 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6165 /* PREFIX_VEX_0F3892 */
6169 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
}, 0 },
6172 /* PREFIX_VEX_0F3893 */
6176 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
}, 0 },
6179 /* PREFIX_VEX_0F3896 */
6183 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6186 /* PREFIX_VEX_0F3897 */
6190 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6193 /* PREFIX_VEX_0F3898 */
6197 { "vfmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6200 /* PREFIX_VEX_0F3899 */
6204 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6207 /* PREFIX_VEX_0F389A */
6211 { "vfmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6214 /* PREFIX_VEX_0F389B */
6218 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6221 /* PREFIX_VEX_0F389C */
6225 { "vfnmadd132p%XW", { XM
, Vex
, EXx
}, 0 },
6228 /* PREFIX_VEX_0F389D */
6232 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6235 /* PREFIX_VEX_0F389E */
6239 { "vfnmsub132p%XW", { XM
, Vex
, EXx
}, 0 },
6242 /* PREFIX_VEX_0F389F */
6246 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6249 /* PREFIX_VEX_0F38A6 */
6253 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6257 /* PREFIX_VEX_0F38A7 */
6261 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6264 /* PREFIX_VEX_0F38A8 */
6268 { "vfmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6271 /* PREFIX_VEX_0F38A9 */
6275 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6278 /* PREFIX_VEX_0F38AA */
6282 { "vfmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6285 /* PREFIX_VEX_0F38AB */
6289 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6292 /* PREFIX_VEX_0F38AC */
6296 { "vfnmadd213p%XW", { XM
, Vex
, EXx
}, 0 },
6299 /* PREFIX_VEX_0F38AD */
6303 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6306 /* PREFIX_VEX_0F38AE */
6310 { "vfnmsub213p%XW", { XM
, Vex
, EXx
}, 0 },
6313 /* PREFIX_VEX_0F38AF */
6317 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6320 /* PREFIX_VEX_0F38B6 */
6324 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6327 /* PREFIX_VEX_0F38B7 */
6331 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6334 /* PREFIX_VEX_0F38B8 */
6338 { "vfmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6341 /* PREFIX_VEX_0F38B9 */
6345 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6348 /* PREFIX_VEX_0F38BA */
6352 { "vfmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6355 /* PREFIX_VEX_0F38BB */
6359 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6362 /* PREFIX_VEX_0F38BC */
6366 { "vfnmadd231p%XW", { XM
, Vex
, EXx
}, 0 },
6369 /* PREFIX_VEX_0F38BD */
6373 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6376 /* PREFIX_VEX_0F38BE */
6380 { "vfnmsub231p%XW", { XM
, Vex
, EXx
}, 0 },
6383 /* PREFIX_VEX_0F38BF */
6387 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
}, 0 },
6390 /* PREFIX_VEX_0F38CF */
6394 { VEX_W_TABLE (VEX_W_0F38CF_P_2
) },
6397 /* PREFIX_VEX_0F38DB */
6401 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
6404 /* PREFIX_VEX_0F38DC */
6408 { "vaesenc", { XM
, Vex
, EXx
}, 0 },
6411 /* PREFIX_VEX_0F38DD */
6415 { "vaesenclast", { XM
, Vex
, EXx
}, 0 },
6418 /* PREFIX_VEX_0F38DE */
6422 { "vaesdec", { XM
, Vex
, EXx
}, 0 },
6425 /* PREFIX_VEX_0F38DF */
6429 { "vaesdeclast", { XM
, Vex
, EXx
}, 0 },
6432 /* PREFIX_VEX_0F38F2 */
6434 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
6437 /* PREFIX_VEX_0F38F3_REG_1 */
6439 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
6442 /* PREFIX_VEX_0F38F3_REG_2 */
6444 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
6447 /* PREFIX_VEX_0F38F3_REG_3 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
6452 /* PREFIX_VEX_0F38F5 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
6455 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
6457 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
6460 /* PREFIX_VEX_0F38F6 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
6468 /* PREFIX_VEX_0F38F7 */
6470 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
6471 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
6472 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
6473 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
6476 /* PREFIX_VEX_0F3A00 */
6480 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
6483 /* PREFIX_VEX_0F3A01 */
6487 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6490 /* PREFIX_VEX_0F3A02 */
6494 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6497 /* PREFIX_VEX_0F3A04 */
6501 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6504 /* PREFIX_VEX_0F3A05 */
6508 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6511 /* PREFIX_VEX_0F3A06 */
6515 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6518 /* PREFIX_VEX_0F3A08 */
6522 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6525 /* PREFIX_VEX_0F3A09 */
6529 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6532 /* PREFIX_VEX_0F3A0A */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6539 /* PREFIX_VEX_0F3A0B */
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6546 /* PREFIX_VEX_0F3A0C */
6550 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6553 /* PREFIX_VEX_0F3A0D */
6557 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6560 /* PREFIX_VEX_0F3A0E */
6564 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6567 /* PREFIX_VEX_0F3A0F */
6571 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6574 /* PREFIX_VEX_0F3A14 */
6578 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6581 /* PREFIX_VEX_0F3A15 */
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6588 /* PREFIX_VEX_0F3A16 */
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6595 /* PREFIX_VEX_0F3A17 */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6602 /* PREFIX_VEX_0F3A18 */
6606 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6609 /* PREFIX_VEX_0F3A19 */
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6616 /* PREFIX_VEX_0F3A1D */
6620 { "vcvtps2ph", { EXxmmq
, XM
, Ib
}, 0 },
6623 /* PREFIX_VEX_0F3A20 */
6627 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6630 /* PREFIX_VEX_0F3A21 */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6637 /* PREFIX_VEX_0F3A22 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6644 /* PREFIX_VEX_0F3A30 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6651 /* PREFIX_VEX_0F3A31 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2
) },
6658 /* PREFIX_VEX_0F3A32 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6665 /* PREFIX_VEX_0F3A33 */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2
) },
6672 /* PREFIX_VEX_0F3A38 */
6676 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6679 /* PREFIX_VEX_0F3A39 */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6686 /* PREFIX_VEX_0F3A40 */
6690 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6693 /* PREFIX_VEX_0F3A41 */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6700 /* PREFIX_VEX_0F3A42 */
6704 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6707 /* PREFIX_VEX_0F3A44 */
6711 { "vpclmulqdq", { XM
, Vex
, EXx
, PCLMUL
}, 0 },
6714 /* PREFIX_VEX_0F3A46 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6721 /* PREFIX_VEX_0F3A48 */
6725 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6728 /* PREFIX_VEX_0F3A49 */
6732 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6735 /* PREFIX_VEX_0F3A4A */
6739 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6742 /* PREFIX_VEX_0F3A4B */
6746 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6749 /* PREFIX_VEX_0F3A4C */
6753 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6756 /* PREFIX_VEX_0F3A5C */
6760 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6763 /* PREFIX_VEX_0F3A5D */
6767 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6770 /* PREFIX_VEX_0F3A5E */
6774 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6777 /* PREFIX_VEX_0F3A5F */
6781 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6784 /* PREFIX_VEX_0F3A60 */
6788 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6792 /* PREFIX_VEX_0F3A61 */
6796 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6799 /* PREFIX_VEX_0F3A62 */
6803 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6806 /* PREFIX_VEX_0F3A63 */
6810 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6813 /* PREFIX_VEX_0F3A68 */
6817 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6820 /* PREFIX_VEX_0F3A69 */
6824 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6827 /* PREFIX_VEX_0F3A6A */
6831 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6834 /* PREFIX_VEX_0F3A6B */
6838 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6841 /* PREFIX_VEX_0F3A6C */
6845 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6848 /* PREFIX_VEX_0F3A6D */
6852 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6855 /* PREFIX_VEX_0F3A6E */
6859 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6862 /* PREFIX_VEX_0F3A6F */
6866 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6869 /* PREFIX_VEX_0F3A78 */
6873 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6876 /* PREFIX_VEX_0F3A79 */
6880 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6883 /* PREFIX_VEX_0F3A7A */
6887 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6890 /* PREFIX_VEX_0F3A7B */
6894 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6897 /* PREFIX_VEX_0F3A7C */
6901 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6905 /* PREFIX_VEX_0F3A7D */
6909 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
6912 /* PREFIX_VEX_0F3A7E */
6916 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6919 /* PREFIX_VEX_0F3A7F */
6923 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6926 /* PREFIX_VEX_0F3ACE */
6930 { VEX_W_TABLE (VEX_W_0F3ACE_P_2
) },
6933 /* PREFIX_VEX_0F3ACF */
6937 { VEX_W_TABLE (VEX_W_0F3ACF_P_2
) },
6940 /* PREFIX_VEX_0F3ADF */
6944 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6947 /* PREFIX_VEX_0F3AF0 */
6952 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6955 #define NEED_PREFIX_TABLE
6956 #include "i386-dis-evex.h"
6957 #undef NEED_PREFIX_TABLE
6960 static const struct dis386 x86_64_table
[][2] = {
6963 { "pushP", { es
}, 0 },
6968 { "popP", { es
}, 0 },
6973 { "pushP", { cs
}, 0 },
6978 { "pushP", { ss
}, 0 },
6983 { "popP", { ss
}, 0 },
6988 { "pushP", { ds
}, 0 },
6993 { "popP", { ds
}, 0 },
6998 { "daa", { XX
}, 0 },
7003 { "das", { XX
}, 0 },
7008 { "aaa", { XX
}, 0 },
7013 { "aas", { XX
}, 0 },
7018 { "pushaP", { XX
}, 0 },
7023 { "popaP", { XX
}, 0 },
7028 { MOD_TABLE (MOD_62_32BIT
) },
7029 { EVEX_TABLE (EVEX_0F
) },
7034 { "arpl", { Ew
, Gw
}, 0 },
7035 { "movs{lq|xd}", { Gv
, Ed
}, 0 },
7040 { "ins{R|}", { Yzr
, indirDX
}, 0 },
7041 { "ins{G|}", { Yzr
, indirDX
}, 0 },
7046 { "outs{R|}", { indirDXr
, Xz
}, 0 },
7047 { "outs{G|}", { indirDXr
, Xz
}, 0 },
7052 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7053 { REG_TABLE (REG_80
) },
7058 { "Jcall{T|}", { Ap
}, 0 },
7063 { MOD_TABLE (MOD_C4_32BIT
) },
7064 { VEX_C4_TABLE (VEX_0F
) },
7069 { MOD_TABLE (MOD_C5_32BIT
) },
7070 { VEX_C5_TABLE (VEX_0F
) },
7075 { "into", { XX
}, 0 },
7080 { "aam", { Ib
}, 0 },
7085 { "aad", { Ib
}, 0 },
7090 { "callP", { Jv
, BND
}, 0 },
7091 { "call@", { Jv
, BND
}, 0 }
7096 { "jmpP", { Jv
, BND
}, 0 },
7097 { "jmp@", { Jv
, BND
}, 0 }
7102 { "Jjmp{T|}", { Ap
}, 0 },
7105 /* X86_64_0F01_REG_0 */
7107 { "sgdt{Q|IQ}", { M
}, 0 },
7108 { "sgdt", { M
}, 0 },
7111 /* X86_64_0F01_REG_1 */
7113 { "sidt{Q|IQ}", { M
}, 0 },
7114 { "sidt", { M
}, 0 },
7117 /* X86_64_0F01_REG_2 */
7119 { "lgdt{Q|Q}", { M
}, 0 },
7120 { "lgdt", { M
}, 0 },
7123 /* X86_64_0F01_REG_3 */
7125 { "lidt{Q|Q}", { M
}, 0 },
7126 { "lidt", { M
}, 0 },
7130 static const struct dis386 three_byte_table
[][256] = {
7132 /* THREE_BYTE_0F38 */
7135 { "pshufb", { MX
, EM
}, PREFIX_OPCODE
},
7136 { "phaddw", { MX
, EM
}, PREFIX_OPCODE
},
7137 { "phaddd", { MX
, EM
}, PREFIX_OPCODE
},
7138 { "phaddsw", { MX
, EM
}, PREFIX_OPCODE
},
7139 { "pmaddubsw", { MX
, EM
}, PREFIX_OPCODE
},
7140 { "phsubw", { MX
, EM
}, PREFIX_OPCODE
},
7141 { "phsubd", { MX
, EM
}, PREFIX_OPCODE
},
7142 { "phsubsw", { MX
, EM
}, PREFIX_OPCODE
},
7144 { "psignb", { MX
, EM
}, PREFIX_OPCODE
},
7145 { "psignw", { MX
, EM
}, PREFIX_OPCODE
},
7146 { "psignd", { MX
, EM
}, PREFIX_OPCODE
},
7147 { "pmulhrsw", { MX
, EM
}, PREFIX_OPCODE
},
7153 { PREFIX_TABLE (PREFIX_0F3810
) },
7157 { PREFIX_TABLE (PREFIX_0F3814
) },
7158 { PREFIX_TABLE (PREFIX_0F3815
) },
7160 { PREFIX_TABLE (PREFIX_0F3817
) },
7166 { "pabsb", { MX
, EM
}, PREFIX_OPCODE
},
7167 { "pabsw", { MX
, EM
}, PREFIX_OPCODE
},
7168 { "pabsd", { MX
, EM
}, PREFIX_OPCODE
},
7171 { PREFIX_TABLE (PREFIX_0F3820
) },
7172 { PREFIX_TABLE (PREFIX_0F3821
) },
7173 { PREFIX_TABLE (PREFIX_0F3822
) },
7174 { PREFIX_TABLE (PREFIX_0F3823
) },
7175 { PREFIX_TABLE (PREFIX_0F3824
) },
7176 { PREFIX_TABLE (PREFIX_0F3825
) },
7180 { PREFIX_TABLE (PREFIX_0F3828
) },
7181 { PREFIX_TABLE (PREFIX_0F3829
) },
7182 { PREFIX_TABLE (PREFIX_0F382A
) },
7183 { PREFIX_TABLE (PREFIX_0F382B
) },
7189 { PREFIX_TABLE (PREFIX_0F3830
) },
7190 { PREFIX_TABLE (PREFIX_0F3831
) },
7191 { PREFIX_TABLE (PREFIX_0F3832
) },
7192 { PREFIX_TABLE (PREFIX_0F3833
) },
7193 { PREFIX_TABLE (PREFIX_0F3834
) },
7194 { PREFIX_TABLE (PREFIX_0F3835
) },
7196 { PREFIX_TABLE (PREFIX_0F3837
) },
7198 { PREFIX_TABLE (PREFIX_0F3838
) },
7199 { PREFIX_TABLE (PREFIX_0F3839
) },
7200 { PREFIX_TABLE (PREFIX_0F383A
) },
7201 { PREFIX_TABLE (PREFIX_0F383B
) },
7202 { PREFIX_TABLE (PREFIX_0F383C
) },
7203 { PREFIX_TABLE (PREFIX_0F383D
) },
7204 { PREFIX_TABLE (PREFIX_0F383E
) },
7205 { PREFIX_TABLE (PREFIX_0F383F
) },
7207 { PREFIX_TABLE (PREFIX_0F3840
) },
7208 { PREFIX_TABLE (PREFIX_0F3841
) },
7279 { PREFIX_TABLE (PREFIX_0F3880
) },
7280 { PREFIX_TABLE (PREFIX_0F3881
) },
7281 { PREFIX_TABLE (PREFIX_0F3882
) },
7360 { PREFIX_TABLE (PREFIX_0F38C8
) },
7361 { PREFIX_TABLE (PREFIX_0F38C9
) },
7362 { PREFIX_TABLE (PREFIX_0F38CA
) },
7363 { PREFIX_TABLE (PREFIX_0F38CB
) },
7364 { PREFIX_TABLE (PREFIX_0F38CC
) },
7365 { PREFIX_TABLE (PREFIX_0F38CD
) },
7367 { PREFIX_TABLE (PREFIX_0F38CF
) },
7381 { PREFIX_TABLE (PREFIX_0F38DB
) },
7382 { PREFIX_TABLE (PREFIX_0F38DC
) },
7383 { PREFIX_TABLE (PREFIX_0F38DD
) },
7384 { PREFIX_TABLE (PREFIX_0F38DE
) },
7385 { PREFIX_TABLE (PREFIX_0F38DF
) },
7405 { PREFIX_TABLE (PREFIX_0F38F0
) },
7406 { PREFIX_TABLE (PREFIX_0F38F1
) },
7410 { PREFIX_TABLE (PREFIX_0F38F5
) },
7411 { PREFIX_TABLE (PREFIX_0F38F6
) },
7423 /* THREE_BYTE_0F3A */
7435 { PREFIX_TABLE (PREFIX_0F3A08
) },
7436 { PREFIX_TABLE (PREFIX_0F3A09
) },
7437 { PREFIX_TABLE (PREFIX_0F3A0A
) },
7438 { PREFIX_TABLE (PREFIX_0F3A0B
) },
7439 { PREFIX_TABLE (PREFIX_0F3A0C
) },
7440 { PREFIX_TABLE (PREFIX_0F3A0D
) },
7441 { PREFIX_TABLE (PREFIX_0F3A0E
) },
7442 { "palignr", { MX
, EM
, Ib
}, PREFIX_OPCODE
},
7448 { PREFIX_TABLE (PREFIX_0F3A14
) },
7449 { PREFIX_TABLE (PREFIX_0F3A15
) },
7450 { PREFIX_TABLE (PREFIX_0F3A16
) },
7451 { PREFIX_TABLE (PREFIX_0F3A17
) },
7462 { PREFIX_TABLE (PREFIX_0F3A20
) },
7463 { PREFIX_TABLE (PREFIX_0F3A21
) },
7464 { PREFIX_TABLE (PREFIX_0F3A22
) },
7498 { PREFIX_TABLE (PREFIX_0F3A40
) },
7499 { PREFIX_TABLE (PREFIX_0F3A41
) },
7500 { PREFIX_TABLE (PREFIX_0F3A42
) },
7502 { PREFIX_TABLE (PREFIX_0F3A44
) },
7534 { PREFIX_TABLE (PREFIX_0F3A60
) },
7535 { PREFIX_TABLE (PREFIX_0F3A61
) },
7536 { PREFIX_TABLE (PREFIX_0F3A62
) },
7537 { PREFIX_TABLE (PREFIX_0F3A63
) },
7655 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7657 { PREFIX_TABLE (PREFIX_0F3ACE
) },
7658 { PREFIX_TABLE (PREFIX_0F3ACF
) },
7676 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7716 static const struct dis386 xop_table
[][256] = {
7869 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7870 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7871 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7879 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7880 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7887 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7888 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7889 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7897 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7898 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7902 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7903 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7906 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7924 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
}, 0 },
7936 { "vprotb", { XM
, Vex_2src_1
, Ib
}, 0 },
7937 { "vprotw", { XM
, Vex_2src_1
, Ib
}, 0 },
7938 { "vprotd", { XM
, Vex_2src_1
, Ib
}, 0 },
7939 { "vprotq", { XM
, Vex_2src_1
, Ib
}, 0 },
7949 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7950 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7951 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7952 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7985 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7986 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7987 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7988 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
8012 { REG_TABLE (REG_XOP_TBM_01
) },
8013 { REG_TABLE (REG_XOP_TBM_02
) },
8031 { REG_TABLE (REG_XOP_LWPCB
) },
8155 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
8156 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
8157 { "vfrczss", { XM
, EXd
}, 0 },
8158 { "vfrczsd", { XM
, EXq
}, 0 },
8173 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8174 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8175 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8176 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8177 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8178 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8179 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8180 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8182 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8183 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8184 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8185 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
}, 0 },
8228 { "vphaddbw", { XM
, EXxmm
}, 0 },
8229 { "vphaddbd", { XM
, EXxmm
}, 0 },
8230 { "vphaddbq", { XM
, EXxmm
}, 0 },
8233 { "vphaddwd", { XM
, EXxmm
}, 0 },
8234 { "vphaddwq", { XM
, EXxmm
}, 0 },
8239 { "vphadddq", { XM
, EXxmm
}, 0 },
8246 { "vphaddubw", { XM
, EXxmm
}, 0 },
8247 { "vphaddubd", { XM
, EXxmm
}, 0 },
8248 { "vphaddubq", { XM
, EXxmm
}, 0 },
8251 { "vphadduwd", { XM
, EXxmm
}, 0 },
8252 { "vphadduwq", { XM
, EXxmm
}, 0 },
8257 { "vphaddudq", { XM
, EXxmm
}, 0 },
8264 { "vphsubbw", { XM
, EXxmm
}, 0 },
8265 { "vphsubwd", { XM
, EXxmm
}, 0 },
8266 { "vphsubdq", { XM
, EXxmm
}, 0 },
8320 { "bextr", { Gv
, Ev
, Iq
}, 0 },
8322 { REG_TABLE (REG_XOP_LWP
) },
8592 static const struct dis386 vex_table
[][256] = {
8614 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8617 { MOD_TABLE (MOD_VEX_0F13
) },
8618 { VEX_W_TABLE (VEX_W_0F14
) },
8619 { VEX_W_TABLE (VEX_W_0F15
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8621 { MOD_TABLE (MOD_VEX_0F17
) },
8641 { VEX_W_TABLE (VEX_W_0F28
) },
8642 { VEX_W_TABLE (VEX_W_0F29
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8644 { MOD_TABLE (MOD_VEX_0F2B
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8669 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F4A
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8686 { MOD_TABLE (MOD_VEX_0F50
) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8690 { "vandpX", { XM
, Vex
, EXx
}, 0 },
8691 { "vandnpX", { XM
, Vex
, EXx
}, 0 },
8692 { "vorpX", { XM
, Vex
, EXx
}, 0 },
8693 { "vxorpX", { XM
, Vex
, EXx
}, 0 },
8695 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8696 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8705 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8717 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8723 { REG_TABLE (REG_VEX_0F71
) },
8724 { REG_TABLE (REG_VEX_0F72
) },
8725 { REG_TABLE (REG_VEX_0F73
) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F99
) },
8791 { REG_TABLE (REG_VEX_0FAE
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8818 { "vshufpX", { XM
, Vex
, EXx
, Ib
}, 0 },
8830 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8840 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8879 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8986 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8987 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
9050 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
9059 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F38CF
) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
9160 { REG_TABLE (REG_VEX_0F38F3
) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
9179 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
9180 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
9182 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
9183 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
9188 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
9210 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
9232 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
9233 { PREFIX_TABLE (PREFIX_VEX_0F3A31
) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A33
) },
9241 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
9242 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9251 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9252 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9254 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9260 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9263 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9320 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9409 { PREFIX_TABLE(PREFIX_VEX_0F3ACE
) },
9410 { PREFIX_TABLE(PREFIX_VEX_0F3ACF
) },
9428 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9448 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9468 #define NEED_OPCODE_TABLE
9469 #include "i386-dis-evex.h"
9470 #undef NEED_OPCODE_TABLE
9471 static const struct dis386 vex_len_table
[][2] = {
9472 /* VEX_LEN_0F10_P_1 */
9474 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9475 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9478 /* VEX_LEN_0F10_P_3 */
9480 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9481 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9484 /* VEX_LEN_0F11_P_1 */
9486 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9487 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9490 /* VEX_LEN_0F11_P_3 */
9492 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9493 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9496 /* VEX_LEN_0F12_P_0_M_0 */
9498 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9501 /* VEX_LEN_0F12_P_0_M_1 */
9503 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9506 /* VEX_LEN_0F12_P_2 */
9508 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9511 /* VEX_LEN_0F13_M_0 */
9513 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9516 /* VEX_LEN_0F16_P_0_M_0 */
9518 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9521 /* VEX_LEN_0F16_P_0_M_1 */
9523 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9526 /* VEX_LEN_0F16_P_2 */
9528 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9531 /* VEX_LEN_0F17_M_0 */
9533 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9536 /* VEX_LEN_0F2A_P_1 */
9538 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9539 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9542 /* VEX_LEN_0F2A_P_3 */
9544 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9545 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
}, 0 },
9548 /* VEX_LEN_0F2C_P_1 */
9550 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9551 { "vcvttss2siY", { Gv
, EXdScalar
}, 0 },
9554 /* VEX_LEN_0F2C_P_3 */
9556 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9557 { "vcvttsd2siY", { Gv
, EXqScalar
}, 0 },
9560 /* VEX_LEN_0F2D_P_1 */
9562 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9563 { "vcvtss2siY", { Gv
, EXdScalar
}, 0 },
9566 /* VEX_LEN_0F2D_P_3 */
9568 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9569 { "vcvtsd2siY", { Gv
, EXqScalar
}, 0 },
9572 /* VEX_LEN_0F2E_P_0 */
9574 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9575 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9578 /* VEX_LEN_0F2E_P_2 */
9580 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9581 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9584 /* VEX_LEN_0F2F_P_0 */
9586 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9587 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9590 /* VEX_LEN_0F2F_P_2 */
9592 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9593 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9596 /* VEX_LEN_0F41_P_0 */
9599 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9601 /* VEX_LEN_0F41_P_2 */
9604 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1
) },
9606 /* VEX_LEN_0F42_P_0 */
9609 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9611 /* VEX_LEN_0F42_P_2 */
9614 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1
) },
9616 /* VEX_LEN_0F44_P_0 */
9618 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9620 /* VEX_LEN_0F44_P_2 */
9622 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0
) },
9624 /* VEX_LEN_0F45_P_0 */
9627 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9629 /* VEX_LEN_0F45_P_2 */
9632 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1
) },
9634 /* VEX_LEN_0F46_P_0 */
9637 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9639 /* VEX_LEN_0F46_P_2 */
9642 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1
) },
9644 /* VEX_LEN_0F47_P_0 */
9647 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9649 /* VEX_LEN_0F47_P_2 */
9652 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1
) },
9654 /* VEX_LEN_0F4A_P_0 */
9657 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1
) },
9659 /* VEX_LEN_0F4A_P_2 */
9662 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1
) },
9664 /* VEX_LEN_0F4B_P_0 */
9667 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1
) },
9669 /* VEX_LEN_0F4B_P_2 */
9672 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9675 /* VEX_LEN_0F51_P_1 */
9677 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9678 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9681 /* VEX_LEN_0F51_P_3 */
9683 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9684 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9687 /* VEX_LEN_0F52_P_1 */
9689 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9690 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9693 /* VEX_LEN_0F53_P_1 */
9695 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9696 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9699 /* VEX_LEN_0F58_P_1 */
9701 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9702 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9705 /* VEX_LEN_0F58_P_3 */
9707 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9708 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9711 /* VEX_LEN_0F59_P_1 */
9713 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9714 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9717 /* VEX_LEN_0F59_P_3 */
9719 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9720 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9723 /* VEX_LEN_0F5A_P_1 */
9725 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9726 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9729 /* VEX_LEN_0F5A_P_3 */
9731 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9732 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9735 /* VEX_LEN_0F5C_P_1 */
9737 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9738 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9741 /* VEX_LEN_0F5C_P_3 */
9743 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9744 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9747 /* VEX_LEN_0F5D_P_1 */
9749 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9750 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9753 /* VEX_LEN_0F5D_P_3 */
9755 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9756 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9759 /* VEX_LEN_0F5E_P_1 */
9761 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9762 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9765 /* VEX_LEN_0F5E_P_3 */
9767 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9768 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9771 /* VEX_LEN_0F5F_P_1 */
9773 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9774 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9777 /* VEX_LEN_0F5F_P_3 */
9779 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9780 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9783 /* VEX_LEN_0F6E_P_2 */
9785 { "vmovK", { XMScalar
, Edq
}, 0 },
9786 { "vmovK", { XMScalar
, Edq
}, 0 },
9789 /* VEX_LEN_0F7E_P_1 */
9791 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9792 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9795 /* VEX_LEN_0F7E_P_2 */
9797 { "vmovK", { Edq
, XMScalar
}, 0 },
9798 { "vmovK", { Edq
, XMScalar
}, 0 },
9801 /* VEX_LEN_0F90_P_0 */
9803 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9806 /* VEX_LEN_0F90_P_2 */
9808 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0
) },
9811 /* VEX_LEN_0F91_P_0 */
9813 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9816 /* VEX_LEN_0F91_P_2 */
9818 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0
) },
9821 /* VEX_LEN_0F92_P_0 */
9823 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9826 /* VEX_LEN_0F92_P_2 */
9828 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0
) },
9831 /* VEX_LEN_0F92_P_3 */
9833 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0
) },
9836 /* VEX_LEN_0F93_P_0 */
9838 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9841 /* VEX_LEN_0F93_P_2 */
9843 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0
) },
9846 /* VEX_LEN_0F93_P_3 */
9848 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0
) },
9851 /* VEX_LEN_0F98_P_0 */
9853 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9856 /* VEX_LEN_0F98_P_2 */
9858 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0
) },
9861 /* VEX_LEN_0F99_P_0 */
9863 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0
) },
9866 /* VEX_LEN_0F99_P_2 */
9868 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0
) },
9871 /* VEX_LEN_0FAE_R_2_M_0 */
9873 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9876 /* VEX_LEN_0FAE_R_3_M_0 */
9878 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9881 /* VEX_LEN_0FC2_P_1 */
9883 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9884 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9887 /* VEX_LEN_0FC2_P_3 */
9889 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9890 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9893 /* VEX_LEN_0FC4_P_2 */
9895 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9898 /* VEX_LEN_0FC5_P_2 */
9900 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9903 /* VEX_LEN_0FD6_P_2 */
9905 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9906 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9909 /* VEX_LEN_0FF7_P_2 */
9911 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9914 /* VEX_LEN_0F3816_P_2 */
9917 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9920 /* VEX_LEN_0F3819_P_2 */
9923 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9926 /* VEX_LEN_0F381A_P_2_M_0 */
9929 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9932 /* VEX_LEN_0F3836_P_2 */
9935 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9938 /* VEX_LEN_0F3841_P_2 */
9940 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9943 /* VEX_LEN_0F385A_P_2_M_0 */
9946 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9949 /* VEX_LEN_0F38DB_P_2 */
9951 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9954 /* VEX_LEN_0F38F2_P_0 */
9956 { "andnS", { Gdq
, VexGdq
, Edq
}, 0 },
9959 /* VEX_LEN_0F38F3_R_1_P_0 */
9961 { "blsrS", { VexGdq
, Edq
}, 0 },
9964 /* VEX_LEN_0F38F3_R_2_P_0 */
9966 { "blsmskS", { VexGdq
, Edq
}, 0 },
9969 /* VEX_LEN_0F38F3_R_3_P_0 */
9971 { "blsiS", { VexGdq
, Edq
}, 0 },
9974 /* VEX_LEN_0F38F5_P_0 */
9976 { "bzhiS", { Gdq
, Edq
, VexGdq
}, 0 },
9979 /* VEX_LEN_0F38F5_P_1 */
9981 { "pextS", { Gdq
, VexGdq
, Edq
}, 0 },
9984 /* VEX_LEN_0F38F5_P_3 */
9986 { "pdepS", { Gdq
, VexGdq
, Edq
}, 0 },
9989 /* VEX_LEN_0F38F6_P_3 */
9991 { "mulxS", { Gdq
, VexGdq
, Edq
}, 0 },
9994 /* VEX_LEN_0F38F7_P_0 */
9996 { "bextrS", { Gdq
, Edq
, VexGdq
}, 0 },
9999 /* VEX_LEN_0F38F7_P_1 */
10001 { "sarxS", { Gdq
, Edq
, VexGdq
}, 0 },
10004 /* VEX_LEN_0F38F7_P_2 */
10006 { "shlxS", { Gdq
, Edq
, VexGdq
}, 0 },
10009 /* VEX_LEN_0F38F7_P_3 */
10011 { "shrxS", { Gdq
, Edq
, VexGdq
}, 0 },
10014 /* VEX_LEN_0F3A00_P_2 */
10017 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
10020 /* VEX_LEN_0F3A01_P_2 */
10023 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
10026 /* VEX_LEN_0F3A06_P_2 */
10029 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
10032 /* VEX_LEN_0F3A0A_P_2 */
10034 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10035 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
10038 /* VEX_LEN_0F3A0B_P_2 */
10040 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10041 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
10044 /* VEX_LEN_0F3A14_P_2 */
10046 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
10049 /* VEX_LEN_0F3A15_P_2 */
10051 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
10054 /* VEX_LEN_0F3A16_P_2 */
10056 { "vpextrK", { Edq
, XM
, Ib
}, 0 },
10059 /* VEX_LEN_0F3A17_P_2 */
10061 { "vextractps", { Edqd
, XM
, Ib
}, 0 },
10064 /* VEX_LEN_0F3A18_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
10070 /* VEX_LEN_0F3A19_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
10076 /* VEX_LEN_0F3A20_P_2 */
10078 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
10081 /* VEX_LEN_0F3A21_P_2 */
10083 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
10086 /* VEX_LEN_0F3A22_P_2 */
10088 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
}, 0 },
10091 /* VEX_LEN_0F3A30_P_2 */
10093 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
10096 /* VEX_LEN_0F3A31_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0
) },
10101 /* VEX_LEN_0F3A32_P_2 */
10103 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
10106 /* VEX_LEN_0F3A33_P_2 */
10108 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0
) },
10111 /* VEX_LEN_0F3A38_P_2 */
10114 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
10117 /* VEX_LEN_0F3A39_P_2 */
10120 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
10123 /* VEX_LEN_0F3A41_P_2 */
10125 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
10128 /* VEX_LEN_0F3A46_P_2 */
10131 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
10134 /* VEX_LEN_0F3A60_P_2 */
10136 { "vpcmpestrm", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10139 /* VEX_LEN_0F3A61_P_2 */
10141 { "vpcmpestri", { XM
, { PCMPESTR_Fixup
, x_mode
}, Ib
}, 0 },
10144 /* VEX_LEN_0F3A62_P_2 */
10146 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
10149 /* VEX_LEN_0F3A63_P_2 */
10151 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
10154 /* VEX_LEN_0F3A6A_P_2 */
10156 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10159 /* VEX_LEN_0F3A6B_P_2 */
10161 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10164 /* VEX_LEN_0F3A6E_P_2 */
10166 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10169 /* VEX_LEN_0F3A6F_P_2 */
10171 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10174 /* VEX_LEN_0F3A7A_P_2 */
10176 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10179 /* VEX_LEN_0F3A7B_P_2 */
10181 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10184 /* VEX_LEN_0F3A7E_P_2 */
10186 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
}, 0 },
10189 /* VEX_LEN_0F3A7F_P_2 */
10191 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
}, 0 },
10194 /* VEX_LEN_0F3ADF_P_2 */
10196 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
10199 /* VEX_LEN_0F3AF0_P_3 */
10201 { "rorxS", { Gdq
, Edq
, Ib
}, 0 },
10204 /* VEX_LEN_0FXOP_08_CC */
10206 { "vpcomb", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10209 /* VEX_LEN_0FXOP_08_CD */
10211 { "vpcomw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10214 /* VEX_LEN_0FXOP_08_CE */
10216 { "vpcomd", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10219 /* VEX_LEN_0FXOP_08_CF */
10221 { "vpcomq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10224 /* VEX_LEN_0FXOP_08_EC */
10226 { "vpcomub", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10229 /* VEX_LEN_0FXOP_08_ED */
10231 { "vpcomuw", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10234 /* VEX_LEN_0FXOP_08_EE */
10236 { "vpcomud", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10239 /* VEX_LEN_0FXOP_08_EF */
10241 { "vpcomuq", { XM
, Vex128
, EXx
, VPCOM
}, 0 },
10244 /* VEX_LEN_0FXOP_09_80 */
10246 { "vfrczps", { XM
, EXxmm
}, 0 },
10247 { "vfrczps", { XM
, EXymmq
}, 0 },
10250 /* VEX_LEN_0FXOP_09_81 */
10252 { "vfrczpd", { XM
, EXxmm
}, 0 },
10253 { "vfrczpd", { XM
, EXymmq
}, 0 },
10257 static const struct dis386 vex_w_table
[][2] = {
10259 /* VEX_W_0F10_P_0 */
10260 { "vmovups", { XM
, EXx
}, 0 },
10263 /* VEX_W_0F10_P_1 */
10264 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
}, 0 },
10267 /* VEX_W_0F10_P_2 */
10268 { "vmovupd", { XM
, EXx
}, 0 },
10271 /* VEX_W_0F10_P_3 */
10272 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
}, 0 },
10275 /* VEX_W_0F11_P_0 */
10276 { "vmovups", { EXxS
, XM
}, 0 },
10279 /* VEX_W_0F11_P_1 */
10280 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
}, 0 },
10283 /* VEX_W_0F11_P_2 */
10284 { "vmovupd", { EXxS
, XM
}, 0 },
10287 /* VEX_W_0F11_P_3 */
10288 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
}, 0 },
10291 /* VEX_W_0F12_P_0_M_0 */
10292 { "vmovlps", { XM
, Vex128
, EXq
}, 0 },
10295 /* VEX_W_0F12_P_0_M_1 */
10296 { "vmovhlps", { XM
, Vex128
, EXq
}, 0 },
10299 /* VEX_W_0F12_P_1 */
10300 { "vmovsldup", { XM
, EXx
}, 0 },
10303 /* VEX_W_0F12_P_2 */
10304 { "vmovlpd", { XM
, Vex128
, EXq
}, 0 },
10307 /* VEX_W_0F12_P_3 */
10308 { "vmovddup", { XM
, EXymmq
}, 0 },
10311 /* VEX_W_0F13_M_0 */
10312 { "vmovlpX", { EXq
, XM
}, 0 },
10316 { "vunpcklpX", { XM
, Vex
, EXx
}, 0 },
10320 { "vunpckhpX", { XM
, Vex
, EXx
}, 0 },
10323 /* VEX_W_0F16_P_0_M_0 */
10324 { "vmovhps", { XM
, Vex128
, EXq
}, 0 },
10327 /* VEX_W_0F16_P_0_M_1 */
10328 { "vmovlhps", { XM
, Vex128
, EXq
}, 0 },
10331 /* VEX_W_0F16_P_1 */
10332 { "vmovshdup", { XM
, EXx
}, 0 },
10335 /* VEX_W_0F16_P_2 */
10336 { "vmovhpd", { XM
, Vex128
, EXq
}, 0 },
10339 /* VEX_W_0F17_M_0 */
10340 { "vmovhpX", { EXq
, XM
}, 0 },
10344 { "vmovapX", { XM
, EXx
}, 0 },
10348 { "vmovapX", { EXxS
, XM
}, 0 },
10351 /* VEX_W_0F2B_M_0 */
10352 { "vmovntpX", { Mx
, XM
}, 0 },
10355 /* VEX_W_0F2E_P_0 */
10356 { "vucomiss", { XMScalar
, EXdScalar
}, 0 },
10359 /* VEX_W_0F2E_P_2 */
10360 { "vucomisd", { XMScalar
, EXqScalar
}, 0 },
10363 /* VEX_W_0F2F_P_0 */
10364 { "vcomiss", { XMScalar
, EXdScalar
}, 0 },
10367 /* VEX_W_0F2F_P_2 */
10368 { "vcomisd", { XMScalar
, EXqScalar
}, 0 },
10371 /* VEX_W_0F41_P_0_LEN_1 */
10372 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1
) },
10373 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1
) },
10376 /* VEX_W_0F41_P_2_LEN_1 */
10377 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1
) },
10378 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1
) }
10381 /* VEX_W_0F42_P_0_LEN_1 */
10382 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1
) },
10383 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1
) },
10386 /* VEX_W_0F42_P_2_LEN_1 */
10387 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1
) },
10388 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1
) },
10391 /* VEX_W_0F44_P_0_LEN_0 */
10392 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1
) },
10393 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1
) },
10396 /* VEX_W_0F44_P_2_LEN_0 */
10397 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1
) },
10398 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1
) },
10401 /* VEX_W_0F45_P_0_LEN_1 */
10402 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1
) },
10403 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1
) },
10406 /* VEX_W_0F45_P_2_LEN_1 */
10407 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1
) },
10408 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1
) },
10411 /* VEX_W_0F46_P_0_LEN_1 */
10412 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1
) },
10413 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1
) },
10416 /* VEX_W_0F46_P_2_LEN_1 */
10417 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1
) },
10418 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1
) },
10421 /* VEX_W_0F47_P_0_LEN_1 */
10422 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1
) },
10423 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1
) },
10426 /* VEX_W_0F47_P_2_LEN_1 */
10427 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1
) },
10428 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1
) },
10431 /* VEX_W_0F4A_P_0_LEN_1 */
10432 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1
) },
10433 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1
) },
10436 /* VEX_W_0F4A_P_2_LEN_1 */
10437 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1
) },
10438 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1
) },
10441 /* VEX_W_0F4B_P_0_LEN_1 */
10442 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1
) },
10443 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1
) },
10446 /* VEX_W_0F4B_P_2_LEN_1 */
10447 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1
) },
10450 /* VEX_W_0F50_M_0 */
10451 { "vmovmskpX", { Gdq
, XS
}, 0 },
10454 /* VEX_W_0F51_P_0 */
10455 { "vsqrtps", { XM
, EXx
}, 0 },
10458 /* VEX_W_0F51_P_1 */
10459 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10462 /* VEX_W_0F51_P_2 */
10463 { "vsqrtpd", { XM
, EXx
}, 0 },
10466 /* VEX_W_0F51_P_3 */
10467 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10470 /* VEX_W_0F52_P_0 */
10471 { "vrsqrtps", { XM
, EXx
}, 0 },
10474 /* VEX_W_0F52_P_1 */
10475 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10478 /* VEX_W_0F53_P_0 */
10479 { "vrcpps", { XM
, EXx
}, 0 },
10482 /* VEX_W_0F53_P_1 */
10483 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10486 /* VEX_W_0F58_P_0 */
10487 { "vaddps", { XM
, Vex
, EXx
}, 0 },
10490 /* VEX_W_0F58_P_1 */
10491 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10494 /* VEX_W_0F58_P_2 */
10495 { "vaddpd", { XM
, Vex
, EXx
}, 0 },
10498 /* VEX_W_0F58_P_3 */
10499 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10502 /* VEX_W_0F59_P_0 */
10503 { "vmulps", { XM
, Vex
, EXx
}, 0 },
10506 /* VEX_W_0F59_P_1 */
10507 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10510 /* VEX_W_0F59_P_2 */
10511 { "vmulpd", { XM
, Vex
, EXx
}, 0 },
10514 /* VEX_W_0F59_P_3 */
10515 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10518 /* VEX_W_0F5A_P_0 */
10519 { "vcvtps2pd", { XM
, EXxmmq
}, 0 },
10522 /* VEX_W_0F5A_P_1 */
10523 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10526 /* VEX_W_0F5A_P_3 */
10527 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10530 /* VEX_W_0F5B_P_0 */
10531 { "vcvtdq2ps", { XM
, EXx
}, 0 },
10534 /* VEX_W_0F5B_P_1 */
10535 { "vcvttps2dq", { XM
, EXx
}, 0 },
10538 /* VEX_W_0F5B_P_2 */
10539 { "vcvtps2dq", { XM
, EXx
}, 0 },
10542 /* VEX_W_0F5C_P_0 */
10543 { "vsubps", { XM
, Vex
, EXx
}, 0 },
10546 /* VEX_W_0F5C_P_1 */
10547 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10550 /* VEX_W_0F5C_P_2 */
10551 { "vsubpd", { XM
, Vex
, EXx
}, 0 },
10554 /* VEX_W_0F5C_P_3 */
10555 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10558 /* VEX_W_0F5D_P_0 */
10559 { "vminps", { XM
, Vex
, EXx
}, 0 },
10562 /* VEX_W_0F5D_P_1 */
10563 { "vminss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10566 /* VEX_W_0F5D_P_2 */
10567 { "vminpd", { XM
, Vex
, EXx
}, 0 },
10570 /* VEX_W_0F5D_P_3 */
10571 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10574 /* VEX_W_0F5E_P_0 */
10575 { "vdivps", { XM
, Vex
, EXx
}, 0 },
10578 /* VEX_W_0F5E_P_1 */
10579 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10582 /* VEX_W_0F5E_P_2 */
10583 { "vdivpd", { XM
, Vex
, EXx
}, 0 },
10586 /* VEX_W_0F5E_P_3 */
10587 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10590 /* VEX_W_0F5F_P_0 */
10591 { "vmaxps", { XM
, Vex
, EXx
}, 0 },
10594 /* VEX_W_0F5F_P_1 */
10595 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
}, 0 },
10598 /* VEX_W_0F5F_P_2 */
10599 { "vmaxpd", { XM
, Vex
, EXx
}, 0 },
10602 /* VEX_W_0F5F_P_3 */
10603 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
}, 0 },
10606 /* VEX_W_0F60_P_2 */
10607 { "vpunpcklbw", { XM
, Vex
, EXx
}, 0 },
10610 /* VEX_W_0F61_P_2 */
10611 { "vpunpcklwd", { XM
, Vex
, EXx
}, 0 },
10614 /* VEX_W_0F62_P_2 */
10615 { "vpunpckldq", { XM
, Vex
, EXx
}, 0 },
10618 /* VEX_W_0F63_P_2 */
10619 { "vpacksswb", { XM
, Vex
, EXx
}, 0 },
10622 /* VEX_W_0F64_P_2 */
10623 { "vpcmpgtb", { XM
, Vex
, EXx
}, 0 },
10626 /* VEX_W_0F65_P_2 */
10627 { "vpcmpgtw", { XM
, Vex
, EXx
}, 0 },
10630 /* VEX_W_0F66_P_2 */
10631 { "vpcmpgtd", { XM
, Vex
, EXx
}, 0 },
10634 /* VEX_W_0F67_P_2 */
10635 { "vpackuswb", { XM
, Vex
, EXx
}, 0 },
10638 /* VEX_W_0F68_P_2 */
10639 { "vpunpckhbw", { XM
, Vex
, EXx
}, 0 },
10642 /* VEX_W_0F69_P_2 */
10643 { "vpunpckhwd", { XM
, Vex
, EXx
}, 0 },
10646 /* VEX_W_0F6A_P_2 */
10647 { "vpunpckhdq", { XM
, Vex
, EXx
}, 0 },
10650 /* VEX_W_0F6B_P_2 */
10651 { "vpackssdw", { XM
, Vex
, EXx
}, 0 },
10654 /* VEX_W_0F6C_P_2 */
10655 { "vpunpcklqdq", { XM
, Vex
, EXx
}, 0 },
10658 /* VEX_W_0F6D_P_2 */
10659 { "vpunpckhqdq", { XM
, Vex
, EXx
}, 0 },
10662 /* VEX_W_0F6F_P_1 */
10663 { "vmovdqu", { XM
, EXx
}, 0 },
10666 /* VEX_W_0F6F_P_2 */
10667 { "vmovdqa", { XM
, EXx
}, 0 },
10670 /* VEX_W_0F70_P_1 */
10671 { "vpshufhw", { XM
, EXx
, Ib
}, 0 },
10674 /* VEX_W_0F70_P_2 */
10675 { "vpshufd", { XM
, EXx
, Ib
}, 0 },
10678 /* VEX_W_0F70_P_3 */
10679 { "vpshuflw", { XM
, EXx
, Ib
}, 0 },
10682 /* VEX_W_0F71_R_2_P_2 */
10683 { "vpsrlw", { Vex
, XS
, Ib
}, 0 },
10686 /* VEX_W_0F71_R_4_P_2 */
10687 { "vpsraw", { Vex
, XS
, Ib
}, 0 },
10690 /* VEX_W_0F71_R_6_P_2 */
10691 { "vpsllw", { Vex
, XS
, Ib
}, 0 },
10694 /* VEX_W_0F72_R_2_P_2 */
10695 { "vpsrld", { Vex
, XS
, Ib
}, 0 },
10698 /* VEX_W_0F72_R_4_P_2 */
10699 { "vpsrad", { Vex
, XS
, Ib
}, 0 },
10702 /* VEX_W_0F72_R_6_P_2 */
10703 { "vpslld", { Vex
, XS
, Ib
}, 0 },
10706 /* VEX_W_0F73_R_2_P_2 */
10707 { "vpsrlq", { Vex
, XS
, Ib
}, 0 },
10710 /* VEX_W_0F73_R_3_P_2 */
10711 { "vpsrldq", { Vex
, XS
, Ib
}, 0 },
10714 /* VEX_W_0F73_R_6_P_2 */
10715 { "vpsllq", { Vex
, XS
, Ib
}, 0 },
10718 /* VEX_W_0F73_R_7_P_2 */
10719 { "vpslldq", { Vex
, XS
, Ib
}, 0 },
10722 /* VEX_W_0F74_P_2 */
10723 { "vpcmpeqb", { XM
, Vex
, EXx
}, 0 },
10726 /* VEX_W_0F75_P_2 */
10727 { "vpcmpeqw", { XM
, Vex
, EXx
}, 0 },
10730 /* VEX_W_0F76_P_2 */
10731 { "vpcmpeqd", { XM
, Vex
, EXx
}, 0 },
10734 /* VEX_W_0F77_P_0 */
10735 { "", { VZERO
}, 0 },
10738 /* VEX_W_0F7C_P_2 */
10739 { "vhaddpd", { XM
, Vex
, EXx
}, 0 },
10742 /* VEX_W_0F7C_P_3 */
10743 { "vhaddps", { XM
, Vex
, EXx
}, 0 },
10746 /* VEX_W_0F7D_P_2 */
10747 { "vhsubpd", { XM
, Vex
, EXx
}, 0 },
10750 /* VEX_W_0F7D_P_3 */
10751 { "vhsubps", { XM
, Vex
, EXx
}, 0 },
10754 /* VEX_W_0F7E_P_1 */
10755 { "vmovq", { XMScalar
, EXqScalar
}, 0 },
10758 /* VEX_W_0F7F_P_1 */
10759 { "vmovdqu", { EXxS
, XM
}, 0 },
10762 /* VEX_W_0F7F_P_2 */
10763 { "vmovdqa", { EXxS
, XM
}, 0 },
10766 /* VEX_W_0F90_P_0_LEN_0 */
10767 { "kmovw", { MaskG
, MaskE
}, 0 },
10768 { "kmovq", { MaskG
, MaskE
}, 0 },
10771 /* VEX_W_0F90_P_2_LEN_0 */
10772 { "kmovb", { MaskG
, MaskBDE
}, 0 },
10773 { "kmovd", { MaskG
, MaskBDE
}, 0 },
10776 /* VEX_W_0F91_P_0_LEN_0 */
10777 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0
) },
10778 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0
) },
10781 /* VEX_W_0F91_P_2_LEN_0 */
10782 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0
) },
10783 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0
) },
10786 /* VEX_W_0F92_P_0_LEN_0 */
10787 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0
) },
10790 /* VEX_W_0F92_P_2_LEN_0 */
10791 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0
) },
10794 /* VEX_W_0F92_P_3_LEN_0 */
10795 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0
) },
10796 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0
) },
10799 /* VEX_W_0F93_P_0_LEN_0 */
10800 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0
) },
10803 /* VEX_W_0F93_P_2_LEN_0 */
10804 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0
) },
10807 /* VEX_W_0F93_P_3_LEN_0 */
10808 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0
) },
10809 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0
) },
10812 /* VEX_W_0F98_P_0_LEN_0 */
10813 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0
) },
10814 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0
) },
10817 /* VEX_W_0F98_P_2_LEN_0 */
10818 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0
) },
10819 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0
) },
10822 /* VEX_W_0F99_P_0_LEN_0 */
10823 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0
) },
10824 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0
) },
10827 /* VEX_W_0F99_P_2_LEN_0 */
10828 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0
) },
10829 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0
) },
10832 /* VEX_W_0FAE_R_2_M_0 */
10833 { "vldmxcsr", { Md
}, 0 },
10836 /* VEX_W_0FAE_R_3_M_0 */
10837 { "vstmxcsr", { Md
}, 0 },
10840 /* VEX_W_0FC2_P_0 */
10841 { "vcmpps", { XM
, Vex
, EXx
, VCMP
}, 0 },
10844 /* VEX_W_0FC2_P_1 */
10845 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
}, 0 },
10848 /* VEX_W_0FC2_P_2 */
10849 { "vcmppd", { XM
, Vex
, EXx
, VCMP
}, 0 },
10852 /* VEX_W_0FC2_P_3 */
10853 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
}, 0 },
10856 /* VEX_W_0FC4_P_2 */
10857 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
}, 0 },
10860 /* VEX_W_0FC5_P_2 */
10861 { "vpextrw", { Gdq
, XS
, Ib
}, 0 },
10864 /* VEX_W_0FD0_P_2 */
10865 { "vaddsubpd", { XM
, Vex
, EXx
}, 0 },
10868 /* VEX_W_0FD0_P_3 */
10869 { "vaddsubps", { XM
, Vex
, EXx
}, 0 },
10872 /* VEX_W_0FD1_P_2 */
10873 { "vpsrlw", { XM
, Vex
, EXxmm
}, 0 },
10876 /* VEX_W_0FD2_P_2 */
10877 { "vpsrld", { XM
, Vex
, EXxmm
}, 0 },
10880 /* VEX_W_0FD3_P_2 */
10881 { "vpsrlq", { XM
, Vex
, EXxmm
}, 0 },
10884 /* VEX_W_0FD4_P_2 */
10885 { "vpaddq", { XM
, Vex
, EXx
}, 0 },
10888 /* VEX_W_0FD5_P_2 */
10889 { "vpmullw", { XM
, Vex
, EXx
}, 0 },
10892 /* VEX_W_0FD6_P_2 */
10893 { "vmovq", { EXqScalarS
, XMScalar
}, 0 },
10896 /* VEX_W_0FD7_P_2_M_1 */
10897 { "vpmovmskb", { Gdq
, XS
}, 0 },
10900 /* VEX_W_0FD8_P_2 */
10901 { "vpsubusb", { XM
, Vex
, EXx
}, 0 },
10904 /* VEX_W_0FD9_P_2 */
10905 { "vpsubusw", { XM
, Vex
, EXx
}, 0 },
10908 /* VEX_W_0FDA_P_2 */
10909 { "vpminub", { XM
, Vex
, EXx
}, 0 },
10912 /* VEX_W_0FDB_P_2 */
10913 { "vpand", { XM
, Vex
, EXx
}, 0 },
10916 /* VEX_W_0FDC_P_2 */
10917 { "vpaddusb", { XM
, Vex
, EXx
}, 0 },
10920 /* VEX_W_0FDD_P_2 */
10921 { "vpaddusw", { XM
, Vex
, EXx
}, 0 },
10924 /* VEX_W_0FDE_P_2 */
10925 { "vpmaxub", { XM
, Vex
, EXx
}, 0 },
10928 /* VEX_W_0FDF_P_2 */
10929 { "vpandn", { XM
, Vex
, EXx
}, 0 },
10932 /* VEX_W_0FE0_P_2 */
10933 { "vpavgb", { XM
, Vex
, EXx
}, 0 },
10936 /* VEX_W_0FE1_P_2 */
10937 { "vpsraw", { XM
, Vex
, EXxmm
}, 0 },
10940 /* VEX_W_0FE2_P_2 */
10941 { "vpsrad", { XM
, Vex
, EXxmm
}, 0 },
10944 /* VEX_W_0FE3_P_2 */
10945 { "vpavgw", { XM
, Vex
, EXx
}, 0 },
10948 /* VEX_W_0FE4_P_2 */
10949 { "vpmulhuw", { XM
, Vex
, EXx
}, 0 },
10952 /* VEX_W_0FE5_P_2 */
10953 { "vpmulhw", { XM
, Vex
, EXx
}, 0 },
10956 /* VEX_W_0FE6_P_1 */
10957 { "vcvtdq2pd", { XM
, EXxmmq
}, 0 },
10960 /* VEX_W_0FE6_P_2 */
10961 { "vcvttpd2dq%XY", { XMM
, EXx
}, 0 },
10964 /* VEX_W_0FE6_P_3 */
10965 { "vcvtpd2dq%XY", { XMM
, EXx
}, 0 },
10968 /* VEX_W_0FE7_P_2_M_0 */
10969 { "vmovntdq", { Mx
, XM
}, 0 },
10972 /* VEX_W_0FE8_P_2 */
10973 { "vpsubsb", { XM
, Vex
, EXx
}, 0 },
10976 /* VEX_W_0FE9_P_2 */
10977 { "vpsubsw", { XM
, Vex
, EXx
}, 0 },
10980 /* VEX_W_0FEA_P_2 */
10981 { "vpminsw", { XM
, Vex
, EXx
}, 0 },
10984 /* VEX_W_0FEB_P_2 */
10985 { "vpor", { XM
, Vex
, EXx
}, 0 },
10988 /* VEX_W_0FEC_P_2 */
10989 { "vpaddsb", { XM
, Vex
, EXx
}, 0 },
10992 /* VEX_W_0FED_P_2 */
10993 { "vpaddsw", { XM
, Vex
, EXx
}, 0 },
10996 /* VEX_W_0FEE_P_2 */
10997 { "vpmaxsw", { XM
, Vex
, EXx
}, 0 },
11000 /* VEX_W_0FEF_P_2 */
11001 { "vpxor", { XM
, Vex
, EXx
}, 0 },
11004 /* VEX_W_0FF0_P_3_M_0 */
11005 { "vlddqu", { XM
, M
}, 0 },
11008 /* VEX_W_0FF1_P_2 */
11009 { "vpsllw", { XM
, Vex
, EXxmm
}, 0 },
11012 /* VEX_W_0FF2_P_2 */
11013 { "vpslld", { XM
, Vex
, EXxmm
}, 0 },
11016 /* VEX_W_0FF3_P_2 */
11017 { "vpsllq", { XM
, Vex
, EXxmm
}, 0 },
11020 /* VEX_W_0FF4_P_2 */
11021 { "vpmuludq", { XM
, Vex
, EXx
}, 0 },
11024 /* VEX_W_0FF5_P_2 */
11025 { "vpmaddwd", { XM
, Vex
, EXx
}, 0 },
11028 /* VEX_W_0FF6_P_2 */
11029 { "vpsadbw", { XM
, Vex
, EXx
}, 0 },
11032 /* VEX_W_0FF7_P_2 */
11033 { "vmaskmovdqu", { XM
, XS
}, 0 },
11036 /* VEX_W_0FF8_P_2 */
11037 { "vpsubb", { XM
, Vex
, EXx
}, 0 },
11040 /* VEX_W_0FF9_P_2 */
11041 { "vpsubw", { XM
, Vex
, EXx
}, 0 },
11044 /* VEX_W_0FFA_P_2 */
11045 { "vpsubd", { XM
, Vex
, EXx
}, 0 },
11048 /* VEX_W_0FFB_P_2 */
11049 { "vpsubq", { XM
, Vex
, EXx
}, 0 },
11052 /* VEX_W_0FFC_P_2 */
11053 { "vpaddb", { XM
, Vex
, EXx
}, 0 },
11056 /* VEX_W_0FFD_P_2 */
11057 { "vpaddw", { XM
, Vex
, EXx
}, 0 },
11060 /* VEX_W_0FFE_P_2 */
11061 { "vpaddd", { XM
, Vex
, EXx
}, 0 },
11064 /* VEX_W_0F3800_P_2 */
11065 { "vpshufb", { XM
, Vex
, EXx
}, 0 },
11068 /* VEX_W_0F3801_P_2 */
11069 { "vphaddw", { XM
, Vex
, EXx
}, 0 },
11072 /* VEX_W_0F3802_P_2 */
11073 { "vphaddd", { XM
, Vex
, EXx
}, 0 },
11076 /* VEX_W_0F3803_P_2 */
11077 { "vphaddsw", { XM
, Vex
, EXx
}, 0 },
11080 /* VEX_W_0F3804_P_2 */
11081 { "vpmaddubsw", { XM
, Vex
, EXx
}, 0 },
11084 /* VEX_W_0F3805_P_2 */
11085 { "vphsubw", { XM
, Vex
, EXx
}, 0 },
11088 /* VEX_W_0F3806_P_2 */
11089 { "vphsubd", { XM
, Vex
, EXx
}, 0 },
11092 /* VEX_W_0F3807_P_2 */
11093 { "vphsubsw", { XM
, Vex
, EXx
}, 0 },
11096 /* VEX_W_0F3808_P_2 */
11097 { "vpsignb", { XM
, Vex
, EXx
}, 0 },
11100 /* VEX_W_0F3809_P_2 */
11101 { "vpsignw", { XM
, Vex
, EXx
}, 0 },
11104 /* VEX_W_0F380A_P_2 */
11105 { "vpsignd", { XM
, Vex
, EXx
}, 0 },
11108 /* VEX_W_0F380B_P_2 */
11109 { "vpmulhrsw", { XM
, Vex
, EXx
}, 0 },
11112 /* VEX_W_0F380C_P_2 */
11113 { "vpermilps", { XM
, Vex
, EXx
}, 0 },
11116 /* VEX_W_0F380D_P_2 */
11117 { "vpermilpd", { XM
, Vex
, EXx
}, 0 },
11120 /* VEX_W_0F380E_P_2 */
11121 { "vtestps", { XM
, EXx
}, 0 },
11124 /* VEX_W_0F380F_P_2 */
11125 { "vtestpd", { XM
, EXx
}, 0 },
11128 /* VEX_W_0F3816_P_2 */
11129 { "vpermps", { XM
, Vex
, EXx
}, 0 },
11132 /* VEX_W_0F3817_P_2 */
11133 { "vptest", { XM
, EXx
}, 0 },
11136 /* VEX_W_0F3818_P_2 */
11137 { "vbroadcastss", { XM
, EXxmm_md
}, 0 },
11140 /* VEX_W_0F3819_P_2 */
11141 { "vbroadcastsd", { XM
, EXxmm_mq
}, 0 },
11144 /* VEX_W_0F381A_P_2_M_0 */
11145 { "vbroadcastf128", { XM
, Mxmm
}, 0 },
11148 /* VEX_W_0F381C_P_2 */
11149 { "vpabsb", { XM
, EXx
}, 0 },
11152 /* VEX_W_0F381D_P_2 */
11153 { "vpabsw", { XM
, EXx
}, 0 },
11156 /* VEX_W_0F381E_P_2 */
11157 { "vpabsd", { XM
, EXx
}, 0 },
11160 /* VEX_W_0F3820_P_2 */
11161 { "vpmovsxbw", { XM
, EXxmmq
}, 0 },
11164 /* VEX_W_0F3821_P_2 */
11165 { "vpmovsxbd", { XM
, EXxmmqd
}, 0 },
11168 /* VEX_W_0F3822_P_2 */
11169 { "vpmovsxbq", { XM
, EXxmmdw
}, 0 },
11172 /* VEX_W_0F3823_P_2 */
11173 { "vpmovsxwd", { XM
, EXxmmq
}, 0 },
11176 /* VEX_W_0F3824_P_2 */
11177 { "vpmovsxwq", { XM
, EXxmmqd
}, 0 },
11180 /* VEX_W_0F3825_P_2 */
11181 { "vpmovsxdq", { XM
, EXxmmq
}, 0 },
11184 /* VEX_W_0F3828_P_2 */
11185 { "vpmuldq", { XM
, Vex
, EXx
}, 0 },
11188 /* VEX_W_0F3829_P_2 */
11189 { "vpcmpeqq", { XM
, Vex
, EXx
}, 0 },
11192 /* VEX_W_0F382A_P_2_M_0 */
11193 { "vmovntdqa", { XM
, Mx
}, 0 },
11196 /* VEX_W_0F382B_P_2 */
11197 { "vpackusdw", { XM
, Vex
, EXx
}, 0 },
11200 /* VEX_W_0F382C_P_2_M_0 */
11201 { "vmaskmovps", { XM
, Vex
, Mx
}, 0 },
11204 /* VEX_W_0F382D_P_2_M_0 */
11205 { "vmaskmovpd", { XM
, Vex
, Mx
}, 0 },
11208 /* VEX_W_0F382E_P_2_M_0 */
11209 { "vmaskmovps", { Mx
, Vex
, XM
}, 0 },
11212 /* VEX_W_0F382F_P_2_M_0 */
11213 { "vmaskmovpd", { Mx
, Vex
, XM
}, 0 },
11216 /* VEX_W_0F3830_P_2 */
11217 { "vpmovzxbw", { XM
, EXxmmq
}, 0 },
11220 /* VEX_W_0F3831_P_2 */
11221 { "vpmovzxbd", { XM
, EXxmmqd
}, 0 },
11224 /* VEX_W_0F3832_P_2 */
11225 { "vpmovzxbq", { XM
, EXxmmdw
}, 0 },
11228 /* VEX_W_0F3833_P_2 */
11229 { "vpmovzxwd", { XM
, EXxmmq
}, 0 },
11232 /* VEX_W_0F3834_P_2 */
11233 { "vpmovzxwq", { XM
, EXxmmqd
}, 0 },
11236 /* VEX_W_0F3835_P_2 */
11237 { "vpmovzxdq", { XM
, EXxmmq
}, 0 },
11240 /* VEX_W_0F3836_P_2 */
11241 { "vpermd", { XM
, Vex
, EXx
}, 0 },
11244 /* VEX_W_0F3837_P_2 */
11245 { "vpcmpgtq", { XM
, Vex
, EXx
}, 0 },
11248 /* VEX_W_0F3838_P_2 */
11249 { "vpminsb", { XM
, Vex
, EXx
}, 0 },
11252 /* VEX_W_0F3839_P_2 */
11253 { "vpminsd", { XM
, Vex
, EXx
}, 0 },
11256 /* VEX_W_0F383A_P_2 */
11257 { "vpminuw", { XM
, Vex
, EXx
}, 0 },
11260 /* VEX_W_0F383B_P_2 */
11261 { "vpminud", { XM
, Vex
, EXx
}, 0 },
11264 /* VEX_W_0F383C_P_2 */
11265 { "vpmaxsb", { XM
, Vex
, EXx
}, 0 },
11268 /* VEX_W_0F383D_P_2 */
11269 { "vpmaxsd", { XM
, Vex
, EXx
}, 0 },
11272 /* VEX_W_0F383E_P_2 */
11273 { "vpmaxuw", { XM
, Vex
, EXx
}, 0 },
11276 /* VEX_W_0F383F_P_2 */
11277 { "vpmaxud", { XM
, Vex
, EXx
}, 0 },
11280 /* VEX_W_0F3840_P_2 */
11281 { "vpmulld", { XM
, Vex
, EXx
}, 0 },
11284 /* VEX_W_0F3841_P_2 */
11285 { "vphminposuw", { XM
, EXx
}, 0 },
11288 /* VEX_W_0F3846_P_2 */
11289 { "vpsravd", { XM
, Vex
, EXx
}, 0 },
11292 /* VEX_W_0F3858_P_2 */
11293 { "vpbroadcastd", { XM
, EXxmm_md
}, 0 },
11296 /* VEX_W_0F3859_P_2 */
11297 { "vpbroadcastq", { XM
, EXxmm_mq
}, 0 },
11300 /* VEX_W_0F385A_P_2_M_0 */
11301 { "vbroadcasti128", { XM
, Mxmm
}, 0 },
11304 /* VEX_W_0F3878_P_2 */
11305 { "vpbroadcastb", { XM
, EXxmm_mb
}, 0 },
11308 /* VEX_W_0F3879_P_2 */
11309 { "vpbroadcastw", { XM
, EXxmm_mw
}, 0 },
11312 /* VEX_W_0F38CF_P_2 */
11313 { "vgf2p8mulb", { XM
, Vex
, EXx
}, 0 },
11316 /* VEX_W_0F38DB_P_2 */
11317 { "vaesimc", { XM
, EXx
}, 0 },
11320 /* VEX_W_0F3A00_P_2 */
11322 { "vpermq", { XM
, EXx
, Ib
}, 0 },
11325 /* VEX_W_0F3A01_P_2 */
11327 { "vpermpd", { XM
, EXx
, Ib
}, 0 },
11330 /* VEX_W_0F3A02_P_2 */
11331 { "vpblendd", { XM
, Vex
, EXx
, Ib
}, 0 },
11334 /* VEX_W_0F3A04_P_2 */
11335 { "vpermilps", { XM
, EXx
, Ib
}, 0 },
11338 /* VEX_W_0F3A05_P_2 */
11339 { "vpermilpd", { XM
, EXx
, Ib
}, 0 },
11342 /* VEX_W_0F3A06_P_2 */
11343 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11346 /* VEX_W_0F3A08_P_2 */
11347 { "vroundps", { XM
, EXx
, Ib
}, 0 },
11350 /* VEX_W_0F3A09_P_2 */
11351 { "vroundpd", { XM
, EXx
, Ib
}, 0 },
11354 /* VEX_W_0F3A0A_P_2 */
11355 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
}, 0 },
11358 /* VEX_W_0F3A0B_P_2 */
11359 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
}, 0 },
11362 /* VEX_W_0F3A0C_P_2 */
11363 { "vblendps", { XM
, Vex
, EXx
, Ib
}, 0 },
11366 /* VEX_W_0F3A0D_P_2 */
11367 { "vblendpd", { XM
, Vex
, EXx
, Ib
}, 0 },
11370 /* VEX_W_0F3A0E_P_2 */
11371 { "vpblendw", { XM
, Vex
, EXx
, Ib
}, 0 },
11374 /* VEX_W_0F3A0F_P_2 */
11375 { "vpalignr", { XM
, Vex
, EXx
, Ib
}, 0 },
11378 /* VEX_W_0F3A14_P_2 */
11379 { "vpextrb", { Edqb
, XM
, Ib
}, 0 },
11382 /* VEX_W_0F3A15_P_2 */
11383 { "vpextrw", { Edqw
, XM
, Ib
}, 0 },
11386 /* VEX_W_0F3A18_P_2 */
11387 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11390 /* VEX_W_0F3A19_P_2 */
11391 { "vextractf128", { EXxmm
, XM
, Ib
}, 0 },
11394 /* VEX_W_0F3A20_P_2 */
11395 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
}, 0 },
11398 /* VEX_W_0F3A21_P_2 */
11399 { "vinsertps", { XM
, Vex128
, EXd
, Ib
}, 0 },
11402 /* VEX_W_0F3A30_P_2_LEN_0 */
11403 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0
) },
11404 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0
) },
11407 /* VEX_W_0F3A31_P_2_LEN_0 */
11408 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0
) },
11409 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0
) },
11412 /* VEX_W_0F3A32_P_2_LEN_0 */
11413 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0
) },
11414 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0
) },
11417 /* VEX_W_0F3A33_P_2_LEN_0 */
11418 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0
) },
11419 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0
) },
11422 /* VEX_W_0F3A38_P_2 */
11423 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
}, 0 },
11426 /* VEX_W_0F3A39_P_2 */
11427 { "vextracti128", { EXxmm
, XM
, Ib
}, 0 },
11430 /* VEX_W_0F3A40_P_2 */
11431 { "vdpps", { XM
, Vex
, EXx
, Ib
}, 0 },
11434 /* VEX_W_0F3A41_P_2 */
11435 { "vdppd", { XM
, Vex128
, EXx
, Ib
}, 0 },
11438 /* VEX_W_0F3A42_P_2 */
11439 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
}, 0 },
11442 /* VEX_W_0F3A46_P_2 */
11443 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
}, 0 },
11446 /* VEX_W_0F3A48_P_2 */
11447 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11448 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11451 /* VEX_W_0F3A49_P_2 */
11452 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11453 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
}, 0 },
11456 /* VEX_W_0F3A4A_P_2 */
11457 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11460 /* VEX_W_0F3A4B_P_2 */
11461 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11464 /* VEX_W_0F3A4C_P_2 */
11465 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
}, 0 },
11468 /* VEX_W_0F3A62_P_2 */
11469 { "vpcmpistrm", { XM
, EXx
, Ib
}, 0 },
11472 /* VEX_W_0F3A63_P_2 */
11473 { "vpcmpistri", { XM
, EXx
, Ib
}, 0 },
11476 /* VEX_W_0F3ACE_P_2 */
11478 { "vgf2p8affineqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11481 /* VEX_W_0F3ACF_P_2 */
11483 { "vgf2p8affineinvqb", { XM
, Vex
, EXx
, Ib
}, 0 },
11486 /* VEX_W_0F3ADF_P_2 */
11487 { "vaeskeygenassist", { XM
, EXx
, Ib
}, 0 },
11489 #define NEED_VEX_W_TABLE
11490 #include "i386-dis-evex.h"
11491 #undef NEED_VEX_W_TABLE
11494 static const struct dis386 mod_table
[][2] = {
11497 { "leaS", { Gv
, M
}, 0 },
11502 { RM_TABLE (RM_C6_REG_7
) },
11507 { RM_TABLE (RM_C7_REG_7
) },
11511 { "Jcall^", { indirEp
}, 0 },
11515 { "Jjmp^", { indirEp
}, 0 },
11518 /* MOD_0F01_REG_0 */
11519 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11520 { RM_TABLE (RM_0F01_REG_0
) },
11523 /* MOD_0F01_REG_1 */
11524 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11525 { RM_TABLE (RM_0F01_REG_1
) },
11528 /* MOD_0F01_REG_2 */
11529 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11530 { RM_TABLE (RM_0F01_REG_2
) },
11533 /* MOD_0F01_REG_3 */
11534 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11535 { RM_TABLE (RM_0F01_REG_3
) },
11538 /* MOD_0F01_REG_5 */
11539 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5
) },
11540 { RM_TABLE (RM_0F01_REG_5
) },
11543 /* MOD_0F01_REG_7 */
11544 { "invlpg", { Mb
}, 0 },
11545 { RM_TABLE (RM_0F01_REG_7
) },
11548 /* MOD_0F12_PREFIX_0 */
11549 { "movlps", { XM
, EXq
}, PREFIX_OPCODE
},
11550 { "movhlps", { XM
, EXq
}, PREFIX_OPCODE
},
11554 { "movlpX", { EXq
, XM
}, PREFIX_OPCODE
},
11557 /* MOD_0F16_PREFIX_0 */
11558 { "movhps", { XM
, EXq
}, 0 },
11559 { "movlhps", { XM
, EXq
}, 0 },
11563 { "movhpX", { EXq
, XM
}, PREFIX_OPCODE
},
11566 /* MOD_0F18_REG_0 */
11567 { "prefetchnta", { Mb
}, 0 },
11570 /* MOD_0F18_REG_1 */
11571 { "prefetcht0", { Mb
}, 0 },
11574 /* MOD_0F18_REG_2 */
11575 { "prefetcht1", { Mb
}, 0 },
11578 /* MOD_0F18_REG_3 */
11579 { "prefetcht2", { Mb
}, 0 },
11582 /* MOD_0F18_REG_4 */
11583 { "nop/reserved", { Mb
}, 0 },
11586 /* MOD_0F18_REG_5 */
11587 { "nop/reserved", { Mb
}, 0 },
11590 /* MOD_0F18_REG_6 */
11591 { "nop/reserved", { Mb
}, 0 },
11594 /* MOD_0F18_REG_7 */
11595 { "nop/reserved", { Mb
}, 0 },
11598 /* MOD_0F1A_PREFIX_0 */
11599 { "bndldx", { Gbnd
, Ev_bnd
}, 0 },
11600 { "nopQ", { Ev
}, 0 },
11603 /* MOD_0F1B_PREFIX_0 */
11604 { "bndstx", { Ev_bnd
, Gbnd
}, 0 },
11605 { "nopQ", { Ev
}, 0 },
11608 /* MOD_0F1B_PREFIX_1 */
11609 { "bndmk", { Gbnd
, Ev_bnd
}, 0 },
11610 { "nopQ", { Ev
}, 0 },
11613 /* MOD_0F1E_PREFIX_1 */
11614 { "nopQ", { Ev
}, 0 },
11615 { REG_TABLE (REG_0F1E_MOD_3
) },
11620 { "movL", { Rd
, Td
}, 0 },
11625 { "movL", { Td
, Rd
}, 0 },
11628 /* MOD_0F2B_PREFIX_0 */
11629 {"movntps", { Mx
, XM
}, PREFIX_OPCODE
},
11632 /* MOD_0F2B_PREFIX_1 */
11633 {"movntss", { Md
, XM
}, PREFIX_OPCODE
},
11636 /* MOD_0F2B_PREFIX_2 */
11637 {"movntpd", { Mx
, XM
}, PREFIX_OPCODE
},
11640 /* MOD_0F2B_PREFIX_3 */
11641 {"movntsd", { Mq
, XM
}, PREFIX_OPCODE
},
11646 { "movmskpX", { Gdq
, XS
}, PREFIX_OPCODE
},
11649 /* MOD_0F71_REG_2 */
11651 { "psrlw", { MS
, Ib
}, 0 },
11654 /* MOD_0F71_REG_4 */
11656 { "psraw", { MS
, Ib
}, 0 },
11659 /* MOD_0F71_REG_6 */
11661 { "psllw", { MS
, Ib
}, 0 },
11664 /* MOD_0F72_REG_2 */
11666 { "psrld", { MS
, Ib
}, 0 },
11669 /* MOD_0F72_REG_4 */
11671 { "psrad", { MS
, Ib
}, 0 },
11674 /* MOD_0F72_REG_6 */
11676 { "pslld", { MS
, Ib
}, 0 },
11679 /* MOD_0F73_REG_2 */
11681 { "psrlq", { MS
, Ib
}, 0 },
11684 /* MOD_0F73_REG_3 */
11686 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11689 /* MOD_0F73_REG_6 */
11691 { "psllq", { MS
, Ib
}, 0 },
11694 /* MOD_0F73_REG_7 */
11696 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11699 /* MOD_0FAE_REG_0 */
11700 { "fxsave", { FXSAVE
}, 0 },
11701 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11704 /* MOD_0FAE_REG_1 */
11705 { "fxrstor", { FXSAVE
}, 0 },
11706 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11709 /* MOD_0FAE_REG_2 */
11710 { "ldmxcsr", { Md
}, 0 },
11711 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11714 /* MOD_0FAE_REG_3 */
11715 { "stmxcsr", { Md
}, 0 },
11716 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11719 /* MOD_0FAE_REG_4 */
11720 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4
) },
11721 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4
) },
11724 /* MOD_0FAE_REG_5 */
11725 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5
) },
11726 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5
) },
11729 /* MOD_0FAE_REG_6 */
11730 { PREFIX_TABLE (PREFIX_0FAE_REG_6
) },
11731 { RM_TABLE (RM_0FAE_REG_6
) },
11734 /* MOD_0FAE_REG_7 */
11735 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11736 { RM_TABLE (RM_0FAE_REG_7
) },
11740 { "lssS", { Gv
, Mp
}, 0 },
11744 { "lfsS", { Gv
, Mp
}, 0 },
11748 { "lgsS", { Gv
, Mp
}, 0 },
11752 { PREFIX_TABLE (PREFIX_MOD_0_0FC3
) },
11755 /* MOD_0FC7_REG_3 */
11756 { "xrstors", { FXSAVE
}, 0 },
11759 /* MOD_0FC7_REG_4 */
11760 { "xsavec", { FXSAVE
}, 0 },
11763 /* MOD_0FC7_REG_5 */
11764 { "xsaves", { FXSAVE
}, 0 },
11767 /* MOD_0FC7_REG_6 */
11768 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6
) },
11769 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6
) }
11772 /* MOD_0FC7_REG_7 */
11773 { "vmptrst", { Mq
}, 0 },
11774 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7
) }
11779 { "pmovmskb", { Gdq
, MS
}, 0 },
11782 /* MOD_0FE7_PREFIX_2 */
11783 { "movntdq", { Mx
, XM
}, 0 },
11786 /* MOD_0FF0_PREFIX_3 */
11787 { "lddqu", { XM
, M
}, 0 },
11790 /* MOD_0F382A_PREFIX_2 */
11791 { "movntdqa", { XM
, Mx
}, 0 },
11794 /* MOD_0F38F5_PREFIX_2 */
11795 { "wrussK", { M
, Gdq
}, PREFIX_OPCODE
},
11798 /* MOD_0F38F6_PREFIX_0 */
11799 { "wrssK", { M
, Gdq
}, PREFIX_OPCODE
},
11803 { "bound{S|}", { Gv
, Ma
}, 0 },
11804 { EVEX_TABLE (EVEX_0F
) },
11808 { "lesS", { Gv
, Mp
}, 0 },
11809 { VEX_C4_TABLE (VEX_0F
) },
11813 { "ldsS", { Gv
, Mp
}, 0 },
11814 { VEX_C5_TABLE (VEX_0F
) },
11817 /* MOD_VEX_0F12_PREFIX_0 */
11818 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11819 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11823 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11826 /* MOD_VEX_0F16_PREFIX_0 */
11827 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11828 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11832 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11836 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11839 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11841 { "kandw", { MaskG
, MaskVex
, MaskR
}, 0 },
11844 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11846 { "kandq", { MaskG
, MaskVex
, MaskR
}, 0 },
11849 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11851 { "kandb", { MaskG
, MaskVex
, MaskR
}, 0 },
11854 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11856 { "kandd", { MaskG
, MaskVex
, MaskR
}, 0 },
11859 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11861 { "kandnw", { MaskG
, MaskVex
, MaskR
}, 0 },
11864 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11866 { "kandnq", { MaskG
, MaskVex
, MaskR
}, 0 },
11869 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11871 { "kandnb", { MaskG
, MaskVex
, MaskR
}, 0 },
11874 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11876 { "kandnd", { MaskG
, MaskVex
, MaskR
}, 0 },
11879 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11881 { "knotw", { MaskG
, MaskR
}, 0 },
11884 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11886 { "knotq", { MaskG
, MaskR
}, 0 },
11889 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11891 { "knotb", { MaskG
, MaskR
}, 0 },
11894 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11896 { "knotd", { MaskG
, MaskR
}, 0 },
11899 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11901 { "korw", { MaskG
, MaskVex
, MaskR
}, 0 },
11904 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11906 { "korq", { MaskG
, MaskVex
, MaskR
}, 0 },
11909 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11911 { "korb", { MaskG
, MaskVex
, MaskR
}, 0 },
11914 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11916 { "kord", { MaskG
, MaskVex
, MaskR
}, 0 },
11919 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11921 { "kxnorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11924 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11926 { "kxnorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11929 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11931 { "kxnorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11934 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11936 { "kxnord", { MaskG
, MaskVex
, MaskR
}, 0 },
11939 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11941 { "kxorw", { MaskG
, MaskVex
, MaskR
}, 0 },
11944 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11946 { "kxorq", { MaskG
, MaskVex
, MaskR
}, 0 },
11949 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11951 { "kxorb", { MaskG
, MaskVex
, MaskR
}, 0 },
11954 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11956 { "kxord", { MaskG
, MaskVex
, MaskR
}, 0 },
11959 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11961 { "kaddw", { MaskG
, MaskVex
, MaskR
}, 0 },
11964 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11966 { "kaddq", { MaskG
, MaskVex
, MaskR
}, 0 },
11969 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11971 { "kaddb", { MaskG
, MaskVex
, MaskR
}, 0 },
11974 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11976 { "kaddd", { MaskG
, MaskVex
, MaskR
}, 0 },
11979 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11981 { "kunpckwd", { MaskG
, MaskVex
, MaskR
}, 0 },
11984 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11986 { "kunpckdq", { MaskG
, MaskVex
, MaskR
}, 0 },
11989 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11991 { "kunpckbw", { MaskG
, MaskVex
, MaskR
}, 0 },
11996 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11999 /* MOD_VEX_0F71_REG_2 */
12001 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
12004 /* MOD_VEX_0F71_REG_4 */
12006 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
12009 /* MOD_VEX_0F71_REG_6 */
12011 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
12014 /* MOD_VEX_0F72_REG_2 */
12016 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
12019 /* MOD_VEX_0F72_REG_4 */
12021 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
12024 /* MOD_VEX_0F72_REG_6 */
12026 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
12029 /* MOD_VEX_0F73_REG_2 */
12031 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
12034 /* MOD_VEX_0F73_REG_3 */
12036 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
12039 /* MOD_VEX_0F73_REG_6 */
12041 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
12044 /* MOD_VEX_0F73_REG_7 */
12046 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
12049 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12050 { "kmovw", { Ew
, MaskG
}, 0 },
12054 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12055 { "kmovq", { Eq
, MaskG
}, 0 },
12059 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12060 { "kmovb", { Eb
, MaskG
}, 0 },
12064 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12065 { "kmovd", { Ed
, MaskG
}, 0 },
12069 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12071 { "kmovw", { MaskG
, Rdq
}, 0 },
12074 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12076 { "kmovb", { MaskG
, Rdq
}, 0 },
12079 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12081 { "kmovd", { MaskG
, Rdq
}, 0 },
12084 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12086 { "kmovq", { MaskG
, Rdq
}, 0 },
12089 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12091 { "kmovw", { Gdq
, MaskR
}, 0 },
12094 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12096 { "kmovb", { Gdq
, MaskR
}, 0 },
12099 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12101 { "kmovd", { Gdq
, MaskR
}, 0 },
12104 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12106 { "kmovq", { Gdq
, MaskR
}, 0 },
12109 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12111 { "kortestw", { MaskG
, MaskR
}, 0 },
12114 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12116 { "kortestq", { MaskG
, MaskR
}, 0 },
12119 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12121 { "kortestb", { MaskG
, MaskR
}, 0 },
12124 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12126 { "kortestd", { MaskG
, MaskR
}, 0 },
12129 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12131 { "ktestw", { MaskG
, MaskR
}, 0 },
12134 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12136 { "ktestq", { MaskG
, MaskR
}, 0 },
12139 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12141 { "ktestb", { MaskG
, MaskR
}, 0 },
12144 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12146 { "ktestd", { MaskG
, MaskR
}, 0 },
12149 /* MOD_VEX_0FAE_REG_2 */
12150 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
12153 /* MOD_VEX_0FAE_REG_3 */
12154 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
12157 /* MOD_VEX_0FD7_PREFIX_2 */
12159 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
12162 /* MOD_VEX_0FE7_PREFIX_2 */
12163 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
12166 /* MOD_VEX_0FF0_PREFIX_3 */
12167 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
12170 /* MOD_VEX_0F381A_PREFIX_2 */
12171 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
12174 /* MOD_VEX_0F382A_PREFIX_2 */
12175 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
12178 /* MOD_VEX_0F382C_PREFIX_2 */
12179 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
12182 /* MOD_VEX_0F382D_PREFIX_2 */
12183 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
12186 /* MOD_VEX_0F382E_PREFIX_2 */
12187 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
12190 /* MOD_VEX_0F382F_PREFIX_2 */
12191 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
12194 /* MOD_VEX_0F385A_PREFIX_2 */
12195 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
12198 /* MOD_VEX_0F388C_PREFIX_2 */
12199 { "vpmaskmov%LW", { XM
, Vex
, Mx
}, 0 },
12202 /* MOD_VEX_0F388E_PREFIX_2 */
12203 { "vpmaskmov%LW", { Mx
, Vex
, XM
}, 0 },
12206 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12208 { "kshiftrb", { MaskG
, MaskR
, Ib
}, 0 },
12211 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12213 { "kshiftrw", { MaskG
, MaskR
, Ib
}, 0 },
12216 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12218 { "kshiftrd", { MaskG
, MaskR
, Ib
}, 0 },
12221 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12223 { "kshiftrq", { MaskG
, MaskR
, Ib
}, 0 },
12226 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12228 { "kshiftlb", { MaskG
, MaskR
, Ib
}, 0 },
12231 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12233 { "kshiftlw", { MaskG
, MaskR
, Ib
}, 0 },
12236 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12238 { "kshiftld", { MaskG
, MaskR
, Ib
}, 0 },
12241 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12243 { "kshiftlq", { MaskG
, MaskR
, Ib
}, 0 },
12245 #define NEED_MOD_TABLE
12246 #include "i386-dis-evex.h"
12247 #undef NEED_MOD_TABLE
12250 static const struct dis386 rm_table
[][8] = {
12253 { "xabort", { Skip_MODRM
, Ib
}, 0 },
12257 { "xbeginT", { Skip_MODRM
, Jv
}, 0 },
12260 /* RM_0F01_REG_0 */
12262 { "vmcall", { Skip_MODRM
}, 0 },
12263 { "vmlaunch", { Skip_MODRM
}, 0 },
12264 { "vmresume", { Skip_MODRM
}, 0 },
12265 { "vmxoff", { Skip_MODRM
}, 0 },
12266 { "pconfig", { Skip_MODRM
}, 0 },
12269 /* RM_0F01_REG_1 */
12270 { "monitor", { { OP_Monitor
, 0 } }, 0 },
12271 { "mwait", { { OP_Mwait
, 0 } }, 0 },
12272 { "clac", { Skip_MODRM
}, 0 },
12273 { "stac", { Skip_MODRM
}, 0 },
12277 { "encls", { Skip_MODRM
}, 0 },
12280 /* RM_0F01_REG_2 */
12281 { "xgetbv", { Skip_MODRM
}, 0 },
12282 { "xsetbv", { Skip_MODRM
}, 0 },
12285 { "vmfunc", { Skip_MODRM
}, 0 },
12286 { "xend", { Skip_MODRM
}, 0 },
12287 { "xtest", { Skip_MODRM
}, 0 },
12288 { "enclu", { Skip_MODRM
}, 0 },
12291 /* RM_0F01_REG_3 */
12292 { "vmrun", { Skip_MODRM
}, 0 },
12293 { "vmmcall", { Skip_MODRM
}, 0 },
12294 { "vmload", { Skip_MODRM
}, 0 },
12295 { "vmsave", { Skip_MODRM
}, 0 },
12296 { "stgi", { Skip_MODRM
}, 0 },
12297 { "clgi", { Skip_MODRM
}, 0 },
12298 { "skinit", { Skip_MODRM
}, 0 },
12299 { "invlpga", { Skip_MODRM
}, 0 },
12302 /* RM_0F01_REG_5 */
12303 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0
) },
12305 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2
) },
12309 { "rdpkru", { Skip_MODRM
}, 0 },
12310 { "wrpkru", { Skip_MODRM
}, 0 },
12313 /* RM_0F01_REG_7 */
12314 { "swapgs", { Skip_MODRM
}, 0 },
12315 { "rdtscp", { Skip_MODRM
}, 0 },
12316 { "monitorx", { { OP_Monitor
, 0 } }, 0 },
12317 { "mwaitx", { { OP_Mwaitx
, 0 } }, 0 },
12318 { "clzero", { Skip_MODRM
}, 0 },
12321 /* RM_0F1E_MOD_3_REG_7 */
12322 { "nopQ", { Ev
}, 0 },
12323 { "nopQ", { Ev
}, 0 },
12324 { "endbr64", { Skip_MODRM
}, PREFIX_OPCODE
},
12325 { "endbr32", { Skip_MODRM
}, PREFIX_OPCODE
},
12326 { "nopQ", { Ev
}, 0 },
12327 { "nopQ", { Ev
}, 0 },
12328 { "nopQ", { Ev
}, 0 },
12329 { "nopQ", { Ev
}, 0 },
12332 /* RM_0FAE_REG_6 */
12333 { "mfence", { Skip_MODRM
}, 0 },
12336 /* RM_0FAE_REG_7 */
12337 { "sfence", { Skip_MODRM
}, 0 },
12342 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12344 /* We use the high bit to indicate different name for the same
12346 #define REP_PREFIX (0xf3 | 0x100)
12347 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12348 #define XRELEASE_PREFIX (0xf3 | 0x400)
12349 #define BND_PREFIX (0xf2 | 0x400)
12350 #define NOTRACK_PREFIX (0x3e | 0x100)
12355 int newrex
, i
, length
;
12361 last_lock_prefix
= -1;
12362 last_repz_prefix
= -1;
12363 last_repnz_prefix
= -1;
12364 last_data_prefix
= -1;
12365 last_addr_prefix
= -1;
12366 last_rex_prefix
= -1;
12367 last_seg_prefix
= -1;
12369 active_seg_prefix
= 0;
12370 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12371 all_prefixes
[i
] = 0;
12374 /* The maximum instruction length is 15bytes. */
12375 while (length
< MAX_CODE_LENGTH
- 1)
12377 FETCH_DATA (the_info
, codep
+ 1);
12381 /* REX prefixes family. */
12398 if (address_mode
== mode_64bit
)
12402 last_rex_prefix
= i
;
12405 prefixes
|= PREFIX_REPZ
;
12406 last_repz_prefix
= i
;
12409 prefixes
|= PREFIX_REPNZ
;
12410 last_repnz_prefix
= i
;
12413 prefixes
|= PREFIX_LOCK
;
12414 last_lock_prefix
= i
;
12417 prefixes
|= PREFIX_CS
;
12418 last_seg_prefix
= i
;
12419 active_seg_prefix
= PREFIX_CS
;
12422 prefixes
|= PREFIX_SS
;
12423 last_seg_prefix
= i
;
12424 active_seg_prefix
= PREFIX_SS
;
12427 prefixes
|= PREFIX_DS
;
12428 last_seg_prefix
= i
;
12429 active_seg_prefix
= PREFIX_DS
;
12432 prefixes
|= PREFIX_ES
;
12433 last_seg_prefix
= i
;
12434 active_seg_prefix
= PREFIX_ES
;
12437 prefixes
|= PREFIX_FS
;
12438 last_seg_prefix
= i
;
12439 active_seg_prefix
= PREFIX_FS
;
12442 prefixes
|= PREFIX_GS
;
12443 last_seg_prefix
= i
;
12444 active_seg_prefix
= PREFIX_GS
;
12447 prefixes
|= PREFIX_DATA
;
12448 last_data_prefix
= i
;
12451 prefixes
|= PREFIX_ADDR
;
12452 last_addr_prefix
= i
;
12455 /* fwait is really an instruction. If there are prefixes
12456 before the fwait, they belong to the fwait, *not* to the
12457 following instruction. */
12459 if (prefixes
|| rex
)
12461 prefixes
|= PREFIX_FWAIT
;
12463 /* This ensures that the previous REX prefixes are noticed
12464 as unused prefixes, as in the return case below. */
12468 prefixes
= PREFIX_FWAIT
;
12473 /* Rex is ignored when followed by another prefix. */
12479 if (*codep
!= FWAIT_OPCODE
)
12480 all_prefixes
[i
++] = *codep
;
12488 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12491 static const char *
12492 prefix_name (int pref
, int sizeflag
)
12494 static const char *rexes
[16] =
12497 "rex.B", /* 0x41 */
12498 "rex.X", /* 0x42 */
12499 "rex.XB", /* 0x43 */
12500 "rex.R", /* 0x44 */
12501 "rex.RB", /* 0x45 */
12502 "rex.RX", /* 0x46 */
12503 "rex.RXB", /* 0x47 */
12504 "rex.W", /* 0x48 */
12505 "rex.WB", /* 0x49 */
12506 "rex.WX", /* 0x4a */
12507 "rex.WXB", /* 0x4b */
12508 "rex.WR", /* 0x4c */
12509 "rex.WRB", /* 0x4d */
12510 "rex.WRX", /* 0x4e */
12511 "rex.WRXB", /* 0x4f */
12516 /* REX prefixes family. */
12533 return rexes
[pref
- 0x40];
12553 return (sizeflag
& DFLAG
) ? "data16" : "data32";
12555 if (address_mode
== mode_64bit
)
12556 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
12558 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
12563 case XACQUIRE_PREFIX
:
12565 case XRELEASE_PREFIX
:
12569 case NOTRACK_PREFIX
:
12576 static char op_out
[MAX_OPERANDS
][100];
12577 static int op_ad
, op_index
[MAX_OPERANDS
];
12578 static int two_source_ops
;
12579 static bfd_vma op_address
[MAX_OPERANDS
];
12580 static bfd_vma op_riprel
[MAX_OPERANDS
];
12581 static bfd_vma start_pc
;
12584 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12585 * (see topic "Redundant prefixes" in the "Differences from 8086"
12586 * section of the "Virtual 8086 Mode" chapter.)
12587 * 'pc' should be the address of this instruction, it will
12588 * be used to print the target address if this is a relative jump or call
12589 * The function returns the length of this instruction in bytes.
12592 static char intel_syntax
;
12593 static char intel_mnemonic
= !SYSV386_COMPAT
;
12594 static char open_char
;
12595 static char close_char
;
12596 static char separator_char
;
12597 static char scale_char
;
12605 static enum x86_64_isa isa64
;
12607 /* Here for backwards compatibility. When gdb stops using
12608 print_insn_i386_att and print_insn_i386_intel these functions can
12609 disappear, and print_insn_i386 be merged into print_insn. */
12611 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
12615 return print_insn (pc
, info
);
12619 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
12623 return print_insn (pc
, info
);
12627 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
12631 return print_insn (pc
, info
);
12635 print_i386_disassembler_options (FILE *stream
)
12637 fprintf (stream
, _("\n\
12638 The following i386/x86-64 specific disassembler options are supported for use\n\
12639 with the -M switch (multiple options should be separated by commas):\n"));
12641 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
12642 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
12643 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
12644 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
12645 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
12646 fprintf (stream
, _(" att-mnemonic\n"
12647 " Display instruction in AT&T mnemonic\n"));
12648 fprintf (stream
, _(" intel-mnemonic\n"
12649 " Display instruction in Intel mnemonic\n"));
12650 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
12651 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
12652 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
12653 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
12654 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
12655 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12656 fprintf (stream
, _(" amd64 Display instruction in AMD64 ISA\n"));
12657 fprintf (stream
, _(" intel64 Display instruction in Intel64 ISA\n"));
12661 static const struct dis386 bad_opcode
= { "(bad)", { XX
}, 0 };
12663 /* Get a pointer to struct dis386 with a valid name. */
12665 static const struct dis386
*
12666 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
12668 int vindex
, vex_table_index
;
12670 if (dp
->name
!= NULL
)
12673 switch (dp
->op
[0].bytemode
)
12675 case USE_REG_TABLE
:
12676 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
12679 case USE_MOD_TABLE
:
12680 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
12681 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
12685 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
12688 case USE_PREFIX_TABLE
:
12691 /* The prefix in VEX is implicit. */
12692 switch (vex
.prefix
)
12697 case REPE_PREFIX_OPCODE
:
12700 case DATA_PREFIX_OPCODE
:
12703 case REPNE_PREFIX_OPCODE
:
12713 int last_prefix
= -1;
12716 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12717 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12719 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
12721 if (last_repz_prefix
> last_repnz_prefix
)
12724 prefix
= PREFIX_REPZ
;
12725 last_prefix
= last_repz_prefix
;
12730 prefix
= PREFIX_REPNZ
;
12731 last_prefix
= last_repnz_prefix
;
12734 /* Check if prefix should be ignored. */
12735 if ((((prefix_table
[dp
->op
[1].bytemode
][vindex
].prefix_requirement
12736 & PREFIX_IGNORED
) >> PREFIX_IGNORED_SHIFT
)
12741 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12744 prefix
= PREFIX_DATA
;
12745 last_prefix
= last_data_prefix
;
12750 used_prefixes
|= prefix
;
12751 all_prefixes
[last_prefix
] = 0;
12754 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12757 case USE_X86_64_TABLE
:
12758 vindex
= address_mode
== mode_64bit
? 1 : 0;
12759 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12762 case USE_3BYTE_TABLE
:
12763 FETCH_DATA (info
, codep
+ 2);
12765 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12767 modrm
.mod
= (*codep
>> 6) & 3;
12768 modrm
.reg
= (*codep
>> 3) & 7;
12769 modrm
.rm
= *codep
& 7;
12772 case USE_VEX_LEN_TABLE
:
12776 switch (vex
.length
)
12789 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12792 case USE_XOP_8F_TABLE
:
12793 FETCH_DATA (info
, codep
+ 3);
12794 /* All bits in the REX prefix are ignored. */
12796 rex
= ~(*codep
>> 5) & 0x7;
12798 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12799 switch ((*codep
& 0x1f))
12805 vex_table_index
= XOP_08
;
12808 vex_table_index
= XOP_09
;
12811 vex_table_index
= XOP_0A
;
12815 vex
.w
= *codep
& 0x80;
12816 if (vex
.w
&& address_mode
== mode_64bit
)
12819 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12820 if (address_mode
!= mode_64bit
)
12822 /* In 16/32-bit mode REX_B is silently ignored. */
12826 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12827 switch ((*codep
& 0x3))
12833 vex
.prefix
= DATA_PREFIX_OPCODE
;
12836 vex
.prefix
= REPE_PREFIX_OPCODE
;
12839 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12846 dp
= &xop_table
[vex_table_index
][vindex
];
12849 FETCH_DATA (info
, codep
+ 1);
12850 modrm
.mod
= (*codep
>> 6) & 3;
12851 modrm
.reg
= (*codep
>> 3) & 7;
12852 modrm
.rm
= *codep
& 7;
12855 case USE_VEX_C4_TABLE
:
12857 FETCH_DATA (info
, codep
+ 3);
12858 /* All bits in the REX prefix are ignored. */
12860 rex
= ~(*codep
>> 5) & 0x7;
12861 switch ((*codep
& 0x1f))
12867 vex_table_index
= VEX_0F
;
12870 vex_table_index
= VEX_0F38
;
12873 vex_table_index
= VEX_0F3A
;
12877 vex
.w
= *codep
& 0x80;
12878 if (address_mode
== mode_64bit
)
12885 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12886 is ignored, other REX bits are 0 and the highest bit in
12887 VEX.vvvv is also ignored (but we mustn't clear it here). */
12890 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12891 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12892 switch ((*codep
& 0x3))
12898 vex
.prefix
= DATA_PREFIX_OPCODE
;
12901 vex
.prefix
= REPE_PREFIX_OPCODE
;
12904 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12911 dp
= &vex_table
[vex_table_index
][vindex
];
12913 /* There is no MODRM byte for VEX0F 77. */
12914 if (vex_table_index
!= VEX_0F
|| vindex
!= 0x77)
12916 FETCH_DATA (info
, codep
+ 1);
12917 modrm
.mod
= (*codep
>> 6) & 3;
12918 modrm
.reg
= (*codep
>> 3) & 7;
12919 modrm
.rm
= *codep
& 7;
12923 case USE_VEX_C5_TABLE
:
12925 FETCH_DATA (info
, codep
+ 2);
12926 /* All bits in the REX prefix are ignored. */
12928 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12930 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12932 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12934 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12935 switch ((*codep
& 0x3))
12941 vex
.prefix
= DATA_PREFIX_OPCODE
;
12944 vex
.prefix
= REPE_PREFIX_OPCODE
;
12947 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12954 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12956 /* There is no MODRM byte for VEX 77. */
12957 if (vindex
!= 0x77)
12959 FETCH_DATA (info
, codep
+ 1);
12960 modrm
.mod
= (*codep
>> 6) & 3;
12961 modrm
.reg
= (*codep
>> 3) & 7;
12962 modrm
.rm
= *codep
& 7;
12966 case USE_VEX_W_TABLE
:
12970 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12973 case USE_EVEX_TABLE
:
12974 two_source_ops
= 0;
12977 FETCH_DATA (info
, codep
+ 4);
12978 /* All bits in the REX prefix are ignored. */
12980 /* The first byte after 0x62. */
12981 rex
= ~(*codep
>> 5) & 0x7;
12982 vex
.r
= *codep
& 0x10;
12983 switch ((*codep
& 0xf))
12986 return &bad_opcode
;
12988 vex_table_index
= EVEX_0F
;
12991 vex_table_index
= EVEX_0F38
;
12994 vex_table_index
= EVEX_0F3A
;
12998 /* The second byte after 0x62. */
13000 vex
.w
= *codep
& 0x80;
13001 if (vex
.w
&& address_mode
== mode_64bit
)
13004 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
13007 if (!(*codep
& 0x4))
13008 return &bad_opcode
;
13010 switch ((*codep
& 0x3))
13016 vex
.prefix
= DATA_PREFIX_OPCODE
;
13019 vex
.prefix
= REPE_PREFIX_OPCODE
;
13022 vex
.prefix
= REPNE_PREFIX_OPCODE
;
13026 /* The third byte after 0x62. */
13029 /* Remember the static rounding bits. */
13030 vex
.ll
= (*codep
>> 5) & 3;
13031 vex
.b
= (*codep
& 0x10) != 0;
13033 vex
.v
= *codep
& 0x8;
13034 vex
.mask_register_specifier
= *codep
& 0x7;
13035 vex
.zeroing
= *codep
& 0x80;
13037 if (address_mode
!= mode_64bit
)
13039 /* In 16/32-bit mode silently ignore following bits. */
13049 dp
= &evex_table
[vex_table_index
][vindex
];
13051 FETCH_DATA (info
, codep
+ 1);
13052 modrm
.mod
= (*codep
>> 6) & 3;
13053 modrm
.reg
= (*codep
>> 3) & 7;
13054 modrm
.rm
= *codep
& 7;
13056 /* Set vector length. */
13057 if (modrm
.mod
== 3 && vex
.b
)
13073 return &bad_opcode
;
13086 if (dp
->name
!= NULL
)
13089 return get_valid_dis386 (dp
, info
);
13093 get_sib (disassemble_info
*info
, int sizeflag
)
13095 /* If modrm.mod == 3, operand must be register. */
13097 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
13101 FETCH_DATA (info
, codep
+ 2);
13102 sib
.index
= (codep
[1] >> 3) & 7;
13103 sib
.scale
= (codep
[1] >> 6) & 3;
13104 sib
.base
= codep
[1] & 7;
13109 print_insn (bfd_vma pc
, disassemble_info
*info
)
13111 const struct dis386
*dp
;
13113 char *op_txt
[MAX_OPERANDS
];
13115 int sizeflag
, orig_sizeflag
;
13117 struct dis_private priv
;
13120 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13121 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
13122 address_mode
= mode_32bit
;
13123 else if (info
->mach
== bfd_mach_i386_i8086
)
13125 address_mode
= mode_16bit
;
13126 priv
.orig_sizeflag
= 0;
13129 address_mode
= mode_64bit
;
13131 if (intel_syntax
== (char) -1)
13132 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
13134 for (p
= info
->disassembler_options
; p
!= NULL
; )
13136 if (CONST_STRNEQ (p
, "amd64"))
13138 else if (CONST_STRNEQ (p
, "intel64"))
13140 else if (CONST_STRNEQ (p
, "x86-64"))
13142 address_mode
= mode_64bit
;
13143 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13145 else if (CONST_STRNEQ (p
, "i386"))
13147 address_mode
= mode_32bit
;
13148 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
13150 else if (CONST_STRNEQ (p
, "i8086"))
13152 address_mode
= mode_16bit
;
13153 priv
.orig_sizeflag
= 0;
13155 else if (CONST_STRNEQ (p
, "intel"))
13158 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
13159 intel_mnemonic
= 1;
13161 else if (CONST_STRNEQ (p
, "att"))
13164 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
13165 intel_mnemonic
= 0;
13167 else if (CONST_STRNEQ (p
, "addr"))
13169 if (address_mode
== mode_64bit
)
13171 if (p
[4] == '3' && p
[5] == '2')
13172 priv
.orig_sizeflag
&= ~AFLAG
;
13173 else if (p
[4] == '6' && p
[5] == '4')
13174 priv
.orig_sizeflag
|= AFLAG
;
13178 if (p
[4] == '1' && p
[5] == '6')
13179 priv
.orig_sizeflag
&= ~AFLAG
;
13180 else if (p
[4] == '3' && p
[5] == '2')
13181 priv
.orig_sizeflag
|= AFLAG
;
13184 else if (CONST_STRNEQ (p
, "data"))
13186 if (p
[4] == '1' && p
[5] == '6')
13187 priv
.orig_sizeflag
&= ~DFLAG
;
13188 else if (p
[4] == '3' && p
[5] == '2')
13189 priv
.orig_sizeflag
|= DFLAG
;
13191 else if (CONST_STRNEQ (p
, "suffix"))
13192 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
13194 p
= strchr (p
, ',');
13199 if (address_mode
== mode_64bit
&& sizeof (bfd_vma
) < 8)
13201 (*info
->fprintf_func
) (info
->stream
,
13202 _("64-bit address is disabled"));
13208 names64
= intel_names64
;
13209 names32
= intel_names32
;
13210 names16
= intel_names16
;
13211 names8
= intel_names8
;
13212 names8rex
= intel_names8rex
;
13213 names_seg
= intel_names_seg
;
13214 names_mm
= intel_names_mm
;
13215 names_bnd
= intel_names_bnd
;
13216 names_xmm
= intel_names_xmm
;
13217 names_ymm
= intel_names_ymm
;
13218 names_zmm
= intel_names_zmm
;
13219 index64
= intel_index64
;
13220 index32
= intel_index32
;
13221 names_mask
= intel_names_mask
;
13222 index16
= intel_index16
;
13225 separator_char
= '+';
13230 names64
= att_names64
;
13231 names32
= att_names32
;
13232 names16
= att_names16
;
13233 names8
= att_names8
;
13234 names8rex
= att_names8rex
;
13235 names_seg
= att_names_seg
;
13236 names_mm
= att_names_mm
;
13237 names_bnd
= att_names_bnd
;
13238 names_xmm
= att_names_xmm
;
13239 names_ymm
= att_names_ymm
;
13240 names_zmm
= att_names_zmm
;
13241 index64
= att_index64
;
13242 index32
= att_index32
;
13243 names_mask
= att_names_mask
;
13244 index16
= att_index16
;
13247 separator_char
= ',';
13251 /* The output looks better if we put 7 bytes on a line, since that
13252 puts most long word instructions on a single line. Use 8 bytes
13254 if ((info
->mach
& bfd_mach_l1om
) != 0)
13255 info
->bytes_per_line
= 8;
13257 info
->bytes_per_line
= 7;
13259 info
->private_data
= &priv
;
13260 priv
.max_fetched
= priv
.the_buffer
;
13261 priv
.insn_start
= pc
;
13264 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13272 start_codep
= priv
.the_buffer
;
13273 codep
= priv
.the_buffer
;
13275 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
13279 /* Getting here means we tried for data but didn't get it. That
13280 means we have an incomplete instruction of some sort. Just
13281 print the first byte as a prefix or a .byte pseudo-op. */
13282 if (codep
> priv
.the_buffer
)
13284 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
13286 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
13289 /* Just print the first byte as a .byte instruction. */
13290 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
13291 (unsigned int) priv
.the_buffer
[0]);
13301 sizeflag
= priv
.orig_sizeflag
;
13303 if (!ckprefix () || rex_used
)
13305 /* Too many prefixes or unused REX prefixes. */
13307 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
13309 (*info
->fprintf_func
) (info
->stream
, "%s%s",
13311 prefix_name (all_prefixes
[i
], sizeflag
));
13315 insn_codep
= codep
;
13317 FETCH_DATA (info
, codep
+ 1);
13318 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
13320 if (((prefixes
& PREFIX_FWAIT
)
13321 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
13323 /* Handle prefixes before fwait. */
13324 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
13326 (*info
->fprintf_func
) (info
->stream
, "%s ",
13327 prefix_name (all_prefixes
[i
], sizeflag
));
13328 (*info
->fprintf_func
) (info
->stream
, "fwait");
13332 if (*codep
== 0x0f)
13334 unsigned char threebyte
;
13337 FETCH_DATA (info
, codep
+ 1);
13338 threebyte
= *codep
;
13339 dp
= &dis386_twobyte
[threebyte
];
13340 need_modrm
= twobyte_has_modrm
[*codep
];
13345 dp
= &dis386
[*codep
];
13346 need_modrm
= onebyte_has_modrm
[*codep
];
13350 /* Save sizeflag for printing the extra prefixes later before updating
13351 it for mnemonic and operand processing. The prefix names depend
13352 only on the address mode. */
13353 orig_sizeflag
= sizeflag
;
13354 if (prefixes
& PREFIX_ADDR
)
13356 if ((prefixes
& PREFIX_DATA
))
13362 FETCH_DATA (info
, codep
+ 1);
13363 modrm
.mod
= (*codep
>> 6) & 3;
13364 modrm
.reg
= (*codep
>> 3) & 7;
13365 modrm
.rm
= *codep
& 7;
13373 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
13375 get_sib (info
, sizeflag
);
13376 dofloat (sizeflag
);
13380 dp
= get_valid_dis386 (dp
, info
);
13381 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
13383 get_sib (info
, sizeflag
);
13384 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13387 op_ad
= MAX_OPERANDS
- 1 - i
;
13389 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
13390 /* For EVEX instruction after the last operand masking
13391 should be printed. */
13392 if (i
== 0 && vex
.evex
)
13394 /* Don't print {%k0}. */
13395 if (vex
.mask_register_specifier
)
13398 oappend (names_mask
[vex
.mask_register_specifier
]);
13408 /* Check if the REX prefix is used. */
13409 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
13410 all_prefixes
[last_rex_prefix
] = 0;
13412 /* Check if the SEG prefix is used. */
13413 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
13414 | PREFIX_FS
| PREFIX_GS
)) != 0
13415 && (used_prefixes
& active_seg_prefix
) != 0)
13416 all_prefixes
[last_seg_prefix
] = 0;
13418 /* Check if the ADDR prefix is used. */
13419 if ((prefixes
& PREFIX_ADDR
) != 0
13420 && (used_prefixes
& PREFIX_ADDR
) != 0)
13421 all_prefixes
[last_addr_prefix
] = 0;
13423 /* Check if the DATA prefix is used. */
13424 if ((prefixes
& PREFIX_DATA
) != 0
13425 && (used_prefixes
& PREFIX_DATA
) != 0)
13426 all_prefixes
[last_data_prefix
] = 0;
13428 /* Print the extra prefixes. */
13430 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
13431 if (all_prefixes
[i
])
13434 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
13437 prefix_length
+= strlen (name
) + 1;
13438 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
13441 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13442 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13443 used by putop and MMX/SSE operand and may be overriden by the
13444 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13446 if (dp
->prefix_requirement
== PREFIX_OPCODE
13447 && dp
!= &bad_opcode
13449 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
13451 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
13453 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
13455 && (used_prefixes
& PREFIX_DATA
) == 0))))
13457 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13458 return end_codep
- priv
.the_buffer
;
13461 /* Check maximum code length. */
13462 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
13464 (*info
->fprintf_func
) (info
->stream
, "(bad)");
13465 return MAX_CODE_LENGTH
;
13468 obufp
= mnemonicendp
;
13469 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
13472 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
13474 /* The enter and bound instructions are printed with operands in the same
13475 order as the intel book; everything else is printed in reverse order. */
13476 if (intel_syntax
|| two_source_ops
)
13480 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13481 op_txt
[i
] = op_out
[i
];
13483 if (intel_syntax
&& dp
&& dp
->op
[2].rtn
== OP_Rounding
13484 && dp
->op
[3].rtn
== OP_E
&& dp
->op
[4].rtn
== NULL
)
13486 op_txt
[2] = op_out
[3];
13487 op_txt
[3] = op_out
[2];
13490 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
13492 op_ad
= op_index
[i
];
13493 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
13494 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
13495 riprel
= op_riprel
[i
];
13496 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
13497 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
13502 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13503 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
13507 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
13511 (*info
->fprintf_func
) (info
->stream
, ",");
13512 if (op_index
[i
] != -1 && !op_riprel
[i
])
13513 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
13515 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
13519 for (i
= 0; i
< MAX_OPERANDS
; i
++)
13520 if (op_index
[i
] != -1 && op_riprel
[i
])
13522 (*info
->fprintf_func
) (info
->stream
, " # ");
13523 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ (codep
- start_codep
)
13524 + op_address
[op_index
[i
]]), info
);
13527 return codep
- priv
.the_buffer
;
13530 static const char *float_mem
[] = {
13605 static const unsigned char float_mem_mode
[] = {
13680 #define ST { OP_ST, 0 }
13681 #define STi { OP_STi, 0 }
13683 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13684 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13685 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13686 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13687 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13688 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13689 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13690 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13691 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13693 static const struct dis386 float_reg
[][8] = {
13696 { "fadd", { ST
, STi
}, 0 },
13697 { "fmul", { ST
, STi
}, 0 },
13698 { "fcom", { STi
}, 0 },
13699 { "fcomp", { STi
}, 0 },
13700 { "fsub", { ST
, STi
}, 0 },
13701 { "fsubr", { ST
, STi
}, 0 },
13702 { "fdiv", { ST
, STi
}, 0 },
13703 { "fdivr", { ST
, STi
}, 0 },
13707 { "fld", { STi
}, 0 },
13708 { "fxch", { STi
}, 0 },
13718 { "fcmovb", { ST
, STi
}, 0 },
13719 { "fcmove", { ST
, STi
}, 0 },
13720 { "fcmovbe",{ ST
, STi
}, 0 },
13721 { "fcmovu", { ST
, STi
}, 0 },
13729 { "fcmovnb",{ ST
, STi
}, 0 },
13730 { "fcmovne",{ ST
, STi
}, 0 },
13731 { "fcmovnbe",{ ST
, STi
}, 0 },
13732 { "fcmovnu",{ ST
, STi
}, 0 },
13734 { "fucomi", { ST
, STi
}, 0 },
13735 { "fcomi", { ST
, STi
}, 0 },
13740 { "fadd", { STi
, ST
}, 0 },
13741 { "fmul", { STi
, ST
}, 0 },
13744 { "fsub{!M|r}", { STi
, ST
}, 0 },
13745 { "fsub{M|}", { STi
, ST
}, 0 },
13746 { "fdiv{!M|r}", { STi
, ST
}, 0 },
13747 { "fdiv{M|}", { STi
, ST
}, 0 },
13751 { "ffree", { STi
}, 0 },
13753 { "fst", { STi
}, 0 },
13754 { "fstp", { STi
}, 0 },
13755 { "fucom", { STi
}, 0 },
13756 { "fucomp", { STi
}, 0 },
13762 { "faddp", { STi
, ST
}, 0 },
13763 { "fmulp", { STi
, ST
}, 0 },
13766 { "fsub{!M|r}p", { STi
, ST
}, 0 },
13767 { "fsub{M|}p", { STi
, ST
}, 0 },
13768 { "fdiv{!M|r}p", { STi
, ST
}, 0 },
13769 { "fdiv{M|}p", { STi
, ST
}, 0 },
13773 { "ffreep", { STi
}, 0 },
13778 { "fucomip", { ST
, STi
}, 0 },
13779 { "fcomip", { ST
, STi
}, 0 },
13784 static char *fgrps
[][8] = {
13787 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13792 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13797 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13802 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13807 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13812 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13817 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13822 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13823 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13828 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13833 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13838 swap_operand (void)
13840 mnemonicendp
[0] = '.';
13841 mnemonicendp
[1] = 's';
13846 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13847 int sizeflag ATTRIBUTE_UNUSED
)
13849 /* Skip mod/rm byte. */
13855 dofloat (int sizeflag
)
13857 const struct dis386
*dp
;
13858 unsigned char floatop
;
13860 floatop
= codep
[-1];
13862 if (modrm
.mod
!= 3)
13864 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13866 putop (float_mem
[fp_indx
], sizeflag
);
13869 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13872 /* Skip mod/rm byte. */
13876 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13877 if (dp
->name
== NULL
)
13879 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13881 /* Instruction fnstsw is only one with strange arg. */
13882 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13883 strcpy (op_out
[0], names16
[0]);
13887 putop (dp
->name
, sizeflag
);
13892 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13897 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13901 /* Like oappend (below), but S is a string starting with '%'.
13902 In Intel syntax, the '%' is elided. */
13904 oappend_maybe_intel (const char *s
)
13906 oappend (s
+ intel_syntax
);
13910 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13912 oappend_maybe_intel ("%st");
13916 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13918 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13919 oappend_maybe_intel (scratchbuf
);
13922 /* Capital letters in template are macros. */
13924 putop (const char *in_template
, int sizeflag
)
13929 unsigned int l
= 0, len
= 1;
13932 #define SAVE_LAST(c) \
13933 if (l < len && l < sizeof (last)) \
13938 for (p
= in_template
; *p
; p
++)
13954 while (*++p
!= '|')
13955 if (*p
== '}' || *p
== '\0')
13958 /* Fall through. */
13963 while (*++p
!= '}')
13974 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13978 if (l
== 0 && len
== 1)
13983 if (sizeflag
& SUFFIX_ALWAYS
)
13996 if (address_mode
== mode_64bit
13997 && !(prefixes
& PREFIX_ADDR
))
14008 if (intel_syntax
&& !alt
)
14010 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14012 if (sizeflag
& DFLAG
)
14013 *obufp
++ = intel_syntax
? 'd' : 'l';
14015 *obufp
++ = intel_syntax
? 'w' : 's';
14016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14020 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14023 if (modrm
.mod
== 3)
14029 if (sizeflag
& DFLAG
)
14030 *obufp
++ = intel_syntax
? 'd' : 'l';
14033 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14039 case 'E': /* For jcxz/jecxz */
14040 if (address_mode
== mode_64bit
)
14042 if (sizeflag
& AFLAG
)
14048 if (sizeflag
& AFLAG
)
14050 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14055 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
14057 if (sizeflag
& AFLAG
)
14058 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
14060 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
14061 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
14065 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
14067 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14071 if (!(rex
& REX_W
))
14072 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14077 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
14078 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
14080 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
14083 if (prefixes
& PREFIX_DS
)
14102 if (l
!= 0 || len
!= 1)
14104 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14109 if (!need_vex
|| !vex
.evex
)
14112 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14114 switch (vex
.length
)
14132 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
14137 /* Fall through. */
14140 if (l
!= 0 || len
!= 1)
14148 if (sizeflag
& SUFFIX_ALWAYS
)
14152 if (intel_mnemonic
!= cond
)
14156 if ((prefixes
& PREFIX_FWAIT
) == 0)
14159 used_prefixes
|= PREFIX_FWAIT
;
14165 else if (intel_syntax
&& (sizeflag
& DFLAG
))
14169 if (!(rex
& REX_W
))
14170 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14174 && address_mode
== mode_64bit
14175 && isa64
== intel64
)
14180 /* Fall through. */
14183 && address_mode
== mode_64bit
14184 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14189 /* Fall through. */
14192 if (l
== 0 && len
== 1)
14197 if ((rex
& REX_W
) == 0
14198 && (prefixes
& PREFIX_DATA
))
14200 if ((sizeflag
& DFLAG
) == 0)
14202 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14206 if ((prefixes
& PREFIX_DATA
)
14208 || (sizeflag
& SUFFIX_ALWAYS
))
14215 if (sizeflag
& DFLAG
)
14219 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14225 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14231 if ((prefixes
& PREFIX_DATA
)
14233 || (sizeflag
& SUFFIX_ALWAYS
))
14240 if (sizeflag
& DFLAG
)
14241 *obufp
++ = intel_syntax
? 'd' : 'l';
14244 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14252 if (address_mode
== mode_64bit
14253 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14255 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14259 /* Fall through. */
14262 if (l
== 0 && len
== 1)
14265 if (intel_syntax
&& !alt
)
14268 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
14274 if (sizeflag
& DFLAG
)
14275 *obufp
++ = intel_syntax
? 'd' : 'l';
14278 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14284 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
14290 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
14305 else if (sizeflag
& DFLAG
)
14314 if (intel_syntax
&& !p
[1]
14315 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
14317 if (!(rex
& REX_W
))
14318 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14321 if (l
== 0 && len
== 1)
14325 if (address_mode
== mode_64bit
14326 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14328 if (sizeflag
& SUFFIX_ALWAYS
)
14350 /* Fall through. */
14353 if (l
== 0 && len
== 1)
14358 if (sizeflag
& SUFFIX_ALWAYS
)
14364 if (sizeflag
& DFLAG
)
14368 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14382 if (address_mode
== mode_64bit
14383 && !(prefixes
& PREFIX_ADDR
))
14394 if (l
!= 0 || len
!= 1)
14399 if (need_vex
&& vex
.prefix
)
14401 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
14408 if (prefixes
& PREFIX_DATA
)
14412 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14416 if (l
== 0 && len
== 1)
14418 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
14429 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
14437 || ((modrm
.mod
== 3 || vex
.b
) && !(sizeflag
& SUFFIX_ALWAYS
)))
14439 switch (vex
.length
)
14455 if (l
== 0 && len
== 1)
14457 /* operand size flag for cwtl, cbtw */
14466 else if (sizeflag
& DFLAG
)
14470 if (!(rex
& REX_W
))
14471 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14478 && last
[0] != 'L'))
14485 if (last
[0] == 'X')
14486 *obufp
++ = vex
.w
? 'd': 's';
14488 *obufp
++ = vex
.w
? 'q': 'd';
14494 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
14496 if (sizeflag
& DFLAG
)
14500 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14506 if (address_mode
== mode_64bit
14507 && (isa64
== intel64
14508 || ((sizeflag
& DFLAG
) || (rex
& REX_W
))))
14510 else if ((prefixes
& PREFIX_DATA
))
14512 if (!(sizeflag
& DFLAG
))
14514 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14521 mnemonicendp
= obufp
;
14526 oappend (const char *s
)
14528 obufp
= stpcpy (obufp
, s
);
14534 /* Only print the active segment register. */
14535 if (!active_seg_prefix
)
14538 used_prefixes
|= active_seg_prefix
;
14539 switch (active_seg_prefix
)
14542 oappend_maybe_intel ("%cs:");
14545 oappend_maybe_intel ("%ds:");
14548 oappend_maybe_intel ("%ss:");
14551 oappend_maybe_intel ("%es:");
14554 oappend_maybe_intel ("%fs:");
14557 oappend_maybe_intel ("%gs:");
14565 OP_indirE (int bytemode
, int sizeflag
)
14569 OP_E (bytemode
, sizeflag
);
14573 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
14575 if (address_mode
== mode_64bit
)
14583 sprintf_vma (tmp
, disp
);
14584 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
14585 strcpy (buf
+ 2, tmp
+ i
);
14589 bfd_signed_vma v
= disp
;
14596 /* Check for possible overflow on 0x8000000000000000. */
14599 strcpy (buf
, "9223372036854775808");
14613 tmp
[28 - i
] = (v
% 10) + '0';
14617 strcpy (buf
, tmp
+ 29 - i
);
14623 sprintf (buf
, "0x%x", (unsigned int) disp
);
14625 sprintf (buf
, "%d", (int) disp
);
14629 /* Put DISP in BUF as signed hex number. */
14632 print_displacement (char *buf
, bfd_vma disp
)
14634 bfd_signed_vma val
= disp
;
14643 /* Check for possible overflow. */
14646 switch (address_mode
)
14649 strcpy (buf
+ j
, "0x8000000000000000");
14652 strcpy (buf
+ j
, "0x80000000");
14655 strcpy (buf
+ j
, "0x8000");
14665 sprintf_vma (tmp
, (bfd_vma
) val
);
14666 for (i
= 0; tmp
[i
] == '0'; i
++)
14668 if (tmp
[i
] == '\0')
14670 strcpy (buf
+ j
, tmp
+ i
);
14674 intel_operand_size (int bytemode
, int sizeflag
)
14678 && (bytemode
== x_mode
14679 || bytemode
== evex_half_bcst_xmmq_mode
))
14682 oappend ("QWORD PTR ");
14684 oappend ("DWORD PTR ");
14693 oappend ("BYTE PTR ");
14698 oappend ("WORD PTR ");
14701 if (address_mode
== mode_64bit
&& isa64
== intel64
)
14703 oappend ("QWORD PTR ");
14706 /* Fall through. */
14708 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14710 oappend ("QWORD PTR ");
14713 /* Fall through. */
14719 oappend ("QWORD PTR ");
14722 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
14723 oappend ("DWORD PTR ");
14725 oappend ("WORD PTR ");
14726 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14730 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14732 oappend ("WORD PTR ");
14733 if (!(rex
& REX_W
))
14734 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14737 if (sizeflag
& DFLAG
)
14738 oappend ("QWORD PTR ");
14740 oappend ("DWORD PTR ");
14741 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14744 case d_scalar_mode
:
14745 case d_scalar_swap_mode
:
14748 oappend ("DWORD PTR ");
14751 case q_scalar_mode
:
14752 case q_scalar_swap_mode
:
14754 oappend ("QWORD PTR ");
14757 if (address_mode
== mode_64bit
)
14758 oappend ("QWORD PTR ");
14760 oappend ("DWORD PTR ");
14763 if (sizeflag
& DFLAG
)
14764 oappend ("FWORD PTR ");
14766 oappend ("DWORD PTR ");
14767 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14770 oappend ("TBYTE PTR ");
14774 case evex_x_gscat_mode
:
14775 case evex_x_nobcst_mode
:
14776 case b_scalar_mode
:
14777 case w_scalar_mode
:
14780 switch (vex
.length
)
14783 oappend ("XMMWORD PTR ");
14786 oappend ("YMMWORD PTR ");
14789 oappend ("ZMMWORD PTR ");
14796 oappend ("XMMWORD PTR ");
14799 oappend ("XMMWORD PTR ");
14802 oappend ("YMMWORD PTR ");
14805 case evex_half_bcst_xmmq_mode
:
14809 switch (vex
.length
)
14812 oappend ("QWORD PTR ");
14815 oappend ("XMMWORD PTR ");
14818 oappend ("YMMWORD PTR ");
14828 switch (vex
.length
)
14833 oappend ("BYTE PTR ");
14843 switch (vex
.length
)
14848 oappend ("WORD PTR ");
14858 switch (vex
.length
)
14863 oappend ("DWORD PTR ");
14873 switch (vex
.length
)
14878 oappend ("QWORD PTR ");
14888 switch (vex
.length
)
14891 oappend ("WORD PTR ");
14894 oappend ("DWORD PTR ");
14897 oappend ("QWORD PTR ");
14907 switch (vex
.length
)
14910 oappend ("DWORD PTR ");
14913 oappend ("QWORD PTR ");
14916 oappend ("XMMWORD PTR ");
14926 switch (vex
.length
)
14929 oappend ("QWORD PTR ");
14932 oappend ("YMMWORD PTR ");
14935 oappend ("ZMMWORD PTR ");
14945 switch (vex
.length
)
14949 oappend ("XMMWORD PTR ");
14956 oappend ("OWORD PTR ");
14959 case vex_w_dq_mode
:
14960 case vex_scalar_w_dq_mode
:
14965 oappend ("QWORD PTR ");
14967 oappend ("DWORD PTR ");
14969 case vex_vsib_d_w_dq_mode
:
14970 case vex_vsib_q_w_dq_mode
:
14977 oappend ("QWORD PTR ");
14979 oappend ("DWORD PTR ");
14983 switch (vex
.length
)
14986 oappend ("XMMWORD PTR ");
14989 oappend ("YMMWORD PTR ");
14992 oappend ("ZMMWORD PTR ");
14999 case vex_vsib_q_w_d_mode
:
15000 case vex_vsib_d_w_d_mode
:
15001 if (!need_vex
|| !vex
.evex
)
15004 switch (vex
.length
)
15007 oappend ("QWORD PTR ");
15010 oappend ("XMMWORD PTR ");
15013 oappend ("YMMWORD PTR ");
15021 if (!need_vex
|| vex
.length
!= 128)
15024 oappend ("DWORD PTR ");
15026 oappend ("BYTE PTR ");
15032 oappend ("QWORD PTR ");
15034 oappend ("WORD PTR ");
15043 OP_E_register (int bytemode
, int sizeflag
)
15045 int reg
= modrm
.rm
;
15046 const char **names
;
15052 if ((sizeflag
& SUFFIX_ALWAYS
)
15053 && (bytemode
== b_swap_mode
15054 || bytemode
== bnd_swap_mode
15055 || bytemode
== v_swap_mode
))
15081 names
= address_mode
== mode_64bit
? names64
: names32
;
15084 case bnd_swap_mode
:
15093 if (address_mode
== mode_64bit
&& isa64
== intel64
)
15098 /* Fall through. */
15100 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15106 /* Fall through. */
15118 if ((sizeflag
& DFLAG
)
15119 || (bytemode
!= v_mode
15120 && bytemode
!= v_swap_mode
))
15124 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15134 names
= names_mask
;
15139 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15142 oappend (names
[reg
]);
15146 OP_E_memory (int bytemode
, int sizeflag
)
15149 int add
= (rex
& REX_B
) ? 8 : 0;
15155 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15157 && bytemode
!= x_mode
15158 && bytemode
!= xmmq_mode
15159 && bytemode
!= evex_half_bcst_xmmq_mode
)
15174 case vex_vsib_d_w_dq_mode
:
15175 case vex_vsib_d_w_d_mode
:
15176 case vex_vsib_q_w_dq_mode
:
15177 case vex_vsib_q_w_d_mode
:
15178 case evex_x_gscat_mode
:
15180 shift
= vex
.w
? 3 : 2;
15183 case evex_half_bcst_xmmq_mode
:
15187 shift
= vex
.w
? 3 : 2;
15190 /* Fall through. */
15194 case evex_x_nobcst_mode
:
15196 switch (vex
.length
)
15219 case q_scalar_mode
:
15221 case q_scalar_swap_mode
:
15227 case d_scalar_mode
:
15229 case d_scalar_swap_mode
:
15232 case w_scalar_mode
:
15236 case b_scalar_mode
:
15243 /* Make necessary corrections to shift for modes that need it.
15244 For these modes we currently have shift 4, 5 or 6 depending on
15245 vex.length (it corresponds to xmmword, ymmword or zmmword
15246 operand). We might want to make it 3, 4 or 5 (e.g. for
15247 xmmq_mode). In case of broadcast enabled the corrections
15248 aren't needed, as element size is always 32 or 64 bits. */
15250 && (bytemode
== xmmq_mode
15251 || bytemode
== evex_half_bcst_xmmq_mode
))
15253 else if (bytemode
== xmmqd_mode
)
15255 else if (bytemode
== xmmdw_mode
)
15257 else if (bytemode
== ymmq_mode
&& vex
.length
== 128)
15265 intel_operand_size (bytemode
, sizeflag
);
15268 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15270 /* 32/64 bit address mode */
15279 int addr32flag
= !((sizeflag
& AFLAG
)
15280 || bytemode
== v_bnd_mode
15281 || bytemode
== bnd_mode
15282 || bytemode
== bnd_swap_mode
);
15283 const char **indexes64
= names64
;
15284 const char **indexes32
= names32
;
15294 vindex
= sib
.index
;
15300 case vex_vsib_d_w_dq_mode
:
15301 case vex_vsib_d_w_d_mode
:
15302 case vex_vsib_q_w_dq_mode
:
15303 case vex_vsib_q_w_d_mode
:
15313 switch (vex
.length
)
15316 indexes64
= indexes32
= names_xmm
;
15320 || bytemode
== vex_vsib_q_w_dq_mode
15321 || bytemode
== vex_vsib_q_w_d_mode
)
15322 indexes64
= indexes32
= names_ymm
;
15324 indexes64
= indexes32
= names_xmm
;
15328 || bytemode
== vex_vsib_q_w_dq_mode
15329 || bytemode
== vex_vsib_q_w_d_mode
)
15330 indexes64
= indexes32
= names_zmm
;
15332 indexes64
= indexes32
= names_ymm
;
15339 haveindex
= vindex
!= 4;
15346 rbase
= base
+ add
;
15354 if (address_mode
== mode_64bit
&& !havesib
)
15360 FETCH_DATA (the_info
, codep
+ 1);
15362 if ((disp
& 0x80) != 0)
15364 if (vex
.evex
&& shift
> 0)
15372 /* In 32bit mode, we need index register to tell [offset] from
15373 [eiz*1 + offset]. */
15374 needindex
= (havesib
15377 && address_mode
== mode_32bit
);
15378 havedisp
= (havebase
15380 || (havesib
&& (haveindex
|| scale
!= 0)));
15383 if (modrm
.mod
!= 0 || base
== 5)
15385 if (havedisp
|| riprel
)
15386 print_displacement (scratchbuf
, disp
);
15388 print_operand_value (scratchbuf
, 1, disp
);
15389 oappend (scratchbuf
);
15393 oappend (!addr32flag
? "(%rip)" : "(%eip)");
15397 if ((havebase
|| haveindex
|| riprel
)
15398 && (bytemode
!= v_bnd_mode
)
15399 && (bytemode
!= bnd_mode
)
15400 && (bytemode
!= bnd_swap_mode
))
15401 used_prefixes
|= PREFIX_ADDR
;
15403 if (havedisp
|| (intel_syntax
&& riprel
))
15405 *obufp
++ = open_char
;
15406 if (intel_syntax
&& riprel
)
15409 oappend (!addr32flag
? "rip" : "eip");
15413 oappend (address_mode
== mode_64bit
&& !addr32flag
15414 ? names64
[rbase
] : names32
[rbase
]);
15417 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15418 print index to tell base + index from base. */
15422 || (havebase
&& base
!= ESP_REG_NUM
))
15424 if (!intel_syntax
|| havebase
)
15426 *obufp
++ = separator_char
;
15430 oappend (address_mode
== mode_64bit
&& !addr32flag
15431 ? indexes64
[vindex
] : indexes32
[vindex
]);
15433 oappend (address_mode
== mode_64bit
&& !addr32flag
15434 ? index64
: index32
);
15436 *obufp
++ = scale_char
;
15438 sprintf (scratchbuf
, "%d", 1 << scale
);
15439 oappend (scratchbuf
);
15443 && (disp
|| modrm
.mod
!= 0 || base
== 5))
15445 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
15450 else if (modrm
.mod
!= 1 && disp
!= -disp
)
15454 disp
= - (bfd_signed_vma
) disp
;
15458 print_displacement (scratchbuf
, disp
);
15460 print_operand_value (scratchbuf
, 1, disp
);
15461 oappend (scratchbuf
);
15464 *obufp
++ = close_char
;
15467 else if (intel_syntax
)
15469 if (modrm
.mod
!= 0 || base
== 5)
15471 if (!active_seg_prefix
)
15473 oappend (names_seg
[ds_reg
- es_reg
]);
15476 print_operand_value (scratchbuf
, 1, disp
);
15477 oappend (scratchbuf
);
15483 /* 16 bit address mode */
15484 used_prefixes
|= prefixes
& PREFIX_ADDR
;
15491 if ((disp
& 0x8000) != 0)
15496 FETCH_DATA (the_info
, codep
+ 1);
15498 if ((disp
& 0x80) != 0)
15500 if (vex
.evex
&& shift
> 0)
15505 if ((disp
& 0x8000) != 0)
15511 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
15513 print_displacement (scratchbuf
, disp
);
15514 oappend (scratchbuf
);
15517 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
15519 *obufp
++ = open_char
;
15521 oappend (index16
[modrm
.rm
]);
15523 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
15525 if ((bfd_signed_vma
) disp
>= 0)
15530 else if (modrm
.mod
!= 1)
15534 disp
= - (bfd_signed_vma
) disp
;
15537 print_displacement (scratchbuf
, disp
);
15538 oappend (scratchbuf
);
15541 *obufp
++ = close_char
;
15544 else if (intel_syntax
)
15546 if (!active_seg_prefix
)
15548 oappend (names_seg
[ds_reg
- es_reg
]);
15551 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
15552 oappend (scratchbuf
);
15555 if (vex
.evex
&& vex
.b
15556 && (bytemode
== x_mode
15557 || bytemode
== xmmq_mode
15558 || bytemode
== evex_half_bcst_xmmq_mode
))
15561 || bytemode
== xmmq_mode
15562 || bytemode
== evex_half_bcst_xmmq_mode
)
15564 switch (vex
.length
)
15567 oappend ("{1to2}");
15570 oappend ("{1to4}");
15573 oappend ("{1to8}");
15581 switch (vex
.length
)
15584 oappend ("{1to4}");
15587 oappend ("{1to8}");
15590 oappend ("{1to16}");
15600 OP_E (int bytemode
, int sizeflag
)
15602 /* Skip mod/rm byte. */
15606 if (modrm
.mod
== 3)
15607 OP_E_register (bytemode
, sizeflag
);
15609 OP_E_memory (bytemode
, sizeflag
);
15613 OP_G (int bytemode
, int sizeflag
)
15624 oappend (names8rex
[modrm
.reg
+ add
]);
15626 oappend (names8
[modrm
.reg
+ add
]);
15629 oappend (names16
[modrm
.reg
+ add
]);
15634 oappend (names32
[modrm
.reg
+ add
]);
15637 oappend (names64
[modrm
.reg
+ add
]);
15640 if (modrm
.reg
> 0x3)
15645 oappend (names_bnd
[modrm
.reg
]);
15654 oappend (names64
[modrm
.reg
+ add
]);
15657 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
15658 oappend (names32
[modrm
.reg
+ add
]);
15660 oappend (names16
[modrm
.reg
+ add
]);
15661 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15665 if (address_mode
== mode_64bit
)
15666 oappend (names64
[modrm
.reg
+ add
]);
15668 oappend (names32
[modrm
.reg
+ add
]);
15672 if ((modrm
.reg
+ add
) > 0x7)
15677 oappend (names_mask
[modrm
.reg
+ add
]);
15680 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15693 FETCH_DATA (the_info
, codep
+ 8);
15694 a
= *codep
++ & 0xff;
15695 a
|= (*codep
++ & 0xff) << 8;
15696 a
|= (*codep
++ & 0xff) << 16;
15697 a
|= (*codep
++ & 0xffu
) << 24;
15698 b
= *codep
++ & 0xff;
15699 b
|= (*codep
++ & 0xff) << 8;
15700 b
|= (*codep
++ & 0xff) << 16;
15701 b
|= (*codep
++ & 0xffu
) << 24;
15702 x
= a
+ ((bfd_vma
) b
<< 32);
15710 static bfd_signed_vma
15713 bfd_signed_vma x
= 0;
15715 FETCH_DATA (the_info
, codep
+ 4);
15716 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15717 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15718 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15719 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15723 static bfd_signed_vma
15726 bfd_signed_vma x
= 0;
15728 FETCH_DATA (the_info
, codep
+ 4);
15729 x
= *codep
++ & (bfd_signed_vma
) 0xff;
15730 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
15731 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
15732 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
15734 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
15744 FETCH_DATA (the_info
, codep
+ 2);
15745 x
= *codep
++ & 0xff;
15746 x
|= (*codep
++ & 0xff) << 8;
15751 set_op (bfd_vma op
, int riprel
)
15753 op_index
[op_ad
] = op_ad
;
15754 if (address_mode
== mode_64bit
)
15756 op_address
[op_ad
] = op
;
15757 op_riprel
[op_ad
] = riprel
;
15761 /* Mask to get a 32-bit address. */
15762 op_address
[op_ad
] = op
& 0xffffffff;
15763 op_riprel
[op_ad
] = riprel
& 0xffffffff;
15768 OP_REG (int code
, int sizeflag
)
15775 case es_reg
: case ss_reg
: case cs_reg
:
15776 case ds_reg
: case fs_reg
: case gs_reg
:
15777 oappend (names_seg
[code
- es_reg
]);
15789 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15790 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15791 s
= names16
[code
- ax_reg
+ add
];
15793 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15794 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15797 s
= names8rex
[code
- al_reg
+ add
];
15799 s
= names8
[code
- al_reg
];
15801 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
15802 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
15803 if (address_mode
== mode_64bit
15804 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15806 s
= names64
[code
- rAX_reg
+ add
];
15809 code
+= eAX_reg
- rAX_reg
;
15810 /* Fall through. */
15811 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15812 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15815 s
= names64
[code
- eAX_reg
+ add
];
15818 if (sizeflag
& DFLAG
)
15819 s
= names32
[code
- eAX_reg
+ add
];
15821 s
= names16
[code
- eAX_reg
+ add
];
15822 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15826 s
= INTERNAL_DISASSEMBLER_ERROR
;
15833 OP_IMREG (int code
, int sizeflag
)
15845 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
15846 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
15847 s
= names16
[code
- ax_reg
];
15849 case es_reg
: case ss_reg
: case cs_reg
:
15850 case ds_reg
: case fs_reg
: case gs_reg
:
15851 s
= names_seg
[code
- es_reg
];
15853 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
15854 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
15857 s
= names8rex
[code
- al_reg
];
15859 s
= names8
[code
- al_reg
];
15861 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
15862 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
15865 s
= names64
[code
- eAX_reg
];
15868 if (sizeflag
& DFLAG
)
15869 s
= names32
[code
- eAX_reg
];
15871 s
= names16
[code
- eAX_reg
];
15872 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15875 case z_mode_ax_reg
:
15876 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
15880 if (!(rex
& REX_W
))
15881 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15884 s
= INTERNAL_DISASSEMBLER_ERROR
;
15891 OP_I (int bytemode
, int sizeflag
)
15894 bfd_signed_vma mask
= -1;
15899 FETCH_DATA (the_info
, codep
+ 1);
15904 if (address_mode
== mode_64bit
)
15909 /* Fall through. */
15916 if (sizeflag
& DFLAG
)
15926 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15938 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15943 scratchbuf
[0] = '$';
15944 print_operand_value (scratchbuf
+ 1, 1, op
);
15945 oappend_maybe_intel (scratchbuf
);
15946 scratchbuf
[0] = '\0';
15950 OP_I64 (int bytemode
, int sizeflag
)
15953 bfd_signed_vma mask
= -1;
15955 if (address_mode
!= mode_64bit
)
15957 OP_I (bytemode
, sizeflag
);
15964 FETCH_DATA (the_info
, codep
+ 1);
15974 if (sizeflag
& DFLAG
)
15984 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15992 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15997 scratchbuf
[0] = '$';
15998 print_operand_value (scratchbuf
+ 1, 1, op
);
15999 oappend_maybe_intel (scratchbuf
);
16000 scratchbuf
[0] = '\0';
16004 OP_sI (int bytemode
, int sizeflag
)
16012 FETCH_DATA (the_info
, codep
+ 1);
16014 if ((op
& 0x80) != 0)
16016 if (bytemode
== b_T_mode
)
16018 if (address_mode
!= mode_64bit
16019 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
16021 /* The operand-size prefix is overridden by a REX prefix. */
16022 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16030 if (!(rex
& REX_W
))
16032 if (sizeflag
& DFLAG
)
16040 /* The operand-size prefix is overridden by a REX prefix. */
16041 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
16047 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16051 scratchbuf
[0] = '$';
16052 print_operand_value (scratchbuf
+ 1, 1, op
);
16053 oappend_maybe_intel (scratchbuf
);
16057 OP_J (int bytemode
, int sizeflag
)
16061 bfd_vma segment
= 0;
16066 FETCH_DATA (the_info
, codep
+ 1);
16068 if ((disp
& 0x80) != 0)
16072 if (isa64
== amd64
)
16074 if ((sizeflag
& DFLAG
)
16075 || (address_mode
== mode_64bit
16076 && (isa64
!= amd64
|| (rex
& REX_W
))))
16081 if ((disp
& 0x8000) != 0)
16083 /* In 16bit mode, address is wrapped around at 64k within
16084 the same segment. Otherwise, a data16 prefix on a jump
16085 instruction means that the pc is masked to 16 bits after
16086 the displacement is added! */
16088 if ((prefixes
& PREFIX_DATA
) == 0)
16089 segment
= ((start_pc
+ (codep
- start_codep
))
16090 & ~((bfd_vma
) 0xffff));
16092 if (address_mode
!= mode_64bit
16093 || (isa64
== amd64
&& !(rex
& REX_W
)))
16094 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16097 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16100 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
16102 print_operand_value (scratchbuf
, 1, disp
);
16103 oappend (scratchbuf
);
16107 OP_SEG (int bytemode
, int sizeflag
)
16109 if (bytemode
== w_mode
)
16110 oappend (names_seg
[modrm
.reg
]);
16112 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
16116 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
16120 if (sizeflag
& DFLAG
)
16130 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16132 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
16134 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
16135 oappend (scratchbuf
);
16139 OP_OFF (int bytemode
, int sizeflag
)
16143 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16144 intel_operand_size (bytemode
, sizeflag
);
16147 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16154 if (!active_seg_prefix
)
16156 oappend (names_seg
[ds_reg
- es_reg
]);
16160 print_operand_value (scratchbuf
, 1, off
);
16161 oappend (scratchbuf
);
16165 OP_OFF64 (int bytemode
, int sizeflag
)
16169 if (address_mode
!= mode_64bit
16170 || (prefixes
& PREFIX_ADDR
))
16172 OP_OFF (bytemode
, sizeflag
);
16176 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
16177 intel_operand_size (bytemode
, sizeflag
);
16184 if (!active_seg_prefix
)
16186 oappend (names_seg
[ds_reg
- es_reg
]);
16190 print_operand_value (scratchbuf
, 1, off
);
16191 oappend (scratchbuf
);
16195 ptr_reg (int code
, int sizeflag
)
16199 *obufp
++ = open_char
;
16200 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
16201 if (address_mode
== mode_64bit
)
16203 if (!(sizeflag
& AFLAG
))
16204 s
= names32
[code
- eAX_reg
];
16206 s
= names64
[code
- eAX_reg
];
16208 else if (sizeflag
& AFLAG
)
16209 s
= names32
[code
- eAX_reg
];
16211 s
= names16
[code
- eAX_reg
];
16213 *obufp
++ = close_char
;
16218 OP_ESreg (int code
, int sizeflag
)
16224 case 0x6d: /* insw/insl */
16225 intel_operand_size (z_mode
, sizeflag
);
16227 case 0xa5: /* movsw/movsl/movsq */
16228 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16229 case 0xab: /* stosw/stosl */
16230 case 0xaf: /* scasw/scasl */
16231 intel_operand_size (v_mode
, sizeflag
);
16234 intel_operand_size (b_mode
, sizeflag
);
16237 oappend_maybe_intel ("%es:");
16238 ptr_reg (code
, sizeflag
);
16242 OP_DSreg (int code
, int sizeflag
)
16248 case 0x6f: /* outsw/outsl */
16249 intel_operand_size (z_mode
, sizeflag
);
16251 case 0xa5: /* movsw/movsl/movsq */
16252 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16253 case 0xad: /* lodsw/lodsl/lodsq */
16254 intel_operand_size (v_mode
, sizeflag
);
16257 intel_operand_size (b_mode
, sizeflag
);
16260 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16261 default segment register DS is printed. */
16262 if (!active_seg_prefix
)
16263 active_seg_prefix
= PREFIX_DS
;
16265 ptr_reg (code
, sizeflag
);
16269 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16277 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
16279 all_prefixes
[last_lock_prefix
] = 0;
16280 used_prefixes
|= PREFIX_LOCK
;
16285 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
16286 oappend_maybe_intel (scratchbuf
);
16290 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16299 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
16301 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
16302 oappend (scratchbuf
);
16306 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16308 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
16309 oappend_maybe_intel (scratchbuf
);
16313 OP_R (int bytemode
, int sizeflag
)
16315 /* Skip mod/rm byte. */
16318 OP_E_register (bytemode
, sizeflag
);
16322 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16324 int reg
= modrm
.reg
;
16325 const char **names
;
16327 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16328 if (prefixes
& PREFIX_DATA
)
16337 oappend (names
[reg
]);
16341 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16343 int reg
= modrm
.reg
;
16344 const char **names
;
16356 && bytemode
!= xmm_mode
16357 && bytemode
!= xmmq_mode
16358 && bytemode
!= evex_half_bcst_xmmq_mode
16359 && bytemode
!= ymm_mode
16360 && bytemode
!= scalar_mode
)
16362 switch (vex
.length
)
16369 || (bytemode
!= vex_vsib_q_w_dq_mode
16370 && bytemode
!= vex_vsib_q_w_d_mode
))
16382 else if (bytemode
== xmmq_mode
16383 || bytemode
== evex_half_bcst_xmmq_mode
)
16385 switch (vex
.length
)
16398 else if (bytemode
== ymm_mode
)
16402 oappend (names
[reg
]);
16406 OP_EM (int bytemode
, int sizeflag
)
16409 const char **names
;
16411 if (modrm
.mod
!= 3)
16414 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16416 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16417 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16419 OP_E (bytemode
, sizeflag
);
16423 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
16426 /* Skip mod/rm byte. */
16429 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16431 if (prefixes
& PREFIX_DATA
)
16440 oappend (names
[reg
]);
16443 /* cvt* are the only instructions in sse2 which have
16444 both SSE and MMX operands and also have 0x66 prefix
16445 in their opcode. 0x66 was originally used to differentiate
16446 between SSE and MMX instruction(operands). So we have to handle the
16447 cvt* separately using OP_EMC and OP_MXC */
16449 OP_EMC (int bytemode
, int sizeflag
)
16451 if (modrm
.mod
!= 3)
16453 if (intel_syntax
&& bytemode
== v_mode
)
16455 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16456 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16458 OP_E (bytemode
, sizeflag
);
16462 /* Skip mod/rm byte. */
16465 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16466 oappend (names_mm
[modrm
.rm
]);
16470 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16472 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16473 oappend (names_mm
[modrm
.reg
]);
16477 OP_EX (int bytemode
, int sizeflag
)
16480 const char **names
;
16482 /* Skip mod/rm byte. */
16486 if (modrm
.mod
!= 3)
16488 OP_E_memory (bytemode
, sizeflag
);
16503 if ((sizeflag
& SUFFIX_ALWAYS
)
16504 && (bytemode
== x_swap_mode
16505 || bytemode
== d_swap_mode
16506 || bytemode
== d_scalar_swap_mode
16507 || bytemode
== q_swap_mode
16508 || bytemode
== q_scalar_swap_mode
))
16512 && bytemode
!= xmm_mode
16513 && bytemode
!= xmmdw_mode
16514 && bytemode
!= xmmqd_mode
16515 && bytemode
!= xmm_mb_mode
16516 && bytemode
!= xmm_mw_mode
16517 && bytemode
!= xmm_md_mode
16518 && bytemode
!= xmm_mq_mode
16519 && bytemode
!= xmm_mdq_mode
16520 && bytemode
!= xmmq_mode
16521 && bytemode
!= evex_half_bcst_xmmq_mode
16522 && bytemode
!= ymm_mode
16523 && bytemode
!= d_scalar_mode
16524 && bytemode
!= d_scalar_swap_mode
16525 && bytemode
!= q_scalar_mode
16526 && bytemode
!= q_scalar_swap_mode
16527 && bytemode
!= vex_scalar_w_dq_mode
)
16529 switch (vex
.length
)
16544 else if (bytemode
== xmmq_mode
16545 || bytemode
== evex_half_bcst_xmmq_mode
)
16547 switch (vex
.length
)
16560 else if (bytemode
== ymm_mode
)
16564 oappend (names
[reg
]);
16568 OP_MS (int bytemode
, int sizeflag
)
16570 if (modrm
.mod
== 3)
16571 OP_EM (bytemode
, sizeflag
);
16577 OP_XS (int bytemode
, int sizeflag
)
16579 if (modrm
.mod
== 3)
16580 OP_EX (bytemode
, sizeflag
);
16586 OP_M (int bytemode
, int sizeflag
)
16588 if (modrm
.mod
== 3)
16589 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16592 OP_E (bytemode
, sizeflag
);
16596 OP_0f07 (int bytemode
, int sizeflag
)
16598 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
16601 OP_E (bytemode
, sizeflag
);
16604 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16605 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16608 NOP_Fixup1 (int bytemode
, int sizeflag
)
16610 if ((prefixes
& PREFIX_DATA
) != 0
16613 && address_mode
== mode_64bit
))
16614 OP_REG (bytemode
, sizeflag
);
16616 strcpy (obuf
, "nop");
16620 NOP_Fixup2 (int bytemode
, int sizeflag
)
16622 if ((prefixes
& PREFIX_DATA
) != 0
16625 && address_mode
== mode_64bit
))
16626 OP_IMREG (bytemode
, sizeflag
);
16629 static const char *const Suffix3DNow
[] = {
16630 /* 00 */ NULL
, NULL
, NULL
, NULL
,
16631 /* 04 */ NULL
, NULL
, NULL
, NULL
,
16632 /* 08 */ NULL
, NULL
, NULL
, NULL
,
16633 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
16634 /* 10 */ NULL
, NULL
, NULL
, NULL
,
16635 /* 14 */ NULL
, NULL
, NULL
, NULL
,
16636 /* 18 */ NULL
, NULL
, NULL
, NULL
,
16637 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
16638 /* 20 */ NULL
, NULL
, NULL
, NULL
,
16639 /* 24 */ NULL
, NULL
, NULL
, NULL
,
16640 /* 28 */ NULL
, NULL
, NULL
, NULL
,
16641 /* 2C */ NULL
, NULL
, NULL
, NULL
,
16642 /* 30 */ NULL
, NULL
, NULL
, NULL
,
16643 /* 34 */ NULL
, NULL
, NULL
, NULL
,
16644 /* 38 */ NULL
, NULL
, NULL
, NULL
,
16645 /* 3C */ NULL
, NULL
, NULL
, NULL
,
16646 /* 40 */ NULL
, NULL
, NULL
, NULL
,
16647 /* 44 */ NULL
, NULL
, NULL
, NULL
,
16648 /* 48 */ NULL
, NULL
, NULL
, NULL
,
16649 /* 4C */ NULL
, NULL
, NULL
, NULL
,
16650 /* 50 */ NULL
, NULL
, NULL
, NULL
,
16651 /* 54 */ NULL
, NULL
, NULL
, NULL
,
16652 /* 58 */ NULL
, NULL
, NULL
, NULL
,
16653 /* 5C */ NULL
, NULL
, NULL
, NULL
,
16654 /* 60 */ NULL
, NULL
, NULL
, NULL
,
16655 /* 64 */ NULL
, NULL
, NULL
, NULL
,
16656 /* 68 */ NULL
, NULL
, NULL
, NULL
,
16657 /* 6C */ NULL
, NULL
, NULL
, NULL
,
16658 /* 70 */ NULL
, NULL
, NULL
, NULL
,
16659 /* 74 */ NULL
, NULL
, NULL
, NULL
,
16660 /* 78 */ NULL
, NULL
, NULL
, NULL
,
16661 /* 7C */ NULL
, NULL
, NULL
, NULL
,
16662 /* 80 */ NULL
, NULL
, NULL
, NULL
,
16663 /* 84 */ NULL
, NULL
, NULL
, NULL
,
16664 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
16665 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
16666 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
16667 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
16668 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
16669 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
16670 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
16671 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
16672 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
16673 /* AC */ NULL
, NULL
, "pfacc", NULL
,
16674 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
16675 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
16676 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
16677 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
16678 /* C0 */ NULL
, NULL
, NULL
, NULL
,
16679 /* C4 */ NULL
, NULL
, NULL
, NULL
,
16680 /* C8 */ NULL
, NULL
, NULL
, NULL
,
16681 /* CC */ NULL
, NULL
, NULL
, NULL
,
16682 /* D0 */ NULL
, NULL
, NULL
, NULL
,
16683 /* D4 */ NULL
, NULL
, NULL
, NULL
,
16684 /* D8 */ NULL
, NULL
, NULL
, NULL
,
16685 /* DC */ NULL
, NULL
, NULL
, NULL
,
16686 /* E0 */ NULL
, NULL
, NULL
, NULL
,
16687 /* E4 */ NULL
, NULL
, NULL
, NULL
,
16688 /* E8 */ NULL
, NULL
, NULL
, NULL
,
16689 /* EC */ NULL
, NULL
, NULL
, NULL
,
16690 /* F0 */ NULL
, NULL
, NULL
, NULL
,
16691 /* F4 */ NULL
, NULL
, NULL
, NULL
,
16692 /* F8 */ NULL
, NULL
, NULL
, NULL
,
16693 /* FC */ NULL
, NULL
, NULL
, NULL
,
16697 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16699 const char *mnemonic
;
16701 FETCH_DATA (the_info
, codep
+ 1);
16702 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16703 place where an 8-bit immediate would normally go. ie. the last
16704 byte of the instruction. */
16705 obufp
= mnemonicendp
;
16706 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
16708 oappend (mnemonic
);
16711 /* Since a variable sized modrm/sib chunk is between the start
16712 of the opcode (0x0f0f) and the opcode suffix, we need to do
16713 all the modrm processing first, and don't know until now that
16714 we have a bad opcode. This necessitates some cleaning up. */
16715 op_out
[0][0] = '\0';
16716 op_out
[1][0] = '\0';
16719 mnemonicendp
= obufp
;
16722 static struct op simd_cmp_op
[] =
16724 { STRING_COMMA_LEN ("eq") },
16725 { STRING_COMMA_LEN ("lt") },
16726 { STRING_COMMA_LEN ("le") },
16727 { STRING_COMMA_LEN ("unord") },
16728 { STRING_COMMA_LEN ("neq") },
16729 { STRING_COMMA_LEN ("nlt") },
16730 { STRING_COMMA_LEN ("nle") },
16731 { STRING_COMMA_LEN ("ord") }
16735 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16737 unsigned int cmp_type
;
16739 FETCH_DATA (the_info
, codep
+ 1);
16740 cmp_type
= *codep
++ & 0xff;
16741 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
16744 char *p
= mnemonicendp
- 2;
16748 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16749 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16753 /* We have a reserved extension byte. Output it directly. */
16754 scratchbuf
[0] = '$';
16755 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16756 oappend_maybe_intel (scratchbuf
);
16757 scratchbuf
[0] = '\0';
16762 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED
,
16763 int sizeflag ATTRIBUTE_UNUSED
)
16765 /* mwaitx %eax,%ecx,%ebx */
16768 const char **names
= (address_mode
== mode_64bit
16769 ? names64
: names32
);
16770 strcpy (op_out
[0], names
[0]);
16771 strcpy (op_out
[1], names
[1]);
16772 strcpy (op_out
[2], names
[3]);
16773 two_source_ops
= 1;
16775 /* Skip mod/rm byte. */
16781 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
16782 int sizeflag ATTRIBUTE_UNUSED
)
16784 /* mwait %eax,%ecx */
16787 const char **names
= (address_mode
== mode_64bit
16788 ? names64
: names32
);
16789 strcpy (op_out
[0], names
[0]);
16790 strcpy (op_out
[1], names
[1]);
16791 two_source_ops
= 1;
16793 /* Skip mod/rm byte. */
16799 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
16800 int sizeflag ATTRIBUTE_UNUSED
)
16802 /* monitor %eax,%ecx,%edx" */
16805 const char **op1_names
;
16806 const char **names
= (address_mode
== mode_64bit
16807 ? names64
: names32
);
16809 if (!(prefixes
& PREFIX_ADDR
))
16810 op1_names
= (address_mode
== mode_16bit
16811 ? names16
: names
);
16814 /* Remove "addr16/addr32". */
16815 all_prefixes
[last_addr_prefix
] = 0;
16816 op1_names
= (address_mode
!= mode_32bit
16817 ? names32
: names16
);
16818 used_prefixes
|= PREFIX_ADDR
;
16820 strcpy (op_out
[0], op1_names
[0]);
16821 strcpy (op_out
[1], names
[1]);
16822 strcpy (op_out
[2], names
[2]);
16823 two_source_ops
= 1;
16825 /* Skip mod/rm byte. */
16833 /* Throw away prefixes and 1st. opcode byte. */
16834 codep
= insn_codep
+ 1;
16839 REP_Fixup (int bytemode
, int sizeflag
)
16841 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16843 if (prefixes
& PREFIX_REPZ
)
16844 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
16851 OP_IMREG (bytemode
, sizeflag
);
16854 OP_ESreg (bytemode
, sizeflag
);
16857 OP_DSreg (bytemode
, sizeflag
);
16865 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16869 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16871 if (prefixes
& PREFIX_REPNZ
)
16872 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
16875 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16879 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16880 int sizeflag ATTRIBUTE_UNUSED
)
16882 if (active_seg_prefix
== PREFIX_DS
16883 && (address_mode
!= mode_64bit
|| last_data_prefix
< 0))
16885 /* NOTRACK prefix is only valid on indirect branch instructions.
16886 NB: DATA prefix is unsupported for Intel64. */
16887 active_seg_prefix
= 0;
16888 all_prefixes
[last_seg_prefix
] = NOTRACK_PREFIX
;
16892 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16893 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16897 HLE_Fixup1 (int bytemode
, int sizeflag
)
16900 && (prefixes
& PREFIX_LOCK
) != 0)
16902 if (prefixes
& PREFIX_REPZ
)
16903 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16904 if (prefixes
& PREFIX_REPNZ
)
16905 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16908 OP_E (bytemode
, sizeflag
);
16911 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16912 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16916 HLE_Fixup2 (int bytemode
, int sizeflag
)
16918 if (modrm
.mod
!= 3)
16920 if (prefixes
& PREFIX_REPZ
)
16921 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16922 if (prefixes
& PREFIX_REPNZ
)
16923 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16926 OP_E (bytemode
, sizeflag
);
16929 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16930 "xrelease" for memory operand. No check for LOCK prefix. */
16933 HLE_Fixup3 (int bytemode
, int sizeflag
)
16936 && last_repz_prefix
> last_repnz_prefix
16937 && (prefixes
& PREFIX_REPZ
) != 0)
16938 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16940 OP_E (bytemode
, sizeflag
);
16944 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
16949 /* Change cmpxchg8b to cmpxchg16b. */
16950 char *p
= mnemonicendp
- 2;
16951 mnemonicendp
= stpcpy (p
, "16b");
16954 else if ((prefixes
& PREFIX_LOCK
) != 0)
16956 if (prefixes
& PREFIX_REPZ
)
16957 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
16958 if (prefixes
& PREFIX_REPNZ
)
16959 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
16962 OP_M (bytemode
, sizeflag
);
16966 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
16968 const char **names
;
16972 switch (vex
.length
)
16986 oappend (names
[reg
]);
16990 CRC32_Fixup (int bytemode
, int sizeflag
)
16992 /* Add proper suffix to "crc32". */
16993 char *p
= mnemonicendp
;
17012 if (sizeflag
& DFLAG
)
17016 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17020 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17027 if (modrm
.mod
== 3)
17031 /* Skip mod/rm byte. */
17036 add
= (rex
& REX_B
) ? 8 : 0;
17037 if (bytemode
== b_mode
)
17041 oappend (names8rex
[modrm
.rm
+ add
]);
17043 oappend (names8
[modrm
.rm
+ add
]);
17049 oappend (names64
[modrm
.rm
+ add
]);
17050 else if ((prefixes
& PREFIX_DATA
))
17051 oappend (names16
[modrm
.rm
+ add
]);
17053 oappend (names32
[modrm
.rm
+ add
]);
17057 OP_E (bytemode
, sizeflag
);
17061 FXSAVE_Fixup (int bytemode
, int sizeflag
)
17063 /* Add proper suffix to "fxsave" and "fxrstor". */
17067 char *p
= mnemonicendp
;
17073 OP_M (bytemode
, sizeflag
);
17077 PCMPESTR_Fixup (int bytemode
, int sizeflag
)
17079 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17082 char *p
= mnemonicendp
;
17087 else if (sizeflag
& SUFFIX_ALWAYS
)
17094 OP_EX (bytemode
, sizeflag
);
17097 /* Display the destination register operand for instructions with
17101 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17104 const char **names
;
17112 reg
= vex
.register_specifier
;
17113 if (address_mode
!= mode_64bit
)
17115 else if (vex
.evex
&& !vex
.v
)
17118 if (bytemode
== vex_scalar_mode
)
17120 oappend (names_xmm
[reg
]);
17124 switch (vex
.length
)
17131 case vex_vsib_q_w_dq_mode
:
17132 case vex_vsib_q_w_d_mode
:
17148 names
= names_mask
;
17162 case vex_vsib_q_w_dq_mode
:
17163 case vex_vsib_q_w_d_mode
:
17164 names
= vex
.w
? names_ymm
: names_xmm
;
17173 names
= names_mask
;
17176 /* See PR binutils/20893 for a reproducer. */
17188 oappend (names
[reg
]);
17191 /* Get the VEX immediate byte without moving codep. */
17193 static unsigned char
17194 get_vex_imm8 (int sizeflag
, int opnum
)
17196 int bytes_before_imm
= 0;
17198 if (modrm
.mod
!= 3)
17200 /* There are SIB/displacement bytes. */
17201 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
17203 /* 32/64 bit address mode */
17204 int base
= modrm
.rm
;
17206 /* Check SIB byte. */
17209 FETCH_DATA (the_info
, codep
+ 1);
17211 /* When decoding the third source, don't increase
17212 bytes_before_imm as this has already been incremented
17213 by one in OP_E_memory while decoding the second
17216 bytes_before_imm
++;
17219 /* Don't increase bytes_before_imm when decoding the third source,
17220 it has already been incremented by OP_E_memory while decoding
17221 the second source operand. */
17227 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17228 SIB == 5, there is a 4 byte displacement. */
17230 /* No displacement. */
17232 /* Fall through. */
17234 /* 4 byte displacement. */
17235 bytes_before_imm
+= 4;
17238 /* 1 byte displacement. */
17239 bytes_before_imm
++;
17246 /* 16 bit address mode */
17247 /* Don't increase bytes_before_imm when decoding the third source,
17248 it has already been incremented by OP_E_memory while decoding
17249 the second source operand. */
17255 /* When modrm.rm == 6, there is a 2 byte displacement. */
17257 /* No displacement. */
17259 /* Fall through. */
17261 /* 2 byte displacement. */
17262 bytes_before_imm
+= 2;
17265 /* 1 byte displacement: when decoding the third source,
17266 don't increase bytes_before_imm as this has already
17267 been incremented by one in OP_E_memory while decoding
17268 the second source operand. */
17270 bytes_before_imm
++;
17278 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
17279 return codep
[bytes_before_imm
];
17283 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
17285 const char **names
;
17287 if (reg
== -1 && modrm
.mod
!= 3)
17289 OP_E_memory (bytemode
, sizeflag
);
17301 if (address_mode
!= mode_64bit
)
17305 switch (vex
.length
)
17316 oappend (names
[reg
]);
17320 OP_EX_VexImmW (int bytemode
, int sizeflag
)
17323 static unsigned char vex_imm8
;
17325 if (vex_w_done
== 0)
17329 /* Skip mod/rm byte. */
17333 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
17336 reg
= vex_imm8
>> 4;
17338 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17340 else if (vex_w_done
== 1)
17345 reg
= vex_imm8
>> 4;
17347 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17351 /* Output the imm8 directly. */
17352 scratchbuf
[0] = '$';
17353 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
17354 oappend_maybe_intel (scratchbuf
);
17355 scratchbuf
[0] = '\0';
17361 OP_Vex_2src (int bytemode
, int sizeflag
)
17363 if (modrm
.mod
== 3)
17365 int reg
= modrm
.rm
;
17369 oappend (names_xmm
[reg
]);
17374 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
17376 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
17377 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17379 OP_E (bytemode
, sizeflag
);
17384 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
17386 if (modrm
.mod
== 3)
17388 /* Skip mod/rm byte. */
17395 unsigned int reg
= vex
.register_specifier
;
17397 if (address_mode
!= mode_64bit
)
17399 oappend (names_xmm
[reg
]);
17402 OP_Vex_2src (bytemode
, sizeflag
);
17406 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
17409 OP_Vex_2src (bytemode
, sizeflag
);
17412 unsigned int reg
= vex
.register_specifier
;
17414 if (address_mode
!= mode_64bit
)
17416 oappend (names_xmm
[reg
]);
17421 OP_EX_VexW (int bytemode
, int sizeflag
)
17427 /* Skip mod/rm byte. */
17432 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
17437 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
17440 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
17448 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17451 const char **names
;
17453 FETCH_DATA (the_info
, codep
+ 1);
17456 if (bytemode
!= x_mode
)
17460 if (address_mode
!= mode_64bit
)
17463 switch (vex
.length
)
17474 oappend (names
[reg
]);
17478 OP_XMM_VexW (int bytemode
, int sizeflag
)
17480 /* Turn off the REX.W bit since it is used for swapping operands
17483 OP_XMM (bytemode
, sizeflag
);
17487 OP_EX_Vex (int bytemode
, int sizeflag
)
17489 if (modrm
.mod
!= 3)
17491 if (vex
.register_specifier
!= 0)
17495 OP_EX (bytemode
, sizeflag
);
17499 OP_XMM_Vex (int bytemode
, int sizeflag
)
17501 if (modrm
.mod
!= 3)
17503 if (vex
.register_specifier
!= 0)
17507 OP_XMM (bytemode
, sizeflag
);
17511 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17513 switch (vex
.length
)
17516 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
17519 mnemonicendp
= stpcpy (obuf
, "vzeroall");
17526 static struct op vex_cmp_op
[] =
17528 { STRING_COMMA_LEN ("eq") },
17529 { STRING_COMMA_LEN ("lt") },
17530 { STRING_COMMA_LEN ("le") },
17531 { STRING_COMMA_LEN ("unord") },
17532 { STRING_COMMA_LEN ("neq") },
17533 { STRING_COMMA_LEN ("nlt") },
17534 { STRING_COMMA_LEN ("nle") },
17535 { STRING_COMMA_LEN ("ord") },
17536 { STRING_COMMA_LEN ("eq_uq") },
17537 { STRING_COMMA_LEN ("nge") },
17538 { STRING_COMMA_LEN ("ngt") },
17539 { STRING_COMMA_LEN ("false") },
17540 { STRING_COMMA_LEN ("neq_oq") },
17541 { STRING_COMMA_LEN ("ge") },
17542 { STRING_COMMA_LEN ("gt") },
17543 { STRING_COMMA_LEN ("true") },
17544 { STRING_COMMA_LEN ("eq_os") },
17545 { STRING_COMMA_LEN ("lt_oq") },
17546 { STRING_COMMA_LEN ("le_oq") },
17547 { STRING_COMMA_LEN ("unord_s") },
17548 { STRING_COMMA_LEN ("neq_us") },
17549 { STRING_COMMA_LEN ("nlt_uq") },
17550 { STRING_COMMA_LEN ("nle_uq") },
17551 { STRING_COMMA_LEN ("ord_s") },
17552 { STRING_COMMA_LEN ("eq_us") },
17553 { STRING_COMMA_LEN ("nge_uq") },
17554 { STRING_COMMA_LEN ("ngt_uq") },
17555 { STRING_COMMA_LEN ("false_os") },
17556 { STRING_COMMA_LEN ("neq_os") },
17557 { STRING_COMMA_LEN ("ge_oq") },
17558 { STRING_COMMA_LEN ("gt_oq") },
17559 { STRING_COMMA_LEN ("true_us") },
17563 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17565 unsigned int cmp_type
;
17567 FETCH_DATA (the_info
, codep
+ 1);
17568 cmp_type
= *codep
++ & 0xff;
17569 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
17572 char *p
= mnemonicendp
- 2;
17576 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
17577 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
17581 /* We have a reserved extension byte. Output it directly. */
17582 scratchbuf
[0] = '$';
17583 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17584 oappend_maybe_intel (scratchbuf
);
17585 scratchbuf
[0] = '\0';
17590 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17591 int sizeflag ATTRIBUTE_UNUSED
)
17593 unsigned int cmp_type
;
17598 FETCH_DATA (the_info
, codep
+ 1);
17599 cmp_type
= *codep
++ & 0xff;
17600 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17601 If it's the case, print suffix, otherwise - print the immediate. */
17602 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
17607 char *p
= mnemonicendp
- 2;
17609 /* vpcmp* can have both one- and two-lettered suffix. */
17623 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
17624 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
17628 /* We have a reserved extension byte. Output it directly. */
17629 scratchbuf
[0] = '$';
17630 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17631 oappend_maybe_intel (scratchbuf
);
17632 scratchbuf
[0] = '\0';
17636 static const struct op xop_cmp_op
[] =
17638 { STRING_COMMA_LEN ("lt") },
17639 { STRING_COMMA_LEN ("le") },
17640 { STRING_COMMA_LEN ("gt") },
17641 { STRING_COMMA_LEN ("ge") },
17642 { STRING_COMMA_LEN ("eq") },
17643 { STRING_COMMA_LEN ("neq") },
17644 { STRING_COMMA_LEN ("false") },
17645 { STRING_COMMA_LEN ("true") }
17649 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17650 int sizeflag ATTRIBUTE_UNUSED
)
17652 unsigned int cmp_type
;
17654 FETCH_DATA (the_info
, codep
+ 1);
17655 cmp_type
= *codep
++ & 0xff;
17656 if (cmp_type
< ARRAY_SIZE (xop_cmp_op
))
17659 char *p
= mnemonicendp
- 2;
17661 /* vpcom* can have both one- and two-lettered suffix. */
17675 sprintf (p
, "%s%s", xop_cmp_op
[cmp_type
].name
, suffix
);
17676 mnemonicendp
+= xop_cmp_op
[cmp_type
].len
;
17680 /* We have a reserved extension byte. Output it directly. */
17681 scratchbuf
[0] = '$';
17682 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
17683 oappend_maybe_intel (scratchbuf
);
17684 scratchbuf
[0] = '\0';
17688 static const struct op pclmul_op
[] =
17690 { STRING_COMMA_LEN ("lql") },
17691 { STRING_COMMA_LEN ("hql") },
17692 { STRING_COMMA_LEN ("lqh") },
17693 { STRING_COMMA_LEN ("hqh") }
17697 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
17698 int sizeflag ATTRIBUTE_UNUSED
)
17700 unsigned int pclmul_type
;
17702 FETCH_DATA (the_info
, codep
+ 1);
17703 pclmul_type
= *codep
++ & 0xff;
17704 switch (pclmul_type
)
17715 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
17718 char *p
= mnemonicendp
- 3;
17723 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
17724 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
17728 /* We have a reserved extension byte. Output it directly. */
17729 scratchbuf
[0] = '$';
17730 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
17731 oappend_maybe_intel (scratchbuf
);
17732 scratchbuf
[0] = '\0';
17737 MOVBE_Fixup (int bytemode
, int sizeflag
)
17739 /* Add proper suffix to "movbe". */
17740 char *p
= mnemonicendp
;
17749 if (sizeflag
& SUFFIX_ALWAYS
)
17755 if (sizeflag
& DFLAG
)
17759 used_prefixes
|= (prefixes
& PREFIX_DATA
);
17764 oappend (INTERNAL_DISASSEMBLER_ERROR
);
17771 OP_M (bytemode
, sizeflag
);
17775 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17778 const char **names
;
17780 /* Skip mod/rm byte. */
17794 oappend (names
[reg
]);
17798 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
17800 const char **names
;
17801 unsigned int reg
= vex
.register_specifier
;
17808 if (address_mode
!= mode_64bit
)
17810 oappend (names
[reg
]);
17814 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17817 || (bytemode
!= mask_mode
&& bytemode
!= mask_bd_mode
))
17821 if ((rex
& REX_R
) != 0 || !vex
.r
)
17827 oappend (names_mask
[modrm
.reg
]);
17831 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
17834 || (bytemode
!= evex_rounding_mode
17835 && bytemode
!= evex_sae_mode
))
17837 if (modrm
.mod
== 3 && vex
.b
)
17840 case evex_rounding_mode
:
17841 oappend (names_rounding
[vex
.ll
]);
17843 case evex_sae_mode
: