opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VZERO_Fixup (int, int);
  99 static void VCMP_Fixup (int, int);
 100 static void VPCMP_Fixup (int, int);
 101 static void VPCOM_Fixup (int, int);
 102 static void OP_0f07 (int, int);
 103 static void OP_Monitor (int, int);
 104 static void OP_Mwait (int, int);
 105 static void OP_Mwaitx (int, int);
 106 static void NOP_Fixup1 (int, int);
 107 static void NOP_Fixup2 (int, int);
 108 static void OP_3DNowSuffix (int, int);
 109 static void CMP_Fixup (int, int);
 110 static void BadOp (void);
 111 static void REP_Fixup (int, int);
 112 static void BND_Fixup (int, int);
 113 static void NOTRACK_Fixup (int, int);
 114 static void HLE_Fixup1 (int, int);
 115 static void HLE_Fixup2 (int, int);
 116 static void HLE_Fixup3 (int, int);
 117 static void CMPXCHG8B_Fixup (int, int);
 118 static void XMM_Fixup (int, int);
 119 static void CRC32_Fixup (int, int);
 120 static void FXSAVE_Fixup (int, int);
 121 static void PCMPESTR_Fixup (int, int);
 122 static void OP_LWPCB_E (int, int);
 123 static void OP_LWP_E (int, int);
 124 static void OP_Vex_2src_1 (int, int);
 125 static void OP_Vex_2src_2 (int, int);
 126
 127 static void MOVBE_Fixup (int, int);
 128
 129 static void OP_Mask (int, int);
 130
 131 struct dis_private {
 132   /* Points to first byte not fetched.  */
 133   bfd_byte *max_fetched;
 134   bfd_byte the_buffer[MAX_MNEM_SIZE];
 135   bfd_vma insn_start;
 136   int orig_sizeflag;
 137   OPCODES_SIGJMP_BUF bailout;
 138 };
 139
 140 enum address_mode
 141 {
 142   mode_16bit,
 143   mode_32bit,
 144   mode_64bit
 145 };
 146
 147 enum address_mode address_mode;
 148
 149 /* Flags for the prefixes for the current instruction.  See below.  */
 150 static int prefixes;
 151
 152 /* REX prefix the current instruction.  See below.  */
 153 static int rex;
 154 /* Bits of REX we've already used.  */
 155 static int rex_used;
 156 /* REX bits in original REX prefix ignored.  */
 157 static int rex_ignored;
 158 /* Mark parts used in the REX prefix.  When we are testing for
 159    empty prefix (for 8bit register REX extension), just mask it
 160    out.  Otherwise test for REX bit is excuse for existence of REX
 161    only in case value is nonzero.  */
 162 #define USED_REX(value)                                 \
 163   {                                                     \
 164     if (value)                                          \
 165       {                                                 \
 166         if ((rex & value))                              \
 167           rex_used |= (value) | REX_OPCODE;             \
 168       }                                                 \
 169     else                                                \
 170       rex_used |= REX_OPCODE;                           \
 171   }
 172
 173 /* Flags for prefixes which we somehow handled when printing the
 174    current instruction.  */
 175 static int used_prefixes;
 176
 177 /* Flags stored in PREFIXES.  */
 178 #define PREFIX_REPZ 1
 179 #define PREFIX_REPNZ 2
 180 #define PREFIX_LOCK 4
 181 #define PREFIX_CS 8
 182 #define PREFIX_SS 0x10
 183 #define PREFIX_DS 0x20
 184 #define PREFIX_ES 0x40
 185 #define PREFIX_FS 0x80
 186 #define PREFIX_GS 0x100
 187 #define PREFIX_DATA 0x200
 188 #define PREFIX_ADDR 0x400
 189 #define PREFIX_FWAIT 0x800
 190
 191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 192    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 193    on error.  */
 194 #define FETCH_DATA(info, addr) \
 195   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 196    ? 1 : fetch_data ((info), (addr)))
 197
 198 static int
 199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 200 {
 201   int status;
 202   struct dis_private *priv = (struct dis_private *) info->private_data;
 203   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 204
 205   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 206     status = (*info->read_memory_func) (start,
 207                                         priv->max_fetched,
 208                                         addr - priv->max_fetched,
 209                                         info);
 210   else
 211     status = -1;
 212   if (status != 0)
 213     {
 214       /* If we did manage to read at least one byte, then
 215          print_insn_i386 will do something sensible.  Otherwise, print
 216          an error.  We do that here because this is where we know
 217          STATUS.  */
 218       if (priv->max_fetched == priv->the_buffer)
 219         (*info->memory_error_func) (status, start, info);
 220       OPCODES_SIGLONGJMP (priv->bailout, 1);
 221     }
 222   else
 223     priv->max_fetched = addr;
 224   return 1;
 225 }
 226
 227 /* Possible values for prefix requirement.  */
 228 #define PREFIX_IGNORED_SHIFT    16
 229 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 233 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 234
 235 /* Opcode prefixes.  */
 236 #define PREFIX_OPCODE           (PREFIX_REPZ \
 237                                  | PREFIX_REPNZ \
 238                                  | PREFIX_DATA)
 239
 240 /* Prefixes ignored.  */
 241 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 242                                  | PREFIX_IGNORED_REPNZ \
 243                                  | PREFIX_IGNORED_DATA)
 244
 245 #define XX { NULL, 0 }
 246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 247
 248 #define Eb { OP_E, b_mode }
 249 #define Ebnd { OP_E, bnd_mode }
 250 #define EbS { OP_E, b_swap_mode }
 251 #define EbndS { OP_E, bnd_swap_mode }
 252 #define Ev { OP_E, v_mode }
 253 #define Eva { OP_E, va_mode }
 254 #define Ev_bnd { OP_E, v_bnd_mode }
 255 #define EvS { OP_E, v_swap_mode }
 256 #define Ed { OP_E, d_mode }
 257 #define Edq { OP_E, dq_mode }
 258 #define Edqw { OP_E, dqw_mode }
 259 #define Edqb { OP_E, dqb_mode }
 260 #define Edb { OP_E, db_mode }
 261 #define Edw { OP_E, dw_mode }
 262 #define Edqd { OP_E, dqd_mode }
 263 #define Eq { OP_E, q_mode }
 264 #define indirEv { OP_indirE, indir_v_mode }
 265 #define indirEp { OP_indirE, f_mode }
 266 #define stackEv { OP_E, stack_v_mode }
 267 #define Em { OP_E, m_mode }
 268 #define Ew { OP_E, w_mode }
 269 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 270 #define Ma { OP_M, a_mode }
 271 #define Mb { OP_M, b_mode }
 272 #define Md { OP_M, d_mode }
 273 #define Mo { OP_M, o_mode }
 274 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 275 #define Mq { OP_M, q_mode }
 276 #define Mv_bnd { OP_M, v_bndmk_mode }
 277 #define Mx { OP_M, x_mode }
 278 #define Mxmm { OP_M, xmm_mode }
 279 #define Gb { OP_G, b_mode }
 280 #define Gbnd { OP_G, bnd_mode }
 281 #define Gv { OP_G, v_mode }
 282 #define Gd { OP_G, d_mode }
 283 #define Gdq { OP_G, dq_mode }
 284 #define Gm { OP_G, m_mode }
 285 #define Gva { OP_G, va_mode }
 286 #define Gw { OP_G, w_mode }
 287 #define Rd { OP_R, d_mode }
 288 #define Rdq { OP_R, dq_mode }
 289 #define Rm { OP_R, m_mode }
 290 #define Ib { OP_I, b_mode }
 291 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 293 #define Iv { OP_I, v_mode }
 294 #define sIv { OP_sI, v_mode }
 295 #define Iq { OP_I, q_mode }
 296 #define Iv64 { OP_I64, v_mode }
 297 #define Iw { OP_I, w_mode }
 298 #define I1 { OP_I, const_1_mode }
 299 #define Jb { OP_J, b_mode }
 300 #define Jv { OP_J, v_mode }
 301 #define Cm { OP_C, m_mode }
 302 #define Dm { OP_D, m_mode }
 303 #define Td { OP_T, d_mode }
 304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 305
 306 #define RMeAX { OP_REG, eAX_reg }
 307 #define RMeBX { OP_REG, eBX_reg }
 308 #define RMeCX { OP_REG, eCX_reg }
 309 #define RMeDX { OP_REG, eDX_reg }
 310 #define RMeSP { OP_REG, eSP_reg }
 311 #define RMeBP { OP_REG, eBP_reg }
 312 #define RMeSI { OP_REG, eSI_reg }
 313 #define RMeDI { OP_REG, eDI_reg }
 314 #define RMrAX { OP_REG, rAX_reg }
 315 #define RMrBX { OP_REG, rBX_reg }
 316 #define RMrCX { OP_REG, rCX_reg }
 317 #define RMrDX { OP_REG, rDX_reg }
 318 #define RMrSP { OP_REG, rSP_reg }
 319 #define RMrBP { OP_REG, rBP_reg }
 320 #define RMrSI { OP_REG, rSI_reg }
 321 #define RMrDI { OP_REG, rDI_reg }
 322 #define RMAL { OP_REG, al_reg }
 323 #define RMCL { OP_REG, cl_reg }
 324 #define RMDL { OP_REG, dl_reg }
 325 #define RMBL { OP_REG, bl_reg }
 326 #define RMAH { OP_REG, ah_reg }
 327 #define RMCH { OP_REG, ch_reg }
 328 #define RMDH { OP_REG, dh_reg }
 329 #define RMBH { OP_REG, bh_reg }
 330 #define RMAX { OP_REG, ax_reg }
 331 #define RMDX { OP_REG, dx_reg }
 332
 333 #define eAX { OP_IMREG, eAX_reg }
 334 #define eBX { OP_IMREG, eBX_reg }
 335 #define eCX { OP_IMREG, eCX_reg }
 336 #define eDX { OP_IMREG, eDX_reg }
 337 #define eSP { OP_IMREG, eSP_reg }
 338 #define eBP { OP_IMREG, eBP_reg }
 339 #define eSI { OP_IMREG, eSI_reg }
 340 #define eDI { OP_IMREG, eDI_reg }
 341 #define AL { OP_IMREG, al_reg }
 342 #define CL { OP_IMREG, cl_reg }
 343 #define DL { OP_IMREG, dl_reg }
 344 #define BL { OP_IMREG, bl_reg }
 345 #define AH { OP_IMREG, ah_reg }
 346 #define CH { OP_IMREG, ch_reg }
 347 #define DH { OP_IMREG, dh_reg }
 348 #define BH { OP_IMREG, bh_reg }
 349 #define AX { OP_IMREG, ax_reg }
 350 #define DX { OP_IMREG, dx_reg }
 351 #define zAX { OP_IMREG, z_mode_ax_reg }
 352 #define indirDX { OP_IMREG, indir_dx_reg }
 353
 354 #define Sw { OP_SEG, w_mode }
 355 #define Sv { OP_SEG, v_mode }
 356 #define Ap { OP_DIR, 0 }
 357 #define Ob { OP_OFF64, b_mode }
 358 #define Ov { OP_OFF64, v_mode }
 359 #define Xb { OP_DSreg, eSI_reg }
 360 #define Xv { OP_DSreg, eSI_reg }
 361 #define Xz { OP_DSreg, eSI_reg }
 362 #define Yb { OP_ESreg, eDI_reg }
 363 #define Yv { OP_ESreg, eDI_reg }
 364 #define DSBX { OP_DSreg, eBX_reg }
 365
 366 #define es { OP_REG, es_reg }
 367 #define ss { OP_REG, ss_reg }
 368 #define cs { OP_REG, cs_reg }
 369 #define ds { OP_REG, ds_reg }
 370 #define fs { OP_REG, fs_reg }
 371 #define gs { OP_REG, gs_reg }
 372
 373 #define MX { OP_MMX, 0 }
 374 #define XM { OP_XMM, 0 }
 375 #define XMScalar { OP_XMM, scalar_mode }
 376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 377 #define XMM { OP_XMM, xmm_mode }
 378 #define XMxmmq { OP_XMM, xmmq_mode }
 379 #define EM { OP_EM, v_mode }
 380 #define EMS { OP_EM, v_swap_mode }
 381 #define EMd { OP_EM, d_mode }
 382 #define EMx { OP_EM, x_mode }
 383 #define EXbScalar { OP_EX, b_scalar_mode }
 384 #define EXw { OP_EX, w_mode }
 385 #define EXwScalar { OP_EX, w_scalar_mode }
 386 #define EXd { OP_EX, d_mode }
 387 #define EXdScalar { OP_EX, d_scalar_mode }
 388 #define EXdS { OP_EX, d_swap_mode }
 389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
 390 #define EXq { OP_EX, q_mode }
 391 #define EXqScalar { OP_EX, q_scalar_mode }
 392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 393 #define EXqS { OP_EX, q_swap_mode }
 394 #define EXx { OP_EX, x_mode }
 395 #define EXxS { OP_EX, x_swap_mode }
 396 #define EXxmm { OP_EX, xmm_mode }
 397 #define EXymm { OP_EX, ymm_mode }
 398 #define EXxmmq { OP_EX, xmmq_mode }
 399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 402 #define EXxmm_md { OP_EX, xmm_md_mode }
 403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 405 #define EXxmmdw { OP_EX, xmmdw_mode }
 406 #define EXxmmqd { OP_EX, xmmqd_mode }
 407 #define EXymmq { OP_EX, ymmq_mode }
 408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 412 #define MS { OP_MS, v_mode }
 413 #define XS { OP_XS, v_mode }
 414 #define EMCq { OP_EMC, q_mode }
 415 #define MXC { OP_MXC, 0 }
 416 #define OPSUF { OP_3DNowSuffix, 0 }
 417 #define CMP { CMP_Fixup, 0 }
 418 #define XMM0 { XMM_Fixup, 0 }
 419 #define FXSAVE { FXSAVE_Fixup, 0 }
 420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 422
 423 #define Vex { OP_VEX, vex_mode }
 424 #define VexScalar { OP_VEX, vex_scalar_mode }
 425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 426 #define Vex128 { OP_VEX, vex128_mode }
 427 #define Vex256 { OP_VEX, vex256_mode }
 428 #define VexGdq { OP_VEX, dq_mode }
 429 #define EXdVex { OP_EX_Vex, d_mode }
 430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
 431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 432 #define EXqVex { OP_EX_Vex, q_mode }
 433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
 434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 435 #define EXVexW { OP_EX_VexW, x_mode }
 436 #define EXdVexW { OP_EX_VexW, d_mode }
 437 #define EXqVexW { OP_EX_VexW, q_mode }
 438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 439 #define XMVex { OP_XMM_Vex, 0 }
 440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 441 #define XMVexW { OP_XMM_VexW, 0 }
 442 #define XMVexI4 { OP_REG_VexI4, x_mode }
 443 #define PCLMUL { PCLMUL_Fixup, 0 }
 444 #define VZERO { VZERO_Fixup, 0 }
 445 #define VCMP { VCMP_Fixup, 0 }
 446 #define VPCMP { VPCMP_Fixup, 0 }
 447 #define VPCOM { VPCOM_Fixup, 0 }
 448
 449 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 451
 452 #define XMask { OP_Mask, mask_mode }
 453 #define MaskG { OP_G, mask_mode }
 454 #define MaskE { OP_E, mask_mode }
 455 #define MaskBDE { OP_E, mask_bd_mode }
 456 #define MaskR { OP_R, mask_mode }
 457 #define MaskVex { OP_VEX, mask_mode }
 458
 459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 463
 464 /* Used handle "rep" prefix for string instructions.  */
 465 #define Xbr { REP_Fixup, eSI_reg }
 466 #define Xvr { REP_Fixup, eSI_reg }
 467 #define Ybr { REP_Fixup, eDI_reg }
 468 #define Yvr { REP_Fixup, eDI_reg }
 469 #define Yzr { REP_Fixup, eDI_reg }
 470 #define indirDXr { REP_Fixup, indir_dx_reg }
 471 #define ALr { REP_Fixup, al_reg }
 472 #define eAXr { REP_Fixup, eAX_reg }
 473
 474 /* Used handle HLE prefix for lockable instructions.  */
 475 #define Ebh1 { HLE_Fixup1, b_mode }
 476 #define Evh1 { HLE_Fixup1, v_mode }
 477 #define Ebh2 { HLE_Fixup2, b_mode }
 478 #define Evh2 { HLE_Fixup2, v_mode }
 479 #define Ebh3 { HLE_Fixup3, b_mode }
 480 #define Evh3 { HLE_Fixup3, v_mode }
 481
 482 #define BND { BND_Fixup, 0 }
 483 #define NOTRACK { NOTRACK_Fixup, 0 }
 484
 485 #define cond_jump_flag { NULL, cond_jump_mode }
 486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 487
 488 /* bits in sizeflag */
 489 #define SUFFIX_ALWAYS 4
 490 #define AFLAG 2
 491 #define DFLAG 1
 492
 493 enum
 494 {
 495   /* byte operand */
 496   b_mode = 1,
 497   /* byte operand with operand swapped */
 498   b_swap_mode,
 499   /* byte operand, sign extend like 'T' suffix */
 500   b_T_mode,
 501   /* operand size depends on prefixes */
 502   v_mode,
 503   /* operand size depends on prefixes with operand swapped */
 504   v_swap_mode,
 505   /* operand size depends on address prefix */
 506   va_mode,
 507   /* word operand */
 508   w_mode,
 509   /* double word operand  */
 510   d_mode,
 511   /* double word operand with operand swapped */
 512   d_swap_mode,
 513   /* quad word operand */
 514   q_mode,
 515   /* quad word operand with operand swapped */
 516   q_swap_mode,
 517   /* ten-byte operand */
 518   t_mode,
 519   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 520      broadcast enabled.  */
 521   x_mode,
 522   /* Similar to x_mode, but with different EVEX mem shifts.  */
 523   evex_x_gscat_mode,
 524   /* Similar to x_mode, but with disabled broadcast.  */
 525   evex_x_nobcst_mode,
 526   /* Similar to x_mode, but with operands swapped and disabled broadcast
 527      in EVEX.  */
 528   x_swap_mode,
 529   /* 16-byte XMM operand */
 530   xmm_mode,
 531   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 532      memory operand (depending on vector length).  Broadcast isn't
 533      allowed.  */
 534   xmmq_mode,
 535   /* Same as xmmq_mode, but broadcast is allowed.  */
 536   evex_half_bcst_xmmq_mode,
 537   /* XMM register or byte memory operand */
 538   xmm_mb_mode,
 539   /* XMM register or word memory operand */
 540   xmm_mw_mode,
 541   /* XMM register or double word memory operand */
 542   xmm_md_mode,
 543   /* XMM register or quad word memory operand */
 544   xmm_mq_mode,
 545   /* XMM register or double/quad word memory operand, depending on
 546      VEX.W.  */
 547   xmm_mdq_mode,
 548   /* 16-byte XMM, word, double word or quad word operand.  */
 549   xmmdw_mode,
 550   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 551   xmmqd_mode,
 552   /* 32-byte YMM operand */
 553   ymm_mode,
 554   /* quad word, ymmword or zmmword memory operand.  */
 555   ymmq_mode,
 556   /* 32-byte YMM or 16-byte word operand */
 557   ymmxmm_mode,
 558   /* d_mode in 32bit, q_mode in 64bit mode.  */
 559   m_mode,
 560   /* pair of v_mode operands */
 561   a_mode,
 562   cond_jump_mode,
 563   loop_jcxz_mode,
 564   v_bnd_mode,
 565   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 566   v_bndmk_mode,
 567   /* operand size depends on REX prefixes.  */
 568   dq_mode,
 569   /* registers like dq_mode, memory like w_mode.  */
 570   dqw_mode,
 571   /* bounds operand */
 572   bnd_mode,
 573   /* bounds operand with operand swapped */
 574   bnd_swap_mode,
 575   /* 4- or 6-byte pointer operand */
 576   f_mode,
 577   const_1_mode,
 578   /* v_mode for indirect branch opcodes.  */
 579   indir_v_mode,
 580   /* v_mode for stack-related opcodes.  */
 581   stack_v_mode,
 582   /* non-quad operand size depends on prefixes */
 583   z_mode,
 584   /* 16-byte operand */
 585   o_mode,
 586   /* registers like dq_mode, memory like b_mode.  */
 587   dqb_mode,
 588   /* registers like d_mode, memory like b_mode.  */
 589   db_mode,
 590   /* registers like d_mode, memory like w_mode.  */
 591   dw_mode,
 592   /* registers like dq_mode, memory like d_mode.  */
 593   dqd_mode,
 594   /* normal vex mode */
 595   vex_mode,
 596   /* 128bit vex mode */
 597   vex128_mode,
 598   /* 256bit vex mode */
 599   vex256_mode,
 600   /* operand size depends on the VEX.W bit.  */
 601   vex_w_dq_mode,
 602
 603   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 604   vex_vsib_d_w_dq_mode,
 605   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 606   vex_vsib_d_w_d_mode,
 607   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 608   vex_vsib_q_w_dq_mode,
 609   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 610   vex_vsib_q_w_d_mode,
 611
 612   /* scalar, ignore vector length.  */
 613   scalar_mode,
 614   /* like b_mode, ignore vector length.  */
 615   b_scalar_mode,
 616   /* like w_mode, ignore vector length.  */
 617   w_scalar_mode,
 618   /* like d_mode, ignore vector length.  */
 619   d_scalar_mode,
 620   /* like d_swap_mode, ignore vector length.  */
 621   d_scalar_swap_mode,
 622   /* like q_mode, ignore vector length.  */
 623   q_scalar_mode,
 624   /* like q_swap_mode, ignore vector length.  */
 625   q_scalar_swap_mode,
 626   /* like vex_mode, ignore vector length.  */
 627   vex_scalar_mode,
 628   /* like vex_w_dq_mode, ignore vector length.  */
 629   vex_scalar_w_dq_mode,
 630
 631   /* Static rounding.  */
 632   evex_rounding_mode,
 633   /* Supress all exceptions.  */
 634   evex_sae_mode,
 635
 636   /* Mask register operand.  */
 637   mask_mode,
 638   /* Mask register operand.  */
 639   mask_bd_mode,
 640
 641   es_reg,
 642   cs_reg,
 643   ss_reg,
 644   ds_reg,
 645   fs_reg,
 646   gs_reg,
 647
 648   eAX_reg,
 649   eCX_reg,
 650   eDX_reg,
 651   eBX_reg,
 652   eSP_reg,
 653   eBP_reg,
 654   eSI_reg,
 655   eDI_reg,
 656
 657   al_reg,
 658   cl_reg,
 659   dl_reg,
 660   bl_reg,
 661   ah_reg,
 662   ch_reg,
 663   dh_reg,
 664   bh_reg,
 665
 666   ax_reg,
 667   cx_reg,
 668   dx_reg,
 669   bx_reg,
 670   sp_reg,
 671   bp_reg,
 672   si_reg,
 673   di_reg,
 674
 675   rAX_reg,
 676   rCX_reg,
 677   rDX_reg,
 678   rBX_reg,
 679   rSP_reg,
 680   rBP_reg,
 681   rSI_reg,
 682   rDI_reg,
 683
 684   z_mode_ax_reg,
 685   indir_dx_reg
 686 };
 687
 688 enum
 689 {
 690   FLOATCODE = 1,
 691   USE_REG_TABLE,
 692   USE_MOD_TABLE,
 693   USE_RM_TABLE,
 694   USE_PREFIX_TABLE,
 695   USE_X86_64_TABLE,
 696   USE_3BYTE_TABLE,
 697   USE_XOP_8F_TABLE,
 698   USE_VEX_C4_TABLE,
 699   USE_VEX_C5_TABLE,
 700   USE_VEX_LEN_TABLE,
 701   USE_VEX_W_TABLE,
 702   USE_EVEX_TABLE
 703 };
 704
 705 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 706
 707 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 708 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 709 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 710 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 711 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 712 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 713 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 714 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 715 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 716 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 717 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 718 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 719 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 720 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 721 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 722
 723 enum
 724 {
 725   REG_80 = 0,
 726   REG_81,
 727   REG_83,
 728   REG_8F,
 729   REG_C0,
 730   REG_C1,
 731   REG_C6,
 732   REG_C7,
 733   REG_D0,
 734   REG_D1,
 735   REG_D2,
 736   REG_D3,
 737   REG_F6,
 738   REG_F7,
 739   REG_FE,
 740   REG_FF,
 741   REG_0F00,
 742   REG_0F01,
 743   REG_0F0D,
 744   REG_0F18,
 745   REG_0F1C_MOD_0,
 746   REG_0F1E_MOD_3,
 747   REG_0F71,
 748   REG_0F72,
 749   REG_0F73,
 750   REG_0FA6,
 751   REG_0FA7,
 752   REG_0FAE,
 753   REG_0FBA,
 754   REG_0FC7,
 755   REG_VEX_0F71,
 756   REG_VEX_0F72,
 757   REG_VEX_0F73,
 758   REG_VEX_0FAE,
 759   REG_VEX_0F38F3,
 760   REG_XOP_LWPCB,
 761   REG_XOP_LWP,
 762   REG_XOP_TBM_01,
 763   REG_XOP_TBM_02,
 764
 765   REG_EVEX_0F71,
 766   REG_EVEX_0F72,
 767   REG_EVEX_0F73,
 768   REG_EVEX_0F38C6,
 769   REG_EVEX_0F38C7
 770 };
 771
 772 enum
 773 {
 774   MOD_8D = 0,
 775   MOD_C6_REG_7,
 776   MOD_C7_REG_7,
 777   MOD_FF_REG_3,
 778   MOD_FF_REG_5,
 779   MOD_0F01_REG_0,
 780   MOD_0F01_REG_1,
 781   MOD_0F01_REG_2,
 782   MOD_0F01_REG_3,
 783   MOD_0F01_REG_5,
 784   MOD_0F01_REG_7,
 785   MOD_0F12_PREFIX_0,
 786   MOD_0F13,
 787   MOD_0F16_PREFIX_0,
 788   MOD_0F17,
 789   MOD_0F18_REG_0,
 790   MOD_0F18_REG_1,
 791   MOD_0F18_REG_2,
 792   MOD_0F18_REG_3,
 793   MOD_0F18_REG_4,
 794   MOD_0F18_REG_5,
 795   MOD_0F18_REG_6,
 796   MOD_0F18_REG_7,
 797   MOD_0F1A_PREFIX_0,
 798   MOD_0F1B_PREFIX_0,
 799   MOD_0F1B_PREFIX_1,
 800   MOD_0F1C_PREFIX_0,
 801   MOD_0F1E_PREFIX_1,
 802   MOD_0F24,
 803   MOD_0F26,
 804   MOD_0F2B_PREFIX_0,
 805   MOD_0F2B_PREFIX_1,
 806   MOD_0F2B_PREFIX_2,
 807   MOD_0F2B_PREFIX_3,
 808   MOD_0F51,
 809   MOD_0F71_REG_2,
 810   MOD_0F71_REG_4,
 811   MOD_0F71_REG_6,
 812   MOD_0F72_REG_2,
 813   MOD_0F72_REG_4,
 814   MOD_0F72_REG_6,
 815   MOD_0F73_REG_2,
 816   MOD_0F73_REG_3,
 817   MOD_0F73_REG_6,
 818   MOD_0F73_REG_7,
 819   MOD_0FAE_REG_0,
 820   MOD_0FAE_REG_1,
 821   MOD_0FAE_REG_2,
 822   MOD_0FAE_REG_3,
 823   MOD_0FAE_REG_4,
 824   MOD_0FAE_REG_5,
 825   MOD_0FAE_REG_6,
 826   MOD_0FAE_REG_7,
 827   MOD_0FB2,
 828   MOD_0FB4,
 829   MOD_0FB5,
 830   MOD_0FC3,
 831   MOD_0FC7_REG_3,
 832   MOD_0FC7_REG_4,
 833   MOD_0FC7_REG_5,
 834   MOD_0FC7_REG_6,
 835   MOD_0FC7_REG_7,
 836   MOD_0FD7,
 837   MOD_0FE7_PREFIX_2,
 838   MOD_0FF0_PREFIX_3,
 839   MOD_0F382A_PREFIX_2,
 840   MOD_0F38F5_PREFIX_2,
 841   MOD_0F38F6_PREFIX_0,
 842   MOD_0F38F8_PREFIX_2,
 843   MOD_0F38F9_PREFIX_0,
 844   MOD_62_32BIT,
 845   MOD_C4_32BIT,
 846   MOD_C5_32BIT,
 847   MOD_VEX_0F12_PREFIX_0,
 848   MOD_VEX_0F13,
 849   MOD_VEX_0F16_PREFIX_0,
 850   MOD_VEX_0F17,
 851   MOD_VEX_0F2B,
 852   MOD_VEX_W_0_0F41_P_0_LEN_1,
 853   MOD_VEX_W_1_0F41_P_0_LEN_1,
 854   MOD_VEX_W_0_0F41_P_2_LEN_1,
 855   MOD_VEX_W_1_0F41_P_2_LEN_1,
 856   MOD_VEX_W_0_0F42_P_0_LEN_1,
 857   MOD_VEX_W_1_0F42_P_0_LEN_1,
 858   MOD_VEX_W_0_0F42_P_2_LEN_1,
 859   MOD_VEX_W_1_0F42_P_2_LEN_1,
 860   MOD_VEX_W_0_0F44_P_0_LEN_1,
 861   MOD_VEX_W_1_0F44_P_0_LEN_1,
 862   MOD_VEX_W_0_0F44_P_2_LEN_1,
 863   MOD_VEX_W_1_0F44_P_2_LEN_1,
 864   MOD_VEX_W_0_0F45_P_0_LEN_1,
 865   MOD_VEX_W_1_0F45_P_0_LEN_1,
 866   MOD_VEX_W_0_0F45_P_2_LEN_1,
 867   MOD_VEX_W_1_0F45_P_2_LEN_1,
 868   MOD_VEX_W_0_0F46_P_0_LEN_1,
 869   MOD_VEX_W_1_0F46_P_0_LEN_1,
 870   MOD_VEX_W_0_0F46_P_2_LEN_1,
 871   MOD_VEX_W_1_0F46_P_2_LEN_1,
 872   MOD_VEX_W_0_0F47_P_0_LEN_1,
 873   MOD_VEX_W_1_0F47_P_0_LEN_1,
 874   MOD_VEX_W_0_0F47_P_2_LEN_1,
 875   MOD_VEX_W_1_0F47_P_2_LEN_1,
 876   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 878   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 880   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 882   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 883   MOD_VEX_0F50,
 884   MOD_VEX_0F71_REG_2,
 885   MOD_VEX_0F71_REG_4,
 886   MOD_VEX_0F71_REG_6,
 887   MOD_VEX_0F72_REG_2,
 888   MOD_VEX_0F72_REG_4,
 889   MOD_VEX_0F72_REG_6,
 890   MOD_VEX_0F73_REG_2,
 891   MOD_VEX_0F73_REG_3,
 892   MOD_VEX_0F73_REG_6,
 893   MOD_VEX_0F73_REG_7,
 894   MOD_VEX_W_0_0F91_P_0_LEN_0,
 895   MOD_VEX_W_1_0F91_P_0_LEN_0,
 896   MOD_VEX_W_0_0F91_P_2_LEN_0,
 897   MOD_VEX_W_1_0F91_P_2_LEN_0,
 898   MOD_VEX_W_0_0F92_P_0_LEN_0,
 899   MOD_VEX_W_0_0F92_P_2_LEN_0,
 900   MOD_VEX_W_0_0F92_P_3_LEN_0,
 901   MOD_VEX_W_1_0F92_P_3_LEN_0,
 902   MOD_VEX_W_0_0F93_P_0_LEN_0,
 903   MOD_VEX_W_0_0F93_P_2_LEN_0,
 904   MOD_VEX_W_0_0F93_P_3_LEN_0,
 905   MOD_VEX_W_1_0F93_P_3_LEN_0,
 906   MOD_VEX_W_0_0F98_P_0_LEN_0,
 907   MOD_VEX_W_1_0F98_P_0_LEN_0,
 908   MOD_VEX_W_0_0F98_P_2_LEN_0,
 909   MOD_VEX_W_1_0F98_P_2_LEN_0,
 910   MOD_VEX_W_0_0F99_P_0_LEN_0,
 911   MOD_VEX_W_1_0F99_P_0_LEN_0,
 912   MOD_VEX_W_0_0F99_P_2_LEN_0,
 913   MOD_VEX_W_1_0F99_P_2_LEN_0,
 914   MOD_VEX_0FAE_REG_2,
 915   MOD_VEX_0FAE_REG_3,
 916   MOD_VEX_0FD7_PREFIX_2,
 917   MOD_VEX_0FE7_PREFIX_2,
 918   MOD_VEX_0FF0_PREFIX_3,
 919   MOD_VEX_0F381A_PREFIX_2,
 920   MOD_VEX_0F382A_PREFIX_2,
 921   MOD_VEX_0F382C_PREFIX_2,
 922   MOD_VEX_0F382D_PREFIX_2,
 923   MOD_VEX_0F382E_PREFIX_2,
 924   MOD_VEX_0F382F_PREFIX_2,
 925   MOD_VEX_0F385A_PREFIX_2,
 926   MOD_VEX_0F388C_PREFIX_2,
 927   MOD_VEX_0F388E_PREFIX_2,
 928   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 929   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 930   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 931   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 932   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 933   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 934   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 935   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 936
 937   MOD_EVEX_0F10_PREFIX_1,
 938   MOD_EVEX_0F10_PREFIX_3,
 939   MOD_EVEX_0F11_PREFIX_1,
 940   MOD_EVEX_0F11_PREFIX_3,
 941   MOD_EVEX_0F12_PREFIX_0,
 942   MOD_EVEX_0F16_PREFIX_0,
 943   MOD_EVEX_0F38C6_REG_1,
 944   MOD_EVEX_0F38C6_REG_2,
 945   MOD_EVEX_0F38C6_REG_5,
 946   MOD_EVEX_0F38C6_REG_6,
 947   MOD_EVEX_0F38C7_REG_1,
 948   MOD_EVEX_0F38C7_REG_2,
 949   MOD_EVEX_0F38C7_REG_5,
 950   MOD_EVEX_0F38C7_REG_6
 951 };
 952
 953 enum
 954 {
 955   RM_C6_REG_7 = 0,
 956   RM_C7_REG_7,
 957   RM_0F01_REG_0,
 958   RM_0F01_REG_1,
 959   RM_0F01_REG_2,
 960   RM_0F01_REG_3,
 961   RM_0F01_REG_5,
 962   RM_0F01_REG_7,
 963   RM_0F1E_MOD_3_REG_7,
 964   RM_0FAE_REG_6,
 965   RM_0FAE_REG_7
 966 };
 967
 968 enum
 969 {
 970   PREFIX_90 = 0,
 971   PREFIX_MOD_0_0F01_REG_5,
 972   PREFIX_MOD_3_0F01_REG_5_RM_0,
 973   PREFIX_MOD_3_0F01_REG_5_RM_2,
 974   PREFIX_0F09,
 975   PREFIX_0F10,
 976   PREFIX_0F11,
 977   PREFIX_0F12,
 978   PREFIX_0F16,
 979   PREFIX_0F1A,
 980   PREFIX_0F1B,
 981   PREFIX_0F1C,
 982   PREFIX_0F1E,
 983   PREFIX_0F2A,
 984   PREFIX_0F2B,
 985   PREFIX_0F2C,
 986   PREFIX_0F2D,
 987   PREFIX_0F2E,
 988   PREFIX_0F2F,
 989   PREFIX_0F51,
 990   PREFIX_0F52,
 991   PREFIX_0F53,
 992   PREFIX_0F58,
 993   PREFIX_0F59,
 994   PREFIX_0F5A,
 995   PREFIX_0F5B,
 996   PREFIX_0F5C,
 997   PREFIX_0F5D,
 998   PREFIX_0F5E,
 999   PREFIX_0F5F,
1000   PREFIX_0F60,
1001   PREFIX_0F61,
1002   PREFIX_0F62,
1003   PREFIX_0F6C,
1004   PREFIX_0F6D,
1005   PREFIX_0F6F,
1006   PREFIX_0F70,
1007   PREFIX_0F73_REG_3,
1008   PREFIX_0F73_REG_7,
1009   PREFIX_0F78,
1010   PREFIX_0F79,
1011   PREFIX_0F7C,
1012   PREFIX_0F7D,
1013   PREFIX_0F7E,
1014   PREFIX_0F7F,
1015   PREFIX_0FAE_REG_0,
1016   PREFIX_0FAE_REG_1,
1017   PREFIX_0FAE_REG_2,
1018   PREFIX_0FAE_REG_3,
1019   PREFIX_MOD_0_0FAE_REG_4,
1020   PREFIX_MOD_3_0FAE_REG_4,
1021   PREFIX_MOD_0_0FAE_REG_5,
1022   PREFIX_MOD_3_0FAE_REG_5,
1023   PREFIX_MOD_0_0FAE_REG_6,
1024   PREFIX_MOD_1_0FAE_REG_6,
1025   PREFIX_0FAE_REG_7,
1026   PREFIX_0FB8,
1027   PREFIX_0FBC,
1028   PREFIX_0FBD,
1029   PREFIX_0FC2,
1030   PREFIX_MOD_0_0FC3,
1031   PREFIX_MOD_0_0FC7_REG_6,
1032   PREFIX_MOD_3_0FC7_REG_6,
1033   PREFIX_MOD_3_0FC7_REG_7,
1034   PREFIX_0FD0,
1035   PREFIX_0FD6,
1036   PREFIX_0FE6,
1037   PREFIX_0FE7,
1038   PREFIX_0FF0,
1039   PREFIX_0FF7,
1040   PREFIX_0F3810,
1041   PREFIX_0F3814,
1042   PREFIX_0F3815,
1043   PREFIX_0F3817,
1044   PREFIX_0F3820,
1045   PREFIX_0F3821,
1046   PREFIX_0F3822,
1047   PREFIX_0F3823,
1048   PREFIX_0F3824,
1049   PREFIX_0F3825,
1050   PREFIX_0F3828,
1051   PREFIX_0F3829,
1052   PREFIX_0F382A,
1053   PREFIX_0F382B,
1054   PREFIX_0F3830,
1055   PREFIX_0F3831,
1056   PREFIX_0F3832,
1057   PREFIX_0F3833,
1058   PREFIX_0F3834,
1059   PREFIX_0F3835,
1060   PREFIX_0F3837,
1061   PREFIX_0F3838,
1062   PREFIX_0F3839,
1063   PREFIX_0F383A,
1064   PREFIX_0F383B,
1065   PREFIX_0F383C,
1066   PREFIX_0F383D,
1067   PREFIX_0F383E,
1068   PREFIX_0F383F,
1069   PREFIX_0F3840,
1070   PREFIX_0F3841,
1071   PREFIX_0F3880,
1072   PREFIX_0F3881,
1073   PREFIX_0F3882,
1074   PREFIX_0F38C8,
1075   PREFIX_0F38C9,
1076   PREFIX_0F38CA,
1077   PREFIX_0F38CB,
1078   PREFIX_0F38CC,
1079   PREFIX_0F38CD,
1080   PREFIX_0F38CF,
1081   PREFIX_0F38DB,
1082   PREFIX_0F38DC,
1083   PREFIX_0F38DD,
1084   PREFIX_0F38DE,
1085   PREFIX_0F38DF,
1086   PREFIX_0F38F0,
1087   PREFIX_0F38F1,
1088   PREFIX_0F38F5,
1089   PREFIX_0F38F6,
1090   PREFIX_0F38F8,
1091   PREFIX_0F38F9,
1092   PREFIX_0F3A08,
1093   PREFIX_0F3A09,
1094   PREFIX_0F3A0A,
1095   PREFIX_0F3A0B,
1096   PREFIX_0F3A0C,
1097   PREFIX_0F3A0D,
1098   PREFIX_0F3A0E,
1099   PREFIX_0F3A14,
1100   PREFIX_0F3A15,
1101   PREFIX_0F3A16,
1102   PREFIX_0F3A17,
1103   PREFIX_0F3A20,
1104   PREFIX_0F3A21,
1105   PREFIX_0F3A22,
1106   PREFIX_0F3A40,
1107   PREFIX_0F3A41,
1108   PREFIX_0F3A42,
1109   PREFIX_0F3A44,
1110   PREFIX_0F3A60,
1111   PREFIX_0F3A61,
1112   PREFIX_0F3A62,
1113   PREFIX_0F3A63,
1114   PREFIX_0F3ACC,
1115   PREFIX_0F3ACE,
1116   PREFIX_0F3ACF,
1117   PREFIX_0F3ADF,
1118   PREFIX_VEX_0F10,
1119   PREFIX_VEX_0F11,
1120   PREFIX_VEX_0F12,
1121   PREFIX_VEX_0F16,
1122   PREFIX_VEX_0F2A,
1123   PREFIX_VEX_0F2C,
1124   PREFIX_VEX_0F2D,
1125   PREFIX_VEX_0F2E,
1126   PREFIX_VEX_0F2F,
1127   PREFIX_VEX_0F41,
1128   PREFIX_VEX_0F42,
1129   PREFIX_VEX_0F44,
1130   PREFIX_VEX_0F45,
1131   PREFIX_VEX_0F46,
1132   PREFIX_VEX_0F47,
1133   PREFIX_VEX_0F4A,
1134   PREFIX_VEX_0F4B,
1135   PREFIX_VEX_0F51,
1136   PREFIX_VEX_0F52,
1137   PREFIX_VEX_0F53,
1138   PREFIX_VEX_0F58,
1139   PREFIX_VEX_0F59,
1140   PREFIX_VEX_0F5A,
1141   PREFIX_VEX_0F5B,
1142   PREFIX_VEX_0F5C,
1143   PREFIX_VEX_0F5D,
1144   PREFIX_VEX_0F5E,
1145   PREFIX_VEX_0F5F,
1146   PREFIX_VEX_0F60,
1147   PREFIX_VEX_0F61,
1148   PREFIX_VEX_0F62,
1149   PREFIX_VEX_0F63,
1150   PREFIX_VEX_0F64,
1151   PREFIX_VEX_0F65,
1152   PREFIX_VEX_0F66,
1153   PREFIX_VEX_0F67,
1154   PREFIX_VEX_0F68,
1155   PREFIX_VEX_0F69,
1156   PREFIX_VEX_0F6A,
1157   PREFIX_VEX_0F6B,
1158   PREFIX_VEX_0F6C,
1159   PREFIX_VEX_0F6D,
1160   PREFIX_VEX_0F6E,
1161   PREFIX_VEX_0F6F,
1162   PREFIX_VEX_0F70,
1163   PREFIX_VEX_0F71_REG_2,
1164   PREFIX_VEX_0F71_REG_4,
1165   PREFIX_VEX_0F71_REG_6,
1166   PREFIX_VEX_0F72_REG_2,
1167   PREFIX_VEX_0F72_REG_4,
1168   PREFIX_VEX_0F72_REG_6,
1169   PREFIX_VEX_0F73_REG_2,
1170   PREFIX_VEX_0F73_REG_3,
1171   PREFIX_VEX_0F73_REG_6,
1172   PREFIX_VEX_0F73_REG_7,
1173   PREFIX_VEX_0F74,
1174   PREFIX_VEX_0F75,
1175   PREFIX_VEX_0F76,
1176   PREFIX_VEX_0F77,
1177   PREFIX_VEX_0F7C,
1178   PREFIX_VEX_0F7D,
1179   PREFIX_VEX_0F7E,
1180   PREFIX_VEX_0F7F,
1181   PREFIX_VEX_0F90,
1182   PREFIX_VEX_0F91,
1183   PREFIX_VEX_0F92,
1184   PREFIX_VEX_0F93,
1185   PREFIX_VEX_0F98,
1186   PREFIX_VEX_0F99,
1187   PREFIX_VEX_0FC2,
1188   PREFIX_VEX_0FC4,
1189   PREFIX_VEX_0FC5,
1190   PREFIX_VEX_0FD0,
1191   PREFIX_VEX_0FD1,
1192   PREFIX_VEX_0FD2,
1193   PREFIX_VEX_0FD3,
1194   PREFIX_VEX_0FD4,
1195   PREFIX_VEX_0FD5,
1196   PREFIX_VEX_0FD6,
1197   PREFIX_VEX_0FD7,
1198   PREFIX_VEX_0FD8,
1199   PREFIX_VEX_0FD9,
1200   PREFIX_VEX_0FDA,
1201   PREFIX_VEX_0FDB,
1202   PREFIX_VEX_0FDC,
1203   PREFIX_VEX_0FDD,
1204   PREFIX_VEX_0FDE,
1205   PREFIX_VEX_0FDF,
1206   PREFIX_VEX_0FE0,
1207   PREFIX_VEX_0FE1,
1208   PREFIX_VEX_0FE2,
1209   PREFIX_VEX_0FE3,
1210   PREFIX_VEX_0FE4,
1211   PREFIX_VEX_0FE5,
1212   PREFIX_VEX_0FE6,
1213   PREFIX_VEX_0FE7,
1214   PREFIX_VEX_0FE8,
1215   PREFIX_VEX_0FE9,
1216   PREFIX_VEX_0FEA,
1217   PREFIX_VEX_0FEB,
1218   PREFIX_VEX_0FEC,
1219   PREFIX_VEX_0FED,
1220   PREFIX_VEX_0FEE,
1221   PREFIX_VEX_0FEF,
1222   PREFIX_VEX_0FF0,
1223   PREFIX_VEX_0FF1,
1224   PREFIX_VEX_0FF2,
1225   PREFIX_VEX_0FF3,
1226   PREFIX_VEX_0FF4,
1227   PREFIX_VEX_0FF5,
1228   PREFIX_VEX_0FF6,
1229   PREFIX_VEX_0FF7,
1230   PREFIX_VEX_0FF8,
1231   PREFIX_VEX_0FF9,
1232   PREFIX_VEX_0FFA,
1233   PREFIX_VEX_0FFB,
1234   PREFIX_VEX_0FFC,
1235   PREFIX_VEX_0FFD,
1236   PREFIX_VEX_0FFE,
1237   PREFIX_VEX_0F3800,
1238   PREFIX_VEX_0F3801,
1239   PREFIX_VEX_0F3802,
1240   PREFIX_VEX_0F3803,
1241   PREFIX_VEX_0F3804,
1242   PREFIX_VEX_0F3805,
1243   PREFIX_VEX_0F3806,
1244   PREFIX_VEX_0F3807,
1245   PREFIX_VEX_0F3808,
1246   PREFIX_VEX_0F3809,
1247   PREFIX_VEX_0F380A,
1248   PREFIX_VEX_0F380B,
1249   PREFIX_VEX_0F380C,
1250   PREFIX_VEX_0F380D,
1251   PREFIX_VEX_0F380E,
1252   PREFIX_VEX_0F380F,
1253   PREFIX_VEX_0F3813,
1254   PREFIX_VEX_0F3816,
1255   PREFIX_VEX_0F3817,
1256   PREFIX_VEX_0F3818,
1257   PREFIX_VEX_0F3819,
1258   PREFIX_VEX_0F381A,
1259   PREFIX_VEX_0F381C,
1260   PREFIX_VEX_0F381D,
1261   PREFIX_VEX_0F381E,
1262   PREFIX_VEX_0F3820,
1263   PREFIX_VEX_0F3821,
1264   PREFIX_VEX_0F3822,
1265   PREFIX_VEX_0F3823,
1266   PREFIX_VEX_0F3824,
1267   PREFIX_VEX_0F3825,
1268   PREFIX_VEX_0F3828,
1269   PREFIX_VEX_0F3829,
1270   PREFIX_VEX_0F382A,
1271   PREFIX_VEX_0F382B,
1272   PREFIX_VEX_0F382C,
1273   PREFIX_VEX_0F382D,
1274   PREFIX_VEX_0F382E,
1275   PREFIX_VEX_0F382F,
1276   PREFIX_VEX_0F3830,
1277   PREFIX_VEX_0F3831,
1278   PREFIX_VEX_0F3832,
1279   PREFIX_VEX_0F3833,
1280   PREFIX_VEX_0F3834,
1281   PREFIX_VEX_0F3835,
1282   PREFIX_VEX_0F3836,
1283   PREFIX_VEX_0F3837,
1284   PREFIX_VEX_0F3838,
1285   PREFIX_VEX_0F3839,
1286   PREFIX_VEX_0F383A,
1287   PREFIX_VEX_0F383B,
1288   PREFIX_VEX_0F383C,
1289   PREFIX_VEX_0F383D,
1290   PREFIX_VEX_0F383E,
1291   PREFIX_VEX_0F383F,
1292   PREFIX_VEX_0F3840,
1293   PREFIX_VEX_0F3841,
1294   PREFIX_VEX_0F3845,
1295   PREFIX_VEX_0F3846,
1296   PREFIX_VEX_0F3847,
1297   PREFIX_VEX_0F3858,
1298   PREFIX_VEX_0F3859,
1299   PREFIX_VEX_0F385A,
1300   PREFIX_VEX_0F3878,
1301   PREFIX_VEX_0F3879,
1302   PREFIX_VEX_0F388C,
1303   PREFIX_VEX_0F388E,
1304   PREFIX_VEX_0F3890,
1305   PREFIX_VEX_0F3891,
1306   PREFIX_VEX_0F3892,
1307   PREFIX_VEX_0F3893,
1308   PREFIX_VEX_0F3896,
1309   PREFIX_VEX_0F3897,
1310   PREFIX_VEX_0F3898,
1311   PREFIX_VEX_0F3899,
1312   PREFIX_VEX_0F389A,
1313   PREFIX_VEX_0F389B,
1314   PREFIX_VEX_0F389C,
1315   PREFIX_VEX_0F389D,
1316   PREFIX_VEX_0F389E,
1317   PREFIX_VEX_0F389F,
1318   PREFIX_VEX_0F38A6,
1319   PREFIX_VEX_0F38A7,
1320   PREFIX_VEX_0F38A8,
1321   PREFIX_VEX_0F38A9,
1322   PREFIX_VEX_0F38AA,
1323   PREFIX_VEX_0F38AB,
1324   PREFIX_VEX_0F38AC,
1325   PREFIX_VEX_0F38AD,
1326   PREFIX_VEX_0F38AE,
1327   PREFIX_VEX_0F38AF,
1328   PREFIX_VEX_0F38B6,
1329   PREFIX_VEX_0F38B7,
1330   PREFIX_VEX_0F38B8,
1331   PREFIX_VEX_0F38B9,
1332   PREFIX_VEX_0F38BA,
1333   PREFIX_VEX_0F38BB,
1334   PREFIX_VEX_0F38BC,
1335   PREFIX_VEX_0F38BD,
1336   PREFIX_VEX_0F38BE,
1337   PREFIX_VEX_0F38BF,
1338   PREFIX_VEX_0F38CF,
1339   PREFIX_VEX_0F38DB,
1340   PREFIX_VEX_0F38DC,
1341   PREFIX_VEX_0F38DD,
1342   PREFIX_VEX_0F38DE,
1343   PREFIX_VEX_0F38DF,
1344   PREFIX_VEX_0F38F2,
1345   PREFIX_VEX_0F38F3_REG_1,
1346   PREFIX_VEX_0F38F3_REG_2,
1347   PREFIX_VEX_0F38F3_REG_3,
1348   PREFIX_VEX_0F38F5,
1349   PREFIX_VEX_0F38F6,
1350   PREFIX_VEX_0F38F7,
1351   PREFIX_VEX_0F3A00,
1352   PREFIX_VEX_0F3A01,
1353   PREFIX_VEX_0F3A02,
1354   PREFIX_VEX_0F3A04,
1355   PREFIX_VEX_0F3A05,
1356   PREFIX_VEX_0F3A06,
1357   PREFIX_VEX_0F3A08,
1358   PREFIX_VEX_0F3A09,
1359   PREFIX_VEX_0F3A0A,
1360   PREFIX_VEX_0F3A0B,
1361   PREFIX_VEX_0F3A0C,
1362   PREFIX_VEX_0F3A0D,
1363   PREFIX_VEX_0F3A0E,
1364   PREFIX_VEX_0F3A0F,
1365   PREFIX_VEX_0F3A14,
1366   PREFIX_VEX_0F3A15,
1367   PREFIX_VEX_0F3A16,
1368   PREFIX_VEX_0F3A17,
1369   PREFIX_VEX_0F3A18,
1370   PREFIX_VEX_0F3A19,
1371   PREFIX_VEX_0F3A1D,
1372   PREFIX_VEX_0F3A20,
1373   PREFIX_VEX_0F3A21,
1374   PREFIX_VEX_0F3A22,
1375   PREFIX_VEX_0F3A30,
1376   PREFIX_VEX_0F3A31,
1377   PREFIX_VEX_0F3A32,
1378   PREFIX_VEX_0F3A33,
1379   PREFIX_VEX_0F3A38,
1380   PREFIX_VEX_0F3A39,
1381   PREFIX_VEX_0F3A40,
1382   PREFIX_VEX_0F3A41,
1383   PREFIX_VEX_0F3A42,
1384   PREFIX_VEX_0F3A44,
1385   PREFIX_VEX_0F3A46,
1386   PREFIX_VEX_0F3A48,
1387   PREFIX_VEX_0F3A49,
1388   PREFIX_VEX_0F3A4A,
1389   PREFIX_VEX_0F3A4B,
1390   PREFIX_VEX_0F3A4C,
1391   PREFIX_VEX_0F3A5C,
1392   PREFIX_VEX_0F3A5D,
1393   PREFIX_VEX_0F3A5E,
1394   PREFIX_VEX_0F3A5F,
1395   PREFIX_VEX_0F3A60,
1396   PREFIX_VEX_0F3A61,
1397   PREFIX_VEX_0F3A62,
1398   PREFIX_VEX_0F3A63,
1399   PREFIX_VEX_0F3A68,
1400   PREFIX_VEX_0F3A69,
1401   PREFIX_VEX_0F3A6A,
1402   PREFIX_VEX_0F3A6B,
1403   PREFIX_VEX_0F3A6C,
1404   PREFIX_VEX_0F3A6D,
1405   PREFIX_VEX_0F3A6E,
1406   PREFIX_VEX_0F3A6F,
1407   PREFIX_VEX_0F3A78,
1408   PREFIX_VEX_0F3A79,
1409   PREFIX_VEX_0F3A7A,
1410   PREFIX_VEX_0F3A7B,
1411   PREFIX_VEX_0F3A7C,
1412   PREFIX_VEX_0F3A7D,
1413   PREFIX_VEX_0F3A7E,
1414   PREFIX_VEX_0F3A7F,
1415   PREFIX_VEX_0F3ACE,
1416   PREFIX_VEX_0F3ACF,
1417   PREFIX_VEX_0F3ADF,
1418   PREFIX_VEX_0F3AF0,
1419
1420   PREFIX_EVEX_0F10,
1421   PREFIX_EVEX_0F11,
1422   PREFIX_EVEX_0F12,
1423   PREFIX_EVEX_0F13,
1424   PREFIX_EVEX_0F14,
1425   PREFIX_EVEX_0F15,
1426   PREFIX_EVEX_0F16,
1427   PREFIX_EVEX_0F17,
1428   PREFIX_EVEX_0F28,
1429   PREFIX_EVEX_0F29,
1430   PREFIX_EVEX_0F2A,
1431   PREFIX_EVEX_0F2B,
1432   PREFIX_EVEX_0F2C,
1433   PREFIX_EVEX_0F2D,
1434   PREFIX_EVEX_0F2E,
1435   PREFIX_EVEX_0F2F,
1436   PREFIX_EVEX_0F51,
1437   PREFIX_EVEX_0F54,
1438   PREFIX_EVEX_0F55,
1439   PREFIX_EVEX_0F56,
1440   PREFIX_EVEX_0F57,
1441   PREFIX_EVEX_0F58,
1442   PREFIX_EVEX_0F59,
1443   PREFIX_EVEX_0F5A,
1444   PREFIX_EVEX_0F5B,
1445   PREFIX_EVEX_0F5C,
1446   PREFIX_EVEX_0F5D,
1447   PREFIX_EVEX_0F5E,
1448   PREFIX_EVEX_0F5F,
1449   PREFIX_EVEX_0F60,
1450   PREFIX_EVEX_0F61,
1451   PREFIX_EVEX_0F62,
1452   PREFIX_EVEX_0F63,
1453   PREFIX_EVEX_0F64,
1454   PREFIX_EVEX_0F65,
1455   PREFIX_EVEX_0F66,
1456   PREFIX_EVEX_0F67,
1457   PREFIX_EVEX_0F68,
1458   PREFIX_EVEX_0F69,
1459   PREFIX_EVEX_0F6A,
1460   PREFIX_EVEX_0F6B,
1461   PREFIX_EVEX_0F6C,
1462   PREFIX_EVEX_0F6D,
1463   PREFIX_EVEX_0F6E,
1464   PREFIX_EVEX_0F6F,
1465   PREFIX_EVEX_0F70,
1466   PREFIX_EVEX_0F71_REG_2,
1467   PREFIX_EVEX_0F71_REG_4,
1468   PREFIX_EVEX_0F71_REG_6,
1469   PREFIX_EVEX_0F72_REG_0,
1470   PREFIX_EVEX_0F72_REG_1,
1471   PREFIX_EVEX_0F72_REG_2,
1472   PREFIX_EVEX_0F72_REG_4,
1473   PREFIX_EVEX_0F72_REG_6,
1474   PREFIX_EVEX_0F73_REG_2,
1475   PREFIX_EVEX_0F73_REG_3,
1476   PREFIX_EVEX_0F73_REG_6,
1477   PREFIX_EVEX_0F73_REG_7,
1478   PREFIX_EVEX_0F74,
1479   PREFIX_EVEX_0F75,
1480   PREFIX_EVEX_0F76,
1481   PREFIX_EVEX_0F78,
1482   PREFIX_EVEX_0F79,
1483   PREFIX_EVEX_0F7A,
1484   PREFIX_EVEX_0F7B,
1485   PREFIX_EVEX_0F7E,
1486   PREFIX_EVEX_0F7F,
1487   PREFIX_EVEX_0FC2,
1488   PREFIX_EVEX_0FC4,
1489   PREFIX_EVEX_0FC5,
1490   PREFIX_EVEX_0FC6,
1491   PREFIX_EVEX_0FD1,
1492   PREFIX_EVEX_0FD2,
1493   PREFIX_EVEX_0FD3,
1494   PREFIX_EVEX_0FD4,
1495   PREFIX_EVEX_0FD5,
1496   PREFIX_EVEX_0FD6,
1497   PREFIX_EVEX_0FD8,
1498   PREFIX_EVEX_0FD9,
1499   PREFIX_EVEX_0FDA,
1500   PREFIX_EVEX_0FDB,
1501   PREFIX_EVEX_0FDC,
1502   PREFIX_EVEX_0FDD,
1503   PREFIX_EVEX_0FDE,
1504   PREFIX_EVEX_0FDF,
1505   PREFIX_EVEX_0FE0,
1506   PREFIX_EVEX_0FE1,
1507   PREFIX_EVEX_0FE2,
1508   PREFIX_EVEX_0FE3,
1509   PREFIX_EVEX_0FE4,
1510   PREFIX_EVEX_0FE5,
1511   PREFIX_EVEX_0FE6,
1512   PREFIX_EVEX_0FE7,
1513   PREFIX_EVEX_0FE8,
1514   PREFIX_EVEX_0FE9,
1515   PREFIX_EVEX_0FEA,
1516   PREFIX_EVEX_0FEB,
1517   PREFIX_EVEX_0FEC,
1518   PREFIX_EVEX_0FED,
1519   PREFIX_EVEX_0FEE,
1520   PREFIX_EVEX_0FEF,
1521   PREFIX_EVEX_0FF1,
1522   PREFIX_EVEX_0FF2,
1523   PREFIX_EVEX_0FF3,
1524   PREFIX_EVEX_0FF4,
1525   PREFIX_EVEX_0FF5,
1526   PREFIX_EVEX_0FF6,
1527   PREFIX_EVEX_0FF8,
1528   PREFIX_EVEX_0FF9,
1529   PREFIX_EVEX_0FFA,
1530   PREFIX_EVEX_0FFB,
1531   PREFIX_EVEX_0FFC,
1532   PREFIX_EVEX_0FFD,
1533   PREFIX_EVEX_0FFE,
1534   PREFIX_EVEX_0F3800,
1535   PREFIX_EVEX_0F3804,
1536   PREFIX_EVEX_0F380B,
1537   PREFIX_EVEX_0F380C,
1538   PREFIX_EVEX_0F380D,
1539   PREFIX_EVEX_0F3810,
1540   PREFIX_EVEX_0F3811,
1541   PREFIX_EVEX_0F3812,
1542   PREFIX_EVEX_0F3813,
1543   PREFIX_EVEX_0F3814,
1544   PREFIX_EVEX_0F3815,
1545   PREFIX_EVEX_0F3816,
1546   PREFIX_EVEX_0F3818,
1547   PREFIX_EVEX_0F3819,
1548   PREFIX_EVEX_0F381A,
1549   PREFIX_EVEX_0F381B,
1550   PREFIX_EVEX_0F381C,
1551   PREFIX_EVEX_0F381D,
1552   PREFIX_EVEX_0F381E,
1553   PREFIX_EVEX_0F381F,
1554   PREFIX_EVEX_0F3820,
1555   PREFIX_EVEX_0F3821,
1556   PREFIX_EVEX_0F3822,
1557   PREFIX_EVEX_0F3823,
1558   PREFIX_EVEX_0F3824,
1559   PREFIX_EVEX_0F3825,
1560   PREFIX_EVEX_0F3826,
1561   PREFIX_EVEX_0F3827,
1562   PREFIX_EVEX_0F3828,
1563   PREFIX_EVEX_0F3829,
1564   PREFIX_EVEX_0F382A,
1565   PREFIX_EVEX_0F382B,
1566   PREFIX_EVEX_0F382C,
1567   PREFIX_EVEX_0F382D,
1568   PREFIX_EVEX_0F3830,
1569   PREFIX_EVEX_0F3831,
1570   PREFIX_EVEX_0F3832,
1571   PREFIX_EVEX_0F3833,
1572   PREFIX_EVEX_0F3834,
1573   PREFIX_EVEX_0F3835,
1574   PREFIX_EVEX_0F3836,
1575   PREFIX_EVEX_0F3837,
1576   PREFIX_EVEX_0F3838,
1577   PREFIX_EVEX_0F3839,
1578   PREFIX_EVEX_0F383A,
1579   PREFIX_EVEX_0F383B,
1580   PREFIX_EVEX_0F383C,
1581   PREFIX_EVEX_0F383D,
1582   PREFIX_EVEX_0F383E,
1583   PREFIX_EVEX_0F383F,
1584   PREFIX_EVEX_0F3840,
1585   PREFIX_EVEX_0F3842,
1586   PREFIX_EVEX_0F3843,
1587   PREFIX_EVEX_0F3844,
1588   PREFIX_EVEX_0F3845,
1589   PREFIX_EVEX_0F3846,
1590   PREFIX_EVEX_0F3847,
1591   PREFIX_EVEX_0F384C,
1592   PREFIX_EVEX_0F384D,
1593   PREFIX_EVEX_0F384E,
1594   PREFIX_EVEX_0F384F,
1595   PREFIX_EVEX_0F3850,
1596   PREFIX_EVEX_0F3851,
1597   PREFIX_EVEX_0F3852,
1598   PREFIX_EVEX_0F3853,
1599   PREFIX_EVEX_0F3854,
1600   PREFIX_EVEX_0F3855,
1601   PREFIX_EVEX_0F3858,
1602   PREFIX_EVEX_0F3859,
1603   PREFIX_EVEX_0F385A,
1604   PREFIX_EVEX_0F385B,
1605   PREFIX_EVEX_0F3862,
1606   PREFIX_EVEX_0F3863,
1607   PREFIX_EVEX_0F3864,
1608   PREFIX_EVEX_0F3865,
1609   PREFIX_EVEX_0F3866,
1610   PREFIX_EVEX_0F3870,
1611   PREFIX_EVEX_0F3871,
1612   PREFIX_EVEX_0F3872,
1613   PREFIX_EVEX_0F3873,
1614   PREFIX_EVEX_0F3875,
1615   PREFIX_EVEX_0F3876,
1616   PREFIX_EVEX_0F3877,
1617   PREFIX_EVEX_0F3878,
1618   PREFIX_EVEX_0F3879,
1619   PREFIX_EVEX_0F387A,
1620   PREFIX_EVEX_0F387B,
1621   PREFIX_EVEX_0F387C,
1622   PREFIX_EVEX_0F387D,
1623   PREFIX_EVEX_0F387E,
1624   PREFIX_EVEX_0F387F,
1625   PREFIX_EVEX_0F3883,
1626   PREFIX_EVEX_0F3888,
1627   PREFIX_EVEX_0F3889,
1628   PREFIX_EVEX_0F388A,
1629   PREFIX_EVEX_0F388B,
1630   PREFIX_EVEX_0F388D,
1631   PREFIX_EVEX_0F388F,
1632   PREFIX_EVEX_0F3890,
1633   PREFIX_EVEX_0F3891,
1634   PREFIX_EVEX_0F3892,
1635   PREFIX_EVEX_0F3893,
1636   PREFIX_EVEX_0F3896,
1637   PREFIX_EVEX_0F3897,
1638   PREFIX_EVEX_0F3898,
1639   PREFIX_EVEX_0F3899,
1640   PREFIX_EVEX_0F389A,
1641   PREFIX_EVEX_0F389B,
1642   PREFIX_EVEX_0F389C,
1643   PREFIX_EVEX_0F389D,
1644   PREFIX_EVEX_0F389E,
1645   PREFIX_EVEX_0F389F,
1646   PREFIX_EVEX_0F38A0,
1647   PREFIX_EVEX_0F38A1,
1648   PREFIX_EVEX_0F38A2,
1649   PREFIX_EVEX_0F38A3,
1650   PREFIX_EVEX_0F38A6,
1651   PREFIX_EVEX_0F38A7,
1652   PREFIX_EVEX_0F38A8,
1653   PREFIX_EVEX_0F38A9,
1654   PREFIX_EVEX_0F38AA,
1655   PREFIX_EVEX_0F38AB,
1656   PREFIX_EVEX_0F38AC,
1657   PREFIX_EVEX_0F38AD,
1658   PREFIX_EVEX_0F38AE,
1659   PREFIX_EVEX_0F38AF,
1660   PREFIX_EVEX_0F38B4,
1661   PREFIX_EVEX_0F38B5,
1662   PREFIX_EVEX_0F38B6,
1663   PREFIX_EVEX_0F38B7,
1664   PREFIX_EVEX_0F38B8,
1665   PREFIX_EVEX_0F38B9,
1666   PREFIX_EVEX_0F38BA,
1667   PREFIX_EVEX_0F38BB,
1668   PREFIX_EVEX_0F38BC,
1669   PREFIX_EVEX_0F38BD,
1670   PREFIX_EVEX_0F38BE,
1671   PREFIX_EVEX_0F38BF,
1672   PREFIX_EVEX_0F38C4,
1673   PREFIX_EVEX_0F38C6_REG_1,
1674   PREFIX_EVEX_0F38C6_REG_2,
1675   PREFIX_EVEX_0F38C6_REG_5,
1676   PREFIX_EVEX_0F38C6_REG_6,
1677   PREFIX_EVEX_0F38C7_REG_1,
1678   PREFIX_EVEX_0F38C7_REG_2,
1679   PREFIX_EVEX_0F38C7_REG_5,
1680   PREFIX_EVEX_0F38C7_REG_6,
1681   PREFIX_EVEX_0F38C8,
1682   PREFIX_EVEX_0F38CA,
1683   PREFIX_EVEX_0F38CB,
1684   PREFIX_EVEX_0F38CC,
1685   PREFIX_EVEX_0F38CD,
1686   PREFIX_EVEX_0F38CF,
1687   PREFIX_EVEX_0F38DC,
1688   PREFIX_EVEX_0F38DD,
1689   PREFIX_EVEX_0F38DE,
1690   PREFIX_EVEX_0F38DF,
1691
1692   PREFIX_EVEX_0F3A00,
1693   PREFIX_EVEX_0F3A01,
1694   PREFIX_EVEX_0F3A03,
1695   PREFIX_EVEX_0F3A04,
1696   PREFIX_EVEX_0F3A05,
1697   PREFIX_EVEX_0F3A08,
1698   PREFIX_EVEX_0F3A09,
1699   PREFIX_EVEX_0F3A0A,
1700   PREFIX_EVEX_0F3A0B,
1701   PREFIX_EVEX_0F3A0F,
1702   PREFIX_EVEX_0F3A14,
1703   PREFIX_EVEX_0F3A15,
1704   PREFIX_EVEX_0F3A16,
1705   PREFIX_EVEX_0F3A17,
1706   PREFIX_EVEX_0F3A18,
1707   PREFIX_EVEX_0F3A19,
1708   PREFIX_EVEX_0F3A1A,
1709   PREFIX_EVEX_0F3A1B,
1710   PREFIX_EVEX_0F3A1D,
1711   PREFIX_EVEX_0F3A1E,
1712   PREFIX_EVEX_0F3A1F,
1713   PREFIX_EVEX_0F3A20,
1714   PREFIX_EVEX_0F3A21,
1715   PREFIX_EVEX_0F3A22,
1716   PREFIX_EVEX_0F3A23,
1717   PREFIX_EVEX_0F3A25,
1718   PREFIX_EVEX_0F3A26,
1719   PREFIX_EVEX_0F3A27,
1720   PREFIX_EVEX_0F3A38,
1721   PREFIX_EVEX_0F3A39,
1722   PREFIX_EVEX_0F3A3A,
1723   PREFIX_EVEX_0F3A3B,
1724   PREFIX_EVEX_0F3A3E,
1725   PREFIX_EVEX_0F3A3F,
1726   PREFIX_EVEX_0F3A42,
1727   PREFIX_EVEX_0F3A43,
1728   PREFIX_EVEX_0F3A44,
1729   PREFIX_EVEX_0F3A50,
1730   PREFIX_EVEX_0F3A51,
1731   PREFIX_EVEX_0F3A54,
1732   PREFIX_EVEX_0F3A55,
1733   PREFIX_EVEX_0F3A56,
1734   PREFIX_EVEX_0F3A57,
1735   PREFIX_EVEX_0F3A66,
1736   PREFIX_EVEX_0F3A67,
1737   PREFIX_EVEX_0F3A70,
1738   PREFIX_EVEX_0F3A71,
1739   PREFIX_EVEX_0F3A72,
1740   PREFIX_EVEX_0F3A73,
1741   PREFIX_EVEX_0F3ACE,
1742   PREFIX_EVEX_0F3ACF
1743 };
1744
1745 enum
1746 {
1747   X86_64_06 = 0,
1748   X86_64_07,
1749   X86_64_0D,
1750   X86_64_16,
1751   X86_64_17,
1752   X86_64_1E,
1753   X86_64_1F,
1754   X86_64_27,
1755   X86_64_2F,
1756   X86_64_37,
1757   X86_64_3F,
1758   X86_64_60,
1759   X86_64_61,
1760   X86_64_62,
1761   X86_64_63,
1762   X86_64_6D,
1763   X86_64_6F,
1764   X86_64_82,
1765   X86_64_9A,
1766   X86_64_C4,
1767   X86_64_C5,
1768   X86_64_CE,
1769   X86_64_D4,
1770   X86_64_D5,
1771   X86_64_E8,
1772   X86_64_E9,
1773   X86_64_EA,
1774   X86_64_0F01_REG_0,
1775   X86_64_0F01_REG_1,
1776   X86_64_0F01_REG_2,
1777   X86_64_0F01_REG_3
1778 };
1779
1780 enum
1781 {
1782   THREE_BYTE_0F38 = 0,
1783   THREE_BYTE_0F3A
1784 };
1785
1786 enum
1787 {
1788   XOP_08 = 0,
1789   XOP_09,
1790   XOP_0A
1791 };
1792
1793 enum
1794 {
1795   VEX_0F = 0,
1796   VEX_0F38,
1797   VEX_0F3A
1798 };
1799
1800 enum
1801 {
1802   EVEX_0F = 0,
1803   EVEX_0F38,
1804   EVEX_0F3A
1805 };
1806
1807 enum
1808 {
1809   VEX_LEN_0F10_P_1 = 0,
1810   VEX_LEN_0F10_P_3,
1811   VEX_LEN_0F11_P_1,
1812   VEX_LEN_0F11_P_3,
1813   VEX_LEN_0F12_P_0_M_0,
1814   VEX_LEN_0F12_P_0_M_1,
1815   VEX_LEN_0F12_P_2,
1816   VEX_LEN_0F13_M_0,
1817   VEX_LEN_0F16_P_0_M_0,
1818   VEX_LEN_0F16_P_0_M_1,
1819   VEX_LEN_0F16_P_2,
1820   VEX_LEN_0F17_M_0,
1821   VEX_LEN_0F2A_P_1,
1822   VEX_LEN_0F2A_P_3,
1823   VEX_LEN_0F2C_P_1,
1824   VEX_LEN_0F2C_P_3,
1825   VEX_LEN_0F2D_P_1,
1826   VEX_LEN_0F2D_P_3,
1827   VEX_LEN_0F2E_P_0,
1828   VEX_LEN_0F2E_P_2,
1829   VEX_LEN_0F2F_P_0,
1830   VEX_LEN_0F2F_P_2,
1831   VEX_LEN_0F41_P_0,
1832   VEX_LEN_0F41_P_2,
1833   VEX_LEN_0F42_P_0,
1834   VEX_LEN_0F42_P_2,
1835   VEX_LEN_0F44_P_0,
1836   VEX_LEN_0F44_P_2,
1837   VEX_LEN_0F45_P_0,
1838   VEX_LEN_0F45_P_2,
1839   VEX_LEN_0F46_P_0,
1840   VEX_LEN_0F46_P_2,
1841   VEX_LEN_0F47_P_0,
1842   VEX_LEN_0F47_P_2,
1843   VEX_LEN_0F4A_P_0,
1844   VEX_LEN_0F4A_P_2,
1845   VEX_LEN_0F4B_P_0,
1846   VEX_LEN_0F4B_P_2,
1847   VEX_LEN_0F51_P_1,
1848   VEX_LEN_0F51_P_3,
1849   VEX_LEN_0F52_P_1,
1850   VEX_LEN_0F53_P_1,
1851   VEX_LEN_0F58_P_1,
1852   VEX_LEN_0F58_P_3,
1853   VEX_LEN_0F59_P_1,
1854   VEX_LEN_0F59_P_3,
1855   VEX_LEN_0F5A_P_1,
1856   VEX_LEN_0F5A_P_3,
1857   VEX_LEN_0F5C_P_1,
1858   VEX_LEN_0F5C_P_3,
1859   VEX_LEN_0F5D_P_1,
1860   VEX_LEN_0F5D_P_3,
1861   VEX_LEN_0F5E_P_1,
1862   VEX_LEN_0F5E_P_3,
1863   VEX_LEN_0F5F_P_1,
1864   VEX_LEN_0F5F_P_3,
1865   VEX_LEN_0F6E_P_2,
1866   VEX_LEN_0F7E_P_1,
1867   VEX_LEN_0F7E_P_2,
1868   VEX_LEN_0F90_P_0,
1869   VEX_LEN_0F90_P_2,
1870   VEX_LEN_0F91_P_0,
1871   VEX_LEN_0F91_P_2,
1872   VEX_LEN_0F92_P_0,
1873   VEX_LEN_0F92_P_2,
1874   VEX_LEN_0F92_P_3,
1875   VEX_LEN_0F93_P_0,
1876   VEX_LEN_0F93_P_2,
1877   VEX_LEN_0F93_P_3,
1878   VEX_LEN_0F98_P_0,
1879   VEX_LEN_0F98_P_2,
1880   VEX_LEN_0F99_P_0,
1881   VEX_LEN_0F99_P_2,
1882   VEX_LEN_0FAE_R_2_M_0,
1883   VEX_LEN_0FAE_R_3_M_0,
1884   VEX_LEN_0FC2_P_1,
1885   VEX_LEN_0FC2_P_3,
1886   VEX_LEN_0FC4_P_2,
1887   VEX_LEN_0FC5_P_2,
1888   VEX_LEN_0FD6_P_2,
1889   VEX_LEN_0FF7_P_2,
1890   VEX_LEN_0F3816_P_2,
1891   VEX_LEN_0F3819_P_2,
1892   VEX_LEN_0F381A_P_2_M_0,
1893   VEX_LEN_0F3836_P_2,
1894   VEX_LEN_0F3841_P_2,
1895   VEX_LEN_0F385A_P_2_M_0,
1896   VEX_LEN_0F38DB_P_2,
1897   VEX_LEN_0F38F2_P_0,
1898   VEX_LEN_0F38F3_R_1_P_0,
1899   VEX_LEN_0F38F3_R_2_P_0,
1900   VEX_LEN_0F38F3_R_3_P_0,
1901   VEX_LEN_0F38F5_P_0,
1902   VEX_LEN_0F38F5_P_1,
1903   VEX_LEN_0F38F5_P_3,
1904   VEX_LEN_0F38F6_P_3,
1905   VEX_LEN_0F38F7_P_0,
1906   VEX_LEN_0F38F7_P_1,
1907   VEX_LEN_0F38F7_P_2,
1908   VEX_LEN_0F38F7_P_3,
1909   VEX_LEN_0F3A00_P_2,
1910   VEX_LEN_0F3A01_P_2,
1911   VEX_LEN_0F3A06_P_2,
1912   VEX_LEN_0F3A0A_P_2,
1913   VEX_LEN_0F3A0B_P_2,
1914   VEX_LEN_0F3A14_P_2,
1915   VEX_LEN_0F3A15_P_2,
1916   VEX_LEN_0F3A16_P_2,
1917   VEX_LEN_0F3A17_P_2,
1918   VEX_LEN_0F3A18_P_2,
1919   VEX_LEN_0F3A19_P_2,
1920   VEX_LEN_0F3A20_P_2,
1921   VEX_LEN_0F3A21_P_2,
1922   VEX_LEN_0F3A22_P_2,
1923   VEX_LEN_0F3A30_P_2,
1924   VEX_LEN_0F3A31_P_2,
1925   VEX_LEN_0F3A32_P_2,
1926   VEX_LEN_0F3A33_P_2,
1927   VEX_LEN_0F3A38_P_2,
1928   VEX_LEN_0F3A39_P_2,
1929   VEX_LEN_0F3A41_P_2,
1930   VEX_LEN_0F3A46_P_2,
1931   VEX_LEN_0F3A60_P_2,
1932   VEX_LEN_0F3A61_P_2,
1933   VEX_LEN_0F3A62_P_2,
1934   VEX_LEN_0F3A63_P_2,
1935   VEX_LEN_0F3A6A_P_2,
1936   VEX_LEN_0F3A6B_P_2,
1937   VEX_LEN_0F3A6E_P_2,
1938   VEX_LEN_0F3A6F_P_2,
1939   VEX_LEN_0F3A7A_P_2,
1940   VEX_LEN_0F3A7B_P_2,
1941   VEX_LEN_0F3A7E_P_2,
1942   VEX_LEN_0F3A7F_P_2,
1943   VEX_LEN_0F3ADF_P_2,
1944   VEX_LEN_0F3AF0_P_3,
1945   VEX_LEN_0FXOP_08_CC,
1946   VEX_LEN_0FXOP_08_CD,
1947   VEX_LEN_0FXOP_08_CE,
1948   VEX_LEN_0FXOP_08_CF,
1949   VEX_LEN_0FXOP_08_EC,
1950   VEX_LEN_0FXOP_08_ED,
1951   VEX_LEN_0FXOP_08_EE,
1952   VEX_LEN_0FXOP_08_EF,
1953   VEX_LEN_0FXOP_09_80,
1954   VEX_LEN_0FXOP_09_81
1955 };
1956
1957 enum
1958 {
1959   VEX_W_0F10_P_0 = 0,
1960   VEX_W_0F10_P_1,
1961   VEX_W_0F10_P_2,
1962   VEX_W_0F10_P_3,
1963   VEX_W_0F11_P_0,
1964   VEX_W_0F11_P_1,
1965   VEX_W_0F11_P_2,
1966   VEX_W_0F11_P_3,
1967   VEX_W_0F12_P_0_M_0,
1968   VEX_W_0F12_P_0_M_1,
1969   VEX_W_0F12_P_1,
1970   VEX_W_0F12_P_2,
1971   VEX_W_0F12_P_3,
1972   VEX_W_0F13_M_0,
1973   VEX_W_0F14,
1974   VEX_W_0F15,
1975   VEX_W_0F16_P_0_M_0,
1976   VEX_W_0F16_P_0_M_1,
1977   VEX_W_0F16_P_1,
1978   VEX_W_0F16_P_2,
1979   VEX_W_0F17_M_0,
1980   VEX_W_0F28,
1981   VEX_W_0F29,
1982   VEX_W_0F2B_M_0,
1983   VEX_W_0F2E_P_0,
1984   VEX_W_0F2E_P_2,
1985   VEX_W_0F2F_P_0,
1986   VEX_W_0F2F_P_2,
1987   VEX_W_0F41_P_0_LEN_1,
1988   VEX_W_0F41_P_2_LEN_1,
1989   VEX_W_0F42_P_0_LEN_1,
1990   VEX_W_0F42_P_2_LEN_1,
1991   VEX_W_0F44_P_0_LEN_0,
1992   VEX_W_0F44_P_2_LEN_0,
1993   VEX_W_0F45_P_0_LEN_1,
1994   VEX_W_0F45_P_2_LEN_1,
1995   VEX_W_0F46_P_0_LEN_1,
1996   VEX_W_0F46_P_2_LEN_1,
1997   VEX_W_0F47_P_0_LEN_1,
1998   VEX_W_0F47_P_2_LEN_1,
1999   VEX_W_0F4A_P_0_LEN_1,
2000   VEX_W_0F4A_P_2_LEN_1,
2001   VEX_W_0F4B_P_0_LEN_1,
2002   VEX_W_0F4B_P_2_LEN_1,
2003   VEX_W_0F50_M_0,
2004   VEX_W_0F51_P_0,
2005   VEX_W_0F51_P_1,
2006   VEX_W_0F51_P_2,
2007   VEX_W_0F51_P_3,
2008   VEX_W_0F52_P_0,
2009   VEX_W_0F52_P_1,
2010   VEX_W_0F53_P_0,
2011   VEX_W_0F53_P_1,
2012   VEX_W_0F58_P_0,
2013   VEX_W_0F58_P_1,
2014   VEX_W_0F58_P_2,
2015   VEX_W_0F58_P_3,
2016   VEX_W_0F59_P_0,
2017   VEX_W_0F59_P_1,
2018   VEX_W_0F59_P_2,
2019   VEX_W_0F59_P_3,
2020   VEX_W_0F5A_P_0,
2021   VEX_W_0F5A_P_1,
2022   VEX_W_0F5A_P_3,
2023   VEX_W_0F5B_P_0,
2024   VEX_W_0F5B_P_1,
2025   VEX_W_0F5B_P_2,
2026   VEX_W_0F5C_P_0,
2027   VEX_W_0F5C_P_1,
2028   VEX_W_0F5C_P_2,
2029   VEX_W_0F5C_P_3,
2030   VEX_W_0F5D_P_0,
2031   VEX_W_0F5D_P_1,
2032   VEX_W_0F5D_P_2,
2033   VEX_W_0F5D_P_3,
2034   VEX_W_0F5E_P_0,
2035   VEX_W_0F5E_P_1,
2036   VEX_W_0F5E_P_2,
2037   VEX_W_0F5E_P_3,
2038   VEX_W_0F5F_P_0,
2039   VEX_W_0F5F_P_1,
2040   VEX_W_0F5F_P_2,
2041   VEX_W_0F5F_P_3,
2042   VEX_W_0F60_P_2,
2043   VEX_W_0F61_P_2,
2044   VEX_W_0F62_P_2,
2045   VEX_W_0F63_P_2,
2046   VEX_W_0F64_P_2,
2047   VEX_W_0F65_P_2,
2048   VEX_W_0F66_P_2,
2049   VEX_W_0F67_P_2,
2050   VEX_W_0F68_P_2,
2051   VEX_W_0F69_P_2,
2052   VEX_W_0F6A_P_2,
2053   VEX_W_0F6B_P_2,
2054   VEX_W_0F6C_P_2,
2055   VEX_W_0F6D_P_2,
2056   VEX_W_0F6F_P_1,
2057   VEX_W_0F6F_P_2,
2058   VEX_W_0F70_P_1,
2059   VEX_W_0F70_P_2,
2060   VEX_W_0F70_P_3,
2061   VEX_W_0F71_R_2_P_2,
2062   VEX_W_0F71_R_4_P_2,
2063   VEX_W_0F71_R_6_P_2,
2064   VEX_W_0F72_R_2_P_2,
2065   VEX_W_0F72_R_4_P_2,
2066   VEX_W_0F72_R_6_P_2,
2067   VEX_W_0F73_R_2_P_2,
2068   VEX_W_0F73_R_3_P_2,
2069   VEX_W_0F73_R_6_P_2,
2070   VEX_W_0F73_R_7_P_2,
2071   VEX_W_0F74_P_2,
2072   VEX_W_0F75_P_2,
2073   VEX_W_0F76_P_2,
2074   VEX_W_0F77_P_0,
2075   VEX_W_0F7C_P_2,
2076   VEX_W_0F7C_P_3,
2077   VEX_W_0F7D_P_2,
2078   VEX_W_0F7D_P_3,
2079   VEX_W_0F7E_P_1,
2080   VEX_W_0F7F_P_1,
2081   VEX_W_0F7F_P_2,
2082   VEX_W_0F90_P_0_LEN_0,
2083   VEX_W_0F90_P_2_LEN_0,
2084   VEX_W_0F91_P_0_LEN_0,
2085   VEX_W_0F91_P_2_LEN_0,
2086   VEX_W_0F92_P_0_LEN_0,
2087   VEX_W_0F92_P_2_LEN_0,
2088   VEX_W_0F92_P_3_LEN_0,
2089   VEX_W_0F93_P_0_LEN_0,
2090   VEX_W_0F93_P_2_LEN_0,
2091   VEX_W_0F93_P_3_LEN_0,
2092   VEX_W_0F98_P_0_LEN_0,
2093   VEX_W_0F98_P_2_LEN_0,
2094   VEX_W_0F99_P_0_LEN_0,
2095   VEX_W_0F99_P_2_LEN_0,
2096   VEX_W_0FAE_R_2_M_0,
2097   VEX_W_0FAE_R_3_M_0,
2098   VEX_W_0FC2_P_0,
2099   VEX_W_0FC2_P_1,
2100   VEX_W_0FC2_P_2,
2101   VEX_W_0FC2_P_3,
2102   VEX_W_0FC4_P_2,
2103   VEX_W_0FC5_P_2,
2104   VEX_W_0FD0_P_2,
2105   VEX_W_0FD0_P_3,
2106   VEX_W_0FD1_P_2,
2107   VEX_W_0FD2_P_2,
2108   VEX_W_0FD3_P_2,
2109   VEX_W_0FD4_P_2,
2110   VEX_W_0FD5_P_2,
2111   VEX_W_0FD6_P_2,
2112   VEX_W_0FD7_P_2_M_1,
2113   VEX_W_0FD8_P_2,
2114   VEX_W_0FD9_P_2,
2115   VEX_W_0FDA_P_2,
2116   VEX_W_0FDB_P_2,
2117   VEX_W_0FDC_P_2,
2118   VEX_W_0FDD_P_2,
2119   VEX_W_0FDE_P_2,
2120   VEX_W_0FDF_P_2,
2121   VEX_W_0FE0_P_2,
2122   VEX_W_0FE1_P_2,
2123   VEX_W_0FE2_P_2,
2124   VEX_W_0FE3_P_2,
2125   VEX_W_0FE4_P_2,
2126   VEX_W_0FE5_P_2,
2127   VEX_W_0FE6_P_1,
2128   VEX_W_0FE6_P_2,
2129   VEX_W_0FE6_P_3,
2130   VEX_W_0FE7_P_2_M_0,
2131   VEX_W_0FE8_P_2,
2132   VEX_W_0FE9_P_2,
2133   VEX_W_0FEA_P_2,
2134   VEX_W_0FEB_P_2,
2135   VEX_W_0FEC_P_2,
2136   VEX_W_0FED_P_2,
2137   VEX_W_0FEE_P_2,
2138   VEX_W_0FEF_P_2,
2139   VEX_W_0FF0_P_3_M_0,
2140   VEX_W_0FF1_P_2,
2141   VEX_W_0FF2_P_2,
2142   VEX_W_0FF3_P_2,
2143   VEX_W_0FF4_P_2,
2144   VEX_W_0FF5_P_2,
2145   VEX_W_0FF6_P_2,
2146   VEX_W_0FF7_P_2,
2147   VEX_W_0FF8_P_2,
2148   VEX_W_0FF9_P_2,
2149   VEX_W_0FFA_P_2,
2150   VEX_W_0FFB_P_2,
2151   VEX_W_0FFC_P_2,
2152   VEX_W_0FFD_P_2,
2153   VEX_W_0FFE_P_2,
2154   VEX_W_0F3800_P_2,
2155   VEX_W_0F3801_P_2,
2156   VEX_W_0F3802_P_2,
2157   VEX_W_0F3803_P_2,
2158   VEX_W_0F3804_P_2,
2159   VEX_W_0F3805_P_2,
2160   VEX_W_0F3806_P_2,
2161   VEX_W_0F3807_P_2,
2162   VEX_W_0F3808_P_2,
2163   VEX_W_0F3809_P_2,
2164   VEX_W_0F380A_P_2,
2165   VEX_W_0F380B_P_2,
2166   VEX_W_0F380C_P_2,
2167   VEX_W_0F380D_P_2,
2168   VEX_W_0F380E_P_2,
2169   VEX_W_0F380F_P_2,
2170   VEX_W_0F3816_P_2,
2171   VEX_W_0F3817_P_2,
2172   VEX_W_0F3818_P_2,
2173   VEX_W_0F3819_P_2,
2174   VEX_W_0F381A_P_2_M_0,
2175   VEX_W_0F381C_P_2,
2176   VEX_W_0F381D_P_2,
2177   VEX_W_0F381E_P_2,
2178   VEX_W_0F3820_P_2,
2179   VEX_W_0F3821_P_2,
2180   VEX_W_0F3822_P_2,
2181   VEX_W_0F3823_P_2,
2182   VEX_W_0F3824_P_2,
2183   VEX_W_0F3825_P_2,
2184   VEX_W_0F3828_P_2,
2185   VEX_W_0F3829_P_2,
2186   VEX_W_0F382A_P_2_M_0,
2187   VEX_W_0F382B_P_2,
2188   VEX_W_0F382C_P_2_M_0,
2189   VEX_W_0F382D_P_2_M_0,
2190   VEX_W_0F382E_P_2_M_0,
2191   VEX_W_0F382F_P_2_M_0,
2192   VEX_W_0F3830_P_2,
2193   VEX_W_0F3831_P_2,
2194   VEX_W_0F3832_P_2,
2195   VEX_W_0F3833_P_2,
2196   VEX_W_0F3834_P_2,
2197   VEX_W_0F3835_P_2,
2198   VEX_W_0F3836_P_2,
2199   VEX_W_0F3837_P_2,
2200   VEX_W_0F3838_P_2,
2201   VEX_W_0F3839_P_2,
2202   VEX_W_0F383A_P_2,
2203   VEX_W_0F383B_P_2,
2204   VEX_W_0F383C_P_2,
2205   VEX_W_0F383D_P_2,
2206   VEX_W_0F383E_P_2,
2207   VEX_W_0F383F_P_2,
2208   VEX_W_0F3840_P_2,
2209   VEX_W_0F3841_P_2,
2210   VEX_W_0F3846_P_2,
2211   VEX_W_0F3858_P_2,
2212   VEX_W_0F3859_P_2,
2213   VEX_W_0F385A_P_2_M_0,
2214   VEX_W_0F3878_P_2,
2215   VEX_W_0F3879_P_2,
2216   VEX_W_0F38CF_P_2,
2217   VEX_W_0F38DB_P_2,
2218   VEX_W_0F3A00_P_2,
2219   VEX_W_0F3A01_P_2,
2220   VEX_W_0F3A02_P_2,
2221   VEX_W_0F3A04_P_2,
2222   VEX_W_0F3A05_P_2,
2223   VEX_W_0F3A06_P_2,
2224   VEX_W_0F3A08_P_2,
2225   VEX_W_0F3A09_P_2,
2226   VEX_W_0F3A0A_P_2,
2227   VEX_W_0F3A0B_P_2,
2228   VEX_W_0F3A0C_P_2,
2229   VEX_W_0F3A0D_P_2,
2230   VEX_W_0F3A0E_P_2,
2231   VEX_W_0F3A0F_P_2,
2232   VEX_W_0F3A14_P_2,
2233   VEX_W_0F3A15_P_2,
2234   VEX_W_0F3A18_P_2,
2235   VEX_W_0F3A19_P_2,
2236   VEX_W_0F3A20_P_2,
2237   VEX_W_0F3A21_P_2,
2238   VEX_W_0F3A30_P_2_LEN_0,
2239   VEX_W_0F3A31_P_2_LEN_0,
2240   VEX_W_0F3A32_P_2_LEN_0,
2241   VEX_W_0F3A33_P_2_LEN_0,
2242   VEX_W_0F3A38_P_2,
2243   VEX_W_0F3A39_P_2,
2244   VEX_W_0F3A40_P_2,
2245   VEX_W_0F3A41_P_2,
2246   VEX_W_0F3A42_P_2,
2247   VEX_W_0F3A46_P_2,
2248   VEX_W_0F3A48_P_2,
2249   VEX_W_0F3A49_P_2,
2250   VEX_W_0F3A4A_P_2,
2251   VEX_W_0F3A4B_P_2,
2252   VEX_W_0F3A4C_P_2,
2253   VEX_W_0F3A62_P_2,
2254   VEX_W_0F3A63_P_2,
2255   VEX_W_0F3ACE_P_2,
2256   VEX_W_0F3ACF_P_2,
2257   VEX_W_0F3ADF_P_2,
2258
2259   EVEX_W_0F10_P_0,
2260   EVEX_W_0F10_P_1_M_0,
2261   EVEX_W_0F10_P_1_M_1,
2262   EVEX_W_0F10_P_2,
2263   EVEX_W_0F10_P_3_M_0,
2264   EVEX_W_0F10_P_3_M_1,
2265   EVEX_W_0F11_P_0,
2266   EVEX_W_0F11_P_1_M_0,
2267   EVEX_W_0F11_P_1_M_1,
2268   EVEX_W_0F11_P_2,
2269   EVEX_W_0F11_P_3_M_0,
2270   EVEX_W_0F11_P_3_M_1,
2271   EVEX_W_0F12_P_0_M_0,
2272   EVEX_W_0F12_P_0_M_1,
2273   EVEX_W_0F12_P_1,
2274   EVEX_W_0F12_P_2,
2275   EVEX_W_0F12_P_3,
2276   EVEX_W_0F13_P_0,
2277   EVEX_W_0F13_P_2,
2278   EVEX_W_0F14_P_0,
2279   EVEX_W_0F14_P_2,
2280   EVEX_W_0F15_P_0,
2281   EVEX_W_0F15_P_2,
2282   EVEX_W_0F16_P_0_M_0,
2283   EVEX_W_0F16_P_0_M_1,
2284   EVEX_W_0F16_P_1,
2285   EVEX_W_0F16_P_2,
2286   EVEX_W_0F17_P_0,
2287   EVEX_W_0F17_P_2,
2288   EVEX_W_0F28_P_0,
2289   EVEX_W_0F28_P_2,
2290   EVEX_W_0F29_P_0,
2291   EVEX_W_0F29_P_2,
2292   EVEX_W_0F2A_P_1,
2293   EVEX_W_0F2A_P_3,
2294   EVEX_W_0F2B_P_0,
2295   EVEX_W_0F2B_P_2,
2296   EVEX_W_0F2E_P_0,
2297   EVEX_W_0F2E_P_2,
2298   EVEX_W_0F2F_P_0,
2299   EVEX_W_0F2F_P_2,
2300   EVEX_W_0F51_P_0,
2301   EVEX_W_0F51_P_1,
2302   EVEX_W_0F51_P_2,
2303   EVEX_W_0F51_P_3,
2304   EVEX_W_0F54_P_0,
2305   EVEX_W_0F54_P_2,
2306   EVEX_W_0F55_P_0,
2307   EVEX_W_0F55_P_2,
2308   EVEX_W_0F56_P_0,
2309   EVEX_W_0F56_P_2,
2310   EVEX_W_0F57_P_0,
2311   EVEX_W_0F57_P_2,
2312   EVEX_W_0F58_P_0,
2313   EVEX_W_0F58_P_1,
2314   EVEX_W_0F58_P_2,
2315   EVEX_W_0F58_P_3,
2316   EVEX_W_0F59_P_0,
2317   EVEX_W_0F59_P_1,
2318   EVEX_W_0F59_P_2,
2319   EVEX_W_0F59_P_3,
2320   EVEX_W_0F5A_P_0,
2321   EVEX_W_0F5A_P_1,
2322   EVEX_W_0F5A_P_2,
2323   EVEX_W_0F5A_P_3,
2324   EVEX_W_0F5B_P_0,
2325   EVEX_W_0F5B_P_1,
2326   EVEX_W_0F5B_P_2,
2327   EVEX_W_0F5C_P_0,
2328   EVEX_W_0F5C_P_1,
2329   EVEX_W_0F5C_P_2,
2330   EVEX_W_0F5C_P_3,
2331   EVEX_W_0F5D_P_0,
2332   EVEX_W_0F5D_P_1,
2333   EVEX_W_0F5D_P_2,
2334   EVEX_W_0F5D_P_3,
2335   EVEX_W_0F5E_P_0,
2336   EVEX_W_0F5E_P_1,
2337   EVEX_W_0F5E_P_2,
2338   EVEX_W_0F5E_P_3,
2339   EVEX_W_0F5F_P_0,
2340   EVEX_W_0F5F_P_1,
2341   EVEX_W_0F5F_P_2,
2342   EVEX_W_0F5F_P_3,
2343   EVEX_W_0F62_P_2,
2344   EVEX_W_0F66_P_2,
2345   EVEX_W_0F6A_P_2,
2346   EVEX_W_0F6B_P_2,
2347   EVEX_W_0F6C_P_2,
2348   EVEX_W_0F6D_P_2,
2349   EVEX_W_0F6E_P_2,
2350   EVEX_W_0F6F_P_1,
2351   EVEX_W_0F6F_P_2,
2352   EVEX_W_0F6F_P_3,
2353   EVEX_W_0F70_P_2,
2354   EVEX_W_0F72_R_2_P_2,
2355   EVEX_W_0F72_R_6_P_2,
2356   EVEX_W_0F73_R_2_P_2,
2357   EVEX_W_0F73_R_6_P_2,
2358   EVEX_W_0F76_P_2,
2359   EVEX_W_0F78_P_0,
2360   EVEX_W_0F78_P_2,
2361   EVEX_W_0F79_P_0,
2362   EVEX_W_0F79_P_2,
2363   EVEX_W_0F7A_P_1,
2364   EVEX_W_0F7A_P_2,
2365   EVEX_W_0F7A_P_3,
2366   EVEX_W_0F7B_P_1,
2367   EVEX_W_0F7B_P_2,
2368   EVEX_W_0F7B_P_3,
2369   EVEX_W_0F7E_P_1,
2370   EVEX_W_0F7E_P_2,
2371   EVEX_W_0F7F_P_1,
2372   EVEX_W_0F7F_P_2,
2373   EVEX_W_0F7F_P_3,
2374   EVEX_W_0FC2_P_0,
2375   EVEX_W_0FC2_P_1,
2376   EVEX_W_0FC2_P_2,
2377   EVEX_W_0FC2_P_3,
2378   EVEX_W_0FC6_P_0,
2379   EVEX_W_0FC6_P_2,
2380   EVEX_W_0FD2_P_2,
2381   EVEX_W_0FD3_P_2,
2382   EVEX_W_0FD4_P_2,
2383   EVEX_W_0FD6_P_2,
2384   EVEX_W_0FE6_P_1,
2385   EVEX_W_0FE6_P_2,
2386   EVEX_W_0FE6_P_3,
2387   EVEX_W_0FE7_P_2,
2388   EVEX_W_0FF2_P_2,
2389   EVEX_W_0FF3_P_2,
2390   EVEX_W_0FF4_P_2,
2391   EVEX_W_0FFA_P_2,
2392   EVEX_W_0FFB_P_2,
2393   EVEX_W_0FFE_P_2,
2394   EVEX_W_0F380C_P_2,
2395   EVEX_W_0F380D_P_2,
2396   EVEX_W_0F3810_P_1,
2397   EVEX_W_0F3810_P_2,
2398   EVEX_W_0F3811_P_1,
2399   EVEX_W_0F3811_P_2,
2400   EVEX_W_0F3812_P_1,
2401   EVEX_W_0F3812_P_2,
2402   EVEX_W_0F3813_P_1,
2403   EVEX_W_0F3813_P_2,
2404   EVEX_W_0F3814_P_1,
2405   EVEX_W_0F3815_P_1,
2406   EVEX_W_0F3818_P_2,
2407   EVEX_W_0F3819_P_2,
2408   EVEX_W_0F381A_P_2,
2409   EVEX_W_0F381B_P_2,
2410   EVEX_W_0F381E_P_2,
2411   EVEX_W_0F381F_P_2,
2412   EVEX_W_0F3820_P_1,
2413   EVEX_W_0F3821_P_1,
2414   EVEX_W_0F3822_P_1,
2415   EVEX_W_0F3823_P_1,
2416   EVEX_W_0F3824_P_1,
2417   EVEX_W_0F3825_P_1,
2418   EVEX_W_0F3825_P_2,
2419   EVEX_W_0F3826_P_1,
2420   EVEX_W_0F3826_P_2,
2421   EVEX_W_0F3828_P_1,
2422   EVEX_W_0F3828_P_2,
2423   EVEX_W_0F3829_P_1,
2424   EVEX_W_0F3829_P_2,
2425   EVEX_W_0F382A_P_1,
2426   EVEX_W_0F382A_P_2,
2427   EVEX_W_0F382B_P_2,
2428   EVEX_W_0F3830_P_1,
2429   EVEX_W_0F3831_P_1,
2430   EVEX_W_0F3832_P_1,
2431   EVEX_W_0F3833_P_1,
2432   EVEX_W_0F3834_P_1,
2433   EVEX_W_0F3835_P_1,
2434   EVEX_W_0F3835_P_2,
2435   EVEX_W_0F3837_P_2,
2436   EVEX_W_0F3838_P_1,
2437   EVEX_W_0F3839_P_1,
2438   EVEX_W_0F383A_P_1,
2439   EVEX_W_0F3840_P_2,
2440   EVEX_W_0F3854_P_2,
2441   EVEX_W_0F3855_P_2,
2442   EVEX_W_0F3858_P_2,
2443   EVEX_W_0F3859_P_2,
2444   EVEX_W_0F385A_P_2,
2445   EVEX_W_0F385B_P_2,
2446   EVEX_W_0F3862_P_2,
2447   EVEX_W_0F3863_P_2,
2448   EVEX_W_0F3866_P_2,
2449   EVEX_W_0F3870_P_2,
2450   EVEX_W_0F3871_P_2,
2451   EVEX_W_0F3872_P_2,
2452   EVEX_W_0F3873_P_2,
2453   EVEX_W_0F3875_P_2,
2454   EVEX_W_0F3878_P_2,
2455   EVEX_W_0F3879_P_2,
2456   EVEX_W_0F387A_P_2,
2457   EVEX_W_0F387B_P_2,
2458   EVEX_W_0F387D_P_2,
2459   EVEX_W_0F3883_P_2,
2460   EVEX_W_0F388D_P_2,
2461   EVEX_W_0F3891_P_2,
2462   EVEX_W_0F3893_P_2,
2463   EVEX_W_0F38A1_P_2,
2464   EVEX_W_0F38A3_P_2,
2465   EVEX_W_0F38C7_R_1_P_2,
2466   EVEX_W_0F38C7_R_2_P_2,
2467   EVEX_W_0F38C7_R_5_P_2,
2468   EVEX_W_0F38C7_R_6_P_2,
2469
2470   EVEX_W_0F3A00_P_2,
2471   EVEX_W_0F3A01_P_2,
2472   EVEX_W_0F3A04_P_2,
2473   EVEX_W_0F3A05_P_2,
2474   EVEX_W_0F3A08_P_2,
2475   EVEX_W_0F3A09_P_2,
2476   EVEX_W_0F3A0A_P_2,
2477   EVEX_W_0F3A0B_P_2,
2478   EVEX_W_0F3A16_P_2,
2479   EVEX_W_0F3A18_P_2,
2480   EVEX_W_0F3A19_P_2,
2481   EVEX_W_0F3A1A_P_2,
2482   EVEX_W_0F3A1B_P_2,
2483   EVEX_W_0F3A1D_P_2,
2484   EVEX_W_0F3A21_P_2,
2485   EVEX_W_0F3A22_P_2,
2486   EVEX_W_0F3A23_P_2,
2487   EVEX_W_0F3A38_P_2,
2488   EVEX_W_0F3A39_P_2,
2489   EVEX_W_0F3A3A_P_2,
2490   EVEX_W_0F3A3B_P_2,
2491   EVEX_W_0F3A3E_P_2,
2492   EVEX_W_0F3A3F_P_2,
2493   EVEX_W_0F3A42_P_2,
2494   EVEX_W_0F3A43_P_2,
2495   EVEX_W_0F3A50_P_2,
2496   EVEX_W_0F3A51_P_2,
2497   EVEX_W_0F3A56_P_2,
2498   EVEX_W_0F3A57_P_2,
2499   EVEX_W_0F3A66_P_2,
2500   EVEX_W_0F3A67_P_2,
2501   EVEX_W_0F3A70_P_2,
2502   EVEX_W_0F3A71_P_2,
2503   EVEX_W_0F3A72_P_2,
2504   EVEX_W_0F3A73_P_2,
2505   EVEX_W_0F3ACE_P_2,
2506   EVEX_W_0F3ACF_P_2
2507 };
2508
2509 typedef void (*op_rtn) (int bytemode, int sizeflag);
2510
2511 struct dis386 {
2512   const char *name;
2513   struct
2514     {
2515       op_rtn rtn;
2516       int bytemode;
2517     } op[MAX_OPERANDS];
2518   unsigned int prefix_requirement;
2519 };
2520
2521 /* Upper case letters in the instruction names here are macros.
2522    'A' => print 'b' if no register operands or suffix_always is true
2523    'B' => print 'b' if suffix_always is true
2524    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2525           size prefix
2526    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2527           suffix_always is true
2528    'E' => print 'e' if 32-bit form of jcxz
2529    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2530    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2531    'H' => print ",pt" or ",pn" branch hint
2532    'I' => honor following macro letter even in Intel mode (implemented only
2533           for some of the macro letters)
2534    'J' => print 'l'
2535    'K' => print 'd' or 'q' if rex prefix is present.
2536    'L' => print 'l' if suffix_always is true
2537    'M' => print 'r' if intel_mnemonic is false.
2538    'N' => print 'n' if instruction has no wait "prefix"
2539    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2540    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2541           or suffix_always is true.  print 'q' if rex prefix is present.
2542    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2543           is true
2544    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2545    'S' => print 'w', 'l' or 'q' if suffix_always is true
2546    'T' => print 'q' in 64bit mode if instruction has no operand size
2547           prefix and behave as 'P' otherwise
2548    'U' => print 'q' in 64bit mode if instruction has no operand size
2549           prefix and behave as 'Q' otherwise
2550    'V' => print 'q' in 64bit mode if instruction has no operand size
2551           prefix and behave as 'S' otherwise
2552    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2553    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2554    'Y' unused.
2555    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2556    '!' => change condition from true to false or from false to true.
2557    '%' => add 1 upper case letter to the macro.
2558    '^' => print 'w' or 'l' depending on operand size prefix or
2559           suffix_always is true (lcall/ljmp).
2560    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2561           on operand size prefix.
2562    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2563           has no operand size prefix for AMD64 ISA, behave as 'P'
2564           otherwise
2565
2566    2 upper case letter macros:
2567    "XY" => print 'x' or 'y' if suffix_always is true or no register
2568            operands and no broadcast.
2569    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2570            register operands and no broadcast.
2571    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2572    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2573            or suffix_always is true
2574    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2575    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2576    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2577    "LW" => print 'd', 'q' depending on the VEX.W bit
2578    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2579            an operand size prefix, or suffix_always is true.  print
2580            'q' if rex prefix is present.
2581
2582    Many of the above letters print nothing in Intel mode.  See "putop"
2583    for the details.
2584
2585    Braces '{' and '}', and vertical bars '|', indicate alternative
2586    mnemonic strings for AT&T and Intel.  */
2587
2588 static const struct dis386 dis386[] = {
2589   /* 00 */
2590   { "addB",             { Ebh1, Gb }, 0 },
2591   { "addS",             { Evh1, Gv }, 0 },
2592   { "addB",             { Gb, EbS }, 0 },
2593   { "addS",             { Gv, EvS }, 0 },
2594   { "addB",             { AL, Ib }, 0 },
2595   { "addS",             { eAX, Iv }, 0 },
2596   { X86_64_TABLE (X86_64_06) },
2597   { X86_64_TABLE (X86_64_07) },
2598   /* 08 */
2599   { "orB",              { Ebh1, Gb }, 0 },
2600   { "orS",              { Evh1, Gv }, 0 },
2601   { "orB",              { Gb, EbS }, 0 },
2602   { "orS",              { Gv, EvS }, 0 },
2603   { "orB",              { AL, Ib }, 0 },
2604   { "orS",              { eAX, Iv }, 0 },
2605   { X86_64_TABLE (X86_64_0D) },
2606   { Bad_Opcode },       /* 0x0f extended opcode escape */
2607   /* 10 */
2608   { "adcB",             { Ebh1, Gb }, 0 },
2609   { "adcS",             { Evh1, Gv }, 0 },
2610   { "adcB",             { Gb, EbS }, 0 },
2611   { "adcS",             { Gv, EvS }, 0 },
2612   { "adcB",             { AL, Ib }, 0 },
2613   { "adcS",             { eAX, Iv }, 0 },
2614   { X86_64_TABLE (X86_64_16) },
2615   { X86_64_TABLE (X86_64_17) },
2616   /* 18 */
2617   { "sbbB",             { Ebh1, Gb }, 0 },
2618   { "sbbS",             { Evh1, Gv }, 0 },
2619   { "sbbB",             { Gb, EbS }, 0 },
2620   { "sbbS",             { Gv, EvS }, 0 },
2621   { "sbbB",             { AL, Ib }, 0 },
2622   { "sbbS",             { eAX, Iv }, 0 },
2623   { X86_64_TABLE (X86_64_1E) },
2624   { X86_64_TABLE (X86_64_1F) },
2625   /* 20 */
2626   { "andB",             { Ebh1, Gb }, 0 },
2627   { "andS",             { Evh1, Gv }, 0 },
2628   { "andB",             { Gb, EbS }, 0 },
2629   { "andS",             { Gv, EvS }, 0 },
2630   { "andB",             { AL, Ib }, 0 },
2631   { "andS",             { eAX, Iv }, 0 },
2632   { Bad_Opcode },       /* SEG ES prefix */
2633   { X86_64_TABLE (X86_64_27) },
2634   /* 28 */
2635   { "subB",             { Ebh1, Gb }, 0 },
2636   { "subS",             { Evh1, Gv }, 0 },
2637   { "subB",             { Gb, EbS }, 0 },
2638   { "subS",             { Gv, EvS }, 0 },
2639   { "subB",             { AL, Ib }, 0 },
2640   { "subS",             { eAX, Iv }, 0 },
2641   { Bad_Opcode },       /* SEG CS prefix */
2642   { X86_64_TABLE (X86_64_2F) },
2643   /* 30 */
2644   { "xorB",             { Ebh1, Gb }, 0 },
2645   { "xorS",             { Evh1, Gv }, 0 },
2646   { "xorB",             { Gb, EbS }, 0 },
2647   { "xorS",             { Gv, EvS }, 0 },
2648   { "xorB",             { AL, Ib }, 0 },
2649   { "xorS",             { eAX, Iv }, 0 },
2650   { Bad_Opcode },       /* SEG SS prefix */
2651   { X86_64_TABLE (X86_64_37) },
2652   /* 38 */
2653   { "cmpB",             { Eb, Gb }, 0 },
2654   { "cmpS",             { Ev, Gv }, 0 },
2655   { "cmpB",             { Gb, EbS }, 0 },
2656   { "cmpS",             { Gv, EvS }, 0 },
2657   { "cmpB",             { AL, Ib }, 0 },
2658   { "cmpS",             { eAX, Iv }, 0 },
2659   { Bad_Opcode },       /* SEG DS prefix */
2660   { X86_64_TABLE (X86_64_3F) },
2661   /* 40 */
2662   { "inc{S|}",          { RMeAX }, 0 },
2663   { "inc{S|}",          { RMeCX }, 0 },
2664   { "inc{S|}",          { RMeDX }, 0 },
2665   { "inc{S|}",          { RMeBX }, 0 },
2666   { "inc{S|}",          { RMeSP }, 0 },
2667   { "inc{S|}",          { RMeBP }, 0 },
2668   { "inc{S|}",          { RMeSI }, 0 },
2669   { "inc{S|}",          { RMeDI }, 0 },
2670   /* 48 */
2671   { "dec{S|}",          { RMeAX }, 0 },
2672   { "dec{S|}",          { RMeCX }, 0 },
2673   { "dec{S|}",          { RMeDX }, 0 },
2674   { "dec{S|}",          { RMeBX }, 0 },
2675   { "dec{S|}",          { RMeSP }, 0 },
2676   { "dec{S|}",          { RMeBP }, 0 },
2677   { "dec{S|}",          { RMeSI }, 0 },
2678   { "dec{S|}",          { RMeDI }, 0 },
2679   /* 50 */
2680   { "pushV",            { RMrAX }, 0 },
2681   { "pushV",            { RMrCX }, 0 },
2682   { "pushV",            { RMrDX }, 0 },
2683   { "pushV",            { RMrBX }, 0 },
2684   { "pushV",            { RMrSP }, 0 },
2685   { "pushV",            { RMrBP }, 0 },
2686   { "pushV",            { RMrSI }, 0 },
2687   { "pushV",            { RMrDI }, 0 },
2688   /* 58 */
2689   { "popV",             { RMrAX }, 0 },
2690   { "popV",             { RMrCX }, 0 },
2691   { "popV",             { RMrDX }, 0 },
2692   { "popV",             { RMrBX }, 0 },
2693   { "popV",             { RMrSP }, 0 },
2694   { "popV",             { RMrBP }, 0 },
2695   { "popV",             { RMrSI }, 0 },
2696   { "popV",             { RMrDI }, 0 },
2697   /* 60 */
2698   { X86_64_TABLE (X86_64_60) },
2699   { X86_64_TABLE (X86_64_61) },
2700   { X86_64_TABLE (X86_64_62) },
2701   { X86_64_TABLE (X86_64_63) },
2702   { Bad_Opcode },       /* seg fs */
2703   { Bad_Opcode },       /* seg gs */
2704   { Bad_Opcode },       /* op size prefix */
2705   { Bad_Opcode },       /* adr size prefix */
2706   /* 68 */
2707   { "pushT",            { sIv }, 0 },
2708   { "imulS",            { Gv, Ev, Iv }, 0 },
2709   { "pushT",            { sIbT }, 0 },
2710   { "imulS",            { Gv, Ev, sIb }, 0 },
2711   { "ins{b|}",          { Ybr, indirDX }, 0 },
2712   { X86_64_TABLE (X86_64_6D) },
2713   { "outs{b|}",         { indirDXr, Xb }, 0 },
2714   { X86_64_TABLE (X86_64_6F) },
2715   /* 70 */
2716   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2717   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2718   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2719   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2720   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2721   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2722   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2723   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2724   /* 78 */
2725   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2726   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2727   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2728   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2729   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2730   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2731   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2732   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2733   /* 80 */
2734   { REG_TABLE (REG_80) },
2735   { REG_TABLE (REG_81) },
2736   { X86_64_TABLE (X86_64_82) },
2737   { REG_TABLE (REG_83) },
2738   { "testB",            { Eb, Gb }, 0 },
2739   { "testS",            { Ev, Gv }, 0 },
2740   { "xchgB",            { Ebh2, Gb }, 0 },
2741   { "xchgS",            { Evh2, Gv }, 0 },
2742   /* 88 */
2743   { "movB",             { Ebh3, Gb }, 0 },
2744   { "movS",             { Evh3, Gv }, 0 },
2745   { "movB",             { Gb, EbS }, 0 },
2746   { "movS",             { Gv, EvS }, 0 },
2747   { "movD",             { Sv, Sw }, 0 },
2748   { MOD_TABLE (MOD_8D) },
2749   { "movD",             { Sw, Sv }, 0 },
2750   { REG_TABLE (REG_8F) },
2751   /* 90 */
2752   { PREFIX_TABLE (PREFIX_90) },
2753   { "xchgS",            { RMeCX, eAX }, 0 },
2754   { "xchgS",            { RMeDX, eAX }, 0 },
2755   { "xchgS",            { RMeBX, eAX }, 0 },
2756   { "xchgS",            { RMeSP, eAX }, 0 },
2757   { "xchgS",            { RMeBP, eAX }, 0 },
2758   { "xchgS",            { RMeSI, eAX }, 0 },
2759   { "xchgS",            { RMeDI, eAX }, 0 },
2760   /* 98 */
2761   { "cW{t|}R",          { XX }, 0 },
2762   { "cR{t|}O",          { XX }, 0 },
2763   { X86_64_TABLE (X86_64_9A) },
2764   { Bad_Opcode },       /* fwait */
2765   { "pushfT",           { XX }, 0 },
2766   { "popfT",            { XX }, 0 },
2767   { "sahf",             { XX }, 0 },
2768   { "lahf",             { XX }, 0 },
2769   /* a0 */
2770   { "mov%LB",           { AL, Ob }, 0 },
2771   { "mov%LS",           { eAX, Ov }, 0 },
2772   { "mov%LB",           { Ob, AL }, 0 },
2773   { "mov%LS",           { Ov, eAX }, 0 },
2774   { "movs{b|}",         { Ybr, Xb }, 0 },
2775   { "movs{R|}",         { Yvr, Xv }, 0 },
2776   { "cmps{b|}",         { Xb, Yb }, 0 },
2777   { "cmps{R|}",         { Xv, Yv }, 0 },
2778   /* a8 */
2779   { "testB",            { AL, Ib }, 0 },
2780   { "testS",            { eAX, Iv }, 0 },
2781   { "stosB",            { Ybr, AL }, 0 },
2782   { "stosS",            { Yvr, eAX }, 0 },
2783   { "lodsB",            { ALr, Xb }, 0 },
2784   { "lodsS",            { eAXr, Xv }, 0 },
2785   { "scasB",            { AL, Yb }, 0 },
2786   { "scasS",            { eAX, Yv }, 0 },
2787   /* b0 */
2788   { "movB",             { RMAL, Ib }, 0 },
2789   { "movB",             { RMCL, Ib }, 0 },
2790   { "movB",             { RMDL, Ib }, 0 },
2791   { "movB",             { RMBL, Ib }, 0 },
2792   { "movB",             { RMAH, Ib }, 0 },
2793   { "movB",             { RMCH, Ib }, 0 },
2794   { "movB",             { RMDH, Ib }, 0 },
2795   { "movB",             { RMBH, Ib }, 0 },
2796   /* b8 */
2797   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2798   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2799   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2800   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2801   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2802   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2803   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2804   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2805   /* c0 */
2806   { REG_TABLE (REG_C0) },
2807   { REG_TABLE (REG_C1) },
2808   { "retT",             { Iw, BND }, 0 },
2809   { "retT",             { BND }, 0 },
2810   { X86_64_TABLE (X86_64_C4) },
2811   { X86_64_TABLE (X86_64_C5) },
2812   { REG_TABLE (REG_C6) },
2813   { REG_TABLE (REG_C7) },
2814   /* c8 */
2815   { "enterT",           { Iw, Ib }, 0 },
2816   { "leaveT",           { XX }, 0 },
2817   { "Jret{|f}P",        { Iw }, 0 },
2818   { "Jret{|f}P",        { XX }, 0 },
2819   { "int3",             { XX }, 0 },
2820   { "int",              { Ib }, 0 },
2821   { X86_64_TABLE (X86_64_CE) },
2822   { "iret%LP",          { XX }, 0 },
2823   /* d0 */
2824   { REG_TABLE (REG_D0) },
2825   { REG_TABLE (REG_D1) },
2826   { REG_TABLE (REG_D2) },
2827   { REG_TABLE (REG_D3) },
2828   { X86_64_TABLE (X86_64_D4) },
2829   { X86_64_TABLE (X86_64_D5) },
2830   { Bad_Opcode },
2831   { "xlat",             { DSBX }, 0 },
2832   /* d8 */
2833   { FLOAT },
2834   { FLOAT },
2835   { FLOAT },
2836   { FLOAT },
2837   { FLOAT },
2838   { FLOAT },
2839   { FLOAT },
2840   { FLOAT },
2841   /* e0 */
2842   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2843   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2844   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2845   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2846   { "inB",              { AL, Ib }, 0 },
2847   { "inG",              { zAX, Ib }, 0 },
2848   { "outB",             { Ib, AL }, 0 },
2849   { "outG",             { Ib, zAX }, 0 },
2850   /* e8 */
2851   { X86_64_TABLE (X86_64_E8) },
2852   { X86_64_TABLE (X86_64_E9) },
2853   { X86_64_TABLE (X86_64_EA) },
2854   { "jmp",              { Jb, BND }, 0 },
2855   { "inB",              { AL, indirDX }, 0 },
2856   { "inG",              { zAX, indirDX }, 0 },
2857   { "outB",             { indirDX, AL }, 0 },
2858   { "outG",             { indirDX, zAX }, 0 },
2859   /* f0 */
2860   { Bad_Opcode },       /* lock prefix */
2861   { "icebp",            { XX }, 0 },
2862   { Bad_Opcode },       /* repne */
2863   { Bad_Opcode },       /* repz */
2864   { "hlt",              { XX }, 0 },
2865   { "cmc",              { XX }, 0 },
2866   { REG_TABLE (REG_F6) },
2867   { REG_TABLE (REG_F7) },
2868   /* f8 */
2869   { "clc",              { XX }, 0 },
2870   { "stc",              { XX }, 0 },
2871   { "cli",              { XX }, 0 },
2872   { "sti",              { XX }, 0 },
2873   { "cld",              { XX }, 0 },
2874   { "std",              { XX }, 0 },
2875   { REG_TABLE (REG_FE) },
2876   { REG_TABLE (REG_FF) },
2877 };
2878
2879 static const struct dis386 dis386_twobyte[] = {
2880   /* 00 */
2881   { REG_TABLE (REG_0F00 ) },
2882   { REG_TABLE (REG_0F01 ) },
2883   { "larS",             { Gv, Ew }, 0 },
2884   { "lslS",             { Gv, Ew }, 0 },
2885   { Bad_Opcode },
2886   { "syscall",          { XX }, 0 },
2887   { "clts",             { XX }, 0 },
2888   { "sysret%LP",                { XX }, 0 },
2889   /* 08 */
2890   { "invd",             { XX }, 0 },
2891   { PREFIX_TABLE (PREFIX_0F09) },
2892   { Bad_Opcode },
2893   { "ud2",              { XX }, 0 },
2894   { Bad_Opcode },
2895   { REG_TABLE (REG_0F0D) },
2896   { "femms",            { XX }, 0 },
2897   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2898   /* 10 */
2899   { PREFIX_TABLE (PREFIX_0F10) },
2900   { PREFIX_TABLE (PREFIX_0F11) },
2901   { PREFIX_TABLE (PREFIX_0F12) },
2902   { MOD_TABLE (MOD_0F13) },
2903   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2904   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2905   { PREFIX_TABLE (PREFIX_0F16) },
2906   { MOD_TABLE (MOD_0F17) },
2907   /* 18 */
2908   { REG_TABLE (REG_0F18) },
2909   { "nopQ",             { Ev }, 0 },
2910   { PREFIX_TABLE (PREFIX_0F1A) },
2911   { PREFIX_TABLE (PREFIX_0F1B) },
2912   { PREFIX_TABLE (PREFIX_0F1C) },
2913   { "nopQ",             { Ev }, 0 },
2914   { PREFIX_TABLE (PREFIX_0F1E) },
2915   { "nopQ",             { Ev }, 0 },
2916   /* 20 */
2917   { "movZ",             { Rm, Cm }, 0 },
2918   { "movZ",             { Rm, Dm }, 0 },
2919   { "movZ",             { Cm, Rm }, 0 },
2920   { "movZ",             { Dm, Rm }, 0 },
2921   { MOD_TABLE (MOD_0F24) },
2922   { Bad_Opcode },
2923   { MOD_TABLE (MOD_0F26) },
2924   { Bad_Opcode },
2925   /* 28 */
2926   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2927   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2928   { PREFIX_TABLE (PREFIX_0F2A) },
2929   { PREFIX_TABLE (PREFIX_0F2B) },
2930   { PREFIX_TABLE (PREFIX_0F2C) },
2931   { PREFIX_TABLE (PREFIX_0F2D) },
2932   { PREFIX_TABLE (PREFIX_0F2E) },
2933   { PREFIX_TABLE (PREFIX_0F2F) },
2934   /* 30 */
2935   { "wrmsr",            { XX }, 0 },
2936   { "rdtsc",            { XX }, 0 },
2937   { "rdmsr",            { XX }, 0 },
2938   { "rdpmc",            { XX }, 0 },
2939   { "sysenter",         { XX }, 0 },
2940   { "sysexit",          { XX }, 0 },
2941   { Bad_Opcode },
2942   { "getsec",           { XX }, 0 },
2943   /* 38 */
2944   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2945   { Bad_Opcode },
2946   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2947   { Bad_Opcode },
2948   { Bad_Opcode },
2949   { Bad_Opcode },
2950   { Bad_Opcode },
2951   { Bad_Opcode },
2952   /* 40 */
2953   { "cmovoS",           { Gv, Ev }, 0 },
2954   { "cmovnoS",          { Gv, Ev }, 0 },
2955   { "cmovbS",           { Gv, Ev }, 0 },
2956   { "cmovaeS",          { Gv, Ev }, 0 },
2957   { "cmoveS",           { Gv, Ev }, 0 },
2958   { "cmovneS",          { Gv, Ev }, 0 },
2959   { "cmovbeS",          { Gv, Ev }, 0 },
2960   { "cmovaS",           { Gv, Ev }, 0 },
2961   /* 48 */
2962   { "cmovsS",           { Gv, Ev }, 0 },
2963   { "cmovnsS",          { Gv, Ev }, 0 },
2964   { "cmovpS",           { Gv, Ev }, 0 },
2965   { "cmovnpS",          { Gv, Ev }, 0 },
2966   { "cmovlS",           { Gv, Ev }, 0 },
2967   { "cmovgeS",          { Gv, Ev }, 0 },
2968   { "cmovleS",          { Gv, Ev }, 0 },
2969   { "cmovgS",           { Gv, Ev }, 0 },
2970   /* 50 */
2971   { MOD_TABLE (MOD_0F51) },
2972   { PREFIX_TABLE (PREFIX_0F51) },
2973   { PREFIX_TABLE (PREFIX_0F52) },
2974   { PREFIX_TABLE (PREFIX_0F53) },
2975   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2976   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2977   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2978   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2979   /* 58 */
2980   { PREFIX_TABLE (PREFIX_0F58) },
2981   { PREFIX_TABLE (PREFIX_0F59) },
2982   { PREFIX_TABLE (PREFIX_0F5A) },
2983   { PREFIX_TABLE (PREFIX_0F5B) },
2984   { PREFIX_TABLE (PREFIX_0F5C) },
2985   { PREFIX_TABLE (PREFIX_0F5D) },
2986   { PREFIX_TABLE (PREFIX_0F5E) },
2987   { PREFIX_TABLE (PREFIX_0F5F) },
2988   /* 60 */
2989   { PREFIX_TABLE (PREFIX_0F60) },
2990   { PREFIX_TABLE (PREFIX_0F61) },
2991   { PREFIX_TABLE (PREFIX_0F62) },
2992   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2993   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2994   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2995   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2996   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2997   /* 68 */
2998   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2999   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
3000   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
3001   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
3002   { PREFIX_TABLE (PREFIX_0F6C) },
3003   { PREFIX_TABLE (PREFIX_0F6D) },
3004   { "movK",             { MX, Edq }, PREFIX_OPCODE },
3005   { PREFIX_TABLE (PREFIX_0F6F) },
3006   /* 70 */
3007   { PREFIX_TABLE (PREFIX_0F70) },
3008   { REG_TABLE (REG_0F71) },
3009   { REG_TABLE (REG_0F72) },
3010   { REG_TABLE (REG_0F73) },
3011   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
3012   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
3013   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
3014   { "emms",             { XX }, PREFIX_OPCODE },
3015   /* 78 */
3016   { PREFIX_TABLE (PREFIX_0F78) },
3017   { PREFIX_TABLE (PREFIX_0F79) },
3018   { Bad_Opcode },
3019   { Bad_Opcode },
3020   { PREFIX_TABLE (PREFIX_0F7C) },
3021   { PREFIX_TABLE (PREFIX_0F7D) },
3022   { PREFIX_TABLE (PREFIX_0F7E) },
3023   { PREFIX_TABLE (PREFIX_0F7F) },
3024   /* 80 */
3025   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
3026   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
3027   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
3028   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
3029   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
3030   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
3031   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
3032   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
3033   /* 88 */
3034   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
3035   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
3036   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
3037   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
3038   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
3039   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
3040   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
3041   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
3042   /* 90 */
3043   { "seto",             { Eb }, 0 },
3044   { "setno",            { Eb }, 0 },
3045   { "setb",             { Eb }, 0 },
3046   { "setae",            { Eb }, 0 },
3047   { "sete",             { Eb }, 0 },
3048   { "setne",            { Eb }, 0 },
3049   { "setbe",            { Eb }, 0 },
3050   { "seta",             { Eb }, 0 },
3051   /* 98 */
3052   { "sets",             { Eb }, 0 },
3053   { "setns",            { Eb }, 0 },
3054   { "setp",             { Eb }, 0 },
3055   { "setnp",            { Eb }, 0 },
3056   { "setl",             { Eb }, 0 },
3057   { "setge",            { Eb }, 0 },
3058   { "setle",            { Eb }, 0 },
3059   { "setg",             { Eb }, 0 },
3060   /* a0 */
3061   { "pushT",            { fs }, 0 },
3062   { "popT",             { fs }, 0 },
3063   { "cpuid",            { XX }, 0 },
3064   { "btS",              { Ev, Gv }, 0 },
3065   { "shldS",            { Ev, Gv, Ib }, 0 },
3066   { "shldS",            { Ev, Gv, CL }, 0 },
3067   { REG_TABLE (REG_0FA6) },
3068   { REG_TABLE (REG_0FA7) },
3069   /* a8 */
3070   { "pushT",            { gs }, 0 },
3071   { "popT",             { gs }, 0 },
3072   { "rsm",              { XX }, 0 },
3073   { "btsS",             { Evh1, Gv }, 0 },
3074   { "shrdS",            { Ev, Gv, Ib }, 0 },
3075   { "shrdS",            { Ev, Gv, CL }, 0 },
3076   { REG_TABLE (REG_0FAE) },
3077   { "imulS",            { Gv, Ev }, 0 },
3078   /* b0 */
3079   { "cmpxchgB",         { Ebh1, Gb }, 0 },
3080   { "cmpxchgS",         { Evh1, Gv }, 0 },
3081   { MOD_TABLE (MOD_0FB2) },
3082   { "btrS",             { Evh1, Gv }, 0 },
3083   { MOD_TABLE (MOD_0FB4) },
3084   { MOD_TABLE (MOD_0FB5) },
3085   { "movz{bR|x}",       { Gv, Eb }, 0 },
3086   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3087   /* b8 */
3088   { PREFIX_TABLE (PREFIX_0FB8) },
3089   { "ud1S",             { Gv, Ev }, 0 },
3090   { REG_TABLE (REG_0FBA) },
3091   { "btcS",             { Evh1, Gv }, 0 },
3092   { PREFIX_TABLE (PREFIX_0FBC) },
3093   { PREFIX_TABLE (PREFIX_0FBD) },
3094   { "movs{bR|x}",       { Gv, Eb }, 0 },
3095   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3096   /* c0 */
3097   { "xaddB",            { Ebh1, Gb }, 0 },
3098   { "xaddS",            { Evh1, Gv }, 0 },
3099   { PREFIX_TABLE (PREFIX_0FC2) },
3100   { MOD_TABLE (MOD_0FC3) },
3101   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
3102   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
3103   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
3104   { REG_TABLE (REG_0FC7) },
3105   /* c8 */
3106   { "bswap",            { RMeAX }, 0 },
3107   { "bswap",            { RMeCX }, 0 },
3108   { "bswap",            { RMeDX }, 0 },
3109   { "bswap",            { RMeBX }, 0 },
3110   { "bswap",            { RMeSP }, 0 },
3111   { "bswap",            { RMeBP }, 0 },
3112   { "bswap",            { RMeSI }, 0 },
3113   { "bswap",            { RMeDI }, 0 },
3114   /* d0 */
3115   { PREFIX_TABLE (PREFIX_0FD0) },
3116   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
3117   { "psrld",            { MX, EM }, PREFIX_OPCODE },
3118   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
3119   { "paddq",            { MX, EM }, PREFIX_OPCODE },
3120   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
3121   { PREFIX_TABLE (PREFIX_0FD6) },
3122   { MOD_TABLE (MOD_0FD7) },
3123   /* d8 */
3124   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
3125   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
3126   { "pminub",           { MX, EM }, PREFIX_OPCODE },
3127   { "pand",             { MX, EM }, PREFIX_OPCODE },
3128   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
3129   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
3130   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
3131   { "pandn",            { MX, EM }, PREFIX_OPCODE },
3132   /* e0 */
3133   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
3134   { "psraw",            { MX, EM }, PREFIX_OPCODE },
3135   { "psrad",            { MX, EM }, PREFIX_OPCODE },
3136   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
3137   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
3138   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
3139   { PREFIX_TABLE (PREFIX_0FE6) },
3140   { PREFIX_TABLE (PREFIX_0FE7) },
3141   /* e8 */
3142   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
3143   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
3144   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
3145   { "por",              { MX, EM }, PREFIX_OPCODE },
3146   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
3147   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
3148   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
3149   { "pxor",             { MX, EM }, PREFIX_OPCODE },
3150   /* f0 */
3151   { PREFIX_TABLE (PREFIX_0FF0) },
3152   { "psllw",            { MX, EM }, PREFIX_OPCODE },
3153   { "pslld",            { MX, EM }, PREFIX_OPCODE },
3154   { "psllq",            { MX, EM }, PREFIX_OPCODE },
3155   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
3156   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
3157   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
3158   { PREFIX_TABLE (PREFIX_0FF7) },
3159   /* f8 */
3160   { "psubb",            { MX, EM }, PREFIX_OPCODE },
3161   { "psubw",            { MX, EM }, PREFIX_OPCODE },
3162   { "psubd",            { MX, EM }, PREFIX_OPCODE },
3163   { "psubq",            { MX, EM }, PREFIX_OPCODE },
3164   { "paddb",            { MX, EM }, PREFIX_OPCODE },
3165   { "paddw",            { MX, EM }, PREFIX_OPCODE },
3166   { "paddd",            { MX, EM }, PREFIX_OPCODE },
3167   { "ud0S",             { Gv, Ev }, 0 },
3168 };
3169
3170 static const unsigned char onebyte_has_modrm[256] = {
3171   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3172   /*       -------------------------------        */
3173   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3174   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3175   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3176   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3177   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3178   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3179   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3180   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3181   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3182   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3183   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3184   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3185   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3186   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3187   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3188   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3189   /*       -------------------------------        */
3190   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3191 };
3192
3193 static const unsigned char twobyte_has_modrm[256] = {
3194   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3195   /*       -------------------------------        */
3196   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3197   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3198   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3199   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3200   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3201   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3202   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3203   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3204   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3205   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3206   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3207   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3208   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3209   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3210   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3211   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
3212   /*       -------------------------------        */
3213   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3214 };
3215
3216 static char obuf[100];
3217 static char *obufp;
3218 static char *mnemonicendp;
3219 static char scratchbuf[100];
3220 static unsigned char *start_codep;
3221 static unsigned char *insn_codep;
3222 static unsigned char *codep;
3223 static unsigned char *end_codep;
3224 static int last_lock_prefix;
3225 static int last_repz_prefix;
3226 static int last_repnz_prefix;
3227 static int last_data_prefix;
3228 static int last_addr_prefix;
3229 static int last_rex_prefix;
3230 static int last_seg_prefix;
3231 static int fwait_prefix;
3232 /* The active segment register prefix.  */
3233 static int active_seg_prefix;
3234 #define MAX_CODE_LENGTH 15
3235 /* We can up to 14 prefixes since the maximum instruction length is
3236    15bytes.  */
3237 static int all_prefixes[MAX_CODE_LENGTH - 1];
3238 static disassemble_info *the_info;
3239 static struct
3240   {
3241     int mod;
3242     int reg;
3243     int rm;
3244   }
3245 modrm;
3246 static unsigned char need_modrm;
3247 static struct
3248   {
3249     int scale;
3250     int index;
3251     int base;
3252   }
3253 sib;
3254 static struct
3255   {
3256     int register_specifier;
3257     int length;
3258     int prefix;
3259     int w;
3260     int evex;
3261     int r;
3262     int v;
3263     int mask_register_specifier;
3264     int zeroing;
3265     int ll;
3266     int b;
3267   }
3268 vex;
3269 static unsigned char need_vex;
3270 static unsigned char need_vex_reg;
3271 static unsigned char vex_w_done;
3272
3273 struct op
3274   {
3275     const char *name;
3276     unsigned int len;
3277   };
3278
3279 /* If we are accessing mod/rm/reg without need_modrm set, then the
3280    values are stale.  Hitting this abort likely indicates that you
3281    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3282 #define MODRM_CHECK  if (!need_modrm) abort ()
3283
3284 static const char **names64;
3285 static const char **names32;
3286 static const char **names16;
3287 static const char **names8;
3288 static const char **names8rex;
3289 static const char **names_seg;
3290 static const char *index64;
3291 static const char *index32;
3292 static const char **index16;
3293 static const char **names_bnd;
3294
3295 static const char *intel_names64[] = {
3296   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3297   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3298 };
3299 static const char *intel_names32[] = {
3300   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3301   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3302 };
3303 static const char *intel_names16[] = {
3304   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3305   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3306 };
3307 static const char *intel_names8[] = {
3308   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3309 };
3310 static const char *intel_names8rex[] = {
3311   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3312   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3313 };
3314 static const char *intel_names_seg[] = {
3315   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3316 };
3317 static const char *intel_index64 = "riz";
3318 static const char *intel_index32 = "eiz";
3319 static const char *intel_index16[] = {
3320   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3321 };
3322
3323 static const char *att_names64[] = {
3324   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3325   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3326 };
3327 static const char *att_names32[] = {
3328   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3329   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3330 };
3331 static const char *att_names16[] = {
3332   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3333   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3334 };
3335 static const char *att_names8[] = {
3336   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3337 };
3338 static const char *att_names8rex[] = {
3339   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3340   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3341 };
3342 static const char *att_names_seg[] = {
3343   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3344 };
3345 static const char *att_index64 = "%riz";
3346 static const char *att_index32 = "%eiz";
3347 static const char *att_index16[] = {
3348   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3349 };
3350
3351 static const char **names_mm;
3352 static const char *intel_names_mm[] = {
3353   "mm0", "mm1", "mm2", "mm3",
3354   "mm4", "mm5", "mm6", "mm7"
3355 };
3356 static const char *att_names_mm[] = {
3357   "%mm0", "%mm1", "%mm2", "%mm3",
3358   "%mm4", "%mm5", "%mm6", "%mm7"
3359 };
3360
3361 static const char *intel_names_bnd[] = {
3362   "bnd0", "bnd1", "bnd2", "bnd3"
3363 };
3364
3365 static const char *att_names_bnd[] = {
3366   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3367 };
3368
3369 static const char **names_xmm;
3370 static const char *intel_names_xmm[] = {
3371   "xmm0", "xmm1", "xmm2", "xmm3",
3372   "xmm4", "xmm5", "xmm6", "xmm7",
3373   "xmm8", "xmm9", "xmm10", "xmm11",
3374   "xmm12", "xmm13", "xmm14", "xmm15",
3375   "xmm16", "xmm17", "xmm18", "xmm19",
3376   "xmm20", "xmm21", "xmm22", "xmm23",
3377   "xmm24", "xmm25", "xmm26", "xmm27",
3378   "xmm28", "xmm29", "xmm30", "xmm31"
3379 };
3380 static const char *att_names_xmm[] = {
3381   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3382   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3383   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3384   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3385   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3386   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3387   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3388   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3389 };
3390
3391 static const char **names_ymm;
3392 static const char *intel_names_ymm[] = {
3393   "ymm0", "ymm1", "ymm2", "ymm3",
3394   "ymm4", "ymm5", "ymm6", "ymm7",
3395   "ymm8", "ymm9", "ymm10", "ymm11",
3396   "ymm12", "ymm13", "ymm14", "ymm15",
3397   "ymm16", "ymm17", "ymm18", "ymm19",
3398   "ymm20", "ymm21", "ymm22", "ymm23",
3399   "ymm24", "ymm25", "ymm26", "ymm27",
3400   "ymm28", "ymm29", "ymm30", "ymm31"
3401 };
3402 static const char *att_names_ymm[] = {
3403   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3404   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3405   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3406   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3407   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3408   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3409   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3410   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3411 };
3412
3413 static const char **names_zmm;
3414 static const char *intel_names_zmm[] = {
3415   "zmm0", "zmm1", "zmm2", "zmm3",
3416   "zmm4", "zmm5", "zmm6", "zmm7",
3417   "zmm8", "zmm9", "zmm10", "zmm11",
3418   "zmm12", "zmm13", "zmm14", "zmm15",
3419   "zmm16", "zmm17", "zmm18", "zmm19",
3420   "zmm20", "zmm21", "zmm22", "zmm23",
3421   "zmm24", "zmm25", "zmm26", "zmm27",
3422   "zmm28", "zmm29", "zmm30", "zmm31"
3423 };
3424 static const char *att_names_zmm[] = {
3425   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3426   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3427   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3428   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3429   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3430   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3431   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3432   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3433 };
3434
3435 static const char **names_mask;
3436 static const char *intel_names_mask[] = {
3437   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3438 };
3439 static const char *att_names_mask[] = {
3440   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3441 };
3442
3443 static const char *names_rounding[] =
3444 {
3445   "{rn-sae}",
3446   "{rd-sae}",
3447   "{ru-sae}",
3448   "{rz-sae}"
3449 };
3450
3451 static const struct dis386 reg_table[][8] = {
3452   /* REG_80 */
3453   {
3454     { "addA",   { Ebh1, Ib }, 0 },
3455     { "orA",    { Ebh1, Ib }, 0 },
3456     { "adcA",   { Ebh1, Ib }, 0 },
3457     { "sbbA",   { Ebh1, Ib }, 0 },
3458     { "andA",   { Ebh1, Ib }, 0 },
3459     { "subA",   { Ebh1, Ib }, 0 },
3460     { "xorA",   { Ebh1, Ib }, 0 },
3461     { "cmpA",   { Eb, Ib }, 0 },
3462   },
3463   /* REG_81 */
3464   {
3465     { "addQ",   { Evh1, Iv }, 0 },
3466     { "orQ",    { Evh1, Iv }, 0 },
3467     { "adcQ",   { Evh1, Iv }, 0 },
3468     { "sbbQ",   { Evh1, Iv }, 0 },
3469     { "andQ",   { Evh1, Iv }, 0 },
3470     { "subQ",   { Evh1, Iv }, 0 },
3471     { "xorQ",   { Evh1, Iv }, 0 },
3472     { "cmpQ",   { Ev, Iv }, 0 },
3473   },
3474   /* REG_83 */
3475   {
3476     { "addQ",   { Evh1, sIb }, 0 },
3477     { "orQ",    { Evh1, sIb }, 0 },
3478     { "adcQ",   { Evh1, sIb }, 0 },
3479     { "sbbQ",   { Evh1, sIb }, 0 },
3480     { "andQ",   { Evh1, sIb }, 0 },
3481     { "subQ",   { Evh1, sIb }, 0 },
3482     { "xorQ",   { Evh1, sIb }, 0 },
3483     { "cmpQ",   { Ev, sIb }, 0 },
3484   },
3485   /* REG_8F */
3486   {
3487     { "popU",   { stackEv }, 0 },
3488     { XOP_8F_TABLE (XOP_09) },
3489     { Bad_Opcode },
3490     { Bad_Opcode },
3491     { Bad_Opcode },
3492     { XOP_8F_TABLE (XOP_09) },
3493   },
3494   /* REG_C0 */
3495   {
3496     { "rolA",   { Eb, Ib }, 0 },
3497     { "rorA",   { Eb, Ib }, 0 },
3498     { "rclA",   { Eb, Ib }, 0 },
3499     { "rcrA",   { Eb, Ib }, 0 },
3500     { "shlA",   { Eb, Ib }, 0 },
3501     { "shrA",   { Eb, Ib }, 0 },
3502     { "shlA",   { Eb, Ib }, 0 },
3503     { "sarA",   { Eb, Ib }, 0 },
3504   },
3505   /* REG_C1 */
3506   {
3507     { "rolQ",   { Ev, Ib }, 0 },
3508     { "rorQ",   { Ev, Ib }, 0 },
3509     { "rclQ",   { Ev, Ib }, 0 },
3510     { "rcrQ",   { Ev, Ib }, 0 },
3511     { "shlQ",   { Ev, Ib }, 0 },
3512     { "shrQ",   { Ev, Ib }, 0 },
3513     { "shlQ",   { Ev, Ib }, 0 },
3514     { "sarQ",   { Ev, Ib }, 0 },
3515   },
3516   /* REG_C6 */
3517   {
3518     { "movA",   { Ebh3, Ib }, 0 },
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { Bad_Opcode },
3524     { Bad_Opcode },
3525     { MOD_TABLE (MOD_C6_REG_7) },
3526   },
3527   /* REG_C7 */
3528   {
3529     { "movQ",   { Evh3, Iv }, 0 },
3530     { Bad_Opcode },
3531     { Bad_Opcode },
3532     { Bad_Opcode },
3533     { Bad_Opcode },
3534     { Bad_Opcode },
3535     { Bad_Opcode },
3536     { MOD_TABLE (MOD_C7_REG_7) },
3537   },
3538   /* REG_D0 */
3539   {
3540     { "rolA",   { Eb, I1 }, 0 },
3541     { "rorA",   { Eb, I1 }, 0 },
3542     { "rclA",   { Eb, I1 }, 0 },
3543     { "rcrA",   { Eb, I1 }, 0 },
3544     { "shlA",   { Eb, I1 }, 0 },
3545     { "shrA",   { Eb, I1 }, 0 },
3546     { "shlA",   { Eb, I1 }, 0 },
3547     { "sarA",   { Eb, I1 }, 0 },
3548   },
3549   /* REG_D1 */
3550   {
3551     { "rolQ",   { Ev, I1 }, 0 },
3552     { "rorQ",   { Ev, I1 }, 0 },
3553     { "rclQ",   { Ev, I1 }, 0 },
3554     { "rcrQ",   { Ev, I1 }, 0 },
3555     { "shlQ",   { Ev, I1 }, 0 },
3556     { "shrQ",   { Ev, I1 }, 0 },
3557     { "shlQ",   { Ev, I1 }, 0 },
3558     { "sarQ",   { Ev, I1 }, 0 },
3559   },
3560   /* REG_D2 */
3561   {
3562     { "rolA",   { Eb, CL }, 0 },
3563     { "rorA",   { Eb, CL }, 0 },
3564     { "rclA",   { Eb, CL }, 0 },
3565     { "rcrA",   { Eb, CL }, 0 },
3566     { "shlA",   { Eb, CL }, 0 },
3567     { "shrA",   { Eb, CL }, 0 },
3568     { "shlA",   { Eb, CL }, 0 },
3569     { "sarA",   { Eb, CL }, 0 },
3570   },
3571   /* REG_D3 */
3572   {
3573     { "rolQ",   { Ev, CL }, 0 },
3574     { "rorQ",   { Ev, CL }, 0 },
3575     { "rclQ",   { Ev, CL }, 0 },
3576     { "rcrQ",   { Ev, CL }, 0 },
3577     { "shlQ",   { Ev, CL }, 0 },
3578     { "shrQ",   { Ev, CL }, 0 },
3579     { "shlQ",   { Ev, CL }, 0 },
3580     { "sarQ",   { Ev, CL }, 0 },
3581   },
3582   /* REG_F6 */
3583   {
3584     { "testA",  { Eb, Ib }, 0 },
3585     { "testA",  { Eb, Ib }, 0 },
3586     { "notA",   { Ebh1 }, 0 },
3587     { "negA",   { Ebh1 }, 0 },
3588     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3589     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3590     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3591     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3592   },
3593   /* REG_F7 */
3594   {
3595     { "testQ",  { Ev, Iv }, 0 },
3596     { "testQ",  { Ev, Iv }, 0 },
3597     { "notQ",   { Evh1 }, 0 },
3598     { "negQ",   { Evh1 }, 0 },
3599     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3600     { "imulQ",  { Ev }, 0 },
3601     { "divQ",   { Ev }, 0 },
3602     { "idivQ",  { Ev }, 0 },
3603   },
3604   /* REG_FE */
3605   {
3606     { "incA",   { Ebh1 }, 0 },
3607     { "decA",   { Ebh1 }, 0 },
3608   },
3609   /* REG_FF */
3610   {
3611     { "incQ",   { Evh1 }, 0 },
3612     { "decQ",   { Evh1 }, 0 },
3613     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3614     { MOD_TABLE (MOD_FF_REG_3) },
3615     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3616     { MOD_TABLE (MOD_FF_REG_5) },
3617     { "pushU",  { stackEv }, 0 },
3618     { Bad_Opcode },
3619   },
3620   /* REG_0F00 */
3621   {
3622     { "sldtD",  { Sv }, 0 },
3623     { "strD",   { Sv }, 0 },
3624     { "lldt",   { Ew }, 0 },
3625     { "ltr",    { Ew }, 0 },
3626     { "verr",   { Ew }, 0 },
3627     { "verw",   { Ew }, 0 },
3628     { Bad_Opcode },
3629     { Bad_Opcode },
3630   },
3631   /* REG_0F01 */
3632   {
3633     { MOD_TABLE (MOD_0F01_REG_0) },
3634     { MOD_TABLE (MOD_0F01_REG_1) },
3635     { MOD_TABLE (MOD_0F01_REG_2) },
3636     { MOD_TABLE (MOD_0F01_REG_3) },
3637     { "smswD",  { Sv }, 0 },
3638     { MOD_TABLE (MOD_0F01_REG_5) },
3639     { "lmsw",   { Ew }, 0 },
3640     { MOD_TABLE (MOD_0F01_REG_7) },
3641   },
3642   /* REG_0F0D */
3643   {
3644     { "prefetch",       { Mb }, 0 },
3645     { "prefetchw",      { Mb }, 0 },
3646     { "prefetchwt1",    { Mb }, 0 },
3647     { "prefetch",       { Mb }, 0 },
3648     { "prefetch",       { Mb }, 0 },
3649     { "prefetch",       { Mb }, 0 },
3650     { "prefetch",       { Mb }, 0 },
3651     { "prefetch",       { Mb }, 0 },
3652   },
3653   /* REG_0F18 */
3654   {
3655     { MOD_TABLE (MOD_0F18_REG_0) },
3656     { MOD_TABLE (MOD_0F18_REG_1) },
3657     { MOD_TABLE (MOD_0F18_REG_2) },
3658     { MOD_TABLE (MOD_0F18_REG_3) },
3659     { MOD_TABLE (MOD_0F18_REG_4) },
3660     { MOD_TABLE (MOD_0F18_REG_5) },
3661     { MOD_TABLE (MOD_0F18_REG_6) },
3662     { MOD_TABLE (MOD_0F18_REG_7) },
3663   },
3664   /* REG_0F1C_MOD_0 */
3665   {
3666     { "cldemote",       { Mb }, 0 },
3667     { "nopQ",           { Ev }, 0 },
3668     { "nopQ",           { Ev }, 0 },
3669     { "nopQ",           { Ev }, 0 },
3670     { "nopQ",           { Ev }, 0 },
3671     { "nopQ",           { Ev }, 0 },
3672     { "nopQ",           { Ev }, 0 },
3673     { "nopQ",           { Ev }, 0 },
3674   },
3675   /* REG_0F1E_MOD_3 */
3676   {
3677     { "nopQ",           { Ev }, 0 },
3678     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3679     { "nopQ",           { Ev }, 0 },
3680     { "nopQ",           { Ev }, 0 },
3681     { "nopQ",           { Ev }, 0 },
3682     { "nopQ",           { Ev }, 0 },
3683     { "nopQ",           { Ev }, 0 },
3684     { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3685   },
3686   /* REG_0F71 */
3687   {
3688     { Bad_Opcode },
3689     { Bad_Opcode },
3690     { MOD_TABLE (MOD_0F71_REG_2) },
3691     { Bad_Opcode },
3692     { MOD_TABLE (MOD_0F71_REG_4) },
3693     { Bad_Opcode },
3694     { MOD_TABLE (MOD_0F71_REG_6) },
3695   },
3696   /* REG_0F72 */
3697   {
3698     { Bad_Opcode },
3699     { Bad_Opcode },
3700     { MOD_TABLE (MOD_0F72_REG_2) },
3701     { Bad_Opcode },
3702     { MOD_TABLE (MOD_0F72_REG_4) },
3703     { Bad_Opcode },
3704     { MOD_TABLE (MOD_0F72_REG_6) },
3705   },
3706   /* REG_0F73 */
3707   {
3708     { Bad_Opcode },
3709     { Bad_Opcode },
3710     { MOD_TABLE (MOD_0F73_REG_2) },
3711     { MOD_TABLE (MOD_0F73_REG_3) },
3712     { Bad_Opcode },
3713     { Bad_Opcode },
3714     { MOD_TABLE (MOD_0F73_REG_6) },
3715     { MOD_TABLE (MOD_0F73_REG_7) },
3716   },
3717   /* REG_0FA6 */
3718   {
3719     { "montmul",        { { OP_0f07, 0 } }, 0 },
3720     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3721     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3722   },
3723   /* REG_0FA7 */
3724   {
3725     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3726     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3727     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3728     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3729     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3730     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3731   },
3732   /* REG_0FAE */
3733   {
3734     { MOD_TABLE (MOD_0FAE_REG_0) },
3735     { MOD_TABLE (MOD_0FAE_REG_1) },
3736     { MOD_TABLE (MOD_0FAE_REG_2) },
3737     { MOD_TABLE (MOD_0FAE_REG_3) },
3738     { MOD_TABLE (MOD_0FAE_REG_4) },
3739     { MOD_TABLE (MOD_0FAE_REG_5) },
3740     { MOD_TABLE (MOD_0FAE_REG_6) },
3741     { MOD_TABLE (MOD_0FAE_REG_7) },
3742   },
3743   /* REG_0FBA */
3744   {
3745     { Bad_Opcode },
3746     { Bad_Opcode },
3747     { Bad_Opcode },
3748     { Bad_Opcode },
3749     { "btQ",    { Ev, Ib }, 0 },
3750     { "btsQ",   { Evh1, Ib }, 0 },
3751     { "btrQ",   { Evh1, Ib }, 0 },
3752     { "btcQ",   { Evh1, Ib }, 0 },
3753   },
3754   /* REG_0FC7 */
3755   {
3756     { Bad_Opcode },
3757     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3758     { Bad_Opcode },
3759     { MOD_TABLE (MOD_0FC7_REG_3) },
3760     { MOD_TABLE (MOD_0FC7_REG_4) },
3761     { MOD_TABLE (MOD_0FC7_REG_5) },
3762     { MOD_TABLE (MOD_0FC7_REG_6) },
3763     { MOD_TABLE (MOD_0FC7_REG_7) },
3764   },
3765   /* REG_VEX_0F71 */
3766   {
3767     { Bad_Opcode },
3768     { Bad_Opcode },
3769     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3770     { Bad_Opcode },
3771     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3772     { Bad_Opcode },
3773     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3774   },
3775   /* REG_VEX_0F72 */
3776   {
3777     { Bad_Opcode },
3778     { Bad_Opcode },
3779     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3780     { Bad_Opcode },
3781     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3782     { Bad_Opcode },
3783     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3784   },
3785   /* REG_VEX_0F73 */
3786   {
3787     { Bad_Opcode },
3788     { Bad_Opcode },
3789     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3790     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3791     { Bad_Opcode },
3792     { Bad_Opcode },
3793     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3794     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3795   },
3796   /* REG_VEX_0FAE */
3797   {
3798     { Bad_Opcode },
3799     { Bad_Opcode },
3800     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3801     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3802   },
3803   /* REG_VEX_0F38F3 */
3804   {
3805     { Bad_Opcode },
3806     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3807     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3808     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3809   },
3810   /* REG_XOP_LWPCB */
3811   {
3812     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3813     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3814   },
3815   /* REG_XOP_LWP */
3816   {
3817     { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3818     { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3819   },
3820   /* REG_XOP_TBM_01 */
3821   {
3822     { Bad_Opcode },
3823     { "blcfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3824     { "blsfill",        { { OP_LWP_E, 0 }, Ev }, 0 },
3825     { "blcs",   { { OP_LWP_E, 0 }, Ev }, 0 },
3826     { "tzmsk",  { { OP_LWP_E, 0 }, Ev }, 0 },
3827     { "blcic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3828     { "blsic",  { { OP_LWP_E, 0 }, Ev }, 0 },
3829     { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3830   },
3831   /* REG_XOP_TBM_02 */
3832   {
3833     { Bad_Opcode },
3834     { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3835     { Bad_Opcode },
3836     { Bad_Opcode },
3837     { Bad_Opcode },
3838     { Bad_Opcode },
3839     { "blci",   { { OP_LWP_E, 0 }, Ev }, 0 },
3840   },
3841 #define NEED_REG_TABLE
3842 #include "i386-dis-evex.h"
3843 #undef NEED_REG_TABLE
3844 };
3845
3846 static const struct dis386 prefix_table[][4] = {
3847   /* PREFIX_90 */
3848   {
3849     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3850     { "pause", { XX }, 0 },
3851     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3852     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3853   },
3854
3855   /* PREFIX_MOD_0_0F01_REG_5 */
3856   {
3857     { Bad_Opcode },
3858     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3859   },
3860
3861   /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3862   {
3863     { Bad_Opcode },
3864     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3865   },
3866
3867   /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3868   {
3869     { Bad_Opcode },
3870     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3871   },
3872
3873   /* PREFIX_0F09 */
3874   {
3875     { "wbinvd",   { XX }, 0 },
3876     { "wbnoinvd", { XX }, 0 },
3877   },
3878
3879   /* PREFIX_0F10 */
3880   {
3881     { "movups", { XM, EXx }, PREFIX_OPCODE },
3882     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3883     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3884     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3885   },
3886
3887   /* PREFIX_0F11 */
3888   {
3889     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3890     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3891     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3892     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3893   },
3894
3895   /* PREFIX_0F12 */
3896   {
3897     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3898     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3899     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3900     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3901   },
3902
3903   /* PREFIX_0F16 */
3904   {
3905     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3906     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3907     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3908   },
3909
3910   /* PREFIX_0F1A */
3911   {
3912     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3913     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3914     { "bndmov", { Gbnd, Ebnd }, 0 },
3915     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3916   },
3917
3918   /* PREFIX_0F1B */
3919   {
3920     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3921     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3922     { "bndmov", { EbndS, Gbnd }, 0 },
3923     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3924   },
3925
3926   /* PREFIX_0F1C */
3927   {
3928     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3929     { "nopQ",   { Ev }, PREFIX_OPCODE },
3930     { "nopQ",   { Ev }, PREFIX_OPCODE },
3931     { "nopQ",   { Ev }, PREFIX_OPCODE },
3932   },
3933
3934   /* PREFIX_0F1E */
3935   {
3936     { "nopQ",   { Ev }, PREFIX_OPCODE },
3937     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3938     { "nopQ",   { Ev }, PREFIX_OPCODE },
3939     { "nopQ",   { Ev }, PREFIX_OPCODE },
3940   },
3941
3942   /* PREFIX_0F2A */
3943   {
3944     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3945     { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3946     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3947     { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3948   },
3949
3950   /* PREFIX_0F2B */
3951   {
3952     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3953     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3954     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3955     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3956   },
3957
3958   /* PREFIX_0F2C */
3959   {
3960     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3961     { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3962     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3963     { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3964   },
3965
3966   /* PREFIX_0F2D */
3967   {
3968     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3969     { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3970     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3971     { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3972   },
3973
3974   /* PREFIX_0F2E */
3975   {
3976     { "ucomiss",{ XM, EXd }, 0 },
3977     { Bad_Opcode },
3978     { "ucomisd",{ XM, EXq }, 0 },
3979   },
3980
3981   /* PREFIX_0F2F */
3982   {
3983     { "comiss", { XM, EXd }, 0 },
3984     { Bad_Opcode },
3985     { "comisd", { XM, EXq }, 0 },
3986   },
3987
3988   /* PREFIX_0F51 */
3989   {
3990     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3991     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3992     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3993     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3994   },
3995
3996   /* PREFIX_0F52 */
3997   {
3998     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3999     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4000   },
4001
4002   /* PREFIX_0F53 */
4003   {
4004     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
4005     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0F58 */
4009   {
4010     { "addps", { XM, EXx }, PREFIX_OPCODE },
4011     { "addss", { XM, EXd }, PREFIX_OPCODE },
4012     { "addpd", { XM, EXx }, PREFIX_OPCODE },
4013     { "addsd", { XM, EXq }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0F59 */
4017   {
4018     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
4019     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
4020     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
4021     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
4022   },
4023
4024   /* PREFIX_0F5A */
4025   {
4026     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4027     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4028     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4029     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4030   },
4031
4032   /* PREFIX_0F5B */
4033   {
4034     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4035     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4036     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4037   },
4038
4039   /* PREFIX_0F5C */
4040   {
4041     { "subps",  { XM, EXx }, PREFIX_OPCODE },
4042     { "subss",  { XM, EXd }, PREFIX_OPCODE },
4043     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
4044     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
4045   },
4046
4047   /* PREFIX_0F5D */
4048   {
4049     { "minps",  { XM, EXx }, PREFIX_OPCODE },
4050     { "minss",  { XM, EXd }, PREFIX_OPCODE },
4051     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
4052     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
4053   },
4054
4055   /* PREFIX_0F5E */
4056   {
4057     { "divps",  { XM, EXx }, PREFIX_OPCODE },
4058     { "divss",  { XM, EXd }, PREFIX_OPCODE },
4059     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
4060     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
4061   },
4062
4063   /* PREFIX_0F5F */
4064   {
4065     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
4066     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
4067     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
4068     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
4069   },
4070
4071   /* PREFIX_0F60 */
4072   {
4073     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4074     { Bad_Opcode },
4075     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4076   },
4077
4078   /* PREFIX_0F61 */
4079   {
4080     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4081     { Bad_Opcode },
4082     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4083   },
4084
4085   /* PREFIX_0F62 */
4086   {
4087     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4088     { Bad_Opcode },
4089     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4090   },
4091
4092   /* PREFIX_0F6C */
4093   {
4094     { Bad_Opcode },
4095     { Bad_Opcode },
4096     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4097   },
4098
4099   /* PREFIX_0F6D */
4100   {
4101     { Bad_Opcode },
4102     { Bad_Opcode },
4103     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4104   },
4105
4106   /* PREFIX_0F6F */
4107   {
4108     { "movq",   { MX, EM }, PREFIX_OPCODE },
4109     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4110     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4111   },
4112
4113   /* PREFIX_0F70 */
4114   {
4115     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4116     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4117     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4118     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4119   },
4120
4121   /* PREFIX_0F73_REG_3 */
4122   {
4123     { Bad_Opcode },
4124     { Bad_Opcode },
4125     { "psrldq", { XS, Ib }, 0 },
4126   },
4127
4128   /* PREFIX_0F73_REG_7 */
4129   {
4130     { Bad_Opcode },
4131     { Bad_Opcode },
4132     { "pslldq", { XS, Ib }, 0 },
4133   },
4134
4135   /* PREFIX_0F78 */
4136   {
4137     {"vmread",  { Em, Gm }, 0 },
4138     { Bad_Opcode },
4139     {"extrq",   { XS, Ib, Ib }, 0 },
4140     {"insertq", { XM, XS, Ib, Ib }, 0 },
4141   },
4142
4143   /* PREFIX_0F79 */
4144   {
4145     {"vmwrite", { Gm, Em }, 0 },
4146     { Bad_Opcode },
4147     {"extrq",   { XM, XS }, 0 },
4148     {"insertq", { XM, XS }, 0 },
4149   },
4150
4151   /* PREFIX_0F7C */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4156     { "haddps", { XM, EXx }, PREFIX_OPCODE },
4157   },
4158
4159   /* PREFIX_0F7D */
4160   {
4161     { Bad_Opcode },
4162     { Bad_Opcode },
4163     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4164     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4165   },
4166
4167   /* PREFIX_0F7E */
4168   {
4169     { "movK",   { Edq, MX }, PREFIX_OPCODE },
4170     { "movq",   { XM, EXq }, PREFIX_OPCODE },
4171     { "movK",   { Edq, XM }, PREFIX_OPCODE },
4172   },
4173
4174   /* PREFIX_0F7F */
4175   {
4176     { "movq",   { EMS, MX }, PREFIX_OPCODE },
4177     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4178     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4179   },
4180
4181   /* PREFIX_0FAE_REG_0 */
4182   {
4183     { Bad_Opcode },
4184     { "rdfsbase", { Ev }, 0 },
4185   },
4186
4187   /* PREFIX_0FAE_REG_1 */
4188   {
4189     { Bad_Opcode },
4190     { "rdgsbase", { Ev }, 0 },
4191   },
4192
4193   /* PREFIX_0FAE_REG_2 */
4194   {
4195     { Bad_Opcode },
4196     { "wrfsbase", { Ev }, 0 },
4197   },
4198
4199   /* PREFIX_0FAE_REG_3 */
4200   {
4201     { Bad_Opcode },
4202     { "wrgsbase", { Ev }, 0 },
4203   },
4204
4205   /* PREFIX_MOD_0_0FAE_REG_4 */
4206   {
4207     { "xsave",  { FXSAVE }, 0 },
4208     { "ptwrite%LQ", { Edq }, 0 },
4209   },
4210
4211   /* PREFIX_MOD_3_0FAE_REG_4 */
4212   {
4213     { Bad_Opcode },
4214     { "ptwrite%LQ", { Edq }, 0 },
4215   },
4216
4217   /* PREFIX_MOD_0_0FAE_REG_5 */
4218   {
4219     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
4220   },
4221
4222   /* PREFIX_MOD_3_0FAE_REG_5 */
4223   {
4224     { "lfence",         { Skip_MODRM }, 0 },
4225     { "incsspK",        { Rdq }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_MOD_0_0FAE_REG_6 */
4229   {
4230     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4231     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4232     { "clwb",   { Mb }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_MOD_1_0FAE_REG_6 */
4236   {
4237     { RM_TABLE (RM_0FAE_REG_6) },
4238     { "umonitor",       { Eva }, PREFIX_OPCODE },
4239     { "tpause", { Edq }, PREFIX_OPCODE },
4240     { "umwait", { Edq }, PREFIX_OPCODE },
4241   },
4242
4243   /* PREFIX_0FAE_REG_7 */
4244   {
4245     { "clflush",        { Mb }, 0 },
4246     { Bad_Opcode },
4247     { "clflushopt",     { Mb }, 0 },
4248   },
4249
4250   /* PREFIX_0FB8 */
4251   {
4252     { Bad_Opcode },
4253     { "popcntS", { Gv, Ev }, 0 },
4254   },
4255
4256   /* PREFIX_0FBC */
4257   {
4258     { "bsfS",   { Gv, Ev }, 0 },
4259     { "tzcntS", { Gv, Ev }, 0 },
4260     { "bsfS",   { Gv, Ev }, 0 },
4261   },
4262
4263   /* PREFIX_0FBD */
4264   {
4265     { "bsrS",   { Gv, Ev }, 0 },
4266     { "lzcntS", { Gv, Ev }, 0 },
4267     { "bsrS",   { Gv, Ev }, 0 },
4268   },
4269
4270   /* PREFIX_0FC2 */
4271   {
4272     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4273     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4274     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4275     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4276   },
4277
4278   /* PREFIX_MOD_0_0FC3 */
4279   {
4280     { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4281   },
4282
4283   /* PREFIX_MOD_0_0FC7_REG_6 */
4284   {
4285     { "vmptrld",{ Mq }, 0 },
4286     { "vmxon",  { Mq }, 0 },
4287     { "vmclear",{ Mq }, 0 },
4288   },
4289
4290   /* PREFIX_MOD_3_0FC7_REG_6 */
4291   {
4292     { "rdrand", { Ev }, 0 },
4293     { Bad_Opcode },
4294     { "rdrand", { Ev }, 0 }
4295   },
4296
4297   /* PREFIX_MOD_3_0FC7_REG_7 */
4298   {
4299     { "rdseed", { Ev }, 0 },
4300     { "rdpid",  { Em }, 0 },
4301     { "rdseed", { Ev }, 0 },
4302   },
4303
4304   /* PREFIX_0FD0 */
4305   {
4306     { Bad_Opcode },
4307     { Bad_Opcode },
4308     { "addsubpd", { XM, EXx }, 0 },
4309     { "addsubps", { XM, EXx }, 0 },
4310   },
4311
4312   /* PREFIX_0FD6 */
4313   {
4314     { Bad_Opcode },
4315     { "movq2dq",{ XM, MS }, 0 },
4316     { "movq",   { EXqS, XM }, 0 },
4317     { "movdq2q",{ MX, XS }, 0 },
4318   },
4319
4320   /* PREFIX_0FE6 */
4321   {
4322     { Bad_Opcode },
4323     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4324     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4325     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4326   },
4327
4328   /* PREFIX_0FE7 */
4329   {
4330     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4331     { Bad_Opcode },
4332     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4333   },
4334
4335   /* PREFIX_0FF0 */
4336   {
4337     { Bad_Opcode },
4338     { Bad_Opcode },
4339     { Bad_Opcode },
4340     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4341   },
4342
4343   /* PREFIX_0FF7 */
4344   {
4345     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4346     { Bad_Opcode },
4347     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4348   },
4349
4350   /* PREFIX_0F3810 */
4351   {
4352     { Bad_Opcode },
4353     { Bad_Opcode },
4354     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4355   },
4356
4357   /* PREFIX_0F3814 */
4358   {
4359     { Bad_Opcode },
4360     { Bad_Opcode },
4361     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4362   },
4363
4364   /* PREFIX_0F3815 */
4365   {
4366     { Bad_Opcode },
4367     { Bad_Opcode },
4368     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F3817 */
4372   {
4373     { Bad_Opcode },
4374     { Bad_Opcode },
4375     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4376   },
4377
4378   /* PREFIX_0F3820 */
4379   {
4380     { Bad_Opcode },
4381     { Bad_Opcode },
4382     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4383   },
4384
4385   /* PREFIX_0F3821 */
4386   {
4387     { Bad_Opcode },
4388     { Bad_Opcode },
4389     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4390   },
4391
4392   /* PREFIX_0F3822 */
4393   {
4394     { Bad_Opcode },
4395     { Bad_Opcode },
4396     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4397   },
4398
4399   /* PREFIX_0F3823 */
4400   {
4401     { Bad_Opcode },
4402     { Bad_Opcode },
4403     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4404   },
4405
4406   /* PREFIX_0F3824 */
4407   {
4408     { Bad_Opcode },
4409     { Bad_Opcode },
4410     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4411   },
4412
4413   /* PREFIX_0F3825 */
4414   {
4415     { Bad_Opcode },
4416     { Bad_Opcode },
4417     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4418   },
4419
4420   /* PREFIX_0F3828 */
4421   {
4422     { Bad_Opcode },
4423     { Bad_Opcode },
4424     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4425   },
4426
4427   /* PREFIX_0F3829 */
4428   {
4429     { Bad_Opcode },
4430     { Bad_Opcode },
4431     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4432   },
4433
4434   /* PREFIX_0F382A */
4435   {
4436     { Bad_Opcode },
4437     { Bad_Opcode },
4438     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4439   },
4440
4441   /* PREFIX_0F382B */
4442   {
4443     { Bad_Opcode },
4444     { Bad_Opcode },
4445     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4446   },
4447
4448   /* PREFIX_0F3830 */
4449   {
4450     { Bad_Opcode },
4451     { Bad_Opcode },
4452     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4453   },
4454
4455   /* PREFIX_0F3831 */
4456   {
4457     { Bad_Opcode },
4458     { Bad_Opcode },
4459     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4460   },
4461
4462   /* PREFIX_0F3832 */
4463   {
4464     { Bad_Opcode },
4465     { Bad_Opcode },
4466     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4467   },
4468
4469   /* PREFIX_0F3833 */
4470   {
4471     { Bad_Opcode },
4472     { Bad_Opcode },
4473     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4474   },
4475
4476   /* PREFIX_0F3834 */
4477   {
4478     { Bad_Opcode },
4479     { Bad_Opcode },
4480     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4481   },
4482
4483   /* PREFIX_0F3835 */
4484   {
4485     { Bad_Opcode },
4486     { Bad_Opcode },
4487     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4488   },
4489
4490   /* PREFIX_0F3837 */
4491   {
4492     { Bad_Opcode },
4493     { Bad_Opcode },
4494     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4495   },
4496
4497   /* PREFIX_0F3838 */
4498   {
4499     { Bad_Opcode },
4500     { Bad_Opcode },
4501     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4502   },
4503
4504   /* PREFIX_0F3839 */
4505   {
4506     { Bad_Opcode },
4507     { Bad_Opcode },
4508     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4509   },
4510
4511   /* PREFIX_0F383A */
4512   {
4513     { Bad_Opcode },
4514     { Bad_Opcode },
4515     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4516   },
4517
4518   /* PREFIX_0F383B */
4519   {
4520     { Bad_Opcode },
4521     { Bad_Opcode },
4522     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4523   },
4524
4525   /* PREFIX_0F383C */
4526   {
4527     { Bad_Opcode },
4528     { Bad_Opcode },
4529     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4530   },
4531
4532   /* PREFIX_0F383D */
4533   {
4534     { Bad_Opcode },
4535     { Bad_Opcode },
4536     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4537   },
4538
4539   /* PREFIX_0F383E */
4540   {
4541     { Bad_Opcode },
4542     { Bad_Opcode },
4543     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4544   },
4545
4546   /* PREFIX_0F383F */
4547   {
4548     { Bad_Opcode },
4549     { Bad_Opcode },
4550     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4551   },
4552
4553   /* PREFIX_0F3840 */
4554   {
4555     { Bad_Opcode },
4556     { Bad_Opcode },
4557     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4558   },
4559
4560   /* PREFIX_0F3841 */
4561   {
4562     { Bad_Opcode },
4563     { Bad_Opcode },
4564     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4565   },
4566
4567   /* PREFIX_0F3880 */
4568   {
4569     { Bad_Opcode },
4570     { Bad_Opcode },
4571     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4572   },
4573
4574   /* PREFIX_0F3881 */
4575   {
4576     { Bad_Opcode },
4577     { Bad_Opcode },
4578     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4579   },
4580
4581   /* PREFIX_0F3882 */
4582   {
4583     { Bad_Opcode },
4584     { Bad_Opcode },
4585     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4586   },
4587
4588   /* PREFIX_0F38C8 */
4589   {
4590     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4591   },
4592
4593   /* PREFIX_0F38C9 */
4594   {
4595     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4596   },
4597
4598   /* PREFIX_0F38CA */
4599   {
4600     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F38CB */
4604   {
4605     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4606   },
4607
4608   /* PREFIX_0F38CC */
4609   {
4610     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4611   },
4612
4613   /* PREFIX_0F38CD */
4614   {
4615     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4616   },
4617
4618   /* PREFIX_0F38CF */
4619   {
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4623   },
4624
4625   /* PREFIX_0F38DB */
4626   {
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4630   },
4631
4632   /* PREFIX_0F38DC */
4633   {
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4637   },
4638
4639   /* PREFIX_0F38DD */
4640   {
4641     { Bad_Opcode },
4642     { Bad_Opcode },
4643     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4644   },
4645
4646   /* PREFIX_0F38DE */
4647   {
4648     { Bad_Opcode },
4649     { Bad_Opcode },
4650     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4651   },
4652
4653   /* PREFIX_0F38DF */
4654   {
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4658   },
4659
4660   /* PREFIX_0F38F0 */
4661   {
4662     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4663     { Bad_Opcode },
4664     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4665     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4666   },
4667
4668   /* PREFIX_0F38F1 */
4669   {
4670     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4671     { Bad_Opcode },
4672     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4673     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4674   },
4675
4676   /* PREFIX_0F38F5 */
4677   {
4678     { Bad_Opcode },
4679     { Bad_Opcode },
4680     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4681   },
4682
4683   /* PREFIX_0F38F6 */
4684   {
4685     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4686     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4687     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4688     { Bad_Opcode },
4689   },
4690
4691   /* PREFIX_0F38F8 */
4692   {
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4696   },
4697
4698   /* PREFIX_0F38F9 */
4699   {
4700     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4701   },
4702
4703   /* PREFIX_0F3A08 */
4704   {
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4708   },
4709
4710   /* PREFIX_0F3A09 */
4711   {
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4715   },
4716
4717   /* PREFIX_0F3A0A */
4718   {
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4722   },
4723
4724   /* PREFIX_0F3A0B */
4725   {
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4729   },
4730
4731   /* PREFIX_0F3A0C */
4732   {
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4736   },
4737
4738   /* PREFIX_0F3A0D */
4739   {
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4743   },
4744
4745   /* PREFIX_0F3A0E */
4746   {
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4750   },
4751
4752   /* PREFIX_0F3A14 */
4753   {
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4757   },
4758
4759   /* PREFIX_0F3A15 */
4760   {
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4764   },
4765
4766   /* PREFIX_0F3A16 */
4767   {
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4771   },
4772
4773   /* PREFIX_0F3A17 */
4774   {
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4778   },
4779
4780   /* PREFIX_0F3A20 */
4781   {
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4785   },
4786
4787   /* PREFIX_0F3A21 */
4788   {
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4792   },
4793
4794   /* PREFIX_0F3A22 */
4795   {
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4799   },
4800
4801   /* PREFIX_0F3A40 */
4802   {
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4806   },
4807
4808   /* PREFIX_0F3A41 */
4809   {
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4813   },
4814
4815   /* PREFIX_0F3A42 */
4816   {
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4820   },
4821
4822   /* PREFIX_0F3A44 */
4823   {
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4827   },
4828
4829   /* PREFIX_0F3A60 */
4830   {
4831     { Bad_Opcode },
4832     { Bad_Opcode },
4833     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4834   },
4835
4836   /* PREFIX_0F3A61 */
4837   {
4838     { Bad_Opcode },
4839     { Bad_Opcode },
4840     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4841   },
4842
4843   /* PREFIX_0F3A62 */
4844   {
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4848   },
4849
4850   /* PREFIX_0F3A63 */
4851   {
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4855   },
4856
4857   /* PREFIX_0F3ACC */
4858   {
4859     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4860   },
4861
4862   /* PREFIX_0F3ACE */
4863   {
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4867   },
4868
4869   /* PREFIX_0F3ACF */
4870   {
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4874   },
4875
4876   /* PREFIX_0F3ADF */
4877   {
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4881   },
4882
4883   /* PREFIX_VEX_0F10 */
4884   {
4885     { VEX_W_TABLE (VEX_W_0F10_P_0) },
4886     { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4887     { VEX_W_TABLE (VEX_W_0F10_P_2) },
4888     { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4889   },
4890
4891   /* PREFIX_VEX_0F11 */
4892   {
4893     { VEX_W_TABLE (VEX_W_0F11_P_0) },
4894     { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4895     { VEX_W_TABLE (VEX_W_0F11_P_2) },
4896     { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4897   },
4898
4899   /* PREFIX_VEX_0F12 */
4900   {
4901     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4902     { VEX_W_TABLE (VEX_W_0F12_P_1) },
4903     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4904     { VEX_W_TABLE (VEX_W_0F12_P_3) },
4905   },
4906
4907   /* PREFIX_VEX_0F16 */
4908   {
4909     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4910     { VEX_W_TABLE (VEX_W_0F16_P_1) },
4911     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4912   },
4913
4914   /* PREFIX_VEX_0F2A */
4915   {
4916     { Bad_Opcode },
4917     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4918     { Bad_Opcode },
4919     { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4920   },
4921
4922   /* PREFIX_VEX_0F2C */
4923   {
4924     { Bad_Opcode },
4925     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4926     { Bad_Opcode },
4927     { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4928   },
4929
4930   /* PREFIX_VEX_0F2D */
4931   {
4932     { Bad_Opcode },
4933     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4934     { Bad_Opcode },
4935     { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4936   },
4937
4938   /* PREFIX_VEX_0F2E */
4939   {
4940     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4941     { Bad_Opcode },
4942     { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4943   },
4944
4945   /* PREFIX_VEX_0F2F */
4946   {
4947     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4948     { Bad_Opcode },
4949     { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4950   },
4951
4952   /* PREFIX_VEX_0F41 */
4953   {
4954     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4955     { Bad_Opcode },
4956     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4957   },
4958
4959   /* PREFIX_VEX_0F42 */
4960   {
4961     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4962     { Bad_Opcode },
4963     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4964   },
4965
4966   /* PREFIX_VEX_0F44 */
4967   {
4968     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4969     { Bad_Opcode },
4970     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4971   },
4972
4973   /* PREFIX_VEX_0F45 */
4974   {
4975     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4976     { Bad_Opcode },
4977     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4978   },
4979
4980   /* PREFIX_VEX_0F46 */
4981   {
4982     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4983     { Bad_Opcode },
4984     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4985   },
4986
4987   /* PREFIX_VEX_0F47 */
4988   {
4989     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4990     { Bad_Opcode },
4991     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4992   },
4993
4994   /* PREFIX_VEX_0F4A */
4995   {
4996     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4997     { Bad_Opcode },
4998     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4999   },
5000
5001   /* PREFIX_VEX_0F4B */
5002   {
5003     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5004     { Bad_Opcode },
5005     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5006   },
5007
5008   /* PREFIX_VEX_0F51 */
5009   {
5010     { VEX_W_TABLE (VEX_W_0F51_P_0) },
5011     { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5012     { VEX_W_TABLE (VEX_W_0F51_P_2) },
5013     { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5014   },
5015
5016   /* PREFIX_VEX_0F52 */
5017   {
5018     { VEX_W_TABLE (VEX_W_0F52_P_0) },
5019     { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5020   },
5021
5022   /* PREFIX_VEX_0F53 */
5023   {
5024     { VEX_W_TABLE (VEX_W_0F53_P_0) },
5025     { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5026   },
5027
5028   /* PREFIX_VEX_0F58 */
5029   {
5030     { VEX_W_TABLE (VEX_W_0F58_P_0) },
5031     { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5032     { VEX_W_TABLE (VEX_W_0F58_P_2) },
5033     { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5034   },
5035
5036   /* PREFIX_VEX_0F59 */
5037   {
5038     { VEX_W_TABLE (VEX_W_0F59_P_0) },
5039     { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5040     { VEX_W_TABLE (VEX_W_0F59_P_2) },
5041     { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5042   },
5043
5044   /* PREFIX_VEX_0F5A */
5045   {
5046     { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5047     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5048     { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5049     { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5050   },
5051
5052   /* PREFIX_VEX_0F5B */
5053   {
5054     { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5055     { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5056     { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5057   },
5058
5059   /* PREFIX_VEX_0F5C */
5060   {
5061     { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5062     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5063     { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5064     { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5065   },
5066
5067   /* PREFIX_VEX_0F5D */
5068   {
5069     { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5070     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5071     { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5072     { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5073   },
5074
5075   /* PREFIX_VEX_0F5E */
5076   {
5077     { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5078     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5079     { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5080     { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5081   },
5082
5083   /* PREFIX_VEX_0F5F */
5084   {
5085     { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5086     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5087     { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5088     { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5089   },
5090
5091   /* PREFIX_VEX_0F60 */
5092   {
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { VEX_W_TABLE (VEX_W_0F60_P_2) },
5096   },
5097
5098   /* PREFIX_VEX_0F61 */
5099   {
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { VEX_W_TABLE (VEX_W_0F61_P_2) },
5103   },
5104
5105   /* PREFIX_VEX_0F62 */
5106   {
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { VEX_W_TABLE (VEX_W_0F62_P_2) },
5110   },
5111
5112   /* PREFIX_VEX_0F63 */
5113   {
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { VEX_W_TABLE (VEX_W_0F63_P_2) },
5117   },
5118
5119   /* PREFIX_VEX_0F64 */
5120   {
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { VEX_W_TABLE (VEX_W_0F64_P_2) },
5124   },
5125
5126   /* PREFIX_VEX_0F65 */
5127   {
5128     { Bad_Opcode },
5129     { Bad_Opcode },
5130     { VEX_W_TABLE (VEX_W_0F65_P_2) },
5131   },
5132
5133   /* PREFIX_VEX_0F66 */
5134   {
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { VEX_W_TABLE (VEX_W_0F66_P_2) },
5138   },
5139
5140   /* PREFIX_VEX_0F67 */
5141   {
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { VEX_W_TABLE (VEX_W_0F67_P_2) },
5145   },
5146
5147   /* PREFIX_VEX_0F68 */
5148   {
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { VEX_W_TABLE (VEX_W_0F68_P_2) },
5152   },
5153
5154   /* PREFIX_VEX_0F69 */
5155   {
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { VEX_W_TABLE (VEX_W_0F69_P_2) },
5159   },
5160
5161   /* PREFIX_VEX_0F6A */
5162   {
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5166   },
5167
5168   /* PREFIX_VEX_0F6B */
5169   {
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5173   },
5174
5175   /* PREFIX_VEX_0F6C */
5176   {
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5180   },
5181
5182   /* PREFIX_VEX_0F6D */
5183   {
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186     { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5187   },
5188
5189   /* PREFIX_VEX_0F6E */
5190   {
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5194   },
5195
5196   /* PREFIX_VEX_0F6F */
5197   {
5198     { Bad_Opcode },
5199     { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5200     { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5201   },
5202
5203   /* PREFIX_VEX_0F70 */
5204   {
5205     { Bad_Opcode },
5206     { VEX_W_TABLE (VEX_W_0F70_P_1) },
5207     { VEX_W_TABLE (VEX_W_0F70_P_2) },
5208     { VEX_W_TABLE (VEX_W_0F70_P_3) },
5209   },
5210
5211   /* PREFIX_VEX_0F71_REG_2 */
5212   {
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5216   },
5217
5218   /* PREFIX_VEX_0F71_REG_4 */
5219   {
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5223   },
5224
5225   /* PREFIX_VEX_0F71_REG_6 */
5226   {
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5230   },
5231
5232   /* PREFIX_VEX_0F72_REG_2 */
5233   {
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5237   },
5238
5239   /* PREFIX_VEX_0F72_REG_4 */
5240   {
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5244   },
5245
5246   /* PREFIX_VEX_0F72_REG_6 */
5247   {
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5251   },
5252
5253   /* PREFIX_VEX_0F73_REG_2 */
5254   {
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5258   },
5259
5260   /* PREFIX_VEX_0F73_REG_3 */
5261   {
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5265   },
5266
5267   /* PREFIX_VEX_0F73_REG_6 */
5268   {
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5272   },
5273
5274   /* PREFIX_VEX_0F73_REG_7 */
5275   {
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5279   },
5280
5281   /* PREFIX_VEX_0F74 */
5282   {
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { VEX_W_TABLE (VEX_W_0F74_P_2) },
5286   },
5287
5288   /* PREFIX_VEX_0F75 */
5289   {
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { VEX_W_TABLE (VEX_W_0F75_P_2) },
5293   },
5294
5295   /* PREFIX_VEX_0F76 */
5296   {
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { VEX_W_TABLE (VEX_W_0F76_P_2) },
5300   },
5301
5302   /* PREFIX_VEX_0F77 */
5303   {
5304     { VEX_W_TABLE (VEX_W_0F77_P_0) },
5305   },
5306
5307   /* PREFIX_VEX_0F7C */
5308   {
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5312     { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5313   },
5314
5315   /* PREFIX_VEX_0F7D */
5316   {
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5320     { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5321   },
5322
5323   /* PREFIX_VEX_0F7E */
5324   {
5325     { Bad_Opcode },
5326     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5327     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5328   },
5329
5330   /* PREFIX_VEX_0F7F */
5331   {
5332     { Bad_Opcode },
5333     { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5334     { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5335   },
5336
5337   /* PREFIX_VEX_0F90 */
5338   {
5339     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5340     { Bad_Opcode },
5341     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5342   },
5343
5344   /* PREFIX_VEX_0F91 */
5345   {
5346     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5347     { Bad_Opcode },
5348     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5349   },
5350
5351   /* PREFIX_VEX_0F92 */
5352   {
5353     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5354     { Bad_Opcode },
5355     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5356     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5357   },
5358
5359   /* PREFIX_VEX_0F93 */
5360   {
5361     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5362     { Bad_Opcode },
5363     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5364     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5365   },
5366
5367   /* PREFIX_VEX_0F98 */
5368   {
5369     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5370     { Bad_Opcode },
5371     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5372   },
5373
5374   /* PREFIX_VEX_0F99 */
5375   {
5376     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5377     { Bad_Opcode },
5378     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5379   },
5380
5381   /* PREFIX_VEX_0FC2 */
5382   {
5383     { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5384     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5385     { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5386     { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5387   },
5388
5389   /* PREFIX_VEX_0FC4 */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5394   },
5395
5396   /* PREFIX_VEX_0FC5 */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5401   },
5402
5403   /* PREFIX_VEX_0FD0 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5408     { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5409   },
5410
5411   /* PREFIX_VEX_0FD1 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5416   },
5417
5418   /* PREFIX_VEX_0FD2 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5423   },
5424
5425   /* PREFIX_VEX_0FD3 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5430   },
5431
5432   /* PREFIX_VEX_0FD4 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5437   },
5438
5439   /* PREFIX_VEX_0FD5 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5444   },
5445
5446   /* PREFIX_VEX_0FD6 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5451   },
5452
5453   /* PREFIX_VEX_0FD7 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5458   },
5459
5460   /* PREFIX_VEX_0FD8 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5465   },
5466
5467   /* PREFIX_VEX_0FD9 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5472   },
5473
5474   /* PREFIX_VEX_0FDA */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5479   },
5480
5481   /* PREFIX_VEX_0FDB */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5486   },
5487
5488   /* PREFIX_VEX_0FDC */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5493   },
5494
5495   /* PREFIX_VEX_0FDD */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5500   },
5501
5502   /* PREFIX_VEX_0FDE */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5507   },
5508
5509   /* PREFIX_VEX_0FDF */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5514   },
5515
5516   /* PREFIX_VEX_0FE0 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5521   },
5522
5523   /* PREFIX_VEX_0FE1 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5528   },
5529
5530   /* PREFIX_VEX_0FE2 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5535   },
5536
5537   /* PREFIX_VEX_0FE3 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5542   },
5543
5544   /* PREFIX_VEX_0FE4 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5549   },
5550
5551   /* PREFIX_VEX_0FE5 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5556   },
5557
5558   /* PREFIX_VEX_0FE6 */
5559   {
5560     { Bad_Opcode },
5561     { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5562     { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5563     { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5564   },
5565
5566   /* PREFIX_VEX_0FE7 */
5567   {
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5571   },
5572
5573   /* PREFIX_VEX_0FE8 */
5574   {
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5578   },
5579
5580   /* PREFIX_VEX_0FE9 */
5581   {
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5585   },
5586
5587   /* PREFIX_VEX_0FEA */
5588   {
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5592   },
5593
5594   /* PREFIX_VEX_0FEB */
5595   {
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5599   },
5600
5601   /* PREFIX_VEX_0FEC */
5602   {
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5606   },
5607
5608   /* PREFIX_VEX_0FED */
5609   {
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { VEX_W_TABLE (VEX_W_0FED_P_2) },
5613   },
5614
5615   /* PREFIX_VEX_0FEE */
5616   {
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5620   },
5621
5622   /* PREFIX_VEX_0FEF */
5623   {
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5627   },
5628
5629   /* PREFIX_VEX_0FF0 */
5630   {
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5635   },
5636
5637   /* PREFIX_VEX_0FF1 */
5638   {
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5642   },
5643
5644   /* PREFIX_VEX_0FF2 */
5645   {
5646     { Bad_Opcode },
5647     { Bad_Opcode },
5648     { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5649   },
5650
5651   /* PREFIX_VEX_0FF3 */
5652   {
5653     { Bad_Opcode },
5654     { Bad_Opcode },
5655     { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5656   },
5657
5658   /* PREFIX_VEX_0FF4 */
5659   {
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5663   },
5664
5665   /* PREFIX_VEX_0FF5 */
5666   {
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5670   },
5671
5672   /* PREFIX_VEX_0FF6 */
5673   {
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5677   },
5678
5679   /* PREFIX_VEX_0FF7 */
5680   {
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5684   },
5685
5686   /* PREFIX_VEX_0FF8 */
5687   {
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5691   },
5692
5693   /* PREFIX_VEX_0FF9 */
5694   {
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5698   },
5699
5700   /* PREFIX_VEX_0FFA */
5701   {
5702     { Bad_Opcode },
5703     { Bad_Opcode },
5704     { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5705   },
5706
5707   /* PREFIX_VEX_0FFB */
5708   {
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5712   },
5713
5714   /* PREFIX_VEX_0FFC */
5715   {
5716     { Bad_Opcode },
5717     { Bad_Opcode },
5718     { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5719   },
5720
5721   /* PREFIX_VEX_0FFD */
5722   {
5723     { Bad_Opcode },
5724     { Bad_Opcode },
5725     { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5726   },
5727
5728   /* PREFIX_VEX_0FFE */
5729   {
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5733   },
5734
5735   /* PREFIX_VEX_0F3800 */
5736   {
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5740   },
5741
5742   /* PREFIX_VEX_0F3801 */
5743   {
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5747   },
5748
5749   /* PREFIX_VEX_0F3802 */
5750   {
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5754   },
5755
5756   /* PREFIX_VEX_0F3803 */
5757   {
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5761   },
5762
5763   /* PREFIX_VEX_0F3804 */
5764   {
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5768   },
5769
5770   /* PREFIX_VEX_0F3805 */
5771   {
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5775   },
5776
5777   /* PREFIX_VEX_0F3806 */
5778   {
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5782   },
5783
5784   /* PREFIX_VEX_0F3807 */
5785   {
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5789   },
5790
5791   /* PREFIX_VEX_0F3808 */
5792   {
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5796   },
5797
5798   /* PREFIX_VEX_0F3809 */
5799   {
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5803   },
5804
5805   /* PREFIX_VEX_0F380A */
5806   {
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5810   },
5811
5812   /* PREFIX_VEX_0F380B */
5813   {
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5817   },
5818
5819   /* PREFIX_VEX_0F380C */
5820   {
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5824   },
5825
5826   /* PREFIX_VEX_0F380D */
5827   {
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5831   },
5832
5833   /* PREFIX_VEX_0F380E */
5834   {
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5838   },
5839
5840   /* PREFIX_VEX_0F380F */
5841   {
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5845   },
5846
5847   /* PREFIX_VEX_0F3813 */
5848   {
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5852   },
5853
5854   /* PREFIX_VEX_0F3816 */
5855   {
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5859   },
5860
5861   /* PREFIX_VEX_0F3817 */
5862   {
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5866   },
5867
5868   /* PREFIX_VEX_0F3818 */
5869   {
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5873   },
5874
5875   /* PREFIX_VEX_0F3819 */
5876   {
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5880   },
5881
5882   /* PREFIX_VEX_0F381A */
5883   {
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5887   },
5888
5889   /* PREFIX_VEX_0F381C */
5890   {
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5894   },
5895
5896   /* PREFIX_VEX_0F381D */
5897   {
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5901   },
5902
5903   /* PREFIX_VEX_0F381E */
5904   {
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5908   },
5909
5910   /* PREFIX_VEX_0F3820 */
5911   {
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5915   },
5916
5917   /* PREFIX_VEX_0F3821 */
5918   {
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5922   },
5923
5924   /* PREFIX_VEX_0F3822 */
5925   {
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5929   },
5930
5931   /* PREFIX_VEX_0F3823 */
5932   {
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5936   },
5937
5938   /* PREFIX_VEX_0F3824 */
5939   {
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5943   },
5944
5945   /* PREFIX_VEX_0F3825 */
5946   {
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5950   },
5951
5952   /* PREFIX_VEX_0F3828 */
5953   {
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5957   },
5958
5959   /* PREFIX_VEX_0F3829 */
5960   {
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5964   },
5965
5966   /* PREFIX_VEX_0F382A */
5967   {
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5971   },
5972
5973   /* PREFIX_VEX_0F382B */
5974   {
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5978   },
5979
5980   /* PREFIX_VEX_0F382C */
5981   {
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5985   },
5986
5987   /* PREFIX_VEX_0F382D */
5988   {
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5992   },
5993
5994   /* PREFIX_VEX_0F382E */
5995   {
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5999   },
6000
6001   /* PREFIX_VEX_0F382F */
6002   {
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6006   },
6007
6008   /* PREFIX_VEX_0F3830 */
6009   {
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6013   },
6014
6015   /* PREFIX_VEX_0F3831 */
6016   {
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6020   },
6021
6022   /* PREFIX_VEX_0F3832 */
6023   {
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6027   },
6028
6029   /* PREFIX_VEX_0F3833 */
6030   {
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6034   },
6035
6036   /* PREFIX_VEX_0F3834 */
6037   {
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6041   },
6042
6043   /* PREFIX_VEX_0F3835 */
6044   {
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6048   },
6049
6050   /* PREFIX_VEX_0F3836 */
6051   {
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6055   },
6056
6057   /* PREFIX_VEX_0F3837 */
6058   {
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6062   },
6063
6064   /* PREFIX_VEX_0F3838 */
6065   {
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6069   },
6070
6071   /* PREFIX_VEX_0F3839 */
6072   {
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6076   },
6077
6078   /* PREFIX_VEX_0F383A */
6079   {
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6083   },
6084
6085   /* PREFIX_VEX_0F383B */
6086   {
6087     { Bad_Opcode },
6088     { Bad_Opcode },
6089     { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6090   },
6091
6092   /* PREFIX_VEX_0F383C */
6093   {
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6097   },
6098
6099   /* PREFIX_VEX_0F383D */
6100   {
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6104   },
6105
6106   /* PREFIX_VEX_0F383E */
6107   {
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6111   },
6112
6113   /* PREFIX_VEX_0F383F */
6114   {
6115     { Bad_Opcode },
6116     { Bad_Opcode },
6117     { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6118   },
6119
6120   /* PREFIX_VEX_0F3840 */
6121   {
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6125   },
6126
6127   /* PREFIX_VEX_0F3841 */
6128   {
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6132   },
6133
6134   /* PREFIX_VEX_0F3845 */
6135   {
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6139   },
6140
6141   /* PREFIX_VEX_0F3846 */
6142   {
6143     { Bad_Opcode },
6144     { Bad_Opcode },
6145     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6146   },
6147
6148   /* PREFIX_VEX_0F3847 */
6149   {
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6153   },
6154
6155   /* PREFIX_VEX_0F3858 */
6156   {
6157     { Bad_Opcode },
6158     { Bad_Opcode },
6159     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6160   },
6161
6162   /* PREFIX_VEX_0F3859 */
6163   {
6164     { Bad_Opcode },
6165     { Bad_Opcode },
6166     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6167   },
6168
6169   /* PREFIX_VEX_0F385A */
6170   {
6171     { Bad_Opcode },
6172     { Bad_Opcode },
6173     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6174   },
6175
6176   /* PREFIX_VEX_0F3878 */
6177   {
6178     { Bad_Opcode },
6179     { Bad_Opcode },
6180     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6181   },
6182
6183   /* PREFIX_VEX_0F3879 */
6184   {
6185     { Bad_Opcode },
6186     { Bad_Opcode },
6187     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6188   },
6189
6190   /* PREFIX_VEX_0F388C */
6191   {
6192     { Bad_Opcode },
6193     { Bad_Opcode },
6194     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6195   },
6196
6197   /* PREFIX_VEX_0F388E */
6198   {
6199     { Bad_Opcode },
6200     { Bad_Opcode },
6201     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6202   },
6203
6204   /* PREFIX_VEX_0F3890 */
6205   {
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6209   },
6210
6211   /* PREFIX_VEX_0F3891 */
6212   {
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6216   },
6217
6218   /* PREFIX_VEX_0F3892 */
6219   {
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6223   },
6224
6225   /* PREFIX_VEX_0F3893 */
6226   {
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6230   },
6231
6232   /* PREFIX_VEX_0F3896 */
6233   {
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6237   },
6238
6239   /* PREFIX_VEX_0F3897 */
6240   {
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6244   },
6245
6246   /* PREFIX_VEX_0F3898 */
6247   {
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6251   },
6252
6253   /* PREFIX_VEX_0F3899 */
6254   {
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6258   },
6259
6260   /* PREFIX_VEX_0F389A */
6261   {
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6265   },
6266
6267   /* PREFIX_VEX_0F389B */
6268   {
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6272   },
6273
6274   /* PREFIX_VEX_0F389C */
6275   {
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6279   },
6280
6281   /* PREFIX_VEX_0F389D */
6282   {
6283     { Bad_Opcode },
6284     { Bad_Opcode },
6285     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6286   },
6287
6288   /* PREFIX_VEX_0F389E */
6289   {
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6293   },
6294
6295   /* PREFIX_VEX_0F389F */
6296   {
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6300   },
6301
6302   /* PREFIX_VEX_0F38A6 */
6303   {
6304     { Bad_Opcode },
6305     { Bad_Opcode },
6306     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6307     { Bad_Opcode },
6308   },
6309
6310   /* PREFIX_VEX_0F38A7 */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6315   },
6316
6317   /* PREFIX_VEX_0F38A8 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6322   },
6323
6324   /* PREFIX_VEX_0F38A9 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6329   },
6330
6331   /* PREFIX_VEX_0F38AA */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6336   },
6337
6338   /* PREFIX_VEX_0F38AB */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6343   },
6344
6345   /* PREFIX_VEX_0F38AC */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6350   },
6351
6352   /* PREFIX_VEX_0F38AD */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6357   },
6358
6359   /* PREFIX_VEX_0F38AE */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F38AF */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F38B6 */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F38B7 */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F38B8 */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F38B9 */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F38BA */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6406   },
6407
6408   /* PREFIX_VEX_0F38BB */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6413   },
6414
6415   /* PREFIX_VEX_0F38BC */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6420   },
6421
6422   /* PREFIX_VEX_0F38BD */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6427   },
6428
6429   /* PREFIX_VEX_0F38BE */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6434   },
6435
6436   /* PREFIX_VEX_0F38BF */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6441   },
6442
6443   /* PREFIX_VEX_0F38CF */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6448   },
6449
6450   /* PREFIX_VEX_0F38DB */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F38DC */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { "vaesenc",        { XM, Vex, EXx }, 0 },
6462   },
6463
6464   /* PREFIX_VEX_0F38DD */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6469   },
6470
6471   /* PREFIX_VEX_0F38DE */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { "vaesdec",        { XM, Vex, EXx }, 0 },
6476   },
6477
6478   /* PREFIX_VEX_0F38DF */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6483   },
6484
6485   /* PREFIX_VEX_0F38F2 */
6486   {
6487     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6488   },
6489
6490   /* PREFIX_VEX_0F38F3_REG_1 */
6491   {
6492     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6493   },
6494
6495   /* PREFIX_VEX_0F38F3_REG_2 */
6496   {
6497     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6498   },
6499
6500   /* PREFIX_VEX_0F38F3_REG_3 */
6501   {
6502     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6503   },
6504
6505   /* PREFIX_VEX_0F38F5 */
6506   {
6507     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6508     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6511   },
6512
6513   /* PREFIX_VEX_0F38F6 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { Bad_Opcode },
6518     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6519   },
6520
6521   /* PREFIX_VEX_0F38F7 */
6522   {
6523     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6524     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6525     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6526     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6527   },
6528
6529   /* PREFIX_VEX_0F3A00 */
6530   {
6531     { Bad_Opcode },
6532     { Bad_Opcode },
6533     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6534   },
6535
6536   /* PREFIX_VEX_0F3A01 */
6537   {
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6541   },
6542
6543   /* PREFIX_VEX_0F3A02 */
6544   {
6545     { Bad_Opcode },
6546     { Bad_Opcode },
6547     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6548   },
6549
6550   /* PREFIX_VEX_0F3A04 */
6551   {
6552     { Bad_Opcode },
6553     { Bad_Opcode },
6554     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6555   },
6556
6557   /* PREFIX_VEX_0F3A05 */
6558   {
6559     { Bad_Opcode },
6560     { Bad_Opcode },
6561     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6562   },
6563
6564   /* PREFIX_VEX_0F3A06 */
6565   {
6566     { Bad_Opcode },
6567     { Bad_Opcode },
6568     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6569   },
6570
6571   /* PREFIX_VEX_0F3A08 */
6572   {
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6576   },
6577
6578   /* PREFIX_VEX_0F3A09 */
6579   {
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6583   },
6584
6585   /* PREFIX_VEX_0F3A0A */
6586   {
6587     { Bad_Opcode },
6588     { Bad_Opcode },
6589     { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6590   },
6591
6592   /* PREFIX_VEX_0F3A0B */
6593   {
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6597   },
6598
6599   /* PREFIX_VEX_0F3A0C */
6600   {
6601     { Bad_Opcode },
6602     { Bad_Opcode },
6603     { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6604   },
6605
6606   /* PREFIX_VEX_0F3A0D */
6607   {
6608     { Bad_Opcode },
6609     { Bad_Opcode },
6610     { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6611   },
6612
6613   /* PREFIX_VEX_0F3A0E */
6614   {
6615     { Bad_Opcode },
6616     { Bad_Opcode },
6617     { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6618   },
6619
6620   /* PREFIX_VEX_0F3A0F */
6621   {
6622     { Bad_Opcode },
6623     { Bad_Opcode },
6624     { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6625   },
6626
6627   /* PREFIX_VEX_0F3A14 */
6628   {
6629     { Bad_Opcode },
6630     { Bad_Opcode },
6631     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6632   },
6633
6634   /* PREFIX_VEX_0F3A15 */
6635   {
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6639   },
6640
6641   /* PREFIX_VEX_0F3A16 */
6642   {
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6646   },
6647
6648   /* PREFIX_VEX_0F3A17 */
6649   {
6650     { Bad_Opcode },
6651     { Bad_Opcode },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6653   },
6654
6655   /* PREFIX_VEX_0F3A18 */
6656   {
6657     { Bad_Opcode },
6658     { Bad_Opcode },
6659     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6660   },
6661
6662   /* PREFIX_VEX_0F3A19 */
6663   {
6664     { Bad_Opcode },
6665     { Bad_Opcode },
6666     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6667   },
6668
6669   /* PREFIX_VEX_0F3A1D */
6670   {
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6674   },
6675
6676   /* PREFIX_VEX_0F3A20 */
6677   {
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6681   },
6682
6683   /* PREFIX_VEX_0F3A21 */
6684   {
6685     { Bad_Opcode },
6686     { Bad_Opcode },
6687     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6688   },
6689
6690   /* PREFIX_VEX_0F3A22 */
6691   {
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6695   },
6696
6697   /* PREFIX_VEX_0F3A30 */
6698   {
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6702   },
6703
6704   /* PREFIX_VEX_0F3A31 */
6705   {
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6709   },
6710
6711   /* PREFIX_VEX_0F3A32 */
6712   {
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6716   },
6717
6718   /* PREFIX_VEX_0F3A33 */
6719   {
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6723   },
6724
6725   /* PREFIX_VEX_0F3A38 */
6726   {
6727     { Bad_Opcode },
6728     { Bad_Opcode },
6729     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6730   },
6731
6732   /* PREFIX_VEX_0F3A39 */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6737   },
6738
6739   /* PREFIX_VEX_0F3A40 */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6744   },
6745
6746   /* PREFIX_VEX_0F3A41 */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6751   },
6752
6753   /* PREFIX_VEX_0F3A42 */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3A44 */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6765   },
6766
6767   /* PREFIX_VEX_0F3A46 */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3A48 */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6779   },
6780
6781   /* PREFIX_VEX_0F3A49 */
6782   {
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6786   },
6787
6788   /* PREFIX_VEX_0F3A4A */
6789   {
6790     { Bad_Opcode },
6791     { Bad_Opcode },
6792     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6793   },
6794
6795   /* PREFIX_VEX_0F3A4B */
6796   {
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6800   },
6801
6802   /* PREFIX_VEX_0F3A4C */
6803   {
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6807   },
6808
6809   /* PREFIX_VEX_0F3A5C */
6810   {
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6814   },
6815
6816   /* PREFIX_VEX_0F3A5D */
6817   {
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6821   },
6822
6823   /* PREFIX_VEX_0F3A5E */
6824   {
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6828   },
6829
6830   /* PREFIX_VEX_0F3A5F */
6831   {
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6835   },
6836
6837   /* PREFIX_VEX_0F3A60 */
6838   {
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6842     { Bad_Opcode },
6843   },
6844
6845   /* PREFIX_VEX_0F3A61 */
6846   {
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6850   },
6851
6852   /* PREFIX_VEX_0F3A62 */
6853   {
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6857   },
6858
6859   /* PREFIX_VEX_0F3A63 */
6860   {
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6864   },
6865
6866   /* PREFIX_VEX_0F3A68 */
6867   {
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6871   },
6872
6873   /* PREFIX_VEX_0F3A69 */
6874   {
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6878   },
6879
6880   /* PREFIX_VEX_0F3A6A */
6881   {
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6885   },
6886
6887   /* PREFIX_VEX_0F3A6B */
6888   {
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6892   },
6893
6894   /* PREFIX_VEX_0F3A6C */
6895   {
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6899   },
6900
6901   /* PREFIX_VEX_0F3A6D */
6902   {
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6906   },
6907
6908   /* PREFIX_VEX_0F3A6E */
6909   {
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6913   },
6914
6915   /* PREFIX_VEX_0F3A6F */
6916   {
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6920   },
6921
6922   /* PREFIX_VEX_0F3A78 */
6923   {
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6927   },
6928
6929   /* PREFIX_VEX_0F3A79 */
6930   {
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6934   },
6935
6936   /* PREFIX_VEX_0F3A7A */
6937   {
6938     { Bad_Opcode },
6939     { Bad_Opcode },
6940     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6941   },
6942
6943   /* PREFIX_VEX_0F3A7B */
6944   {
6945     { Bad_Opcode },
6946     { Bad_Opcode },
6947     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6948   },
6949
6950   /* PREFIX_VEX_0F3A7C */
6951   {
6952     { Bad_Opcode },
6953     { Bad_Opcode },
6954     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6955     { Bad_Opcode },
6956   },
6957
6958   /* PREFIX_VEX_0F3A7D */
6959   {
6960     { Bad_Opcode },
6961     { Bad_Opcode },
6962     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6963   },
6964
6965   /* PREFIX_VEX_0F3A7E */
6966   {
6967     { Bad_Opcode },
6968     { Bad_Opcode },
6969     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6970   },
6971
6972   /* PREFIX_VEX_0F3A7F */
6973   {
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6977   },
6978
6979   /* PREFIX_VEX_0F3ACE */
6980   {
6981     { Bad_Opcode },
6982     { Bad_Opcode },
6983     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6984   },
6985
6986   /* PREFIX_VEX_0F3ACF */
6987   {
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6991   },
6992
6993   /* PREFIX_VEX_0F3ADF */
6994   {
6995     { Bad_Opcode },
6996     { Bad_Opcode },
6997     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6998   },
6999
7000   /* PREFIX_VEX_0F3AF0 */
7001   {
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     { Bad_Opcode },
7005     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7006   },
7007
7008 #define NEED_PREFIX_TABLE
7009 #include "i386-dis-evex.h"
7010 #undef NEED_PREFIX_TABLE
7011 };
7012
7013 static const struct dis386 x86_64_table[][2] = {
7014   /* X86_64_06 */
7015   {
7016     { "pushP", { es }, 0 },
7017   },
7018
7019   /* X86_64_07 */
7020   {
7021     { "popP", { es }, 0 },
7022   },
7023
7024   /* X86_64_0D */
7025   {
7026     { "pushP", { cs }, 0 },
7027   },
7028
7029   /* X86_64_16 */
7030   {
7031     { "pushP", { ss }, 0 },
7032   },
7033
7034   /* X86_64_17 */
7035   {
7036     { "popP", { ss }, 0 },
7037   },
7038
7039   /* X86_64_1E */
7040   {
7041     { "pushP", { ds }, 0 },
7042   },
7043
7044   /* X86_64_1F */
7045   {
7046     { "popP", { ds }, 0 },
7047   },
7048
7049   /* X86_64_27 */
7050   {
7051     { "daa", { XX }, 0 },
7052   },
7053
7054   /* X86_64_2F */
7055   {
7056     { "das", { XX }, 0 },
7057   },
7058
7059   /* X86_64_37 */
7060   {
7061     { "aaa", { XX }, 0 },
7062   },
7063
7064   /* X86_64_3F */
7065   {
7066     { "aas", { XX }, 0 },
7067   },
7068
7069   /* X86_64_60 */
7070   {
7071     { "pushaP", { XX }, 0 },
7072   },
7073
7074   /* X86_64_61 */
7075   {
7076     { "popaP", { XX }, 0 },
7077   },
7078
7079   /* X86_64_62 */
7080   {
7081     { MOD_TABLE (MOD_62_32BIT) },
7082     { EVEX_TABLE (EVEX_0F) },
7083   },
7084
7085   /* X86_64_63 */
7086   {
7087     { "arpl", { Ew, Gw }, 0 },
7088     { "movs{lq|xd}", { Gv, Ed }, 0 },
7089   },
7090
7091   /* X86_64_6D */
7092   {
7093     { "ins{R|}", { Yzr, indirDX }, 0 },
7094     { "ins{G|}", { Yzr, indirDX }, 0 },
7095   },
7096
7097   /* X86_64_6F */
7098   {
7099     { "outs{R|}", { indirDXr, Xz }, 0 },
7100     { "outs{G|}", { indirDXr, Xz }, 0 },
7101   },
7102
7103   /* X86_64_82 */
7104   {
7105     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
7106     { REG_TABLE (REG_80) },
7107   },
7108
7109   /* X86_64_9A */
7110   {
7111     { "Jcall{T|}", { Ap }, 0 },
7112   },
7113
7114   /* X86_64_C4 */
7115   {
7116     { MOD_TABLE (MOD_C4_32BIT) },
7117     { VEX_C4_TABLE (VEX_0F) },
7118   },
7119
7120   /* X86_64_C5 */
7121   {
7122     { MOD_TABLE (MOD_C5_32BIT) },
7123     { VEX_C5_TABLE (VEX_0F) },
7124   },
7125
7126   /* X86_64_CE */
7127   {
7128     { "into", { XX }, 0 },
7129   },
7130
7131   /* X86_64_D4 */
7132   {
7133     { "aam", { Ib }, 0 },
7134   },
7135
7136   /* X86_64_D5 */
7137   {
7138     { "aad", { Ib }, 0 },
7139   },
7140
7141   /* X86_64_E8 */
7142   {
7143     { "callP",          { Jv, BND }, 0 },
7144     { "call@",          { Jv, BND }, 0 }
7145   },
7146
7147   /* X86_64_E9 */
7148   {
7149     { "jmpP",           { Jv, BND }, 0 },
7150     { "jmp@",           { Jv, BND }, 0 }
7151   },
7152
7153   /* X86_64_EA */
7154   {
7155     { "Jjmp{T|}", { Ap }, 0 },
7156   },
7157
7158   /* X86_64_0F01_REG_0 */
7159   {
7160     { "sgdt{Q|IQ}", { M }, 0 },
7161     { "sgdt", { M }, 0 },
7162   },
7163
7164   /* X86_64_0F01_REG_1 */
7165   {
7166     { "sidt{Q|IQ}", { M }, 0 },
7167     { "sidt", { M }, 0 },
7168   },
7169
7170   /* X86_64_0F01_REG_2 */
7171   {
7172     { "lgdt{Q|Q}", { M }, 0 },
7173     { "lgdt", { M }, 0 },
7174   },
7175
7176   /* X86_64_0F01_REG_3 */
7177   {
7178     { "lidt{Q|Q}", { M }, 0 },
7179     { "lidt", { M }, 0 },
7180   },
7181 };
7182
7183 static const struct dis386 three_byte_table[][256] = {
7184
7185   /* THREE_BYTE_0F38 */
7186   {
7187     /* 00 */
7188     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
7189     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
7190     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
7191     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
7192     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
7193     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
7194     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
7195     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
7196     /* 08 */
7197     { "psignb",         { MX, EM }, PREFIX_OPCODE },
7198     { "psignw",         { MX, EM }, PREFIX_OPCODE },
7199     { "psignd",         { MX, EM }, PREFIX_OPCODE },
7200     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
7201     { Bad_Opcode },
7202     { Bad_Opcode },
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     /* 10 */
7206     { PREFIX_TABLE (PREFIX_0F3810) },
7207     { Bad_Opcode },
7208     { Bad_Opcode },
7209     { Bad_Opcode },
7210     { PREFIX_TABLE (PREFIX_0F3814) },
7211     { PREFIX_TABLE (PREFIX_0F3815) },
7212     { Bad_Opcode },
7213     { PREFIX_TABLE (PREFIX_0F3817) },
7214     /* 18 */
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
7220     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
7221     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
7222     { Bad_Opcode },
7223     /* 20 */
7224     { PREFIX_TABLE (PREFIX_0F3820) },
7225     { PREFIX_TABLE (PREFIX_0F3821) },
7226     { PREFIX_TABLE (PREFIX_0F3822) },
7227     { PREFIX_TABLE (PREFIX_0F3823) },
7228     { PREFIX_TABLE (PREFIX_0F3824) },
7229     { PREFIX_TABLE (PREFIX_0F3825) },
7230     { Bad_Opcode },
7231     { Bad_Opcode },
7232     /* 28 */
7233     { PREFIX_TABLE (PREFIX_0F3828) },
7234     { PREFIX_TABLE (PREFIX_0F3829) },
7235     { PREFIX_TABLE (PREFIX_0F382A) },
7236     { PREFIX_TABLE (PREFIX_0F382B) },
7237     { Bad_Opcode },
7238     { Bad_Opcode },
7239     { Bad_Opcode },
7240     { Bad_Opcode },
7241     /* 30 */
7242     { PREFIX_TABLE (PREFIX_0F3830) },
7243     { PREFIX_TABLE (PREFIX_0F3831) },
7244     { PREFIX_TABLE (PREFIX_0F3832) },
7245     { PREFIX_TABLE (PREFIX_0F3833) },
7246     { PREFIX_TABLE (PREFIX_0F3834) },
7247     { PREFIX_TABLE (PREFIX_0F3835) },
7248     { Bad_Opcode },
7249     { PREFIX_TABLE (PREFIX_0F3837) },
7250     /* 38 */
7251     { PREFIX_TABLE (PREFIX_0F3838) },
7252     { PREFIX_TABLE (PREFIX_0F3839) },
7253     { PREFIX_TABLE (PREFIX_0F383A) },
7254     { PREFIX_TABLE (PREFIX_0F383B) },
7255     { PREFIX_TABLE (PREFIX_0F383C) },
7256     { PREFIX_TABLE (PREFIX_0F383D) },
7257     { PREFIX_TABLE (PREFIX_0F383E) },
7258     { PREFIX_TABLE (PREFIX_0F383F) },
7259     /* 40 */
7260     { PREFIX_TABLE (PREFIX_0F3840) },
7261     { PREFIX_TABLE (PREFIX_0F3841) },
7262     { Bad_Opcode },
7263     { Bad_Opcode },
7264     { Bad_Opcode },
7265     { Bad_Opcode },
7266     { Bad_Opcode },
7267     { Bad_Opcode },
7268     /* 48 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { Bad_Opcode },
7274     { Bad_Opcode },
7275     { Bad_Opcode },
7276     { Bad_Opcode },
7277     /* 50 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 58 */
7287     { Bad_Opcode },
7288     { Bad_Opcode },
7289     { Bad_Opcode },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 60 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 68 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 70 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 78 */
7323     { Bad_Opcode },
7324     { Bad_Opcode },
7325     { Bad_Opcode },
7326     { Bad_Opcode },
7327     { Bad_Opcode },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 80 */
7332     { PREFIX_TABLE (PREFIX_0F3880) },
7333     { PREFIX_TABLE (PREFIX_0F3881) },
7334     { PREFIX_TABLE (PREFIX_0F3882) },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 88 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 90 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 98 */
7359     { Bad_Opcode },
7360     { Bad_Opcode },
7361     { Bad_Opcode },
7362     { Bad_Opcode },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* a0 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* a8 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* b0 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* b8 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* c0 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* c8 */
7413     { PREFIX_TABLE (PREFIX_0F38C8) },
7414     { PREFIX_TABLE (PREFIX_0F38C9) },
7415     { PREFIX_TABLE (PREFIX_0F38CA) },
7416     { PREFIX_TABLE (PREFIX_0F38CB) },
7417     { PREFIX_TABLE (PREFIX_0F38CC) },
7418     { PREFIX_TABLE (PREFIX_0F38CD) },
7419     { Bad_Opcode },
7420     { PREFIX_TABLE (PREFIX_0F38CF) },
7421     /* d0 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* d8 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { PREFIX_TABLE (PREFIX_0F38DB) },
7435     { PREFIX_TABLE (PREFIX_0F38DC) },
7436     { PREFIX_TABLE (PREFIX_0F38DD) },
7437     { PREFIX_TABLE (PREFIX_0F38DE) },
7438     { PREFIX_TABLE (PREFIX_0F38DF) },
7439     /* e0 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* e8 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* f0 */
7458     { PREFIX_TABLE (PREFIX_0F38F0) },
7459     { PREFIX_TABLE (PREFIX_0F38F1) },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { PREFIX_TABLE (PREFIX_0F38F5) },
7464     { PREFIX_TABLE (PREFIX_0F38F6) },
7465     { Bad_Opcode },
7466     /* f8 */
7467     { PREFIX_TABLE (PREFIX_0F38F8) },
7468     { PREFIX_TABLE (PREFIX_0F38F9) },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475   },
7476   /* THREE_BYTE_0F3A */
7477   {
7478     /* 00 */
7479     { Bad_Opcode },
7480     { Bad_Opcode },
7481     { Bad_Opcode },
7482     { Bad_Opcode },
7483     { Bad_Opcode },
7484     { Bad_Opcode },
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     /* 08 */
7488     { PREFIX_TABLE (PREFIX_0F3A08) },
7489     { PREFIX_TABLE (PREFIX_0F3A09) },
7490     { PREFIX_TABLE (PREFIX_0F3A0A) },
7491     { PREFIX_TABLE (PREFIX_0F3A0B) },
7492     { PREFIX_TABLE (PREFIX_0F3A0C) },
7493     { PREFIX_TABLE (PREFIX_0F3A0D) },
7494     { PREFIX_TABLE (PREFIX_0F3A0E) },
7495     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7496     /* 10 */
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { PREFIX_TABLE (PREFIX_0F3A14) },
7502     { PREFIX_TABLE (PREFIX_0F3A15) },
7503     { PREFIX_TABLE (PREFIX_0F3A16) },
7504     { PREFIX_TABLE (PREFIX_0F3A17) },
7505     /* 18 */
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     { Bad_Opcode },
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     /* 20 */
7515     { PREFIX_TABLE (PREFIX_0F3A20) },
7516     { PREFIX_TABLE (PREFIX_0F3A21) },
7517     { PREFIX_TABLE (PREFIX_0F3A22) },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     { Bad_Opcode },
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     /* 28 */
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     { Bad_Opcode },
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     /* 30 */
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538     { Bad_Opcode },
7539     { Bad_Opcode },
7540     { Bad_Opcode },
7541     /* 38 */
7542     { Bad_Opcode },
7543     { Bad_Opcode },
7544     { Bad_Opcode },
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     /* 40 */
7551     { PREFIX_TABLE (PREFIX_0F3A40) },
7552     { PREFIX_TABLE (PREFIX_0F3A41) },
7553     { PREFIX_TABLE (PREFIX_0F3A42) },
7554     { Bad_Opcode },
7555     { PREFIX_TABLE (PREFIX_0F3A44) },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     /* 48 */
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     { Bad_Opcode },
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     /* 50 */
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     { Bad_Opcode },
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     /* 58 */
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     { Bad_Opcode },
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     /* 60 */
7587     { PREFIX_TABLE (PREFIX_0F3A60) },
7588     { PREFIX_TABLE (PREFIX_0F3A61) },
7589     { PREFIX_TABLE (PREFIX_0F3A62) },
7590     { PREFIX_TABLE (PREFIX_0F3A63) },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     /* 68 */
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     { Bad_Opcode },
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     /* 70 */
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     { Bad_Opcode },
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     /* 78 */
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     { Bad_Opcode },
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     /* 80 */
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     { Bad_Opcode },
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     /* 88 */
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     { Bad_Opcode },
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     /* 90 */
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     { Bad_Opcode },
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     /* 98 */
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     { Bad_Opcode },
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     /* a0 */
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     { Bad_Opcode },
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     /* a8 */
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     { Bad_Opcode },
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     /* b0 */
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     { Bad_Opcode },
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     /* b8 */
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     { Bad_Opcode },
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     /* c0 */
7695     { Bad_Opcode },
7696     { Bad_Opcode },
7697     { Bad_Opcode },
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     /* c8 */
7704     { Bad_Opcode },
7705     { Bad_Opcode },
7706     { Bad_Opcode },
7707     { Bad_Opcode },
7708     { PREFIX_TABLE (PREFIX_0F3ACC) },
7709     { Bad_Opcode },
7710     { PREFIX_TABLE (PREFIX_0F3ACE) },
7711     { PREFIX_TABLE (PREFIX_0F3ACF) },
7712     /* d0 */
7713     { Bad_Opcode },
7714     { Bad_Opcode },
7715     { Bad_Opcode },
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     /* d8 */
7722     { Bad_Opcode },
7723     { Bad_Opcode },
7724     { Bad_Opcode },
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { Bad_Opcode },
7728     { Bad_Opcode },
7729     { PREFIX_TABLE (PREFIX_0F3ADF) },
7730     /* e0 */
7731     { Bad_Opcode },
7732     { Bad_Opcode },
7733     { Bad_Opcode },
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     /* e8 */
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     { Bad_Opcode },
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     /* f0 */
7749     { Bad_Opcode },
7750     { Bad_Opcode },
7751     { Bad_Opcode },
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     /* f8 */
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     { Bad_Opcode },
7761     { Bad_Opcode },
7762     { Bad_Opcode },
7763     { Bad_Opcode },
7764     { Bad_Opcode },
7765     { Bad_Opcode },
7766   },
7767 };
7768
7769 static const struct dis386 xop_table[][256] = {
7770   /* XOP_08 */
7771   {
7772     /* 00 */
7773     { Bad_Opcode },
7774     { Bad_Opcode },
7775     { Bad_Opcode },
7776     { Bad_Opcode },
7777     { Bad_Opcode },
7778     { Bad_Opcode },
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     /* 08 */
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     { Bad_Opcode },
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     /* 10 */
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     { Bad_Opcode },
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     /* 18 */
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     { Bad_Opcode },
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     /* 20 */
7809     { Bad_Opcode },
7810     { Bad_Opcode },
7811     { Bad_Opcode },
7812     { Bad_Opcode },
7813     { Bad_Opcode },
7814     { Bad_Opcode },
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     /* 28 */
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     { Bad_Opcode },
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     /* 30 */
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832     { Bad_Opcode },
7833     { Bad_Opcode },
7834     { Bad_Opcode },
7835     /* 38 */
7836     { Bad_Opcode },
7837     { Bad_Opcode },
7838     { Bad_Opcode },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 40 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 48 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { Bad_Opcode },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 50 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 58 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 60 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 68 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 70 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 78 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 80 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7923     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7924     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7925     /* 88 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7933     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7934     /* 90 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7941     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7942     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7943     /* 98 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7951     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7952     /* a0 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7956     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7960     { Bad_Opcode },
7961     /* a8 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* b0 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7978     { Bad_Opcode },
7979     /* b8 */
7980     { Bad_Opcode },
7981     { Bad_Opcode },
7982     { Bad_Opcode },
7983     { Bad_Opcode },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* c0 */
7989     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7990     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7991     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7992     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* c8 */
7998     { Bad_Opcode },
7999     { Bad_Opcode },
8000     { Bad_Opcode },
8001     { Bad_Opcode },
8002     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8003     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8004     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8005     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8006     /* d0 */
8007     { Bad_Opcode },
8008     { Bad_Opcode },
8009     { Bad_Opcode },
8010     { Bad_Opcode },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* d8 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* e0 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* e8 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8039     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8040     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8041     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8042     /* f0 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* f8 */
8052     { Bad_Opcode },
8053     { Bad_Opcode },
8054     { Bad_Opcode },
8055     { Bad_Opcode },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { Bad_Opcode },
8059     { Bad_Opcode },
8060   },
8061   /* XOP_09 */
8062   {
8063     /* 00 */
8064     { Bad_Opcode },
8065     { REG_TABLE (REG_XOP_TBM_01) },
8066     { REG_TABLE (REG_XOP_TBM_02) },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     { Bad_Opcode },
8070     { Bad_Opcode },
8071     { Bad_Opcode },
8072     /* 08 */
8073     { Bad_Opcode },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { Bad_Opcode },
8077     { Bad_Opcode },
8078     { Bad_Opcode },
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     /* 10 */
8082     { Bad_Opcode },
8083     { Bad_Opcode },
8084     { REG_TABLE (REG_XOP_LWPCB) },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     { Bad_Opcode },
8088     { Bad_Opcode },
8089     { Bad_Opcode },
8090     /* 18 */
8091     { Bad_Opcode },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     { Bad_Opcode },
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     /* 20 */
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     { Bad_Opcode },
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     /* 28 */
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     { Bad_Opcode },
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     /* 30 */
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123     { Bad_Opcode },
8124     { Bad_Opcode },
8125     { Bad_Opcode },
8126     /* 38 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 40 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 48 */
8145     { Bad_Opcode },
8146     { Bad_Opcode },
8147     { Bad_Opcode },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 50 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 58 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 60 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 68 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 70 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 78 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 80 */
8208     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8209     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8210     { "vfrczss",        { XM, EXd }, 0 },
8211     { "vfrczsd",        { XM, EXq }, 0 },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 88 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 90 */
8226     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8227     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8228     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8229     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8230     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8232     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234     /* 98 */
8235     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8237     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* a0 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* a8 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* b0 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* b8 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* c0 */
8280     { Bad_Opcode },
8281     { "vphaddbw",       { XM, EXxmm }, 0 },
8282     { "vphaddbd",       { XM, EXxmm }, 0 },
8283     { "vphaddbq",       { XM, EXxmm }, 0 },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { "vphaddwd",       { XM, EXxmm }, 0 },
8287     { "vphaddwq",       { XM, EXxmm }, 0 },
8288     /* c8 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { "vphadddq",       { XM, EXxmm }, 0 },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* d0 */
8298     { Bad_Opcode },
8299     { "vphaddubw",      { XM, EXxmm }, 0 },
8300     { "vphaddubd",      { XM, EXxmm }, 0 },
8301     { "vphaddubq",      { XM, EXxmm }, 0 },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { "vphadduwd",      { XM, EXxmm }, 0 },
8305     { "vphadduwq",      { XM, EXxmm }, 0 },
8306     /* d8 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { "vphaddudq",      { XM, EXxmm }, 0 },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* e0 */
8316     { Bad_Opcode },
8317     { "vphsubbw",       { XM, EXxmm }, 0 },
8318     { "vphsubwd",       { XM, EXxmm }, 0 },
8319     { "vphsubdq",       { XM, EXxmm }, 0 },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* e8 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* f0 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* f8 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351   },
8352   /* XOP_0A */
8353   {
8354     /* 00 */
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     /* 08 */
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     { Bad_Opcode },
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     /* 10 */
8373     { "bextr",  { Gv, Ev, Iq }, 0 },
8374     { Bad_Opcode },
8375     { REG_TABLE (REG_XOP_LWP) },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     { Bad_Opcode },
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     /* 18 */
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     { Bad_Opcode },
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     /* 20 */
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     { Bad_Opcode },
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     /* 28 */
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     { Bad_Opcode },
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     /* 30 */
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414     { Bad_Opcode },
8415     { Bad_Opcode },
8416     { Bad_Opcode },
8417     /* 38 */
8418     { Bad_Opcode },
8419     { Bad_Opcode },
8420     { Bad_Opcode },
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     /* 40 */
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     { Bad_Opcode },
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     /* 48 */
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     { Bad_Opcode },
8439     { Bad_Opcode },
8440     { Bad_Opcode },
8441     { Bad_Opcode },
8442     { Bad_Opcode },
8443     { Bad_Opcode },
8444     /* 50 */
8445     { Bad_Opcode },
8446     { Bad_Opcode },
8447     { Bad_Opcode },
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     /* 58 */
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     { Bad_Opcode },
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     /* 60 */
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     { Bad_Opcode },
8466     { Bad_Opcode },
8467     { Bad_Opcode },
8468     { Bad_Opcode },
8469     { Bad_Opcode },
8470     { Bad_Opcode },
8471     /* 68 */
8472     { Bad_Opcode },
8473     { Bad_Opcode },
8474     { Bad_Opcode },
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     /* 70 */
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     { Bad_Opcode },
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     /* 78 */
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     { Bad_Opcode },
8493     { Bad_Opcode },
8494     { Bad_Opcode },
8495     { Bad_Opcode },
8496     { Bad_Opcode },
8497     { Bad_Opcode },
8498     /* 80 */
8499     { Bad_Opcode },
8500     { Bad_Opcode },
8501     { Bad_Opcode },
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { Bad_Opcode },
8505     { Bad_Opcode },
8506     { Bad_Opcode },
8507     /* 88 */
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     { Bad_Opcode },
8511     { Bad_Opcode },
8512     { Bad_Opcode },
8513     { Bad_Opcode },
8514     { Bad_Opcode },
8515     { Bad_Opcode },
8516     /* 90 */
8517     { Bad_Opcode },
8518     { Bad_Opcode },
8519     { Bad_Opcode },
8520     { Bad_Opcode },
8521     { Bad_Opcode },
8522     { Bad_Opcode },
8523     { Bad_Opcode },
8524     { Bad_Opcode },
8525     /* 98 */
8526     { Bad_Opcode },
8527     { Bad_Opcode },
8528     { Bad_Opcode },
8529     { Bad_Opcode },
8530     { Bad_Opcode },
8531     { Bad_Opcode },
8532     { Bad_Opcode },
8533     { Bad_Opcode },
8534     /* a0 */
8535     { Bad_Opcode },
8536     { Bad_Opcode },
8537     { Bad_Opcode },
8538     { Bad_Opcode },
8539     { Bad_Opcode },
8540     { Bad_Opcode },
8541     { Bad_Opcode },
8542     { Bad_Opcode },
8543     /* a8 */
8544     { Bad_Opcode },
8545     { Bad_Opcode },
8546     { Bad_Opcode },
8547     { Bad_Opcode },
8548     { Bad_Opcode },
8549     { Bad_Opcode },
8550     { Bad_Opcode },
8551     { Bad_Opcode },
8552     /* b0 */
8553     { Bad_Opcode },
8554     { Bad_Opcode },
8555     { Bad_Opcode },
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { Bad_Opcode },
8561     /* b8 */
8562     { Bad_Opcode },
8563     { Bad_Opcode },
8564     { Bad_Opcode },
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     /* c0 */
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     { Bad_Opcode },
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     /* c8 */
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     { Bad_Opcode },
8583     { Bad_Opcode },
8584     { Bad_Opcode },
8585     { Bad_Opcode },
8586     { Bad_Opcode },
8587     { Bad_Opcode },
8588     /* d0 */
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     { Bad_Opcode },
8592     { Bad_Opcode },
8593     { Bad_Opcode },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     /* d8 */
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     { Bad_Opcode },
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     /* e0 */
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     { Bad_Opcode },
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     /* e8 */
8616     { Bad_Opcode },
8617     { Bad_Opcode },
8618     { Bad_Opcode },
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     /* f0 */
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     { Bad_Opcode },
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     /* f8 */
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     { Bad_Opcode },
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { Bad_Opcode },
8640     { Bad_Opcode },
8641     { Bad_Opcode },
8642   },
8643 };
8644
8645 static const struct dis386 vex_table[][256] = {
8646   /* VEX_0F */
8647   {
8648     /* 00 */
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     { Bad_Opcode },
8655     { Bad_Opcode },
8656     { Bad_Opcode },
8657     /* 08 */
8658     { Bad_Opcode },
8659     { Bad_Opcode },
8660     { Bad_Opcode },
8661     { Bad_Opcode },
8662     { Bad_Opcode },
8663     { Bad_Opcode },
8664     { Bad_Opcode },
8665     { Bad_Opcode },
8666     /* 10 */
8667     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8668     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8669     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8670     { MOD_TABLE (MOD_VEX_0F13) },
8671     { VEX_W_TABLE (VEX_W_0F14) },
8672     { VEX_W_TABLE (VEX_W_0F15) },
8673     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8674     { MOD_TABLE (MOD_VEX_0F17) },
8675     /* 18 */
8676     { Bad_Opcode },
8677     { Bad_Opcode },
8678     { Bad_Opcode },
8679     { Bad_Opcode },
8680     { Bad_Opcode },
8681     { Bad_Opcode },
8682     { Bad_Opcode },
8683     { Bad_Opcode },
8684     /* 20 */
8685     { Bad_Opcode },
8686     { Bad_Opcode },
8687     { Bad_Opcode },
8688     { Bad_Opcode },
8689     { Bad_Opcode },
8690     { Bad_Opcode },
8691     { Bad_Opcode },
8692     { Bad_Opcode },
8693     /* 28 */
8694     { VEX_W_TABLE (VEX_W_0F28) },
8695     { VEX_W_TABLE (VEX_W_0F29) },
8696     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8697     { MOD_TABLE (MOD_VEX_0F2B) },
8698     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8699     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8700     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8701     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8702     /* 30 */
8703     { Bad_Opcode },
8704     { Bad_Opcode },
8705     { Bad_Opcode },
8706     { Bad_Opcode },
8707     { Bad_Opcode },
8708     { Bad_Opcode },
8709     { Bad_Opcode },
8710     { Bad_Opcode },
8711     /* 38 */
8712     { Bad_Opcode },
8713     { Bad_Opcode },
8714     { Bad_Opcode },
8715     { Bad_Opcode },
8716     { Bad_Opcode },
8717     { Bad_Opcode },
8718     { Bad_Opcode },
8719     { Bad_Opcode },
8720     /* 40 */
8721     { Bad_Opcode },
8722     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8724     { Bad_Opcode },
8725     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8729     /* 48 */
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8733     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { Bad_Opcode },
8737     { Bad_Opcode },
8738     /* 50 */
8739     { MOD_TABLE (MOD_VEX_0F50) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8742     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8743     { "vandpX",         { XM, Vex, EXx }, 0 },
8744     { "vandnpX",        { XM, Vex, EXx }, 0 },
8745     { "vorpX",          { XM, Vex, EXx }, 0 },
8746     { "vxorpX",         { XM, Vex, EXx }, 0 },
8747     /* 58 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8754     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8755     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8756     /* 60 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8765     /* 68 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8774     /* 70 */
8775     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8776     { REG_TABLE (REG_VEX_0F71) },
8777     { REG_TABLE (REG_VEX_0F72) },
8778     { REG_TABLE (REG_VEX_0F73) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8783     /* 78 */
8784     { Bad_Opcode },
8785     { Bad_Opcode },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8789     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8792     /* 80 */
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 88 */
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* 90 */
8811     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8814     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* 98 */
8820     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8821     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* a0 */
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* a8 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { REG_TABLE (REG_VEX_0FAE) },
8845     { Bad_Opcode },
8846     /* b0 */
8847     { Bad_Opcode },
8848     { Bad_Opcode },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     /* b8 */
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* c0 */
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8870     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8871     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8872     { Bad_Opcode },
8873     /* c8 */
8874     { Bad_Opcode },
8875     { Bad_Opcode },
8876     { Bad_Opcode },
8877     { Bad_Opcode },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { Bad_Opcode },
8881     { Bad_Opcode },
8882     /* d0 */
8883     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8884     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8885     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8886     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8887     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8888     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8889     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8890     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8891     /* d8 */
8892     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8893     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8894     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8895     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8896     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8897     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8898     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8899     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8900     /* e0 */
8901     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8902     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8903     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8904     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8905     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8906     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8907     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8908     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8909     /* e8 */
8910     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8911     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8912     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8913     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8914     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8915     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8916     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8917     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8918     /* f0 */
8919     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8920     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8921     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8922     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8923     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8924     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8925     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8926     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8927     /* f8 */
8928     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8929     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8930     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8931     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8932     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8933     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8934     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8935     { Bad_Opcode },
8936   },
8937   /* VEX_0F38 */
8938   {
8939     /* 00 */
8940     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8941     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8942     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8943     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8944     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8945     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8946     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8947     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8948     /* 08 */
8949     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8950     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8951     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8952     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8953     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8954     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8955     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8956     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8957     /* 10 */
8958     { Bad_Opcode },
8959     { Bad_Opcode },
8960     { Bad_Opcode },
8961     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8962     { Bad_Opcode },
8963     { Bad_Opcode },
8964     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8965     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8966     /* 18 */
8967     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8968     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8969     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8970     { Bad_Opcode },
8971     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8972     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8973     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8974     { Bad_Opcode },
8975     /* 20 */
8976     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8977     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8978     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8979     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8980     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8981     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     /* 28 */
8985     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8986     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8987     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8990     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8991     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8992     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8993     /* 30 */
8994     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8995     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8996     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8997     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8998     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8999     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9000     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9001     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9002     /* 38 */
9003     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9006     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9007     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9010     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9011     /* 40 */
9012     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9014     { Bad_Opcode },
9015     { Bad_Opcode },
9016     { Bad_Opcode },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9020     /* 48 */
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { Bad_Opcode },
9026     { Bad_Opcode },
9027     { Bad_Opcode },
9028     { Bad_Opcode },
9029     /* 50 */
9030     { Bad_Opcode },
9031     { Bad_Opcode },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { Bad_Opcode },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 58 */
9039     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 60 */
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 68 */
9057     { Bad_Opcode },
9058     { Bad_Opcode },
9059     { Bad_Opcode },
9060     { Bad_Opcode },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     /* 70 */
9066     { Bad_Opcode },
9067     { Bad_Opcode },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     /* 78 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9077     { Bad_Opcode },
9078     { Bad_Opcode },
9079     { Bad_Opcode },
9080     { Bad_Opcode },
9081     { Bad_Opcode },
9082     { Bad_Opcode },
9083     /* 80 */
9084     { Bad_Opcode },
9085     { Bad_Opcode },
9086     { Bad_Opcode },
9087     { Bad_Opcode },
9088     { Bad_Opcode },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     /* 88 */
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9098     { Bad_Opcode },
9099     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9100     { Bad_Opcode },
9101     /* 90 */
9102     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9103     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9104     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9105     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9106     { Bad_Opcode },
9107     { Bad_Opcode },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9110     /* 98 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9115     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9116     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9117     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9118     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9119     /* a0 */
9120     { Bad_Opcode },
9121     { Bad_Opcode },
9122     { Bad_Opcode },
9123     { Bad_Opcode },
9124     { Bad_Opcode },
9125     { Bad_Opcode },
9126     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9128     /* a8 */
9129     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9130     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9131     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9132     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9133     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9134     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9135     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9136     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9137     /* b0 */
9138     { Bad_Opcode },
9139     { Bad_Opcode },
9140     { Bad_Opcode },
9141     { Bad_Opcode },
9142     { Bad_Opcode },
9143     { Bad_Opcode },
9144     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9146     /* b8 */
9147     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9148     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9149     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9150     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9151     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9152     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9153     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9154     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9155     /* c0 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* c8 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9173     /* d0 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* d8 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9187     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9188     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9189     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9190     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9191     /* e0 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* e8 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* f0 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9213     { REG_TABLE (REG_VEX_0F38F3) },
9214     { Bad_Opcode },
9215     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9216     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9217     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9218     /* f8 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227   },
9228   /* VEX_0F3A */
9229   {
9230     /* 00 */
9231     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9232     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9233     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9234     { Bad_Opcode },
9235     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9236     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9237     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9238     { Bad_Opcode },
9239     /* 08 */
9240     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9241     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9242     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9243     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9244     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9245     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9246     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9247     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9248     /* 10 */
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9254     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9255     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9256     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9257     /* 18 */
9258     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9259     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     /* 20 */
9267     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9268     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9269     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     { Bad_Opcode },
9273     { Bad_Opcode },
9274     { Bad_Opcode },
9275     /* 28 */
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     { Bad_Opcode },
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     /* 30 */
9285     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9286     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9287     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9288     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9289     { Bad_Opcode },
9290     { Bad_Opcode },
9291     { Bad_Opcode },
9292     { Bad_Opcode },
9293     /* 38 */
9294     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9295     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9296     { Bad_Opcode },
9297     { Bad_Opcode },
9298     { Bad_Opcode },
9299     { Bad_Opcode },
9300     { Bad_Opcode },
9301     { Bad_Opcode },
9302     /* 40 */
9303     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9304     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9305     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9306     { Bad_Opcode },
9307     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9308     { Bad_Opcode },
9309     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9310     { Bad_Opcode },
9311     /* 48 */
9312     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9313     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9314     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9315     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9316     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9317     { Bad_Opcode },
9318     { Bad_Opcode },
9319     { Bad_Opcode },
9320     /* 50 */
9321     { Bad_Opcode },
9322     { Bad_Opcode },
9323     { Bad_Opcode },
9324     { Bad_Opcode },
9325     { Bad_Opcode },
9326     { Bad_Opcode },
9327     { Bad_Opcode },
9328     { Bad_Opcode },
9329     /* 58 */
9330     { Bad_Opcode },
9331     { Bad_Opcode },
9332     { Bad_Opcode },
9333     { Bad_Opcode },
9334     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9335     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9336     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9337     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9338     /* 60 */
9339     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9340     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9341     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9342     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9343     { Bad_Opcode },
9344     { Bad_Opcode },
9345     { Bad_Opcode },
9346     { Bad_Opcode },
9347     /* 68 */
9348     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9349     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9350     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9351     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9352     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9353     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9354     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9355     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9356     /* 70 */
9357     { Bad_Opcode },
9358     { Bad_Opcode },
9359     { Bad_Opcode },
9360     { Bad_Opcode },
9361     { Bad_Opcode },
9362     { Bad_Opcode },
9363     { Bad_Opcode },
9364     { Bad_Opcode },
9365     /* 78 */
9366     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9367     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9368     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9369     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9370     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9371     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9372     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9373     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9374     /* 80 */
9375     { Bad_Opcode },
9376     { Bad_Opcode },
9377     { Bad_Opcode },
9378     { Bad_Opcode },
9379     { Bad_Opcode },
9380     { Bad_Opcode },
9381     { Bad_Opcode },
9382     { Bad_Opcode },
9383     /* 88 */
9384     { Bad_Opcode },
9385     { Bad_Opcode },
9386     { Bad_Opcode },
9387     { Bad_Opcode },
9388     { Bad_Opcode },
9389     { Bad_Opcode },
9390     { Bad_Opcode },
9391     { Bad_Opcode },
9392     /* 90 */
9393     { Bad_Opcode },
9394     { Bad_Opcode },
9395     { Bad_Opcode },
9396     { Bad_Opcode },
9397     { Bad_Opcode },
9398     { Bad_Opcode },
9399     { Bad_Opcode },
9400     { Bad_Opcode },
9401     /* 98 */
9402     { Bad_Opcode },
9403     { Bad_Opcode },
9404     { Bad_Opcode },
9405     { Bad_Opcode },
9406     { Bad_Opcode },
9407     { Bad_Opcode },
9408     { Bad_Opcode },
9409     { Bad_Opcode },
9410     /* a0 */
9411     { Bad_Opcode },
9412     { Bad_Opcode },
9413     { Bad_Opcode },
9414     { Bad_Opcode },
9415     { Bad_Opcode },
9416     { Bad_Opcode },
9417     { Bad_Opcode },
9418     { Bad_Opcode },
9419     /* a8 */
9420     { Bad_Opcode },
9421     { Bad_Opcode },
9422     { Bad_Opcode },
9423     { Bad_Opcode },
9424     { Bad_Opcode },
9425     { Bad_Opcode },
9426     { Bad_Opcode },
9427     { Bad_Opcode },
9428     /* b0 */
9429     { Bad_Opcode },
9430     { Bad_Opcode },
9431     { Bad_Opcode },
9432     { Bad_Opcode },
9433     { Bad_Opcode },
9434     { Bad_Opcode },
9435     { Bad_Opcode },
9436     { Bad_Opcode },
9437     /* b8 */
9438     { Bad_Opcode },
9439     { Bad_Opcode },
9440     { Bad_Opcode },
9441     { Bad_Opcode },
9442     { Bad_Opcode },
9443     { Bad_Opcode },
9444     { Bad_Opcode },
9445     { Bad_Opcode },
9446     /* c0 */
9447     { Bad_Opcode },
9448     { Bad_Opcode },
9449     { Bad_Opcode },
9450     { Bad_Opcode },
9451     { Bad_Opcode },
9452     { Bad_Opcode },
9453     { Bad_Opcode },
9454     { Bad_Opcode },
9455     /* c8 */
9456     { Bad_Opcode },
9457     { Bad_Opcode },
9458     { Bad_Opcode },
9459     { Bad_Opcode },
9460     { Bad_Opcode },
9461     { Bad_Opcode },
9462     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9463     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9464     /* d0 */
9465     { Bad_Opcode },
9466     { Bad_Opcode },
9467     { Bad_Opcode },
9468     { Bad_Opcode },
9469     { Bad_Opcode },
9470     { Bad_Opcode },
9471     { Bad_Opcode },
9472     { Bad_Opcode },
9473     /* d8 */
9474     { Bad_Opcode },
9475     { Bad_Opcode },
9476     { Bad_Opcode },
9477     { Bad_Opcode },
9478     { Bad_Opcode },
9479     { Bad_Opcode },
9480     { Bad_Opcode },
9481     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9482     /* e0 */
9483     { Bad_Opcode },
9484     { Bad_Opcode },
9485     { Bad_Opcode },
9486     { Bad_Opcode },
9487     { Bad_Opcode },
9488     { Bad_Opcode },
9489     { Bad_Opcode },
9490     { Bad_Opcode },
9491     /* e8 */
9492     { Bad_Opcode },
9493     { Bad_Opcode },
9494     { Bad_Opcode },
9495     { Bad_Opcode },
9496     { Bad_Opcode },
9497     { Bad_Opcode },
9498     { Bad_Opcode },
9499     { Bad_Opcode },
9500     /* f0 */
9501     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9502     { Bad_Opcode },
9503     { Bad_Opcode },
9504     { Bad_Opcode },
9505     { Bad_Opcode },
9506     { Bad_Opcode },
9507     { Bad_Opcode },
9508     { Bad_Opcode },
9509     /* f8 */
9510     { Bad_Opcode },
9511     { Bad_Opcode },
9512     { Bad_Opcode },
9513     { Bad_Opcode },
9514     { Bad_Opcode },
9515     { Bad_Opcode },
9516     { Bad_Opcode },
9517     { Bad_Opcode },
9518   },
9519 };
9520
9521 #define NEED_OPCODE_TABLE
9522 #include "i386-dis-evex.h"
9523 #undef NEED_OPCODE_TABLE
9524 static const struct dis386 vex_len_table[][2] = {
9525   /* VEX_LEN_0F10_P_1 */
9526   {
9527     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9528     { VEX_W_TABLE (VEX_W_0F10_P_1) },
9529   },
9530
9531   /* VEX_LEN_0F10_P_3 */
9532   {
9533     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9534     { VEX_W_TABLE (VEX_W_0F10_P_3) },
9535   },
9536
9537   /* VEX_LEN_0F11_P_1 */
9538   {
9539     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9540     { VEX_W_TABLE (VEX_W_0F11_P_1) },
9541   },
9542
9543   /* VEX_LEN_0F11_P_3 */
9544   {
9545     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9546     { VEX_W_TABLE (VEX_W_0F11_P_3) },
9547   },
9548
9549   /* VEX_LEN_0F12_P_0_M_0 */
9550   {
9551     { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9552   },
9553
9554   /* VEX_LEN_0F12_P_0_M_1 */
9555   {
9556     { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9557   },
9558
9559   /* VEX_LEN_0F12_P_2 */
9560   {
9561     { VEX_W_TABLE (VEX_W_0F12_P_2) },
9562   },
9563
9564   /* VEX_LEN_0F13_M_0 */
9565   {
9566     { VEX_W_TABLE (VEX_W_0F13_M_0) },
9567   },
9568
9569   /* VEX_LEN_0F16_P_0_M_0 */
9570   {
9571     { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9572   },
9573
9574   /* VEX_LEN_0F16_P_0_M_1 */
9575   {
9576     { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9577   },
9578
9579   /* VEX_LEN_0F16_P_2 */
9580   {
9581     { VEX_W_TABLE (VEX_W_0F16_P_2) },
9582   },
9583
9584   /* VEX_LEN_0F17_M_0 */
9585   {
9586     { VEX_W_TABLE (VEX_W_0F17_M_0) },
9587   },
9588
9589   /* VEX_LEN_0F2A_P_1 */
9590   {
9591     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9592     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9593   },
9594
9595   /* VEX_LEN_0F2A_P_3 */
9596   {
9597     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9598     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Ev }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F2C_P_1 */
9602   {
9603     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9604     { "vcvttss2si",     { Gv, EXdScalar }, 0 },
9605   },
9606
9607   /* VEX_LEN_0F2C_P_3 */
9608   {
9609     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9610     { "vcvttsd2si",     { Gv, EXqScalar }, 0 },
9611   },
9612
9613   /* VEX_LEN_0F2D_P_1 */
9614   {
9615     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9616     { "vcvtss2si",      { Gv, EXdScalar }, 0 },
9617   },
9618
9619   /* VEX_LEN_0F2D_P_3 */
9620   {
9621     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9622     { "vcvtsd2si",      { Gv, EXqScalar }, 0 },
9623   },
9624
9625   /* VEX_LEN_0F2E_P_0 */
9626   {
9627     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9628     { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9629   },
9630
9631   /* VEX_LEN_0F2E_P_2 */
9632   {
9633     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9634     { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9635   },
9636
9637   /* VEX_LEN_0F2F_P_0 */
9638   {
9639     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9640     { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9641   },
9642
9643   /* VEX_LEN_0F2F_P_2 */
9644   {
9645     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9646     { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9647   },
9648
9649   /* VEX_LEN_0F41_P_0 */
9650   {
9651     { Bad_Opcode },
9652     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9653   },
9654   /* VEX_LEN_0F41_P_2 */
9655   {
9656     { Bad_Opcode },
9657     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9658   },
9659   /* VEX_LEN_0F42_P_0 */
9660   {
9661     { Bad_Opcode },
9662     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9663   },
9664   /* VEX_LEN_0F42_P_2 */
9665   {
9666     { Bad_Opcode },
9667     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9668   },
9669   /* VEX_LEN_0F44_P_0 */
9670   {
9671     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9672   },
9673   /* VEX_LEN_0F44_P_2 */
9674   {
9675     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9676   },
9677   /* VEX_LEN_0F45_P_0 */
9678   {
9679     { Bad_Opcode },
9680     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9681   },
9682   /* VEX_LEN_0F45_P_2 */
9683   {
9684     { Bad_Opcode },
9685     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9686   },
9687   /* VEX_LEN_0F46_P_0 */
9688   {
9689     { Bad_Opcode },
9690     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9691   },
9692   /* VEX_LEN_0F46_P_2 */
9693   {
9694     { Bad_Opcode },
9695     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9696   },
9697   /* VEX_LEN_0F47_P_0 */
9698   {
9699     { Bad_Opcode },
9700     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9701   },
9702   /* VEX_LEN_0F47_P_2 */
9703   {
9704     { Bad_Opcode },
9705     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9706   },
9707   /* VEX_LEN_0F4A_P_0 */
9708   {
9709     { Bad_Opcode },
9710     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9711   },
9712   /* VEX_LEN_0F4A_P_2 */
9713   {
9714     { Bad_Opcode },
9715     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9716   },
9717   /* VEX_LEN_0F4B_P_0 */
9718   {
9719     { Bad_Opcode },
9720     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9721   },
9722   /* VEX_LEN_0F4B_P_2 */
9723   {
9724     { Bad_Opcode },
9725     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9726   },
9727
9728   /* VEX_LEN_0F51_P_1 */
9729   {
9730     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9731     { VEX_W_TABLE (VEX_W_0F51_P_1) },
9732   },
9733
9734   /* VEX_LEN_0F51_P_3 */
9735   {
9736     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9737     { VEX_W_TABLE (VEX_W_0F51_P_3) },
9738   },
9739
9740   /* VEX_LEN_0F52_P_1 */
9741   {
9742     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9743     { VEX_W_TABLE (VEX_W_0F52_P_1) },
9744   },
9745
9746   /* VEX_LEN_0F53_P_1 */
9747   {
9748     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9749     { VEX_W_TABLE (VEX_W_0F53_P_1) },
9750   },
9751
9752   /* VEX_LEN_0F58_P_1 */
9753   {
9754     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9755     { VEX_W_TABLE (VEX_W_0F58_P_1) },
9756   },
9757
9758   /* VEX_LEN_0F58_P_3 */
9759   {
9760     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9761     { VEX_W_TABLE (VEX_W_0F58_P_3) },
9762   },
9763
9764   /* VEX_LEN_0F59_P_1 */
9765   {
9766     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9767     { VEX_W_TABLE (VEX_W_0F59_P_1) },
9768   },
9769
9770   /* VEX_LEN_0F59_P_3 */
9771   {
9772     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9773     { VEX_W_TABLE (VEX_W_0F59_P_3) },
9774   },
9775
9776   /* VEX_LEN_0F5A_P_1 */
9777   {
9778     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9779     { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9780   },
9781
9782   /* VEX_LEN_0F5A_P_3 */
9783   {
9784     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9785     { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9786   },
9787
9788   /* VEX_LEN_0F5C_P_1 */
9789   {
9790     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9791     { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9792   },
9793
9794   /* VEX_LEN_0F5C_P_3 */
9795   {
9796     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9797     { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9798   },
9799
9800   /* VEX_LEN_0F5D_P_1 */
9801   {
9802     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9803     { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9804   },
9805
9806   /* VEX_LEN_0F5D_P_3 */
9807   {
9808     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9809     { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9810   },
9811
9812   /* VEX_LEN_0F5E_P_1 */
9813   {
9814     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9815     { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9816   },
9817
9818   /* VEX_LEN_0F5E_P_3 */
9819   {
9820     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9821     { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9822   },
9823
9824   /* VEX_LEN_0F5F_P_1 */
9825   {
9826     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9827     { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9828   },
9829
9830   /* VEX_LEN_0F5F_P_3 */
9831   {
9832     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9833     { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9834   },
9835
9836   /* VEX_LEN_0F6E_P_2 */
9837   {
9838     { "vmovK",          { XMScalar, Edq }, 0 },
9839     { "vmovK",          { XMScalar, Edq }, 0 },
9840   },
9841
9842   /* VEX_LEN_0F7E_P_1 */
9843   {
9844     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9845     { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9846   },
9847
9848   /* VEX_LEN_0F7E_P_2 */
9849   {
9850     { "vmovK",          { Edq, XMScalar }, 0 },
9851     { "vmovK",          { Edq, XMScalar }, 0 },
9852   },
9853
9854   /* VEX_LEN_0F90_P_0 */
9855   {
9856     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9857   },
9858
9859   /* VEX_LEN_0F90_P_2 */
9860   {
9861     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9862   },
9863
9864   /* VEX_LEN_0F91_P_0 */
9865   {
9866     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9867   },
9868
9869   /* VEX_LEN_0F91_P_2 */
9870   {
9871     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9872   },
9873
9874   /* VEX_LEN_0F92_P_0 */
9875   {
9876     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9877   },
9878
9879   /* VEX_LEN_0F92_P_2 */
9880   {
9881     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9882   },
9883
9884   /* VEX_LEN_0F92_P_3 */
9885   {
9886     { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9887   },
9888
9889   /* VEX_LEN_0F93_P_0 */
9890   {
9891     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9892   },
9893
9894   /* VEX_LEN_0F93_P_2 */
9895   {
9896     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9897   },
9898
9899   /* VEX_LEN_0F93_P_3 */
9900   {
9901     { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9902   },
9903
9904   /* VEX_LEN_0F98_P_0 */
9905   {
9906     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9907   },
9908
9909   /* VEX_LEN_0F98_P_2 */
9910   {
9911     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9912   },
9913
9914   /* VEX_LEN_0F99_P_0 */
9915   {
9916     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9917   },
9918
9919   /* VEX_LEN_0F99_P_2 */
9920   {
9921     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9922   },
9923
9924   /* VEX_LEN_0FAE_R_2_M_0 */
9925   {
9926     { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9927   },
9928
9929   /* VEX_LEN_0FAE_R_3_M_0 */
9930   {
9931     { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9932   },
9933
9934   /* VEX_LEN_0FC2_P_1 */
9935   {
9936     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9937     { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9938   },
9939
9940   /* VEX_LEN_0FC2_P_3 */
9941   {
9942     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9943     { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9944   },
9945
9946   /* VEX_LEN_0FC4_P_2 */
9947   {
9948     { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9949   },
9950
9951   /* VEX_LEN_0FC5_P_2 */
9952   {
9953     { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9954   },
9955
9956   /* VEX_LEN_0FD6_P_2 */
9957   {
9958     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9959     { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9960   },
9961
9962   /* VEX_LEN_0FF7_P_2 */
9963   {
9964     { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9965   },
9966
9967   /* VEX_LEN_0F3816_P_2 */
9968   {
9969     { Bad_Opcode },
9970     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9971   },
9972
9973   /* VEX_LEN_0F3819_P_2 */
9974   {
9975     { Bad_Opcode },
9976     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9977   },
9978
9979   /* VEX_LEN_0F381A_P_2_M_0 */
9980   {
9981     { Bad_Opcode },
9982     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9983   },
9984
9985   /* VEX_LEN_0F3836_P_2 */
9986   {
9987     { Bad_Opcode },
9988     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9989   },
9990
9991   /* VEX_LEN_0F3841_P_2 */
9992   {
9993     { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9994   },
9995
9996   /* VEX_LEN_0F385A_P_2_M_0 */
9997   {
9998     { Bad_Opcode },
9999     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10000   },
10001
10002   /* VEX_LEN_0F38DB_P_2 */
10003   {
10004     { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10005   },
10006
10007   /* VEX_LEN_0F38F2_P_0 */
10008   {
10009     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
10010   },
10011
10012   /* VEX_LEN_0F38F3_R_1_P_0 */
10013   {
10014     { "blsrS",          { VexGdq, Edq }, 0 },
10015   },
10016
10017   /* VEX_LEN_0F38F3_R_2_P_0 */
10018   {
10019     { "blsmskS",        { VexGdq, Edq }, 0 },
10020   },
10021
10022   /* VEX_LEN_0F38F3_R_3_P_0 */
10023   {
10024     { "blsiS",          { VexGdq, Edq }, 0 },
10025   },
10026
10027   /* VEX_LEN_0F38F5_P_0 */
10028   {
10029     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
10030   },
10031
10032   /* VEX_LEN_0F38F5_P_1 */
10033   {
10034     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
10035   },
10036
10037   /* VEX_LEN_0F38F5_P_3 */
10038   {
10039     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
10040   },
10041
10042   /* VEX_LEN_0F38F6_P_3 */
10043   {
10044     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
10045   },
10046
10047   /* VEX_LEN_0F38F7_P_0 */
10048   {
10049     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
10050   },
10051
10052   /* VEX_LEN_0F38F7_P_1 */
10053   {
10054     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
10055   },
10056
10057   /* VEX_LEN_0F38F7_P_2 */
10058   {
10059     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
10060   },
10061
10062   /* VEX_LEN_0F38F7_P_3 */
10063   {
10064     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
10065   },
10066
10067   /* VEX_LEN_0F3A00_P_2 */
10068   {
10069     { Bad_Opcode },
10070     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10071   },
10072
10073   /* VEX_LEN_0F3A01_P_2 */
10074   {
10075     { Bad_Opcode },
10076     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10077   },
10078
10079   /* VEX_LEN_0F3A06_P_2 */
10080   {
10081     { Bad_Opcode },
10082     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10083   },
10084
10085   /* VEX_LEN_0F3A0A_P_2 */
10086   {
10087     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10088     { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10089   },
10090
10091   /* VEX_LEN_0F3A0B_P_2 */
10092   {
10093     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10094     { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10095   },
10096
10097   /* VEX_LEN_0F3A14_P_2 */
10098   {
10099     { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10100   },
10101
10102   /* VEX_LEN_0F3A15_P_2 */
10103   {
10104     { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10105   },
10106
10107   /* VEX_LEN_0F3A16_P_2  */
10108   {
10109     { "vpextrK",        { Edq, XM, Ib }, 0 },
10110   },
10111
10112   /* VEX_LEN_0F3A17_P_2 */
10113   {
10114     { "vextractps",     { Edqd, XM, Ib }, 0 },
10115   },
10116
10117   /* VEX_LEN_0F3A18_P_2 */
10118   {
10119     { Bad_Opcode },
10120     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10121   },
10122
10123   /* VEX_LEN_0F3A19_P_2 */
10124   {
10125     { Bad_Opcode },
10126     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10127   },
10128
10129   /* VEX_LEN_0F3A20_P_2 */
10130   {
10131     { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10132   },
10133
10134   /* VEX_LEN_0F3A21_P_2 */
10135   {
10136     { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10137   },
10138
10139   /* VEX_LEN_0F3A22_P_2 */
10140   {
10141     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
10142   },
10143
10144   /* VEX_LEN_0F3A30_P_2 */
10145   {
10146     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10147   },
10148
10149   /* VEX_LEN_0F3A31_P_2 */
10150   {
10151     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10152   },
10153
10154   /* VEX_LEN_0F3A32_P_2 */
10155   {
10156     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10157   },
10158
10159   /* VEX_LEN_0F3A33_P_2 */
10160   {
10161     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10162   },
10163
10164   /* VEX_LEN_0F3A38_P_2 */
10165   {
10166     { Bad_Opcode },
10167     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10168   },
10169
10170   /* VEX_LEN_0F3A39_P_2 */
10171   {
10172     { Bad_Opcode },
10173     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10174   },
10175
10176   /* VEX_LEN_0F3A41_P_2 */
10177   {
10178     { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10179   },
10180
10181   /* VEX_LEN_0F3A46_P_2 */
10182   {
10183     { Bad_Opcode },
10184     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10185   },
10186
10187   /* VEX_LEN_0F3A60_P_2 */
10188   {
10189     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10190   },
10191
10192   /* VEX_LEN_0F3A61_P_2 */
10193   {
10194     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10195   },
10196
10197   /* VEX_LEN_0F3A62_P_2 */
10198   {
10199     { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10200   },
10201
10202   /* VEX_LEN_0F3A63_P_2 */
10203   {
10204     { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10205   },
10206
10207   /* VEX_LEN_0F3A6A_P_2 */
10208   {
10209     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10210   },
10211
10212   /* VEX_LEN_0F3A6B_P_2 */
10213   {
10214     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10215   },
10216
10217   /* VEX_LEN_0F3A6E_P_2 */
10218   {
10219     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10220   },
10221
10222   /* VEX_LEN_0F3A6F_P_2 */
10223   {
10224     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10225   },
10226
10227   /* VEX_LEN_0F3A7A_P_2 */
10228   {
10229     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10230   },
10231
10232   /* VEX_LEN_0F3A7B_P_2 */
10233   {
10234     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10235   },
10236
10237   /* VEX_LEN_0F3A7E_P_2 */
10238   {
10239     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10240   },
10241
10242   /* VEX_LEN_0F3A7F_P_2 */
10243   {
10244     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10245   },
10246
10247   /* VEX_LEN_0F3ADF_P_2 */
10248   {
10249     { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10250   },
10251
10252   /* VEX_LEN_0F3AF0_P_3 */
10253   {
10254     { "rorxS",          { Gdq, Edq, Ib }, 0 },
10255   },
10256
10257   /* VEX_LEN_0FXOP_08_CC */
10258   {
10259      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
10260   },
10261
10262   /* VEX_LEN_0FXOP_08_CD */
10263   {
10264      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
10265   },
10266
10267   /* VEX_LEN_0FXOP_08_CE */
10268   {
10269      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
10270   },
10271
10272   /* VEX_LEN_0FXOP_08_CF */
10273   {
10274      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
10275   },
10276
10277   /* VEX_LEN_0FXOP_08_EC */
10278   {
10279      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
10280   },
10281
10282   /* VEX_LEN_0FXOP_08_ED */
10283   {
10284      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
10285   },
10286
10287   /* VEX_LEN_0FXOP_08_EE */
10288   {
10289      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
10290   },
10291
10292   /* VEX_LEN_0FXOP_08_EF */
10293   {
10294      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
10295   },
10296
10297   /* VEX_LEN_0FXOP_09_80 */
10298   {
10299     { "vfrczps",        { XM, EXxmm }, 0 },
10300     { "vfrczps",        { XM, EXymmq }, 0 },
10301   },
10302
10303   /* VEX_LEN_0FXOP_09_81 */
10304   {
10305     { "vfrczpd",        { XM, EXxmm }, 0 },
10306     { "vfrczpd",        { XM, EXymmq }, 0 },
10307   },
10308 };
10309
10310 static const struct dis386 vex_w_table[][2] = {
10311   {
10312     /* VEX_W_0F10_P_0 */
10313     { "vmovups",        { XM, EXx }, 0 },
10314   },
10315   {
10316     /* VEX_W_0F10_P_1 */
10317     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
10318   },
10319   {
10320     /* VEX_W_0F10_P_2 */
10321     { "vmovupd",        { XM, EXx }, 0 },
10322   },
10323   {
10324     /* VEX_W_0F10_P_3 */
10325     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
10326   },
10327   {
10328     /* VEX_W_0F11_P_0 */
10329     { "vmovups",        { EXxS, XM }, 0 },
10330   },
10331   {
10332     /* VEX_W_0F11_P_1 */
10333     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10334   },
10335   {
10336     /* VEX_W_0F11_P_2 */
10337     { "vmovupd",        { EXxS, XM }, 0 },
10338   },
10339   {
10340     /* VEX_W_0F11_P_3 */
10341     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10342   },
10343   {
10344     /* VEX_W_0F12_P_0_M_0 */
10345     { "vmovlps",        { XM, Vex128, EXq }, 0 },
10346   },
10347   {
10348     /* VEX_W_0F12_P_0_M_1 */
10349     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
10350   },
10351   {
10352     /* VEX_W_0F12_P_1 */
10353     { "vmovsldup",      { XM, EXx }, 0 },
10354   },
10355   {
10356     /* VEX_W_0F12_P_2 */
10357     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
10358   },
10359   {
10360     /* VEX_W_0F12_P_3 */
10361     { "vmovddup",       { XM, EXymmq }, 0 },
10362   },
10363   {
10364     /* VEX_W_0F13_M_0 */
10365     { "vmovlpX",        { EXq, XM }, 0 },
10366   },
10367   {
10368     /* VEX_W_0F14 */
10369     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
10370   },
10371   {
10372     /* VEX_W_0F15 */
10373     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
10374   },
10375   {
10376     /* VEX_W_0F16_P_0_M_0 */
10377     { "vmovhps",        { XM, Vex128, EXq }, 0 },
10378   },
10379   {
10380     /* VEX_W_0F16_P_0_M_1 */
10381     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
10382   },
10383   {
10384     /* VEX_W_0F16_P_1 */
10385     { "vmovshdup",      { XM, EXx }, 0 },
10386   },
10387   {
10388     /* VEX_W_0F16_P_2 */
10389     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
10390   },
10391   {
10392     /* VEX_W_0F17_M_0 */
10393     { "vmovhpX",        { EXq, XM }, 0 },
10394   },
10395   {
10396     /* VEX_W_0F28 */
10397     { "vmovapX",        { XM, EXx }, 0 },
10398   },
10399   {
10400     /* VEX_W_0F29 */
10401     { "vmovapX",        { EXxS, XM }, 0 },
10402   },
10403   {
10404     /* VEX_W_0F2B_M_0 */
10405     { "vmovntpX",       { Mx, XM }, 0 },
10406   },
10407   {
10408     /* VEX_W_0F2E_P_0 */
10409     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
10410   },
10411   {
10412     /* VEX_W_0F2E_P_2 */
10413     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
10414   },
10415   {
10416     /* VEX_W_0F2F_P_0 */
10417     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
10418   },
10419   {
10420     /* VEX_W_0F2F_P_2 */
10421     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
10422   },
10423   {
10424     /* VEX_W_0F41_P_0_LEN_1 */
10425     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10426     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10427   },
10428   {
10429     /* VEX_W_0F41_P_2_LEN_1 */
10430     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10431     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10432   },
10433   {
10434     /* VEX_W_0F42_P_0_LEN_1 */
10435     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10436     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10437   },
10438   {
10439     /* VEX_W_0F42_P_2_LEN_1 */
10440     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10441     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10442   },
10443   {
10444     /* VEX_W_0F44_P_0_LEN_0 */
10445     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10446     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10447   },
10448   {
10449     /* VEX_W_0F44_P_2_LEN_0 */
10450     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10451     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10452   },
10453   {
10454     /* VEX_W_0F45_P_0_LEN_1 */
10455     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10456     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10457   },
10458   {
10459     /* VEX_W_0F45_P_2_LEN_1 */
10460     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10461     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10462   },
10463   {
10464     /* VEX_W_0F46_P_0_LEN_1 */
10465     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10466     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10467   },
10468   {
10469     /* VEX_W_0F46_P_2_LEN_1 */
10470     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10471     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10472   },
10473   {
10474     /* VEX_W_0F47_P_0_LEN_1 */
10475     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10476     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10477   },
10478   {
10479     /* VEX_W_0F47_P_2_LEN_1 */
10480     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10481     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10482   },
10483   {
10484     /* VEX_W_0F4A_P_0_LEN_1 */
10485     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10486     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10487   },
10488   {
10489     /* VEX_W_0F4A_P_2_LEN_1 */
10490     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10491     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10492   },
10493   {
10494     /* VEX_W_0F4B_P_0_LEN_1 */
10495     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10496     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10497   },
10498   {
10499     /* VEX_W_0F4B_P_2_LEN_1 */
10500     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10501   },
10502   {
10503     /* VEX_W_0F50_M_0 */
10504     { "vmovmskpX",      { Gdq, XS }, 0 },
10505   },
10506   {
10507     /* VEX_W_0F51_P_0 */
10508     { "vsqrtps",        { XM, EXx }, 0 },
10509   },
10510   {
10511     /* VEX_W_0F51_P_1 */
10512     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
10513   },
10514   {
10515     /* VEX_W_0F51_P_2  */
10516     { "vsqrtpd",        { XM, EXx }, 0 },
10517   },
10518   {
10519     /* VEX_W_0F51_P_3 */
10520     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
10521   },
10522   {
10523     /* VEX_W_0F52_P_0 */
10524     { "vrsqrtps",       { XM, EXx }, 0 },
10525   },
10526   {
10527     /* VEX_W_0F52_P_1 */
10528     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
10529   },
10530   {
10531     /* VEX_W_0F53_P_0  */
10532     { "vrcpps",         { XM, EXx }, 0 },
10533   },
10534   {
10535     /* VEX_W_0F53_P_1  */
10536     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10537   },
10538   {
10539     /* VEX_W_0F58_P_0  */
10540     { "vaddps",         { XM, Vex, EXx }, 0 },
10541   },
10542   {
10543     /* VEX_W_0F58_P_1  */
10544     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10545   },
10546   {
10547     /* VEX_W_0F58_P_2  */
10548     { "vaddpd",         { XM, Vex, EXx }, 0 },
10549   },
10550   {
10551     /* VEX_W_0F58_P_3  */
10552     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10553   },
10554   {
10555     /* VEX_W_0F59_P_0  */
10556     { "vmulps",         { XM, Vex, EXx }, 0 },
10557   },
10558   {
10559     /* VEX_W_0F59_P_1  */
10560     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10561   },
10562   {
10563     /* VEX_W_0F59_P_2  */
10564     { "vmulpd",         { XM, Vex, EXx }, 0 },
10565   },
10566   {
10567     /* VEX_W_0F59_P_3  */
10568     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10569   },
10570   {
10571     /* VEX_W_0F5A_P_0  */
10572     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
10573   },
10574   {
10575     /* VEX_W_0F5A_P_1  */
10576     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
10577   },
10578   {
10579     /* VEX_W_0F5A_P_3  */
10580     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
10581   },
10582   {
10583     /* VEX_W_0F5B_P_0  */
10584     { "vcvtdq2ps",      { XM, EXx }, 0 },
10585   },
10586   {
10587     /* VEX_W_0F5B_P_1  */
10588     { "vcvttps2dq",     { XM, EXx }, 0 },
10589   },
10590   {
10591     /* VEX_W_0F5B_P_2  */
10592     { "vcvtps2dq",      { XM, EXx }, 0 },
10593   },
10594   {
10595     /* VEX_W_0F5C_P_0  */
10596     { "vsubps",         { XM, Vex, EXx }, 0 },
10597   },
10598   {
10599     /* VEX_W_0F5C_P_1  */
10600     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10601   },
10602   {
10603     /* VEX_W_0F5C_P_2  */
10604     { "vsubpd",         { XM, Vex, EXx }, 0 },
10605   },
10606   {
10607     /* VEX_W_0F5C_P_3  */
10608     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10609   },
10610   {
10611     /* VEX_W_0F5D_P_0  */
10612     { "vminps",         { XM, Vex, EXx }, 0 },
10613   },
10614   {
10615     /* VEX_W_0F5D_P_1  */
10616     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10617   },
10618   {
10619     /* VEX_W_0F5D_P_2  */
10620     { "vminpd",         { XM, Vex, EXx }, 0 },
10621   },
10622   {
10623     /* VEX_W_0F5D_P_3  */
10624     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10625   },
10626   {
10627     /* VEX_W_0F5E_P_0  */
10628     { "vdivps",         { XM, Vex, EXx }, 0 },
10629   },
10630   {
10631     /* VEX_W_0F5E_P_1  */
10632     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10633   },
10634   {
10635     /* VEX_W_0F5E_P_2  */
10636     { "vdivpd",         { XM, Vex, EXx }, 0 },
10637   },
10638   {
10639     /* VEX_W_0F5E_P_3  */
10640     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10641   },
10642   {
10643     /* VEX_W_0F5F_P_0  */
10644     { "vmaxps",         { XM, Vex, EXx }, 0 },
10645   },
10646   {
10647     /* VEX_W_0F5F_P_1  */
10648     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
10649   },
10650   {
10651     /* VEX_W_0F5F_P_2  */
10652     { "vmaxpd",         { XM, Vex, EXx }, 0 },
10653   },
10654   {
10655     /* VEX_W_0F5F_P_3  */
10656     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
10657   },
10658   {
10659     /* VEX_W_0F60_P_2  */
10660     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
10661   },
10662   {
10663     /* VEX_W_0F61_P_2  */
10664     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
10665   },
10666   {
10667     /* VEX_W_0F62_P_2  */
10668     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
10669   },
10670   {
10671     /* VEX_W_0F63_P_2  */
10672     { "vpacksswb",      { XM, Vex, EXx }, 0 },
10673   },
10674   {
10675     /* VEX_W_0F64_P_2  */
10676     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
10677   },
10678   {
10679     /* VEX_W_0F65_P_2  */
10680     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
10681   },
10682   {
10683     /* VEX_W_0F66_P_2  */
10684     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
10685   },
10686   {
10687     /* VEX_W_0F67_P_2  */
10688     { "vpackuswb",      { XM, Vex, EXx }, 0 },
10689   },
10690   {
10691     /* VEX_W_0F68_P_2  */
10692     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
10693   },
10694   {
10695     /* VEX_W_0F69_P_2  */
10696     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
10697   },
10698   {
10699     /* VEX_W_0F6A_P_2  */
10700     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
10701   },
10702   {
10703     /* VEX_W_0F6B_P_2  */
10704     { "vpackssdw",      { XM, Vex, EXx }, 0 },
10705   },
10706   {
10707     /* VEX_W_0F6C_P_2  */
10708     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
10709   },
10710   {
10711     /* VEX_W_0F6D_P_2  */
10712     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
10713   },
10714   {
10715     /* VEX_W_0F6F_P_1  */
10716     { "vmovdqu",        { XM, EXx }, 0 },
10717   },
10718   {
10719     /* VEX_W_0F6F_P_2  */
10720     { "vmovdqa",        { XM, EXx }, 0 },
10721   },
10722   {
10723     /* VEX_W_0F70_P_1 */
10724     { "vpshufhw",       { XM, EXx, Ib }, 0 },
10725   },
10726   {
10727     /* VEX_W_0F70_P_2 */
10728     { "vpshufd",        { XM, EXx, Ib }, 0 },
10729   },
10730   {
10731     /* VEX_W_0F70_P_3 */
10732     { "vpshuflw",       { XM, EXx, Ib }, 0 },
10733   },
10734   {
10735     /* VEX_W_0F71_R_2_P_2  */
10736     { "vpsrlw",         { Vex, XS, Ib }, 0 },
10737   },
10738   {
10739     /* VEX_W_0F71_R_4_P_2  */
10740     { "vpsraw",         { Vex, XS, Ib }, 0 },
10741   },
10742   {
10743     /* VEX_W_0F71_R_6_P_2  */
10744     { "vpsllw",         { Vex, XS, Ib }, 0 },
10745   },
10746   {
10747     /* VEX_W_0F72_R_2_P_2  */
10748     { "vpsrld",         { Vex, XS, Ib }, 0 },
10749   },
10750   {
10751     /* VEX_W_0F72_R_4_P_2  */
10752     { "vpsrad",         { Vex, XS, Ib }, 0 },
10753   },
10754   {
10755     /* VEX_W_0F72_R_6_P_2  */
10756     { "vpslld",         { Vex, XS, Ib }, 0 },
10757   },
10758   {
10759     /* VEX_W_0F73_R_2_P_2  */
10760     { "vpsrlq",         { Vex, XS, Ib }, 0 },
10761   },
10762   {
10763     /* VEX_W_0F73_R_3_P_2  */
10764     { "vpsrldq",        { Vex, XS, Ib }, 0 },
10765   },
10766   {
10767     /* VEX_W_0F73_R_6_P_2  */
10768     { "vpsllq",         { Vex, XS, Ib }, 0 },
10769   },
10770   {
10771     /* VEX_W_0F73_R_7_P_2  */
10772     { "vpslldq",        { Vex, XS, Ib }, 0 },
10773   },
10774   {
10775     /* VEX_W_0F74_P_2 */
10776     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
10777   },
10778   {
10779     /* VEX_W_0F75_P_2 */
10780     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
10781   },
10782   {
10783     /* VEX_W_0F76_P_2 */
10784     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
10785   },
10786   {
10787     /* VEX_W_0F77_P_0 */
10788     { "",               { VZERO }, 0 },
10789   },
10790   {
10791     /* VEX_W_0F7C_P_2 */
10792     { "vhaddpd",        { XM, Vex, EXx }, 0 },
10793   },
10794   {
10795     /* VEX_W_0F7C_P_3 */
10796     { "vhaddps",        { XM, Vex, EXx }, 0 },
10797   },
10798   {
10799     /* VEX_W_0F7D_P_2 */
10800     { "vhsubpd",        { XM, Vex, EXx }, 0 },
10801   },
10802   {
10803     /* VEX_W_0F7D_P_3 */
10804     { "vhsubps",        { XM, Vex, EXx }, 0 },
10805   },
10806   {
10807     /* VEX_W_0F7E_P_1 */
10808     { "vmovq",          { XMScalar, EXqScalar }, 0 },
10809   },
10810   {
10811     /* VEX_W_0F7F_P_1 */
10812     { "vmovdqu",        { EXxS, XM }, 0 },
10813   },
10814   {
10815     /* VEX_W_0F7F_P_2 */
10816     { "vmovdqa",        { EXxS, XM }, 0 },
10817   },
10818   {
10819     /* VEX_W_0F90_P_0_LEN_0 */
10820     { "kmovw",          { MaskG, MaskE }, 0 },
10821     { "kmovq",          { MaskG, MaskE }, 0 },
10822   },
10823   {
10824     /* VEX_W_0F90_P_2_LEN_0 */
10825     { "kmovb",          { MaskG, MaskBDE }, 0 },
10826     { "kmovd",          { MaskG, MaskBDE }, 0 },
10827   },
10828   {
10829     /* VEX_W_0F91_P_0_LEN_0 */
10830     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10831     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10832   },
10833   {
10834     /* VEX_W_0F91_P_2_LEN_0 */
10835     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10836     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10837   },
10838   {
10839     /* VEX_W_0F92_P_0_LEN_0 */
10840     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10841   },
10842   {
10843     /* VEX_W_0F92_P_2_LEN_0 */
10844     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10845   },
10846   {
10847     /* VEX_W_0F92_P_3_LEN_0 */
10848     { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10849     { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10850   },
10851   {
10852     /* VEX_W_0F93_P_0_LEN_0 */
10853     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10854   },
10855   {
10856     /* VEX_W_0F93_P_2_LEN_0 */
10857     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10858   },
10859   {
10860     /* VEX_W_0F93_P_3_LEN_0 */
10861     { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10862     { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10863   },
10864   {
10865     /* VEX_W_0F98_P_0_LEN_0 */
10866     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10867     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10868   },
10869   {
10870     /* VEX_W_0F98_P_2_LEN_0 */
10871     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10872     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10873   },
10874   {
10875     /* VEX_W_0F99_P_0_LEN_0 */
10876     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10877     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10878   },
10879   {
10880     /* VEX_W_0F99_P_2_LEN_0 */
10881     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10882     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10883   },
10884   {
10885     /* VEX_W_0FAE_R_2_M_0 */
10886     { "vldmxcsr",       { Md }, 0 },
10887   },
10888   {
10889     /* VEX_W_0FAE_R_3_M_0 */
10890     { "vstmxcsr",       { Md }, 0 },
10891   },
10892   {
10893     /* VEX_W_0FC2_P_0 */
10894     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
10895   },
10896   {
10897     /* VEX_W_0FC2_P_1 */
10898     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10899   },
10900   {
10901     /* VEX_W_0FC2_P_2 */
10902     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
10903   },
10904   {
10905     /* VEX_W_0FC2_P_3 */
10906     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10907   },
10908   {
10909     /* VEX_W_0FC4_P_2 */
10910     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
10911   },
10912   {
10913     /* VEX_W_0FC5_P_2 */
10914     { "vpextrw",        { Gdq, XS, Ib }, 0 },
10915   },
10916   {
10917     /* VEX_W_0FD0_P_2 */
10918     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
10919   },
10920   {
10921     /* VEX_W_0FD0_P_3 */
10922     { "vaddsubps",      { XM, Vex, EXx }, 0 },
10923   },
10924   {
10925     /* VEX_W_0FD1_P_2 */
10926     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
10927   },
10928   {
10929     /* VEX_W_0FD2_P_2 */
10930     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
10931   },
10932   {
10933     /* VEX_W_0FD3_P_2 */
10934     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
10935   },
10936   {
10937     /* VEX_W_0FD4_P_2 */
10938     { "vpaddq",         { XM, Vex, EXx }, 0 },
10939   },
10940   {
10941     /* VEX_W_0FD5_P_2 */
10942     { "vpmullw",        { XM, Vex, EXx }, 0 },
10943   },
10944   {
10945     /* VEX_W_0FD6_P_2 */
10946     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
10947   },
10948   {
10949     /* VEX_W_0FD7_P_2_M_1 */
10950     { "vpmovmskb",      { Gdq, XS }, 0 },
10951   },
10952   {
10953     /* VEX_W_0FD8_P_2 */
10954     { "vpsubusb",       { XM, Vex, EXx }, 0 },
10955   },
10956   {
10957     /* VEX_W_0FD9_P_2 */
10958     { "vpsubusw",       { XM, Vex, EXx }, 0 },
10959   },
10960   {
10961     /* VEX_W_0FDA_P_2 */
10962     { "vpminub",        { XM, Vex, EXx }, 0 },
10963   },
10964   {
10965     /* VEX_W_0FDB_P_2 */
10966     { "vpand",          { XM, Vex, EXx }, 0 },
10967   },
10968   {
10969     /* VEX_W_0FDC_P_2 */
10970     { "vpaddusb",       { XM, Vex, EXx }, 0 },
10971   },
10972   {
10973     /* VEX_W_0FDD_P_2 */
10974     { "vpaddusw",       { XM, Vex, EXx }, 0 },
10975   },
10976   {
10977     /* VEX_W_0FDE_P_2 */
10978     { "vpmaxub",        { XM, Vex, EXx }, 0 },
10979   },
10980   {
10981     /* VEX_W_0FDF_P_2 */
10982     { "vpandn",         { XM, Vex, EXx }, 0 },
10983   },
10984   {
10985     /* VEX_W_0FE0_P_2  */
10986     { "vpavgb",         { XM, Vex, EXx }, 0 },
10987   },
10988   {
10989     /* VEX_W_0FE1_P_2  */
10990     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
10991   },
10992   {
10993     /* VEX_W_0FE2_P_2  */
10994     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
10995   },
10996   {
10997     /* VEX_W_0FE3_P_2  */
10998     { "vpavgw",         { XM, Vex, EXx }, 0 },
10999   },
11000   {
11001     /* VEX_W_0FE4_P_2  */
11002     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
11003   },
11004   {
11005     /* VEX_W_0FE5_P_2  */
11006     { "vpmulhw",        { XM, Vex, EXx }, 0 },
11007   },
11008   {
11009     /* VEX_W_0FE6_P_1  */
11010     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
11011   },
11012   {
11013     /* VEX_W_0FE6_P_2  */
11014     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
11015   },
11016   {
11017     /* VEX_W_0FE6_P_3  */
11018     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
11019   },
11020   {
11021     /* VEX_W_0FE7_P_2_M_0 */
11022     { "vmovntdq",       { Mx, XM }, 0 },
11023   },
11024   {
11025     /* VEX_W_0FE8_P_2  */
11026     { "vpsubsb",        { XM, Vex, EXx }, 0 },
11027   },
11028   {
11029     /* VEX_W_0FE9_P_2  */
11030     { "vpsubsw",        { XM, Vex, EXx }, 0 },
11031   },
11032   {
11033     /* VEX_W_0FEA_P_2  */
11034     { "vpminsw",        { XM, Vex, EXx }, 0 },
11035   },
11036   {
11037     /* VEX_W_0FEB_P_2  */
11038     { "vpor",           { XM, Vex, EXx }, 0 },
11039   },
11040   {
11041     /* VEX_W_0FEC_P_2  */
11042     { "vpaddsb",        { XM, Vex, EXx }, 0 },
11043   },
11044   {
11045     /* VEX_W_0FED_P_2  */
11046     { "vpaddsw",        { XM, Vex, EXx }, 0 },
11047   },
11048   {
11049     /* VEX_W_0FEE_P_2  */
11050     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
11051   },
11052   {
11053     /* VEX_W_0FEF_P_2  */
11054     { "vpxor",          { XM, Vex, EXx }, 0 },
11055   },
11056   {
11057     /* VEX_W_0FF0_P_3_M_0 */
11058     { "vlddqu",         { XM, M }, 0 },
11059   },
11060   {
11061     /* VEX_W_0FF1_P_2 */
11062     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
11063   },
11064   {
11065     /* VEX_W_0FF2_P_2 */
11066     { "vpslld",         { XM, Vex, EXxmm }, 0 },
11067   },
11068   {
11069     /* VEX_W_0FF3_P_2 */
11070     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
11071   },
11072   {
11073     /* VEX_W_0FF4_P_2 */
11074     { "vpmuludq",       { XM, Vex, EXx }, 0 },
11075   },
11076   {
11077     /* VEX_W_0FF5_P_2 */
11078     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
11079   },
11080   {
11081     /* VEX_W_0FF6_P_2 */
11082     { "vpsadbw",        { XM, Vex, EXx }, 0 },
11083   },
11084   {
11085     /* VEX_W_0FF7_P_2 */
11086     { "vmaskmovdqu",    { XM, XS }, 0 },
11087   },
11088   {
11089     /* VEX_W_0FF8_P_2 */
11090     { "vpsubb",         { XM, Vex, EXx }, 0 },
11091   },
11092   {
11093     /* VEX_W_0FF9_P_2 */
11094     { "vpsubw",         { XM, Vex, EXx }, 0 },
11095   },
11096   {
11097     /* VEX_W_0FFA_P_2 */
11098     { "vpsubd",         { XM, Vex, EXx }, 0 },
11099   },
11100   {
11101     /* VEX_W_0FFB_P_2 */
11102     { "vpsubq",         { XM, Vex, EXx }, 0 },
11103   },
11104   {
11105     /* VEX_W_0FFC_P_2 */
11106     { "vpaddb",         { XM, Vex, EXx }, 0 },
11107   },
11108   {
11109     /* VEX_W_0FFD_P_2 */
11110     { "vpaddw",         { XM, Vex, EXx }, 0 },
11111   },
11112   {
11113     /* VEX_W_0FFE_P_2 */
11114     { "vpaddd",         { XM, Vex, EXx }, 0 },
11115   },
11116   {
11117     /* VEX_W_0F3800_P_2  */
11118     { "vpshufb",        { XM, Vex, EXx }, 0 },
11119   },
11120   {
11121     /* VEX_W_0F3801_P_2  */
11122     { "vphaddw",        { XM, Vex, EXx }, 0 },
11123   },
11124   {
11125     /* VEX_W_0F3802_P_2  */
11126     { "vphaddd",        { XM, Vex, EXx }, 0 },
11127   },
11128   {
11129     /* VEX_W_0F3803_P_2  */
11130     { "vphaddsw",       { XM, Vex, EXx }, 0 },
11131   },
11132   {
11133     /* VEX_W_0F3804_P_2  */
11134     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
11135   },
11136   {
11137     /* VEX_W_0F3805_P_2  */
11138     { "vphsubw",        { XM, Vex, EXx }, 0 },
11139   },
11140   {
11141     /* VEX_W_0F3806_P_2  */
11142     { "vphsubd",        { XM, Vex, EXx }, 0 },
11143   },
11144   {
11145     /* VEX_W_0F3807_P_2  */
11146     { "vphsubsw",       { XM, Vex, EXx }, 0 },
11147   },
11148   {
11149     /* VEX_W_0F3808_P_2  */
11150     { "vpsignb",        { XM, Vex, EXx }, 0 },
11151   },
11152   {
11153     /* VEX_W_0F3809_P_2  */
11154     { "vpsignw",        { XM, Vex, EXx }, 0 },
11155   },
11156   {
11157     /* VEX_W_0F380A_P_2  */
11158     { "vpsignd",        { XM, Vex, EXx }, 0 },
11159   },
11160   {
11161     /* VEX_W_0F380B_P_2  */
11162     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
11163   },
11164   {
11165     /* VEX_W_0F380C_P_2  */
11166     { "vpermilps",      { XM, Vex, EXx }, 0 },
11167   },
11168   {
11169     /* VEX_W_0F380D_P_2  */
11170     { "vpermilpd",      { XM, Vex, EXx }, 0 },
11171   },
11172   {
11173     /* VEX_W_0F380E_P_2  */
11174     { "vtestps",        { XM, EXx }, 0 },
11175   },
11176   {
11177     /* VEX_W_0F380F_P_2  */
11178     { "vtestpd",        { XM, EXx }, 0 },
11179   },
11180   {
11181     /* VEX_W_0F3816_P_2  */
11182     { "vpermps",        { XM, Vex, EXx }, 0 },
11183   },
11184   {
11185     /* VEX_W_0F3817_P_2 */
11186     { "vptest",         { XM, EXx }, 0 },
11187   },
11188   {
11189     /* VEX_W_0F3818_P_2 */
11190     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
11191   },
11192   {
11193     /* VEX_W_0F3819_P_2 */
11194     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
11195   },
11196   {
11197     /* VEX_W_0F381A_P_2_M_0 */
11198     { "vbroadcastf128", { XM, Mxmm }, 0 },
11199   },
11200   {
11201     /* VEX_W_0F381C_P_2 */
11202     { "vpabsb",         { XM, EXx }, 0 },
11203   },
11204   {
11205     /* VEX_W_0F381D_P_2 */
11206     { "vpabsw",         { XM, EXx }, 0 },
11207   },
11208   {
11209     /* VEX_W_0F381E_P_2 */
11210     { "vpabsd",         { XM, EXx }, 0 },
11211   },
11212   {
11213     /* VEX_W_0F3820_P_2 */
11214     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
11215   },
11216   {
11217     /* VEX_W_0F3821_P_2 */
11218     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
11219   },
11220   {
11221     /* VEX_W_0F3822_P_2 */
11222     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
11223   },
11224   {
11225     /* VEX_W_0F3823_P_2 */
11226     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
11227   },
11228   {
11229     /* VEX_W_0F3824_P_2 */
11230     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
11231   },
11232   {
11233     /* VEX_W_0F3825_P_2 */
11234     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
11235   },
11236   {
11237     /* VEX_W_0F3828_P_2 */
11238     { "vpmuldq",        { XM, Vex, EXx }, 0 },
11239   },
11240   {
11241     /* VEX_W_0F3829_P_2 */
11242     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
11243   },
11244   {
11245     /* VEX_W_0F382A_P_2_M_0 */
11246     { "vmovntdqa",      { XM, Mx }, 0 },
11247   },
11248   {
11249     /* VEX_W_0F382B_P_2 */
11250     { "vpackusdw",      { XM, Vex, EXx }, 0 },
11251   },
11252   {
11253     /* VEX_W_0F382C_P_2_M_0 */
11254     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
11255   },
11256   {
11257     /* VEX_W_0F382D_P_2_M_0 */
11258     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
11259   },
11260   {
11261     /* VEX_W_0F382E_P_2_M_0 */
11262     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
11263   },
11264   {
11265     /* VEX_W_0F382F_P_2_M_0 */
11266     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
11267   },
11268   {
11269     /* VEX_W_0F3830_P_2 */
11270     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
11271   },
11272   {
11273     /* VEX_W_0F3831_P_2 */
11274     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
11275   },
11276   {
11277     /* VEX_W_0F3832_P_2 */
11278     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
11279   },
11280   {
11281     /* VEX_W_0F3833_P_2 */
11282     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
11283   },
11284   {
11285     /* VEX_W_0F3834_P_2 */
11286     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
11287   },
11288   {
11289     /* VEX_W_0F3835_P_2 */
11290     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
11291   },
11292   {
11293     /* VEX_W_0F3836_P_2  */
11294     { "vpermd",         { XM, Vex, EXx }, 0 },
11295   },
11296   {
11297     /* VEX_W_0F3837_P_2 */
11298     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
11299   },
11300   {
11301     /* VEX_W_0F3838_P_2 */
11302     { "vpminsb",        { XM, Vex, EXx }, 0 },
11303   },
11304   {
11305     /* VEX_W_0F3839_P_2 */
11306     { "vpminsd",        { XM, Vex, EXx }, 0 },
11307   },
11308   {
11309     /* VEX_W_0F383A_P_2 */
11310     { "vpminuw",        { XM, Vex, EXx }, 0 },
11311   },
11312   {
11313     /* VEX_W_0F383B_P_2 */
11314     { "vpminud",        { XM, Vex, EXx }, 0 },
11315   },
11316   {
11317     /* VEX_W_0F383C_P_2 */
11318     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
11319   },
11320   {
11321     /* VEX_W_0F383D_P_2 */
11322     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
11323   },
11324   {
11325     /* VEX_W_0F383E_P_2 */
11326     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
11327   },
11328   {
11329     /* VEX_W_0F383F_P_2 */
11330     { "vpmaxud",        { XM, Vex, EXx }, 0 },
11331   },
11332   {
11333     /* VEX_W_0F3840_P_2 */
11334     { "vpmulld",        { XM, Vex, EXx }, 0 },
11335   },
11336   {
11337     /* VEX_W_0F3841_P_2 */
11338     { "vphminposuw",    { XM, EXx }, 0 },
11339   },
11340   {
11341     /* VEX_W_0F3846_P_2 */
11342     { "vpsravd",        { XM, Vex, EXx }, 0 },
11343   },
11344   {
11345     /* VEX_W_0F3858_P_2 */
11346     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11347   },
11348   {
11349     /* VEX_W_0F3859_P_2 */
11350     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
11351   },
11352   {
11353     /* VEX_W_0F385A_P_2_M_0 */
11354     { "vbroadcasti128", { XM, Mxmm }, 0 },
11355   },
11356   {
11357     /* VEX_W_0F3878_P_2 */
11358     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
11359   },
11360   {
11361     /* VEX_W_0F3879_P_2 */
11362     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
11363   },
11364   {
11365     /* VEX_W_0F38CF_P_2 */
11366     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11367   },
11368   {
11369     /* VEX_W_0F38DB_P_2 */
11370     { "vaesimc",        { XM, EXx }, 0 },
11371   },
11372   {
11373     /* VEX_W_0F3A00_P_2 */
11374     { Bad_Opcode },
11375     { "vpermq",         { XM, EXx, Ib }, 0 },
11376   },
11377   {
11378     /* VEX_W_0F3A01_P_2 */
11379     { Bad_Opcode },
11380     { "vpermpd",        { XM, EXx, Ib }, 0 },
11381   },
11382   {
11383     /* VEX_W_0F3A02_P_2 */
11384     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
11385   },
11386   {
11387     /* VEX_W_0F3A04_P_2 */
11388     { "vpermilps",      { XM, EXx, Ib }, 0 },
11389   },
11390   {
11391     /* VEX_W_0F3A05_P_2 */
11392     { "vpermilpd",      { XM, EXx, Ib }, 0 },
11393   },
11394   {
11395     /* VEX_W_0F3A06_P_2 */
11396     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
11397   },
11398   {
11399     /* VEX_W_0F3A08_P_2 */
11400     { "vroundps",       { XM, EXx, Ib }, 0 },
11401   },
11402   {
11403     /* VEX_W_0F3A09_P_2 */
11404     { "vroundpd",       { XM, EXx, Ib }, 0 },
11405   },
11406   {
11407     /* VEX_W_0F3A0A_P_2 */
11408     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11409   },
11410   {
11411     /* VEX_W_0F3A0B_P_2 */
11412     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11413   },
11414   {
11415     /* VEX_W_0F3A0C_P_2 */
11416     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
11417   },
11418   {
11419     /* VEX_W_0F3A0D_P_2 */
11420     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
11421   },
11422   {
11423     /* VEX_W_0F3A0E_P_2 */
11424     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
11425   },
11426   {
11427     /* VEX_W_0F3A0F_P_2 */
11428     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
11429   },
11430   {
11431     /* VEX_W_0F3A14_P_2 */
11432     { "vpextrb",        { Edqb, XM, Ib }, 0 },
11433   },
11434   {
11435     /* VEX_W_0F3A15_P_2 */
11436     { "vpextrw",        { Edqw, XM, Ib }, 0 },
11437   },
11438   {
11439     /* VEX_W_0F3A18_P_2 */
11440     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
11441   },
11442   {
11443     /* VEX_W_0F3A19_P_2 */
11444     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
11445   },
11446   {
11447     /* VEX_W_0F3A20_P_2 */
11448     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
11449   },
11450   {
11451     /* VEX_W_0F3A21_P_2 */
11452     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
11453   },
11454   {
11455     /* VEX_W_0F3A30_P_2_LEN_0 */
11456     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11457     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11458   },
11459   {
11460     /* VEX_W_0F3A31_P_2_LEN_0 */
11461     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11462     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11463   },
11464   {
11465     /* VEX_W_0F3A32_P_2_LEN_0 */
11466     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11467     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11468   },
11469   {
11470     /* VEX_W_0F3A33_P_2_LEN_0 */
11471     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11472     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11473   },
11474   {
11475     /* VEX_W_0F3A38_P_2 */
11476     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
11477   },
11478   {
11479     /* VEX_W_0F3A39_P_2 */
11480     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
11481   },
11482   {
11483     /* VEX_W_0F3A40_P_2 */
11484     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
11485   },
11486   {
11487     /* VEX_W_0F3A41_P_2 */
11488     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
11489   },
11490   {
11491     /* VEX_W_0F3A42_P_2 */
11492     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
11493   },
11494   {
11495     /* VEX_W_0F3A46_P_2 */
11496     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
11497   },
11498   {
11499     /* VEX_W_0F3A48_P_2 */
11500     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11501     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11502   },
11503   {
11504     /* VEX_W_0F3A49_P_2 */
11505     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11506     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11507   },
11508   {
11509     /* VEX_W_0F3A4A_P_2 */
11510     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
11511   },
11512   {
11513     /* VEX_W_0F3A4B_P_2 */
11514     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
11515   },
11516   {
11517     /* VEX_W_0F3A4C_P_2 */
11518     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
11519   },
11520   {
11521     /* VEX_W_0F3A62_P_2 */
11522     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
11523   },
11524   {
11525     /* VEX_W_0F3A63_P_2 */
11526     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
11527   },
11528   {
11529     /* VEX_W_0F3ACE_P_2 */
11530     { Bad_Opcode },
11531     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11532   },
11533   {
11534     /* VEX_W_0F3ACF_P_2 */
11535     { Bad_Opcode },
11536     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
11537   },
11538   {
11539     /* VEX_W_0F3ADF_P_2 */
11540     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11541   },
11542 #define NEED_VEX_W_TABLE
11543 #include "i386-dis-evex.h"
11544 #undef NEED_VEX_W_TABLE
11545 };
11546
11547 static const struct dis386 mod_table[][2] = {
11548   {
11549     /* MOD_8D */
11550     { "leaS",           { Gv, M }, 0 },
11551   },
11552   {
11553     /* MOD_C6_REG_7 */
11554     { Bad_Opcode },
11555     { RM_TABLE (RM_C6_REG_7) },
11556   },
11557   {
11558     /* MOD_C7_REG_7 */
11559     { Bad_Opcode },
11560     { RM_TABLE (RM_C7_REG_7) },
11561   },
11562   {
11563     /* MOD_FF_REG_3 */
11564     { "Jcall^", { indirEp }, 0 },
11565   },
11566   {
11567     /* MOD_FF_REG_5 */
11568     { "Jjmp^", { indirEp }, 0 },
11569   },
11570   {
11571     /* MOD_0F01_REG_0 */
11572     { X86_64_TABLE (X86_64_0F01_REG_0) },
11573     { RM_TABLE (RM_0F01_REG_0) },
11574   },
11575   {
11576     /* MOD_0F01_REG_1 */
11577     { X86_64_TABLE (X86_64_0F01_REG_1) },
11578     { RM_TABLE (RM_0F01_REG_1) },
11579   },
11580   {
11581     /* MOD_0F01_REG_2 */
11582     { X86_64_TABLE (X86_64_0F01_REG_2) },
11583     { RM_TABLE (RM_0F01_REG_2) },
11584   },
11585   {
11586     /* MOD_0F01_REG_3 */
11587     { X86_64_TABLE (X86_64_0F01_REG_3) },
11588     { RM_TABLE (RM_0F01_REG_3) },
11589   },
11590   {
11591     /* MOD_0F01_REG_5 */
11592     { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11593     { RM_TABLE (RM_0F01_REG_5) },
11594   },
11595   {
11596     /* MOD_0F01_REG_7 */
11597     { "invlpg",         { Mb }, 0 },
11598     { RM_TABLE (RM_0F01_REG_7) },
11599   },
11600   {
11601     /* MOD_0F12_PREFIX_0 */
11602     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
11603     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
11604   },
11605   {
11606     /* MOD_0F13 */
11607     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
11608   },
11609   {
11610     /* MOD_0F16_PREFIX_0 */
11611     { "movhps",         { XM, EXq }, 0 },
11612     { "movlhps",        { XM, EXq }, 0 },
11613   },
11614   {
11615     /* MOD_0F17 */
11616     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
11617   },
11618   {
11619     /* MOD_0F18_REG_0 */
11620     { "prefetchnta",    { Mb }, 0 },
11621   },
11622   {
11623     /* MOD_0F18_REG_1 */
11624     { "prefetcht0",     { Mb }, 0 },
11625   },
11626   {
11627     /* MOD_0F18_REG_2 */
11628     { "prefetcht1",     { Mb }, 0 },
11629   },
11630   {
11631     /* MOD_0F18_REG_3 */
11632     { "prefetcht2",     { Mb }, 0 },
11633   },
11634   {
11635     /* MOD_0F18_REG_4 */
11636     { "nop/reserved",   { Mb }, 0 },
11637   },
11638   {
11639     /* MOD_0F18_REG_5 */
11640     { "nop/reserved",   { Mb }, 0 },
11641   },
11642   {
11643     /* MOD_0F18_REG_6 */
11644     { "nop/reserved",   { Mb }, 0 },
11645   },
11646   {
11647     /* MOD_0F18_REG_7 */
11648     { "nop/reserved",   { Mb }, 0 },
11649   },
11650   {
11651     /* MOD_0F1A_PREFIX_0 */
11652     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
11653     { "nopQ",           { Ev }, 0 },
11654   },
11655   {
11656     /* MOD_0F1B_PREFIX_0 */
11657     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
11658     { "nopQ",           { Ev }, 0 },
11659   },
11660   {
11661     /* MOD_0F1B_PREFIX_1 */
11662     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
11663     { "nopQ",           { Ev }, 0 },
11664   },
11665   {
11666     /* MOD_0F1C_PREFIX_0 */
11667     { REG_TABLE (REG_0F1C_MOD_0) },
11668     { "nopQ",           { Ev }, 0 },
11669   },
11670   {
11671     /* MOD_0F1E_PREFIX_1 */
11672     { "nopQ",           { Ev }, 0 },
11673     { REG_TABLE (REG_0F1E_MOD_3) },
11674   },
11675   {
11676     /* MOD_0F24 */
11677     { Bad_Opcode },
11678     { "movL",           { Rd, Td }, 0 },
11679   },
11680   {
11681     /* MOD_0F26 */
11682     { Bad_Opcode },
11683     { "movL",           { Td, Rd }, 0 },
11684   },
11685   {
11686     /* MOD_0F2B_PREFIX_0 */
11687     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
11688   },
11689   {
11690     /* MOD_0F2B_PREFIX_1 */
11691     {"movntss",         { Md, XM }, PREFIX_OPCODE },
11692   },
11693   {
11694     /* MOD_0F2B_PREFIX_2 */
11695     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
11696   },
11697   {
11698     /* MOD_0F2B_PREFIX_3 */
11699     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
11700   },
11701   {
11702     /* MOD_0F51 */
11703     { Bad_Opcode },
11704     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
11705   },
11706   {
11707     /* MOD_0F71_REG_2 */
11708     { Bad_Opcode },
11709     { "psrlw",          { MS, Ib }, 0 },
11710   },
11711   {
11712     /* MOD_0F71_REG_4 */
11713     { Bad_Opcode },
11714     { "psraw",          { MS, Ib }, 0 },
11715   },
11716   {
11717     /* MOD_0F71_REG_6 */
11718     { Bad_Opcode },
11719     { "psllw",          { MS, Ib }, 0 },
11720   },
11721   {
11722     /* MOD_0F72_REG_2 */
11723     { Bad_Opcode },
11724     { "psrld",          { MS, Ib }, 0 },
11725   },
11726   {
11727     /* MOD_0F72_REG_4 */
11728     { Bad_Opcode },
11729     { "psrad",          { MS, Ib }, 0 },
11730   },
11731   {
11732     /* MOD_0F72_REG_6 */
11733     { Bad_Opcode },
11734     { "pslld",          { MS, Ib }, 0 },
11735   },
11736   {
11737     /* MOD_0F73_REG_2 */
11738     { Bad_Opcode },
11739     { "psrlq",          { MS, Ib }, 0 },
11740   },
11741   {
11742     /* MOD_0F73_REG_3 */
11743     { Bad_Opcode },
11744     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11745   },
11746   {
11747     /* MOD_0F73_REG_6 */
11748     { Bad_Opcode },
11749     { "psllq",          { MS, Ib }, 0 },
11750   },
11751   {
11752     /* MOD_0F73_REG_7 */
11753     { Bad_Opcode },
11754     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11755   },
11756   {
11757     /* MOD_0FAE_REG_0 */
11758     { "fxsave",         { FXSAVE }, 0 },
11759     { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11760   },
11761   {
11762     /* MOD_0FAE_REG_1 */
11763     { "fxrstor",        { FXSAVE }, 0 },
11764     { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11765   },
11766   {
11767     /* MOD_0FAE_REG_2 */
11768     { "ldmxcsr",        { Md }, 0 },
11769     { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11770   },
11771   {
11772     /* MOD_0FAE_REG_3 */
11773     { "stmxcsr",        { Md }, 0 },
11774     { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11775   },
11776   {
11777     /* MOD_0FAE_REG_4 */
11778     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11779     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11780   },
11781   {
11782     /* MOD_0FAE_REG_5 */
11783     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11784     { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11785   },
11786   {
11787     /* MOD_0FAE_REG_6 */
11788     { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11789     { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11790   },
11791   {
11792     /* MOD_0FAE_REG_7 */
11793     { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11794     { RM_TABLE (RM_0FAE_REG_7) },
11795   },
11796   {
11797     /* MOD_0FB2 */
11798     { "lssS",           { Gv, Mp }, 0 },
11799   },
11800   {
11801     /* MOD_0FB4 */
11802     { "lfsS",           { Gv, Mp }, 0 },
11803   },
11804   {
11805     /* MOD_0FB5 */
11806     { "lgsS",           { Gv, Mp }, 0 },
11807   },
11808   {
11809     /* MOD_0FC3 */
11810     { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11811   },
11812   {
11813     /* MOD_0FC7_REG_3 */
11814     { "xrstors",        { FXSAVE }, 0 },
11815   },
11816   {
11817     /* MOD_0FC7_REG_4 */
11818     { "xsavec",         { FXSAVE }, 0 },
11819   },
11820   {
11821     /* MOD_0FC7_REG_5 */
11822     { "xsaves",         { FXSAVE }, 0 },
11823   },
11824   {
11825     /* MOD_0FC7_REG_6 */
11826     { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11827     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11828   },
11829   {
11830     /* MOD_0FC7_REG_7 */
11831     { "vmptrst",        { Mq }, 0 },
11832     { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11833   },
11834   {
11835     /* MOD_0FD7 */
11836     { Bad_Opcode },
11837     { "pmovmskb",       { Gdq, MS }, 0 },
11838   },
11839   {
11840     /* MOD_0FE7_PREFIX_2 */
11841     { "movntdq",        { Mx, XM }, 0 },
11842   },
11843   {
11844     /* MOD_0FF0_PREFIX_3 */
11845     { "lddqu",          { XM, M }, 0 },
11846   },
11847   {
11848     /* MOD_0F382A_PREFIX_2 */
11849     { "movntdqa",       { XM, Mx }, 0 },
11850   },
11851   {
11852     /* MOD_0F38F5_PREFIX_2 */
11853     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
11854   },
11855   {
11856     /* MOD_0F38F6_PREFIX_0 */
11857     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
11858   },
11859   {
11860     /* MOD_0F38F8_PREFIX_2 */
11861     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
11862   },
11863   {
11864     /* MOD_0F38F9_PREFIX_0 */
11865     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
11866   },
11867   {
11868     /* MOD_62_32BIT */
11869     { "bound{S|}",      { Gv, Ma }, 0 },
11870     { EVEX_TABLE (EVEX_0F) },
11871   },
11872   {
11873     /* MOD_C4_32BIT */
11874     { "lesS",           { Gv, Mp }, 0 },
11875     { VEX_C4_TABLE (VEX_0F) },
11876   },
11877   {
11878     /* MOD_C5_32BIT */
11879     { "ldsS",           { Gv, Mp }, 0 },
11880     { VEX_C5_TABLE (VEX_0F) },
11881   },
11882   {
11883     /* MOD_VEX_0F12_PREFIX_0 */
11884     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11885     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11886   },
11887   {
11888     /* MOD_VEX_0F13 */
11889     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11890   },
11891   {
11892     /* MOD_VEX_0F16_PREFIX_0 */
11893     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11894     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11895   },
11896   {
11897     /* MOD_VEX_0F17 */
11898     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11899   },
11900   {
11901     /* MOD_VEX_0F2B */
11902     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11903   },
11904   {
11905     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11906     { Bad_Opcode },
11907     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
11908   },
11909   {
11910     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11911     { Bad_Opcode },
11912     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
11913   },
11914   {
11915     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11916     { Bad_Opcode },
11917     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
11918   },
11919   {
11920     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11921     { Bad_Opcode },
11922     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
11923   },
11924   {
11925     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11926     { Bad_Opcode },
11927     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
11928   },
11929   {
11930     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11931     { Bad_Opcode },
11932     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
11933   },
11934   {
11935     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11936     { Bad_Opcode },
11937     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
11938   },
11939   {
11940     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11941     { Bad_Opcode },
11942     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
11943   },
11944   {
11945     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11946     { Bad_Opcode },
11947     { "knotw",          { MaskG, MaskR }, 0 },
11948   },
11949   {
11950     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11951     { Bad_Opcode },
11952     { "knotq",          { MaskG, MaskR }, 0 },
11953   },
11954   {
11955     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11956     { Bad_Opcode },
11957     { "knotb",          { MaskG, MaskR }, 0 },
11958   },
11959   {
11960     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11961     { Bad_Opcode },
11962     { "knotd",          { MaskG, MaskR }, 0 },
11963   },
11964   {
11965     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11966     { Bad_Opcode },
11967     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
11968   },
11969   {
11970     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11971     { Bad_Opcode },
11972     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
11973   },
11974   {
11975     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11976     { Bad_Opcode },
11977     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
11978   },
11979   {
11980     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11981     { Bad_Opcode },
11982     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
11983   },
11984  {
11985     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11986     { Bad_Opcode },
11987     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
11988   },
11989   {
11990     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11991     { Bad_Opcode },
11992     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
11993   },
11994   {
11995     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11996     { Bad_Opcode },
11997     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
11998   },
11999   {
12000     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12001     { Bad_Opcode },
12002     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
12003   },
12004   {
12005     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12006     { Bad_Opcode },
12007     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
12008   },
12009   {
12010     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12011     { Bad_Opcode },
12012     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
12013   },
12014   {
12015     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12016     { Bad_Opcode },
12017     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
12018   },
12019   {
12020     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12021     { Bad_Opcode },
12022     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
12023   },
12024   {
12025     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12026     { Bad_Opcode },
12027     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
12028   },
12029   {
12030     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12031     { Bad_Opcode },
12032     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
12033   },
12034   {
12035     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12036     { Bad_Opcode },
12037     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
12038   },
12039   {
12040     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12041     { Bad_Opcode },
12042     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
12043   },
12044   {
12045     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12046     { Bad_Opcode },
12047     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
12048   },
12049   {
12050     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12051     { Bad_Opcode },
12052     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
12053   },
12054   {
12055     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12056     { Bad_Opcode },
12057     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
12058   },
12059   {
12060     /* MOD_VEX_0F50 */
12061     { Bad_Opcode },
12062     { VEX_W_TABLE (VEX_W_0F50_M_0) },
12063   },
12064   {
12065     /* MOD_VEX_0F71_REG_2 */
12066     { Bad_Opcode },
12067     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12068   },
12069   {
12070     /* MOD_VEX_0F71_REG_4 */
12071     { Bad_Opcode },
12072     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12073   },
12074   {
12075     /* MOD_VEX_0F71_REG_6 */
12076     { Bad_Opcode },
12077     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12078   },
12079   {
12080     /* MOD_VEX_0F72_REG_2 */
12081     { Bad_Opcode },
12082     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12083   },
12084   {
12085     /* MOD_VEX_0F72_REG_4 */
12086     { Bad_Opcode },
12087     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12088   },
12089   {
12090     /* MOD_VEX_0F72_REG_6 */
12091     { Bad_Opcode },
12092     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12093   },
12094   {
12095     /* MOD_VEX_0F73_REG_2 */
12096     { Bad_Opcode },
12097     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12098   },
12099   {
12100     /* MOD_VEX_0F73_REG_3 */
12101     { Bad_Opcode },
12102     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12103   },
12104   {
12105     /* MOD_VEX_0F73_REG_6 */
12106     { Bad_Opcode },
12107     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12108   },
12109   {
12110     /* MOD_VEX_0F73_REG_7 */
12111     { Bad_Opcode },
12112     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12113   },
12114   {
12115     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12116     { "kmovw",          { Ew, MaskG }, 0 },
12117     { Bad_Opcode },
12118   },
12119   {
12120     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12121     { "kmovq",          { Eq, MaskG }, 0 },
12122     { Bad_Opcode },
12123   },
12124   {
12125     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12126     { "kmovb",          { Eb, MaskG }, 0 },
12127     { Bad_Opcode },
12128   },
12129   {
12130     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12131     { "kmovd",          { Ed, MaskG }, 0 },
12132     { Bad_Opcode },
12133   },
12134   {
12135     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12136     { Bad_Opcode },
12137     { "kmovw",          { MaskG, Rdq }, 0 },
12138   },
12139   {
12140     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12141     { Bad_Opcode },
12142     { "kmovb",          { MaskG, Rdq }, 0 },
12143   },
12144   {
12145     /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12146     { Bad_Opcode },
12147     { "kmovd",          { MaskG, Rdq }, 0 },
12148   },
12149   {
12150     /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12151     { Bad_Opcode },
12152     { "kmovq",          { MaskG, Rdq }, 0 },
12153   },
12154   {
12155     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12156     { Bad_Opcode },
12157     { "kmovw",          { Gdq, MaskR }, 0 },
12158   },
12159   {
12160     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12161     { Bad_Opcode },
12162     { "kmovb",          { Gdq, MaskR }, 0 },
12163   },
12164   {
12165     /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12166     { Bad_Opcode },
12167     { "kmovd",          { Gdq, MaskR }, 0 },
12168   },
12169   {
12170     /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12171     { Bad_Opcode },
12172     { "kmovq",          { Gdq, MaskR }, 0 },
12173   },
12174   {
12175     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12176     { Bad_Opcode },
12177     { "kortestw", { MaskG, MaskR }, 0 },
12178   },
12179   {
12180     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12181     { Bad_Opcode },
12182     { "kortestq", { MaskG, MaskR }, 0 },
12183   },
12184   {
12185     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12186     { Bad_Opcode },
12187     { "kortestb", { MaskG, MaskR }, 0 },
12188   },
12189   {
12190     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12191     { Bad_Opcode },
12192     { "kortestd", { MaskG, MaskR }, 0 },
12193   },
12194   {
12195     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12196     { Bad_Opcode },
12197     { "ktestw", { MaskG, MaskR }, 0 },
12198   },
12199   {
12200     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12201     { Bad_Opcode },
12202     { "ktestq", { MaskG, MaskR }, 0 },
12203   },
12204   {
12205     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12206     { Bad_Opcode },
12207     { "ktestb", { MaskG, MaskR }, 0 },
12208   },
12209   {
12210     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12211     { Bad_Opcode },
12212     { "ktestd", { MaskG, MaskR }, 0 },
12213   },
12214   {
12215     /* MOD_VEX_0FAE_REG_2 */
12216     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12217   },
12218   {
12219     /* MOD_VEX_0FAE_REG_3 */
12220     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12221   },
12222   {
12223     /* MOD_VEX_0FD7_PREFIX_2 */
12224     { Bad_Opcode },
12225     { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12226   },
12227   {
12228     /* MOD_VEX_0FE7_PREFIX_2 */
12229     { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12230   },
12231   {
12232     /* MOD_VEX_0FF0_PREFIX_3 */
12233     { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12234   },
12235   {
12236     /* MOD_VEX_0F381A_PREFIX_2 */
12237     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12238   },
12239   {
12240     /* MOD_VEX_0F382A_PREFIX_2 */
12241     { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12242   },
12243   {
12244     /* MOD_VEX_0F382C_PREFIX_2 */
12245     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12246   },
12247   {
12248     /* MOD_VEX_0F382D_PREFIX_2 */
12249     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12250   },
12251   {
12252     /* MOD_VEX_0F382E_PREFIX_2 */
12253     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12254   },
12255   {
12256     /* MOD_VEX_0F382F_PREFIX_2 */
12257     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12258   },
12259   {
12260     /* MOD_VEX_0F385A_PREFIX_2 */
12261     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12262   },
12263   {
12264     /* MOD_VEX_0F388C_PREFIX_2 */
12265     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
12266   },
12267   {
12268     /* MOD_VEX_0F388E_PREFIX_2 */
12269     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
12270   },
12271   {
12272     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12273     { Bad_Opcode },
12274     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
12275   },
12276   {
12277     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12278     { Bad_Opcode },
12279     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
12280   },
12281   {
12282     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12283     { Bad_Opcode },
12284     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
12285   },
12286   {
12287     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12288     { Bad_Opcode },
12289     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
12290   },
12291   {
12292     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12293     { Bad_Opcode },
12294     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
12295   },
12296   {
12297     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12298     { Bad_Opcode },
12299     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
12300   },
12301   {
12302     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12303     { Bad_Opcode },
12304     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
12305   },
12306   {
12307     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12308     { Bad_Opcode },
12309     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
12310   },
12311 #define NEED_MOD_TABLE
12312 #include "i386-dis-evex.h"
12313 #undef NEED_MOD_TABLE
12314 };
12315
12316 static const struct dis386 rm_table[][8] = {
12317   {
12318     /* RM_C6_REG_7 */
12319     { "xabort",         { Skip_MODRM, Ib }, 0 },
12320   },
12321   {
12322     /* RM_C7_REG_7 */
12323     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
12324   },
12325   {
12326     /* RM_0F01_REG_0 */
12327     { Bad_Opcode },
12328     { "vmcall",         { Skip_MODRM }, 0 },
12329     { "vmlaunch",       { Skip_MODRM }, 0 },
12330     { "vmresume",       { Skip_MODRM }, 0 },
12331     { "vmxoff",         { Skip_MODRM }, 0 },
12332     { "pconfig",        { Skip_MODRM }, 0 },
12333   },
12334   {
12335     /* RM_0F01_REG_1 */
12336     { "monitor",        { { OP_Monitor, 0 } }, 0 },
12337     { "mwait",          { { OP_Mwait, 0 } }, 0 },
12338     { "clac",           { Skip_MODRM }, 0 },
12339     { "stac",           { Skip_MODRM }, 0 },
12340     { Bad_Opcode },
12341     { Bad_Opcode },
12342     { Bad_Opcode },
12343     { "encls",          { Skip_MODRM }, 0 },
12344   },
12345   {
12346     /* RM_0F01_REG_2 */
12347     { "xgetbv",         { Skip_MODRM }, 0 },
12348     { "xsetbv",         { Skip_MODRM }, 0 },
12349     { Bad_Opcode },
12350     { Bad_Opcode },
12351     { "vmfunc",         { Skip_MODRM }, 0 },
12352     { "xend",           { Skip_MODRM }, 0 },
12353     { "xtest",          { Skip_MODRM }, 0 },
12354     { "enclu",          { Skip_MODRM }, 0 },
12355   },
12356   {
12357     /* RM_0F01_REG_3 */
12358     { "vmrun",          { Skip_MODRM }, 0 },
12359     { "vmmcall",        { Skip_MODRM }, 0 },
12360     { "vmload",         { Skip_MODRM }, 0 },
12361     { "vmsave",         { Skip_MODRM }, 0 },
12362     { "stgi",           { Skip_MODRM }, 0 },
12363     { "clgi",           { Skip_MODRM }, 0 },
12364     { "skinit",         { Skip_MODRM }, 0 },
12365     { "invlpga",        { Skip_MODRM }, 0 },
12366   },
12367   {
12368     /* RM_0F01_REG_5 */
12369     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12370     { Bad_Opcode },
12371     { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12372     { Bad_Opcode },
12373     { Bad_Opcode },
12374     { Bad_Opcode },
12375     { "rdpkru",         { Skip_MODRM }, 0 },
12376     { "wrpkru",         { Skip_MODRM }, 0 },
12377   },
12378   {
12379     /* RM_0F01_REG_7 */
12380     { "swapgs",         { Skip_MODRM }, 0  },
12381     { "rdtscp",         { Skip_MODRM }, 0  },
12382     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
12383     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
12384     { "clzero",         { Skip_MODRM }, 0  },
12385   },
12386   {
12387     /* RM_0F1E_MOD_3_REG_7 */
12388     { "nopQ",           { Ev }, 0 },
12389     { "nopQ",           { Ev }, 0 },
12390     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
12391     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
12392     { "nopQ",           { Ev }, 0 },
12393     { "nopQ",           { Ev }, 0 },
12394     { "nopQ",           { Ev }, 0 },
12395     { "nopQ",           { Ev }, 0 },
12396   },
12397   {
12398     /* RM_0FAE_REG_6 */
12399     { "mfence",         { Skip_MODRM }, 0 },
12400   },
12401   {
12402     /* RM_0FAE_REG_7 */
12403     { "sfence",         { Skip_MODRM }, 0 },
12404
12405   },
12406 };
12407
12408 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12409
12410 /* We use the high bit to indicate different name for the same
12411    prefix.  */
12412 #define REP_PREFIX      (0xf3 | 0x100)
12413 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12414 #define XRELEASE_PREFIX (0xf3 | 0x400)
12415 #define BND_PREFIX      (0xf2 | 0x400)
12416 #define NOTRACK_PREFIX  (0x3e | 0x100)
12417
12418 static int
12419 ckprefix (void)
12420 {
12421   int newrex, i, length;
12422   rex = 0;
12423   rex_ignored = 0;
12424   prefixes = 0;
12425   used_prefixes = 0;
12426   rex_used = 0;
12427   last_lock_prefix = -1;
12428   last_repz_prefix = -1;
12429   last_repnz_prefix = -1;
12430   last_data_prefix = -1;
12431   last_addr_prefix = -1;
12432   last_rex_prefix = -1;
12433   last_seg_prefix = -1;
12434   fwait_prefix = -1;
12435   active_seg_prefix = 0;
12436   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12437     all_prefixes[i] = 0;
12438   i = 0;
12439   length = 0;
12440   /* The maximum instruction length is 15bytes.  */
12441   while (length < MAX_CODE_LENGTH - 1)
12442     {
12443       FETCH_DATA (the_info, codep + 1);
12444       newrex = 0;
12445       switch (*codep)
12446         {
12447         /* REX prefixes family.  */
12448         case 0x40:
12449         case 0x41:
12450         case 0x42:
12451         case 0x43:
12452         case 0x44:
12453         case 0x45:
12454         case 0x46:
12455         case 0x47:
12456         case 0x48:
12457         case 0x49:
12458         case 0x4a:
12459         case 0x4b:
12460         case 0x4c:
12461         case 0x4d:
12462         case 0x4e:
12463         case 0x4f:
12464           if (address_mode == mode_64bit)
12465             newrex = *codep;
12466           else
12467             return 1;
12468           last_rex_prefix = i;
12469           break;
12470         case 0xf3:
12471           prefixes |= PREFIX_REPZ;
12472           last_repz_prefix = i;
12473           break;
12474         case 0xf2:
12475           prefixes |= PREFIX_REPNZ;
12476           last_repnz_prefix = i;
12477           break;
12478         case 0xf0:
12479           prefixes |= PREFIX_LOCK;
12480           last_lock_prefix = i;
12481           break;
12482         case 0x2e:
12483           prefixes |= PREFIX_CS;
12484           last_seg_prefix = i;
12485           active_seg_prefix = PREFIX_CS;
12486           break;
12487         case 0x36:
12488           prefixes |= PREFIX_SS;
12489           last_seg_prefix = i;
12490           active_seg_prefix = PREFIX_SS;
12491           break;
12492         case 0x3e:
12493           prefixes |= PREFIX_DS;
12494           last_seg_prefix = i;
12495           active_seg_prefix = PREFIX_DS;
12496           break;
12497         case 0x26:
12498           prefixes |= PREFIX_ES;
12499           last_seg_prefix = i;
12500           active_seg_prefix = PREFIX_ES;
12501           break;
12502         case 0x64:
12503           prefixes |= PREFIX_FS;
12504           last_seg_prefix = i;
12505           active_seg_prefix = PREFIX_FS;
12506           break;
12507         case 0x65:
12508           prefixes |= PREFIX_GS;
12509           last_seg_prefix = i;
12510           active_seg_prefix = PREFIX_GS;
12511           break;
12512         case 0x66:
12513           prefixes |= PREFIX_DATA;
12514           last_data_prefix = i;
12515           break;
12516         case 0x67:
12517           prefixes |= PREFIX_ADDR;
12518           last_addr_prefix = i;
12519           break;
12520         case FWAIT_OPCODE:
12521           /* fwait is really an instruction.  If there are prefixes
12522              before the fwait, they belong to the fwait, *not* to the
12523              following instruction.  */
12524           fwait_prefix = i;
12525           if (prefixes || rex)
12526             {
12527               prefixes |= PREFIX_FWAIT;
12528               codep++;
12529               /* This ensures that the previous REX prefixes are noticed
12530                  as unused prefixes, as in the return case below.  */
12531               rex_used = rex;
12532               return 1;
12533             }
12534           prefixes = PREFIX_FWAIT;
12535           break;
12536         default:
12537           return 1;
12538         }
12539       /* Rex is ignored when followed by another prefix.  */
12540       if (rex)
12541         {
12542           rex_used = rex;
12543           return 1;
12544         }
12545       if (*codep != FWAIT_OPCODE)
12546         all_prefixes[i++] = *codep;
12547       rex = newrex;
12548       codep++;
12549       length++;
12550     }
12551   return 0;
12552 }
12553
12554 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12555    prefix byte.  */
12556
12557 static const char *
12558 prefix_name (int pref, int sizeflag)
12559 {
12560   static const char *rexes [16] =
12561     {
12562       "rex",            /* 0x40 */
12563       "rex.B",          /* 0x41 */
12564       "rex.X",          /* 0x42 */
12565       "rex.XB",         /* 0x43 */
12566       "rex.R",          /* 0x44 */
12567       "rex.RB",         /* 0x45 */
12568       "rex.RX",         /* 0x46 */
12569       "rex.RXB",        /* 0x47 */
12570       "rex.W",          /* 0x48 */
12571       "rex.WB",         /* 0x49 */
12572       "rex.WX",         /* 0x4a */
12573       "rex.WXB",        /* 0x4b */
12574       "rex.WR",         /* 0x4c */
12575       "rex.WRB",        /* 0x4d */
12576       "rex.WRX",        /* 0x4e */
12577       "rex.WRXB",       /* 0x4f */
12578     };
12579
12580   switch (pref)
12581     {
12582     /* REX prefixes family.  */
12583     case 0x40:
12584     case 0x41:
12585     case 0x42:
12586     case 0x43:
12587     case 0x44:
12588     case 0x45:
12589     case 0x46:
12590     case 0x47:
12591     case 0x48:
12592     case 0x49:
12593     case 0x4a:
12594     case 0x4b:
12595     case 0x4c:
12596     case 0x4d:
12597     case 0x4e:
12598     case 0x4f:
12599       return rexes [pref - 0x40];
12600     case 0xf3:
12601       return "repz";
12602     case 0xf2:
12603       return "repnz";
12604     case 0xf0:
12605       return "lock";
12606     case 0x2e:
12607       return "cs";
12608     case 0x36:
12609       return "ss";
12610     case 0x3e:
12611       return "ds";
12612     case 0x26:
12613       return "es";
12614     case 0x64:
12615       return "fs";
12616     case 0x65:
12617       return "gs";
12618     case 0x66:
12619       return (sizeflag & DFLAG) ? "data16" : "data32";
12620     case 0x67:
12621       if (address_mode == mode_64bit)
12622         return (sizeflag & AFLAG) ? "addr32" : "addr64";
12623       else
12624         return (sizeflag & AFLAG) ? "addr16" : "addr32";
12625     case FWAIT_OPCODE:
12626       return "fwait";
12627     case REP_PREFIX:
12628       return "rep";
12629     case XACQUIRE_PREFIX:
12630       return "xacquire";
12631     case XRELEASE_PREFIX:
12632       return "xrelease";
12633     case BND_PREFIX:
12634       return "bnd";
12635     case NOTRACK_PREFIX:
12636       return "notrack";
12637     default:
12638       return NULL;
12639     }
12640 }
12641
12642 static char op_out[MAX_OPERANDS][100];
12643 static int op_ad, op_index[MAX_OPERANDS];
12644 static int two_source_ops;
12645 static bfd_vma op_address[MAX_OPERANDS];
12646 static bfd_vma op_riprel[MAX_OPERANDS];
12647 static bfd_vma start_pc;
12648
12649 /*
12650  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12651  *   (see topic "Redundant prefixes" in the "Differences from 8086"
12652  *   section of the "Virtual 8086 Mode" chapter.)
12653  * 'pc' should be the address of this instruction, it will
12654  *   be used to print the target address if this is a relative jump or call
12655  * The function returns the length of this instruction in bytes.
12656  */
12657
12658 static char intel_syntax;
12659 static char intel_mnemonic = !SYSV386_COMPAT;
12660 static char open_char;
12661 static char close_char;
12662 static char separator_char;
12663 static char scale_char;
12664
12665 enum x86_64_isa
12666 {
12667   amd64 = 0,
12668   intel64
12669 };
12670
12671 static enum x86_64_isa isa64;
12672
12673 /* Here for backwards compatibility.  When gdb stops using
12674    print_insn_i386_att and print_insn_i386_intel these functions can
12675    disappear, and print_insn_i386 be merged into print_insn.  */
12676 int
12677 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12678 {
12679   intel_syntax = 0;
12680
12681   return print_insn (pc, info);
12682 }
12683
12684 int
12685 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12686 {
12687   intel_syntax = 1;
12688
12689   return print_insn (pc, info);
12690 }
12691
12692 int
12693 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12694 {
12695   intel_syntax = -1;
12696
12697   return print_insn (pc, info);
12698 }
12699
12700 void
12701 print_i386_disassembler_options (FILE *stream)
12702 {
12703   fprintf (stream, _("\n\
12704 The following i386/x86-64 specific disassembler options are supported for use\n\
12705 with the -M switch (multiple options should be separated by commas):\n"));
12706
12707   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12708   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12709   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12710   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12711   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12712   fprintf (stream, _("  att-mnemonic\n"
12713                      "              Display instruction in AT&T mnemonic\n"));
12714   fprintf (stream, _("  intel-mnemonic\n"
12715                      "              Display instruction in Intel mnemonic\n"));
12716   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12717   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12718   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12719   fprintf (stream, _("  data32      Assume 32bit data size\n"));
12720   fprintf (stream, _("  data16      Assume 16bit data size\n"));
12721   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12722   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
12723   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
12724 }
12725
12726 /* Bad opcode.  */
12727 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12728
12729 /* Get a pointer to struct dis386 with a valid name.  */
12730
12731 static const struct dis386 *
12732 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12733 {
12734   int vindex, vex_table_index;
12735
12736   if (dp->name != NULL)
12737     return dp;
12738
12739   switch (dp->op[0].bytemode)
12740     {
12741     case USE_REG_TABLE:
12742       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12743       break;
12744
12745     case USE_MOD_TABLE:
12746       vindex = modrm.mod == 0x3 ? 1 : 0;
12747       dp = &mod_table[dp->op[1].bytemode][vindex];
12748       break;
12749
12750     case USE_RM_TABLE:
12751       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12752       break;
12753
12754     case USE_PREFIX_TABLE:
12755       if (need_vex)
12756         {
12757           /* The prefix in VEX is implicit.  */
12758           switch (vex.prefix)
12759             {
12760             case 0:
12761               vindex = 0;
12762               break;
12763             case REPE_PREFIX_OPCODE:
12764               vindex = 1;
12765               break;
12766             case DATA_PREFIX_OPCODE:
12767               vindex = 2;
12768               break;
12769             case REPNE_PREFIX_OPCODE:
12770               vindex = 3;
12771               break;
12772             default:
12773               abort ();
12774               break;
12775             }
12776         }
12777       else
12778         {
12779           int last_prefix = -1;
12780           int prefix = 0;
12781           vindex = 0;
12782           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12783              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12784              last one wins.  */
12785           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12786             {
12787               if (last_repz_prefix > last_repnz_prefix)
12788                 {
12789                   vindex = 1;
12790                   prefix = PREFIX_REPZ;
12791                   last_prefix = last_repz_prefix;
12792                 }
12793               else
12794                 {
12795                   vindex = 3;
12796                   prefix = PREFIX_REPNZ;
12797                   last_prefix = last_repnz_prefix;
12798                 }
12799
12800               /* Check if prefix should be ignored.  */
12801               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12802                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12803                    & prefix) != 0)
12804                 vindex = 0;
12805             }
12806
12807           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12808             {
12809               vindex = 2;
12810               prefix = PREFIX_DATA;
12811               last_prefix = last_data_prefix;
12812             }
12813
12814           if (vindex != 0)
12815             {
12816               used_prefixes |= prefix;
12817               all_prefixes[last_prefix] = 0;
12818             }
12819         }
12820       dp = &prefix_table[dp->op[1].bytemode][vindex];
12821       break;
12822
12823     case USE_X86_64_TABLE:
12824       vindex = address_mode == mode_64bit ? 1 : 0;
12825       dp = &x86_64_table[dp->op[1].bytemode][vindex];
12826       break;
12827
12828     case USE_3BYTE_TABLE:
12829       FETCH_DATA (info, codep + 2);
12830       vindex = *codep++;
12831       dp = &three_byte_table[dp->op[1].bytemode][vindex];
12832       end_codep = codep;
12833       modrm.mod = (*codep >> 6) & 3;
12834       modrm.reg = (*codep >> 3) & 7;
12835       modrm.rm = *codep & 7;
12836       break;
12837
12838     case USE_VEX_LEN_TABLE:
12839       if (!need_vex)
12840         abort ();
12841
12842       switch (vex.length)
12843         {
12844         case 128:
12845           vindex = 0;
12846           break;
12847         case 256:
12848           vindex = 1;
12849           break;
12850         default:
12851           abort ();
12852           break;
12853         }
12854
12855       dp = &vex_len_table[dp->op[1].bytemode][vindex];
12856       break;
12857
12858     case USE_XOP_8F_TABLE:
12859       FETCH_DATA (info, codep + 3);
12860       /* All bits in the REX prefix are ignored.  */
12861       rex_ignored = rex;
12862       rex = ~(*codep >> 5) & 0x7;
12863
12864       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12865       switch ((*codep & 0x1f))
12866         {
12867         default:
12868           dp = &bad_opcode;
12869           return dp;
12870         case 0x8:
12871           vex_table_index = XOP_08;
12872           break;
12873         case 0x9:
12874           vex_table_index = XOP_09;
12875           break;
12876         case 0xa:
12877           vex_table_index = XOP_0A;
12878           break;
12879         }
12880       codep++;
12881       vex.w = *codep & 0x80;
12882       if (vex.w && address_mode == mode_64bit)
12883         rex |= REX_W;
12884
12885       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12886       if (address_mode != mode_64bit)
12887         {
12888           /* In 16/32-bit mode REX_B is silently ignored.  */
12889           rex &= ~REX_B;
12890         }
12891
12892       vex.length = (*codep & 0x4) ? 256 : 128;
12893       switch ((*codep & 0x3))
12894         {
12895         case 0:
12896           break;
12897         case 1:
12898           vex.prefix = DATA_PREFIX_OPCODE;
12899           break;
12900         case 2:
12901           vex.prefix = REPE_PREFIX_OPCODE;
12902           break;
12903         case 3:
12904           vex.prefix = REPNE_PREFIX_OPCODE;
12905           break;
12906         }
12907       need_vex = 1;
12908       need_vex_reg = 1;
12909       codep++;
12910       vindex = *codep++;
12911       dp = &xop_table[vex_table_index][vindex];
12912
12913       end_codep = codep;
12914       FETCH_DATA (info, codep + 1);
12915       modrm.mod = (*codep >> 6) & 3;
12916       modrm.reg = (*codep >> 3) & 7;
12917       modrm.rm = *codep & 7;
12918       break;
12919
12920     case USE_VEX_C4_TABLE:
12921       /* VEX prefix.  */
12922       FETCH_DATA (info, codep + 3);
12923       /* All bits in the REX prefix are ignored.  */
12924       rex_ignored = rex;
12925       rex = ~(*codep >> 5) & 0x7;
12926       switch ((*codep & 0x1f))
12927         {
12928         default:
12929           dp = &bad_opcode;
12930           return dp;
12931         case 0x1:
12932           vex_table_index = VEX_0F;
12933           break;
12934         case 0x2:
12935           vex_table_index = VEX_0F38;
12936           break;
12937         case 0x3:
12938           vex_table_index = VEX_0F3A;
12939           break;
12940         }
12941       codep++;
12942       vex.w = *codep & 0x80;
12943       if (address_mode == mode_64bit)
12944         {
12945           if (vex.w)
12946             rex |= REX_W;
12947         }
12948       else
12949         {
12950           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12951              is ignored, other REX bits are 0 and the highest bit in
12952              VEX.vvvv is also ignored (but we mustn't clear it here).  */
12953           rex = 0;
12954         }
12955       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12956       vex.length = (*codep & 0x4) ? 256 : 128;
12957       switch ((*codep & 0x3))
12958         {
12959         case 0:
12960           break;
12961         case 1:
12962           vex.prefix = DATA_PREFIX_OPCODE;
12963           break;
12964         case 2:
12965           vex.prefix = REPE_PREFIX_OPCODE;
12966           break;
12967         case 3:
12968           vex.prefix = REPNE_PREFIX_OPCODE;
12969           break;
12970         }
12971       need_vex = 1;
12972       need_vex_reg = 1;
12973       codep++;
12974       vindex = *codep++;
12975       dp = &vex_table[vex_table_index][vindex];
12976       end_codep = codep;
12977       /* There is no MODRM byte for VEX0F 77.  */
12978       if (vex_table_index != VEX_0F || vindex != 0x77)
12979         {
12980           FETCH_DATA (info, codep + 1);
12981           modrm.mod = (*codep >> 6) & 3;
12982           modrm.reg = (*codep >> 3) & 7;
12983           modrm.rm = *codep & 7;
12984         }
12985       break;
12986
12987     case USE_VEX_C5_TABLE:
12988       /* VEX prefix.  */
12989       FETCH_DATA (info, codep + 2);
12990       /* All bits in the REX prefix are ignored.  */
12991       rex_ignored = rex;
12992       rex = (*codep & 0x80) ? 0 : REX_R;
12993
12994       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12995          VEX.vvvv is 1.  */
12996       vex.register_specifier = (~(*codep >> 3)) & 0xf;
12997       vex.length = (*codep & 0x4) ? 256 : 128;
12998       switch ((*codep & 0x3))
12999         {
13000         case 0:
13001           break;
13002         case 1:
13003           vex.prefix = DATA_PREFIX_OPCODE;
13004           break;
13005         case 2:
13006           vex.prefix = REPE_PREFIX_OPCODE;
13007           break;
13008         case 3:
13009           vex.prefix = REPNE_PREFIX_OPCODE;
13010           break;
13011         }
13012       need_vex = 1;
13013       need_vex_reg = 1;
13014       codep++;
13015       vindex = *codep++;
13016       dp = &vex_table[dp->op[1].bytemode][vindex];
13017       end_codep = codep;
13018       /* There is no MODRM byte for VEX 77.  */
13019       if (vindex != 0x77)
13020         {
13021           FETCH_DATA (info, codep + 1);
13022           modrm.mod = (*codep >> 6) & 3;
13023           modrm.reg = (*codep >> 3) & 7;
13024           modrm.rm = *codep & 7;
13025         }
13026       break;
13027
13028     case USE_VEX_W_TABLE:
13029       if (!need_vex)
13030         abort ();
13031
13032       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13033       break;
13034
13035     case USE_EVEX_TABLE:
13036       two_source_ops = 0;
13037       /* EVEX prefix.  */
13038       vex.evex = 1;
13039       FETCH_DATA (info, codep + 4);
13040       /* All bits in the REX prefix are ignored.  */
13041       rex_ignored = rex;
13042       /* The first byte after 0x62.  */
13043       rex = ~(*codep >> 5) & 0x7;
13044       vex.r = *codep & 0x10;
13045       switch ((*codep & 0xf))
13046         {
13047         default:
13048           return &bad_opcode;
13049         case 0x1:
13050           vex_table_index = EVEX_0F;
13051           break;
13052         case 0x2:
13053           vex_table_index = EVEX_0F38;
13054           break;
13055         case 0x3:
13056           vex_table_index = EVEX_0F3A;
13057           break;
13058         }
13059
13060       /* The second byte after 0x62.  */
13061       codep++;
13062       vex.w = *codep & 0x80;
13063       if (vex.w && address_mode == mode_64bit)
13064         rex |= REX_W;
13065
13066       vex.register_specifier = (~(*codep >> 3)) & 0xf;
13067
13068       /* The U bit.  */
13069       if (!(*codep & 0x4))
13070         return &bad_opcode;
13071
13072       switch ((*codep & 0x3))
13073         {
13074         case 0:
13075           break;
13076         case 1:
13077           vex.prefix = DATA_PREFIX_OPCODE;
13078           break;
13079         case 2:
13080           vex.prefix = REPE_PREFIX_OPCODE;
13081           break;
13082         case 3:
13083           vex.prefix = REPNE_PREFIX_OPCODE;
13084           break;
13085         }
13086
13087       /* The third byte after 0x62.  */
13088       codep++;
13089
13090       /* Remember the static rounding bits.  */
13091       vex.ll = (*codep >> 5) & 3;
13092       vex.b = (*codep & 0x10) != 0;
13093
13094       vex.v = *codep & 0x8;
13095       vex.mask_register_specifier = *codep & 0x7;
13096       vex.zeroing = *codep & 0x80;
13097
13098       if (address_mode != mode_64bit)
13099         {
13100           /* In 16/32-bit mode silently ignore following bits.  */
13101           rex &= ~REX_B;
13102           vex.r = 1;
13103           vex.v = 1;
13104         }
13105
13106       need_vex = 1;
13107       need_vex_reg = 1;
13108       codep++;
13109       vindex = *codep++;
13110       dp = &evex_table[vex_table_index][vindex];
13111       end_codep = codep;
13112       FETCH_DATA (info, codep + 1);
13113       modrm.mod = (*codep >> 6) & 3;
13114       modrm.reg = (*codep >> 3) & 7;
13115       modrm.rm = *codep & 7;
13116
13117       /* Set vector length.  */
13118       if (modrm.mod == 3 && vex.b)
13119         vex.length = 512;
13120       else
13121         {
13122           switch (vex.ll)
13123             {
13124             case 0x0:
13125               vex.length = 128;
13126               break;
13127             case 0x1:
13128               vex.length = 256;
13129               break;
13130             case 0x2:
13131               vex.length = 512;
13132               break;
13133             default:
13134               return &bad_opcode;
13135             }
13136         }
13137       break;
13138
13139     case 0:
13140       dp = &bad_opcode;
13141       break;
13142
13143     default:
13144       abort ();
13145     }
13146
13147   if (dp->name != NULL)
13148     return dp;
13149   else
13150     return get_valid_dis386 (dp, info);
13151 }
13152
13153 static void
13154 get_sib (disassemble_info *info, int sizeflag)
13155 {
13156   /* If modrm.mod == 3, operand must be register.  */
13157   if (need_modrm
13158       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13159       && modrm.mod != 3
13160       && modrm.rm == 4)
13161     {
13162       FETCH_DATA (info, codep + 2);
13163       sib.index = (codep [1] >> 3) & 7;
13164       sib.scale = (codep [1] >> 6) & 3;
13165       sib.base = codep [1] & 7;
13166     }
13167 }
13168
13169 static int
13170 print_insn (bfd_vma pc, disassemble_info *info)
13171 {
13172   const struct dis386 *dp;
13173   int i;
13174   char *op_txt[MAX_OPERANDS];
13175   int needcomma;
13176   int sizeflag, orig_sizeflag;
13177   const char *p;
13178   struct dis_private priv;
13179   int prefix_length;
13180
13181   priv.orig_sizeflag = AFLAG | DFLAG;
13182   if ((info->mach & bfd_mach_i386_i386) != 0)
13183     address_mode = mode_32bit;
13184   else if (info->mach == bfd_mach_i386_i8086)
13185     {
13186       address_mode = mode_16bit;
13187       priv.orig_sizeflag = 0;
13188     }
13189   else
13190     address_mode = mode_64bit;
13191
13192   if (intel_syntax == (char) -1)
13193     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13194
13195   for (p = info->disassembler_options; p != NULL; )
13196     {
13197       if (CONST_STRNEQ (p, "amd64"))
13198         isa64 = amd64;
13199       else if (CONST_STRNEQ (p, "intel64"))
13200         isa64 = intel64;
13201       else if (CONST_STRNEQ (p, "x86-64"))
13202         {
13203           address_mode = mode_64bit;
13204           priv.orig_sizeflag = AFLAG | DFLAG;
13205         }
13206       else if (CONST_STRNEQ (p, "i386"))
13207         {
13208           address_mode = mode_32bit;
13209           priv.orig_sizeflag = AFLAG | DFLAG;
13210         }
13211       else if (CONST_STRNEQ (p, "i8086"))
13212         {
13213           address_mode = mode_16bit;
13214           priv.orig_sizeflag = 0;
13215         }
13216       else if (CONST_STRNEQ (p, "intel"))
13217         {
13218           intel_syntax = 1;
13219           if (CONST_STRNEQ (p + 5, "-mnemonic"))
13220             intel_mnemonic = 1;
13221         }
13222       else if (CONST_STRNEQ (p, "att"))
13223         {
13224           intel_syntax = 0;
13225           if (CONST_STRNEQ (p + 3, "-mnemonic"))
13226             intel_mnemonic = 0;
13227         }
13228       else if (CONST_STRNEQ (p, "addr"))
13229         {
13230           if (address_mode == mode_64bit)
13231             {
13232               if (p[4] == '3' && p[5] == '2')
13233                 priv.orig_sizeflag &= ~AFLAG;
13234               else if (p[4] == '6' && p[5] == '4')
13235                 priv.orig_sizeflag |= AFLAG;
13236             }
13237           else
13238             {
13239               if (p[4] == '1' && p[5] == '6')
13240                 priv.orig_sizeflag &= ~AFLAG;
13241               else if (p[4] == '3' && p[5] == '2')
13242                 priv.orig_sizeflag |= AFLAG;
13243             }
13244         }
13245       else if (CONST_STRNEQ (p, "data"))
13246         {
13247           if (p[4] == '1' && p[5] == '6')
13248             priv.orig_sizeflag &= ~DFLAG;
13249           else if (p[4] == '3' && p[5] == '2')
13250             priv.orig_sizeflag |= DFLAG;
13251         }
13252       else if (CONST_STRNEQ (p, "suffix"))
13253         priv.orig_sizeflag |= SUFFIX_ALWAYS;
13254
13255       p = strchr (p, ',');
13256       if (p != NULL)
13257         p++;
13258     }
13259
13260   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13261     {
13262       (*info->fprintf_func) (info->stream,
13263                              _("64-bit address is disabled"));
13264       return -1;
13265     }
13266
13267   if (intel_syntax)
13268     {
13269       names64 = intel_names64;
13270       names32 = intel_names32;
13271       names16 = intel_names16;
13272       names8 = intel_names8;
13273       names8rex = intel_names8rex;
13274       names_seg = intel_names_seg;
13275       names_mm = intel_names_mm;
13276       names_bnd = intel_names_bnd;
13277       names_xmm = intel_names_xmm;
13278       names_ymm = intel_names_ymm;
13279       names_zmm = intel_names_zmm;
13280       index64 = intel_index64;
13281       index32 = intel_index32;
13282       names_mask = intel_names_mask;
13283       index16 = intel_index16;
13284       open_char = '[';
13285       close_char = ']';
13286       separator_char = '+';
13287       scale_char = '*';
13288     }
13289   else
13290     {
13291       names64 = att_names64;
13292       names32 = att_names32;
13293       names16 = att_names16;
13294       names8 = att_names8;
13295       names8rex = att_names8rex;
13296       names_seg = att_names_seg;
13297       names_mm = att_names_mm;
13298       names_bnd = att_names_bnd;
13299       names_xmm = att_names_xmm;
13300       names_ymm = att_names_ymm;
13301       names_zmm = att_names_zmm;
13302       index64 = att_index64;
13303       index32 = att_index32;
13304       names_mask = att_names_mask;
13305       index16 = att_index16;
13306       open_char = '(';
13307       close_char =  ')';
13308       separator_char = ',';
13309       scale_char = ',';
13310     }
13311
13312   /* The output looks better if we put 7 bytes on a line, since that
13313      puts most long word instructions on a single line.  Use 8 bytes
13314      for Intel L1OM.  */
13315   if ((info->mach & bfd_mach_l1om) != 0)
13316     info->bytes_per_line = 8;
13317   else
13318     info->bytes_per_line = 7;
13319
13320   info->private_data = &priv;
13321   priv.max_fetched = priv.the_buffer;
13322   priv.insn_start = pc;
13323
13324   obuf[0] = 0;
13325   for (i = 0; i < MAX_OPERANDS; ++i)
13326     {
13327       op_out[i][0] = 0;
13328       op_index[i] = -1;
13329     }
13330
13331   the_info = info;
13332   start_pc = pc;
13333   start_codep = priv.the_buffer;
13334   codep = priv.the_buffer;
13335
13336   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13337     {
13338       const char *name;
13339
13340       /* Getting here means we tried for data but didn't get it.  That
13341          means we have an incomplete instruction of some sort.  Just
13342          print the first byte as a prefix or a .byte pseudo-op.  */
13343       if (codep > priv.the_buffer)
13344         {
13345           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13346           if (name != NULL)
13347             (*info->fprintf_func) (info->stream, "%s", name);
13348           else
13349             {
13350               /* Just print the first byte as a .byte instruction.  */
13351               (*info->fprintf_func) (info->stream, ".byte 0x%x",
13352                                      (unsigned int) priv.the_buffer[0]);
13353             }
13354
13355           return 1;
13356         }
13357
13358       return -1;
13359     }
13360
13361   obufp = obuf;
13362   sizeflag = priv.orig_sizeflag;
13363
13364   if (!ckprefix () || rex_used)
13365     {
13366       /* Too many prefixes or unused REX prefixes.  */
13367       for (i = 0;
13368            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13369            i++)
13370         (*info->fprintf_func) (info->stream, "%s%s",
13371                                i == 0 ? "" : " ",
13372                                prefix_name (all_prefixes[i], sizeflag));
13373       return i;
13374     }
13375
13376   insn_codep = codep;
13377
13378   FETCH_DATA (info, codep + 1);
13379   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13380
13381   if (((prefixes & PREFIX_FWAIT)
13382        && ((*codep < 0xd8) || (*codep > 0xdf))))
13383     {
13384       /* Handle prefixes before fwait.  */
13385       for (i = 0; i < fwait_prefix && all_prefixes[i];
13386            i++)
13387         (*info->fprintf_func) (info->stream, "%s ",
13388                                prefix_name (all_prefixes[i], sizeflag));
13389       (*info->fprintf_func) (info->stream, "fwait");
13390       return i + 1;
13391     }
13392
13393   if (*codep == 0x0f)
13394     {
13395       unsigned char threebyte;
13396
13397       codep++;
13398       FETCH_DATA (info, codep + 1);
13399       threebyte = *codep;
13400       dp = &dis386_twobyte[threebyte];
13401       need_modrm = twobyte_has_modrm[*codep];
13402       codep++;
13403     }
13404   else
13405     {
13406       dp = &dis386[*codep];
13407       need_modrm = onebyte_has_modrm[*codep];
13408       codep++;
13409     }
13410
13411   /* Save sizeflag for printing the extra prefixes later before updating
13412      it for mnemonic and operand processing.  The prefix names depend
13413      only on the address mode.  */
13414   orig_sizeflag = sizeflag;
13415   if (prefixes & PREFIX_ADDR)
13416     sizeflag ^= AFLAG;
13417   if ((prefixes & PREFIX_DATA))
13418     sizeflag ^= DFLAG;
13419
13420   end_codep = codep;
13421   if (need_modrm)
13422     {
13423       FETCH_DATA (info, codep + 1);
13424       modrm.mod = (*codep >> 6) & 3;
13425       modrm.reg = (*codep >> 3) & 7;
13426       modrm.rm = *codep & 7;
13427     }
13428
13429   need_vex = 0;
13430   need_vex_reg = 0;
13431   vex_w_done = 0;
13432   memset (&vex, 0, sizeof (vex));
13433
13434   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13435     {
13436       get_sib (info, sizeflag);
13437       dofloat (sizeflag);
13438     }
13439   else
13440     {
13441       dp = get_valid_dis386 (dp, info);
13442       if (dp != NULL && putop (dp->name, sizeflag) == 0)
13443         {
13444           get_sib (info, sizeflag);
13445           for (i = 0; i < MAX_OPERANDS; ++i)
13446             {
13447               obufp = op_out[i];
13448               op_ad = MAX_OPERANDS - 1 - i;
13449               if (dp->op[i].rtn)
13450                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13451               /* For EVEX instruction after the last operand masking
13452                  should be printed.  */
13453               if (i == 0 && vex.evex)
13454                 {
13455                   /* Don't print {%k0}.  */
13456                   if (vex.mask_register_specifier)
13457                     {
13458                       oappend ("{");
13459                       oappend (names_mask[vex.mask_register_specifier]);
13460                       oappend ("}");
13461                     }
13462                   if (vex.zeroing)
13463                     oappend ("{z}");
13464                 }
13465             }
13466         }
13467     }
13468
13469   /* Check if the REX prefix is used.  */
13470   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13471     all_prefixes[last_rex_prefix] = 0;
13472
13473   /* Check if the SEG prefix is used.  */
13474   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13475                    | PREFIX_FS | PREFIX_GS)) != 0
13476       && (used_prefixes & active_seg_prefix) != 0)
13477     all_prefixes[last_seg_prefix] = 0;
13478
13479   /* Check if the ADDR prefix is used.  */
13480   if ((prefixes & PREFIX_ADDR) != 0
13481       && (used_prefixes & PREFIX_ADDR) != 0)
13482     all_prefixes[last_addr_prefix] = 0;
13483
13484   /* Check if the DATA prefix is used.  */
13485   if ((prefixes & PREFIX_DATA) != 0
13486       && (used_prefixes & PREFIX_DATA) != 0)
13487     all_prefixes[last_data_prefix] = 0;
13488
13489   /* Print the extra prefixes.  */
13490   prefix_length = 0;
13491   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13492     if (all_prefixes[i])
13493       {
13494         const char *name;
13495         name = prefix_name (all_prefixes[i], orig_sizeflag);
13496         if (name == NULL)
13497           abort ();
13498         prefix_length += strlen (name) + 1;
13499         (*info->fprintf_func) (info->stream, "%s ", name);
13500       }
13501
13502   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13503      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13504      used by putop and MMX/SSE operand and may be overriden by the
13505      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13506      separately.  */
13507   if (dp->prefix_requirement == PREFIX_OPCODE
13508       && dp != &bad_opcode
13509       && (((prefixes
13510             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13511            && (used_prefixes
13512                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13513           || ((((prefixes
13514                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13515                 == PREFIX_DATA)
13516                && (used_prefixes & PREFIX_DATA) == 0))))
13517     {
13518       (*info->fprintf_func) (info->stream, "(bad)");
13519       return end_codep - priv.the_buffer;
13520     }
13521
13522   /* Check maximum code length.  */
13523   if ((codep - start_codep) > MAX_CODE_LENGTH)
13524     {
13525       (*info->fprintf_func) (info->stream, "(bad)");
13526       return MAX_CODE_LENGTH;
13527     }
13528
13529   obufp = mnemonicendp;
13530   for (i = strlen (obuf) + prefix_length; i < 6; i++)
13531     oappend (" ");
13532   oappend (" ");
13533   (*info->fprintf_func) (info->stream, "%s", obuf);
13534
13535   /* The enter and bound instructions are printed with operands in the same
13536      order as the intel book; everything else is printed in reverse order.  */
13537   if (intel_syntax || two_source_ops)
13538     {
13539       bfd_vma riprel;
13540
13541       for (i = 0; i < MAX_OPERANDS; ++i)
13542         op_txt[i] = op_out[i];
13543
13544       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13545           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13546         {
13547           op_txt[2] = op_out[3];
13548           op_txt[3] = op_out[2];
13549         }
13550
13551       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13552         {
13553           op_ad = op_index[i];
13554           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13555           op_index[MAX_OPERANDS - 1 - i] = op_ad;
13556           riprel = op_riprel[i];
13557           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13558           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13559         }
13560     }
13561   else
13562     {
13563       for (i = 0; i < MAX_OPERANDS; ++i)
13564         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13565     }
13566
13567   needcomma = 0;
13568   for (i = 0; i < MAX_OPERANDS; ++i)
13569     if (*op_txt[i])
13570       {
13571         if (needcomma)
13572           (*info->fprintf_func) (info->stream, ",");
13573         if (op_index[i] != -1 && !op_riprel[i])
13574           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13575         else
13576           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13577         needcomma = 1;
13578       }
13579
13580   for (i = 0; i < MAX_OPERANDS; i++)
13581     if (op_index[i] != -1 && op_riprel[i])
13582       {
13583         (*info->fprintf_func) (info->stream, "        # ");
13584         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13585                                                 + op_address[op_index[i]]), info);
13586         break;
13587       }
13588   return codep - priv.the_buffer;
13589 }
13590
13591 static const char *float_mem[] = {
13592   /* d8 */
13593   "fadd{s|}",
13594   "fmul{s|}",
13595   "fcom{s|}",
13596   "fcomp{s|}",
13597   "fsub{s|}",
13598   "fsubr{s|}",
13599   "fdiv{s|}",
13600   "fdivr{s|}",
13601   /* d9 */
13602   "fld{s|}",
13603   "(bad)",
13604   "fst{s|}",
13605   "fstp{s|}",
13606   "fldenvIC",
13607   "fldcw",
13608   "fNstenvIC",
13609   "fNstcw",
13610   /* da */
13611   "fiadd{l|}",
13612   "fimul{l|}",
13613   "ficom{l|}",
13614   "ficomp{l|}",
13615   "fisub{l|}",
13616   "fisubr{l|}",
13617   "fidiv{l|}",
13618   "fidivr{l|}",
13619   /* db */
13620   "fild{l|}",
13621   "fisttp{l|}",
13622   "fist{l|}",
13623   "fistp{l|}",
13624   "(bad)",
13625   "fld{t||t|}",
13626   "(bad)",
13627   "fstp{t||t|}",
13628   /* dc */
13629   "fadd{l|}",
13630   "fmul{l|}",
13631   "fcom{l|}",
13632   "fcomp{l|}",
13633   "fsub{l|}",
13634   "fsubr{l|}",
13635   "fdiv{l|}",
13636   "fdivr{l|}",
13637   /* dd */
13638   "fld{l|}",
13639   "fisttp{ll|}",
13640   "fst{l||}",
13641   "fstp{l|}",
13642   "frstorIC",
13643   "(bad)",
13644   "fNsaveIC",
13645   "fNstsw",
13646   /* de */
13647   "fiadd{s|}",
13648   "fimul{s|}",
13649   "ficom{s|}",
13650   "ficomp{s|}",
13651   "fisub{s|}",
13652   "fisubr{s|}",
13653   "fidiv{s|}",
13654   "fidivr{s|}",
13655   /* df */
13656   "fild{s|}",
13657   "fisttp{s|}",
13658   "fist{s|}",
13659   "fistp{s|}",
13660   "fbld",
13661   "fild{ll|}",
13662   "fbstp",
13663   "fistp{ll|}",
13664 };
13665
13666 static const unsigned char float_mem_mode[] = {
13667   /* d8 */
13668   d_mode,
13669   d_mode,
13670   d_mode,
13671   d_mode,
13672   d_mode,
13673   d_mode,
13674   d_mode,
13675   d_mode,
13676   /* d9 */
13677   d_mode,
13678   0,
13679   d_mode,
13680   d_mode,
13681   0,
13682   w_mode,
13683   0,
13684   w_mode,
13685   /* da */
13686   d_mode,
13687   d_mode,
13688   d_mode,
13689   d_mode,
13690   d_mode,
13691   d_mode,
13692   d_mode,
13693   d_mode,
13694   /* db */
13695   d_mode,
13696   d_mode,
13697   d_mode,
13698   d_mode,
13699   0,
13700   t_mode,
13701   0,
13702   t_mode,
13703   /* dc */
13704   q_mode,
13705   q_mode,
13706   q_mode,
13707   q_mode,
13708   q_mode,
13709   q_mode,
13710   q_mode,
13711   q_mode,
13712   /* dd */
13713   q_mode,
13714   q_mode,
13715   q_mode,
13716   q_mode,
13717   0,
13718   0,
13719   0,
13720   w_mode,
13721   /* de */
13722   w_mode,
13723   w_mode,
13724   w_mode,
13725   w_mode,
13726   w_mode,
13727   w_mode,
13728   w_mode,
13729   w_mode,
13730   /* df */
13731   w_mode,
13732   w_mode,
13733   w_mode,
13734   w_mode,
13735   t_mode,
13736   q_mode,
13737   t_mode,
13738   q_mode
13739 };
13740
13741 #define ST { OP_ST, 0 }
13742 #define STi { OP_STi, 0 }
13743
13744 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13745 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13746 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13747 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13748 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13749 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13750 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13751 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13752 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13753
13754 static const struct dis386 float_reg[][8] = {
13755   /* d8 */
13756   {
13757     { "fadd",   { ST, STi }, 0 },
13758     { "fmul",   { ST, STi }, 0 },
13759     { "fcom",   { STi }, 0 },
13760     { "fcomp",  { STi }, 0 },
13761     { "fsub",   { ST, STi }, 0 },
13762     { "fsubr",  { ST, STi }, 0 },
13763     { "fdiv",   { ST, STi }, 0 },
13764     { "fdivr",  { ST, STi }, 0 },
13765   },
13766   /* d9 */
13767   {
13768     { "fld",    { STi }, 0 },
13769     { "fxch",   { STi }, 0 },
13770     { FGRPd9_2 },
13771     { Bad_Opcode },
13772     { FGRPd9_4 },
13773     { FGRPd9_5 },
13774     { FGRPd9_6 },
13775     { FGRPd9_7 },
13776   },
13777   /* da */
13778   {
13779     { "fcmovb", { ST, STi }, 0 },
13780     { "fcmove", { ST, STi }, 0 },
13781     { "fcmovbe",{ ST, STi }, 0 },
13782     { "fcmovu", { ST, STi }, 0 },
13783     { Bad_Opcode },
13784     { FGRPda_5 },
13785     { Bad_Opcode },
13786     { Bad_Opcode },
13787   },
13788   /* db */
13789   {
13790     { "fcmovnb",{ ST, STi }, 0 },
13791     { "fcmovne",{ ST, STi }, 0 },
13792     { "fcmovnbe",{ ST, STi }, 0 },
13793     { "fcmovnu",{ ST, STi }, 0 },
13794     { FGRPdb_4 },
13795     { "fucomi", { ST, STi }, 0 },
13796     { "fcomi",  { ST, STi }, 0 },
13797     { Bad_Opcode },
13798   },
13799   /* dc */
13800   {
13801     { "fadd",   { STi, ST }, 0 },
13802     { "fmul",   { STi, ST }, 0 },
13803     { Bad_Opcode },
13804     { Bad_Opcode },
13805     { "fsub{!M|r}",     { STi, ST }, 0 },
13806     { "fsub{M|}",       { STi, ST }, 0 },
13807     { "fdiv{!M|r}",     { STi, ST }, 0 },
13808     { "fdiv{M|}",       { STi, ST }, 0 },
13809   },
13810   /* dd */
13811   {
13812     { "ffree",  { STi }, 0 },
13813     { Bad_Opcode },
13814     { "fst",    { STi }, 0 },
13815     { "fstp",   { STi }, 0 },
13816     { "fucom",  { STi }, 0 },
13817     { "fucomp", { STi }, 0 },
13818     { Bad_Opcode },
13819     { Bad_Opcode },
13820   },
13821   /* de */
13822   {
13823     { "faddp",  { STi, ST }, 0 },
13824     { "fmulp",  { STi, ST }, 0 },
13825     { Bad_Opcode },
13826     { FGRPde_3 },
13827     { "fsub{!M|r}p",    { STi, ST }, 0 },
13828     { "fsub{M|}p",      { STi, ST }, 0 },
13829     { "fdiv{!M|r}p",    { STi, ST }, 0 },
13830     { "fdiv{M|}p",      { STi, ST }, 0 },
13831   },
13832   /* df */
13833   {
13834     { "ffreep", { STi }, 0 },
13835     { Bad_Opcode },
13836     { Bad_Opcode },
13837     { Bad_Opcode },
13838     { FGRPdf_4 },
13839     { "fucomip", { ST, STi }, 0 },
13840     { "fcomip", { ST, STi }, 0 },
13841     { Bad_Opcode },
13842   },
13843 };
13844
13845 static char *fgrps[][8] = {
13846   /* Bad opcode 0 */
13847   {
13848     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13849   },
13850
13851   /* d9_2  1 */
13852   {
13853     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13854   },
13855
13856   /* d9_4  2 */
13857   {
13858     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13859   },
13860
13861   /* d9_5  3 */
13862   {
13863     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13864   },
13865
13866   /* d9_6  4 */
13867   {
13868     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13869   },
13870
13871   /* d9_7  5 */
13872   {
13873     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13874   },
13875
13876   /* da_5  6 */
13877   {
13878     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13879   },
13880
13881   /* db_4  7 */
13882   {
13883     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13884     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13885   },
13886
13887   /* de_3  8 */
13888   {
13889     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13890   },
13891
13892   /* df_4  9 */
13893   {
13894     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13895   },
13896 };
13897
13898 static void
13899 swap_operand (void)
13900 {
13901   mnemonicendp[0] = '.';
13902   mnemonicendp[1] = 's';
13903   mnemonicendp += 2;
13904 }
13905
13906 static void
13907 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13908                int sizeflag ATTRIBUTE_UNUSED)
13909 {
13910   /* Skip mod/rm byte.  */
13911   MODRM_CHECK;
13912   codep++;
13913 }
13914
13915 static void
13916 dofloat (int sizeflag)
13917 {
13918   const struct dis386 *dp;
13919   unsigned char floatop;
13920
13921   floatop = codep[-1];
13922
13923   if (modrm.mod != 3)
13924     {
13925       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13926
13927       putop (float_mem[fp_indx], sizeflag);
13928       obufp = op_out[0];
13929       op_ad = 2;
13930       OP_E (float_mem_mode[fp_indx], sizeflag);
13931       return;
13932     }
13933   /* Skip mod/rm byte.  */
13934   MODRM_CHECK;
13935   codep++;
13936
13937   dp = &float_reg[floatop - 0xd8][modrm.reg];
13938   if (dp->name == NULL)
13939     {
13940       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13941
13942       /* Instruction fnstsw is only one with strange arg.  */
13943       if (floatop == 0xdf && codep[-1] == 0xe0)
13944         strcpy (op_out[0], names16[0]);
13945     }
13946   else
13947     {
13948       putop (dp->name, sizeflag);
13949
13950       obufp = op_out[0];
13951       op_ad = 2;
13952       if (dp->op[0].rtn)
13953         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13954
13955       obufp = op_out[1];
13956       op_ad = 1;
13957       if (dp->op[1].rtn)
13958         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13959     }
13960 }
13961
13962 /* Like oappend (below), but S is a string starting with '%'.
13963    In Intel syntax, the '%' is elided.  */
13964 static void
13965 oappend_maybe_intel (const char *s)
13966 {
13967   oappend (s + intel_syntax);
13968 }
13969
13970 static void
13971 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13972 {
13973   oappend_maybe_intel ("%st");
13974 }
13975
13976 static void
13977 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13978 {
13979   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13980   oappend_maybe_intel (scratchbuf);
13981 }
13982
13983 /* Capital letters in template are macros.  */
13984 static int
13985 putop (const char *in_template, int sizeflag)
13986 {
13987   const char *p;
13988   int alt = 0;
13989   int cond = 1;
13990   unsigned int l = 0, len = 1;
13991   char last[4];
13992
13993 #define SAVE_LAST(c)                    \
13994   if (l < len && l < sizeof (last))     \
13995     last[l++] = c;                      \
13996   else                                  \
13997     abort ();
13998
13999   for (p = in_template; *p; p++)
14000     {
14001       switch (*p)
14002         {
14003         default:
14004           *obufp++ = *p;
14005           break;
14006         case '%':
14007           len++;
14008           break;
14009         case '!':
14010           cond = 0;
14011           break;
14012         case '{':
14013           if (intel_syntax)
14014             {
14015               while (*++p != '|')
14016                 if (*p == '}' || *p == '\0')
14017                   abort ();
14018             }
14019           /* Fall through.  */
14020         case 'I':
14021           alt = 1;
14022           continue;
14023         case '|':
14024           while (*++p != '}')
14025             {
14026               if (*p == '\0')
14027                 abort ();
14028             }
14029           break;
14030         case '}':
14031           break;
14032         case 'A':
14033           if (intel_syntax)
14034             break;
14035           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14036             *obufp++ = 'b';
14037           break;
14038         case 'B':
14039           if (l == 0 && len == 1)
14040             {
14041 case_B:
14042               if (intel_syntax)
14043                 break;
14044               if (sizeflag & SUFFIX_ALWAYS)
14045                 *obufp++ = 'b';
14046             }
14047           else
14048             {
14049               if (l != 1
14050                   || len != 2
14051                   || last[0] != 'L')
14052                 {
14053                   SAVE_LAST (*p);
14054                   break;
14055                 }
14056
14057               if (address_mode == mode_64bit
14058                   && !(prefixes & PREFIX_ADDR))
14059                 {
14060                   *obufp++ = 'a';
14061                   *obufp++ = 'b';
14062                   *obufp++ = 's';
14063                 }
14064
14065               goto case_B;
14066             }
14067           break;
14068         case 'C':
14069           if (intel_syntax && !alt)
14070             break;
14071           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14072             {
14073               if (sizeflag & DFLAG)
14074                 *obufp++ = intel_syntax ? 'd' : 'l';
14075               else
14076                 *obufp++ = intel_syntax ? 'w' : 's';
14077               used_prefixes |= (prefixes & PREFIX_DATA);
14078             }
14079           break;
14080         case 'D':
14081           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14082             break;
14083           USED_REX (REX_W);
14084           if (modrm.mod == 3)
14085             {
14086               if (rex & REX_W)
14087                 *obufp++ = 'q';
14088               else
14089                 {
14090                   if (sizeflag & DFLAG)
14091                     *obufp++ = intel_syntax ? 'd' : 'l';
14092                   else
14093                     *obufp++ = 'w';
14094                   used_prefixes |= (prefixes & PREFIX_DATA);
14095                 }
14096             }
14097           else
14098             *obufp++ = 'w';
14099           break;
14100         case 'E':               /* For jcxz/jecxz */
14101           if (address_mode == mode_64bit)
14102             {
14103               if (sizeflag & AFLAG)
14104                 *obufp++ = 'r';
14105               else
14106                 *obufp++ = 'e';
14107             }
14108           else
14109             if (sizeflag & AFLAG)
14110               *obufp++ = 'e';
14111           used_prefixes |= (prefixes & PREFIX_ADDR);
14112           break;
14113         case 'F':
14114           if (intel_syntax)
14115             break;
14116           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14117             {
14118               if (sizeflag & AFLAG)
14119                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14120               else
14121                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14122               used_prefixes |= (prefixes & PREFIX_ADDR);
14123             }
14124           break;
14125         case 'G':
14126           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14127             break;
14128           if ((rex & REX_W) || (sizeflag & DFLAG))
14129             *obufp++ = 'l';
14130           else
14131             *obufp++ = 'w';
14132           if (!(rex & REX_W))
14133             used_prefixes |= (prefixes & PREFIX_DATA);
14134           break;
14135         case 'H':
14136           if (intel_syntax)
14137             break;
14138           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14139               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14140             {
14141               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14142               *obufp++ = ',';
14143               *obufp++ = 'p';
14144               if (prefixes & PREFIX_DS)
14145                 *obufp++ = 't';
14146               else
14147                 *obufp++ = 'n';
14148             }
14149           break;
14150         case 'J':
14151           if (intel_syntax)
14152             break;
14153           *obufp++ = 'l';
14154           break;
14155         case 'K':
14156           USED_REX (REX_W);
14157           if (rex & REX_W)
14158             *obufp++ = 'q';
14159           else
14160             *obufp++ = 'd';
14161           break;
14162         case 'Z':
14163           if (l != 0 || len != 1)
14164             {
14165               if (l != 1 || len != 2 || last[0] != 'X')
14166                 {
14167                   SAVE_LAST (*p);
14168                   break;
14169                 }
14170               if (!need_vex || !vex.evex)
14171                 abort ();
14172               if (intel_syntax
14173                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14174                 break;
14175               switch (vex.length)
14176                 {
14177                 case 128:
14178                   *obufp++ = 'x';
14179                   break;
14180                 case 256:
14181                   *obufp++ = 'y';
14182                   break;
14183                 case 512:
14184                   *obufp++ = 'z';
14185                   break;
14186                 default:
14187                   abort ();
14188                 }
14189               break;
14190             }
14191           if (intel_syntax)
14192             break;
14193           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14194             {
14195               *obufp++ = 'q';
14196               break;
14197             }
14198           /* Fall through.  */
14199           goto case_L;
14200         case 'L':
14201           if (l != 0 || len != 1)
14202             {
14203               SAVE_LAST (*p);
14204               break;
14205             }
14206 case_L:
14207           if (intel_syntax)
14208             break;
14209           if (sizeflag & SUFFIX_ALWAYS)
14210             *obufp++ = 'l';
14211           break;
14212         case 'M':
14213           if (intel_mnemonic != cond)
14214             *obufp++ = 'r';
14215           break;
14216         case 'N':
14217           if ((prefixes & PREFIX_FWAIT) == 0)
14218             *obufp++ = 'n';
14219           else
14220             used_prefixes |= PREFIX_FWAIT;
14221           break;
14222         case 'O':
14223           USED_REX (REX_W);
14224           if (rex & REX_W)
14225             *obufp++ = 'o';
14226           else if (intel_syntax && (sizeflag & DFLAG))
14227             *obufp++ = 'q';
14228           else
14229             *obufp++ = 'd';
14230           if (!(rex & REX_W))
14231             used_prefixes |= (prefixes & PREFIX_DATA);
14232           break;
14233         case '&':
14234           if (!intel_syntax
14235               && address_mode == mode_64bit
14236               && isa64 == intel64)
14237             {
14238               *obufp++ = 'q';
14239               break;
14240             }
14241           /* Fall through.  */
14242         case 'T':
14243           if (!intel_syntax
14244               && address_mode == mode_64bit
14245               && ((sizeflag & DFLAG) || (rex & REX_W)))
14246             {
14247               *obufp++ = 'q';
14248               break;
14249             }
14250           /* Fall through.  */
14251           goto case_P;
14252         case 'P':
14253           if (l == 0 && len == 1)
14254             {
14255 case_P:
14256               if (intel_syntax)
14257                 {
14258                   if ((rex & REX_W) == 0
14259                       && (prefixes & PREFIX_DATA))
14260                     {
14261                       if ((sizeflag & DFLAG) == 0)
14262                         *obufp++ = 'w';
14263                       used_prefixes |= (prefixes & PREFIX_DATA);
14264                     }
14265                   break;
14266                 }
14267               if ((prefixes & PREFIX_DATA)
14268                   || (rex & REX_W)
14269                   || (sizeflag & SUFFIX_ALWAYS))
14270                 {
14271                   USED_REX (REX_W);
14272                   if (rex & REX_W)
14273                     *obufp++ = 'q';
14274                   else
14275                     {
14276                       if (sizeflag & DFLAG)
14277                         *obufp++ = 'l';
14278                       else
14279                         *obufp++ = 'w';
14280                       used_prefixes |= (prefixes & PREFIX_DATA);
14281                     }
14282                 }
14283             }
14284           else
14285             {
14286               if (l != 1 || len != 2 || last[0] != 'L')
14287                 {
14288                   SAVE_LAST (*p);
14289                   break;
14290                 }
14291
14292               if ((prefixes & PREFIX_DATA)
14293                   || (rex & REX_W)
14294                   || (sizeflag & SUFFIX_ALWAYS))
14295                 {
14296                   USED_REX (REX_W);
14297                   if (rex & REX_W)
14298                     *obufp++ = 'q';
14299                   else
14300                     {
14301                       if (sizeflag & DFLAG)
14302                         *obufp++ = intel_syntax ? 'd' : 'l';
14303                       else
14304                         *obufp++ = 'w';
14305                       used_prefixes |= (prefixes & PREFIX_DATA);
14306                     }
14307                 }
14308             }
14309           break;
14310         case 'U':
14311           if (intel_syntax)
14312             break;
14313           if (address_mode == mode_64bit
14314               && ((sizeflag & DFLAG) || (rex & REX_W)))
14315             {
14316               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14317                 *obufp++ = 'q';
14318               break;
14319             }
14320           /* Fall through.  */
14321           goto case_Q;
14322         case 'Q':
14323           if (l == 0 && len == 1)
14324             {
14325 case_Q:
14326               if (intel_syntax && !alt)
14327                 break;
14328               USED_REX (REX_W);
14329               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14330                 {
14331                   if (rex & REX_W)
14332                     *obufp++ = 'q';
14333                   else
14334                     {
14335                       if (sizeflag & DFLAG)
14336                         *obufp++ = intel_syntax ? 'd' : 'l';
14337                       else
14338                         *obufp++ = 'w';
14339                       used_prefixes |= (prefixes & PREFIX_DATA);
14340                     }
14341                 }
14342             }
14343           else
14344             {
14345               if (l != 1 || len != 2 || last[0] != 'L')
14346                 {
14347                   SAVE_LAST (*p);
14348                   break;
14349                 }
14350               if (intel_syntax
14351                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14352                 break;
14353               if ((rex & REX_W))
14354                 {
14355                   USED_REX (REX_W);
14356                   *obufp++ = 'q';
14357                 }
14358               else
14359                 *obufp++ = 'l';
14360             }
14361           break;
14362         case 'R':
14363           USED_REX (REX_W);
14364           if (rex & REX_W)
14365             *obufp++ = 'q';
14366           else if (sizeflag & DFLAG)
14367             {
14368               if (intel_syntax)
14369                   *obufp++ = 'd';
14370               else
14371                   *obufp++ = 'l';
14372             }
14373           else
14374             *obufp++ = 'w';
14375           if (intel_syntax && !p[1]
14376               && ((rex & REX_W) || (sizeflag & DFLAG)))
14377             *obufp++ = 'e';
14378           if (!(rex & REX_W))
14379             used_prefixes |= (prefixes & PREFIX_DATA);
14380           break;
14381         case 'V':
14382           if (l == 0 && len == 1)
14383             {
14384               if (intel_syntax)
14385                 break;
14386               if (address_mode == mode_64bit
14387                   && ((sizeflag & DFLAG) || (rex & REX_W)))
14388                 {
14389                   if (sizeflag & SUFFIX_ALWAYS)
14390                     *obufp++ = 'q';
14391                   break;
14392                 }
14393             }
14394           else
14395             {
14396               if (l != 1
14397                   || len != 2
14398                   || last[0] != 'L')
14399                 {
14400                   SAVE_LAST (*p);
14401                   break;
14402                 }
14403
14404               if (rex & REX_W)
14405                 {
14406                   *obufp++ = 'a';
14407                   *obufp++ = 'b';
14408                   *obufp++ = 's';
14409                 }
14410             }
14411           /* Fall through.  */
14412           goto case_S;
14413         case 'S':
14414           if (l == 0 && len == 1)
14415             {
14416 case_S:
14417               if (intel_syntax)
14418                 break;
14419               if (sizeflag & SUFFIX_ALWAYS)
14420                 {
14421                   if (rex & REX_W)
14422                     *obufp++ = 'q';
14423                   else
14424                     {
14425                       if (sizeflag & DFLAG)
14426                         *obufp++ = 'l';
14427                       else
14428                         *obufp++ = 'w';
14429                       used_prefixes |= (prefixes & PREFIX_DATA);
14430                     }
14431                 }
14432             }
14433           else
14434             {
14435               if (l != 1
14436                   || len != 2
14437                   || last[0] != 'L')
14438                 {
14439                   SAVE_LAST (*p);
14440                   break;
14441                 }
14442
14443               if (address_mode == mode_64bit
14444                   && !(prefixes & PREFIX_ADDR))
14445                 {
14446                   *obufp++ = 'a';
14447                   *obufp++ = 'b';
14448                   *obufp++ = 's';
14449                 }
14450
14451               goto case_S;
14452             }
14453           break;
14454         case 'X':
14455           if (l != 0 || len != 1)
14456             {
14457               SAVE_LAST (*p);
14458               break;
14459             }
14460           if (need_vex && vex.prefix)
14461             {
14462               if (vex.prefix == DATA_PREFIX_OPCODE)
14463                 *obufp++ = 'd';
14464               else
14465                 *obufp++ = 's';
14466             }
14467           else
14468             {
14469               if (prefixes & PREFIX_DATA)
14470                 *obufp++ = 'd';
14471               else
14472                 *obufp++ = 's';
14473               used_prefixes |= (prefixes & PREFIX_DATA);
14474             }
14475           break;
14476         case 'Y':
14477           if (l == 0 && len == 1)
14478             abort ();
14479           else
14480             {
14481               if (l != 1 || len != 2 || last[0] != 'X')
14482                 {
14483                   SAVE_LAST (*p);
14484                   break;
14485                 }
14486               if (!need_vex)
14487                 abort ();
14488               if (intel_syntax
14489                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14490                 break;
14491               switch (vex.length)
14492                 {
14493                 case 128:
14494                   *obufp++ = 'x';
14495                   break;
14496                 case 256:
14497                   *obufp++ = 'y';
14498                   break;
14499                 case 512:
14500                   if (!vex.evex)
14501                 default:
14502                     abort ();
14503                 }
14504             }
14505           break;
14506         case 'W':
14507           if (l == 0 && len == 1)
14508             {
14509               /* operand size flag for cwtl, cbtw */
14510               USED_REX (REX_W);
14511               if (rex & REX_W)
14512                 {
14513                   if (intel_syntax)
14514                     *obufp++ = 'd';
14515                   else
14516                     *obufp++ = 'l';
14517                 }
14518               else if (sizeflag & DFLAG)
14519                 *obufp++ = 'w';
14520               else
14521                 *obufp++ = 'b';
14522               if (!(rex & REX_W))
14523                 used_prefixes |= (prefixes & PREFIX_DATA);
14524             }
14525           else
14526             {
14527               if (l != 1
14528                   || len != 2
14529                   || (last[0] != 'X'
14530                       && last[0] != 'L'))
14531                 {
14532                   SAVE_LAST (*p);
14533                   break;
14534                 }
14535               if (!need_vex)
14536                 abort ();
14537               if (last[0] == 'X')
14538                 *obufp++ = vex.w ? 'd': 's';
14539               else
14540                 *obufp++ = vex.w ? 'q': 'd';
14541             }
14542           break;
14543         case '^':
14544           if (intel_syntax)
14545             break;
14546           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14547             {
14548               if (sizeflag & DFLAG)
14549                 *obufp++ = 'l';
14550               else
14551                 *obufp++ = 'w';
14552               used_prefixes |= (prefixes & PREFIX_DATA);
14553             }
14554           break;
14555         case '@':
14556           if (intel_syntax)
14557             break;
14558           if (address_mode == mode_64bit
14559               && (isa64 == intel64
14560                   || ((sizeflag & DFLAG) || (rex & REX_W))))
14561               *obufp++ = 'q';
14562           else if ((prefixes & PREFIX_DATA))
14563             {
14564               if (!(sizeflag & DFLAG))
14565                 *obufp++ = 'w';
14566               used_prefixes |= (prefixes & PREFIX_DATA);
14567             }
14568           break;
14569         }
14570       alt = 0;
14571     }
14572   *obufp = 0;
14573   mnemonicendp = obufp;
14574   return 0;
14575 }
14576
14577 static void
14578 oappend (const char *s)
14579 {
14580   obufp = stpcpy (obufp, s);
14581 }
14582
14583 static void
14584 append_seg (void)
14585 {
14586   /* Only print the active segment register.  */
14587   if (!active_seg_prefix)
14588     return;
14589
14590   used_prefixes |= active_seg_prefix;
14591   switch (active_seg_prefix)
14592     {
14593     case PREFIX_CS:
14594       oappend_maybe_intel ("%cs:");
14595       break;
14596     case PREFIX_DS:
14597       oappend_maybe_intel ("%ds:");
14598       break;
14599     case PREFIX_SS:
14600       oappend_maybe_intel ("%ss:");
14601       break;
14602     case PREFIX_ES:
14603       oappend_maybe_intel ("%es:");
14604       break;
14605     case PREFIX_FS:
14606       oappend_maybe_intel ("%fs:");
14607       break;
14608     case PREFIX_GS:
14609       oappend_maybe_intel ("%gs:");
14610       break;
14611     default:
14612       break;
14613     }
14614 }
14615
14616 static void
14617 OP_indirE (int bytemode, int sizeflag)
14618 {
14619   if (!intel_syntax)
14620     oappend ("*");
14621   OP_E (bytemode, sizeflag);
14622 }
14623
14624 static void
14625 print_operand_value (char *buf, int hex, bfd_vma disp)
14626 {
14627   if (address_mode == mode_64bit)
14628     {
14629       if (hex)
14630         {
14631           char tmp[30];
14632           int i;
14633           buf[0] = '0';
14634           buf[1] = 'x';
14635           sprintf_vma (tmp, disp);
14636           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14637           strcpy (buf + 2, tmp + i);
14638         }
14639       else
14640         {
14641           bfd_signed_vma v = disp;
14642           char tmp[30];
14643           int i;
14644           if (v < 0)
14645             {
14646               *(buf++) = '-';
14647               v = -disp;
14648               /* Check for possible overflow on 0x8000000000000000.  */
14649               if (v < 0)
14650                 {
14651                   strcpy (buf, "9223372036854775808");
14652                   return;
14653                 }
14654             }
14655           if (!v)
14656             {
14657               strcpy (buf, "0");
14658               return;
14659             }
14660
14661           i = 0;
14662           tmp[29] = 0;
14663           while (v)
14664             {
14665               tmp[28 - i] = (v % 10) + '0';
14666               v /= 10;
14667               i++;
14668             }
14669           strcpy (buf, tmp + 29 - i);
14670         }
14671     }
14672   else
14673     {
14674       if (hex)
14675         sprintf (buf, "0x%x", (unsigned int) disp);
14676       else
14677         sprintf (buf, "%d", (int) disp);
14678     }
14679 }
14680
14681 /* Put DISP in BUF as signed hex number.  */
14682
14683 static void
14684 print_displacement (char *buf, bfd_vma disp)
14685 {
14686   bfd_signed_vma val = disp;
14687   char tmp[30];
14688   int i, j = 0;
14689
14690   if (val < 0)
14691     {
14692       buf[j++] = '-';
14693       val = -disp;
14694
14695       /* Check for possible overflow.  */
14696       if (val < 0)
14697         {
14698           switch (address_mode)
14699             {
14700             case mode_64bit:
14701               strcpy (buf + j, "0x8000000000000000");
14702               break;
14703             case mode_32bit:
14704               strcpy (buf + j, "0x80000000");
14705               break;
14706             case mode_16bit:
14707               strcpy (buf + j, "0x8000");
14708               break;
14709             }
14710           return;
14711         }
14712     }
14713
14714   buf[j++] = '0';
14715   buf[j++] = 'x';
14716
14717   sprintf_vma (tmp, (bfd_vma) val);
14718   for (i = 0; tmp[i] == '0'; i++)
14719     continue;
14720   if (tmp[i] == '\0')
14721     i--;
14722   strcpy (buf + j, tmp + i);
14723 }
14724
14725 static void
14726 intel_operand_size (int bytemode, int sizeflag)
14727 {
14728   if (vex.evex
14729       && vex.b
14730       && (bytemode == x_mode
14731           || bytemode == evex_half_bcst_xmmq_mode))
14732     {
14733       if (vex.w)
14734         oappend ("QWORD PTR ");
14735       else
14736         oappend ("DWORD PTR ");
14737       return;
14738     }
14739   switch (bytemode)
14740     {
14741     case b_mode:
14742     case b_swap_mode:
14743     case dqb_mode:
14744     case db_mode:
14745       oappend ("BYTE PTR ");
14746       break;
14747     case w_mode:
14748     case dw_mode:
14749     case dqw_mode:
14750       oappend ("WORD PTR ");
14751       break;
14752     case indir_v_mode:
14753       if (address_mode == mode_64bit && isa64 == intel64)
14754         {
14755           oappend ("QWORD PTR ");
14756           break;
14757         }
14758       /* Fall through.  */
14759     case stack_v_mode:
14760       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14761         {
14762           oappend ("QWORD PTR ");
14763           break;
14764         }
14765       /* Fall through.  */
14766     case v_mode:
14767     case v_swap_mode:
14768     case dq_mode:
14769       USED_REX (REX_W);
14770       if (rex & REX_W)
14771         oappend ("QWORD PTR ");
14772       else
14773         {
14774           if ((sizeflag & DFLAG) || bytemode == dq_mode)
14775             oappend ("DWORD PTR ");
14776           else
14777             oappend ("WORD PTR ");
14778           used_prefixes |= (prefixes & PREFIX_DATA);
14779         }
14780       break;
14781     case z_mode:
14782       if ((rex & REX_W) || (sizeflag & DFLAG))
14783         *obufp++ = 'D';
14784       oappend ("WORD PTR ");
14785       if (!(rex & REX_W))
14786         used_prefixes |= (prefixes & PREFIX_DATA);
14787       break;
14788     case a_mode:
14789       if (sizeflag & DFLAG)
14790         oappend ("QWORD PTR ");
14791       else
14792         oappend ("DWORD PTR ");
14793       used_prefixes |= (prefixes & PREFIX_DATA);
14794       break;
14795     case d_mode:
14796     case d_scalar_mode:
14797     case d_scalar_swap_mode:
14798     case d_swap_mode:
14799     case dqd_mode:
14800       oappend ("DWORD PTR ");
14801       break;
14802     case q_mode:
14803     case q_scalar_mode:
14804     case q_scalar_swap_mode:
14805     case q_swap_mode:
14806       oappend ("QWORD PTR ");
14807       break;
14808     case m_mode:
14809       if (address_mode == mode_64bit)
14810         oappend ("QWORD PTR ");
14811       else
14812         oappend ("DWORD PTR ");
14813       break;
14814     case f_mode:
14815       if (sizeflag & DFLAG)
14816         oappend ("FWORD PTR ");
14817       else
14818         oappend ("DWORD PTR ");
14819       used_prefixes |= (prefixes & PREFIX_DATA);
14820       break;
14821     case t_mode:
14822       oappend ("TBYTE PTR ");
14823       break;
14824     case x_mode:
14825     case x_swap_mode:
14826     case evex_x_gscat_mode:
14827     case evex_x_nobcst_mode:
14828     case b_scalar_mode:
14829     case w_scalar_mode:
14830       if (need_vex)
14831         {
14832           switch (vex.length)
14833             {
14834             case 128:
14835               oappend ("XMMWORD PTR ");
14836               break;
14837             case 256:
14838               oappend ("YMMWORD PTR ");
14839               break;
14840             case 512:
14841               oappend ("ZMMWORD PTR ");
14842               break;
14843             default:
14844               abort ();
14845             }
14846         }
14847       else
14848         oappend ("XMMWORD PTR ");
14849       break;
14850     case xmm_mode:
14851       oappend ("XMMWORD PTR ");
14852       break;
14853     case ymm_mode:
14854       oappend ("YMMWORD PTR ");
14855       break;
14856     case xmmq_mode:
14857     case evex_half_bcst_xmmq_mode:
14858       if (!need_vex)
14859         abort ();
14860
14861       switch (vex.length)
14862         {
14863         case 128:
14864           oappend ("QWORD PTR ");
14865           break;
14866         case 256:
14867           oappend ("XMMWORD PTR ");
14868           break;
14869         case 512:
14870           oappend ("YMMWORD PTR ");
14871           break;
14872         default:
14873           abort ();
14874         }
14875       break;
14876     case xmm_mb_mode:
14877       if (!need_vex)
14878         abort ();
14879
14880       switch (vex.length)
14881         {
14882         case 128:
14883         case 256:
14884         case 512:
14885           oappend ("BYTE PTR ");
14886           break;
14887         default:
14888           abort ();
14889         }
14890       break;
14891     case xmm_mw_mode:
14892       if (!need_vex)
14893         abort ();
14894
14895       switch (vex.length)
14896         {
14897         case 128:
14898         case 256:
14899         case 512:
14900           oappend ("WORD PTR ");
14901           break;
14902         default:
14903           abort ();
14904         }
14905       break;
14906     case xmm_md_mode:
14907       if (!need_vex)
14908         abort ();
14909
14910       switch (vex.length)
14911         {
14912         case 128:
14913         case 256:
14914         case 512:
14915           oappend ("DWORD PTR ");
14916           break;
14917         default:
14918           abort ();
14919         }
14920       break;
14921     case xmm_mq_mode:
14922       if (!need_vex)
14923         abort ();
14924
14925       switch (vex.length)
14926         {
14927         case 128:
14928         case 256:
14929         case 512:
14930           oappend ("QWORD PTR ");
14931           break;
14932         default:
14933           abort ();
14934         }
14935       break;
14936     case xmmdw_mode:
14937       if (!need_vex)
14938         abort ();
14939
14940       switch (vex.length)
14941         {
14942         case 128:
14943           oappend ("WORD PTR ");
14944           break;
14945         case 256:
14946           oappend ("DWORD PTR ");
14947           break;
14948         case 512:
14949           oappend ("QWORD PTR ");
14950           break;
14951         default:
14952           abort ();
14953         }
14954       break;
14955     case xmmqd_mode:
14956       if (!need_vex)
14957         abort ();
14958
14959       switch (vex.length)
14960         {
14961         case 128:
14962           oappend ("DWORD PTR ");
14963           break;
14964         case 256:
14965           oappend ("QWORD PTR ");
14966           break;
14967         case 512:
14968           oappend ("XMMWORD PTR ");
14969           break;
14970         default:
14971           abort ();
14972         }
14973       break;
14974     case ymmq_mode:
14975       if (!need_vex)
14976         abort ();
14977
14978       switch (vex.length)
14979         {
14980         case 128:
14981           oappend ("QWORD PTR ");
14982           break;
14983         case 256:
14984           oappend ("YMMWORD PTR ");
14985           break;
14986         case 512:
14987           oappend ("ZMMWORD PTR ");
14988           break;
14989         default:
14990           abort ();
14991         }
14992       break;
14993     case ymmxmm_mode:
14994       if (!need_vex)
14995         abort ();
14996
14997       switch (vex.length)
14998         {
14999         case 128:
15000         case 256:
15001           oappend ("XMMWORD PTR ");
15002           break;
15003         default:
15004           abort ();
15005         }
15006       break;
15007     case o_mode:
15008       oappend ("OWORD PTR ");
15009       break;
15010     case xmm_mdq_mode:
15011     case vex_w_dq_mode:
15012     case vex_scalar_w_dq_mode:
15013       if (!need_vex)
15014         abort ();
15015
15016       if (vex.w)
15017         oappend ("QWORD PTR ");
15018       else
15019         oappend ("DWORD PTR ");
15020       break;
15021     case vex_vsib_d_w_dq_mode:
15022     case vex_vsib_q_w_dq_mode:
15023       if (!need_vex)
15024         abort ();
15025
15026       if (!vex.evex)
15027         {
15028           if (vex.w)
15029             oappend ("QWORD PTR ");
15030           else
15031             oappend ("DWORD PTR ");
15032         }
15033       else
15034         {
15035           switch (vex.length)
15036             {
15037             case 128:
15038               oappend ("XMMWORD PTR ");
15039               break;
15040             case 256:
15041               oappend ("YMMWORD PTR ");
15042               break;
15043             case 512:
15044               oappend ("ZMMWORD PTR ");
15045               break;
15046             default:
15047               abort ();
15048             }
15049         }
15050       break;
15051     case vex_vsib_q_w_d_mode:
15052     case vex_vsib_d_w_d_mode:
15053       if (!need_vex || !vex.evex)
15054         abort ();
15055
15056       switch (vex.length)
15057         {
15058         case 128:
15059           oappend ("QWORD PTR ");
15060           break;
15061         case 256:
15062           oappend ("XMMWORD PTR ");
15063           break;
15064         case 512:
15065           oappend ("YMMWORD PTR ");
15066           break;
15067         default:
15068           abort ();
15069         }
15070
15071       break;
15072     case mask_bd_mode:
15073       if (!need_vex || vex.length != 128)
15074         abort ();
15075       if (vex.w)
15076         oappend ("DWORD PTR ");
15077       else
15078         oappend ("BYTE PTR ");
15079       break;
15080     case mask_mode:
15081       if (!need_vex)
15082         abort ();
15083       if (vex.w)
15084         oappend ("QWORD PTR ");
15085       else
15086         oappend ("WORD PTR ");
15087       break;
15088     case v_bnd_mode:
15089     case v_bndmk_mode:
15090     default:
15091       break;
15092     }
15093 }
15094
15095 static void
15096 OP_E_register (int bytemode, int sizeflag)
15097 {
15098   int reg = modrm.rm;
15099   const char **names;
15100
15101   USED_REX (REX_B);
15102   if ((rex & REX_B))
15103     reg += 8;
15104
15105   if ((sizeflag & SUFFIX_ALWAYS)
15106       && (bytemode == b_swap_mode
15107           || bytemode == bnd_swap_mode
15108           || bytemode == v_swap_mode))
15109     swap_operand ();
15110
15111   switch (bytemode)
15112     {
15113     case b_mode:
15114     case b_swap_mode:
15115       USED_REX (0);
15116       if (rex)
15117         names = names8rex;
15118       else
15119         names = names8;
15120       break;
15121     case w_mode:
15122       names = names16;
15123       break;
15124     case d_mode:
15125     case dw_mode:
15126     case db_mode:
15127       names = names32;
15128       break;
15129     case q_mode:
15130       names = names64;
15131       break;
15132     case m_mode:
15133     case v_bnd_mode:
15134       names = address_mode == mode_64bit ? names64 : names32;
15135       break;
15136     case bnd_mode:
15137     case bnd_swap_mode:
15138       if (reg > 0x3)
15139         {
15140           oappend ("(bad)");
15141           return;
15142         }
15143       names = names_bnd;
15144       break;
15145     case indir_v_mode:
15146       if (address_mode == mode_64bit && isa64 == intel64)
15147         {
15148           names = names64;
15149           break;
15150         }
15151       /* Fall through.  */
15152     case stack_v_mode:
15153       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15154         {
15155           names = names64;
15156           break;
15157         }
15158       bytemode = v_mode;
15159       /* Fall through.  */
15160     case v_mode:
15161     case v_swap_mode:
15162     case dq_mode:
15163     case dqb_mode:
15164     case dqd_mode:
15165     case dqw_mode:
15166       USED_REX (REX_W);
15167       if (rex & REX_W)
15168         names = names64;
15169       else
15170         {
15171           if ((sizeflag & DFLAG)
15172               || (bytemode != v_mode
15173                   && bytemode != v_swap_mode))
15174             names = names32;
15175           else
15176             names = names16;
15177           used_prefixes |= (prefixes & PREFIX_DATA);
15178         }
15179       break;
15180     case va_mode:
15181       names = (address_mode == mode_64bit
15182                ? names64 : names32);
15183       if (!(prefixes & PREFIX_ADDR))
15184         names = (address_mode == mode_16bit
15185                      ? names16 : names);
15186       else
15187         {
15188           /* Remove "addr16/addr32".  */
15189           all_prefixes[last_addr_prefix] = 0;
15190           names = (address_mode != mode_32bit
15191                        ? names32 : names16);
15192           used_prefixes |= PREFIX_ADDR;
15193         }
15194       break;
15195     case mask_bd_mode:
15196     case mask_mode:
15197       if (reg > 0x7)
15198         {
15199           oappend ("(bad)");
15200           return;
15201         }
15202       names = names_mask;
15203       break;
15204     case 0:
15205       return;
15206     default:
15207       oappend (INTERNAL_DISASSEMBLER_ERROR);
15208       return;
15209     }
15210   oappend (names[reg]);
15211 }
15212
15213 static void
15214 OP_E_memory (int bytemode, int sizeflag)
15215 {
15216   bfd_vma disp = 0;
15217   int add = (rex & REX_B) ? 8 : 0;
15218   int riprel = 0;
15219   int shift;
15220
15221   if (vex.evex)
15222     {
15223       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
15224       if (vex.b
15225           && bytemode != x_mode
15226           && bytemode != xmmq_mode
15227           && bytemode != evex_half_bcst_xmmq_mode)
15228         {
15229           BadOp ();
15230           return;
15231         }
15232       switch (bytemode)
15233         {
15234         case dqw_mode:
15235         case dw_mode:
15236           shift = 1;
15237           break;
15238         case dqb_mode:
15239         case db_mode:
15240           shift = 0;
15241           break;
15242         case vex_vsib_d_w_dq_mode:
15243         case vex_vsib_d_w_d_mode:
15244         case vex_vsib_q_w_dq_mode:
15245         case vex_vsib_q_w_d_mode:
15246         case evex_x_gscat_mode:
15247         case xmm_mdq_mode:
15248           shift = vex.w ? 3 : 2;
15249           break;
15250         case x_mode:
15251         case evex_half_bcst_xmmq_mode:
15252         case xmmq_mode:
15253           if (vex.b)
15254             {
15255               shift = vex.w ? 3 : 2;
15256               break;
15257             }
15258           /* Fall through.  */
15259         case xmmqd_mode:
15260         case xmmdw_mode:
15261         case ymmq_mode:
15262         case evex_x_nobcst_mode:
15263         case x_swap_mode:
15264           switch (vex.length)
15265             {
15266             case 128:
15267               shift = 4;
15268               break;
15269             case 256:
15270               shift = 5;
15271               break;
15272             case 512:
15273               shift = 6;
15274               break;
15275             default:
15276               abort ();
15277             }
15278           break;
15279         case ymm_mode:
15280           shift = 5;
15281           break;
15282         case xmm_mode:
15283           shift = 4;
15284           break;
15285         case xmm_mq_mode:
15286         case q_mode:
15287         case q_scalar_mode:
15288         case q_swap_mode:
15289         case q_scalar_swap_mode:
15290           shift = 3;
15291           break;
15292         case dqd_mode:
15293         case xmm_md_mode:
15294         case d_mode:
15295         case d_scalar_mode:
15296         case d_swap_mode:
15297         case d_scalar_swap_mode:
15298           shift = 2;
15299           break;
15300     case w_scalar_mode:
15301         case xmm_mw_mode:
15302           shift = 1;
15303           break;
15304     case b_scalar_mode:
15305         case xmm_mb_mode:
15306           shift = 0;
15307           break;
15308         default:
15309           abort ();
15310         }
15311       /* Make necessary corrections to shift for modes that need it.
15312          For these modes we currently have shift 4, 5 or 6 depending on
15313          vex.length (it corresponds to xmmword, ymmword or zmmword
15314          operand).  We might want to make it 3, 4 or 5 (e.g. for
15315          xmmq_mode).  In case of broadcast enabled the corrections
15316          aren't needed, as element size is always 32 or 64 bits.  */
15317       if (!vex.b
15318           && (bytemode == xmmq_mode
15319               || bytemode == evex_half_bcst_xmmq_mode))
15320         shift -= 1;
15321       else if (bytemode == xmmqd_mode)
15322         shift -= 2;
15323       else if (bytemode == xmmdw_mode)
15324         shift -= 3;
15325       else if (bytemode == ymmq_mode && vex.length == 128)
15326         shift -= 1;
15327     }
15328   else
15329     shift = 0;
15330
15331   USED_REX (REX_B);
15332   if (intel_syntax)
15333     intel_operand_size (bytemode, sizeflag);
15334   append_seg ();
15335
15336   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15337     {
15338       /* 32/64 bit address mode */
15339       int havedisp;
15340       int havesib;
15341       int havebase;
15342       int haveindex;
15343       int needindex;
15344       int needaddr32;
15345       int base, rbase;
15346       int vindex = 0;
15347       int scale = 0;
15348       int addr32flag = !((sizeflag & AFLAG)
15349                          || bytemode == v_bnd_mode
15350                          || bytemode == v_bndmk_mode
15351                          || bytemode == bnd_mode
15352                          || bytemode == bnd_swap_mode);
15353       const char **indexes64 = names64;
15354       const char **indexes32 = names32;
15355
15356       havesib = 0;
15357       havebase = 1;
15358       haveindex = 0;
15359       base = modrm.rm;
15360
15361       if (base == 4)
15362         {
15363           havesib = 1;
15364           vindex = sib.index;
15365           USED_REX (REX_X);
15366           if (rex & REX_X)
15367             vindex += 8;
15368           switch (bytemode)
15369             {
15370             case vex_vsib_d_w_dq_mode:
15371             case vex_vsib_d_w_d_mode:
15372             case vex_vsib_q_w_dq_mode:
15373             case vex_vsib_q_w_d_mode:
15374               if (!need_vex)
15375                 abort ();
15376               if (vex.evex)
15377                 {
15378                   if (!vex.v)
15379                     vindex += 16;
15380                 }
15381
15382               haveindex = 1;
15383               switch (vex.length)
15384                 {
15385                 case 128:
15386                   indexes64 = indexes32 = names_xmm;
15387                   break;
15388                 case 256:
15389                   if (!vex.w
15390                       || bytemode == vex_vsib_q_w_dq_mode
15391                       || bytemode == vex_vsib_q_w_d_mode)
15392                     indexes64 = indexes32 = names_ymm;
15393                   else
15394                     indexes64 = indexes32 = names_xmm;
15395                   break;
15396                 case 512:
15397                   if (!vex.w
15398                       || bytemode == vex_vsib_q_w_dq_mode
15399                       || bytemode == vex_vsib_q_w_d_mode)
15400                     indexes64 = indexes32 = names_zmm;
15401                   else
15402                     indexes64 = indexes32 = names_ymm;
15403                   break;
15404                 default:
15405                   abort ();
15406                 }
15407               break;
15408             default:
15409               haveindex = vindex != 4;
15410               break;
15411             }
15412           scale = sib.scale;
15413           base = sib.base;
15414           codep++;
15415         }
15416       rbase = base + add;
15417
15418       switch (modrm.mod)
15419         {
15420         case 0:
15421           if (base == 5)
15422             {
15423               havebase = 0;
15424               if (address_mode == mode_64bit && !havesib)
15425                 riprel = 1;
15426               disp = get32s ();
15427               if (riprel && bytemode == v_bndmk_mode)
15428                 {
15429                   oappend ("(bad)");
15430                   return;
15431                 }
15432             }
15433           break;
15434         case 1:
15435           FETCH_DATA (the_info, codep + 1);
15436           disp = *codep++;
15437           if ((disp & 0x80) != 0)
15438             disp -= 0x100;
15439           if (vex.evex && shift > 0)
15440             disp <<= shift;
15441           break;
15442         case 2:
15443           disp = get32s ();
15444           break;
15445         }
15446
15447       needindex = 0;
15448       needaddr32 = 0;
15449       if (havesib
15450           && !havebase
15451           && !haveindex
15452           && address_mode != mode_16bit)
15453         {
15454           if (address_mode == mode_64bit)
15455             {
15456               /* Display eiz instead of addr32.  */
15457               needindex = addr32flag;
15458               needaddr32 = 1;
15459             }
15460           else
15461             {
15462               /* In 32-bit mode, we need index register to tell [offset]
15463                  from [eiz*1 + offset].  */
15464               needindex = 1;
15465             }
15466         }
15467
15468       havedisp = (havebase
15469                   || needindex
15470                   || (havesib && (haveindex || scale != 0)));
15471
15472       if (!intel_syntax)
15473         if (modrm.mod != 0 || base == 5)
15474           {
15475             if (havedisp || riprel)
15476               print_displacement (scratchbuf, disp);
15477             else
15478               print_operand_value (scratchbuf, 1, disp);
15479             oappend (scratchbuf);
15480             if (riprel)
15481               {
15482                 set_op (disp, 1);
15483                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15484               }
15485           }
15486
15487       if ((havebase || haveindex || needaddr32 || riprel)
15488           && (bytemode != v_bnd_mode)
15489           && (bytemode != v_bndmk_mode)
15490           && (bytemode != bnd_mode)
15491           && (bytemode != bnd_swap_mode))
15492         used_prefixes |= PREFIX_ADDR;
15493
15494       if (havedisp || (intel_syntax && riprel))
15495         {
15496           *obufp++ = open_char;
15497           if (intel_syntax && riprel)
15498             {
15499               set_op (disp, 1);
15500               oappend (!addr32flag ? "rip" : "eip");
15501             }
15502           *obufp = '\0';
15503           if (havebase)
15504             oappend (address_mode == mode_64bit && !addr32flag
15505                      ? names64[rbase] : names32[rbase]);
15506           if (havesib)
15507             {
15508               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15509                  print index to tell base + index from base.  */
15510               if (scale != 0
15511                   || needindex
15512                   || haveindex
15513                   || (havebase && base != ESP_REG_NUM))
15514                 {
15515                   if (!intel_syntax || havebase)
15516                     {
15517                       *obufp++ = separator_char;
15518                       *obufp = '\0';
15519                     }
15520                   if (haveindex)
15521                     oappend (address_mode == mode_64bit && !addr32flag
15522                              ? indexes64[vindex] : indexes32[vindex]);
15523                   else
15524                     oappend (address_mode == mode_64bit && !addr32flag
15525                              ? index64 : index32);
15526
15527                   *obufp++ = scale_char;
15528                   *obufp = '\0';
15529                   sprintf (scratchbuf, "%d", 1 << scale);
15530                   oappend (scratchbuf);
15531                 }
15532             }
15533           if (intel_syntax
15534               && (disp || modrm.mod != 0 || base == 5))
15535             {
15536               if (!havedisp || (bfd_signed_vma) disp >= 0)
15537                 {
15538                   *obufp++ = '+';
15539                   *obufp = '\0';
15540                 }
15541               else if (modrm.mod != 1 && disp != -disp)
15542                 {
15543                   *obufp++ = '-';
15544                   *obufp = '\0';
15545                   disp = - (bfd_signed_vma) disp;
15546                 }
15547
15548               if (havedisp)
15549                 print_displacement (scratchbuf, disp);
15550               else
15551                 print_operand_value (scratchbuf, 1, disp);
15552               oappend (scratchbuf);
15553             }
15554
15555           *obufp++ = close_char;
15556           *obufp = '\0';
15557         }
15558       else if (intel_syntax)
15559         {
15560           if (modrm.mod != 0 || base == 5)
15561             {
15562               if (!active_seg_prefix)
15563                 {
15564                   oappend (names_seg[ds_reg - es_reg]);
15565                   oappend (":");
15566                 }
15567               print_operand_value (scratchbuf, 1, disp);
15568               oappend (scratchbuf);
15569             }
15570         }
15571     }
15572   else
15573     {
15574       /* 16 bit address mode */
15575       used_prefixes |= prefixes & PREFIX_ADDR;
15576       switch (modrm.mod)
15577         {
15578         case 0:
15579           if (modrm.rm == 6)
15580             {
15581               disp = get16 ();
15582               if ((disp & 0x8000) != 0)
15583                 disp -= 0x10000;
15584             }
15585           break;
15586         case 1:
15587           FETCH_DATA (the_info, codep + 1);
15588           disp = *codep++;
15589           if ((disp & 0x80) != 0)
15590             disp -= 0x100;
15591           if (vex.evex && shift > 0)
15592             disp <<= shift;
15593           break;
15594         case 2:
15595           disp = get16 ();
15596           if ((disp & 0x8000) != 0)
15597             disp -= 0x10000;
15598           break;
15599         }
15600
15601       if (!intel_syntax)
15602         if (modrm.mod != 0 || modrm.rm == 6)
15603           {
15604             print_displacement (scratchbuf, disp);
15605             oappend (scratchbuf);
15606           }
15607
15608       if (modrm.mod != 0 || modrm.rm != 6)
15609         {
15610           *obufp++ = open_char;
15611           *obufp = '\0';
15612           oappend (index16[modrm.rm]);
15613           if (intel_syntax
15614               && (disp || modrm.mod != 0 || modrm.rm == 6))
15615             {
15616               if ((bfd_signed_vma) disp >= 0)
15617                 {
15618                   *obufp++ = '+';
15619                   *obufp = '\0';
15620                 }
15621               else if (modrm.mod != 1)
15622                 {
15623                   *obufp++ = '-';
15624                   *obufp = '\0';
15625                   disp = - (bfd_signed_vma) disp;
15626                 }
15627
15628               print_displacement (scratchbuf, disp);
15629               oappend (scratchbuf);
15630             }
15631
15632           *obufp++ = close_char;
15633           *obufp = '\0';
15634         }
15635       else if (intel_syntax)
15636         {
15637           if (!active_seg_prefix)
15638             {
15639               oappend (names_seg[ds_reg - es_reg]);
15640               oappend (":");
15641             }
15642           print_operand_value (scratchbuf, 1, disp & 0xffff);
15643           oappend (scratchbuf);
15644         }
15645     }
15646   if (vex.evex && vex.b
15647       && (bytemode == x_mode
15648           || bytemode == xmmq_mode
15649           || bytemode == evex_half_bcst_xmmq_mode))
15650     {
15651       if (vex.w
15652           || bytemode == xmmq_mode
15653           || bytemode == evex_half_bcst_xmmq_mode)
15654         {
15655           switch (vex.length)
15656             {
15657             case 128:
15658               oappend ("{1to2}");
15659               break;
15660             case 256:
15661               oappend ("{1to4}");
15662               break;
15663             case 512:
15664               oappend ("{1to8}");
15665               break;
15666             default:
15667               abort ();
15668             }
15669         }
15670       else
15671         {
15672           switch (vex.length)
15673             {
15674             case 128:
15675               oappend ("{1to4}");
15676               break;
15677             case 256:
15678               oappend ("{1to8}");
15679               break;
15680             case 512:
15681               oappend ("{1to16}");
15682               break;
15683             default:
15684               abort ();
15685             }
15686         }
15687     }
15688 }
15689
15690 static void
15691 OP_E (int bytemode, int sizeflag)
15692 {
15693   /* Skip mod/rm byte.  */
15694   MODRM_CHECK;
15695   codep++;
15696
15697   if (modrm.mod == 3)
15698     OP_E_register (bytemode, sizeflag);
15699   else
15700     OP_E_memory (bytemode, sizeflag);
15701 }
15702
15703 static void
15704 OP_G (int bytemode, int sizeflag)
15705 {
15706   int add = 0;
15707   const char **names;
15708   USED_REX (REX_R);
15709   if (rex & REX_R)
15710     add += 8;
15711   switch (bytemode)
15712     {
15713     case b_mode:
15714       USED_REX (0);
15715       if (rex)
15716         oappend (names8rex[modrm.reg + add]);
15717       else
15718         oappend (names8[modrm.reg + add]);
15719       break;
15720     case w_mode:
15721       oappend (names16[modrm.reg + add]);
15722       break;
15723     case d_mode:
15724     case db_mode:
15725     case dw_mode:
15726       oappend (names32[modrm.reg + add]);
15727       break;
15728     case q_mode:
15729       oappend (names64[modrm.reg + add]);
15730       break;
15731     case bnd_mode:
15732       if (modrm.reg > 0x3)
15733         {
15734           oappend ("(bad)");
15735           return;
15736         }
15737       oappend (names_bnd[modrm.reg]);
15738       break;
15739     case v_mode:
15740     case dq_mode:
15741     case dqb_mode:
15742     case dqd_mode:
15743     case dqw_mode:
15744       USED_REX (REX_W);
15745       if (rex & REX_W)
15746         oappend (names64[modrm.reg + add]);
15747       else
15748         {
15749           if ((sizeflag & DFLAG) || bytemode != v_mode)
15750             oappend (names32[modrm.reg + add]);
15751           else
15752             oappend (names16[modrm.reg + add]);
15753           used_prefixes |= (prefixes & PREFIX_DATA);
15754         }
15755       break;
15756     case va_mode:
15757       names = (address_mode == mode_64bit
15758                ? names64 : names32);
15759       if (!(prefixes & PREFIX_ADDR))
15760         {
15761           if (address_mode == mode_16bit)
15762             names = names16;
15763         }
15764       else
15765         {
15766           /* Remove "addr16/addr32".  */
15767           all_prefixes[last_addr_prefix] = 0;
15768           names = (address_mode != mode_32bit
15769                        ? names32 : names16);
15770           used_prefixes |= PREFIX_ADDR;
15771         }
15772       oappend (names[modrm.reg + add]);
15773       break;
15774     case m_mode:
15775       if (address_mode == mode_64bit)
15776         oappend (names64[modrm.reg + add]);
15777       else
15778         oappend (names32[modrm.reg + add]);
15779       break;
15780     case mask_bd_mode:
15781     case mask_mode:
15782       if ((modrm.reg + add) > 0x7)
15783         {
15784           oappend ("(bad)");
15785           return;
15786         }
15787       oappend (names_mask[modrm.reg + add]);
15788       break;
15789     default:
15790       oappend (INTERNAL_DISASSEMBLER_ERROR);
15791       break;
15792     }
15793 }
15794
15795 static bfd_vma
15796 get64 (void)
15797 {
15798   bfd_vma x;
15799 #ifdef BFD64
15800   unsigned int a;
15801   unsigned int b;
15802
15803   FETCH_DATA (the_info, codep + 8);
15804   a = *codep++ & 0xff;
15805   a |= (*codep++ & 0xff) << 8;
15806   a |= (*codep++ & 0xff) << 16;
15807   a |= (*codep++ & 0xffu) << 24;
15808   b = *codep++ & 0xff;
15809   b |= (*codep++ & 0xff) << 8;
15810   b |= (*codep++ & 0xff) << 16;
15811   b |= (*codep++ & 0xffu) << 24;
15812   x = a + ((bfd_vma) b << 32);
15813 #else
15814   abort ();
15815   x = 0;
15816 #endif
15817   return x;
15818 }
15819
15820 static bfd_signed_vma
15821 get32 (void)
15822 {
15823   bfd_signed_vma x = 0;
15824
15825   FETCH_DATA (the_info, codep + 4);
15826   x = *codep++ & (bfd_signed_vma) 0xff;
15827   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15828   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15829   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15830   return x;
15831 }
15832
15833 static bfd_signed_vma
15834 get32s (void)
15835 {
15836   bfd_signed_vma x = 0;
15837
15838   FETCH_DATA (the_info, codep + 4);
15839   x = *codep++ & (bfd_signed_vma) 0xff;
15840   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15841   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15842   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15843
15844   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15845
15846   return x;
15847 }
15848
15849 static int
15850 get16 (void)
15851 {
15852   int x = 0;
15853
15854   FETCH_DATA (the_info, codep + 2);
15855   x = *codep++ & 0xff;
15856   x |= (*codep++ & 0xff) << 8;
15857   return x;
15858 }
15859
15860 static void
15861 set_op (bfd_vma op, int riprel)
15862 {
15863   op_index[op_ad] = op_ad;
15864   if (address_mode == mode_64bit)
15865     {
15866       op_address[op_ad] = op;
15867       op_riprel[op_ad] = riprel;
15868     }
15869   else
15870     {
15871       /* Mask to get a 32-bit address.  */
15872       op_address[op_ad] = op & 0xffffffff;
15873       op_riprel[op_ad] = riprel & 0xffffffff;
15874     }
15875 }
15876
15877 static void
15878 OP_REG (int code, int sizeflag)
15879 {
15880   const char *s;
15881   int add;
15882
15883   switch (code)
15884     {
15885     case es_reg: case ss_reg: case cs_reg:
15886     case ds_reg: case fs_reg: case gs_reg:
15887       oappend (names_seg[code - es_reg]);
15888       return;
15889     }
15890
15891   USED_REX (REX_B);
15892   if (rex & REX_B)
15893     add = 8;
15894   else
15895     add = 0;
15896
15897   switch (code)
15898     {
15899     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15900     case sp_reg: case bp_reg: case si_reg: case di_reg:
15901       s = names16[code - ax_reg + add];
15902       break;
15903     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15904     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15905       USED_REX (0);
15906       if (rex)
15907         s = names8rex[code - al_reg + add];
15908       else
15909         s = names8[code - al_reg];
15910       break;
15911     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15912     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15913       if (address_mode == mode_64bit
15914           && ((sizeflag & DFLAG) || (rex & REX_W)))
15915         {
15916           s = names64[code - rAX_reg + add];
15917           break;
15918         }
15919       code += eAX_reg - rAX_reg;
15920       /* Fall through.  */
15921     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15922     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15923       USED_REX (REX_W);
15924       if (rex & REX_W)
15925         s = names64[code - eAX_reg + add];
15926       else
15927         {
15928           if (sizeflag & DFLAG)
15929             s = names32[code - eAX_reg + add];
15930           else
15931             s = names16[code - eAX_reg + add];
15932           used_prefixes |= (prefixes & PREFIX_DATA);
15933         }
15934       break;
15935     default:
15936       s = INTERNAL_DISASSEMBLER_ERROR;
15937       break;
15938     }
15939   oappend (s);
15940 }
15941
15942 static void
15943 OP_IMREG (int code, int sizeflag)
15944 {
15945   const char *s;
15946
15947   switch (code)
15948     {
15949     case indir_dx_reg:
15950       if (intel_syntax)
15951         s = "dx";
15952       else
15953         s = "(%dx)";
15954       break;
15955     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15956     case sp_reg: case bp_reg: case si_reg: case di_reg:
15957       s = names16[code - ax_reg];
15958       break;
15959     case es_reg: case ss_reg: case cs_reg:
15960     case ds_reg: case fs_reg: case gs_reg:
15961       s = names_seg[code - es_reg];
15962       break;
15963     case al_reg: case ah_reg: case cl_reg: case ch_reg:
15964     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15965       USED_REX (0);
15966       if (rex)
15967         s = names8rex[code - al_reg];
15968       else
15969         s = names8[code - al_reg];
15970       break;
15971     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15972     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15973       USED_REX (REX_W);
15974       if (rex & REX_W)
15975         s = names64[code - eAX_reg];
15976       else
15977         {
15978           if (sizeflag & DFLAG)
15979             s = names32[code - eAX_reg];
15980           else
15981             s = names16[code - eAX_reg];
15982           used_prefixes |= (prefixes & PREFIX_DATA);
15983         }
15984       break;
15985     case z_mode_ax_reg:
15986       if ((rex & REX_W) || (sizeflag & DFLAG))
15987         s = *names32;
15988       else
15989         s = *names16;
15990       if (!(rex & REX_W))
15991         used_prefixes |= (prefixes & PREFIX_DATA);
15992       break;
15993     default:
15994       s = INTERNAL_DISASSEMBLER_ERROR;
15995       break;
15996     }
15997   oappend (s);
15998 }
15999
16000 static void
16001 OP_I (int bytemode, int sizeflag)
16002 {
16003   bfd_signed_vma op;
16004   bfd_signed_vma mask = -1;
16005
16006   switch (bytemode)
16007     {
16008     case b_mode:
16009       FETCH_DATA (the_info, codep + 1);
16010       op = *codep++;
16011       mask = 0xff;
16012       break;
16013     case q_mode:
16014       if (address_mode == mode_64bit)
16015         {
16016           op = get32s ();
16017           break;
16018         }
16019       /* Fall through.  */
16020     case v_mode:
16021       USED_REX (REX_W);
16022       if (rex & REX_W)
16023         op = get32s ();
16024       else
16025         {
16026           if (sizeflag & DFLAG)
16027             {
16028               op = get32 ();
16029               mask = 0xffffffff;
16030             }
16031           else
16032             {
16033               op = get16 ();
16034               mask = 0xfffff;
16035             }
16036           used_prefixes |= (prefixes & PREFIX_DATA);
16037         }
16038       break;
16039     case w_mode:
16040       mask = 0xfffff;
16041       op = get16 ();
16042       break;
16043     case const_1_mode:
16044       if (intel_syntax)
16045         oappend ("1");
16046       return;
16047     default:
16048       oappend (INTERNAL_DISASSEMBLER_ERROR);
16049       return;
16050     }
16051
16052   op &= mask;
16053   scratchbuf[0] = '$';
16054   print_operand_value (scratchbuf + 1, 1, op);
16055   oappend_maybe_intel (scratchbuf);
16056   scratchbuf[0] = '\0';
16057 }
16058
16059 static void
16060 OP_I64 (int bytemode, int sizeflag)
16061 {
16062   bfd_signed_vma op;
16063   bfd_signed_vma mask = -1;
16064
16065   if (address_mode != mode_64bit)
16066     {
16067       OP_I (bytemode, sizeflag);
16068       return;
16069     }
16070
16071   switch (bytemode)
16072     {
16073     case b_mode:
16074       FETCH_DATA (the_info, codep + 1);
16075       op = *codep++;
16076       mask = 0xff;
16077       break;
16078     case v_mode:
16079       USED_REX (REX_W);
16080       if (rex & REX_W)
16081         op = get64 ();
16082       else
16083         {
16084           if (sizeflag & DFLAG)
16085             {
16086               op = get32 ();
16087               mask = 0xffffffff;
16088             }
16089           else
16090             {
16091               op = get16 ();
16092               mask = 0xfffff;
16093             }
16094           used_prefixes |= (prefixes & PREFIX_DATA);
16095         }
16096       break;
16097     case w_mode:
16098       mask = 0xfffff;
16099       op = get16 ();
16100       break;
16101     default:
16102       oappend (INTERNAL_DISASSEMBLER_ERROR);
16103       return;
16104     }
16105
16106   op &= mask;
16107   scratchbuf[0] = '$';
16108   print_operand_value (scratchbuf + 1, 1, op);
16109   oappend_maybe_intel (scratchbuf);
16110   scratchbuf[0] = '\0';
16111 }
16112
16113 static void
16114 OP_sI (int bytemode, int sizeflag)
16115 {
16116   bfd_signed_vma op;
16117
16118   switch (bytemode)
16119     {
16120     case b_mode:
16121     case b_T_mode:
16122       FETCH_DATA (the_info, codep + 1);
16123       op = *codep++;
16124       if ((op & 0x80) != 0)
16125         op -= 0x100;
16126       if (bytemode == b_T_mode)
16127         {
16128           if (address_mode != mode_64bit
16129               || !((sizeflag & DFLAG) || (rex & REX_W)))
16130             {
16131               /* The operand-size prefix is overridden by a REX prefix.  */
16132               if ((sizeflag & DFLAG) || (rex & REX_W))
16133                 op &= 0xffffffff;
16134               else
16135                 op &= 0xffff;
16136           }
16137         }
16138       else
16139         {
16140           if (!(rex & REX_W))
16141             {
16142               if (sizeflag & DFLAG)
16143                 op &= 0xffffffff;
16144               else
16145                 op &= 0xffff;
16146             }
16147         }
16148       break;
16149     case v_mode:
16150       /* The operand-size prefix is overridden by a REX prefix.  */
16151       if ((sizeflag & DFLAG) || (rex & REX_W))
16152         op = get32s ();
16153       else
16154         op = get16 ();
16155       break;
16156     default:
16157       oappend (INTERNAL_DISASSEMBLER_ERROR);
16158       return;
16159     }
16160
16161   scratchbuf[0] = '$';
16162   print_operand_value (scratchbuf + 1, 1, op);
16163   oappend_maybe_intel (scratchbuf);
16164 }
16165
16166 static void
16167 OP_J (int bytemode, int sizeflag)
16168 {
16169   bfd_vma disp;
16170   bfd_vma mask = -1;
16171   bfd_vma segment = 0;
16172
16173   switch (bytemode)
16174     {
16175     case b_mode:
16176       FETCH_DATA (the_info, codep + 1);
16177       disp = *codep++;
16178       if ((disp & 0x80) != 0)
16179         disp -= 0x100;
16180       break;
16181     case v_mode:
16182       if (isa64 == amd64)
16183         USED_REX (REX_W);
16184       if ((sizeflag & DFLAG)
16185           || (address_mode == mode_64bit
16186               && (isa64 != amd64 || (rex & REX_W))))
16187         disp = get32s ();
16188       else
16189         {
16190           disp = get16 ();
16191           if ((disp & 0x8000) != 0)
16192             disp -= 0x10000;
16193           /* In 16bit mode, address is wrapped around at 64k within
16194              the same segment.  Otherwise, a data16 prefix on a jump
16195              instruction means that the pc is masked to 16 bits after
16196              the displacement is added!  */
16197           mask = 0xffff;
16198           if ((prefixes & PREFIX_DATA) == 0)
16199             segment = ((start_pc + (codep - start_codep))
16200                        & ~((bfd_vma) 0xffff));
16201         }
16202       if (address_mode != mode_64bit
16203           || (isa64 == amd64 && !(rex & REX_W)))
16204         used_prefixes |= (prefixes & PREFIX_DATA);
16205       break;
16206     default:
16207       oappend (INTERNAL_DISASSEMBLER_ERROR);
16208       return;
16209     }
16210   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16211   set_op (disp, 0);
16212   print_operand_value (scratchbuf, 1, disp);
16213   oappend (scratchbuf);
16214 }
16215
16216 static void
16217 OP_SEG (int bytemode, int sizeflag)
16218 {
16219   if (bytemode == w_mode)
16220     oappend (names_seg[modrm.reg]);
16221   else
16222     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16223 }
16224
16225 static void
16226 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16227 {
16228   int seg, offset;
16229
16230   if (sizeflag & DFLAG)
16231     {
16232       offset = get32 ();
16233       seg = get16 ();
16234     }
16235   else
16236     {
16237       offset = get16 ();
16238       seg = get16 ();
16239     }
16240   used_prefixes |= (prefixes & PREFIX_DATA);
16241   if (intel_syntax)
16242     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16243   else
16244     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16245   oappend (scratchbuf);
16246 }
16247
16248 static void
16249 OP_OFF (int bytemode, int sizeflag)
16250 {
16251   bfd_vma off;
16252
16253   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16254     intel_operand_size (bytemode, sizeflag);
16255   append_seg ();
16256
16257   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16258     off = get32 ();
16259   else
16260     off = get16 ();
16261
16262   if (intel_syntax)
16263     {
16264       if (!active_seg_prefix)
16265         {
16266           oappend (names_seg[ds_reg - es_reg]);
16267           oappend (":");
16268         }
16269     }
16270   print_operand_value (scratchbuf, 1, off);
16271   oappend (scratchbuf);
16272 }
16273
16274 static void
16275 OP_OFF64 (int bytemode, int sizeflag)
16276 {
16277   bfd_vma off;
16278
16279   if (address_mode != mode_64bit
16280       || (prefixes & PREFIX_ADDR))
16281     {
16282       OP_OFF (bytemode, sizeflag);
16283       return;
16284     }
16285
16286   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16287     intel_operand_size (bytemode, sizeflag);
16288   append_seg ();
16289
16290   off = get64 ();
16291
16292   if (intel_syntax)
16293     {
16294       if (!active_seg_prefix)
16295         {
16296           oappend (names_seg[ds_reg - es_reg]);
16297           oappend (":");
16298         }
16299     }
16300   print_operand_value (scratchbuf, 1, off);
16301   oappend (scratchbuf);
16302 }
16303
16304 static void
16305 ptr_reg (int code, int sizeflag)
16306 {
16307   const char *s;
16308
16309   *obufp++ = open_char;
16310   used_prefixes |= (prefixes & PREFIX_ADDR);
16311   if (address_mode == mode_64bit)
16312     {
16313       if (!(sizeflag & AFLAG))
16314         s = names32[code - eAX_reg];
16315       else
16316         s = names64[code - eAX_reg];
16317     }
16318   else if (sizeflag & AFLAG)
16319     s = names32[code - eAX_reg];
16320   else
16321     s = names16[code - eAX_reg];
16322   oappend (s);
16323   *obufp++ = close_char;
16324   *obufp = 0;
16325 }
16326
16327 static void
16328 OP_ESreg (int code, int sizeflag)
16329 {
16330   if (intel_syntax)
16331     {
16332       switch (codep[-1])
16333         {
16334         case 0x6d:      /* insw/insl */
16335           intel_operand_size (z_mode, sizeflag);
16336           break;
16337         case 0xa5:      /* movsw/movsl/movsq */
16338         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16339         case 0xab:      /* stosw/stosl */
16340         case 0xaf:      /* scasw/scasl */
16341           intel_operand_size (v_mode, sizeflag);
16342           break;
16343         default:
16344           intel_operand_size (b_mode, sizeflag);
16345         }
16346     }
16347   oappend_maybe_intel ("%es:");
16348   ptr_reg (code, sizeflag);
16349 }
16350
16351 static void
16352 OP_DSreg (int code, int sizeflag)
16353 {
16354   if (intel_syntax)
16355     {
16356       switch (codep[-1])
16357         {
16358         case 0x6f:      /* outsw/outsl */
16359           intel_operand_size (z_mode, sizeflag);
16360           break;
16361         case 0xa5:      /* movsw/movsl/movsq */
16362         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
16363         case 0xad:      /* lodsw/lodsl/lodsq */
16364           intel_operand_size (v_mode, sizeflag);
16365           break;
16366         default:
16367           intel_operand_size (b_mode, sizeflag);
16368         }
16369     }
16370   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16371      default segment register DS is printed.  */
16372   if (!active_seg_prefix)
16373     active_seg_prefix = PREFIX_DS;
16374   append_seg ();
16375   ptr_reg (code, sizeflag);
16376 }
16377
16378 static void
16379 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16380 {
16381   int add;
16382   if (rex & REX_R)
16383     {
16384       USED_REX (REX_R);
16385       add = 8;
16386     }
16387   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16388     {
16389       all_prefixes[last_lock_prefix] = 0;
16390       used_prefixes |= PREFIX_LOCK;
16391       add = 8;
16392     }
16393   else
16394     add = 0;
16395   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16396   oappend_maybe_intel (scratchbuf);
16397 }
16398
16399 static void
16400 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16401 {
16402   int add;
16403   USED_REX (REX_R);
16404   if (rex & REX_R)
16405     add = 8;
16406   else
16407     add = 0;
16408   if (intel_syntax)
16409     sprintf (scratchbuf, "db%d", modrm.reg + add);
16410   else
16411     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16412   oappend (scratchbuf);
16413 }
16414
16415 static void
16416 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16417 {
16418   sprintf (scratchbuf, "%%tr%d", modrm.reg);
16419   oappend_maybe_intel (scratchbuf);
16420 }
16421
16422 static void
16423 OP_R (int bytemode, int sizeflag)
16424 {
16425   /* Skip mod/rm byte.  */
16426   MODRM_CHECK;
16427   codep++;
16428   OP_E_register (bytemode, sizeflag);
16429 }
16430
16431 static void
16432 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16433 {
16434   int reg = modrm.reg;
16435   const char **names;
16436
16437   used_prefixes |= (prefixes & PREFIX_DATA);
16438   if (prefixes & PREFIX_DATA)
16439     {
16440       names = names_xmm;
16441       USED_REX (REX_R);
16442       if (rex & REX_R)
16443         reg += 8;
16444     }
16445   else
16446     names = names_mm;
16447   oappend (names[reg]);
16448 }
16449
16450 static void
16451 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16452 {
16453   int reg = modrm.reg;
16454   const char **names;
16455
16456   USED_REX (REX_R);
16457   if (rex & REX_R)
16458     reg += 8;
16459   if (vex.evex)
16460     {
16461       if (!vex.r)
16462         reg += 16;
16463     }
16464
16465   if (need_vex
16466       && bytemode != xmm_mode
16467       && bytemode != xmmq_mode
16468       && bytemode != evex_half_bcst_xmmq_mode
16469       && bytemode != ymm_mode
16470       && bytemode != scalar_mode)
16471     {
16472       switch (vex.length)
16473         {
16474         case 128:
16475           names = names_xmm;
16476           break;
16477         case 256:
16478           if (vex.w
16479               || (bytemode != vex_vsib_q_w_dq_mode
16480                   && bytemode != vex_vsib_q_w_d_mode))
16481             names = names_ymm;
16482           else
16483             names = names_xmm;
16484           break;
16485         case 512:
16486           names = names_zmm;
16487           break;
16488         default:
16489           abort ();
16490         }
16491     }
16492   else if (bytemode == xmmq_mode
16493            || bytemode == evex_half_bcst_xmmq_mode)
16494     {
16495       switch (vex.length)
16496         {
16497         case 128:
16498         case 256:
16499           names = names_xmm;
16500           break;
16501         case 512:
16502           names = names_ymm;
16503           break;
16504         default:
16505           abort ();
16506         }
16507     }
16508   else if (bytemode == ymm_mode)
16509     names = names_ymm;
16510   else
16511     names = names_xmm;
16512   oappend (names[reg]);
16513 }
16514
16515 static void
16516 OP_EM (int bytemode, int sizeflag)
16517 {
16518   int reg;
16519   const char **names;
16520
16521   if (modrm.mod != 3)
16522     {
16523       if (intel_syntax
16524           && (bytemode == v_mode || bytemode == v_swap_mode))
16525         {
16526           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16527           used_prefixes |= (prefixes & PREFIX_DATA);
16528         }
16529       OP_E (bytemode, sizeflag);
16530       return;
16531     }
16532
16533   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16534     swap_operand ();
16535
16536   /* Skip mod/rm byte.  */
16537   MODRM_CHECK;
16538   codep++;
16539   used_prefixes |= (prefixes & PREFIX_DATA);
16540   reg = modrm.rm;
16541   if (prefixes & PREFIX_DATA)
16542     {
16543       names = names_xmm;
16544       USED_REX (REX_B);
16545       if (rex & REX_B)
16546         reg += 8;
16547     }
16548   else
16549     names = names_mm;
16550   oappend (names[reg]);
16551 }
16552
16553 /* cvt* are the only instructions in sse2 which have
16554    both SSE and MMX operands and also have 0x66 prefix
16555    in their opcode. 0x66 was originally used to differentiate
16556    between SSE and MMX instruction(operands). So we have to handle the
16557    cvt* separately using OP_EMC and OP_MXC */
16558 static void
16559 OP_EMC (int bytemode, int sizeflag)
16560 {
16561   if (modrm.mod != 3)
16562     {
16563       if (intel_syntax && bytemode == v_mode)
16564         {
16565           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16566           used_prefixes |= (prefixes & PREFIX_DATA);
16567         }
16568       OP_E (bytemode, sizeflag);
16569       return;
16570     }
16571
16572   /* Skip mod/rm byte.  */
16573   MODRM_CHECK;
16574   codep++;
16575   used_prefixes |= (prefixes & PREFIX_DATA);
16576   oappend (names_mm[modrm.rm]);
16577 }
16578
16579 static void
16580 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16581 {
16582   used_prefixes |= (prefixes & PREFIX_DATA);
16583   oappend (names_mm[modrm.reg]);
16584 }
16585
16586 static void
16587 OP_EX (int bytemode, int sizeflag)
16588 {
16589   int reg;
16590   const char **names;
16591
16592   /* Skip mod/rm byte.  */
16593   MODRM_CHECK;
16594   codep++;
16595
16596   if (modrm.mod != 3)
16597     {
16598       OP_E_memory (bytemode, sizeflag);
16599       return;
16600     }
16601
16602   reg = modrm.rm;
16603   USED_REX (REX_B);
16604   if (rex & REX_B)
16605     reg += 8;
16606   if (vex.evex)
16607     {
16608       USED_REX (REX_X);
16609       if ((rex & REX_X))
16610         reg += 16;
16611     }
16612
16613   if ((sizeflag & SUFFIX_ALWAYS)
16614       && (bytemode == x_swap_mode
16615           || bytemode == d_swap_mode
16616           || bytemode == d_scalar_swap_mode
16617           || bytemode == q_swap_mode
16618           || bytemode == q_scalar_swap_mode))
16619     swap_operand ();
16620
16621   if (need_vex
16622       && bytemode != xmm_mode
16623       && bytemode != xmmdw_mode
16624       && bytemode != xmmqd_mode
16625       && bytemode != xmm_mb_mode
16626       && bytemode != xmm_mw_mode
16627       && bytemode != xmm_md_mode
16628       && bytemode != xmm_mq_mode
16629       && bytemode != xmm_mdq_mode
16630       && bytemode != xmmq_mode
16631       && bytemode != evex_half_bcst_xmmq_mode
16632       && bytemode != ymm_mode
16633       && bytemode != d_scalar_mode
16634       && bytemode != d_scalar_swap_mode
16635       && bytemode != q_scalar_mode
16636       && bytemode != q_scalar_swap_mode
16637       && bytemode != vex_scalar_w_dq_mode)
16638     {
16639       switch (vex.length)
16640         {
16641         case 128:
16642           names = names_xmm;
16643           break;
16644         case 256:
16645           names = names_ymm;
16646           break;
16647         case 512:
16648           names = names_zmm;
16649           break;
16650         default:
16651           abort ();
16652         }
16653     }
16654   else if (bytemode == xmmq_mode
16655            || bytemode == evex_half_bcst_xmmq_mode)
16656     {
16657       switch (vex.length)
16658         {
16659         case 128:
16660         case 256:
16661           names = names_xmm;
16662           break;
16663         case 512:
16664           names = names_ymm;
16665           break;
16666         default:
16667           abort ();
16668         }
16669     }
16670   else if (bytemode == ymm_mode)
16671     names = names_ymm;
16672   else
16673     names = names_xmm;
16674   oappend (names[reg]);
16675 }
16676
16677 static void
16678 OP_MS (int bytemode, int sizeflag)
16679 {
16680   if (modrm.mod == 3)
16681     OP_EM (bytemode, sizeflag);
16682   else
16683     BadOp ();
16684 }
16685
16686 static void
16687 OP_XS (int bytemode, int sizeflag)
16688 {
16689   if (modrm.mod == 3)
16690     OP_EX (bytemode, sizeflag);
16691   else
16692     BadOp ();
16693 }
16694
16695 static void
16696 OP_M (int bytemode, int sizeflag)
16697 {
16698   if (modrm.mod == 3)
16699     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16700     BadOp ();
16701   else
16702     OP_E (bytemode, sizeflag);
16703 }
16704
16705 static void
16706 OP_0f07 (int bytemode, int sizeflag)
16707 {
16708   if (modrm.mod != 3 || modrm.rm != 0)
16709     BadOp ();
16710   else
16711     OP_E (bytemode, sizeflag);
16712 }
16713
16714 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16715    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16716
16717 static void
16718 NOP_Fixup1 (int bytemode, int sizeflag)
16719 {
16720   if ((prefixes & PREFIX_DATA) != 0
16721       || (rex != 0
16722           && rex != 0x48
16723           && address_mode == mode_64bit))
16724     OP_REG (bytemode, sizeflag);
16725   else
16726     strcpy (obuf, "nop");
16727 }
16728
16729 static void
16730 NOP_Fixup2 (int bytemode, int sizeflag)
16731 {
16732   if ((prefixes & PREFIX_DATA) != 0
16733       || (rex != 0
16734           && rex != 0x48
16735           && address_mode == mode_64bit))
16736     OP_IMREG (bytemode, sizeflag);
16737 }
16738
16739 static const char *const Suffix3DNow[] = {
16740 /* 00 */        NULL,           NULL,           NULL,           NULL,
16741 /* 04 */        NULL,           NULL,           NULL,           NULL,
16742 /* 08 */        NULL,           NULL,           NULL,           NULL,
16743 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
16744 /* 10 */        NULL,           NULL,           NULL,           NULL,
16745 /* 14 */        NULL,           NULL,           NULL,           NULL,
16746 /* 18 */        NULL,           NULL,           NULL,           NULL,
16747 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
16748 /* 20 */        NULL,           NULL,           NULL,           NULL,
16749 /* 24 */        NULL,           NULL,           NULL,           NULL,
16750 /* 28 */        NULL,           NULL,           NULL,           NULL,
16751 /* 2C */        NULL,           NULL,           NULL,           NULL,
16752 /* 30 */        NULL,           NULL,           NULL,           NULL,
16753 /* 34 */        NULL,           NULL,           NULL,           NULL,
16754 /* 38 */        NULL,           NULL,           NULL,           NULL,
16755 /* 3C */        NULL,           NULL,           NULL,           NULL,
16756 /* 40 */        NULL,           NULL,           NULL,           NULL,
16757 /* 44 */        NULL,           NULL,           NULL,           NULL,
16758 /* 48 */        NULL,           NULL,           NULL,           NULL,
16759 /* 4C */        NULL,           NULL,           NULL,           NULL,
16760 /* 50 */        NULL,           NULL,           NULL,           NULL,
16761 /* 54 */        NULL,           NULL,           NULL,           NULL,
16762 /* 58 */        NULL,           NULL,           NULL,           NULL,
16763 /* 5C */        NULL,           NULL,           NULL,           NULL,
16764 /* 60 */        NULL,           NULL,           NULL,           NULL,
16765 /* 64 */        NULL,           NULL,           NULL,           NULL,
16766 /* 68 */        NULL,           NULL,           NULL,           NULL,
16767 /* 6C */        NULL,           NULL,           NULL,           NULL,
16768 /* 70 */        NULL,           NULL,           NULL,           NULL,
16769 /* 74 */        NULL,           NULL,           NULL,           NULL,
16770 /* 78 */        NULL,           NULL,           NULL,           NULL,
16771 /* 7C */        NULL,           NULL,           NULL,           NULL,
16772 /* 80 */        NULL,           NULL,           NULL,           NULL,
16773 /* 84 */        NULL,           NULL,           NULL,           NULL,
16774 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
16775 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
16776 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
16777 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
16778 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
16779 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
16780 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
16781 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
16782 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
16783 /* AC */        NULL,           NULL,           "pfacc",        NULL,
16784 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
16785 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
16786 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
16787 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
16788 /* C0 */        NULL,           NULL,           NULL,           NULL,
16789 /* C4 */        NULL,           NULL,           NULL,           NULL,
16790 /* C8 */        NULL,           NULL,           NULL,           NULL,
16791 /* CC */        NULL,           NULL,           NULL,           NULL,
16792 /* D0 */        NULL,           NULL,           NULL,           NULL,
16793 /* D4 */        NULL,           NULL,           NULL,           NULL,
16794 /* D8 */        NULL,           NULL,           NULL,           NULL,
16795 /* DC */        NULL,           NULL,           NULL,           NULL,
16796 /* E0 */        NULL,           NULL,           NULL,           NULL,
16797 /* E4 */        NULL,           NULL,           NULL,           NULL,
16798 /* E8 */        NULL,           NULL,           NULL,           NULL,
16799 /* EC */        NULL,           NULL,           NULL,           NULL,
16800 /* F0 */        NULL,           NULL,           NULL,           NULL,
16801 /* F4 */        NULL,           NULL,           NULL,           NULL,
16802 /* F8 */        NULL,           NULL,           NULL,           NULL,
16803 /* FC */        NULL,           NULL,           NULL,           NULL,
16804 };
16805
16806 static void
16807 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16808 {
16809   const char *mnemonic;
16810
16811   FETCH_DATA (the_info, codep + 1);
16812   /* AMD 3DNow! instructions are specified by an opcode suffix in the
16813      place where an 8-bit immediate would normally go.  ie. the last
16814      byte of the instruction.  */
16815   obufp = mnemonicendp;
16816   mnemonic = Suffix3DNow[*codep++ & 0xff];
16817   if (mnemonic)
16818     oappend (mnemonic);
16819   else
16820     {
16821       /* Since a variable sized modrm/sib chunk is between the start
16822          of the opcode (0x0f0f) and the opcode suffix, we need to do
16823          all the modrm processing first, and don't know until now that
16824          we have a bad opcode.  This necessitates some cleaning up.  */
16825       op_out[0][0] = '\0';
16826       op_out[1][0] = '\0';
16827       BadOp ();
16828     }
16829   mnemonicendp = obufp;
16830 }
16831
16832 static struct op simd_cmp_op[] =
16833 {
16834   { STRING_COMMA_LEN ("eq") },
16835   { STRING_COMMA_LEN ("lt") },
16836   { STRING_COMMA_LEN ("le") },
16837   { STRING_COMMA_LEN ("unord") },
16838   { STRING_COMMA_LEN ("neq") },
16839   { STRING_COMMA_LEN ("nlt") },
16840   { STRING_COMMA_LEN ("nle") },
16841   { STRING_COMMA_LEN ("ord") }
16842 };
16843
16844 static void
16845 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16846 {
16847   unsigned int cmp_type;
16848
16849   FETCH_DATA (the_info, codep + 1);
16850   cmp_type = *codep++ & 0xff;
16851   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16852     {
16853       char suffix [3];
16854       char *p = mnemonicendp - 2;
16855       suffix[0] = p[0];
16856       suffix[1] = p[1];
16857       suffix[2] = '\0';
16858       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16859       mnemonicendp += simd_cmp_op[cmp_type].len;
16860     }
16861   else
16862     {
16863       /* We have a reserved extension byte.  Output it directly.  */
16864       scratchbuf[0] = '$';
16865       print_operand_value (scratchbuf + 1, 1, cmp_type);
16866       oappend_maybe_intel (scratchbuf);
16867       scratchbuf[0] = '\0';
16868     }
16869 }
16870
16871 static void
16872 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16873           int sizeflag ATTRIBUTE_UNUSED)
16874 {
16875   /* mwaitx %eax,%ecx,%ebx */
16876   if (!intel_syntax)
16877     {
16878       const char **names = (address_mode == mode_64bit
16879                             ? names64 : names32);
16880       strcpy (op_out[0], names[0]);
16881       strcpy (op_out[1], names[1]);
16882       strcpy (op_out[2], names[3]);
16883       two_source_ops = 1;
16884     }
16885   /* Skip mod/rm byte.  */
16886   MODRM_CHECK;
16887   codep++;
16888 }
16889
16890 static void
16891 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16892           int sizeflag ATTRIBUTE_UNUSED)
16893 {
16894   /* mwait %eax,%ecx  */
16895   if (!intel_syntax)
16896     {
16897       const char **names = (address_mode == mode_64bit
16898                             ? names64 : names32);
16899       strcpy (op_out[0], names[0]);
16900       strcpy (op_out[1], names[1]);
16901       two_source_ops = 1;
16902     }
16903   /* Skip mod/rm byte.  */
16904   MODRM_CHECK;
16905   codep++;
16906 }
16907
16908 static void
16909 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16910             int sizeflag ATTRIBUTE_UNUSED)
16911 {
16912   /* monitor %eax,%ecx,%edx"  */
16913   if (!intel_syntax)
16914     {
16915       const char **op1_names;
16916       const char **names = (address_mode == mode_64bit
16917                             ? names64 : names32);
16918
16919       if (!(prefixes & PREFIX_ADDR))
16920         op1_names = (address_mode == mode_16bit
16921                      ? names16 : names);
16922       else
16923         {
16924           /* Remove "addr16/addr32".  */
16925           all_prefixes[last_addr_prefix] = 0;
16926           op1_names = (address_mode != mode_32bit
16927                        ? names32 : names16);
16928           used_prefixes |= PREFIX_ADDR;
16929         }
16930       strcpy (op_out[0], op1_names[0]);
16931       strcpy (op_out[1], names[1]);
16932       strcpy (op_out[2], names[2]);
16933       two_source_ops = 1;
16934     }
16935   /* Skip mod/rm byte.  */
16936   MODRM_CHECK;
16937   codep++;
16938 }
16939
16940 static void
16941 BadOp (void)
16942 {
16943   /* Throw away prefixes and 1st. opcode byte.  */
16944   codep = insn_codep + 1;
16945   oappend ("(bad)");
16946 }
16947
16948 static void
16949 REP_Fixup (int bytemode, int sizeflag)
16950 {
16951   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16952      lods and stos.  */
16953   if (prefixes & PREFIX_REPZ)
16954     all_prefixes[last_repz_prefix] = REP_PREFIX;
16955
16956   switch (bytemode)
16957     {
16958     case al_reg:
16959     case eAX_reg:
16960     case indir_dx_reg:
16961       OP_IMREG (bytemode, sizeflag);
16962       break;
16963     case eDI_reg:
16964       OP_ESreg (bytemode, sizeflag);
16965       break;
16966     case eSI_reg:
16967       OP_DSreg (bytemode, sizeflag);
16968       break;
16969     default:
16970       abort ();
16971       break;
16972     }
16973 }
16974
16975 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16976    "bnd".  */
16977
16978 static void
16979 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16980 {
16981   if (prefixes & PREFIX_REPNZ)
16982     all_prefixes[last_repnz_prefix] = BND_PREFIX;
16983 }
16984
16985 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16986    "notrack".  */
16987
16988 static void
16989 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16990                int sizeflag ATTRIBUTE_UNUSED)
16991 {
16992   if (active_seg_prefix == PREFIX_DS
16993       && (address_mode != mode_64bit || last_data_prefix < 0))
16994     {
16995       /* NOTRACK prefix is only valid on indirect branch instructions.
16996          NB: DATA prefix is unsupported for Intel64.  */
16997       active_seg_prefix = 0;
16998       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16999     }
17000 }
17001
17002 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17003    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17004  */
17005
17006 static void
17007 HLE_Fixup1 (int bytemode, int sizeflag)
17008 {
17009   if (modrm.mod != 3
17010       && (prefixes & PREFIX_LOCK) != 0)
17011     {
17012       if (prefixes & PREFIX_REPZ)
17013         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17014       if (prefixes & PREFIX_REPNZ)
17015         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17016     }
17017
17018   OP_E (bytemode, sizeflag);
17019 }
17020
17021 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
17022    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
17023  */
17024
17025 static void
17026 HLE_Fixup2 (int bytemode, int sizeflag)
17027 {
17028   if (modrm.mod != 3)
17029     {
17030       if (prefixes & PREFIX_REPZ)
17031         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17032       if (prefixes & PREFIX_REPNZ)
17033         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17034     }
17035
17036   OP_E (bytemode, sizeflag);
17037 }
17038
17039 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
17040    "xrelease" for memory operand.  No check for LOCK prefix.   */
17041
17042 static void
17043 HLE_Fixup3 (int bytemode, int sizeflag)
17044 {
17045   if (modrm.mod != 3
17046       && last_repz_prefix > last_repnz_prefix
17047       && (prefixes & PREFIX_REPZ) != 0)
17048     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17049
17050   OP_E (bytemode, sizeflag);
17051 }
17052
17053 static void
17054 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17055 {
17056   USED_REX (REX_W);
17057   if (rex & REX_W)
17058     {
17059       /* Change cmpxchg8b to cmpxchg16b.  */
17060       char *p = mnemonicendp - 2;
17061       mnemonicendp = stpcpy (p, "16b");
17062       bytemode = o_mode;
17063     }
17064   else if ((prefixes & PREFIX_LOCK) != 0)
17065     {
17066       if (prefixes & PREFIX_REPZ)
17067         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17068       if (prefixes & PREFIX_REPNZ)
17069         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17070     }
17071
17072   OP_M (bytemode, sizeflag);
17073 }
17074
17075 static void
17076 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17077 {
17078   const char **names;
17079
17080   if (need_vex)
17081     {
17082       switch (vex.length)
17083         {
17084         case 128:
17085           names = names_xmm;
17086           break;
17087         case 256:
17088           names = names_ymm;
17089           break;
17090         default:
17091           abort ();
17092         }
17093     }
17094   else
17095     names = names_xmm;
17096   oappend (names[reg]);
17097 }
17098
17099 static void
17100 CRC32_Fixup (int bytemode, int sizeflag)
17101 {
17102   /* Add proper suffix to "crc32".  */
17103   char *p = mnemonicendp;
17104
17105   switch (bytemode)
17106     {
17107     case b_mode:
17108       if (intel_syntax)
17109         goto skip;
17110
17111       *p++ = 'b';
17112       break;
17113     case v_mode:
17114       if (intel_syntax)
17115         goto skip;
17116
17117       USED_REX (REX_W);
17118       if (rex & REX_W)
17119         *p++ = 'q';
17120       else
17121         {
17122           if (sizeflag & DFLAG)
17123             *p++ = 'l';
17124           else
17125             *p++ = 'w';
17126           used_prefixes |= (prefixes & PREFIX_DATA);
17127         }
17128       break;
17129     default:
17130       oappend (INTERNAL_DISASSEMBLER_ERROR);
17131       break;
17132     }
17133   mnemonicendp = p;
17134   *p = '\0';
17135
17136 skip:
17137   if (modrm.mod == 3)
17138     {
17139       int add;
17140
17141       /* Skip mod/rm byte.  */
17142       MODRM_CHECK;
17143       codep++;
17144
17145       USED_REX (REX_B);
17146       add = (rex & REX_B) ? 8 : 0;
17147       if (bytemode == b_mode)
17148         {
17149           USED_REX (0);
17150           if (rex)
17151             oappend (names8rex[modrm.rm + add]);
17152           else
17153             oappend (names8[modrm.rm + add]);
17154         }
17155       else
17156         {
17157           USED_REX (REX_W);
17158           if (rex & REX_W)
17159             oappend (names64[modrm.rm + add]);
17160           else if ((prefixes & PREFIX_DATA))
17161             oappend (names16[modrm.rm + add]);
17162           else
17163             oappend (names32[modrm.rm + add]);
17164         }
17165     }
17166   else
17167     OP_E (bytemode, sizeflag);
17168 }
17169
17170 static void
17171 FXSAVE_Fixup (int bytemode, int sizeflag)
17172 {
17173   /* Add proper suffix to "fxsave" and "fxrstor".  */
17174   USED_REX (REX_W);
17175   if (rex & REX_W)
17176     {
17177       char *p = mnemonicendp;
17178       *p++ = '6';
17179       *p++ = '4';
17180       *p = '\0';
17181       mnemonicendp = p;
17182     }
17183   OP_M (bytemode, sizeflag);
17184 }
17185
17186 static void
17187 PCMPESTR_Fixup (int bytemode, int sizeflag)
17188 {
17189   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
17190   if (!intel_syntax)
17191     {
17192       char *p = mnemonicendp;
17193
17194       USED_REX (REX_W);
17195       if (rex & REX_W)
17196         *p++ = 'q';
17197       else if (sizeflag & SUFFIX_ALWAYS)
17198         *p++ = 'l';
17199
17200       *p = '\0';
17201       mnemonicendp = p;
17202     }
17203
17204   OP_EX (bytemode, sizeflag);
17205 }
17206
17207 /* Display the destination register operand for instructions with
17208    VEX. */
17209
17210 static void
17211 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17212 {
17213   int reg;
17214   const char **names;
17215
17216   if (!need_vex)
17217     abort ();
17218
17219   if (!need_vex_reg)
17220     return;
17221
17222   reg = vex.register_specifier;
17223   if (address_mode != mode_64bit)
17224     reg &= 7;
17225   else if (vex.evex && !vex.v)
17226     reg += 16;
17227
17228   if (bytemode == vex_scalar_mode)
17229     {
17230       oappend (names_xmm[reg]);
17231       return;
17232     }
17233
17234   switch (vex.length)
17235     {
17236     case 128:
17237       switch (bytemode)
17238         {
17239         case vex_mode:
17240         case vex128_mode:
17241         case vex_vsib_q_w_dq_mode:
17242         case vex_vsib_q_w_d_mode:
17243           names = names_xmm;
17244           break;
17245         case dq_mode:
17246           if (rex & REX_W)
17247             names = names64;
17248           else
17249             names = names32;
17250           break;
17251         case mask_bd_mode:
17252         case mask_mode:
17253           if (reg > 0x7)
17254             {
17255               oappend ("(bad)");
17256               return;
17257             }
17258           names = names_mask;
17259           break;
17260         default:
17261           abort ();
17262           return;
17263         }
17264       break;
17265     case 256:
17266       switch (bytemode)
17267         {
17268         case vex_mode:
17269         case vex256_mode:
17270           names = names_ymm;
17271           break;
17272         case vex_vsib_q_w_dq_mode:
17273         case vex_vsib_q_w_d_mode:
17274           names = vex.w ? names_ymm : names_xmm;
17275           break;
17276         case mask_bd_mode:
17277         case mask_mode:
17278           if (reg > 0x7)
17279             {
17280               oappend ("(bad)");
17281               return;
17282             }
17283           names = names_mask;
17284           break;
17285         default:
17286           /* See PR binutils/20893 for a reproducer.  */
17287           oappend ("(bad)");
17288           return;
17289         }
17290       break;
17291     case 512:
17292       names = names_zmm;
17293       break;
17294     default:
17295       abort ();
17296       break;
17297     }
17298   oappend (names[reg]);
17299 }
17300
17301 /* Get the VEX immediate byte without moving codep.  */
17302
17303 static unsigned char
17304 get_vex_imm8 (int sizeflag, int opnum)
17305 {
17306   int bytes_before_imm = 0;
17307
17308   if (modrm.mod != 3)
17309     {
17310       /* There are SIB/displacement bytes.  */
17311       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17312         {
17313           /* 32/64 bit address mode */
17314           int base = modrm.rm;
17315
17316           /* Check SIB byte.  */
17317           if (base == 4)
17318             {
17319               FETCH_DATA (the_info, codep + 1);
17320               base = *codep & 7;
17321               /* When decoding the third source, don't increase
17322                  bytes_before_imm as this has already been incremented
17323                  by one in OP_E_memory while decoding the second
17324                  source operand.  */
17325               if (opnum == 0)
17326                 bytes_before_imm++;
17327             }
17328
17329           /* Don't increase bytes_before_imm when decoding the third source,
17330              it has already been incremented by OP_E_memory while decoding
17331              the second source operand.  */
17332           if (opnum == 0)
17333             {
17334               switch (modrm.mod)
17335                 {
17336                   case 0:
17337                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
17338                        SIB == 5, there is a 4 byte displacement.  */
17339                     if (base != 5)
17340                       /* No displacement. */
17341                       break;
17342                     /* Fall through.  */
17343                   case 2:
17344                     /* 4 byte displacement.  */
17345                     bytes_before_imm += 4;
17346                     break;
17347                   case 1:
17348                     /* 1 byte displacement.  */
17349                     bytes_before_imm++;
17350                     break;
17351                 }
17352             }
17353         }
17354       else
17355         {
17356           /* 16 bit address mode */
17357           /* Don't increase bytes_before_imm when decoding the third source,
17358              it has already been incremented by OP_E_memory while decoding
17359              the second source operand.  */
17360           if (opnum == 0)
17361             {
17362               switch (modrm.mod)
17363                 {
17364                 case 0:
17365                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
17366                   if (modrm.rm != 6)
17367                     /* No displacement. */
17368                     break;
17369                   /* Fall through.  */
17370                 case 2:
17371                   /* 2 byte displacement.  */
17372                   bytes_before_imm += 2;
17373                   break;
17374                 case 1:
17375                   /* 1 byte displacement: when decoding the third source,
17376                      don't increase bytes_before_imm as this has already
17377                      been incremented by one in OP_E_memory while decoding
17378                      the second source operand.  */
17379                   if (opnum == 0)
17380                     bytes_before_imm++;
17381
17382                   break;
17383                 }
17384             }
17385         }
17386     }
17387
17388   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17389   return codep [bytes_before_imm];
17390 }
17391
17392 static void
17393 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17394 {
17395   const char **names;
17396
17397   if (reg == -1 && modrm.mod != 3)
17398     {
17399       OP_E_memory (bytemode, sizeflag);
17400       return;
17401     }
17402   else
17403     {
17404       if (reg == -1)
17405         {
17406           reg = modrm.rm;
17407           USED_REX (REX_B);
17408           if (rex & REX_B)
17409             reg += 8;
17410         }
17411       if (address_mode != mode_64bit)
17412         reg &= 7;
17413     }
17414
17415   switch (vex.length)
17416     {
17417     case 128:
17418       names = names_xmm;
17419       break;
17420     case 256:
17421       names = names_ymm;
17422       break;
17423     default:
17424       abort ();
17425     }
17426   oappend (names[reg]);
17427 }
17428
17429 static void
17430 OP_EX_VexImmW (int bytemode, int sizeflag)
17431 {
17432   int reg = -1;
17433   static unsigned char vex_imm8;
17434
17435   if (vex_w_done == 0)
17436     {
17437       vex_w_done = 1;
17438
17439       /* Skip mod/rm byte.  */
17440       MODRM_CHECK;
17441       codep++;
17442
17443       vex_imm8 = get_vex_imm8 (sizeflag, 0);
17444
17445       if (vex.w)
17446           reg = vex_imm8 >> 4;
17447
17448       OP_EX_VexReg (bytemode, sizeflag, reg);
17449     }
17450   else if (vex_w_done == 1)
17451     {
17452       vex_w_done = 2;
17453
17454       if (!vex.w)
17455           reg = vex_imm8 >> 4;
17456
17457       OP_EX_VexReg (bytemode, sizeflag, reg);
17458     }
17459   else
17460     {
17461       /* Output the imm8 directly.  */
17462       scratchbuf[0] = '$';
17463       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17464       oappend_maybe_intel (scratchbuf);
17465       scratchbuf[0] = '\0';
17466       codep++;
17467     }
17468 }
17469
17470 static void
17471 OP_Vex_2src (int bytemode, int sizeflag)
17472 {
17473   if (modrm.mod == 3)
17474     {
17475       int reg = modrm.rm;
17476       USED_REX (REX_B);
17477       if (rex & REX_B)
17478         reg += 8;
17479       oappend (names_xmm[reg]);
17480     }
17481   else
17482     {
17483       if (intel_syntax
17484           && (bytemode == v_mode || bytemode == v_swap_mode))
17485         {
17486           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17487           used_prefixes |= (prefixes & PREFIX_DATA);
17488         }
17489       OP_E (bytemode, sizeflag);
17490     }
17491 }
17492
17493 static void
17494 OP_Vex_2src_1 (int bytemode, int sizeflag)
17495 {
17496   if (modrm.mod == 3)
17497     {
17498       /* Skip mod/rm byte.   */
17499       MODRM_CHECK;
17500       codep++;
17501     }
17502
17503   if (vex.w)
17504     {
17505       unsigned int reg = vex.register_specifier;
17506
17507       if (address_mode != mode_64bit)
17508         reg &= 7;
17509       oappend (names_xmm[reg]);
17510     }
17511   else
17512     OP_Vex_2src (bytemode, sizeflag);
17513 }
17514
17515 static void
17516 OP_Vex_2src_2 (int bytemode, int sizeflag)
17517 {
17518   if (vex.w)
17519     OP_Vex_2src (bytemode, sizeflag);
17520   else
17521     {
17522       unsigned int reg = vex.register_specifier;
17523
17524       if (address_mode != mode_64bit)
17525         reg &= 7;
17526       oappend (names_xmm[reg]);
17527     }
17528 }
17529
17530 static void
17531 OP_EX_VexW (int bytemode, int sizeflag)
17532 {
17533   int reg = -1;
17534
17535   if (!vex_w_done)
17536     {
17537       /* Skip mod/rm byte.  */
17538       MODRM_CHECK;
17539       codep++;
17540
17541       if (vex.w)
17542         reg = get_vex_imm8 (sizeflag, 0) >> 4;
17543     }
17544   else
17545     {
17546       if (!vex.w)
17547         reg = get_vex_imm8 (sizeflag, 1) >> 4;
17548     }
17549
17550   OP_EX_VexReg (bytemode, sizeflag, reg);
17551
17552   if (vex_w_done)
17553     codep++;
17554   vex_w_done = 1;
17555 }
17556
17557 static void
17558 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17559 {
17560   int reg;
17561   const char **names;
17562
17563   FETCH_DATA (the_info, codep + 1);
17564   reg = *codep++;
17565
17566   if (bytemode != x_mode)
17567     abort ();
17568
17569   reg >>= 4;
17570   if (address_mode != mode_64bit)
17571     reg &= 7;
17572
17573   switch (vex.length)
17574     {
17575     case 128:
17576       names = names_xmm;
17577       break;
17578     case 256:
17579       names = names_ymm;
17580       break;
17581     default:
17582       abort ();
17583     }
17584   oappend (names[reg]);
17585 }
17586
17587 static void
17588 OP_XMM_VexW (int bytemode, int sizeflag)
17589 {
17590   /* Turn off the REX.W bit since it is used for swapping operands
17591      now.  */
17592   rex &= ~REX_W;
17593   OP_XMM (bytemode, sizeflag);
17594 }
17595
17596 static void
17597 OP_EX_Vex (int bytemode, int sizeflag)
17598 {
17599   if (modrm.mod != 3)
17600     {
17601       if (vex.register_specifier != 0)
17602         BadOp ();
17603       need_vex_reg = 0;
17604     }
17605   OP_EX (bytemode, sizeflag);
17606 }
17607
17608 static void
17609 OP_XMM_Vex (int bytemode, int sizeflag)
17610 {
17611   if (modrm.mod != 3)
17612     {
17613       if (vex.register_specifier != 0)
17614         BadOp ();
17615       need_vex_reg = 0;
17616     }
17617   OP_XMM (bytemode, sizeflag);
17618 }
17619
17620 static void
17621 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17622 {
17623   switch (vex.length)
17624     {
17625     case 128:
17626       mnemonicendp = stpcpy (obuf, "vzeroupper");
17627       break;
17628     case 256:
17629       mnemonicendp = stpcpy (obuf, "vzeroall");
17630       break;
17631     default:
17632       abort ();
17633     }
17634 }
17635
17636 static struct op vex_cmp_op[] =
17637 {
17638   { STRING_COMMA_LEN ("eq") },
17639   { STRING_COMMA_LEN ("lt") },
17640   { STRING_COMMA_LEN ("le") },
17641   { STRING_COMMA_LEN ("unord") },
17642   { STRING_COMMA_LEN ("neq") },
17643   { STRING_COMMA_LEN ("nlt") },
17644   { STRING_COMMA_LEN ("nle") },
17645   { STRING_COMMA_LEN ("ord") },
17646   { STRING_COMMA_LEN ("eq_uq") },
17647   { STRING_COMMA_LEN ("nge") },
17648   { STRING_COMMA_LEN ("ngt") },
17649   { STRING_COMMA_LEN ("false") },
17650   { STRING_COMMA_LEN ("neq_oq") },
17651   { STRING_COMMA_LEN ("ge") },
17652   { STRING_COMMA_LEN ("gt") },
17653   { STRING_COMMA_LEN ("true") },
17654   { STRING_COMMA_LEN ("eq_os") },
17655   { STRING_COMMA_LEN ("lt_oq") },
17656   { STRING_COMMA_LEN ("le_oq") },
17657   { STRING_COMMA_LEN ("unord_s") },
17658   { STRING_COMMA_LEN ("neq_us") },
17659   { STRING_COMMA_LEN ("nlt_uq") },
17660   { STRING_COMMA_LEN ("nle_uq") },
17661   { STRING_COMMA_LEN ("ord_s") },
17662   { STRING_COMMA_LEN ("eq_us") },
17663   { STRING_COMMA_LEN ("nge_uq") },
17664   { STRING_COMMA_LEN ("ngt_uq") },
17665   { STRING_COMMA_LEN ("false_os") },
17666   { STRING_COMMA_LEN ("neq_os") },
17667   { STRING_COMMA_LEN ("ge_oq") },
17668   { STRING_COMMA_LEN ("gt_oq") },
17669   { STRING_COMMA_LEN ("true_us") },
17670 };
17671
17672 static void
17673 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17674 {
17675   unsigned int cmp_type;
17676
17677   FETCH_DATA (the_info, codep + 1);
17678   cmp_type = *codep++ & 0xff;
17679   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17680     {
17681       char suffix [3];
17682       char *p = mnemonicendp - 2;
17683       suffix[0] = p[0];
17684       suffix[1] = p[1];
17685       suffix[2] = '\0';
17686       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17687       mnemonicendp += vex_cmp_op[cmp_type].len;
17688     }
17689   else
17690     {
17691       /* We have a reserved extension byte.  Output it directly.  */
17692       scratchbuf[0] = '$';
17693       print_operand_value (scratchbuf + 1, 1, cmp_type);
17694       oappend_maybe_intel (scratchbuf);
17695       scratchbuf[0] = '\0';
17696     }
17697 }
17698
17699 static void
17700 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17701              int sizeflag ATTRIBUTE_UNUSED)
17702 {
17703   unsigned int cmp_type;
17704
17705   if (!vex.evex)
17706     abort ();
17707
17708   FETCH_DATA (the_info, codep + 1);
17709   cmp_type = *codep++ & 0xff;
17710   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17711      If it's the case, print suffix, otherwise - print the immediate.  */
17712   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17713       && cmp_type != 3
17714       && cmp_type != 7)
17715     {
17716       char suffix [3];
17717       char *p = mnemonicendp - 2;
17718
17719       /* vpcmp* can have both one- and two-lettered suffix.  */
17720       if (p[0] == 'p')
17721         {
17722           p++;
17723           suffix[0] = p[0];
17724           suffix[1] = '\0';
17725         }
17726       else
17727         {
17728           suffix[0] = p[0];
17729           suffix[1] = p[1];
17730           suffix[2] = '\0';
17731         }
17732
17733       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17734       mnemonicendp += simd_cmp_op[cmp_type].len;
17735     }
17736   else
17737     {
17738       /* We have a reserved extension byte.  Output it directly.  */
17739       scratchbuf[0] = '$';
17740       print_operand_value (scratchbuf + 1, 1, cmp_type);
17741       oappend_maybe_intel (scratchbuf);
17742       scratchbuf[0] = '\0';
17743     }
17744 }
17745
17746 static const struct op xop_cmp_op[] =
17747 {
17748   { STRING_COMMA_LEN ("lt") },
17749   { STRING_COMMA_LEN ("le") },
17750   { STRING_COMMA_LEN ("gt") },
17751   { STRING_COMMA_LEN ("ge") },
17752   { STRING_COMMA_LEN ("eq") },
17753   { STRING_COMMA_LEN ("neq") },
17754   { STRING_COMMA_LEN ("false") },
17755   { STRING_COMMA_LEN ("true") }
17756 };
17757
17758 static void
17759 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17760              int sizeflag ATTRIBUTE_UNUSED)
17761 {
17762   unsigned int cmp_type;
17763
17764   FETCH_DATA (the_info, codep + 1);
17765   cmp_type = *codep++ & 0xff;
17766   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17767     {
17768       char suffix[3];
17769       char *p = mnemonicendp - 2;
17770
17771       /* vpcom* can have both one- and two-lettered suffix.  */
17772       if (p[0] == 'm')
17773         {
17774           p++;
17775           suffix[0] = p[0];
17776           suffix[1] = '\0';
17777         }
17778       else
17779         {
17780           suffix[0] = p[0];
17781           suffix[1] = p[1];
17782           suffix[2] = '\0';
17783         }
17784
17785       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17786       mnemonicendp += xop_cmp_op[cmp_type].len;
17787     }
17788   else
17789     {
17790       /* We have a reserved extension byte.  Output it directly.  */
17791       scratchbuf[0] = '$';
17792       print_operand_value (scratchbuf + 1, 1, cmp_type);
17793       oappend_maybe_intel (scratchbuf);
17794       scratchbuf[0] = '\0';
17795     }
17796 }
17797
17798 static const struct op pclmul_op[] =
17799 {
17800   { STRING_COMMA_LEN ("lql") },
17801   { STRING_COMMA_LEN ("hql") },
17802   { STRING_COMMA_LEN ("lqh") },
17803   { STRING_COMMA_LEN ("hqh") }
17804 };
17805
17806 static void
17807 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17808               int sizeflag ATTRIBUTE_UNUSED)
17809 {
17810   unsigned int pclmul_type;
17811
17812   FETCH_DATA (the_info, codep + 1);
17813   pclmul_type = *codep++ & 0xff;
17814   switch (pclmul_type)
17815     {
17816     case 0x10:
17817       pclmul_type = 2;
17818       break;
17819     case 0x11:
17820       pclmul_type = 3;
17821       break;
17822     default:
17823       break;
17824     }
17825   if (pclmul_type < ARRAY_SIZE (pclmul_op))
17826     {
17827       char suffix [4];
17828       char *p = mnemonicendp - 3;
17829       suffix[0] = p[0];
17830       suffix[1] = p[1];
17831       suffix[2] = p[2];
17832       suffix[3] = '\0';
17833       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17834       mnemonicendp += pclmul_op[pclmul_type].len;
17835     }
17836   else
17837     {
17838       /* We have a reserved extension byte.  Output it directly.  */
17839       scratchbuf[0] = '$';
17840       print_operand_value (scratchbuf + 1, 1, pclmul_type);
17841       oappend_maybe_intel (scratchbuf);
17842       scratchbuf[0] = '\0';
17843     }
17844 }
17845
17846 static void
17847 MOVBE_Fixup (int bytemode, int sizeflag)
17848 {
17849   /* Add proper suffix to "movbe".  */
17850   char *p = mnemonicendp;
17851
17852   switch (bytemode)
17853     {
17854     case v_mode:
17855       if (intel_syntax)
17856         goto skip;
17857
17858       USED_REX (REX_W);
17859       if (sizeflag & SUFFIX_ALWAYS)
17860         {
17861           if (rex & REX_W)
17862             *p++ = 'q';
17863           else
17864             {
17865               if (sizeflag & DFLAG)
17866                 *p++ = 'l';
17867               else
17868                 *p++ = 'w';
17869               used_prefixes |= (prefixes & PREFIX_DATA);
17870             }
17871         }
17872       break;
17873     default:
17874       oappend (INTERNAL_DISASSEMBLER_ERROR);
17875       break;
17876     }
17877   mnemonicendp = p;
17878   *p = '\0';
17879
17880 skip:
17881   OP_M (bytemode, sizeflag);
17882 }
17883
17884 static void
17885 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17886 {
17887   int reg;
17888   const char **names;
17889
17890   /* Skip mod/rm byte.  */
17891   MODRM_CHECK;
17892   codep++;
17893
17894   if (rex & REX_W)
17895     names = names64;
17896   else
17897     names = names32;
17898
17899   reg = modrm.rm;
17900   USED_REX (REX_B);
17901   if (rex & REX_B)
17902     reg += 8;
17903
17904   oappend (names[reg]);
17905 }
17906
17907 static void
17908 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17909 {
17910   const char **names;
17911   unsigned int reg = vex.register_specifier;
17912
17913   if (rex & REX_W)
17914     names = names64;
17915   else
17916     names = names32;
17917
17918   if (address_mode != mode_64bit)
17919     reg &= 7;
17920   oappend (names[reg]);
17921 }
17922
17923 static void
17924 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17925 {
17926   if (!vex.evex
17927       || (bytemode != mask_mode && bytemode != mask_bd_mode))
17928     abort ();
17929
17930   USED_REX (REX_R);
17931   if ((rex & REX_R) != 0 || !vex.r)
17932     {
17933       BadOp ();
17934       return;
17935     }
17936
17937   oappend (names_mask [modrm.reg]);
17938 }
17939
17940 static void
17941 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17942 {
17943   if (!vex.evex
17944       || (bytemode != evex_rounding_mode
17945           && bytemode != evex_sae_mode))
17946     abort ();
17947   if (modrm.mod == 3 && vex.b)
17948     switch (bytemode)
17949       {
17950       case evex_rounding_mode:
17951         oappend (names_rounding[vex.ll]);
17952         break;
17953       case evex_sae_mode:
17954         oappend ("{sae}");
17955         break;
17956       default:
17957         break;
17958       }
17959 }