1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma
, disassemble_info
*);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma
);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma
);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma
get64 (void);
58 static bfd_signed_vma
get32 (void);
59 static bfd_signed_vma
get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma
, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte
*max_fetched
;
131 bfd_byte the_buffer
[MAX_MNEM_SIZE
];
134 OPCODES_SIGJMP_BUF bailout
;
144 enum address_mode address_mode
;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored
;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes
;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info
*info
, bfd_byte
*addr
)
199 struct dis_private
*priv
= (struct dis_private
*) info
->private_data
;
200 bfd_vma start
= priv
->insn_start
+ (priv
->max_fetched
- priv
->the_buffer
);
202 if (addr
<= priv
->the_buffer
+ MAX_MNEM_SIZE
)
203 status
= (*info
->read_memory_func
) (start
,
205 addr
- priv
->max_fetched
,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv
->max_fetched
== priv
->the_buffer
)
216 (*info
->memory_error_func
) (status
, start
, info
);
217 OPCODES_SIGLONGJMP (priv
->bailout
, 1);
220 priv
->max_fetched
= addr
;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define Edqb { OP_E, dqb_mode }
237 #define Edqd { OP_E, dqd_mode }
238 #define Eq { OP_E, q_mode }
239 #define indirEv { OP_indirE, stack_v_mode }
240 #define indirEp { OP_indirE, f_mode }
241 #define stackEv { OP_E, stack_v_mode }
242 #define Em { OP_E, m_mode }
243 #define Ew { OP_E, w_mode }
244 #define M { OP_M, 0 } /* lea, lgdt, etc. */
245 #define Ma { OP_M, a_mode }
246 #define Mb { OP_M, b_mode }
247 #define Md { OP_M, d_mode }
248 #define Mo { OP_M, o_mode }
249 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
250 #define Mq { OP_M, q_mode }
251 #define Mx { OP_M, x_mode }
252 #define Mxmm { OP_M, xmm_mode }
253 #define Gb { OP_G, b_mode }
254 #define Gbnd { OP_G, bnd_mode }
255 #define Gv { OP_G, v_mode }
256 #define Gd { OP_G, d_mode }
257 #define Gdq { OP_G, dq_mode }
258 #define Gm { OP_G, m_mode }
259 #define Gw { OP_G, w_mode }
260 #define Rd { OP_R, d_mode }
261 #define Rdq { OP_R, dq_mode }
262 #define Rm { OP_R, m_mode }
263 #define Ib { OP_I, b_mode }
264 #define sIb { OP_sI, b_mode } /* sign extened byte */
265 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
266 #define Iv { OP_I, v_mode }
267 #define sIv { OP_sI, v_mode }
268 #define Iq { OP_I, q_mode }
269 #define Iv64 { OP_I64, v_mode }
270 #define Iw { OP_I, w_mode }
271 #define I1 { OP_I, const_1_mode }
272 #define Jb { OP_J, b_mode }
273 #define Jv { OP_J, v_mode }
274 #define Cm { OP_C, m_mode }
275 #define Dm { OP_D, m_mode }
276 #define Td { OP_T, d_mode }
277 #define Skip_MODRM { OP_Skip_MODRM, 0 }
279 #define RMeAX { OP_REG, eAX_reg }
280 #define RMeBX { OP_REG, eBX_reg }
281 #define RMeCX { OP_REG, eCX_reg }
282 #define RMeDX { OP_REG, eDX_reg }
283 #define RMeSP { OP_REG, eSP_reg }
284 #define RMeBP { OP_REG, eBP_reg }
285 #define RMeSI { OP_REG, eSI_reg }
286 #define RMeDI { OP_REG, eDI_reg }
287 #define RMrAX { OP_REG, rAX_reg }
288 #define RMrBX { OP_REG, rBX_reg }
289 #define RMrCX { OP_REG, rCX_reg }
290 #define RMrDX { OP_REG, rDX_reg }
291 #define RMrSP { OP_REG, rSP_reg }
292 #define RMrBP { OP_REG, rBP_reg }
293 #define RMrSI { OP_REG, rSI_reg }
294 #define RMrDI { OP_REG, rDI_reg }
295 #define RMAL { OP_REG, al_reg }
296 #define RMCL { OP_REG, cl_reg }
297 #define RMDL { OP_REG, dl_reg }
298 #define RMBL { OP_REG, bl_reg }
299 #define RMAH { OP_REG, ah_reg }
300 #define RMCH { OP_REG, ch_reg }
301 #define RMDH { OP_REG, dh_reg }
302 #define RMBH { OP_REG, bh_reg }
303 #define RMAX { OP_REG, ax_reg }
304 #define RMDX { OP_REG, dx_reg }
306 #define eAX { OP_IMREG, eAX_reg }
307 #define eBX { OP_IMREG, eBX_reg }
308 #define eCX { OP_IMREG, eCX_reg }
309 #define eDX { OP_IMREG, eDX_reg }
310 #define eSP { OP_IMREG, eSP_reg }
311 #define eBP { OP_IMREG, eBP_reg }
312 #define eSI { OP_IMREG, eSI_reg }
313 #define eDI { OP_IMREG, eDI_reg }
314 #define AL { OP_IMREG, al_reg }
315 #define CL { OP_IMREG, cl_reg }
316 #define DL { OP_IMREG, dl_reg }
317 #define BL { OP_IMREG, bl_reg }
318 #define AH { OP_IMREG, ah_reg }
319 #define CH { OP_IMREG, ch_reg }
320 #define DH { OP_IMREG, dh_reg }
321 #define BH { OP_IMREG, bh_reg }
322 #define AX { OP_IMREG, ax_reg }
323 #define DX { OP_IMREG, dx_reg }
324 #define zAX { OP_IMREG, z_mode_ax_reg }
325 #define indirDX { OP_IMREG, indir_dx_reg }
327 #define Sw { OP_SEG, w_mode }
328 #define Sv { OP_SEG, v_mode }
329 #define Ap { OP_DIR, 0 }
330 #define Ob { OP_OFF64, b_mode }
331 #define Ov { OP_OFF64, v_mode }
332 #define Xb { OP_DSreg, eSI_reg }
333 #define Xv { OP_DSreg, eSI_reg }
334 #define Xz { OP_DSreg, eSI_reg }
335 #define Yb { OP_ESreg, eDI_reg }
336 #define Yv { OP_ESreg, eDI_reg }
337 #define DSBX { OP_DSreg, eBX_reg }
339 #define es { OP_REG, es_reg }
340 #define ss { OP_REG, ss_reg }
341 #define cs { OP_REG, cs_reg }
342 #define ds { OP_REG, ds_reg }
343 #define fs { OP_REG, fs_reg }
344 #define gs { OP_REG, gs_reg }
346 #define MX { OP_MMX, 0 }
347 #define XM { OP_XMM, 0 }
348 #define XMScalar { OP_XMM, scalar_mode }
349 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
350 #define XMM { OP_XMM, xmm_mode }
351 #define XMxmmq { OP_XMM, xmmq_mode }
352 #define EM { OP_EM, v_mode }
353 #define EMS { OP_EM, v_swap_mode }
354 #define EMd { OP_EM, d_mode }
355 #define EMx { OP_EM, x_mode }
356 #define EXw { OP_EX, w_mode }
357 #define EXd { OP_EX, d_mode }
358 #define EXdScalar { OP_EX, d_scalar_mode }
359 #define EXdS { OP_EX, d_swap_mode }
360 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
361 #define EXq { OP_EX, q_mode }
362 #define EXqScalar { OP_EX, q_scalar_mode }
363 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
364 #define EXqS { OP_EX, q_swap_mode }
365 #define EXx { OP_EX, x_mode }
366 #define EXxS { OP_EX, x_swap_mode }
367 #define EXxmm { OP_EX, xmm_mode }
368 #define EXymm { OP_EX, ymm_mode }
369 #define EXxmmq { OP_EX, xmmq_mode }
370 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
371 #define EXxmm_mb { OP_EX, xmm_mb_mode }
372 #define EXxmm_mw { OP_EX, xmm_mw_mode }
373 #define EXxmm_md { OP_EX, xmm_md_mode }
374 #define EXxmm_mq { OP_EX, xmm_mq_mode }
375 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
376 #define EXxmmdw { OP_EX, xmmdw_mode }
377 #define EXxmmqd { OP_EX, xmmqd_mode }
378 #define EXymmq { OP_EX, ymmq_mode }
379 #define EXVexWdq { OP_EX, vex_w_dq_mode }
380 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
381 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
382 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
383 #define MS { OP_MS, v_mode }
384 #define XS { OP_XS, v_mode }
385 #define EMCq { OP_EMC, q_mode }
386 #define MXC { OP_MXC, 0 }
387 #define OPSUF { OP_3DNowSuffix, 0 }
388 #define CMP { CMP_Fixup, 0 }
389 #define XMM0 { XMM_Fixup, 0 }
390 #define FXSAVE { FXSAVE_Fixup, 0 }
391 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
392 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
394 #define Vex { OP_VEX, vex_mode }
395 #define VexScalar { OP_VEX, vex_scalar_mode }
396 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
397 #define Vex128 { OP_VEX, vex128_mode }
398 #define Vex256 { OP_VEX, vex256_mode }
399 #define VexGdq { OP_VEX, dq_mode }
400 #define VexI4 { VEXI4_Fixup, 0}
401 #define EXdVex { OP_EX_Vex, d_mode }
402 #define EXdVexS { OP_EX_Vex, d_swap_mode }
403 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
404 #define EXqVex { OP_EX_Vex, q_mode }
405 #define EXqVexS { OP_EX_Vex, q_swap_mode }
406 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
407 #define EXVexW { OP_EX_VexW, x_mode }
408 #define EXdVexW { OP_EX_VexW, d_mode }
409 #define EXqVexW { OP_EX_VexW, q_mode }
410 #define EXVexImmW { OP_EX_VexImmW, x_mode }
411 #define XMVex { OP_XMM_Vex, 0 }
412 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
413 #define XMVexW { OP_XMM_VexW, 0 }
414 #define XMVexI4 { OP_REG_VexI4, x_mode }
415 #define PCLMUL { PCLMUL_Fixup, 0 }
416 #define VZERO { VZERO_Fixup, 0 }
417 #define VCMP { VCMP_Fixup, 0 }
418 #define VPCMP { VPCMP_Fixup, 0 }
420 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
421 #define EXxEVexS { OP_Rounding, evex_sae_mode }
423 #define XMask { OP_Mask, mask_mode }
424 #define MaskG { OP_G, mask_mode }
425 #define MaskE { OP_E, mask_mode }
426 #define MaskR { OP_R, mask_mode }
427 #define MaskVex { OP_VEX, mask_mode }
429 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
430 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
431 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
432 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
434 /* Used handle "rep" prefix for string instructions. */
435 #define Xbr { REP_Fixup, eSI_reg }
436 #define Xvr { REP_Fixup, eSI_reg }
437 #define Ybr { REP_Fixup, eDI_reg }
438 #define Yvr { REP_Fixup, eDI_reg }
439 #define Yzr { REP_Fixup, eDI_reg }
440 #define indirDXr { REP_Fixup, indir_dx_reg }
441 #define ALr { REP_Fixup, al_reg }
442 #define eAXr { REP_Fixup, eAX_reg }
444 /* Used handle HLE prefix for lockable instructions. */
445 #define Ebh1 { HLE_Fixup1, b_mode }
446 #define Evh1 { HLE_Fixup1, v_mode }
447 #define Ebh2 { HLE_Fixup2, b_mode }
448 #define Evh2 { HLE_Fixup2, v_mode }
449 #define Ebh3 { HLE_Fixup3, b_mode }
450 #define Evh3 { HLE_Fixup3, v_mode }
452 #define BND { BND_Fixup, 0 }
454 #define cond_jump_flag { NULL, cond_jump_mode }
455 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
457 /* bits in sizeflag */
458 #define SUFFIX_ALWAYS 4
466 /* byte operand with operand swapped */
468 /* byte operand, sign extend like 'T' suffix */
470 /* operand size depends on prefixes */
472 /* operand size depends on prefixes with operand swapped */
476 /* double word operand */
478 /* double word operand with operand swapped */
480 /* quad word operand */
482 /* quad word operand with operand swapped */
484 /* ten-byte operand */
486 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
487 broadcast enabled. */
489 /* Similar to x_mode, but with different EVEX mem shifts. */
491 /* Similar to x_mode, but with disabled broadcast. */
493 /* Similar to x_mode, but with operands swapped and disabled broadcast
496 /* 16-byte XMM operand */
498 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
499 memory operand (depending on vector length). Broadcast isn't
502 /* Same as xmmq_mode, but broadcast is allowed. */
503 evex_half_bcst_xmmq_mode
,
504 /* XMM register or byte memory operand */
506 /* XMM register or word memory operand */
508 /* XMM register or double word memory operand */
510 /* XMM register or quad word memory operand */
512 /* XMM register or double/quad word memory operand, depending on
515 /* 16-byte XMM, word, double word or quad word operand. */
517 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
519 /* 32-byte YMM operand */
521 /* quad word, ymmword or zmmword memory operand. */
523 /* 32-byte YMM or 16-byte word operand */
525 /* d_mode in 32bit, q_mode in 64bit mode. */
527 /* pair of v_mode operands */
532 /* operand size depends on REX prefixes. */
534 /* registers like dq_mode, memory like w_mode. */
537 /* 4- or 6-byte pointer operand */
540 /* v_mode for stack-related opcodes. */
542 /* non-quad operand size depends on prefixes */
544 /* 16-byte operand */
546 /* registers like dq_mode, memory like b_mode. */
548 /* registers like dq_mode, memory like d_mode. */
550 /* normal vex mode */
552 /* 128bit vex mode */
554 /* 256bit vex mode */
556 /* operand size depends on the VEX.W bit. */
559 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
560 vex_vsib_d_w_dq_mode
,
561 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
563 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
564 vex_vsib_q_w_dq_mode
,
565 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
568 /* scalar, ignore vector length. */
570 /* like d_mode, ignore vector length. */
572 /* like d_swap_mode, ignore vector length. */
574 /* like q_mode, ignore vector length. */
576 /* like q_swap_mode, ignore vector length. */
578 /* like vex_mode, ignore vector length. */
580 /* like vex_w_dq_mode, ignore vector length. */
581 vex_scalar_w_dq_mode
,
583 /* Static rounding. */
585 /* Supress all exceptions. */
588 /* Mask register operand. */
655 #define FLOAT NULL, { { NULL, FLOATCODE } }
657 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
658 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
659 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
660 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
661 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
662 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
663 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
664 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
665 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
666 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
667 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
668 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
669 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
788 MOD_VEX_0F12_PREFIX_0
,
790 MOD_VEX_0F16_PREFIX_0
,
806 MOD_VEX_0FD7_PREFIX_2
,
807 MOD_VEX_0FE7_PREFIX_2
,
808 MOD_VEX_0FF0_PREFIX_3
,
809 MOD_VEX_0F381A_PREFIX_2
,
810 MOD_VEX_0F382A_PREFIX_2
,
811 MOD_VEX_0F382C_PREFIX_2
,
812 MOD_VEX_0F382D_PREFIX_2
,
813 MOD_VEX_0F382E_PREFIX_2
,
814 MOD_VEX_0F382F_PREFIX_2
,
815 MOD_VEX_0F385A_PREFIX_2
,
816 MOD_VEX_0F388C_PREFIX_2
,
817 MOD_VEX_0F388E_PREFIX_2
,
819 MOD_EVEX_0F10_PREFIX_1
,
820 MOD_EVEX_0F10_PREFIX_3
,
821 MOD_EVEX_0F11_PREFIX_1
,
822 MOD_EVEX_0F11_PREFIX_3
,
823 MOD_EVEX_0F12_PREFIX_0
,
824 MOD_EVEX_0F16_PREFIX_0
,
825 MOD_EVEX_0F38C6_REG_1
,
826 MOD_EVEX_0F38C6_REG_2
,
827 MOD_EVEX_0F38C6_REG_5
,
828 MOD_EVEX_0F38C6_REG_6
,
829 MOD_EVEX_0F38C7_REG_1
,
830 MOD_EVEX_0F38C7_REG_2
,
831 MOD_EVEX_0F38C7_REG_5
,
832 MOD_EVEX_0F38C7_REG_6
1023 PREFIX_VEX_0F71_REG_2
,
1024 PREFIX_VEX_0F71_REG_4
,
1025 PREFIX_VEX_0F71_REG_6
,
1026 PREFIX_VEX_0F72_REG_2
,
1027 PREFIX_VEX_0F72_REG_4
,
1028 PREFIX_VEX_0F72_REG_6
,
1029 PREFIX_VEX_0F73_REG_2
,
1030 PREFIX_VEX_0F73_REG_3
,
1031 PREFIX_VEX_0F73_REG_6
,
1032 PREFIX_VEX_0F73_REG_7
,
1203 PREFIX_VEX_0F38F3_REG_1
,
1204 PREFIX_VEX_0F38F3_REG_2
,
1205 PREFIX_VEX_0F38F3_REG_3
,
1307 PREFIX_EVEX_0F72_REG_0
,
1308 PREFIX_EVEX_0F72_REG_1
,
1309 PREFIX_EVEX_0F72_REG_2
,
1310 PREFIX_EVEX_0F72_REG_4
,
1311 PREFIX_EVEX_0F72_REG_6
,
1312 PREFIX_EVEX_0F73_REG_2
,
1313 PREFIX_EVEX_0F73_REG_6
,
1442 PREFIX_EVEX_0F38C6_REG_1
,
1443 PREFIX_EVEX_0F38C6_REG_2
,
1444 PREFIX_EVEX_0F38C6_REG_5
,
1445 PREFIX_EVEX_0F38C6_REG_6
,
1446 PREFIX_EVEX_0F38C7_REG_1
,
1447 PREFIX_EVEX_0F38C7_REG_2
,
1448 PREFIX_EVEX_0F38C7_REG_5
,
1449 PREFIX_EVEX_0F38C7_REG_6
,
1521 THREE_BYTE_0F38
= 0,
1549 VEX_LEN_0F10_P_1
= 0,
1553 VEX_LEN_0F12_P_0_M_0
,
1554 VEX_LEN_0F12_P_0_M_1
,
1557 VEX_LEN_0F16_P_0_M_0
,
1558 VEX_LEN_0F16_P_0_M_1
,
1604 VEX_LEN_0FAE_R_2_M_0
,
1605 VEX_LEN_0FAE_R_3_M_0
,
1614 VEX_LEN_0F381A_P_2_M_0
,
1617 VEX_LEN_0F385A_P_2_M_0
,
1624 VEX_LEN_0F38F3_R_1_P_0
,
1625 VEX_LEN_0F38F3_R_2_P_0
,
1626 VEX_LEN_0F38F3_R_3_P_0
,
1670 VEX_LEN_0FXOP_08_CC
,
1671 VEX_LEN_0FXOP_08_CD
,
1672 VEX_LEN_0FXOP_08_CE
,
1673 VEX_LEN_0FXOP_08_CF
,
1674 VEX_LEN_0FXOP_08_EC
,
1675 VEX_LEN_0FXOP_08_ED
,
1676 VEX_LEN_0FXOP_08_EE
,
1677 VEX_LEN_0FXOP_08_EF
,
1678 VEX_LEN_0FXOP_09_80
,
1712 VEX_W_0F41_P_0_LEN_1
,
1713 VEX_W_0F42_P_0_LEN_1
,
1714 VEX_W_0F44_P_0_LEN_0
,
1715 VEX_W_0F45_P_0_LEN_1
,
1716 VEX_W_0F46_P_0_LEN_1
,
1717 VEX_W_0F47_P_0_LEN_1
,
1718 VEX_W_0F4B_P_2_LEN_1
,
1798 VEX_W_0F90_P_0_LEN_0
,
1799 VEX_W_0F91_P_0_LEN_0
,
1800 VEX_W_0F92_P_0_LEN_0
,
1801 VEX_W_0F93_P_0_LEN_0
,
1802 VEX_W_0F98_P_0_LEN_0
,
1881 VEX_W_0F381A_P_2_M_0
,
1893 VEX_W_0F382A_P_2_M_0
,
1895 VEX_W_0F382C_P_2_M_0
,
1896 VEX_W_0F382D_P_2_M_0
,
1897 VEX_W_0F382E_P_2_M_0
,
1898 VEX_W_0F382F_P_2_M_0
,
1920 VEX_W_0F385A_P_2_M_0
,
1948 VEX_W_0F3A30_P_2_LEN_0
,
1949 VEX_W_0F3A32_P_2_LEN_0
,
1969 EVEX_W_0F10_P_1_M_0
,
1970 EVEX_W_0F10_P_1_M_1
,
1972 EVEX_W_0F10_P_3_M_0
,
1973 EVEX_W_0F10_P_3_M_1
,
1975 EVEX_W_0F11_P_1_M_0
,
1976 EVEX_W_0F11_P_1_M_1
,
1978 EVEX_W_0F11_P_3_M_0
,
1979 EVEX_W_0F11_P_3_M_1
,
1980 EVEX_W_0F12_P_0_M_0
,
1981 EVEX_W_0F12_P_0_M_1
,
1991 EVEX_W_0F16_P_0_M_0
,
1992 EVEX_W_0F16_P_0_M_1
,
2053 EVEX_W_0F72_R_2_P_2
,
2054 EVEX_W_0F72_R_6_P_2
,
2055 EVEX_W_0F73_R_2_P_2
,
2056 EVEX_W_0F73_R_6_P_2
,
2129 EVEX_W_0F38C7_R_1_P_2
,
2130 EVEX_W_0F38C7_R_2_P_2
,
2131 EVEX_W_0F38C7_R_5_P_2
,
2132 EVEX_W_0F38C7_R_6_P_2
,
2156 typedef void (*op_rtn
) (int bytemode
, int sizeflag
);
2167 /* Upper case letters in the instruction names here are macros.
2168 'A' => print 'b' if no register operands or suffix_always is true
2169 'B' => print 'b' if suffix_always is true
2170 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2172 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2173 suffix_always is true
2174 'E' => print 'e' if 32-bit form of jcxz
2175 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2176 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2177 'H' => print ",pt" or ",pn" branch hint
2178 'I' => honor following macro letter even in Intel mode (implemented only
2179 for some of the macro letters)
2181 'K' => print 'd' or 'q' if rex prefix is present.
2182 'L' => print 'l' if suffix_always is true
2183 'M' => print 'r' if intel_mnemonic is false.
2184 'N' => print 'n' if instruction has no wait "prefix"
2185 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2186 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2187 or suffix_always is true. print 'q' if rex prefix is present.
2188 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2190 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2191 'S' => print 'w', 'l' or 'q' if suffix_always is true
2192 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2193 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2194 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2195 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2196 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2197 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2198 suffix_always is true.
2199 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2200 '!' => change condition from true to false or from false to true.
2201 '%' => add 1 upper case letter to the macro.
2203 2 upper case letter macros:
2204 "XY" => print 'x' or 'y' if no register operands or suffix_always
2206 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2207 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2208 or suffix_always is true
2209 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2210 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2211 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2212 "LW" => print 'd', 'q' depending on the VEX.W bit
2214 Many of the above letters print nothing in Intel mode. See "putop"
2217 Braces '{' and '}', and vertical bars '|', indicate alternative
2218 mnemonic strings for AT&T and Intel. */
2220 static const struct dis386 dis386
[] = {
2222 { "addB", { Ebh1
, Gb
} },
2223 { "addS", { Evh1
, Gv
} },
2224 { "addB", { Gb
, EbS
} },
2225 { "addS", { Gv
, EvS
} },
2226 { "addB", { AL
, Ib
} },
2227 { "addS", { eAX
, Iv
} },
2228 { X86_64_TABLE (X86_64_06
) },
2229 { X86_64_TABLE (X86_64_07
) },
2231 { "orB", { Ebh1
, Gb
} },
2232 { "orS", { Evh1
, Gv
} },
2233 { "orB", { Gb
, EbS
} },
2234 { "orS", { Gv
, EvS
} },
2235 { "orB", { AL
, Ib
} },
2236 { "orS", { eAX
, Iv
} },
2237 { X86_64_TABLE (X86_64_0D
) },
2238 { Bad_Opcode
}, /* 0x0f extended opcode escape */
2240 { "adcB", { Ebh1
, Gb
} },
2241 { "adcS", { Evh1
, Gv
} },
2242 { "adcB", { Gb
, EbS
} },
2243 { "adcS", { Gv
, EvS
} },
2244 { "adcB", { AL
, Ib
} },
2245 { "adcS", { eAX
, Iv
} },
2246 { X86_64_TABLE (X86_64_16
) },
2247 { X86_64_TABLE (X86_64_17
) },
2249 { "sbbB", { Ebh1
, Gb
} },
2250 { "sbbS", { Evh1
, Gv
} },
2251 { "sbbB", { Gb
, EbS
} },
2252 { "sbbS", { Gv
, EvS
} },
2253 { "sbbB", { AL
, Ib
} },
2254 { "sbbS", { eAX
, Iv
} },
2255 { X86_64_TABLE (X86_64_1E
) },
2256 { X86_64_TABLE (X86_64_1F
) },
2258 { "andB", { Ebh1
, Gb
} },
2259 { "andS", { Evh1
, Gv
} },
2260 { "andB", { Gb
, EbS
} },
2261 { "andS", { Gv
, EvS
} },
2262 { "andB", { AL
, Ib
} },
2263 { "andS", { eAX
, Iv
} },
2264 { Bad_Opcode
}, /* SEG ES prefix */
2265 { X86_64_TABLE (X86_64_27
) },
2267 { "subB", { Ebh1
, Gb
} },
2268 { "subS", { Evh1
, Gv
} },
2269 { "subB", { Gb
, EbS
} },
2270 { "subS", { Gv
, EvS
} },
2271 { "subB", { AL
, Ib
} },
2272 { "subS", { eAX
, Iv
} },
2273 { Bad_Opcode
}, /* SEG CS prefix */
2274 { X86_64_TABLE (X86_64_2F
) },
2276 { "xorB", { Ebh1
, Gb
} },
2277 { "xorS", { Evh1
, Gv
} },
2278 { "xorB", { Gb
, EbS
} },
2279 { "xorS", { Gv
, EvS
} },
2280 { "xorB", { AL
, Ib
} },
2281 { "xorS", { eAX
, Iv
} },
2282 { Bad_Opcode
}, /* SEG SS prefix */
2283 { X86_64_TABLE (X86_64_37
) },
2285 { "cmpB", { Eb
, Gb
} },
2286 { "cmpS", { Ev
, Gv
} },
2287 { "cmpB", { Gb
, EbS
} },
2288 { "cmpS", { Gv
, EvS
} },
2289 { "cmpB", { AL
, Ib
} },
2290 { "cmpS", { eAX
, Iv
} },
2291 { Bad_Opcode
}, /* SEG DS prefix */
2292 { X86_64_TABLE (X86_64_3F
) },
2294 { "inc{S|}", { RMeAX
} },
2295 { "inc{S|}", { RMeCX
} },
2296 { "inc{S|}", { RMeDX
} },
2297 { "inc{S|}", { RMeBX
} },
2298 { "inc{S|}", { RMeSP
} },
2299 { "inc{S|}", { RMeBP
} },
2300 { "inc{S|}", { RMeSI
} },
2301 { "inc{S|}", { RMeDI
} },
2303 { "dec{S|}", { RMeAX
} },
2304 { "dec{S|}", { RMeCX
} },
2305 { "dec{S|}", { RMeDX
} },
2306 { "dec{S|}", { RMeBX
} },
2307 { "dec{S|}", { RMeSP
} },
2308 { "dec{S|}", { RMeBP
} },
2309 { "dec{S|}", { RMeSI
} },
2310 { "dec{S|}", { RMeDI
} },
2312 { "pushV", { RMrAX
} },
2313 { "pushV", { RMrCX
} },
2314 { "pushV", { RMrDX
} },
2315 { "pushV", { RMrBX
} },
2316 { "pushV", { RMrSP
} },
2317 { "pushV", { RMrBP
} },
2318 { "pushV", { RMrSI
} },
2319 { "pushV", { RMrDI
} },
2321 { "popV", { RMrAX
} },
2322 { "popV", { RMrCX
} },
2323 { "popV", { RMrDX
} },
2324 { "popV", { RMrBX
} },
2325 { "popV", { RMrSP
} },
2326 { "popV", { RMrBP
} },
2327 { "popV", { RMrSI
} },
2328 { "popV", { RMrDI
} },
2330 { X86_64_TABLE (X86_64_60
) },
2331 { X86_64_TABLE (X86_64_61
) },
2332 { X86_64_TABLE (X86_64_62
) },
2333 { X86_64_TABLE (X86_64_63
) },
2334 { Bad_Opcode
}, /* seg fs */
2335 { Bad_Opcode
}, /* seg gs */
2336 { Bad_Opcode
}, /* op size prefix */
2337 { Bad_Opcode
}, /* adr size prefix */
2339 { "pushT", { sIv
} },
2340 { "imulS", { Gv
, Ev
, Iv
} },
2341 { "pushT", { sIbT
} },
2342 { "imulS", { Gv
, Ev
, sIb
} },
2343 { "ins{b|}", { Ybr
, indirDX
} },
2344 { X86_64_TABLE (X86_64_6D
) },
2345 { "outs{b|}", { indirDXr
, Xb
} },
2346 { X86_64_TABLE (X86_64_6F
) },
2348 { "joH", { Jb
, BND
, cond_jump_flag
} },
2349 { "jnoH", { Jb
, BND
, cond_jump_flag
} },
2350 { "jbH", { Jb
, BND
, cond_jump_flag
} },
2351 { "jaeH", { Jb
, BND
, cond_jump_flag
} },
2352 { "jeH", { Jb
, BND
, cond_jump_flag
} },
2353 { "jneH", { Jb
, BND
, cond_jump_flag
} },
2354 { "jbeH", { Jb
, BND
, cond_jump_flag
} },
2355 { "jaH", { Jb
, BND
, cond_jump_flag
} },
2357 { "jsH", { Jb
, BND
, cond_jump_flag
} },
2358 { "jnsH", { Jb
, BND
, cond_jump_flag
} },
2359 { "jpH", { Jb
, BND
, cond_jump_flag
} },
2360 { "jnpH", { Jb
, BND
, cond_jump_flag
} },
2361 { "jlH", { Jb
, BND
, cond_jump_flag
} },
2362 { "jgeH", { Jb
, BND
, cond_jump_flag
} },
2363 { "jleH", { Jb
, BND
, cond_jump_flag
} },
2364 { "jgH", { Jb
, BND
, cond_jump_flag
} },
2366 { REG_TABLE (REG_80
) },
2367 { REG_TABLE (REG_81
) },
2369 { REG_TABLE (REG_82
) },
2370 { "testB", { Eb
, Gb
} },
2371 { "testS", { Ev
, Gv
} },
2372 { "xchgB", { Ebh2
, Gb
} },
2373 { "xchgS", { Evh2
, Gv
} },
2375 { "movB", { Ebh3
, Gb
} },
2376 { "movS", { Evh3
, Gv
} },
2377 { "movB", { Gb
, EbS
} },
2378 { "movS", { Gv
, EvS
} },
2379 { "movD", { Sv
, Sw
} },
2380 { MOD_TABLE (MOD_8D
) },
2381 { "movD", { Sw
, Sv
} },
2382 { REG_TABLE (REG_8F
) },
2384 { PREFIX_TABLE (PREFIX_90
) },
2385 { "xchgS", { RMeCX
, eAX
} },
2386 { "xchgS", { RMeDX
, eAX
} },
2387 { "xchgS", { RMeBX
, eAX
} },
2388 { "xchgS", { RMeSP
, eAX
} },
2389 { "xchgS", { RMeBP
, eAX
} },
2390 { "xchgS", { RMeSI
, eAX
} },
2391 { "xchgS", { RMeDI
, eAX
} },
2393 { "cW{t|}R", { XX
} },
2394 { "cR{t|}O", { XX
} },
2395 { X86_64_TABLE (X86_64_9A
) },
2396 { Bad_Opcode
}, /* fwait */
2397 { "pushfT", { XX
} },
2398 { "popfT", { XX
} },
2402 { "mov%LB", { AL
, Ob
} },
2403 { "mov%LS", { eAX
, Ov
} },
2404 { "mov%LB", { Ob
, AL
} },
2405 { "mov%LS", { Ov
, eAX
} },
2406 { "movs{b|}", { Ybr
, Xb
} },
2407 { "movs{R|}", { Yvr
, Xv
} },
2408 { "cmps{b|}", { Xb
, Yb
} },
2409 { "cmps{R|}", { Xv
, Yv
} },
2411 { "testB", { AL
, Ib
} },
2412 { "testS", { eAX
, Iv
} },
2413 { "stosB", { Ybr
, AL
} },
2414 { "stosS", { Yvr
, eAX
} },
2415 { "lodsB", { ALr
, Xb
} },
2416 { "lodsS", { eAXr
, Xv
} },
2417 { "scasB", { AL
, Yb
} },
2418 { "scasS", { eAX
, Yv
} },
2420 { "movB", { RMAL
, Ib
} },
2421 { "movB", { RMCL
, Ib
} },
2422 { "movB", { RMDL
, Ib
} },
2423 { "movB", { RMBL
, Ib
} },
2424 { "movB", { RMAH
, Ib
} },
2425 { "movB", { RMCH
, Ib
} },
2426 { "movB", { RMDH
, Ib
} },
2427 { "movB", { RMBH
, Ib
} },
2429 { "mov%LV", { RMeAX
, Iv64
} },
2430 { "mov%LV", { RMeCX
, Iv64
} },
2431 { "mov%LV", { RMeDX
, Iv64
} },
2432 { "mov%LV", { RMeBX
, Iv64
} },
2433 { "mov%LV", { RMeSP
, Iv64
} },
2434 { "mov%LV", { RMeBP
, Iv64
} },
2435 { "mov%LV", { RMeSI
, Iv64
} },
2436 { "mov%LV", { RMeDI
, Iv64
} },
2438 { REG_TABLE (REG_C0
) },
2439 { REG_TABLE (REG_C1
) },
2440 { "retT", { Iw
, BND
} },
2441 { "retT", { BND
} },
2442 { X86_64_TABLE (X86_64_C4
) },
2443 { X86_64_TABLE (X86_64_C5
) },
2444 { REG_TABLE (REG_C6
) },
2445 { REG_TABLE (REG_C7
) },
2447 { "enterT", { Iw
, Ib
} },
2448 { "leaveT", { XX
} },
2449 { "Jret{|f}P", { Iw
} },
2450 { "Jret{|f}P", { XX
} },
2453 { X86_64_TABLE (X86_64_CE
) },
2454 { "iretP", { XX
} },
2456 { REG_TABLE (REG_D0
) },
2457 { REG_TABLE (REG_D1
) },
2458 { REG_TABLE (REG_D2
) },
2459 { REG_TABLE (REG_D3
) },
2460 { X86_64_TABLE (X86_64_D4
) },
2461 { X86_64_TABLE (X86_64_D5
) },
2463 { "xlat", { DSBX
} },
2474 { "loopneFH", { Jb
, XX
, loop_jcxz_flag
} },
2475 { "loopeFH", { Jb
, XX
, loop_jcxz_flag
} },
2476 { "loopFH", { Jb
, XX
, loop_jcxz_flag
} },
2477 { "jEcxzH", { Jb
, XX
, loop_jcxz_flag
} },
2478 { "inB", { AL
, Ib
} },
2479 { "inG", { zAX
, Ib
} },
2480 { "outB", { Ib
, AL
} },
2481 { "outG", { Ib
, zAX
} },
2483 { "callT", { Jv
, BND
} },
2484 { "jmpT", { Jv
, BND
} },
2485 { X86_64_TABLE (X86_64_EA
) },
2486 { "jmp", { Jb
, BND
} },
2487 { "inB", { AL
, indirDX
} },
2488 { "inG", { zAX
, indirDX
} },
2489 { "outB", { indirDX
, AL
} },
2490 { "outG", { indirDX
, zAX
} },
2492 { Bad_Opcode
}, /* lock prefix */
2493 { "icebp", { XX
} },
2494 { Bad_Opcode
}, /* repne */
2495 { Bad_Opcode
}, /* repz */
2498 { REG_TABLE (REG_F6
) },
2499 { REG_TABLE (REG_F7
) },
2507 { REG_TABLE (REG_FE
) },
2508 { REG_TABLE (REG_FF
) },
2511 static const struct dis386 dis386_twobyte
[] = {
2513 { REG_TABLE (REG_0F00
) },
2514 { REG_TABLE (REG_0F01
) },
2515 { "larS", { Gv
, Ew
} },
2516 { "lslS", { Gv
, Ew
} },
2518 { "syscall", { XX
} },
2520 { "sysretP", { XX
} },
2523 { "wbinvd", { XX
} },
2527 { REG_TABLE (REG_0F0D
) },
2528 { "femms", { XX
} },
2529 { "", { MX
, EM
, OPSUF
} }, /* See OP_3DNowSuffix. */
2531 { PREFIX_TABLE (PREFIX_0F10
) },
2532 { PREFIX_TABLE (PREFIX_0F11
) },
2533 { PREFIX_TABLE (PREFIX_0F12
) },
2534 { MOD_TABLE (MOD_0F13
) },
2535 { "unpcklpX", { XM
, EXx
} },
2536 { "unpckhpX", { XM
, EXx
} },
2537 { PREFIX_TABLE (PREFIX_0F16
) },
2538 { MOD_TABLE (MOD_0F17
) },
2540 { REG_TABLE (REG_0F18
) },
2542 { PREFIX_TABLE (PREFIX_0F1A
) },
2543 { PREFIX_TABLE (PREFIX_0F1B
) },
2549 { MOD_TABLE (MOD_0F20
) },
2550 { MOD_TABLE (MOD_0F21
) },
2551 { MOD_TABLE (MOD_0F22
) },
2552 { MOD_TABLE (MOD_0F23
) },
2553 { MOD_TABLE (MOD_0F24
) },
2555 { MOD_TABLE (MOD_0F26
) },
2558 { "movapX", { XM
, EXx
} },
2559 { "movapX", { EXxS
, XM
} },
2560 { PREFIX_TABLE (PREFIX_0F2A
) },
2561 { PREFIX_TABLE (PREFIX_0F2B
) },
2562 { PREFIX_TABLE (PREFIX_0F2C
) },
2563 { PREFIX_TABLE (PREFIX_0F2D
) },
2564 { PREFIX_TABLE (PREFIX_0F2E
) },
2565 { PREFIX_TABLE (PREFIX_0F2F
) },
2567 { "wrmsr", { XX
} },
2568 { "rdtsc", { XX
} },
2569 { "rdmsr", { XX
} },
2570 { "rdpmc", { XX
} },
2571 { "sysenter", { XX
} },
2572 { "sysexit", { XX
} },
2574 { "getsec", { XX
} },
2576 { THREE_BYTE_TABLE (THREE_BYTE_0F38
) },
2578 { THREE_BYTE_TABLE (THREE_BYTE_0F3A
) },
2585 { "cmovoS", { Gv
, Ev
} },
2586 { "cmovnoS", { Gv
, Ev
} },
2587 { "cmovbS", { Gv
, Ev
} },
2588 { "cmovaeS", { Gv
, Ev
} },
2589 { "cmoveS", { Gv
, Ev
} },
2590 { "cmovneS", { Gv
, Ev
} },
2591 { "cmovbeS", { Gv
, Ev
} },
2592 { "cmovaS", { Gv
, Ev
} },
2594 { "cmovsS", { Gv
, Ev
} },
2595 { "cmovnsS", { Gv
, Ev
} },
2596 { "cmovpS", { Gv
, Ev
} },
2597 { "cmovnpS", { Gv
, Ev
} },
2598 { "cmovlS", { Gv
, Ev
} },
2599 { "cmovgeS", { Gv
, Ev
} },
2600 { "cmovleS", { Gv
, Ev
} },
2601 { "cmovgS", { Gv
, Ev
} },
2603 { MOD_TABLE (MOD_0F51
) },
2604 { PREFIX_TABLE (PREFIX_0F51
) },
2605 { PREFIX_TABLE (PREFIX_0F52
) },
2606 { PREFIX_TABLE (PREFIX_0F53
) },
2607 { "andpX", { XM
, EXx
} },
2608 { "andnpX", { XM
, EXx
} },
2609 { "orpX", { XM
, EXx
} },
2610 { "xorpX", { XM
, EXx
} },
2612 { PREFIX_TABLE (PREFIX_0F58
) },
2613 { PREFIX_TABLE (PREFIX_0F59
) },
2614 { PREFIX_TABLE (PREFIX_0F5A
) },
2615 { PREFIX_TABLE (PREFIX_0F5B
) },
2616 { PREFIX_TABLE (PREFIX_0F5C
) },
2617 { PREFIX_TABLE (PREFIX_0F5D
) },
2618 { PREFIX_TABLE (PREFIX_0F5E
) },
2619 { PREFIX_TABLE (PREFIX_0F5F
) },
2621 { PREFIX_TABLE (PREFIX_0F60
) },
2622 { PREFIX_TABLE (PREFIX_0F61
) },
2623 { PREFIX_TABLE (PREFIX_0F62
) },
2624 { "packsswb", { MX
, EM
} },
2625 { "pcmpgtb", { MX
, EM
} },
2626 { "pcmpgtw", { MX
, EM
} },
2627 { "pcmpgtd", { MX
, EM
} },
2628 { "packuswb", { MX
, EM
} },
2630 { "punpckhbw", { MX
, EM
} },
2631 { "punpckhwd", { MX
, EM
} },
2632 { "punpckhdq", { MX
, EM
} },
2633 { "packssdw", { MX
, EM
} },
2634 { PREFIX_TABLE (PREFIX_0F6C
) },
2635 { PREFIX_TABLE (PREFIX_0F6D
) },
2636 { "movK", { MX
, Edq
} },
2637 { PREFIX_TABLE (PREFIX_0F6F
) },
2639 { PREFIX_TABLE (PREFIX_0F70
) },
2640 { REG_TABLE (REG_0F71
) },
2641 { REG_TABLE (REG_0F72
) },
2642 { REG_TABLE (REG_0F73
) },
2643 { "pcmpeqb", { MX
, EM
} },
2644 { "pcmpeqw", { MX
, EM
} },
2645 { "pcmpeqd", { MX
, EM
} },
2648 { PREFIX_TABLE (PREFIX_0F78
) },
2649 { PREFIX_TABLE (PREFIX_0F79
) },
2650 { THREE_BYTE_TABLE (THREE_BYTE_0F7A
) },
2652 { PREFIX_TABLE (PREFIX_0F7C
) },
2653 { PREFIX_TABLE (PREFIX_0F7D
) },
2654 { PREFIX_TABLE (PREFIX_0F7E
) },
2655 { PREFIX_TABLE (PREFIX_0F7F
) },
2657 { "joH", { Jv
, BND
, cond_jump_flag
} },
2658 { "jnoH", { Jv
, BND
, cond_jump_flag
} },
2659 { "jbH", { Jv
, BND
, cond_jump_flag
} },
2660 { "jaeH", { Jv
, BND
, cond_jump_flag
} },
2661 { "jeH", { Jv
, BND
, cond_jump_flag
} },
2662 { "jneH", { Jv
, BND
, cond_jump_flag
} },
2663 { "jbeH", { Jv
, BND
, cond_jump_flag
} },
2664 { "jaH", { Jv
, BND
, cond_jump_flag
} },
2666 { "jsH", { Jv
, BND
, cond_jump_flag
} },
2667 { "jnsH", { Jv
, BND
, cond_jump_flag
} },
2668 { "jpH", { Jv
, BND
, cond_jump_flag
} },
2669 { "jnpH", { Jv
, BND
, cond_jump_flag
} },
2670 { "jlH", { Jv
, BND
, cond_jump_flag
} },
2671 { "jgeH", { Jv
, BND
, cond_jump_flag
} },
2672 { "jleH", { Jv
, BND
, cond_jump_flag
} },
2673 { "jgH", { Jv
, BND
, cond_jump_flag
} },
2676 { "setno", { Eb
} },
2678 { "setae", { Eb
} },
2680 { "setne", { Eb
} },
2681 { "setbe", { Eb
} },
2685 { "setns", { Eb
} },
2687 { "setnp", { Eb
} },
2689 { "setge", { Eb
} },
2690 { "setle", { Eb
} },
2693 { "pushT", { fs
} },
2695 { "cpuid", { XX
} },
2696 { "btS", { Ev
, Gv
} },
2697 { "shldS", { Ev
, Gv
, Ib
} },
2698 { "shldS", { Ev
, Gv
, CL
} },
2699 { REG_TABLE (REG_0FA6
) },
2700 { REG_TABLE (REG_0FA7
) },
2702 { "pushT", { gs
} },
2705 { "btsS", { Evh1
, Gv
} },
2706 { "shrdS", { Ev
, Gv
, Ib
} },
2707 { "shrdS", { Ev
, Gv
, CL
} },
2708 { REG_TABLE (REG_0FAE
) },
2709 { "imulS", { Gv
, Ev
} },
2711 { "cmpxchgB", { Ebh1
, Gb
} },
2712 { "cmpxchgS", { Evh1
, Gv
} },
2713 { MOD_TABLE (MOD_0FB2
) },
2714 { "btrS", { Evh1
, Gv
} },
2715 { MOD_TABLE (MOD_0FB4
) },
2716 { MOD_TABLE (MOD_0FB5
) },
2717 { "movz{bR|x}", { Gv
, Eb
} },
2718 { "movz{wR|x}", { Gv
, Ew
} }, /* yes, there really is movzww ! */
2720 { PREFIX_TABLE (PREFIX_0FB8
) },
2722 { REG_TABLE (REG_0FBA
) },
2723 { "btcS", { Evh1
, Gv
} },
2724 { PREFIX_TABLE (PREFIX_0FBC
) },
2725 { PREFIX_TABLE (PREFIX_0FBD
) },
2726 { "movs{bR|x}", { Gv
, Eb
} },
2727 { "movs{wR|x}", { Gv
, Ew
} }, /* yes, there really is movsww ! */
2729 { "xaddB", { Ebh1
, Gb
} },
2730 { "xaddS", { Evh1
, Gv
} },
2731 { PREFIX_TABLE (PREFIX_0FC2
) },
2732 { PREFIX_TABLE (PREFIX_0FC3
) },
2733 { "pinsrw", { MX
, Edqw
, Ib
} },
2734 { "pextrw", { Gdq
, MS
, Ib
} },
2735 { "shufpX", { XM
, EXx
, Ib
} },
2736 { REG_TABLE (REG_0FC7
) },
2738 { "bswap", { RMeAX
} },
2739 { "bswap", { RMeCX
} },
2740 { "bswap", { RMeDX
} },
2741 { "bswap", { RMeBX
} },
2742 { "bswap", { RMeSP
} },
2743 { "bswap", { RMeBP
} },
2744 { "bswap", { RMeSI
} },
2745 { "bswap", { RMeDI
} },
2747 { PREFIX_TABLE (PREFIX_0FD0
) },
2748 { "psrlw", { MX
, EM
} },
2749 { "psrld", { MX
, EM
} },
2750 { "psrlq", { MX
, EM
} },
2751 { "paddq", { MX
, EM
} },
2752 { "pmullw", { MX
, EM
} },
2753 { PREFIX_TABLE (PREFIX_0FD6
) },
2754 { MOD_TABLE (MOD_0FD7
) },
2756 { "psubusb", { MX
, EM
} },
2757 { "psubusw", { MX
, EM
} },
2758 { "pminub", { MX
, EM
} },
2759 { "pand", { MX
, EM
} },
2760 { "paddusb", { MX
, EM
} },
2761 { "paddusw", { MX
, EM
} },
2762 { "pmaxub", { MX
, EM
} },
2763 { "pandn", { MX
, EM
} },
2765 { "pavgb", { MX
, EM
} },
2766 { "psraw", { MX
, EM
} },
2767 { "psrad", { MX
, EM
} },
2768 { "pavgw", { MX
, EM
} },
2769 { "pmulhuw", { MX
, EM
} },
2770 { "pmulhw", { MX
, EM
} },
2771 { PREFIX_TABLE (PREFIX_0FE6
) },
2772 { PREFIX_TABLE (PREFIX_0FE7
) },
2774 { "psubsb", { MX
, EM
} },
2775 { "psubsw", { MX
, EM
} },
2776 { "pminsw", { MX
, EM
} },
2777 { "por", { MX
, EM
} },
2778 { "paddsb", { MX
, EM
} },
2779 { "paddsw", { MX
, EM
} },
2780 { "pmaxsw", { MX
, EM
} },
2781 { "pxor", { MX
, EM
} },
2783 { PREFIX_TABLE (PREFIX_0FF0
) },
2784 { "psllw", { MX
, EM
} },
2785 { "pslld", { MX
, EM
} },
2786 { "psllq", { MX
, EM
} },
2787 { "pmuludq", { MX
, EM
} },
2788 { "pmaddwd", { MX
, EM
} },
2789 { "psadbw", { MX
, EM
} },
2790 { PREFIX_TABLE (PREFIX_0FF7
) },
2792 { "psubb", { MX
, EM
} },
2793 { "psubw", { MX
, EM
} },
2794 { "psubd", { MX
, EM
} },
2795 { "psubq", { MX
, EM
} },
2796 { "paddb", { MX
, EM
} },
2797 { "paddw", { MX
, EM
} },
2798 { "paddd", { MX
, EM
} },
2802 static const unsigned char onebyte_has_modrm
[256] = {
2803 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2804 /* ------------------------------- */
2805 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2806 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2807 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2808 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2809 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2810 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2811 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2812 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2813 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2814 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2815 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2816 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2817 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2818 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2819 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2820 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2821 /* ------------------------------- */
2822 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2825 static const unsigned char twobyte_has_modrm
[256] = {
2826 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2827 /* ------------------------------- */
2828 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2829 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2830 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2831 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2832 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2833 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2834 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2835 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2836 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2837 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2838 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2839 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2840 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2841 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2842 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2843 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2844 /* ------------------------------- */
2845 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2848 static const unsigned char twobyte_has_mandatory_prefix
[256] = {
2849 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2850 /* ------------------------------- */
2851 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
2852 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
2853 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
2854 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2855 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
2856 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2857 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2858 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
2859 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2860 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
2861 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
2862 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
2863 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
2864 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2865 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2866 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2867 /* ------------------------------- */
2868 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2871 static char obuf
[100];
2873 static char *mnemonicendp
;
2874 static char scratchbuf
[100];
2875 static unsigned char *start_codep
;
2876 static unsigned char *insn_codep
;
2877 static unsigned char *codep
;
2878 static unsigned char *end_codep
;
2879 static int last_lock_prefix
;
2880 static int last_repz_prefix
;
2881 static int last_repnz_prefix
;
2882 static int last_data_prefix
;
2883 static int last_addr_prefix
;
2884 static int last_rex_prefix
;
2885 static int last_seg_prefix
;
2886 static int fwait_prefix
;
2887 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
2888 static int mandatory_prefix
;
2889 /* The active segment register prefix. */
2890 static int active_seg_prefix
;
2891 #define MAX_CODE_LENGTH 15
2892 /* We can up to 14 prefixes since the maximum instruction length is
2894 static int all_prefixes
[MAX_CODE_LENGTH
- 1];
2895 static disassemble_info
*the_info
;
2903 static unsigned char need_modrm
;
2913 int register_specifier
;
2920 int mask_register_specifier
;
2926 static unsigned char need_vex
;
2927 static unsigned char need_vex_reg
;
2928 static unsigned char vex_w_done
;
2936 /* If we are accessing mod/rm/reg without need_modrm set, then the
2937 values are stale. Hitting this abort likely indicates that you
2938 need to update onebyte_has_modrm or twobyte_has_modrm. */
2939 #define MODRM_CHECK if (!need_modrm) abort ()
2941 static const char **names64
;
2942 static const char **names32
;
2943 static const char **names16
;
2944 static const char **names8
;
2945 static const char **names8rex
;
2946 static const char **names_seg
;
2947 static const char *index64
;
2948 static const char *index32
;
2949 static const char **index16
;
2950 static const char **names_bnd
;
2952 static const char *intel_names64
[] = {
2953 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2954 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2956 static const char *intel_names32
[] = {
2957 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2958 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2960 static const char *intel_names16
[] = {
2961 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2962 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2964 static const char *intel_names8
[] = {
2965 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2967 static const char *intel_names8rex
[] = {
2968 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2969 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2971 static const char *intel_names_seg
[] = {
2972 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2974 static const char *intel_index64
= "riz";
2975 static const char *intel_index32
= "eiz";
2976 static const char *intel_index16
[] = {
2977 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2980 static const char *att_names64
[] = {
2981 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2982 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2984 static const char *att_names32
[] = {
2985 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2986 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2988 static const char *att_names16
[] = {
2989 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2990 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2992 static const char *att_names8
[] = {
2993 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2995 static const char *att_names8rex
[] = {
2996 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2997 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2999 static const char *att_names_seg
[] = {
3000 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3002 static const char *att_index64
= "%riz";
3003 static const char *att_index32
= "%eiz";
3004 static const char *att_index16
[] = {
3005 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3008 static const char **names_mm
;
3009 static const char *intel_names_mm
[] = {
3010 "mm0", "mm1", "mm2", "mm3",
3011 "mm4", "mm5", "mm6", "mm7"
3013 static const char *att_names_mm
[] = {
3014 "%mm0", "%mm1", "%mm2", "%mm3",
3015 "%mm4", "%mm5", "%mm6", "%mm7"
3018 static const char *intel_names_bnd
[] = {
3019 "bnd0", "bnd1", "bnd2", "bnd3"
3022 static const char *att_names_bnd
[] = {
3023 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3026 static const char **names_xmm
;
3027 static const char *intel_names_xmm
[] = {
3028 "xmm0", "xmm1", "xmm2", "xmm3",
3029 "xmm4", "xmm5", "xmm6", "xmm7",
3030 "xmm8", "xmm9", "xmm10", "xmm11",
3031 "xmm12", "xmm13", "xmm14", "xmm15",
3032 "xmm16", "xmm17", "xmm18", "xmm19",
3033 "xmm20", "xmm21", "xmm22", "xmm23",
3034 "xmm24", "xmm25", "xmm26", "xmm27",
3035 "xmm28", "xmm29", "xmm30", "xmm31"
3037 static const char *att_names_xmm
[] = {
3038 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3039 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3040 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3041 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3042 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3043 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3044 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3045 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3048 static const char **names_ymm
;
3049 static const char *intel_names_ymm
[] = {
3050 "ymm0", "ymm1", "ymm2", "ymm3",
3051 "ymm4", "ymm5", "ymm6", "ymm7",
3052 "ymm8", "ymm9", "ymm10", "ymm11",
3053 "ymm12", "ymm13", "ymm14", "ymm15",
3054 "ymm16", "ymm17", "ymm18", "ymm19",
3055 "ymm20", "ymm21", "ymm22", "ymm23",
3056 "ymm24", "ymm25", "ymm26", "ymm27",
3057 "ymm28", "ymm29", "ymm30", "ymm31"
3059 static const char *att_names_ymm
[] = {
3060 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3061 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3062 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3063 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3064 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3065 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3066 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3067 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3070 static const char **names_zmm
;
3071 static const char *intel_names_zmm
[] = {
3072 "zmm0", "zmm1", "zmm2", "zmm3",
3073 "zmm4", "zmm5", "zmm6", "zmm7",
3074 "zmm8", "zmm9", "zmm10", "zmm11",
3075 "zmm12", "zmm13", "zmm14", "zmm15",
3076 "zmm16", "zmm17", "zmm18", "zmm19",
3077 "zmm20", "zmm21", "zmm22", "zmm23",
3078 "zmm24", "zmm25", "zmm26", "zmm27",
3079 "zmm28", "zmm29", "zmm30", "zmm31"
3081 static const char *att_names_zmm
[] = {
3082 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3083 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3084 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3085 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3086 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3087 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3088 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3089 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3092 static const char **names_mask
;
3093 static const char *intel_names_mask
[] = {
3094 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3096 static const char *att_names_mask
[] = {
3097 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3100 static const char *names_rounding
[] =
3108 static const struct dis386 reg_table
[][8] = {
3111 { "addA", { Ebh1
, Ib
} },
3112 { "orA", { Ebh1
, Ib
} },
3113 { "adcA", { Ebh1
, Ib
} },
3114 { "sbbA", { Ebh1
, Ib
} },
3115 { "andA", { Ebh1
, Ib
} },
3116 { "subA", { Ebh1
, Ib
} },
3117 { "xorA", { Ebh1
, Ib
} },
3118 { "cmpA", { Eb
, Ib
} },
3122 { "addQ", { Evh1
, Iv
} },
3123 { "orQ", { Evh1
, Iv
} },
3124 { "adcQ", { Evh1
, Iv
} },
3125 { "sbbQ", { Evh1
, Iv
} },
3126 { "andQ", { Evh1
, Iv
} },
3127 { "subQ", { Evh1
, Iv
} },
3128 { "xorQ", { Evh1
, Iv
} },
3129 { "cmpQ", { Ev
, Iv
} },
3133 { "addQ", { Evh1
, sIb
} },
3134 { "orQ", { Evh1
, sIb
} },
3135 { "adcQ", { Evh1
, sIb
} },
3136 { "sbbQ", { Evh1
, sIb
} },
3137 { "andQ", { Evh1
, sIb
} },
3138 { "subQ", { Evh1
, sIb
} },
3139 { "xorQ", { Evh1
, sIb
} },
3140 { "cmpQ", { Ev
, sIb
} },
3144 { "popU", { stackEv
} },
3145 { XOP_8F_TABLE (XOP_09
) },
3149 { XOP_8F_TABLE (XOP_09
) },
3153 { "rolA", { Eb
, Ib
} },
3154 { "rorA", { Eb
, Ib
} },
3155 { "rclA", { Eb
, Ib
} },
3156 { "rcrA", { Eb
, Ib
} },
3157 { "shlA", { Eb
, Ib
} },
3158 { "shrA", { Eb
, Ib
} },
3160 { "sarA", { Eb
, Ib
} },
3164 { "rolQ", { Ev
, Ib
} },
3165 { "rorQ", { Ev
, Ib
} },
3166 { "rclQ", { Ev
, Ib
} },
3167 { "rcrQ", { Ev
, Ib
} },
3168 { "shlQ", { Ev
, Ib
} },
3169 { "shrQ", { Ev
, Ib
} },
3171 { "sarQ", { Ev
, Ib
} },
3175 { "movA", { Ebh3
, Ib
} },
3182 { MOD_TABLE (MOD_C6_REG_7
) },
3186 { "movQ", { Evh3
, Iv
} },
3193 { MOD_TABLE (MOD_C7_REG_7
) },
3197 { "rolA", { Eb
, I1
} },
3198 { "rorA", { Eb
, I1
} },
3199 { "rclA", { Eb
, I1
} },
3200 { "rcrA", { Eb
, I1
} },
3201 { "shlA", { Eb
, I1
} },
3202 { "shrA", { Eb
, I1
} },
3204 { "sarA", { Eb
, I1
} },
3208 { "rolQ", { Ev
, I1
} },
3209 { "rorQ", { Ev
, I1
} },
3210 { "rclQ", { Ev
, I1
} },
3211 { "rcrQ", { Ev
, I1
} },
3212 { "shlQ", { Ev
, I1
} },
3213 { "shrQ", { Ev
, I1
} },
3215 { "sarQ", { Ev
, I1
} },
3219 { "rolA", { Eb
, CL
} },
3220 { "rorA", { Eb
, CL
} },
3221 { "rclA", { Eb
, CL
} },
3222 { "rcrA", { Eb
, CL
} },
3223 { "shlA", { Eb
, CL
} },
3224 { "shrA", { Eb
, CL
} },
3226 { "sarA", { Eb
, CL
} },
3230 { "rolQ", { Ev
, CL
} },
3231 { "rorQ", { Ev
, CL
} },
3232 { "rclQ", { Ev
, CL
} },
3233 { "rcrQ", { Ev
, CL
} },
3234 { "shlQ", { Ev
, CL
} },
3235 { "shrQ", { Ev
, CL
} },
3237 { "sarQ", { Ev
, CL
} },
3241 { "testA", { Eb
, Ib
} },
3243 { "notA", { Ebh1
} },
3244 { "negA", { Ebh1
} },
3245 { "mulA", { Eb
} }, /* Don't print the implicit %al register, */
3246 { "imulA", { Eb
} }, /* to distinguish these opcodes from other */
3247 { "divA", { Eb
} }, /* mul/imul opcodes. Do the same for div */
3248 { "idivA", { Eb
} }, /* and idiv for consistency. */
3252 { "testQ", { Ev
, Iv
} },
3254 { "notQ", { Evh1
} },
3255 { "negQ", { Evh1
} },
3256 { "mulQ", { Ev
} }, /* Don't print the implicit register. */
3257 { "imulQ", { Ev
} },
3259 { "idivQ", { Ev
} },
3263 { "incA", { Ebh1
} },
3264 { "decA", { Ebh1
} },
3268 { "incQ", { Evh1
} },
3269 { "decQ", { Evh1
} },
3270 { "call{T|}", { indirEv
, BND
} },
3271 { MOD_TABLE (MOD_FF_REG_3
) },
3272 { "jmp{T|}", { indirEv
, BND
} },
3273 { MOD_TABLE (MOD_FF_REG_5
) },
3274 { "pushU", { stackEv
} },
3279 { "sldtD", { Sv
} },
3290 { MOD_TABLE (MOD_0F01_REG_0
) },
3291 { MOD_TABLE (MOD_0F01_REG_1
) },
3292 { MOD_TABLE (MOD_0F01_REG_2
) },
3293 { MOD_TABLE (MOD_0F01_REG_3
) },
3294 { "smswD", { Sv
} },
3297 { MOD_TABLE (MOD_0F01_REG_7
) },
3301 { "prefetch", { Mb
} },
3302 { "prefetchw", { Mb
} },
3303 { "prefetchwt1", { Mb
} },
3304 { "prefetch", { Mb
} },
3305 { "prefetch", { Mb
} },
3306 { "prefetch", { Mb
} },
3307 { "prefetch", { Mb
} },
3308 { "prefetch", { Mb
} },
3312 { MOD_TABLE (MOD_0F18_REG_0
) },
3313 { MOD_TABLE (MOD_0F18_REG_1
) },
3314 { MOD_TABLE (MOD_0F18_REG_2
) },
3315 { MOD_TABLE (MOD_0F18_REG_3
) },
3316 { MOD_TABLE (MOD_0F18_REG_4
) },
3317 { MOD_TABLE (MOD_0F18_REG_5
) },
3318 { MOD_TABLE (MOD_0F18_REG_6
) },
3319 { MOD_TABLE (MOD_0F18_REG_7
) },
3325 { MOD_TABLE (MOD_0F71_REG_2
) },
3327 { MOD_TABLE (MOD_0F71_REG_4
) },
3329 { MOD_TABLE (MOD_0F71_REG_6
) },
3335 { MOD_TABLE (MOD_0F72_REG_2
) },
3337 { MOD_TABLE (MOD_0F72_REG_4
) },
3339 { MOD_TABLE (MOD_0F72_REG_6
) },
3345 { MOD_TABLE (MOD_0F73_REG_2
) },
3346 { MOD_TABLE (MOD_0F73_REG_3
) },
3349 { MOD_TABLE (MOD_0F73_REG_6
) },
3350 { MOD_TABLE (MOD_0F73_REG_7
) },
3354 { "montmul", { { OP_0f07
, 0 } } },
3355 { "xsha1", { { OP_0f07
, 0 } } },
3356 { "xsha256", { { OP_0f07
, 0 } } },
3360 { "xstore-rng", { { OP_0f07
, 0 } } },
3361 { "xcrypt-ecb", { { OP_0f07
, 0 } } },
3362 { "xcrypt-cbc", { { OP_0f07
, 0 } } },
3363 { "xcrypt-ctr", { { OP_0f07
, 0 } } },
3364 { "xcrypt-cfb", { { OP_0f07
, 0 } } },
3365 { "xcrypt-ofb", { { OP_0f07
, 0 } } },
3369 { MOD_TABLE (MOD_0FAE_REG_0
) },
3370 { MOD_TABLE (MOD_0FAE_REG_1
) },
3371 { MOD_TABLE (MOD_0FAE_REG_2
) },
3372 { MOD_TABLE (MOD_0FAE_REG_3
) },
3373 { MOD_TABLE (MOD_0FAE_REG_4
) },
3374 { MOD_TABLE (MOD_0FAE_REG_5
) },
3375 { MOD_TABLE (MOD_0FAE_REG_6
) },
3376 { MOD_TABLE (MOD_0FAE_REG_7
) },
3384 { "btQ", { Ev
, Ib
} },
3385 { "btsQ", { Evh1
, Ib
} },
3386 { "btrQ", { Evh1
, Ib
} },
3387 { "btcQ", { Evh1
, Ib
} },
3392 { "cmpxchg8b", { { CMPXCHG8B_Fixup
, q_mode
} } },
3394 { MOD_TABLE (MOD_0FC7_REG_3
) },
3395 { MOD_TABLE (MOD_0FC7_REG_4
) },
3396 { MOD_TABLE (MOD_0FC7_REG_5
) },
3397 { MOD_TABLE (MOD_0FC7_REG_6
) },
3398 { MOD_TABLE (MOD_0FC7_REG_7
) },
3404 { MOD_TABLE (MOD_VEX_0F71_REG_2
) },
3406 { MOD_TABLE (MOD_VEX_0F71_REG_4
) },
3408 { MOD_TABLE (MOD_VEX_0F71_REG_6
) },
3414 { MOD_TABLE (MOD_VEX_0F72_REG_2
) },
3416 { MOD_TABLE (MOD_VEX_0F72_REG_4
) },
3418 { MOD_TABLE (MOD_VEX_0F72_REG_6
) },
3424 { MOD_TABLE (MOD_VEX_0F73_REG_2
) },
3425 { MOD_TABLE (MOD_VEX_0F73_REG_3
) },
3428 { MOD_TABLE (MOD_VEX_0F73_REG_6
) },
3429 { MOD_TABLE (MOD_VEX_0F73_REG_7
) },
3435 { MOD_TABLE (MOD_VEX_0FAE_REG_2
) },
3436 { MOD_TABLE (MOD_VEX_0FAE_REG_3
) },
3438 /* REG_VEX_0F38F3 */
3441 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1
) },
3442 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2
) },
3443 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3
) },
3447 { "llwpcb", { { OP_LWPCB_E
, 0 } } },
3448 { "slwpcb", { { OP_LWPCB_E
, 0 } } },
3452 { "lwpins", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3453 { "lwpval", { { OP_LWP_E
, 0 }, Ed
, Iq
} },
3455 /* REG_XOP_TBM_01 */
3458 { "blcfill", { { OP_LWP_E
, 0 }, Ev
} },
3459 { "blsfill", { { OP_LWP_E
, 0 }, Ev
} },
3460 { "blcs", { { OP_LWP_E
, 0 }, Ev
} },
3461 { "tzmsk", { { OP_LWP_E
, 0 }, Ev
} },
3462 { "blcic", { { OP_LWP_E
, 0 }, Ev
} },
3463 { "blsic", { { OP_LWP_E
, 0 }, Ev
} },
3464 { "t1mskc", { { OP_LWP_E
, 0 }, Ev
} },
3466 /* REG_XOP_TBM_02 */
3469 { "blcmsk", { { OP_LWP_E
, 0 }, Ev
} },
3474 { "blci", { { OP_LWP_E
, 0 }, Ev
} },
3476 #define NEED_REG_TABLE
3477 #include "i386-dis-evex.h"
3478 #undef NEED_REG_TABLE
3481 static const struct dis386 prefix_table
[][4] = {
3484 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3485 { "pause", { XX
} },
3486 { "xchgS", { { NOP_Fixup1
, eAX_reg
}, { NOP_Fixup2
, eAX_reg
} } },
3491 { "movups", { XM
, EXx
} },
3492 { "movss", { XM
, EXd
} },
3493 { "movupd", { XM
, EXx
} },
3494 { "movsd", { XM
, EXq
} },
3499 { "movups", { EXxS
, XM
} },
3500 { "movss", { EXdS
, XM
} },
3501 { "movupd", { EXxS
, XM
} },
3502 { "movsd", { EXqS
, XM
} },
3507 { MOD_TABLE (MOD_0F12_PREFIX_0
) },
3508 { "movsldup", { XM
, EXx
} },
3509 { "movlpd", { XM
, EXq
} },
3510 { "movddup", { XM
, EXq
} },
3515 { MOD_TABLE (MOD_0F16_PREFIX_0
) },
3516 { "movshdup", { XM
, EXx
} },
3517 { "movhpd", { XM
, EXq
} },
3522 { MOD_TABLE (MOD_0F1A_PREFIX_0
) },
3523 { "bndcl", { Gbnd
, Ev_bnd
} },
3524 { "bndmov", { Gbnd
, Ebnd
} },
3525 { "bndcu", { Gbnd
, Ev_bnd
} },
3530 { MOD_TABLE (MOD_0F1B_PREFIX_0
) },
3531 { MOD_TABLE (MOD_0F1B_PREFIX_1
) },
3532 { "bndmov", { Ebnd
, Gbnd
} },
3533 { "bndcn", { Gbnd
, Ev_bnd
} },
3538 { "cvtpi2ps", { XM
, EMCq
} },
3539 { "cvtsi2ss%LQ", { XM
, Ev
} },
3540 { "cvtpi2pd", { XM
, EMCq
} },
3541 { "cvtsi2sd%LQ", { XM
, Ev
} },
3546 { MOD_TABLE (MOD_0F2B_PREFIX_0
) },
3547 { MOD_TABLE (MOD_0F2B_PREFIX_1
) },
3548 { MOD_TABLE (MOD_0F2B_PREFIX_2
) },
3549 { MOD_TABLE (MOD_0F2B_PREFIX_3
) },
3554 { "cvttps2pi", { MXC
, EXq
} },
3555 { "cvttss2siY", { Gv
, EXd
} },
3556 { "cvttpd2pi", { MXC
, EXx
} },
3557 { "cvttsd2siY", { Gv
, EXq
} },
3562 { "cvtps2pi", { MXC
, EXq
} },
3563 { "cvtss2siY", { Gv
, EXd
} },
3564 { "cvtpd2pi", { MXC
, EXx
} },
3565 { "cvtsd2siY", { Gv
, EXq
} },
3570 { "ucomiss",{ XM
, EXd
} },
3572 { "ucomisd",{ XM
, EXq
} },
3577 { "comiss", { XM
, EXd
} },
3579 { "comisd", { XM
, EXq
} },
3584 { "sqrtps", { XM
, EXx
} },
3585 { "sqrtss", { XM
, EXd
} },
3586 { "sqrtpd", { XM
, EXx
} },
3587 { "sqrtsd", { XM
, EXq
} },
3592 { "rsqrtps",{ XM
, EXx
} },
3593 { "rsqrtss",{ XM
, EXd
} },
3598 { "rcpps", { XM
, EXx
} },
3599 { "rcpss", { XM
, EXd
} },
3604 { "addps", { XM
, EXx
} },
3605 { "addss", { XM
, EXd
} },
3606 { "addpd", { XM
, EXx
} },
3607 { "addsd", { XM
, EXq
} },
3612 { "mulps", { XM
, EXx
} },
3613 { "mulss", { XM
, EXd
} },
3614 { "mulpd", { XM
, EXx
} },
3615 { "mulsd", { XM
, EXq
} },
3620 { "cvtps2pd", { XM
, EXq
} },
3621 { "cvtss2sd", { XM
, EXd
} },
3622 { "cvtpd2ps", { XM
, EXx
} },
3623 { "cvtsd2ss", { XM
, EXq
} },
3628 { "cvtdq2ps", { XM
, EXx
} },
3629 { "cvttps2dq", { XM
, EXx
} },
3630 { "cvtps2dq", { XM
, EXx
} },
3635 { "subps", { XM
, EXx
} },
3636 { "subss", { XM
, EXd
} },
3637 { "subpd", { XM
, EXx
} },
3638 { "subsd", { XM
, EXq
} },
3643 { "minps", { XM
, EXx
} },
3644 { "minss", { XM
, EXd
} },
3645 { "minpd", { XM
, EXx
} },
3646 { "minsd", { XM
, EXq
} },
3651 { "divps", { XM
, EXx
} },
3652 { "divss", { XM
, EXd
} },
3653 { "divpd", { XM
, EXx
} },
3654 { "divsd", { XM
, EXq
} },
3659 { "maxps", { XM
, EXx
} },
3660 { "maxss", { XM
, EXd
} },
3661 { "maxpd", { XM
, EXx
} },
3662 { "maxsd", { XM
, EXq
} },
3667 { "punpcklbw",{ MX
, EMd
} },
3669 { "punpcklbw",{ MX
, EMx
} },
3674 { "punpcklwd",{ MX
, EMd
} },
3676 { "punpcklwd",{ MX
, EMx
} },
3681 { "punpckldq",{ MX
, EMd
} },
3683 { "punpckldq",{ MX
, EMx
} },
3690 { "punpcklqdq", { XM
, EXx
} },
3697 { "punpckhqdq", { XM
, EXx
} },
3702 { "movq", { MX
, EM
} },
3703 { "movdqu", { XM
, EXx
} },
3704 { "movdqa", { XM
, EXx
} },
3709 { "pshufw", { MX
, EM
, Ib
} },
3710 { "pshufhw",{ XM
, EXx
, Ib
} },
3711 { "pshufd", { XM
, EXx
, Ib
} },
3712 { "pshuflw",{ XM
, EXx
, Ib
} },
3715 /* PREFIX_0F73_REG_3 */
3719 { "psrldq", { XS
, Ib
} },
3722 /* PREFIX_0F73_REG_7 */
3726 { "pslldq", { XS
, Ib
} },
3731 {"vmread", { Em
, Gm
} },
3733 {"extrq", { XS
, Ib
, Ib
} },
3734 {"insertq", { XM
, XS
, Ib
, Ib
} },
3739 {"vmwrite", { Gm
, Em
} },
3741 {"extrq", { XM
, XS
} },
3742 {"insertq", { XM
, XS
} },
3749 { "haddpd", { XM
, EXx
} },
3750 { "haddps", { XM
, EXx
} },
3757 { "hsubpd", { XM
, EXx
} },
3758 { "hsubps", { XM
, EXx
} },
3763 { "movK", { Edq
, MX
} },
3764 { "movq", { XM
, EXq
} },
3765 { "movK", { Edq
, XM
} },
3770 { "movq", { EMS
, MX
} },
3771 { "movdqu", { EXxS
, XM
} },
3772 { "movdqa", { EXxS
, XM
} },
3775 /* PREFIX_0FAE_REG_0 */
3778 { "rdfsbase", { Ev
} },
3781 /* PREFIX_0FAE_REG_1 */
3784 { "rdgsbase", { Ev
} },
3787 /* PREFIX_0FAE_REG_2 */
3790 { "wrfsbase", { Ev
} },
3793 /* PREFIX_0FAE_REG_3 */
3796 { "wrgsbase", { Ev
} },
3799 /* PREFIX_0FAE_REG_7 */
3801 { "clflush", { Mb
} },
3803 { "clflushopt", { Mb
} },
3809 { "popcntS", { Gv
, Ev
} },
3814 { "bsfS", { Gv
, Ev
} },
3815 { "tzcntS", { Gv
, Ev
} },
3816 { "bsfS", { Gv
, Ev
} },
3821 { "bsrS", { Gv
, Ev
} },
3822 { "lzcntS", { Gv
, Ev
} },
3823 { "bsrS", { Gv
, Ev
} },
3828 { "cmpps", { XM
, EXx
, CMP
} },
3829 { "cmpss", { XM
, EXd
, CMP
} },
3830 { "cmppd", { XM
, EXx
, CMP
} },
3831 { "cmpsd", { XM
, EXq
, CMP
} },
3836 { "movntiS", { Ma
, Gv
} },
3839 /* PREFIX_0FC7_REG_6 */
3841 { "vmptrld",{ Mq
} },
3842 { "vmxon", { Mq
} },
3843 { "vmclear",{ Mq
} },
3850 { "addsubpd", { XM
, EXx
} },
3851 { "addsubps", { XM
, EXx
} },
3857 { "movq2dq",{ XM
, MS
} },
3858 { "movq", { EXqS
, XM
} },
3859 { "movdq2q",{ MX
, XS
} },
3865 { "cvtdq2pd", { XM
, EXq
} },
3866 { "cvttpd2dq", { XM
, EXx
} },
3867 { "cvtpd2dq", { XM
, EXx
} },
3872 { "movntq", { Mq
, MX
} },
3874 { MOD_TABLE (MOD_0FE7_PREFIX_2
) },
3882 { MOD_TABLE (MOD_0FF0_PREFIX_3
) },
3887 { "maskmovq", { MX
, MS
} },
3889 { "maskmovdqu", { XM
, XS
} },
3896 { "pblendvb", { XM
, EXx
, XMM0
} },
3903 { "blendvps", { XM
, EXx
, XMM0
} },
3910 { "blendvpd", { XM
, EXx
, XMM0
} },
3917 { "ptest", { XM
, EXx
} },
3924 { "pmovsxbw", { XM
, EXq
} },
3931 { "pmovsxbd", { XM
, EXd
} },
3938 { "pmovsxbq", { XM
, EXw
} },
3945 { "pmovsxwd", { XM
, EXq
} },
3952 { "pmovsxwq", { XM
, EXd
} },
3959 { "pmovsxdq", { XM
, EXq
} },
3966 { "pmuldq", { XM
, EXx
} },
3973 { "pcmpeqq", { XM
, EXx
} },
3980 { MOD_TABLE (MOD_0F382A_PREFIX_2
) },
3987 { "packusdw", { XM
, EXx
} },
3994 { "pmovzxbw", { XM
, EXq
} },
4001 { "pmovzxbd", { XM
, EXd
} },
4008 { "pmovzxbq", { XM
, EXw
} },
4015 { "pmovzxwd", { XM
, EXq
} },
4022 { "pmovzxwq", { XM
, EXd
} },
4029 { "pmovzxdq", { XM
, EXq
} },
4036 { "pcmpgtq", { XM
, EXx
} },
4043 { "pminsb", { XM
, EXx
} },
4050 { "pminsd", { XM
, EXx
} },
4057 { "pminuw", { XM
, EXx
} },
4064 { "pminud", { XM
, EXx
} },
4071 { "pmaxsb", { XM
, EXx
} },
4078 { "pmaxsd", { XM
, EXx
} },
4085 { "pmaxuw", { XM
, EXx
} },
4092 { "pmaxud", { XM
, EXx
} },
4099 { "pmulld", { XM
, EXx
} },
4106 { "phminposuw", { XM
, EXx
} },
4113 { "invept", { Gm
, Mo
} },
4120 { "invvpid", { Gm
, Mo
} },
4127 { "invpcid", { Gm
, M
} },
4132 { "sha1nexte", { XM
, EXxmm
} },
4137 { "sha1msg1", { XM
, EXxmm
} },
4142 { "sha1msg2", { XM
, EXxmm
} },
4147 { "sha256rnds2", { XM
, EXxmm
, XMM0
} },
4152 { "sha256msg1", { XM
, EXxmm
} },
4157 { "sha256msg2", { XM
, EXxmm
} },
4164 { "aesimc", { XM
, EXx
} },
4171 { "aesenc", { XM
, EXx
} },
4178 { "aesenclast", { XM
, EXx
} },
4185 { "aesdec", { XM
, EXx
} },
4192 { "aesdeclast", { XM
, EXx
} },
4197 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4199 { "movbeS", { Gv
, { MOVBE_Fixup
, v_mode
} } },
4200 { "crc32", { Gdq
, { CRC32_Fixup
, b_mode
} } },
4205 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4207 { "movbeS", { { MOVBE_Fixup
, v_mode
}, Gv
} },
4208 { "crc32", { Gdq
, { CRC32_Fixup
, v_mode
} } },
4214 { "adoxS", { Gdq
, Edq
} },
4215 { "adcxS", { Gdq
, Edq
} },
4223 { "roundps", { XM
, EXx
, Ib
} },
4230 { "roundpd", { XM
, EXx
, Ib
} },
4237 { "roundss", { XM
, EXd
, Ib
} },
4244 { "roundsd", { XM
, EXq
, Ib
} },
4251 { "blendps", { XM
, EXx
, Ib
} },
4258 { "blendpd", { XM
, EXx
, Ib
} },
4265 { "pblendw", { XM
, EXx
, Ib
} },
4272 { "pextrb", { Edqb
, XM
, Ib
} },
4279 { "pextrw", { Edqw
, XM
, Ib
} },
4286 { "pextrK", { Edq
, XM
, Ib
} },
4293 { "extractps", { Edqd
, XM
, Ib
} },
4300 { "pinsrb", { XM
, Edqb
, Ib
} },
4307 { "insertps", { XM
, EXd
, Ib
} },
4314 { "pinsrK", { XM
, Edq
, Ib
} },
4321 { "dpps", { XM
, EXx
, Ib
} },
4328 { "dppd", { XM
, EXx
, Ib
} },
4335 { "mpsadbw", { XM
, EXx
, Ib
} },
4342 { "pclmulqdq", { XM
, EXx
, PCLMUL
} },
4349 { "pcmpestrm", { XM
, EXx
, Ib
} },
4356 { "pcmpestri", { XM
, EXx
, Ib
} },
4363 { "pcmpistrm", { XM
, EXx
, Ib
} },
4370 { "pcmpistri", { XM
, EXx
, Ib
} },
4375 { "sha1rnds4", { XM
, EXxmm
, Ib
} },
4382 { "aeskeygenassist", { XM
, EXx
, Ib
} },
4385 /* PREFIX_VEX_0F10 */
4387 { VEX_W_TABLE (VEX_W_0F10_P_0
) },
4388 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1
) },
4389 { VEX_W_TABLE (VEX_W_0F10_P_2
) },
4390 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3
) },
4393 /* PREFIX_VEX_0F11 */
4395 { VEX_W_TABLE (VEX_W_0F11_P_0
) },
4396 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1
) },
4397 { VEX_W_TABLE (VEX_W_0F11_P_2
) },
4398 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3
) },
4401 /* PREFIX_VEX_0F12 */
4403 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0
) },
4404 { VEX_W_TABLE (VEX_W_0F12_P_1
) },
4405 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2
) },
4406 { VEX_W_TABLE (VEX_W_0F12_P_3
) },
4409 /* PREFIX_VEX_0F16 */
4411 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0
) },
4412 { VEX_W_TABLE (VEX_W_0F16_P_1
) },
4413 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2
) },
4416 /* PREFIX_VEX_0F2A */
4419 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1
) },
4421 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3
) },
4424 /* PREFIX_VEX_0F2C */
4427 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1
) },
4429 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3
) },
4432 /* PREFIX_VEX_0F2D */
4435 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1
) },
4437 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3
) },
4440 /* PREFIX_VEX_0F2E */
4442 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0
) },
4444 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2
) },
4447 /* PREFIX_VEX_0F2F */
4449 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0
) },
4451 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2
) },
4454 /* PREFIX_VEX_0F41 */
4456 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0
) },
4459 /* PREFIX_VEX_0F42 */
4461 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0
) },
4464 /* PREFIX_VEX_0F44 */
4466 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0
) },
4469 /* PREFIX_VEX_0F45 */
4471 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0
) },
4474 /* PREFIX_VEX_0F46 */
4476 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0
) },
4479 /* PREFIX_VEX_0F47 */
4481 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0
) },
4484 /* PREFIX_VEX_0F4B */
4488 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2
) },
4491 /* PREFIX_VEX_0F51 */
4493 { VEX_W_TABLE (VEX_W_0F51_P_0
) },
4494 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1
) },
4495 { VEX_W_TABLE (VEX_W_0F51_P_2
) },
4496 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3
) },
4499 /* PREFIX_VEX_0F52 */
4501 { VEX_W_TABLE (VEX_W_0F52_P_0
) },
4502 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1
) },
4505 /* PREFIX_VEX_0F53 */
4507 { VEX_W_TABLE (VEX_W_0F53_P_0
) },
4508 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1
) },
4511 /* PREFIX_VEX_0F58 */
4513 { VEX_W_TABLE (VEX_W_0F58_P_0
) },
4514 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1
) },
4515 { VEX_W_TABLE (VEX_W_0F58_P_2
) },
4516 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3
) },
4519 /* PREFIX_VEX_0F59 */
4521 { VEX_W_TABLE (VEX_W_0F59_P_0
) },
4522 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1
) },
4523 { VEX_W_TABLE (VEX_W_0F59_P_2
) },
4524 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3
) },
4527 /* PREFIX_VEX_0F5A */
4529 { VEX_W_TABLE (VEX_W_0F5A_P_0
) },
4530 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1
) },
4531 { "vcvtpd2ps%XY", { XMM
, EXx
} },
4532 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3
) },
4535 /* PREFIX_VEX_0F5B */
4537 { VEX_W_TABLE (VEX_W_0F5B_P_0
) },
4538 { VEX_W_TABLE (VEX_W_0F5B_P_1
) },
4539 { VEX_W_TABLE (VEX_W_0F5B_P_2
) },
4542 /* PREFIX_VEX_0F5C */
4544 { VEX_W_TABLE (VEX_W_0F5C_P_0
) },
4545 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1
) },
4546 { VEX_W_TABLE (VEX_W_0F5C_P_2
) },
4547 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3
) },
4550 /* PREFIX_VEX_0F5D */
4552 { VEX_W_TABLE (VEX_W_0F5D_P_0
) },
4553 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1
) },
4554 { VEX_W_TABLE (VEX_W_0F5D_P_2
) },
4555 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3
) },
4558 /* PREFIX_VEX_0F5E */
4560 { VEX_W_TABLE (VEX_W_0F5E_P_0
) },
4561 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1
) },
4562 { VEX_W_TABLE (VEX_W_0F5E_P_2
) },
4563 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3
) },
4566 /* PREFIX_VEX_0F5F */
4568 { VEX_W_TABLE (VEX_W_0F5F_P_0
) },
4569 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1
) },
4570 { VEX_W_TABLE (VEX_W_0F5F_P_2
) },
4571 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3
) },
4574 /* PREFIX_VEX_0F60 */
4578 { VEX_W_TABLE (VEX_W_0F60_P_2
) },
4581 /* PREFIX_VEX_0F61 */
4585 { VEX_W_TABLE (VEX_W_0F61_P_2
) },
4588 /* PREFIX_VEX_0F62 */
4592 { VEX_W_TABLE (VEX_W_0F62_P_2
) },
4595 /* PREFIX_VEX_0F63 */
4599 { VEX_W_TABLE (VEX_W_0F63_P_2
) },
4602 /* PREFIX_VEX_0F64 */
4606 { VEX_W_TABLE (VEX_W_0F64_P_2
) },
4609 /* PREFIX_VEX_0F65 */
4613 { VEX_W_TABLE (VEX_W_0F65_P_2
) },
4616 /* PREFIX_VEX_0F66 */
4620 { VEX_W_TABLE (VEX_W_0F66_P_2
) },
4623 /* PREFIX_VEX_0F67 */
4627 { VEX_W_TABLE (VEX_W_0F67_P_2
) },
4630 /* PREFIX_VEX_0F68 */
4634 { VEX_W_TABLE (VEX_W_0F68_P_2
) },
4637 /* PREFIX_VEX_0F69 */
4641 { VEX_W_TABLE (VEX_W_0F69_P_2
) },
4644 /* PREFIX_VEX_0F6A */
4648 { VEX_W_TABLE (VEX_W_0F6A_P_2
) },
4651 /* PREFIX_VEX_0F6B */
4655 { VEX_W_TABLE (VEX_W_0F6B_P_2
) },
4658 /* PREFIX_VEX_0F6C */
4662 { VEX_W_TABLE (VEX_W_0F6C_P_2
) },
4665 /* PREFIX_VEX_0F6D */
4669 { VEX_W_TABLE (VEX_W_0F6D_P_2
) },
4672 /* PREFIX_VEX_0F6E */
4676 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2
) },
4679 /* PREFIX_VEX_0F6F */
4682 { VEX_W_TABLE (VEX_W_0F6F_P_1
) },
4683 { VEX_W_TABLE (VEX_W_0F6F_P_2
) },
4686 /* PREFIX_VEX_0F70 */
4689 { VEX_W_TABLE (VEX_W_0F70_P_1
) },
4690 { VEX_W_TABLE (VEX_W_0F70_P_2
) },
4691 { VEX_W_TABLE (VEX_W_0F70_P_3
) },
4694 /* PREFIX_VEX_0F71_REG_2 */
4698 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2
) },
4701 /* PREFIX_VEX_0F71_REG_4 */
4705 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2
) },
4708 /* PREFIX_VEX_0F71_REG_6 */
4712 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2
) },
4715 /* PREFIX_VEX_0F72_REG_2 */
4719 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2
) },
4722 /* PREFIX_VEX_0F72_REG_4 */
4726 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2
) },
4729 /* PREFIX_VEX_0F72_REG_6 */
4733 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2
) },
4736 /* PREFIX_VEX_0F73_REG_2 */
4740 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2
) },
4743 /* PREFIX_VEX_0F73_REG_3 */
4747 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2
) },
4750 /* PREFIX_VEX_0F73_REG_6 */
4754 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2
) },
4757 /* PREFIX_VEX_0F73_REG_7 */
4761 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2
) },
4764 /* PREFIX_VEX_0F74 */
4768 { VEX_W_TABLE (VEX_W_0F74_P_2
) },
4771 /* PREFIX_VEX_0F75 */
4775 { VEX_W_TABLE (VEX_W_0F75_P_2
) },
4778 /* PREFIX_VEX_0F76 */
4782 { VEX_W_TABLE (VEX_W_0F76_P_2
) },
4785 /* PREFIX_VEX_0F77 */
4787 { VEX_W_TABLE (VEX_W_0F77_P_0
) },
4790 /* PREFIX_VEX_0F7C */
4794 { VEX_W_TABLE (VEX_W_0F7C_P_2
) },
4795 { VEX_W_TABLE (VEX_W_0F7C_P_3
) },
4798 /* PREFIX_VEX_0F7D */
4802 { VEX_W_TABLE (VEX_W_0F7D_P_2
) },
4803 { VEX_W_TABLE (VEX_W_0F7D_P_3
) },
4806 /* PREFIX_VEX_0F7E */
4809 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1
) },
4810 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2
) },
4813 /* PREFIX_VEX_0F7F */
4816 { VEX_W_TABLE (VEX_W_0F7F_P_1
) },
4817 { VEX_W_TABLE (VEX_W_0F7F_P_2
) },
4820 /* PREFIX_VEX_0F90 */
4822 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0
) },
4825 /* PREFIX_VEX_0F91 */
4827 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0
) },
4830 /* PREFIX_VEX_0F92 */
4832 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0
) },
4835 /* PREFIX_VEX_0F93 */
4837 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0
) },
4840 /* PREFIX_VEX_0F98 */
4842 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0
) },
4845 /* PREFIX_VEX_0FC2 */
4847 { VEX_W_TABLE (VEX_W_0FC2_P_0
) },
4848 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1
) },
4849 { VEX_W_TABLE (VEX_W_0FC2_P_2
) },
4850 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3
) },
4853 /* PREFIX_VEX_0FC4 */
4857 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2
) },
4860 /* PREFIX_VEX_0FC5 */
4864 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2
) },
4867 /* PREFIX_VEX_0FD0 */
4871 { VEX_W_TABLE (VEX_W_0FD0_P_2
) },
4872 { VEX_W_TABLE (VEX_W_0FD0_P_3
) },
4875 /* PREFIX_VEX_0FD1 */
4879 { VEX_W_TABLE (VEX_W_0FD1_P_2
) },
4882 /* PREFIX_VEX_0FD2 */
4886 { VEX_W_TABLE (VEX_W_0FD2_P_2
) },
4889 /* PREFIX_VEX_0FD3 */
4893 { VEX_W_TABLE (VEX_W_0FD3_P_2
) },
4896 /* PREFIX_VEX_0FD4 */
4900 { VEX_W_TABLE (VEX_W_0FD4_P_2
) },
4903 /* PREFIX_VEX_0FD5 */
4907 { VEX_W_TABLE (VEX_W_0FD5_P_2
) },
4910 /* PREFIX_VEX_0FD6 */
4914 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2
) },
4917 /* PREFIX_VEX_0FD7 */
4921 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2
) },
4924 /* PREFIX_VEX_0FD8 */
4928 { VEX_W_TABLE (VEX_W_0FD8_P_2
) },
4931 /* PREFIX_VEX_0FD9 */
4935 { VEX_W_TABLE (VEX_W_0FD9_P_2
) },
4938 /* PREFIX_VEX_0FDA */
4942 { VEX_W_TABLE (VEX_W_0FDA_P_2
) },
4945 /* PREFIX_VEX_0FDB */
4949 { VEX_W_TABLE (VEX_W_0FDB_P_2
) },
4952 /* PREFIX_VEX_0FDC */
4956 { VEX_W_TABLE (VEX_W_0FDC_P_2
) },
4959 /* PREFIX_VEX_0FDD */
4963 { VEX_W_TABLE (VEX_W_0FDD_P_2
) },
4966 /* PREFIX_VEX_0FDE */
4970 { VEX_W_TABLE (VEX_W_0FDE_P_2
) },
4973 /* PREFIX_VEX_0FDF */
4977 { VEX_W_TABLE (VEX_W_0FDF_P_2
) },
4980 /* PREFIX_VEX_0FE0 */
4984 { VEX_W_TABLE (VEX_W_0FE0_P_2
) },
4987 /* PREFIX_VEX_0FE1 */
4991 { VEX_W_TABLE (VEX_W_0FE1_P_2
) },
4994 /* PREFIX_VEX_0FE2 */
4998 { VEX_W_TABLE (VEX_W_0FE2_P_2
) },
5001 /* PREFIX_VEX_0FE3 */
5005 { VEX_W_TABLE (VEX_W_0FE3_P_2
) },
5008 /* PREFIX_VEX_0FE4 */
5012 { VEX_W_TABLE (VEX_W_0FE4_P_2
) },
5015 /* PREFIX_VEX_0FE5 */
5019 { VEX_W_TABLE (VEX_W_0FE5_P_2
) },
5022 /* PREFIX_VEX_0FE6 */
5025 { VEX_W_TABLE (VEX_W_0FE6_P_1
) },
5026 { VEX_W_TABLE (VEX_W_0FE6_P_2
) },
5027 { VEX_W_TABLE (VEX_W_0FE6_P_3
) },
5030 /* PREFIX_VEX_0FE7 */
5034 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2
) },
5037 /* PREFIX_VEX_0FE8 */
5041 { VEX_W_TABLE (VEX_W_0FE8_P_2
) },
5044 /* PREFIX_VEX_0FE9 */
5048 { VEX_W_TABLE (VEX_W_0FE9_P_2
) },
5051 /* PREFIX_VEX_0FEA */
5055 { VEX_W_TABLE (VEX_W_0FEA_P_2
) },
5058 /* PREFIX_VEX_0FEB */
5062 { VEX_W_TABLE (VEX_W_0FEB_P_2
) },
5065 /* PREFIX_VEX_0FEC */
5069 { VEX_W_TABLE (VEX_W_0FEC_P_2
) },
5072 /* PREFIX_VEX_0FED */
5076 { VEX_W_TABLE (VEX_W_0FED_P_2
) },
5079 /* PREFIX_VEX_0FEE */
5083 { VEX_W_TABLE (VEX_W_0FEE_P_2
) },
5086 /* PREFIX_VEX_0FEF */
5090 { VEX_W_TABLE (VEX_W_0FEF_P_2
) },
5093 /* PREFIX_VEX_0FF0 */
5098 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3
) },
5101 /* PREFIX_VEX_0FF1 */
5105 { VEX_W_TABLE (VEX_W_0FF1_P_2
) },
5108 /* PREFIX_VEX_0FF2 */
5112 { VEX_W_TABLE (VEX_W_0FF2_P_2
) },
5115 /* PREFIX_VEX_0FF3 */
5119 { VEX_W_TABLE (VEX_W_0FF3_P_2
) },
5122 /* PREFIX_VEX_0FF4 */
5126 { VEX_W_TABLE (VEX_W_0FF4_P_2
) },
5129 /* PREFIX_VEX_0FF5 */
5133 { VEX_W_TABLE (VEX_W_0FF5_P_2
) },
5136 /* PREFIX_VEX_0FF6 */
5140 { VEX_W_TABLE (VEX_W_0FF6_P_2
) },
5143 /* PREFIX_VEX_0FF7 */
5147 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2
) },
5150 /* PREFIX_VEX_0FF8 */
5154 { VEX_W_TABLE (VEX_W_0FF8_P_2
) },
5157 /* PREFIX_VEX_0FF9 */
5161 { VEX_W_TABLE (VEX_W_0FF9_P_2
) },
5164 /* PREFIX_VEX_0FFA */
5168 { VEX_W_TABLE (VEX_W_0FFA_P_2
) },
5171 /* PREFIX_VEX_0FFB */
5175 { VEX_W_TABLE (VEX_W_0FFB_P_2
) },
5178 /* PREFIX_VEX_0FFC */
5182 { VEX_W_TABLE (VEX_W_0FFC_P_2
) },
5185 /* PREFIX_VEX_0FFD */
5189 { VEX_W_TABLE (VEX_W_0FFD_P_2
) },
5192 /* PREFIX_VEX_0FFE */
5196 { VEX_W_TABLE (VEX_W_0FFE_P_2
) },
5199 /* PREFIX_VEX_0F3800 */
5203 { VEX_W_TABLE (VEX_W_0F3800_P_2
) },
5206 /* PREFIX_VEX_0F3801 */
5210 { VEX_W_TABLE (VEX_W_0F3801_P_2
) },
5213 /* PREFIX_VEX_0F3802 */
5217 { VEX_W_TABLE (VEX_W_0F3802_P_2
) },
5220 /* PREFIX_VEX_0F3803 */
5224 { VEX_W_TABLE (VEX_W_0F3803_P_2
) },
5227 /* PREFIX_VEX_0F3804 */
5231 { VEX_W_TABLE (VEX_W_0F3804_P_2
) },
5234 /* PREFIX_VEX_0F3805 */
5238 { VEX_W_TABLE (VEX_W_0F3805_P_2
) },
5241 /* PREFIX_VEX_0F3806 */
5245 { VEX_W_TABLE (VEX_W_0F3806_P_2
) },
5248 /* PREFIX_VEX_0F3807 */
5252 { VEX_W_TABLE (VEX_W_0F3807_P_2
) },
5255 /* PREFIX_VEX_0F3808 */
5259 { VEX_W_TABLE (VEX_W_0F3808_P_2
) },
5262 /* PREFIX_VEX_0F3809 */
5266 { VEX_W_TABLE (VEX_W_0F3809_P_2
) },
5269 /* PREFIX_VEX_0F380A */
5273 { VEX_W_TABLE (VEX_W_0F380A_P_2
) },
5276 /* PREFIX_VEX_0F380B */
5280 { VEX_W_TABLE (VEX_W_0F380B_P_2
) },
5283 /* PREFIX_VEX_0F380C */
5287 { VEX_W_TABLE (VEX_W_0F380C_P_2
) },
5290 /* PREFIX_VEX_0F380D */
5294 { VEX_W_TABLE (VEX_W_0F380D_P_2
) },
5297 /* PREFIX_VEX_0F380E */
5301 { VEX_W_TABLE (VEX_W_0F380E_P_2
) },
5304 /* PREFIX_VEX_0F380F */
5308 { VEX_W_TABLE (VEX_W_0F380F_P_2
) },
5311 /* PREFIX_VEX_0F3813 */
5315 { "vcvtph2ps", { XM
, EXxmmq
} },
5318 /* PREFIX_VEX_0F3816 */
5322 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2
) },
5325 /* PREFIX_VEX_0F3817 */
5329 { VEX_W_TABLE (VEX_W_0F3817_P_2
) },
5332 /* PREFIX_VEX_0F3818 */
5336 { VEX_W_TABLE (VEX_W_0F3818_P_2
) },
5339 /* PREFIX_VEX_0F3819 */
5343 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2
) },
5346 /* PREFIX_VEX_0F381A */
5350 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2
) },
5353 /* PREFIX_VEX_0F381C */
5357 { VEX_W_TABLE (VEX_W_0F381C_P_2
) },
5360 /* PREFIX_VEX_0F381D */
5364 { VEX_W_TABLE (VEX_W_0F381D_P_2
) },
5367 /* PREFIX_VEX_0F381E */
5371 { VEX_W_TABLE (VEX_W_0F381E_P_2
) },
5374 /* PREFIX_VEX_0F3820 */
5378 { VEX_W_TABLE (VEX_W_0F3820_P_2
) },
5381 /* PREFIX_VEX_0F3821 */
5385 { VEX_W_TABLE (VEX_W_0F3821_P_2
) },
5388 /* PREFIX_VEX_0F3822 */
5392 { VEX_W_TABLE (VEX_W_0F3822_P_2
) },
5395 /* PREFIX_VEX_0F3823 */
5399 { VEX_W_TABLE (VEX_W_0F3823_P_2
) },
5402 /* PREFIX_VEX_0F3824 */
5406 { VEX_W_TABLE (VEX_W_0F3824_P_2
) },
5409 /* PREFIX_VEX_0F3825 */
5413 { VEX_W_TABLE (VEX_W_0F3825_P_2
) },
5416 /* PREFIX_VEX_0F3828 */
5420 { VEX_W_TABLE (VEX_W_0F3828_P_2
) },
5423 /* PREFIX_VEX_0F3829 */
5427 { VEX_W_TABLE (VEX_W_0F3829_P_2
) },
5430 /* PREFIX_VEX_0F382A */
5434 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2
) },
5437 /* PREFIX_VEX_0F382B */
5441 { VEX_W_TABLE (VEX_W_0F382B_P_2
) },
5444 /* PREFIX_VEX_0F382C */
5448 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2
) },
5451 /* PREFIX_VEX_0F382D */
5455 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2
) },
5458 /* PREFIX_VEX_0F382E */
5462 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2
) },
5465 /* PREFIX_VEX_0F382F */
5469 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2
) },
5472 /* PREFIX_VEX_0F3830 */
5476 { VEX_W_TABLE (VEX_W_0F3830_P_2
) },
5479 /* PREFIX_VEX_0F3831 */
5483 { VEX_W_TABLE (VEX_W_0F3831_P_2
) },
5486 /* PREFIX_VEX_0F3832 */
5490 { VEX_W_TABLE (VEX_W_0F3832_P_2
) },
5493 /* PREFIX_VEX_0F3833 */
5497 { VEX_W_TABLE (VEX_W_0F3833_P_2
) },
5500 /* PREFIX_VEX_0F3834 */
5504 { VEX_W_TABLE (VEX_W_0F3834_P_2
) },
5507 /* PREFIX_VEX_0F3835 */
5511 { VEX_W_TABLE (VEX_W_0F3835_P_2
) },
5514 /* PREFIX_VEX_0F3836 */
5518 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2
) },
5521 /* PREFIX_VEX_0F3837 */
5525 { VEX_W_TABLE (VEX_W_0F3837_P_2
) },
5528 /* PREFIX_VEX_0F3838 */
5532 { VEX_W_TABLE (VEX_W_0F3838_P_2
) },
5535 /* PREFIX_VEX_0F3839 */
5539 { VEX_W_TABLE (VEX_W_0F3839_P_2
) },
5542 /* PREFIX_VEX_0F383A */
5546 { VEX_W_TABLE (VEX_W_0F383A_P_2
) },
5549 /* PREFIX_VEX_0F383B */
5553 { VEX_W_TABLE (VEX_W_0F383B_P_2
) },
5556 /* PREFIX_VEX_0F383C */
5560 { VEX_W_TABLE (VEX_W_0F383C_P_2
) },
5563 /* PREFIX_VEX_0F383D */
5567 { VEX_W_TABLE (VEX_W_0F383D_P_2
) },
5570 /* PREFIX_VEX_0F383E */
5574 { VEX_W_TABLE (VEX_W_0F383E_P_2
) },
5577 /* PREFIX_VEX_0F383F */
5581 { VEX_W_TABLE (VEX_W_0F383F_P_2
) },
5584 /* PREFIX_VEX_0F3840 */
5588 { VEX_W_TABLE (VEX_W_0F3840_P_2
) },
5591 /* PREFIX_VEX_0F3841 */
5595 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2
) },
5598 /* PREFIX_VEX_0F3845 */
5602 { "vpsrlv%LW", { XM
, Vex
, EXx
} },
5605 /* PREFIX_VEX_0F3846 */
5609 { VEX_W_TABLE (VEX_W_0F3846_P_2
) },
5612 /* PREFIX_VEX_0F3847 */
5616 { "vpsllv%LW", { XM
, Vex
, EXx
} },
5619 /* PREFIX_VEX_0F3858 */
5623 { VEX_W_TABLE (VEX_W_0F3858_P_2
) },
5626 /* PREFIX_VEX_0F3859 */
5630 { VEX_W_TABLE (VEX_W_0F3859_P_2
) },
5633 /* PREFIX_VEX_0F385A */
5637 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2
) },
5640 /* PREFIX_VEX_0F3878 */
5644 { VEX_W_TABLE (VEX_W_0F3878_P_2
) },
5647 /* PREFIX_VEX_0F3879 */
5651 { VEX_W_TABLE (VEX_W_0F3879_P_2
) },
5654 /* PREFIX_VEX_0F388C */
5658 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2
) },
5661 /* PREFIX_VEX_0F388E */
5665 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2
) },
5668 /* PREFIX_VEX_0F3890 */
5672 { "vpgatherd%LW", { XM
, MVexVSIBDWpX
, Vex
} },
5675 /* PREFIX_VEX_0F3891 */
5679 { "vpgatherq%LW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5682 /* PREFIX_VEX_0F3892 */
5686 { "vgatherdp%XW", { XM
, MVexVSIBDWpX
, Vex
} },
5689 /* PREFIX_VEX_0F3893 */
5693 { "vgatherqp%XW", { XMGatherQ
, MVexVSIBQWpX
, VexGatherQ
} },
5696 /* PREFIX_VEX_0F3896 */
5700 { "vfmaddsub132p%XW", { XM
, Vex
, EXx
} },
5703 /* PREFIX_VEX_0F3897 */
5707 { "vfmsubadd132p%XW", { XM
, Vex
, EXx
} },
5710 /* PREFIX_VEX_0F3898 */
5714 { "vfmadd132p%XW", { XM
, Vex
, EXx
} },
5717 /* PREFIX_VEX_0F3899 */
5721 { "vfmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5724 /* PREFIX_VEX_0F389A */
5728 { "vfmsub132p%XW", { XM
, Vex
, EXx
} },
5731 /* PREFIX_VEX_0F389B */
5735 { "vfmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5738 /* PREFIX_VEX_0F389C */
5742 { "vfnmadd132p%XW", { XM
, Vex
, EXx
} },
5745 /* PREFIX_VEX_0F389D */
5749 { "vfnmadd132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5752 /* PREFIX_VEX_0F389E */
5756 { "vfnmsub132p%XW", { XM
, Vex
, EXx
} },
5759 /* PREFIX_VEX_0F389F */
5763 { "vfnmsub132s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5766 /* PREFIX_VEX_0F38A6 */
5770 { "vfmaddsub213p%XW", { XM
, Vex
, EXx
} },
5774 /* PREFIX_VEX_0F38A7 */
5778 { "vfmsubadd213p%XW", { XM
, Vex
, EXx
} },
5781 /* PREFIX_VEX_0F38A8 */
5785 { "vfmadd213p%XW", { XM
, Vex
, EXx
} },
5788 /* PREFIX_VEX_0F38A9 */
5792 { "vfmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5795 /* PREFIX_VEX_0F38AA */
5799 { "vfmsub213p%XW", { XM
, Vex
, EXx
} },
5802 /* PREFIX_VEX_0F38AB */
5806 { "vfmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5809 /* PREFIX_VEX_0F38AC */
5813 { "vfnmadd213p%XW", { XM
, Vex
, EXx
} },
5816 /* PREFIX_VEX_0F38AD */
5820 { "vfnmadd213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5823 /* PREFIX_VEX_0F38AE */
5827 { "vfnmsub213p%XW", { XM
, Vex
, EXx
} },
5830 /* PREFIX_VEX_0F38AF */
5834 { "vfnmsub213s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5837 /* PREFIX_VEX_0F38B6 */
5841 { "vfmaddsub231p%XW", { XM
, Vex
, EXx
} },
5844 /* PREFIX_VEX_0F38B7 */
5848 { "vfmsubadd231p%XW", { XM
, Vex
, EXx
} },
5851 /* PREFIX_VEX_0F38B8 */
5855 { "vfmadd231p%XW", { XM
, Vex
, EXx
} },
5858 /* PREFIX_VEX_0F38B9 */
5862 { "vfmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5865 /* PREFIX_VEX_0F38BA */
5869 { "vfmsub231p%XW", { XM
, Vex
, EXx
} },
5872 /* PREFIX_VEX_0F38BB */
5876 { "vfmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5879 /* PREFIX_VEX_0F38BC */
5883 { "vfnmadd231p%XW", { XM
, Vex
, EXx
} },
5886 /* PREFIX_VEX_0F38BD */
5890 { "vfnmadd231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5893 /* PREFIX_VEX_0F38BE */
5897 { "vfnmsub231p%XW", { XM
, Vex
, EXx
} },
5900 /* PREFIX_VEX_0F38BF */
5904 { "vfnmsub231s%XW", { XMScalar
, VexScalar
, EXVexWdqScalar
} },
5907 /* PREFIX_VEX_0F38DB */
5911 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2
) },
5914 /* PREFIX_VEX_0F38DC */
5918 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2
) },
5921 /* PREFIX_VEX_0F38DD */
5925 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2
) },
5928 /* PREFIX_VEX_0F38DE */
5932 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2
) },
5935 /* PREFIX_VEX_0F38DF */
5939 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2
) },
5942 /* PREFIX_VEX_0F38F2 */
5944 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0
) },
5947 /* PREFIX_VEX_0F38F3_REG_1 */
5949 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0
) },
5952 /* PREFIX_VEX_0F38F3_REG_2 */
5954 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0
) },
5957 /* PREFIX_VEX_0F38F3_REG_3 */
5959 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0
) },
5962 /* PREFIX_VEX_0F38F5 */
5964 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0
) },
5965 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1
) },
5967 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3
) },
5970 /* PREFIX_VEX_0F38F6 */
5975 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3
) },
5978 /* PREFIX_VEX_0F38F7 */
5980 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0
) },
5981 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1
) },
5982 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2
) },
5983 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3
) },
5986 /* PREFIX_VEX_0F3A00 */
5990 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2
) },
5993 /* PREFIX_VEX_0F3A01 */
5997 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2
) },
6000 /* PREFIX_VEX_0F3A02 */
6004 { VEX_W_TABLE (VEX_W_0F3A02_P_2
) },
6007 /* PREFIX_VEX_0F3A04 */
6011 { VEX_W_TABLE (VEX_W_0F3A04_P_2
) },
6014 /* PREFIX_VEX_0F3A05 */
6018 { VEX_W_TABLE (VEX_W_0F3A05_P_2
) },
6021 /* PREFIX_VEX_0F3A06 */
6025 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2
) },
6028 /* PREFIX_VEX_0F3A08 */
6032 { VEX_W_TABLE (VEX_W_0F3A08_P_2
) },
6035 /* PREFIX_VEX_0F3A09 */
6039 { VEX_W_TABLE (VEX_W_0F3A09_P_2
) },
6042 /* PREFIX_VEX_0F3A0A */
6046 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2
) },
6049 /* PREFIX_VEX_0F3A0B */
6053 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2
) },
6056 /* PREFIX_VEX_0F3A0C */
6060 { VEX_W_TABLE (VEX_W_0F3A0C_P_2
) },
6063 /* PREFIX_VEX_0F3A0D */
6067 { VEX_W_TABLE (VEX_W_0F3A0D_P_2
) },
6070 /* PREFIX_VEX_0F3A0E */
6074 { VEX_W_TABLE (VEX_W_0F3A0E_P_2
) },
6077 /* PREFIX_VEX_0F3A0F */
6081 { VEX_W_TABLE (VEX_W_0F3A0F_P_2
) },
6084 /* PREFIX_VEX_0F3A14 */
6088 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2
) },
6091 /* PREFIX_VEX_0F3A15 */
6095 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2
) },
6098 /* PREFIX_VEX_0F3A16 */
6102 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2
) },
6105 /* PREFIX_VEX_0F3A17 */
6109 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2
) },
6112 /* PREFIX_VEX_0F3A18 */
6116 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2
) },
6119 /* PREFIX_VEX_0F3A19 */
6123 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2
) },
6126 /* PREFIX_VEX_0F3A1D */
6130 { "vcvtps2ph", { EXxmmq
, XM
, Ib
} },
6133 /* PREFIX_VEX_0F3A20 */
6137 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2
) },
6140 /* PREFIX_VEX_0F3A21 */
6144 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2
) },
6147 /* PREFIX_VEX_0F3A22 */
6151 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2
) },
6154 /* PREFIX_VEX_0F3A30 */
6158 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2
) },
6161 /* PREFIX_VEX_0F3A32 */
6165 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2
) },
6168 /* PREFIX_VEX_0F3A38 */
6172 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2
) },
6175 /* PREFIX_VEX_0F3A39 */
6179 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2
) },
6182 /* PREFIX_VEX_0F3A40 */
6186 { VEX_W_TABLE (VEX_W_0F3A40_P_2
) },
6189 /* PREFIX_VEX_0F3A41 */
6193 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2
) },
6196 /* PREFIX_VEX_0F3A42 */
6200 { VEX_W_TABLE (VEX_W_0F3A42_P_2
) },
6203 /* PREFIX_VEX_0F3A44 */
6207 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2
) },
6210 /* PREFIX_VEX_0F3A46 */
6214 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2
) },
6217 /* PREFIX_VEX_0F3A48 */
6221 { VEX_W_TABLE (VEX_W_0F3A48_P_2
) },
6224 /* PREFIX_VEX_0F3A49 */
6228 { VEX_W_TABLE (VEX_W_0F3A49_P_2
) },
6231 /* PREFIX_VEX_0F3A4A */
6235 { VEX_W_TABLE (VEX_W_0F3A4A_P_2
) },
6238 /* PREFIX_VEX_0F3A4B */
6242 { VEX_W_TABLE (VEX_W_0F3A4B_P_2
) },
6245 /* PREFIX_VEX_0F3A4C */
6249 { VEX_W_TABLE (VEX_W_0F3A4C_P_2
) },
6252 /* PREFIX_VEX_0F3A5C */
6256 { "vfmaddsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6259 /* PREFIX_VEX_0F3A5D */
6263 { "vfmaddsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6266 /* PREFIX_VEX_0F3A5E */
6270 { "vfmsubaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6273 /* PREFIX_VEX_0F3A5F */
6277 { "vfmsubaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6280 /* PREFIX_VEX_0F3A60 */
6284 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2
) },
6288 /* PREFIX_VEX_0F3A61 */
6292 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2
) },
6295 /* PREFIX_VEX_0F3A62 */
6299 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2
) },
6302 /* PREFIX_VEX_0F3A63 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2
) },
6309 /* PREFIX_VEX_0F3A68 */
6313 { "vfmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6316 /* PREFIX_VEX_0F3A69 */
6320 { "vfmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6323 /* PREFIX_VEX_0F3A6A */
6327 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2
) },
6330 /* PREFIX_VEX_0F3A6B */
6334 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2
) },
6337 /* PREFIX_VEX_0F3A6C */
6341 { "vfmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6344 /* PREFIX_VEX_0F3A6D */
6348 { "vfmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6351 /* PREFIX_VEX_0F3A6E */
6355 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2
) },
6358 /* PREFIX_VEX_0F3A6F */
6362 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2
) },
6365 /* PREFIX_VEX_0F3A78 */
6369 { "vfnmaddps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6372 /* PREFIX_VEX_0F3A79 */
6376 { "vfnmaddpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6379 /* PREFIX_VEX_0F3A7A */
6383 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2
) },
6386 /* PREFIX_VEX_0F3A7B */
6390 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2
) },
6393 /* PREFIX_VEX_0F3A7C */
6397 { "vfnmsubps", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6401 /* PREFIX_VEX_0F3A7D */
6405 { "vfnmsubpd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
6408 /* PREFIX_VEX_0F3A7E */
6412 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2
) },
6415 /* PREFIX_VEX_0F3A7F */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2
) },
6422 /* PREFIX_VEX_0F3ADF */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2
) },
6429 /* PREFIX_VEX_0F3AF0 */
6434 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3
) },
6437 #define NEED_PREFIX_TABLE
6438 #include "i386-dis-evex.h"
6439 #undef NEED_PREFIX_TABLE
6442 static const struct dis386 x86_64_table
[][2] = {
6445 { "pushP", { es
} },
6455 { "pushP", { cs
} },
6460 { "pushP", { ss
} },
6470 { "pushP", { ds
} },
6500 { "pushaP", { XX
} },
6505 { "popaP", { XX
} },
6510 { MOD_TABLE (MOD_62_32BIT
) },
6511 { EVEX_TABLE (EVEX_0F
) },
6516 { "arpl", { Ew
, Gw
} },
6517 { "movs{lq|xd}", { Gv
, Ed
} },
6522 { "ins{R|}", { Yzr
, indirDX
} },
6523 { "ins{G|}", { Yzr
, indirDX
} },
6528 { "outs{R|}", { indirDXr
, Xz
} },
6529 { "outs{G|}", { indirDXr
, Xz
} },
6534 { "Jcall{T|}", { Ap
} },
6539 { MOD_TABLE (MOD_C4_32BIT
) },
6540 { VEX_C4_TABLE (VEX_0F
) },
6545 { MOD_TABLE (MOD_C5_32BIT
) },
6546 { VEX_C5_TABLE (VEX_0F
) },
6566 { "Jjmp{T|}", { Ap
} },
6569 /* X86_64_0F01_REG_0 */
6571 { "sgdt{Q|IQ}", { M
} },
6575 /* X86_64_0F01_REG_1 */
6577 { "sidt{Q|IQ}", { M
} },
6581 /* X86_64_0F01_REG_2 */
6583 { "lgdt{Q|Q}", { M
} },
6587 /* X86_64_0F01_REG_3 */
6589 { "lidt{Q|Q}", { M
} },
6594 static const struct dis386 three_byte_table
[][256] = {
6596 /* THREE_BYTE_0F38 */
6599 { "pshufb", { MX
, EM
} },
6600 { "phaddw", { MX
, EM
} },
6601 { "phaddd", { MX
, EM
} },
6602 { "phaddsw", { MX
, EM
} },
6603 { "pmaddubsw", { MX
, EM
} },
6604 { "phsubw", { MX
, EM
} },
6605 { "phsubd", { MX
, EM
} },
6606 { "phsubsw", { MX
, EM
} },
6608 { "psignb", { MX
, EM
} },
6609 { "psignw", { MX
, EM
} },
6610 { "psignd", { MX
, EM
} },
6611 { "pmulhrsw", { MX
, EM
} },
6617 { PREFIX_TABLE (PREFIX_0F3810
) },
6621 { PREFIX_TABLE (PREFIX_0F3814
) },
6622 { PREFIX_TABLE (PREFIX_0F3815
) },
6624 { PREFIX_TABLE (PREFIX_0F3817
) },
6630 { "pabsb", { MX
, EM
} },
6631 { "pabsw", { MX
, EM
} },
6632 { "pabsd", { MX
, EM
} },
6635 { PREFIX_TABLE (PREFIX_0F3820
) },
6636 { PREFIX_TABLE (PREFIX_0F3821
) },
6637 { PREFIX_TABLE (PREFIX_0F3822
) },
6638 { PREFIX_TABLE (PREFIX_0F3823
) },
6639 { PREFIX_TABLE (PREFIX_0F3824
) },
6640 { PREFIX_TABLE (PREFIX_0F3825
) },
6644 { PREFIX_TABLE (PREFIX_0F3828
) },
6645 { PREFIX_TABLE (PREFIX_0F3829
) },
6646 { PREFIX_TABLE (PREFIX_0F382A
) },
6647 { PREFIX_TABLE (PREFIX_0F382B
) },
6653 { PREFIX_TABLE (PREFIX_0F3830
) },
6654 { PREFIX_TABLE (PREFIX_0F3831
) },
6655 { PREFIX_TABLE (PREFIX_0F3832
) },
6656 { PREFIX_TABLE (PREFIX_0F3833
) },
6657 { PREFIX_TABLE (PREFIX_0F3834
) },
6658 { PREFIX_TABLE (PREFIX_0F3835
) },
6660 { PREFIX_TABLE (PREFIX_0F3837
) },
6662 { PREFIX_TABLE (PREFIX_0F3838
) },
6663 { PREFIX_TABLE (PREFIX_0F3839
) },
6664 { PREFIX_TABLE (PREFIX_0F383A
) },
6665 { PREFIX_TABLE (PREFIX_0F383B
) },
6666 { PREFIX_TABLE (PREFIX_0F383C
) },
6667 { PREFIX_TABLE (PREFIX_0F383D
) },
6668 { PREFIX_TABLE (PREFIX_0F383E
) },
6669 { PREFIX_TABLE (PREFIX_0F383F
) },
6671 { PREFIX_TABLE (PREFIX_0F3840
) },
6672 { PREFIX_TABLE (PREFIX_0F3841
) },
6743 { PREFIX_TABLE (PREFIX_0F3880
) },
6744 { PREFIX_TABLE (PREFIX_0F3881
) },
6745 { PREFIX_TABLE (PREFIX_0F3882
) },
6824 { PREFIX_TABLE (PREFIX_0F38C8
) },
6825 { PREFIX_TABLE (PREFIX_0F38C9
) },
6826 { PREFIX_TABLE (PREFIX_0F38CA
) },
6827 { PREFIX_TABLE (PREFIX_0F38CB
) },
6828 { PREFIX_TABLE (PREFIX_0F38CC
) },
6829 { PREFIX_TABLE (PREFIX_0F38CD
) },
6845 { PREFIX_TABLE (PREFIX_0F38DB
) },
6846 { PREFIX_TABLE (PREFIX_0F38DC
) },
6847 { PREFIX_TABLE (PREFIX_0F38DD
) },
6848 { PREFIX_TABLE (PREFIX_0F38DE
) },
6849 { PREFIX_TABLE (PREFIX_0F38DF
) },
6869 { PREFIX_TABLE (PREFIX_0F38F0
) },
6870 { PREFIX_TABLE (PREFIX_0F38F1
) },
6875 { PREFIX_TABLE (PREFIX_0F38F6
) },
6887 /* THREE_BYTE_0F3A */
6899 { PREFIX_TABLE (PREFIX_0F3A08
) },
6900 { PREFIX_TABLE (PREFIX_0F3A09
) },
6901 { PREFIX_TABLE (PREFIX_0F3A0A
) },
6902 { PREFIX_TABLE (PREFIX_0F3A0B
) },
6903 { PREFIX_TABLE (PREFIX_0F3A0C
) },
6904 { PREFIX_TABLE (PREFIX_0F3A0D
) },
6905 { PREFIX_TABLE (PREFIX_0F3A0E
) },
6906 { "palignr", { MX
, EM
, Ib
} },
6912 { PREFIX_TABLE (PREFIX_0F3A14
) },
6913 { PREFIX_TABLE (PREFIX_0F3A15
) },
6914 { PREFIX_TABLE (PREFIX_0F3A16
) },
6915 { PREFIX_TABLE (PREFIX_0F3A17
) },
6926 { PREFIX_TABLE (PREFIX_0F3A20
) },
6927 { PREFIX_TABLE (PREFIX_0F3A21
) },
6928 { PREFIX_TABLE (PREFIX_0F3A22
) },
6962 { PREFIX_TABLE (PREFIX_0F3A40
) },
6963 { PREFIX_TABLE (PREFIX_0F3A41
) },
6964 { PREFIX_TABLE (PREFIX_0F3A42
) },
6966 { PREFIX_TABLE (PREFIX_0F3A44
) },
6998 { PREFIX_TABLE (PREFIX_0F3A60
) },
6999 { PREFIX_TABLE (PREFIX_0F3A61
) },
7000 { PREFIX_TABLE (PREFIX_0F3A62
) },
7001 { PREFIX_TABLE (PREFIX_0F3A63
) },
7119 { PREFIX_TABLE (PREFIX_0F3ACC
) },
7140 { PREFIX_TABLE (PREFIX_0F3ADF
) },
7179 /* THREE_BYTE_0F7A */
7218 { "ptest", { XX
} },
7255 { "phaddbw", { XM
, EXq
} },
7256 { "phaddbd", { XM
, EXq
} },
7257 { "phaddbq", { XM
, EXq
} },
7260 { "phaddwd", { XM
, EXq
} },
7261 { "phaddwq", { XM
, EXq
} },
7266 { "phadddq", { XM
, EXq
} },
7273 { "phaddubw", { XM
, EXq
} },
7274 { "phaddubd", { XM
, EXq
} },
7275 { "phaddubq", { XM
, EXq
} },
7278 { "phadduwd", { XM
, EXq
} },
7279 { "phadduwq", { XM
, EXq
} },
7284 { "phaddudq", { XM
, EXq
} },
7291 { "phsubbw", { XM
, EXq
} },
7292 { "phsubbd", { XM
, EXq
} },
7293 { "phsubbq", { XM
, EXq
} },
7472 static const struct dis386 xop_table
[][256] = {
7625 { "vpmacssww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7626 { "vpmacsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7627 { "vpmacssdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7635 { "vpmacssdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7636 { "vpmacssdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7643 { "vpmacsww", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7644 { "vpmacswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7645 { "vpmacsdql", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7653 { "vpmacsdd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7654 { "vpmacsdqh", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7658 { "vpcmov", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7659 { "vpperm", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7662 { "vpmadcsswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7680 { "vpmadcswd", { XMVexW
, Vex
, EXVexW
, EXVexW
, VexI4
} },
7692 { "vprotb", { XM
, Vex_2src_1
, Ib
} },
7693 { "vprotw", { XM
, Vex_2src_1
, Ib
} },
7694 { "vprotd", { XM
, Vex_2src_1
, Ib
} },
7695 { "vprotq", { XM
, Vex_2src_1
, Ib
} },
7705 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC
) },
7706 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD
) },
7707 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE
) },
7708 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF
) },
7741 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC
) },
7742 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED
) },
7743 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE
) },
7744 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF
) },
7768 { REG_TABLE (REG_XOP_TBM_01
) },
7769 { REG_TABLE (REG_XOP_TBM_02
) },
7787 { REG_TABLE (REG_XOP_LWPCB
) },
7911 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80
) },
7912 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81
) },
7913 { "vfrczss", { XM
, EXd
} },
7914 { "vfrczsd", { XM
, EXq
} },
7929 { "vprotb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7930 { "vprotw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7931 { "vprotd", { XM
, Vex_2src_1
, Vex_2src_2
} },
7932 { "vprotq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7933 { "vpshlb", { XM
, Vex_2src_1
, Vex_2src_2
} },
7934 { "vpshlw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7935 { "vpshld", { XM
, Vex_2src_1
, Vex_2src_2
} },
7936 { "vpshlq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7938 { "vpshab", { XM
, Vex_2src_1
, Vex_2src_2
} },
7939 { "vpshaw", { XM
, Vex_2src_1
, Vex_2src_2
} },
7940 { "vpshad", { XM
, Vex_2src_1
, Vex_2src_2
} },
7941 { "vpshaq", { XM
, Vex_2src_1
, Vex_2src_2
} },
7984 { "vphaddbw", { XM
, EXxmm
} },
7985 { "vphaddbd", { XM
, EXxmm
} },
7986 { "vphaddbq", { XM
, EXxmm
} },
7989 { "vphaddwd", { XM
, EXxmm
} },
7990 { "vphaddwq", { XM
, EXxmm
} },
7995 { "vphadddq", { XM
, EXxmm
} },
8002 { "vphaddubw", { XM
, EXxmm
} },
8003 { "vphaddubd", { XM
, EXxmm
} },
8004 { "vphaddubq", { XM
, EXxmm
} },
8007 { "vphadduwd", { XM
, EXxmm
} },
8008 { "vphadduwq", { XM
, EXxmm
} },
8013 { "vphaddudq", { XM
, EXxmm
} },
8020 { "vphsubbw", { XM
, EXxmm
} },
8021 { "vphsubwd", { XM
, EXxmm
} },
8022 { "vphsubdq", { XM
, EXxmm
} },
8076 { "bextr", { Gv
, Ev
, Iq
} },
8078 { REG_TABLE (REG_XOP_LWP
) },
8348 static const struct dis386 vex_table
[][256] = {
8370 { PREFIX_TABLE (PREFIX_VEX_0F10
) },
8371 { PREFIX_TABLE (PREFIX_VEX_0F11
) },
8372 { PREFIX_TABLE (PREFIX_VEX_0F12
) },
8373 { MOD_TABLE (MOD_VEX_0F13
) },
8374 { VEX_W_TABLE (VEX_W_0F14
) },
8375 { VEX_W_TABLE (VEX_W_0F15
) },
8376 { PREFIX_TABLE (PREFIX_VEX_0F16
) },
8377 { MOD_TABLE (MOD_VEX_0F17
) },
8397 { VEX_W_TABLE (VEX_W_0F28
) },
8398 { VEX_W_TABLE (VEX_W_0F29
) },
8399 { PREFIX_TABLE (PREFIX_VEX_0F2A
) },
8400 { MOD_TABLE (MOD_VEX_0F2B
) },
8401 { PREFIX_TABLE (PREFIX_VEX_0F2C
) },
8402 { PREFIX_TABLE (PREFIX_VEX_0F2D
) },
8403 { PREFIX_TABLE (PREFIX_VEX_0F2E
) },
8404 { PREFIX_TABLE (PREFIX_VEX_0F2F
) },
8425 { PREFIX_TABLE (PREFIX_VEX_0F41
) },
8426 { PREFIX_TABLE (PREFIX_VEX_0F42
) },
8428 { PREFIX_TABLE (PREFIX_VEX_0F44
) },
8429 { PREFIX_TABLE (PREFIX_VEX_0F45
) },
8430 { PREFIX_TABLE (PREFIX_VEX_0F46
) },
8431 { PREFIX_TABLE (PREFIX_VEX_0F47
) },
8436 { PREFIX_TABLE (PREFIX_VEX_0F4B
) },
8442 { MOD_TABLE (MOD_VEX_0F50
) },
8443 { PREFIX_TABLE (PREFIX_VEX_0F51
) },
8444 { PREFIX_TABLE (PREFIX_VEX_0F52
) },
8445 { PREFIX_TABLE (PREFIX_VEX_0F53
) },
8446 { "vandpX", { XM
, Vex
, EXx
} },
8447 { "vandnpX", { XM
, Vex
, EXx
} },
8448 { "vorpX", { XM
, Vex
, EXx
} },
8449 { "vxorpX", { XM
, Vex
, EXx
} },
8451 { PREFIX_TABLE (PREFIX_VEX_0F58
) },
8452 { PREFIX_TABLE (PREFIX_VEX_0F59
) },
8453 { PREFIX_TABLE (PREFIX_VEX_0F5A
) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F5B
) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F5C
) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F5D
) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F5E
) },
8458 { PREFIX_TABLE (PREFIX_VEX_0F5F
) },
8460 { PREFIX_TABLE (PREFIX_VEX_0F60
) },
8461 { PREFIX_TABLE (PREFIX_VEX_0F61
) },
8462 { PREFIX_TABLE (PREFIX_VEX_0F62
) },
8463 { PREFIX_TABLE (PREFIX_VEX_0F63
) },
8464 { PREFIX_TABLE (PREFIX_VEX_0F64
) },
8465 { PREFIX_TABLE (PREFIX_VEX_0F65
) },
8466 { PREFIX_TABLE (PREFIX_VEX_0F66
) },
8467 { PREFIX_TABLE (PREFIX_VEX_0F67
) },
8469 { PREFIX_TABLE (PREFIX_VEX_0F68
) },
8470 { PREFIX_TABLE (PREFIX_VEX_0F69
) },
8471 { PREFIX_TABLE (PREFIX_VEX_0F6A
) },
8472 { PREFIX_TABLE (PREFIX_VEX_0F6B
) },
8473 { PREFIX_TABLE (PREFIX_VEX_0F6C
) },
8474 { PREFIX_TABLE (PREFIX_VEX_0F6D
) },
8475 { PREFIX_TABLE (PREFIX_VEX_0F6E
) },
8476 { PREFIX_TABLE (PREFIX_VEX_0F6F
) },
8478 { PREFIX_TABLE (PREFIX_VEX_0F70
) },
8479 { REG_TABLE (REG_VEX_0F71
) },
8480 { REG_TABLE (REG_VEX_0F72
) },
8481 { REG_TABLE (REG_VEX_0F73
) },
8482 { PREFIX_TABLE (PREFIX_VEX_0F74
) },
8483 { PREFIX_TABLE (PREFIX_VEX_0F75
) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F76
) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F77
) },
8491 { PREFIX_TABLE (PREFIX_VEX_0F7C
) },
8492 { PREFIX_TABLE (PREFIX_VEX_0F7D
) },
8493 { PREFIX_TABLE (PREFIX_VEX_0F7E
) },
8494 { PREFIX_TABLE (PREFIX_VEX_0F7F
) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F90
) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F91
) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F92
) },
8517 { PREFIX_TABLE (PREFIX_VEX_0F93
) },
8523 { PREFIX_TABLE (PREFIX_VEX_0F98
) },
8547 { REG_TABLE (REG_VEX_0FAE
) },
8570 { PREFIX_TABLE (PREFIX_VEX_0FC2
) },
8572 { PREFIX_TABLE (PREFIX_VEX_0FC4
) },
8573 { PREFIX_TABLE (PREFIX_VEX_0FC5
) },
8574 { "vshufpX", { XM
, Vex
, EXx
, Ib
} },
8586 { PREFIX_TABLE (PREFIX_VEX_0FD0
) },
8587 { PREFIX_TABLE (PREFIX_VEX_0FD1
) },
8588 { PREFIX_TABLE (PREFIX_VEX_0FD2
) },
8589 { PREFIX_TABLE (PREFIX_VEX_0FD3
) },
8590 { PREFIX_TABLE (PREFIX_VEX_0FD4
) },
8591 { PREFIX_TABLE (PREFIX_VEX_0FD5
) },
8592 { PREFIX_TABLE (PREFIX_VEX_0FD6
) },
8593 { PREFIX_TABLE (PREFIX_VEX_0FD7
) },
8595 { PREFIX_TABLE (PREFIX_VEX_0FD8
) },
8596 { PREFIX_TABLE (PREFIX_VEX_0FD9
) },
8597 { PREFIX_TABLE (PREFIX_VEX_0FDA
) },
8598 { PREFIX_TABLE (PREFIX_VEX_0FDB
) },
8599 { PREFIX_TABLE (PREFIX_VEX_0FDC
) },
8600 { PREFIX_TABLE (PREFIX_VEX_0FDD
) },
8601 { PREFIX_TABLE (PREFIX_VEX_0FDE
) },
8602 { PREFIX_TABLE (PREFIX_VEX_0FDF
) },
8604 { PREFIX_TABLE (PREFIX_VEX_0FE0
) },
8605 { PREFIX_TABLE (PREFIX_VEX_0FE1
) },
8606 { PREFIX_TABLE (PREFIX_VEX_0FE2
) },
8607 { PREFIX_TABLE (PREFIX_VEX_0FE3
) },
8608 { PREFIX_TABLE (PREFIX_VEX_0FE4
) },
8609 { PREFIX_TABLE (PREFIX_VEX_0FE5
) },
8610 { PREFIX_TABLE (PREFIX_VEX_0FE6
) },
8611 { PREFIX_TABLE (PREFIX_VEX_0FE7
) },
8613 { PREFIX_TABLE (PREFIX_VEX_0FE8
) },
8614 { PREFIX_TABLE (PREFIX_VEX_0FE9
) },
8615 { PREFIX_TABLE (PREFIX_VEX_0FEA
) },
8616 { PREFIX_TABLE (PREFIX_VEX_0FEB
) },
8617 { PREFIX_TABLE (PREFIX_VEX_0FEC
) },
8618 { PREFIX_TABLE (PREFIX_VEX_0FED
) },
8619 { PREFIX_TABLE (PREFIX_VEX_0FEE
) },
8620 { PREFIX_TABLE (PREFIX_VEX_0FEF
) },
8622 { PREFIX_TABLE (PREFIX_VEX_0FF0
) },
8623 { PREFIX_TABLE (PREFIX_VEX_0FF1
) },
8624 { PREFIX_TABLE (PREFIX_VEX_0FF2
) },
8625 { PREFIX_TABLE (PREFIX_VEX_0FF3
) },
8626 { PREFIX_TABLE (PREFIX_VEX_0FF4
) },
8627 { PREFIX_TABLE (PREFIX_VEX_0FF5
) },
8628 { PREFIX_TABLE (PREFIX_VEX_0FF6
) },
8629 { PREFIX_TABLE (PREFIX_VEX_0FF7
) },
8631 { PREFIX_TABLE (PREFIX_VEX_0FF8
) },
8632 { PREFIX_TABLE (PREFIX_VEX_0FF9
) },
8633 { PREFIX_TABLE (PREFIX_VEX_0FFA
) },
8634 { PREFIX_TABLE (PREFIX_VEX_0FFB
) },
8635 { PREFIX_TABLE (PREFIX_VEX_0FFC
) },
8636 { PREFIX_TABLE (PREFIX_VEX_0FFD
) },
8637 { PREFIX_TABLE (PREFIX_VEX_0FFE
) },
8643 { PREFIX_TABLE (PREFIX_VEX_0F3800
) },
8644 { PREFIX_TABLE (PREFIX_VEX_0F3801
) },
8645 { PREFIX_TABLE (PREFIX_VEX_0F3802
) },
8646 { PREFIX_TABLE (PREFIX_VEX_0F3803
) },
8647 { PREFIX_TABLE (PREFIX_VEX_0F3804
) },
8648 { PREFIX_TABLE (PREFIX_VEX_0F3805
) },
8649 { PREFIX_TABLE (PREFIX_VEX_0F3806
) },
8650 { PREFIX_TABLE (PREFIX_VEX_0F3807
) },
8652 { PREFIX_TABLE (PREFIX_VEX_0F3808
) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F3809
) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F380A
) },
8655 { PREFIX_TABLE (PREFIX_VEX_0F380B
) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F380C
) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F380D
) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F380E
) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F380F
) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F3813
) },
8667 { PREFIX_TABLE (PREFIX_VEX_0F3816
) },
8668 { PREFIX_TABLE (PREFIX_VEX_0F3817
) },
8670 { PREFIX_TABLE (PREFIX_VEX_0F3818
) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F3819
) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F381A
) },
8674 { PREFIX_TABLE (PREFIX_VEX_0F381C
) },
8675 { PREFIX_TABLE (PREFIX_VEX_0F381D
) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F381E
) },
8679 { PREFIX_TABLE (PREFIX_VEX_0F3820
) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F3821
) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F3822
) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F3823
) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F3824
) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F3825
) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F3828
) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F3829
) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F382A
) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F382B
) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F382C
) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F382D
) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F382E
) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F382F
) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F3830
) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F3831
) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F3832
) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F3833
) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F3834
) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F3835
) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F3836
) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F3837
) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F3838
) },
8707 { PREFIX_TABLE (PREFIX_VEX_0F3839
) },
8708 { PREFIX_TABLE (PREFIX_VEX_0F383A
) },
8709 { PREFIX_TABLE (PREFIX_VEX_0F383B
) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F383C
) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F383D
) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F383E
) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F383F
) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F3840
) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F3841
) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F3845
) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F3846
) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F3847
) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F3858
) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F3859
) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F385A
) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F3878
) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F3879
) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F388C
) },
8802 { PREFIX_TABLE (PREFIX_VEX_0F388E
) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3890
) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3891
) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3892
) },
8808 { PREFIX_TABLE (PREFIX_VEX_0F3893
) },
8811 { PREFIX_TABLE (PREFIX_VEX_0F3896
) },
8812 { PREFIX_TABLE (PREFIX_VEX_0F3897
) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F3898
) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F3899
) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F389A
) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F389B
) },
8818 { PREFIX_TABLE (PREFIX_VEX_0F389C
) },
8819 { PREFIX_TABLE (PREFIX_VEX_0F389D
) },
8820 { PREFIX_TABLE (PREFIX_VEX_0F389E
) },
8821 { PREFIX_TABLE (PREFIX_VEX_0F389F
) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F38A6
) },
8830 { PREFIX_TABLE (PREFIX_VEX_0F38A7
) },
8832 { PREFIX_TABLE (PREFIX_VEX_0F38A8
) },
8833 { PREFIX_TABLE (PREFIX_VEX_0F38A9
) },
8834 { PREFIX_TABLE (PREFIX_VEX_0F38AA
) },
8835 { PREFIX_TABLE (PREFIX_VEX_0F38AB
) },
8836 { PREFIX_TABLE (PREFIX_VEX_0F38AC
) },
8837 { PREFIX_TABLE (PREFIX_VEX_0F38AD
) },
8838 { PREFIX_TABLE (PREFIX_VEX_0F38AE
) },
8839 { PREFIX_TABLE (PREFIX_VEX_0F38AF
) },
8847 { PREFIX_TABLE (PREFIX_VEX_0F38B6
) },
8848 { PREFIX_TABLE (PREFIX_VEX_0F38B7
) },
8850 { PREFIX_TABLE (PREFIX_VEX_0F38B8
) },
8851 { PREFIX_TABLE (PREFIX_VEX_0F38B9
) },
8852 { PREFIX_TABLE (PREFIX_VEX_0F38BA
) },
8853 { PREFIX_TABLE (PREFIX_VEX_0F38BB
) },
8854 { PREFIX_TABLE (PREFIX_VEX_0F38BC
) },
8855 { PREFIX_TABLE (PREFIX_VEX_0F38BD
) },
8856 { PREFIX_TABLE (PREFIX_VEX_0F38BE
) },
8857 { PREFIX_TABLE (PREFIX_VEX_0F38BF
) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F38DB
) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F38DC
) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F38DD
) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F38DE
) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F38DF
) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38F2
) },
8916 { REG_TABLE (REG_VEX_0F38F3
) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38F5
) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38F6
) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38F7
) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3A00
) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3A01
) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F3A02
) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3A04
) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3A05
) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3A06
) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3A08
) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3A09
) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3A0A
) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3A0B
) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3A0C
) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3A0D
) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3A0E
) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3A0F
) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3A14
) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3A15
) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3A16
) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3A17
) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3A18
) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3A19
) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F3A1D
) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3A20
) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3A21
) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F3A22
) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3A30
) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F3A32
) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3A38
) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3A39
) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3A40
) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3A41
) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F3A42
) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F3A44
) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F3A46
) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3A48
) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3A49
) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A4A
) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A4B
) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A4C
) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3A5C
) },
9038 { PREFIX_TABLE (PREFIX_VEX_0F3A5D
) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A5E
) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A5F
) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A60
) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A61
) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A62
) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A63
) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A68
) },
9052 { PREFIX_TABLE (PREFIX_VEX_0F3A69
) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A6A
) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A6B
) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A6C
) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A6D
) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A6E
) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F3A6F
) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3A78
) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3A79
) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A7A
) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A7B
) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A7C
) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A7D
) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A7E
) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A7F
) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3ADF
) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3AF0
) },
9224 #define NEED_OPCODE_TABLE
9225 #include "i386-dis-evex.h"
9226 #undef NEED_OPCODE_TABLE
9227 static const struct dis386 vex_len_table
[][2] = {
9228 /* VEX_LEN_0F10_P_1 */
9230 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9231 { VEX_W_TABLE (VEX_W_0F10_P_1
) },
9234 /* VEX_LEN_0F10_P_3 */
9236 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9237 { VEX_W_TABLE (VEX_W_0F10_P_3
) },
9240 /* VEX_LEN_0F11_P_1 */
9242 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9243 { VEX_W_TABLE (VEX_W_0F11_P_1
) },
9246 /* VEX_LEN_0F11_P_3 */
9248 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9249 { VEX_W_TABLE (VEX_W_0F11_P_3
) },
9252 /* VEX_LEN_0F12_P_0_M_0 */
9254 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0
) },
9257 /* VEX_LEN_0F12_P_0_M_1 */
9259 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1
) },
9262 /* VEX_LEN_0F12_P_2 */
9264 { VEX_W_TABLE (VEX_W_0F12_P_2
) },
9267 /* VEX_LEN_0F13_M_0 */
9269 { VEX_W_TABLE (VEX_W_0F13_M_0
) },
9272 /* VEX_LEN_0F16_P_0_M_0 */
9274 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0
) },
9277 /* VEX_LEN_0F16_P_0_M_1 */
9279 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1
) },
9282 /* VEX_LEN_0F16_P_2 */
9284 { VEX_W_TABLE (VEX_W_0F16_P_2
) },
9287 /* VEX_LEN_0F17_M_0 */
9289 { VEX_W_TABLE (VEX_W_0F17_M_0
) },
9292 /* VEX_LEN_0F2A_P_1 */
9294 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9295 { "vcvtsi2ss%LQ", { XMScalar
, VexScalar
, Ev
} },
9298 /* VEX_LEN_0F2A_P_3 */
9300 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9301 { "vcvtsi2sd%LQ", { XMScalar
, VexScalar
, Ev
} },
9304 /* VEX_LEN_0F2C_P_1 */
9306 { "vcvttss2siY", { Gv
, EXdScalar
} },
9307 { "vcvttss2siY", { Gv
, EXdScalar
} },
9310 /* VEX_LEN_0F2C_P_3 */
9312 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9313 { "vcvttsd2siY", { Gv
, EXqScalar
} },
9316 /* VEX_LEN_0F2D_P_1 */
9318 { "vcvtss2siY", { Gv
, EXdScalar
} },
9319 { "vcvtss2siY", { Gv
, EXdScalar
} },
9322 /* VEX_LEN_0F2D_P_3 */
9324 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9325 { "vcvtsd2siY", { Gv
, EXqScalar
} },
9328 /* VEX_LEN_0F2E_P_0 */
9330 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9331 { VEX_W_TABLE (VEX_W_0F2E_P_0
) },
9334 /* VEX_LEN_0F2E_P_2 */
9336 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9337 { VEX_W_TABLE (VEX_W_0F2E_P_2
) },
9340 /* VEX_LEN_0F2F_P_0 */
9342 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9343 { VEX_W_TABLE (VEX_W_0F2F_P_0
) },
9346 /* VEX_LEN_0F2F_P_2 */
9348 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9349 { VEX_W_TABLE (VEX_W_0F2F_P_2
) },
9352 /* VEX_LEN_0F41_P_0 */
9355 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1
) },
9357 /* VEX_LEN_0F42_P_0 */
9360 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1
) },
9362 /* VEX_LEN_0F44_P_0 */
9364 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0
) },
9366 /* VEX_LEN_0F45_P_0 */
9369 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1
) },
9371 /* VEX_LEN_0F46_P_0 */
9374 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1
) },
9376 /* VEX_LEN_0F47_P_0 */
9379 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1
) },
9381 /* VEX_LEN_0F4B_P_2 */
9384 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1
) },
9387 /* VEX_LEN_0F51_P_1 */
9389 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9390 { VEX_W_TABLE (VEX_W_0F51_P_1
) },
9393 /* VEX_LEN_0F51_P_3 */
9395 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9396 { VEX_W_TABLE (VEX_W_0F51_P_3
) },
9399 /* VEX_LEN_0F52_P_1 */
9401 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9402 { VEX_W_TABLE (VEX_W_0F52_P_1
) },
9405 /* VEX_LEN_0F53_P_1 */
9407 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9408 { VEX_W_TABLE (VEX_W_0F53_P_1
) },
9411 /* VEX_LEN_0F58_P_1 */
9413 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9414 { VEX_W_TABLE (VEX_W_0F58_P_1
) },
9417 /* VEX_LEN_0F58_P_3 */
9419 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9420 { VEX_W_TABLE (VEX_W_0F58_P_3
) },
9423 /* VEX_LEN_0F59_P_1 */
9425 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9426 { VEX_W_TABLE (VEX_W_0F59_P_1
) },
9429 /* VEX_LEN_0F59_P_3 */
9431 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9432 { VEX_W_TABLE (VEX_W_0F59_P_3
) },
9435 /* VEX_LEN_0F5A_P_1 */
9437 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9438 { VEX_W_TABLE (VEX_W_0F5A_P_1
) },
9441 /* VEX_LEN_0F5A_P_3 */
9443 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9444 { VEX_W_TABLE (VEX_W_0F5A_P_3
) },
9447 /* VEX_LEN_0F5C_P_1 */
9449 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9450 { VEX_W_TABLE (VEX_W_0F5C_P_1
) },
9453 /* VEX_LEN_0F5C_P_3 */
9455 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9456 { VEX_W_TABLE (VEX_W_0F5C_P_3
) },
9459 /* VEX_LEN_0F5D_P_1 */
9461 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9462 { VEX_W_TABLE (VEX_W_0F5D_P_1
) },
9465 /* VEX_LEN_0F5D_P_3 */
9467 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9468 { VEX_W_TABLE (VEX_W_0F5D_P_3
) },
9471 /* VEX_LEN_0F5E_P_1 */
9473 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9474 { VEX_W_TABLE (VEX_W_0F5E_P_1
) },
9477 /* VEX_LEN_0F5E_P_3 */
9479 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9480 { VEX_W_TABLE (VEX_W_0F5E_P_3
) },
9483 /* VEX_LEN_0F5F_P_1 */
9485 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9486 { VEX_W_TABLE (VEX_W_0F5F_P_1
) },
9489 /* VEX_LEN_0F5F_P_3 */
9491 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9492 { VEX_W_TABLE (VEX_W_0F5F_P_3
) },
9495 /* VEX_LEN_0F6E_P_2 */
9497 { "vmovK", { XMScalar
, Edq
} },
9498 { "vmovK", { XMScalar
, Edq
} },
9501 /* VEX_LEN_0F7E_P_1 */
9503 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9504 { VEX_W_TABLE (VEX_W_0F7E_P_1
) },
9507 /* VEX_LEN_0F7E_P_2 */
9509 { "vmovK", { Edq
, XMScalar
} },
9510 { "vmovK", { Edq
, XMScalar
} },
9513 /* VEX_LEN_0F90_P_0 */
9515 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0
) },
9518 /* VEX_LEN_0F91_P_0 */
9520 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0
) },
9523 /* VEX_LEN_0F92_P_0 */
9525 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0
) },
9528 /* VEX_LEN_0F93_P_0 */
9530 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0
) },
9533 /* VEX_LEN_0F98_P_0 */
9535 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0
) },
9538 /* VEX_LEN_0FAE_R_2_M_0 */
9540 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0
) },
9543 /* VEX_LEN_0FAE_R_3_M_0 */
9545 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0
) },
9548 /* VEX_LEN_0FC2_P_1 */
9550 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9551 { VEX_W_TABLE (VEX_W_0FC2_P_1
) },
9554 /* VEX_LEN_0FC2_P_3 */
9556 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9557 { VEX_W_TABLE (VEX_W_0FC2_P_3
) },
9560 /* VEX_LEN_0FC4_P_2 */
9562 { VEX_W_TABLE (VEX_W_0FC4_P_2
) },
9565 /* VEX_LEN_0FC5_P_2 */
9567 { VEX_W_TABLE (VEX_W_0FC5_P_2
) },
9570 /* VEX_LEN_0FD6_P_2 */
9572 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9573 { VEX_W_TABLE (VEX_W_0FD6_P_2
) },
9576 /* VEX_LEN_0FF7_P_2 */
9578 { VEX_W_TABLE (VEX_W_0FF7_P_2
) },
9581 /* VEX_LEN_0F3816_P_2 */
9584 { VEX_W_TABLE (VEX_W_0F3816_P_2
) },
9587 /* VEX_LEN_0F3819_P_2 */
9590 { VEX_W_TABLE (VEX_W_0F3819_P_2
) },
9593 /* VEX_LEN_0F381A_P_2_M_0 */
9596 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0
) },
9599 /* VEX_LEN_0F3836_P_2 */
9602 { VEX_W_TABLE (VEX_W_0F3836_P_2
) },
9605 /* VEX_LEN_0F3841_P_2 */
9607 { VEX_W_TABLE (VEX_W_0F3841_P_2
) },
9610 /* VEX_LEN_0F385A_P_2_M_0 */
9613 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0
) },
9616 /* VEX_LEN_0F38DB_P_2 */
9618 { VEX_W_TABLE (VEX_W_0F38DB_P_2
) },
9621 /* VEX_LEN_0F38DC_P_2 */
9623 { VEX_W_TABLE (VEX_W_0F38DC_P_2
) },
9626 /* VEX_LEN_0F38DD_P_2 */
9628 { VEX_W_TABLE (VEX_W_0F38DD_P_2
) },
9631 /* VEX_LEN_0F38DE_P_2 */
9633 { VEX_W_TABLE (VEX_W_0F38DE_P_2
) },
9636 /* VEX_LEN_0F38DF_P_2 */
9638 { VEX_W_TABLE (VEX_W_0F38DF_P_2
) },
9641 /* VEX_LEN_0F38F2_P_0 */
9643 { "andnS", { Gdq
, VexGdq
, Edq
} },
9646 /* VEX_LEN_0F38F3_R_1_P_0 */
9648 { "blsrS", { VexGdq
, Edq
} },
9651 /* VEX_LEN_0F38F3_R_2_P_0 */
9653 { "blsmskS", { VexGdq
, Edq
} },
9656 /* VEX_LEN_0F38F3_R_3_P_0 */
9658 { "blsiS", { VexGdq
, Edq
} },
9661 /* VEX_LEN_0F38F5_P_0 */
9663 { "bzhiS", { Gdq
, Edq
, VexGdq
} },
9666 /* VEX_LEN_0F38F5_P_1 */
9668 { "pextS", { Gdq
, VexGdq
, Edq
} },
9671 /* VEX_LEN_0F38F5_P_3 */
9673 { "pdepS", { Gdq
, VexGdq
, Edq
} },
9676 /* VEX_LEN_0F38F6_P_3 */
9678 { "mulxS", { Gdq
, VexGdq
, Edq
} },
9681 /* VEX_LEN_0F38F7_P_0 */
9683 { "bextrS", { Gdq
, Edq
, VexGdq
} },
9686 /* VEX_LEN_0F38F7_P_1 */
9688 { "sarxS", { Gdq
, Edq
, VexGdq
} },
9691 /* VEX_LEN_0F38F7_P_2 */
9693 { "shlxS", { Gdq
, Edq
, VexGdq
} },
9696 /* VEX_LEN_0F38F7_P_3 */
9698 { "shrxS", { Gdq
, Edq
, VexGdq
} },
9701 /* VEX_LEN_0F3A00_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F3A00_P_2
) },
9707 /* VEX_LEN_0F3A01_P_2 */
9710 { VEX_W_TABLE (VEX_W_0F3A01_P_2
) },
9713 /* VEX_LEN_0F3A06_P_2 */
9716 { VEX_W_TABLE (VEX_W_0F3A06_P_2
) },
9719 /* VEX_LEN_0F3A0A_P_2 */
9721 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9722 { VEX_W_TABLE (VEX_W_0F3A0A_P_2
) },
9725 /* VEX_LEN_0F3A0B_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9728 { VEX_W_TABLE (VEX_W_0F3A0B_P_2
) },
9731 /* VEX_LEN_0F3A14_P_2 */
9733 { VEX_W_TABLE (VEX_W_0F3A14_P_2
) },
9736 /* VEX_LEN_0F3A15_P_2 */
9738 { VEX_W_TABLE (VEX_W_0F3A15_P_2
) },
9741 /* VEX_LEN_0F3A16_P_2 */
9743 { "vpextrK", { Edq
, XM
, Ib
} },
9746 /* VEX_LEN_0F3A17_P_2 */
9748 { "vextractps", { Edqd
, XM
, Ib
} },
9751 /* VEX_LEN_0F3A18_P_2 */
9754 { VEX_W_TABLE (VEX_W_0F3A18_P_2
) },
9757 /* VEX_LEN_0F3A19_P_2 */
9760 { VEX_W_TABLE (VEX_W_0F3A19_P_2
) },
9763 /* VEX_LEN_0F3A20_P_2 */
9765 { VEX_W_TABLE (VEX_W_0F3A20_P_2
) },
9768 /* VEX_LEN_0F3A21_P_2 */
9770 { VEX_W_TABLE (VEX_W_0F3A21_P_2
) },
9773 /* VEX_LEN_0F3A22_P_2 */
9775 { "vpinsrK", { XM
, Vex128
, Edq
, Ib
} },
9778 /* VEX_LEN_0F3A30_P_2 */
9780 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0
) },
9783 /* VEX_LEN_0F3A32_P_2 */
9785 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0
) },
9788 /* VEX_LEN_0F3A38_P_2 */
9791 { VEX_W_TABLE (VEX_W_0F3A38_P_2
) },
9794 /* VEX_LEN_0F3A39_P_2 */
9797 { VEX_W_TABLE (VEX_W_0F3A39_P_2
) },
9800 /* VEX_LEN_0F3A41_P_2 */
9802 { VEX_W_TABLE (VEX_W_0F3A41_P_2
) },
9805 /* VEX_LEN_0F3A44_P_2 */
9807 { VEX_W_TABLE (VEX_W_0F3A44_P_2
) },
9810 /* VEX_LEN_0F3A46_P_2 */
9813 { VEX_W_TABLE (VEX_W_0F3A46_P_2
) },
9816 /* VEX_LEN_0F3A60_P_2 */
9818 { VEX_W_TABLE (VEX_W_0F3A60_P_2
) },
9821 /* VEX_LEN_0F3A61_P_2 */
9823 { VEX_W_TABLE (VEX_W_0F3A61_P_2
) },
9826 /* VEX_LEN_0F3A62_P_2 */
9828 { VEX_W_TABLE (VEX_W_0F3A62_P_2
) },
9831 /* VEX_LEN_0F3A63_P_2 */
9833 { VEX_W_TABLE (VEX_W_0F3A63_P_2
) },
9836 /* VEX_LEN_0F3A6A_P_2 */
9838 { "vfmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9841 /* VEX_LEN_0F3A6B_P_2 */
9843 { "vfmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9846 /* VEX_LEN_0F3A6E_P_2 */
9848 { "vfmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9851 /* VEX_LEN_0F3A6F_P_2 */
9853 { "vfmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9856 /* VEX_LEN_0F3A7A_P_2 */
9858 { "vfnmaddss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9861 /* VEX_LEN_0F3A7B_P_2 */
9863 { "vfnmaddsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9866 /* VEX_LEN_0F3A7E_P_2 */
9868 { "vfnmsubss", { XMVexW
, Vex128
, EXdVexW
, EXdVexW
, VexI4
} },
9871 /* VEX_LEN_0F3A7F_P_2 */
9873 { "vfnmsubsd", { XMVexW
, Vex128
, EXqVexW
, EXqVexW
, VexI4
} },
9876 /* VEX_LEN_0F3ADF_P_2 */
9878 { VEX_W_TABLE (VEX_W_0F3ADF_P_2
) },
9881 /* VEX_LEN_0F3AF0_P_3 */
9883 { "rorxS", { Gdq
, Edq
, Ib
} },
9886 /* VEX_LEN_0FXOP_08_CC */
9888 { "vpcomb", { XM
, Vex128
, EXx
, Ib
} },
9891 /* VEX_LEN_0FXOP_08_CD */
9893 { "vpcomw", { XM
, Vex128
, EXx
, Ib
} },
9896 /* VEX_LEN_0FXOP_08_CE */
9898 { "vpcomd", { XM
, Vex128
, EXx
, Ib
} },
9901 /* VEX_LEN_0FXOP_08_CF */
9903 { "vpcomq", { XM
, Vex128
, EXx
, Ib
} },
9906 /* VEX_LEN_0FXOP_08_EC */
9908 { "vpcomub", { XM
, Vex128
, EXx
, Ib
} },
9911 /* VEX_LEN_0FXOP_08_ED */
9913 { "vpcomuw", { XM
, Vex128
, EXx
, Ib
} },
9916 /* VEX_LEN_0FXOP_08_EE */
9918 { "vpcomud", { XM
, Vex128
, EXx
, Ib
} },
9921 /* VEX_LEN_0FXOP_08_EF */
9923 { "vpcomuq", { XM
, Vex128
, EXx
, Ib
} },
9926 /* VEX_LEN_0FXOP_09_80 */
9928 { "vfrczps", { XM
, EXxmm
} },
9929 { "vfrczps", { XM
, EXymmq
} },
9932 /* VEX_LEN_0FXOP_09_81 */
9934 { "vfrczpd", { XM
, EXxmm
} },
9935 { "vfrczpd", { XM
, EXymmq
} },
9939 static const struct dis386 vex_w_table
[][2] = {
9941 /* VEX_W_0F10_P_0 */
9942 { "vmovups", { XM
, EXx
} },
9945 /* VEX_W_0F10_P_1 */
9946 { "vmovss", { XMVexScalar
, VexScalar
, EXdScalar
} },
9949 /* VEX_W_0F10_P_2 */
9950 { "vmovupd", { XM
, EXx
} },
9953 /* VEX_W_0F10_P_3 */
9954 { "vmovsd", { XMVexScalar
, VexScalar
, EXqScalar
} },
9957 /* VEX_W_0F11_P_0 */
9958 { "vmovups", { EXxS
, XM
} },
9961 /* VEX_W_0F11_P_1 */
9962 { "vmovss", { EXdVexScalarS
, VexScalar
, XMScalar
} },
9965 /* VEX_W_0F11_P_2 */
9966 { "vmovupd", { EXxS
, XM
} },
9969 /* VEX_W_0F11_P_3 */
9970 { "vmovsd", { EXqVexScalarS
, VexScalar
, XMScalar
} },
9973 /* VEX_W_0F12_P_0_M_0 */
9974 { "vmovlps", { XM
, Vex128
, EXq
} },
9977 /* VEX_W_0F12_P_0_M_1 */
9978 { "vmovhlps", { XM
, Vex128
, EXq
} },
9981 /* VEX_W_0F12_P_1 */
9982 { "vmovsldup", { XM
, EXx
} },
9985 /* VEX_W_0F12_P_2 */
9986 { "vmovlpd", { XM
, Vex128
, EXq
} },
9989 /* VEX_W_0F12_P_3 */
9990 { "vmovddup", { XM
, EXymmq
} },
9993 /* VEX_W_0F13_M_0 */
9994 { "vmovlpX", { EXq
, XM
} },
9998 { "vunpcklpX", { XM
, Vex
, EXx
} },
10002 { "vunpckhpX", { XM
, Vex
, EXx
} },
10005 /* VEX_W_0F16_P_0_M_0 */
10006 { "vmovhps", { XM
, Vex128
, EXq
} },
10009 /* VEX_W_0F16_P_0_M_1 */
10010 { "vmovlhps", { XM
, Vex128
, EXq
} },
10013 /* VEX_W_0F16_P_1 */
10014 { "vmovshdup", { XM
, EXx
} },
10017 /* VEX_W_0F16_P_2 */
10018 { "vmovhpd", { XM
, Vex128
, EXq
} },
10021 /* VEX_W_0F17_M_0 */
10022 { "vmovhpX", { EXq
, XM
} },
10026 { "vmovapX", { XM
, EXx
} },
10030 { "vmovapX", { EXxS
, XM
} },
10033 /* VEX_W_0F2B_M_0 */
10034 { "vmovntpX", { Mx
, XM
} },
10037 /* VEX_W_0F2E_P_0 */
10038 { "vucomiss", { XMScalar
, EXdScalar
} },
10041 /* VEX_W_0F2E_P_2 */
10042 { "vucomisd", { XMScalar
, EXqScalar
} },
10045 /* VEX_W_0F2F_P_0 */
10046 { "vcomiss", { XMScalar
, EXdScalar
} },
10049 /* VEX_W_0F2F_P_2 */
10050 { "vcomisd", { XMScalar
, EXqScalar
} },
10053 /* VEX_W_0F41_P_0_LEN_1 */
10054 { "kandw", { MaskG
, MaskVex
, MaskR
} },
10057 /* VEX_W_0F42_P_0_LEN_1 */
10058 { "kandnw", { MaskG
, MaskVex
, MaskR
} },
10061 /* VEX_W_0F44_P_0_LEN_0 */
10062 { "knotw", { MaskG
, MaskR
} },
10065 /* VEX_W_0F45_P_0_LEN_1 */
10066 { "korw", { MaskG
, MaskVex
, MaskR
} },
10069 /* VEX_W_0F46_P_0_LEN_1 */
10070 { "kxnorw", { MaskG
, MaskVex
, MaskR
} },
10073 /* VEX_W_0F47_P_0_LEN_1 */
10074 { "kxorw", { MaskG
, MaskVex
, MaskR
} },
10077 /* VEX_W_0F4B_P_2_LEN_1 */
10078 { "kunpckbw", { MaskG
, MaskVex
, MaskR
} },
10081 /* VEX_W_0F50_M_0 */
10082 { "vmovmskpX", { Gdq
, XS
} },
10085 /* VEX_W_0F51_P_0 */
10086 { "vsqrtps", { XM
, EXx
} },
10089 /* VEX_W_0F51_P_1 */
10090 { "vsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10093 /* VEX_W_0F51_P_2 */
10094 { "vsqrtpd", { XM
, EXx
} },
10097 /* VEX_W_0F51_P_3 */
10098 { "vsqrtsd", { XMScalar
, VexScalar
, EXqScalar
} },
10101 /* VEX_W_0F52_P_0 */
10102 { "vrsqrtps", { XM
, EXx
} },
10105 /* VEX_W_0F52_P_1 */
10106 { "vrsqrtss", { XMScalar
, VexScalar
, EXdScalar
} },
10109 /* VEX_W_0F53_P_0 */
10110 { "vrcpps", { XM
, EXx
} },
10113 /* VEX_W_0F53_P_1 */
10114 { "vrcpss", { XMScalar
, VexScalar
, EXdScalar
} },
10117 /* VEX_W_0F58_P_0 */
10118 { "vaddps", { XM
, Vex
, EXx
} },
10121 /* VEX_W_0F58_P_1 */
10122 { "vaddss", { XMScalar
, VexScalar
, EXdScalar
} },
10125 /* VEX_W_0F58_P_2 */
10126 { "vaddpd", { XM
, Vex
, EXx
} },
10129 /* VEX_W_0F58_P_3 */
10130 { "vaddsd", { XMScalar
, VexScalar
, EXqScalar
} },
10133 /* VEX_W_0F59_P_0 */
10134 { "vmulps", { XM
, Vex
, EXx
} },
10137 /* VEX_W_0F59_P_1 */
10138 { "vmulss", { XMScalar
, VexScalar
, EXdScalar
} },
10141 /* VEX_W_0F59_P_2 */
10142 { "vmulpd", { XM
, Vex
, EXx
} },
10145 /* VEX_W_0F59_P_3 */
10146 { "vmulsd", { XMScalar
, VexScalar
, EXqScalar
} },
10149 /* VEX_W_0F5A_P_0 */
10150 { "vcvtps2pd", { XM
, EXxmmq
} },
10153 /* VEX_W_0F5A_P_1 */
10154 { "vcvtss2sd", { XMScalar
, VexScalar
, EXdScalar
} },
10157 /* VEX_W_0F5A_P_3 */
10158 { "vcvtsd2ss", { XMScalar
, VexScalar
, EXqScalar
} },
10161 /* VEX_W_0F5B_P_0 */
10162 { "vcvtdq2ps", { XM
, EXx
} },
10165 /* VEX_W_0F5B_P_1 */
10166 { "vcvttps2dq", { XM
, EXx
} },
10169 /* VEX_W_0F5B_P_2 */
10170 { "vcvtps2dq", { XM
, EXx
} },
10173 /* VEX_W_0F5C_P_0 */
10174 { "vsubps", { XM
, Vex
, EXx
} },
10177 /* VEX_W_0F5C_P_1 */
10178 { "vsubss", { XMScalar
, VexScalar
, EXdScalar
} },
10181 /* VEX_W_0F5C_P_2 */
10182 { "vsubpd", { XM
, Vex
, EXx
} },
10185 /* VEX_W_0F5C_P_3 */
10186 { "vsubsd", { XMScalar
, VexScalar
, EXqScalar
} },
10189 /* VEX_W_0F5D_P_0 */
10190 { "vminps", { XM
, Vex
, EXx
} },
10193 /* VEX_W_0F5D_P_1 */
10194 { "vminss", { XMScalar
, VexScalar
, EXdScalar
} },
10197 /* VEX_W_0F5D_P_2 */
10198 { "vminpd", { XM
, Vex
, EXx
} },
10201 /* VEX_W_0F5D_P_3 */
10202 { "vminsd", { XMScalar
, VexScalar
, EXqScalar
} },
10205 /* VEX_W_0F5E_P_0 */
10206 { "vdivps", { XM
, Vex
, EXx
} },
10209 /* VEX_W_0F5E_P_1 */
10210 { "vdivss", { XMScalar
, VexScalar
, EXdScalar
} },
10213 /* VEX_W_0F5E_P_2 */
10214 { "vdivpd", { XM
, Vex
, EXx
} },
10217 /* VEX_W_0F5E_P_3 */
10218 { "vdivsd", { XMScalar
, VexScalar
, EXqScalar
} },
10221 /* VEX_W_0F5F_P_0 */
10222 { "vmaxps", { XM
, Vex
, EXx
} },
10225 /* VEX_W_0F5F_P_1 */
10226 { "vmaxss", { XMScalar
, VexScalar
, EXdScalar
} },
10229 /* VEX_W_0F5F_P_2 */
10230 { "vmaxpd", { XM
, Vex
, EXx
} },
10233 /* VEX_W_0F5F_P_3 */
10234 { "vmaxsd", { XMScalar
, VexScalar
, EXqScalar
} },
10237 /* VEX_W_0F60_P_2 */
10238 { "vpunpcklbw", { XM
, Vex
, EXx
} },
10241 /* VEX_W_0F61_P_2 */
10242 { "vpunpcklwd", { XM
, Vex
, EXx
} },
10245 /* VEX_W_0F62_P_2 */
10246 { "vpunpckldq", { XM
, Vex
, EXx
} },
10249 /* VEX_W_0F63_P_2 */
10250 { "vpacksswb", { XM
, Vex
, EXx
} },
10253 /* VEX_W_0F64_P_2 */
10254 { "vpcmpgtb", { XM
, Vex
, EXx
} },
10257 /* VEX_W_0F65_P_2 */
10258 { "vpcmpgtw", { XM
, Vex
, EXx
} },
10261 /* VEX_W_0F66_P_2 */
10262 { "vpcmpgtd", { XM
, Vex
, EXx
} },
10265 /* VEX_W_0F67_P_2 */
10266 { "vpackuswb", { XM
, Vex
, EXx
} },
10269 /* VEX_W_0F68_P_2 */
10270 { "vpunpckhbw", { XM
, Vex
, EXx
} },
10273 /* VEX_W_0F69_P_2 */
10274 { "vpunpckhwd", { XM
, Vex
, EXx
} },
10277 /* VEX_W_0F6A_P_2 */
10278 { "vpunpckhdq", { XM
, Vex
, EXx
} },
10281 /* VEX_W_0F6B_P_2 */
10282 { "vpackssdw", { XM
, Vex
, EXx
} },
10285 /* VEX_W_0F6C_P_2 */
10286 { "vpunpcklqdq", { XM
, Vex
, EXx
} },
10289 /* VEX_W_0F6D_P_2 */
10290 { "vpunpckhqdq", { XM
, Vex
, EXx
} },
10293 /* VEX_W_0F6F_P_1 */
10294 { "vmovdqu", { XM
, EXx
} },
10297 /* VEX_W_0F6F_P_2 */
10298 { "vmovdqa", { XM
, EXx
} },
10301 /* VEX_W_0F70_P_1 */
10302 { "vpshufhw", { XM
, EXx
, Ib
} },
10305 /* VEX_W_0F70_P_2 */
10306 { "vpshufd", { XM
, EXx
, Ib
} },
10309 /* VEX_W_0F70_P_3 */
10310 { "vpshuflw", { XM
, EXx
, Ib
} },
10313 /* VEX_W_0F71_R_2_P_2 */
10314 { "vpsrlw", { Vex
, XS
, Ib
} },
10317 /* VEX_W_0F71_R_4_P_2 */
10318 { "vpsraw", { Vex
, XS
, Ib
} },
10321 /* VEX_W_0F71_R_6_P_2 */
10322 { "vpsllw", { Vex
, XS
, Ib
} },
10325 /* VEX_W_0F72_R_2_P_2 */
10326 { "vpsrld", { Vex
, XS
, Ib
} },
10329 /* VEX_W_0F72_R_4_P_2 */
10330 { "vpsrad", { Vex
, XS
, Ib
} },
10333 /* VEX_W_0F72_R_6_P_2 */
10334 { "vpslld", { Vex
, XS
, Ib
} },
10337 /* VEX_W_0F73_R_2_P_2 */
10338 { "vpsrlq", { Vex
, XS
, Ib
} },
10341 /* VEX_W_0F73_R_3_P_2 */
10342 { "vpsrldq", { Vex
, XS
, Ib
} },
10345 /* VEX_W_0F73_R_6_P_2 */
10346 { "vpsllq", { Vex
, XS
, Ib
} },
10349 /* VEX_W_0F73_R_7_P_2 */
10350 { "vpslldq", { Vex
, XS
, Ib
} },
10353 /* VEX_W_0F74_P_2 */
10354 { "vpcmpeqb", { XM
, Vex
, EXx
} },
10357 /* VEX_W_0F75_P_2 */
10358 { "vpcmpeqw", { XM
, Vex
, EXx
} },
10361 /* VEX_W_0F76_P_2 */
10362 { "vpcmpeqd", { XM
, Vex
, EXx
} },
10365 /* VEX_W_0F77_P_0 */
10369 /* VEX_W_0F7C_P_2 */
10370 { "vhaddpd", { XM
, Vex
, EXx
} },
10373 /* VEX_W_0F7C_P_3 */
10374 { "vhaddps", { XM
, Vex
, EXx
} },
10377 /* VEX_W_0F7D_P_2 */
10378 { "vhsubpd", { XM
, Vex
, EXx
} },
10381 /* VEX_W_0F7D_P_3 */
10382 { "vhsubps", { XM
, Vex
, EXx
} },
10385 /* VEX_W_0F7E_P_1 */
10386 { "vmovq", { XMScalar
, EXqScalar
} },
10389 /* VEX_W_0F7F_P_1 */
10390 { "vmovdqu", { EXxS
, XM
} },
10393 /* VEX_W_0F7F_P_2 */
10394 { "vmovdqa", { EXxS
, XM
} },
10397 /* VEX_W_0F90_P_0_LEN_0 */
10398 { "kmovw", { MaskG
, MaskE
} },
10401 /* VEX_W_0F91_P_0_LEN_0 */
10402 { "kmovw", { Ew
, MaskG
} },
10405 /* VEX_W_0F92_P_0_LEN_0 */
10406 { "kmovw", { MaskG
, Rdq
} },
10409 /* VEX_W_0F93_P_0_LEN_0 */
10410 { "kmovw", { Gdq
, MaskR
} },
10413 /* VEX_W_0F98_P_0_LEN_0 */
10414 { "kortestw", { MaskG
, MaskR
} },
10417 /* VEX_W_0FAE_R_2_M_0 */
10418 { "vldmxcsr", { Md
} },
10421 /* VEX_W_0FAE_R_3_M_0 */
10422 { "vstmxcsr", { Md
} },
10425 /* VEX_W_0FC2_P_0 */
10426 { "vcmpps", { XM
, Vex
, EXx
, VCMP
} },
10429 /* VEX_W_0FC2_P_1 */
10430 { "vcmpss", { XMScalar
, VexScalar
, EXdScalar
, VCMP
} },
10433 /* VEX_W_0FC2_P_2 */
10434 { "vcmppd", { XM
, Vex
, EXx
, VCMP
} },
10437 /* VEX_W_0FC2_P_3 */
10438 { "vcmpsd", { XMScalar
, VexScalar
, EXqScalar
, VCMP
} },
10441 /* VEX_W_0FC4_P_2 */
10442 { "vpinsrw", { XM
, Vex128
, Edqw
, Ib
} },
10445 /* VEX_W_0FC5_P_2 */
10446 { "vpextrw", { Gdq
, XS
, Ib
} },
10449 /* VEX_W_0FD0_P_2 */
10450 { "vaddsubpd", { XM
, Vex
, EXx
} },
10453 /* VEX_W_0FD0_P_3 */
10454 { "vaddsubps", { XM
, Vex
, EXx
} },
10457 /* VEX_W_0FD1_P_2 */
10458 { "vpsrlw", { XM
, Vex
, EXxmm
} },
10461 /* VEX_W_0FD2_P_2 */
10462 { "vpsrld", { XM
, Vex
, EXxmm
} },
10465 /* VEX_W_0FD3_P_2 */
10466 { "vpsrlq", { XM
, Vex
, EXxmm
} },
10469 /* VEX_W_0FD4_P_2 */
10470 { "vpaddq", { XM
, Vex
, EXx
} },
10473 /* VEX_W_0FD5_P_2 */
10474 { "vpmullw", { XM
, Vex
, EXx
} },
10477 /* VEX_W_0FD6_P_2 */
10478 { "vmovq", { EXqScalarS
, XMScalar
} },
10481 /* VEX_W_0FD7_P_2_M_1 */
10482 { "vpmovmskb", { Gdq
, XS
} },
10485 /* VEX_W_0FD8_P_2 */
10486 { "vpsubusb", { XM
, Vex
, EXx
} },
10489 /* VEX_W_0FD9_P_2 */
10490 { "vpsubusw", { XM
, Vex
, EXx
} },
10493 /* VEX_W_0FDA_P_2 */
10494 { "vpminub", { XM
, Vex
, EXx
} },
10497 /* VEX_W_0FDB_P_2 */
10498 { "vpand", { XM
, Vex
, EXx
} },
10501 /* VEX_W_0FDC_P_2 */
10502 { "vpaddusb", { XM
, Vex
, EXx
} },
10505 /* VEX_W_0FDD_P_2 */
10506 { "vpaddusw", { XM
, Vex
, EXx
} },
10509 /* VEX_W_0FDE_P_2 */
10510 { "vpmaxub", { XM
, Vex
, EXx
} },
10513 /* VEX_W_0FDF_P_2 */
10514 { "vpandn", { XM
, Vex
, EXx
} },
10517 /* VEX_W_0FE0_P_2 */
10518 { "vpavgb", { XM
, Vex
, EXx
} },
10521 /* VEX_W_0FE1_P_2 */
10522 { "vpsraw", { XM
, Vex
, EXxmm
} },
10525 /* VEX_W_0FE2_P_2 */
10526 { "vpsrad", { XM
, Vex
, EXxmm
} },
10529 /* VEX_W_0FE3_P_2 */
10530 { "vpavgw", { XM
, Vex
, EXx
} },
10533 /* VEX_W_0FE4_P_2 */
10534 { "vpmulhuw", { XM
, Vex
, EXx
} },
10537 /* VEX_W_0FE5_P_2 */
10538 { "vpmulhw", { XM
, Vex
, EXx
} },
10541 /* VEX_W_0FE6_P_1 */
10542 { "vcvtdq2pd", { XM
, EXxmmq
} },
10545 /* VEX_W_0FE6_P_2 */
10546 { "vcvttpd2dq%XY", { XMM
, EXx
} },
10549 /* VEX_W_0FE6_P_3 */
10550 { "vcvtpd2dq%XY", { XMM
, EXx
} },
10553 /* VEX_W_0FE7_P_2_M_0 */
10554 { "vmovntdq", { Mx
, XM
} },
10557 /* VEX_W_0FE8_P_2 */
10558 { "vpsubsb", { XM
, Vex
, EXx
} },
10561 /* VEX_W_0FE9_P_2 */
10562 { "vpsubsw", { XM
, Vex
, EXx
} },
10565 /* VEX_W_0FEA_P_2 */
10566 { "vpminsw", { XM
, Vex
, EXx
} },
10569 /* VEX_W_0FEB_P_2 */
10570 { "vpor", { XM
, Vex
, EXx
} },
10573 /* VEX_W_0FEC_P_2 */
10574 { "vpaddsb", { XM
, Vex
, EXx
} },
10577 /* VEX_W_0FED_P_2 */
10578 { "vpaddsw", { XM
, Vex
, EXx
} },
10581 /* VEX_W_0FEE_P_2 */
10582 { "vpmaxsw", { XM
, Vex
, EXx
} },
10585 /* VEX_W_0FEF_P_2 */
10586 { "vpxor", { XM
, Vex
, EXx
} },
10589 /* VEX_W_0FF0_P_3_M_0 */
10590 { "vlddqu", { XM
, M
} },
10593 /* VEX_W_0FF1_P_2 */
10594 { "vpsllw", { XM
, Vex
, EXxmm
} },
10597 /* VEX_W_0FF2_P_2 */
10598 { "vpslld", { XM
, Vex
, EXxmm
} },
10601 /* VEX_W_0FF3_P_2 */
10602 { "vpsllq", { XM
, Vex
, EXxmm
} },
10605 /* VEX_W_0FF4_P_2 */
10606 { "vpmuludq", { XM
, Vex
, EXx
} },
10609 /* VEX_W_0FF5_P_2 */
10610 { "vpmaddwd", { XM
, Vex
, EXx
} },
10613 /* VEX_W_0FF6_P_2 */
10614 { "vpsadbw", { XM
, Vex
, EXx
} },
10617 /* VEX_W_0FF7_P_2 */
10618 { "vmaskmovdqu", { XM
, XS
} },
10621 /* VEX_W_0FF8_P_2 */
10622 { "vpsubb", { XM
, Vex
, EXx
} },
10625 /* VEX_W_0FF9_P_2 */
10626 { "vpsubw", { XM
, Vex
, EXx
} },
10629 /* VEX_W_0FFA_P_2 */
10630 { "vpsubd", { XM
, Vex
, EXx
} },
10633 /* VEX_W_0FFB_P_2 */
10634 { "vpsubq", { XM
, Vex
, EXx
} },
10637 /* VEX_W_0FFC_P_2 */
10638 { "vpaddb", { XM
, Vex
, EXx
} },
10641 /* VEX_W_0FFD_P_2 */
10642 { "vpaddw", { XM
, Vex
, EXx
} },
10645 /* VEX_W_0FFE_P_2 */
10646 { "vpaddd", { XM
, Vex
, EXx
} },
10649 /* VEX_W_0F3800_P_2 */
10650 { "vpshufb", { XM
, Vex
, EXx
} },
10653 /* VEX_W_0F3801_P_2 */
10654 { "vphaddw", { XM
, Vex
, EXx
} },
10657 /* VEX_W_0F3802_P_2 */
10658 { "vphaddd", { XM
, Vex
, EXx
} },
10661 /* VEX_W_0F3803_P_2 */
10662 { "vphaddsw", { XM
, Vex
, EXx
} },
10665 /* VEX_W_0F3804_P_2 */
10666 { "vpmaddubsw", { XM
, Vex
, EXx
} },
10669 /* VEX_W_0F3805_P_2 */
10670 { "vphsubw", { XM
, Vex
, EXx
} },
10673 /* VEX_W_0F3806_P_2 */
10674 { "vphsubd", { XM
, Vex
, EXx
} },
10677 /* VEX_W_0F3807_P_2 */
10678 { "vphsubsw", { XM
, Vex
, EXx
} },
10681 /* VEX_W_0F3808_P_2 */
10682 { "vpsignb", { XM
, Vex
, EXx
} },
10685 /* VEX_W_0F3809_P_2 */
10686 { "vpsignw", { XM
, Vex
, EXx
} },
10689 /* VEX_W_0F380A_P_2 */
10690 { "vpsignd", { XM
, Vex
, EXx
} },
10693 /* VEX_W_0F380B_P_2 */
10694 { "vpmulhrsw", { XM
, Vex
, EXx
} },
10697 /* VEX_W_0F380C_P_2 */
10698 { "vpermilps", { XM
, Vex
, EXx
} },
10701 /* VEX_W_0F380D_P_2 */
10702 { "vpermilpd", { XM
, Vex
, EXx
} },
10705 /* VEX_W_0F380E_P_2 */
10706 { "vtestps", { XM
, EXx
} },
10709 /* VEX_W_0F380F_P_2 */
10710 { "vtestpd", { XM
, EXx
} },
10713 /* VEX_W_0F3816_P_2 */
10714 { "vpermps", { XM
, Vex
, EXx
} },
10717 /* VEX_W_0F3817_P_2 */
10718 { "vptest", { XM
, EXx
} },
10721 /* VEX_W_0F3818_P_2 */
10722 { "vbroadcastss", { XM
, EXxmm_md
} },
10725 /* VEX_W_0F3819_P_2 */
10726 { "vbroadcastsd", { XM
, EXxmm_mq
} },
10729 /* VEX_W_0F381A_P_2_M_0 */
10730 { "vbroadcastf128", { XM
, Mxmm
} },
10733 /* VEX_W_0F381C_P_2 */
10734 { "vpabsb", { XM
, EXx
} },
10737 /* VEX_W_0F381D_P_2 */
10738 { "vpabsw", { XM
, EXx
} },
10741 /* VEX_W_0F381E_P_2 */
10742 { "vpabsd", { XM
, EXx
} },
10745 /* VEX_W_0F3820_P_2 */
10746 { "vpmovsxbw", { XM
, EXxmmq
} },
10749 /* VEX_W_0F3821_P_2 */
10750 { "vpmovsxbd", { XM
, EXxmmqd
} },
10753 /* VEX_W_0F3822_P_2 */
10754 { "vpmovsxbq", { XM
, EXxmmdw
} },
10757 /* VEX_W_0F3823_P_2 */
10758 { "vpmovsxwd", { XM
, EXxmmq
} },
10761 /* VEX_W_0F3824_P_2 */
10762 { "vpmovsxwq", { XM
, EXxmmqd
} },
10765 /* VEX_W_0F3825_P_2 */
10766 { "vpmovsxdq", { XM
, EXxmmq
} },
10769 /* VEX_W_0F3828_P_2 */
10770 { "vpmuldq", { XM
, Vex
, EXx
} },
10773 /* VEX_W_0F3829_P_2 */
10774 { "vpcmpeqq", { XM
, Vex
, EXx
} },
10777 /* VEX_W_0F382A_P_2_M_0 */
10778 { "vmovntdqa", { XM
, Mx
} },
10781 /* VEX_W_0F382B_P_2 */
10782 { "vpackusdw", { XM
, Vex
, EXx
} },
10785 /* VEX_W_0F382C_P_2_M_0 */
10786 { "vmaskmovps", { XM
, Vex
, Mx
} },
10789 /* VEX_W_0F382D_P_2_M_0 */
10790 { "vmaskmovpd", { XM
, Vex
, Mx
} },
10793 /* VEX_W_0F382E_P_2_M_0 */
10794 { "vmaskmovps", { Mx
, Vex
, XM
} },
10797 /* VEX_W_0F382F_P_2_M_0 */
10798 { "vmaskmovpd", { Mx
, Vex
, XM
} },
10801 /* VEX_W_0F3830_P_2 */
10802 { "vpmovzxbw", { XM
, EXxmmq
} },
10805 /* VEX_W_0F3831_P_2 */
10806 { "vpmovzxbd", { XM
, EXxmmqd
} },
10809 /* VEX_W_0F3832_P_2 */
10810 { "vpmovzxbq", { XM
, EXxmmdw
} },
10813 /* VEX_W_0F3833_P_2 */
10814 { "vpmovzxwd", { XM
, EXxmmq
} },
10817 /* VEX_W_0F3834_P_2 */
10818 { "vpmovzxwq", { XM
, EXxmmqd
} },
10821 /* VEX_W_0F3835_P_2 */
10822 { "vpmovzxdq", { XM
, EXxmmq
} },
10825 /* VEX_W_0F3836_P_2 */
10826 { "vpermd", { XM
, Vex
, EXx
} },
10829 /* VEX_W_0F3837_P_2 */
10830 { "vpcmpgtq", { XM
, Vex
, EXx
} },
10833 /* VEX_W_0F3838_P_2 */
10834 { "vpminsb", { XM
, Vex
, EXx
} },
10837 /* VEX_W_0F3839_P_2 */
10838 { "vpminsd", { XM
, Vex
, EXx
} },
10841 /* VEX_W_0F383A_P_2 */
10842 { "vpminuw", { XM
, Vex
, EXx
} },
10845 /* VEX_W_0F383B_P_2 */
10846 { "vpminud", { XM
, Vex
, EXx
} },
10849 /* VEX_W_0F383C_P_2 */
10850 { "vpmaxsb", { XM
, Vex
, EXx
} },
10853 /* VEX_W_0F383D_P_2 */
10854 { "vpmaxsd", { XM
, Vex
, EXx
} },
10857 /* VEX_W_0F383E_P_2 */
10858 { "vpmaxuw", { XM
, Vex
, EXx
} },
10861 /* VEX_W_0F383F_P_2 */
10862 { "vpmaxud", { XM
, Vex
, EXx
} },
10865 /* VEX_W_0F3840_P_2 */
10866 { "vpmulld", { XM
, Vex
, EXx
} },
10869 /* VEX_W_0F3841_P_2 */
10870 { "vphminposuw", { XM
, EXx
} },
10873 /* VEX_W_0F3846_P_2 */
10874 { "vpsravd", { XM
, Vex
, EXx
} },
10877 /* VEX_W_0F3858_P_2 */
10878 { "vpbroadcastd", { XM
, EXxmm_md
} },
10881 /* VEX_W_0F3859_P_2 */
10882 { "vpbroadcastq", { XM
, EXxmm_mq
} },
10885 /* VEX_W_0F385A_P_2_M_0 */
10886 { "vbroadcasti128", { XM
, Mxmm
} },
10889 /* VEX_W_0F3878_P_2 */
10890 { "vpbroadcastb", { XM
, EXxmm_mb
} },
10893 /* VEX_W_0F3879_P_2 */
10894 { "vpbroadcastw", { XM
, EXxmm_mw
} },
10897 /* VEX_W_0F38DB_P_2 */
10898 { "vaesimc", { XM
, EXx
} },
10901 /* VEX_W_0F38DC_P_2 */
10902 { "vaesenc", { XM
, Vex128
, EXx
} },
10905 /* VEX_W_0F38DD_P_2 */
10906 { "vaesenclast", { XM
, Vex128
, EXx
} },
10909 /* VEX_W_0F38DE_P_2 */
10910 { "vaesdec", { XM
, Vex128
, EXx
} },
10913 /* VEX_W_0F38DF_P_2 */
10914 { "vaesdeclast", { XM
, Vex128
, EXx
} },
10917 /* VEX_W_0F3A00_P_2 */
10919 { "vpermq", { XM
, EXx
, Ib
} },
10922 /* VEX_W_0F3A01_P_2 */
10924 { "vpermpd", { XM
, EXx
, Ib
} },
10927 /* VEX_W_0F3A02_P_2 */
10928 { "vpblendd", { XM
, Vex
, EXx
, Ib
} },
10931 /* VEX_W_0F3A04_P_2 */
10932 { "vpermilps", { XM
, EXx
, Ib
} },
10935 /* VEX_W_0F3A05_P_2 */
10936 { "vpermilpd", { XM
, EXx
, Ib
} },
10939 /* VEX_W_0F3A06_P_2 */
10940 { "vperm2f128", { XM
, Vex256
, EXx
, Ib
} },
10943 /* VEX_W_0F3A08_P_2 */
10944 { "vroundps", { XM
, EXx
, Ib
} },
10947 /* VEX_W_0F3A09_P_2 */
10948 { "vroundpd", { XM
, EXx
, Ib
} },
10951 /* VEX_W_0F3A0A_P_2 */
10952 { "vroundss", { XMScalar
, VexScalar
, EXdScalar
, Ib
} },
10955 /* VEX_W_0F3A0B_P_2 */
10956 { "vroundsd", { XMScalar
, VexScalar
, EXqScalar
, Ib
} },
10959 /* VEX_W_0F3A0C_P_2 */
10960 { "vblendps", { XM
, Vex
, EXx
, Ib
} },
10963 /* VEX_W_0F3A0D_P_2 */
10964 { "vblendpd", { XM
, Vex
, EXx
, Ib
} },
10967 /* VEX_W_0F3A0E_P_2 */
10968 { "vpblendw", { XM
, Vex
, EXx
, Ib
} },
10971 /* VEX_W_0F3A0F_P_2 */
10972 { "vpalignr", { XM
, Vex
, EXx
, Ib
} },
10975 /* VEX_W_0F3A14_P_2 */
10976 { "vpextrb", { Edqb
, XM
, Ib
} },
10979 /* VEX_W_0F3A15_P_2 */
10980 { "vpextrw", { Edqw
, XM
, Ib
} },
10983 /* VEX_W_0F3A18_P_2 */
10984 { "vinsertf128", { XM
, Vex256
, EXxmm
, Ib
} },
10987 /* VEX_W_0F3A19_P_2 */
10988 { "vextractf128", { EXxmm
, XM
, Ib
} },
10991 /* VEX_W_0F3A20_P_2 */
10992 { "vpinsrb", { XM
, Vex128
, Edqb
, Ib
} },
10995 /* VEX_W_0F3A21_P_2 */
10996 { "vinsertps", { XM
, Vex128
, EXd
, Ib
} },
10999 /* VEX_W_0F3A30_P_2 */
11001 { "kshiftrw", { MaskG
, MaskR
, Ib
} },
11004 /* VEX_W_0F3A32_P_2 */
11006 { "kshiftlw", { MaskG
, MaskR
, Ib
} },
11009 /* VEX_W_0F3A38_P_2 */
11010 { "vinserti128", { XM
, Vex256
, EXxmm
, Ib
} },
11013 /* VEX_W_0F3A39_P_2 */
11014 { "vextracti128", { EXxmm
, XM
, Ib
} },
11017 /* VEX_W_0F3A40_P_2 */
11018 { "vdpps", { XM
, Vex
, EXx
, Ib
} },
11021 /* VEX_W_0F3A41_P_2 */
11022 { "vdppd", { XM
, Vex128
, EXx
, Ib
} },
11025 /* VEX_W_0F3A42_P_2 */
11026 { "vmpsadbw", { XM
, Vex
, EXx
, Ib
} },
11029 /* VEX_W_0F3A44_P_2 */
11030 { "vpclmulqdq", { XM
, Vex128
, EXx
, PCLMUL
} },
11033 /* VEX_W_0F3A46_P_2 */
11034 { "vperm2i128", { XM
, Vex256
, EXx
, Ib
} },
11037 /* VEX_W_0F3A48_P_2 */
11038 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11039 { "vpermil2ps", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11042 /* VEX_W_0F3A49_P_2 */
11043 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11044 { "vpermil2pd", { XMVexW
, Vex
, EXVexImmW
, EXVexImmW
, EXVexImmW
} },
11047 /* VEX_W_0F3A4A_P_2 */
11048 { "vblendvps", { XM
, Vex
, EXx
, XMVexI4
} },
11051 /* VEX_W_0F3A4B_P_2 */
11052 { "vblendvpd", { XM
, Vex
, EXx
, XMVexI4
} },
11055 /* VEX_W_0F3A4C_P_2 */
11056 { "vpblendvb", { XM
, Vex
, EXx
, XMVexI4
} },
11059 /* VEX_W_0F3A60_P_2 */
11060 { "vpcmpestrm", { XM
, EXx
, Ib
} },
11063 /* VEX_W_0F3A61_P_2 */
11064 { "vpcmpestri", { XM
, EXx
, Ib
} },
11067 /* VEX_W_0F3A62_P_2 */
11068 { "vpcmpistrm", { XM
, EXx
, Ib
} },
11071 /* VEX_W_0F3A63_P_2 */
11072 { "vpcmpistri", { XM
, EXx
, Ib
} },
11075 /* VEX_W_0F3ADF_P_2 */
11076 { "vaeskeygenassist", { XM
, EXx
, Ib
} },
11078 #define NEED_VEX_W_TABLE
11079 #include "i386-dis-evex.h"
11080 #undef NEED_VEX_W_TABLE
11083 static const struct dis386 mod_table
[][2] = {
11086 { "leaS", { Gv
, M
} },
11091 { RM_TABLE (RM_C6_REG_7
) },
11096 { RM_TABLE (RM_C7_REG_7
) },
11100 { "Jcall{T|}", { indirEp
} },
11104 { "Jjmp{T|}", { indirEp
} },
11107 /* MOD_0F01_REG_0 */
11108 { X86_64_TABLE (X86_64_0F01_REG_0
) },
11109 { RM_TABLE (RM_0F01_REG_0
) },
11112 /* MOD_0F01_REG_1 */
11113 { X86_64_TABLE (X86_64_0F01_REG_1
) },
11114 { RM_TABLE (RM_0F01_REG_1
) },
11117 /* MOD_0F01_REG_2 */
11118 { X86_64_TABLE (X86_64_0F01_REG_2
) },
11119 { RM_TABLE (RM_0F01_REG_2
) },
11122 /* MOD_0F01_REG_3 */
11123 { X86_64_TABLE (X86_64_0F01_REG_3
) },
11124 { RM_TABLE (RM_0F01_REG_3
) },
11127 /* MOD_0F01_REG_7 */
11128 { "invlpg", { Mb
} },
11129 { RM_TABLE (RM_0F01_REG_7
) },
11132 /* MOD_0F12_PREFIX_0 */
11133 { "movlps", { XM
, EXq
} },
11134 { "movhlps", { XM
, EXq
} },
11138 { "movlpX", { EXq
, XM
} },
11141 /* MOD_0F16_PREFIX_0 */
11142 { "movhps", { XM
, EXq
} },
11143 { "movlhps", { XM
, EXq
} },
11147 { "movhpX", { EXq
, XM
} },
11150 /* MOD_0F18_REG_0 */
11151 { "prefetchnta", { Mb
} },
11154 /* MOD_0F18_REG_1 */
11155 { "prefetcht0", { Mb
} },
11158 /* MOD_0F18_REG_2 */
11159 { "prefetcht1", { Mb
} },
11162 /* MOD_0F18_REG_3 */
11163 { "prefetcht2", { Mb
} },
11166 /* MOD_0F18_REG_4 */
11167 { "nop/reserved", { Mb
} },
11170 /* MOD_0F18_REG_5 */
11171 { "nop/reserved", { Mb
} },
11174 /* MOD_0F18_REG_6 */
11175 { "nop/reserved", { Mb
} },
11178 /* MOD_0F18_REG_7 */
11179 { "nop/reserved", { Mb
} },
11182 /* MOD_0F1A_PREFIX_0 */
11183 { "bndldx", { Gbnd
, Ev_bnd
} },
11184 { "nopQ", { Ev
} },
11187 /* MOD_0F1B_PREFIX_0 */
11188 { "bndstx", { Ev_bnd
, Gbnd
} },
11189 { "nopQ", { Ev
} },
11192 /* MOD_0F1B_PREFIX_1 */
11193 { "bndmk", { Gbnd
, Ev_bnd
} },
11194 { "nopQ", { Ev
} },
11199 { "movZ", { Rm
, Cm
} },
11204 { "movZ", { Rm
, Dm
} },
11209 { "movZ", { Cm
, Rm
} },
11214 { "movZ", { Dm
, Rm
} },
11219 { "movL", { Rd
, Td
} },
11224 { "movL", { Td
, Rd
} },
11227 /* MOD_0F2B_PREFIX_0 */
11228 {"movntps", { Mx
, XM
} },
11231 /* MOD_0F2B_PREFIX_1 */
11232 {"movntss", { Md
, XM
} },
11235 /* MOD_0F2B_PREFIX_2 */
11236 {"movntpd", { Mx
, XM
} },
11239 /* MOD_0F2B_PREFIX_3 */
11240 {"movntsd", { Mq
, XM
} },
11245 { "movmskpX", { Gdq
, XS
} },
11248 /* MOD_0F71_REG_2 */
11250 { "psrlw", { MS
, Ib
} },
11253 /* MOD_0F71_REG_4 */
11255 { "psraw", { MS
, Ib
} },
11258 /* MOD_0F71_REG_6 */
11260 { "psllw", { MS
, Ib
} },
11263 /* MOD_0F72_REG_2 */
11265 { "psrld", { MS
, Ib
} },
11268 /* MOD_0F72_REG_4 */
11270 { "psrad", { MS
, Ib
} },
11273 /* MOD_0F72_REG_6 */
11275 { "pslld", { MS
, Ib
} },
11278 /* MOD_0F73_REG_2 */
11280 { "psrlq", { MS
, Ib
} },
11283 /* MOD_0F73_REG_3 */
11285 { PREFIX_TABLE (PREFIX_0F73_REG_3
) },
11288 /* MOD_0F73_REG_6 */
11290 { "psllq", { MS
, Ib
} },
11293 /* MOD_0F73_REG_7 */
11295 { PREFIX_TABLE (PREFIX_0F73_REG_7
) },
11298 /* MOD_0FAE_REG_0 */
11299 { "fxsave", { FXSAVE
} },
11300 { PREFIX_TABLE (PREFIX_0FAE_REG_0
) },
11303 /* MOD_0FAE_REG_1 */
11304 { "fxrstor", { FXSAVE
} },
11305 { PREFIX_TABLE (PREFIX_0FAE_REG_1
) },
11308 /* MOD_0FAE_REG_2 */
11309 { "ldmxcsr", { Md
} },
11310 { PREFIX_TABLE (PREFIX_0FAE_REG_2
) },
11313 /* MOD_0FAE_REG_3 */
11314 { "stmxcsr", { Md
} },
11315 { PREFIX_TABLE (PREFIX_0FAE_REG_3
) },
11318 /* MOD_0FAE_REG_4 */
11319 { "xsave", { FXSAVE
} },
11322 /* MOD_0FAE_REG_5 */
11323 { "xrstor", { FXSAVE
} },
11324 { RM_TABLE (RM_0FAE_REG_5
) },
11327 /* MOD_0FAE_REG_6 */
11328 { "xsaveopt", { FXSAVE
} },
11329 { RM_TABLE (RM_0FAE_REG_6
) },
11332 /* MOD_0FAE_REG_7 */
11333 { PREFIX_TABLE (PREFIX_0FAE_REG_7
) },
11334 { RM_TABLE (RM_0FAE_REG_7
) },
11338 { "lssS", { Gv
, Mp
} },
11342 { "lfsS", { Gv
, Mp
} },
11346 { "lgsS", { Gv
, Mp
} },
11349 /* MOD_0FC7_REG_3 */
11350 { "xrstors", { FXSAVE
} },
11353 /* MOD_0FC7_REG_4 */
11354 { "xsavec", { FXSAVE
} },
11357 /* MOD_0FC7_REG_5 */
11358 { "xsaves", { FXSAVE
} },
11361 /* MOD_0FC7_REG_6 */
11362 { PREFIX_TABLE (PREFIX_0FC7_REG_6
) },
11363 { "rdrand", { Ev
} },
11366 /* MOD_0FC7_REG_7 */
11367 { "vmptrst", { Mq
} },
11368 { "rdseed", { Ev
} },
11373 { "pmovmskb", { Gdq
, MS
} },
11376 /* MOD_0FE7_PREFIX_2 */
11377 { "movntdq", { Mx
, XM
} },
11380 /* MOD_0FF0_PREFIX_3 */
11381 { "lddqu", { XM
, M
} },
11384 /* MOD_0F382A_PREFIX_2 */
11385 { "movntdqa", { XM
, Mx
} },
11389 { "bound{S|}", { Gv
, Ma
} },
11390 { EVEX_TABLE (EVEX_0F
) },
11394 { "lesS", { Gv
, Mp
} },
11395 { VEX_C4_TABLE (VEX_0F
) },
11399 { "ldsS", { Gv
, Mp
} },
11400 { VEX_C5_TABLE (VEX_0F
) },
11403 /* MOD_VEX_0F12_PREFIX_0 */
11404 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0
) },
11405 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1
) },
11409 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0
) },
11412 /* MOD_VEX_0F16_PREFIX_0 */
11413 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0
) },
11414 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1
) },
11418 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0
) },
11422 { VEX_W_TABLE (VEX_W_0F2B_M_0
) },
11427 { VEX_W_TABLE (VEX_W_0F50_M_0
) },
11430 /* MOD_VEX_0F71_REG_2 */
11432 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2
) },
11435 /* MOD_VEX_0F71_REG_4 */
11437 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4
) },
11440 /* MOD_VEX_0F71_REG_6 */
11442 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6
) },
11445 /* MOD_VEX_0F72_REG_2 */
11447 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2
) },
11450 /* MOD_VEX_0F72_REG_4 */
11452 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4
) },
11455 /* MOD_VEX_0F72_REG_6 */
11457 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6
) },
11460 /* MOD_VEX_0F73_REG_2 */
11462 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2
) },
11465 /* MOD_VEX_0F73_REG_3 */
11467 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3
) },
11470 /* MOD_VEX_0F73_REG_6 */
11472 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6
) },
11475 /* MOD_VEX_0F73_REG_7 */
11477 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7
) },
11480 /* MOD_VEX_0FAE_REG_2 */
11481 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0
) },
11484 /* MOD_VEX_0FAE_REG_3 */
11485 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0
) },
11488 /* MOD_VEX_0FD7_PREFIX_2 */
11490 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1
) },
11493 /* MOD_VEX_0FE7_PREFIX_2 */
11494 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0
) },
11497 /* MOD_VEX_0FF0_PREFIX_3 */
11498 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0
) },
11501 /* MOD_VEX_0F381A_PREFIX_2 */
11502 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0
) },
11505 /* MOD_VEX_0F382A_PREFIX_2 */
11506 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0
) },
11509 /* MOD_VEX_0F382C_PREFIX_2 */
11510 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0
) },
11513 /* MOD_VEX_0F382D_PREFIX_2 */
11514 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0
) },
11517 /* MOD_VEX_0F382E_PREFIX_2 */
11518 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0
) },
11521 /* MOD_VEX_0F382F_PREFIX_2 */
11522 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0
) },
11525 /* MOD_VEX_0F385A_PREFIX_2 */
11526 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0
) },
11529 /* MOD_VEX_0F388C_PREFIX_2 */
11530 { "vpmaskmov%LW", { XM
, Vex
, Mx
} },
11533 /* MOD_VEX_0F388E_PREFIX_2 */
11534 { "vpmaskmov%LW", { Mx
, Vex
, XM
} },
11536 #define NEED_MOD_TABLE
11537 #include "i386-dis-evex.h"
11538 #undef NEED_MOD_TABLE
11541 static const struct dis386 rm_table
[][8] = {
11544 { "xabort", { Skip_MODRM
, Ib
} },
11548 { "xbeginT", { Skip_MODRM
, Jv
} },
11551 /* RM_0F01_REG_0 */
11553 { "vmcall", { Skip_MODRM
} },
11554 { "vmlaunch", { Skip_MODRM
} },
11555 { "vmresume", { Skip_MODRM
} },
11556 { "vmxoff", { Skip_MODRM
} },
11559 /* RM_0F01_REG_1 */
11560 { "monitor", { { OP_Monitor
, 0 } } },
11561 { "mwait", { { OP_Mwait
, 0 } } },
11562 { "clac", { Skip_MODRM
} },
11563 { "stac", { Skip_MODRM
} },
11567 { "encls", { Skip_MODRM
} },
11570 /* RM_0F01_REG_2 */
11571 { "xgetbv", { Skip_MODRM
} },
11572 { "xsetbv", { Skip_MODRM
} },
11575 { "vmfunc", { Skip_MODRM
} },
11576 { "xend", { Skip_MODRM
} },
11577 { "xtest", { Skip_MODRM
} },
11578 { "enclu", { Skip_MODRM
} },
11581 /* RM_0F01_REG_3 */
11582 { "vmrun", { Skip_MODRM
} },
11583 { "vmmcall", { Skip_MODRM
} },
11584 { "vmload", { Skip_MODRM
} },
11585 { "vmsave", { Skip_MODRM
} },
11586 { "stgi", { Skip_MODRM
} },
11587 { "clgi", { Skip_MODRM
} },
11588 { "skinit", { Skip_MODRM
} },
11589 { "invlpga", { Skip_MODRM
} },
11592 /* RM_0F01_REG_7 */
11593 { "swapgs", { Skip_MODRM
} },
11594 { "rdtscp", { Skip_MODRM
} },
11597 /* RM_0FAE_REG_5 */
11598 { "lfence", { Skip_MODRM
} },
11601 /* RM_0FAE_REG_6 */
11602 { "mfence", { Skip_MODRM
} },
11605 /* RM_0FAE_REG_7 */
11606 { "sfence", { Skip_MODRM
} },
11610 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11612 /* We use the high bit to indicate different name for the same
11614 #define REP_PREFIX (0xf3 | 0x100)
11615 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11616 #define XRELEASE_PREFIX (0xf3 | 0x400)
11617 #define BND_PREFIX (0xf2 | 0x400)
11622 int newrex
, i
, length
;
11628 last_lock_prefix
= -1;
11629 last_repz_prefix
= -1;
11630 last_repnz_prefix
= -1;
11631 last_data_prefix
= -1;
11632 last_addr_prefix
= -1;
11633 last_rex_prefix
= -1;
11634 last_seg_prefix
= -1;
11636 active_seg_prefix
= 0;
11637 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
11638 all_prefixes
[i
] = 0;
11641 /* The maximum instruction length is 15bytes. */
11642 while (length
< MAX_CODE_LENGTH
- 1)
11644 FETCH_DATA (the_info
, codep
+ 1);
11648 /* REX prefixes family. */
11665 if (address_mode
== mode_64bit
)
11669 last_rex_prefix
= i
;
11672 prefixes
|= PREFIX_REPZ
;
11673 last_repz_prefix
= i
;
11676 prefixes
|= PREFIX_REPNZ
;
11677 last_repnz_prefix
= i
;
11680 prefixes
|= PREFIX_LOCK
;
11681 last_lock_prefix
= i
;
11684 prefixes
|= PREFIX_CS
;
11685 last_seg_prefix
= i
;
11686 active_seg_prefix
= PREFIX_CS
;
11689 prefixes
|= PREFIX_SS
;
11690 last_seg_prefix
= i
;
11691 active_seg_prefix
= PREFIX_SS
;
11694 prefixes
|= PREFIX_DS
;
11695 last_seg_prefix
= i
;
11696 active_seg_prefix
= PREFIX_DS
;
11699 prefixes
|= PREFIX_ES
;
11700 last_seg_prefix
= i
;
11701 active_seg_prefix
= PREFIX_ES
;
11704 prefixes
|= PREFIX_FS
;
11705 last_seg_prefix
= i
;
11706 active_seg_prefix
= PREFIX_FS
;
11709 prefixes
|= PREFIX_GS
;
11710 last_seg_prefix
= i
;
11711 active_seg_prefix
= PREFIX_GS
;
11714 prefixes
|= PREFIX_DATA
;
11715 last_data_prefix
= i
;
11718 prefixes
|= PREFIX_ADDR
;
11719 last_addr_prefix
= i
;
11722 /* fwait is really an instruction. If there are prefixes
11723 before the fwait, they belong to the fwait, *not* to the
11724 following instruction. */
11726 if (prefixes
|| rex
)
11728 prefixes
|= PREFIX_FWAIT
;
11730 /* This ensures that the previous REX prefixes are noticed
11731 as unused prefixes, as in the return case below. */
11735 prefixes
= PREFIX_FWAIT
;
11740 /* Rex is ignored when followed by another prefix. */
11746 if (*codep
!= FWAIT_OPCODE
)
11747 all_prefixes
[i
++] = *codep
;
11755 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11758 static const char *
11759 prefix_name (int pref
, int sizeflag
)
11761 static const char *rexes
[16] =
11764 "rex.B", /* 0x41 */
11765 "rex.X", /* 0x42 */
11766 "rex.XB", /* 0x43 */
11767 "rex.R", /* 0x44 */
11768 "rex.RB", /* 0x45 */
11769 "rex.RX", /* 0x46 */
11770 "rex.RXB", /* 0x47 */
11771 "rex.W", /* 0x48 */
11772 "rex.WB", /* 0x49 */
11773 "rex.WX", /* 0x4a */
11774 "rex.WXB", /* 0x4b */
11775 "rex.WR", /* 0x4c */
11776 "rex.WRB", /* 0x4d */
11777 "rex.WRX", /* 0x4e */
11778 "rex.WRXB", /* 0x4f */
11783 /* REX prefixes family. */
11800 return rexes
[pref
- 0x40];
11820 return (sizeflag
& DFLAG
) ? "data16" : "data32";
11822 if (address_mode
== mode_64bit
)
11823 return (sizeflag
& AFLAG
) ? "addr32" : "addr64";
11825 return (sizeflag
& AFLAG
) ? "addr16" : "addr32";
11830 case XACQUIRE_PREFIX
:
11832 case XRELEASE_PREFIX
:
11841 static char op_out
[MAX_OPERANDS
][100];
11842 static int op_ad
, op_index
[MAX_OPERANDS
];
11843 static int two_source_ops
;
11844 static bfd_vma op_address
[MAX_OPERANDS
];
11845 static bfd_vma op_riprel
[MAX_OPERANDS
];
11846 static bfd_vma start_pc
;
11849 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11850 * (see topic "Redundant prefixes" in the "Differences from 8086"
11851 * section of the "Virtual 8086 Mode" chapter.)
11852 * 'pc' should be the address of this instruction, it will
11853 * be used to print the target address if this is a relative jump or call
11854 * The function returns the length of this instruction in bytes.
11857 static char intel_syntax
;
11858 static char intel_mnemonic
= !SYSV386_COMPAT
;
11859 static char open_char
;
11860 static char close_char
;
11861 static char separator_char
;
11862 static char scale_char
;
11864 /* Here for backwards compatibility. When gdb stops using
11865 print_insn_i386_att and print_insn_i386_intel these functions can
11866 disappear, and print_insn_i386 be merged into print_insn. */
11868 print_insn_i386_att (bfd_vma pc
, disassemble_info
*info
)
11872 return print_insn (pc
, info
);
11876 print_insn_i386_intel (bfd_vma pc
, disassemble_info
*info
)
11880 return print_insn (pc
, info
);
11884 print_insn_i386 (bfd_vma pc
, disassemble_info
*info
)
11888 return print_insn (pc
, info
);
11892 print_i386_disassembler_options (FILE *stream
)
11894 fprintf (stream
, _("\n\
11895 The following i386/x86-64 specific disassembler options are supported for use\n\
11896 with the -M switch (multiple options should be separated by commas):\n"));
11898 fprintf (stream
, _(" x86-64 Disassemble in 64bit mode\n"));
11899 fprintf (stream
, _(" i386 Disassemble in 32bit mode\n"));
11900 fprintf (stream
, _(" i8086 Disassemble in 16bit mode\n"));
11901 fprintf (stream
, _(" att Display instruction in AT&T syntax\n"));
11902 fprintf (stream
, _(" intel Display instruction in Intel syntax\n"));
11903 fprintf (stream
, _(" att-mnemonic\n"
11904 " Display instruction in AT&T mnemonic\n"));
11905 fprintf (stream
, _(" intel-mnemonic\n"
11906 " Display instruction in Intel mnemonic\n"));
11907 fprintf (stream
, _(" addr64 Assume 64bit address size\n"));
11908 fprintf (stream
, _(" addr32 Assume 32bit address size\n"));
11909 fprintf (stream
, _(" addr16 Assume 16bit address size\n"));
11910 fprintf (stream
, _(" data32 Assume 32bit data size\n"));
11911 fprintf (stream
, _(" data16 Assume 16bit data size\n"));
11912 fprintf (stream
, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11916 static const struct dis386 bad_opcode
= { "(bad)", { XX
} };
11918 /* Get a pointer to struct dis386 with a valid name. */
11920 static const struct dis386
*
11921 get_valid_dis386 (const struct dis386
*dp
, disassemble_info
*info
)
11923 int vindex
, vex_table_index
;
11925 if (dp
->name
!= NULL
)
11928 switch (dp
->op
[0].bytemode
)
11930 case USE_REG_TABLE
:
11931 dp
= ®_table
[dp
->op
[1].bytemode
][modrm
.reg
];
11934 case USE_MOD_TABLE
:
11935 vindex
= modrm
.mod
== 0x3 ? 1 : 0;
11936 dp
= &mod_table
[dp
->op
[1].bytemode
][vindex
];
11940 dp
= &rm_table
[dp
->op
[1].bytemode
][modrm
.rm
];
11943 case USE_PREFIX_TABLE
:
11946 /* The prefix in VEX is implicit. */
11947 switch (vex
.prefix
)
11952 case REPE_PREFIX_OPCODE
:
11955 case DATA_PREFIX_OPCODE
:
11958 case REPNE_PREFIX_OPCODE
:
11968 int last_prefix
= -1;
11971 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11972 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11974 if ((prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0)
11976 if (last_repz_prefix
> last_repnz_prefix
)
11979 prefix
= PREFIX_REPZ
;
11980 last_prefix
= last_repz_prefix
;
11985 prefix
= PREFIX_REPNZ
;
11986 last_prefix
= last_repnz_prefix
;
11989 /* Ignore the invalid index if it isn't mandatory. */
11990 if (!mandatory_prefix
11991 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].name
11993 && (prefix_table
[dp
->op
[1].bytemode
][vindex
].op
[0].bytemode
11998 if (vindex
== 0 && (prefixes
& PREFIX_DATA
) != 0)
12001 prefix
= PREFIX_DATA
;
12002 last_prefix
= last_data_prefix
;
12007 used_prefixes
|= prefix
;
12008 all_prefixes
[last_prefix
] = 0;
12011 dp
= &prefix_table
[dp
->op
[1].bytemode
][vindex
];
12014 case USE_X86_64_TABLE
:
12015 vindex
= address_mode
== mode_64bit
? 1 : 0;
12016 dp
= &x86_64_table
[dp
->op
[1].bytemode
][vindex
];
12019 case USE_3BYTE_TABLE
:
12020 FETCH_DATA (info
, codep
+ 2);
12022 dp
= &three_byte_table
[dp
->op
[1].bytemode
][vindex
];
12024 modrm
.mod
= (*codep
>> 6) & 3;
12025 modrm
.reg
= (*codep
>> 3) & 7;
12026 modrm
.rm
= *codep
& 7;
12029 case USE_VEX_LEN_TABLE
:
12033 switch (vex
.length
)
12046 dp
= &vex_len_table
[dp
->op
[1].bytemode
][vindex
];
12049 case USE_XOP_8F_TABLE
:
12050 FETCH_DATA (info
, codep
+ 3);
12051 /* All bits in the REX prefix are ignored. */
12053 rex
= ~(*codep
>> 5) & 0x7;
12055 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12056 switch ((*codep
& 0x1f))
12062 vex_table_index
= XOP_08
;
12065 vex_table_index
= XOP_09
;
12068 vex_table_index
= XOP_0A
;
12072 vex
.w
= *codep
& 0x80;
12073 if (vex
.w
&& address_mode
== mode_64bit
)
12076 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12077 if (address_mode
!= mode_64bit
12078 && vex
.register_specifier
> 0x7)
12084 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12085 switch ((*codep
& 0x3))
12091 vex
.prefix
= DATA_PREFIX_OPCODE
;
12094 vex
.prefix
= REPE_PREFIX_OPCODE
;
12097 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12104 dp
= &xop_table
[vex_table_index
][vindex
];
12107 FETCH_DATA (info
, codep
+ 1);
12108 modrm
.mod
= (*codep
>> 6) & 3;
12109 modrm
.reg
= (*codep
>> 3) & 7;
12110 modrm
.rm
= *codep
& 7;
12113 case USE_VEX_C4_TABLE
:
12115 FETCH_DATA (info
, codep
+ 3);
12116 /* All bits in the REX prefix are ignored. */
12118 rex
= ~(*codep
>> 5) & 0x7;
12119 switch ((*codep
& 0x1f))
12125 vex_table_index
= VEX_0F
;
12128 vex_table_index
= VEX_0F38
;
12131 vex_table_index
= VEX_0F3A
;
12135 vex
.w
= *codep
& 0x80;
12136 if (vex
.w
&& address_mode
== mode_64bit
)
12139 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12140 if (address_mode
!= mode_64bit
12141 && vex
.register_specifier
> 0x7)
12147 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12148 switch ((*codep
& 0x3))
12154 vex
.prefix
= DATA_PREFIX_OPCODE
;
12157 vex
.prefix
= REPE_PREFIX_OPCODE
;
12160 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12167 dp
= &vex_table
[vex_table_index
][vindex
];
12169 /* There is no MODRM byte for VEX [82|77]. */
12170 if (vindex
!= 0x77 && vindex
!= 0x82)
12172 FETCH_DATA (info
, codep
+ 1);
12173 modrm
.mod
= (*codep
>> 6) & 3;
12174 modrm
.reg
= (*codep
>> 3) & 7;
12175 modrm
.rm
= *codep
& 7;
12179 case USE_VEX_C5_TABLE
:
12181 FETCH_DATA (info
, codep
+ 2);
12182 /* All bits in the REX prefix are ignored. */
12184 rex
= (*codep
& 0x80) ? 0 : REX_R
;
12186 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12187 if (address_mode
!= mode_64bit
12188 && vex
.register_specifier
> 0x7)
12196 vex
.length
= (*codep
& 0x4) ? 256 : 128;
12197 switch ((*codep
& 0x3))
12203 vex
.prefix
= DATA_PREFIX_OPCODE
;
12206 vex
.prefix
= REPE_PREFIX_OPCODE
;
12209 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12216 dp
= &vex_table
[dp
->op
[1].bytemode
][vindex
];
12218 /* There is no MODRM byte for VEX [82|77]. */
12219 if (vindex
!= 0x77 && vindex
!= 0x82)
12221 FETCH_DATA (info
, codep
+ 1);
12222 modrm
.mod
= (*codep
>> 6) & 3;
12223 modrm
.reg
= (*codep
>> 3) & 7;
12224 modrm
.rm
= *codep
& 7;
12228 case USE_VEX_W_TABLE
:
12232 dp
= &vex_w_table
[dp
->op
[1].bytemode
][vex
.w
? 1 : 0];
12235 case USE_EVEX_TABLE
:
12236 two_source_ops
= 0;
12239 FETCH_DATA (info
, codep
+ 4);
12240 /* All bits in the REX prefix are ignored. */
12242 /* The first byte after 0x62. */
12243 rex
= ~(*codep
>> 5) & 0x7;
12244 vex
.r
= *codep
& 0x10;
12245 switch ((*codep
& 0xf))
12248 return &bad_opcode
;
12250 vex_table_index
= EVEX_0F
;
12253 vex_table_index
= EVEX_0F38
;
12256 vex_table_index
= EVEX_0F3A
;
12260 /* The second byte after 0x62. */
12262 vex
.w
= *codep
& 0x80;
12263 if (vex
.w
&& address_mode
== mode_64bit
)
12266 vex
.register_specifier
= (~(*codep
>> 3)) & 0xf;
12267 if (address_mode
!= mode_64bit
)
12269 /* In 16/32-bit mode silently ignore following bits. */
12273 vex
.register_specifier
&= 0x7;
12277 if (!(*codep
& 0x4))
12278 return &bad_opcode
;
12280 switch ((*codep
& 0x3))
12286 vex
.prefix
= DATA_PREFIX_OPCODE
;
12289 vex
.prefix
= REPE_PREFIX_OPCODE
;
12292 vex
.prefix
= REPNE_PREFIX_OPCODE
;
12296 /* The third byte after 0x62. */
12299 /* Remember the static rounding bits. */
12300 vex
.ll
= (*codep
>> 5) & 3;
12301 vex
.b
= (*codep
& 0x10) != 0;
12303 vex
.v
= *codep
& 0x8;
12304 vex
.mask_register_specifier
= *codep
& 0x7;
12305 vex
.zeroing
= *codep
& 0x80;
12311 dp
= &evex_table
[vex_table_index
][vindex
];
12313 FETCH_DATA (info
, codep
+ 1);
12314 modrm
.mod
= (*codep
>> 6) & 3;
12315 modrm
.reg
= (*codep
>> 3) & 7;
12316 modrm
.rm
= *codep
& 7;
12318 /* Set vector length. */
12319 if (modrm
.mod
== 3 && vex
.b
)
12335 return &bad_opcode
;
12348 if (dp
->name
!= NULL
)
12351 return get_valid_dis386 (dp
, info
);
12355 get_sib (disassemble_info
*info
, int sizeflag
)
12357 /* If modrm.mod == 3, operand must be register. */
12359 && ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
12363 FETCH_DATA (info
, codep
+ 2);
12364 sib
.index
= (codep
[1] >> 3) & 7;
12365 sib
.scale
= (codep
[1] >> 6) & 3;
12366 sib
.base
= codep
[1] & 7;
12371 print_insn (bfd_vma pc
, disassemble_info
*info
)
12373 const struct dis386
*dp
;
12375 char *op_txt
[MAX_OPERANDS
];
12377 int sizeflag
, orig_sizeflag
;
12379 struct dis_private priv
;
12382 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12383 if ((info
->mach
& bfd_mach_i386_i386
) != 0)
12384 address_mode
= mode_32bit
;
12385 else if (info
->mach
== bfd_mach_i386_i8086
)
12387 address_mode
= mode_16bit
;
12388 priv
.orig_sizeflag
= 0;
12391 address_mode
= mode_64bit
;
12393 if (intel_syntax
== (char) -1)
12394 intel_syntax
= (info
->mach
& bfd_mach_i386_intel_syntax
) != 0;
12396 for (p
= info
->disassembler_options
; p
!= NULL
; )
12398 if (CONST_STRNEQ (p
, "x86-64"))
12400 address_mode
= mode_64bit
;
12401 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12403 else if (CONST_STRNEQ (p
, "i386"))
12405 address_mode
= mode_32bit
;
12406 priv
.orig_sizeflag
= AFLAG
| DFLAG
;
12408 else if (CONST_STRNEQ (p
, "i8086"))
12410 address_mode
= mode_16bit
;
12411 priv
.orig_sizeflag
= 0;
12413 else if (CONST_STRNEQ (p
, "intel"))
12416 if (CONST_STRNEQ (p
+ 5, "-mnemonic"))
12417 intel_mnemonic
= 1;
12419 else if (CONST_STRNEQ (p
, "att"))
12422 if (CONST_STRNEQ (p
+ 3, "-mnemonic"))
12423 intel_mnemonic
= 0;
12425 else if (CONST_STRNEQ (p
, "addr"))
12427 if (address_mode
== mode_64bit
)
12429 if (p
[4] == '3' && p
[5] == '2')
12430 priv
.orig_sizeflag
&= ~AFLAG
;
12431 else if (p
[4] == '6' && p
[5] == '4')
12432 priv
.orig_sizeflag
|= AFLAG
;
12436 if (p
[4] == '1' && p
[5] == '6')
12437 priv
.orig_sizeflag
&= ~AFLAG
;
12438 else if (p
[4] == '3' && p
[5] == '2')
12439 priv
.orig_sizeflag
|= AFLAG
;
12442 else if (CONST_STRNEQ (p
, "data"))
12444 if (p
[4] == '1' && p
[5] == '6')
12445 priv
.orig_sizeflag
&= ~DFLAG
;
12446 else if (p
[4] == '3' && p
[5] == '2')
12447 priv
.orig_sizeflag
|= DFLAG
;
12449 else if (CONST_STRNEQ (p
, "suffix"))
12450 priv
.orig_sizeflag
|= SUFFIX_ALWAYS
;
12452 p
= strchr (p
, ',');
12459 names64
= intel_names64
;
12460 names32
= intel_names32
;
12461 names16
= intel_names16
;
12462 names8
= intel_names8
;
12463 names8rex
= intel_names8rex
;
12464 names_seg
= intel_names_seg
;
12465 names_mm
= intel_names_mm
;
12466 names_bnd
= intel_names_bnd
;
12467 names_xmm
= intel_names_xmm
;
12468 names_ymm
= intel_names_ymm
;
12469 names_zmm
= intel_names_zmm
;
12470 index64
= intel_index64
;
12471 index32
= intel_index32
;
12472 names_mask
= intel_names_mask
;
12473 index16
= intel_index16
;
12476 separator_char
= '+';
12481 names64
= att_names64
;
12482 names32
= att_names32
;
12483 names16
= att_names16
;
12484 names8
= att_names8
;
12485 names8rex
= att_names8rex
;
12486 names_seg
= att_names_seg
;
12487 names_mm
= att_names_mm
;
12488 names_bnd
= att_names_bnd
;
12489 names_xmm
= att_names_xmm
;
12490 names_ymm
= att_names_ymm
;
12491 names_zmm
= att_names_zmm
;
12492 index64
= att_index64
;
12493 index32
= att_index32
;
12494 names_mask
= att_names_mask
;
12495 index16
= att_index16
;
12498 separator_char
= ',';
12502 /* The output looks better if we put 7 bytes on a line, since that
12503 puts most long word instructions on a single line. Use 8 bytes
12505 if ((info
->mach
& bfd_mach_l1om
) != 0)
12506 info
->bytes_per_line
= 8;
12508 info
->bytes_per_line
= 7;
12510 info
->private_data
= &priv
;
12511 priv
.max_fetched
= priv
.the_buffer
;
12512 priv
.insn_start
= pc
;
12515 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12523 start_codep
= priv
.the_buffer
;
12524 codep
= priv
.the_buffer
;
12526 if (OPCODES_SIGSETJMP (priv
.bailout
) != 0)
12530 /* Getting here means we tried for data but didn't get it. That
12531 means we have an incomplete instruction of some sort. Just
12532 print the first byte as a prefix or a .byte pseudo-op. */
12533 if (codep
> priv
.the_buffer
)
12535 name
= prefix_name (priv
.the_buffer
[0], priv
.orig_sizeflag
);
12537 (*info
->fprintf_func
) (info
->stream
, "%s", name
);
12540 /* Just print the first byte as a .byte instruction. */
12541 (*info
->fprintf_func
) (info
->stream
, ".byte 0x%x",
12542 (unsigned int) priv
.the_buffer
[0]);
12552 sizeflag
= priv
.orig_sizeflag
;
12554 if (!ckprefix () || rex_used
)
12556 /* Too many prefixes or unused REX prefixes. */
12558 i
< (int) ARRAY_SIZE (all_prefixes
) && all_prefixes
[i
];
12560 (*info
->fprintf_func
) (info
->stream
, "%s%s",
12562 prefix_name (all_prefixes
[i
], sizeflag
));
12566 insn_codep
= codep
;
12568 FETCH_DATA (info
, codep
+ 1);
12569 two_source_ops
= (*codep
== 0x62) || (*codep
== 0xc8);
12571 if (((prefixes
& PREFIX_FWAIT
)
12572 && ((*codep
< 0xd8) || (*codep
> 0xdf))))
12574 /* Handle prefixes before fwait. */
12575 for (i
= 0; i
< fwait_prefix
&& all_prefixes
[i
];
12577 (*info
->fprintf_func
) (info
->stream
, "%s ",
12578 prefix_name (all_prefixes
[i
], sizeflag
));
12579 (*info
->fprintf_func
) (info
->stream
, "fwait");
12583 if (*codep
== 0x0f)
12585 unsigned char threebyte
;
12586 FETCH_DATA (info
, codep
+ 2);
12587 threebyte
= *++codep
;
12588 dp
= &dis386_twobyte
[threebyte
];
12589 need_modrm
= twobyte_has_modrm
[*codep
];
12590 mandatory_prefix
= twobyte_has_mandatory_prefix
[*codep
];
12595 dp
= &dis386
[*codep
];
12596 need_modrm
= onebyte_has_modrm
[*codep
];
12597 mandatory_prefix
= 0;
12601 /* Save sizeflag for printing the extra prefixes later before updating
12602 it for mnemonic and operand processing. The prefix names depend
12603 only on the address mode. */
12604 orig_sizeflag
= sizeflag
;
12605 if (prefixes
& PREFIX_ADDR
)
12607 if ((prefixes
& PREFIX_DATA
))
12613 FETCH_DATA (info
, codep
+ 1);
12614 modrm
.mod
= (*codep
>> 6) & 3;
12615 modrm
.reg
= (*codep
>> 3) & 7;
12616 modrm
.rm
= *codep
& 7;
12624 if (dp
->name
== NULL
&& dp
->op
[0].bytemode
== FLOATCODE
)
12626 get_sib (info
, sizeflag
);
12627 dofloat (sizeflag
);
12631 dp
= get_valid_dis386 (dp
, info
);
12632 if (dp
!= NULL
&& putop (dp
->name
, sizeflag
) == 0)
12634 get_sib (info
, sizeflag
);
12635 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12638 op_ad
= MAX_OPERANDS
- 1 - i
;
12640 (*dp
->op
[i
].rtn
) (dp
->op
[i
].bytemode
, sizeflag
);
12641 /* For EVEX instruction after the last operand masking
12642 should be printed. */
12643 if (i
== 0 && vex
.evex
)
12645 /* Don't print {%k0}. */
12646 if (vex
.mask_register_specifier
)
12649 oappend (names_mask
[vex
.mask_register_specifier
]);
12659 /* Check if the REX prefix is used. */
12660 if (rex_ignored
== 0 && (rex
^ rex_used
) == 0 && last_rex_prefix
>= 0)
12661 all_prefixes
[last_rex_prefix
] = 0;
12663 /* Check if the SEG prefix is used. */
12664 if ((prefixes
& (PREFIX_CS
| PREFIX_SS
| PREFIX_DS
| PREFIX_ES
12665 | PREFIX_FS
| PREFIX_GS
)) != 0
12666 && (used_prefixes
& active_seg_prefix
) != 0)
12667 all_prefixes
[last_seg_prefix
] = 0;
12669 /* Check if the ADDR prefix is used. */
12670 if ((prefixes
& PREFIX_ADDR
) != 0
12671 && (used_prefixes
& PREFIX_ADDR
) != 0)
12672 all_prefixes
[last_addr_prefix
] = 0;
12674 /* Check if the DATA prefix is used. */
12675 if ((prefixes
& PREFIX_DATA
) != 0
12676 && (used_prefixes
& PREFIX_DATA
) != 0)
12677 all_prefixes
[last_data_prefix
] = 0;
12679 /* Print the extra prefixes. */
12681 for (i
= 0; i
< (int) ARRAY_SIZE (all_prefixes
); i
++)
12682 if (all_prefixes
[i
])
12685 name
= prefix_name (all_prefixes
[i
], orig_sizeflag
);
12688 prefix_length
+= strlen (name
) + 1;
12689 (*info
->fprintf_func
) (info
->stream
, "%s ", name
);
12692 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12693 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12694 used by putop and MMX/SSE operand and may be overriden by the
12695 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12697 if (mandatory_prefix
12698 && dp
!= &bad_opcode
12700 & (PREFIX_REPZ
| PREFIX_REPNZ
)) != 0
12702 & (PREFIX_REPZ
| PREFIX_REPNZ
)) == 0)
12704 & (PREFIX_REPZ
| PREFIX_REPNZ
| PREFIX_DATA
))
12706 && (used_prefixes
& PREFIX_DATA
) == 0))))
12708 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12709 return end_codep
- priv
.the_buffer
;
12712 /* Check maximum code length. */
12713 if ((codep
- start_codep
) > MAX_CODE_LENGTH
)
12715 (*info
->fprintf_func
) (info
->stream
, "(bad)");
12716 return MAX_CODE_LENGTH
;
12719 obufp
= mnemonicendp
;
12720 for (i
= strlen (obuf
) + prefix_length
; i
< 6; i
++)
12723 (*info
->fprintf_func
) (info
->stream
, "%s", obuf
);
12725 /* The enter and bound instructions are printed with operands in the same
12726 order as the intel book; everything else is printed in reverse order. */
12727 if (intel_syntax
|| two_source_ops
)
12731 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12732 op_txt
[i
] = op_out
[i
];
12734 for (i
= 0; i
< (MAX_OPERANDS
>> 1); ++i
)
12736 op_ad
= op_index
[i
];
12737 op_index
[i
] = op_index
[MAX_OPERANDS
- 1 - i
];
12738 op_index
[MAX_OPERANDS
- 1 - i
] = op_ad
;
12739 riprel
= op_riprel
[i
];
12740 op_riprel
[i
] = op_riprel
[MAX_OPERANDS
- 1 - i
];
12741 op_riprel
[MAX_OPERANDS
- 1 - i
] = riprel
;
12746 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12747 op_txt
[MAX_OPERANDS
- 1 - i
] = op_out
[i
];
12751 for (i
= 0; i
< MAX_OPERANDS
; ++i
)
12755 (*info
->fprintf_func
) (info
->stream
, ",");
12756 if (op_index
[i
] != -1 && !op_riprel
[i
])
12757 (*info
->print_address_func
) ((bfd_vma
) op_address
[op_index
[i
]], info
);
12759 (*info
->fprintf_func
) (info
->stream
, "%s", op_txt
[i
]);
12763 for (i
= 0; i
< MAX_OPERANDS
; i
++)
12764 if (op_index
[i
] != -1 && op_riprel
[i
])
12766 (*info
->fprintf_func
) (info
->stream
, " # ");
12767 (*info
->print_address_func
) ((bfd_vma
) (start_pc
+ codep
- start_codep
12768 + op_address
[op_index
[i
]]), info
);
12771 return codep
- priv
.the_buffer
;
12774 static const char *float_mem
[] = {
12849 static const unsigned char float_mem_mode
[] = {
12924 #define ST { OP_ST, 0 }
12925 #define STi { OP_STi, 0 }
12927 #define FGRPd9_2 NULL, { { NULL, 0 } }
12928 #define FGRPd9_4 NULL, { { NULL, 1 } }
12929 #define FGRPd9_5 NULL, { { NULL, 2 } }
12930 #define FGRPd9_6 NULL, { { NULL, 3 } }
12931 #define FGRPd9_7 NULL, { { NULL, 4 } }
12932 #define FGRPda_5 NULL, { { NULL, 5 } }
12933 #define FGRPdb_4 NULL, { { NULL, 6 } }
12934 #define FGRPde_3 NULL, { { NULL, 7 } }
12935 #define FGRPdf_4 NULL, { { NULL, 8 } }
12937 static const struct dis386 float_reg
[][8] = {
12940 { "fadd", { ST
, STi
} },
12941 { "fmul", { ST
, STi
} },
12942 { "fcom", { STi
} },
12943 { "fcomp", { STi
} },
12944 { "fsub", { ST
, STi
} },
12945 { "fsubr", { ST
, STi
} },
12946 { "fdiv", { ST
, STi
} },
12947 { "fdivr", { ST
, STi
} },
12951 { "fld", { STi
} },
12952 { "fxch", { STi
} },
12962 { "fcmovb", { ST
, STi
} },
12963 { "fcmove", { ST
, STi
} },
12964 { "fcmovbe",{ ST
, STi
} },
12965 { "fcmovu", { ST
, STi
} },
12973 { "fcmovnb",{ ST
, STi
} },
12974 { "fcmovne",{ ST
, STi
} },
12975 { "fcmovnbe",{ ST
, STi
} },
12976 { "fcmovnu",{ ST
, STi
} },
12978 { "fucomi", { ST
, STi
} },
12979 { "fcomi", { ST
, STi
} },
12984 { "fadd", { STi
, ST
} },
12985 { "fmul", { STi
, ST
} },
12988 { "fsub!M", { STi
, ST
} },
12989 { "fsubM", { STi
, ST
} },
12990 { "fdiv!M", { STi
, ST
} },
12991 { "fdivM", { STi
, ST
} },
12995 { "ffree", { STi
} },
12997 { "fst", { STi
} },
12998 { "fstp", { STi
} },
12999 { "fucom", { STi
} },
13000 { "fucomp", { STi
} },
13006 { "faddp", { STi
, ST
} },
13007 { "fmulp", { STi
, ST
} },
13010 { "fsub!Mp", { STi
, ST
} },
13011 { "fsubMp", { STi
, ST
} },
13012 { "fdiv!Mp", { STi
, ST
} },
13013 { "fdivMp", { STi
, ST
} },
13017 { "ffreep", { STi
} },
13022 { "fucomip", { ST
, STi
} },
13023 { "fcomip", { ST
, STi
} },
13028 static char *fgrps
[][8] = {
13031 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13036 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13041 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13046 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13051 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13056 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13061 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13062 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13067 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13072 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13077 swap_operand (void)
13079 mnemonicendp
[0] = '.';
13080 mnemonicendp
[1] = 's';
13085 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED
,
13086 int sizeflag ATTRIBUTE_UNUSED
)
13088 /* Skip mod/rm byte. */
13094 dofloat (int sizeflag
)
13096 const struct dis386
*dp
;
13097 unsigned char floatop
;
13099 floatop
= codep
[-1];
13101 if (modrm
.mod
!= 3)
13103 int fp_indx
= (floatop
- 0xd8) * 8 + modrm
.reg
;
13105 putop (float_mem
[fp_indx
], sizeflag
);
13108 OP_E (float_mem_mode
[fp_indx
], sizeflag
);
13111 /* Skip mod/rm byte. */
13115 dp
= &float_reg
[floatop
- 0xd8][modrm
.reg
];
13116 if (dp
->name
== NULL
)
13118 putop (fgrps
[dp
->op
[0].bytemode
][modrm
.rm
], sizeflag
);
13120 /* Instruction fnstsw is only one with strange arg. */
13121 if (floatop
== 0xdf && codep
[-1] == 0xe0)
13122 strcpy (op_out
[0], names16
[0]);
13126 putop (dp
->name
, sizeflag
);
13131 (*dp
->op
[0].rtn
) (dp
->op
[0].bytemode
, sizeflag
);
13136 (*dp
->op
[1].rtn
) (dp
->op
[1].bytemode
, sizeflag
);
13140 /* Like oappend (below), but S is a string starting with '%'.
13141 In Intel syntax, the '%' is elided. */
13143 oappend_maybe_intel (const char *s
)
13145 oappend (s
+ intel_syntax
);
13149 OP_ST (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13151 oappend_maybe_intel ("%st");
13155 OP_STi (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
13157 sprintf (scratchbuf
, "%%st(%d)", modrm
.rm
);
13158 oappend_maybe_intel (scratchbuf
);
13161 /* Capital letters in template are macros. */
13163 putop (const char *in_template
, int sizeflag
)
13168 unsigned int l
= 0, len
= 1;
13171 #define SAVE_LAST(c) \
13172 if (l < len && l < sizeof (last)) \
13177 for (p
= in_template
; *p
; p
++)
13194 while (*++p
!= '|')
13195 if (*p
== '}' || *p
== '\0')
13198 /* Fall through. */
13203 while (*++p
!= '}')
13214 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13218 if (l
== 0 && len
== 1)
13223 if (sizeflag
& SUFFIX_ALWAYS
)
13236 if (address_mode
== mode_64bit
13237 && !(prefixes
& PREFIX_ADDR
))
13248 if (intel_syntax
&& !alt
)
13250 if ((prefixes
& PREFIX_DATA
) || (sizeflag
& SUFFIX_ALWAYS
))
13252 if (sizeflag
& DFLAG
)
13253 *obufp
++ = intel_syntax
? 'd' : 'l';
13255 *obufp
++ = intel_syntax
? 'w' : 's';
13256 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13260 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13263 if (modrm
.mod
== 3)
13269 if (sizeflag
& DFLAG
)
13270 *obufp
++ = intel_syntax
? 'd' : 'l';
13273 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13279 case 'E': /* For jcxz/jecxz */
13280 if (address_mode
== mode_64bit
)
13282 if (sizeflag
& AFLAG
)
13288 if (sizeflag
& AFLAG
)
13290 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13295 if ((prefixes
& PREFIX_ADDR
) || (sizeflag
& SUFFIX_ALWAYS
))
13297 if (sizeflag
& AFLAG
)
13298 *obufp
++ = address_mode
== mode_64bit
? 'q' : 'l';
13300 *obufp
++ = address_mode
== mode_64bit
? 'l' : 'w';
13301 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
13305 if (intel_syntax
|| (obufp
[-1] != 's' && !(sizeflag
& SUFFIX_ALWAYS
)))
13307 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13311 if (!(rex
& REX_W
))
13312 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13317 if ((prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_CS
13318 || (prefixes
& (PREFIX_CS
| PREFIX_DS
)) == PREFIX_DS
)
13320 used_prefixes
|= prefixes
& (PREFIX_CS
| PREFIX_DS
);
13323 if (prefixes
& PREFIX_DS
)
13344 if (address_mode
== mode_64bit
&& (sizeflag
& SUFFIX_ALWAYS
))
13349 /* Fall through. */
13352 if (l
!= 0 || len
!= 1)
13360 if (sizeflag
& SUFFIX_ALWAYS
)
13364 if (intel_mnemonic
!= cond
)
13368 if ((prefixes
& PREFIX_FWAIT
) == 0)
13371 used_prefixes
|= PREFIX_FWAIT
;
13377 else if (intel_syntax
&& (sizeflag
& DFLAG
))
13381 if (!(rex
& REX_W
))
13382 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13386 && address_mode
== mode_64bit
13387 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13392 /* Fall through. */
13396 if ((rex
& REX_W
) == 0
13397 && (prefixes
& PREFIX_DATA
))
13399 if ((sizeflag
& DFLAG
) == 0)
13401 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13405 if ((prefixes
& PREFIX_DATA
)
13407 || (sizeflag
& SUFFIX_ALWAYS
))
13414 if (sizeflag
& DFLAG
)
13418 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13425 if (address_mode
== mode_64bit
13426 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13428 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13432 /* Fall through. */
13435 if (l
== 0 && len
== 1)
13438 if (intel_syntax
&& !alt
)
13441 if (modrm
.mod
!= 3 || (sizeflag
& SUFFIX_ALWAYS
))
13447 if (sizeflag
& DFLAG
)
13448 *obufp
++ = intel_syntax
? 'd' : 'l';
13451 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13457 if (l
!= 1 || len
!= 2 || last
[0] != 'L')
13463 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13478 else if (sizeflag
& DFLAG
)
13487 if (intel_syntax
&& !p
[1]
13488 && ((rex
& REX_W
) || (sizeflag
& DFLAG
)))
13490 if (!(rex
& REX_W
))
13491 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13494 if (l
== 0 && len
== 1)
13498 if (address_mode
== mode_64bit
13499 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13501 if (sizeflag
& SUFFIX_ALWAYS
)
13523 /* Fall through. */
13526 if (l
== 0 && len
== 1)
13531 if (sizeflag
& SUFFIX_ALWAYS
)
13537 if (sizeflag
& DFLAG
)
13541 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13555 if (address_mode
== mode_64bit
13556 && !(prefixes
& PREFIX_ADDR
))
13567 if (l
!= 0 || len
!= 1)
13572 if (need_vex
&& vex
.prefix
)
13574 if (vex
.prefix
== DATA_PREFIX_OPCODE
)
13581 if (prefixes
& PREFIX_DATA
)
13585 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13589 if (l
== 0 && len
== 1)
13591 if (intel_syntax
|| !(sizeflag
& SUFFIX_ALWAYS
))
13602 if (l
!= 1 || len
!= 2 || last
[0] != 'X')
13610 || (modrm
.mod
== 3 && !(sizeflag
& SUFFIX_ALWAYS
)))
13612 switch (vex
.length
)
13626 if (l
== 0 && len
== 1)
13628 /* operand size flag for cwtl, cbtw */
13637 else if (sizeflag
& DFLAG
)
13641 if (!(rex
& REX_W
))
13642 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13649 && last
[0] != 'L'))
13656 if (last
[0] == 'X')
13657 *obufp
++ = vex
.w
? 'd': 's';
13659 *obufp
++ = vex
.w
? 'q': 'd';
13666 mnemonicendp
= obufp
;
13671 oappend (const char *s
)
13673 obufp
= stpcpy (obufp
, s
);
13679 /* Only print the active segment register. */
13680 if (!active_seg_prefix
)
13683 used_prefixes
|= active_seg_prefix
;
13684 switch (active_seg_prefix
)
13687 oappend_maybe_intel ("%cs:");
13690 oappend_maybe_intel ("%ds:");
13693 oappend_maybe_intel ("%ss:");
13696 oappend_maybe_intel ("%es:");
13699 oappend_maybe_intel ("%fs:");
13702 oappend_maybe_intel ("%gs:");
13710 OP_indirE (int bytemode
, int sizeflag
)
13714 OP_E (bytemode
, sizeflag
);
13718 print_operand_value (char *buf
, int hex
, bfd_vma disp
)
13720 if (address_mode
== mode_64bit
)
13728 sprintf_vma (tmp
, disp
);
13729 for (i
= 0; tmp
[i
] == '0' && tmp
[i
+ 1]; i
++);
13730 strcpy (buf
+ 2, tmp
+ i
);
13734 bfd_signed_vma v
= disp
;
13741 /* Check for possible overflow on 0x8000000000000000. */
13744 strcpy (buf
, "9223372036854775808");
13758 tmp
[28 - i
] = (v
% 10) + '0';
13762 strcpy (buf
, tmp
+ 29 - i
);
13768 sprintf (buf
, "0x%x", (unsigned int) disp
);
13770 sprintf (buf
, "%d", (int) disp
);
13774 /* Put DISP in BUF as signed hex number. */
13777 print_displacement (char *buf
, bfd_vma disp
)
13779 bfd_signed_vma val
= disp
;
13788 /* Check for possible overflow. */
13791 switch (address_mode
)
13794 strcpy (buf
+ j
, "0x8000000000000000");
13797 strcpy (buf
+ j
, "0x80000000");
13800 strcpy (buf
+ j
, "0x8000");
13810 sprintf_vma (tmp
, (bfd_vma
) val
);
13811 for (i
= 0; tmp
[i
] == '0'; i
++)
13813 if (tmp
[i
] == '\0')
13815 strcpy (buf
+ j
, tmp
+ i
);
13819 intel_operand_size (int bytemode
, int sizeflag
)
13823 && (bytemode
== x_mode
13824 || bytemode
== evex_half_bcst_xmmq_mode
))
13827 oappend ("QWORD PTR ");
13829 oappend ("DWORD PTR ");
13837 oappend ("BYTE PTR ");
13841 oappend ("WORD PTR ");
13844 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
13846 oappend ("QWORD PTR ");
13855 oappend ("QWORD PTR ");
13858 if ((sizeflag
& DFLAG
) || bytemode
== dq_mode
)
13859 oappend ("DWORD PTR ");
13861 oappend ("WORD PTR ");
13862 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13866 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
13868 oappend ("WORD PTR ");
13869 if (!(rex
& REX_W
))
13870 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13873 if (sizeflag
& DFLAG
)
13874 oappend ("QWORD PTR ");
13876 oappend ("DWORD PTR ");
13877 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13880 case d_scalar_mode
:
13881 case d_scalar_swap_mode
:
13884 oappend ("DWORD PTR ");
13887 case q_scalar_mode
:
13888 case q_scalar_swap_mode
:
13890 oappend ("QWORD PTR ");
13893 if (address_mode
== mode_64bit
)
13894 oappend ("QWORD PTR ");
13896 oappend ("DWORD PTR ");
13899 if (sizeflag
& DFLAG
)
13900 oappend ("FWORD PTR ");
13902 oappend ("DWORD PTR ");
13903 used_prefixes
|= (prefixes
& PREFIX_DATA
);
13906 oappend ("TBYTE PTR ");
13910 case evex_x_gscat_mode
:
13911 case evex_x_nobcst_mode
:
13914 switch (vex
.length
)
13917 oappend ("XMMWORD PTR ");
13920 oappend ("YMMWORD PTR ");
13923 oappend ("ZMMWORD PTR ");
13930 oappend ("XMMWORD PTR ");
13933 oappend ("XMMWORD PTR ");
13936 oappend ("YMMWORD PTR ");
13939 case evex_half_bcst_xmmq_mode
:
13943 switch (vex
.length
)
13946 oappend ("QWORD PTR ");
13949 oappend ("XMMWORD PTR ");
13952 oappend ("YMMWORD PTR ");
13962 switch (vex
.length
)
13967 oappend ("BYTE PTR ");
13977 switch (vex
.length
)
13982 oappend ("WORD PTR ");
13992 switch (vex
.length
)
13997 oappend ("DWORD PTR ");
14007 switch (vex
.length
)
14012 oappend ("QWORD PTR ");
14022 switch (vex
.length
)
14025 oappend ("WORD PTR ");
14028 oappend ("DWORD PTR ");
14031 oappend ("QWORD PTR ");
14041 switch (vex
.length
)
14044 oappend ("DWORD PTR ");
14047 oappend ("QWORD PTR ");
14050 oappend ("XMMWORD PTR ");
14060 switch (vex
.length
)
14063 oappend ("QWORD PTR ");
14066 oappend ("YMMWORD PTR ");
14069 oappend ("ZMMWORD PTR ");
14079 switch (vex
.length
)
14083 oappend ("XMMWORD PTR ");
14090 oappend ("OWORD PTR ");
14093 case vex_w_dq_mode
:
14094 case vex_scalar_w_dq_mode
:
14099 oappend ("QWORD PTR ");
14101 oappend ("DWORD PTR ");
14103 case vex_vsib_d_w_dq_mode
:
14104 case vex_vsib_q_w_dq_mode
:
14111 oappend ("QWORD PTR ");
14113 oappend ("DWORD PTR ");
14117 if (vex
.length
!= 512)
14119 oappend ("ZMMWORD PTR ");
14122 case vex_vsib_q_w_d_mode
:
14123 case vex_vsib_d_w_d_mode
:
14124 if (!need_vex
|| !vex
.evex
|| vex
.length
!= 512)
14127 oappend ("YMMWORD PTR ");
14133 /* Currently the only instructions, which allows either mask or
14134 memory operand, are AVX512's KMOVW instructions. They need
14135 Word-sized operand. */
14136 if (vex
.w
|| vex
.length
!= 128)
14138 oappend ("WORD PTR ");
14147 OP_E_register (int bytemode
, int sizeflag
)
14149 int reg
= modrm
.rm
;
14150 const char **names
;
14156 if ((sizeflag
& SUFFIX_ALWAYS
)
14157 && (bytemode
== b_swap_mode
|| bytemode
== v_swap_mode
))
14181 names
= address_mode
== mode_64bit
? names64
: names32
;
14187 if (address_mode
== mode_64bit
&& ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14205 if ((sizeflag
& DFLAG
)
14206 || (bytemode
!= v_mode
14207 && bytemode
!= v_swap_mode
))
14211 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14215 names
= names_mask
;
14220 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14223 oappend (names
[reg
]);
14227 OP_E_memory (int bytemode
, int sizeflag
)
14230 int add
= (rex
& REX_B
) ? 8 : 0;
14236 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14238 && bytemode
!= x_mode
14239 && bytemode
!= evex_half_bcst_xmmq_mode
)
14246 case vex_vsib_d_w_dq_mode
:
14247 case vex_vsib_d_w_d_mode
:
14248 case vex_vsib_q_w_dq_mode
:
14249 case vex_vsib_q_w_d_mode
:
14250 case evex_x_gscat_mode
:
14252 shift
= vex
.w
? 3 : 2;
14255 case evex_half_bcst_xmmq_mode
:
14258 shift
= vex
.w
? 3 : 2;
14261 /* Fall through if vex.b == 0. */
14266 case evex_x_nobcst_mode
:
14268 switch (vex
.length
)
14291 case q_scalar_mode
:
14293 case q_scalar_swap_mode
:
14299 case d_scalar_mode
:
14301 case d_scalar_swap_mode
:
14313 /* Make necessary corrections to shift for modes that need it.
14314 For these modes we currently have shift 4, 5 or 6 depending on
14315 vex.length (it corresponds to xmmword, ymmword or zmmword
14316 operand). We might want to make it 3, 4 or 5 (e.g. for
14317 xmmq_mode). In case of broadcast enabled the corrections
14318 aren't needed, as element size is always 32 or 64 bits. */
14319 if (bytemode
== xmmq_mode
14320 || (bytemode
== evex_half_bcst_xmmq_mode
14323 else if (bytemode
== xmmqd_mode
)
14325 else if (bytemode
== xmmdw_mode
)
14333 intel_operand_size (bytemode
, sizeflag
);
14336 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
14338 /* 32/64 bit address mode */
14347 int addr32flag
= !((sizeflag
& AFLAG
)
14348 || bytemode
== v_bnd_mode
14349 || bytemode
== bnd_mode
);
14350 const char **indexes64
= names64
;
14351 const char **indexes32
= names32
;
14361 vindex
= sib
.index
;
14367 case vex_vsib_d_w_dq_mode
:
14368 case vex_vsib_d_w_d_mode
:
14369 case vex_vsib_q_w_dq_mode
:
14370 case vex_vsib_q_w_d_mode
:
14380 switch (vex
.length
)
14383 indexes64
= indexes32
= names_xmm
;
14387 || bytemode
== vex_vsib_q_w_dq_mode
14388 || bytemode
== vex_vsib_q_w_d_mode
)
14389 indexes64
= indexes32
= names_ymm
;
14391 indexes64
= indexes32
= names_xmm
;
14395 || bytemode
== vex_vsib_q_w_dq_mode
14396 || bytemode
== vex_vsib_q_w_d_mode
)
14397 indexes64
= indexes32
= names_zmm
;
14399 indexes64
= indexes32
= names_ymm
;
14406 haveindex
= vindex
!= 4;
14413 rbase
= base
+ add
;
14421 if (address_mode
== mode_64bit
&& !havesib
)
14427 FETCH_DATA (the_info
, codep
+ 1);
14429 if ((disp
& 0x80) != 0)
14431 if (vex
.evex
&& shift
> 0)
14439 /* In 32bit mode, we need index register to tell [offset] from
14440 [eiz*1 + offset]. */
14441 needindex
= (havesib
14444 && address_mode
== mode_32bit
);
14445 havedisp
= (havebase
14447 || (havesib
&& (haveindex
|| scale
!= 0)));
14450 if (modrm
.mod
!= 0 || base
== 5)
14452 if (havedisp
|| riprel
)
14453 print_displacement (scratchbuf
, disp
);
14455 print_operand_value (scratchbuf
, 1, disp
);
14456 oappend (scratchbuf
);
14460 oappend (sizeflag
& AFLAG
? "(%rip)" : "(%eip)");
14464 if ((havebase
|| haveindex
|| riprel
)
14465 && (bytemode
!= v_bnd_mode
)
14466 && (bytemode
!= bnd_mode
))
14467 used_prefixes
|= PREFIX_ADDR
;
14469 if (havedisp
|| (intel_syntax
&& riprel
))
14471 *obufp
++ = open_char
;
14472 if (intel_syntax
&& riprel
)
14475 oappend (sizeflag
& AFLAG
? "rip" : "eip");
14479 oappend (address_mode
== mode_64bit
&& !addr32flag
14480 ? names64
[rbase
] : names32
[rbase
]);
14483 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14484 print index to tell base + index from base. */
14488 || (havebase
&& base
!= ESP_REG_NUM
))
14490 if (!intel_syntax
|| havebase
)
14492 *obufp
++ = separator_char
;
14496 oappend (address_mode
== mode_64bit
&& !addr32flag
14497 ? indexes64
[vindex
] : indexes32
[vindex
]);
14499 oappend (address_mode
== mode_64bit
&& !addr32flag
14500 ? index64
: index32
);
14502 *obufp
++ = scale_char
;
14504 sprintf (scratchbuf
, "%d", 1 << scale
);
14505 oappend (scratchbuf
);
14509 && (disp
|| modrm
.mod
!= 0 || base
== 5))
14511 if (!havedisp
|| (bfd_signed_vma
) disp
>= 0)
14516 else if (modrm
.mod
!= 1 && disp
!= -disp
)
14520 disp
= - (bfd_signed_vma
) disp
;
14524 print_displacement (scratchbuf
, disp
);
14526 print_operand_value (scratchbuf
, 1, disp
);
14527 oappend (scratchbuf
);
14530 *obufp
++ = close_char
;
14533 else if (intel_syntax
)
14535 if (modrm
.mod
!= 0 || base
== 5)
14537 if (!active_seg_prefix
)
14539 oappend (names_seg
[ds_reg
- es_reg
]);
14542 print_operand_value (scratchbuf
, 1, disp
);
14543 oappend (scratchbuf
);
14549 /* 16 bit address mode */
14550 used_prefixes
|= prefixes
& PREFIX_ADDR
;
14557 if ((disp
& 0x8000) != 0)
14562 FETCH_DATA (the_info
, codep
+ 1);
14564 if ((disp
& 0x80) != 0)
14569 if ((disp
& 0x8000) != 0)
14575 if (modrm
.mod
!= 0 || modrm
.rm
== 6)
14577 print_displacement (scratchbuf
, disp
);
14578 oappend (scratchbuf
);
14581 if (modrm
.mod
!= 0 || modrm
.rm
!= 6)
14583 *obufp
++ = open_char
;
14585 oappend (index16
[modrm
.rm
]);
14587 && (disp
|| modrm
.mod
!= 0 || modrm
.rm
== 6))
14589 if ((bfd_signed_vma
) disp
>= 0)
14594 else if (modrm
.mod
!= 1)
14598 disp
= - (bfd_signed_vma
) disp
;
14601 print_displacement (scratchbuf
, disp
);
14602 oappend (scratchbuf
);
14605 *obufp
++ = close_char
;
14608 else if (intel_syntax
)
14610 if (!active_seg_prefix
)
14612 oappend (names_seg
[ds_reg
- es_reg
]);
14615 print_operand_value (scratchbuf
, 1, disp
& 0xffff);
14616 oappend (scratchbuf
);
14619 if (vex
.evex
&& vex
.b
14620 && (bytemode
== x_mode
14621 || bytemode
== evex_half_bcst_xmmq_mode
))
14623 if (vex
.w
|| bytemode
== evex_half_bcst_xmmq_mode
)
14624 oappend ("{1to8}");
14626 oappend ("{1to16}");
14631 OP_E (int bytemode
, int sizeflag
)
14633 /* Skip mod/rm byte. */
14637 if (modrm
.mod
== 3)
14638 OP_E_register (bytemode
, sizeflag
);
14640 OP_E_memory (bytemode
, sizeflag
);
14644 OP_G (int bytemode
, int sizeflag
)
14655 oappend (names8rex
[modrm
.reg
+ add
]);
14657 oappend (names8
[modrm
.reg
+ add
]);
14660 oappend (names16
[modrm
.reg
+ add
]);
14663 oappend (names32
[modrm
.reg
+ add
]);
14666 oappend (names64
[modrm
.reg
+ add
]);
14669 oappend (names_bnd
[modrm
.reg
]);
14678 oappend (names64
[modrm
.reg
+ add
]);
14681 if ((sizeflag
& DFLAG
) || bytemode
!= v_mode
)
14682 oappend (names32
[modrm
.reg
+ add
]);
14684 oappend (names16
[modrm
.reg
+ add
]);
14685 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14689 if (address_mode
== mode_64bit
)
14690 oappend (names64
[modrm
.reg
+ add
]);
14692 oappend (names32
[modrm
.reg
+ add
]);
14695 oappend (names_mask
[modrm
.reg
+ add
]);
14698 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14711 FETCH_DATA (the_info
, codep
+ 8);
14712 a
= *codep
++ & 0xff;
14713 a
|= (*codep
++ & 0xff) << 8;
14714 a
|= (*codep
++ & 0xff) << 16;
14715 a
|= (*codep
++ & 0xff) << 24;
14716 b
= *codep
++ & 0xff;
14717 b
|= (*codep
++ & 0xff) << 8;
14718 b
|= (*codep
++ & 0xff) << 16;
14719 b
|= (*codep
++ & 0xff) << 24;
14720 x
= a
+ ((bfd_vma
) b
<< 32);
14728 static bfd_signed_vma
14731 bfd_signed_vma x
= 0;
14733 FETCH_DATA (the_info
, codep
+ 4);
14734 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14735 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14736 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14737 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14741 static bfd_signed_vma
14744 bfd_signed_vma x
= 0;
14746 FETCH_DATA (the_info
, codep
+ 4);
14747 x
= *codep
++ & (bfd_signed_vma
) 0xff;
14748 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 8;
14749 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 16;
14750 x
|= (*codep
++ & (bfd_signed_vma
) 0xff) << 24;
14752 x
= (x
^ ((bfd_signed_vma
) 1 << 31)) - ((bfd_signed_vma
) 1 << 31);
14762 FETCH_DATA (the_info
, codep
+ 2);
14763 x
= *codep
++ & 0xff;
14764 x
|= (*codep
++ & 0xff) << 8;
14769 set_op (bfd_vma op
, int riprel
)
14771 op_index
[op_ad
] = op_ad
;
14772 if (address_mode
== mode_64bit
)
14774 op_address
[op_ad
] = op
;
14775 op_riprel
[op_ad
] = riprel
;
14779 /* Mask to get a 32-bit address. */
14780 op_address
[op_ad
] = op
& 0xffffffff;
14781 op_riprel
[op_ad
] = riprel
& 0xffffffff;
14786 OP_REG (int code
, int sizeflag
)
14793 case es_reg
: case ss_reg
: case cs_reg
:
14794 case ds_reg
: case fs_reg
: case gs_reg
:
14795 oappend (names_seg
[code
- es_reg
]);
14807 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14808 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14809 s
= names16
[code
- ax_reg
+ add
];
14811 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14812 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14815 s
= names8rex
[code
- al_reg
+ add
];
14817 s
= names8
[code
- al_reg
];
14819 case rAX_reg
: case rCX_reg
: case rDX_reg
: case rBX_reg
:
14820 case rSP_reg
: case rBP_reg
: case rSI_reg
: case rDI_reg
:
14821 if (address_mode
== mode_64bit
14822 && ((sizeflag
& DFLAG
) || (rex
& REX_W
)))
14824 s
= names64
[code
- rAX_reg
+ add
];
14827 code
+= eAX_reg
- rAX_reg
;
14828 /* Fall through. */
14829 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14830 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14833 s
= names64
[code
- eAX_reg
+ add
];
14836 if (sizeflag
& DFLAG
)
14837 s
= names32
[code
- eAX_reg
+ add
];
14839 s
= names16
[code
- eAX_reg
+ add
];
14840 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14844 s
= INTERNAL_DISASSEMBLER_ERROR
;
14851 OP_IMREG (int code
, int sizeflag
)
14863 case ax_reg
: case cx_reg
: case dx_reg
: case bx_reg
:
14864 case sp_reg
: case bp_reg
: case si_reg
: case di_reg
:
14865 s
= names16
[code
- ax_reg
];
14867 case es_reg
: case ss_reg
: case cs_reg
:
14868 case ds_reg
: case fs_reg
: case gs_reg
:
14869 s
= names_seg
[code
- es_reg
];
14871 case al_reg
: case ah_reg
: case cl_reg
: case ch_reg
:
14872 case dl_reg
: case dh_reg
: case bl_reg
: case bh_reg
:
14875 s
= names8rex
[code
- al_reg
];
14877 s
= names8
[code
- al_reg
];
14879 case eAX_reg
: case eCX_reg
: case eDX_reg
: case eBX_reg
:
14880 case eSP_reg
: case eBP_reg
: case eSI_reg
: case eDI_reg
:
14883 s
= names64
[code
- eAX_reg
];
14886 if (sizeflag
& DFLAG
)
14887 s
= names32
[code
- eAX_reg
];
14889 s
= names16
[code
- eAX_reg
];
14890 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14893 case z_mode_ax_reg
:
14894 if ((rex
& REX_W
) || (sizeflag
& DFLAG
))
14898 if (!(rex
& REX_W
))
14899 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14902 s
= INTERNAL_DISASSEMBLER_ERROR
;
14909 OP_I (int bytemode
, int sizeflag
)
14912 bfd_signed_vma mask
= -1;
14917 FETCH_DATA (the_info
, codep
+ 1);
14922 if (address_mode
== mode_64bit
)
14927 /* Fall through. */
14934 if (sizeflag
& DFLAG
)
14944 used_prefixes
|= (prefixes
& PREFIX_DATA
);
14956 oappend (INTERNAL_DISASSEMBLER_ERROR
);
14961 scratchbuf
[0] = '$';
14962 print_operand_value (scratchbuf
+ 1, 1, op
);
14963 oappend_maybe_intel (scratchbuf
);
14964 scratchbuf
[0] = '\0';
14968 OP_I64 (int bytemode
, int sizeflag
)
14971 bfd_signed_vma mask
= -1;
14973 if (address_mode
!= mode_64bit
)
14975 OP_I (bytemode
, sizeflag
);
14982 FETCH_DATA (the_info
, codep
+ 1);
14992 if (sizeflag
& DFLAG
)
15002 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15010 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15015 scratchbuf
[0] = '$';
15016 print_operand_value (scratchbuf
+ 1, 1, op
);
15017 oappend_maybe_intel (scratchbuf
);
15018 scratchbuf
[0] = '\0';
15022 OP_sI (int bytemode
, int sizeflag
)
15030 FETCH_DATA (the_info
, codep
+ 1);
15032 if ((op
& 0x80) != 0)
15034 if (bytemode
== b_T_mode
)
15036 if (address_mode
!= mode_64bit
15037 || !((sizeflag
& DFLAG
) || (rex
& REX_W
)))
15039 /* The operand-size prefix is overridden by a REX prefix. */
15040 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15048 if (!(rex
& REX_W
))
15050 if (sizeflag
& DFLAG
)
15058 /* The operand-size prefix is overridden by a REX prefix. */
15059 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15065 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15069 scratchbuf
[0] = '$';
15070 print_operand_value (scratchbuf
+ 1, 1, op
);
15071 oappend_maybe_intel (scratchbuf
);
15075 OP_J (int bytemode
, int sizeflag
)
15079 bfd_vma segment
= 0;
15084 FETCH_DATA (the_info
, codep
+ 1);
15086 if ((disp
& 0x80) != 0)
15091 if ((sizeflag
& DFLAG
) || (rex
& REX_W
))
15096 if ((disp
& 0x8000) != 0)
15098 /* In 16bit mode, address is wrapped around at 64k within
15099 the same segment. Otherwise, a data16 prefix on a jump
15100 instruction means that the pc is masked to 16 bits after
15101 the displacement is added! */
15103 if ((prefixes
& PREFIX_DATA
) == 0)
15104 segment
= ((start_pc
+ codep
- start_codep
)
15105 & ~((bfd_vma
) 0xffff));
15107 if (!(rex
& REX_W
))
15108 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15111 oappend (INTERNAL_DISASSEMBLER_ERROR
);
15114 disp
= ((start_pc
+ (codep
- start_codep
) + disp
) & mask
) | segment
;
15116 print_operand_value (scratchbuf
, 1, disp
);
15117 oappend (scratchbuf
);
15121 OP_SEG (int bytemode
, int sizeflag
)
15123 if (bytemode
== w_mode
)
15124 oappend (names_seg
[modrm
.reg
]);
15126 OP_E (modrm
.mod
== 3 ? bytemode
: w_mode
, sizeflag
);
15130 OP_DIR (int dummy ATTRIBUTE_UNUSED
, int sizeflag
)
15134 if (sizeflag
& DFLAG
)
15144 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15146 sprintf (scratchbuf
, "0x%x:0x%x", seg
, offset
);
15148 sprintf (scratchbuf
, "$0x%x,$0x%x", seg
, offset
);
15149 oappend (scratchbuf
);
15153 OP_OFF (int bytemode
, int sizeflag
)
15157 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15158 intel_operand_size (bytemode
, sizeflag
);
15161 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
15168 if (!active_seg_prefix
)
15170 oappend (names_seg
[ds_reg
- es_reg
]);
15174 print_operand_value (scratchbuf
, 1, off
);
15175 oappend (scratchbuf
);
15179 OP_OFF64 (int bytemode
, int sizeflag
)
15183 if (address_mode
!= mode_64bit
15184 || (prefixes
& PREFIX_ADDR
))
15186 OP_OFF (bytemode
, sizeflag
);
15190 if (intel_syntax
&& (sizeflag
& SUFFIX_ALWAYS
))
15191 intel_operand_size (bytemode
, sizeflag
);
15198 if (!active_seg_prefix
)
15200 oappend (names_seg
[ds_reg
- es_reg
]);
15204 print_operand_value (scratchbuf
, 1, off
);
15205 oappend (scratchbuf
);
15209 ptr_reg (int code
, int sizeflag
)
15213 *obufp
++ = open_char
;
15214 used_prefixes
|= (prefixes
& PREFIX_ADDR
);
15215 if (address_mode
== mode_64bit
)
15217 if (!(sizeflag
& AFLAG
))
15218 s
= names32
[code
- eAX_reg
];
15220 s
= names64
[code
- eAX_reg
];
15222 else if (sizeflag
& AFLAG
)
15223 s
= names32
[code
- eAX_reg
];
15225 s
= names16
[code
- eAX_reg
];
15227 *obufp
++ = close_char
;
15232 OP_ESreg (int code
, int sizeflag
)
15238 case 0x6d: /* insw/insl */
15239 intel_operand_size (z_mode
, sizeflag
);
15241 case 0xa5: /* movsw/movsl/movsq */
15242 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15243 case 0xab: /* stosw/stosl */
15244 case 0xaf: /* scasw/scasl */
15245 intel_operand_size (v_mode
, sizeflag
);
15248 intel_operand_size (b_mode
, sizeflag
);
15251 oappend_maybe_intel ("%es:");
15252 ptr_reg (code
, sizeflag
);
15256 OP_DSreg (int code
, int sizeflag
)
15262 case 0x6f: /* outsw/outsl */
15263 intel_operand_size (z_mode
, sizeflag
);
15265 case 0xa5: /* movsw/movsl/movsq */
15266 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15267 case 0xad: /* lodsw/lodsl/lodsq */
15268 intel_operand_size (v_mode
, sizeflag
);
15271 intel_operand_size (b_mode
, sizeflag
);
15274 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15275 default segment register DS is printed. */
15276 if (!active_seg_prefix
)
15277 active_seg_prefix
= PREFIX_DS
;
15279 ptr_reg (code
, sizeflag
);
15283 OP_C (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15291 else if (address_mode
!= mode_64bit
&& (prefixes
& PREFIX_LOCK
))
15293 all_prefixes
[last_lock_prefix
] = 0;
15294 used_prefixes
|= PREFIX_LOCK
;
15299 sprintf (scratchbuf
, "%%cr%d", modrm
.reg
+ add
);
15300 oappend_maybe_intel (scratchbuf
);
15304 OP_D (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15313 sprintf (scratchbuf
, "db%d", modrm
.reg
+ add
);
15315 sprintf (scratchbuf
, "%%db%d", modrm
.reg
+ add
);
15316 oappend (scratchbuf
);
15320 OP_T (int dummy ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15322 sprintf (scratchbuf
, "%%tr%d", modrm
.reg
);
15323 oappend_maybe_intel (scratchbuf
);
15327 OP_R (int bytemode
, int sizeflag
)
15329 if (modrm
.mod
== 3)
15330 OP_E (bytemode
, sizeflag
);
15336 OP_MMX (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15338 int reg
= modrm
.reg
;
15339 const char **names
;
15341 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15342 if (prefixes
& PREFIX_DATA
)
15351 oappend (names
[reg
]);
15355 OP_XMM (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
15357 int reg
= modrm
.reg
;
15358 const char **names
;
15370 && bytemode
!= xmm_mode
15371 && bytemode
!= xmmq_mode
15372 && bytemode
!= evex_half_bcst_xmmq_mode
15373 && bytemode
!= ymm_mode
15374 && bytemode
!= scalar_mode
)
15376 switch (vex
.length
)
15383 || (bytemode
!= vex_vsib_q_w_dq_mode
15384 && bytemode
!= vex_vsib_q_w_d_mode
))
15396 else if (bytemode
== xmmq_mode
15397 || bytemode
== evex_half_bcst_xmmq_mode
)
15399 switch (vex
.length
)
15412 else if (bytemode
== ymm_mode
)
15416 oappend (names
[reg
]);
15420 OP_EM (int bytemode
, int sizeflag
)
15423 const char **names
;
15425 if (modrm
.mod
!= 3)
15428 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
15430 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15431 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15433 OP_E (bytemode
, sizeflag
);
15437 if ((sizeflag
& SUFFIX_ALWAYS
) && bytemode
== v_swap_mode
)
15440 /* Skip mod/rm byte. */
15443 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15445 if (prefixes
& PREFIX_DATA
)
15454 oappend (names
[reg
]);
15457 /* cvt* are the only instructions in sse2 which have
15458 both SSE and MMX operands and also have 0x66 prefix
15459 in their opcode. 0x66 was originally used to differentiate
15460 between SSE and MMX instruction(operands). So we have to handle the
15461 cvt* separately using OP_EMC and OP_MXC */
15463 OP_EMC (int bytemode
, int sizeflag
)
15465 if (modrm
.mod
!= 3)
15467 if (intel_syntax
&& bytemode
== v_mode
)
15469 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
15470 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15472 OP_E (bytemode
, sizeflag
);
15476 /* Skip mod/rm byte. */
15479 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15480 oappend (names_mm
[modrm
.rm
]);
15484 OP_MXC (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15486 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15487 oappend (names_mm
[modrm
.reg
]);
15491 OP_EX (int bytemode
, int sizeflag
)
15494 const char **names
;
15496 /* Skip mod/rm byte. */
15500 if (modrm
.mod
!= 3)
15502 OP_E_memory (bytemode
, sizeflag
);
15517 if ((sizeflag
& SUFFIX_ALWAYS
)
15518 && (bytemode
== x_swap_mode
15519 || bytemode
== d_swap_mode
15520 || bytemode
== d_scalar_swap_mode
15521 || bytemode
== q_swap_mode
15522 || bytemode
== q_scalar_swap_mode
))
15526 && bytemode
!= xmm_mode
15527 && bytemode
!= xmmdw_mode
15528 && bytemode
!= xmmqd_mode
15529 && bytemode
!= xmm_mb_mode
15530 && bytemode
!= xmm_mw_mode
15531 && bytemode
!= xmm_md_mode
15532 && bytemode
!= xmm_mq_mode
15533 && bytemode
!= xmm_mdq_mode
15534 && bytemode
!= xmmq_mode
15535 && bytemode
!= evex_half_bcst_xmmq_mode
15536 && bytemode
!= ymm_mode
15537 && bytemode
!= d_scalar_mode
15538 && bytemode
!= d_scalar_swap_mode
15539 && bytemode
!= q_scalar_mode
15540 && bytemode
!= q_scalar_swap_mode
15541 && bytemode
!= vex_scalar_w_dq_mode
)
15543 switch (vex
.length
)
15558 else if (bytemode
== xmmq_mode
15559 || bytemode
== evex_half_bcst_xmmq_mode
)
15561 switch (vex
.length
)
15574 else if (bytemode
== ymm_mode
)
15578 oappend (names
[reg
]);
15582 OP_MS (int bytemode
, int sizeflag
)
15584 if (modrm
.mod
== 3)
15585 OP_EM (bytemode
, sizeflag
);
15591 OP_XS (int bytemode
, int sizeflag
)
15593 if (modrm
.mod
== 3)
15594 OP_EX (bytemode
, sizeflag
);
15600 OP_M (int bytemode
, int sizeflag
)
15602 if (modrm
.mod
== 3)
15603 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15606 OP_E (bytemode
, sizeflag
);
15610 OP_0f07 (int bytemode
, int sizeflag
)
15612 if (modrm
.mod
!= 3 || modrm
.rm
!= 0)
15615 OP_E (bytemode
, sizeflag
);
15618 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15619 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15622 NOP_Fixup1 (int bytemode
, int sizeflag
)
15624 if ((prefixes
& PREFIX_DATA
) != 0
15627 && address_mode
== mode_64bit
))
15628 OP_REG (bytemode
, sizeflag
);
15630 strcpy (obuf
, "nop");
15634 NOP_Fixup2 (int bytemode
, int sizeflag
)
15636 if ((prefixes
& PREFIX_DATA
) != 0
15639 && address_mode
== mode_64bit
))
15640 OP_IMREG (bytemode
, sizeflag
);
15643 static const char *const Suffix3DNow
[] = {
15644 /* 00 */ NULL
, NULL
, NULL
, NULL
,
15645 /* 04 */ NULL
, NULL
, NULL
, NULL
,
15646 /* 08 */ NULL
, NULL
, NULL
, NULL
,
15647 /* 0C */ "pi2fw", "pi2fd", NULL
, NULL
,
15648 /* 10 */ NULL
, NULL
, NULL
, NULL
,
15649 /* 14 */ NULL
, NULL
, NULL
, NULL
,
15650 /* 18 */ NULL
, NULL
, NULL
, NULL
,
15651 /* 1C */ "pf2iw", "pf2id", NULL
, NULL
,
15652 /* 20 */ NULL
, NULL
, NULL
, NULL
,
15653 /* 24 */ NULL
, NULL
, NULL
, NULL
,
15654 /* 28 */ NULL
, NULL
, NULL
, NULL
,
15655 /* 2C */ NULL
, NULL
, NULL
, NULL
,
15656 /* 30 */ NULL
, NULL
, NULL
, NULL
,
15657 /* 34 */ NULL
, NULL
, NULL
, NULL
,
15658 /* 38 */ NULL
, NULL
, NULL
, NULL
,
15659 /* 3C */ NULL
, NULL
, NULL
, NULL
,
15660 /* 40 */ NULL
, NULL
, NULL
, NULL
,
15661 /* 44 */ NULL
, NULL
, NULL
, NULL
,
15662 /* 48 */ NULL
, NULL
, NULL
, NULL
,
15663 /* 4C */ NULL
, NULL
, NULL
, NULL
,
15664 /* 50 */ NULL
, NULL
, NULL
, NULL
,
15665 /* 54 */ NULL
, NULL
, NULL
, NULL
,
15666 /* 58 */ NULL
, NULL
, NULL
, NULL
,
15667 /* 5C */ NULL
, NULL
, NULL
, NULL
,
15668 /* 60 */ NULL
, NULL
, NULL
, NULL
,
15669 /* 64 */ NULL
, NULL
, NULL
, NULL
,
15670 /* 68 */ NULL
, NULL
, NULL
, NULL
,
15671 /* 6C */ NULL
, NULL
, NULL
, NULL
,
15672 /* 70 */ NULL
, NULL
, NULL
, NULL
,
15673 /* 74 */ NULL
, NULL
, NULL
, NULL
,
15674 /* 78 */ NULL
, NULL
, NULL
, NULL
,
15675 /* 7C */ NULL
, NULL
, NULL
, NULL
,
15676 /* 80 */ NULL
, NULL
, NULL
, NULL
,
15677 /* 84 */ NULL
, NULL
, NULL
, NULL
,
15678 /* 88 */ NULL
, NULL
, "pfnacc", NULL
,
15679 /* 8C */ NULL
, NULL
, "pfpnacc", NULL
,
15680 /* 90 */ "pfcmpge", NULL
, NULL
, NULL
,
15681 /* 94 */ "pfmin", NULL
, "pfrcp", "pfrsqrt",
15682 /* 98 */ NULL
, NULL
, "pfsub", NULL
,
15683 /* 9C */ NULL
, NULL
, "pfadd", NULL
,
15684 /* A0 */ "pfcmpgt", NULL
, NULL
, NULL
,
15685 /* A4 */ "pfmax", NULL
, "pfrcpit1", "pfrsqit1",
15686 /* A8 */ NULL
, NULL
, "pfsubr", NULL
,
15687 /* AC */ NULL
, NULL
, "pfacc", NULL
,
15688 /* B0 */ "pfcmpeq", NULL
, NULL
, NULL
,
15689 /* B4 */ "pfmul", NULL
, "pfrcpit2", "pmulhrw",
15690 /* B8 */ NULL
, NULL
, NULL
, "pswapd",
15691 /* BC */ NULL
, NULL
, NULL
, "pavgusb",
15692 /* C0 */ NULL
, NULL
, NULL
, NULL
,
15693 /* C4 */ NULL
, NULL
, NULL
, NULL
,
15694 /* C8 */ NULL
, NULL
, NULL
, NULL
,
15695 /* CC */ NULL
, NULL
, NULL
, NULL
,
15696 /* D0 */ NULL
, NULL
, NULL
, NULL
,
15697 /* D4 */ NULL
, NULL
, NULL
, NULL
,
15698 /* D8 */ NULL
, NULL
, NULL
, NULL
,
15699 /* DC */ NULL
, NULL
, NULL
, NULL
,
15700 /* E0 */ NULL
, NULL
, NULL
, NULL
,
15701 /* E4 */ NULL
, NULL
, NULL
, NULL
,
15702 /* E8 */ NULL
, NULL
, NULL
, NULL
,
15703 /* EC */ NULL
, NULL
, NULL
, NULL
,
15704 /* F0 */ NULL
, NULL
, NULL
, NULL
,
15705 /* F4 */ NULL
, NULL
, NULL
, NULL
,
15706 /* F8 */ NULL
, NULL
, NULL
, NULL
,
15707 /* FC */ NULL
, NULL
, NULL
, NULL
,
15711 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15713 const char *mnemonic
;
15715 FETCH_DATA (the_info
, codep
+ 1);
15716 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15717 place where an 8-bit immediate would normally go. ie. the last
15718 byte of the instruction. */
15719 obufp
= mnemonicendp
;
15720 mnemonic
= Suffix3DNow
[*codep
++ & 0xff];
15722 oappend (mnemonic
);
15725 /* Since a variable sized modrm/sib chunk is between the start
15726 of the opcode (0x0f0f) and the opcode suffix, we need to do
15727 all the modrm processing first, and don't know until now that
15728 we have a bad opcode. This necessitates some cleaning up. */
15729 op_out
[0][0] = '\0';
15730 op_out
[1][0] = '\0';
15733 mnemonicendp
= obufp
;
15736 static struct op simd_cmp_op
[] =
15738 { STRING_COMMA_LEN ("eq") },
15739 { STRING_COMMA_LEN ("lt") },
15740 { STRING_COMMA_LEN ("le") },
15741 { STRING_COMMA_LEN ("unord") },
15742 { STRING_COMMA_LEN ("neq") },
15743 { STRING_COMMA_LEN ("nlt") },
15744 { STRING_COMMA_LEN ("nle") },
15745 { STRING_COMMA_LEN ("ord") }
15749 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15751 unsigned int cmp_type
;
15753 FETCH_DATA (the_info
, codep
+ 1);
15754 cmp_type
= *codep
++ & 0xff;
15755 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
))
15758 char *p
= mnemonicendp
- 2;
15762 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
15763 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
15767 /* We have a reserved extension byte. Output it directly. */
15768 scratchbuf
[0] = '$';
15769 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
15770 oappend_maybe_intel (scratchbuf
);
15771 scratchbuf
[0] = '\0';
15776 OP_Mwait (int bytemode ATTRIBUTE_UNUSED
,
15777 int sizeflag ATTRIBUTE_UNUSED
)
15779 /* mwait %eax,%ecx */
15782 const char **names
= (address_mode
== mode_64bit
15783 ? names64
: names32
);
15784 strcpy (op_out
[0], names
[0]);
15785 strcpy (op_out
[1], names
[1]);
15786 two_source_ops
= 1;
15788 /* Skip mod/rm byte. */
15794 OP_Monitor (int bytemode ATTRIBUTE_UNUSED
,
15795 int sizeflag ATTRIBUTE_UNUSED
)
15797 /* monitor %eax,%ecx,%edx" */
15800 const char **op1_names
;
15801 const char **names
= (address_mode
== mode_64bit
15802 ? names64
: names32
);
15804 if (!(prefixes
& PREFIX_ADDR
))
15805 op1_names
= (address_mode
== mode_16bit
15806 ? names16
: names
);
15809 /* Remove "addr16/addr32". */
15810 all_prefixes
[last_addr_prefix
] = 0;
15811 op1_names
= (address_mode
!= mode_32bit
15812 ? names32
: names16
);
15813 used_prefixes
|= PREFIX_ADDR
;
15815 strcpy (op_out
[0], op1_names
[0]);
15816 strcpy (op_out
[1], names
[1]);
15817 strcpy (op_out
[2], names
[2]);
15818 two_source_ops
= 1;
15820 /* Skip mod/rm byte. */
15828 /* Throw away prefixes and 1st. opcode byte. */
15829 codep
= insn_codep
+ 1;
15834 REP_Fixup (int bytemode
, int sizeflag
)
15836 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15838 if (prefixes
& PREFIX_REPZ
)
15839 all_prefixes
[last_repz_prefix
] = REP_PREFIX
;
15846 OP_IMREG (bytemode
, sizeflag
);
15849 OP_ESreg (bytemode
, sizeflag
);
15852 OP_DSreg (bytemode
, sizeflag
);
15860 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15864 BND_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
15866 if (prefixes
& PREFIX_REPNZ
)
15867 all_prefixes
[last_repnz_prefix
] = BND_PREFIX
;
15870 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15871 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15875 HLE_Fixup1 (int bytemode
, int sizeflag
)
15878 && (prefixes
& PREFIX_LOCK
) != 0)
15880 if (prefixes
& PREFIX_REPZ
)
15881 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15882 if (prefixes
& PREFIX_REPNZ
)
15883 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15886 OP_E (bytemode
, sizeflag
);
15889 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15890 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15894 HLE_Fixup2 (int bytemode
, int sizeflag
)
15896 if (modrm
.mod
!= 3)
15898 if (prefixes
& PREFIX_REPZ
)
15899 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15900 if (prefixes
& PREFIX_REPNZ
)
15901 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15904 OP_E (bytemode
, sizeflag
);
15907 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15908 "xrelease" for memory operand. No check for LOCK prefix. */
15911 HLE_Fixup3 (int bytemode
, int sizeflag
)
15914 && last_repz_prefix
> last_repnz_prefix
15915 && (prefixes
& PREFIX_REPZ
) != 0)
15916 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15918 OP_E (bytemode
, sizeflag
);
15922 CMPXCHG8B_Fixup (int bytemode
, int sizeflag
)
15927 /* Change cmpxchg8b to cmpxchg16b. */
15928 char *p
= mnemonicendp
- 2;
15929 mnemonicendp
= stpcpy (p
, "16b");
15932 else if ((prefixes
& PREFIX_LOCK
) != 0)
15934 if (prefixes
& PREFIX_REPZ
)
15935 all_prefixes
[last_repz_prefix
] = XRELEASE_PREFIX
;
15936 if (prefixes
& PREFIX_REPNZ
)
15937 all_prefixes
[last_repnz_prefix
] = XACQUIRE_PREFIX
;
15940 OP_M (bytemode
, sizeflag
);
15944 XMM_Fixup (int reg
, int sizeflag ATTRIBUTE_UNUSED
)
15946 const char **names
;
15950 switch (vex
.length
)
15964 oappend (names
[reg
]);
15968 CRC32_Fixup (int bytemode
, int sizeflag
)
15970 /* Add proper suffix to "crc32". */
15971 char *p
= mnemonicendp
;
15990 if (sizeflag
& DFLAG
)
15994 used_prefixes
|= (prefixes
& PREFIX_DATA
);
15998 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16005 if (modrm
.mod
== 3)
16009 /* Skip mod/rm byte. */
16014 add
= (rex
& REX_B
) ? 8 : 0;
16015 if (bytemode
== b_mode
)
16019 oappend (names8rex
[modrm
.rm
+ add
]);
16021 oappend (names8
[modrm
.rm
+ add
]);
16027 oappend (names64
[modrm
.rm
+ add
]);
16028 else if ((prefixes
& PREFIX_DATA
))
16029 oappend (names16
[modrm
.rm
+ add
]);
16031 oappend (names32
[modrm
.rm
+ add
]);
16035 OP_E (bytemode
, sizeflag
);
16039 FXSAVE_Fixup (int bytemode
, int sizeflag
)
16041 /* Add proper suffix to "fxsave" and "fxrstor". */
16045 char *p
= mnemonicendp
;
16051 OP_M (bytemode
, sizeflag
);
16054 /* Display the destination register operand for instructions with
16058 OP_VEX (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16061 const char **names
;
16069 reg
= vex
.register_specifier
;
16076 if (bytemode
== vex_scalar_mode
)
16078 oappend (names_xmm
[reg
]);
16082 switch (vex
.length
)
16089 case vex_vsib_q_w_dq_mode
:
16090 case vex_vsib_q_w_d_mode
:
16100 names
= names_mask
;
16114 case vex_vsib_q_w_dq_mode
:
16115 case vex_vsib_q_w_d_mode
:
16116 names
= vex
.w
? names_ymm
: names_xmm
;
16119 names
= names_mask
;
16133 oappend (names
[reg
]);
16136 /* Get the VEX immediate byte without moving codep. */
16138 static unsigned char
16139 get_vex_imm8 (int sizeflag
, int opnum
)
16141 int bytes_before_imm
= 0;
16143 if (modrm
.mod
!= 3)
16145 /* There are SIB/displacement bytes. */
16146 if ((sizeflag
& AFLAG
) || address_mode
== mode_64bit
)
16148 /* 32/64 bit address mode */
16149 int base
= modrm
.rm
;
16151 /* Check SIB byte. */
16154 FETCH_DATA (the_info
, codep
+ 1);
16156 /* When decoding the third source, don't increase
16157 bytes_before_imm as this has already been incremented
16158 by one in OP_E_memory while decoding the second
16161 bytes_before_imm
++;
16164 /* Don't increase bytes_before_imm when decoding the third source,
16165 it has already been incremented by OP_E_memory while decoding
16166 the second source operand. */
16172 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16173 SIB == 5, there is a 4 byte displacement. */
16175 /* No displacement. */
16178 /* 4 byte displacement. */
16179 bytes_before_imm
+= 4;
16182 /* 1 byte displacement. */
16183 bytes_before_imm
++;
16190 /* 16 bit address mode */
16191 /* Don't increase bytes_before_imm when decoding the third source,
16192 it has already been incremented by OP_E_memory while decoding
16193 the second source operand. */
16199 /* When modrm.rm == 6, there is a 2 byte displacement. */
16201 /* No displacement. */
16204 /* 2 byte displacement. */
16205 bytes_before_imm
+= 2;
16208 /* 1 byte displacement: when decoding the third source,
16209 don't increase bytes_before_imm as this has already
16210 been incremented by one in OP_E_memory while decoding
16211 the second source operand. */
16213 bytes_before_imm
++;
16221 FETCH_DATA (the_info
, codep
+ bytes_before_imm
+ 1);
16222 return codep
[bytes_before_imm
];
16226 OP_EX_VexReg (int bytemode
, int sizeflag
, int reg
)
16228 const char **names
;
16230 if (reg
== -1 && modrm
.mod
!= 3)
16232 OP_E_memory (bytemode
, sizeflag
);
16244 else if (reg
> 7 && address_mode
!= mode_64bit
)
16248 switch (vex
.length
)
16259 oappend (names
[reg
]);
16263 OP_EX_VexImmW (int bytemode
, int sizeflag
)
16266 static unsigned char vex_imm8
;
16268 if (vex_w_done
== 0)
16272 /* Skip mod/rm byte. */
16276 vex_imm8
= get_vex_imm8 (sizeflag
, 0);
16279 reg
= vex_imm8
>> 4;
16281 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16283 else if (vex_w_done
== 1)
16288 reg
= vex_imm8
>> 4;
16290 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16294 /* Output the imm8 directly. */
16295 scratchbuf
[0] = '$';
16296 print_operand_value (scratchbuf
+ 1, 1, vex_imm8
& 0xf);
16297 oappend_maybe_intel (scratchbuf
);
16298 scratchbuf
[0] = '\0';
16304 OP_Vex_2src (int bytemode
, int sizeflag
)
16306 if (modrm
.mod
== 3)
16308 int reg
= modrm
.rm
;
16312 oappend (names_xmm
[reg
]);
16317 && (bytemode
== v_mode
|| bytemode
== v_swap_mode
))
16319 bytemode
= (prefixes
& PREFIX_DATA
) ? x_mode
: q_mode
;
16320 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16322 OP_E (bytemode
, sizeflag
);
16327 OP_Vex_2src_1 (int bytemode
, int sizeflag
)
16329 if (modrm
.mod
== 3)
16331 /* Skip mod/rm byte. */
16337 oappend (names_xmm
[vex
.register_specifier
]);
16339 OP_Vex_2src (bytemode
, sizeflag
);
16343 OP_Vex_2src_2 (int bytemode
, int sizeflag
)
16346 OP_Vex_2src (bytemode
, sizeflag
);
16348 oappend (names_xmm
[vex
.register_specifier
]);
16352 OP_EX_VexW (int bytemode
, int sizeflag
)
16360 /* Skip mod/rm byte. */
16365 reg
= get_vex_imm8 (sizeflag
, 0) >> 4;
16370 reg
= get_vex_imm8 (sizeflag
, 1) >> 4;
16373 OP_EX_VexReg (bytemode
, sizeflag
, reg
);
16377 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16378 int sizeflag ATTRIBUTE_UNUSED
)
16380 /* Skip the immediate byte and check for invalid bits. */
16381 FETCH_DATA (the_info
, codep
+ 1);
16382 if (*codep
++ & 0xf)
16387 OP_REG_VexI4 (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16390 const char **names
;
16392 FETCH_DATA (the_info
, codep
+ 1);
16395 if (bytemode
!= x_mode
)
16402 if (reg
> 7 && address_mode
!= mode_64bit
)
16405 switch (vex
.length
)
16416 oappend (names
[reg
]);
16420 OP_XMM_VexW (int bytemode
, int sizeflag
)
16422 /* Turn off the REX.W bit since it is used for swapping operands
16425 OP_XMM (bytemode
, sizeflag
);
16429 OP_EX_Vex (int bytemode
, int sizeflag
)
16431 if (modrm
.mod
!= 3)
16433 if (vex
.register_specifier
!= 0)
16437 OP_EX (bytemode
, sizeflag
);
16441 OP_XMM_Vex (int bytemode
, int sizeflag
)
16443 if (modrm
.mod
!= 3)
16445 if (vex
.register_specifier
!= 0)
16449 OP_XMM (bytemode
, sizeflag
);
16453 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16455 switch (vex
.length
)
16458 mnemonicendp
= stpcpy (obuf
, "vzeroupper");
16461 mnemonicendp
= stpcpy (obuf
, "vzeroall");
16468 static struct op vex_cmp_op
[] =
16470 { STRING_COMMA_LEN ("eq") },
16471 { STRING_COMMA_LEN ("lt") },
16472 { STRING_COMMA_LEN ("le") },
16473 { STRING_COMMA_LEN ("unord") },
16474 { STRING_COMMA_LEN ("neq") },
16475 { STRING_COMMA_LEN ("nlt") },
16476 { STRING_COMMA_LEN ("nle") },
16477 { STRING_COMMA_LEN ("ord") },
16478 { STRING_COMMA_LEN ("eq_uq") },
16479 { STRING_COMMA_LEN ("nge") },
16480 { STRING_COMMA_LEN ("ngt") },
16481 { STRING_COMMA_LEN ("false") },
16482 { STRING_COMMA_LEN ("neq_oq") },
16483 { STRING_COMMA_LEN ("ge") },
16484 { STRING_COMMA_LEN ("gt") },
16485 { STRING_COMMA_LEN ("true") },
16486 { STRING_COMMA_LEN ("eq_os") },
16487 { STRING_COMMA_LEN ("lt_oq") },
16488 { STRING_COMMA_LEN ("le_oq") },
16489 { STRING_COMMA_LEN ("unord_s") },
16490 { STRING_COMMA_LEN ("neq_us") },
16491 { STRING_COMMA_LEN ("nlt_uq") },
16492 { STRING_COMMA_LEN ("nle_uq") },
16493 { STRING_COMMA_LEN ("ord_s") },
16494 { STRING_COMMA_LEN ("eq_us") },
16495 { STRING_COMMA_LEN ("nge_uq") },
16496 { STRING_COMMA_LEN ("ngt_uq") },
16497 { STRING_COMMA_LEN ("false_os") },
16498 { STRING_COMMA_LEN ("neq_os") },
16499 { STRING_COMMA_LEN ("ge_oq") },
16500 { STRING_COMMA_LEN ("gt_oq") },
16501 { STRING_COMMA_LEN ("true_us") },
16505 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16507 unsigned int cmp_type
;
16509 FETCH_DATA (the_info
, codep
+ 1);
16510 cmp_type
= *codep
++ & 0xff;
16511 if (cmp_type
< ARRAY_SIZE (vex_cmp_op
))
16514 char *p
= mnemonicendp
- 2;
16518 sprintf (p
, "%s%s", vex_cmp_op
[cmp_type
].name
, suffix
);
16519 mnemonicendp
+= vex_cmp_op
[cmp_type
].len
;
16523 /* We have a reserved extension byte. Output it directly. */
16524 scratchbuf
[0] = '$';
16525 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16526 oappend_maybe_intel (scratchbuf
);
16527 scratchbuf
[0] = '\0';
16532 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16533 int sizeflag ATTRIBUTE_UNUSED
)
16535 unsigned int cmp_type
;
16540 FETCH_DATA (the_info
, codep
+ 1);
16541 cmp_type
= *codep
++ & 0xff;
16542 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16543 If it's the case, print suffix, otherwise - print the immediate. */
16544 if (cmp_type
< ARRAY_SIZE (simd_cmp_op
)
16549 char *p
= mnemonicendp
- 2;
16551 /* vpcmp* can have both one- and two-lettered suffix. */
16565 sprintf (p
, "%s%s", simd_cmp_op
[cmp_type
].name
, suffix
);
16566 mnemonicendp
+= simd_cmp_op
[cmp_type
].len
;
16570 /* We have a reserved extension byte. Output it directly. */
16571 scratchbuf
[0] = '$';
16572 print_operand_value (scratchbuf
+ 1, 1, cmp_type
);
16573 oappend_maybe_intel (scratchbuf
);
16574 scratchbuf
[0] = '\0';
16578 static const struct op pclmul_op
[] =
16580 { STRING_COMMA_LEN ("lql") },
16581 { STRING_COMMA_LEN ("hql") },
16582 { STRING_COMMA_LEN ("lqh") },
16583 { STRING_COMMA_LEN ("hqh") }
16587 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED
,
16588 int sizeflag ATTRIBUTE_UNUSED
)
16590 unsigned int pclmul_type
;
16592 FETCH_DATA (the_info
, codep
+ 1);
16593 pclmul_type
= *codep
++ & 0xff;
16594 switch (pclmul_type
)
16605 if (pclmul_type
< ARRAY_SIZE (pclmul_op
))
16608 char *p
= mnemonicendp
- 3;
16613 sprintf (p
, "%s%s", pclmul_op
[pclmul_type
].name
, suffix
);
16614 mnemonicendp
+= pclmul_op
[pclmul_type
].len
;
16618 /* We have a reserved extension byte. Output it directly. */
16619 scratchbuf
[0] = '$';
16620 print_operand_value (scratchbuf
+ 1, 1, pclmul_type
);
16621 oappend_maybe_intel (scratchbuf
);
16622 scratchbuf
[0] = '\0';
16627 MOVBE_Fixup (int bytemode
, int sizeflag
)
16629 /* Add proper suffix to "movbe". */
16630 char *p
= mnemonicendp
;
16639 if (sizeflag
& SUFFIX_ALWAYS
)
16645 if (sizeflag
& DFLAG
)
16649 used_prefixes
|= (prefixes
& PREFIX_DATA
);
16654 oappend (INTERNAL_DISASSEMBLER_ERROR
);
16661 OP_M (bytemode
, sizeflag
);
16665 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16668 const char **names
;
16670 /* Skip mod/rm byte. */
16684 oappend (names
[reg
]);
16688 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED
, int sizeflag ATTRIBUTE_UNUSED
)
16690 const char **names
;
16697 oappend (names
[vex
.register_specifier
]);
16701 OP_Mask (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16704 || bytemode
!= mask_mode
)
16708 if ((rex
& REX_R
) != 0 || !vex
.r
)
16714 oappend (names_mask
[modrm
.reg
]);
16718 OP_Rounding (int bytemode
, int sizeflag ATTRIBUTE_UNUSED
)
16721 || (bytemode
!= evex_rounding_mode
16722 && bytemode
!= evex_sae_mode
))
16724 if (modrm
.mod
== 3 && vex
.b
)
16727 case evex_rounding_mode
:
16728 oappend (names_rounding
[vex
.ll
]);
16730 case evex_sae_mode
: