opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2019 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40
  41 #include <setjmp.h>
  42
  43 static int print_insn (bfd_vma, disassemble_info *);
  44 static void dofloat (int);
  45 static void OP_ST (int, int);
  46 static void OP_STi (int, int);
  47 static int putop (const char *, int);
  48 static void oappend (const char *);
  49 static void append_seg (void);
  50 static void OP_indirE (int, int);
  51 static void print_operand_value (char *, int, bfd_vma);
  52 static void OP_E_register (int, int);
  53 static void OP_E_memory (int, int);
  54 static void print_displacement (char *, bfd_vma);
  55 static void OP_E (int, int);
  56 static void OP_G (int, int);
  57 static bfd_vma get64 (void);
  58 static bfd_signed_vma get32 (void);
  59 static bfd_signed_vma get32s (void);
  60 static int get16 (void);
  61 static void set_op (bfd_vma, int);
  62 static void OP_Skip_MODRM (int, int);
  63 static void OP_REG (int, int);
  64 static void OP_IMREG (int, int);
  65 static void OP_I (int, int);
  66 static void OP_I64 (int, int);
  67 static void OP_sI (int, int);
  68 static void OP_J (int, int);
  69 static void OP_SEG (int, int);
  70 static void OP_DIR (int, int);
  71 static void OP_OFF (int, int);
  72 static void OP_OFF64 (int, int);
  73 static void ptr_reg (int, int);
  74 static void OP_ESreg (int, int);
  75 static void OP_DSreg (int, int);
  76 static void OP_C (int, int);
  77 static void OP_D (int, int);
  78 static void OP_T (int, int);
  79 static void OP_R (int, int);
  80 static void OP_MMX (int, int);
  81 static void OP_XMM (int, int);
  82 static void OP_EM (int, int);
  83 static void OP_EX (int, int);
  84 static void OP_EMC (int,int);
  85 static void OP_MXC (int,int);
  86 static void OP_MS (int, int);
  87 static void OP_XS (int, int);
  88 static void OP_M (int, int);
  89 static void OP_VEX (int, int);
  90 static void OP_EX_Vex (int, int);
  91 static void OP_EX_VexW (int, int);
  92 static void OP_EX_VexImmW (int, int);
  93 static void OP_XMM_Vex (int, int);
  94 static void OP_XMM_VexW (int, int);
  95 static void OP_Rounding (int, int);
  96 static void OP_REG_VexI4 (int, int);
  97 static void PCLMUL_Fixup (int, int);
  98 static void VCMP_Fixup (int, int);
  99 static void VPCMP_Fixup (int, int);
 100 static void VPCOM_Fixup (int, int);
 101 static void OP_0f07 (int, int);
 102 static void OP_Monitor (int, int);
 103 static void OP_Mwait (int, int);
 104 static void OP_Mwaitx (int, int);
 105 static void NOP_Fixup1 (int, int);
 106 static void NOP_Fixup2 (int, int);
 107 static void OP_3DNowSuffix (int, int);
 108 static void CMP_Fixup (int, int);
 109 static void BadOp (void);
 110 static void REP_Fixup (int, int);
 111 static void BND_Fixup (int, int);
 112 static void NOTRACK_Fixup (int, int);
 113 static void HLE_Fixup1 (int, int);
 114 static void HLE_Fixup2 (int, int);
 115 static void HLE_Fixup3 (int, int);
 116 static void CMPXCHG8B_Fixup (int, int);
 117 static void XMM_Fixup (int, int);
 118 static void CRC32_Fixup (int, int);
 119 static void FXSAVE_Fixup (int, int);
 120 static void PCMPESTR_Fixup (int, int);
 121 static void OP_LWPCB_E (int, int);
 122 static void OP_LWP_E (int, int);
 123 static void OP_Vex_2src_1 (int, int);
 124 static void OP_Vex_2src_2 (int, int);
 125
 126 static void MOVBE_Fixup (int, int);
 127
 128 static void OP_Mask (int, int);
 129
 130 struct dis_private {
 131   /* Points to first byte not fetched.  */
 132   bfd_byte *max_fetched;
 133   bfd_byte the_buffer[MAX_MNEM_SIZE];
 134   bfd_vma insn_start;
 135   int orig_sizeflag;
 136   OPCODES_SIGJMP_BUF bailout;
 137 };
 138
 139 enum address_mode
 140 {
 141   mode_16bit,
 142   mode_32bit,
 143   mode_64bit
 144 };
 145
 146 enum address_mode address_mode;
 147
 148 /* Flags for the prefixes for the current instruction.  See below.  */
 149 static int prefixes;
 150
 151 /* REX prefix the current instruction.  See below.  */
 152 static int rex;
 153 /* Bits of REX we've already used.  */
 154 static int rex_used;
 155 /* REX bits in original REX prefix ignored.  */
 156 static int rex_ignored;
 157 /* Mark parts used in the REX prefix.  When we are testing for
 158    empty prefix (for 8bit register REX extension), just mask it
 159    out.  Otherwise test for REX bit is excuse for existence of REX
 160    only in case value is nonzero.  */
 161 #define USED_REX(value)                                 \
 162   {                                                     \
 163     if (value)                                          \
 164       {                                                 \
 165         if ((rex & value))                              \
 166           rex_used |= (value) | REX_OPCODE;             \
 167       }                                                 \
 168     else                                                \
 169       rex_used |= REX_OPCODE;                           \
 170   }
 171
 172 /* Flags for prefixes which we somehow handled when printing the
 173    current instruction.  */
 174 static int used_prefixes;
 175
 176 /* Flags stored in PREFIXES.  */
 177 #define PREFIX_REPZ 1
 178 #define PREFIX_REPNZ 2
 179 #define PREFIX_LOCK 4
 180 #define PREFIX_CS 8
 181 #define PREFIX_SS 0x10
 182 #define PREFIX_DS 0x20
 183 #define PREFIX_ES 0x40
 184 #define PREFIX_FS 0x80
 185 #define PREFIX_GS 0x100
 186 #define PREFIX_DATA 0x200
 187 #define PREFIX_ADDR 0x400
 188 #define PREFIX_FWAIT 0x800
 189
 190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 191    to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
 192    on error.  */
 193 #define FETCH_DATA(info, addr) \
 194   ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
 195    ? 1 : fetch_data ((info), (addr)))
 196
 197 static int
 198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
 199 {
 200   int status;
 201   struct dis_private *priv = (struct dis_private *) info->private_data;
 202   bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
 203
 204   if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
 205     status = (*info->read_memory_func) (start,
 206                                         priv->max_fetched,
 207                                         addr - priv->max_fetched,
 208                                         info);
 209   else
 210     status = -1;
 211   if (status != 0)
 212     {
 213       /* If we did manage to read at least one byte, then
 214          print_insn_i386 will do something sensible.  Otherwise, print
 215          an error.  We do that here because this is where we know
 216          STATUS.  */
 217       if (priv->max_fetched == priv->the_buffer)
 218         (*info->memory_error_func) (status, start, info);
 219       OPCODES_SIGLONGJMP (priv->bailout, 1);
 220     }
 221   else
 222     priv->max_fetched = addr;
 223   return 1;
 224 }
 225
 226 /* Possible values for prefix requirement.  */
 227 #define PREFIX_IGNORED_SHIFT    16
 228 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 229 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 230 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 231 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 232 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 233
 234 /* Opcode prefixes.  */
 235 #define PREFIX_OPCODE           (PREFIX_REPZ \
 236                                  | PREFIX_REPNZ \
 237                                  | PREFIX_DATA)
 238
 239 /* Prefixes ignored.  */
 240 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 241                                  | PREFIX_IGNORED_REPNZ \
 242                                  | PREFIX_IGNORED_DATA)
 243
 244 #define XX { NULL, 0 }
 245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 246
 247 #define Eb { OP_E, b_mode }
 248 #define Ebnd { OP_E, bnd_mode }
 249 #define EbS { OP_E, b_swap_mode }
 250 #define EbndS { OP_E, bnd_swap_mode }
 251 #define Ev { OP_E, v_mode }
 252 #define Eva { OP_E, va_mode }
 253 #define Ev_bnd { OP_E, v_bnd_mode }
 254 #define EvS { OP_E, v_swap_mode }
 255 #define Ed { OP_E, d_mode }
 256 #define Edq { OP_E, dq_mode }
 257 #define Edqw { OP_E, dqw_mode }
 258 #define Edqb { OP_E, dqb_mode }
 259 #define Edb { OP_E, db_mode }
 260 #define Edw { OP_E, dw_mode }
 261 #define Edqd { OP_E, dqd_mode }
 262 #define Eq { OP_E, q_mode }
 263 #define indirEv { OP_indirE, indir_v_mode }
 264 #define indirEp { OP_indirE, f_mode }
 265 #define stackEv { OP_E, stack_v_mode }
 266 #define Em { OP_E, m_mode }
 267 #define Ew { OP_E, w_mode }
 268 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 269 #define Ma { OP_M, a_mode }
 270 #define Mb { OP_M, b_mode }
 271 #define Md { OP_M, d_mode }
 272 #define Mo { OP_M, o_mode }
 273 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 274 #define Mq { OP_M, q_mode }
 275 #define Mv_bnd { OP_M, v_bndmk_mode }
 276 #define Mx { OP_M, x_mode }
 277 #define Mxmm { OP_M, xmm_mode }
 278 #define Gb { OP_G, b_mode }
 279 #define Gbnd { OP_G, bnd_mode }
 280 #define Gv { OP_G, v_mode }
 281 #define Gd { OP_G, d_mode }
 282 #define Gdq { OP_G, dq_mode }
 283 #define Gm { OP_G, m_mode }
 284 #define Gva { OP_G, va_mode }
 285 #define Gw { OP_G, w_mode }
 286 #define Rd { OP_R, d_mode }
 287 #define Rdq { OP_R, dq_mode }
 288 #define Rm { OP_R, m_mode }
 289 #define Ib { OP_I, b_mode }
 290 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 292 #define Iv { OP_I, v_mode }
 293 #define sIv { OP_sI, v_mode }
 294 #define Iv64 { OP_I64, v_mode }
 295 #define Id { OP_I, d_mode }
 296 #define Iw { OP_I, w_mode }
 297 #define I1 { OP_I, const_1_mode }
 298 #define Jb { OP_J, b_mode }
 299 #define Jv { OP_J, v_mode }
 300 #define Cm { OP_C, m_mode }
 301 #define Dm { OP_D, m_mode }
 302 #define Td { OP_T, d_mode }
 303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 304
 305 #define RMeAX { OP_REG, eAX_reg }
 306 #define RMeBX { OP_REG, eBX_reg }
 307 #define RMeCX { OP_REG, eCX_reg }
 308 #define RMeDX { OP_REG, eDX_reg }
 309 #define RMeSP { OP_REG, eSP_reg }
 310 #define RMeBP { OP_REG, eBP_reg }
 311 #define RMeSI { OP_REG, eSI_reg }
 312 #define RMeDI { OP_REG, eDI_reg }
 313 #define RMrAX { OP_REG, rAX_reg }
 314 #define RMrBX { OP_REG, rBX_reg }
 315 #define RMrCX { OP_REG, rCX_reg }
 316 #define RMrDX { OP_REG, rDX_reg }
 317 #define RMrSP { OP_REG, rSP_reg }
 318 #define RMrBP { OP_REG, rBP_reg }
 319 #define RMrSI { OP_REG, rSI_reg }
 320 #define RMrDI { OP_REG, rDI_reg }
 321 #define RMAL { OP_REG, al_reg }
 322 #define RMCL { OP_REG, cl_reg }
 323 #define RMDL { OP_REG, dl_reg }
 324 #define RMBL { OP_REG, bl_reg }
 325 #define RMAH { OP_REG, ah_reg }
 326 #define RMCH { OP_REG, ch_reg }
 327 #define RMDH { OP_REG, dh_reg }
 328 #define RMBH { OP_REG, bh_reg }
 329 #define RMAX { OP_REG, ax_reg }
 330 #define RMDX { OP_REG, dx_reg }
 331
 332 #define eAX { OP_IMREG, eAX_reg }
 333 #define eBX { OP_IMREG, eBX_reg }
 334 #define eCX { OP_IMREG, eCX_reg }
 335 #define eDX { OP_IMREG, eDX_reg }
 336 #define eSP { OP_IMREG, eSP_reg }
 337 #define eBP { OP_IMREG, eBP_reg }
 338 #define eSI { OP_IMREG, eSI_reg }
 339 #define eDI { OP_IMREG, eDI_reg }
 340 #define AL { OP_IMREG, al_reg }
 341 #define CL { OP_IMREG, cl_reg }
 342 #define DL { OP_IMREG, dl_reg }
 343 #define BL { OP_IMREG, bl_reg }
 344 #define AH { OP_IMREG, ah_reg }
 345 #define CH { OP_IMREG, ch_reg }
 346 #define DH { OP_IMREG, dh_reg }
 347 #define BH { OP_IMREG, bh_reg }
 348 #define AX { OP_IMREG, ax_reg }
 349 #define DX { OP_IMREG, dx_reg }
 350 #define zAX { OP_IMREG, z_mode_ax_reg }
 351 #define indirDX { OP_IMREG, indir_dx_reg }
 352
 353 #define Sw { OP_SEG, w_mode }
 354 #define Sv { OP_SEG, v_mode }
 355 #define Ap { OP_DIR, 0 }
 356 #define Ob { OP_OFF64, b_mode }
 357 #define Ov { OP_OFF64, v_mode }
 358 #define Xb { OP_DSreg, eSI_reg }
 359 #define Xv { OP_DSreg, eSI_reg }
 360 #define Xz { OP_DSreg, eSI_reg }
 361 #define Yb { OP_ESreg, eDI_reg }
 362 #define Yv { OP_ESreg, eDI_reg }
 363 #define DSBX { OP_DSreg, eBX_reg }
 364
 365 #define es { OP_REG, es_reg }
 366 #define ss { OP_REG, ss_reg }
 367 #define cs { OP_REG, cs_reg }
 368 #define ds { OP_REG, ds_reg }
 369 #define fs { OP_REG, fs_reg }
 370 #define gs { OP_REG, gs_reg }
 371
 372 #define MX { OP_MMX, 0 }
 373 #define XM { OP_XMM, 0 }
 374 #define XMScalar { OP_XMM, scalar_mode }
 375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 376 #define XMM { OP_XMM, xmm_mode }
 377 #define XMxmmq { OP_XMM, xmmq_mode }
 378 #define EM { OP_EM, v_mode }
 379 #define EMS { OP_EM, v_swap_mode }
 380 #define EMd { OP_EM, d_mode }
 381 #define EMx { OP_EM, x_mode }
 382 #define EXbScalar { OP_EX, b_scalar_mode }
 383 #define EXw { OP_EX, w_mode }
 384 #define EXwScalar { OP_EX, w_scalar_mode }
 385 #define EXd { OP_EX, d_mode }
 386 #define EXdScalar { OP_EX, d_scalar_mode }
 387 #define EXdS { OP_EX, d_swap_mode }
 388 #define EXq { OP_EX, q_mode }
 389 #define EXqScalar { OP_EX, q_scalar_mode }
 390 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
 391 #define EXqS { OP_EX, q_swap_mode }
 392 #define EXx { OP_EX, x_mode }
 393 #define EXxS { OP_EX, x_swap_mode }
 394 #define EXxmm { OP_EX, xmm_mode }
 395 #define EXymm { OP_EX, ymm_mode }
 396 #define EXxmmq { OP_EX, xmmq_mode }
 397 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 398 #define EXxmm_mb { OP_EX, xmm_mb_mode }
 399 #define EXxmm_mw { OP_EX, xmm_mw_mode }
 400 #define EXxmm_md { OP_EX, xmm_md_mode }
 401 #define EXxmm_mq { OP_EX, xmm_mq_mode }
 402 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
 403 #define EXxmmdw { OP_EX, xmmdw_mode }
 404 #define EXxmmqd { OP_EX, xmmqd_mode }
 405 #define EXymmq { OP_EX, ymmq_mode }
 406 #define EXVexWdq { OP_EX, vex_w_dq_mode }
 407 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
 408 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 409 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 410 #define MS { OP_MS, v_mode }
 411 #define XS { OP_XS, v_mode }
 412 #define EMCq { OP_EMC, q_mode }
 413 #define MXC { OP_MXC, 0 }
 414 #define OPSUF { OP_3DNowSuffix, 0 }
 415 #define CMP { CMP_Fixup, 0 }
 416 #define XMM0 { XMM_Fixup, 0 }
 417 #define FXSAVE { FXSAVE_Fixup, 0 }
 418 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
 419 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
 420
 421 #define Vex { OP_VEX, vex_mode }
 422 #define VexScalar { OP_VEX, vex_scalar_mode }
 423 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 424 #define Vex128 { OP_VEX, vex128_mode }
 425 #define Vex256 { OP_VEX, vex256_mode }
 426 #define VexGdq { OP_VEX, dq_mode }
 427 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
 428 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
 429 #define EXVexW { OP_EX_VexW, x_mode }
 430 #define EXdVexW { OP_EX_VexW, d_mode }
 431 #define EXqVexW { OP_EX_VexW, q_mode }
 432 #define EXVexImmW { OP_EX_VexImmW, x_mode }
 433 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
 434 #define XMVexW { OP_XMM_VexW, 0 }
 435 #define XMVexI4 { OP_REG_VexI4, x_mode }
 436 #define PCLMUL { PCLMUL_Fixup, 0 }
 437 #define VCMP { VCMP_Fixup, 0 }
 438 #define VPCMP { VPCMP_Fixup, 0 }
 439 #define VPCOM { VPCOM_Fixup, 0 }
 440
 441 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 442 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 443 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 444
 445 #define XMask { OP_Mask, mask_mode }
 446 #define MaskG { OP_G, mask_mode }
 447 #define MaskE { OP_E, mask_mode }
 448 #define MaskBDE { OP_E, mask_bd_mode }
 449 #define MaskR { OP_R, mask_mode }
 450 #define MaskVex { OP_VEX, mask_mode }
 451
 452 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 453 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
 454 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 455 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
 456
 457 /* Used handle "rep" prefix for string instructions.  */
 458 #define Xbr { REP_Fixup, eSI_reg }
 459 #define Xvr { REP_Fixup, eSI_reg }
 460 #define Ybr { REP_Fixup, eDI_reg }
 461 #define Yvr { REP_Fixup, eDI_reg }
 462 #define Yzr { REP_Fixup, eDI_reg }
 463 #define indirDXr { REP_Fixup, indir_dx_reg }
 464 #define ALr { REP_Fixup, al_reg }
 465 #define eAXr { REP_Fixup, eAX_reg }
 466
 467 /* Used handle HLE prefix for lockable instructions.  */
 468 #define Ebh1 { HLE_Fixup1, b_mode }
 469 #define Evh1 { HLE_Fixup1, v_mode }
 470 #define Ebh2 { HLE_Fixup2, b_mode }
 471 #define Evh2 { HLE_Fixup2, v_mode }
 472 #define Ebh3 { HLE_Fixup3, b_mode }
 473 #define Evh3 { HLE_Fixup3, v_mode }
 474
 475 #define BND { BND_Fixup, 0 }
 476 #define NOTRACK { NOTRACK_Fixup, 0 }
 477
 478 #define cond_jump_flag { NULL, cond_jump_mode }
 479 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 480
 481 /* bits in sizeflag */
 482 #define SUFFIX_ALWAYS 4
 483 #define AFLAG 2
 484 #define DFLAG 1
 485
 486 enum
 487 {
 488   /* byte operand */
 489   b_mode = 1,
 490   /* byte operand with operand swapped */
 491   b_swap_mode,
 492   /* byte operand, sign extend like 'T' suffix */
 493   b_T_mode,
 494   /* operand size depends on prefixes */
 495   v_mode,
 496   /* operand size depends on prefixes with operand swapped */
 497   v_swap_mode,
 498   /* operand size depends on address prefix */
 499   va_mode,
 500   /* word operand */
 501   w_mode,
 502   /* double word operand  */
 503   d_mode,
 504   /* double word operand with operand swapped */
 505   d_swap_mode,
 506   /* quad word operand */
 507   q_mode,
 508   /* quad word operand with operand swapped */
 509   q_swap_mode,
 510   /* ten-byte operand */
 511   t_mode,
 512   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 513      broadcast enabled.  */
 514   x_mode,
 515   /* Similar to x_mode, but with different EVEX mem shifts.  */
 516   evex_x_gscat_mode,
 517   /* Similar to x_mode, but with disabled broadcast.  */
 518   evex_x_nobcst_mode,
 519   /* Similar to x_mode, but with operands swapped and disabled broadcast
 520      in EVEX.  */
 521   x_swap_mode,
 522   /* 16-byte XMM operand */
 523   xmm_mode,
 524   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 525      memory operand (depending on vector length).  Broadcast isn't
 526      allowed.  */
 527   xmmq_mode,
 528   /* Same as xmmq_mode, but broadcast is allowed.  */
 529   evex_half_bcst_xmmq_mode,
 530   /* XMM register or byte memory operand */
 531   xmm_mb_mode,
 532   /* XMM register or word memory operand */
 533   xmm_mw_mode,
 534   /* XMM register or double word memory operand */
 535   xmm_md_mode,
 536   /* XMM register or quad word memory operand */
 537   xmm_mq_mode,
 538   /* XMM register or double/quad word memory operand, depending on
 539      VEX.W.  */
 540   xmm_mdq_mode,
 541   /* 16-byte XMM, word, double word or quad word operand.  */
 542   xmmdw_mode,
 543   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 544   xmmqd_mode,
 545   /* 32-byte YMM operand */
 546   ymm_mode,
 547   /* quad word, ymmword or zmmword memory operand.  */
 548   ymmq_mode,
 549   /* 32-byte YMM or 16-byte word operand */
 550   ymmxmm_mode,
 551   /* d_mode in 32bit, q_mode in 64bit mode.  */
 552   m_mode,
 553   /* pair of v_mode operands */
 554   a_mode,
 555   cond_jump_mode,
 556   loop_jcxz_mode,
 557   v_bnd_mode,
 558   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 559   v_bndmk_mode,
 560   /* operand size depends on REX prefixes.  */
 561   dq_mode,
 562   /* registers like dq_mode, memory like w_mode.  */
 563   dqw_mode,
 564   /* bounds operand */
 565   bnd_mode,
 566   /* bounds operand with operand swapped */
 567   bnd_swap_mode,
 568   /* 4- or 6-byte pointer operand */
 569   f_mode,
 570   const_1_mode,
 571   /* v_mode for indirect branch opcodes.  */
 572   indir_v_mode,
 573   /* v_mode for stack-related opcodes.  */
 574   stack_v_mode,
 575   /* non-quad operand size depends on prefixes */
 576   z_mode,
 577   /* 16-byte operand */
 578   o_mode,
 579   /* registers like dq_mode, memory like b_mode.  */
 580   dqb_mode,
 581   /* registers like d_mode, memory like b_mode.  */
 582   db_mode,
 583   /* registers like d_mode, memory like w_mode.  */
 584   dw_mode,
 585   /* registers like dq_mode, memory like d_mode.  */
 586   dqd_mode,
 587   /* normal vex mode */
 588   vex_mode,
 589   /* 128bit vex mode */
 590   vex128_mode,
 591   /* 256bit vex mode */
 592   vex256_mode,
 593   /* operand size depends on the VEX.W bit.  */
 594   vex_w_dq_mode,
 595
 596   /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
 597   vex_vsib_d_w_dq_mode,
 598   /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
 599   vex_vsib_d_w_d_mode,
 600   /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
 601   vex_vsib_q_w_dq_mode,
 602   /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
 603   vex_vsib_q_w_d_mode,
 604
 605   /* scalar, ignore vector length.  */
 606   scalar_mode,
 607   /* like b_mode, ignore vector length.  */
 608   b_scalar_mode,
 609   /* like w_mode, ignore vector length.  */
 610   w_scalar_mode,
 611   /* like d_mode, ignore vector length.  */
 612   d_scalar_mode,
 613   /* like d_swap_mode, ignore vector length.  */
 614   d_scalar_swap_mode,
 615   /* like q_mode, ignore vector length.  */
 616   q_scalar_mode,
 617   /* like q_swap_mode, ignore vector length.  */
 618   q_scalar_swap_mode,
 619   /* like vex_mode, ignore vector length.  */
 620   vex_scalar_mode,
 621   /* like vex_w_dq_mode, ignore vector length.  */
 622   vex_scalar_w_dq_mode,
 623
 624   /* Static rounding.  */
 625   evex_rounding_mode,
 626   /* Static rounding, 64-bit mode only.  */
 627   evex_rounding_64_mode,
 628   /* Supress all exceptions.  */
 629   evex_sae_mode,
 630
 631   /* Mask register operand.  */
 632   mask_mode,
 633   /* Mask register operand.  */
 634   mask_bd_mode,
 635
 636   es_reg,
 637   cs_reg,
 638   ss_reg,
 639   ds_reg,
 640   fs_reg,
 641   gs_reg,
 642
 643   eAX_reg,
 644   eCX_reg,
 645   eDX_reg,
 646   eBX_reg,
 647   eSP_reg,
 648   eBP_reg,
 649   eSI_reg,
 650   eDI_reg,
 651
 652   al_reg,
 653   cl_reg,
 654   dl_reg,
 655   bl_reg,
 656   ah_reg,
 657   ch_reg,
 658   dh_reg,
 659   bh_reg,
 660
 661   ax_reg,
 662   cx_reg,
 663   dx_reg,
 664   bx_reg,
 665   sp_reg,
 666   bp_reg,
 667   si_reg,
 668   di_reg,
 669
 670   rAX_reg,
 671   rCX_reg,
 672   rDX_reg,
 673   rBX_reg,
 674   rSP_reg,
 675   rBP_reg,
 676   rSI_reg,
 677   rDI_reg,
 678
 679   z_mode_ax_reg,
 680   indir_dx_reg
 681 };
 682
 683 enum
 684 {
 685   FLOATCODE = 1,
 686   USE_REG_TABLE,
 687   USE_MOD_TABLE,
 688   USE_RM_TABLE,
 689   USE_PREFIX_TABLE,
 690   USE_X86_64_TABLE,
 691   USE_3BYTE_TABLE,
 692   USE_XOP_8F_TABLE,
 693   USE_VEX_C4_TABLE,
 694   USE_VEX_C5_TABLE,
 695   USE_VEX_LEN_TABLE,
 696   USE_VEX_W_TABLE,
 697   USE_EVEX_TABLE,
 698   USE_EVEX_LEN_TABLE
 699 };
 700
 701 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 702
 703 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 704 #define DIS386_PREFIX(T, I, P)          NULL, { { NULL, (T)}, { NULL,  (I) } }, P
 705 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 706 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 707 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 708 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 709 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 710 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 711 #define THREE_BYTE_TABLE_PREFIX(I, P)   DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
 712 #define XOP_8F_TABLE(I)         DIS386 (USE_XOP_8F_TABLE, (I))
 713 #define VEX_C4_TABLE(I)         DIS386 (USE_VEX_C4_TABLE, (I))
 714 #define VEX_C5_TABLE(I)         DIS386 (USE_VEX_C5_TABLE, (I))
 715 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 716 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 717 #define EVEX_TABLE(I)           DIS386 (USE_EVEX_TABLE, (I))
 718 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 719
 720 enum
 721 {
 722   REG_80 = 0,
 723   REG_81,
 724   REG_83,
 725   REG_8F,
 726   REG_C0,
 727   REG_C1,
 728   REG_C6,
 729   REG_C7,
 730   REG_D0,
 731   REG_D1,
 732   REG_D2,
 733   REG_D3,
 734   REG_F6,
 735   REG_F7,
 736   REG_FE,
 737   REG_FF,
 738   REG_0F00,
 739   REG_0F01,
 740   REG_0F0D,
 741   REG_0F18,
 742   REG_0F1C_P_0_MOD_0,
 743   REG_0F1E_P_1_MOD_3,
 744   REG_0F71,
 745   REG_0F72,
 746   REG_0F73,
 747   REG_0FA6,
 748   REG_0FA7,
 749   REG_0FAE,
 750   REG_0FBA,
 751   REG_0FC7,
 752   REG_VEX_0F71,
 753   REG_VEX_0F72,
 754   REG_VEX_0F73,
 755   REG_VEX_0FAE,
 756   REG_VEX_0F38F3,
 757   REG_XOP_LWPCB,
 758   REG_XOP_LWP,
 759   REG_XOP_TBM_01,
 760   REG_XOP_TBM_02,
 761
 762   REG_EVEX_0F71,
 763   REG_EVEX_0F72,
 764   REG_EVEX_0F73,
 765   REG_EVEX_0F38C6,
 766   REG_EVEX_0F38C7
 767 };
 768
 769 enum
 770 {
 771   MOD_8D = 0,
 772   MOD_C6_REG_7,
 773   MOD_C7_REG_7,
 774   MOD_FF_REG_3,
 775   MOD_FF_REG_5,
 776   MOD_0F01_REG_0,
 777   MOD_0F01_REG_1,
 778   MOD_0F01_REG_2,
 779   MOD_0F01_REG_3,
 780   MOD_0F01_REG_5,
 781   MOD_0F01_REG_7,
 782   MOD_0F12_PREFIX_0,
 783   MOD_0F13,
 784   MOD_0F16_PREFIX_0,
 785   MOD_0F17,
 786   MOD_0F18_REG_0,
 787   MOD_0F18_REG_1,
 788   MOD_0F18_REG_2,
 789   MOD_0F18_REG_3,
 790   MOD_0F18_REG_4,
 791   MOD_0F18_REG_5,
 792   MOD_0F18_REG_6,
 793   MOD_0F18_REG_7,
 794   MOD_0F1A_PREFIX_0,
 795   MOD_0F1B_PREFIX_0,
 796   MOD_0F1B_PREFIX_1,
 797   MOD_0F1C_PREFIX_0,
 798   MOD_0F1E_PREFIX_1,
 799   MOD_0F24,
 800   MOD_0F26,
 801   MOD_0F2B_PREFIX_0,
 802   MOD_0F2B_PREFIX_1,
 803   MOD_0F2B_PREFIX_2,
 804   MOD_0F2B_PREFIX_3,
 805   MOD_0F51,
 806   MOD_0F71_REG_2,
 807   MOD_0F71_REG_4,
 808   MOD_0F71_REG_6,
 809   MOD_0F72_REG_2,
 810   MOD_0F72_REG_4,
 811   MOD_0F72_REG_6,
 812   MOD_0F73_REG_2,
 813   MOD_0F73_REG_3,
 814   MOD_0F73_REG_6,
 815   MOD_0F73_REG_7,
 816   MOD_0FAE_REG_0,
 817   MOD_0FAE_REG_1,
 818   MOD_0FAE_REG_2,
 819   MOD_0FAE_REG_3,
 820   MOD_0FAE_REG_4,
 821   MOD_0FAE_REG_5,
 822   MOD_0FAE_REG_6,
 823   MOD_0FAE_REG_7,
 824   MOD_0FB2,
 825   MOD_0FB4,
 826   MOD_0FB5,
 827   MOD_0FC3,
 828   MOD_0FC7_REG_3,
 829   MOD_0FC7_REG_4,
 830   MOD_0FC7_REG_5,
 831   MOD_0FC7_REG_6,
 832   MOD_0FC7_REG_7,
 833   MOD_0FD7,
 834   MOD_0FE7_PREFIX_2,
 835   MOD_0FF0_PREFIX_3,
 836   MOD_0F382A_PREFIX_2,
 837   MOD_0F38F5_PREFIX_2,
 838   MOD_0F38F6_PREFIX_0,
 839   MOD_0F38F8_PREFIX_1,
 840   MOD_0F38F8_PREFIX_2,
 841   MOD_0F38F8_PREFIX_3,
 842   MOD_0F38F9_PREFIX_0,
 843   MOD_62_32BIT,
 844   MOD_C4_32BIT,
 845   MOD_C5_32BIT,
 846   MOD_VEX_0F12_PREFIX_0,
 847   MOD_VEX_0F13,
 848   MOD_VEX_0F16_PREFIX_0,
 849   MOD_VEX_0F17,
 850   MOD_VEX_0F2B,
 851   MOD_VEX_W_0_0F41_P_0_LEN_1,
 852   MOD_VEX_W_1_0F41_P_0_LEN_1,
 853   MOD_VEX_W_0_0F41_P_2_LEN_1,
 854   MOD_VEX_W_1_0F41_P_2_LEN_1,
 855   MOD_VEX_W_0_0F42_P_0_LEN_1,
 856   MOD_VEX_W_1_0F42_P_0_LEN_1,
 857   MOD_VEX_W_0_0F42_P_2_LEN_1,
 858   MOD_VEX_W_1_0F42_P_2_LEN_1,
 859   MOD_VEX_W_0_0F44_P_0_LEN_1,
 860   MOD_VEX_W_1_0F44_P_0_LEN_1,
 861   MOD_VEX_W_0_0F44_P_2_LEN_1,
 862   MOD_VEX_W_1_0F44_P_2_LEN_1,
 863   MOD_VEX_W_0_0F45_P_0_LEN_1,
 864   MOD_VEX_W_1_0F45_P_0_LEN_1,
 865   MOD_VEX_W_0_0F45_P_2_LEN_1,
 866   MOD_VEX_W_1_0F45_P_2_LEN_1,
 867   MOD_VEX_W_0_0F46_P_0_LEN_1,
 868   MOD_VEX_W_1_0F46_P_0_LEN_1,
 869   MOD_VEX_W_0_0F46_P_2_LEN_1,
 870   MOD_VEX_W_1_0F46_P_2_LEN_1,
 871   MOD_VEX_W_0_0F47_P_0_LEN_1,
 872   MOD_VEX_W_1_0F47_P_0_LEN_1,
 873   MOD_VEX_W_0_0F47_P_2_LEN_1,
 874   MOD_VEX_W_1_0F47_P_2_LEN_1,
 875   MOD_VEX_W_0_0F4A_P_0_LEN_1,
 876   MOD_VEX_W_1_0F4A_P_0_LEN_1,
 877   MOD_VEX_W_0_0F4A_P_2_LEN_1,
 878   MOD_VEX_W_1_0F4A_P_2_LEN_1,
 879   MOD_VEX_W_0_0F4B_P_0_LEN_1,
 880   MOD_VEX_W_1_0F4B_P_0_LEN_1,
 881   MOD_VEX_W_0_0F4B_P_2_LEN_1,
 882   MOD_VEX_0F50,
 883   MOD_VEX_0F71_REG_2,
 884   MOD_VEX_0F71_REG_4,
 885   MOD_VEX_0F71_REG_6,
 886   MOD_VEX_0F72_REG_2,
 887   MOD_VEX_0F72_REG_4,
 888   MOD_VEX_0F72_REG_6,
 889   MOD_VEX_0F73_REG_2,
 890   MOD_VEX_0F73_REG_3,
 891   MOD_VEX_0F73_REG_6,
 892   MOD_VEX_0F73_REG_7,
 893   MOD_VEX_W_0_0F91_P_0_LEN_0,
 894   MOD_VEX_W_1_0F91_P_0_LEN_0,
 895   MOD_VEX_W_0_0F91_P_2_LEN_0,
 896   MOD_VEX_W_1_0F91_P_2_LEN_0,
 897   MOD_VEX_W_0_0F92_P_0_LEN_0,
 898   MOD_VEX_W_0_0F92_P_2_LEN_0,
 899   MOD_VEX_0F92_P_3_LEN_0,
 900   MOD_VEX_W_0_0F93_P_0_LEN_0,
 901   MOD_VEX_W_0_0F93_P_2_LEN_0,
 902   MOD_VEX_0F93_P_3_LEN_0,
 903   MOD_VEX_W_0_0F98_P_0_LEN_0,
 904   MOD_VEX_W_1_0F98_P_0_LEN_0,
 905   MOD_VEX_W_0_0F98_P_2_LEN_0,
 906   MOD_VEX_W_1_0F98_P_2_LEN_0,
 907   MOD_VEX_W_0_0F99_P_0_LEN_0,
 908   MOD_VEX_W_1_0F99_P_0_LEN_0,
 909   MOD_VEX_W_0_0F99_P_2_LEN_0,
 910   MOD_VEX_W_1_0F99_P_2_LEN_0,
 911   MOD_VEX_0FAE_REG_2,
 912   MOD_VEX_0FAE_REG_3,
 913   MOD_VEX_0FD7_PREFIX_2,
 914   MOD_VEX_0FE7_PREFIX_2,
 915   MOD_VEX_0FF0_PREFIX_3,
 916   MOD_VEX_0F381A_PREFIX_2,
 917   MOD_VEX_0F382A_PREFIX_2,
 918   MOD_VEX_0F382C_PREFIX_2,
 919   MOD_VEX_0F382D_PREFIX_2,
 920   MOD_VEX_0F382E_PREFIX_2,
 921   MOD_VEX_0F382F_PREFIX_2,
 922   MOD_VEX_0F385A_PREFIX_2,
 923   MOD_VEX_0F388C_PREFIX_2,
 924   MOD_VEX_0F388E_PREFIX_2,
 925   MOD_VEX_W_0_0F3A30_P_2_LEN_0,
 926   MOD_VEX_W_1_0F3A30_P_2_LEN_0,
 927   MOD_VEX_W_0_0F3A31_P_2_LEN_0,
 928   MOD_VEX_W_1_0F3A31_P_2_LEN_0,
 929   MOD_VEX_W_0_0F3A32_P_2_LEN_0,
 930   MOD_VEX_W_1_0F3A32_P_2_LEN_0,
 931   MOD_VEX_W_0_0F3A33_P_2_LEN_0,
 932   MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 933
 934   MOD_EVEX_0F12_PREFIX_0,
 935   MOD_EVEX_0F16_PREFIX_0,
 936   MOD_EVEX_0F38C6_REG_1,
 937   MOD_EVEX_0F38C6_REG_2,
 938   MOD_EVEX_0F38C6_REG_5,
 939   MOD_EVEX_0F38C6_REG_6,
 940   MOD_EVEX_0F38C7_REG_1,
 941   MOD_EVEX_0F38C7_REG_2,
 942   MOD_EVEX_0F38C7_REG_5,
 943   MOD_EVEX_0F38C7_REG_6
 944 };
 945
 946 enum
 947 {
 948   RM_C6_REG_7 = 0,
 949   RM_C7_REG_7,
 950   RM_0F01_REG_0,
 951   RM_0F01_REG_1,
 952   RM_0F01_REG_2,
 953   RM_0F01_REG_3,
 954   RM_0F01_REG_5_MOD_3,
 955   RM_0F01_REG_7_MOD_3,
 956   RM_0F1E_P_1_MOD_3_REG_7,
 957   RM_0FAE_REG_6_MOD_3_P_0,
 958   RM_0FAE_REG_7_MOD_3,
 959 };
 960
 961 enum
 962 {
 963   PREFIX_90 = 0,
 964   PREFIX_0F01_REG_5_MOD_0,
 965   PREFIX_0F01_REG_5_MOD_3_RM_0,
 966   PREFIX_0F01_REG_5_MOD_3_RM_2,
 967   PREFIX_0F09,
 968   PREFIX_0F10,
 969   PREFIX_0F11,
 970   PREFIX_0F12,
 971   PREFIX_0F16,
 972   PREFIX_0F1A,
 973   PREFIX_0F1B,
 974   PREFIX_0F1C,
 975   PREFIX_0F1E,
 976   PREFIX_0F2A,
 977   PREFIX_0F2B,
 978   PREFIX_0F2C,
 979   PREFIX_0F2D,
 980   PREFIX_0F2E,
 981   PREFIX_0F2F,
 982   PREFIX_0F51,
 983   PREFIX_0F52,
 984   PREFIX_0F53,
 985   PREFIX_0F58,
 986   PREFIX_0F59,
 987   PREFIX_0F5A,
 988   PREFIX_0F5B,
 989   PREFIX_0F5C,
 990   PREFIX_0F5D,
 991   PREFIX_0F5E,
 992   PREFIX_0F5F,
 993   PREFIX_0F60,
 994   PREFIX_0F61,
 995   PREFIX_0F62,
 996   PREFIX_0F6C,
 997   PREFIX_0F6D,
 998   PREFIX_0F6F,
 999   PREFIX_0F70,
1000   PREFIX_0F73_REG_3,
1001   PREFIX_0F73_REG_7,
1002   PREFIX_0F78,
1003   PREFIX_0F79,
1004   PREFIX_0F7C,
1005   PREFIX_0F7D,
1006   PREFIX_0F7E,
1007   PREFIX_0F7F,
1008   PREFIX_0FAE_REG_0_MOD_3,
1009   PREFIX_0FAE_REG_1_MOD_3,
1010   PREFIX_0FAE_REG_2_MOD_3,
1011   PREFIX_0FAE_REG_3_MOD_3,
1012   PREFIX_0FAE_REG_4_MOD_0,
1013   PREFIX_0FAE_REG_4_MOD_3,
1014   PREFIX_0FAE_REG_5_MOD_0,
1015   PREFIX_0FAE_REG_5_MOD_3,
1016   PREFIX_0FAE_REG_6_MOD_0,
1017   PREFIX_0FAE_REG_6_MOD_3,
1018   PREFIX_0FAE_REG_7_MOD_0,
1019   PREFIX_0FB8,
1020   PREFIX_0FBC,
1021   PREFIX_0FBD,
1022   PREFIX_0FC2,
1023   PREFIX_0FC3_MOD_0,
1024   PREFIX_0FC7_REG_6_MOD_0,
1025   PREFIX_0FC7_REG_6_MOD_3,
1026   PREFIX_0FC7_REG_7_MOD_3,
1027   PREFIX_0FD0,
1028   PREFIX_0FD6,
1029   PREFIX_0FE6,
1030   PREFIX_0FE7,
1031   PREFIX_0FF0,
1032   PREFIX_0FF7,
1033   PREFIX_0F3810,
1034   PREFIX_0F3814,
1035   PREFIX_0F3815,
1036   PREFIX_0F3817,
1037   PREFIX_0F3820,
1038   PREFIX_0F3821,
1039   PREFIX_0F3822,
1040   PREFIX_0F3823,
1041   PREFIX_0F3824,
1042   PREFIX_0F3825,
1043   PREFIX_0F3828,
1044   PREFIX_0F3829,
1045   PREFIX_0F382A,
1046   PREFIX_0F382B,
1047   PREFIX_0F3830,
1048   PREFIX_0F3831,
1049   PREFIX_0F3832,
1050   PREFIX_0F3833,
1051   PREFIX_0F3834,
1052   PREFIX_0F3835,
1053   PREFIX_0F3837,
1054   PREFIX_0F3838,
1055   PREFIX_0F3839,
1056   PREFIX_0F383A,
1057   PREFIX_0F383B,
1058   PREFIX_0F383C,
1059   PREFIX_0F383D,
1060   PREFIX_0F383E,
1061   PREFIX_0F383F,
1062   PREFIX_0F3840,
1063   PREFIX_0F3841,
1064   PREFIX_0F3880,
1065   PREFIX_0F3881,
1066   PREFIX_0F3882,
1067   PREFIX_0F38C8,
1068   PREFIX_0F38C9,
1069   PREFIX_0F38CA,
1070   PREFIX_0F38CB,
1071   PREFIX_0F38CC,
1072   PREFIX_0F38CD,
1073   PREFIX_0F38CF,
1074   PREFIX_0F38DB,
1075   PREFIX_0F38DC,
1076   PREFIX_0F38DD,
1077   PREFIX_0F38DE,
1078   PREFIX_0F38DF,
1079   PREFIX_0F38F0,
1080   PREFIX_0F38F1,
1081   PREFIX_0F38F5,
1082   PREFIX_0F38F6,
1083   PREFIX_0F38F8,
1084   PREFIX_0F38F9,
1085   PREFIX_0F3A08,
1086   PREFIX_0F3A09,
1087   PREFIX_0F3A0A,
1088   PREFIX_0F3A0B,
1089   PREFIX_0F3A0C,
1090   PREFIX_0F3A0D,
1091   PREFIX_0F3A0E,
1092   PREFIX_0F3A14,
1093   PREFIX_0F3A15,
1094   PREFIX_0F3A16,
1095   PREFIX_0F3A17,
1096   PREFIX_0F3A20,
1097   PREFIX_0F3A21,
1098   PREFIX_0F3A22,
1099   PREFIX_0F3A40,
1100   PREFIX_0F3A41,
1101   PREFIX_0F3A42,
1102   PREFIX_0F3A44,
1103   PREFIX_0F3A60,
1104   PREFIX_0F3A61,
1105   PREFIX_0F3A62,
1106   PREFIX_0F3A63,
1107   PREFIX_0F3ACC,
1108   PREFIX_0F3ACE,
1109   PREFIX_0F3ACF,
1110   PREFIX_0F3ADF,
1111   PREFIX_VEX_0F10,
1112   PREFIX_VEX_0F11,
1113   PREFIX_VEX_0F12,
1114   PREFIX_VEX_0F16,
1115   PREFIX_VEX_0F2A,
1116   PREFIX_VEX_0F2C,
1117   PREFIX_VEX_0F2D,
1118   PREFIX_VEX_0F2E,
1119   PREFIX_VEX_0F2F,
1120   PREFIX_VEX_0F41,
1121   PREFIX_VEX_0F42,
1122   PREFIX_VEX_0F44,
1123   PREFIX_VEX_0F45,
1124   PREFIX_VEX_0F46,
1125   PREFIX_VEX_0F47,
1126   PREFIX_VEX_0F4A,
1127   PREFIX_VEX_0F4B,
1128   PREFIX_VEX_0F51,
1129   PREFIX_VEX_0F52,
1130   PREFIX_VEX_0F53,
1131   PREFIX_VEX_0F58,
1132   PREFIX_VEX_0F59,
1133   PREFIX_VEX_0F5A,
1134   PREFIX_VEX_0F5B,
1135   PREFIX_VEX_0F5C,
1136   PREFIX_VEX_0F5D,
1137   PREFIX_VEX_0F5E,
1138   PREFIX_VEX_0F5F,
1139   PREFIX_VEX_0F60,
1140   PREFIX_VEX_0F61,
1141   PREFIX_VEX_0F62,
1142   PREFIX_VEX_0F63,
1143   PREFIX_VEX_0F64,
1144   PREFIX_VEX_0F65,
1145   PREFIX_VEX_0F66,
1146   PREFIX_VEX_0F67,
1147   PREFIX_VEX_0F68,
1148   PREFIX_VEX_0F69,
1149   PREFIX_VEX_0F6A,
1150   PREFIX_VEX_0F6B,
1151   PREFIX_VEX_0F6C,
1152   PREFIX_VEX_0F6D,
1153   PREFIX_VEX_0F6E,
1154   PREFIX_VEX_0F6F,
1155   PREFIX_VEX_0F70,
1156   PREFIX_VEX_0F71_REG_2,
1157   PREFIX_VEX_0F71_REG_4,
1158   PREFIX_VEX_0F71_REG_6,
1159   PREFIX_VEX_0F72_REG_2,
1160   PREFIX_VEX_0F72_REG_4,
1161   PREFIX_VEX_0F72_REG_6,
1162   PREFIX_VEX_0F73_REG_2,
1163   PREFIX_VEX_0F73_REG_3,
1164   PREFIX_VEX_0F73_REG_6,
1165   PREFIX_VEX_0F73_REG_7,
1166   PREFIX_VEX_0F74,
1167   PREFIX_VEX_0F75,
1168   PREFIX_VEX_0F76,
1169   PREFIX_VEX_0F77,
1170   PREFIX_VEX_0F7C,
1171   PREFIX_VEX_0F7D,
1172   PREFIX_VEX_0F7E,
1173   PREFIX_VEX_0F7F,
1174   PREFIX_VEX_0F90,
1175   PREFIX_VEX_0F91,
1176   PREFIX_VEX_0F92,
1177   PREFIX_VEX_0F93,
1178   PREFIX_VEX_0F98,
1179   PREFIX_VEX_0F99,
1180   PREFIX_VEX_0FC2,
1181   PREFIX_VEX_0FC4,
1182   PREFIX_VEX_0FC5,
1183   PREFIX_VEX_0FD0,
1184   PREFIX_VEX_0FD1,
1185   PREFIX_VEX_0FD2,
1186   PREFIX_VEX_0FD3,
1187   PREFIX_VEX_0FD4,
1188   PREFIX_VEX_0FD5,
1189   PREFIX_VEX_0FD6,
1190   PREFIX_VEX_0FD7,
1191   PREFIX_VEX_0FD8,
1192   PREFIX_VEX_0FD9,
1193   PREFIX_VEX_0FDA,
1194   PREFIX_VEX_0FDB,
1195   PREFIX_VEX_0FDC,
1196   PREFIX_VEX_0FDD,
1197   PREFIX_VEX_0FDE,
1198   PREFIX_VEX_0FDF,
1199   PREFIX_VEX_0FE0,
1200   PREFIX_VEX_0FE1,
1201   PREFIX_VEX_0FE2,
1202   PREFIX_VEX_0FE3,
1203   PREFIX_VEX_0FE4,
1204   PREFIX_VEX_0FE5,
1205   PREFIX_VEX_0FE6,
1206   PREFIX_VEX_0FE7,
1207   PREFIX_VEX_0FE8,
1208   PREFIX_VEX_0FE9,
1209   PREFIX_VEX_0FEA,
1210   PREFIX_VEX_0FEB,
1211   PREFIX_VEX_0FEC,
1212   PREFIX_VEX_0FED,
1213   PREFIX_VEX_0FEE,
1214   PREFIX_VEX_0FEF,
1215   PREFIX_VEX_0FF0,
1216   PREFIX_VEX_0FF1,
1217   PREFIX_VEX_0FF2,
1218   PREFIX_VEX_0FF3,
1219   PREFIX_VEX_0FF4,
1220   PREFIX_VEX_0FF5,
1221   PREFIX_VEX_0FF6,
1222   PREFIX_VEX_0FF7,
1223   PREFIX_VEX_0FF8,
1224   PREFIX_VEX_0FF9,
1225   PREFIX_VEX_0FFA,
1226   PREFIX_VEX_0FFB,
1227   PREFIX_VEX_0FFC,
1228   PREFIX_VEX_0FFD,
1229   PREFIX_VEX_0FFE,
1230   PREFIX_VEX_0F3800,
1231   PREFIX_VEX_0F3801,
1232   PREFIX_VEX_0F3802,
1233   PREFIX_VEX_0F3803,
1234   PREFIX_VEX_0F3804,
1235   PREFIX_VEX_0F3805,
1236   PREFIX_VEX_0F3806,
1237   PREFIX_VEX_0F3807,
1238   PREFIX_VEX_0F3808,
1239   PREFIX_VEX_0F3809,
1240   PREFIX_VEX_0F380A,
1241   PREFIX_VEX_0F380B,
1242   PREFIX_VEX_0F380C,
1243   PREFIX_VEX_0F380D,
1244   PREFIX_VEX_0F380E,
1245   PREFIX_VEX_0F380F,
1246   PREFIX_VEX_0F3813,
1247   PREFIX_VEX_0F3816,
1248   PREFIX_VEX_0F3817,
1249   PREFIX_VEX_0F3818,
1250   PREFIX_VEX_0F3819,
1251   PREFIX_VEX_0F381A,
1252   PREFIX_VEX_0F381C,
1253   PREFIX_VEX_0F381D,
1254   PREFIX_VEX_0F381E,
1255   PREFIX_VEX_0F3820,
1256   PREFIX_VEX_0F3821,
1257   PREFIX_VEX_0F3822,
1258   PREFIX_VEX_0F3823,
1259   PREFIX_VEX_0F3824,
1260   PREFIX_VEX_0F3825,
1261   PREFIX_VEX_0F3828,
1262   PREFIX_VEX_0F3829,
1263   PREFIX_VEX_0F382A,
1264   PREFIX_VEX_0F382B,
1265   PREFIX_VEX_0F382C,
1266   PREFIX_VEX_0F382D,
1267   PREFIX_VEX_0F382E,
1268   PREFIX_VEX_0F382F,
1269   PREFIX_VEX_0F3830,
1270   PREFIX_VEX_0F3831,
1271   PREFIX_VEX_0F3832,
1272   PREFIX_VEX_0F3833,
1273   PREFIX_VEX_0F3834,
1274   PREFIX_VEX_0F3835,
1275   PREFIX_VEX_0F3836,
1276   PREFIX_VEX_0F3837,
1277   PREFIX_VEX_0F3838,
1278   PREFIX_VEX_0F3839,
1279   PREFIX_VEX_0F383A,
1280   PREFIX_VEX_0F383B,
1281   PREFIX_VEX_0F383C,
1282   PREFIX_VEX_0F383D,
1283   PREFIX_VEX_0F383E,
1284   PREFIX_VEX_0F383F,
1285   PREFIX_VEX_0F3840,
1286   PREFIX_VEX_0F3841,
1287   PREFIX_VEX_0F3845,
1288   PREFIX_VEX_0F3846,
1289   PREFIX_VEX_0F3847,
1290   PREFIX_VEX_0F3858,
1291   PREFIX_VEX_0F3859,
1292   PREFIX_VEX_0F385A,
1293   PREFIX_VEX_0F3878,
1294   PREFIX_VEX_0F3879,
1295   PREFIX_VEX_0F388C,
1296   PREFIX_VEX_0F388E,
1297   PREFIX_VEX_0F3890,
1298   PREFIX_VEX_0F3891,
1299   PREFIX_VEX_0F3892,
1300   PREFIX_VEX_0F3893,
1301   PREFIX_VEX_0F3896,
1302   PREFIX_VEX_0F3897,
1303   PREFIX_VEX_0F3898,
1304   PREFIX_VEX_0F3899,
1305   PREFIX_VEX_0F389A,
1306   PREFIX_VEX_0F389B,
1307   PREFIX_VEX_0F389C,
1308   PREFIX_VEX_0F389D,
1309   PREFIX_VEX_0F389E,
1310   PREFIX_VEX_0F389F,
1311   PREFIX_VEX_0F38A6,
1312   PREFIX_VEX_0F38A7,
1313   PREFIX_VEX_0F38A8,
1314   PREFIX_VEX_0F38A9,
1315   PREFIX_VEX_0F38AA,
1316   PREFIX_VEX_0F38AB,
1317   PREFIX_VEX_0F38AC,
1318   PREFIX_VEX_0F38AD,
1319   PREFIX_VEX_0F38AE,
1320   PREFIX_VEX_0F38AF,
1321   PREFIX_VEX_0F38B6,
1322   PREFIX_VEX_0F38B7,
1323   PREFIX_VEX_0F38B8,
1324   PREFIX_VEX_0F38B9,
1325   PREFIX_VEX_0F38BA,
1326   PREFIX_VEX_0F38BB,
1327   PREFIX_VEX_0F38BC,
1328   PREFIX_VEX_0F38BD,
1329   PREFIX_VEX_0F38BE,
1330   PREFIX_VEX_0F38BF,
1331   PREFIX_VEX_0F38CF,
1332   PREFIX_VEX_0F38DB,
1333   PREFIX_VEX_0F38DC,
1334   PREFIX_VEX_0F38DD,
1335   PREFIX_VEX_0F38DE,
1336   PREFIX_VEX_0F38DF,
1337   PREFIX_VEX_0F38F2,
1338   PREFIX_VEX_0F38F3_REG_1,
1339   PREFIX_VEX_0F38F3_REG_2,
1340   PREFIX_VEX_0F38F3_REG_3,
1341   PREFIX_VEX_0F38F5,
1342   PREFIX_VEX_0F38F6,
1343   PREFIX_VEX_0F38F7,
1344   PREFIX_VEX_0F3A00,
1345   PREFIX_VEX_0F3A01,
1346   PREFIX_VEX_0F3A02,
1347   PREFIX_VEX_0F3A04,
1348   PREFIX_VEX_0F3A05,
1349   PREFIX_VEX_0F3A06,
1350   PREFIX_VEX_0F3A08,
1351   PREFIX_VEX_0F3A09,
1352   PREFIX_VEX_0F3A0A,
1353   PREFIX_VEX_0F3A0B,
1354   PREFIX_VEX_0F3A0C,
1355   PREFIX_VEX_0F3A0D,
1356   PREFIX_VEX_0F3A0E,
1357   PREFIX_VEX_0F3A0F,
1358   PREFIX_VEX_0F3A14,
1359   PREFIX_VEX_0F3A15,
1360   PREFIX_VEX_0F3A16,
1361   PREFIX_VEX_0F3A17,
1362   PREFIX_VEX_0F3A18,
1363   PREFIX_VEX_0F3A19,
1364   PREFIX_VEX_0F3A1D,
1365   PREFIX_VEX_0F3A20,
1366   PREFIX_VEX_0F3A21,
1367   PREFIX_VEX_0F3A22,
1368   PREFIX_VEX_0F3A30,
1369   PREFIX_VEX_0F3A31,
1370   PREFIX_VEX_0F3A32,
1371   PREFIX_VEX_0F3A33,
1372   PREFIX_VEX_0F3A38,
1373   PREFIX_VEX_0F3A39,
1374   PREFIX_VEX_0F3A40,
1375   PREFIX_VEX_0F3A41,
1376   PREFIX_VEX_0F3A42,
1377   PREFIX_VEX_0F3A44,
1378   PREFIX_VEX_0F3A46,
1379   PREFIX_VEX_0F3A48,
1380   PREFIX_VEX_0F3A49,
1381   PREFIX_VEX_0F3A4A,
1382   PREFIX_VEX_0F3A4B,
1383   PREFIX_VEX_0F3A4C,
1384   PREFIX_VEX_0F3A5C,
1385   PREFIX_VEX_0F3A5D,
1386   PREFIX_VEX_0F3A5E,
1387   PREFIX_VEX_0F3A5F,
1388   PREFIX_VEX_0F3A60,
1389   PREFIX_VEX_0F3A61,
1390   PREFIX_VEX_0F3A62,
1391   PREFIX_VEX_0F3A63,
1392   PREFIX_VEX_0F3A68,
1393   PREFIX_VEX_0F3A69,
1394   PREFIX_VEX_0F3A6A,
1395   PREFIX_VEX_0F3A6B,
1396   PREFIX_VEX_0F3A6C,
1397   PREFIX_VEX_0F3A6D,
1398   PREFIX_VEX_0F3A6E,
1399   PREFIX_VEX_0F3A6F,
1400   PREFIX_VEX_0F3A78,
1401   PREFIX_VEX_0F3A79,
1402   PREFIX_VEX_0F3A7A,
1403   PREFIX_VEX_0F3A7B,
1404   PREFIX_VEX_0F3A7C,
1405   PREFIX_VEX_0F3A7D,
1406   PREFIX_VEX_0F3A7E,
1407   PREFIX_VEX_0F3A7F,
1408   PREFIX_VEX_0F3ACE,
1409   PREFIX_VEX_0F3ACF,
1410   PREFIX_VEX_0F3ADF,
1411   PREFIX_VEX_0F3AF0,
1412
1413   PREFIX_EVEX_0F10,
1414   PREFIX_EVEX_0F11,
1415   PREFIX_EVEX_0F12,
1416   PREFIX_EVEX_0F13,
1417   PREFIX_EVEX_0F14,
1418   PREFIX_EVEX_0F15,
1419   PREFIX_EVEX_0F16,
1420   PREFIX_EVEX_0F17,
1421   PREFIX_EVEX_0F28,
1422   PREFIX_EVEX_0F29,
1423   PREFIX_EVEX_0F2A,
1424   PREFIX_EVEX_0F2B,
1425   PREFIX_EVEX_0F2C,
1426   PREFIX_EVEX_0F2D,
1427   PREFIX_EVEX_0F2E,
1428   PREFIX_EVEX_0F2F,
1429   PREFIX_EVEX_0F51,
1430   PREFIX_EVEX_0F54,
1431   PREFIX_EVEX_0F55,
1432   PREFIX_EVEX_0F56,
1433   PREFIX_EVEX_0F57,
1434   PREFIX_EVEX_0F58,
1435   PREFIX_EVEX_0F59,
1436   PREFIX_EVEX_0F5A,
1437   PREFIX_EVEX_0F5B,
1438   PREFIX_EVEX_0F5C,
1439   PREFIX_EVEX_0F5D,
1440   PREFIX_EVEX_0F5E,
1441   PREFIX_EVEX_0F5F,
1442   PREFIX_EVEX_0F60,
1443   PREFIX_EVEX_0F61,
1444   PREFIX_EVEX_0F62,
1445   PREFIX_EVEX_0F63,
1446   PREFIX_EVEX_0F64,
1447   PREFIX_EVEX_0F65,
1448   PREFIX_EVEX_0F66,
1449   PREFIX_EVEX_0F67,
1450   PREFIX_EVEX_0F68,
1451   PREFIX_EVEX_0F69,
1452   PREFIX_EVEX_0F6A,
1453   PREFIX_EVEX_0F6B,
1454   PREFIX_EVEX_0F6C,
1455   PREFIX_EVEX_0F6D,
1456   PREFIX_EVEX_0F6E,
1457   PREFIX_EVEX_0F6F,
1458   PREFIX_EVEX_0F70,
1459   PREFIX_EVEX_0F71_REG_2,
1460   PREFIX_EVEX_0F71_REG_4,
1461   PREFIX_EVEX_0F71_REG_6,
1462   PREFIX_EVEX_0F72_REG_0,
1463   PREFIX_EVEX_0F72_REG_1,
1464   PREFIX_EVEX_0F72_REG_2,
1465   PREFIX_EVEX_0F72_REG_4,
1466   PREFIX_EVEX_0F72_REG_6,
1467   PREFIX_EVEX_0F73_REG_2,
1468   PREFIX_EVEX_0F73_REG_3,
1469   PREFIX_EVEX_0F73_REG_6,
1470   PREFIX_EVEX_0F73_REG_7,
1471   PREFIX_EVEX_0F74,
1472   PREFIX_EVEX_0F75,
1473   PREFIX_EVEX_0F76,
1474   PREFIX_EVEX_0F78,
1475   PREFIX_EVEX_0F79,
1476   PREFIX_EVEX_0F7A,
1477   PREFIX_EVEX_0F7B,
1478   PREFIX_EVEX_0F7E,
1479   PREFIX_EVEX_0F7F,
1480   PREFIX_EVEX_0FC2,
1481   PREFIX_EVEX_0FC4,
1482   PREFIX_EVEX_0FC5,
1483   PREFIX_EVEX_0FC6,
1484   PREFIX_EVEX_0FD1,
1485   PREFIX_EVEX_0FD2,
1486   PREFIX_EVEX_0FD3,
1487   PREFIX_EVEX_0FD4,
1488   PREFIX_EVEX_0FD5,
1489   PREFIX_EVEX_0FD6,
1490   PREFIX_EVEX_0FD8,
1491   PREFIX_EVEX_0FD9,
1492   PREFIX_EVEX_0FDA,
1493   PREFIX_EVEX_0FDB,
1494   PREFIX_EVEX_0FDC,
1495   PREFIX_EVEX_0FDD,
1496   PREFIX_EVEX_0FDE,
1497   PREFIX_EVEX_0FDF,
1498   PREFIX_EVEX_0FE0,
1499   PREFIX_EVEX_0FE1,
1500   PREFIX_EVEX_0FE2,
1501   PREFIX_EVEX_0FE3,
1502   PREFIX_EVEX_0FE4,
1503   PREFIX_EVEX_0FE5,
1504   PREFIX_EVEX_0FE6,
1505   PREFIX_EVEX_0FE7,
1506   PREFIX_EVEX_0FE8,
1507   PREFIX_EVEX_0FE9,
1508   PREFIX_EVEX_0FEA,
1509   PREFIX_EVEX_0FEB,
1510   PREFIX_EVEX_0FEC,
1511   PREFIX_EVEX_0FED,
1512   PREFIX_EVEX_0FEE,
1513   PREFIX_EVEX_0FEF,
1514   PREFIX_EVEX_0FF1,
1515   PREFIX_EVEX_0FF2,
1516   PREFIX_EVEX_0FF3,
1517   PREFIX_EVEX_0FF4,
1518   PREFIX_EVEX_0FF5,
1519   PREFIX_EVEX_0FF6,
1520   PREFIX_EVEX_0FF8,
1521   PREFIX_EVEX_0FF9,
1522   PREFIX_EVEX_0FFA,
1523   PREFIX_EVEX_0FFB,
1524   PREFIX_EVEX_0FFC,
1525   PREFIX_EVEX_0FFD,
1526   PREFIX_EVEX_0FFE,
1527   PREFIX_EVEX_0F3800,
1528   PREFIX_EVEX_0F3804,
1529   PREFIX_EVEX_0F380B,
1530   PREFIX_EVEX_0F380C,
1531   PREFIX_EVEX_0F380D,
1532   PREFIX_EVEX_0F3810,
1533   PREFIX_EVEX_0F3811,
1534   PREFIX_EVEX_0F3812,
1535   PREFIX_EVEX_0F3813,
1536   PREFIX_EVEX_0F3814,
1537   PREFIX_EVEX_0F3815,
1538   PREFIX_EVEX_0F3816,
1539   PREFIX_EVEX_0F3818,
1540   PREFIX_EVEX_0F3819,
1541   PREFIX_EVEX_0F381A,
1542   PREFIX_EVEX_0F381B,
1543   PREFIX_EVEX_0F381C,
1544   PREFIX_EVEX_0F381D,
1545   PREFIX_EVEX_0F381E,
1546   PREFIX_EVEX_0F381F,
1547   PREFIX_EVEX_0F3820,
1548   PREFIX_EVEX_0F3821,
1549   PREFIX_EVEX_0F3822,
1550   PREFIX_EVEX_0F3823,
1551   PREFIX_EVEX_0F3824,
1552   PREFIX_EVEX_0F3825,
1553   PREFIX_EVEX_0F3826,
1554   PREFIX_EVEX_0F3827,
1555   PREFIX_EVEX_0F3828,
1556   PREFIX_EVEX_0F3829,
1557   PREFIX_EVEX_0F382A,
1558   PREFIX_EVEX_0F382B,
1559   PREFIX_EVEX_0F382C,
1560   PREFIX_EVEX_0F382D,
1561   PREFIX_EVEX_0F3830,
1562   PREFIX_EVEX_0F3831,
1563   PREFIX_EVEX_0F3832,
1564   PREFIX_EVEX_0F3833,
1565   PREFIX_EVEX_0F3834,
1566   PREFIX_EVEX_0F3835,
1567   PREFIX_EVEX_0F3836,
1568   PREFIX_EVEX_0F3837,
1569   PREFIX_EVEX_0F3838,
1570   PREFIX_EVEX_0F3839,
1571   PREFIX_EVEX_0F383A,
1572   PREFIX_EVEX_0F383B,
1573   PREFIX_EVEX_0F383C,
1574   PREFIX_EVEX_0F383D,
1575   PREFIX_EVEX_0F383E,
1576   PREFIX_EVEX_0F383F,
1577   PREFIX_EVEX_0F3840,
1578   PREFIX_EVEX_0F3842,
1579   PREFIX_EVEX_0F3843,
1580   PREFIX_EVEX_0F3844,
1581   PREFIX_EVEX_0F3845,
1582   PREFIX_EVEX_0F3846,
1583   PREFIX_EVEX_0F3847,
1584   PREFIX_EVEX_0F384C,
1585   PREFIX_EVEX_0F384D,
1586   PREFIX_EVEX_0F384E,
1587   PREFIX_EVEX_0F384F,
1588   PREFIX_EVEX_0F3850,
1589   PREFIX_EVEX_0F3851,
1590   PREFIX_EVEX_0F3852,
1591   PREFIX_EVEX_0F3853,
1592   PREFIX_EVEX_0F3854,
1593   PREFIX_EVEX_0F3855,
1594   PREFIX_EVEX_0F3858,
1595   PREFIX_EVEX_0F3859,
1596   PREFIX_EVEX_0F385A,
1597   PREFIX_EVEX_0F385B,
1598   PREFIX_EVEX_0F3862,
1599   PREFIX_EVEX_0F3863,
1600   PREFIX_EVEX_0F3864,
1601   PREFIX_EVEX_0F3865,
1602   PREFIX_EVEX_0F3866,
1603   PREFIX_EVEX_0F3868,
1604   PREFIX_EVEX_0F3870,
1605   PREFIX_EVEX_0F3871,
1606   PREFIX_EVEX_0F3872,
1607   PREFIX_EVEX_0F3873,
1608   PREFIX_EVEX_0F3875,
1609   PREFIX_EVEX_0F3876,
1610   PREFIX_EVEX_0F3877,
1611   PREFIX_EVEX_0F3878,
1612   PREFIX_EVEX_0F3879,
1613   PREFIX_EVEX_0F387A,
1614   PREFIX_EVEX_0F387B,
1615   PREFIX_EVEX_0F387C,
1616   PREFIX_EVEX_0F387D,
1617   PREFIX_EVEX_0F387E,
1618   PREFIX_EVEX_0F387F,
1619   PREFIX_EVEX_0F3883,
1620   PREFIX_EVEX_0F3888,
1621   PREFIX_EVEX_0F3889,
1622   PREFIX_EVEX_0F388A,
1623   PREFIX_EVEX_0F388B,
1624   PREFIX_EVEX_0F388D,
1625   PREFIX_EVEX_0F388F,
1626   PREFIX_EVEX_0F3890,
1627   PREFIX_EVEX_0F3891,
1628   PREFIX_EVEX_0F3892,
1629   PREFIX_EVEX_0F3893,
1630   PREFIX_EVEX_0F3896,
1631   PREFIX_EVEX_0F3897,
1632   PREFIX_EVEX_0F3898,
1633   PREFIX_EVEX_0F3899,
1634   PREFIX_EVEX_0F389A,
1635   PREFIX_EVEX_0F389B,
1636   PREFIX_EVEX_0F389C,
1637   PREFIX_EVEX_0F389D,
1638   PREFIX_EVEX_0F389E,
1639   PREFIX_EVEX_0F389F,
1640   PREFIX_EVEX_0F38A0,
1641   PREFIX_EVEX_0F38A1,
1642   PREFIX_EVEX_0F38A2,
1643   PREFIX_EVEX_0F38A3,
1644   PREFIX_EVEX_0F38A6,
1645   PREFIX_EVEX_0F38A7,
1646   PREFIX_EVEX_0F38A8,
1647   PREFIX_EVEX_0F38A9,
1648   PREFIX_EVEX_0F38AA,
1649   PREFIX_EVEX_0F38AB,
1650   PREFIX_EVEX_0F38AC,
1651   PREFIX_EVEX_0F38AD,
1652   PREFIX_EVEX_0F38AE,
1653   PREFIX_EVEX_0F38AF,
1654   PREFIX_EVEX_0F38B4,
1655   PREFIX_EVEX_0F38B5,
1656   PREFIX_EVEX_0F38B6,
1657   PREFIX_EVEX_0F38B7,
1658   PREFIX_EVEX_0F38B8,
1659   PREFIX_EVEX_0F38B9,
1660   PREFIX_EVEX_0F38BA,
1661   PREFIX_EVEX_0F38BB,
1662   PREFIX_EVEX_0F38BC,
1663   PREFIX_EVEX_0F38BD,
1664   PREFIX_EVEX_0F38BE,
1665   PREFIX_EVEX_0F38BF,
1666   PREFIX_EVEX_0F38C4,
1667   PREFIX_EVEX_0F38C6_REG_1,
1668   PREFIX_EVEX_0F38C6_REG_2,
1669   PREFIX_EVEX_0F38C6_REG_5,
1670   PREFIX_EVEX_0F38C6_REG_6,
1671   PREFIX_EVEX_0F38C7_REG_1,
1672   PREFIX_EVEX_0F38C7_REG_2,
1673   PREFIX_EVEX_0F38C7_REG_5,
1674   PREFIX_EVEX_0F38C7_REG_6,
1675   PREFIX_EVEX_0F38C8,
1676   PREFIX_EVEX_0F38CA,
1677   PREFIX_EVEX_0F38CB,
1678   PREFIX_EVEX_0F38CC,
1679   PREFIX_EVEX_0F38CD,
1680   PREFIX_EVEX_0F38CF,
1681   PREFIX_EVEX_0F38DC,
1682   PREFIX_EVEX_0F38DD,
1683   PREFIX_EVEX_0F38DE,
1684   PREFIX_EVEX_0F38DF,
1685
1686   PREFIX_EVEX_0F3A00,
1687   PREFIX_EVEX_0F3A01,
1688   PREFIX_EVEX_0F3A03,
1689   PREFIX_EVEX_0F3A04,
1690   PREFIX_EVEX_0F3A05,
1691   PREFIX_EVEX_0F3A08,
1692   PREFIX_EVEX_0F3A09,
1693   PREFIX_EVEX_0F3A0A,
1694   PREFIX_EVEX_0F3A0B,
1695   PREFIX_EVEX_0F3A0F,
1696   PREFIX_EVEX_0F3A14,
1697   PREFIX_EVEX_0F3A15,
1698   PREFIX_EVEX_0F3A16,
1699   PREFIX_EVEX_0F3A17,
1700   PREFIX_EVEX_0F3A18,
1701   PREFIX_EVEX_0F3A19,
1702   PREFIX_EVEX_0F3A1A,
1703   PREFIX_EVEX_0F3A1B,
1704   PREFIX_EVEX_0F3A1D,
1705   PREFIX_EVEX_0F3A1E,
1706   PREFIX_EVEX_0F3A1F,
1707   PREFIX_EVEX_0F3A20,
1708   PREFIX_EVEX_0F3A21,
1709   PREFIX_EVEX_0F3A22,
1710   PREFIX_EVEX_0F3A23,
1711   PREFIX_EVEX_0F3A25,
1712   PREFIX_EVEX_0F3A26,
1713   PREFIX_EVEX_0F3A27,
1714   PREFIX_EVEX_0F3A38,
1715   PREFIX_EVEX_0F3A39,
1716   PREFIX_EVEX_0F3A3A,
1717   PREFIX_EVEX_0F3A3B,
1718   PREFIX_EVEX_0F3A3E,
1719   PREFIX_EVEX_0F3A3F,
1720   PREFIX_EVEX_0F3A42,
1721   PREFIX_EVEX_0F3A43,
1722   PREFIX_EVEX_0F3A44,
1723   PREFIX_EVEX_0F3A50,
1724   PREFIX_EVEX_0F3A51,
1725   PREFIX_EVEX_0F3A54,
1726   PREFIX_EVEX_0F3A55,
1727   PREFIX_EVEX_0F3A56,
1728   PREFIX_EVEX_0F3A57,
1729   PREFIX_EVEX_0F3A66,
1730   PREFIX_EVEX_0F3A67,
1731   PREFIX_EVEX_0F3A70,
1732   PREFIX_EVEX_0F3A71,
1733   PREFIX_EVEX_0F3A72,
1734   PREFIX_EVEX_0F3A73,
1735   PREFIX_EVEX_0F3ACE,
1736   PREFIX_EVEX_0F3ACF
1737 };
1738
1739 enum
1740 {
1741   X86_64_06 = 0,
1742   X86_64_07,
1743   X86_64_0D,
1744   X86_64_16,
1745   X86_64_17,
1746   X86_64_1E,
1747   X86_64_1F,
1748   X86_64_27,
1749   X86_64_2F,
1750   X86_64_37,
1751   X86_64_3F,
1752   X86_64_60,
1753   X86_64_61,
1754   X86_64_62,
1755   X86_64_63,
1756   X86_64_6D,
1757   X86_64_6F,
1758   X86_64_82,
1759   X86_64_9A,
1760   X86_64_C4,
1761   X86_64_C5,
1762   X86_64_CE,
1763   X86_64_D4,
1764   X86_64_D5,
1765   X86_64_E8,
1766   X86_64_E9,
1767   X86_64_EA,
1768   X86_64_0F01_REG_0,
1769   X86_64_0F01_REG_1,
1770   X86_64_0F01_REG_2,
1771   X86_64_0F01_REG_3
1772 };
1773
1774 enum
1775 {
1776   THREE_BYTE_0F38 = 0,
1777   THREE_BYTE_0F3A
1778 };
1779
1780 enum
1781 {
1782   XOP_08 = 0,
1783   XOP_09,
1784   XOP_0A
1785 };
1786
1787 enum
1788 {
1789   VEX_0F = 0,
1790   VEX_0F38,
1791   VEX_0F3A
1792 };
1793
1794 enum
1795 {
1796   EVEX_0F = 0,
1797   EVEX_0F38,
1798   EVEX_0F3A
1799 };
1800
1801 enum
1802 {
1803   VEX_LEN_0F12_P_0_M_0 = 0,
1804   VEX_LEN_0F12_P_0_M_1,
1805   VEX_LEN_0F12_P_2,
1806   VEX_LEN_0F13_M_0,
1807   VEX_LEN_0F16_P_0_M_0,
1808   VEX_LEN_0F16_P_0_M_1,
1809   VEX_LEN_0F16_P_2,
1810   VEX_LEN_0F17_M_0,
1811   VEX_LEN_0F41_P_0,
1812   VEX_LEN_0F41_P_2,
1813   VEX_LEN_0F42_P_0,
1814   VEX_LEN_0F42_P_2,
1815   VEX_LEN_0F44_P_0,
1816   VEX_LEN_0F44_P_2,
1817   VEX_LEN_0F45_P_0,
1818   VEX_LEN_0F45_P_2,
1819   VEX_LEN_0F46_P_0,
1820   VEX_LEN_0F46_P_2,
1821   VEX_LEN_0F47_P_0,
1822   VEX_LEN_0F47_P_2,
1823   VEX_LEN_0F4A_P_0,
1824   VEX_LEN_0F4A_P_2,
1825   VEX_LEN_0F4B_P_0,
1826   VEX_LEN_0F4B_P_2,
1827   VEX_LEN_0F6E_P_2,
1828   VEX_LEN_0F77_P_0,
1829   VEX_LEN_0F7E_P_1,
1830   VEX_LEN_0F7E_P_2,
1831   VEX_LEN_0F90_P_0,
1832   VEX_LEN_0F90_P_2,
1833   VEX_LEN_0F91_P_0,
1834   VEX_LEN_0F91_P_2,
1835   VEX_LEN_0F92_P_0,
1836   VEX_LEN_0F92_P_2,
1837   VEX_LEN_0F92_P_3,
1838   VEX_LEN_0F93_P_0,
1839   VEX_LEN_0F93_P_2,
1840   VEX_LEN_0F93_P_3,
1841   VEX_LEN_0F98_P_0,
1842   VEX_LEN_0F98_P_2,
1843   VEX_LEN_0F99_P_0,
1844   VEX_LEN_0F99_P_2,
1845   VEX_LEN_0FAE_R_2_M_0,
1846   VEX_LEN_0FAE_R_3_M_0,
1847   VEX_LEN_0FC4_P_2,
1848   VEX_LEN_0FC5_P_2,
1849   VEX_LEN_0FD6_P_2,
1850   VEX_LEN_0FF7_P_2,
1851   VEX_LEN_0F3816_P_2,
1852   VEX_LEN_0F3819_P_2,
1853   VEX_LEN_0F381A_P_2_M_0,
1854   VEX_LEN_0F3836_P_2,
1855   VEX_LEN_0F3841_P_2,
1856   VEX_LEN_0F385A_P_2_M_0,
1857   VEX_LEN_0F38DB_P_2,
1858   VEX_LEN_0F38F2_P_0,
1859   VEX_LEN_0F38F3_R_1_P_0,
1860   VEX_LEN_0F38F3_R_2_P_0,
1861   VEX_LEN_0F38F3_R_3_P_0,
1862   VEX_LEN_0F38F5_P_0,
1863   VEX_LEN_0F38F5_P_1,
1864   VEX_LEN_0F38F5_P_3,
1865   VEX_LEN_0F38F6_P_3,
1866   VEX_LEN_0F38F7_P_0,
1867   VEX_LEN_0F38F7_P_1,
1868   VEX_LEN_0F38F7_P_2,
1869   VEX_LEN_0F38F7_P_3,
1870   VEX_LEN_0F3A00_P_2,
1871   VEX_LEN_0F3A01_P_2,
1872   VEX_LEN_0F3A06_P_2,
1873   VEX_LEN_0F3A14_P_2,
1874   VEX_LEN_0F3A15_P_2,
1875   VEX_LEN_0F3A16_P_2,
1876   VEX_LEN_0F3A17_P_2,
1877   VEX_LEN_0F3A18_P_2,
1878   VEX_LEN_0F3A19_P_2,
1879   VEX_LEN_0F3A20_P_2,
1880   VEX_LEN_0F3A21_P_2,
1881   VEX_LEN_0F3A22_P_2,
1882   VEX_LEN_0F3A30_P_2,
1883   VEX_LEN_0F3A31_P_2,
1884   VEX_LEN_0F3A32_P_2,
1885   VEX_LEN_0F3A33_P_2,
1886   VEX_LEN_0F3A38_P_2,
1887   VEX_LEN_0F3A39_P_2,
1888   VEX_LEN_0F3A41_P_2,
1889   VEX_LEN_0F3A46_P_2,
1890   VEX_LEN_0F3A60_P_2,
1891   VEX_LEN_0F3A61_P_2,
1892   VEX_LEN_0F3A62_P_2,
1893   VEX_LEN_0F3A63_P_2,
1894   VEX_LEN_0F3A6A_P_2,
1895   VEX_LEN_0F3A6B_P_2,
1896   VEX_LEN_0F3A6E_P_2,
1897   VEX_LEN_0F3A6F_P_2,
1898   VEX_LEN_0F3A7A_P_2,
1899   VEX_LEN_0F3A7B_P_2,
1900   VEX_LEN_0F3A7E_P_2,
1901   VEX_LEN_0F3A7F_P_2,
1902   VEX_LEN_0F3ADF_P_2,
1903   VEX_LEN_0F3AF0_P_3,
1904   VEX_LEN_0FXOP_08_CC,
1905   VEX_LEN_0FXOP_08_CD,
1906   VEX_LEN_0FXOP_08_CE,
1907   VEX_LEN_0FXOP_08_CF,
1908   VEX_LEN_0FXOP_08_EC,
1909   VEX_LEN_0FXOP_08_ED,
1910   VEX_LEN_0FXOP_08_EE,
1911   VEX_LEN_0FXOP_08_EF,
1912   VEX_LEN_0FXOP_09_80,
1913   VEX_LEN_0FXOP_09_81
1914 };
1915
1916 enum
1917 {
1918   EVEX_LEN_0F6E_P_2 = 0,
1919   EVEX_LEN_0F7E_P_1,
1920   EVEX_LEN_0F7E_P_2,
1921   EVEX_LEN_0FD6_P_2,
1922   EVEX_LEN_0F3819_P_2_W_0,
1923   EVEX_LEN_0F3819_P_2_W_1,
1924   EVEX_LEN_0F381A_P_2_W_0,
1925   EVEX_LEN_0F381A_P_2_W_1,
1926   EVEX_LEN_0F381B_P_2_W_0,
1927   EVEX_LEN_0F381B_P_2_W_1,
1928   EVEX_LEN_0F385A_P_2_W_0,
1929   EVEX_LEN_0F385A_P_2_W_1,
1930   EVEX_LEN_0F385B_P_2_W_0,
1931   EVEX_LEN_0F385B_P_2_W_1,
1932   EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1933   EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1934   EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1935   EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1936   EVEX_LEN_0F38C7_R_1_P_2_W_0,
1937   EVEX_LEN_0F38C7_R_1_P_2_W_1,
1938   EVEX_LEN_0F38C7_R_2_P_2_W_0,
1939   EVEX_LEN_0F38C7_R_2_P_2_W_1,
1940   EVEX_LEN_0F38C7_R_5_P_2_W_0,
1941   EVEX_LEN_0F38C7_R_5_P_2_W_1,
1942   EVEX_LEN_0F38C7_R_6_P_2_W_0,
1943   EVEX_LEN_0F38C7_R_6_P_2_W_1,
1944   EVEX_LEN_0F3A18_P_2_W_0,
1945   EVEX_LEN_0F3A18_P_2_W_1,
1946   EVEX_LEN_0F3A19_P_2_W_0,
1947   EVEX_LEN_0F3A19_P_2_W_1,
1948   EVEX_LEN_0F3A1A_P_2_W_0,
1949   EVEX_LEN_0F3A1A_P_2_W_1,
1950   EVEX_LEN_0F3A1B_P_2_W_0,
1951   EVEX_LEN_0F3A1B_P_2_W_1,
1952   EVEX_LEN_0F3A23_P_2_W_0,
1953   EVEX_LEN_0F3A23_P_2_W_1,
1954   EVEX_LEN_0F3A38_P_2_W_0,
1955   EVEX_LEN_0F3A38_P_2_W_1,
1956   EVEX_LEN_0F3A39_P_2_W_0,
1957   EVEX_LEN_0F3A39_P_2_W_1,
1958   EVEX_LEN_0F3A3A_P_2_W_0,
1959   EVEX_LEN_0F3A3A_P_2_W_1,
1960   EVEX_LEN_0F3A3B_P_2_W_0,
1961   EVEX_LEN_0F3A3B_P_2_W_1,
1962   EVEX_LEN_0F3A43_P_2_W_0,
1963   EVEX_LEN_0F3A43_P_2_W_1
1964 };
1965
1966 enum
1967 {
1968   VEX_W_0F41_P_0_LEN_1 = 0,
1969   VEX_W_0F41_P_2_LEN_1,
1970   VEX_W_0F42_P_0_LEN_1,
1971   VEX_W_0F42_P_2_LEN_1,
1972   VEX_W_0F44_P_0_LEN_0,
1973   VEX_W_0F44_P_2_LEN_0,
1974   VEX_W_0F45_P_0_LEN_1,
1975   VEX_W_0F45_P_2_LEN_1,
1976   VEX_W_0F46_P_0_LEN_1,
1977   VEX_W_0F46_P_2_LEN_1,
1978   VEX_W_0F47_P_0_LEN_1,
1979   VEX_W_0F47_P_2_LEN_1,
1980   VEX_W_0F4A_P_0_LEN_1,
1981   VEX_W_0F4A_P_2_LEN_1,
1982   VEX_W_0F4B_P_0_LEN_1,
1983   VEX_W_0F4B_P_2_LEN_1,
1984   VEX_W_0F90_P_0_LEN_0,
1985   VEX_W_0F90_P_2_LEN_0,
1986   VEX_W_0F91_P_0_LEN_0,
1987   VEX_W_0F91_P_2_LEN_0,
1988   VEX_W_0F92_P_0_LEN_0,
1989   VEX_W_0F92_P_2_LEN_0,
1990   VEX_W_0F93_P_0_LEN_0,
1991   VEX_W_0F93_P_2_LEN_0,
1992   VEX_W_0F98_P_0_LEN_0,
1993   VEX_W_0F98_P_2_LEN_0,
1994   VEX_W_0F99_P_0_LEN_0,
1995   VEX_W_0F99_P_2_LEN_0,
1996   VEX_W_0F380C_P_2,
1997   VEX_W_0F380D_P_2,
1998   VEX_W_0F380E_P_2,
1999   VEX_W_0F380F_P_2,
2000   VEX_W_0F3816_P_2,
2001   VEX_W_0F3818_P_2,
2002   VEX_W_0F3819_P_2,
2003   VEX_W_0F381A_P_2_M_0,
2004   VEX_W_0F382C_P_2_M_0,
2005   VEX_W_0F382D_P_2_M_0,
2006   VEX_W_0F382E_P_2_M_0,
2007   VEX_W_0F382F_P_2_M_0,
2008   VEX_W_0F3836_P_2,
2009   VEX_W_0F3846_P_2,
2010   VEX_W_0F3858_P_2,
2011   VEX_W_0F3859_P_2,
2012   VEX_W_0F385A_P_2_M_0,
2013   VEX_W_0F3878_P_2,
2014   VEX_W_0F3879_P_2,
2015   VEX_W_0F38CF_P_2,
2016   VEX_W_0F3A00_P_2,
2017   VEX_W_0F3A01_P_2,
2018   VEX_W_0F3A02_P_2,
2019   VEX_W_0F3A04_P_2,
2020   VEX_W_0F3A05_P_2,
2021   VEX_W_0F3A06_P_2,
2022   VEX_W_0F3A18_P_2,
2023   VEX_W_0F3A19_P_2,
2024   VEX_W_0F3A30_P_2_LEN_0,
2025   VEX_W_0F3A31_P_2_LEN_0,
2026   VEX_W_0F3A32_P_2_LEN_0,
2027   VEX_W_0F3A33_P_2_LEN_0,
2028   VEX_W_0F3A38_P_2,
2029   VEX_W_0F3A39_P_2,
2030   VEX_W_0F3A46_P_2,
2031   VEX_W_0F3A48_P_2,
2032   VEX_W_0F3A49_P_2,
2033   VEX_W_0F3A4A_P_2,
2034   VEX_W_0F3A4B_P_2,
2035   VEX_W_0F3A4C_P_2,
2036   VEX_W_0F3ACE_P_2,
2037   VEX_W_0F3ACF_P_2,
2038
2039   EVEX_W_0F10_P_0,
2040   EVEX_W_0F10_P_1,
2041   EVEX_W_0F10_P_2,
2042   EVEX_W_0F10_P_3,
2043   EVEX_W_0F11_P_0,
2044   EVEX_W_0F11_P_1,
2045   EVEX_W_0F11_P_2,
2046   EVEX_W_0F11_P_3,
2047   EVEX_W_0F12_P_0_M_0,
2048   EVEX_W_0F12_P_0_M_1,
2049   EVEX_W_0F12_P_1,
2050   EVEX_W_0F12_P_2,
2051   EVEX_W_0F12_P_3,
2052   EVEX_W_0F13_P_0,
2053   EVEX_W_0F13_P_2,
2054   EVEX_W_0F14_P_0,
2055   EVEX_W_0F14_P_2,
2056   EVEX_W_0F15_P_0,
2057   EVEX_W_0F15_P_2,
2058   EVEX_W_0F16_P_0_M_0,
2059   EVEX_W_0F16_P_0_M_1,
2060   EVEX_W_0F16_P_1,
2061   EVEX_W_0F16_P_2,
2062   EVEX_W_0F17_P_0,
2063   EVEX_W_0F17_P_2,
2064   EVEX_W_0F28_P_0,
2065   EVEX_W_0F28_P_2,
2066   EVEX_W_0F29_P_0,
2067   EVEX_W_0F29_P_2,
2068   EVEX_W_0F2A_P_3,
2069   EVEX_W_0F2B_P_0,
2070   EVEX_W_0F2B_P_2,
2071   EVEX_W_0F2E_P_0,
2072   EVEX_W_0F2E_P_2,
2073   EVEX_W_0F2F_P_0,
2074   EVEX_W_0F2F_P_2,
2075   EVEX_W_0F51_P_0,
2076   EVEX_W_0F51_P_1,
2077   EVEX_W_0F51_P_2,
2078   EVEX_W_0F51_P_3,
2079   EVEX_W_0F54_P_0,
2080   EVEX_W_0F54_P_2,
2081   EVEX_W_0F55_P_0,
2082   EVEX_W_0F55_P_2,
2083   EVEX_W_0F56_P_0,
2084   EVEX_W_0F56_P_2,
2085   EVEX_W_0F57_P_0,
2086   EVEX_W_0F57_P_2,
2087   EVEX_W_0F58_P_0,
2088   EVEX_W_0F58_P_1,
2089   EVEX_W_0F58_P_2,
2090   EVEX_W_0F58_P_3,
2091   EVEX_W_0F59_P_0,
2092   EVEX_W_0F59_P_1,
2093   EVEX_W_0F59_P_2,
2094   EVEX_W_0F59_P_3,
2095   EVEX_W_0F5A_P_0,
2096   EVEX_W_0F5A_P_1,
2097   EVEX_W_0F5A_P_2,
2098   EVEX_W_0F5A_P_3,
2099   EVEX_W_0F5B_P_0,
2100   EVEX_W_0F5B_P_1,
2101   EVEX_W_0F5B_P_2,
2102   EVEX_W_0F5C_P_0,
2103   EVEX_W_0F5C_P_1,
2104   EVEX_W_0F5C_P_2,
2105   EVEX_W_0F5C_P_3,
2106   EVEX_W_0F5D_P_0,
2107   EVEX_W_0F5D_P_1,
2108   EVEX_W_0F5D_P_2,
2109   EVEX_W_0F5D_P_3,
2110   EVEX_W_0F5E_P_0,
2111   EVEX_W_0F5E_P_1,
2112   EVEX_W_0F5E_P_2,
2113   EVEX_W_0F5E_P_3,
2114   EVEX_W_0F5F_P_0,
2115   EVEX_W_0F5F_P_1,
2116   EVEX_W_0F5F_P_2,
2117   EVEX_W_0F5F_P_3,
2118   EVEX_W_0F62_P_2,
2119   EVEX_W_0F66_P_2,
2120   EVEX_W_0F6A_P_2,
2121   EVEX_W_0F6B_P_2,
2122   EVEX_W_0F6C_P_2,
2123   EVEX_W_0F6D_P_2,
2124   EVEX_W_0F6F_P_1,
2125   EVEX_W_0F6F_P_2,
2126   EVEX_W_0F6F_P_3,
2127   EVEX_W_0F70_P_2,
2128   EVEX_W_0F72_R_2_P_2,
2129   EVEX_W_0F72_R_6_P_2,
2130   EVEX_W_0F73_R_2_P_2,
2131   EVEX_W_0F73_R_6_P_2,
2132   EVEX_W_0F76_P_2,
2133   EVEX_W_0F78_P_0,
2134   EVEX_W_0F78_P_2,
2135   EVEX_W_0F79_P_0,
2136   EVEX_W_0F79_P_2,
2137   EVEX_W_0F7A_P_1,
2138   EVEX_W_0F7A_P_2,
2139   EVEX_W_0F7A_P_3,
2140   EVEX_W_0F7B_P_2,
2141   EVEX_W_0F7B_P_3,
2142   EVEX_W_0F7E_P_1,
2143   EVEX_W_0F7F_P_1,
2144   EVEX_W_0F7F_P_2,
2145   EVEX_W_0F7F_P_3,
2146   EVEX_W_0FC2_P_0,
2147   EVEX_W_0FC2_P_1,
2148   EVEX_W_0FC2_P_2,
2149   EVEX_W_0FC2_P_3,
2150   EVEX_W_0FC6_P_0,
2151   EVEX_W_0FC6_P_2,
2152   EVEX_W_0FD2_P_2,
2153   EVEX_W_0FD3_P_2,
2154   EVEX_W_0FD4_P_2,
2155   EVEX_W_0FD6_P_2,
2156   EVEX_W_0FE6_P_1,
2157   EVEX_W_0FE6_P_2,
2158   EVEX_W_0FE6_P_3,
2159   EVEX_W_0FE7_P_2,
2160   EVEX_W_0FF2_P_2,
2161   EVEX_W_0FF3_P_2,
2162   EVEX_W_0FF4_P_2,
2163   EVEX_W_0FFA_P_2,
2164   EVEX_W_0FFB_P_2,
2165   EVEX_W_0FFE_P_2,
2166   EVEX_W_0F380C_P_2,
2167   EVEX_W_0F380D_P_2,
2168   EVEX_W_0F3810_P_1,
2169   EVEX_W_0F3810_P_2,
2170   EVEX_W_0F3811_P_1,
2171   EVEX_W_0F3811_P_2,
2172   EVEX_W_0F3812_P_1,
2173   EVEX_W_0F3812_P_2,
2174   EVEX_W_0F3813_P_1,
2175   EVEX_W_0F3813_P_2,
2176   EVEX_W_0F3814_P_1,
2177   EVEX_W_0F3815_P_1,
2178   EVEX_W_0F3818_P_2,
2179   EVEX_W_0F3819_P_2,
2180   EVEX_W_0F381A_P_2,
2181   EVEX_W_0F381B_P_2,
2182   EVEX_W_0F381E_P_2,
2183   EVEX_W_0F381F_P_2,
2184   EVEX_W_0F3820_P_1,
2185   EVEX_W_0F3821_P_1,
2186   EVEX_W_0F3822_P_1,
2187   EVEX_W_0F3823_P_1,
2188   EVEX_W_0F3824_P_1,
2189   EVEX_W_0F3825_P_1,
2190   EVEX_W_0F3825_P_2,
2191   EVEX_W_0F3826_P_1,
2192   EVEX_W_0F3826_P_2,
2193   EVEX_W_0F3828_P_1,
2194   EVEX_W_0F3828_P_2,
2195   EVEX_W_0F3829_P_1,
2196   EVEX_W_0F3829_P_2,
2197   EVEX_W_0F382A_P_1,
2198   EVEX_W_0F382A_P_2,
2199   EVEX_W_0F382B_P_2,
2200   EVEX_W_0F3830_P_1,
2201   EVEX_W_0F3831_P_1,
2202   EVEX_W_0F3832_P_1,
2203   EVEX_W_0F3833_P_1,
2204   EVEX_W_0F3834_P_1,
2205   EVEX_W_0F3835_P_1,
2206   EVEX_W_0F3835_P_2,
2207   EVEX_W_0F3837_P_2,
2208   EVEX_W_0F3838_P_1,
2209   EVEX_W_0F3839_P_1,
2210   EVEX_W_0F383A_P_1,
2211   EVEX_W_0F3840_P_2,
2212   EVEX_W_0F3852_P_1,
2213   EVEX_W_0F3854_P_2,
2214   EVEX_W_0F3855_P_2,
2215   EVEX_W_0F3858_P_2,
2216   EVEX_W_0F3859_P_2,
2217   EVEX_W_0F385A_P_2,
2218   EVEX_W_0F385B_P_2,
2219   EVEX_W_0F3862_P_2,
2220   EVEX_W_0F3863_P_2,
2221   EVEX_W_0F3866_P_2,
2222   EVEX_W_0F3868_P_3,
2223   EVEX_W_0F3870_P_2,
2224   EVEX_W_0F3871_P_2,
2225   EVEX_W_0F3872_P_1,
2226   EVEX_W_0F3872_P_2,
2227   EVEX_W_0F3872_P_3,
2228   EVEX_W_0F3873_P_2,
2229   EVEX_W_0F3875_P_2,
2230   EVEX_W_0F3878_P_2,
2231   EVEX_W_0F3879_P_2,
2232   EVEX_W_0F387A_P_2,
2233   EVEX_W_0F387B_P_2,
2234   EVEX_W_0F387D_P_2,
2235   EVEX_W_0F3883_P_2,
2236   EVEX_W_0F388D_P_2,
2237   EVEX_W_0F3891_P_2,
2238   EVEX_W_0F3893_P_2,
2239   EVEX_W_0F38A1_P_2,
2240   EVEX_W_0F38A3_P_2,
2241   EVEX_W_0F38C7_R_1_P_2,
2242   EVEX_W_0F38C7_R_2_P_2,
2243   EVEX_W_0F38C7_R_5_P_2,
2244   EVEX_W_0F38C7_R_6_P_2,
2245
2246   EVEX_W_0F3A00_P_2,
2247   EVEX_W_0F3A01_P_2,
2248   EVEX_W_0F3A04_P_2,
2249   EVEX_W_0F3A05_P_2,
2250   EVEX_W_0F3A08_P_2,
2251   EVEX_W_0F3A09_P_2,
2252   EVEX_W_0F3A0A_P_2,
2253   EVEX_W_0F3A0B_P_2,
2254   EVEX_W_0F3A18_P_2,
2255   EVEX_W_0F3A19_P_2,
2256   EVEX_W_0F3A1A_P_2,
2257   EVEX_W_0F3A1B_P_2,
2258   EVEX_W_0F3A1D_P_2,
2259   EVEX_W_0F3A21_P_2,
2260   EVEX_W_0F3A23_P_2,
2261   EVEX_W_0F3A38_P_2,
2262   EVEX_W_0F3A39_P_2,
2263   EVEX_W_0F3A3A_P_2,
2264   EVEX_W_0F3A3B_P_2,
2265   EVEX_W_0F3A3E_P_2,
2266   EVEX_W_0F3A3F_P_2,
2267   EVEX_W_0F3A42_P_2,
2268   EVEX_W_0F3A43_P_2,
2269   EVEX_W_0F3A50_P_2,
2270   EVEX_W_0F3A51_P_2,
2271   EVEX_W_0F3A56_P_2,
2272   EVEX_W_0F3A57_P_2,
2273   EVEX_W_0F3A66_P_2,
2274   EVEX_W_0F3A67_P_2,
2275   EVEX_W_0F3A70_P_2,
2276   EVEX_W_0F3A71_P_2,
2277   EVEX_W_0F3A72_P_2,
2278   EVEX_W_0F3A73_P_2,
2279   EVEX_W_0F3ACE_P_2,
2280   EVEX_W_0F3ACF_P_2
2281 };
2282
2283 typedef void (*op_rtn) (int bytemode, int sizeflag);
2284
2285 struct dis386 {
2286   const char *name;
2287   struct
2288     {
2289       op_rtn rtn;
2290       int bytemode;
2291     } op[MAX_OPERANDS];
2292   unsigned int prefix_requirement;
2293 };
2294
2295 /* Upper case letters in the instruction names here are macros.
2296    'A' => print 'b' if no register operands or suffix_always is true
2297    'B' => print 'b' if suffix_always is true
2298    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2299           size prefix
2300    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2301           suffix_always is true
2302    'E' => print 'e' if 32-bit form of jcxz
2303    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2304    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2305    'H' => print ",pt" or ",pn" branch hint
2306    'I' => honor following macro letter even in Intel mode (implemented only
2307           for some of the macro letters)
2308    'J' => print 'l'
2309    'K' => print 'd' or 'q' if rex prefix is present.
2310    'L' => print 'l' if suffix_always is true
2311    'M' => print 'r' if intel_mnemonic is false.
2312    'N' => print 'n' if instruction has no wait "prefix"
2313    'O' => print 'd' or 'o' (or 'q' in Intel mode)
2314    'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2315           or suffix_always is true.  print 'q' if rex prefix is present.
2316    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2317           is true
2318    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2319    'S' => print 'w', 'l' or 'q' if suffix_always is true
2320    'T' => print 'q' in 64bit mode if instruction has no operand size
2321           prefix and behave as 'P' otherwise
2322    'U' => print 'q' in 64bit mode if instruction has no operand size
2323           prefix and behave as 'Q' otherwise
2324    'V' => print 'q' in 64bit mode if instruction has no operand size
2325           prefix and behave as 'S' otherwise
2326    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2327    'X' => print 's', 'd' depending on data16 prefix (for XMM)
2328    'Y' unused.
2329    'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2330    '!' => change condition from true to false or from false to true.
2331    '%' => add 1 upper case letter to the macro.
2332    '^' => print 'w' or 'l' depending on operand size prefix or
2333           suffix_always is true (lcall/ljmp).
2334    '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2335           on operand size prefix.
2336    '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2337           has no operand size prefix for AMD64 ISA, behave as 'P'
2338           otherwise
2339
2340    2 upper case letter macros:
2341    "XY" => print 'x' or 'y' if suffix_always is true or no register
2342            operands and no broadcast.
2343    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2344            register operands and no broadcast.
2345    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2346    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2347            or suffix_always is true
2348    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2349    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2350    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2351    "LW" => print 'd', 'q' depending on the VEX.W bit
2352    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2353            an operand size prefix, or suffix_always is true.  print
2354            'q' if rex prefix is present.
2355
2356    Many of the above letters print nothing in Intel mode.  See "putop"
2357    for the details.
2358
2359    Braces '{' and '}', and vertical bars '|', indicate alternative
2360    mnemonic strings for AT&T and Intel.  */
2361
2362 static const struct dis386 dis386[] = {
2363   /* 00 */
2364   { "addB",             { Ebh1, Gb }, 0 },
2365   { "addS",             { Evh1, Gv }, 0 },
2366   { "addB",             { Gb, EbS }, 0 },
2367   { "addS",             { Gv, EvS }, 0 },
2368   { "addB",             { AL, Ib }, 0 },
2369   { "addS",             { eAX, Iv }, 0 },
2370   { X86_64_TABLE (X86_64_06) },
2371   { X86_64_TABLE (X86_64_07) },
2372   /* 08 */
2373   { "orB",              { Ebh1, Gb }, 0 },
2374   { "orS",              { Evh1, Gv }, 0 },
2375   { "orB",              { Gb, EbS }, 0 },
2376   { "orS",              { Gv, EvS }, 0 },
2377   { "orB",              { AL, Ib }, 0 },
2378   { "orS",              { eAX, Iv }, 0 },
2379   { X86_64_TABLE (X86_64_0D) },
2380   { Bad_Opcode },       /* 0x0f extended opcode escape */
2381   /* 10 */
2382   { "adcB",             { Ebh1, Gb }, 0 },
2383   { "adcS",             { Evh1, Gv }, 0 },
2384   { "adcB",             { Gb, EbS }, 0 },
2385   { "adcS",             { Gv, EvS }, 0 },
2386   { "adcB",             { AL, Ib }, 0 },
2387   { "adcS",             { eAX, Iv }, 0 },
2388   { X86_64_TABLE (X86_64_16) },
2389   { X86_64_TABLE (X86_64_17) },
2390   /* 18 */
2391   { "sbbB",             { Ebh1, Gb }, 0 },
2392   { "sbbS",             { Evh1, Gv }, 0 },
2393   { "sbbB",             { Gb, EbS }, 0 },
2394   { "sbbS",             { Gv, EvS }, 0 },
2395   { "sbbB",             { AL, Ib }, 0 },
2396   { "sbbS",             { eAX, Iv }, 0 },
2397   { X86_64_TABLE (X86_64_1E) },
2398   { X86_64_TABLE (X86_64_1F) },
2399   /* 20 */
2400   { "andB",             { Ebh1, Gb }, 0 },
2401   { "andS",             { Evh1, Gv }, 0 },
2402   { "andB",             { Gb, EbS }, 0 },
2403   { "andS",             { Gv, EvS }, 0 },
2404   { "andB",             { AL, Ib }, 0 },
2405   { "andS",             { eAX, Iv }, 0 },
2406   { Bad_Opcode },       /* SEG ES prefix */
2407   { X86_64_TABLE (X86_64_27) },
2408   /* 28 */
2409   { "subB",             { Ebh1, Gb }, 0 },
2410   { "subS",             { Evh1, Gv }, 0 },
2411   { "subB",             { Gb, EbS }, 0 },
2412   { "subS",             { Gv, EvS }, 0 },
2413   { "subB",             { AL, Ib }, 0 },
2414   { "subS",             { eAX, Iv }, 0 },
2415   { Bad_Opcode },       /* SEG CS prefix */
2416   { X86_64_TABLE (X86_64_2F) },
2417   /* 30 */
2418   { "xorB",             { Ebh1, Gb }, 0 },
2419   { "xorS",             { Evh1, Gv }, 0 },
2420   { "xorB",             { Gb, EbS }, 0 },
2421   { "xorS",             { Gv, EvS }, 0 },
2422   { "xorB",             { AL, Ib }, 0 },
2423   { "xorS",             { eAX, Iv }, 0 },
2424   { Bad_Opcode },       /* SEG SS prefix */
2425   { X86_64_TABLE (X86_64_37) },
2426   /* 38 */
2427   { "cmpB",             { Eb, Gb }, 0 },
2428   { "cmpS",             { Ev, Gv }, 0 },
2429   { "cmpB",             { Gb, EbS }, 0 },
2430   { "cmpS",             { Gv, EvS }, 0 },
2431   { "cmpB",             { AL, Ib }, 0 },
2432   { "cmpS",             { eAX, Iv }, 0 },
2433   { Bad_Opcode },       /* SEG DS prefix */
2434   { X86_64_TABLE (X86_64_3F) },
2435   /* 40 */
2436   { "inc{S|}",          { RMeAX }, 0 },
2437   { "inc{S|}",          { RMeCX }, 0 },
2438   { "inc{S|}",          { RMeDX }, 0 },
2439   { "inc{S|}",          { RMeBX }, 0 },
2440   { "inc{S|}",          { RMeSP }, 0 },
2441   { "inc{S|}",          { RMeBP }, 0 },
2442   { "inc{S|}",          { RMeSI }, 0 },
2443   { "inc{S|}",          { RMeDI }, 0 },
2444   /* 48 */
2445   { "dec{S|}",          { RMeAX }, 0 },
2446   { "dec{S|}",          { RMeCX }, 0 },
2447   { "dec{S|}",          { RMeDX }, 0 },
2448   { "dec{S|}",          { RMeBX }, 0 },
2449   { "dec{S|}",          { RMeSP }, 0 },
2450   { "dec{S|}",          { RMeBP }, 0 },
2451   { "dec{S|}",          { RMeSI }, 0 },
2452   { "dec{S|}",          { RMeDI }, 0 },
2453   /* 50 */
2454   { "pushV",            { RMrAX }, 0 },
2455   { "pushV",            { RMrCX }, 0 },
2456   { "pushV",            { RMrDX }, 0 },
2457   { "pushV",            { RMrBX }, 0 },
2458   { "pushV",            { RMrSP }, 0 },
2459   { "pushV",            { RMrBP }, 0 },
2460   { "pushV",            { RMrSI }, 0 },
2461   { "pushV",            { RMrDI }, 0 },
2462   /* 58 */
2463   { "popV",             { RMrAX }, 0 },
2464   { "popV",             { RMrCX }, 0 },
2465   { "popV",             { RMrDX }, 0 },
2466   { "popV",             { RMrBX }, 0 },
2467   { "popV",             { RMrSP }, 0 },
2468   { "popV",             { RMrBP }, 0 },
2469   { "popV",             { RMrSI }, 0 },
2470   { "popV",             { RMrDI }, 0 },
2471   /* 60 */
2472   { X86_64_TABLE (X86_64_60) },
2473   { X86_64_TABLE (X86_64_61) },
2474   { X86_64_TABLE (X86_64_62) },
2475   { X86_64_TABLE (X86_64_63) },
2476   { Bad_Opcode },       /* seg fs */
2477   { Bad_Opcode },       /* seg gs */
2478   { Bad_Opcode },       /* op size prefix */
2479   { Bad_Opcode },       /* adr size prefix */
2480   /* 68 */
2481   { "pushT",            { sIv }, 0 },
2482   { "imulS",            { Gv, Ev, Iv }, 0 },
2483   { "pushT",            { sIbT }, 0 },
2484   { "imulS",            { Gv, Ev, sIb }, 0 },
2485   { "ins{b|}",          { Ybr, indirDX }, 0 },
2486   { X86_64_TABLE (X86_64_6D) },
2487   { "outs{b|}",         { indirDXr, Xb }, 0 },
2488   { X86_64_TABLE (X86_64_6F) },
2489   /* 70 */
2490   { "joH",              { Jb, BND, cond_jump_flag }, 0 },
2491   { "jnoH",             { Jb, BND, cond_jump_flag }, 0 },
2492   { "jbH",              { Jb, BND, cond_jump_flag }, 0 },
2493   { "jaeH",             { Jb, BND, cond_jump_flag }, 0 },
2494   { "jeH",              { Jb, BND, cond_jump_flag }, 0 },
2495   { "jneH",             { Jb, BND, cond_jump_flag }, 0 },
2496   { "jbeH",             { Jb, BND, cond_jump_flag }, 0 },
2497   { "jaH",              { Jb, BND, cond_jump_flag }, 0 },
2498   /* 78 */
2499   { "jsH",              { Jb, BND, cond_jump_flag }, 0 },
2500   { "jnsH",             { Jb, BND, cond_jump_flag }, 0 },
2501   { "jpH",              { Jb, BND, cond_jump_flag }, 0 },
2502   { "jnpH",             { Jb, BND, cond_jump_flag }, 0 },
2503   { "jlH",              { Jb, BND, cond_jump_flag }, 0 },
2504   { "jgeH",             { Jb, BND, cond_jump_flag }, 0 },
2505   { "jleH",             { Jb, BND, cond_jump_flag }, 0 },
2506   { "jgH",              { Jb, BND, cond_jump_flag }, 0 },
2507   /* 80 */
2508   { REG_TABLE (REG_80) },
2509   { REG_TABLE (REG_81) },
2510   { X86_64_TABLE (X86_64_82) },
2511   { REG_TABLE (REG_83) },
2512   { "testB",            { Eb, Gb }, 0 },
2513   { "testS",            { Ev, Gv }, 0 },
2514   { "xchgB",            { Ebh2, Gb }, 0 },
2515   { "xchgS",            { Evh2, Gv }, 0 },
2516   /* 88 */
2517   { "movB",             { Ebh3, Gb }, 0 },
2518   { "movS",             { Evh3, Gv }, 0 },
2519   { "movB",             { Gb, EbS }, 0 },
2520   { "movS",             { Gv, EvS }, 0 },
2521   { "movD",             { Sv, Sw }, 0 },
2522   { MOD_TABLE (MOD_8D) },
2523   { "movD",             { Sw, Sv }, 0 },
2524   { REG_TABLE (REG_8F) },
2525   /* 90 */
2526   { PREFIX_TABLE (PREFIX_90) },
2527   { "xchgS",            { RMeCX, eAX }, 0 },
2528   { "xchgS",            { RMeDX, eAX }, 0 },
2529   { "xchgS",            { RMeBX, eAX }, 0 },
2530   { "xchgS",            { RMeSP, eAX }, 0 },
2531   { "xchgS",            { RMeBP, eAX }, 0 },
2532   { "xchgS",            { RMeSI, eAX }, 0 },
2533   { "xchgS",            { RMeDI, eAX }, 0 },
2534   /* 98 */
2535   { "cW{t|}R",          { XX }, 0 },
2536   { "cR{t|}O",          { XX }, 0 },
2537   { X86_64_TABLE (X86_64_9A) },
2538   { Bad_Opcode },       /* fwait */
2539   { "pushfT",           { XX }, 0 },
2540   { "popfT",            { XX }, 0 },
2541   { "sahf",             { XX }, 0 },
2542   { "lahf",             { XX }, 0 },
2543   /* a0 */
2544   { "mov%LB",           { AL, Ob }, 0 },
2545   { "mov%LS",           { eAX, Ov }, 0 },
2546   { "mov%LB",           { Ob, AL }, 0 },
2547   { "mov%LS",           { Ov, eAX }, 0 },
2548   { "movs{b|}",         { Ybr, Xb }, 0 },
2549   { "movs{R|}",         { Yvr, Xv }, 0 },
2550   { "cmps{b|}",         { Xb, Yb }, 0 },
2551   { "cmps{R|}",         { Xv, Yv }, 0 },
2552   /* a8 */
2553   { "testB",            { AL, Ib }, 0 },
2554   { "testS",            { eAX, Iv }, 0 },
2555   { "stosB",            { Ybr, AL }, 0 },
2556   { "stosS",            { Yvr, eAX }, 0 },
2557   { "lodsB",            { ALr, Xb }, 0 },
2558   { "lodsS",            { eAXr, Xv }, 0 },
2559   { "scasB",            { AL, Yb }, 0 },
2560   { "scasS",            { eAX, Yv }, 0 },
2561   /* b0 */
2562   { "movB",             { RMAL, Ib }, 0 },
2563   { "movB",             { RMCL, Ib }, 0 },
2564   { "movB",             { RMDL, Ib }, 0 },
2565   { "movB",             { RMBL, Ib }, 0 },
2566   { "movB",             { RMAH, Ib }, 0 },
2567   { "movB",             { RMCH, Ib }, 0 },
2568   { "movB",             { RMDH, Ib }, 0 },
2569   { "movB",             { RMBH, Ib }, 0 },
2570   /* b8 */
2571   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2572   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2573   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2574   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2575   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2576   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2577   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2578   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2579   /* c0 */
2580   { REG_TABLE (REG_C0) },
2581   { REG_TABLE (REG_C1) },
2582   { "retT",             { Iw, BND }, 0 },
2583   { "retT",             { BND }, 0 },
2584   { X86_64_TABLE (X86_64_C4) },
2585   { X86_64_TABLE (X86_64_C5) },
2586   { REG_TABLE (REG_C6) },
2587   { REG_TABLE (REG_C7) },
2588   /* c8 */
2589   { "enterT",           { Iw, Ib }, 0 },
2590   { "leaveT",           { XX }, 0 },
2591   { "Jret{|f}P",        { Iw }, 0 },
2592   { "Jret{|f}P",        { XX }, 0 },
2593   { "int3",             { XX }, 0 },
2594   { "int",              { Ib }, 0 },
2595   { X86_64_TABLE (X86_64_CE) },
2596   { "iret%LP",          { XX }, 0 },
2597   /* d0 */
2598   { REG_TABLE (REG_D0) },
2599   { REG_TABLE (REG_D1) },
2600   { REG_TABLE (REG_D2) },
2601   { REG_TABLE (REG_D3) },
2602   { X86_64_TABLE (X86_64_D4) },
2603   { X86_64_TABLE (X86_64_D5) },
2604   { Bad_Opcode },
2605   { "xlat",             { DSBX }, 0 },
2606   /* d8 */
2607   { FLOAT },
2608   { FLOAT },
2609   { FLOAT },
2610   { FLOAT },
2611   { FLOAT },
2612   { FLOAT },
2613   { FLOAT },
2614   { FLOAT },
2615   /* e0 */
2616   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, 0 },
2617   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, 0 },
2618   { "loopFH",           { Jb, XX, loop_jcxz_flag }, 0 },
2619   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, 0 },
2620   { "inB",              { AL, Ib }, 0 },
2621   { "inG",              { zAX, Ib }, 0 },
2622   { "outB",             { Ib, AL }, 0 },
2623   { "outG",             { Ib, zAX }, 0 },
2624   /* e8 */
2625   { X86_64_TABLE (X86_64_E8) },
2626   { X86_64_TABLE (X86_64_E9) },
2627   { X86_64_TABLE (X86_64_EA) },
2628   { "jmp",              { Jb, BND }, 0 },
2629   { "inB",              { AL, indirDX }, 0 },
2630   { "inG",              { zAX, indirDX }, 0 },
2631   { "outB",             { indirDX, AL }, 0 },
2632   { "outG",             { indirDX, zAX }, 0 },
2633   /* f0 */
2634   { Bad_Opcode },       /* lock prefix */
2635   { "icebp",            { XX }, 0 },
2636   { Bad_Opcode },       /* repne */
2637   { Bad_Opcode },       /* repz */
2638   { "hlt",              { XX }, 0 },
2639   { "cmc",              { XX }, 0 },
2640   { REG_TABLE (REG_F6) },
2641   { REG_TABLE (REG_F7) },
2642   /* f8 */
2643   { "clc",              { XX }, 0 },
2644   { "stc",              { XX }, 0 },
2645   { "cli",              { XX }, 0 },
2646   { "sti",              { XX }, 0 },
2647   { "cld",              { XX }, 0 },
2648   { "std",              { XX }, 0 },
2649   { REG_TABLE (REG_FE) },
2650   { REG_TABLE (REG_FF) },
2651 };
2652
2653 static const struct dis386 dis386_twobyte[] = {
2654   /* 00 */
2655   { REG_TABLE (REG_0F00 ) },
2656   { REG_TABLE (REG_0F01 ) },
2657   { "larS",             { Gv, Ew }, 0 },
2658   { "lslS",             { Gv, Ew }, 0 },
2659   { Bad_Opcode },
2660   { "syscall",          { XX }, 0 },
2661   { "clts",             { XX }, 0 },
2662   { "sysret%LP",                { XX }, 0 },
2663   /* 08 */
2664   { "invd",             { XX }, 0 },
2665   { PREFIX_TABLE (PREFIX_0F09) },
2666   { Bad_Opcode },
2667   { "ud2",              { XX }, 0 },
2668   { Bad_Opcode },
2669   { REG_TABLE (REG_0F0D) },
2670   { "femms",            { XX }, 0 },
2671   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2672   /* 10 */
2673   { PREFIX_TABLE (PREFIX_0F10) },
2674   { PREFIX_TABLE (PREFIX_0F11) },
2675   { PREFIX_TABLE (PREFIX_0F12) },
2676   { MOD_TABLE (MOD_0F13) },
2677   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2678   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2679   { PREFIX_TABLE (PREFIX_0F16) },
2680   { MOD_TABLE (MOD_0F17) },
2681   /* 18 */
2682   { REG_TABLE (REG_0F18) },
2683   { "nopQ",             { Ev }, 0 },
2684   { PREFIX_TABLE (PREFIX_0F1A) },
2685   { PREFIX_TABLE (PREFIX_0F1B) },
2686   { PREFIX_TABLE (PREFIX_0F1C) },
2687   { "nopQ",             { Ev }, 0 },
2688   { PREFIX_TABLE (PREFIX_0F1E) },
2689   { "nopQ",             { Ev }, 0 },
2690   /* 20 */
2691   { "movZ",             { Rm, Cm }, 0 },
2692   { "movZ",             { Rm, Dm }, 0 },
2693   { "movZ",             { Cm, Rm }, 0 },
2694   { "movZ",             { Dm, Rm }, 0 },
2695   { MOD_TABLE (MOD_0F24) },
2696   { Bad_Opcode },
2697   { MOD_TABLE (MOD_0F26) },
2698   { Bad_Opcode },
2699   /* 28 */
2700   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2701   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2702   { PREFIX_TABLE (PREFIX_0F2A) },
2703   { PREFIX_TABLE (PREFIX_0F2B) },
2704   { PREFIX_TABLE (PREFIX_0F2C) },
2705   { PREFIX_TABLE (PREFIX_0F2D) },
2706   { PREFIX_TABLE (PREFIX_0F2E) },
2707   { PREFIX_TABLE (PREFIX_0F2F) },
2708   /* 30 */
2709   { "wrmsr",            { XX }, 0 },
2710   { "rdtsc",            { XX }, 0 },
2711   { "rdmsr",            { XX }, 0 },
2712   { "rdpmc",            { XX }, 0 },
2713   { "sysenter",         { XX }, 0 },
2714   { "sysexit",          { XX }, 0 },
2715   { Bad_Opcode },
2716   { "getsec",           { XX }, 0 },
2717   /* 38 */
2718   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2719   { Bad_Opcode },
2720   { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2721   { Bad_Opcode },
2722   { Bad_Opcode },
2723   { Bad_Opcode },
2724   { Bad_Opcode },
2725   { Bad_Opcode },
2726   /* 40 */
2727   { "cmovoS",           { Gv, Ev }, 0 },
2728   { "cmovnoS",          { Gv, Ev }, 0 },
2729   { "cmovbS",           { Gv, Ev }, 0 },
2730   { "cmovaeS",          { Gv, Ev }, 0 },
2731   { "cmoveS",           { Gv, Ev }, 0 },
2732   { "cmovneS",          { Gv, Ev }, 0 },
2733   { "cmovbeS",          { Gv, Ev }, 0 },
2734   { "cmovaS",           { Gv, Ev }, 0 },
2735   /* 48 */
2736   { "cmovsS",           { Gv, Ev }, 0 },
2737   { "cmovnsS",          { Gv, Ev }, 0 },
2738   { "cmovpS",           { Gv, Ev }, 0 },
2739   { "cmovnpS",          { Gv, Ev }, 0 },
2740   { "cmovlS",           { Gv, Ev }, 0 },
2741   { "cmovgeS",          { Gv, Ev }, 0 },
2742   { "cmovleS",          { Gv, Ev }, 0 },
2743   { "cmovgS",           { Gv, Ev }, 0 },
2744   /* 50 */
2745   { MOD_TABLE (MOD_0F51) },
2746   { PREFIX_TABLE (PREFIX_0F51) },
2747   { PREFIX_TABLE (PREFIX_0F52) },
2748   { PREFIX_TABLE (PREFIX_0F53) },
2749   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2750   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2751   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2752   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2753   /* 58 */
2754   { PREFIX_TABLE (PREFIX_0F58) },
2755   { PREFIX_TABLE (PREFIX_0F59) },
2756   { PREFIX_TABLE (PREFIX_0F5A) },
2757   { PREFIX_TABLE (PREFIX_0F5B) },
2758   { PREFIX_TABLE (PREFIX_0F5C) },
2759   { PREFIX_TABLE (PREFIX_0F5D) },
2760   { PREFIX_TABLE (PREFIX_0F5E) },
2761   { PREFIX_TABLE (PREFIX_0F5F) },
2762   /* 60 */
2763   { PREFIX_TABLE (PREFIX_0F60) },
2764   { PREFIX_TABLE (PREFIX_0F61) },
2765   { PREFIX_TABLE (PREFIX_0F62) },
2766   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2767   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2768   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2769   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2770   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2771   /* 68 */
2772   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2773   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2774   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2775   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2776   { PREFIX_TABLE (PREFIX_0F6C) },
2777   { PREFIX_TABLE (PREFIX_0F6D) },
2778   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2779   { PREFIX_TABLE (PREFIX_0F6F) },
2780   /* 70 */
2781   { PREFIX_TABLE (PREFIX_0F70) },
2782   { REG_TABLE (REG_0F71) },
2783   { REG_TABLE (REG_0F72) },
2784   { REG_TABLE (REG_0F73) },
2785   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2786   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2787   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2788   { "emms",             { XX }, PREFIX_OPCODE },
2789   /* 78 */
2790   { PREFIX_TABLE (PREFIX_0F78) },
2791   { PREFIX_TABLE (PREFIX_0F79) },
2792   { Bad_Opcode },
2793   { Bad_Opcode },
2794   { PREFIX_TABLE (PREFIX_0F7C) },
2795   { PREFIX_TABLE (PREFIX_0F7D) },
2796   { PREFIX_TABLE (PREFIX_0F7E) },
2797   { PREFIX_TABLE (PREFIX_0F7F) },
2798   /* 80 */
2799   { "joH",              { Jv, BND, cond_jump_flag }, 0 },
2800   { "jnoH",             { Jv, BND, cond_jump_flag }, 0 },
2801   { "jbH",              { Jv, BND, cond_jump_flag }, 0 },
2802   { "jaeH",             { Jv, BND, cond_jump_flag }, 0 },
2803   { "jeH",              { Jv, BND, cond_jump_flag }, 0 },
2804   { "jneH",             { Jv, BND, cond_jump_flag }, 0 },
2805   { "jbeH",             { Jv, BND, cond_jump_flag }, 0 },
2806   { "jaH",              { Jv, BND, cond_jump_flag }, 0 },
2807   /* 88 */
2808   { "jsH",              { Jv, BND, cond_jump_flag }, 0 },
2809   { "jnsH",             { Jv, BND, cond_jump_flag }, 0 },
2810   { "jpH",              { Jv, BND, cond_jump_flag }, 0 },
2811   { "jnpH",             { Jv, BND, cond_jump_flag }, 0 },
2812   { "jlH",              { Jv, BND, cond_jump_flag }, 0 },
2813   { "jgeH",             { Jv, BND, cond_jump_flag }, 0 },
2814   { "jleH",             { Jv, BND, cond_jump_flag }, 0 },
2815   { "jgH",              { Jv, BND, cond_jump_flag }, 0 },
2816   /* 90 */
2817   { "seto",             { Eb }, 0 },
2818   { "setno",            { Eb }, 0 },
2819   { "setb",             { Eb }, 0 },
2820   { "setae",            { Eb }, 0 },
2821   { "sete",             { Eb }, 0 },
2822   { "setne",            { Eb }, 0 },
2823   { "setbe",            { Eb }, 0 },
2824   { "seta",             { Eb }, 0 },
2825   /* 98 */
2826   { "sets",             { Eb }, 0 },
2827   { "setns",            { Eb }, 0 },
2828   { "setp",             { Eb }, 0 },
2829   { "setnp",            { Eb }, 0 },
2830   { "setl",             { Eb }, 0 },
2831   { "setge",            { Eb }, 0 },
2832   { "setle",            { Eb }, 0 },
2833   { "setg",             { Eb }, 0 },
2834   /* a0 */
2835   { "pushT",            { fs }, 0 },
2836   { "popT",             { fs }, 0 },
2837   { "cpuid",            { XX }, 0 },
2838   { "btS",              { Ev, Gv }, 0 },
2839   { "shldS",            { Ev, Gv, Ib }, 0 },
2840   { "shldS",            { Ev, Gv, CL }, 0 },
2841   { REG_TABLE (REG_0FA6) },
2842   { REG_TABLE (REG_0FA7) },
2843   /* a8 */
2844   { "pushT",            { gs }, 0 },
2845   { "popT",             { gs }, 0 },
2846   { "rsm",              { XX }, 0 },
2847   { "btsS",             { Evh1, Gv }, 0 },
2848   { "shrdS",            { Ev, Gv, Ib }, 0 },
2849   { "shrdS",            { Ev, Gv, CL }, 0 },
2850   { REG_TABLE (REG_0FAE) },
2851   { "imulS",            { Gv, Ev }, 0 },
2852   /* b0 */
2853   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2854   { "cmpxchgS",         { Evh1, Gv }, 0 },
2855   { MOD_TABLE (MOD_0FB2) },
2856   { "btrS",             { Evh1, Gv }, 0 },
2857   { MOD_TABLE (MOD_0FB4) },
2858   { MOD_TABLE (MOD_0FB5) },
2859   { "movz{bR|x}",       { Gv, Eb }, 0 },
2860   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2861   /* b8 */
2862   { PREFIX_TABLE (PREFIX_0FB8) },
2863   { "ud1S",             { Gv, Ev }, 0 },
2864   { REG_TABLE (REG_0FBA) },
2865   { "btcS",             { Evh1, Gv }, 0 },
2866   { PREFIX_TABLE (PREFIX_0FBC) },
2867   { PREFIX_TABLE (PREFIX_0FBD) },
2868   { "movs{bR|x}",       { Gv, Eb }, 0 },
2869   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2870   /* c0 */
2871   { "xaddB",            { Ebh1, Gb }, 0 },
2872   { "xaddS",            { Evh1, Gv }, 0 },
2873   { PREFIX_TABLE (PREFIX_0FC2) },
2874   { MOD_TABLE (MOD_0FC3) },
2875   { "pinsrw",           { MX, Edqw, Ib }, PREFIX_OPCODE },
2876   { "pextrw",           { Gdq, MS, Ib }, PREFIX_OPCODE },
2877   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2878   { REG_TABLE (REG_0FC7) },
2879   /* c8 */
2880   { "bswap",            { RMeAX }, 0 },
2881   { "bswap",            { RMeCX }, 0 },
2882   { "bswap",            { RMeDX }, 0 },
2883   { "bswap",            { RMeBX }, 0 },
2884   { "bswap",            { RMeSP }, 0 },
2885   { "bswap",            { RMeBP }, 0 },
2886   { "bswap",            { RMeSI }, 0 },
2887   { "bswap",            { RMeDI }, 0 },
2888   /* d0 */
2889   { PREFIX_TABLE (PREFIX_0FD0) },
2890   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2891   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2892   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2893   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2894   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2895   { PREFIX_TABLE (PREFIX_0FD6) },
2896   { MOD_TABLE (MOD_0FD7) },
2897   /* d8 */
2898   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2899   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2900   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2901   { "pand",             { MX, EM }, PREFIX_OPCODE },
2902   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2903   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2904   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2905   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2906   /* e0 */
2907   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2908   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2909   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2910   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2911   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2912   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2913   { PREFIX_TABLE (PREFIX_0FE6) },
2914   { PREFIX_TABLE (PREFIX_0FE7) },
2915   /* e8 */
2916   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2917   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2918   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2919   { "por",              { MX, EM }, PREFIX_OPCODE },
2920   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2921   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2922   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2923   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2924   /* f0 */
2925   { PREFIX_TABLE (PREFIX_0FF0) },
2926   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2927   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2928   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2929   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2930   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2931   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2932   { PREFIX_TABLE (PREFIX_0FF7) },
2933   /* f8 */
2934   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2935   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2936   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2937   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2938   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2939   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2940   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2941   { "ud0S",             { Gv, Ev }, 0 },
2942 };
2943
2944 static const unsigned char onebyte_has_modrm[256] = {
2945   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2946   /*       -------------------------------        */
2947   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2948   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2949   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2950   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2951   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2952   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2953   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2954   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2955   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2956   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2957   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2958   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2959   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2960   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2961   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2962   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2963   /*       -------------------------------        */
2964   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2965 };
2966
2967 static const unsigned char twobyte_has_modrm[256] = {
2968   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2969   /*       -------------------------------        */
2970   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2971   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2972   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2973   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2974   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2975   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2976   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2977   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2978   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2979   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2980   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2981   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2982   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2983   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2984   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2985   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2986   /*       -------------------------------        */
2987   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2988 };
2989
2990 static char obuf[100];
2991 static char *obufp;
2992 static char *mnemonicendp;
2993 static char scratchbuf[100];
2994 static unsigned char *start_codep;
2995 static unsigned char *insn_codep;
2996 static unsigned char *codep;
2997 static unsigned char *end_codep;
2998 static int last_lock_prefix;
2999 static int last_repz_prefix;
3000 static int last_repnz_prefix;
3001 static int last_data_prefix;
3002 static int last_addr_prefix;
3003 static int last_rex_prefix;
3004 static int last_seg_prefix;
3005 static int fwait_prefix;
3006 /* The active segment register prefix.  */
3007 static int active_seg_prefix;
3008 #define MAX_CODE_LENGTH 15
3009 /* We can up to 14 prefixes since the maximum instruction length is
3010    15bytes.  */
3011 static int all_prefixes[MAX_CODE_LENGTH - 1];
3012 static disassemble_info *the_info;
3013 static struct
3014   {
3015     int mod;
3016     int reg;
3017     int rm;
3018   }
3019 modrm;
3020 static unsigned char need_modrm;
3021 static struct
3022   {
3023     int scale;
3024     int index;
3025     int base;
3026   }
3027 sib;
3028 static struct
3029   {
3030     int register_specifier;
3031     int length;
3032     int prefix;
3033     int w;
3034     int evex;
3035     int r;
3036     int v;
3037     int mask_register_specifier;
3038     int zeroing;
3039     int ll;
3040     int b;
3041   }
3042 vex;
3043 static unsigned char need_vex;
3044 static unsigned char need_vex_reg;
3045 static unsigned char vex_w_done;
3046
3047 struct op
3048   {
3049     const char *name;
3050     unsigned int len;
3051   };
3052
3053 /* If we are accessing mod/rm/reg without need_modrm set, then the
3054    values are stale.  Hitting this abort likely indicates that you
3055    need to update onebyte_has_modrm or twobyte_has_modrm.  */
3056 #define MODRM_CHECK  if (!need_modrm) abort ()
3057
3058 static const char **names64;
3059 static const char **names32;
3060 static const char **names16;
3061 static const char **names8;
3062 static const char **names8rex;
3063 static const char **names_seg;
3064 static const char *index64;
3065 static const char *index32;
3066 static const char **index16;
3067 static const char **names_bnd;
3068
3069 static const char *intel_names64[] = {
3070   "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3071   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3072 };
3073 static const char *intel_names32[] = {
3074   "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3075   "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3076 };
3077 static const char *intel_names16[] = {
3078   "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3079   "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3080 };
3081 static const char *intel_names8[] = {
3082   "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3083 };
3084 static const char *intel_names8rex[] = {
3085   "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3086   "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3087 };
3088 static const char *intel_names_seg[] = {
3089   "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3090 };
3091 static const char *intel_index64 = "riz";
3092 static const char *intel_index32 = "eiz";
3093 static const char *intel_index16[] = {
3094   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3095 };
3096
3097 static const char *att_names64[] = {
3098   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3099   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3100 };
3101 static const char *att_names32[] = {
3102   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3103   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3104 };
3105 static const char *att_names16[] = {
3106   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3107   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3108 };
3109 static const char *att_names8[] = {
3110   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3111 };
3112 static const char *att_names8rex[] = {
3113   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3114   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3115 };
3116 static const char *att_names_seg[] = {
3117   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3118 };
3119 static const char *att_index64 = "%riz";
3120 static const char *att_index32 = "%eiz";
3121 static const char *att_index16[] = {
3122   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3123 };
3124
3125 static const char **names_mm;
3126 static const char *intel_names_mm[] = {
3127   "mm0", "mm1", "mm2", "mm3",
3128   "mm4", "mm5", "mm6", "mm7"
3129 };
3130 static const char *att_names_mm[] = {
3131   "%mm0", "%mm1", "%mm2", "%mm3",
3132   "%mm4", "%mm5", "%mm6", "%mm7"
3133 };
3134
3135 static const char *intel_names_bnd[] = {
3136   "bnd0", "bnd1", "bnd2", "bnd3"
3137 };
3138
3139 static const char *att_names_bnd[] = {
3140   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3141 };
3142
3143 static const char **names_xmm;
3144 static const char *intel_names_xmm[] = {
3145   "xmm0", "xmm1", "xmm2", "xmm3",
3146   "xmm4", "xmm5", "xmm6", "xmm7",
3147   "xmm8", "xmm9", "xmm10", "xmm11",
3148   "xmm12", "xmm13", "xmm14", "xmm15",
3149   "xmm16", "xmm17", "xmm18", "xmm19",
3150   "xmm20", "xmm21", "xmm22", "xmm23",
3151   "xmm24", "xmm25", "xmm26", "xmm27",
3152   "xmm28", "xmm29", "xmm30", "xmm31"
3153 };
3154 static const char *att_names_xmm[] = {
3155   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3156   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3157   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3158   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3159   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3160   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3161   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3162   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3163 };
3164
3165 static const char **names_ymm;
3166 static const char *intel_names_ymm[] = {
3167   "ymm0", "ymm1", "ymm2", "ymm3",
3168   "ymm4", "ymm5", "ymm6", "ymm7",
3169   "ymm8", "ymm9", "ymm10", "ymm11",
3170   "ymm12", "ymm13", "ymm14", "ymm15",
3171   "ymm16", "ymm17", "ymm18", "ymm19",
3172   "ymm20", "ymm21", "ymm22", "ymm23",
3173   "ymm24", "ymm25", "ymm26", "ymm27",
3174   "ymm28", "ymm29", "ymm30", "ymm31"
3175 };
3176 static const char *att_names_ymm[] = {
3177   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3178   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3179   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3180   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3181   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3182   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3183   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3184   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3185 };
3186
3187 static const char **names_zmm;
3188 static const char *intel_names_zmm[] = {
3189   "zmm0", "zmm1", "zmm2", "zmm3",
3190   "zmm4", "zmm5", "zmm6", "zmm7",
3191   "zmm8", "zmm9", "zmm10", "zmm11",
3192   "zmm12", "zmm13", "zmm14", "zmm15",
3193   "zmm16", "zmm17", "zmm18", "zmm19",
3194   "zmm20", "zmm21", "zmm22", "zmm23",
3195   "zmm24", "zmm25", "zmm26", "zmm27",
3196   "zmm28", "zmm29", "zmm30", "zmm31"
3197 };
3198 static const char *att_names_zmm[] = {
3199   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3200   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3201   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3202   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3203   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3204   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3205   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3206   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3207 };
3208
3209 static const char **names_mask;
3210 static const char *intel_names_mask[] = {
3211   "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3212 };
3213 static const char *att_names_mask[] = {
3214   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3215 };
3216
3217 static const char *names_rounding[] =
3218 {
3219   "{rn-sae}",
3220   "{rd-sae}",
3221   "{ru-sae}",
3222   "{rz-sae}"
3223 };
3224
3225 static const struct dis386 reg_table[][8] = {
3226   /* REG_80 */
3227   {
3228     { "addA",   { Ebh1, Ib }, 0 },
3229     { "orA",    { Ebh1, Ib }, 0 },
3230     { "adcA",   { Ebh1, Ib }, 0 },
3231     { "sbbA",   { Ebh1, Ib }, 0 },
3232     { "andA",   { Ebh1, Ib }, 0 },
3233     { "subA",   { Ebh1, Ib }, 0 },
3234     { "xorA",   { Ebh1, Ib }, 0 },
3235     { "cmpA",   { Eb, Ib }, 0 },
3236   },
3237   /* REG_81 */
3238   {
3239     { "addQ",   { Evh1, Iv }, 0 },
3240     { "orQ",    { Evh1, Iv }, 0 },
3241     { "adcQ",   { Evh1, Iv }, 0 },
3242     { "sbbQ",   { Evh1, Iv }, 0 },
3243     { "andQ",   { Evh1, Iv }, 0 },
3244     { "subQ",   { Evh1, Iv }, 0 },
3245     { "xorQ",   { Evh1, Iv }, 0 },
3246     { "cmpQ",   { Ev, Iv }, 0 },
3247   },
3248   /* REG_83 */
3249   {
3250     { "addQ",   { Evh1, sIb }, 0 },
3251     { "orQ",    { Evh1, sIb }, 0 },
3252     { "adcQ",   { Evh1, sIb }, 0 },
3253     { "sbbQ",   { Evh1, sIb }, 0 },
3254     { "andQ",   { Evh1, sIb }, 0 },
3255     { "subQ",   { Evh1, sIb }, 0 },
3256     { "xorQ",   { Evh1, sIb }, 0 },
3257     { "cmpQ",   { Ev, sIb }, 0 },
3258   },
3259   /* REG_8F */
3260   {
3261     { "popU",   { stackEv }, 0 },
3262     { XOP_8F_TABLE (XOP_09) },
3263     { Bad_Opcode },
3264     { Bad_Opcode },
3265     { Bad_Opcode },
3266     { XOP_8F_TABLE (XOP_09) },
3267   },
3268   /* REG_C0 */
3269   {
3270     { "rolA",   { Eb, Ib }, 0 },
3271     { "rorA",   { Eb, Ib }, 0 },
3272     { "rclA",   { Eb, Ib }, 0 },
3273     { "rcrA",   { Eb, Ib }, 0 },
3274     { "shlA",   { Eb, Ib }, 0 },
3275     { "shrA",   { Eb, Ib }, 0 },
3276     { "shlA",   { Eb, Ib }, 0 },
3277     { "sarA",   { Eb, Ib }, 0 },
3278   },
3279   /* REG_C1 */
3280   {
3281     { "rolQ",   { Ev, Ib }, 0 },
3282     { "rorQ",   { Ev, Ib }, 0 },
3283     { "rclQ",   { Ev, Ib }, 0 },
3284     { "rcrQ",   { Ev, Ib }, 0 },
3285     { "shlQ",   { Ev, Ib }, 0 },
3286     { "shrQ",   { Ev, Ib }, 0 },
3287     { "shlQ",   { Ev, Ib }, 0 },
3288     { "sarQ",   { Ev, Ib }, 0 },
3289   },
3290   /* REG_C6 */
3291   {
3292     { "movA",   { Ebh3, Ib }, 0 },
3293     { Bad_Opcode },
3294     { Bad_Opcode },
3295     { Bad_Opcode },
3296     { Bad_Opcode },
3297     { Bad_Opcode },
3298     { Bad_Opcode },
3299     { MOD_TABLE (MOD_C6_REG_7) },
3300   },
3301   /* REG_C7 */
3302   {
3303     { "movQ",   { Evh3, Iv }, 0 },
3304     { Bad_Opcode },
3305     { Bad_Opcode },
3306     { Bad_Opcode },
3307     { Bad_Opcode },
3308     { Bad_Opcode },
3309     { Bad_Opcode },
3310     { MOD_TABLE (MOD_C7_REG_7) },
3311   },
3312   /* REG_D0 */
3313   {
3314     { "rolA",   { Eb, I1 }, 0 },
3315     { "rorA",   { Eb, I1 }, 0 },
3316     { "rclA",   { Eb, I1 }, 0 },
3317     { "rcrA",   { Eb, I1 }, 0 },
3318     { "shlA",   { Eb, I1 }, 0 },
3319     { "shrA",   { Eb, I1 }, 0 },
3320     { "shlA",   { Eb, I1 }, 0 },
3321     { "sarA",   { Eb, I1 }, 0 },
3322   },
3323   /* REG_D1 */
3324   {
3325     { "rolQ",   { Ev, I1 }, 0 },
3326     { "rorQ",   { Ev, I1 }, 0 },
3327     { "rclQ",   { Ev, I1 }, 0 },
3328     { "rcrQ",   { Ev, I1 }, 0 },
3329     { "shlQ",   { Ev, I1 }, 0 },
3330     { "shrQ",   { Ev, I1 }, 0 },
3331     { "shlQ",   { Ev, I1 }, 0 },
3332     { "sarQ",   { Ev, I1 }, 0 },
3333   },
3334   /* REG_D2 */
3335   {
3336     { "rolA",   { Eb, CL }, 0 },
3337     { "rorA",   { Eb, CL }, 0 },
3338     { "rclA",   { Eb, CL }, 0 },
3339     { "rcrA",   { Eb, CL }, 0 },
3340     { "shlA",   { Eb, CL }, 0 },
3341     { "shrA",   { Eb, CL }, 0 },
3342     { "shlA",   { Eb, CL }, 0 },
3343     { "sarA",   { Eb, CL }, 0 },
3344   },
3345   /* REG_D3 */
3346   {
3347     { "rolQ",   { Ev, CL }, 0 },
3348     { "rorQ",   { Ev, CL }, 0 },
3349     { "rclQ",   { Ev, CL }, 0 },
3350     { "rcrQ",   { Ev, CL }, 0 },
3351     { "shlQ",   { Ev, CL }, 0 },
3352     { "shrQ",   { Ev, CL }, 0 },
3353     { "shlQ",   { Ev, CL }, 0 },
3354     { "sarQ",   { Ev, CL }, 0 },
3355   },
3356   /* REG_F6 */
3357   {
3358     { "testA",  { Eb, Ib }, 0 },
3359     { "testA",  { Eb, Ib }, 0 },
3360     { "notA",   { Ebh1 }, 0 },
3361     { "negA",   { Ebh1 }, 0 },
3362     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
3363     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
3364     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
3365     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
3366   },
3367   /* REG_F7 */
3368   {
3369     { "testQ",  { Ev, Iv }, 0 },
3370     { "testQ",  { Ev, Iv }, 0 },
3371     { "notQ",   { Evh1 }, 0 },
3372     { "negQ",   { Evh1 }, 0 },
3373     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
3374     { "imulQ",  { Ev }, 0 },
3375     { "divQ",   { Ev }, 0 },
3376     { "idivQ",  { Ev }, 0 },
3377   },
3378   /* REG_FE */
3379   {
3380     { "incA",   { Ebh1 }, 0 },
3381     { "decA",   { Ebh1 }, 0 },
3382   },
3383   /* REG_FF */
3384   {
3385     { "incQ",   { Evh1 }, 0 },
3386     { "decQ",   { Evh1 }, 0 },
3387     { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3388     { MOD_TABLE (MOD_FF_REG_3) },
3389     { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3390     { MOD_TABLE (MOD_FF_REG_5) },
3391     { "pushU",  { stackEv }, 0 },
3392     { Bad_Opcode },
3393   },
3394   /* REG_0F00 */
3395   {
3396     { "sldtD",  { Sv }, 0 },
3397     { "strD",   { Sv }, 0 },
3398     { "lldt",   { Ew }, 0 },
3399     { "ltr",    { Ew }, 0 },
3400     { "verr",   { Ew }, 0 },
3401     { "verw",   { Ew }, 0 },
3402     { Bad_Opcode },
3403     { Bad_Opcode },
3404   },
3405   /* REG_0F01 */
3406   {
3407     { MOD_TABLE (MOD_0F01_REG_0) },
3408     { MOD_TABLE (MOD_0F01_REG_1) },
3409     { MOD_TABLE (MOD_0F01_REG_2) },
3410     { MOD_TABLE (MOD_0F01_REG_3) },
3411     { "smswD",  { Sv }, 0 },
3412     { MOD_TABLE (MOD_0F01_REG_5) },
3413     { "lmsw",   { Ew }, 0 },
3414     { MOD_TABLE (MOD_0F01_REG_7) },
3415   },
3416   /* REG_0F0D */
3417   {
3418     { "prefetch",       { Mb }, 0 },
3419     { "prefetchw",      { Mb }, 0 },
3420     { "prefetchwt1",    { Mb }, 0 },
3421     { "prefetch",       { Mb }, 0 },
3422     { "prefetch",       { Mb }, 0 },
3423     { "prefetch",       { Mb }, 0 },
3424     { "prefetch",       { Mb }, 0 },
3425     { "prefetch",       { Mb }, 0 },
3426   },
3427   /* REG_0F18 */
3428   {
3429     { MOD_TABLE (MOD_0F18_REG_0) },
3430     { MOD_TABLE (MOD_0F18_REG_1) },
3431     { MOD_TABLE (MOD_0F18_REG_2) },
3432     { MOD_TABLE (MOD_0F18_REG_3) },
3433     { MOD_TABLE (MOD_0F18_REG_4) },
3434     { MOD_TABLE (MOD_0F18_REG_5) },
3435     { MOD_TABLE (MOD_0F18_REG_6) },
3436     { MOD_TABLE (MOD_0F18_REG_7) },
3437   },
3438   /* REG_0F1C_P_0_MOD_0 */
3439   {
3440     { "cldemote",       { Mb }, 0 },
3441     { "nopQ",           { Ev }, 0 },
3442     { "nopQ",           { Ev }, 0 },
3443     { "nopQ",           { Ev }, 0 },
3444     { "nopQ",           { Ev }, 0 },
3445     { "nopQ",           { Ev }, 0 },
3446     { "nopQ",           { Ev }, 0 },
3447     { "nopQ",           { Ev }, 0 },
3448   },
3449   /* REG_0F1E_P_1_MOD_3 */
3450   {
3451     { "nopQ",           { Ev }, 0 },
3452     { "rdsspK",         { Rdq }, PREFIX_OPCODE },
3453     { "nopQ",           { Ev }, 0 },
3454     { "nopQ",           { Ev }, 0 },
3455     { "nopQ",           { Ev }, 0 },
3456     { "nopQ",           { Ev }, 0 },
3457     { "nopQ",           { Ev }, 0 },
3458     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
3459   },
3460   /* REG_0F71 */
3461   {
3462     { Bad_Opcode },
3463     { Bad_Opcode },
3464     { MOD_TABLE (MOD_0F71_REG_2) },
3465     { Bad_Opcode },
3466     { MOD_TABLE (MOD_0F71_REG_4) },
3467     { Bad_Opcode },
3468     { MOD_TABLE (MOD_0F71_REG_6) },
3469   },
3470   /* REG_0F72 */
3471   {
3472     { Bad_Opcode },
3473     { Bad_Opcode },
3474     { MOD_TABLE (MOD_0F72_REG_2) },
3475     { Bad_Opcode },
3476     { MOD_TABLE (MOD_0F72_REG_4) },
3477     { Bad_Opcode },
3478     { MOD_TABLE (MOD_0F72_REG_6) },
3479   },
3480   /* REG_0F73 */
3481   {
3482     { Bad_Opcode },
3483     { Bad_Opcode },
3484     { MOD_TABLE (MOD_0F73_REG_2) },
3485     { MOD_TABLE (MOD_0F73_REG_3) },
3486     { Bad_Opcode },
3487     { Bad_Opcode },
3488     { MOD_TABLE (MOD_0F73_REG_6) },
3489     { MOD_TABLE (MOD_0F73_REG_7) },
3490   },
3491   /* REG_0FA6 */
3492   {
3493     { "montmul",        { { OP_0f07, 0 } }, 0 },
3494     { "xsha1",          { { OP_0f07, 0 } }, 0 },
3495     { "xsha256",        { { OP_0f07, 0 } }, 0 },
3496   },
3497   /* REG_0FA7 */
3498   {
3499     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
3500     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
3501     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
3502     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
3503     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
3504     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
3505   },
3506   /* REG_0FAE */
3507   {
3508     { MOD_TABLE (MOD_0FAE_REG_0) },
3509     { MOD_TABLE (MOD_0FAE_REG_1) },
3510     { MOD_TABLE (MOD_0FAE_REG_2) },
3511     { MOD_TABLE (MOD_0FAE_REG_3) },
3512     { MOD_TABLE (MOD_0FAE_REG_4) },
3513     { MOD_TABLE (MOD_0FAE_REG_5) },
3514     { MOD_TABLE (MOD_0FAE_REG_6) },
3515     { MOD_TABLE (MOD_0FAE_REG_7) },
3516   },
3517   /* REG_0FBA */
3518   {
3519     { Bad_Opcode },
3520     { Bad_Opcode },
3521     { Bad_Opcode },
3522     { Bad_Opcode },
3523     { "btQ",    { Ev, Ib }, 0 },
3524     { "btsQ",   { Evh1, Ib }, 0 },
3525     { "btrQ",   { Evh1, Ib }, 0 },
3526     { "btcQ",   { Evh1, Ib }, 0 },
3527   },
3528   /* REG_0FC7 */
3529   {
3530     { Bad_Opcode },
3531     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3532     { Bad_Opcode },
3533     { MOD_TABLE (MOD_0FC7_REG_3) },
3534     { MOD_TABLE (MOD_0FC7_REG_4) },
3535     { MOD_TABLE (MOD_0FC7_REG_5) },
3536     { MOD_TABLE (MOD_0FC7_REG_6) },
3537     { MOD_TABLE (MOD_0FC7_REG_7) },
3538   },
3539   /* REG_VEX_0F71 */
3540   {
3541     { Bad_Opcode },
3542     { Bad_Opcode },
3543     { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3544     { Bad_Opcode },
3545     { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3546     { Bad_Opcode },
3547     { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3548   },
3549   /* REG_VEX_0F72 */
3550   {
3551     { Bad_Opcode },
3552     { Bad_Opcode },
3553     { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3554     { Bad_Opcode },
3555     { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3556     { Bad_Opcode },
3557     { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3558   },
3559   /* REG_VEX_0F73 */
3560   {
3561     { Bad_Opcode },
3562     { Bad_Opcode },
3563     { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3564     { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3565     { Bad_Opcode },
3566     { Bad_Opcode },
3567     { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3568     { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3569   },
3570   /* REG_VEX_0FAE */
3571   {
3572     { Bad_Opcode },
3573     { Bad_Opcode },
3574     { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3575     { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3576   },
3577   /* REG_VEX_0F38F3 */
3578   {
3579     { Bad_Opcode },
3580     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3581     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3582     { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3583   },
3584   /* REG_XOP_LWPCB */
3585   {
3586     { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3587     { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3588   },
3589   /* REG_XOP_LWP */
3590   {
3591     { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3592     { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3593   },
3594   /* REG_XOP_TBM_01 */
3595   {
3596     { Bad_Opcode },
3597     { "blcfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3598     { "blsfill",        { { OP_LWP_E, 0 }, Edq }, 0 },
3599     { "blcs",   { { OP_LWP_E, 0 }, Edq }, 0 },
3600     { "tzmsk",  { { OP_LWP_E, 0 }, Edq }, 0 },
3601     { "blcic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3602     { "blsic",  { { OP_LWP_E, 0 }, Edq }, 0 },
3603     { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3604   },
3605   /* REG_XOP_TBM_02 */
3606   {
3607     { Bad_Opcode },
3608     { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3609     { Bad_Opcode },
3610     { Bad_Opcode },
3611     { Bad_Opcode },
3612     { Bad_Opcode },
3613     { "blci",   { { OP_LWP_E, 0 }, Edq }, 0 },
3614   },
3615
3616 #include "i386-dis-evex-reg.h"
3617 };
3618
3619 static const struct dis386 prefix_table[][4] = {
3620   /* PREFIX_90 */
3621   {
3622     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3623     { "pause", { XX }, 0 },
3624     { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3625     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3626   },
3627
3628   /* PREFIX_0F01_REG_5_MOD_0 */
3629   {
3630     { Bad_Opcode },
3631     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3632   },
3633
3634   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3635   {
3636     { Bad_Opcode },
3637     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3638   },
3639
3640   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3641   {
3642     { Bad_Opcode },
3643     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F09 */
3647   {
3648     { "wbinvd",   { XX }, 0 },
3649     { "wbnoinvd", { XX }, 0 },
3650   },
3651
3652   /* PREFIX_0F10 */
3653   {
3654     { "movups", { XM, EXx }, PREFIX_OPCODE },
3655     { "movss",  { XM, EXd }, PREFIX_OPCODE },
3656     { "movupd", { XM, EXx }, PREFIX_OPCODE },
3657     { "movsd",  { XM, EXq }, PREFIX_OPCODE },
3658   },
3659
3660   /* PREFIX_0F11 */
3661   {
3662     { "movups", { EXxS, XM }, PREFIX_OPCODE },
3663     { "movss",  { EXdS, XM }, PREFIX_OPCODE },
3664     { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3665     { "movsd",  { EXqS, XM }, PREFIX_OPCODE },
3666   },
3667
3668   /* PREFIX_0F12 */
3669   {
3670     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3671     { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3672     { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3673     { "movddup", { XM, EXq }, PREFIX_OPCODE },
3674   },
3675
3676   /* PREFIX_0F16 */
3677   {
3678     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3679     { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3680     { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3681   },
3682
3683   /* PREFIX_0F1A */
3684   {
3685     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3686     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3687     { "bndmov", { Gbnd, Ebnd }, 0 },
3688     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3689   },
3690
3691   /* PREFIX_0F1B */
3692   {
3693     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3694     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3695     { "bndmov", { EbndS, Gbnd }, 0 },
3696     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3697   },
3698
3699   /* PREFIX_0F1C */
3700   {
3701     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3702     { "nopQ",   { Ev }, PREFIX_OPCODE },
3703     { "nopQ",   { Ev }, PREFIX_OPCODE },
3704     { "nopQ",   { Ev }, PREFIX_OPCODE },
3705   },
3706
3707   /* PREFIX_0F1E */
3708   {
3709     { "nopQ",   { Ev }, PREFIX_OPCODE },
3710     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3711     { "nopQ",   { Ev }, PREFIX_OPCODE },
3712     { "nopQ",   { Ev }, PREFIX_OPCODE },
3713   },
3714
3715   /* PREFIX_0F2A */
3716   {
3717     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3718     { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3719     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3720     { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3721   },
3722
3723   /* PREFIX_0F2B */
3724   {
3725     { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3726     { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3727     { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3728     { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3729   },
3730
3731   /* PREFIX_0F2C */
3732   {
3733     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3734     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3735     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3736     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3737   },
3738
3739   /* PREFIX_0F2D */
3740   {
3741     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3742     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3743     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3744     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3745   },
3746
3747   /* PREFIX_0F2E */
3748   {
3749     { "ucomiss",{ XM, EXd }, 0 },
3750     { Bad_Opcode },
3751     { "ucomisd",{ XM, EXq }, 0 },
3752   },
3753
3754   /* PREFIX_0F2F */
3755   {
3756     { "comiss", { XM, EXd }, 0 },
3757     { Bad_Opcode },
3758     { "comisd", { XM, EXq }, 0 },
3759   },
3760
3761   /* PREFIX_0F51 */
3762   {
3763     { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3764     { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3765     { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3766     { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3767   },
3768
3769   /* PREFIX_0F52 */
3770   {
3771     { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3772     { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3773   },
3774
3775   /* PREFIX_0F53 */
3776   {
3777     { "rcpps",  { XM, EXx }, PREFIX_OPCODE },
3778     { "rcpss",  { XM, EXd }, PREFIX_OPCODE },
3779   },
3780
3781   /* PREFIX_0F58 */
3782   {
3783     { "addps", { XM, EXx }, PREFIX_OPCODE },
3784     { "addss", { XM, EXd }, PREFIX_OPCODE },
3785     { "addpd", { XM, EXx }, PREFIX_OPCODE },
3786     { "addsd", { XM, EXq }, PREFIX_OPCODE },
3787   },
3788
3789   /* PREFIX_0F59 */
3790   {
3791     { "mulps",  { XM, EXx }, PREFIX_OPCODE },
3792     { "mulss",  { XM, EXd }, PREFIX_OPCODE },
3793     { "mulpd",  { XM, EXx }, PREFIX_OPCODE },
3794     { "mulsd",  { XM, EXq }, PREFIX_OPCODE },
3795   },
3796
3797   /* PREFIX_0F5A */
3798   {
3799     { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3800     { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3801     { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3802     { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3803   },
3804
3805   /* PREFIX_0F5B */
3806   {
3807     { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3808     { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3809     { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3810   },
3811
3812   /* PREFIX_0F5C */
3813   {
3814     { "subps",  { XM, EXx }, PREFIX_OPCODE },
3815     { "subss",  { XM, EXd }, PREFIX_OPCODE },
3816     { "subpd",  { XM, EXx }, PREFIX_OPCODE },
3817     { "subsd",  { XM, EXq }, PREFIX_OPCODE },
3818   },
3819
3820   /* PREFIX_0F5D */
3821   {
3822     { "minps",  { XM, EXx }, PREFIX_OPCODE },
3823     { "minss",  { XM, EXd }, PREFIX_OPCODE },
3824     { "minpd",  { XM, EXx }, PREFIX_OPCODE },
3825     { "minsd",  { XM, EXq }, PREFIX_OPCODE },
3826   },
3827
3828   /* PREFIX_0F5E */
3829   {
3830     { "divps",  { XM, EXx }, PREFIX_OPCODE },
3831     { "divss",  { XM, EXd }, PREFIX_OPCODE },
3832     { "divpd",  { XM, EXx }, PREFIX_OPCODE },
3833     { "divsd",  { XM, EXq }, PREFIX_OPCODE },
3834   },
3835
3836   /* PREFIX_0F5F */
3837   {
3838     { "maxps",  { XM, EXx }, PREFIX_OPCODE },
3839     { "maxss",  { XM, EXd }, PREFIX_OPCODE },
3840     { "maxpd",  { XM, EXx }, PREFIX_OPCODE },
3841     { "maxsd",  { XM, EXq }, PREFIX_OPCODE },
3842   },
3843
3844   /* PREFIX_0F60 */
3845   {
3846     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3847     { Bad_Opcode },
3848     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3849   },
3850
3851   /* PREFIX_0F61 */
3852   {
3853     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3854     { Bad_Opcode },
3855     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3856   },
3857
3858   /* PREFIX_0F62 */
3859   {
3860     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3861     { Bad_Opcode },
3862     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3863   },
3864
3865   /* PREFIX_0F6C */
3866   {
3867     { Bad_Opcode },
3868     { Bad_Opcode },
3869     { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3870   },
3871
3872   /* PREFIX_0F6D */
3873   {
3874     { Bad_Opcode },
3875     { Bad_Opcode },
3876     { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3877   },
3878
3879   /* PREFIX_0F6F */
3880   {
3881     { "movq",   { MX, EM }, PREFIX_OPCODE },
3882     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3883     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3884   },
3885
3886   /* PREFIX_0F70 */
3887   {
3888     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3889     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3890     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3891     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3892   },
3893
3894   /* PREFIX_0F73_REG_3 */
3895   {
3896     { Bad_Opcode },
3897     { Bad_Opcode },
3898     { "psrldq", { XS, Ib }, 0 },
3899   },
3900
3901   /* PREFIX_0F73_REG_7 */
3902   {
3903     { Bad_Opcode },
3904     { Bad_Opcode },
3905     { "pslldq", { XS, Ib }, 0 },
3906   },
3907
3908   /* PREFIX_0F78 */
3909   {
3910     {"vmread",  { Em, Gm }, 0 },
3911     { Bad_Opcode },
3912     {"extrq",   { XS, Ib, Ib }, 0 },
3913     {"insertq", { XM, XS, Ib, Ib }, 0 },
3914   },
3915
3916   /* PREFIX_0F79 */
3917   {
3918     {"vmwrite", { Gm, Em }, 0 },
3919     { Bad_Opcode },
3920     {"extrq",   { XM, XS }, 0 },
3921     {"insertq", { XM, XS }, 0 },
3922   },
3923
3924   /* PREFIX_0F7C */
3925   {
3926     { Bad_Opcode },
3927     { Bad_Opcode },
3928     { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3929     { "haddps", { XM, EXx }, PREFIX_OPCODE },
3930   },
3931
3932   /* PREFIX_0F7D */
3933   {
3934     { Bad_Opcode },
3935     { Bad_Opcode },
3936     { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3937     { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3938   },
3939
3940   /* PREFIX_0F7E */
3941   {
3942     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3943     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3944     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3945   },
3946
3947   /* PREFIX_0F7F */
3948   {
3949     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3950     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3951     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3952   },
3953
3954   /* PREFIX_0FAE_REG_0_MOD_3 */
3955   {
3956     { Bad_Opcode },
3957     { "rdfsbase", { Ev }, 0 },
3958   },
3959
3960   /* PREFIX_0FAE_REG_1_MOD_3 */
3961   {
3962     { Bad_Opcode },
3963     { "rdgsbase", { Ev }, 0 },
3964   },
3965
3966   /* PREFIX_0FAE_REG_2_MOD_3 */
3967   {
3968     { Bad_Opcode },
3969     { "wrfsbase", { Ev }, 0 },
3970   },
3971
3972   /* PREFIX_0FAE_REG_3_MOD_3 */
3973   {
3974     { Bad_Opcode },
3975     { "wrgsbase", { Ev }, 0 },
3976   },
3977
3978   /* PREFIX_0FAE_REG_4_MOD_0 */
3979   {
3980     { "xsave",  { FXSAVE }, 0 },
3981     { "ptwrite%LQ", { Edq }, 0 },
3982   },
3983
3984   /* PREFIX_0FAE_REG_4_MOD_3 */
3985   {
3986     { Bad_Opcode },
3987     { "ptwrite%LQ", { Edq }, 0 },
3988   },
3989
3990   /* PREFIX_0FAE_REG_5_MOD_0 */
3991   {
3992     { "xrstor",         { FXSAVE }, PREFIX_OPCODE },
3993   },
3994
3995   /* PREFIX_0FAE_REG_5_MOD_3 */
3996   {
3997     { "lfence",         { Skip_MODRM }, 0 },
3998     { "incsspK",        { Rdq }, PREFIX_OPCODE },
3999   },
4000
4001   /* PREFIX_0FAE_REG_6_MOD_0 */
4002   {
4003     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE },
4004     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
4005     { "clwb",   { Mb }, PREFIX_OPCODE },
4006   },
4007
4008   /* PREFIX_0FAE_REG_6_MOD_3 */
4009   {
4010     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
4011     { "umonitor",       { Eva }, PREFIX_OPCODE },
4012     { "tpause", { Edq }, PREFIX_OPCODE },
4013     { "umwait", { Edq }, PREFIX_OPCODE },
4014   },
4015
4016   /* PREFIX_0FAE_REG_7_MOD_0 */
4017   {
4018     { "clflush",        { Mb }, 0 },
4019     { Bad_Opcode },
4020     { "clflushopt",     { Mb }, 0 },
4021   },
4022
4023   /* PREFIX_0FB8 */
4024   {
4025     { Bad_Opcode },
4026     { "popcntS", { Gv, Ev }, 0 },
4027   },
4028
4029   /* PREFIX_0FBC */
4030   {
4031     { "bsfS",   { Gv, Ev }, 0 },
4032     { "tzcntS", { Gv, Ev }, 0 },
4033     { "bsfS",   { Gv, Ev }, 0 },
4034   },
4035
4036   /* PREFIX_0FBD */
4037   {
4038     { "bsrS",   { Gv, Ev }, 0 },
4039     { "lzcntS", { Gv, Ev }, 0 },
4040     { "bsrS",   { Gv, Ev }, 0 },
4041   },
4042
4043   /* PREFIX_0FC2 */
4044   {
4045     { "cmpps",  { XM, EXx, CMP }, PREFIX_OPCODE },
4046     { "cmpss",  { XM, EXd, CMP }, PREFIX_OPCODE },
4047     { "cmppd",  { XM, EXx, CMP }, PREFIX_OPCODE },
4048     { "cmpsd",  { XM, EXq, CMP }, PREFIX_OPCODE },
4049   },
4050
4051   /* PREFIX_0FC3_MOD_0 */
4052   {
4053     { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4054   },
4055
4056   /* PREFIX_0FC7_REG_6_MOD_0 */
4057   {
4058     { "vmptrld",{ Mq }, 0 },
4059     { "vmxon",  { Mq }, 0 },
4060     { "vmclear",{ Mq }, 0 },
4061   },
4062
4063   /* PREFIX_0FC7_REG_6_MOD_3 */
4064   {
4065     { "rdrand", { Ev }, 0 },
4066     { Bad_Opcode },
4067     { "rdrand", { Ev }, 0 }
4068   },
4069
4070   /* PREFIX_0FC7_REG_7_MOD_3 */
4071   {
4072     { "rdseed", { Ev }, 0 },
4073     { "rdpid",  { Em }, 0 },
4074     { "rdseed", { Ev }, 0 },
4075   },
4076
4077   /* PREFIX_0FD0 */
4078   {
4079     { Bad_Opcode },
4080     { Bad_Opcode },
4081     { "addsubpd", { XM, EXx }, 0 },
4082     { "addsubps", { XM, EXx }, 0 },
4083   },
4084
4085   /* PREFIX_0FD6 */
4086   {
4087     { Bad_Opcode },
4088     { "movq2dq",{ XM, MS }, 0 },
4089     { "movq",   { EXqS, XM }, 0 },
4090     { "movdq2q",{ MX, XS }, 0 },
4091   },
4092
4093   /* PREFIX_0FE6 */
4094   {
4095     { Bad_Opcode },
4096     { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4097     { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4098     { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4099   },
4100
4101   /* PREFIX_0FE7 */
4102   {
4103     { "movntq", { Mq, MX }, PREFIX_OPCODE },
4104     { Bad_Opcode },
4105     { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4106   },
4107
4108   /* PREFIX_0FF0 */
4109   {
4110     { Bad_Opcode },
4111     { Bad_Opcode },
4112     { Bad_Opcode },
4113     { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4114   },
4115
4116   /* PREFIX_0FF7 */
4117   {
4118     { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4119     { Bad_Opcode },
4120     { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4121   },
4122
4123   /* PREFIX_0F3810 */
4124   {
4125     { Bad_Opcode },
4126     { Bad_Opcode },
4127     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4128   },
4129
4130   /* PREFIX_0F3814 */
4131   {
4132     { Bad_Opcode },
4133     { Bad_Opcode },
4134     { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4135   },
4136
4137   /* PREFIX_0F3815 */
4138   {
4139     { Bad_Opcode },
4140     { Bad_Opcode },
4141     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4142   },
4143
4144   /* PREFIX_0F3817 */
4145   {
4146     { Bad_Opcode },
4147     { Bad_Opcode },
4148     { "ptest",  { XM, EXx }, PREFIX_OPCODE },
4149   },
4150
4151   /* PREFIX_0F3820 */
4152   {
4153     { Bad_Opcode },
4154     { Bad_Opcode },
4155     { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4156   },
4157
4158   /* PREFIX_0F3821 */
4159   {
4160     { Bad_Opcode },
4161     { Bad_Opcode },
4162     { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4163   },
4164
4165   /* PREFIX_0F3822 */
4166   {
4167     { Bad_Opcode },
4168     { Bad_Opcode },
4169     { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4170   },
4171
4172   /* PREFIX_0F3823 */
4173   {
4174     { Bad_Opcode },
4175     { Bad_Opcode },
4176     { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4177   },
4178
4179   /* PREFIX_0F3824 */
4180   {
4181     { Bad_Opcode },
4182     { Bad_Opcode },
4183     { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4184   },
4185
4186   /* PREFIX_0F3825 */
4187   {
4188     { Bad_Opcode },
4189     { Bad_Opcode },
4190     { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4191   },
4192
4193   /* PREFIX_0F3828 */
4194   {
4195     { Bad_Opcode },
4196     { Bad_Opcode },
4197     { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4198   },
4199
4200   /* PREFIX_0F3829 */
4201   {
4202     { Bad_Opcode },
4203     { Bad_Opcode },
4204     { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4205   },
4206
4207   /* PREFIX_0F382A */
4208   {
4209     { Bad_Opcode },
4210     { Bad_Opcode },
4211     { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4212   },
4213
4214   /* PREFIX_0F382B */
4215   {
4216     { Bad_Opcode },
4217     { Bad_Opcode },
4218     { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4219   },
4220
4221   /* PREFIX_0F3830 */
4222   {
4223     { Bad_Opcode },
4224     { Bad_Opcode },
4225     { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4226   },
4227
4228   /* PREFIX_0F3831 */
4229   {
4230     { Bad_Opcode },
4231     { Bad_Opcode },
4232     { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4233   },
4234
4235   /* PREFIX_0F3832 */
4236   {
4237     { Bad_Opcode },
4238     { Bad_Opcode },
4239     { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4240   },
4241
4242   /* PREFIX_0F3833 */
4243   {
4244     { Bad_Opcode },
4245     { Bad_Opcode },
4246     { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4247   },
4248
4249   /* PREFIX_0F3834 */
4250   {
4251     { Bad_Opcode },
4252     { Bad_Opcode },
4253     { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4254   },
4255
4256   /* PREFIX_0F3835 */
4257   {
4258     { Bad_Opcode },
4259     { Bad_Opcode },
4260     { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4261   },
4262
4263   /* PREFIX_0F3837 */
4264   {
4265     { Bad_Opcode },
4266     { Bad_Opcode },
4267     { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4268   },
4269
4270   /* PREFIX_0F3838 */
4271   {
4272     { Bad_Opcode },
4273     { Bad_Opcode },
4274     { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4275   },
4276
4277   /* PREFIX_0F3839 */
4278   {
4279     { Bad_Opcode },
4280     { Bad_Opcode },
4281     { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4282   },
4283
4284   /* PREFIX_0F383A */
4285   {
4286     { Bad_Opcode },
4287     { Bad_Opcode },
4288     { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4289   },
4290
4291   /* PREFIX_0F383B */
4292   {
4293     { Bad_Opcode },
4294     { Bad_Opcode },
4295     { "pminud", { XM, EXx }, PREFIX_OPCODE },
4296   },
4297
4298   /* PREFIX_0F383C */
4299   {
4300     { Bad_Opcode },
4301     { Bad_Opcode },
4302     { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4303   },
4304
4305   /* PREFIX_0F383D */
4306   {
4307     { Bad_Opcode },
4308     { Bad_Opcode },
4309     { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4310   },
4311
4312   /* PREFIX_0F383E */
4313   {
4314     { Bad_Opcode },
4315     { Bad_Opcode },
4316     { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4317   },
4318
4319   /* PREFIX_0F383F */
4320   {
4321     { Bad_Opcode },
4322     { Bad_Opcode },
4323     { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4324   },
4325
4326   /* PREFIX_0F3840 */
4327   {
4328     { Bad_Opcode },
4329     { Bad_Opcode },
4330     { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4331   },
4332
4333   /* PREFIX_0F3841 */
4334   {
4335     { Bad_Opcode },
4336     { Bad_Opcode },
4337     { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4338   },
4339
4340   /* PREFIX_0F3880 */
4341   {
4342     { Bad_Opcode },
4343     { Bad_Opcode },
4344     { "invept", { Gm, Mo }, PREFIX_OPCODE },
4345   },
4346
4347   /* PREFIX_0F3881 */
4348   {
4349     { Bad_Opcode },
4350     { Bad_Opcode },
4351     { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4352   },
4353
4354   /* PREFIX_0F3882 */
4355   {
4356     { Bad_Opcode },
4357     { Bad_Opcode },
4358     { "invpcid", { Gm, M }, PREFIX_OPCODE },
4359   },
4360
4361   /* PREFIX_0F38C8 */
4362   {
4363     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4364   },
4365
4366   /* PREFIX_0F38C9 */
4367   {
4368     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4369   },
4370
4371   /* PREFIX_0F38CA */
4372   {
4373     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4374   },
4375
4376   /* PREFIX_0F38CB */
4377   {
4378     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4379   },
4380
4381   /* PREFIX_0F38CC */
4382   {
4383     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4384   },
4385
4386   /* PREFIX_0F38CD */
4387   {
4388     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4389   },
4390
4391   /* PREFIX_0F38CF */
4392   {
4393     { Bad_Opcode },
4394     { Bad_Opcode },
4395     { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4396   },
4397
4398   /* PREFIX_0F38DB */
4399   {
4400     { Bad_Opcode },
4401     { Bad_Opcode },
4402     { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4403   },
4404
4405   /* PREFIX_0F38DC */
4406   {
4407     { Bad_Opcode },
4408     { Bad_Opcode },
4409     { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4410   },
4411
4412   /* PREFIX_0F38DD */
4413   {
4414     { Bad_Opcode },
4415     { Bad_Opcode },
4416     { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4417   },
4418
4419   /* PREFIX_0F38DE */
4420   {
4421     { Bad_Opcode },
4422     { Bad_Opcode },
4423     { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4424   },
4425
4426   /* PREFIX_0F38DF */
4427   {
4428     { Bad_Opcode },
4429     { Bad_Opcode },
4430     { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4431   },
4432
4433   /* PREFIX_0F38F0 */
4434   {
4435     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4436     { Bad_Opcode },
4437     { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4438     { "crc32",  { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4439   },
4440
4441   /* PREFIX_0F38F1 */
4442   {
4443     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4444     { Bad_Opcode },
4445     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4446     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4447   },
4448
4449   /* PREFIX_0F38F5 */
4450   {
4451     { Bad_Opcode },
4452     { Bad_Opcode },
4453     { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4454   },
4455
4456   /* PREFIX_0F38F6 */
4457   {
4458     { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4459     { "adoxS",  { Gdq, Edq}, PREFIX_OPCODE },
4460     { "adcxS",  { Gdq, Edq}, PREFIX_OPCODE },
4461     { Bad_Opcode },
4462   },
4463
4464   /* PREFIX_0F38F8 */
4465   {
4466     { Bad_Opcode },
4467     { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4468     { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4469     { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4470   },
4471
4472   /* PREFIX_0F38F9 */
4473   {
4474     { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4475   },
4476
4477   /* PREFIX_0F3A08 */
4478   {
4479     { Bad_Opcode },
4480     { Bad_Opcode },
4481     { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4482   },
4483
4484   /* PREFIX_0F3A09 */
4485   {
4486     { Bad_Opcode },
4487     { Bad_Opcode },
4488     { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4489   },
4490
4491   /* PREFIX_0F3A0A */
4492   {
4493     { Bad_Opcode },
4494     { Bad_Opcode },
4495     { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4496   },
4497
4498   /* PREFIX_0F3A0B */
4499   {
4500     { Bad_Opcode },
4501     { Bad_Opcode },
4502     { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4503   },
4504
4505   /* PREFIX_0F3A0C */
4506   {
4507     { Bad_Opcode },
4508     { Bad_Opcode },
4509     { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4510   },
4511
4512   /* PREFIX_0F3A0D */
4513   {
4514     { Bad_Opcode },
4515     { Bad_Opcode },
4516     { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4517   },
4518
4519   /* PREFIX_0F3A0E */
4520   {
4521     { Bad_Opcode },
4522     { Bad_Opcode },
4523     { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4524   },
4525
4526   /* PREFIX_0F3A14 */
4527   {
4528     { Bad_Opcode },
4529     { Bad_Opcode },
4530     { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4531   },
4532
4533   /* PREFIX_0F3A15 */
4534   {
4535     { Bad_Opcode },
4536     { Bad_Opcode },
4537     { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4538   },
4539
4540   /* PREFIX_0F3A16 */
4541   {
4542     { Bad_Opcode },
4543     { Bad_Opcode },
4544     { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4545   },
4546
4547   /* PREFIX_0F3A17 */
4548   {
4549     { Bad_Opcode },
4550     { Bad_Opcode },
4551     { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4552   },
4553
4554   /* PREFIX_0F3A20 */
4555   {
4556     { Bad_Opcode },
4557     { Bad_Opcode },
4558     { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4559   },
4560
4561   /* PREFIX_0F3A21 */
4562   {
4563     { Bad_Opcode },
4564     { Bad_Opcode },
4565     { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4566   },
4567
4568   /* PREFIX_0F3A22 */
4569   {
4570     { Bad_Opcode },
4571     { Bad_Opcode },
4572     { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4573   },
4574
4575   /* PREFIX_0F3A40 */
4576   {
4577     { Bad_Opcode },
4578     { Bad_Opcode },
4579     { "dpps",   { XM, EXx, Ib }, PREFIX_OPCODE },
4580   },
4581
4582   /* PREFIX_0F3A41 */
4583   {
4584     { Bad_Opcode },
4585     { Bad_Opcode },
4586     { "dppd",   { XM, EXx, Ib }, PREFIX_OPCODE },
4587   },
4588
4589   /* PREFIX_0F3A42 */
4590   {
4591     { Bad_Opcode },
4592     { Bad_Opcode },
4593     { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4594   },
4595
4596   /* PREFIX_0F3A44 */
4597   {
4598     { Bad_Opcode },
4599     { Bad_Opcode },
4600     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4601   },
4602
4603   /* PREFIX_0F3A60 */
4604   {
4605     { Bad_Opcode },
4606     { Bad_Opcode },
4607     { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4608   },
4609
4610   /* PREFIX_0F3A61 */
4611   {
4612     { Bad_Opcode },
4613     { Bad_Opcode },
4614     { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4615   },
4616
4617   /* PREFIX_0F3A62 */
4618   {
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4622   },
4623
4624   /* PREFIX_0F3A63 */
4625   {
4626     { Bad_Opcode },
4627     { Bad_Opcode },
4628     { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4629   },
4630
4631   /* PREFIX_0F3ACC */
4632   {
4633     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4634   },
4635
4636   /* PREFIX_0F3ACE */
4637   {
4638     { Bad_Opcode },
4639     { Bad_Opcode },
4640     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4641   },
4642
4643   /* PREFIX_0F3ACF */
4644   {
4645     { Bad_Opcode },
4646     { Bad_Opcode },
4647     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4648   },
4649
4650   /* PREFIX_0F3ADF */
4651   {
4652     { Bad_Opcode },
4653     { Bad_Opcode },
4654     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4655   },
4656
4657   /* PREFIX_VEX_0F10 */
4658   {
4659     { "vmovups",        { XM, EXx }, 0 },
4660     { "vmovss",         { XMVexScalar, VexScalar, EXdScalar }, 0 },
4661     { "vmovupd",        { XM, EXx }, 0 },
4662     { "vmovsd",         { XMVexScalar, VexScalar, EXqScalar }, 0 },
4663   },
4664
4665   /* PREFIX_VEX_0F11 */
4666   {
4667     { "vmovups",        { EXxS, XM }, 0 },
4668     { "vmovss",         { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4669     { "vmovupd",        { EXxS, XM }, 0 },
4670     { "vmovsd",         { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4671   },
4672
4673   /* PREFIX_VEX_0F12 */
4674   {
4675     { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4676     { "vmovsldup",      { XM, EXx }, 0 },
4677     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4678     { "vmovddup",       { XM, EXymmq }, 0 },
4679   },
4680
4681   /* PREFIX_VEX_0F16 */
4682   {
4683     { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4684     { "vmovshdup",      { XM, EXx }, 0 },
4685     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4686   },
4687
4688   /* PREFIX_VEX_0F2A */
4689   {
4690     { Bad_Opcode },
4691     { "vcvtsi2ss%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4692     { Bad_Opcode },
4693     { "vcvtsi2sd%LQ",   { XMScalar, VexScalar, Edq }, 0 },
4694   },
4695
4696   /* PREFIX_VEX_0F2C */
4697   {
4698     { Bad_Opcode },
4699     { "vcvttss2si",     { Gdq, EXdScalar }, 0 },
4700     { Bad_Opcode },
4701     { "vcvttsd2si",     { Gdq, EXqScalar }, 0 },
4702   },
4703
4704   /* PREFIX_VEX_0F2D */
4705   {
4706     { Bad_Opcode },
4707     { "vcvtss2si",      { Gdq, EXdScalar }, 0 },
4708     { Bad_Opcode },
4709     { "vcvtsd2si",      { Gdq, EXqScalar }, 0 },
4710   },
4711
4712   /* PREFIX_VEX_0F2E */
4713   {
4714     { "vucomiss",       { XMScalar, EXdScalar }, 0 },
4715     { Bad_Opcode },
4716     { "vucomisd",       { XMScalar, EXqScalar }, 0 },
4717   },
4718
4719   /* PREFIX_VEX_0F2F */
4720   {
4721     { "vcomiss",        { XMScalar, EXdScalar }, 0 },
4722     { Bad_Opcode },
4723     { "vcomisd",        { XMScalar, EXqScalar }, 0 },
4724   },
4725
4726   /* PREFIX_VEX_0F41 */
4727   {
4728     { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4729     { Bad_Opcode },
4730     { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4731   },
4732
4733   /* PREFIX_VEX_0F42 */
4734   {
4735     { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4736     { Bad_Opcode },
4737     { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4738   },
4739
4740   /* PREFIX_VEX_0F44 */
4741   {
4742     { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4743     { Bad_Opcode },
4744     { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4745   },
4746
4747   /* PREFIX_VEX_0F45 */
4748   {
4749     { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4750     { Bad_Opcode },
4751     { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4752   },
4753
4754   /* PREFIX_VEX_0F46 */
4755   {
4756     { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4757     { Bad_Opcode },
4758     { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4759   },
4760
4761   /* PREFIX_VEX_0F47 */
4762   {
4763     { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4764     { Bad_Opcode },
4765     { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4766   },
4767
4768   /* PREFIX_VEX_0F4A */
4769   {
4770     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4771     { Bad_Opcode },
4772     { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4773   },
4774
4775   /* PREFIX_VEX_0F4B */
4776   {
4777     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4778     { Bad_Opcode },
4779     { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4780   },
4781
4782   /* PREFIX_VEX_0F51 */
4783   {
4784     { "vsqrtps",        { XM, EXx }, 0 },
4785     { "vsqrtss",        { XMScalar, VexScalar, EXdScalar }, 0 },
4786     { "vsqrtpd",        { XM, EXx }, 0 },
4787     { "vsqrtsd",        { XMScalar, VexScalar, EXqScalar }, 0 },
4788   },
4789
4790   /* PREFIX_VEX_0F52 */
4791   {
4792     { "vrsqrtps",       { XM, EXx }, 0 },
4793     { "vrsqrtss",       { XMScalar, VexScalar, EXdScalar }, 0 },
4794   },
4795
4796   /* PREFIX_VEX_0F53 */
4797   {
4798     { "vrcpps",         { XM, EXx }, 0 },
4799     { "vrcpss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4800   },
4801
4802   /* PREFIX_VEX_0F58 */
4803   {
4804     { "vaddps",         { XM, Vex, EXx }, 0 },
4805     { "vaddss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4806     { "vaddpd",         { XM, Vex, EXx }, 0 },
4807     { "vaddsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4808   },
4809
4810   /* PREFIX_VEX_0F59 */
4811   {
4812     { "vmulps",         { XM, Vex, EXx }, 0 },
4813     { "vmulss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4814     { "vmulpd",         { XM, Vex, EXx }, 0 },
4815     { "vmulsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4816   },
4817
4818   /* PREFIX_VEX_0F5A */
4819   {
4820     { "vcvtps2pd",      { XM, EXxmmq }, 0 },
4821     { "vcvtss2sd",      { XMScalar, VexScalar, EXdScalar }, 0 },
4822     { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4823     { "vcvtsd2ss",      { XMScalar, VexScalar, EXqScalar }, 0 },
4824   },
4825
4826   /* PREFIX_VEX_0F5B */
4827   {
4828     { "vcvtdq2ps",      { XM, EXx }, 0 },
4829     { "vcvttps2dq",     { XM, EXx }, 0 },
4830     { "vcvtps2dq",      { XM, EXx }, 0 },
4831   },
4832
4833   /* PREFIX_VEX_0F5C */
4834   {
4835     { "vsubps",         { XM, Vex, EXx }, 0 },
4836     { "vsubss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4837     { "vsubpd",         { XM, Vex, EXx }, 0 },
4838     { "vsubsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4839   },
4840
4841   /* PREFIX_VEX_0F5D */
4842   {
4843     { "vminps",         { XM, Vex, EXx }, 0 },
4844     { "vminss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4845     { "vminpd",         { XM, Vex, EXx }, 0 },
4846     { "vminsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4847   },
4848
4849   /* PREFIX_VEX_0F5E */
4850   {
4851     { "vdivps",         { XM, Vex, EXx }, 0 },
4852     { "vdivss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4853     { "vdivpd",         { XM, Vex, EXx }, 0 },
4854     { "vdivsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4855   },
4856
4857   /* PREFIX_VEX_0F5F */
4858   {
4859     { "vmaxps",         { XM, Vex, EXx }, 0 },
4860     { "vmaxss",         { XMScalar, VexScalar, EXdScalar }, 0 },
4861     { "vmaxpd",         { XM, Vex, EXx }, 0 },
4862     { "vmaxsd",         { XMScalar, VexScalar, EXqScalar }, 0 },
4863   },
4864
4865   /* PREFIX_VEX_0F60 */
4866   {
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { "vpunpcklbw",     { XM, Vex, EXx }, 0 },
4870   },
4871
4872   /* PREFIX_VEX_0F61 */
4873   {
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { "vpunpcklwd",     { XM, Vex, EXx }, 0 },
4877   },
4878
4879   /* PREFIX_VEX_0F62 */
4880   {
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "vpunpckldq",     { XM, Vex, EXx }, 0 },
4884   },
4885
4886   /* PREFIX_VEX_0F63 */
4887   {
4888     { Bad_Opcode },
4889     { Bad_Opcode },
4890     { "vpacksswb",      { XM, Vex, EXx }, 0 },
4891   },
4892
4893   /* PREFIX_VEX_0F64 */
4894   {
4895     { Bad_Opcode },
4896     { Bad_Opcode },
4897     { "vpcmpgtb",       { XM, Vex, EXx }, 0 },
4898   },
4899
4900   /* PREFIX_VEX_0F65 */
4901   {
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { "vpcmpgtw",       { XM, Vex, EXx }, 0 },
4905   },
4906
4907   /* PREFIX_VEX_0F66 */
4908   {
4909     { Bad_Opcode },
4910     { Bad_Opcode },
4911     { "vpcmpgtd",       { XM, Vex, EXx }, 0 },
4912   },
4913
4914   /* PREFIX_VEX_0F67 */
4915   {
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "vpackuswb",      { XM, Vex, EXx }, 0 },
4919   },
4920
4921   /* PREFIX_VEX_0F68 */
4922   {
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { "vpunpckhbw",     { XM, Vex, EXx }, 0 },
4926   },
4927
4928   /* PREFIX_VEX_0F69 */
4929   {
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { "vpunpckhwd",     { XM, Vex, EXx }, 0 },
4933   },
4934
4935   /* PREFIX_VEX_0F6A */
4936   {
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { "vpunpckhdq",     { XM, Vex, EXx }, 0 },
4940   },
4941
4942   /* PREFIX_VEX_0F6B */
4943   {
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { "vpackssdw",      { XM, Vex, EXx }, 0 },
4947   },
4948
4949   /* PREFIX_VEX_0F6C */
4950   {
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { "vpunpcklqdq",    { XM, Vex, EXx }, 0 },
4954   },
4955
4956   /* PREFIX_VEX_0F6D */
4957   {
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { "vpunpckhqdq",    { XM, Vex, EXx }, 0 },
4961   },
4962
4963   /* PREFIX_VEX_0F6E */
4964   {
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4968   },
4969
4970   /* PREFIX_VEX_0F6F */
4971   {
4972     { Bad_Opcode },
4973     { "vmovdqu",        { XM, EXx }, 0 },
4974     { "vmovdqa",        { XM, EXx }, 0 },
4975   },
4976
4977   /* PREFIX_VEX_0F70 */
4978   {
4979     { Bad_Opcode },
4980     { "vpshufhw",       { XM, EXx, Ib }, 0 },
4981     { "vpshufd",        { XM, EXx, Ib }, 0 },
4982     { "vpshuflw",       { XM, EXx, Ib }, 0 },
4983   },
4984
4985   /* PREFIX_VEX_0F71_REG_2 */
4986   {
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { "vpsrlw",         { Vex, XS, Ib }, 0 },
4990   },
4991
4992   /* PREFIX_VEX_0F71_REG_4 */
4993   {
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { "vpsraw",         { Vex, XS, Ib }, 0 },
4997   },
4998
4999   /* PREFIX_VEX_0F71_REG_6 */
5000   {
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { "vpsllw",         { Vex, XS, Ib }, 0 },
5004   },
5005
5006   /* PREFIX_VEX_0F72_REG_2 */
5007   {
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { "vpsrld",         { Vex, XS, Ib }, 0 },
5011   },
5012
5013   /* PREFIX_VEX_0F72_REG_4 */
5014   {
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { "vpsrad",         { Vex, XS, Ib }, 0 },
5018   },
5019
5020   /* PREFIX_VEX_0F72_REG_6 */
5021   {
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { "vpslld",         { Vex, XS, Ib }, 0 },
5025   },
5026
5027   /* PREFIX_VEX_0F73_REG_2 */
5028   {
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { "vpsrlq",         { Vex, XS, Ib }, 0 },
5032   },
5033
5034   /* PREFIX_VEX_0F73_REG_3 */
5035   {
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { "vpsrldq",        { Vex, XS, Ib }, 0 },
5039   },
5040
5041   /* PREFIX_VEX_0F73_REG_6 */
5042   {
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { "vpsllq",         { Vex, XS, Ib }, 0 },
5046   },
5047
5048   /* PREFIX_VEX_0F73_REG_7 */
5049   {
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { "vpslldq",        { Vex, XS, Ib }, 0 },
5053   },
5054
5055   /* PREFIX_VEX_0F74 */
5056   {
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { "vpcmpeqb",       { XM, Vex, EXx }, 0 },
5060   },
5061
5062   /* PREFIX_VEX_0F75 */
5063   {
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { "vpcmpeqw",       { XM, Vex, EXx }, 0 },
5067   },
5068
5069   /* PREFIX_VEX_0F76 */
5070   {
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { "vpcmpeqd",       { XM, Vex, EXx }, 0 },
5074   },
5075
5076   /* PREFIX_VEX_0F77 */
5077   {
5078     { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5079   },
5080
5081   /* PREFIX_VEX_0F7C */
5082   {
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { "vhaddpd",        { XM, Vex, EXx }, 0 },
5086     { "vhaddps",        { XM, Vex, EXx }, 0 },
5087   },
5088
5089   /* PREFIX_VEX_0F7D */
5090   {
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { "vhsubpd",        { XM, Vex, EXx }, 0 },
5094     { "vhsubps",        { XM, Vex, EXx }, 0 },
5095   },
5096
5097   /* PREFIX_VEX_0F7E */
5098   {
5099     { Bad_Opcode },
5100     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5101     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5102   },
5103
5104   /* PREFIX_VEX_0F7F */
5105   {
5106     { Bad_Opcode },
5107     { "vmovdqu",        { EXxS, XM }, 0 },
5108     { "vmovdqa",        { EXxS, XM }, 0 },
5109   },
5110
5111   /* PREFIX_VEX_0F90 */
5112   {
5113     { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5114     { Bad_Opcode },
5115     { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5116   },
5117
5118   /* PREFIX_VEX_0F91 */
5119   {
5120     { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5121     { Bad_Opcode },
5122     { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5123   },
5124
5125   /* PREFIX_VEX_0F92 */
5126   {
5127     { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5128     { Bad_Opcode },
5129     { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5130     { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5131   },
5132
5133   /* PREFIX_VEX_0F93 */
5134   {
5135     { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5136     { Bad_Opcode },
5137     { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5138     { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5139   },
5140
5141   /* PREFIX_VEX_0F98 */
5142   {
5143     { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5144     { Bad_Opcode },
5145     { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5146   },
5147
5148   /* PREFIX_VEX_0F99 */
5149   {
5150     { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5151     { Bad_Opcode },
5152     { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5153   },
5154
5155   /* PREFIX_VEX_0FC2 */
5156   {
5157     { "vcmpps",         { XM, Vex, EXx, VCMP }, 0 },
5158     { "vcmpss",         { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5159     { "vcmppd",         { XM, Vex, EXx, VCMP }, 0 },
5160     { "vcmpsd",         { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5161   },
5162
5163   /* PREFIX_VEX_0FC4 */
5164   {
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5168   },
5169
5170   /* PREFIX_VEX_0FC5 */
5171   {
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5175   },
5176
5177   /* PREFIX_VEX_0FD0 */
5178   {
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { "vaddsubpd",      { XM, Vex, EXx }, 0 },
5182     { "vaddsubps",      { XM, Vex, EXx }, 0 },
5183   },
5184
5185   /* PREFIX_VEX_0FD1 */
5186   {
5187     { Bad_Opcode },
5188     { Bad_Opcode },
5189     { "vpsrlw",         { XM, Vex, EXxmm }, 0 },
5190   },
5191
5192   /* PREFIX_VEX_0FD2 */
5193   {
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { "vpsrld",         { XM, Vex, EXxmm }, 0 },
5197   },
5198
5199   /* PREFIX_VEX_0FD3 */
5200   {
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { "vpsrlq",         { XM, Vex, EXxmm }, 0 },
5204   },
5205
5206   /* PREFIX_VEX_0FD4 */
5207   {
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { "vpaddq",         { XM, Vex, EXx }, 0 },
5211   },
5212
5213   /* PREFIX_VEX_0FD5 */
5214   {
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { "vpmullw",        { XM, Vex, EXx }, 0 },
5218   },
5219
5220   /* PREFIX_VEX_0FD6 */
5221   {
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5225   },
5226
5227   /* PREFIX_VEX_0FD7 */
5228   {
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5232   },
5233
5234   /* PREFIX_VEX_0FD8 */
5235   {
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { "vpsubusb",       { XM, Vex, EXx }, 0 },
5239   },
5240
5241   /* PREFIX_VEX_0FD9 */
5242   {
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { "vpsubusw",       { XM, Vex, EXx }, 0 },
5246   },
5247
5248   /* PREFIX_VEX_0FDA */
5249   {
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { "vpminub",        { XM, Vex, EXx }, 0 },
5253   },
5254
5255   /* PREFIX_VEX_0FDB */
5256   {
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { "vpand",          { XM, Vex, EXx }, 0 },
5260   },
5261
5262   /* PREFIX_VEX_0FDC */
5263   {
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { "vpaddusb",       { XM, Vex, EXx }, 0 },
5267   },
5268
5269   /* PREFIX_VEX_0FDD */
5270   {
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { "vpaddusw",       { XM, Vex, EXx }, 0 },
5274   },
5275
5276   /* PREFIX_VEX_0FDE */
5277   {
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { "vpmaxub",        { XM, Vex, EXx }, 0 },
5281   },
5282
5283   /* PREFIX_VEX_0FDF */
5284   {
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { "vpandn",         { XM, Vex, EXx }, 0 },
5288   },
5289
5290   /* PREFIX_VEX_0FE0 */
5291   {
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { "vpavgb",         { XM, Vex, EXx }, 0 },
5295   },
5296
5297   /* PREFIX_VEX_0FE1 */
5298   {
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { "vpsraw",         { XM, Vex, EXxmm }, 0 },
5302   },
5303
5304   /* PREFIX_VEX_0FE2 */
5305   {
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { "vpsrad",         { XM, Vex, EXxmm }, 0 },
5309   },
5310
5311   /* PREFIX_VEX_0FE3 */
5312   {
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { "vpavgw",         { XM, Vex, EXx }, 0 },
5316   },
5317
5318   /* PREFIX_VEX_0FE4 */
5319   {
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { "vpmulhuw",       { XM, Vex, EXx }, 0 },
5323   },
5324
5325   /* PREFIX_VEX_0FE5 */
5326   {
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { "vpmulhw",        { XM, Vex, EXx }, 0 },
5330   },
5331
5332   /* PREFIX_VEX_0FE6 */
5333   {
5334     { Bad_Opcode },
5335     { "vcvtdq2pd",      { XM, EXxmmq }, 0 },
5336     { "vcvttpd2dq%XY",  { XMM, EXx }, 0 },
5337     { "vcvtpd2dq%XY",   { XMM, EXx }, 0 },
5338   },
5339
5340   /* PREFIX_VEX_0FE7 */
5341   {
5342     { Bad_Opcode },
5343     { Bad_Opcode },
5344     { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5345   },
5346
5347   /* PREFIX_VEX_0FE8 */
5348   {
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { "vpsubsb",        { XM, Vex, EXx }, 0 },
5352   },
5353
5354   /* PREFIX_VEX_0FE9 */
5355   {
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { "vpsubsw",        { XM, Vex, EXx }, 0 },
5359   },
5360
5361   /* PREFIX_VEX_0FEA */
5362   {
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { "vpminsw",        { XM, Vex, EXx }, 0 },
5366   },
5367
5368   /* PREFIX_VEX_0FEB */
5369   {
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpor",           { XM, Vex, EXx }, 0 },
5373   },
5374
5375   /* PREFIX_VEX_0FEC */
5376   {
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { "vpaddsb",        { XM, Vex, EXx }, 0 },
5380   },
5381
5382   /* PREFIX_VEX_0FED */
5383   {
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { "vpaddsw",        { XM, Vex, EXx }, 0 },
5387   },
5388
5389   /* PREFIX_VEX_0FEE */
5390   {
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { "vpmaxsw",        { XM, Vex, EXx }, 0 },
5394   },
5395
5396   /* PREFIX_VEX_0FEF */
5397   {
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { "vpxor",          { XM, Vex, EXx }, 0 },
5401   },
5402
5403   /* PREFIX_VEX_0FF0 */
5404   {
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5409   },
5410
5411   /* PREFIX_VEX_0FF1 */
5412   {
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { "vpsllw",         { XM, Vex, EXxmm }, 0 },
5416   },
5417
5418   /* PREFIX_VEX_0FF2 */
5419   {
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { "vpslld",         { XM, Vex, EXxmm }, 0 },
5423   },
5424
5425   /* PREFIX_VEX_0FF3 */
5426   {
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { "vpsllq",         { XM, Vex, EXxmm }, 0 },
5430   },
5431
5432   /* PREFIX_VEX_0FF4 */
5433   {
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { "vpmuludq",       { XM, Vex, EXx }, 0 },
5437   },
5438
5439   /* PREFIX_VEX_0FF5 */
5440   {
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { "vpmaddwd",       { XM, Vex, EXx }, 0 },
5444   },
5445
5446   /* PREFIX_VEX_0FF6 */
5447   {
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { "vpsadbw",        { XM, Vex, EXx }, 0 },
5451   },
5452
5453   /* PREFIX_VEX_0FF7 */
5454   {
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5458   },
5459
5460   /* PREFIX_VEX_0FF8 */
5461   {
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { "vpsubb",         { XM, Vex, EXx }, 0 },
5465   },
5466
5467   /* PREFIX_VEX_0FF9 */
5468   {
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { "vpsubw",         { XM, Vex, EXx }, 0 },
5472   },
5473
5474   /* PREFIX_VEX_0FFA */
5475   {
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { "vpsubd",         { XM, Vex, EXx }, 0 },
5479   },
5480
5481   /* PREFIX_VEX_0FFB */
5482   {
5483     { Bad_Opcode },
5484     { Bad_Opcode },
5485     { "vpsubq",         { XM, Vex, EXx }, 0 },
5486   },
5487
5488   /* PREFIX_VEX_0FFC */
5489   {
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { "vpaddb",         { XM, Vex, EXx }, 0 },
5493   },
5494
5495   /* PREFIX_VEX_0FFD */
5496   {
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { "vpaddw",         { XM, Vex, EXx }, 0 },
5500   },
5501
5502   /* PREFIX_VEX_0FFE */
5503   {
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { "vpaddd",         { XM, Vex, EXx }, 0 },
5507   },
5508
5509   /* PREFIX_VEX_0F3800 */
5510   {
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { "vpshufb",        { XM, Vex, EXx }, 0 },
5514   },
5515
5516   /* PREFIX_VEX_0F3801 */
5517   {
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { "vphaddw",        { XM, Vex, EXx }, 0 },
5521   },
5522
5523   /* PREFIX_VEX_0F3802 */
5524   {
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { "vphaddd",        { XM, Vex, EXx }, 0 },
5528   },
5529
5530   /* PREFIX_VEX_0F3803 */
5531   {
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { "vphaddsw",       { XM, Vex, EXx }, 0 },
5535   },
5536
5537   /* PREFIX_VEX_0F3804 */
5538   {
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { "vpmaddubsw",     { XM, Vex, EXx }, 0 },
5542   },
5543
5544   /* PREFIX_VEX_0F3805 */
5545   {
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { "vphsubw",        { XM, Vex, EXx }, 0 },
5549   },
5550
5551   /* PREFIX_VEX_0F3806 */
5552   {
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { "vphsubd",        { XM, Vex, EXx }, 0 },
5556   },
5557
5558   /* PREFIX_VEX_0F3807 */
5559   {
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { "vphsubsw",       { XM, Vex, EXx }, 0 },
5563   },
5564
5565   /* PREFIX_VEX_0F3808 */
5566   {
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { "vpsignb",        { XM, Vex, EXx }, 0 },
5570   },
5571
5572   /* PREFIX_VEX_0F3809 */
5573   {
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { "vpsignw",        { XM, Vex, EXx }, 0 },
5577   },
5578
5579   /* PREFIX_VEX_0F380A */
5580   {
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { "vpsignd",        { XM, Vex, EXx }, 0 },
5584   },
5585
5586   /* PREFIX_VEX_0F380B */
5587   {
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { "vpmulhrsw",      { XM, Vex, EXx }, 0 },
5591   },
5592
5593   /* PREFIX_VEX_0F380C */
5594   {
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5598   },
5599
5600   /* PREFIX_VEX_0F380D */
5601   {
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5605   },
5606
5607   /* PREFIX_VEX_0F380E */
5608   {
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5612   },
5613
5614   /* PREFIX_VEX_0F380F */
5615   {
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5619   },
5620
5621   /* PREFIX_VEX_0F3813 */
5622   {
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { "vcvtph2ps", { XM, EXxmmq }, 0 },
5626   },
5627
5628   /* PREFIX_VEX_0F3816 */
5629   {
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5633   },
5634
5635   /* PREFIX_VEX_0F3817 */
5636   {
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { "vptest",         { XM, EXx }, 0 },
5640   },
5641
5642   /* PREFIX_VEX_0F3818 */
5643   {
5644     { Bad_Opcode },
5645     { Bad_Opcode },
5646     { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5647   },
5648
5649   /* PREFIX_VEX_0F3819 */
5650   {
5651     { Bad_Opcode },
5652     { Bad_Opcode },
5653     { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5654   },
5655
5656   /* PREFIX_VEX_0F381A */
5657   {
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5661   },
5662
5663   /* PREFIX_VEX_0F381C */
5664   {
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { "vpabsb",         { XM, EXx }, 0 },
5668   },
5669
5670   /* PREFIX_VEX_0F381D */
5671   {
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { "vpabsw",         { XM, EXx }, 0 },
5675   },
5676
5677   /* PREFIX_VEX_0F381E */
5678   {
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { "vpabsd",         { XM, EXx }, 0 },
5682   },
5683
5684   /* PREFIX_VEX_0F3820 */
5685   {
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { "vpmovsxbw",      { XM, EXxmmq }, 0 },
5689   },
5690
5691   /* PREFIX_VEX_0F3821 */
5692   {
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { "vpmovsxbd",      { XM, EXxmmqd }, 0 },
5696   },
5697
5698   /* PREFIX_VEX_0F3822 */
5699   {
5700     { Bad_Opcode },
5701     { Bad_Opcode },
5702     { "vpmovsxbq",      { XM, EXxmmdw }, 0 },
5703   },
5704
5705   /* PREFIX_VEX_0F3823 */
5706   {
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { "vpmovsxwd",      { XM, EXxmmq }, 0 },
5710   },
5711
5712   /* PREFIX_VEX_0F3824 */
5713   {
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { "vpmovsxwq",      { XM, EXxmmqd }, 0 },
5717   },
5718
5719   /* PREFIX_VEX_0F3825 */
5720   {
5721     { Bad_Opcode },
5722     { Bad_Opcode },
5723     { "vpmovsxdq",      { XM, EXxmmq }, 0 },
5724   },
5725
5726   /* PREFIX_VEX_0F3828 */
5727   {
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { "vpmuldq",        { XM, Vex, EXx }, 0 },
5731   },
5732
5733   /* PREFIX_VEX_0F3829 */
5734   {
5735     { Bad_Opcode },
5736     { Bad_Opcode },
5737     { "vpcmpeqq",       { XM, Vex, EXx }, 0 },
5738   },
5739
5740   /* PREFIX_VEX_0F382A */
5741   {
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5745   },
5746
5747   /* PREFIX_VEX_0F382B */
5748   {
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { "vpackusdw",      { XM, Vex, EXx }, 0 },
5752   },
5753
5754   /* PREFIX_VEX_0F382C */
5755   {
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758      { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5759   },
5760
5761   /* PREFIX_VEX_0F382D */
5762   {
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765      { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5766   },
5767
5768   /* PREFIX_VEX_0F382E */
5769   {
5770     { Bad_Opcode },
5771     { Bad_Opcode },
5772      { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5773   },
5774
5775   /* PREFIX_VEX_0F382F */
5776   {
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779      { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5780   },
5781
5782   /* PREFIX_VEX_0F3830 */
5783   {
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { "vpmovzxbw",      { XM, EXxmmq }, 0 },
5787   },
5788
5789   /* PREFIX_VEX_0F3831 */
5790   {
5791     { Bad_Opcode },
5792     { Bad_Opcode },
5793     { "vpmovzxbd",      { XM, EXxmmqd }, 0 },
5794   },
5795
5796   /* PREFIX_VEX_0F3832 */
5797   {
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { "vpmovzxbq",      { XM, EXxmmdw }, 0 },
5801   },
5802
5803   /* PREFIX_VEX_0F3833 */
5804   {
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { "vpmovzxwd",      { XM, EXxmmq }, 0 },
5808   },
5809
5810   /* PREFIX_VEX_0F3834 */
5811   {
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { "vpmovzxwq",      { XM, EXxmmqd }, 0 },
5815   },
5816
5817   /* PREFIX_VEX_0F3835 */
5818   {
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { "vpmovzxdq",      { XM, EXxmmq }, 0 },
5822   },
5823
5824   /* PREFIX_VEX_0F3836 */
5825   {
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5829   },
5830
5831   /* PREFIX_VEX_0F3837 */
5832   {
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { "vpcmpgtq",       { XM, Vex, EXx }, 0 },
5836   },
5837
5838   /* PREFIX_VEX_0F3838 */
5839   {
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { "vpminsb",        { XM, Vex, EXx }, 0 },
5843   },
5844
5845   /* PREFIX_VEX_0F3839 */
5846   {
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { "vpminsd",        { XM, Vex, EXx }, 0 },
5850   },
5851
5852   /* PREFIX_VEX_0F383A */
5853   {
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { "vpminuw",        { XM, Vex, EXx }, 0 },
5857   },
5858
5859   /* PREFIX_VEX_0F383B */
5860   {
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { "vpminud",        { XM, Vex, EXx }, 0 },
5864   },
5865
5866   /* PREFIX_VEX_0F383C */
5867   {
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { "vpmaxsb",        { XM, Vex, EXx }, 0 },
5871   },
5872
5873   /* PREFIX_VEX_0F383D */
5874   {
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { "vpmaxsd",        { XM, Vex, EXx }, 0 },
5878   },
5879
5880   /* PREFIX_VEX_0F383E */
5881   {
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { "vpmaxuw",        { XM, Vex, EXx }, 0 },
5885   },
5886
5887   /* PREFIX_VEX_0F383F */
5888   {
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { "vpmaxud",        { XM, Vex, EXx }, 0 },
5892   },
5893
5894   /* PREFIX_VEX_0F3840 */
5895   {
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { "vpmulld",        { XM, Vex, EXx }, 0 },
5899   },
5900
5901   /* PREFIX_VEX_0F3841 */
5902   {
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5906   },
5907
5908   /* PREFIX_VEX_0F3845 */
5909   {
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5913   },
5914
5915   /* PREFIX_VEX_0F3846 */
5916   {
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5920   },
5921
5922   /* PREFIX_VEX_0F3847 */
5923   {
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5927   },
5928
5929   /* PREFIX_VEX_0F3858 */
5930   {
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5934   },
5935
5936   /* PREFIX_VEX_0F3859 */
5937   {
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5941   },
5942
5943   /* PREFIX_VEX_0F385A */
5944   {
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5948   },
5949
5950   /* PREFIX_VEX_0F3878 */
5951   {
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5955   },
5956
5957   /* PREFIX_VEX_0F3879 */
5958   {
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5962   },
5963
5964   /* PREFIX_VEX_0F388C */
5965   {
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5969   },
5970
5971   /* PREFIX_VEX_0F388E */
5972   {
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5976   },
5977
5978   /* PREFIX_VEX_0F3890 */
5979   {
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5983   },
5984
5985   /* PREFIX_VEX_0F3891 */
5986   {
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
5990   },
5991
5992   /* PREFIX_VEX_0F3892 */
5993   {
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
5997   },
5998
5999   /* PREFIX_VEX_0F3893 */
6000   {
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6004   },
6005
6006   /* PREFIX_VEX_0F3896 */
6007   {
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6011   },
6012
6013   /* PREFIX_VEX_0F3897 */
6014   {
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6018   },
6019
6020   /* PREFIX_VEX_0F3898 */
6021   {
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6025   },
6026
6027   /* PREFIX_VEX_0F3899 */
6028   {
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6032   },
6033
6034   /* PREFIX_VEX_0F389A */
6035   {
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6039   },
6040
6041   /* PREFIX_VEX_0F389B */
6042   {
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6046   },
6047
6048   /* PREFIX_VEX_0F389C */
6049   {
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6053   },
6054
6055   /* PREFIX_VEX_0F389D */
6056   {
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6060   },
6061
6062   /* PREFIX_VEX_0F389E */
6063   {
6064     { Bad_Opcode },
6065     { Bad_Opcode },
6066     { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6067   },
6068
6069   /* PREFIX_VEX_0F389F */
6070   {
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6074   },
6075
6076   /* PREFIX_VEX_0F38A6 */
6077   {
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6081     { Bad_Opcode },
6082   },
6083
6084   /* PREFIX_VEX_0F38A7 */
6085   {
6086     { Bad_Opcode },
6087     { Bad_Opcode },
6088     { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6089   },
6090
6091   /* PREFIX_VEX_0F38A8 */
6092   {
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6096   },
6097
6098   /* PREFIX_VEX_0F38A9 */
6099   {
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6103   },
6104
6105   /* PREFIX_VEX_0F38AA */
6106   {
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6110   },
6111
6112   /* PREFIX_VEX_0F38AB */
6113   {
6114     { Bad_Opcode },
6115     { Bad_Opcode },
6116     { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6117   },
6118
6119   /* PREFIX_VEX_0F38AC */
6120   {
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6124   },
6125
6126   /* PREFIX_VEX_0F38AD */
6127   {
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6131   },
6132
6133   /* PREFIX_VEX_0F38AE */
6134   {
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6138   },
6139
6140   /* PREFIX_VEX_0F38AF */
6141   {
6142     { Bad_Opcode },
6143     { Bad_Opcode },
6144     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6145   },
6146
6147   /* PREFIX_VEX_0F38B6 */
6148   {
6149     { Bad_Opcode },
6150     { Bad_Opcode },
6151     { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6152   },
6153
6154   /* PREFIX_VEX_0F38B7 */
6155   {
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6159   },
6160
6161   /* PREFIX_VEX_0F38B8 */
6162   {
6163     { Bad_Opcode },
6164     { Bad_Opcode },
6165     { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6166   },
6167
6168   /* PREFIX_VEX_0F38B9 */
6169   {
6170     { Bad_Opcode },
6171     { Bad_Opcode },
6172     { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6173   },
6174
6175   /* PREFIX_VEX_0F38BA */
6176   {
6177     { Bad_Opcode },
6178     { Bad_Opcode },
6179     { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6180   },
6181
6182   /* PREFIX_VEX_0F38BB */
6183   {
6184     { Bad_Opcode },
6185     { Bad_Opcode },
6186     { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6187   },
6188
6189   /* PREFIX_VEX_0F38BC */
6190   {
6191     { Bad_Opcode },
6192     { Bad_Opcode },
6193     { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6194   },
6195
6196   /* PREFIX_VEX_0F38BD */
6197   {
6198     { Bad_Opcode },
6199     { Bad_Opcode },
6200     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6201   },
6202
6203   /* PREFIX_VEX_0F38BE */
6204   {
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6208   },
6209
6210   /* PREFIX_VEX_0F38BF */
6211   {
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6215   },
6216
6217   /* PREFIX_VEX_0F38CF */
6218   {
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6222   },
6223
6224   /* PREFIX_VEX_0F38DB */
6225   {
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6229   },
6230
6231   /* PREFIX_VEX_0F38DC */
6232   {
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { "vaesenc",        { XM, Vex, EXx }, 0 },
6236   },
6237
6238   /* PREFIX_VEX_0F38DD */
6239   {
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { "vaesenclast",    { XM, Vex, EXx }, 0 },
6243   },
6244
6245   /* PREFIX_VEX_0F38DE */
6246   {
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { "vaesdec",        { XM, Vex, EXx }, 0 },
6250   },
6251
6252   /* PREFIX_VEX_0F38DF */
6253   {
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { "vaesdeclast",    { XM, Vex, EXx }, 0 },
6257   },
6258
6259   /* PREFIX_VEX_0F38F2 */
6260   {
6261     { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6262   },
6263
6264   /* PREFIX_VEX_0F38F3_REG_1 */
6265   {
6266     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6267   },
6268
6269   /* PREFIX_VEX_0F38F3_REG_2 */
6270   {
6271     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6272   },
6273
6274   /* PREFIX_VEX_0F38F3_REG_3 */
6275   {
6276     { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6277   },
6278
6279   /* PREFIX_VEX_0F38F5 */
6280   {
6281     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6282     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6283     { Bad_Opcode },
6284     { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6285   },
6286
6287   /* PREFIX_VEX_0F38F6 */
6288   {
6289     { Bad_Opcode },
6290     { Bad_Opcode },
6291     { Bad_Opcode },
6292     { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6293   },
6294
6295   /* PREFIX_VEX_0F38F7 */
6296   {
6297     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6298     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6299     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6300     { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6301   },
6302
6303   /* PREFIX_VEX_0F3A00 */
6304   {
6305     { Bad_Opcode },
6306     { Bad_Opcode },
6307     { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6308   },
6309
6310   /* PREFIX_VEX_0F3A01 */
6311   {
6312     { Bad_Opcode },
6313     { Bad_Opcode },
6314     { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6315   },
6316
6317   /* PREFIX_VEX_0F3A02 */
6318   {
6319     { Bad_Opcode },
6320     { Bad_Opcode },
6321     { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6322   },
6323
6324   /* PREFIX_VEX_0F3A04 */
6325   {
6326     { Bad_Opcode },
6327     { Bad_Opcode },
6328     { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6329   },
6330
6331   /* PREFIX_VEX_0F3A05 */
6332   {
6333     { Bad_Opcode },
6334     { Bad_Opcode },
6335     { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6336   },
6337
6338   /* PREFIX_VEX_0F3A06 */
6339   {
6340     { Bad_Opcode },
6341     { Bad_Opcode },
6342     { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6343   },
6344
6345   /* PREFIX_VEX_0F3A08 */
6346   {
6347     { Bad_Opcode },
6348     { Bad_Opcode },
6349     { "vroundps",       { XM, EXx, Ib }, 0 },
6350   },
6351
6352   /* PREFIX_VEX_0F3A09 */
6353   {
6354     { Bad_Opcode },
6355     { Bad_Opcode },
6356     { "vroundpd",       { XM, EXx, Ib }, 0 },
6357   },
6358
6359   /* PREFIX_VEX_0F3A0A */
6360   {
6361     { Bad_Opcode },
6362     { Bad_Opcode },
6363     { "vroundss",       { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6364   },
6365
6366   /* PREFIX_VEX_0F3A0B */
6367   {
6368     { Bad_Opcode },
6369     { Bad_Opcode },
6370     { "vroundsd",       { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6371   },
6372
6373   /* PREFIX_VEX_0F3A0C */
6374   {
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { "vblendps",       { XM, Vex, EXx, Ib }, 0 },
6378   },
6379
6380   /* PREFIX_VEX_0F3A0D */
6381   {
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { "vblendpd",       { XM, Vex, EXx, Ib }, 0 },
6385   },
6386
6387   /* PREFIX_VEX_0F3A0E */
6388   {
6389     { Bad_Opcode },
6390     { Bad_Opcode },
6391     { "vpblendw",       { XM, Vex, EXx, Ib }, 0 },
6392   },
6393
6394   /* PREFIX_VEX_0F3A0F */
6395   {
6396     { Bad_Opcode },
6397     { Bad_Opcode },
6398     { "vpalignr",       { XM, Vex, EXx, Ib }, 0 },
6399   },
6400
6401   /* PREFIX_VEX_0F3A14 */
6402   {
6403     { Bad_Opcode },
6404     { Bad_Opcode },
6405     { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6406   },
6407
6408   /* PREFIX_VEX_0F3A15 */
6409   {
6410     { Bad_Opcode },
6411     { Bad_Opcode },
6412     { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6413   },
6414
6415   /* PREFIX_VEX_0F3A16 */
6416   {
6417     { Bad_Opcode },
6418     { Bad_Opcode },
6419     { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6420   },
6421
6422   /* PREFIX_VEX_0F3A17 */
6423   {
6424     { Bad_Opcode },
6425     { Bad_Opcode },
6426     { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6427   },
6428
6429   /* PREFIX_VEX_0F3A18 */
6430   {
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6434   },
6435
6436   /* PREFIX_VEX_0F3A19 */
6437   {
6438     { Bad_Opcode },
6439     { Bad_Opcode },
6440     { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6441   },
6442
6443   /* PREFIX_VEX_0F3A1D */
6444   {
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6448   },
6449
6450   /* PREFIX_VEX_0F3A20 */
6451   {
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6455   },
6456
6457   /* PREFIX_VEX_0F3A21 */
6458   {
6459     { Bad_Opcode },
6460     { Bad_Opcode },
6461     { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6462   },
6463
6464   /* PREFIX_VEX_0F3A22 */
6465   {
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6469   },
6470
6471   /* PREFIX_VEX_0F3A30 */
6472   {
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6476   },
6477
6478   /* PREFIX_VEX_0F3A31 */
6479   {
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6483   },
6484
6485   /* PREFIX_VEX_0F3A32 */
6486   {
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6490   },
6491
6492   /* PREFIX_VEX_0F3A33 */
6493   {
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6497   },
6498
6499   /* PREFIX_VEX_0F3A38 */
6500   {
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6504   },
6505
6506   /* PREFIX_VEX_0F3A39 */
6507   {
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6511   },
6512
6513   /* PREFIX_VEX_0F3A40 */
6514   {
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { "vdpps",          { XM, Vex, EXx, Ib }, 0 },
6518   },
6519
6520   /* PREFIX_VEX_0F3A41 */
6521   {
6522     { Bad_Opcode },
6523     { Bad_Opcode },
6524     { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6525   },
6526
6527   /* PREFIX_VEX_0F3A42 */
6528   {
6529     { Bad_Opcode },
6530     { Bad_Opcode },
6531     { "vmpsadbw",       { XM, Vex, EXx, Ib }, 0 },
6532   },
6533
6534   /* PREFIX_VEX_0F3A44 */
6535   {
6536     { Bad_Opcode },
6537     { Bad_Opcode },
6538     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, 0 },
6539   },
6540
6541   /* PREFIX_VEX_0F3A46 */
6542   {
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6546   },
6547
6548   /* PREFIX_VEX_0F3A48 */
6549   {
6550     { Bad_Opcode },
6551     { Bad_Opcode },
6552     { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6553   },
6554
6555   /* PREFIX_VEX_0F3A49 */
6556   {
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6560   },
6561
6562   /* PREFIX_VEX_0F3A4A */
6563   {
6564     { Bad_Opcode },
6565     { Bad_Opcode },
6566     { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6567   },
6568
6569   /* PREFIX_VEX_0F3A4B */
6570   {
6571     { Bad_Opcode },
6572     { Bad_Opcode },
6573     { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6574   },
6575
6576   /* PREFIX_VEX_0F3A4C */
6577   {
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6581   },
6582
6583   /* PREFIX_VEX_0F3A5C */
6584   {
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6588   },
6589
6590   /* PREFIX_VEX_0F3A5D */
6591   {
6592     { Bad_Opcode },
6593     { Bad_Opcode },
6594     { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6595   },
6596
6597   /* PREFIX_VEX_0F3A5E */
6598   {
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6602   },
6603
6604   /* PREFIX_VEX_0F3A5F */
6605   {
6606     { Bad_Opcode },
6607     { Bad_Opcode },
6608     { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6609   },
6610
6611   /* PREFIX_VEX_0F3A60 */
6612   {
6613     { Bad_Opcode },
6614     { Bad_Opcode },
6615     { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6616     { Bad_Opcode },
6617   },
6618
6619   /* PREFIX_VEX_0F3A61 */
6620   {
6621     { Bad_Opcode },
6622     { Bad_Opcode },
6623     { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6624   },
6625
6626   /* PREFIX_VEX_0F3A62 */
6627   {
6628     { Bad_Opcode },
6629     { Bad_Opcode },
6630     { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6631   },
6632
6633   /* PREFIX_VEX_0F3A63 */
6634   {
6635     { Bad_Opcode },
6636     { Bad_Opcode },
6637     { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6638   },
6639
6640   /* PREFIX_VEX_0F3A68 */
6641   {
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6645   },
6646
6647   /* PREFIX_VEX_0F3A69 */
6648   {
6649     { Bad_Opcode },
6650     { Bad_Opcode },
6651     { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6652   },
6653
6654   /* PREFIX_VEX_0F3A6A */
6655   {
6656     { Bad_Opcode },
6657     { Bad_Opcode },
6658     { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6659   },
6660
6661   /* PREFIX_VEX_0F3A6B */
6662   {
6663     { Bad_Opcode },
6664     { Bad_Opcode },
6665     { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6666   },
6667
6668   /* PREFIX_VEX_0F3A6C */
6669   {
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6673   },
6674
6675   /* PREFIX_VEX_0F3A6D */
6676   {
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6680   },
6681
6682   /* PREFIX_VEX_0F3A6E */
6683   {
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6687   },
6688
6689   /* PREFIX_VEX_0F3A6F */
6690   {
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6694   },
6695
6696   /* PREFIX_VEX_0F3A78 */
6697   {
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6701   },
6702
6703   /* PREFIX_VEX_0F3A79 */
6704   {
6705     { Bad_Opcode },
6706     { Bad_Opcode },
6707     { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6708   },
6709
6710   /* PREFIX_VEX_0F3A7A */
6711   {
6712     { Bad_Opcode },
6713     { Bad_Opcode },
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6715   },
6716
6717   /* PREFIX_VEX_0F3A7B */
6718   {
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6722   },
6723
6724   /* PREFIX_VEX_0F3A7C */
6725   {
6726     { Bad_Opcode },
6727     { Bad_Opcode },
6728     { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6729     { Bad_Opcode },
6730   },
6731
6732   /* PREFIX_VEX_0F3A7D */
6733   {
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6737   },
6738
6739   /* PREFIX_VEX_0F3A7E */
6740   {
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6744   },
6745
6746   /* PREFIX_VEX_0F3A7F */
6747   {
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6751   },
6752
6753   /* PREFIX_VEX_0F3ACE */
6754   {
6755     { Bad_Opcode },
6756     { Bad_Opcode },
6757     { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6758   },
6759
6760   /* PREFIX_VEX_0F3ACF */
6761   {
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6765   },
6766
6767   /* PREFIX_VEX_0F3ADF */
6768   {
6769     { Bad_Opcode },
6770     { Bad_Opcode },
6771     { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6772   },
6773
6774   /* PREFIX_VEX_0F3AF0 */
6775   {
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6780   },
6781
6782 #include "i386-dis-evex-prefix.h"
6783 };
6784
6785 static const struct dis386 x86_64_table[][2] = {
6786   /* X86_64_06 */
6787   {
6788     { "pushP", { es }, 0 },
6789   },
6790
6791   /* X86_64_07 */
6792   {
6793     { "popP", { es }, 0 },
6794   },
6795
6796   /* X86_64_0D */
6797   {
6798     { "pushP", { cs }, 0 },
6799   },
6800
6801   /* X86_64_16 */
6802   {
6803     { "pushP", { ss }, 0 },
6804   },
6805
6806   /* X86_64_17 */
6807   {
6808     { "popP", { ss }, 0 },
6809   },
6810
6811   /* X86_64_1E */
6812   {
6813     { "pushP", { ds }, 0 },
6814   },
6815
6816   /* X86_64_1F */
6817   {
6818     { "popP", { ds }, 0 },
6819   },
6820
6821   /* X86_64_27 */
6822   {
6823     { "daa", { XX }, 0 },
6824   },
6825
6826   /* X86_64_2F */
6827   {
6828     { "das", { XX }, 0 },
6829   },
6830
6831   /* X86_64_37 */
6832   {
6833     { "aaa", { XX }, 0 },
6834   },
6835
6836   /* X86_64_3F */
6837   {
6838     { "aas", { XX }, 0 },
6839   },
6840
6841   /* X86_64_60 */
6842   {
6843     { "pushaP", { XX }, 0 },
6844   },
6845
6846   /* X86_64_61 */
6847   {
6848     { "popaP", { XX }, 0 },
6849   },
6850
6851   /* X86_64_62 */
6852   {
6853     { MOD_TABLE (MOD_62_32BIT) },
6854     { EVEX_TABLE (EVEX_0F) },
6855   },
6856
6857   /* X86_64_63 */
6858   {
6859     { "arpl", { Ew, Gw }, 0 },
6860     { "movs{lq|xd}", { Gv, Ed }, 0 },
6861   },
6862
6863   /* X86_64_6D */
6864   {
6865     { "ins{R|}", { Yzr, indirDX }, 0 },
6866     { "ins{G|}", { Yzr, indirDX }, 0 },
6867   },
6868
6869   /* X86_64_6F */
6870   {
6871     { "outs{R|}", { indirDXr, Xz }, 0 },
6872     { "outs{G|}", { indirDXr, Xz }, 0 },
6873   },
6874
6875   /* X86_64_82 */
6876   {
6877     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
6878     { REG_TABLE (REG_80) },
6879   },
6880
6881   /* X86_64_9A */
6882   {
6883     { "Jcall{T|}", { Ap }, 0 },
6884   },
6885
6886   /* X86_64_C4 */
6887   {
6888     { MOD_TABLE (MOD_C4_32BIT) },
6889     { VEX_C4_TABLE (VEX_0F) },
6890   },
6891
6892   /* X86_64_C5 */
6893   {
6894     { MOD_TABLE (MOD_C5_32BIT) },
6895     { VEX_C5_TABLE (VEX_0F) },
6896   },
6897
6898   /* X86_64_CE */
6899   {
6900     { "into", { XX }, 0 },
6901   },
6902
6903   /* X86_64_D4 */
6904   {
6905     { "aam", { Ib }, 0 },
6906   },
6907
6908   /* X86_64_D5 */
6909   {
6910     { "aad", { Ib }, 0 },
6911   },
6912
6913   /* X86_64_E8 */
6914   {
6915     { "callP",          { Jv, BND }, 0 },
6916     { "call@",          { Jv, BND }, 0 }
6917   },
6918
6919   /* X86_64_E9 */
6920   {
6921     { "jmpP",           { Jv, BND }, 0 },
6922     { "jmp@",           { Jv, BND }, 0 }
6923   },
6924
6925   /* X86_64_EA */
6926   {
6927     { "Jjmp{T|}", { Ap }, 0 },
6928   },
6929
6930   /* X86_64_0F01_REG_0 */
6931   {
6932     { "sgdt{Q|IQ}", { M }, 0 },
6933     { "sgdt", { M }, 0 },
6934   },
6935
6936   /* X86_64_0F01_REG_1 */
6937   {
6938     { "sidt{Q|IQ}", { M }, 0 },
6939     { "sidt", { M }, 0 },
6940   },
6941
6942   /* X86_64_0F01_REG_2 */
6943   {
6944     { "lgdt{Q|Q}", { M }, 0 },
6945     { "lgdt", { M }, 0 },
6946   },
6947
6948   /* X86_64_0F01_REG_3 */
6949   {
6950     { "lidt{Q|Q}", { M }, 0 },
6951     { "lidt", { M }, 0 },
6952   },
6953 };
6954
6955 static const struct dis386 three_byte_table[][256] = {
6956
6957   /* THREE_BYTE_0F38 */
6958   {
6959     /* 00 */
6960     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
6961     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
6962     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
6963     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
6964     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
6965     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
6966     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
6967     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
6968     /* 08 */
6969     { "psignb",         { MX, EM }, PREFIX_OPCODE },
6970     { "psignw",         { MX, EM }, PREFIX_OPCODE },
6971     { "psignd",         { MX, EM }, PREFIX_OPCODE },
6972     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
6973     { Bad_Opcode },
6974     { Bad_Opcode },
6975     { Bad_Opcode },
6976     { Bad_Opcode },
6977     /* 10 */
6978     { PREFIX_TABLE (PREFIX_0F3810) },
6979     { Bad_Opcode },
6980     { Bad_Opcode },
6981     { Bad_Opcode },
6982     { PREFIX_TABLE (PREFIX_0F3814) },
6983     { PREFIX_TABLE (PREFIX_0F3815) },
6984     { Bad_Opcode },
6985     { PREFIX_TABLE (PREFIX_0F3817) },
6986     /* 18 */
6987     { Bad_Opcode },
6988     { Bad_Opcode },
6989     { Bad_Opcode },
6990     { Bad_Opcode },
6991     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
6992     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
6993     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
6994     { Bad_Opcode },
6995     /* 20 */
6996     { PREFIX_TABLE (PREFIX_0F3820) },
6997     { PREFIX_TABLE (PREFIX_0F3821) },
6998     { PREFIX_TABLE (PREFIX_0F3822) },
6999     { PREFIX_TABLE (PREFIX_0F3823) },
7000     { PREFIX_TABLE (PREFIX_0F3824) },
7001     { PREFIX_TABLE (PREFIX_0F3825) },
7002     { Bad_Opcode },
7003     { Bad_Opcode },
7004     /* 28 */
7005     { PREFIX_TABLE (PREFIX_0F3828) },
7006     { PREFIX_TABLE (PREFIX_0F3829) },
7007     { PREFIX_TABLE (PREFIX_0F382A) },
7008     { PREFIX_TABLE (PREFIX_0F382B) },
7009     { Bad_Opcode },
7010     { Bad_Opcode },
7011     { Bad_Opcode },
7012     { Bad_Opcode },
7013     /* 30 */
7014     { PREFIX_TABLE (PREFIX_0F3830) },
7015     { PREFIX_TABLE (PREFIX_0F3831) },
7016     { PREFIX_TABLE (PREFIX_0F3832) },
7017     { PREFIX_TABLE (PREFIX_0F3833) },
7018     { PREFIX_TABLE (PREFIX_0F3834) },
7019     { PREFIX_TABLE (PREFIX_0F3835) },
7020     { Bad_Opcode },
7021     { PREFIX_TABLE (PREFIX_0F3837) },
7022     /* 38 */
7023     { PREFIX_TABLE (PREFIX_0F3838) },
7024     { PREFIX_TABLE (PREFIX_0F3839) },
7025     { PREFIX_TABLE (PREFIX_0F383A) },
7026     { PREFIX_TABLE (PREFIX_0F383B) },
7027     { PREFIX_TABLE (PREFIX_0F383C) },
7028     { PREFIX_TABLE (PREFIX_0F383D) },
7029     { PREFIX_TABLE (PREFIX_0F383E) },
7030     { PREFIX_TABLE (PREFIX_0F383F) },
7031     /* 40 */
7032     { PREFIX_TABLE (PREFIX_0F3840) },
7033     { PREFIX_TABLE (PREFIX_0F3841) },
7034     { Bad_Opcode },
7035     { Bad_Opcode },
7036     { Bad_Opcode },
7037     { Bad_Opcode },
7038     { Bad_Opcode },
7039     { Bad_Opcode },
7040     /* 48 */
7041     { Bad_Opcode },
7042     { Bad_Opcode },
7043     { Bad_Opcode },
7044     { Bad_Opcode },
7045     { Bad_Opcode },
7046     { Bad_Opcode },
7047     { Bad_Opcode },
7048     { Bad_Opcode },
7049     /* 50 */
7050     { Bad_Opcode },
7051     { Bad_Opcode },
7052     { Bad_Opcode },
7053     { Bad_Opcode },
7054     { Bad_Opcode },
7055     { Bad_Opcode },
7056     { Bad_Opcode },
7057     { Bad_Opcode },
7058     /* 58 */
7059     { Bad_Opcode },
7060     { Bad_Opcode },
7061     { Bad_Opcode },
7062     { Bad_Opcode },
7063     { Bad_Opcode },
7064     { Bad_Opcode },
7065     { Bad_Opcode },
7066     { Bad_Opcode },
7067     /* 60 */
7068     { Bad_Opcode },
7069     { Bad_Opcode },
7070     { Bad_Opcode },
7071     { Bad_Opcode },
7072     { Bad_Opcode },
7073     { Bad_Opcode },
7074     { Bad_Opcode },
7075     { Bad_Opcode },
7076     /* 68 */
7077     { Bad_Opcode },
7078     { Bad_Opcode },
7079     { Bad_Opcode },
7080     { Bad_Opcode },
7081     { Bad_Opcode },
7082     { Bad_Opcode },
7083     { Bad_Opcode },
7084     { Bad_Opcode },
7085     /* 70 */
7086     { Bad_Opcode },
7087     { Bad_Opcode },
7088     { Bad_Opcode },
7089     { Bad_Opcode },
7090     { Bad_Opcode },
7091     { Bad_Opcode },
7092     { Bad_Opcode },
7093     { Bad_Opcode },
7094     /* 78 */
7095     { Bad_Opcode },
7096     { Bad_Opcode },
7097     { Bad_Opcode },
7098     { Bad_Opcode },
7099     { Bad_Opcode },
7100     { Bad_Opcode },
7101     { Bad_Opcode },
7102     { Bad_Opcode },
7103     /* 80 */
7104     { PREFIX_TABLE (PREFIX_0F3880) },
7105     { PREFIX_TABLE (PREFIX_0F3881) },
7106     { PREFIX_TABLE (PREFIX_0F3882) },
7107     { Bad_Opcode },
7108     { Bad_Opcode },
7109     { Bad_Opcode },
7110     { Bad_Opcode },
7111     { Bad_Opcode },
7112     /* 88 */
7113     { Bad_Opcode },
7114     { Bad_Opcode },
7115     { Bad_Opcode },
7116     { Bad_Opcode },
7117     { Bad_Opcode },
7118     { Bad_Opcode },
7119     { Bad_Opcode },
7120     { Bad_Opcode },
7121     /* 90 */
7122     { Bad_Opcode },
7123     { Bad_Opcode },
7124     { Bad_Opcode },
7125     { Bad_Opcode },
7126     { Bad_Opcode },
7127     { Bad_Opcode },
7128     { Bad_Opcode },
7129     { Bad_Opcode },
7130     /* 98 */
7131     { Bad_Opcode },
7132     { Bad_Opcode },
7133     { Bad_Opcode },
7134     { Bad_Opcode },
7135     { Bad_Opcode },
7136     { Bad_Opcode },
7137     { Bad_Opcode },
7138     { Bad_Opcode },
7139     /* a0 */
7140     { Bad_Opcode },
7141     { Bad_Opcode },
7142     { Bad_Opcode },
7143     { Bad_Opcode },
7144     { Bad_Opcode },
7145     { Bad_Opcode },
7146     { Bad_Opcode },
7147     { Bad_Opcode },
7148     /* a8 */
7149     { Bad_Opcode },
7150     { Bad_Opcode },
7151     { Bad_Opcode },
7152     { Bad_Opcode },
7153     { Bad_Opcode },
7154     { Bad_Opcode },
7155     { Bad_Opcode },
7156     { Bad_Opcode },
7157     /* b0 */
7158     { Bad_Opcode },
7159     { Bad_Opcode },
7160     { Bad_Opcode },
7161     { Bad_Opcode },
7162     { Bad_Opcode },
7163     { Bad_Opcode },
7164     { Bad_Opcode },
7165     { Bad_Opcode },
7166     /* b8 */
7167     { Bad_Opcode },
7168     { Bad_Opcode },
7169     { Bad_Opcode },
7170     { Bad_Opcode },
7171     { Bad_Opcode },
7172     { Bad_Opcode },
7173     { Bad_Opcode },
7174     { Bad_Opcode },
7175     /* c0 */
7176     { Bad_Opcode },
7177     { Bad_Opcode },
7178     { Bad_Opcode },
7179     { Bad_Opcode },
7180     { Bad_Opcode },
7181     { Bad_Opcode },
7182     { Bad_Opcode },
7183     { Bad_Opcode },
7184     /* c8 */
7185     { PREFIX_TABLE (PREFIX_0F38C8) },
7186     { PREFIX_TABLE (PREFIX_0F38C9) },
7187     { PREFIX_TABLE (PREFIX_0F38CA) },
7188     { PREFIX_TABLE (PREFIX_0F38CB) },
7189     { PREFIX_TABLE (PREFIX_0F38CC) },
7190     { PREFIX_TABLE (PREFIX_0F38CD) },
7191     { Bad_Opcode },
7192     { PREFIX_TABLE (PREFIX_0F38CF) },
7193     /* d0 */
7194     { Bad_Opcode },
7195     { Bad_Opcode },
7196     { Bad_Opcode },
7197     { Bad_Opcode },
7198     { Bad_Opcode },
7199     { Bad_Opcode },
7200     { Bad_Opcode },
7201     { Bad_Opcode },
7202     /* d8 */
7203     { Bad_Opcode },
7204     { Bad_Opcode },
7205     { Bad_Opcode },
7206     { PREFIX_TABLE (PREFIX_0F38DB) },
7207     { PREFIX_TABLE (PREFIX_0F38DC) },
7208     { PREFIX_TABLE (PREFIX_0F38DD) },
7209     { PREFIX_TABLE (PREFIX_0F38DE) },
7210     { PREFIX_TABLE (PREFIX_0F38DF) },
7211     /* e0 */
7212     { Bad_Opcode },
7213     { Bad_Opcode },
7214     { Bad_Opcode },
7215     { Bad_Opcode },
7216     { Bad_Opcode },
7217     { Bad_Opcode },
7218     { Bad_Opcode },
7219     { Bad_Opcode },
7220     /* e8 */
7221     { Bad_Opcode },
7222     { Bad_Opcode },
7223     { Bad_Opcode },
7224     { Bad_Opcode },
7225     { Bad_Opcode },
7226     { Bad_Opcode },
7227     { Bad_Opcode },
7228     { Bad_Opcode },
7229     /* f0 */
7230     { PREFIX_TABLE (PREFIX_0F38F0) },
7231     { PREFIX_TABLE (PREFIX_0F38F1) },
7232     { Bad_Opcode },
7233     { Bad_Opcode },
7234     { Bad_Opcode },
7235     { PREFIX_TABLE (PREFIX_0F38F5) },
7236     { PREFIX_TABLE (PREFIX_0F38F6) },
7237     { Bad_Opcode },
7238     /* f8 */
7239     { PREFIX_TABLE (PREFIX_0F38F8) },
7240     { PREFIX_TABLE (PREFIX_0F38F9) },
7241     { Bad_Opcode },
7242     { Bad_Opcode },
7243     { Bad_Opcode },
7244     { Bad_Opcode },
7245     { Bad_Opcode },
7246     { Bad_Opcode },
7247   },
7248   /* THREE_BYTE_0F3A */
7249   {
7250     /* 00 */
7251     { Bad_Opcode },
7252     { Bad_Opcode },
7253     { Bad_Opcode },
7254     { Bad_Opcode },
7255     { Bad_Opcode },
7256     { Bad_Opcode },
7257     { Bad_Opcode },
7258     { Bad_Opcode },
7259     /* 08 */
7260     { PREFIX_TABLE (PREFIX_0F3A08) },
7261     { PREFIX_TABLE (PREFIX_0F3A09) },
7262     { PREFIX_TABLE (PREFIX_0F3A0A) },
7263     { PREFIX_TABLE (PREFIX_0F3A0B) },
7264     { PREFIX_TABLE (PREFIX_0F3A0C) },
7265     { PREFIX_TABLE (PREFIX_0F3A0D) },
7266     { PREFIX_TABLE (PREFIX_0F3A0E) },
7267     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
7268     /* 10 */
7269     { Bad_Opcode },
7270     { Bad_Opcode },
7271     { Bad_Opcode },
7272     { Bad_Opcode },
7273     { PREFIX_TABLE (PREFIX_0F3A14) },
7274     { PREFIX_TABLE (PREFIX_0F3A15) },
7275     { PREFIX_TABLE (PREFIX_0F3A16) },
7276     { PREFIX_TABLE (PREFIX_0F3A17) },
7277     /* 18 */
7278     { Bad_Opcode },
7279     { Bad_Opcode },
7280     { Bad_Opcode },
7281     { Bad_Opcode },
7282     { Bad_Opcode },
7283     { Bad_Opcode },
7284     { Bad_Opcode },
7285     { Bad_Opcode },
7286     /* 20 */
7287     { PREFIX_TABLE (PREFIX_0F3A20) },
7288     { PREFIX_TABLE (PREFIX_0F3A21) },
7289     { PREFIX_TABLE (PREFIX_0F3A22) },
7290     { Bad_Opcode },
7291     { Bad_Opcode },
7292     { Bad_Opcode },
7293     { Bad_Opcode },
7294     { Bad_Opcode },
7295     /* 28 */
7296     { Bad_Opcode },
7297     { Bad_Opcode },
7298     { Bad_Opcode },
7299     { Bad_Opcode },
7300     { Bad_Opcode },
7301     { Bad_Opcode },
7302     { Bad_Opcode },
7303     { Bad_Opcode },
7304     /* 30 */
7305     { Bad_Opcode },
7306     { Bad_Opcode },
7307     { Bad_Opcode },
7308     { Bad_Opcode },
7309     { Bad_Opcode },
7310     { Bad_Opcode },
7311     { Bad_Opcode },
7312     { Bad_Opcode },
7313     /* 38 */
7314     { Bad_Opcode },
7315     { Bad_Opcode },
7316     { Bad_Opcode },
7317     { Bad_Opcode },
7318     { Bad_Opcode },
7319     { Bad_Opcode },
7320     { Bad_Opcode },
7321     { Bad_Opcode },
7322     /* 40 */
7323     { PREFIX_TABLE (PREFIX_0F3A40) },
7324     { PREFIX_TABLE (PREFIX_0F3A41) },
7325     { PREFIX_TABLE (PREFIX_0F3A42) },
7326     { Bad_Opcode },
7327     { PREFIX_TABLE (PREFIX_0F3A44) },
7328     { Bad_Opcode },
7329     { Bad_Opcode },
7330     { Bad_Opcode },
7331     /* 48 */
7332     { Bad_Opcode },
7333     { Bad_Opcode },
7334     { Bad_Opcode },
7335     { Bad_Opcode },
7336     { Bad_Opcode },
7337     { Bad_Opcode },
7338     { Bad_Opcode },
7339     { Bad_Opcode },
7340     /* 50 */
7341     { Bad_Opcode },
7342     { Bad_Opcode },
7343     { Bad_Opcode },
7344     { Bad_Opcode },
7345     { Bad_Opcode },
7346     { Bad_Opcode },
7347     { Bad_Opcode },
7348     { Bad_Opcode },
7349     /* 58 */
7350     { Bad_Opcode },
7351     { Bad_Opcode },
7352     { Bad_Opcode },
7353     { Bad_Opcode },
7354     { Bad_Opcode },
7355     { Bad_Opcode },
7356     { Bad_Opcode },
7357     { Bad_Opcode },
7358     /* 60 */
7359     { PREFIX_TABLE (PREFIX_0F3A60) },
7360     { PREFIX_TABLE (PREFIX_0F3A61) },
7361     { PREFIX_TABLE (PREFIX_0F3A62) },
7362     { PREFIX_TABLE (PREFIX_0F3A63) },
7363     { Bad_Opcode },
7364     { Bad_Opcode },
7365     { Bad_Opcode },
7366     { Bad_Opcode },
7367     /* 68 */
7368     { Bad_Opcode },
7369     { Bad_Opcode },
7370     { Bad_Opcode },
7371     { Bad_Opcode },
7372     { Bad_Opcode },
7373     { Bad_Opcode },
7374     { Bad_Opcode },
7375     { Bad_Opcode },
7376     /* 70 */
7377     { Bad_Opcode },
7378     { Bad_Opcode },
7379     { Bad_Opcode },
7380     { Bad_Opcode },
7381     { Bad_Opcode },
7382     { Bad_Opcode },
7383     { Bad_Opcode },
7384     { Bad_Opcode },
7385     /* 78 */
7386     { Bad_Opcode },
7387     { Bad_Opcode },
7388     { Bad_Opcode },
7389     { Bad_Opcode },
7390     { Bad_Opcode },
7391     { Bad_Opcode },
7392     { Bad_Opcode },
7393     { Bad_Opcode },
7394     /* 80 */
7395     { Bad_Opcode },
7396     { Bad_Opcode },
7397     { Bad_Opcode },
7398     { Bad_Opcode },
7399     { Bad_Opcode },
7400     { Bad_Opcode },
7401     { Bad_Opcode },
7402     { Bad_Opcode },
7403     /* 88 */
7404     { Bad_Opcode },
7405     { Bad_Opcode },
7406     { Bad_Opcode },
7407     { Bad_Opcode },
7408     { Bad_Opcode },
7409     { Bad_Opcode },
7410     { Bad_Opcode },
7411     { Bad_Opcode },
7412     /* 90 */
7413     { Bad_Opcode },
7414     { Bad_Opcode },
7415     { Bad_Opcode },
7416     { Bad_Opcode },
7417     { Bad_Opcode },
7418     { Bad_Opcode },
7419     { Bad_Opcode },
7420     { Bad_Opcode },
7421     /* 98 */
7422     { Bad_Opcode },
7423     { Bad_Opcode },
7424     { Bad_Opcode },
7425     { Bad_Opcode },
7426     { Bad_Opcode },
7427     { Bad_Opcode },
7428     { Bad_Opcode },
7429     { Bad_Opcode },
7430     /* a0 */
7431     { Bad_Opcode },
7432     { Bad_Opcode },
7433     { Bad_Opcode },
7434     { Bad_Opcode },
7435     { Bad_Opcode },
7436     { Bad_Opcode },
7437     { Bad_Opcode },
7438     { Bad_Opcode },
7439     /* a8 */
7440     { Bad_Opcode },
7441     { Bad_Opcode },
7442     { Bad_Opcode },
7443     { Bad_Opcode },
7444     { Bad_Opcode },
7445     { Bad_Opcode },
7446     { Bad_Opcode },
7447     { Bad_Opcode },
7448     /* b0 */
7449     { Bad_Opcode },
7450     { Bad_Opcode },
7451     { Bad_Opcode },
7452     { Bad_Opcode },
7453     { Bad_Opcode },
7454     { Bad_Opcode },
7455     { Bad_Opcode },
7456     { Bad_Opcode },
7457     /* b8 */
7458     { Bad_Opcode },
7459     { Bad_Opcode },
7460     { Bad_Opcode },
7461     { Bad_Opcode },
7462     { Bad_Opcode },
7463     { Bad_Opcode },
7464     { Bad_Opcode },
7465     { Bad_Opcode },
7466     /* c0 */
7467     { Bad_Opcode },
7468     { Bad_Opcode },
7469     { Bad_Opcode },
7470     { Bad_Opcode },
7471     { Bad_Opcode },
7472     { Bad_Opcode },
7473     { Bad_Opcode },
7474     { Bad_Opcode },
7475     /* c8 */
7476     { Bad_Opcode },
7477     { Bad_Opcode },
7478     { Bad_Opcode },
7479     { Bad_Opcode },
7480     { PREFIX_TABLE (PREFIX_0F3ACC) },
7481     { Bad_Opcode },
7482     { PREFIX_TABLE (PREFIX_0F3ACE) },
7483     { PREFIX_TABLE (PREFIX_0F3ACF) },
7484     /* d0 */
7485     { Bad_Opcode },
7486     { Bad_Opcode },
7487     { Bad_Opcode },
7488     { Bad_Opcode },
7489     { Bad_Opcode },
7490     { Bad_Opcode },
7491     { Bad_Opcode },
7492     { Bad_Opcode },
7493     /* d8 */
7494     { Bad_Opcode },
7495     { Bad_Opcode },
7496     { Bad_Opcode },
7497     { Bad_Opcode },
7498     { Bad_Opcode },
7499     { Bad_Opcode },
7500     { Bad_Opcode },
7501     { PREFIX_TABLE (PREFIX_0F3ADF) },
7502     /* e0 */
7503     { Bad_Opcode },
7504     { Bad_Opcode },
7505     { Bad_Opcode },
7506     { Bad_Opcode },
7507     { Bad_Opcode },
7508     { Bad_Opcode },
7509     { Bad_Opcode },
7510     { Bad_Opcode },
7511     /* e8 */
7512     { Bad_Opcode },
7513     { Bad_Opcode },
7514     { Bad_Opcode },
7515     { Bad_Opcode },
7516     { Bad_Opcode },
7517     { Bad_Opcode },
7518     { Bad_Opcode },
7519     { Bad_Opcode },
7520     /* f0 */
7521     { Bad_Opcode },
7522     { Bad_Opcode },
7523     { Bad_Opcode },
7524     { Bad_Opcode },
7525     { Bad_Opcode },
7526     { Bad_Opcode },
7527     { Bad_Opcode },
7528     { Bad_Opcode },
7529     /* f8 */
7530     { Bad_Opcode },
7531     { Bad_Opcode },
7532     { Bad_Opcode },
7533     { Bad_Opcode },
7534     { Bad_Opcode },
7535     { Bad_Opcode },
7536     { Bad_Opcode },
7537     { Bad_Opcode },
7538   },
7539 };
7540
7541 static const struct dis386 xop_table[][256] = {
7542   /* XOP_08 */
7543   {
7544     /* 00 */
7545     { Bad_Opcode },
7546     { Bad_Opcode },
7547     { Bad_Opcode },
7548     { Bad_Opcode },
7549     { Bad_Opcode },
7550     { Bad_Opcode },
7551     { Bad_Opcode },
7552     { Bad_Opcode },
7553     /* 08 */
7554     { Bad_Opcode },
7555     { Bad_Opcode },
7556     { Bad_Opcode },
7557     { Bad_Opcode },
7558     { Bad_Opcode },
7559     { Bad_Opcode },
7560     { Bad_Opcode },
7561     { Bad_Opcode },
7562     /* 10 */
7563     { Bad_Opcode },
7564     { Bad_Opcode },
7565     { Bad_Opcode },
7566     { Bad_Opcode },
7567     { Bad_Opcode },
7568     { Bad_Opcode },
7569     { Bad_Opcode },
7570     { Bad_Opcode },
7571     /* 18 */
7572     { Bad_Opcode },
7573     { Bad_Opcode },
7574     { Bad_Opcode },
7575     { Bad_Opcode },
7576     { Bad_Opcode },
7577     { Bad_Opcode },
7578     { Bad_Opcode },
7579     { Bad_Opcode },
7580     /* 20 */
7581     { Bad_Opcode },
7582     { Bad_Opcode },
7583     { Bad_Opcode },
7584     { Bad_Opcode },
7585     { Bad_Opcode },
7586     { Bad_Opcode },
7587     { Bad_Opcode },
7588     { Bad_Opcode },
7589     /* 28 */
7590     { Bad_Opcode },
7591     { Bad_Opcode },
7592     { Bad_Opcode },
7593     { Bad_Opcode },
7594     { Bad_Opcode },
7595     { Bad_Opcode },
7596     { Bad_Opcode },
7597     { Bad_Opcode },
7598     /* 30 */
7599     { Bad_Opcode },
7600     { Bad_Opcode },
7601     { Bad_Opcode },
7602     { Bad_Opcode },
7603     { Bad_Opcode },
7604     { Bad_Opcode },
7605     { Bad_Opcode },
7606     { Bad_Opcode },
7607     /* 38 */
7608     { Bad_Opcode },
7609     { Bad_Opcode },
7610     { Bad_Opcode },
7611     { Bad_Opcode },
7612     { Bad_Opcode },
7613     { Bad_Opcode },
7614     { Bad_Opcode },
7615     { Bad_Opcode },
7616     /* 40 */
7617     { Bad_Opcode },
7618     { Bad_Opcode },
7619     { Bad_Opcode },
7620     { Bad_Opcode },
7621     { Bad_Opcode },
7622     { Bad_Opcode },
7623     { Bad_Opcode },
7624     { Bad_Opcode },
7625     /* 48 */
7626     { Bad_Opcode },
7627     { Bad_Opcode },
7628     { Bad_Opcode },
7629     { Bad_Opcode },
7630     { Bad_Opcode },
7631     { Bad_Opcode },
7632     { Bad_Opcode },
7633     { Bad_Opcode },
7634     /* 50 */
7635     { Bad_Opcode },
7636     { Bad_Opcode },
7637     { Bad_Opcode },
7638     { Bad_Opcode },
7639     { Bad_Opcode },
7640     { Bad_Opcode },
7641     { Bad_Opcode },
7642     { Bad_Opcode },
7643     /* 58 */
7644     { Bad_Opcode },
7645     { Bad_Opcode },
7646     { Bad_Opcode },
7647     { Bad_Opcode },
7648     { Bad_Opcode },
7649     { Bad_Opcode },
7650     { Bad_Opcode },
7651     { Bad_Opcode },
7652     /* 60 */
7653     { Bad_Opcode },
7654     { Bad_Opcode },
7655     { Bad_Opcode },
7656     { Bad_Opcode },
7657     { Bad_Opcode },
7658     { Bad_Opcode },
7659     { Bad_Opcode },
7660     { Bad_Opcode },
7661     /* 68 */
7662     { Bad_Opcode },
7663     { Bad_Opcode },
7664     { Bad_Opcode },
7665     { Bad_Opcode },
7666     { Bad_Opcode },
7667     { Bad_Opcode },
7668     { Bad_Opcode },
7669     { Bad_Opcode },
7670     /* 70 */
7671     { Bad_Opcode },
7672     { Bad_Opcode },
7673     { Bad_Opcode },
7674     { Bad_Opcode },
7675     { Bad_Opcode },
7676     { Bad_Opcode },
7677     { Bad_Opcode },
7678     { Bad_Opcode },
7679     /* 78 */
7680     { Bad_Opcode },
7681     { Bad_Opcode },
7682     { Bad_Opcode },
7683     { Bad_Opcode },
7684     { Bad_Opcode },
7685     { Bad_Opcode },
7686     { Bad_Opcode },
7687     { Bad_Opcode },
7688     /* 80 */
7689     { Bad_Opcode },
7690     { Bad_Opcode },
7691     { Bad_Opcode },
7692     { Bad_Opcode },
7693     { Bad_Opcode },
7694     { "vpmacssww",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7695     { "vpmacsswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7696     { "vpmacssdql",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7697     /* 88 */
7698     { Bad_Opcode },
7699     { Bad_Opcode },
7700     { Bad_Opcode },
7701     { Bad_Opcode },
7702     { Bad_Opcode },
7703     { Bad_Opcode },
7704     { "vpmacssdd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7705     { "vpmacssdqh",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7706     /* 90 */
7707     { Bad_Opcode },
7708     { Bad_Opcode },
7709     { Bad_Opcode },
7710     { Bad_Opcode },
7711     { Bad_Opcode },
7712     { "vpmacsww",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7713     { "vpmacswd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7714     { "vpmacsdql",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7715     /* 98 */
7716     { Bad_Opcode },
7717     { Bad_Opcode },
7718     { Bad_Opcode },
7719     { Bad_Opcode },
7720     { Bad_Opcode },
7721     { Bad_Opcode },
7722     { "vpmacsdd",       { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7723     { "vpmacsdqh",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7724     /* a0 */
7725     { Bad_Opcode },
7726     { Bad_Opcode },
7727     { "vpcmov",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728     { "vpperm",         { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729     { Bad_Opcode },
7730     { Bad_Opcode },
7731     { "vpmadcsswd",     { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7732     { Bad_Opcode },
7733     /* a8 */
7734     { Bad_Opcode },
7735     { Bad_Opcode },
7736     { Bad_Opcode },
7737     { Bad_Opcode },
7738     { Bad_Opcode },
7739     { Bad_Opcode },
7740     { Bad_Opcode },
7741     { Bad_Opcode },
7742     /* b0 */
7743     { Bad_Opcode },
7744     { Bad_Opcode },
7745     { Bad_Opcode },
7746     { Bad_Opcode },
7747     { Bad_Opcode },
7748     { Bad_Opcode },
7749     { "vpmadcswd",      { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7750     { Bad_Opcode },
7751     /* b8 */
7752     { Bad_Opcode },
7753     { Bad_Opcode },
7754     { Bad_Opcode },
7755     { Bad_Opcode },
7756     { Bad_Opcode },
7757     { Bad_Opcode },
7758     { Bad_Opcode },
7759     { Bad_Opcode },
7760     /* c0 */
7761     { "vprotb",         { XM, Vex_2src_1, Ib }, 0 },
7762     { "vprotw",         { XM, Vex_2src_1, Ib }, 0 },
7763     { "vprotd",         { XM, Vex_2src_1, Ib }, 0 },
7764     { "vprotq",         { XM, Vex_2src_1, Ib }, 0 },
7765     { Bad_Opcode },
7766     { Bad_Opcode },
7767     { Bad_Opcode },
7768     { Bad_Opcode },
7769     /* c8 */
7770     { Bad_Opcode },
7771     { Bad_Opcode },
7772     { Bad_Opcode },
7773     { Bad_Opcode },
7774     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7775     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7776     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7777     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7778     /* d0 */
7779     { Bad_Opcode },
7780     { Bad_Opcode },
7781     { Bad_Opcode },
7782     { Bad_Opcode },
7783     { Bad_Opcode },
7784     { Bad_Opcode },
7785     { Bad_Opcode },
7786     { Bad_Opcode },
7787     /* d8 */
7788     { Bad_Opcode },
7789     { Bad_Opcode },
7790     { Bad_Opcode },
7791     { Bad_Opcode },
7792     { Bad_Opcode },
7793     { Bad_Opcode },
7794     { Bad_Opcode },
7795     { Bad_Opcode },
7796     /* e0 */
7797     { Bad_Opcode },
7798     { Bad_Opcode },
7799     { Bad_Opcode },
7800     { Bad_Opcode },
7801     { Bad_Opcode },
7802     { Bad_Opcode },
7803     { Bad_Opcode },
7804     { Bad_Opcode },
7805     /* e8 */
7806     { Bad_Opcode },
7807     { Bad_Opcode },
7808     { Bad_Opcode },
7809     { Bad_Opcode },
7810     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7811     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7812     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7813     { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7814     /* f0 */
7815     { Bad_Opcode },
7816     { Bad_Opcode },
7817     { Bad_Opcode },
7818     { Bad_Opcode },
7819     { Bad_Opcode },
7820     { Bad_Opcode },
7821     { Bad_Opcode },
7822     { Bad_Opcode },
7823     /* f8 */
7824     { Bad_Opcode },
7825     { Bad_Opcode },
7826     { Bad_Opcode },
7827     { Bad_Opcode },
7828     { Bad_Opcode },
7829     { Bad_Opcode },
7830     { Bad_Opcode },
7831     { Bad_Opcode },
7832   },
7833   /* XOP_09 */
7834   {
7835     /* 00 */
7836     { Bad_Opcode },
7837     { REG_TABLE (REG_XOP_TBM_01) },
7838     { REG_TABLE (REG_XOP_TBM_02) },
7839     { Bad_Opcode },
7840     { Bad_Opcode },
7841     { Bad_Opcode },
7842     { Bad_Opcode },
7843     { Bad_Opcode },
7844     /* 08 */
7845     { Bad_Opcode },
7846     { Bad_Opcode },
7847     { Bad_Opcode },
7848     { Bad_Opcode },
7849     { Bad_Opcode },
7850     { Bad_Opcode },
7851     { Bad_Opcode },
7852     { Bad_Opcode },
7853     /* 10 */
7854     { Bad_Opcode },
7855     { Bad_Opcode },
7856     { REG_TABLE (REG_XOP_LWPCB) },
7857     { Bad_Opcode },
7858     { Bad_Opcode },
7859     { Bad_Opcode },
7860     { Bad_Opcode },
7861     { Bad_Opcode },
7862     /* 18 */
7863     { Bad_Opcode },
7864     { Bad_Opcode },
7865     { Bad_Opcode },
7866     { Bad_Opcode },
7867     { Bad_Opcode },
7868     { Bad_Opcode },
7869     { Bad_Opcode },
7870     { Bad_Opcode },
7871     /* 20 */
7872     { Bad_Opcode },
7873     { Bad_Opcode },
7874     { Bad_Opcode },
7875     { Bad_Opcode },
7876     { Bad_Opcode },
7877     { Bad_Opcode },
7878     { Bad_Opcode },
7879     { Bad_Opcode },
7880     /* 28 */
7881     { Bad_Opcode },
7882     { Bad_Opcode },
7883     { Bad_Opcode },
7884     { Bad_Opcode },
7885     { Bad_Opcode },
7886     { Bad_Opcode },
7887     { Bad_Opcode },
7888     { Bad_Opcode },
7889     /* 30 */
7890     { Bad_Opcode },
7891     { Bad_Opcode },
7892     { Bad_Opcode },
7893     { Bad_Opcode },
7894     { Bad_Opcode },
7895     { Bad_Opcode },
7896     { Bad_Opcode },
7897     { Bad_Opcode },
7898     /* 38 */
7899     { Bad_Opcode },
7900     { Bad_Opcode },
7901     { Bad_Opcode },
7902     { Bad_Opcode },
7903     { Bad_Opcode },
7904     { Bad_Opcode },
7905     { Bad_Opcode },
7906     { Bad_Opcode },
7907     /* 40 */
7908     { Bad_Opcode },
7909     { Bad_Opcode },
7910     { Bad_Opcode },
7911     { Bad_Opcode },
7912     { Bad_Opcode },
7913     { Bad_Opcode },
7914     { Bad_Opcode },
7915     { Bad_Opcode },
7916     /* 48 */
7917     { Bad_Opcode },
7918     { Bad_Opcode },
7919     { Bad_Opcode },
7920     { Bad_Opcode },
7921     { Bad_Opcode },
7922     { Bad_Opcode },
7923     { Bad_Opcode },
7924     { Bad_Opcode },
7925     /* 50 */
7926     { Bad_Opcode },
7927     { Bad_Opcode },
7928     { Bad_Opcode },
7929     { Bad_Opcode },
7930     { Bad_Opcode },
7931     { Bad_Opcode },
7932     { Bad_Opcode },
7933     { Bad_Opcode },
7934     /* 58 */
7935     { Bad_Opcode },
7936     { Bad_Opcode },
7937     { Bad_Opcode },
7938     { Bad_Opcode },
7939     { Bad_Opcode },
7940     { Bad_Opcode },
7941     { Bad_Opcode },
7942     { Bad_Opcode },
7943     /* 60 */
7944     { Bad_Opcode },
7945     { Bad_Opcode },
7946     { Bad_Opcode },
7947     { Bad_Opcode },
7948     { Bad_Opcode },
7949     { Bad_Opcode },
7950     { Bad_Opcode },
7951     { Bad_Opcode },
7952     /* 68 */
7953     { Bad_Opcode },
7954     { Bad_Opcode },
7955     { Bad_Opcode },
7956     { Bad_Opcode },
7957     { Bad_Opcode },
7958     { Bad_Opcode },
7959     { Bad_Opcode },
7960     { Bad_Opcode },
7961     /* 70 */
7962     { Bad_Opcode },
7963     { Bad_Opcode },
7964     { Bad_Opcode },
7965     { Bad_Opcode },
7966     { Bad_Opcode },
7967     { Bad_Opcode },
7968     { Bad_Opcode },
7969     { Bad_Opcode },
7970     /* 78 */
7971     { Bad_Opcode },
7972     { Bad_Opcode },
7973     { Bad_Opcode },
7974     { Bad_Opcode },
7975     { Bad_Opcode },
7976     { Bad_Opcode },
7977     { Bad_Opcode },
7978     { Bad_Opcode },
7979     /* 80 */
7980     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7981     { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7982     { "vfrczss",        { XM, EXd }, 0 },
7983     { "vfrczsd",        { XM, EXq }, 0 },
7984     { Bad_Opcode },
7985     { Bad_Opcode },
7986     { Bad_Opcode },
7987     { Bad_Opcode },
7988     /* 88 */
7989     { Bad_Opcode },
7990     { Bad_Opcode },
7991     { Bad_Opcode },
7992     { Bad_Opcode },
7993     { Bad_Opcode },
7994     { Bad_Opcode },
7995     { Bad_Opcode },
7996     { Bad_Opcode },
7997     /* 90 */
7998     { "vprotb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
7999     { "vprotw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8000     { "vprotd",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8001     { "vprotq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8002     { "vpshlb",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8003     { "vpshlw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8004     { "vpshld",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8005     { "vpshlq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8006     /* 98 */
8007     { "vpshab",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8008     { "vpshaw",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8009     { "vpshad",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8010     { "vpshaq",         { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8011     { Bad_Opcode },
8012     { Bad_Opcode },
8013     { Bad_Opcode },
8014     { Bad_Opcode },
8015     /* a0 */
8016     { Bad_Opcode },
8017     { Bad_Opcode },
8018     { Bad_Opcode },
8019     { Bad_Opcode },
8020     { Bad_Opcode },
8021     { Bad_Opcode },
8022     { Bad_Opcode },
8023     { Bad_Opcode },
8024     /* a8 */
8025     { Bad_Opcode },
8026     { Bad_Opcode },
8027     { Bad_Opcode },
8028     { Bad_Opcode },
8029     { Bad_Opcode },
8030     { Bad_Opcode },
8031     { Bad_Opcode },
8032     { Bad_Opcode },
8033     /* b0 */
8034     { Bad_Opcode },
8035     { Bad_Opcode },
8036     { Bad_Opcode },
8037     { Bad_Opcode },
8038     { Bad_Opcode },
8039     { Bad_Opcode },
8040     { Bad_Opcode },
8041     { Bad_Opcode },
8042     /* b8 */
8043     { Bad_Opcode },
8044     { Bad_Opcode },
8045     { Bad_Opcode },
8046     { Bad_Opcode },
8047     { Bad_Opcode },
8048     { Bad_Opcode },
8049     { Bad_Opcode },
8050     { Bad_Opcode },
8051     /* c0 */
8052     { Bad_Opcode },
8053     { "vphaddbw",       { XM, EXxmm }, 0 },
8054     { "vphaddbd",       { XM, EXxmm }, 0 },
8055     { "vphaddbq",       { XM, EXxmm }, 0 },
8056     { Bad_Opcode },
8057     { Bad_Opcode },
8058     { "vphaddwd",       { XM, EXxmm }, 0 },
8059     { "vphaddwq",       { XM, EXxmm }, 0 },
8060     /* c8 */
8061     { Bad_Opcode },
8062     { Bad_Opcode },
8063     { Bad_Opcode },
8064     { "vphadddq",       { XM, EXxmm }, 0 },
8065     { Bad_Opcode },
8066     { Bad_Opcode },
8067     { Bad_Opcode },
8068     { Bad_Opcode },
8069     /* d0 */
8070     { Bad_Opcode },
8071     { "vphaddubw",      { XM, EXxmm }, 0 },
8072     { "vphaddubd",      { XM, EXxmm }, 0 },
8073     { "vphaddubq",      { XM, EXxmm }, 0 },
8074     { Bad_Opcode },
8075     { Bad_Opcode },
8076     { "vphadduwd",      { XM, EXxmm }, 0 },
8077     { "vphadduwq",      { XM, EXxmm }, 0 },
8078     /* d8 */
8079     { Bad_Opcode },
8080     { Bad_Opcode },
8081     { Bad_Opcode },
8082     { "vphaddudq",      { XM, EXxmm }, 0 },
8083     { Bad_Opcode },
8084     { Bad_Opcode },
8085     { Bad_Opcode },
8086     { Bad_Opcode },
8087     /* e0 */
8088     { Bad_Opcode },
8089     { "vphsubbw",       { XM, EXxmm }, 0 },
8090     { "vphsubwd",       { XM, EXxmm }, 0 },
8091     { "vphsubdq",       { XM, EXxmm }, 0 },
8092     { Bad_Opcode },
8093     { Bad_Opcode },
8094     { Bad_Opcode },
8095     { Bad_Opcode },
8096     /* e8 */
8097     { Bad_Opcode },
8098     { Bad_Opcode },
8099     { Bad_Opcode },
8100     { Bad_Opcode },
8101     { Bad_Opcode },
8102     { Bad_Opcode },
8103     { Bad_Opcode },
8104     { Bad_Opcode },
8105     /* f0 */
8106     { Bad_Opcode },
8107     { Bad_Opcode },
8108     { Bad_Opcode },
8109     { Bad_Opcode },
8110     { Bad_Opcode },
8111     { Bad_Opcode },
8112     { Bad_Opcode },
8113     { Bad_Opcode },
8114     /* f8 */
8115     { Bad_Opcode },
8116     { Bad_Opcode },
8117     { Bad_Opcode },
8118     { Bad_Opcode },
8119     { Bad_Opcode },
8120     { Bad_Opcode },
8121     { Bad_Opcode },
8122     { Bad_Opcode },
8123   },
8124   /* XOP_0A */
8125   {
8126     /* 00 */
8127     { Bad_Opcode },
8128     { Bad_Opcode },
8129     { Bad_Opcode },
8130     { Bad_Opcode },
8131     { Bad_Opcode },
8132     { Bad_Opcode },
8133     { Bad_Opcode },
8134     { Bad_Opcode },
8135     /* 08 */
8136     { Bad_Opcode },
8137     { Bad_Opcode },
8138     { Bad_Opcode },
8139     { Bad_Opcode },
8140     { Bad_Opcode },
8141     { Bad_Opcode },
8142     { Bad_Opcode },
8143     { Bad_Opcode },
8144     /* 10 */
8145     { "bextrS", { Gdq, Edq, Id }, 0 },
8146     { Bad_Opcode },
8147     { REG_TABLE (REG_XOP_LWP) },
8148     { Bad_Opcode },
8149     { Bad_Opcode },
8150     { Bad_Opcode },
8151     { Bad_Opcode },
8152     { Bad_Opcode },
8153     /* 18 */
8154     { Bad_Opcode },
8155     { Bad_Opcode },
8156     { Bad_Opcode },
8157     { Bad_Opcode },
8158     { Bad_Opcode },
8159     { Bad_Opcode },
8160     { Bad_Opcode },
8161     { Bad_Opcode },
8162     /* 20 */
8163     { Bad_Opcode },
8164     { Bad_Opcode },
8165     { Bad_Opcode },
8166     { Bad_Opcode },
8167     { Bad_Opcode },
8168     { Bad_Opcode },
8169     { Bad_Opcode },
8170     { Bad_Opcode },
8171     /* 28 */
8172     { Bad_Opcode },
8173     { Bad_Opcode },
8174     { Bad_Opcode },
8175     { Bad_Opcode },
8176     { Bad_Opcode },
8177     { Bad_Opcode },
8178     { Bad_Opcode },
8179     { Bad_Opcode },
8180     /* 30 */
8181     { Bad_Opcode },
8182     { Bad_Opcode },
8183     { Bad_Opcode },
8184     { Bad_Opcode },
8185     { Bad_Opcode },
8186     { Bad_Opcode },
8187     { Bad_Opcode },
8188     { Bad_Opcode },
8189     /* 38 */
8190     { Bad_Opcode },
8191     { Bad_Opcode },
8192     { Bad_Opcode },
8193     { Bad_Opcode },
8194     { Bad_Opcode },
8195     { Bad_Opcode },
8196     { Bad_Opcode },
8197     { Bad_Opcode },
8198     /* 40 */
8199     { Bad_Opcode },
8200     { Bad_Opcode },
8201     { Bad_Opcode },
8202     { Bad_Opcode },
8203     { Bad_Opcode },
8204     { Bad_Opcode },
8205     { Bad_Opcode },
8206     { Bad_Opcode },
8207     /* 48 */
8208     { Bad_Opcode },
8209     { Bad_Opcode },
8210     { Bad_Opcode },
8211     { Bad_Opcode },
8212     { Bad_Opcode },
8213     { Bad_Opcode },
8214     { Bad_Opcode },
8215     { Bad_Opcode },
8216     /* 50 */
8217     { Bad_Opcode },
8218     { Bad_Opcode },
8219     { Bad_Opcode },
8220     { Bad_Opcode },
8221     { Bad_Opcode },
8222     { Bad_Opcode },
8223     { Bad_Opcode },
8224     { Bad_Opcode },
8225     /* 58 */
8226     { Bad_Opcode },
8227     { Bad_Opcode },
8228     { Bad_Opcode },
8229     { Bad_Opcode },
8230     { Bad_Opcode },
8231     { Bad_Opcode },
8232     { Bad_Opcode },
8233     { Bad_Opcode },
8234     /* 60 */
8235     { Bad_Opcode },
8236     { Bad_Opcode },
8237     { Bad_Opcode },
8238     { Bad_Opcode },
8239     { Bad_Opcode },
8240     { Bad_Opcode },
8241     { Bad_Opcode },
8242     { Bad_Opcode },
8243     /* 68 */
8244     { Bad_Opcode },
8245     { Bad_Opcode },
8246     { Bad_Opcode },
8247     { Bad_Opcode },
8248     { Bad_Opcode },
8249     { Bad_Opcode },
8250     { Bad_Opcode },
8251     { Bad_Opcode },
8252     /* 70 */
8253     { Bad_Opcode },
8254     { Bad_Opcode },
8255     { Bad_Opcode },
8256     { Bad_Opcode },
8257     { Bad_Opcode },
8258     { Bad_Opcode },
8259     { Bad_Opcode },
8260     { Bad_Opcode },
8261     /* 78 */
8262     { Bad_Opcode },
8263     { Bad_Opcode },
8264     { Bad_Opcode },
8265     { Bad_Opcode },
8266     { Bad_Opcode },
8267     { Bad_Opcode },
8268     { Bad_Opcode },
8269     { Bad_Opcode },
8270     /* 80 */
8271     { Bad_Opcode },
8272     { Bad_Opcode },
8273     { Bad_Opcode },
8274     { Bad_Opcode },
8275     { Bad_Opcode },
8276     { Bad_Opcode },
8277     { Bad_Opcode },
8278     { Bad_Opcode },
8279     /* 88 */
8280     { Bad_Opcode },
8281     { Bad_Opcode },
8282     { Bad_Opcode },
8283     { Bad_Opcode },
8284     { Bad_Opcode },
8285     { Bad_Opcode },
8286     { Bad_Opcode },
8287     { Bad_Opcode },
8288     /* 90 */
8289     { Bad_Opcode },
8290     { Bad_Opcode },
8291     { Bad_Opcode },
8292     { Bad_Opcode },
8293     { Bad_Opcode },
8294     { Bad_Opcode },
8295     { Bad_Opcode },
8296     { Bad_Opcode },
8297     /* 98 */
8298     { Bad_Opcode },
8299     { Bad_Opcode },
8300     { Bad_Opcode },
8301     { Bad_Opcode },
8302     { Bad_Opcode },
8303     { Bad_Opcode },
8304     { Bad_Opcode },
8305     { Bad_Opcode },
8306     /* a0 */
8307     { Bad_Opcode },
8308     { Bad_Opcode },
8309     { Bad_Opcode },
8310     { Bad_Opcode },
8311     { Bad_Opcode },
8312     { Bad_Opcode },
8313     { Bad_Opcode },
8314     { Bad_Opcode },
8315     /* a8 */
8316     { Bad_Opcode },
8317     { Bad_Opcode },
8318     { Bad_Opcode },
8319     { Bad_Opcode },
8320     { Bad_Opcode },
8321     { Bad_Opcode },
8322     { Bad_Opcode },
8323     { Bad_Opcode },
8324     /* b0 */
8325     { Bad_Opcode },
8326     { Bad_Opcode },
8327     { Bad_Opcode },
8328     { Bad_Opcode },
8329     { Bad_Opcode },
8330     { Bad_Opcode },
8331     { Bad_Opcode },
8332     { Bad_Opcode },
8333     /* b8 */
8334     { Bad_Opcode },
8335     { Bad_Opcode },
8336     { Bad_Opcode },
8337     { Bad_Opcode },
8338     { Bad_Opcode },
8339     { Bad_Opcode },
8340     { Bad_Opcode },
8341     { Bad_Opcode },
8342     /* c0 */
8343     { Bad_Opcode },
8344     { Bad_Opcode },
8345     { Bad_Opcode },
8346     { Bad_Opcode },
8347     { Bad_Opcode },
8348     { Bad_Opcode },
8349     { Bad_Opcode },
8350     { Bad_Opcode },
8351     /* c8 */
8352     { Bad_Opcode },
8353     { Bad_Opcode },
8354     { Bad_Opcode },
8355     { Bad_Opcode },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { Bad_Opcode },
8359     { Bad_Opcode },
8360     /* d0 */
8361     { Bad_Opcode },
8362     { Bad_Opcode },
8363     { Bad_Opcode },
8364     { Bad_Opcode },
8365     { Bad_Opcode },
8366     { Bad_Opcode },
8367     { Bad_Opcode },
8368     { Bad_Opcode },
8369     /* d8 */
8370     { Bad_Opcode },
8371     { Bad_Opcode },
8372     { Bad_Opcode },
8373     { Bad_Opcode },
8374     { Bad_Opcode },
8375     { Bad_Opcode },
8376     { Bad_Opcode },
8377     { Bad_Opcode },
8378     /* e0 */
8379     { Bad_Opcode },
8380     { Bad_Opcode },
8381     { Bad_Opcode },
8382     { Bad_Opcode },
8383     { Bad_Opcode },
8384     { Bad_Opcode },
8385     { Bad_Opcode },
8386     { Bad_Opcode },
8387     /* e8 */
8388     { Bad_Opcode },
8389     { Bad_Opcode },
8390     { Bad_Opcode },
8391     { Bad_Opcode },
8392     { Bad_Opcode },
8393     { Bad_Opcode },
8394     { Bad_Opcode },
8395     { Bad_Opcode },
8396     /* f0 */
8397     { Bad_Opcode },
8398     { Bad_Opcode },
8399     { Bad_Opcode },
8400     { Bad_Opcode },
8401     { Bad_Opcode },
8402     { Bad_Opcode },
8403     { Bad_Opcode },
8404     { Bad_Opcode },
8405     /* f8 */
8406     { Bad_Opcode },
8407     { Bad_Opcode },
8408     { Bad_Opcode },
8409     { Bad_Opcode },
8410     { Bad_Opcode },
8411     { Bad_Opcode },
8412     { Bad_Opcode },
8413     { Bad_Opcode },
8414   },
8415 };
8416
8417 static const struct dis386 vex_table[][256] = {
8418   /* VEX_0F */
8419   {
8420     /* 00 */
8421     { Bad_Opcode },
8422     { Bad_Opcode },
8423     { Bad_Opcode },
8424     { Bad_Opcode },
8425     { Bad_Opcode },
8426     { Bad_Opcode },
8427     { Bad_Opcode },
8428     { Bad_Opcode },
8429     /* 08 */
8430     { Bad_Opcode },
8431     { Bad_Opcode },
8432     { Bad_Opcode },
8433     { Bad_Opcode },
8434     { Bad_Opcode },
8435     { Bad_Opcode },
8436     { Bad_Opcode },
8437     { Bad_Opcode },
8438     /* 10 */
8439     { PREFIX_TABLE (PREFIX_VEX_0F10) },
8440     { PREFIX_TABLE (PREFIX_VEX_0F11) },
8441     { PREFIX_TABLE (PREFIX_VEX_0F12) },
8442     { MOD_TABLE (MOD_VEX_0F13) },
8443     { "vunpcklpX",      { XM, Vex, EXx }, 0 },
8444     { "vunpckhpX",      { XM, Vex, EXx }, 0 },
8445     { PREFIX_TABLE (PREFIX_VEX_0F16) },
8446     { MOD_TABLE (MOD_VEX_0F17) },
8447     /* 18 */
8448     { Bad_Opcode },
8449     { Bad_Opcode },
8450     { Bad_Opcode },
8451     { Bad_Opcode },
8452     { Bad_Opcode },
8453     { Bad_Opcode },
8454     { Bad_Opcode },
8455     { Bad_Opcode },
8456     /* 20 */
8457     { Bad_Opcode },
8458     { Bad_Opcode },
8459     { Bad_Opcode },
8460     { Bad_Opcode },
8461     { Bad_Opcode },
8462     { Bad_Opcode },
8463     { Bad_Opcode },
8464     { Bad_Opcode },
8465     /* 28 */
8466     { "vmovapX",        { XM, EXx }, 0 },
8467     { "vmovapX",        { EXxS, XM }, 0 },
8468     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8469     { MOD_TABLE (MOD_VEX_0F2B) },
8470     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8471     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8472     { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8473     { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8474     /* 30 */
8475     { Bad_Opcode },
8476     { Bad_Opcode },
8477     { Bad_Opcode },
8478     { Bad_Opcode },
8479     { Bad_Opcode },
8480     { Bad_Opcode },
8481     { Bad_Opcode },
8482     { Bad_Opcode },
8483     /* 38 */
8484     { Bad_Opcode },
8485     { Bad_Opcode },
8486     { Bad_Opcode },
8487     { Bad_Opcode },
8488     { Bad_Opcode },
8489     { Bad_Opcode },
8490     { Bad_Opcode },
8491     { Bad_Opcode },
8492     /* 40 */
8493     { Bad_Opcode },
8494     { PREFIX_TABLE (PREFIX_VEX_0F41) },
8495     { PREFIX_TABLE (PREFIX_VEX_0F42) },
8496     { Bad_Opcode },
8497     { PREFIX_TABLE (PREFIX_VEX_0F44) },
8498     { PREFIX_TABLE (PREFIX_VEX_0F45) },
8499     { PREFIX_TABLE (PREFIX_VEX_0F46) },
8500     { PREFIX_TABLE (PREFIX_VEX_0F47) },
8501     /* 48 */
8502     { Bad_Opcode },
8503     { Bad_Opcode },
8504     { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8505     { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8506     { Bad_Opcode },
8507     { Bad_Opcode },
8508     { Bad_Opcode },
8509     { Bad_Opcode },
8510     /* 50 */
8511     { MOD_TABLE (MOD_VEX_0F50) },
8512     { PREFIX_TABLE (PREFIX_VEX_0F51) },
8513     { PREFIX_TABLE (PREFIX_VEX_0F52) },
8514     { PREFIX_TABLE (PREFIX_VEX_0F53) },
8515     { "vandpX",         { XM, Vex, EXx }, 0 },
8516     { "vandnpX",        { XM, Vex, EXx }, 0 },
8517     { "vorpX",          { XM, Vex, EXx }, 0 },
8518     { "vxorpX",         { XM, Vex, EXx }, 0 },
8519     /* 58 */
8520     { PREFIX_TABLE (PREFIX_VEX_0F58) },
8521     { PREFIX_TABLE (PREFIX_VEX_0F59) },
8522     { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8523     { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8524     { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8525     { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8526     { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8527     { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8528     /* 60 */
8529     { PREFIX_TABLE (PREFIX_VEX_0F60) },
8530     { PREFIX_TABLE (PREFIX_VEX_0F61) },
8531     { PREFIX_TABLE (PREFIX_VEX_0F62) },
8532     { PREFIX_TABLE (PREFIX_VEX_0F63) },
8533     { PREFIX_TABLE (PREFIX_VEX_0F64) },
8534     { PREFIX_TABLE (PREFIX_VEX_0F65) },
8535     { PREFIX_TABLE (PREFIX_VEX_0F66) },
8536     { PREFIX_TABLE (PREFIX_VEX_0F67) },
8537     /* 68 */
8538     { PREFIX_TABLE (PREFIX_VEX_0F68) },
8539     { PREFIX_TABLE (PREFIX_VEX_0F69) },
8540     { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8541     { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8542     { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8543     { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8544     { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8545     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8546     /* 70 */
8547     { PREFIX_TABLE (PREFIX_VEX_0F70) },
8548     { REG_TABLE (REG_VEX_0F71) },
8549     { REG_TABLE (REG_VEX_0F72) },
8550     { REG_TABLE (REG_VEX_0F73) },
8551     { PREFIX_TABLE (PREFIX_VEX_0F74) },
8552     { PREFIX_TABLE (PREFIX_VEX_0F75) },
8553     { PREFIX_TABLE (PREFIX_VEX_0F76) },
8554     { PREFIX_TABLE (PREFIX_VEX_0F77) },
8555     /* 78 */
8556     { Bad_Opcode },
8557     { Bad_Opcode },
8558     { Bad_Opcode },
8559     { Bad_Opcode },
8560     { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8561     { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8562     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8563     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8564     /* 80 */
8565     { Bad_Opcode },
8566     { Bad_Opcode },
8567     { Bad_Opcode },
8568     { Bad_Opcode },
8569     { Bad_Opcode },
8570     { Bad_Opcode },
8571     { Bad_Opcode },
8572     { Bad_Opcode },
8573     /* 88 */
8574     { Bad_Opcode },
8575     { Bad_Opcode },
8576     { Bad_Opcode },
8577     { Bad_Opcode },
8578     { Bad_Opcode },
8579     { Bad_Opcode },
8580     { Bad_Opcode },
8581     { Bad_Opcode },
8582     /* 90 */
8583     { PREFIX_TABLE (PREFIX_VEX_0F90) },
8584     { PREFIX_TABLE (PREFIX_VEX_0F91) },
8585     { PREFIX_TABLE (PREFIX_VEX_0F92) },
8586     { PREFIX_TABLE (PREFIX_VEX_0F93) },
8587     { Bad_Opcode },
8588     { Bad_Opcode },
8589     { Bad_Opcode },
8590     { Bad_Opcode },
8591     /* 98 */
8592     { PREFIX_TABLE (PREFIX_VEX_0F98) },
8593     { PREFIX_TABLE (PREFIX_VEX_0F99) },
8594     { Bad_Opcode },
8595     { Bad_Opcode },
8596     { Bad_Opcode },
8597     { Bad_Opcode },
8598     { Bad_Opcode },
8599     { Bad_Opcode },
8600     /* a0 */
8601     { Bad_Opcode },
8602     { Bad_Opcode },
8603     { Bad_Opcode },
8604     { Bad_Opcode },
8605     { Bad_Opcode },
8606     { Bad_Opcode },
8607     { Bad_Opcode },
8608     { Bad_Opcode },
8609     /* a8 */
8610     { Bad_Opcode },
8611     { Bad_Opcode },
8612     { Bad_Opcode },
8613     { Bad_Opcode },
8614     { Bad_Opcode },
8615     { Bad_Opcode },
8616     { REG_TABLE (REG_VEX_0FAE) },
8617     { Bad_Opcode },
8618     /* b0 */
8619     { Bad_Opcode },
8620     { Bad_Opcode },
8621     { Bad_Opcode },
8622     { Bad_Opcode },
8623     { Bad_Opcode },
8624     { Bad_Opcode },
8625     { Bad_Opcode },
8626     { Bad_Opcode },
8627     /* b8 */
8628     { Bad_Opcode },
8629     { Bad_Opcode },
8630     { Bad_Opcode },
8631     { Bad_Opcode },
8632     { Bad_Opcode },
8633     { Bad_Opcode },
8634     { Bad_Opcode },
8635     { Bad_Opcode },
8636     /* c0 */
8637     { Bad_Opcode },
8638     { Bad_Opcode },
8639     { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8640     { Bad_Opcode },
8641     { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8642     { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8643     { "vshufpX",        { XM, Vex, EXx, Ib }, 0 },
8644     { Bad_Opcode },
8645     /* c8 */
8646     { Bad_Opcode },
8647     { Bad_Opcode },
8648     { Bad_Opcode },
8649     { Bad_Opcode },
8650     { Bad_Opcode },
8651     { Bad_Opcode },
8652     { Bad_Opcode },
8653     { Bad_Opcode },
8654     /* d0 */
8655     { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8656     { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8657     { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8658     { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8659     { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8660     { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8661     { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8662     { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8663     /* d8 */
8664     { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8665     { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8666     { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8667     { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8668     { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8669     { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8670     { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8671     { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8672     /* e0 */
8673     { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8674     { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8675     { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8676     { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8677     { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8678     { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8679     { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8680     { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8681     /* e8 */
8682     { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8683     { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8684     { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8685     { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8686     { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8687     { PREFIX_TABLE (PREFIX_VEX_0FED) },
8688     { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8689     { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8690     /* f0 */
8691     { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8692     { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8693     { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8694     { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8695     { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8696     { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8697     { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8698     { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8699     /* f8 */
8700     { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8701     { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8702     { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8703     { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8704     { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8705     { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8706     { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8707     { Bad_Opcode },
8708   },
8709   /* VEX_0F38 */
8710   {
8711     /* 00 */
8712     { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8713     { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8714     { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8715     { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8716     { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8717     { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8718     { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8719     { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8720     /* 08 */
8721     { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8722     { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8723     { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8724     { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8725     { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8726     { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8727     { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8728     { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8729     /* 10 */
8730     { Bad_Opcode },
8731     { Bad_Opcode },
8732     { Bad_Opcode },
8733     { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8734     { Bad_Opcode },
8735     { Bad_Opcode },
8736     { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8737     { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8738     /* 18 */
8739     { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8740     { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8741     { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8742     { Bad_Opcode },
8743     { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8744     { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8745     { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8746     { Bad_Opcode },
8747     /* 20 */
8748     { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8749     { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8750     { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8751     { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8752     { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8753     { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8754     { Bad_Opcode },
8755     { Bad_Opcode },
8756     /* 28 */
8757     { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8758     { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8759     { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8760     { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8761     { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8762     { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8763     { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8764     { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8765     /* 30 */
8766     { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8767     { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8768     { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8769     { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8770     { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8771     { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8772     { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8773     { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8774     /* 38 */
8775     { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8776     { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8777     { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8778     { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8779     { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8780     { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8781     { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8782     { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8783     /* 40 */
8784     { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8785     { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8786     { Bad_Opcode },
8787     { Bad_Opcode },
8788     { Bad_Opcode },
8789     { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8790     { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8791     { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8792     /* 48 */
8793     { Bad_Opcode },
8794     { Bad_Opcode },
8795     { Bad_Opcode },
8796     { Bad_Opcode },
8797     { Bad_Opcode },
8798     { Bad_Opcode },
8799     { Bad_Opcode },
8800     { Bad_Opcode },
8801     /* 50 */
8802     { Bad_Opcode },
8803     { Bad_Opcode },
8804     { Bad_Opcode },
8805     { Bad_Opcode },
8806     { Bad_Opcode },
8807     { Bad_Opcode },
8808     { Bad_Opcode },
8809     { Bad_Opcode },
8810     /* 58 */
8811     { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8812     { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8813     { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8814     { Bad_Opcode },
8815     { Bad_Opcode },
8816     { Bad_Opcode },
8817     { Bad_Opcode },
8818     { Bad_Opcode },
8819     /* 60 */
8820     { Bad_Opcode },
8821     { Bad_Opcode },
8822     { Bad_Opcode },
8823     { Bad_Opcode },
8824     { Bad_Opcode },
8825     { Bad_Opcode },
8826     { Bad_Opcode },
8827     { Bad_Opcode },
8828     /* 68 */
8829     { Bad_Opcode },
8830     { Bad_Opcode },
8831     { Bad_Opcode },
8832     { Bad_Opcode },
8833     { Bad_Opcode },
8834     { Bad_Opcode },
8835     { Bad_Opcode },
8836     { Bad_Opcode },
8837     /* 70 */
8838     { Bad_Opcode },
8839     { Bad_Opcode },
8840     { Bad_Opcode },
8841     { Bad_Opcode },
8842     { Bad_Opcode },
8843     { Bad_Opcode },
8844     { Bad_Opcode },
8845     { Bad_Opcode },
8846     /* 78 */
8847     { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8848     { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8849     { Bad_Opcode },
8850     { Bad_Opcode },
8851     { Bad_Opcode },
8852     { Bad_Opcode },
8853     { Bad_Opcode },
8854     { Bad_Opcode },
8855     /* 80 */
8856     { Bad_Opcode },
8857     { Bad_Opcode },
8858     { Bad_Opcode },
8859     { Bad_Opcode },
8860     { Bad_Opcode },
8861     { Bad_Opcode },
8862     { Bad_Opcode },
8863     { Bad_Opcode },
8864     /* 88 */
8865     { Bad_Opcode },
8866     { Bad_Opcode },
8867     { Bad_Opcode },
8868     { Bad_Opcode },
8869     { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8870     { Bad_Opcode },
8871     { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8872     { Bad_Opcode },
8873     /* 90 */
8874     { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8875     { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8876     { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8877     { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8878     { Bad_Opcode },
8879     { Bad_Opcode },
8880     { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8881     { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8882     /* 98 */
8883     { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8884     { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8885     { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8886     { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8887     { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8888     { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8889     { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8890     { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8891     /* a0 */
8892     { Bad_Opcode },
8893     { Bad_Opcode },
8894     { Bad_Opcode },
8895     { Bad_Opcode },
8896     { Bad_Opcode },
8897     { Bad_Opcode },
8898     { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8899     { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8900     /* a8 */
8901     { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8902     { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8903     { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8904     { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8905     { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8906     { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8907     { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8908     { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8909     /* b0 */
8910     { Bad_Opcode },
8911     { Bad_Opcode },
8912     { Bad_Opcode },
8913     { Bad_Opcode },
8914     { Bad_Opcode },
8915     { Bad_Opcode },
8916     { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8917     { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8918     /* b8 */
8919     { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8920     { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8921     { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8922     { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8923     { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8924     { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8925     { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8926     { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8927     /* c0 */
8928     { Bad_Opcode },
8929     { Bad_Opcode },
8930     { Bad_Opcode },
8931     { Bad_Opcode },
8932     { Bad_Opcode },
8933     { Bad_Opcode },
8934     { Bad_Opcode },
8935     { Bad_Opcode },
8936     /* c8 */
8937     { Bad_Opcode },
8938     { Bad_Opcode },
8939     { Bad_Opcode },
8940     { Bad_Opcode },
8941     { Bad_Opcode },
8942     { Bad_Opcode },
8943     { Bad_Opcode },
8944     { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8945     /* d0 */
8946     { Bad_Opcode },
8947     { Bad_Opcode },
8948     { Bad_Opcode },
8949     { Bad_Opcode },
8950     { Bad_Opcode },
8951     { Bad_Opcode },
8952     { Bad_Opcode },
8953     { Bad_Opcode },
8954     /* d8 */
8955     { Bad_Opcode },
8956     { Bad_Opcode },
8957     { Bad_Opcode },
8958     { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8959     { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8960     { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8961     { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8962     { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8963     /* e0 */
8964     { Bad_Opcode },
8965     { Bad_Opcode },
8966     { Bad_Opcode },
8967     { Bad_Opcode },
8968     { Bad_Opcode },
8969     { Bad_Opcode },
8970     { Bad_Opcode },
8971     { Bad_Opcode },
8972     /* e8 */
8973     { Bad_Opcode },
8974     { Bad_Opcode },
8975     { Bad_Opcode },
8976     { Bad_Opcode },
8977     { Bad_Opcode },
8978     { Bad_Opcode },
8979     { Bad_Opcode },
8980     { Bad_Opcode },
8981     /* f0 */
8982     { Bad_Opcode },
8983     { Bad_Opcode },
8984     { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8985     { REG_TABLE (REG_VEX_0F38F3) },
8986     { Bad_Opcode },
8987     { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8988     { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8989     { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8990     /* f8 */
8991     { Bad_Opcode },
8992     { Bad_Opcode },
8993     { Bad_Opcode },
8994     { Bad_Opcode },
8995     { Bad_Opcode },
8996     { Bad_Opcode },
8997     { Bad_Opcode },
8998     { Bad_Opcode },
8999   },
9000   /* VEX_0F3A */
9001   {
9002     /* 00 */
9003     { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9004     { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9005     { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9006     { Bad_Opcode },
9007     { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9008     { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9009     { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9010     { Bad_Opcode },
9011     /* 08 */
9012     { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9013     { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9014     { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9015     { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9016     { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9017     { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9018     { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9019     { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9020     /* 10 */
9021     { Bad_Opcode },
9022     { Bad_Opcode },
9023     { Bad_Opcode },
9024     { Bad_Opcode },
9025     { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9026     { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9027     { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9028     { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9029     /* 18 */
9030     { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9031     { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9032     { Bad_Opcode },
9033     { Bad_Opcode },
9034     { Bad_Opcode },
9035     { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9036     { Bad_Opcode },
9037     { Bad_Opcode },
9038     /* 20 */
9039     { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9040     { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9041     { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9042     { Bad_Opcode },
9043     { Bad_Opcode },
9044     { Bad_Opcode },
9045     { Bad_Opcode },
9046     { Bad_Opcode },
9047     /* 28 */
9048     { Bad_Opcode },
9049     { Bad_Opcode },
9050     { Bad_Opcode },
9051     { Bad_Opcode },
9052     { Bad_Opcode },
9053     { Bad_Opcode },
9054     { Bad_Opcode },
9055     { Bad_Opcode },
9056     /* 30 */
9057     { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9058     { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9059     { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9060     { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9061     { Bad_Opcode },
9062     { Bad_Opcode },
9063     { Bad_Opcode },
9064     { Bad_Opcode },
9065     /* 38 */
9066     { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9067     { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9068     { Bad_Opcode },
9069     { Bad_Opcode },
9070     { Bad_Opcode },
9071     { Bad_Opcode },
9072     { Bad_Opcode },
9073     { Bad_Opcode },
9074     /* 40 */
9075     { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9076     { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9077     { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9078     { Bad_Opcode },
9079     { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9080     { Bad_Opcode },
9081     { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9082     { Bad_Opcode },
9083     /* 48 */
9084     { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9085     { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9086     { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9087     { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9088     { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9089     { Bad_Opcode },
9090     { Bad_Opcode },
9091     { Bad_Opcode },
9092     /* 50 */
9093     { Bad_Opcode },
9094     { Bad_Opcode },
9095     { Bad_Opcode },
9096     { Bad_Opcode },
9097     { Bad_Opcode },
9098     { Bad_Opcode },
9099     { Bad_Opcode },
9100     { Bad_Opcode },
9101     /* 58 */
9102     { Bad_Opcode },
9103     { Bad_Opcode },
9104     { Bad_Opcode },
9105     { Bad_Opcode },
9106     { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9107     { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9108     { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9109     { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9110     /* 60 */
9111     { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9112     { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9113     { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9114     { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9115     { Bad_Opcode },
9116     { Bad_Opcode },
9117     { Bad_Opcode },
9118     { Bad_Opcode },
9119     /* 68 */
9120     { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9121     { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9122     { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9123     { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9124     { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9125     { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9126     { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9127     { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9128     /* 70 */
9129     { Bad_Opcode },
9130     { Bad_Opcode },
9131     { Bad_Opcode },
9132     { Bad_Opcode },
9133     { Bad_Opcode },
9134     { Bad_Opcode },
9135     { Bad_Opcode },
9136     { Bad_Opcode },
9137     /* 78 */
9138     { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9139     { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9140     { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9141     { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9142     { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9143     { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9144     { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9145     { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9146     /* 80 */
9147     { Bad_Opcode },
9148     { Bad_Opcode },
9149     { Bad_Opcode },
9150     { Bad_Opcode },
9151     { Bad_Opcode },
9152     { Bad_Opcode },
9153     { Bad_Opcode },
9154     { Bad_Opcode },
9155     /* 88 */
9156     { Bad_Opcode },
9157     { Bad_Opcode },
9158     { Bad_Opcode },
9159     { Bad_Opcode },
9160     { Bad_Opcode },
9161     { Bad_Opcode },
9162     { Bad_Opcode },
9163     { Bad_Opcode },
9164     /* 90 */
9165     { Bad_Opcode },
9166     { Bad_Opcode },
9167     { Bad_Opcode },
9168     { Bad_Opcode },
9169     { Bad_Opcode },
9170     { Bad_Opcode },
9171     { Bad_Opcode },
9172     { Bad_Opcode },
9173     /* 98 */
9174     { Bad_Opcode },
9175     { Bad_Opcode },
9176     { Bad_Opcode },
9177     { Bad_Opcode },
9178     { Bad_Opcode },
9179     { Bad_Opcode },
9180     { Bad_Opcode },
9181     { Bad_Opcode },
9182     /* a0 */
9183     { Bad_Opcode },
9184     { Bad_Opcode },
9185     { Bad_Opcode },
9186     { Bad_Opcode },
9187     { Bad_Opcode },
9188     { Bad_Opcode },
9189     { Bad_Opcode },
9190     { Bad_Opcode },
9191     /* a8 */
9192     { Bad_Opcode },
9193     { Bad_Opcode },
9194     { Bad_Opcode },
9195     { Bad_Opcode },
9196     { Bad_Opcode },
9197     { Bad_Opcode },
9198     { Bad_Opcode },
9199     { Bad_Opcode },
9200     /* b0 */
9201     { Bad_Opcode },
9202     { Bad_Opcode },
9203     { Bad_Opcode },
9204     { Bad_Opcode },
9205     { Bad_Opcode },
9206     { Bad_Opcode },
9207     { Bad_Opcode },
9208     { Bad_Opcode },
9209     /* b8 */
9210     { Bad_Opcode },
9211     { Bad_Opcode },
9212     { Bad_Opcode },
9213     { Bad_Opcode },
9214     { Bad_Opcode },
9215     { Bad_Opcode },
9216     { Bad_Opcode },
9217     { Bad_Opcode },
9218     /* c0 */
9219     { Bad_Opcode },
9220     { Bad_Opcode },
9221     { Bad_Opcode },
9222     { Bad_Opcode },
9223     { Bad_Opcode },
9224     { Bad_Opcode },
9225     { Bad_Opcode },
9226     { Bad_Opcode },
9227     /* c8 */
9228     { Bad_Opcode },
9229     { Bad_Opcode },
9230     { Bad_Opcode },
9231     { Bad_Opcode },
9232     { Bad_Opcode },
9233     { Bad_Opcode },
9234     { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9235     { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9236     /* d0 */
9237     { Bad_Opcode },
9238     { Bad_Opcode },
9239     { Bad_Opcode },
9240     { Bad_Opcode },
9241     { Bad_Opcode },
9242     { Bad_Opcode },
9243     { Bad_Opcode },
9244     { Bad_Opcode },
9245     /* d8 */
9246     { Bad_Opcode },
9247     { Bad_Opcode },
9248     { Bad_Opcode },
9249     { Bad_Opcode },
9250     { Bad_Opcode },
9251     { Bad_Opcode },
9252     { Bad_Opcode },
9253     { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9254     /* e0 */
9255     { Bad_Opcode },
9256     { Bad_Opcode },
9257     { Bad_Opcode },
9258     { Bad_Opcode },
9259     { Bad_Opcode },
9260     { Bad_Opcode },
9261     { Bad_Opcode },
9262     { Bad_Opcode },
9263     /* e8 */
9264     { Bad_Opcode },
9265     { Bad_Opcode },
9266     { Bad_Opcode },
9267     { Bad_Opcode },
9268     { Bad_Opcode },
9269     { Bad_Opcode },
9270     { Bad_Opcode },
9271     { Bad_Opcode },
9272     /* f0 */
9273     { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9274     { Bad_Opcode },
9275     { Bad_Opcode },
9276     { Bad_Opcode },
9277     { Bad_Opcode },
9278     { Bad_Opcode },
9279     { Bad_Opcode },
9280     { Bad_Opcode },
9281     /* f8 */
9282     { Bad_Opcode },
9283     { Bad_Opcode },
9284     { Bad_Opcode },
9285     { Bad_Opcode },
9286     { Bad_Opcode },
9287     { Bad_Opcode },
9288     { Bad_Opcode },
9289     { Bad_Opcode },
9290   },
9291 };
9292
9293 #include "i386-dis-evex.h"
9294
9295 static const struct dis386 vex_len_table[][2] = {
9296   /* VEX_LEN_0F12_P_0_M_0 */
9297   {
9298     { "vmovlps",        { XM, Vex128, EXq }, 0 },
9299   },
9300
9301   /* VEX_LEN_0F12_P_0_M_1 */
9302   {
9303     { "vmovhlps",       { XM, Vex128, EXq }, 0 },
9304   },
9305
9306   /* VEX_LEN_0F12_P_2 */
9307   {
9308     { "vmovlpd",        { XM, Vex128, EXq }, 0 },
9309   },
9310
9311   /* VEX_LEN_0F13_M_0 */
9312   {
9313     { "vmovlpX",        { EXq, XM }, 0 },
9314   },
9315
9316   /* VEX_LEN_0F16_P_0_M_0 */
9317   {
9318     { "vmovhps",        { XM, Vex128, EXq }, 0 },
9319   },
9320
9321   /* VEX_LEN_0F16_P_0_M_1 */
9322   {
9323     { "vmovlhps",       { XM, Vex128, EXq }, 0 },
9324   },
9325
9326   /* VEX_LEN_0F16_P_2 */
9327   {
9328     { "vmovhpd",        { XM, Vex128, EXq }, 0 },
9329   },
9330
9331   /* VEX_LEN_0F17_M_0 */
9332   {
9333     { "vmovhpX",        { EXq, XM }, 0 },
9334   },
9335
9336   /* VEX_LEN_0F41_P_0 */
9337   {
9338     { Bad_Opcode },
9339     { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9340   },
9341   /* VEX_LEN_0F41_P_2 */
9342   {
9343     { Bad_Opcode },
9344     { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9345   },
9346   /* VEX_LEN_0F42_P_0 */
9347   {
9348     { Bad_Opcode },
9349     { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9350   },
9351   /* VEX_LEN_0F42_P_2 */
9352   {
9353     { Bad_Opcode },
9354     { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9355   },
9356   /* VEX_LEN_0F44_P_0 */
9357   {
9358     { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9359   },
9360   /* VEX_LEN_0F44_P_2 */
9361   {
9362     { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9363   },
9364   /* VEX_LEN_0F45_P_0 */
9365   {
9366     { Bad_Opcode },
9367     { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9368   },
9369   /* VEX_LEN_0F45_P_2 */
9370   {
9371     { Bad_Opcode },
9372     { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9373   },
9374   /* VEX_LEN_0F46_P_0 */
9375   {
9376     { Bad_Opcode },
9377     { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9378   },
9379   /* VEX_LEN_0F46_P_2 */
9380   {
9381     { Bad_Opcode },
9382     { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9383   },
9384   /* VEX_LEN_0F47_P_0 */
9385   {
9386     { Bad_Opcode },
9387     { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9388   },
9389   /* VEX_LEN_0F47_P_2 */
9390   {
9391     { Bad_Opcode },
9392     { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9393   },
9394   /* VEX_LEN_0F4A_P_0 */
9395   {
9396     { Bad_Opcode },
9397     { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9398   },
9399   /* VEX_LEN_0F4A_P_2 */
9400   {
9401     { Bad_Opcode },
9402     { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9403   },
9404   /* VEX_LEN_0F4B_P_0 */
9405   {
9406     { Bad_Opcode },
9407     { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9408   },
9409   /* VEX_LEN_0F4B_P_2 */
9410   {
9411     { Bad_Opcode },
9412     { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9413   },
9414
9415   /* VEX_LEN_0F6E_P_2 */
9416   {
9417     { "vmovK",          { XMScalar, Edq }, 0 },
9418   },
9419
9420   /* VEX_LEN_0F77_P_1 */
9421   {
9422     { "vzeroupper",     { XX }, 0 },
9423     { "vzeroall",       { XX }, 0 },
9424   },
9425
9426   /* VEX_LEN_0F7E_P_1 */
9427   {
9428     { "vmovq",          { XMScalar, EXqScalar }, 0 },
9429   },
9430
9431   /* VEX_LEN_0F7E_P_2 */
9432   {
9433     { "vmovK",          { Edq, XMScalar }, 0 },
9434   },
9435
9436   /* VEX_LEN_0F90_P_0 */
9437   {
9438     { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9439   },
9440
9441   /* VEX_LEN_0F90_P_2 */
9442   {
9443     { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9444   },
9445
9446   /* VEX_LEN_0F91_P_0 */
9447   {
9448     { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9449   },
9450
9451   /* VEX_LEN_0F91_P_2 */
9452   {
9453     { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9454   },
9455
9456   /* VEX_LEN_0F92_P_0 */
9457   {
9458     { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9459   },
9460
9461   /* VEX_LEN_0F92_P_2 */
9462   {
9463     { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9464   },
9465
9466   /* VEX_LEN_0F92_P_3 */
9467   {
9468     { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9469   },
9470
9471   /* VEX_LEN_0F93_P_0 */
9472   {
9473     { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9474   },
9475
9476   /* VEX_LEN_0F93_P_2 */
9477   {
9478     { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9479   },
9480
9481   /* VEX_LEN_0F93_P_3 */
9482   {
9483     { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9484   },
9485
9486   /* VEX_LEN_0F98_P_0 */
9487   {
9488     { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9489   },
9490
9491   /* VEX_LEN_0F98_P_2 */
9492   {
9493     { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9494   },
9495
9496   /* VEX_LEN_0F99_P_0 */
9497   {
9498     { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9499   },
9500
9501   /* VEX_LEN_0F99_P_2 */
9502   {
9503     { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9504   },
9505
9506   /* VEX_LEN_0FAE_R_2_M_0 */
9507   {
9508     { "vldmxcsr",       { Md }, 0 },
9509   },
9510
9511   /* VEX_LEN_0FAE_R_3_M_0 */
9512   {
9513     { "vstmxcsr",       { Md }, 0 },
9514   },
9515
9516   /* VEX_LEN_0FC4_P_2 */
9517   {
9518     { "vpinsrw",        { XM, Vex128, Edqw, Ib }, 0 },
9519   },
9520
9521   /* VEX_LEN_0FC5_P_2 */
9522   {
9523     { "vpextrw",        { Gdq, XS, Ib }, 0 },
9524   },
9525
9526   /* VEX_LEN_0FD6_P_2 */
9527   {
9528     { "vmovq",          { EXqScalarS, XMScalar }, 0 },
9529   },
9530
9531   /* VEX_LEN_0FF7_P_2 */
9532   {
9533     { "vmaskmovdqu",    { XM, XS }, 0 },
9534   },
9535
9536   /* VEX_LEN_0F3816_P_2 */
9537   {
9538     { Bad_Opcode },
9539     { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9540   },
9541
9542   /* VEX_LEN_0F3819_P_2 */
9543   {
9544     { Bad_Opcode },
9545     { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9546   },
9547
9548   /* VEX_LEN_0F381A_P_2_M_0 */
9549   {
9550     { Bad_Opcode },
9551     { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9552   },
9553
9554   /* VEX_LEN_0F3836_P_2 */
9555   {
9556     { Bad_Opcode },
9557     { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9558   },
9559
9560   /* VEX_LEN_0F3841_P_2 */
9561   {
9562     { "vphminposuw",    { XM, EXx }, 0 },
9563   },
9564
9565   /* VEX_LEN_0F385A_P_2_M_0 */
9566   {
9567     { Bad_Opcode },
9568     { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9569   },
9570
9571   /* VEX_LEN_0F38DB_P_2 */
9572   {
9573     { "vaesimc",        { XM, EXx }, 0 },
9574   },
9575
9576   /* VEX_LEN_0F38F2_P_0 */
9577   {
9578     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
9579   },
9580
9581   /* VEX_LEN_0F38F3_R_1_P_0 */
9582   {
9583     { "blsrS",          { VexGdq, Edq }, 0 },
9584   },
9585
9586   /* VEX_LEN_0F38F3_R_2_P_0 */
9587   {
9588     { "blsmskS",        { VexGdq, Edq }, 0 },
9589   },
9590
9591   /* VEX_LEN_0F38F3_R_3_P_0 */
9592   {
9593     { "blsiS",          { VexGdq, Edq }, 0 },
9594   },
9595
9596   /* VEX_LEN_0F38F5_P_0 */
9597   {
9598     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
9599   },
9600
9601   /* VEX_LEN_0F38F5_P_1 */
9602   {
9603     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
9604   },
9605
9606   /* VEX_LEN_0F38F5_P_3 */
9607   {
9608     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
9609   },
9610
9611   /* VEX_LEN_0F38F6_P_3 */
9612   {
9613     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
9614   },
9615
9616   /* VEX_LEN_0F38F7_P_0 */
9617   {
9618     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
9619   },
9620
9621   /* VEX_LEN_0F38F7_P_1 */
9622   {
9623     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
9624   },
9625
9626   /* VEX_LEN_0F38F7_P_2 */
9627   {
9628     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
9629   },
9630
9631   /* VEX_LEN_0F38F7_P_3 */
9632   {
9633     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
9634   },
9635
9636   /* VEX_LEN_0F3A00_P_2 */
9637   {
9638     { Bad_Opcode },
9639     { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9640   },
9641
9642   /* VEX_LEN_0F3A01_P_2 */
9643   {
9644     { Bad_Opcode },
9645     { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9646   },
9647
9648   /* VEX_LEN_0F3A06_P_2 */
9649   {
9650     { Bad_Opcode },
9651     { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9652   },
9653
9654   /* VEX_LEN_0F3A14_P_2 */
9655   {
9656     { "vpextrb",        { Edqb, XM, Ib }, 0 },
9657   },
9658
9659   /* VEX_LEN_0F3A15_P_2 */
9660   {
9661     { "vpextrw",        { Edqw, XM, Ib }, 0 },
9662   },
9663
9664   /* VEX_LEN_0F3A16_P_2  */
9665   {
9666     { "vpextrK",        { Edq, XM, Ib }, 0 },
9667   },
9668
9669   /* VEX_LEN_0F3A17_P_2 */
9670   {
9671     { "vextractps",     { Edqd, XM, Ib }, 0 },
9672   },
9673
9674   /* VEX_LEN_0F3A18_P_2 */
9675   {
9676     { Bad_Opcode },
9677     { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9678   },
9679
9680   /* VEX_LEN_0F3A19_P_2 */
9681   {
9682     { Bad_Opcode },
9683     { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9684   },
9685
9686   /* VEX_LEN_0F3A20_P_2 */
9687   {
9688     { "vpinsrb",        { XM, Vex128, Edqb, Ib }, 0 },
9689   },
9690
9691   /* VEX_LEN_0F3A21_P_2 */
9692   {
9693     { "vinsertps",      { XM, Vex128, EXd, Ib }, 0 },
9694   },
9695
9696   /* VEX_LEN_0F3A22_P_2 */
9697   {
9698     { "vpinsrK",        { XM, Vex128, Edq, Ib }, 0 },
9699   },
9700
9701   /* VEX_LEN_0F3A30_P_2 */
9702   {
9703     { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9704   },
9705
9706   /* VEX_LEN_0F3A31_P_2 */
9707   {
9708     { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9709   },
9710
9711   /* VEX_LEN_0F3A32_P_2 */
9712   {
9713     { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9714   },
9715
9716   /* VEX_LEN_0F3A33_P_2 */
9717   {
9718     { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9719   },
9720
9721   /* VEX_LEN_0F3A38_P_2 */
9722   {
9723     { Bad_Opcode },
9724     { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9725   },
9726
9727   /* VEX_LEN_0F3A39_P_2 */
9728   {
9729     { Bad_Opcode },
9730     { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9731   },
9732
9733   /* VEX_LEN_0F3A41_P_2 */
9734   {
9735     { "vdppd",          { XM, Vex128, EXx, Ib }, 0 },
9736   },
9737
9738   /* VEX_LEN_0F3A46_P_2 */
9739   {
9740     { Bad_Opcode },
9741     { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9742   },
9743
9744   /* VEX_LEN_0F3A60_P_2 */
9745   {
9746     { "vpcmpestrm",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9747   },
9748
9749   /* VEX_LEN_0F3A61_P_2 */
9750   {
9751     { "vpcmpestri",     { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9752   },
9753
9754   /* VEX_LEN_0F3A62_P_2 */
9755   {
9756     { "vpcmpistrm",     { XM, EXx, Ib }, 0 },
9757   },
9758
9759   /* VEX_LEN_0F3A63_P_2 */
9760   {
9761     { "vpcmpistri",     { XM, EXx, Ib }, 0 },
9762   },
9763
9764   /* VEX_LEN_0F3A6A_P_2 */
9765   {
9766     { "vfmaddss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9767   },
9768
9769   /* VEX_LEN_0F3A6B_P_2 */
9770   {
9771     { "vfmaddsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9772   },
9773
9774   /* VEX_LEN_0F3A6E_P_2 */
9775   {
9776     { "vfmsubss",       { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9777   },
9778
9779   /* VEX_LEN_0F3A6F_P_2 */
9780   {
9781     { "vfmsubsd",       { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9782   },
9783
9784   /* VEX_LEN_0F3A7A_P_2 */
9785   {
9786     { "vfnmaddss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9787   },
9788
9789   /* VEX_LEN_0F3A7B_P_2 */
9790   {
9791     { "vfnmaddsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9792   },
9793
9794   /* VEX_LEN_0F3A7E_P_2 */
9795   {
9796     { "vfnmsubss",      { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9797   },
9798
9799   /* VEX_LEN_0F3A7F_P_2 */
9800   {
9801     { "vfnmsubsd",      { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9802   },
9803
9804   /* VEX_LEN_0F3ADF_P_2 */
9805   {
9806     { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9807   },
9808
9809   /* VEX_LEN_0F3AF0_P_3 */
9810   {
9811     { "rorxS",          { Gdq, Edq, Ib }, 0 },
9812   },
9813
9814   /* VEX_LEN_0FXOP_08_CC */
9815   {
9816      { "vpcomb",        { XM, Vex128, EXx, VPCOM }, 0 },
9817   },
9818
9819   /* VEX_LEN_0FXOP_08_CD */
9820   {
9821      { "vpcomw",        { XM, Vex128, EXx, VPCOM }, 0 },
9822   },
9823
9824   /* VEX_LEN_0FXOP_08_CE */
9825   {
9826      { "vpcomd",        { XM, Vex128, EXx, VPCOM }, 0 },
9827   },
9828
9829   /* VEX_LEN_0FXOP_08_CF */
9830   {
9831      { "vpcomq",        { XM, Vex128, EXx, VPCOM }, 0 },
9832   },
9833
9834   /* VEX_LEN_0FXOP_08_EC */
9835   {
9836      { "vpcomub",       { XM, Vex128, EXx, VPCOM }, 0 },
9837   },
9838
9839   /* VEX_LEN_0FXOP_08_ED */
9840   {
9841      { "vpcomuw",       { XM, Vex128, EXx, VPCOM }, 0 },
9842   },
9843
9844   /* VEX_LEN_0FXOP_08_EE */
9845   {
9846      { "vpcomud",       { XM, Vex128, EXx, VPCOM }, 0 },
9847   },
9848
9849   /* VEX_LEN_0FXOP_08_EF */
9850   {
9851      { "vpcomuq",       { XM, Vex128, EXx, VPCOM }, 0 },
9852   },
9853
9854   /* VEX_LEN_0FXOP_09_80 */
9855   {
9856     { "vfrczps",        { XM, EXxmm }, 0 },
9857     { "vfrczps",        { XM, EXymmq }, 0 },
9858   },
9859
9860   /* VEX_LEN_0FXOP_09_81 */
9861   {
9862     { "vfrczpd",        { XM, EXxmm }, 0 },
9863     { "vfrczpd",        { XM, EXymmq }, 0 },
9864   },
9865 };
9866
9867 #include "i386-dis-evex-len.h"
9868
9869 static const struct dis386 vex_w_table[][2] = {
9870   {
9871     /* VEX_W_0F41_P_0_LEN_1 */
9872     { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9873     { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9874   },
9875   {
9876     /* VEX_W_0F41_P_2_LEN_1 */
9877     { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9878     { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9879   },
9880   {
9881     /* VEX_W_0F42_P_0_LEN_1 */
9882     { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9883     { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9884   },
9885   {
9886     /* VEX_W_0F42_P_2_LEN_1 */
9887     { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9888     { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9889   },
9890   {
9891     /* VEX_W_0F44_P_0_LEN_0 */
9892     { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9893     { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9894   },
9895   {
9896     /* VEX_W_0F44_P_2_LEN_0 */
9897     { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9898     { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9899   },
9900   {
9901     /* VEX_W_0F45_P_0_LEN_1 */
9902     { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9903     { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9904   },
9905   {
9906     /* VEX_W_0F45_P_2_LEN_1 */
9907     { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9908     { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9909   },
9910   {
9911     /* VEX_W_0F46_P_0_LEN_1 */
9912     { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9913     { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9914   },
9915   {
9916     /* VEX_W_0F46_P_2_LEN_1 */
9917     { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9918     { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9919   },
9920   {
9921     /* VEX_W_0F47_P_0_LEN_1 */
9922     { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9923     { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9924   },
9925   {
9926     /* VEX_W_0F47_P_2_LEN_1 */
9927     { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9928     { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9929   },
9930   {
9931     /* VEX_W_0F4A_P_0_LEN_1 */
9932     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9933     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9934   },
9935   {
9936     /* VEX_W_0F4A_P_2_LEN_1 */
9937     { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9938     { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9939   },
9940   {
9941     /* VEX_W_0F4B_P_0_LEN_1 */
9942     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9943     { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9944   },
9945   {
9946     /* VEX_W_0F4B_P_2_LEN_1 */
9947     { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9948   },
9949   {
9950     /* VEX_W_0F90_P_0_LEN_0 */
9951     { "kmovw",          { MaskG, MaskE }, 0 },
9952     { "kmovq",          { MaskG, MaskE }, 0 },
9953   },
9954   {
9955     /* VEX_W_0F90_P_2_LEN_0 */
9956     { "kmovb",          { MaskG, MaskBDE }, 0 },
9957     { "kmovd",          { MaskG, MaskBDE }, 0 },
9958   },
9959   {
9960     /* VEX_W_0F91_P_0_LEN_0 */
9961     { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9962     { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9963   },
9964   {
9965     /* VEX_W_0F91_P_2_LEN_0 */
9966     { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9967     { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9968   },
9969   {
9970     /* VEX_W_0F92_P_0_LEN_0 */
9971     { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9972   },
9973   {
9974     /* VEX_W_0F92_P_2_LEN_0 */
9975     { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9976   },
9977   {
9978     /* VEX_W_0F93_P_0_LEN_0 */
9979     { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9980   },
9981   {
9982     /* VEX_W_0F93_P_2_LEN_0 */
9983     { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
9984   },
9985   {
9986     /* VEX_W_0F98_P_0_LEN_0 */
9987     { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
9988     { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
9989   },
9990   {
9991     /* VEX_W_0F98_P_2_LEN_0 */
9992     { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
9993     { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
9994   },
9995   {
9996     /* VEX_W_0F99_P_0_LEN_0 */
9997     { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
9998     { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
9999   },
10000   {
10001     /* VEX_W_0F99_P_2_LEN_0 */
10002     { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10003     { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10004   },
10005   {
10006     /* VEX_W_0F380C_P_2  */
10007     { "vpermilps",      { XM, Vex, EXx }, 0 },
10008   },
10009   {
10010     /* VEX_W_0F380D_P_2  */
10011     { "vpermilpd",      { XM, Vex, EXx }, 0 },
10012   },
10013   {
10014     /* VEX_W_0F380E_P_2  */
10015     { "vtestps",        { XM, EXx }, 0 },
10016   },
10017   {
10018     /* VEX_W_0F380F_P_2  */
10019     { "vtestpd",        { XM, EXx }, 0 },
10020   },
10021   {
10022     /* VEX_W_0F3816_P_2  */
10023     { "vpermps",        { XM, Vex, EXx }, 0 },
10024   },
10025   {
10026     /* VEX_W_0F3818_P_2 */
10027     { "vbroadcastss",   { XM, EXxmm_md }, 0 },
10028   },
10029   {
10030     /* VEX_W_0F3819_P_2 */
10031     { "vbroadcastsd",   { XM, EXxmm_mq }, 0 },
10032   },
10033   {
10034     /* VEX_W_0F381A_P_2_M_0 */
10035     { "vbroadcastf128", { XM, Mxmm }, 0 },
10036   },
10037   {
10038     /* VEX_W_0F382C_P_2_M_0 */
10039     { "vmaskmovps",     { XM, Vex, Mx }, 0 },
10040   },
10041   {
10042     /* VEX_W_0F382D_P_2_M_0 */
10043     { "vmaskmovpd",     { XM, Vex, Mx }, 0 },
10044   },
10045   {
10046     /* VEX_W_0F382E_P_2_M_0 */
10047     { "vmaskmovps",     { Mx, Vex, XM }, 0 },
10048   },
10049   {
10050     /* VEX_W_0F382F_P_2_M_0 */
10051     { "vmaskmovpd",     { Mx, Vex, XM }, 0 },
10052   },
10053   {
10054     /* VEX_W_0F3836_P_2  */
10055     { "vpermd",         { XM, Vex, EXx }, 0 },
10056   },
10057   {
10058     /* VEX_W_0F3846_P_2 */
10059     { "vpsravd",        { XM, Vex, EXx }, 0 },
10060   },
10061   {
10062     /* VEX_W_0F3858_P_2 */
10063     { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10064   },
10065   {
10066     /* VEX_W_0F3859_P_2 */
10067     { "vpbroadcastq",   { XM, EXxmm_mq }, 0 },
10068   },
10069   {
10070     /* VEX_W_0F385A_P_2_M_0 */
10071     { "vbroadcasti128", { XM, Mxmm }, 0 },
10072   },
10073   {
10074     /* VEX_W_0F3878_P_2 */
10075     { "vpbroadcastb",   { XM, EXxmm_mb }, 0 },
10076   },
10077   {
10078     /* VEX_W_0F3879_P_2 */
10079     { "vpbroadcastw",   { XM, EXxmm_mw }, 0 },
10080   },
10081   {
10082     /* VEX_W_0F38CF_P_2 */
10083     { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10084   },
10085   {
10086     /* VEX_W_0F3A00_P_2 */
10087     { Bad_Opcode },
10088     { "vpermq",         { XM, EXx, Ib }, 0 },
10089   },
10090   {
10091     /* VEX_W_0F3A01_P_2 */
10092     { Bad_Opcode },
10093     { "vpermpd",        { XM, EXx, Ib }, 0 },
10094   },
10095   {
10096     /* VEX_W_0F3A02_P_2 */
10097     { "vpblendd",       { XM, Vex, EXx, Ib }, 0 },
10098   },
10099   {
10100     /* VEX_W_0F3A04_P_2 */
10101     { "vpermilps",      { XM, EXx, Ib }, 0 },
10102   },
10103   {
10104     /* VEX_W_0F3A05_P_2 */
10105     { "vpermilpd",      { XM, EXx, Ib }, 0 },
10106   },
10107   {
10108     /* VEX_W_0F3A06_P_2 */
10109     { "vperm2f128",     { XM, Vex256, EXx, Ib }, 0 },
10110   },
10111   {
10112     /* VEX_W_0F3A18_P_2 */
10113     { "vinsertf128",    { XM, Vex256, EXxmm, Ib }, 0 },
10114   },
10115   {
10116     /* VEX_W_0F3A19_P_2 */
10117     { "vextractf128",   { EXxmm, XM, Ib }, 0 },
10118   },
10119   {
10120     /* VEX_W_0F3A30_P_2_LEN_0 */
10121     { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10122     { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10123   },
10124   {
10125     /* VEX_W_0F3A31_P_2_LEN_0 */
10126     { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10127     { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10128   },
10129   {
10130     /* VEX_W_0F3A32_P_2_LEN_0 */
10131     { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10132     { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10133   },
10134   {
10135     /* VEX_W_0F3A33_P_2_LEN_0 */
10136     { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10137     { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10138   },
10139   {
10140     /* VEX_W_0F3A38_P_2 */
10141     { "vinserti128",    { XM, Vex256, EXxmm, Ib }, 0 },
10142   },
10143   {
10144     /* VEX_W_0F3A39_P_2 */
10145     { "vextracti128",   { EXxmm, XM, Ib }, 0 },
10146   },
10147   {
10148     /* VEX_W_0F3A46_P_2 */
10149     { "vperm2i128",     { XM, Vex256, EXx, Ib }, 0 },
10150   },
10151   {
10152     /* VEX_W_0F3A48_P_2 */
10153     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10154     { "vpermil2ps",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10155   },
10156   {
10157     /* VEX_W_0F3A49_P_2 */
10158     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10159     { "vpermil2pd",     { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10160   },
10161   {
10162     /* VEX_W_0F3A4A_P_2 */
10163     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, 0 },
10164   },
10165   {
10166     /* VEX_W_0F3A4B_P_2 */
10167     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, 0 },
10168   },
10169   {
10170     /* VEX_W_0F3A4C_P_2 */
10171     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, 0 },
10172   },
10173   {
10174     /* VEX_W_0F3ACE_P_2 */
10175     { Bad_Opcode },
10176     { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10177   },
10178   {
10179     /* VEX_W_0F3ACF_P_2 */
10180     { Bad_Opcode },
10181     { "vgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, 0 },
10182   },
10183
10184 #include "i386-dis-evex-w.h"
10185 };
10186
10187 static const struct dis386 mod_table[][2] = {
10188   {
10189     /* MOD_8D */
10190     { "leaS",           { Gv, M }, 0 },
10191   },
10192   {
10193     /* MOD_C6_REG_7 */
10194     { Bad_Opcode },
10195     { RM_TABLE (RM_C6_REG_7) },
10196   },
10197   {
10198     /* MOD_C7_REG_7 */
10199     { Bad_Opcode },
10200     { RM_TABLE (RM_C7_REG_7) },
10201   },
10202   {
10203     /* MOD_FF_REG_3 */
10204     { "Jcall^", { indirEp }, 0 },
10205   },
10206   {
10207     /* MOD_FF_REG_5 */
10208     { "Jjmp^", { indirEp }, 0 },
10209   },
10210   {
10211     /* MOD_0F01_REG_0 */
10212     { X86_64_TABLE (X86_64_0F01_REG_0) },
10213     { RM_TABLE (RM_0F01_REG_0) },
10214   },
10215   {
10216     /* MOD_0F01_REG_1 */
10217     { X86_64_TABLE (X86_64_0F01_REG_1) },
10218     { RM_TABLE (RM_0F01_REG_1) },
10219   },
10220   {
10221     /* MOD_0F01_REG_2 */
10222     { X86_64_TABLE (X86_64_0F01_REG_2) },
10223     { RM_TABLE (RM_0F01_REG_2) },
10224   },
10225   {
10226     /* MOD_0F01_REG_3 */
10227     { X86_64_TABLE (X86_64_0F01_REG_3) },
10228     { RM_TABLE (RM_0F01_REG_3) },
10229   },
10230   {
10231     /* MOD_0F01_REG_5 */
10232     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
10233     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
10234   },
10235   {
10236     /* MOD_0F01_REG_7 */
10237     { "invlpg",         { Mb }, 0 },
10238     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
10239   },
10240   {
10241     /* MOD_0F12_PREFIX_0 */
10242     { "movlps",         { XM, EXq }, PREFIX_OPCODE },
10243     { "movhlps",        { XM, EXq }, PREFIX_OPCODE },
10244   },
10245   {
10246     /* MOD_0F13 */
10247     { "movlpX",         { EXq, XM }, PREFIX_OPCODE },
10248   },
10249   {
10250     /* MOD_0F16_PREFIX_0 */
10251     { "movhps",         { XM, EXq }, 0 },
10252     { "movlhps",        { XM, EXq }, 0 },
10253   },
10254   {
10255     /* MOD_0F17 */
10256     { "movhpX",         { EXq, XM }, PREFIX_OPCODE },
10257   },
10258   {
10259     /* MOD_0F18_REG_0 */
10260     { "prefetchnta",    { Mb }, 0 },
10261   },
10262   {
10263     /* MOD_0F18_REG_1 */
10264     { "prefetcht0",     { Mb }, 0 },
10265   },
10266   {
10267     /* MOD_0F18_REG_2 */
10268     { "prefetcht1",     { Mb }, 0 },
10269   },
10270   {
10271     /* MOD_0F18_REG_3 */
10272     { "prefetcht2",     { Mb }, 0 },
10273   },
10274   {
10275     /* MOD_0F18_REG_4 */
10276     { "nop/reserved",   { Mb }, 0 },
10277   },
10278   {
10279     /* MOD_0F18_REG_5 */
10280     { "nop/reserved",   { Mb }, 0 },
10281   },
10282   {
10283     /* MOD_0F18_REG_6 */
10284     { "nop/reserved",   { Mb }, 0 },
10285   },
10286   {
10287     /* MOD_0F18_REG_7 */
10288     { "nop/reserved",   { Mb }, 0 },
10289   },
10290   {
10291     /* MOD_0F1A_PREFIX_0 */
10292     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
10293     { "nopQ",           { Ev }, 0 },
10294   },
10295   {
10296     /* MOD_0F1B_PREFIX_0 */
10297     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
10298     { "nopQ",           { Ev }, 0 },
10299   },
10300   {
10301     /* MOD_0F1B_PREFIX_1 */
10302     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
10303     { "nopQ",           { Ev }, 0 },
10304   },
10305   {
10306     /* MOD_0F1C_PREFIX_0 */
10307     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
10308     { "nopQ",           { Ev }, 0 },
10309   },
10310   {
10311     /* MOD_0F1E_PREFIX_1 */
10312     { "nopQ",           { Ev }, 0 },
10313     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
10314   },
10315   {
10316     /* MOD_0F24 */
10317     { Bad_Opcode },
10318     { "movL",           { Rd, Td }, 0 },
10319   },
10320   {
10321     /* MOD_0F26 */
10322     { Bad_Opcode },
10323     { "movL",           { Td, Rd }, 0 },
10324   },
10325   {
10326     /* MOD_0F2B_PREFIX_0 */
10327     {"movntps",         { Mx, XM }, PREFIX_OPCODE },
10328   },
10329   {
10330     /* MOD_0F2B_PREFIX_1 */
10331     {"movntss",         { Md, XM }, PREFIX_OPCODE },
10332   },
10333   {
10334     /* MOD_0F2B_PREFIX_2 */
10335     {"movntpd",         { Mx, XM }, PREFIX_OPCODE },
10336   },
10337   {
10338     /* MOD_0F2B_PREFIX_3 */
10339     {"movntsd",         { Mq, XM }, PREFIX_OPCODE },
10340   },
10341   {
10342     /* MOD_0F51 */
10343     { Bad_Opcode },
10344     { "movmskpX",       { Gdq, XS }, PREFIX_OPCODE },
10345   },
10346   {
10347     /* MOD_0F71_REG_2 */
10348     { Bad_Opcode },
10349     { "psrlw",          { MS, Ib }, 0 },
10350   },
10351   {
10352     /* MOD_0F71_REG_4 */
10353     { Bad_Opcode },
10354     { "psraw",          { MS, Ib }, 0 },
10355   },
10356   {
10357     /* MOD_0F71_REG_6 */
10358     { Bad_Opcode },
10359     { "psllw",          { MS, Ib }, 0 },
10360   },
10361   {
10362     /* MOD_0F72_REG_2 */
10363     { Bad_Opcode },
10364     { "psrld",          { MS, Ib }, 0 },
10365   },
10366   {
10367     /* MOD_0F72_REG_4 */
10368     { Bad_Opcode },
10369     { "psrad",          { MS, Ib }, 0 },
10370   },
10371   {
10372     /* MOD_0F72_REG_6 */
10373     { Bad_Opcode },
10374     { "pslld",          { MS, Ib }, 0 },
10375   },
10376   {
10377     /* MOD_0F73_REG_2 */
10378     { Bad_Opcode },
10379     { "psrlq",          { MS, Ib }, 0 },
10380   },
10381   {
10382     /* MOD_0F73_REG_3 */
10383     { Bad_Opcode },
10384     { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10385   },
10386   {
10387     /* MOD_0F73_REG_6 */
10388     { Bad_Opcode },
10389     { "psllq",          { MS, Ib }, 0 },
10390   },
10391   {
10392     /* MOD_0F73_REG_7 */
10393     { Bad_Opcode },
10394     { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10395   },
10396   {
10397     /* MOD_0FAE_REG_0 */
10398     { "fxsave",         { FXSAVE }, 0 },
10399     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
10400   },
10401   {
10402     /* MOD_0FAE_REG_1 */
10403     { "fxrstor",        { FXSAVE }, 0 },
10404     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
10405   },
10406   {
10407     /* MOD_0FAE_REG_2 */
10408     { "ldmxcsr",        { Md }, 0 },
10409     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
10410   },
10411   {
10412     /* MOD_0FAE_REG_3 */
10413     { "stmxcsr",        { Md }, 0 },
10414     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
10415   },
10416   {
10417     /* MOD_0FAE_REG_4 */
10418     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
10419     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
10420   },
10421   {
10422     /* MOD_0FAE_REG_5 */
10423     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
10424     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
10425   },
10426   {
10427     /* MOD_0FAE_REG_6 */
10428     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
10429     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
10430   },
10431   {
10432     /* MOD_0FAE_REG_7 */
10433     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
10434     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
10435   },
10436   {
10437     /* MOD_0FB2 */
10438     { "lssS",           { Gv, Mp }, 0 },
10439   },
10440   {
10441     /* MOD_0FB4 */
10442     { "lfsS",           { Gv, Mp }, 0 },
10443   },
10444   {
10445     /* MOD_0FB5 */
10446     { "lgsS",           { Gv, Mp }, 0 },
10447   },
10448   {
10449     /* MOD_0FC3 */
10450     { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
10451   },
10452   {
10453     /* MOD_0FC7_REG_3 */
10454     { "xrstors",        { FXSAVE }, 0 },
10455   },
10456   {
10457     /* MOD_0FC7_REG_4 */
10458     { "xsavec",         { FXSAVE }, 0 },
10459   },
10460   {
10461     /* MOD_0FC7_REG_5 */
10462     { "xsaves",         { FXSAVE }, 0 },
10463   },
10464   {
10465     /* MOD_0FC7_REG_6 */
10466     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
10467     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
10468   },
10469   {
10470     /* MOD_0FC7_REG_7 */
10471     { "vmptrst",        { Mq }, 0 },
10472     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
10473   },
10474   {
10475     /* MOD_0FD7 */
10476     { Bad_Opcode },
10477     { "pmovmskb",       { Gdq, MS }, 0 },
10478   },
10479   {
10480     /* MOD_0FE7_PREFIX_2 */
10481     { "movntdq",        { Mx, XM }, 0 },
10482   },
10483   {
10484     /* MOD_0FF0_PREFIX_3 */
10485     { "lddqu",          { XM, M }, 0 },
10486   },
10487   {
10488     /* MOD_0F382A_PREFIX_2 */
10489     { "movntdqa",       { XM, Mx }, 0 },
10490   },
10491   {
10492     /* MOD_0F38F5_PREFIX_2 */
10493     { "wrussK",         { M, Gdq }, PREFIX_OPCODE },
10494   },
10495   {
10496     /* MOD_0F38F6_PREFIX_0 */
10497     { "wrssK",          { M, Gdq }, PREFIX_OPCODE },
10498   },
10499   {
10500     /* MOD_0F38F8_PREFIX_1 */
10501     { "enqcmds",        { Gva, M }, PREFIX_OPCODE },
10502   },
10503   {
10504     /* MOD_0F38F8_PREFIX_2 */
10505     { "movdir64b",      { Gva, M }, PREFIX_OPCODE },
10506   },
10507   {
10508     /* MOD_0F38F8_PREFIX_3 */
10509     { "enqcmd",         { Gva, M }, PREFIX_OPCODE },
10510   },
10511   {
10512     /* MOD_0F38F9_PREFIX_0 */
10513     { "movdiri",        { Em, Gv }, PREFIX_OPCODE },
10514   },
10515   {
10516     /* MOD_62_32BIT */
10517     { "bound{S|}",      { Gv, Ma }, 0 },
10518     { EVEX_TABLE (EVEX_0F) },
10519   },
10520   {
10521     /* MOD_C4_32BIT */
10522     { "lesS",           { Gv, Mp }, 0 },
10523     { VEX_C4_TABLE (VEX_0F) },
10524   },
10525   {
10526     /* MOD_C5_32BIT */
10527     { "ldsS",           { Gv, Mp }, 0 },
10528     { VEX_C5_TABLE (VEX_0F) },
10529   },
10530   {
10531     /* MOD_VEX_0F12_PREFIX_0 */
10532     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10533     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10534   },
10535   {
10536     /* MOD_VEX_0F13 */
10537     { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10538   },
10539   {
10540     /* MOD_VEX_0F16_PREFIX_0 */
10541     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10542     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10543   },
10544   {
10545     /* MOD_VEX_0F17 */
10546     { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10547   },
10548   {
10549     /* MOD_VEX_0F2B */
10550     { "vmovntpX",       { Mx, XM }, 0 },
10551   },
10552   {
10553     /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10554     { Bad_Opcode },
10555     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
10556   },
10557   {
10558     /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10559     { Bad_Opcode },
10560     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
10561   },
10562   {
10563     /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10564     { Bad_Opcode },
10565     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
10566   },
10567   {
10568     /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10569     { Bad_Opcode },
10570     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
10571   },
10572   {
10573     /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10574     { Bad_Opcode },
10575     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
10576   },
10577   {
10578     /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10579     { Bad_Opcode },
10580     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
10581   },
10582   {
10583     /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10584     { Bad_Opcode },
10585     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
10586   },
10587   {
10588     /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10589     { Bad_Opcode },
10590     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
10591   },
10592   {
10593     /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10594     { Bad_Opcode },
10595     { "knotw",          { MaskG, MaskR }, 0 },
10596   },
10597   {
10598     /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10599     { Bad_Opcode },
10600     { "knotq",          { MaskG, MaskR }, 0 },
10601   },
10602   {
10603     /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10604     { Bad_Opcode },
10605     { "knotb",          { MaskG, MaskR }, 0 },
10606   },
10607   {
10608     /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10609     { Bad_Opcode },
10610     { "knotd",          { MaskG, MaskR }, 0 },
10611   },
10612   {
10613     /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10614     { Bad_Opcode },
10615     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
10616   },
10617   {
10618     /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10619     { Bad_Opcode },
10620     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
10621   },
10622   {
10623     /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10624     { Bad_Opcode },
10625     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
10626   },
10627   {
10628     /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10629     { Bad_Opcode },
10630     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
10631   },
10632  {
10633     /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10634     { Bad_Opcode },
10635     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
10636   },
10637   {
10638     /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10639     { Bad_Opcode },
10640     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
10641   },
10642   {
10643     /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10644     { Bad_Opcode },
10645     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
10646   },
10647   {
10648     /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10649     { Bad_Opcode },
10650     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
10651   },
10652   {
10653     /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10654     { Bad_Opcode },
10655     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
10656   },
10657   {
10658     /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10659     { Bad_Opcode },
10660     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
10661   },
10662   {
10663     /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10664     { Bad_Opcode },
10665     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
10666   },
10667   {
10668     /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10669     { Bad_Opcode },
10670     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
10671   },
10672   {
10673     /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10674     { Bad_Opcode },
10675     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
10676   },
10677   {
10678     /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10679     { Bad_Opcode },
10680     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
10681   },
10682   {
10683     /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10684     { Bad_Opcode },
10685     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
10686   },
10687   {
10688     /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10689     { Bad_Opcode },
10690     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
10691   },
10692   {
10693     /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10694     { Bad_Opcode },
10695     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
10696   },
10697   {
10698     /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10699     { Bad_Opcode },
10700     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
10701   },
10702   {
10703     /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10704     { Bad_Opcode },
10705     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
10706   },
10707   {
10708     /* MOD_VEX_0F50 */
10709     { Bad_Opcode },
10710     { "vmovmskpX",      { Gdq, XS }, 0 },
10711   },
10712   {
10713     /* MOD_VEX_0F71_REG_2 */
10714     { Bad_Opcode },
10715     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10716   },
10717   {
10718     /* MOD_VEX_0F71_REG_4 */
10719     { Bad_Opcode },
10720     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10721   },
10722   {
10723     /* MOD_VEX_0F71_REG_6 */
10724     { Bad_Opcode },
10725     { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10726   },
10727   {
10728     /* MOD_VEX_0F72_REG_2 */
10729     { Bad_Opcode },
10730     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10731   },
10732   {
10733     /* MOD_VEX_0F72_REG_4 */
10734     { Bad_Opcode },
10735     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10736   },
10737   {
10738     /* MOD_VEX_0F72_REG_6 */
10739     { Bad_Opcode },
10740     { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10741   },
10742   {
10743     /* MOD_VEX_0F73_REG_2 */
10744     { Bad_Opcode },
10745     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10746   },
10747   {
10748     /* MOD_VEX_0F73_REG_3 */
10749     { Bad_Opcode },
10750     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10751   },
10752   {
10753     /* MOD_VEX_0F73_REG_6 */
10754     { Bad_Opcode },
10755     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10756   },
10757   {
10758     /* MOD_VEX_0F73_REG_7 */
10759     { Bad_Opcode },
10760     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10761   },
10762   {
10763     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10764     { "kmovw",          { Ew, MaskG }, 0 },
10765     { Bad_Opcode },
10766   },
10767   {
10768     /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10769     { "kmovq",          { Eq, MaskG }, 0 },
10770     { Bad_Opcode },
10771   },
10772   {
10773     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10774     { "kmovb",          { Eb, MaskG }, 0 },
10775     { Bad_Opcode },
10776   },
10777   {
10778     /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10779     { "kmovd",          { Ed, MaskG }, 0 },
10780     { Bad_Opcode },
10781   },
10782   {
10783     /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10784     { Bad_Opcode },
10785     { "kmovw",          { MaskG, Rdq }, 0 },
10786   },
10787   {
10788     /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10789     { Bad_Opcode },
10790     { "kmovb",          { MaskG, Rdq }, 0 },
10791   },
10792   {
10793     /* MOD_VEX_0F92_P_3_LEN_0 */
10794     { Bad_Opcode },
10795     { "kmovK",          { MaskG, Rdq }, 0 },
10796   },
10797   {
10798     /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10799     { Bad_Opcode },
10800     { "kmovw",          { Gdq, MaskR }, 0 },
10801   },
10802   {
10803     /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10804     { Bad_Opcode },
10805     { "kmovb",          { Gdq, MaskR }, 0 },
10806   },
10807   {
10808     /* MOD_VEX_0F93_P_3_LEN_0 */
10809     { Bad_Opcode },
10810     { "kmovK",          { Gdq, MaskR }, 0 },
10811   },
10812   {
10813     /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10814     { Bad_Opcode },
10815     { "kortestw", { MaskG, MaskR }, 0 },
10816   },
10817   {
10818     /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10819     { Bad_Opcode },
10820     { "kortestq", { MaskG, MaskR }, 0 },
10821   },
10822   {
10823     /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10824     { Bad_Opcode },
10825     { "kortestb", { MaskG, MaskR }, 0 },
10826   },
10827   {
10828     /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10829     { Bad_Opcode },
10830     { "kortestd", { MaskG, MaskR }, 0 },
10831   },
10832   {
10833     /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10834     { Bad_Opcode },
10835     { "ktestw", { MaskG, MaskR }, 0 },
10836   },
10837   {
10838     /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10839     { Bad_Opcode },
10840     { "ktestq", { MaskG, MaskR }, 0 },
10841   },
10842   {
10843     /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10844     { Bad_Opcode },
10845     { "ktestb", { MaskG, MaskR }, 0 },
10846   },
10847   {
10848     /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10849     { Bad_Opcode },
10850     { "ktestd", { MaskG, MaskR }, 0 },
10851   },
10852   {
10853     /* MOD_VEX_0FAE_REG_2 */
10854     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10855   },
10856   {
10857     /* MOD_VEX_0FAE_REG_3 */
10858     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10859   },
10860   {
10861     /* MOD_VEX_0FD7_PREFIX_2 */
10862     { Bad_Opcode },
10863     { "vpmovmskb",      { Gdq, XS }, 0 },
10864   },
10865   {
10866     /* MOD_VEX_0FE7_PREFIX_2 */
10867     { "vmovntdq",       { Mx, XM }, 0 },
10868   },
10869   {
10870     /* MOD_VEX_0FF0_PREFIX_3 */
10871     { "vlddqu",         { XM, M }, 0 },
10872   },
10873   {
10874     /* MOD_VEX_0F381A_PREFIX_2 */
10875     { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10876   },
10877   {
10878     /* MOD_VEX_0F382A_PREFIX_2 */
10879     { "vmovntdqa",      { XM, Mx }, 0 },
10880   },
10881   {
10882     /* MOD_VEX_0F382C_PREFIX_2 */
10883     { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10884   },
10885   {
10886     /* MOD_VEX_0F382D_PREFIX_2 */
10887     { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10888   },
10889   {
10890     /* MOD_VEX_0F382E_PREFIX_2 */
10891     { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10892   },
10893   {
10894     /* MOD_VEX_0F382F_PREFIX_2 */
10895     { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10896   },
10897   {
10898     /* MOD_VEX_0F385A_PREFIX_2 */
10899     { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10900   },
10901   {
10902     /* MOD_VEX_0F388C_PREFIX_2 */
10903     { "vpmaskmov%LW",   { XM, Vex, Mx }, 0 },
10904   },
10905   {
10906     /* MOD_VEX_0F388E_PREFIX_2 */
10907     { "vpmaskmov%LW",   { Mx, Vex, XM }, 0 },
10908   },
10909   {
10910     /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10911     { Bad_Opcode },
10912     { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
10913   },
10914   {
10915     /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10916     { Bad_Opcode },
10917     { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
10918   },
10919   {
10920     /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10921     { Bad_Opcode },
10922     { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
10923   },
10924   {
10925     /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10926     { Bad_Opcode },
10927     { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
10928   },
10929   {
10930     /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10931     { Bad_Opcode },
10932     { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
10933   },
10934   {
10935     /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10936     { Bad_Opcode },
10937     { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
10938   },
10939   {
10940     /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10941     { Bad_Opcode },
10942     { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
10943   },
10944   {
10945     /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10946     { Bad_Opcode },
10947     { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
10948   },
10949
10950 #include "i386-dis-evex-mod.h"
10951 };
10952
10953 static const struct dis386 rm_table[][8] = {
10954   {
10955     /* RM_C6_REG_7 */
10956     { "xabort",         { Skip_MODRM, Ib }, 0 },
10957   },
10958   {
10959     /* RM_C7_REG_7 */
10960     { "xbeginT",        { Skip_MODRM, Jv }, 0 },
10961   },
10962   {
10963     /* RM_0F01_REG_0 */
10964     { "enclv",          { Skip_MODRM }, 0 },
10965     { "vmcall",         { Skip_MODRM }, 0 },
10966     { "vmlaunch",       { Skip_MODRM }, 0 },
10967     { "vmresume",       { Skip_MODRM }, 0 },
10968     { "vmxoff",         { Skip_MODRM }, 0 },
10969     { "pconfig",        { Skip_MODRM }, 0 },
10970   },
10971   {
10972     /* RM_0F01_REG_1 */
10973     { "monitor",        { { OP_Monitor, 0 } }, 0 },
10974     { "mwait",          { { OP_Mwait, 0 } }, 0 },
10975     { "clac",           { Skip_MODRM }, 0 },
10976     { "stac",           { Skip_MODRM }, 0 },
10977     { Bad_Opcode },
10978     { Bad_Opcode },
10979     { Bad_Opcode },
10980     { "encls",          { Skip_MODRM }, 0 },
10981   },
10982   {
10983     /* RM_0F01_REG_2 */
10984     { "xgetbv",         { Skip_MODRM }, 0 },
10985     { "xsetbv",         { Skip_MODRM }, 0 },
10986     { Bad_Opcode },
10987     { Bad_Opcode },
10988     { "vmfunc",         { Skip_MODRM }, 0 },
10989     { "xend",           { Skip_MODRM }, 0 },
10990     { "xtest",          { Skip_MODRM }, 0 },
10991     { "enclu",          { Skip_MODRM }, 0 },
10992   },
10993   {
10994     /* RM_0F01_REG_3 */
10995     { "vmrun",          { Skip_MODRM }, 0 },
10996     { "vmmcall",        { Skip_MODRM }, 0 },
10997     { "vmload",         { Skip_MODRM }, 0 },
10998     { "vmsave",         { Skip_MODRM }, 0 },
10999     { "stgi",           { Skip_MODRM }, 0 },
11000     { "clgi",           { Skip_MODRM }, 0 },
11001     { "skinit",         { Skip_MODRM }, 0 },
11002     { "invlpga",        { Skip_MODRM }, 0 },
11003   },
11004   {
11005     /* RM_0F01_REG_5_MOD_3 */
11006     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
11007     { Bad_Opcode },
11008     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
11009     { Bad_Opcode },
11010     { Bad_Opcode },
11011     { Bad_Opcode },
11012     { "rdpkru",         { Skip_MODRM }, 0 },
11013     { "wrpkru",         { Skip_MODRM }, 0 },
11014   },
11015   {
11016     /* RM_0F01_REG_7_MOD_3 */
11017     { "swapgs",         { Skip_MODRM }, 0  },
11018     { "rdtscp",         { Skip_MODRM }, 0  },
11019     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
11020     { "mwaitx",         { { OP_Mwaitx,  0 } }, 0  },
11021     { "clzero",         { Skip_MODRM }, 0  },
11022   },
11023   {
11024     /* RM_0F1E_P_1_MOD_3_REG_7 */
11025     { "nopQ",           { Ev }, 0 },
11026     { "nopQ",           { Ev }, 0 },
11027     { "endbr64",        { Skip_MODRM },  PREFIX_OPCODE },
11028     { "endbr32",        { Skip_MODRM },  PREFIX_OPCODE },
11029     { "nopQ",           { Ev }, 0 },
11030     { "nopQ",           { Ev }, 0 },
11031     { "nopQ",           { Ev }, 0 },
11032     { "nopQ",           { Ev }, 0 },
11033   },
11034   {
11035     /* RM_0FAE_REG_6_MOD_3 */
11036     { "mfence",         { Skip_MODRM }, 0 },
11037   },
11038   {
11039     /* RM_0FAE_REG_7_MOD_3 */
11040     { "sfence",         { Skip_MODRM }, 0 },
11041
11042   },
11043 };
11044
11045 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11046
11047 /* We use the high bit to indicate different name for the same
11048    prefix.  */
11049 #define REP_PREFIX      (0xf3 | 0x100)
11050 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11051 #define XRELEASE_PREFIX (0xf3 | 0x400)
11052 #define BND_PREFIX      (0xf2 | 0x400)
11053 #define NOTRACK_PREFIX  (0x3e | 0x100)
11054
11055 static int
11056 ckprefix (void)
11057 {
11058   int newrex, i, length;
11059   rex = 0;
11060   rex_ignored = 0;
11061   prefixes = 0;
11062   used_prefixes = 0;
11063   rex_used = 0;
11064   last_lock_prefix = -1;
11065   last_repz_prefix = -1;
11066   last_repnz_prefix = -1;
11067   last_data_prefix = -1;
11068   last_addr_prefix = -1;
11069   last_rex_prefix = -1;
11070   last_seg_prefix = -1;
11071   fwait_prefix = -1;
11072   active_seg_prefix = 0;
11073   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11074     all_prefixes[i] = 0;
11075   i = 0;
11076   length = 0;
11077   /* The maximum instruction length is 15bytes.  */
11078   while (length < MAX_CODE_LENGTH - 1)
11079     {
11080       FETCH_DATA (the_info, codep + 1);
11081       newrex = 0;
11082       switch (*codep)
11083         {
11084         /* REX prefixes family.  */
11085         case 0x40:
11086         case 0x41:
11087         case 0x42:
11088         case 0x43:
11089         case 0x44:
11090         case 0x45:
11091         case 0x46:
11092         case 0x47:
11093         case 0x48:
11094         case 0x49:
11095         case 0x4a:
11096         case 0x4b:
11097         case 0x4c:
11098         case 0x4d:
11099         case 0x4e:
11100         case 0x4f:
11101           if (address_mode == mode_64bit)
11102             newrex = *codep;
11103           else
11104             return 1;
11105           last_rex_prefix = i;
11106           break;
11107         case 0xf3:
11108           prefixes |= PREFIX_REPZ;
11109           last_repz_prefix = i;
11110           break;
11111         case 0xf2:
11112           prefixes |= PREFIX_REPNZ;
11113           last_repnz_prefix = i;
11114           break;
11115         case 0xf0:
11116           prefixes |= PREFIX_LOCK;
11117           last_lock_prefix = i;
11118           break;
11119         case 0x2e:
11120           prefixes |= PREFIX_CS;
11121           last_seg_prefix = i;
11122           active_seg_prefix = PREFIX_CS;
11123           break;
11124         case 0x36:
11125           prefixes |= PREFIX_SS;
11126           last_seg_prefix = i;
11127           active_seg_prefix = PREFIX_SS;
11128           break;
11129         case 0x3e:
11130           prefixes |= PREFIX_DS;
11131           last_seg_prefix = i;
11132           active_seg_prefix = PREFIX_DS;
11133           break;
11134         case 0x26:
11135           prefixes |= PREFIX_ES;
11136           last_seg_prefix = i;
11137           active_seg_prefix = PREFIX_ES;
11138           break;
11139         case 0x64:
11140           prefixes |= PREFIX_FS;
11141           last_seg_prefix = i;
11142           active_seg_prefix = PREFIX_FS;
11143           break;
11144         case 0x65:
11145           prefixes |= PREFIX_GS;
11146           last_seg_prefix = i;
11147           active_seg_prefix = PREFIX_GS;
11148           break;
11149         case 0x66:
11150           prefixes |= PREFIX_DATA;
11151           last_data_prefix = i;
11152           break;
11153         case 0x67:
11154           prefixes |= PREFIX_ADDR;
11155           last_addr_prefix = i;
11156           break;
11157         case FWAIT_OPCODE:
11158           /* fwait is really an instruction.  If there are prefixes
11159              before the fwait, they belong to the fwait, *not* to the
11160              following instruction.  */
11161           fwait_prefix = i;
11162           if (prefixes || rex)
11163             {
11164               prefixes |= PREFIX_FWAIT;
11165               codep++;
11166               /* This ensures that the previous REX prefixes are noticed
11167                  as unused prefixes, as in the return case below.  */
11168               rex_used = rex;
11169               return 1;
11170             }
11171           prefixes = PREFIX_FWAIT;
11172           break;
11173         default:
11174           return 1;
11175         }
11176       /* Rex is ignored when followed by another prefix.  */
11177       if (rex)
11178         {
11179           rex_used = rex;
11180           return 1;
11181         }
11182       if (*codep != FWAIT_OPCODE)
11183         all_prefixes[i++] = *codep;
11184       rex = newrex;
11185       codep++;
11186       length++;
11187     }
11188   return 0;
11189 }
11190
11191 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11192    prefix byte.  */
11193
11194 static const char *
11195 prefix_name (int pref, int sizeflag)
11196 {
11197   static const char *rexes [16] =
11198     {
11199       "rex",            /* 0x40 */
11200       "rex.B",          /* 0x41 */
11201       "rex.X",          /* 0x42 */
11202       "rex.XB",         /* 0x43 */
11203       "rex.R",          /* 0x44 */
11204       "rex.RB",         /* 0x45 */
11205       "rex.RX",         /* 0x46 */
11206       "rex.RXB",        /* 0x47 */
11207       "rex.W",          /* 0x48 */
11208       "rex.WB",         /* 0x49 */
11209       "rex.WX",         /* 0x4a */
11210       "rex.WXB",        /* 0x4b */
11211       "rex.WR",         /* 0x4c */
11212       "rex.WRB",        /* 0x4d */
11213       "rex.WRX",        /* 0x4e */
11214       "rex.WRXB",       /* 0x4f */
11215     };
11216
11217   switch (pref)
11218     {
11219     /* REX prefixes family.  */
11220     case 0x40:
11221     case 0x41:
11222     case 0x42:
11223     case 0x43:
11224     case 0x44:
11225     case 0x45:
11226     case 0x46:
11227     case 0x47:
11228     case 0x48:
11229     case 0x49:
11230     case 0x4a:
11231     case 0x4b:
11232     case 0x4c:
11233     case 0x4d:
11234     case 0x4e:
11235     case 0x4f:
11236       return rexes [pref - 0x40];
11237     case 0xf3:
11238       return "repz";
11239     case 0xf2:
11240       return "repnz";
11241     case 0xf0:
11242       return "lock";
11243     case 0x2e:
11244       return "cs";
11245     case 0x36:
11246       return "ss";
11247     case 0x3e:
11248       return "ds";
11249     case 0x26:
11250       return "es";
11251     case 0x64:
11252       return "fs";
11253     case 0x65:
11254       return "gs";
11255     case 0x66:
11256       return (sizeflag & DFLAG) ? "data16" : "data32";
11257     case 0x67:
11258       if (address_mode == mode_64bit)
11259         return (sizeflag & AFLAG) ? "addr32" : "addr64";
11260       else
11261         return (sizeflag & AFLAG) ? "addr16" : "addr32";
11262     case FWAIT_OPCODE:
11263       return "fwait";
11264     case REP_PREFIX:
11265       return "rep";
11266     case XACQUIRE_PREFIX:
11267       return "xacquire";
11268     case XRELEASE_PREFIX:
11269       return "xrelease";
11270     case BND_PREFIX:
11271       return "bnd";
11272     case NOTRACK_PREFIX:
11273       return "notrack";
11274     default:
11275       return NULL;
11276     }
11277 }
11278
11279 static char op_out[MAX_OPERANDS][100];
11280 static int op_ad, op_index[MAX_OPERANDS];
11281 static int two_source_ops;
11282 static bfd_vma op_address[MAX_OPERANDS];
11283 static bfd_vma op_riprel[MAX_OPERANDS];
11284 static bfd_vma start_pc;
11285
11286 /*
11287  *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11288  *   (see topic "Redundant prefixes" in the "Differences from 8086"
11289  *   section of the "Virtual 8086 Mode" chapter.)
11290  * 'pc' should be the address of this instruction, it will
11291  *   be used to print the target address if this is a relative jump or call
11292  * The function returns the length of this instruction in bytes.
11293  */
11294
11295 static char intel_syntax;
11296 static char intel_mnemonic = !SYSV386_COMPAT;
11297 static char open_char;
11298 static char close_char;
11299 static char separator_char;
11300 static char scale_char;
11301
11302 enum x86_64_isa
11303 {
11304   amd64 = 0,
11305   intel64
11306 };
11307
11308 static enum x86_64_isa isa64;
11309
11310 /* Here for backwards compatibility.  When gdb stops using
11311    print_insn_i386_att and print_insn_i386_intel these functions can
11312    disappear, and print_insn_i386 be merged into print_insn.  */
11313 int
11314 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11315 {
11316   intel_syntax = 0;
11317
11318   return print_insn (pc, info);
11319 }
11320
11321 int
11322 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11323 {
11324   intel_syntax = 1;
11325
11326   return print_insn (pc, info);
11327 }
11328
11329 int
11330 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11331 {
11332   intel_syntax = -1;
11333
11334   return print_insn (pc, info);
11335 }
11336
11337 void
11338 print_i386_disassembler_options (FILE *stream)
11339 {
11340   fprintf (stream, _("\n\
11341 The following i386/x86-64 specific disassembler options are supported for use\n\
11342 with the -M switch (multiple options should be separated by commas):\n"));
11343
11344   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
11345   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
11346   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
11347   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
11348   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
11349   fprintf (stream, _("  att-mnemonic\n"
11350                      "              Display instruction in AT&T mnemonic\n"));
11351   fprintf (stream, _("  intel-mnemonic\n"
11352                      "              Display instruction in Intel mnemonic\n"));
11353   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
11354   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
11355   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
11356   fprintf (stream, _("  data32      Assume 32bit data size\n"));
11357   fprintf (stream, _("  data16      Assume 16bit data size\n"));
11358   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
11359   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
11360   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
11361 }
11362
11363 /* Bad opcode.  */
11364 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11365
11366 /* Get a pointer to struct dis386 with a valid name.  */
11367
11368 static const struct dis386 *
11369 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11370 {
11371   int vindex, vex_table_index;
11372
11373   if (dp->name != NULL)
11374     return dp;
11375
11376   switch (dp->op[0].bytemode)
11377     {
11378     case USE_REG_TABLE:
11379       dp = &reg_table[dp->op[1].bytemode][modrm.reg];
11380       break;
11381
11382     case USE_MOD_TABLE:
11383       vindex = modrm.mod == 0x3 ? 1 : 0;
11384       dp = &mod_table[dp->op[1].bytemode][vindex];
11385       break;
11386
11387     case USE_RM_TABLE:
11388       dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11389       break;
11390
11391     case USE_PREFIX_TABLE:
11392       if (need_vex)
11393         {
11394           /* The prefix in VEX is implicit.  */
11395           switch (vex.prefix)
11396             {
11397             case 0:
11398               vindex = 0;
11399               break;
11400             case REPE_PREFIX_OPCODE:
11401               vindex = 1;
11402               break;
11403             case DATA_PREFIX_OPCODE:
11404               vindex = 2;
11405               break;
11406             case REPNE_PREFIX_OPCODE:
11407               vindex = 3;
11408               break;
11409             default:
11410               abort ();
11411               break;
11412             }
11413         }
11414       else
11415         {
11416           int last_prefix = -1;
11417           int prefix = 0;
11418           vindex = 0;
11419           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11420              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11421              last one wins.  */
11422           if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11423             {
11424               if (last_repz_prefix > last_repnz_prefix)
11425                 {
11426                   vindex = 1;
11427                   prefix = PREFIX_REPZ;
11428                   last_prefix = last_repz_prefix;
11429                 }
11430               else
11431                 {
11432                   vindex = 3;
11433                   prefix = PREFIX_REPNZ;
11434                   last_prefix = last_repnz_prefix;
11435                 }
11436
11437               /* Check if prefix should be ignored.  */
11438               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11439                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11440                    & prefix) != 0)
11441                 vindex = 0;
11442             }
11443
11444           if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11445             {
11446               vindex = 2;
11447               prefix = PREFIX_DATA;
11448               last_prefix = last_data_prefix;
11449             }
11450
11451           if (vindex != 0)
11452             {
11453               used_prefixes |= prefix;
11454               all_prefixes[last_prefix] = 0;
11455             }
11456         }
11457       dp = &prefix_table[dp->op[1].bytemode][vindex];
11458       break;
11459
11460     case USE_X86_64_TABLE:
11461       vindex = address_mode == mode_64bit ? 1 : 0;
11462       dp = &x86_64_table[dp->op[1].bytemode][vindex];
11463       break;
11464
11465     case USE_3BYTE_TABLE:
11466       FETCH_DATA (info, codep + 2);
11467       vindex = *codep++;
11468       dp = &three_byte_table[dp->op[1].bytemode][vindex];
11469       end_codep = codep;
11470       modrm.mod = (*codep >> 6) & 3;
11471       modrm.reg = (*codep >> 3) & 7;
11472       modrm.rm = *codep & 7;
11473       break;
11474
11475     case USE_VEX_LEN_TABLE:
11476       if (!need_vex)
11477         abort ();
11478
11479       switch (vex.length)
11480         {
11481         case 128:
11482           vindex = 0;
11483           break;
11484         case 256:
11485           vindex = 1;
11486           break;
11487         default:
11488           abort ();
11489           break;
11490         }
11491
11492       dp = &vex_len_table[dp->op[1].bytemode][vindex];
11493       break;
11494
11495     case USE_EVEX_LEN_TABLE:
11496       if (!vex.evex)
11497         abort ();
11498
11499       switch (vex.length)
11500         {
11501         case 128:
11502           vindex = 0;
11503           break;
11504         case 256:
11505           vindex = 1;
11506           break;
11507         case 512:
11508           vindex = 2;
11509           break;
11510         default:
11511           abort ();
11512           break;
11513         }
11514
11515       dp = &evex_len_table[dp->op[1].bytemode][vindex];
11516       break;
11517
11518     case USE_XOP_8F_TABLE:
11519       FETCH_DATA (info, codep + 3);
11520       /* All bits in the REX prefix are ignored.  */
11521       rex_ignored = rex;
11522       rex = ~(*codep >> 5) & 0x7;
11523
11524       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
11525       switch ((*codep & 0x1f))
11526         {
11527         default:
11528           dp = &bad_opcode;
11529           return dp;
11530         case 0x8:
11531           vex_table_index = XOP_08;
11532           break;
11533         case 0x9:
11534           vex_table_index = XOP_09;
11535           break;
11536         case 0xa:
11537           vex_table_index = XOP_0A;
11538           break;
11539         }
11540       codep++;
11541       vex.w = *codep & 0x80;
11542       if (vex.w && address_mode == mode_64bit)
11543         rex |= REX_W;
11544
11545       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11546       if (address_mode != mode_64bit)
11547         {
11548           /* In 16/32-bit mode REX_B is silently ignored.  */
11549           rex &= ~REX_B;
11550         }
11551
11552       vex.length = (*codep & 0x4) ? 256 : 128;
11553       switch ((*codep & 0x3))
11554         {
11555         case 0:
11556           break;
11557         case 1:
11558           vex.prefix = DATA_PREFIX_OPCODE;
11559           break;
11560         case 2:
11561           vex.prefix = REPE_PREFIX_OPCODE;
11562           break;
11563         case 3:
11564           vex.prefix = REPNE_PREFIX_OPCODE;
11565           break;
11566         }
11567       need_vex = 1;
11568       need_vex_reg = 1;
11569       codep++;
11570       vindex = *codep++;
11571       dp = &xop_table[vex_table_index][vindex];
11572
11573       end_codep = codep;
11574       FETCH_DATA (info, codep + 1);
11575       modrm.mod = (*codep >> 6) & 3;
11576       modrm.reg = (*codep >> 3) & 7;
11577       modrm.rm = *codep & 7;
11578       break;
11579
11580     case USE_VEX_C4_TABLE:
11581       /* VEX prefix.  */
11582       FETCH_DATA (info, codep + 3);
11583       /* All bits in the REX prefix are ignored.  */
11584       rex_ignored = rex;
11585       rex = ~(*codep >> 5) & 0x7;
11586       switch ((*codep & 0x1f))
11587         {
11588         default:
11589           dp = &bad_opcode;
11590           return dp;
11591         case 0x1:
11592           vex_table_index = VEX_0F;
11593           break;
11594         case 0x2:
11595           vex_table_index = VEX_0F38;
11596           break;
11597         case 0x3:
11598           vex_table_index = VEX_0F3A;
11599           break;
11600         }
11601       codep++;
11602       vex.w = *codep & 0x80;
11603       if (address_mode == mode_64bit)
11604         {
11605           if (vex.w)
11606             rex |= REX_W;
11607         }
11608       else
11609         {
11610           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11611              is ignored, other REX bits are 0 and the highest bit in
11612              VEX.vvvv is also ignored (but we mustn't clear it here).  */
11613           rex = 0;
11614         }
11615       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11616       vex.length = (*codep & 0x4) ? 256 : 128;
11617       switch ((*codep & 0x3))
11618         {
11619         case 0:
11620           break;
11621         case 1:
11622           vex.prefix = DATA_PREFIX_OPCODE;
11623           break;
11624         case 2:
11625           vex.prefix = REPE_PREFIX_OPCODE;
11626           break;
11627         case 3:
11628           vex.prefix = REPNE_PREFIX_OPCODE;
11629           break;
11630         }
11631       need_vex = 1;
11632       need_vex_reg = 1;
11633       codep++;
11634       vindex = *codep++;
11635       dp = &vex_table[vex_table_index][vindex];
11636       end_codep = codep;
11637       /* There is no MODRM byte for VEX0F 77.  */
11638       if (vex_table_index != VEX_0F || vindex != 0x77)
11639         {
11640           FETCH_DATA (info, codep + 1);
11641           modrm.mod = (*codep >> 6) & 3;
11642           modrm.reg = (*codep >> 3) & 7;
11643           modrm.rm = *codep & 7;
11644         }
11645       break;
11646
11647     case USE_VEX_C5_TABLE:
11648       /* VEX prefix.  */
11649       FETCH_DATA (info, codep + 2);
11650       /* All bits in the REX prefix are ignored.  */
11651       rex_ignored = rex;
11652       rex = (*codep & 0x80) ? 0 : REX_R;
11653
11654       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11655          VEX.vvvv is 1.  */
11656       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11657       vex.length = (*codep & 0x4) ? 256 : 128;
11658       switch ((*codep & 0x3))
11659         {
11660         case 0:
11661           break;
11662         case 1:
11663           vex.prefix = DATA_PREFIX_OPCODE;
11664           break;
11665         case 2:
11666           vex.prefix = REPE_PREFIX_OPCODE;
11667           break;
11668         case 3:
11669           vex.prefix = REPNE_PREFIX_OPCODE;
11670           break;
11671         }
11672       need_vex = 1;
11673       need_vex_reg = 1;
11674       codep++;
11675       vindex = *codep++;
11676       dp = &vex_table[dp->op[1].bytemode][vindex];
11677       end_codep = codep;
11678       /* There is no MODRM byte for VEX 77.  */
11679       if (vindex != 0x77)
11680         {
11681           FETCH_DATA (info, codep + 1);
11682           modrm.mod = (*codep >> 6) & 3;
11683           modrm.reg = (*codep >> 3) & 7;
11684           modrm.rm = *codep & 7;
11685         }
11686       break;
11687
11688     case USE_VEX_W_TABLE:
11689       if (!need_vex)
11690         abort ();
11691
11692       dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11693       break;
11694
11695     case USE_EVEX_TABLE:
11696       two_source_ops = 0;
11697       /* EVEX prefix.  */
11698       vex.evex = 1;
11699       FETCH_DATA (info, codep + 4);
11700       /* All bits in the REX prefix are ignored.  */
11701       rex_ignored = rex;
11702       /* The first byte after 0x62.  */
11703       rex = ~(*codep >> 5) & 0x7;
11704       vex.r = *codep & 0x10;
11705       switch ((*codep & 0xf))
11706         {
11707         default:
11708           return &bad_opcode;
11709         case 0x1:
11710           vex_table_index = EVEX_0F;
11711           break;
11712         case 0x2:
11713           vex_table_index = EVEX_0F38;
11714           break;
11715         case 0x3:
11716           vex_table_index = EVEX_0F3A;
11717           break;
11718         }
11719
11720       /* The second byte after 0x62.  */
11721       codep++;
11722       vex.w = *codep & 0x80;
11723       if (vex.w && address_mode == mode_64bit)
11724         rex |= REX_W;
11725
11726       vex.register_specifier = (~(*codep >> 3)) & 0xf;
11727
11728       /* The U bit.  */
11729       if (!(*codep & 0x4))
11730         return &bad_opcode;
11731
11732       switch ((*codep & 0x3))
11733         {
11734         case 0:
11735           break;
11736         case 1:
11737           vex.prefix = DATA_PREFIX_OPCODE;
11738           break;
11739         case 2:
11740           vex.prefix = REPE_PREFIX_OPCODE;
11741           break;
11742         case 3:
11743           vex.prefix = REPNE_PREFIX_OPCODE;
11744           break;
11745         }
11746
11747       /* The third byte after 0x62.  */
11748       codep++;
11749
11750       /* Remember the static rounding bits.  */
11751       vex.ll = (*codep >> 5) & 3;
11752       vex.b = (*codep & 0x10) != 0;
11753
11754       vex.v = *codep & 0x8;
11755       vex.mask_register_specifier = *codep & 0x7;
11756       vex.zeroing = *codep & 0x80;
11757
11758       if (address_mode != mode_64bit)
11759         {
11760           /* In 16/32-bit mode silently ignore following bits.  */
11761           rex &= ~REX_B;
11762           vex.r = 1;
11763           vex.v = 1;
11764         }
11765
11766       need_vex = 1;
11767       need_vex_reg = 1;
11768       codep++;
11769       vindex = *codep++;
11770       dp = &evex_table[vex_table_index][vindex];
11771       end_codep = codep;
11772       FETCH_DATA (info, codep + 1);
11773       modrm.mod = (*codep >> 6) & 3;
11774       modrm.reg = (*codep >> 3) & 7;
11775       modrm.rm = *codep & 7;
11776
11777       /* Set vector length.  */
11778       if (modrm.mod == 3 && vex.b)
11779         vex.length = 512;
11780       else
11781         {
11782           switch (vex.ll)
11783             {
11784             case 0x0:
11785               vex.length = 128;
11786               break;
11787             case 0x1:
11788               vex.length = 256;
11789               break;
11790             case 0x2:
11791               vex.length = 512;
11792               break;
11793             default:
11794               return &bad_opcode;
11795             }
11796         }
11797       break;
11798
11799     case 0:
11800       dp = &bad_opcode;
11801       break;
11802
11803     default:
11804       abort ();
11805     }
11806
11807   if (dp->name != NULL)
11808     return dp;
11809   else
11810     return get_valid_dis386 (dp, info);
11811 }
11812
11813 static void
11814 get_sib (disassemble_info *info, int sizeflag)
11815 {
11816   /* If modrm.mod == 3, operand must be register.  */
11817   if (need_modrm
11818       && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11819       && modrm.mod != 3
11820       && modrm.rm == 4)
11821     {
11822       FETCH_DATA (info, codep + 2);
11823       sib.index = (codep [1] >> 3) & 7;
11824       sib.scale = (codep [1] >> 6) & 3;
11825       sib.base = codep [1] & 7;
11826     }
11827 }
11828
11829 static int
11830 print_insn (bfd_vma pc, disassemble_info *info)
11831 {
11832   const struct dis386 *dp;
11833   int i;
11834   char *op_txt[MAX_OPERANDS];
11835   int needcomma;
11836   int sizeflag, orig_sizeflag;
11837   const char *p;
11838   struct dis_private priv;
11839   int prefix_length;
11840
11841   priv.orig_sizeflag = AFLAG | DFLAG;
11842   if ((info->mach & bfd_mach_i386_i386) != 0)
11843     address_mode = mode_32bit;
11844   else if (info->mach == bfd_mach_i386_i8086)
11845     {
11846       address_mode = mode_16bit;
11847       priv.orig_sizeflag = 0;
11848     }
11849   else
11850     address_mode = mode_64bit;
11851
11852   if (intel_syntax == (char) -1)
11853     intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11854
11855   for (p = info->disassembler_options; p != NULL; )
11856     {
11857       if (CONST_STRNEQ (p, "amd64"))
11858         isa64 = amd64;
11859       else if (CONST_STRNEQ (p, "intel64"))
11860         isa64 = intel64;
11861       else if (CONST_STRNEQ (p, "x86-64"))
11862         {
11863           address_mode = mode_64bit;
11864           priv.orig_sizeflag = AFLAG | DFLAG;
11865         }
11866       else if (CONST_STRNEQ (p, "i386"))
11867         {
11868           address_mode = mode_32bit;
11869           priv.orig_sizeflag = AFLAG | DFLAG;
11870         }
11871       else if (CONST_STRNEQ (p, "i8086"))
11872         {
11873           address_mode = mode_16bit;
11874           priv.orig_sizeflag = 0;
11875         }
11876       else if (CONST_STRNEQ (p, "intel"))
11877         {
11878           intel_syntax = 1;
11879           if (CONST_STRNEQ (p + 5, "-mnemonic"))
11880             intel_mnemonic = 1;
11881         }
11882       else if (CONST_STRNEQ (p, "att"))
11883         {
11884           intel_syntax = 0;
11885           if (CONST_STRNEQ (p + 3, "-mnemonic"))
11886             intel_mnemonic = 0;
11887         }
11888       else if (CONST_STRNEQ (p, "addr"))
11889         {
11890           if (address_mode == mode_64bit)
11891             {
11892               if (p[4] == '3' && p[5] == '2')
11893                 priv.orig_sizeflag &= ~AFLAG;
11894               else if (p[4] == '6' && p[5] == '4')
11895                 priv.orig_sizeflag |= AFLAG;
11896             }
11897           else
11898             {
11899               if (p[4] == '1' && p[5] == '6')
11900                 priv.orig_sizeflag &= ~AFLAG;
11901               else if (p[4] == '3' && p[5] == '2')
11902                 priv.orig_sizeflag |= AFLAG;
11903             }
11904         }
11905       else if (CONST_STRNEQ (p, "data"))
11906         {
11907           if (p[4] == '1' && p[5] == '6')
11908             priv.orig_sizeflag &= ~DFLAG;
11909           else if (p[4] == '3' && p[5] == '2')
11910             priv.orig_sizeflag |= DFLAG;
11911         }
11912       else if (CONST_STRNEQ (p, "suffix"))
11913         priv.orig_sizeflag |= SUFFIX_ALWAYS;
11914
11915       p = strchr (p, ',');
11916       if (p != NULL)
11917         p++;
11918     }
11919
11920   if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11921     {
11922       (*info->fprintf_func) (info->stream,
11923                              _("64-bit address is disabled"));
11924       return -1;
11925     }
11926
11927   if (intel_syntax)
11928     {
11929       names64 = intel_names64;
11930       names32 = intel_names32;
11931       names16 = intel_names16;
11932       names8 = intel_names8;
11933       names8rex = intel_names8rex;
11934       names_seg = intel_names_seg;
11935       names_mm = intel_names_mm;
11936       names_bnd = intel_names_bnd;
11937       names_xmm = intel_names_xmm;
11938       names_ymm = intel_names_ymm;
11939       names_zmm = intel_names_zmm;
11940       index64 = intel_index64;
11941       index32 = intel_index32;
11942       names_mask = intel_names_mask;
11943       index16 = intel_index16;
11944       open_char = '[';
11945       close_char = ']';
11946       separator_char = '+';
11947       scale_char = '*';
11948     }
11949   else
11950     {
11951       names64 = att_names64;
11952       names32 = att_names32;
11953       names16 = att_names16;
11954       names8 = att_names8;
11955       names8rex = att_names8rex;
11956       names_seg = att_names_seg;
11957       names_mm = att_names_mm;
11958       names_bnd = att_names_bnd;
11959       names_xmm = att_names_xmm;
11960       names_ymm = att_names_ymm;
11961       names_zmm = att_names_zmm;
11962       index64 = att_index64;
11963       index32 = att_index32;
11964       names_mask = att_names_mask;
11965       index16 = att_index16;
11966       open_char = '(';
11967       close_char =  ')';
11968       separator_char = ',';
11969       scale_char = ',';
11970     }
11971
11972   /* The output looks better if we put 7 bytes on a line, since that
11973      puts most long word instructions on a single line.  Use 8 bytes
11974      for Intel L1OM.  */
11975   if ((info->mach & bfd_mach_l1om) != 0)
11976     info->bytes_per_line = 8;
11977   else
11978     info->bytes_per_line = 7;
11979
11980   info->private_data = &priv;
11981   priv.max_fetched = priv.the_buffer;
11982   priv.insn_start = pc;
11983
11984   obuf[0] = 0;
11985   for (i = 0; i < MAX_OPERANDS; ++i)
11986     {
11987       op_out[i][0] = 0;
11988       op_index[i] = -1;
11989     }
11990
11991   the_info = info;
11992   start_pc = pc;
11993   start_codep = priv.the_buffer;
11994   codep = priv.the_buffer;
11995
11996   if (OPCODES_SIGSETJMP (priv.bailout) != 0)
11997     {
11998       const char *name;
11999
12000       /* Getting here means we tried for data but didn't get it.  That
12001          means we have an incomplete instruction of some sort.  Just
12002          print the first byte as a prefix or a .byte pseudo-op.  */
12003       if (codep > priv.the_buffer)
12004         {
12005           name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12006           if (name != NULL)
12007             (*info->fprintf_func) (info->stream, "%s", name);
12008           else
12009             {
12010               /* Just print the first byte as a .byte instruction.  */
12011               (*info->fprintf_func) (info->stream, ".byte 0x%x",
12012                                      (unsigned int) priv.the_buffer[0]);
12013             }
12014
12015           return 1;
12016         }
12017
12018       return -1;
12019     }
12020
12021   obufp = obuf;
12022   sizeflag = priv.orig_sizeflag;
12023
12024   if (!ckprefix () || rex_used)
12025     {
12026       /* Too many prefixes or unused REX prefixes.  */
12027       for (i = 0;
12028            i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12029            i++)
12030         (*info->fprintf_func) (info->stream, "%s%s",
12031                                i == 0 ? "" : " ",
12032                                prefix_name (all_prefixes[i], sizeflag));
12033       return i;
12034     }
12035
12036   insn_codep = codep;
12037
12038   FETCH_DATA (info, codep + 1);
12039   two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12040
12041   if (((prefixes & PREFIX_FWAIT)
12042        && ((*codep < 0xd8) || (*codep > 0xdf))))
12043     {
12044       /* Handle prefixes before fwait.  */
12045       for (i = 0; i < fwait_prefix && all_prefixes[i];
12046            i++)
12047         (*info->fprintf_func) (info->stream, "%s ",
12048                                prefix_name (all_prefixes[i], sizeflag));
12049       (*info->fprintf_func) (info->stream, "fwait");
12050       return i + 1;
12051     }
12052
12053   if (*codep == 0x0f)
12054     {
12055       unsigned char threebyte;
12056
12057       codep++;
12058       FETCH_DATA (info, codep + 1);
12059       threebyte = *codep;
12060       dp = &dis386_twobyte[threebyte];
12061       need_modrm = twobyte_has_modrm[*codep];
12062       codep++;
12063     }
12064   else
12065     {
12066       dp = &dis386[*codep];
12067       need_modrm = onebyte_has_modrm[*codep];
12068       codep++;
12069     }
12070
12071   /* Save sizeflag for printing the extra prefixes later before updating
12072      it for mnemonic and operand processing.  The prefix names depend
12073      only on the address mode.  */
12074   orig_sizeflag = sizeflag;
12075   if (prefixes & PREFIX_ADDR)
12076     sizeflag ^= AFLAG;
12077   if ((prefixes & PREFIX_DATA))
12078     sizeflag ^= DFLAG;
12079
12080   end_codep = codep;
12081   if (need_modrm)
12082     {
12083       FETCH_DATA (info, codep + 1);
12084       modrm.mod = (*codep >> 6) & 3;
12085       modrm.reg = (*codep >> 3) & 7;
12086       modrm.rm = *codep & 7;
12087     }
12088
12089   need_vex = 0;
12090   need_vex_reg = 0;
12091   vex_w_done = 0;
12092   memset (&vex, 0, sizeof (vex));
12093
12094   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12095     {
12096       get_sib (info, sizeflag);
12097       dofloat (sizeflag);
12098     }
12099   else
12100     {
12101       dp = get_valid_dis386 (dp, info);
12102       if (dp != NULL && putop (dp->name, sizeflag) == 0)
12103         {
12104           get_sib (info, sizeflag);
12105           for (i = 0; i < MAX_OPERANDS; ++i)
12106             {
12107               obufp = op_out[i];
12108               op_ad = MAX_OPERANDS - 1 - i;
12109               if (dp->op[i].rtn)
12110                 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12111               /* For EVEX instruction after the last operand masking
12112                  should be printed.  */
12113               if (i == 0 && vex.evex)
12114                 {
12115                   /* Don't print {%k0}.  */
12116                   if (vex.mask_register_specifier)
12117                     {
12118                       oappend ("{");
12119                       oappend (names_mask[vex.mask_register_specifier]);
12120                       oappend ("}");
12121                     }
12122                   if (vex.zeroing)
12123                     oappend ("{z}");
12124                 }
12125             }
12126         }
12127     }
12128
12129   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12130      are all 0s in inverted form.  */
12131   if (need_vex && vex.register_specifier != 0)
12132     {
12133       (*info->fprintf_func) (info->stream, "(bad)");
12134       return end_codep - priv.the_buffer;
12135     }
12136
12137   /* Check if the REX prefix is used.  */
12138   if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12139     all_prefixes[last_rex_prefix] = 0;
12140
12141   /* Check if the SEG prefix is used.  */
12142   if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12143                    | PREFIX_FS | PREFIX_GS)) != 0
12144       && (used_prefixes & active_seg_prefix) != 0)
12145     all_prefixes[last_seg_prefix] = 0;
12146
12147   /* Check if the ADDR prefix is used.  */
12148   if ((prefixes & PREFIX_ADDR) != 0
12149       && (used_prefixes & PREFIX_ADDR) != 0)
12150     all_prefixes[last_addr_prefix] = 0;
12151
12152   /* Check if the DATA prefix is used.  */
12153   if ((prefixes & PREFIX_DATA) != 0
12154       && (used_prefixes & PREFIX_DATA) != 0)
12155     all_prefixes[last_data_prefix] = 0;
12156
12157   /* Print the extra prefixes.  */
12158   prefix_length = 0;
12159   for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12160     if (all_prefixes[i])
12161       {
12162         const char *name;
12163         name = prefix_name (all_prefixes[i], orig_sizeflag);
12164         if (name == NULL)
12165           abort ();
12166         prefix_length += strlen (name) + 1;
12167         (*info->fprintf_func) (info->stream, "%s ", name);
12168       }
12169
12170   /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12171      unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
12172      used by putop and MMX/SSE operand and may be overriden by the
12173      PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12174      separately.  */
12175   if (dp->prefix_requirement == PREFIX_OPCODE
12176       && dp != &bad_opcode
12177       && (((prefixes
12178             & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12179            && (used_prefixes
12180                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12181           || ((((prefixes
12182                  & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12183                 == PREFIX_DATA)
12184                && (used_prefixes & PREFIX_DATA) == 0))))
12185     {
12186       (*info->fprintf_func) (info->stream, "(bad)");
12187       return end_codep - priv.the_buffer;
12188     }
12189
12190   /* Check maximum code length.  */
12191   if ((codep - start_codep) > MAX_CODE_LENGTH)
12192     {
12193       (*info->fprintf_func) (info->stream, "(bad)");
12194       return MAX_CODE_LENGTH;
12195     }
12196
12197   obufp = mnemonicendp;
12198   for (i = strlen (obuf) + prefix_length; i < 6; i++)
12199     oappend (" ");
12200   oappend (" ");
12201   (*info->fprintf_func) (info->stream, "%s", obuf);
12202
12203   /* The enter and bound instructions are printed with operands in the same
12204      order as the intel book; everything else is printed in reverse order.  */
12205   if (intel_syntax || two_source_ops)
12206     {
12207       bfd_vma riprel;
12208
12209       for (i = 0; i < MAX_OPERANDS; ++i)
12210         op_txt[i] = op_out[i];
12211
12212       if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12213           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12214         {
12215           op_txt[2] = op_out[3];
12216           op_txt[3] = op_out[2];
12217         }
12218
12219       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12220         {
12221           op_ad = op_index[i];
12222           op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12223           op_index[MAX_OPERANDS - 1 - i] = op_ad;
12224           riprel = op_riprel[i];
12225           op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12226           op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12227         }
12228     }
12229   else
12230     {
12231       for (i = 0; i < MAX_OPERANDS; ++i)
12232         op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12233     }
12234
12235   needcomma = 0;
12236   for (i = 0; i < MAX_OPERANDS; ++i)
12237     if (*op_txt[i])
12238       {
12239         if (needcomma)
12240           (*info->fprintf_func) (info->stream, ",");
12241         if (op_index[i] != -1 && !op_riprel[i])
12242           (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12243         else
12244           (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12245         needcomma = 1;
12246       }
12247
12248   for (i = 0; i < MAX_OPERANDS; i++)
12249     if (op_index[i] != -1 && op_riprel[i])
12250       {
12251         (*info->fprintf_func) (info->stream, "        # ");
12252         (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12253                                                 + op_address[op_index[i]]), info);
12254         break;
12255       }
12256   return codep - priv.the_buffer;
12257 }
12258
12259 static const char *float_mem[] = {
12260   /* d8 */
12261   "fadd{s|}",
12262   "fmul{s|}",
12263   "fcom{s|}",
12264   "fcomp{s|}",
12265   "fsub{s|}",
12266   "fsubr{s|}",
12267   "fdiv{s|}",
12268   "fdivr{s|}",
12269   /* d9 */
12270   "fld{s|}",
12271   "(bad)",
12272   "fst{s|}",
12273   "fstp{s|}",
12274   "fldenvIC",
12275   "fldcw",
12276   "fNstenvIC",
12277   "fNstcw",
12278   /* da */
12279   "fiadd{l|}",
12280   "fimul{l|}",
12281   "ficom{l|}",
12282   "ficomp{l|}",
12283   "fisub{l|}",
12284   "fisubr{l|}",
12285   "fidiv{l|}",
12286   "fidivr{l|}",
12287   /* db */
12288   "fild{l|}",
12289   "fisttp{l|}",
12290   "fist{l|}",
12291   "fistp{l|}",
12292   "(bad)",
12293   "fld{t||t|}",
12294   "(bad)",
12295   "fstp{t||t|}",
12296   /* dc */
12297   "fadd{l|}",
12298   "fmul{l|}",
12299   "fcom{l|}",
12300   "fcomp{l|}",
12301   "fsub{l|}",
12302   "fsubr{l|}",
12303   "fdiv{l|}",
12304   "fdivr{l|}",
12305   /* dd */
12306   "fld{l|}",
12307   "fisttp{ll|}",
12308   "fst{l||}",
12309   "fstp{l|}",
12310   "frstorIC",
12311   "(bad)",
12312   "fNsaveIC",
12313   "fNstsw",
12314   /* de */
12315   "fiadd{s|}",
12316   "fimul{s|}",
12317   "ficom{s|}",
12318   "ficomp{s|}",
12319   "fisub{s|}",
12320   "fisubr{s|}",
12321   "fidiv{s|}",
12322   "fidivr{s|}",
12323   /* df */
12324   "fild{s|}",
12325   "fisttp{s|}",
12326   "fist{s|}",
12327   "fistp{s|}",
12328   "fbld",
12329   "fild{ll|}",
12330   "fbstp",
12331   "fistp{ll|}",
12332 };
12333
12334 static const unsigned char float_mem_mode[] = {
12335   /* d8 */
12336   d_mode,
12337   d_mode,
12338   d_mode,
12339   d_mode,
12340   d_mode,
12341   d_mode,
12342   d_mode,
12343   d_mode,
12344   /* d9 */
12345   d_mode,
12346   0,
12347   d_mode,
12348   d_mode,
12349   0,
12350   w_mode,
12351   0,
12352   w_mode,
12353   /* da */
12354   d_mode,
12355   d_mode,
12356   d_mode,
12357   d_mode,
12358   d_mode,
12359   d_mode,
12360   d_mode,
12361   d_mode,
12362   /* db */
12363   d_mode,
12364   d_mode,
12365   d_mode,
12366   d_mode,
12367   0,
12368   t_mode,
12369   0,
12370   t_mode,
12371   /* dc */
12372   q_mode,
12373   q_mode,
12374   q_mode,
12375   q_mode,
12376   q_mode,
12377   q_mode,
12378   q_mode,
12379   q_mode,
12380   /* dd */
12381   q_mode,
12382   q_mode,
12383   q_mode,
12384   q_mode,
12385   0,
12386   0,
12387   0,
12388   w_mode,
12389   /* de */
12390   w_mode,
12391   w_mode,
12392   w_mode,
12393   w_mode,
12394   w_mode,
12395   w_mode,
12396   w_mode,
12397   w_mode,
12398   /* df */
12399   w_mode,
12400   w_mode,
12401   w_mode,
12402   w_mode,
12403   t_mode,
12404   q_mode,
12405   t_mode,
12406   q_mode
12407 };
12408
12409 #define ST { OP_ST, 0 }
12410 #define STi { OP_STi, 0 }
12411
12412 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12413 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12414 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12415 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12416 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12417 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12418 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12419 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12420 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12421
12422 static const struct dis386 float_reg[][8] = {
12423   /* d8 */
12424   {
12425     { "fadd",   { ST, STi }, 0 },
12426     { "fmul",   { ST, STi }, 0 },
12427     { "fcom",   { STi }, 0 },
12428     { "fcomp",  { STi }, 0 },
12429     { "fsub",   { ST, STi }, 0 },
12430     { "fsubr",  { ST, STi }, 0 },
12431     { "fdiv",   { ST, STi }, 0 },
12432     { "fdivr",  { ST, STi }, 0 },
12433   },
12434   /* d9 */
12435   {
12436     { "fld",    { STi }, 0 },
12437     { "fxch",   { STi }, 0 },
12438     { FGRPd9_2 },
12439     { Bad_Opcode },
12440     { FGRPd9_4 },
12441     { FGRPd9_5 },
12442     { FGRPd9_6 },
12443     { FGRPd9_7 },
12444   },
12445   /* da */
12446   {
12447     { "fcmovb", { ST, STi }, 0 },
12448     { "fcmove", { ST, STi }, 0 },
12449     { "fcmovbe",{ ST, STi }, 0 },
12450     { "fcmovu", { ST, STi }, 0 },
12451     { Bad_Opcode },
12452     { FGRPda_5 },
12453     { Bad_Opcode },
12454     { Bad_Opcode },
12455   },
12456   /* db */
12457   {
12458     { "fcmovnb",{ ST, STi }, 0 },
12459     { "fcmovne",{ ST, STi }, 0 },
12460     { "fcmovnbe",{ ST, STi }, 0 },
12461     { "fcmovnu",{ ST, STi }, 0 },
12462     { FGRPdb_4 },
12463     { "fucomi", { ST, STi }, 0 },
12464     { "fcomi",  { ST, STi }, 0 },
12465     { Bad_Opcode },
12466   },
12467   /* dc */
12468   {
12469     { "fadd",   { STi, ST }, 0 },
12470     { "fmul",   { STi, ST }, 0 },
12471     { Bad_Opcode },
12472     { Bad_Opcode },
12473     { "fsub{!M|r}",     { STi, ST }, 0 },
12474     { "fsub{M|}",       { STi, ST }, 0 },
12475     { "fdiv{!M|r}",     { STi, ST }, 0 },
12476     { "fdiv{M|}",       { STi, ST }, 0 },
12477   },
12478   /* dd */
12479   {
12480     { "ffree",  { STi }, 0 },
12481     { Bad_Opcode },
12482     { "fst",    { STi }, 0 },
12483     { "fstp",   { STi }, 0 },
12484     { "fucom",  { STi }, 0 },
12485     { "fucomp", { STi }, 0 },
12486     { Bad_Opcode },
12487     { Bad_Opcode },
12488   },
12489   /* de */
12490   {
12491     { "faddp",  { STi, ST }, 0 },
12492     { "fmulp",  { STi, ST }, 0 },
12493     { Bad_Opcode },
12494     { FGRPde_3 },
12495     { "fsub{!M|r}p",    { STi, ST }, 0 },
12496     { "fsub{M|}p",      { STi, ST }, 0 },
12497     { "fdiv{!M|r}p",    { STi, ST }, 0 },
12498     { "fdiv{M|}p",      { STi, ST }, 0 },
12499   },
12500   /* df */
12501   {
12502     { "ffreep", { STi }, 0 },
12503     { Bad_Opcode },
12504     { Bad_Opcode },
12505     { Bad_Opcode },
12506     { FGRPdf_4 },
12507     { "fucomip", { ST, STi }, 0 },
12508     { "fcomip", { ST, STi }, 0 },
12509     { Bad_Opcode },
12510   },
12511 };
12512
12513 static char *fgrps[][8] = {
12514   /* Bad opcode 0 */
12515   {
12516     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12517   },
12518
12519   /* d9_2  1 */
12520   {
12521     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12522   },
12523
12524   /* d9_4  2 */
12525   {
12526     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12527   },
12528
12529   /* d9_5  3 */
12530   {
12531     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12532   },
12533
12534   /* d9_6  4 */
12535   {
12536     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12537   },
12538
12539   /* d9_7  5 */
12540   {
12541     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12542   },
12543
12544   /* da_5  6 */
12545   {
12546     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12547   },
12548
12549   /* db_4  7 */
12550   {
12551     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12552     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12553   },
12554
12555   /* de_3  8 */
12556   {
12557     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12558   },
12559
12560   /* df_4  9 */
12561   {
12562     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12563   },
12564 };
12565
12566 static void
12567 swap_operand (void)
12568 {
12569   mnemonicendp[0] = '.';
12570   mnemonicendp[1] = 's';
12571   mnemonicendp += 2;
12572 }
12573
12574 static void
12575 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12576                int sizeflag ATTRIBUTE_UNUSED)
12577 {
12578   /* Skip mod/rm byte.  */
12579   MODRM_CHECK;
12580   codep++;
12581 }
12582
12583 static void
12584 dofloat (int sizeflag)
12585 {
12586   const struct dis386 *dp;
12587   unsigned char floatop;
12588
12589   floatop = codep[-1];
12590
12591   if (modrm.mod != 3)
12592     {
12593       int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12594
12595       putop (float_mem[fp_indx], sizeflag);
12596       obufp = op_out[0];
12597       op_ad = 2;
12598       OP_E (float_mem_mode[fp_indx], sizeflag);
12599       return;
12600     }
12601   /* Skip mod/rm byte.  */
12602   MODRM_CHECK;
12603   codep++;
12604
12605   dp = &float_reg[floatop - 0xd8][modrm.reg];
12606   if (dp->name == NULL)
12607     {
12608       putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12609
12610       /* Instruction fnstsw is only one with strange arg.  */
12611       if (floatop == 0xdf && codep[-1] == 0xe0)
12612         strcpy (op_out[0], names16[0]);
12613     }
12614   else
12615     {
12616       putop (dp->name, sizeflag);
12617
12618       obufp = op_out[0];
12619       op_ad = 2;
12620       if (dp->op[0].rtn)
12621         (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12622
12623       obufp = op_out[1];
12624       op_ad = 1;
12625       if (dp->op[1].rtn)
12626         (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12627     }
12628 }
12629
12630 /* Like oappend (below), but S is a string starting with '%'.
12631    In Intel syntax, the '%' is elided.  */
12632 static void
12633 oappend_maybe_intel (const char *s)
12634 {
12635   oappend (s + intel_syntax);
12636 }
12637
12638 static void
12639 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12640 {
12641   oappend_maybe_intel ("%st");
12642 }
12643
12644 static void
12645 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12646 {
12647   sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12648   oappend_maybe_intel (scratchbuf);
12649 }
12650
12651 /* Capital letters in template are macros.  */
12652 static int
12653 putop (const char *in_template, int sizeflag)
12654 {
12655   const char *p;
12656   int alt = 0;
12657   int cond = 1;
12658   unsigned int l = 0, len = 1;
12659   char last[4];
12660
12661 #define SAVE_LAST(c)                    \
12662   if (l < len && l < sizeof (last))     \
12663     last[l++] = c;                      \
12664   else                                  \
12665     abort ();
12666
12667   for (p = in_template; *p; p++)
12668     {
12669       switch (*p)
12670         {
12671         default:
12672           *obufp++ = *p;
12673           break;
12674         case '%':
12675           len++;
12676           break;
12677         case '!':
12678           cond = 0;
12679           break;
12680         case '{':
12681           if (intel_syntax)
12682             {
12683               while (*++p != '|')
12684                 if (*p == '}' || *p == '\0')
12685                   abort ();
12686             }
12687           /* Fall through.  */
12688         case 'I':
12689           alt = 1;
12690           continue;
12691         case '|':
12692           while (*++p != '}')
12693             {
12694               if (*p == '\0')
12695                 abort ();
12696             }
12697           break;
12698         case '}':
12699           break;
12700         case 'A':
12701           if (intel_syntax)
12702             break;
12703           if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12704             *obufp++ = 'b';
12705           break;
12706         case 'B':
12707           if (l == 0 && len == 1)
12708             {
12709 case_B:
12710               if (intel_syntax)
12711                 break;
12712               if (sizeflag & SUFFIX_ALWAYS)
12713                 *obufp++ = 'b';
12714             }
12715           else
12716             {
12717               if (l != 1
12718                   || len != 2
12719                   || last[0] != 'L')
12720                 {
12721                   SAVE_LAST (*p);
12722                   break;
12723                 }
12724
12725               if (address_mode == mode_64bit
12726                   && !(prefixes & PREFIX_ADDR))
12727                 {
12728                   *obufp++ = 'a';
12729                   *obufp++ = 'b';
12730                   *obufp++ = 's';
12731                 }
12732
12733               goto case_B;
12734             }
12735           break;
12736         case 'C':
12737           if (intel_syntax && !alt)
12738             break;
12739           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12740             {
12741               if (sizeflag & DFLAG)
12742                 *obufp++ = intel_syntax ? 'd' : 'l';
12743               else
12744                 *obufp++ = intel_syntax ? 'w' : 's';
12745               used_prefixes |= (prefixes & PREFIX_DATA);
12746             }
12747           break;
12748         case 'D':
12749           if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12750             break;
12751           USED_REX (REX_W);
12752           if (modrm.mod == 3)
12753             {
12754               if (rex & REX_W)
12755                 *obufp++ = 'q';
12756               else
12757                 {
12758                   if (sizeflag & DFLAG)
12759                     *obufp++ = intel_syntax ? 'd' : 'l';
12760                   else
12761                     *obufp++ = 'w';
12762                   used_prefixes |= (prefixes & PREFIX_DATA);
12763                 }
12764             }
12765           else
12766             *obufp++ = 'w';
12767           break;
12768         case 'E':               /* For jcxz/jecxz */
12769           if (address_mode == mode_64bit)
12770             {
12771               if (sizeflag & AFLAG)
12772                 *obufp++ = 'r';
12773               else
12774                 *obufp++ = 'e';
12775             }
12776           else
12777             if (sizeflag & AFLAG)
12778               *obufp++ = 'e';
12779           used_prefixes |= (prefixes & PREFIX_ADDR);
12780           break;
12781         case 'F':
12782           if (intel_syntax)
12783             break;
12784           if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12785             {
12786               if (sizeflag & AFLAG)
12787                 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12788               else
12789                 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12790               used_prefixes |= (prefixes & PREFIX_ADDR);
12791             }
12792           break;
12793         case 'G':
12794           if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12795             break;
12796           if ((rex & REX_W) || (sizeflag & DFLAG))
12797             *obufp++ = 'l';
12798           else
12799             *obufp++ = 'w';
12800           if (!(rex & REX_W))
12801             used_prefixes |= (prefixes & PREFIX_DATA);
12802           break;
12803         case 'H':
12804           if (intel_syntax)
12805             break;
12806           if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12807               || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12808             {
12809               used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12810               *obufp++ = ',';
12811               *obufp++ = 'p';
12812               if (prefixes & PREFIX_DS)
12813                 *obufp++ = 't';
12814               else
12815                 *obufp++ = 'n';
12816             }
12817           break;
12818         case 'J':
12819           if (intel_syntax)
12820             break;
12821           *obufp++ = 'l';
12822           break;
12823         case 'K':
12824           USED_REX (REX_W);
12825           if (rex & REX_W)
12826             *obufp++ = 'q';
12827           else
12828             *obufp++ = 'd';
12829           break;
12830         case 'Z':
12831           if (l != 0 || len != 1)
12832             {
12833               if (l != 1 || len != 2 || last[0] != 'X')
12834                 {
12835                   SAVE_LAST (*p);
12836                   break;
12837                 }
12838               if (!need_vex || !vex.evex)
12839                 abort ();
12840               if (intel_syntax
12841                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12842                 break;
12843               switch (vex.length)
12844                 {
12845                 case 128:
12846                   *obufp++ = 'x';
12847                   break;
12848                 case 256:
12849                   *obufp++ = 'y';
12850                   break;
12851                 case 512:
12852                   *obufp++ = 'z';
12853                   break;
12854                 default:
12855                   abort ();
12856                 }
12857               break;
12858             }
12859           if (intel_syntax)
12860             break;
12861           if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12862             {
12863               *obufp++ = 'q';
12864               break;
12865             }
12866           /* Fall through.  */
12867           goto case_L;
12868         case 'L':
12869           if (l != 0 || len != 1)
12870             {
12871               SAVE_LAST (*p);
12872               break;
12873             }
12874 case_L:
12875           if (intel_syntax)
12876             break;
12877           if (sizeflag & SUFFIX_ALWAYS)
12878             *obufp++ = 'l';
12879           break;
12880         case 'M':
12881           if (intel_mnemonic != cond)
12882             *obufp++ = 'r';
12883           break;
12884         case 'N':
12885           if ((prefixes & PREFIX_FWAIT) == 0)
12886             *obufp++ = 'n';
12887           else
12888             used_prefixes |= PREFIX_FWAIT;
12889           break;
12890         case 'O':
12891           USED_REX (REX_W);
12892           if (rex & REX_W)
12893             *obufp++ = 'o';
12894           else if (intel_syntax && (sizeflag & DFLAG))
12895             *obufp++ = 'q';
12896           else
12897             *obufp++ = 'd';
12898           if (!(rex & REX_W))
12899             used_prefixes |= (prefixes & PREFIX_DATA);
12900           break;
12901         case '&':
12902           if (!intel_syntax
12903               && address_mode == mode_64bit
12904               && isa64 == intel64)
12905             {
12906               *obufp++ = 'q';
12907               break;
12908             }
12909           /* Fall through.  */
12910         case 'T':
12911           if (!intel_syntax
12912               && address_mode == mode_64bit
12913               && ((sizeflag & DFLAG) || (rex & REX_W)))
12914             {
12915               *obufp++ = 'q';
12916               break;
12917             }
12918           /* Fall through.  */
12919           goto case_P;
12920         case 'P':
12921           if (l == 0 && len == 1)
12922             {
12923 case_P:
12924               if (intel_syntax)
12925                 {
12926                   if ((rex & REX_W) == 0
12927                       && (prefixes & PREFIX_DATA))
12928                     {
12929                       if ((sizeflag & DFLAG) == 0)
12930                         *obufp++ = 'w';
12931                       used_prefixes |= (prefixes & PREFIX_DATA);
12932                     }
12933                   break;
12934                 }
12935               if ((prefixes & PREFIX_DATA)
12936                   || (rex & REX_W)
12937                   || (sizeflag & SUFFIX_ALWAYS))
12938                 {
12939                   USED_REX (REX_W);
12940                   if (rex & REX_W)
12941                     *obufp++ = 'q';
12942                   else
12943                     {
12944                       if (sizeflag & DFLAG)
12945                         *obufp++ = 'l';
12946                       else
12947                         *obufp++ = 'w';
12948                       used_prefixes |= (prefixes & PREFIX_DATA);
12949                     }
12950                 }
12951             }
12952           else
12953             {
12954               if (l != 1 || len != 2 || last[0] != 'L')
12955                 {
12956                   SAVE_LAST (*p);
12957                   break;
12958                 }
12959
12960               if ((prefixes & PREFIX_DATA)
12961                   || (rex & REX_W)
12962                   || (sizeflag & SUFFIX_ALWAYS))
12963                 {
12964                   USED_REX (REX_W);
12965                   if (rex & REX_W)
12966                     *obufp++ = 'q';
12967                   else
12968                     {
12969                       if (sizeflag & DFLAG)
12970                         *obufp++ = intel_syntax ? 'd' : 'l';
12971                       else
12972                         *obufp++ = 'w';
12973                       used_prefixes |= (prefixes & PREFIX_DATA);
12974                     }
12975                 }
12976             }
12977           break;
12978         case 'U':
12979           if (intel_syntax)
12980             break;
12981           if (address_mode == mode_64bit
12982               && ((sizeflag & DFLAG) || (rex & REX_W)))
12983             {
12984               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12985                 *obufp++ = 'q';
12986               break;
12987             }
12988           /* Fall through.  */
12989           goto case_Q;
12990         case 'Q':
12991           if (l == 0 && len == 1)
12992             {
12993 case_Q:
12994               if (intel_syntax && !alt)
12995                 break;
12996               USED_REX (REX_W);
12997               if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12998                 {
12999                   if (rex & REX_W)
13000                     *obufp++ = 'q';
13001                   else
13002                     {
13003                       if (sizeflag & DFLAG)
13004                         *obufp++ = intel_syntax ? 'd' : 'l';
13005                       else
13006                         *obufp++ = 'w';
13007                       used_prefixes |= (prefixes & PREFIX_DATA);
13008                     }
13009                 }
13010             }
13011           else
13012             {
13013               if (l != 1 || len != 2 || last[0] != 'L')
13014                 {
13015                   SAVE_LAST (*p);
13016                   break;
13017                 }
13018               if (intel_syntax
13019                   || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13020                 break;
13021               if ((rex & REX_W))
13022                 {
13023                   USED_REX (REX_W);
13024                   *obufp++ = 'q';
13025                 }
13026               else
13027                 *obufp++ = 'l';
13028             }
13029           break;
13030         case 'R':
13031           USED_REX (REX_W);
13032           if (rex & REX_W)
13033             *obufp++ = 'q';
13034           else if (sizeflag & DFLAG)
13035             {
13036               if (intel_syntax)
13037                   *obufp++ = 'd';
13038               else
13039                   *obufp++ = 'l';
13040             }
13041           else
13042             *obufp++ = 'w';
13043           if (intel_syntax && !p[1]
13044               && ((rex & REX_W) || (sizeflag & DFLAG)))
13045             *obufp++ = 'e';
13046           if (!(rex & REX_W))
13047             used_prefixes |= (prefixes & PREFIX_DATA);
13048           break;
13049         case 'V':
13050           if (l == 0 && len == 1)
13051             {
13052               if (intel_syntax)
13053                 break;
13054               if (address_mode == mode_64bit
13055                   && ((sizeflag & DFLAG) || (rex & REX_W)))
13056                 {
13057                   if (sizeflag & SUFFIX_ALWAYS)
13058                     *obufp++ = 'q';
13059                   break;
13060                 }
13061             }
13062           else
13063             {
13064               if (l != 1
13065                   || len != 2
13066                   || last[0] != 'L')
13067                 {
13068                   SAVE_LAST (*p);
13069                   break;
13070                 }
13071
13072               if (rex & REX_W)
13073                 {
13074                   *obufp++ = 'a';
13075                   *obufp++ = 'b';
13076                   *obufp++ = 's';
13077                 }
13078             }
13079           /* Fall through.  */
13080           goto case_S;
13081         case 'S':
13082           if (l == 0 && len == 1)
13083             {
13084 case_S:
13085               if (intel_syntax)
13086                 break;
13087               if (sizeflag & SUFFIX_ALWAYS)
13088                 {
13089                   if (rex & REX_W)
13090                     *obufp++ = 'q';
13091                   else
13092                     {
13093                       if (sizeflag & DFLAG)
13094                         *obufp++ = 'l';
13095                       else
13096                         *obufp++ = 'w';
13097                       used_prefixes |= (prefixes & PREFIX_DATA);
13098                     }
13099                 }
13100             }
13101           else
13102             {
13103               if (l != 1
13104                   || len != 2
13105                   || last[0] != 'L')
13106                 {
13107                   SAVE_LAST (*p);
13108                   break;
13109                 }
13110
13111               if (address_mode == mode_64bit
13112                   && !(prefixes & PREFIX_ADDR))
13113                 {
13114                   *obufp++ = 'a';
13115                   *obufp++ = 'b';
13116                   *obufp++ = 's';
13117                 }
13118
13119               goto case_S;
13120             }
13121           break;
13122         case 'X':
13123           if (l != 0 || len != 1)
13124             {
13125               SAVE_LAST (*p);
13126               break;
13127             }
13128           if (need_vex && vex.prefix)
13129             {
13130               if (vex.prefix == DATA_PREFIX_OPCODE)
13131                 *obufp++ = 'd';
13132               else
13133                 *obufp++ = 's';
13134             }
13135           else
13136             {
13137               if (prefixes & PREFIX_DATA)
13138                 *obufp++ = 'd';
13139               else
13140                 *obufp++ = 's';
13141               used_prefixes |= (prefixes & PREFIX_DATA);
13142             }
13143           break;
13144         case 'Y':
13145           if (l == 0 && len == 1)
13146             abort ();
13147           else
13148             {
13149               if (l != 1 || len != 2 || last[0] != 'X')
13150                 {
13151                   SAVE_LAST (*p);
13152                   break;
13153                 }
13154               if (!need_vex)
13155                 abort ();
13156               if (intel_syntax
13157                   || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13158                 break;
13159               switch (vex.length)
13160                 {
13161                 case 128:
13162                   *obufp++ = 'x';
13163                   break;
13164                 case 256:
13165                   *obufp++ = 'y';
13166                   break;
13167                 case 512:
13168                   if (!vex.evex)
13169                 default:
13170                     abort ();
13171                 }
13172             }
13173           break;
13174         case 'W':
13175           if (l == 0 && len == 1)
13176             {
13177               /* operand size flag for cwtl, cbtw */
13178               USED_REX (REX_W);
13179               if (rex & REX_W)
13180                 {
13181                   if (intel_syntax)
13182                     *obufp++ = 'd';
13183                   else
13184                     *obufp++ = 'l';
13185                 }
13186               else if (sizeflag & DFLAG)
13187                 *obufp++ = 'w';
13188               else
13189                 *obufp++ = 'b';
13190               if (!(rex & REX_W))
13191                 used_prefixes |= (prefixes & PREFIX_DATA);
13192             }
13193           else
13194             {
13195               if (l != 1
13196                   || len != 2
13197                   || (last[0] != 'X'
13198                       && last[0] != 'L'))
13199                 {
13200                   SAVE_LAST (*p);
13201                   break;
13202                 }
13203               if (!need_vex)
13204                 abort ();
13205               if (last[0] == 'X')
13206                 *obufp++ = vex.w ? 'd': 's';
13207               else
13208                 *obufp++ = vex.w ? 'q': 'd';
13209             }
13210           break;
13211         case '^':
13212           if (intel_syntax)
13213             break;
13214           if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13215             {
13216               if (sizeflag & DFLAG)
13217                 *obufp++ = 'l';
13218               else
13219                 *obufp++ = 'w';
13220               used_prefixes |= (prefixes & PREFIX_DATA);
13221             }
13222           break;
13223         case '@':
13224           if (intel_syntax)
13225             break;
13226           if (address_mode == mode_64bit
13227               && (isa64 == intel64
13228                   || ((sizeflag & DFLAG) || (rex & REX_W))))
13229               *obufp++ = 'q';
13230           else if ((prefixes & PREFIX_DATA))
13231             {
13232               if (!(sizeflag & DFLAG))
13233                 *obufp++ = 'w';
13234               used_prefixes |= (prefixes & PREFIX_DATA);
13235             }
13236           break;
13237         }
13238       alt = 0;
13239     }
13240   *obufp = 0;
13241   mnemonicendp = obufp;
13242   return 0;
13243 }
13244
13245 static void
13246 oappend (const char *s)
13247 {
13248   obufp = stpcpy (obufp, s);
13249 }
13250
13251 static void
13252 append_seg (void)
13253 {
13254   /* Only print the active segment register.  */
13255   if (!active_seg_prefix)
13256     return;
13257
13258   used_prefixes |= active_seg_prefix;
13259   switch (active_seg_prefix)
13260     {
13261     case PREFIX_CS:
13262       oappend_maybe_intel ("%cs:");
13263       break;
13264     case PREFIX_DS:
13265       oappend_maybe_intel ("%ds:");
13266       break;
13267     case PREFIX_SS:
13268       oappend_maybe_intel ("%ss:");
13269       break;
13270     case PREFIX_ES:
13271       oappend_maybe_intel ("%es:");
13272       break;
13273     case PREFIX_FS:
13274       oappend_maybe_intel ("%fs:");
13275       break;
13276     case PREFIX_GS:
13277       oappend_maybe_intel ("%gs:");
13278       break;
13279     default:
13280       break;
13281     }
13282 }
13283
13284 static void
13285 OP_indirE (int bytemode, int sizeflag)
13286 {
13287   if (!intel_syntax)
13288     oappend ("*");
13289   OP_E (bytemode, sizeflag);
13290 }
13291
13292 static void
13293 print_operand_value (char *buf, int hex, bfd_vma disp)
13294 {
13295   if (address_mode == mode_64bit)
13296     {
13297       if (hex)
13298         {
13299           char tmp[30];
13300           int i;
13301           buf[0] = '0';
13302           buf[1] = 'x';
13303           sprintf_vma (tmp, disp);
13304           for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13305           strcpy (buf + 2, tmp + i);
13306         }
13307       else
13308         {
13309           bfd_signed_vma v = disp;
13310           char tmp[30];
13311           int i;
13312           if (v < 0)
13313             {
13314               *(buf++) = '-';
13315               v = -disp;
13316               /* Check for possible overflow on 0x8000000000000000.  */
13317               if (v < 0)
13318                 {
13319                   strcpy (buf, "9223372036854775808");
13320                   return;
13321                 }
13322             }
13323           if (!v)
13324             {
13325               strcpy (buf, "0");
13326               return;
13327             }
13328
13329           i = 0;
13330           tmp[29] = 0;
13331           while (v)
13332             {
13333               tmp[28 - i] = (v % 10) + '0';
13334               v /= 10;
13335               i++;
13336             }
13337           strcpy (buf, tmp + 29 - i);
13338         }
13339     }
13340   else
13341     {
13342       if (hex)
13343         sprintf (buf, "0x%x", (unsigned int) disp);
13344       else
13345         sprintf (buf, "%d", (int) disp);
13346     }
13347 }
13348
13349 /* Put DISP in BUF as signed hex number.  */
13350
13351 static void
13352 print_displacement (char *buf, bfd_vma disp)
13353 {
13354   bfd_signed_vma val = disp;
13355   char tmp[30];
13356   int i, j = 0;
13357
13358   if (val < 0)
13359     {
13360       buf[j++] = '-';
13361       val = -disp;
13362
13363       /* Check for possible overflow.  */
13364       if (val < 0)
13365         {
13366           switch (address_mode)
13367             {
13368             case mode_64bit:
13369               strcpy (buf + j, "0x8000000000000000");
13370               break;
13371             case mode_32bit:
13372               strcpy (buf + j, "0x80000000");
13373               break;
13374             case mode_16bit:
13375               strcpy (buf + j, "0x8000");
13376               break;
13377             }
13378           return;
13379         }
13380     }
13381
13382   buf[j++] = '0';
13383   buf[j++] = 'x';
13384
13385   sprintf_vma (tmp, (bfd_vma) val);
13386   for (i = 0; tmp[i] == '0'; i++)
13387     continue;
13388   if (tmp[i] == '\0')
13389     i--;
13390   strcpy (buf + j, tmp + i);
13391 }
13392
13393 static void
13394 intel_operand_size (int bytemode, int sizeflag)
13395 {
13396   if (vex.evex
13397       && vex.b
13398       && (bytemode == x_mode
13399           || bytemode == evex_half_bcst_xmmq_mode))
13400     {
13401       if (vex.w)
13402         oappend ("QWORD PTR ");
13403       else
13404         oappend ("DWORD PTR ");
13405       return;
13406     }
13407   switch (bytemode)
13408     {
13409     case b_mode:
13410     case b_swap_mode:
13411     case dqb_mode:
13412     case db_mode:
13413       oappend ("BYTE PTR ");
13414       break;
13415     case w_mode:
13416     case dw_mode:
13417     case dqw_mode:
13418       oappend ("WORD PTR ");
13419       break;
13420     case indir_v_mode:
13421       if (address_mode == mode_64bit && isa64 == intel64)
13422         {
13423           oappend ("QWORD PTR ");
13424           break;
13425         }
13426       /* Fall through.  */
13427     case stack_v_mode:
13428       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13429         {
13430           oappend ("QWORD PTR ");
13431           break;
13432         }
13433       /* Fall through.  */
13434     case v_mode:
13435     case v_swap_mode:
13436     case dq_mode:
13437       USED_REX (REX_W);
13438       if (rex & REX_W)
13439         oappend ("QWORD PTR ");
13440       else
13441         {
13442           if ((sizeflag & DFLAG) || bytemode == dq_mode)
13443             oappend ("DWORD PTR ");
13444           else
13445             oappend ("WORD PTR ");
13446           used_prefixes |= (prefixes & PREFIX_DATA);
13447         }
13448       break;
13449     case z_mode:
13450       if ((rex & REX_W) || (sizeflag & DFLAG))
13451         *obufp++ = 'D';
13452       oappend ("WORD PTR ");
13453       if (!(rex & REX_W))
13454         used_prefixes |= (prefixes & PREFIX_DATA);
13455       break;
13456     case a_mode:
13457       if (sizeflag & DFLAG)
13458         oappend ("QWORD PTR ");
13459       else
13460         oappend ("DWORD PTR ");
13461       used_prefixes |= (prefixes & PREFIX_DATA);
13462       break;
13463     case d_mode:
13464     case d_scalar_mode:
13465     case d_scalar_swap_mode:
13466     case d_swap_mode:
13467     case dqd_mode:
13468       oappend ("DWORD PTR ");
13469       break;
13470     case q_mode:
13471     case q_scalar_mode:
13472     case q_scalar_swap_mode:
13473     case q_swap_mode:
13474       oappend ("QWORD PTR ");
13475       break;
13476     case m_mode:
13477       if (address_mode == mode_64bit)
13478         oappend ("QWORD PTR ");
13479       else
13480         oappend ("DWORD PTR ");
13481       break;
13482     case f_mode:
13483       if (sizeflag & DFLAG)
13484         oappend ("FWORD PTR ");
13485       else
13486         oappend ("DWORD PTR ");
13487       used_prefixes |= (prefixes & PREFIX_DATA);
13488       break;
13489     case t_mode:
13490       oappend ("TBYTE PTR ");
13491       break;
13492     case x_mode:
13493     case x_swap_mode:
13494     case evex_x_gscat_mode:
13495     case evex_x_nobcst_mode:
13496     case b_scalar_mode:
13497     case w_scalar_mode:
13498       if (need_vex)
13499         {
13500           switch (vex.length)
13501             {
13502             case 128:
13503               oappend ("XMMWORD PTR ");
13504               break;
13505             case 256:
13506               oappend ("YMMWORD PTR ");
13507               break;
13508             case 512:
13509               oappend ("ZMMWORD PTR ");
13510               break;
13511             default:
13512               abort ();
13513             }
13514         }
13515       else
13516         oappend ("XMMWORD PTR ");
13517       break;
13518     case xmm_mode:
13519       oappend ("XMMWORD PTR ");
13520       break;
13521     case ymm_mode:
13522       oappend ("YMMWORD PTR ");
13523       break;
13524     case xmmq_mode:
13525     case evex_half_bcst_xmmq_mode:
13526       if (!need_vex)
13527         abort ();
13528
13529       switch (vex.length)
13530         {
13531         case 128:
13532           oappend ("QWORD PTR ");
13533           break;
13534         case 256:
13535           oappend ("XMMWORD PTR ");
13536           break;
13537         case 512:
13538           oappend ("YMMWORD PTR ");
13539           break;
13540         default:
13541           abort ();
13542         }
13543       break;
13544     case xmm_mb_mode:
13545       if (!need_vex)
13546         abort ();
13547
13548       switch (vex.length)
13549         {
13550         case 128:
13551         case 256:
13552         case 512:
13553           oappend ("BYTE PTR ");
13554           break;
13555         default:
13556           abort ();
13557         }
13558       break;
13559     case xmm_mw_mode:
13560       if (!need_vex)
13561         abort ();
13562
13563       switch (vex.length)
13564         {
13565         case 128:
13566         case 256:
13567         case 512:
13568           oappend ("WORD PTR ");
13569           break;
13570         default:
13571           abort ();
13572         }
13573       break;
13574     case xmm_md_mode:
13575       if (!need_vex)
13576         abort ();
13577
13578       switch (vex.length)
13579         {
13580         case 128:
13581         case 256:
13582         case 512:
13583           oappend ("DWORD PTR ");
13584           break;
13585         default:
13586           abort ();
13587         }
13588       break;
13589     case xmm_mq_mode:
13590       if (!need_vex)
13591         abort ();
13592
13593       switch (vex.length)
13594         {
13595         case 128:
13596         case 256:
13597         case 512:
13598           oappend ("QWORD PTR ");
13599           break;
13600         default:
13601           abort ();
13602         }
13603       break;
13604     case xmmdw_mode:
13605       if (!need_vex)
13606         abort ();
13607
13608       switch (vex.length)
13609         {
13610         case 128:
13611           oappend ("WORD PTR ");
13612           break;
13613         case 256:
13614           oappend ("DWORD PTR ");
13615           break;
13616         case 512:
13617           oappend ("QWORD PTR ");
13618           break;
13619         default:
13620           abort ();
13621         }
13622       break;
13623     case xmmqd_mode:
13624       if (!need_vex)
13625         abort ();
13626
13627       switch (vex.length)
13628         {
13629         case 128:
13630           oappend ("DWORD PTR ");
13631           break;
13632         case 256:
13633           oappend ("QWORD PTR ");
13634           break;
13635         case 512:
13636           oappend ("XMMWORD PTR ");
13637           break;
13638         default:
13639           abort ();
13640         }
13641       break;
13642     case ymmq_mode:
13643       if (!need_vex)
13644         abort ();
13645
13646       switch (vex.length)
13647         {
13648         case 128:
13649           oappend ("QWORD PTR ");
13650           break;
13651         case 256:
13652           oappend ("YMMWORD PTR ");
13653           break;
13654         case 512:
13655           oappend ("ZMMWORD PTR ");
13656           break;
13657         default:
13658           abort ();
13659         }
13660       break;
13661     case ymmxmm_mode:
13662       if (!need_vex)
13663         abort ();
13664
13665       switch (vex.length)
13666         {
13667         case 128:
13668         case 256:
13669           oappend ("XMMWORD PTR ");
13670           break;
13671         default:
13672           abort ();
13673         }
13674       break;
13675     case o_mode:
13676       oappend ("OWORD PTR ");
13677       break;
13678     case xmm_mdq_mode:
13679     case vex_w_dq_mode:
13680     case vex_scalar_w_dq_mode:
13681       if (!need_vex)
13682         abort ();
13683
13684       if (vex.w)
13685         oappend ("QWORD PTR ");
13686       else
13687         oappend ("DWORD PTR ");
13688       break;
13689     case vex_vsib_d_w_dq_mode:
13690     case vex_vsib_q_w_dq_mode:
13691       if (!need_vex)
13692         abort ();
13693
13694       if (!vex.evex)
13695         {
13696           if (vex.w)
13697             oappend ("QWORD PTR ");
13698           else
13699             oappend ("DWORD PTR ");
13700         }
13701       else
13702         {
13703           switch (vex.length)
13704             {
13705             case 128:
13706               oappend ("XMMWORD PTR ");
13707               break;
13708             case 256:
13709               oappend ("YMMWORD PTR ");
13710               break;
13711             case 512:
13712               oappend ("ZMMWORD PTR ");
13713               break;
13714             default:
13715               abort ();
13716             }
13717         }
13718       break;
13719     case vex_vsib_q_w_d_mode:
13720     case vex_vsib_d_w_d_mode:
13721       if (!need_vex || !vex.evex)
13722         abort ();
13723
13724       switch (vex.length)
13725         {
13726         case 128:
13727           oappend ("QWORD PTR ");
13728           break;
13729         case 256:
13730           oappend ("XMMWORD PTR ");
13731           break;
13732         case 512:
13733           oappend ("YMMWORD PTR ");
13734           break;
13735         default:
13736           abort ();
13737         }
13738
13739       break;
13740     case mask_bd_mode:
13741       if (!need_vex || vex.length != 128)
13742         abort ();
13743       if (vex.w)
13744         oappend ("DWORD PTR ");
13745       else
13746         oappend ("BYTE PTR ");
13747       break;
13748     case mask_mode:
13749       if (!need_vex)
13750         abort ();
13751       if (vex.w)
13752         oappend ("QWORD PTR ");
13753       else
13754         oappend ("WORD PTR ");
13755       break;
13756     case v_bnd_mode:
13757     case v_bndmk_mode:
13758     default:
13759       break;
13760     }
13761 }
13762
13763 static void
13764 OP_E_register (int bytemode, int sizeflag)
13765 {
13766   int reg = modrm.rm;
13767   const char **names;
13768
13769   USED_REX (REX_B);
13770   if ((rex & REX_B))
13771     reg += 8;
13772
13773   if ((sizeflag & SUFFIX_ALWAYS)
13774       && (bytemode == b_swap_mode
13775           || bytemode == bnd_swap_mode
13776           || bytemode == v_swap_mode))
13777     swap_operand ();
13778
13779   switch (bytemode)
13780     {
13781     case b_mode:
13782     case b_swap_mode:
13783       USED_REX (0);
13784       if (rex)
13785         names = names8rex;
13786       else
13787         names = names8;
13788       break;
13789     case w_mode:
13790       names = names16;
13791       break;
13792     case d_mode:
13793     case dw_mode:
13794     case db_mode:
13795       names = names32;
13796       break;
13797     case q_mode:
13798       names = names64;
13799       break;
13800     case m_mode:
13801     case v_bnd_mode:
13802       names = address_mode == mode_64bit ? names64 : names32;
13803       break;
13804     case bnd_mode:
13805     case bnd_swap_mode:
13806       if (reg > 0x3)
13807         {
13808           oappend ("(bad)");
13809           return;
13810         }
13811       names = names_bnd;
13812       break;
13813     case indir_v_mode:
13814       if (address_mode == mode_64bit && isa64 == intel64)
13815         {
13816           names = names64;
13817           break;
13818         }
13819       /* Fall through.  */
13820     case stack_v_mode:
13821       if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13822         {
13823           names = names64;
13824           break;
13825         }
13826       bytemode = v_mode;
13827       /* Fall through.  */
13828     case v_mode:
13829     case v_swap_mode:
13830     case dq_mode:
13831     case dqb_mode:
13832     case dqd_mode:
13833     case dqw_mode:
13834       USED_REX (REX_W);
13835       if (rex & REX_W)
13836         names = names64;
13837       else
13838         {
13839           if ((sizeflag & DFLAG)
13840               || (bytemode != v_mode
13841                   && bytemode != v_swap_mode))
13842             names = names32;
13843           else
13844             names = names16;
13845           used_prefixes |= (prefixes & PREFIX_DATA);
13846         }
13847       break;
13848     case va_mode:
13849       names = (address_mode == mode_64bit
13850                ? names64 : names32);
13851       if (!(prefixes & PREFIX_ADDR))
13852         names = (address_mode == mode_16bit
13853                      ? names16 : names);
13854       else
13855         {
13856           /* Remove "addr16/addr32".  */
13857           all_prefixes[last_addr_prefix] = 0;
13858           names = (address_mode != mode_32bit
13859                        ? names32 : names16);
13860           used_prefixes |= PREFIX_ADDR;
13861         }
13862       break;
13863     case mask_bd_mode:
13864     case mask_mode:
13865       if (reg > 0x7)
13866         {
13867           oappend ("(bad)");
13868           return;
13869         }
13870       names = names_mask;
13871       break;
13872     case 0:
13873       return;
13874     default:
13875       oappend (INTERNAL_DISASSEMBLER_ERROR);
13876       return;
13877     }
13878   oappend (names[reg]);
13879 }
13880
13881 static void
13882 OP_E_memory (int bytemode, int sizeflag)
13883 {
13884   bfd_vma disp = 0;
13885   int add = (rex & REX_B) ? 8 : 0;
13886   int riprel = 0;
13887   int shift;
13888
13889   if (vex.evex)
13890     {
13891       /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
13892       if (vex.b
13893           && bytemode != x_mode
13894           && bytemode != xmmq_mode
13895           && bytemode != evex_half_bcst_xmmq_mode)
13896         {
13897           BadOp ();
13898           return;
13899         }
13900       switch (bytemode)
13901         {
13902         case dqw_mode:
13903         case dw_mode:
13904           shift = 1;
13905           break;
13906         case dqb_mode:
13907         case db_mode:
13908           shift = 0;
13909           break;
13910         case dq_mode:
13911           if (address_mode != mode_64bit)
13912             {
13913               shift = 2;
13914               break;
13915             }
13916             /* fall through */
13917         case vex_vsib_d_w_dq_mode:
13918         case vex_vsib_d_w_d_mode:
13919         case vex_vsib_q_w_dq_mode:
13920         case vex_vsib_q_w_d_mode:
13921         case evex_x_gscat_mode:
13922         case xmm_mdq_mode:
13923           shift = vex.w ? 3 : 2;
13924           break;
13925         case x_mode:
13926         case evex_half_bcst_xmmq_mode:
13927         case xmmq_mode:
13928           if (vex.b)
13929             {
13930               shift = vex.w ? 3 : 2;
13931               break;
13932             }
13933           /* Fall through.  */
13934         case xmmqd_mode:
13935         case xmmdw_mode:
13936         case ymmq_mode:
13937         case evex_x_nobcst_mode:
13938         case x_swap_mode:
13939           switch (vex.length)
13940             {
13941             case 128:
13942               shift = 4;
13943               break;
13944             case 256:
13945               shift = 5;
13946               break;
13947             case 512:
13948               shift = 6;
13949               break;
13950             default:
13951               abort ();
13952             }
13953           break;
13954         case ymm_mode:
13955           shift = 5;
13956           break;
13957         case xmm_mode:
13958           shift = 4;
13959           break;
13960         case xmm_mq_mode:
13961         case q_mode:
13962         case q_scalar_mode:
13963         case q_swap_mode:
13964         case q_scalar_swap_mode:
13965           shift = 3;
13966           break;
13967         case dqd_mode:
13968         case xmm_md_mode:
13969         case d_mode:
13970         case d_scalar_mode:
13971         case d_swap_mode:
13972         case d_scalar_swap_mode:
13973           shift = 2;
13974           break;
13975         case w_scalar_mode:
13976         case xmm_mw_mode:
13977           shift = 1;
13978           break;
13979         case b_scalar_mode:
13980         case xmm_mb_mode:
13981           shift = 0;
13982           break;
13983         default:
13984           abort ();
13985         }
13986       /* Make necessary corrections to shift for modes that need it.
13987          For these modes we currently have shift 4, 5 or 6 depending on
13988          vex.length (it corresponds to xmmword, ymmword or zmmword
13989          operand).  We might want to make it 3, 4 or 5 (e.g. for
13990          xmmq_mode).  In case of broadcast enabled the corrections
13991          aren't needed, as element size is always 32 or 64 bits.  */
13992       if (!vex.b
13993           && (bytemode == xmmq_mode
13994               || bytemode == evex_half_bcst_xmmq_mode))
13995         shift -= 1;
13996       else if (bytemode == xmmqd_mode)
13997         shift -= 2;
13998       else if (bytemode == xmmdw_mode)
13999         shift -= 3;
14000       else if (bytemode == ymmq_mode && vex.length == 128)
14001         shift -= 1;
14002     }
14003   else
14004     shift = 0;
14005
14006   USED_REX (REX_B);
14007   if (intel_syntax)
14008     intel_operand_size (bytemode, sizeflag);
14009   append_seg ();
14010
14011   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14012     {
14013       /* 32/64 bit address mode */
14014       int havedisp;
14015       int havesib;
14016       int havebase;
14017       int haveindex;
14018       int needindex;
14019       int needaddr32;
14020       int base, rbase;
14021       int vindex = 0;
14022       int scale = 0;
14023       int addr32flag = !((sizeflag & AFLAG)
14024                          || bytemode == v_bnd_mode
14025                          || bytemode == v_bndmk_mode
14026                          || bytemode == bnd_mode
14027                          || bytemode == bnd_swap_mode);
14028       const char **indexes64 = names64;
14029       const char **indexes32 = names32;
14030
14031       havesib = 0;
14032       havebase = 1;
14033       haveindex = 0;
14034       base = modrm.rm;
14035
14036       if (base == 4)
14037         {
14038           havesib = 1;
14039           vindex = sib.index;
14040           USED_REX (REX_X);
14041           if (rex & REX_X)
14042             vindex += 8;
14043           switch (bytemode)
14044             {
14045             case vex_vsib_d_w_dq_mode:
14046             case vex_vsib_d_w_d_mode:
14047             case vex_vsib_q_w_dq_mode:
14048             case vex_vsib_q_w_d_mode:
14049               if (!need_vex)
14050                 abort ();
14051               if (vex.evex)
14052                 {
14053                   if (!vex.v)
14054                     vindex += 16;
14055                 }
14056
14057               haveindex = 1;
14058               switch (vex.length)
14059                 {
14060                 case 128:
14061                   indexes64 = indexes32 = names_xmm;
14062                   break;
14063                 case 256:
14064                   if (!vex.w
14065                       || bytemode == vex_vsib_q_w_dq_mode
14066                       || bytemode == vex_vsib_q_w_d_mode)
14067                     indexes64 = indexes32 = names_ymm;
14068                   else
14069                     indexes64 = indexes32 = names_xmm;
14070                   break;
14071                 case 512:
14072                   if (!vex.w
14073                       || bytemode == vex_vsib_q_w_dq_mode
14074                       || bytemode == vex_vsib_q_w_d_mode)
14075                     indexes64 = indexes32 = names_zmm;
14076                   else
14077                     indexes64 = indexes32 = names_ymm;
14078                   break;
14079                 default:
14080                   abort ();
14081                 }
14082               break;
14083             default:
14084               haveindex = vindex != 4;
14085               break;
14086             }
14087           scale = sib.scale;
14088           base = sib.base;
14089           codep++;
14090         }
14091       rbase = base + add;
14092
14093       switch (modrm.mod)
14094         {
14095         case 0:
14096           if (base == 5)
14097             {
14098               havebase = 0;
14099               if (address_mode == mode_64bit && !havesib)
14100                 riprel = 1;
14101               disp = get32s ();
14102               if (riprel && bytemode == v_bndmk_mode)
14103                 {
14104                   oappend ("(bad)");
14105                   return;
14106                 }
14107             }
14108           break;
14109         case 1:
14110           FETCH_DATA (the_info, codep + 1);
14111           disp = *codep++;
14112           if ((disp & 0x80) != 0)
14113             disp -= 0x100;
14114           if (vex.evex && shift > 0)
14115             disp <<= shift;
14116           break;
14117         case 2:
14118           disp = get32s ();
14119           break;
14120         }
14121
14122       needindex = 0;
14123       needaddr32 = 0;
14124       if (havesib
14125           && !havebase
14126           && !haveindex
14127           && address_mode != mode_16bit)
14128         {
14129           if (address_mode == mode_64bit)
14130             {
14131               /* Display eiz instead of addr32.  */
14132               needindex = addr32flag;
14133               needaddr32 = 1;
14134             }
14135           else
14136             {
14137               /* In 32-bit mode, we need index register to tell [offset]
14138                  from [eiz*1 + offset].  */
14139               needindex = 1;
14140             }
14141         }
14142
14143       havedisp = (havebase
14144                   || needindex
14145                   || (havesib && (haveindex || scale != 0)));
14146
14147       if (!intel_syntax)
14148         if (modrm.mod != 0 || base == 5)
14149           {
14150             if (havedisp || riprel)
14151               print_displacement (scratchbuf, disp);
14152             else
14153               print_operand_value (scratchbuf, 1, disp);
14154             oappend (scratchbuf);
14155             if (riprel)
14156               {
14157                 set_op (disp, 1);
14158                 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14159               }
14160           }
14161
14162       if ((havebase || haveindex || needindex || needaddr32 || riprel)
14163           && (bytemode != v_bnd_mode)
14164           && (bytemode != v_bndmk_mode)
14165           && (bytemode != bnd_mode)
14166           && (bytemode != bnd_swap_mode))
14167         used_prefixes |= PREFIX_ADDR;
14168
14169       if (havedisp || (intel_syntax && riprel))
14170         {
14171           *obufp++ = open_char;
14172           if (intel_syntax && riprel)
14173             {
14174               set_op (disp, 1);
14175               oappend (!addr32flag ? "rip" : "eip");
14176             }
14177           *obufp = '\0';
14178           if (havebase)
14179             oappend (address_mode == mode_64bit && !addr32flag
14180                      ? names64[rbase] : names32[rbase]);
14181           if (havesib)
14182             {
14183               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
14184                  print index to tell base + index from base.  */
14185               if (scale != 0
14186                   || needindex
14187                   || haveindex
14188                   || (havebase && base != ESP_REG_NUM))
14189                 {
14190                   if (!intel_syntax || havebase)
14191                     {
14192                       *obufp++ = separator_char;
14193                       *obufp = '\0';
14194                     }
14195                   if (haveindex)
14196                     oappend (address_mode == mode_64bit && !addr32flag
14197                              ? indexes64[vindex] : indexes32[vindex]);
14198                   else
14199                     oappend (address_mode == mode_64bit && !addr32flag
14200                              ? index64 : index32);
14201
14202                   *obufp++ = scale_char;
14203                   *obufp = '\0';
14204                   sprintf (scratchbuf, "%d", 1 << scale);
14205                   oappend (scratchbuf);
14206                 }
14207             }
14208           if (intel_syntax
14209               && (disp || modrm.mod != 0 || base == 5))
14210             {
14211               if (!havedisp || (bfd_signed_vma) disp >= 0)
14212                 {
14213                   *obufp++ = '+';
14214                   *obufp = '\0';
14215                 }
14216               else if (modrm.mod != 1 && disp != -disp)
14217                 {
14218                   *obufp++ = '-';
14219                   *obufp = '\0';
14220                   disp = - (bfd_signed_vma) disp;
14221                 }
14222
14223               if (havedisp)
14224                 print_displacement (scratchbuf, disp);
14225               else
14226                 print_operand_value (scratchbuf, 1, disp);
14227               oappend (scratchbuf);
14228             }
14229
14230           *obufp++ = close_char;
14231           *obufp = '\0';
14232         }
14233       else if (intel_syntax)
14234         {
14235           if (modrm.mod != 0 || base == 5)
14236             {
14237               if (!active_seg_prefix)
14238                 {
14239                   oappend (names_seg[ds_reg - es_reg]);
14240                   oappend (":");
14241                 }
14242               print_operand_value (scratchbuf, 1, disp);
14243               oappend (scratchbuf);
14244             }
14245         }
14246     }
14247   else
14248     {
14249       /* 16 bit address mode */
14250       used_prefixes |= prefixes & PREFIX_ADDR;
14251       switch (modrm.mod)
14252         {
14253         case 0:
14254           if (modrm.rm == 6)
14255             {
14256               disp = get16 ();
14257               if ((disp & 0x8000) != 0)
14258                 disp -= 0x10000;
14259             }
14260           break;
14261         case 1:
14262           FETCH_DATA (the_info, codep + 1);
14263           disp = *codep++;
14264           if ((disp & 0x80) != 0)
14265             disp -= 0x100;
14266           if (vex.evex && shift > 0)
14267             disp <<= shift;
14268           break;
14269         case 2:
14270           disp = get16 ();
14271           if ((disp & 0x8000) != 0)
14272             disp -= 0x10000;
14273           break;
14274         }
14275
14276       if (!intel_syntax)
14277         if (modrm.mod != 0 || modrm.rm == 6)
14278           {
14279             print_displacement (scratchbuf, disp);
14280             oappend (scratchbuf);
14281           }
14282
14283       if (modrm.mod != 0 || modrm.rm != 6)
14284         {
14285           *obufp++ = open_char;
14286           *obufp = '\0';
14287           oappend (index16[modrm.rm]);
14288           if (intel_syntax
14289               && (disp || modrm.mod != 0 || modrm.rm == 6))
14290             {
14291               if ((bfd_signed_vma) disp >= 0)
14292                 {
14293                   *obufp++ = '+';
14294                   *obufp = '\0';
14295                 }
14296               else if (modrm.mod != 1)
14297                 {
14298                   *obufp++ = '-';
14299                   *obufp = '\0';
14300                   disp = - (bfd_signed_vma) disp;
14301                 }
14302
14303               print_displacement (scratchbuf, disp);
14304               oappend (scratchbuf);
14305             }
14306
14307           *obufp++ = close_char;
14308           *obufp = '\0';
14309         }
14310       else if (intel_syntax)
14311         {
14312           if (!active_seg_prefix)
14313             {
14314               oappend (names_seg[ds_reg - es_reg]);
14315               oappend (":");
14316             }
14317           print_operand_value (scratchbuf, 1, disp & 0xffff);
14318           oappend (scratchbuf);
14319         }
14320     }
14321   if (vex.evex && vex.b
14322       && (bytemode == x_mode
14323           || bytemode == xmmq_mode
14324           || bytemode == evex_half_bcst_xmmq_mode))
14325     {
14326       if (vex.w
14327           || bytemode == xmmq_mode
14328           || bytemode == evex_half_bcst_xmmq_mode)
14329         {
14330           switch (vex.length)
14331             {
14332             case 128:
14333               oappend ("{1to2}");
14334               break;
14335             case 256:
14336               oappend ("{1to4}");
14337               break;
14338             case 512:
14339               oappend ("{1to8}");
14340               break;
14341             default:
14342               abort ();
14343             }
14344         }
14345       else
14346         {
14347           switch (vex.length)
14348             {
14349             case 128:
14350               oappend ("{1to4}");
14351               break;
14352             case 256:
14353               oappend ("{1to8}");
14354               break;
14355             case 512:
14356               oappend ("{1to16}");
14357               break;
14358             default:
14359               abort ();
14360             }
14361         }
14362     }
14363 }
14364
14365 static void
14366 OP_E (int bytemode, int sizeflag)
14367 {
14368   /* Skip mod/rm byte.  */
14369   MODRM_CHECK;
14370   codep++;
14371
14372   if (modrm.mod == 3)
14373     OP_E_register (bytemode, sizeflag);
14374   else
14375     OP_E_memory (bytemode, sizeflag);
14376 }
14377
14378 static void
14379 OP_G (int bytemode, int sizeflag)
14380 {
14381   int add = 0;
14382   const char **names;
14383   USED_REX (REX_R);
14384   if (rex & REX_R)
14385     add += 8;
14386   switch (bytemode)
14387     {
14388     case b_mode:
14389       USED_REX (0);
14390       if (rex)
14391         oappend (names8rex[modrm.reg + add]);
14392       else
14393         oappend (names8[modrm.reg + add]);
14394       break;
14395     case w_mode:
14396       oappend (names16[modrm.reg + add]);
14397       break;
14398     case d_mode:
14399     case db_mode:
14400     case dw_mode:
14401       oappend (names32[modrm.reg + add]);
14402       break;
14403     case q_mode:
14404       oappend (names64[modrm.reg + add]);
14405       break;
14406     case bnd_mode:
14407       if (modrm.reg > 0x3)
14408         {
14409           oappend ("(bad)");
14410           return;
14411         }
14412       oappend (names_bnd[modrm.reg]);
14413       break;
14414     case v_mode:
14415     case dq_mode:
14416     case dqb_mode:
14417     case dqd_mode:
14418     case dqw_mode:
14419       USED_REX (REX_W);
14420       if (rex & REX_W)
14421         oappend (names64[modrm.reg + add]);
14422       else
14423         {
14424           if ((sizeflag & DFLAG) || bytemode != v_mode)
14425             oappend (names32[modrm.reg + add]);
14426           else
14427             oappend (names16[modrm.reg + add]);
14428           used_prefixes |= (prefixes & PREFIX_DATA);
14429         }
14430       break;
14431     case va_mode:
14432       names = (address_mode == mode_64bit
14433                ? names64 : names32);
14434       if (!(prefixes & PREFIX_ADDR))
14435         {
14436           if (address_mode == mode_16bit)
14437             names = names16;
14438         }
14439       else
14440         {
14441           /* Remove "addr16/addr32".  */
14442           all_prefixes[last_addr_prefix] = 0;
14443           names = (address_mode != mode_32bit
14444                        ? names32 : names16);
14445           used_prefixes |= PREFIX_ADDR;
14446         }
14447       oappend (names[modrm.reg + add]);
14448       break;
14449     case m_mode:
14450       if (address_mode == mode_64bit)
14451         oappend (names64[modrm.reg + add]);
14452       else
14453         oappend (names32[modrm.reg + add]);
14454       break;
14455     case mask_bd_mode:
14456     case mask_mode:
14457       if ((modrm.reg + add) > 0x7)
14458         {
14459           oappend ("(bad)");
14460           return;
14461         }
14462       oappend (names_mask[modrm.reg + add]);
14463       break;
14464     default:
14465       oappend (INTERNAL_DISASSEMBLER_ERROR);
14466       break;
14467     }
14468 }
14469
14470 static bfd_vma
14471 get64 (void)
14472 {
14473   bfd_vma x;
14474 #ifdef BFD64
14475   unsigned int a;
14476   unsigned int b;
14477
14478   FETCH_DATA (the_info, codep + 8);
14479   a = *codep++ & 0xff;
14480   a |= (*codep++ & 0xff) << 8;
14481   a |= (*codep++ & 0xff) << 16;
14482   a |= (*codep++ & 0xffu) << 24;
14483   b = *codep++ & 0xff;
14484   b |= (*codep++ & 0xff) << 8;
14485   b |= (*codep++ & 0xff) << 16;
14486   b |= (*codep++ & 0xffu) << 24;
14487   x = a + ((bfd_vma) b << 32);
14488 #else
14489   abort ();
14490   x = 0;
14491 #endif
14492   return x;
14493 }
14494
14495 static bfd_signed_vma
14496 get32 (void)
14497 {
14498   bfd_signed_vma x = 0;
14499
14500   FETCH_DATA (the_info, codep + 4);
14501   x = *codep++ & (bfd_signed_vma) 0xff;
14502   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14503   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14504   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14505   return x;
14506 }
14507
14508 static bfd_signed_vma
14509 get32s (void)
14510 {
14511   bfd_signed_vma x = 0;
14512
14513   FETCH_DATA (the_info, codep + 4);
14514   x = *codep++ & (bfd_signed_vma) 0xff;
14515   x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14516   x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14517   x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14518
14519   x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14520
14521   return x;
14522 }
14523
14524 static int
14525 get16 (void)
14526 {
14527   int x = 0;
14528
14529   FETCH_DATA (the_info, codep + 2);
14530   x = *codep++ & 0xff;
14531   x |= (*codep++ & 0xff) << 8;
14532   return x;
14533 }
14534
14535 static void
14536 set_op (bfd_vma op, int riprel)
14537 {
14538   op_index[op_ad] = op_ad;
14539   if (address_mode == mode_64bit)
14540     {
14541       op_address[op_ad] = op;
14542       op_riprel[op_ad] = riprel;
14543     }
14544   else
14545     {
14546       /* Mask to get a 32-bit address.  */
14547       op_address[op_ad] = op & 0xffffffff;
14548       op_riprel[op_ad] = riprel & 0xffffffff;
14549     }
14550 }
14551
14552 static void
14553 OP_REG (int code, int sizeflag)
14554 {
14555   const char *s;
14556   int add;
14557
14558   switch (code)
14559     {
14560     case es_reg: case ss_reg: case cs_reg:
14561     case ds_reg: case fs_reg: case gs_reg:
14562       oappend (names_seg[code - es_reg]);
14563       return;
14564     }
14565
14566   USED_REX (REX_B);
14567   if (rex & REX_B)
14568     add = 8;
14569   else
14570     add = 0;
14571
14572   switch (code)
14573     {
14574     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14575     case sp_reg: case bp_reg: case si_reg: case di_reg:
14576       s = names16[code - ax_reg + add];
14577       break;
14578     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14579     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14580       USED_REX (0);
14581       if (rex)
14582         s = names8rex[code - al_reg + add];
14583       else
14584         s = names8[code - al_reg];
14585       break;
14586     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14587     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14588       if (address_mode == mode_64bit
14589           && ((sizeflag & DFLAG) || (rex & REX_W)))
14590         {
14591           s = names64[code - rAX_reg + add];
14592           break;
14593         }
14594       code += eAX_reg - rAX_reg;
14595       /* Fall through.  */
14596     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14597     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14598       USED_REX (REX_W);
14599       if (rex & REX_W)
14600         s = names64[code - eAX_reg + add];
14601       else
14602         {
14603           if (sizeflag & DFLAG)
14604             s = names32[code - eAX_reg + add];
14605           else
14606             s = names16[code - eAX_reg + add];
14607           used_prefixes |= (prefixes & PREFIX_DATA);
14608         }
14609       break;
14610     default:
14611       s = INTERNAL_DISASSEMBLER_ERROR;
14612       break;
14613     }
14614   oappend (s);
14615 }
14616
14617 static void
14618 OP_IMREG (int code, int sizeflag)
14619 {
14620   const char *s;
14621
14622   switch (code)
14623     {
14624     case indir_dx_reg:
14625       if (intel_syntax)
14626         s = "dx";
14627       else
14628         s = "(%dx)";
14629       break;
14630     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14631     case sp_reg: case bp_reg: case si_reg: case di_reg:
14632       s = names16[code - ax_reg];
14633       break;
14634     case es_reg: case ss_reg: case cs_reg:
14635     case ds_reg: case fs_reg: case gs_reg:
14636       s = names_seg[code - es_reg];
14637       break;
14638     case al_reg: case ah_reg: case cl_reg: case ch_reg:
14639     case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14640       USED_REX (0);
14641       if (rex)
14642         s = names8rex[code - al_reg];
14643       else
14644         s = names8[code - al_reg];
14645       break;
14646     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14647     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14648       USED_REX (REX_W);
14649       if (rex & REX_W)
14650         s = names64[code - eAX_reg];
14651       else
14652         {
14653           if (sizeflag & DFLAG)
14654             s = names32[code - eAX_reg];
14655           else
14656             s = names16[code - eAX_reg];
14657           used_prefixes |= (prefixes & PREFIX_DATA);
14658         }
14659       break;
14660     case z_mode_ax_reg:
14661       if ((rex & REX_W) || (sizeflag & DFLAG))
14662         s = *names32;
14663       else
14664         s = *names16;
14665       if (!(rex & REX_W))
14666         used_prefixes |= (prefixes & PREFIX_DATA);
14667       break;
14668     default:
14669       s = INTERNAL_DISASSEMBLER_ERROR;
14670       break;
14671     }
14672   oappend (s);
14673 }
14674
14675 static void
14676 OP_I (int bytemode, int sizeflag)
14677 {
14678   bfd_signed_vma op;
14679   bfd_signed_vma mask = -1;
14680
14681   switch (bytemode)
14682     {
14683     case b_mode:
14684       FETCH_DATA (the_info, codep + 1);
14685       op = *codep++;
14686       mask = 0xff;
14687       break;
14688     case v_mode:
14689       USED_REX (REX_W);
14690       if (rex & REX_W)
14691         op = get32s ();
14692       else
14693         {
14694           if (sizeflag & DFLAG)
14695             {
14696               op = get32 ();
14697               mask = 0xffffffff;
14698             }
14699           else
14700             {
14701               op = get16 ();
14702               mask = 0xfffff;
14703             }
14704           used_prefixes |= (prefixes & PREFIX_DATA);
14705         }
14706       break;
14707     case d_mode:
14708       mask = 0xffffffff;
14709       op = get32 ();
14710       break;
14711     case w_mode:
14712       mask = 0xfffff;
14713       op = get16 ();
14714       break;
14715     case const_1_mode:
14716       if (intel_syntax)
14717         oappend ("1");
14718       return;
14719     default:
14720       oappend (INTERNAL_DISASSEMBLER_ERROR);
14721       return;
14722     }
14723
14724   op &= mask;
14725   scratchbuf[0] = '$';
14726   print_operand_value (scratchbuf + 1, 1, op);
14727   oappend_maybe_intel (scratchbuf);
14728   scratchbuf[0] = '\0';
14729 }
14730
14731 static void
14732 OP_I64 (int bytemode, int sizeflag)
14733 {
14734   if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14735     {
14736       OP_I (bytemode, sizeflag);
14737       return;
14738     }
14739
14740   USED_REX (REX_W);
14741
14742   scratchbuf[0] = '$';
14743   print_operand_value (scratchbuf + 1, 1, get64 ());
14744   oappend_maybe_intel (scratchbuf);
14745   scratchbuf[0] = '\0';
14746 }
14747
14748 static void
14749 OP_sI (int bytemode, int sizeflag)
14750 {
14751   bfd_signed_vma op;
14752
14753   switch (bytemode)
14754     {
14755     case b_mode:
14756     case b_T_mode:
14757       FETCH_DATA (the_info, codep + 1);
14758       op = *codep++;
14759       if ((op & 0x80) != 0)
14760         op -= 0x100;
14761       if (bytemode == b_T_mode)
14762         {
14763           if (address_mode != mode_64bit
14764               || !((sizeflag & DFLAG) || (rex & REX_W)))
14765             {
14766               /* The operand-size prefix is overridden by a REX prefix.  */
14767               if ((sizeflag & DFLAG) || (rex & REX_W))
14768                 op &= 0xffffffff;
14769               else
14770                 op &= 0xffff;
14771           }
14772         }
14773       else
14774         {
14775           if (!(rex & REX_W))
14776             {
14777               if (sizeflag & DFLAG)
14778                 op &= 0xffffffff;
14779               else
14780                 op &= 0xffff;
14781             }
14782         }
14783       break;
14784     case v_mode:
14785       /* The operand-size prefix is overridden by a REX prefix.  */
14786       if ((sizeflag & DFLAG) || (rex & REX_W))
14787         op = get32s ();
14788       else
14789         op = get16 ();
14790       break;
14791     default:
14792       oappend (INTERNAL_DISASSEMBLER_ERROR);
14793       return;
14794     }
14795
14796   scratchbuf[0] = '$';
14797   print_operand_value (scratchbuf + 1, 1, op);
14798   oappend_maybe_intel (scratchbuf);
14799 }
14800
14801 static void
14802 OP_J (int bytemode, int sizeflag)
14803 {
14804   bfd_vma disp;
14805   bfd_vma mask = -1;
14806   bfd_vma segment = 0;
14807
14808   switch (bytemode)
14809     {
14810     case b_mode:
14811       FETCH_DATA (the_info, codep + 1);
14812       disp = *codep++;
14813       if ((disp & 0x80) != 0)
14814         disp -= 0x100;
14815       break;
14816     case v_mode:
14817       if (isa64 == amd64)
14818         USED_REX (REX_W);
14819       if ((sizeflag & DFLAG)
14820           || (address_mode == mode_64bit
14821               && (isa64 != amd64 || (rex & REX_W))))
14822         disp = get32s ();
14823       else
14824         {
14825           disp = get16 ();
14826           if ((disp & 0x8000) != 0)
14827             disp -= 0x10000;
14828           /* In 16bit mode, address is wrapped around at 64k within
14829              the same segment.  Otherwise, a data16 prefix on a jump
14830              instruction means that the pc is masked to 16 bits after
14831              the displacement is added!  */
14832           mask = 0xffff;
14833           if ((prefixes & PREFIX_DATA) == 0)
14834             segment = ((start_pc + (codep - start_codep))
14835                        & ~((bfd_vma) 0xffff));
14836         }
14837       if (address_mode != mode_64bit
14838           || (isa64 == amd64 && !(rex & REX_W)))
14839         used_prefixes |= (prefixes & PREFIX_DATA);
14840       break;
14841     default:
14842       oappend (INTERNAL_DISASSEMBLER_ERROR);
14843       return;
14844     }
14845   disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14846   set_op (disp, 0);
14847   print_operand_value (scratchbuf, 1, disp);
14848   oappend (scratchbuf);
14849 }
14850
14851 static void
14852 OP_SEG (int bytemode, int sizeflag)
14853 {
14854   if (bytemode == w_mode)
14855     oappend (names_seg[modrm.reg]);
14856   else
14857     OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14858 }
14859
14860 static void
14861 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14862 {
14863   int seg, offset;
14864
14865   if (sizeflag & DFLAG)
14866     {
14867       offset = get32 ();
14868       seg = get16 ();
14869     }
14870   else
14871     {
14872       offset = get16 ();
14873       seg = get16 ();
14874     }
14875   used_prefixes |= (prefixes & PREFIX_DATA);
14876   if (intel_syntax)
14877     sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14878   else
14879     sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14880   oappend (scratchbuf);
14881 }
14882
14883 static void
14884 OP_OFF (int bytemode, int sizeflag)
14885 {
14886   bfd_vma off;
14887
14888   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14889     intel_operand_size (bytemode, sizeflag);
14890   append_seg ();
14891
14892   if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14893     off = get32 ();
14894   else
14895     off = get16 ();
14896
14897   if (intel_syntax)
14898     {
14899       if (!active_seg_prefix)
14900         {
14901           oappend (names_seg[ds_reg - es_reg]);
14902           oappend (":");
14903         }
14904     }
14905   print_operand_value (scratchbuf, 1, off);
14906   oappend (scratchbuf);
14907 }
14908
14909 static void
14910 OP_OFF64 (int bytemode, int sizeflag)
14911 {
14912   bfd_vma off;
14913
14914   if (address_mode != mode_64bit
14915       || (prefixes & PREFIX_ADDR))
14916     {
14917       OP_OFF (bytemode, sizeflag);
14918       return;
14919     }
14920
14921   if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14922     intel_operand_size (bytemode, sizeflag);
14923   append_seg ();
14924
14925   off = get64 ();
14926
14927   if (intel_syntax)
14928     {
14929       if (!active_seg_prefix)
14930         {
14931           oappend (names_seg[ds_reg - es_reg]);
14932           oappend (":");
14933         }
14934     }
14935   print_operand_value (scratchbuf, 1, off);
14936   oappend (scratchbuf);
14937 }
14938
14939 static void
14940 ptr_reg (int code, int sizeflag)
14941 {
14942   const char *s;
14943
14944   *obufp++ = open_char;
14945   used_prefixes |= (prefixes & PREFIX_ADDR);
14946   if (address_mode == mode_64bit)
14947     {
14948       if (!(sizeflag & AFLAG))
14949         s = names32[code - eAX_reg];
14950       else
14951         s = names64[code - eAX_reg];
14952     }
14953   else if (sizeflag & AFLAG)
14954     s = names32[code - eAX_reg];
14955   else
14956     s = names16[code - eAX_reg];
14957   oappend (s);
14958   *obufp++ = close_char;
14959   *obufp = 0;
14960 }
14961
14962 static void
14963 OP_ESreg (int code, int sizeflag)
14964 {
14965   if (intel_syntax)
14966     {
14967       switch (codep[-1])
14968         {
14969         case 0x6d:      /* insw/insl */
14970           intel_operand_size (z_mode, sizeflag);
14971           break;
14972         case 0xa5:      /* movsw/movsl/movsq */
14973         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14974         case 0xab:      /* stosw/stosl */
14975         case 0xaf:      /* scasw/scasl */
14976           intel_operand_size (v_mode, sizeflag);
14977           break;
14978         default:
14979           intel_operand_size (b_mode, sizeflag);
14980         }
14981     }
14982   oappend_maybe_intel ("%es:");
14983   ptr_reg (code, sizeflag);
14984 }
14985
14986 static void
14987 OP_DSreg (int code, int sizeflag)
14988 {
14989   if (intel_syntax)
14990     {
14991       switch (codep[-1])
14992         {
14993         case 0x6f:      /* outsw/outsl */
14994           intel_operand_size (z_mode, sizeflag);
14995           break;
14996         case 0xa5:      /* movsw/movsl/movsq */
14997         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
14998         case 0xad:      /* lodsw/lodsl/lodsq */
14999           intel_operand_size (v_mode, sizeflag);
15000           break;
15001         default:
15002           intel_operand_size (b_mode, sizeflag);
15003         }
15004     }
15005   /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15006      default segment register DS is printed.  */
15007   if (!active_seg_prefix)
15008     active_seg_prefix = PREFIX_DS;
15009   append_seg ();
15010   ptr_reg (code, sizeflag);
15011 }
15012
15013 static void
15014 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15015 {
15016   int add;
15017   if (rex & REX_R)
15018     {
15019       USED_REX (REX_R);
15020       add = 8;
15021     }
15022   else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15023     {
15024       all_prefixes[last_lock_prefix] = 0;
15025       used_prefixes |= PREFIX_LOCK;
15026       add = 8;
15027     }
15028   else
15029     add = 0;
15030   sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15031   oappend_maybe_intel (scratchbuf);
15032 }
15033
15034 static void
15035 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15036 {
15037   int add;
15038   USED_REX (REX_R);
15039   if (rex & REX_R)
15040     add = 8;
15041   else
15042     add = 0;
15043   if (intel_syntax)
15044     sprintf (scratchbuf, "db%d", modrm.reg + add);
15045   else
15046     sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15047   oappend (scratchbuf);
15048 }
15049
15050 static void
15051 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15052 {
15053   sprintf (scratchbuf, "%%tr%d", modrm.reg);
15054   oappend_maybe_intel (scratchbuf);
15055 }
15056
15057 static void
15058 OP_R (int bytemode, int sizeflag)
15059 {
15060   /* Skip mod/rm byte.  */
15061   MODRM_CHECK;
15062   codep++;
15063   OP_E_register (bytemode, sizeflag);
15064 }
15065
15066 static void
15067 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15068 {
15069   int reg = modrm.reg;
15070   const char **names;
15071
15072   used_prefixes |= (prefixes & PREFIX_DATA);
15073   if (prefixes & PREFIX_DATA)
15074     {
15075       names = names_xmm;
15076       USED_REX (REX_R);
15077       if (rex & REX_R)
15078         reg += 8;
15079     }
15080   else
15081     names = names_mm;
15082   oappend (names[reg]);
15083 }
15084
15085 static void
15086 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15087 {
15088   int reg = modrm.reg;
15089   const char **names;
15090
15091   USED_REX (REX_R);
15092   if (rex & REX_R)
15093     reg += 8;
15094   if (vex.evex)
15095     {
15096       if (!vex.r)
15097         reg += 16;
15098     }
15099
15100   if (need_vex
15101       && bytemode != xmm_mode
15102       && bytemode != xmmq_mode
15103       && bytemode != evex_half_bcst_xmmq_mode
15104       && bytemode != ymm_mode
15105       && bytemode != scalar_mode)
15106     {
15107       switch (vex.length)
15108         {
15109         case 128:
15110           names = names_xmm;
15111           break;
15112         case 256:
15113           if (vex.w
15114               || (bytemode != vex_vsib_q_w_dq_mode
15115                   && bytemode != vex_vsib_q_w_d_mode))
15116             names = names_ymm;
15117           else
15118             names = names_xmm;
15119           break;
15120         case 512:
15121           names = names_zmm;
15122           break;
15123         default:
15124           abort ();
15125         }
15126     }
15127   else if (bytemode == xmmq_mode
15128            || bytemode == evex_half_bcst_xmmq_mode)
15129     {
15130       switch (vex.length)
15131         {
15132         case 128:
15133         case 256:
15134           names = names_xmm;
15135           break;
15136         case 512:
15137           names = names_ymm;
15138           break;
15139         default:
15140           abort ();
15141         }
15142     }
15143   else if (bytemode == ymm_mode)
15144     names = names_ymm;
15145   else
15146     names = names_xmm;
15147   oappend (names[reg]);
15148 }
15149
15150 static void
15151 OP_EM (int bytemode, int sizeflag)
15152 {
15153   int reg;
15154   const char **names;
15155
15156   if (modrm.mod != 3)
15157     {
15158       if (intel_syntax
15159           && (bytemode == v_mode || bytemode == v_swap_mode))
15160         {
15161           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15162           used_prefixes |= (prefixes & PREFIX_DATA);
15163         }
15164       OP_E (bytemode, sizeflag);
15165       return;
15166     }
15167
15168   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15169     swap_operand ();
15170
15171   /* Skip mod/rm byte.  */
15172   MODRM_CHECK;
15173   codep++;
15174   used_prefixes |= (prefixes & PREFIX_DATA);
15175   reg = modrm.rm;
15176   if (prefixes & PREFIX_DATA)
15177     {
15178       names = names_xmm;
15179       USED_REX (REX_B);
15180       if (rex & REX_B)
15181         reg += 8;
15182     }
15183   else
15184     names = names_mm;
15185   oappend (names[reg]);
15186 }
15187
15188 /* cvt* are the only instructions in sse2 which have
15189    both SSE and MMX operands and also have 0x66 prefix
15190    in their opcode. 0x66 was originally used to differentiate
15191    between SSE and MMX instruction(operands). So we have to handle the
15192    cvt* separately using OP_EMC and OP_MXC */
15193 static void
15194 OP_EMC (int bytemode, int sizeflag)
15195 {
15196   if (modrm.mod != 3)
15197     {
15198       if (intel_syntax && bytemode == v_mode)
15199         {
15200           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15201           used_prefixes |= (prefixes & PREFIX_DATA);
15202         }
15203       OP_E (bytemode, sizeflag);
15204       return;
15205     }
15206
15207   /* Skip mod/rm byte.  */
15208   MODRM_CHECK;
15209   codep++;
15210   used_prefixes |= (prefixes & PREFIX_DATA);
15211   oappend (names_mm[modrm.rm]);
15212 }
15213
15214 static void
15215 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15216 {
15217   used_prefixes |= (prefixes & PREFIX_DATA);
15218   oappend (names_mm[modrm.reg]);
15219 }
15220
15221 static void
15222 OP_EX (int bytemode, int sizeflag)
15223 {
15224   int reg;
15225   const char **names;
15226
15227   /* Skip mod/rm byte.  */
15228   MODRM_CHECK;
15229   codep++;
15230
15231   if (modrm.mod != 3)
15232     {
15233       OP_E_memory (bytemode, sizeflag);
15234       return;
15235     }
15236
15237   reg = modrm.rm;
15238   USED_REX (REX_B);
15239   if (rex & REX_B)
15240     reg += 8;
15241   if (vex.evex)
15242     {
15243       USED_REX (REX_X);
15244       if ((rex & REX_X))
15245         reg += 16;
15246     }
15247
15248   if ((sizeflag & SUFFIX_ALWAYS)
15249       && (bytemode == x_swap_mode
15250           || bytemode == d_swap_mode
15251           || bytemode == d_scalar_swap_mode
15252           || bytemode == q_swap_mode
15253           || bytemode == q_scalar_swap_mode))
15254     swap_operand ();
15255
15256   if (need_vex
15257       && bytemode != xmm_mode
15258       && bytemode != xmmdw_mode
15259       && bytemode != xmmqd_mode
15260       && bytemode != xmm_mb_mode
15261       && bytemode != xmm_mw_mode
15262       && bytemode != xmm_md_mode
15263       && bytemode != xmm_mq_mode
15264       && bytemode != xmm_mdq_mode
15265       && bytemode != xmmq_mode
15266       && bytemode != evex_half_bcst_xmmq_mode
15267       && bytemode != ymm_mode
15268       && bytemode != d_scalar_mode
15269       && bytemode != d_scalar_swap_mode
15270       && bytemode != q_scalar_mode
15271       && bytemode != q_scalar_swap_mode
15272       && bytemode != vex_scalar_w_dq_mode)
15273     {
15274       switch (vex.length)
15275         {
15276         case 128:
15277           names = names_xmm;
15278           break;
15279         case 256:
15280           names = names_ymm;
15281           break;
15282         case 512:
15283           names = names_zmm;
15284           break;
15285         default:
15286           abort ();
15287         }
15288     }
15289   else if (bytemode == xmmq_mode
15290            || bytemode == evex_half_bcst_xmmq_mode)
15291     {
15292       switch (vex.length)
15293         {
15294         case 128:
15295         case 256:
15296           names = names_xmm;
15297           break;
15298         case 512:
15299           names = names_ymm;
15300           break;
15301         default:
15302           abort ();
15303         }
15304     }
15305   else if (bytemode == ymm_mode)
15306     names = names_ymm;
15307   else
15308     names = names_xmm;
15309   oappend (names[reg]);
15310 }
15311
15312 static void
15313 OP_MS (int bytemode, int sizeflag)
15314 {
15315   if (modrm.mod == 3)
15316     OP_EM (bytemode, sizeflag);
15317   else
15318     BadOp ();
15319 }
15320
15321 static void
15322 OP_XS (int bytemode, int sizeflag)
15323 {
15324   if (modrm.mod == 3)
15325     OP_EX (bytemode, sizeflag);
15326   else
15327     BadOp ();
15328 }
15329
15330 static void
15331 OP_M (int bytemode, int sizeflag)
15332 {
15333   if (modrm.mod == 3)
15334     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15335     BadOp ();
15336   else
15337     OP_E (bytemode, sizeflag);
15338 }
15339
15340 static void
15341 OP_0f07 (int bytemode, int sizeflag)
15342 {
15343   if (modrm.mod != 3 || modrm.rm != 0)
15344     BadOp ();
15345   else
15346     OP_E (bytemode, sizeflag);
15347 }
15348
15349 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15350    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
15351
15352 static void
15353 NOP_Fixup1 (int bytemode, int sizeflag)
15354 {
15355   if ((prefixes & PREFIX_DATA) != 0
15356       || (rex != 0
15357           && rex != 0x48
15358           && address_mode == mode_64bit))
15359     OP_REG (bytemode, sizeflag);
15360   else
15361     strcpy (obuf, "nop");
15362 }
15363
15364 static void
15365 NOP_Fixup2 (int bytemode, int sizeflag)
15366 {
15367   if ((prefixes & PREFIX_DATA) != 0
15368       || (rex != 0
15369           && rex != 0x48
15370           && address_mode == mode_64bit))
15371     OP_IMREG (bytemode, sizeflag);
15372 }
15373
15374 static const char *const Suffix3DNow[] = {
15375 /* 00 */        NULL,           NULL,           NULL,           NULL,
15376 /* 04 */        NULL,           NULL,           NULL,           NULL,
15377 /* 08 */        NULL,           NULL,           NULL,           NULL,
15378 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
15379 /* 10 */        NULL,           NULL,           NULL,           NULL,
15380 /* 14 */        NULL,           NULL,           NULL,           NULL,
15381 /* 18 */        NULL,           NULL,           NULL,           NULL,
15382 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
15383 /* 20 */        NULL,           NULL,           NULL,           NULL,
15384 /* 24 */        NULL,           NULL,           NULL,           NULL,
15385 /* 28 */        NULL,           NULL,           NULL,           NULL,
15386 /* 2C */        NULL,           NULL,           NULL,           NULL,
15387 /* 30 */        NULL,           NULL,           NULL,           NULL,
15388 /* 34 */        NULL,           NULL,           NULL,           NULL,
15389 /* 38 */        NULL,           NULL,           NULL,           NULL,
15390 /* 3C */        NULL,           NULL,           NULL,           NULL,
15391 /* 40 */        NULL,           NULL,           NULL,           NULL,
15392 /* 44 */        NULL,           NULL,           NULL,           NULL,
15393 /* 48 */        NULL,           NULL,           NULL,           NULL,
15394 /* 4C */        NULL,           NULL,           NULL,           NULL,
15395 /* 50 */        NULL,           NULL,           NULL,           NULL,
15396 /* 54 */        NULL,           NULL,           NULL,           NULL,
15397 /* 58 */        NULL,           NULL,           NULL,           NULL,
15398 /* 5C */        NULL,           NULL,           NULL,           NULL,
15399 /* 60 */        NULL,           NULL,           NULL,           NULL,
15400 /* 64 */        NULL,           NULL,           NULL,           NULL,
15401 /* 68 */        NULL,           NULL,           NULL,           NULL,
15402 /* 6C */        NULL,           NULL,           NULL,           NULL,
15403 /* 70 */        NULL,           NULL,           NULL,           NULL,
15404 /* 74 */        NULL,           NULL,           NULL,           NULL,
15405 /* 78 */        NULL,           NULL,           NULL,           NULL,
15406 /* 7C */        NULL,           NULL,           NULL,           NULL,
15407 /* 80 */        NULL,           NULL,           NULL,           NULL,
15408 /* 84 */        NULL,           NULL,           NULL,           NULL,
15409 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
15410 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
15411 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
15412 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
15413 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
15414 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
15415 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
15416 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
15417 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
15418 /* AC */        NULL,           NULL,           "pfacc",        NULL,
15419 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
15420 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
15421 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
15422 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
15423 /* C0 */        NULL,           NULL,           NULL,           NULL,
15424 /* C4 */        NULL,           NULL,           NULL,           NULL,
15425 /* C8 */        NULL,           NULL,           NULL,           NULL,
15426 /* CC */        NULL,           NULL,           NULL,           NULL,
15427 /* D0 */        NULL,           NULL,           NULL,           NULL,
15428 /* D4 */        NULL,           NULL,           NULL,           NULL,
15429 /* D8 */        NULL,           NULL,           NULL,           NULL,
15430 /* DC */        NULL,           NULL,           NULL,           NULL,
15431 /* E0 */        NULL,           NULL,           NULL,           NULL,
15432 /* E4 */        NULL,           NULL,           NULL,           NULL,
15433 /* E8 */        NULL,           NULL,           NULL,           NULL,
15434 /* EC */        NULL,           NULL,           NULL,           NULL,
15435 /* F0 */        NULL,           NULL,           NULL,           NULL,
15436 /* F4 */        NULL,           NULL,           NULL,           NULL,
15437 /* F8 */        NULL,           NULL,           NULL,           NULL,
15438 /* FC */        NULL,           NULL,           NULL,           NULL,
15439 };
15440
15441 static void
15442 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15443 {
15444   const char *mnemonic;
15445
15446   FETCH_DATA (the_info, codep + 1);
15447   /* AMD 3DNow! instructions are specified by an opcode suffix in the
15448      place where an 8-bit immediate would normally go.  ie. the last
15449      byte of the instruction.  */
15450   obufp = mnemonicendp;
15451   mnemonic = Suffix3DNow[*codep++ & 0xff];
15452   if (mnemonic)
15453     oappend (mnemonic);
15454   else
15455     {
15456       /* Since a variable sized modrm/sib chunk is between the start
15457          of the opcode (0x0f0f) and the opcode suffix, we need to do
15458          all the modrm processing first, and don't know until now that
15459          we have a bad opcode.  This necessitates some cleaning up.  */
15460       op_out[0][0] = '\0';
15461       op_out[1][0] = '\0';
15462       BadOp ();
15463     }
15464   mnemonicendp = obufp;
15465 }
15466
15467 static struct op simd_cmp_op[] =
15468 {
15469   { STRING_COMMA_LEN ("eq") },
15470   { STRING_COMMA_LEN ("lt") },
15471   { STRING_COMMA_LEN ("le") },
15472   { STRING_COMMA_LEN ("unord") },
15473   { STRING_COMMA_LEN ("neq") },
15474   { STRING_COMMA_LEN ("nlt") },
15475   { STRING_COMMA_LEN ("nle") },
15476   { STRING_COMMA_LEN ("ord") }
15477 };
15478
15479 static void
15480 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15481 {
15482   unsigned int cmp_type;
15483
15484   FETCH_DATA (the_info, codep + 1);
15485   cmp_type = *codep++ & 0xff;
15486   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15487     {
15488       char suffix [3];
15489       char *p = mnemonicendp - 2;
15490       suffix[0] = p[0];
15491       suffix[1] = p[1];
15492       suffix[2] = '\0';
15493       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15494       mnemonicendp += simd_cmp_op[cmp_type].len;
15495     }
15496   else
15497     {
15498       /* We have a reserved extension byte.  Output it directly.  */
15499       scratchbuf[0] = '$';
15500       print_operand_value (scratchbuf + 1, 1, cmp_type);
15501       oappend_maybe_intel (scratchbuf);
15502       scratchbuf[0] = '\0';
15503     }
15504 }
15505
15506 static void
15507 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15508           int sizeflag ATTRIBUTE_UNUSED)
15509 {
15510   /* mwaitx %eax,%ecx,%ebx */
15511   if (!intel_syntax)
15512     {
15513       const char **names = (address_mode == mode_64bit
15514                             ? names64 : names32);
15515       strcpy (op_out[0], names[0]);
15516       strcpy (op_out[1], names[1]);
15517       strcpy (op_out[2], names[3]);
15518       two_source_ops = 1;
15519     }
15520   /* Skip mod/rm byte.  */
15521   MODRM_CHECK;
15522   codep++;
15523 }
15524
15525 static void
15526 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15527           int sizeflag ATTRIBUTE_UNUSED)
15528 {
15529   /* mwait %eax,%ecx  */
15530   if (!intel_syntax)
15531     {
15532       const char **names = (address_mode == mode_64bit
15533                             ? names64 : names32);
15534       strcpy (op_out[0], names[0]);
15535       strcpy (op_out[1], names[1]);
15536       two_source_ops = 1;
15537     }
15538   /* Skip mod/rm byte.  */
15539   MODRM_CHECK;
15540   codep++;
15541 }
15542
15543 static void
15544 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15545             int sizeflag ATTRIBUTE_UNUSED)
15546 {
15547   /* monitor %eax,%ecx,%edx"  */
15548   if (!intel_syntax)
15549     {
15550       const char **op1_names;
15551       const char **names = (address_mode == mode_64bit
15552                             ? names64 : names32);
15553
15554       if (!(prefixes & PREFIX_ADDR))
15555         op1_names = (address_mode == mode_16bit
15556                      ? names16 : names);
15557       else
15558         {
15559           /* Remove "addr16/addr32".  */
15560           all_prefixes[last_addr_prefix] = 0;
15561           op1_names = (address_mode != mode_32bit
15562                        ? names32 : names16);
15563           used_prefixes |= PREFIX_ADDR;
15564         }
15565       strcpy (op_out[0], op1_names[0]);
15566       strcpy (op_out[1], names[1]);
15567       strcpy (op_out[2], names[2]);
15568       two_source_ops = 1;
15569     }
15570   /* Skip mod/rm byte.  */
15571   MODRM_CHECK;
15572   codep++;
15573 }
15574
15575 static void
15576 BadOp (void)
15577 {
15578   /* Throw away prefixes and 1st. opcode byte.  */
15579   codep = insn_codep + 1;
15580   oappend ("(bad)");
15581 }
15582
15583 static void
15584 REP_Fixup (int bytemode, int sizeflag)
15585 {
15586   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15587      lods and stos.  */
15588   if (prefixes & PREFIX_REPZ)
15589     all_prefixes[last_repz_prefix] = REP_PREFIX;
15590
15591   switch (bytemode)
15592     {
15593     case al_reg:
15594     case eAX_reg:
15595     case indir_dx_reg:
15596       OP_IMREG (bytemode, sizeflag);
15597       break;
15598     case eDI_reg:
15599       OP_ESreg (bytemode, sizeflag);
15600       break;
15601     case eSI_reg:
15602       OP_DSreg (bytemode, sizeflag);
15603       break;
15604     default:
15605       abort ();
15606       break;
15607     }
15608 }
15609
15610 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15611    "bnd".  */
15612
15613 static void
15614 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15615 {
15616   if (prefixes & PREFIX_REPNZ)
15617     all_prefixes[last_repnz_prefix] = BND_PREFIX;
15618 }
15619
15620 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15621    "notrack".  */
15622
15623 static void
15624 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15625                int sizeflag ATTRIBUTE_UNUSED)
15626 {
15627   if (active_seg_prefix == PREFIX_DS
15628       && (address_mode != mode_64bit || last_data_prefix < 0))
15629     {
15630       /* NOTRACK prefix is only valid on indirect branch instructions.
15631          NB: DATA prefix is unsupported for Intel64.  */
15632       active_seg_prefix = 0;
15633       all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15634     }
15635 }
15636
15637 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15638    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15639  */
15640
15641 static void
15642 HLE_Fixup1 (int bytemode, int sizeflag)
15643 {
15644   if (modrm.mod != 3
15645       && (prefixes & PREFIX_LOCK) != 0)
15646     {
15647       if (prefixes & PREFIX_REPZ)
15648         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15649       if (prefixes & PREFIX_REPNZ)
15650         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15651     }
15652
15653   OP_E (bytemode, sizeflag);
15654 }
15655
15656 /* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
15657    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
15658  */
15659
15660 static void
15661 HLE_Fixup2 (int bytemode, int sizeflag)
15662 {
15663   if (modrm.mod != 3)
15664     {
15665       if (prefixes & PREFIX_REPZ)
15666         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15667       if (prefixes & PREFIX_REPNZ)
15668         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15669     }
15670
15671   OP_E (bytemode, sizeflag);
15672 }
15673
15674 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
15675    "xrelease" for memory operand.  No check for LOCK prefix.   */
15676
15677 static void
15678 HLE_Fixup3 (int bytemode, int sizeflag)
15679 {
15680   if (modrm.mod != 3
15681       && last_repz_prefix > last_repnz_prefix
15682       && (prefixes & PREFIX_REPZ) != 0)
15683     all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15684
15685   OP_E (bytemode, sizeflag);
15686 }
15687
15688 static void
15689 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15690 {
15691   USED_REX (REX_W);
15692   if (rex & REX_W)
15693     {
15694       /* Change cmpxchg8b to cmpxchg16b.  */
15695       char *p = mnemonicendp - 2;
15696       mnemonicendp = stpcpy (p, "16b");
15697       bytemode = o_mode;
15698     }
15699   else if ((prefixes & PREFIX_LOCK) != 0)
15700     {
15701       if (prefixes & PREFIX_REPZ)
15702         all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15703       if (prefixes & PREFIX_REPNZ)
15704         all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15705     }
15706
15707   OP_M (bytemode, sizeflag);
15708 }
15709
15710 static void
15711 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15712 {
15713   const char **names;
15714
15715   if (need_vex)
15716     {
15717       switch (vex.length)
15718         {
15719         case 128:
15720           names = names_xmm;
15721           break;
15722         case 256:
15723           names = names_ymm;
15724           break;
15725         default:
15726           abort ();
15727         }
15728     }
15729   else
15730     names = names_xmm;
15731   oappend (names[reg]);
15732 }
15733
15734 static void
15735 CRC32_Fixup (int bytemode, int sizeflag)
15736 {
15737   /* Add proper suffix to "crc32".  */
15738   char *p = mnemonicendp;
15739
15740   switch (bytemode)
15741     {
15742     case b_mode:
15743       if (intel_syntax)
15744         goto skip;
15745
15746       *p++ = 'b';
15747       break;
15748     case v_mode:
15749       if (intel_syntax)
15750         goto skip;
15751
15752       USED_REX (REX_W);
15753       if (rex & REX_W)
15754         *p++ = 'q';
15755       else
15756         {
15757           if (sizeflag & DFLAG)
15758             *p++ = 'l';
15759           else
15760             *p++ = 'w';
15761           used_prefixes |= (prefixes & PREFIX_DATA);
15762         }
15763       break;
15764     default:
15765       oappend (INTERNAL_DISASSEMBLER_ERROR);
15766       break;
15767     }
15768   mnemonicendp = p;
15769   *p = '\0';
15770
15771 skip:
15772   if (modrm.mod == 3)
15773     {
15774       int add;
15775
15776       /* Skip mod/rm byte.  */
15777       MODRM_CHECK;
15778       codep++;
15779
15780       USED_REX (REX_B);
15781       add = (rex & REX_B) ? 8 : 0;
15782       if (bytemode == b_mode)
15783         {
15784           USED_REX (0);
15785           if (rex)
15786             oappend (names8rex[modrm.rm + add]);
15787           else
15788             oappend (names8[modrm.rm + add]);
15789         }
15790       else
15791         {
15792           USED_REX (REX_W);
15793           if (rex & REX_W)
15794             oappend (names64[modrm.rm + add]);
15795           else if ((prefixes & PREFIX_DATA))
15796             oappend (names16[modrm.rm + add]);
15797           else
15798             oappend (names32[modrm.rm + add]);
15799         }
15800     }
15801   else
15802     OP_E (bytemode, sizeflag);
15803 }
15804
15805 static void
15806 FXSAVE_Fixup (int bytemode, int sizeflag)
15807 {
15808   /* Add proper suffix to "fxsave" and "fxrstor".  */
15809   USED_REX (REX_W);
15810   if (rex & REX_W)
15811     {
15812       char *p = mnemonicendp;
15813       *p++ = '6';
15814       *p++ = '4';
15815       *p = '\0';
15816       mnemonicendp = p;
15817     }
15818   OP_M (bytemode, sizeflag);
15819 }
15820
15821 static void
15822 PCMPESTR_Fixup (int bytemode, int sizeflag)
15823 {
15824   /* Add proper suffix to "{,v}pcmpestr{i,m}".  */
15825   if (!intel_syntax)
15826     {
15827       char *p = mnemonicendp;
15828
15829       USED_REX (REX_W);
15830       if (rex & REX_W)
15831         *p++ = 'q';
15832       else if (sizeflag & SUFFIX_ALWAYS)
15833         *p++ = 'l';
15834
15835       *p = '\0';
15836       mnemonicendp = p;
15837     }
15838
15839   OP_EX (bytemode, sizeflag);
15840 }
15841
15842 /* Display the destination register operand for instructions with
15843    VEX. */
15844
15845 static void
15846 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15847 {
15848   int reg;
15849   const char **names;
15850
15851   if (!need_vex)
15852     abort ();
15853
15854   if (!need_vex_reg)
15855     return;
15856
15857   reg = vex.register_specifier;
15858   vex.register_specifier = 0;
15859   if (address_mode != mode_64bit)
15860     reg &= 7;
15861   else if (vex.evex && !vex.v)
15862     reg += 16;
15863
15864   if (bytemode == vex_scalar_mode)
15865     {
15866       oappend (names_xmm[reg]);
15867       return;
15868     }
15869
15870   switch (vex.length)
15871     {
15872     case 128:
15873       switch (bytemode)
15874         {
15875         case vex_mode:
15876         case vex128_mode:
15877         case vex_vsib_q_w_dq_mode:
15878         case vex_vsib_q_w_d_mode:
15879           names = names_xmm;
15880           break;
15881         case dq_mode:
15882           if (rex & REX_W)
15883             names = names64;
15884           else
15885             names = names32;
15886           break;
15887         case mask_bd_mode:
15888         case mask_mode:
15889           if (reg > 0x7)
15890             {
15891               oappend ("(bad)");
15892               return;
15893             }
15894           names = names_mask;
15895           break;
15896         default:
15897           abort ();
15898           return;
15899         }
15900       break;
15901     case 256:
15902       switch (bytemode)
15903         {
15904         case vex_mode:
15905         case vex256_mode:
15906           names = names_ymm;
15907           break;
15908         case vex_vsib_q_w_dq_mode:
15909         case vex_vsib_q_w_d_mode:
15910           names = vex.w ? names_ymm : names_xmm;
15911           break;
15912         case mask_bd_mode:
15913         case mask_mode:
15914           if (reg > 0x7)
15915             {
15916               oappend ("(bad)");
15917               return;
15918             }
15919           names = names_mask;
15920           break;
15921         default:
15922           /* See PR binutils/20893 for a reproducer.  */
15923           oappend ("(bad)");
15924           return;
15925         }
15926       break;
15927     case 512:
15928       names = names_zmm;
15929       break;
15930     default:
15931       abort ();
15932       break;
15933     }
15934   oappend (names[reg]);
15935 }
15936
15937 /* Get the VEX immediate byte without moving codep.  */
15938
15939 static unsigned char
15940 get_vex_imm8 (int sizeflag, int opnum)
15941 {
15942   int bytes_before_imm = 0;
15943
15944   if (modrm.mod != 3)
15945     {
15946       /* There are SIB/displacement bytes.  */
15947       if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15948         {
15949           /* 32/64 bit address mode */
15950           int base = modrm.rm;
15951
15952           /* Check SIB byte.  */
15953           if (base == 4)
15954             {
15955               FETCH_DATA (the_info, codep + 1);
15956               base = *codep & 7;
15957               /* When decoding the third source, don't increase
15958                  bytes_before_imm as this has already been incremented
15959                  by one in OP_E_memory while decoding the second
15960                  source operand.  */
15961               if (opnum == 0)
15962                 bytes_before_imm++;
15963             }
15964
15965           /* Don't increase bytes_before_imm when decoding the third source,
15966              it has already been incremented by OP_E_memory while decoding
15967              the second source operand.  */
15968           if (opnum == 0)
15969             {
15970               switch (modrm.mod)
15971                 {
15972                   case 0:
15973                     /* When modrm.rm == 5 or modrm.rm == 4 and base in
15974                        SIB == 5, there is a 4 byte displacement.  */
15975                     if (base != 5)
15976                       /* No displacement. */
15977                       break;
15978                     /* Fall through.  */
15979                   case 2:
15980                     /* 4 byte displacement.  */
15981                     bytes_before_imm += 4;
15982                     break;
15983                   case 1:
15984                     /* 1 byte displacement.  */
15985                     bytes_before_imm++;
15986                     break;
15987                 }
15988             }
15989         }
15990       else
15991         {
15992           /* 16 bit address mode */
15993           /* Don't increase bytes_before_imm when decoding the third source,
15994              it has already been incremented by OP_E_memory while decoding
15995              the second source operand.  */
15996           if (opnum == 0)
15997             {
15998               switch (modrm.mod)
15999                 {
16000                 case 0:
16001                   /* When modrm.rm == 6, there is a 2 byte displacement.  */
16002                   if (modrm.rm != 6)
16003                     /* No displacement. */
16004                     break;
16005                   /* Fall through.  */
16006                 case 2:
16007                   /* 2 byte displacement.  */
16008                   bytes_before_imm += 2;
16009                   break;
16010                 case 1:
16011                   /* 1 byte displacement: when decoding the third source,
16012                      don't increase bytes_before_imm as this has already
16013                      been incremented by one in OP_E_memory while decoding
16014                      the second source operand.  */
16015                   if (opnum == 0)
16016                     bytes_before_imm++;
16017
16018                   break;
16019                 }
16020             }
16021         }
16022     }
16023
16024   FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16025   return codep [bytes_before_imm];
16026 }
16027
16028 static void
16029 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16030 {
16031   const char **names;
16032
16033   if (reg == -1 && modrm.mod != 3)
16034     {
16035       OP_E_memory (bytemode, sizeflag);
16036       return;
16037     }
16038   else
16039     {
16040       if (reg == -1)
16041         {
16042           reg = modrm.rm;
16043           USED_REX (REX_B);
16044           if (rex & REX_B)
16045             reg += 8;
16046         }
16047       if (address_mode != mode_64bit)
16048         reg &= 7;
16049     }
16050
16051   switch (vex.length)
16052     {
16053     case 128:
16054       names = names_xmm;
16055       break;
16056     case 256:
16057       names = names_ymm;
16058       break;
16059     default:
16060       abort ();
16061     }
16062   oappend (names[reg]);
16063 }
16064
16065 static void
16066 OP_EX_VexImmW (int bytemode, int sizeflag)
16067 {
16068   int reg = -1;
16069   static unsigned char vex_imm8;
16070
16071   if (vex_w_done == 0)
16072     {
16073       vex_w_done = 1;
16074
16075       /* Skip mod/rm byte.  */
16076       MODRM_CHECK;
16077       codep++;
16078
16079       vex_imm8 = get_vex_imm8 (sizeflag, 0);
16080
16081       if (vex.w)
16082           reg = vex_imm8 >> 4;
16083
16084       OP_EX_VexReg (bytemode, sizeflag, reg);
16085     }
16086   else if (vex_w_done == 1)
16087     {
16088       vex_w_done = 2;
16089
16090       if (!vex.w)
16091           reg = vex_imm8 >> 4;
16092
16093       OP_EX_VexReg (bytemode, sizeflag, reg);
16094     }
16095   else
16096     {
16097       /* Output the imm8 directly.  */
16098       scratchbuf[0] = '$';
16099       print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16100       oappend_maybe_intel (scratchbuf);
16101       scratchbuf[0] = '\0';
16102       codep++;
16103     }
16104 }
16105
16106 static void
16107 OP_Vex_2src (int bytemode, int sizeflag)
16108 {
16109   if (modrm.mod == 3)
16110     {
16111       int reg = modrm.rm;
16112       USED_REX (REX_B);
16113       if (rex & REX_B)
16114         reg += 8;
16115       oappend (names_xmm[reg]);
16116     }
16117   else
16118     {
16119       if (intel_syntax
16120           && (bytemode == v_mode || bytemode == v_swap_mode))
16121         {
16122           bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16123           used_prefixes |= (prefixes & PREFIX_DATA);
16124         }
16125       OP_E (bytemode, sizeflag);
16126     }
16127 }
16128
16129 static void
16130 OP_Vex_2src_1 (int bytemode, int sizeflag)
16131 {
16132   if (modrm.mod == 3)
16133     {
16134       /* Skip mod/rm byte.   */
16135       MODRM_CHECK;
16136       codep++;
16137     }
16138
16139   if (vex.w)
16140     {
16141       unsigned int reg = vex.register_specifier;
16142       vex.register_specifier = 0;
16143
16144       if (address_mode != mode_64bit)
16145         reg &= 7;
16146       oappend (names_xmm[reg]);
16147     }
16148   else
16149     OP_Vex_2src (bytemode, sizeflag);
16150 }
16151
16152 static void
16153 OP_Vex_2src_2 (int bytemode, int sizeflag)
16154 {
16155   if (vex.w)
16156     OP_Vex_2src (bytemode, sizeflag);
16157   else
16158     {
16159       unsigned int reg = vex.register_specifier;
16160       vex.register_specifier = 0;
16161
16162       if (address_mode != mode_64bit)
16163         reg &= 7;
16164       oappend (names_xmm[reg]);
16165     }
16166 }
16167
16168 static void
16169 OP_EX_VexW (int bytemode, int sizeflag)
16170 {
16171   int reg = -1;
16172
16173   if (!vex_w_done)
16174     {
16175       /* Skip mod/rm byte.  */
16176       MODRM_CHECK;
16177       codep++;
16178
16179       if (vex.w)
16180         reg = get_vex_imm8 (sizeflag, 0) >> 4;
16181     }
16182   else
16183     {
16184       if (!vex.w)
16185         reg = get_vex_imm8 (sizeflag, 1) >> 4;
16186     }
16187
16188   OP_EX_VexReg (bytemode, sizeflag, reg);
16189
16190   if (vex_w_done)
16191     codep++;
16192   vex_w_done = 1;
16193 }
16194
16195 static void
16196 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16197 {
16198   int reg;
16199   const char **names;
16200
16201   FETCH_DATA (the_info, codep + 1);
16202   reg = *codep++;
16203
16204   if (bytemode != x_mode)
16205     abort ();
16206
16207   reg >>= 4;
16208   if (address_mode != mode_64bit)
16209     reg &= 7;
16210
16211   switch (vex.length)
16212     {
16213     case 128:
16214       names = names_xmm;
16215       break;
16216     case 256:
16217       names = names_ymm;
16218       break;
16219     default:
16220       abort ();
16221     }
16222   oappend (names[reg]);
16223 }
16224
16225 static void
16226 OP_XMM_VexW (int bytemode, int sizeflag)
16227 {
16228   /* Turn off the REX.W bit since it is used for swapping operands
16229      now.  */
16230   rex &= ~REX_W;
16231   OP_XMM (bytemode, sizeflag);
16232 }
16233
16234 static void
16235 OP_EX_Vex (int bytemode, int sizeflag)
16236 {
16237   if (modrm.mod != 3)
16238     need_vex_reg = 0;
16239   OP_EX (bytemode, sizeflag);
16240 }
16241
16242 static void
16243 OP_XMM_Vex (int bytemode, int sizeflag)
16244 {
16245   if (modrm.mod != 3)
16246     need_vex_reg = 0;
16247   OP_XMM (bytemode, sizeflag);
16248 }
16249
16250 static struct op vex_cmp_op[] =
16251 {
16252   { STRING_COMMA_LEN ("eq") },
16253   { STRING_COMMA_LEN ("lt") },
16254   { STRING_COMMA_LEN ("le") },
16255   { STRING_COMMA_LEN ("unord") },
16256   { STRING_COMMA_LEN ("neq") },
16257   { STRING_COMMA_LEN ("nlt") },
16258   { STRING_COMMA_LEN ("nle") },
16259   { STRING_COMMA_LEN ("ord") },
16260   { STRING_COMMA_LEN ("eq_uq") },
16261   { STRING_COMMA_LEN ("nge") },
16262   { STRING_COMMA_LEN ("ngt") },
16263   { STRING_COMMA_LEN ("false") },
16264   { STRING_COMMA_LEN ("neq_oq") },
16265   { STRING_COMMA_LEN ("ge") },
16266   { STRING_COMMA_LEN ("gt") },
16267   { STRING_COMMA_LEN ("true") },
16268   { STRING_COMMA_LEN ("eq_os") },
16269   { STRING_COMMA_LEN ("lt_oq") },
16270   { STRING_COMMA_LEN ("le_oq") },
16271   { STRING_COMMA_LEN ("unord_s") },
16272   { STRING_COMMA_LEN ("neq_us") },
16273   { STRING_COMMA_LEN ("nlt_uq") },
16274   { STRING_COMMA_LEN ("nle_uq") },
16275   { STRING_COMMA_LEN ("ord_s") },
16276   { STRING_COMMA_LEN ("eq_us") },
16277   { STRING_COMMA_LEN ("nge_uq") },
16278   { STRING_COMMA_LEN ("ngt_uq") },
16279   { STRING_COMMA_LEN ("false_os") },
16280   { STRING_COMMA_LEN ("neq_os") },
16281   { STRING_COMMA_LEN ("ge_oq") },
16282   { STRING_COMMA_LEN ("gt_oq") },
16283   { STRING_COMMA_LEN ("true_us") },
16284 };
16285
16286 static void
16287 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16288 {
16289   unsigned int cmp_type;
16290
16291   FETCH_DATA (the_info, codep + 1);
16292   cmp_type = *codep++ & 0xff;
16293   if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16294     {
16295       char suffix [3];
16296       char *p = mnemonicendp - 2;
16297       suffix[0] = p[0];
16298       suffix[1] = p[1];
16299       suffix[2] = '\0';
16300       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16301       mnemonicendp += vex_cmp_op[cmp_type].len;
16302     }
16303   else
16304     {
16305       /* We have a reserved extension byte.  Output it directly.  */
16306       scratchbuf[0] = '$';
16307       print_operand_value (scratchbuf + 1, 1, cmp_type);
16308       oappend_maybe_intel (scratchbuf);
16309       scratchbuf[0] = '\0';
16310     }
16311 }
16312
16313 static void
16314 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16315              int sizeflag ATTRIBUTE_UNUSED)
16316 {
16317   unsigned int cmp_type;
16318
16319   if (!vex.evex)
16320     abort ();
16321
16322   FETCH_DATA (the_info, codep + 1);
16323   cmp_type = *codep++ & 0xff;
16324   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16325      If it's the case, print suffix, otherwise - print the immediate.  */
16326   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16327       && cmp_type != 3
16328       && cmp_type != 7)
16329     {
16330       char suffix [3];
16331       char *p = mnemonicendp - 2;
16332
16333       /* vpcmp* can have both one- and two-lettered suffix.  */
16334       if (p[0] == 'p')
16335         {
16336           p++;
16337           suffix[0] = p[0];
16338           suffix[1] = '\0';
16339         }
16340       else
16341         {
16342           suffix[0] = p[0];
16343           suffix[1] = p[1];
16344           suffix[2] = '\0';
16345         }
16346
16347       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16348       mnemonicendp += simd_cmp_op[cmp_type].len;
16349     }
16350   else
16351     {
16352       /* We have a reserved extension byte.  Output it directly.  */
16353       scratchbuf[0] = '$';
16354       print_operand_value (scratchbuf + 1, 1, cmp_type);
16355       oappend_maybe_intel (scratchbuf);
16356       scratchbuf[0] = '\0';
16357     }
16358 }
16359
16360 static const struct op xop_cmp_op[] =
16361 {
16362   { STRING_COMMA_LEN ("lt") },
16363   { STRING_COMMA_LEN ("le") },
16364   { STRING_COMMA_LEN ("gt") },
16365   { STRING_COMMA_LEN ("ge") },
16366   { STRING_COMMA_LEN ("eq") },
16367   { STRING_COMMA_LEN ("neq") },
16368   { STRING_COMMA_LEN ("false") },
16369   { STRING_COMMA_LEN ("true") }
16370 };
16371
16372 static void
16373 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16374              int sizeflag ATTRIBUTE_UNUSED)
16375 {
16376   unsigned int cmp_type;
16377
16378   FETCH_DATA (the_info, codep + 1);
16379   cmp_type = *codep++ & 0xff;
16380   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16381     {
16382       char suffix[3];
16383       char *p = mnemonicendp - 2;
16384
16385       /* vpcom* can have both one- and two-lettered suffix.  */
16386       if (p[0] == 'm')
16387         {
16388           p++;
16389           suffix[0] = p[0];
16390           suffix[1] = '\0';
16391         }
16392       else
16393         {
16394           suffix[0] = p[0];
16395           suffix[1] = p[1];
16396           suffix[2] = '\0';
16397         }
16398
16399       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16400       mnemonicendp += xop_cmp_op[cmp_type].len;
16401     }
16402   else
16403     {
16404       /* We have a reserved extension byte.  Output it directly.  */
16405       scratchbuf[0] = '$';
16406       print_operand_value (scratchbuf + 1, 1, cmp_type);
16407       oappend_maybe_intel (scratchbuf);
16408       scratchbuf[0] = '\0';
16409     }
16410 }
16411
16412 static const struct op pclmul_op[] =
16413 {
16414   { STRING_COMMA_LEN ("lql") },
16415   { STRING_COMMA_LEN ("hql") },
16416   { STRING_COMMA_LEN ("lqh") },
16417   { STRING_COMMA_LEN ("hqh") }
16418 };
16419
16420 static void
16421 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16422               int sizeflag ATTRIBUTE_UNUSED)
16423 {
16424   unsigned int pclmul_type;
16425
16426   FETCH_DATA (the_info, codep + 1);
16427   pclmul_type = *codep++ & 0xff;
16428   switch (pclmul_type)
16429     {
16430     case 0x10:
16431       pclmul_type = 2;
16432       break;
16433     case 0x11:
16434       pclmul_type = 3;
16435       break;
16436     default:
16437       break;
16438     }
16439   if (pclmul_type < ARRAY_SIZE (pclmul_op))
16440     {
16441       char suffix [4];
16442       char *p = mnemonicendp - 3;
16443       suffix[0] = p[0];
16444       suffix[1] = p[1];
16445       suffix[2] = p[2];
16446       suffix[3] = '\0';
16447       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16448       mnemonicendp += pclmul_op[pclmul_type].len;
16449     }
16450   else
16451     {
16452       /* We have a reserved extension byte.  Output it directly.  */
16453       scratchbuf[0] = '$';
16454       print_operand_value (scratchbuf + 1, 1, pclmul_type);
16455       oappend_maybe_intel (scratchbuf);
16456       scratchbuf[0] = '\0';
16457     }
16458 }
16459
16460 static void
16461 MOVBE_Fixup (int bytemode, int sizeflag)
16462 {
16463   /* Add proper suffix to "movbe".  */
16464   char *p = mnemonicendp;
16465
16466   switch (bytemode)
16467     {
16468     case v_mode:
16469       if (intel_syntax)
16470         goto skip;
16471
16472       USED_REX (REX_W);
16473       if (sizeflag & SUFFIX_ALWAYS)
16474         {
16475           if (rex & REX_W)
16476             *p++ = 'q';
16477           else
16478             {
16479               if (sizeflag & DFLAG)
16480                 *p++ = 'l';
16481               else
16482                 *p++ = 'w';
16483               used_prefixes |= (prefixes & PREFIX_DATA);
16484             }
16485         }
16486       break;
16487     default:
16488       oappend (INTERNAL_DISASSEMBLER_ERROR);
16489       break;
16490     }
16491   mnemonicendp = p;
16492   *p = '\0';
16493
16494 skip:
16495   OP_M (bytemode, sizeflag);
16496 }
16497
16498 static void
16499 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16500 {
16501   int reg;
16502   const char **names;
16503
16504   /* Skip mod/rm byte.  */
16505   MODRM_CHECK;
16506   codep++;
16507
16508   if (rex & REX_W)
16509     names = names64;
16510   else
16511     names = names32;
16512
16513   reg = modrm.rm;
16514   USED_REX (REX_B);
16515   if (rex & REX_B)
16516     reg += 8;
16517
16518   oappend (names[reg]);
16519 }
16520
16521 static void
16522 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16523 {
16524   const char **names;
16525   unsigned int reg = vex.register_specifier;
16526   vex.register_specifier = 0;
16527
16528   if (rex & REX_W)
16529     names = names64;
16530   else
16531     names = names32;
16532
16533   if (address_mode != mode_64bit)
16534     reg &= 7;
16535   oappend (names[reg]);
16536 }
16537
16538 static void
16539 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16540 {
16541   if (!vex.evex
16542       || (bytemode != mask_mode && bytemode != mask_bd_mode))
16543     abort ();
16544
16545   USED_REX (REX_R);
16546   if ((rex & REX_R) != 0 || !vex.r)
16547     {
16548       BadOp ();
16549       return;
16550     }
16551
16552   oappend (names_mask [modrm.reg]);
16553 }
16554
16555 static void
16556 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16557 {
16558   if (!vex.evex
16559       || (bytemode != evex_rounding_mode
16560           && bytemode != evex_rounding_64_mode
16561           && bytemode != evex_sae_mode))
16562     abort ();
16563   if (modrm.mod == 3 && vex.b)
16564     switch (bytemode)
16565       {
16566       case evex_rounding_64_mode:
16567         if (address_mode != mode_64bit)
16568           {
16569             oappend ("(bad)");
16570             break;
16571           }
16572         /* Fall through.  */
16573       case evex_rounding_mode:
16574         oappend (names_rounding[vex.ll]);
16575         break;
16576       case evex_sae_mode:
16577         oappend ("{sae}");
16578         break;
16579       default:
16580         break;
16581       }
16582 }