opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* mwaitx instruction required */
 214   CpuMWAITX,
 215   /* Clzero instruction required */
 216   CpuCLZERO,
 217   /* OSPKE instruction required */
 218   CpuOSPKE,
 219   /* RDPID instruction required */
 220   CpuRDPID,
 221   /* PTWRITE instruction required */
 222   CpuPTWRITE,
 223   /* CET instructions support required */
 224   CpuIBT,
 225   CpuSHSTK,
 226   /* AMX-INT8 instructions required */
 227   CpuAMX_INT8,
 228   /* AMX-BF16 instructions required */
 229   CpuAMX_BF16,
 230   /* AMX-TILE instructions required */
 231   CpuAMX_TILE,
 232   /* GFNI instructions required */
 233   CpuGFNI,
 234   /* VAES instructions required */
 235   CpuVAES,
 236   /* VPCLMULQDQ instructions required */
 237   CpuVPCLMULQDQ,
 238   /* WBNOINVD instructions required */
 239   CpuWBNOINVD,
 240   /* PCONFIG instructions required */
 241   CpuPCONFIG,
 242   /* WAITPKG instructions required */
 243   CpuWAITPKG,
 244   /* CLDEMOTE instruction required */
 245   CpuCLDEMOTE,
 246   /* MOVDIRI instruction support required */
 247   CpuMOVDIRI,
 248   /* MOVDIRR64B instruction required */
 249   CpuMOVDIR64B,
 250   /* ENQCMD instruction required */
 251   CpuENQCMD,
 252   /* SERIALIZE instruction required */
 253   CpuSERIALIZE,
 254   /* RDPRU instruction required */
 255   CpuRDPRU,
 256   /* MCOMMIT instruction required */
 257   CpuMCOMMIT,
 258   /* SEV-ES instruction(s) required */
 259   CpuSEV_ES,
 260   /* TSXLDTRK instruction required */
 261   CpuTSXLDTRK,
 262   /* 64bit support required  */
 263   Cpu64,
 264   /* Not supported in the 64bit mode  */
 265   CpuNo64,
 266   /* The last bitfield in i386_cpu_flags.  */
 267   CpuMax = CpuNo64
 268 };
 269
 270 #define CpuNumOfUints \
 271   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 272 #define CpuNumOfBits \
 273   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 274
 275 /* If you get a compiler error for zero width of the unused field,
 276    comment it out.  */
 277 #define CpuUnused       (CpuMax + 1)
 278
 279 /* We can check if an instruction is available with array instead
 280    of bitfield. */
 281 typedef union i386_cpu_flags
 282 {
 283   struct
 284     {
 285       unsigned int cpui186:1;
 286       unsigned int cpui286:1;
 287       unsigned int cpui386:1;
 288       unsigned int cpui486:1;
 289       unsigned int cpui586:1;
 290       unsigned int cpui686:1;
 291       unsigned int cpucmov:1;
 292       unsigned int cpufxsr:1;
 293       unsigned int cpuclflush:1;
 294       unsigned int cpunop:1;
 295       unsigned int cpusyscall:1;
 296       unsigned int cpu8087:1;
 297       unsigned int cpu287:1;
 298       unsigned int cpu387:1;
 299       unsigned int cpu687:1;
 300       unsigned int cpufisttp:1;
 301       unsigned int cpummx:1;
 302       unsigned int cpusse:1;
 303       unsigned int cpusse2:1;
 304       unsigned int cpua3dnow:1;
 305       unsigned int cpua3dnowa:1;
 306       unsigned int cpusse3:1;
 307       unsigned int cpupadlock:1;
 308       unsigned int cpusvme:1;
 309       unsigned int cpuvmx:1;
 310       unsigned int cpusmx:1;
 311       unsigned int cpussse3:1;
 312       unsigned int cpusse4a:1;
 313       unsigned int cpulzcnt:1;
 314       unsigned int cpupopcnt:1;
 315       unsigned int cpusse4_1:1;
 316       unsigned int cpusse4_2:1;
 317       unsigned int cpuavx:1;
 318       unsigned int cpuavx2:1;
 319       unsigned int cpuavx512f:1;
 320       unsigned int cpuavx512cd:1;
 321       unsigned int cpuavx512er:1;
 322       unsigned int cpuavx512pf:1;
 323       unsigned int cpuavx512vl:1;
 324       unsigned int cpuavx512dq:1;
 325       unsigned int cpuavx512bw:1;
 326       unsigned int cpul1om:1;
 327       unsigned int cpuk1om:1;
 328       unsigned int cpuiamcu:1;
 329       unsigned int cpuxsave:1;
 330       unsigned int cpuxsaveopt:1;
 331       unsigned int cpuaes:1;
 332       unsigned int cpupclmul:1;
 333       unsigned int cpufma:1;
 334       unsigned int cpufma4:1;
 335       unsigned int cpuxop:1;
 336       unsigned int cpulwp:1;
 337       unsigned int cpubmi:1;
 338       unsigned int cputbm:1;
 339       unsigned int cpumovbe:1;
 340       unsigned int cpucx16:1;
 341       unsigned int cpuept:1;
 342       unsigned int cpurdtscp:1;
 343       unsigned int cpufsgsbase:1;
 344       unsigned int cpurdrnd:1;
 345       unsigned int cpuf16c:1;
 346       unsigned int cpubmi2:1;
 347       unsigned int cpuhle:1;
 348       unsigned int cpurtm:1;
 349       unsigned int cpuinvpcid:1;
 350       unsigned int cpuvmfunc:1;
 351       unsigned int cpumpx:1;
 352       unsigned int cpulm:1;
 353       unsigned int cpurdseed:1;
 354       unsigned int cpuadx:1;
 355       unsigned int cpuprfchw:1;
 356       unsigned int cpusmap:1;
 357       unsigned int cpusha:1;
 358       unsigned int cpuclflushopt:1;
 359       unsigned int cpuxsaves:1;
 360       unsigned int cpuxsavec:1;
 361       unsigned int cpuprefetchwt1:1;
 362       unsigned int cpuse1:1;
 363       unsigned int cpuclwb:1;
 364       unsigned int cpuavx512ifma:1;
 365       unsigned int cpuavx512vbmi:1;
 366       unsigned int cpuavx512_4fmaps:1;
 367       unsigned int cpuavx512_4vnniw:1;
 368       unsigned int cpuavx512_vpopcntdq:1;
 369       unsigned int cpuavx512_vbmi2:1;
 370       unsigned int cpuavx512_vnni:1;
 371       unsigned int cpuavx512_bitalg:1;
 372       unsigned int cpuavx512_bf16:1;
 373       unsigned int cpuavx512_vp2intersect:1;
 374       unsigned int cpumwaitx:1;
 375       unsigned int cpuclzero:1;
 376       unsigned int cpuospke:1;
 377       unsigned int cpurdpid:1;
 378       unsigned int cpuptwrite:1;
 379       unsigned int cpuibt:1;
 380       unsigned int cpushstk:1;
 381       unsigned int cpuamx_int8:1;
 382       unsigned int cpuamx_bf16:1;
 383       unsigned int cpuamx_tile:1;
 384       unsigned int cpugfni:1;
 385       unsigned int cpuvaes:1;
 386       unsigned int cpuvpclmulqdq:1;
 387       unsigned int cpuwbnoinvd:1;
 388       unsigned int cpupconfig:1;
 389       unsigned int cpuwaitpkg:1;
 390       unsigned int cpucldemote:1;
 391       unsigned int cpumovdiri:1;
 392       unsigned int cpumovdir64b:1;
 393       unsigned int cpuenqcmd:1;
 394       unsigned int cpuserialize:1;
 395       unsigned int cpurdpru:1;
 396       unsigned int cpumcommit:1;
 397       unsigned int cpusev_es:1;
 398       unsigned int cputsxldtrk:1;
 399       unsigned int cpu64:1;
 400       unsigned int cpuno64:1;
 401 #ifdef CpuUnused
 402       unsigned int unused:(CpuNumOfBits - CpuUnused);
 403 #endif
 404     } bitfield;
 405   unsigned int array[CpuNumOfUints];
 406 } i386_cpu_flags;
 407
 408 /* Position of opcode_modifier bits.  */
 409
 410 enum
 411 {
 412   /* has direction bit. */
 413   D = 0,
 414   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 415      canonical way; the base_opcode field should hold the encoding for byte
 416      operands  */
 417   W,
 418   /* load form instruction. Must be placed before store form.  */
 419   Load,
 420   /* insn has a modrm byte. */
 421   Modrm,
 422   /* special case for jump insns; value has to be 1 */
 423 #define JUMP 1
 424   /* call and jump */
 425 #define JUMP_DWORD 2
 426   /* loop and jecxz */
 427 #define JUMP_BYTE 3
 428   /* special case for intersegment leaps/calls */
 429 #define JUMP_INTERSEGMENT 4
 430   /* absolute address for jump */
 431 #define JUMP_ABSOLUTE 5
 432   Jump,
 433   /* FP insn memory format bit, sized by 0x4 */
 434   FloatMF,
 435   /* src/dest swap for floats. */
 436   FloatR,
 437   /* needs size prefix if in 32-bit mode */
 438 #define SIZE16 1
 439   /* needs size prefix if in 16-bit mode */
 440 #define SIZE32 2
 441   /* needs size prefix if in 64-bit mode */
 442 #define SIZE64 3
 443   Size,
 444   /* check register size.  */
 445   CheckRegSize,
 446   /* instruction ignores operand size prefix and in Intel mode ignores
 447      mnemonic size suffix check.  */
 448 #define IGNORESIZE      1
 449   /* default insn size depends on mode */
 450 #define DEFAULTSIZE     2
 451   MnemonicSize,
 452   /* any memory size */
 453   Anysize,
 454   /* b suffix on instruction illegal */
 455   No_bSuf,
 456   /* w suffix on instruction illegal */
 457   No_wSuf,
 458   /* l suffix on instruction illegal */
 459   No_lSuf,
 460   /* s suffix on instruction illegal */
 461   No_sSuf,
 462   /* q suffix on instruction illegal */
 463   No_qSuf,
 464   /* long double suffix on instruction illegal */
 465   No_ldSuf,
 466   /* instruction needs FWAIT */
 467   FWait,
 468   /* IsString provides for a quick test for string instructions, and
 469      its actual value also indicates which of the operands (if any)
 470      requires use of the %es segment.  */
 471 #define IS_STRING_ES_OP0 2
 472 #define IS_STRING_ES_OP1 3
 473   IsString,
 474   /* RegMem is for instructions with a modrm byte where the register
 475      destination operand should be encoded in the mod and regmem fields.
 476      Normally, it will be encoded in the reg field. We add a RegMem
 477      flag to indicate that it should be encoded in the regmem field.  */
 478   RegMem,
 479   /* quick test if branch instruction is MPX supported */
 480   BNDPrefixOk,
 481   /* quick test if NOTRACK prefix is supported */
 482   NoTrackPrefixOk,
 483   /* quick test for lockable instructions */
 484   IsLockable,
 485   /* fake an extra reg operand for clr, imul and special register
 486      processing for some instructions.  */
 487   RegKludge,
 488   /* An implicit xmm0 as the first operand */
 489   Implicit1stXmm0,
 490   /* The HLE prefix is OK:
 491      1. With a LOCK prefix.
 492      2. With or without a LOCK prefix.
 493      3. With a RELEASE (0xf3) prefix.
 494    */
 495 #define HLEPrefixNone           0
 496 #define HLEPrefixLock           1
 497 #define HLEPrefixAny            2
 498 #define HLEPrefixRelease        3
 499   HLEPrefixOk,
 500   /* An instruction on which a "rep" prefix is acceptable.  */
 501   RepPrefixOk,
 502   /* Convert to DWORD */
 503   ToDword,
 504   /* Convert to QWORD */
 505   ToQword,
 506   /* Address prefix changes register operand */
 507   AddrPrefixOpReg,
 508   /* opcode is a prefix */
 509   IsPrefix,
 510   /* instruction has extension in 8 bit imm */
 511   ImmExt,
 512   /* instruction don't need Rex64 prefix.  */
 513   NoRex64,
 514   /* deprecated fp insn, gets a warning */
 515   Ugh,
 516   /* insn has VEX prefix:
 517         1: 128bit VEX prefix (or operand dependent).
 518         2: 256bit VEX prefix.
 519         3: Scalar VEX prefix.
 520    */
 521 #define VEX128          1
 522 #define VEX256          2
 523 #define VEXScalar       3
 524   Vex,
 525   /* How to encode VEX.vvvv:
 526      0: VEX.vvvv must be 1111b.
 527      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 528         the content of source registers will be preserved.
 529         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 530         where the content of first source register will be overwritten
 531         by the result.
 532         VEX.NDD2.  The second destination register operand is encoded in
 533         VEX.vvvv for instructions with 2 destination register operands.
 534         For assembler, there are no difference between VEX.NDS, VEX.DDS
 535         and VEX.NDD2.
 536      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 537      instructions with 1 destination register operand.
 538      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 539         of the operands can access a memory location.
 540    */
 541 #define VEXXDS  1
 542 #define VEXNDD  2
 543 #define VEXLWP  3
 544   VexVVVV,
 545   /* How the VEX.W bit is used:
 546      0: Set by the REX.W bit.
 547      1: VEX.W0.  Should always be 0.
 548      2: VEX.W1.  Should always be 1.
 549      3: VEX.WIG. The VEX.W bit is ignored.
 550    */
 551 #define VEXW0   1
 552 #define VEXW1   2
 553 #define VEXWIG  3
 554   VexW,
 555   /* VEX opcode prefix:
 556      0: VEX 0x0F opcode prefix.
 557      1: VEX 0x0F38 opcode prefix.
 558      2: VEX 0x0F3A opcode prefix
 559      3: XOP 0x08 opcode prefix.
 560      4: XOP 0x09 opcode prefix
 561      5: XOP 0x0A opcode prefix.
 562    */
 563 #define VEX0F           0
 564 #define VEX0F38         1
 565 #define VEX0F3A         2
 566 #define XOP08           3
 567 #define XOP09           4
 568 #define XOP0A           5
 569   VexOpcode,
 570   /* number of VEX source operands:
 571      0: <= 2 source operands.
 572      1: 2 XOP source operands.
 573      2: 3 source operands.
 574    */
 575 #define XOP2SOURCES     1
 576 #define VEX3SOURCES     2
 577   VexSources,
 578   /* Instruction with a mandatory SIB byte:
 579         1: 128bit vector register.
 580         2: 256bit vector register.
 581         3: 512bit vector register.
 582    */
 583 #define VECSIB128       1
 584 #define VECSIB256       2
 585 #define VECSIB512       3
 586 #define SIBMEM          4
 587   SIB,
 588
 589   /* SSE to AVX support required */
 590   SSE2AVX,
 591   /* No AVX equivalent */
 592   NoAVX,
 593
 594   /* insn has EVEX prefix:
 595         1: 512bit EVEX prefix.
 596         2: 128bit EVEX prefix.
 597         3: 256bit EVEX prefix.
 598         4: Length-ignored (LIG) EVEX prefix.
 599         5: Length determined from actual operands.
 600    */
 601 #define EVEX512                1
 602 #define EVEX128                2
 603 #define EVEX256                3
 604 #define EVEXLIG                4
 605 #define EVEXDYN                5
 606   EVex,
 607
 608   /* AVX512 masking support:
 609         1: Zeroing or merging masking depending on operands.
 610         2: Merging-masking.
 611         3: Both zeroing and merging masking.
 612    */
 613 #define DYNAMIC_MASKING 1
 614 #define MERGING_MASKING 2
 615 #define BOTH_MASKING    3
 616   Masking,
 617
 618   /* AVX512 broadcast support.  The number of bytes to broadcast is
 619      1 << (Broadcast - 1):
 620         1: Byte broadcast.
 621         2: Word broadcast.
 622         3: Dword broadcast.
 623         4: Qword broadcast.
 624    */
 625 #define BYTE_BROADCAST  1
 626 #define WORD_BROADCAST  2
 627 #define DWORD_BROADCAST 3
 628 #define QWORD_BROADCAST 4
 629   Broadcast,
 630
 631   /* Static rounding control is supported.  */
 632   StaticRounding,
 633
 634   /* Supress All Exceptions is supported.  */
 635   SAE,
 636
 637   /* Compressed Disp8*N attribute.  */
 638 #define DISP8_SHIFT_VL 7
 639   Disp8MemShift,
 640
 641   /* Default mask isn't allowed.  */
 642   NoDefMask,
 643
 644   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 645      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 646    */
 647   ImplicitQuadGroup,
 648
 649   /* Two source operands are swapped.  */
 650   SwapSources,
 651
 652   /* Support encoding optimization.  */
 653   Optimize,
 654
 655   /* AT&T mnemonic.  */
 656   ATTMnemonic,
 657   /* AT&T syntax.  */
 658   ATTSyntax,
 659   /* Intel syntax.  */
 660   IntelSyntax,
 661   /* ISA64: Don't change the order without other code adjustments.
 662         0: Common to AMD64 and Intel64.
 663         1: AMD64.
 664         2: Intel64.
 665         3: Only in Intel64.
 666    */
 667 #define AMD64           1
 668 #define INTEL64         2
 669 #define INTEL64ONLY     3
 670   ISA64,
 671   /* The last bitfield in i386_opcode_modifier.  */
 672   Opcode_Modifier_Num
 673 };
 674
 675 typedef struct i386_opcode_modifier
 676 {
 677   unsigned int d:1;
 678   unsigned int w:1;
 679   unsigned int load:1;
 680   unsigned int modrm:1;
 681   unsigned int jump:3;
 682   unsigned int floatmf:1;
 683   unsigned int floatr:1;
 684   unsigned int size:2;
 685   unsigned int checkregsize:1;
 686   unsigned int mnemonicsize:2;
 687   unsigned int anysize:1;
 688   unsigned int no_bsuf:1;
 689   unsigned int no_wsuf:1;
 690   unsigned int no_lsuf:1;
 691   unsigned int no_ssuf:1;
 692   unsigned int no_qsuf:1;
 693   unsigned int no_ldsuf:1;
 694   unsigned int fwait:1;
 695   unsigned int isstring:2;
 696   unsigned int regmem:1;
 697   unsigned int bndprefixok:1;
 698   unsigned int notrackprefixok:1;
 699   unsigned int islockable:1;
 700   unsigned int regkludge:1;
 701   unsigned int implicit1stxmm0:1;
 702   unsigned int hleprefixok:2;
 703   unsigned int repprefixok:1;
 704   unsigned int todword:1;
 705   unsigned int toqword:1;
 706   unsigned int addrprefixopreg:1;
 707   unsigned int isprefix:1;
 708   unsigned int immext:1;
 709   unsigned int norex64:1;
 710   unsigned int ugh:1;
 711   unsigned int vex:2;
 712   unsigned int vexvvvv:2;
 713   unsigned int vexw:2;
 714   unsigned int vexopcode:3;
 715   unsigned int vexsources:2;
 716   unsigned int sib:3;
 717   unsigned int sse2avx:1;
 718   unsigned int noavx:1;
 719   unsigned int evex:3;
 720   unsigned int masking:2;
 721   unsigned int broadcast:3;
 722   unsigned int staticrounding:1;
 723   unsigned int sae:1;
 724   unsigned int disp8memshift:3;
 725   unsigned int nodefmask:1;
 726   unsigned int implicitquadgroup:1;
 727   unsigned int swapsources:1;
 728   unsigned int optimize:1;
 729   unsigned int attmnemonic:1;
 730   unsigned int attsyntax:1;
 731   unsigned int intelsyntax:1;
 732   unsigned int isa64:2;
 733 } i386_opcode_modifier;
 734
 735 /* Operand classes.  */
 736
 737 #define CLASS_WIDTH 4
 738 enum operand_class
 739 {
 740   ClassNone,
 741   Reg, /* GPRs and FP regs, distinguished by operand size */
 742   SReg, /* Segment register */
 743   RegCR, /* Control register */
 744   RegDR, /* Debug register */
 745   RegTR, /* Test register */
 746   RegMMX, /* MMX register */
 747   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 748   RegMask, /* Vector Mask register */
 749   RegBND, /* Bound register */
 750 };
 751
 752 /* Special operand instances.  */
 753
 754 #define INSTANCE_WIDTH 3
 755 enum operand_instance
 756 {
 757   InstanceNone,
 758   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 759   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 760   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 761   RegB,  /* %bl / %bx / %ebx / %rbx */
 762 };
 763
 764 /* Position of operand_type bits.  */
 765
 766 enum
 767 {
 768   /* Class and Instance */
 769   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 770   /* 1 bit immediate */
 771   Imm1,
 772   /* 8 bit immediate */
 773   Imm8,
 774   /* 8 bit immediate sign extended */
 775   Imm8S,
 776   /* 16 bit immediate */
 777   Imm16,
 778   /* 32 bit immediate */
 779   Imm32,
 780   /* 32 bit immediate sign extended */
 781   Imm32S,
 782   /* 64 bit immediate */
 783   Imm64,
 784   /* 8bit/16bit/32bit displacements are used in different ways,
 785      depending on the instruction.  For jumps, they specify the
 786      size of the PC relative displacement, for instructions with
 787      memory operand, they specify the size of the offset relative
 788      to the base register, and for instructions with memory offset
 789      such as `mov 1234,%al' they specify the size of the offset
 790      relative to the segment base.  */
 791   /* 8 bit displacement */
 792   Disp8,
 793   /* 16 bit displacement */
 794   Disp16,
 795   /* 32 bit displacement */
 796   Disp32,
 797   /* 32 bit signed displacement */
 798   Disp32S,
 799   /* 64 bit displacement */
 800   Disp64,
 801   /* Register which can be used for base or index in memory operand.  */
 802   BaseIndex,
 803   /* BYTE size. */
 804   Byte,
 805   /* WORD size. 2 byte */
 806   Word,
 807   /* DWORD size. 4 byte */
 808   Dword,
 809   /* FWORD size. 6 byte */
 810   Fword,
 811   /* QWORD size. 8 byte */
 812   Qword,
 813   /* TBYTE size. 10 byte */
 814   Tbyte,
 815   /* XMMWORD size. */
 816   Xmmword,
 817   /* YMMWORD size. */
 818   Ymmword,
 819   /* ZMMWORD size.  */
 820   Zmmword,
 821   /* TMMWORD size.  */
 822   Tmmword,
 823   /* Unspecified memory size.  */
 824   Unspecified,
 825
 826   /* The number of bits in i386_operand_type.  */
 827   OTNum
 828 };
 829
 830 #define OTNumOfUints \
 831   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 832 #define OTNumOfBits \
 833   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 834
 835 /* If you get a compiler error for zero width of the unused field,
 836    comment it out.  */
 837 #define OTUnused                OTNum
 838
 839 typedef union i386_operand_type
 840 {
 841   struct
 842     {
 843       unsigned int class:CLASS_WIDTH;
 844       unsigned int instance:INSTANCE_WIDTH;
 845       unsigned int imm1:1;
 846       unsigned int imm8:1;
 847       unsigned int imm8s:1;
 848       unsigned int imm16:1;
 849       unsigned int imm32:1;
 850       unsigned int imm32s:1;
 851       unsigned int imm64:1;
 852       unsigned int disp8:1;
 853       unsigned int disp16:1;
 854       unsigned int disp32:1;
 855       unsigned int disp32s:1;
 856       unsigned int disp64:1;
 857       unsigned int baseindex:1;
 858       unsigned int byte:1;
 859       unsigned int word:1;
 860       unsigned int dword:1;
 861       unsigned int fword:1;
 862       unsigned int qword:1;
 863       unsigned int tbyte:1;
 864       unsigned int xmmword:1;
 865       unsigned int ymmword:1;
 866       unsigned int zmmword:1;
 867       unsigned int tmmword:1;
 868       unsigned int unspecified:1;
 869 #ifdef OTUnused
 870       unsigned int unused:(OTNumOfBits - OTUnused);
 871 #endif
 872     } bitfield;
 873   unsigned int array[OTNumOfUints];
 874 } i386_operand_type;
 875
 876 typedef struct insn_template
 877 {
 878   /* instruction name sans width suffix ("mov" for movl insns) */
 879   char *name;
 880
 881   /* base_opcode is the fundamental opcode byte without optional
 882      prefix(es).  */
 883   unsigned int base_opcode;
 884 #define Opcode_D        0x2 /* Direction bit:
 885                                set if Reg --> Regmem;
 886                                unset if Regmem --> Reg. */
 887 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 888 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 889 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 890 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 891
 892 /* Pseudo prefixes.  */
 893 #define Prefix_Disp8            0       /* {disp8} */
 894 #define Prefix_Disp16           1       /* {disp16} */
 895 #define Prefix_Disp32           2       /* {disp32} */
 896 #define Prefix_Load             3       /* {load} */
 897 #define Prefix_Store            4       /* {store} */
 898 #define Prefix_VEX              5       /* {vex} */
 899 #define Prefix_VEX3             6       /* {vex3} */
 900 #define Prefix_EVEX             7       /* {evex} */
 901 #define Prefix_REX              8       /* {rex} */
 902 #define Prefix_NoOptimize       9       /* {nooptimize} */
 903
 904   /* extension_opcode is the 3 bit extension for group <n> insns.
 905      This field is also used to store the 8-bit opcode suffix for the
 906      AMD 3DNow! instructions.
 907      If this template has no extension opcode (the usual case) use None
 908      Instructions */
 909   unsigned short extension_opcode;
 910 #define None 0xffff             /* If no extension_opcode is possible.  */
 911
 912   /* Opcode length.  */
 913   unsigned char opcode_length;
 914
 915   /* how many operands */
 916   unsigned char operands;
 917
 918   /* cpu feature flags */
 919   i386_cpu_flags cpu_flags;
 920
 921   /* the bits in opcode_modifier are used to generate the final opcode from
 922      the base_opcode.  These bits also are used to detect alternate forms of
 923      the same instruction */
 924   i386_opcode_modifier opcode_modifier;
 925
 926   /* operand_types[i] describes the type of operand i.  This is made
 927      by OR'ing together all of the possible type masks.  (e.g.
 928      'operand_types[i] = Reg|Imm' specifies that operand i can be
 929      either a register or an immediate operand.  */
 930   i386_operand_type operand_types[MAX_OPERANDS];
 931 }
 932 insn_template;
 933
 934 extern const insn_template i386_optab[];
 935
 936 /* these are for register name --> number & type hash lookup */
 937 typedef struct
 938 {
 939   const char *reg_name;
 940   i386_operand_type reg_type;
 941   unsigned char reg_flags;
 942 #define RegRex      0x1  /* Extended register.  */
 943 #define RegRex64    0x2  /* Extended 8 bit register.  */
 944 #define RegVRex     0x4  /* Extended vector register.  */
 945   unsigned char reg_num;
 946 #define RegIP   ((unsigned char ) ~0)
 947 /* EIZ and RIZ are fake index registers.  */
 948 #define RegIZ   (RegIP - 1)
 949 /* FLAT is a fake segment register (Intel mode).  */
 950 #define RegFlat     ((unsigned char) ~0)
 951   signed char dw2_regnum[2];
 952 #define Dw2Inval (-1)
 953 }
 954 reg_entry;
 955
 956 /* Entries in i386_regtab.  */
 957 #define REGNAM_AL 1
 958 #define REGNAM_AX 25
 959 #define REGNAM_EAX 41
 960
 961 extern const reg_entry i386_regtab[];
 962 extern const unsigned int i386_regtab_size;
 963
 964 typedef struct
 965 {
 966   char *seg_name;
 967   unsigned int seg_prefix;
 968 }
 969 seg_entry;
 970
 971 extern const seg_entry cs;
 972 extern const seg_entry ds;
 973 extern const seg_entry ss;
 974 extern const seg_entry es;
 975 extern const seg_entry fs;
 976 extern const seg_entry gs;