opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010, 2012
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel AVX-512 Foundation Instructions support required */
  98   CpuAVX512F,
  99   /* Intel AVX-512 Conflict Detection Instructions support required */
 100   CpuAVX512CD,
 101   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 102      required */
 103   CpuAVX512ER,
 104   /* Intel AVX-512 Prefetch Instructions support required */
 105   CpuAVX512PF,
 106   /* Intel L1OM support required */
 107   CpuL1OM,
 108   /* Intel K1OM support required */
 109   CpuK1OM,
 110   /* Xsave/xrstor New Instructions support required */
 111   CpuXsave,
 112   /* Xsaveopt New Instructions support required */
 113   CpuXsaveopt,
 114   /* AES support required */
 115   CpuAES,
 116   /* PCLMUL support required */
 117   CpuPCLMUL,
 118   /* FMA support required */
 119   CpuFMA,
 120   /* FMA4 support required */
 121   CpuFMA4,
 122   /* XOP support required */
 123   CpuXOP,
 124   /* LWP support required */
 125   CpuLWP,
 126   /* BMI support required */
 127   CpuBMI,
 128   /* TBM support required */
 129   CpuTBM,
 130   /* MOVBE Instruction support required */
 131   CpuMovbe,
 132   /* CMPXCHG16B instruction support required.  */
 133   CpuCX16,
 134   /* EPT Instructions required */
 135   CpuEPT,
 136   /* RDTSCP Instruction support required */
 137   CpuRdtscp,
 138   /* FSGSBASE Instructions required */
 139   CpuFSGSBase,
 140   /* RDRND Instructions required */
 141   CpuRdRnd,
 142   /* F16C Instructions required */
 143   CpuF16C,
 144   /* Intel BMI2 support required */
 145   CpuBMI2,
 146   /* LZCNT support required */
 147   CpuLZCNT,
 148   /* HLE support required */
 149   CpuHLE,
 150   /* RTM support required */
 151   CpuRTM,
 152   /* INVPCID Instructions required */
 153   CpuINVPCID,
 154   /* VMFUNC Instruction required */
 155   CpuVMFUNC,
 156   /* Intel MPX Instructions required  */
 157   CpuMPX,
 158   /* 64bit support available, used by -march= in assembler.  */
 159   CpuLM,
 160   /* RDRSEED instruction required.  */
 161   CpuRDSEED,
 162   /* Multi-presisionn add-carry instructions are required.  */
 163   CpuADX,
 164   /* Supports prefetchw and prefetch instructions.  */
 165   CpuPRFCHW,
 166   /* SMAP instructions required.  */
 167   CpuSMAP,
 168   /* SHA instructions required.  */
 169   CpuSHA,
 170   /* VREX support required  */
 171   CpuVREX,
 172   /* CLFLUSHOPT instruction required */
 173   CpuClflushOpt,
 174   /* XSAVES/XRSTORS instruction required */
 175   CpuXSAVES,
 176   /* XSAVEC instruction required */
 177   CpuXSAVEC,
 178   /* 64bit support required  */
 179   Cpu64,
 180   /* Not supported in the 64bit mode  */
 181   CpuNo64,
 182   /* The last bitfield in i386_cpu_flags.  */
 183   CpuMax = CpuNo64
 184 };
 185
 186 #define CpuNumOfUints \
 187   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 188 #define CpuNumOfBits \
 189   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 190
 191 /* If you get a compiler error for zero width of the unused field,
 192    comment it out.  */
 193 #define CpuUnused       (CpuMax + 1)
 194
 195 /* We can check if an instruction is available with array instead
 196    of bitfield. */
 197 typedef union i386_cpu_flags
 198 {
 199   struct
 200     {
 201       unsigned int cpui186:1;
 202       unsigned int cpui286:1;
 203       unsigned int cpui386:1;
 204       unsigned int cpui486:1;
 205       unsigned int cpui586:1;
 206       unsigned int cpui686:1;
 207       unsigned int cpuclflush:1;
 208       unsigned int cpunop:1;
 209       unsigned int cpusyscall:1;
 210       unsigned int cpu8087:1;
 211       unsigned int cpu287:1;
 212       unsigned int cpu387:1;
 213       unsigned int cpu687:1;
 214       unsigned int cpufisttp:1;
 215       unsigned int cpummx:1;
 216       unsigned int cpusse:1;
 217       unsigned int cpusse2:1;
 218       unsigned int cpua3dnow:1;
 219       unsigned int cpua3dnowa:1;
 220       unsigned int cpusse3:1;
 221       unsigned int cpupadlock:1;
 222       unsigned int cpusvme:1;
 223       unsigned int cpuvmx:1;
 224       unsigned int cpusmx:1;
 225       unsigned int cpussse3:1;
 226       unsigned int cpusse4a:1;
 227       unsigned int cpuabm:1;
 228       unsigned int cpusse4_1:1;
 229       unsigned int cpusse4_2:1;
 230       unsigned int cpuavx:1;
 231       unsigned int cpuavx2:1;
 232       unsigned int cpuavx512f:1;
 233       unsigned int cpuavx512cd:1;
 234       unsigned int cpuavx512er:1;
 235       unsigned int cpuavx512pf:1;
 236       unsigned int cpul1om:1;
 237       unsigned int cpuk1om:1;
 238       unsigned int cpuxsave:1;
 239       unsigned int cpuxsaveopt:1;
 240       unsigned int cpuaes:1;
 241       unsigned int cpupclmul:1;
 242       unsigned int cpufma:1;
 243       unsigned int cpufma4:1;
 244       unsigned int cpuxop:1;
 245       unsigned int cpulwp:1;
 246       unsigned int cpubmi:1;
 247       unsigned int cputbm:1;
 248       unsigned int cpumovbe:1;
 249       unsigned int cpucx16:1;
 250       unsigned int cpuept:1;
 251       unsigned int cpurdtscp:1;
 252       unsigned int cpufsgsbase:1;
 253       unsigned int cpurdrnd:1;
 254       unsigned int cpuf16c:1;
 255       unsigned int cpubmi2:1;
 256       unsigned int cpulzcnt:1;
 257       unsigned int cpuhle:1;
 258       unsigned int cpurtm:1;
 259       unsigned int cpuinvpcid:1;
 260       unsigned int cpuvmfunc:1;
 261       unsigned int cpumpx:1;
 262       unsigned int cpulm:1;
 263       unsigned int cpurdseed:1;
 264       unsigned int cpuadx:1;
 265       unsigned int cpuprfchw:1;
 266       unsigned int cpusmap:1;
 267       unsigned int cpusha:1;
 268       unsigned int cpuvrex:1;
 269       unsigned int cpuclflushopt:1;
 270       unsigned int cpuxsaves:1;
 271       unsigned int cpuxsavec:1;
 272       unsigned int cpu64:1;
 273       unsigned int cpuno64:1;
 274 #ifdef CpuUnused
 275       unsigned int unused:(CpuNumOfBits - CpuUnused);
 276 #endif
 277     } bitfield;
 278   unsigned int array[CpuNumOfUints];
 279 } i386_cpu_flags;
 280
 281 /* Position of opcode_modifier bits.  */
 282
 283 enum
 284 {
 285   /* has direction bit. */
 286   D = 0,
 287   /* set if operands can be words or dwords encoded the canonical way */
 288   W,
 289   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 290      operand in encoding.  */
 291   S,
 292   /* insn has a modrm byte. */
 293   Modrm,
 294   /* register is in low 3 bits of opcode */
 295   ShortForm,
 296   /* special case for jump insns.  */
 297   Jump,
 298   /* call and jump */
 299   JumpDword,
 300   /* loop and jecxz */
 301   JumpByte,
 302   /* special case for intersegment leaps/calls */
 303   JumpInterSegment,
 304   /* FP insn memory format bit, sized by 0x4 */
 305   FloatMF,
 306   /* src/dest swap for floats. */
 307   FloatR,
 308   /* has float insn direction bit. */
 309   FloatD,
 310   /* needs size prefix if in 32-bit mode */
 311   Size16,
 312   /* needs size prefix if in 16-bit mode */
 313   Size32,
 314   /* needs size prefix if in 64-bit mode */
 315   Size64,
 316   /* check register size.  */
 317   CheckRegSize,
 318   /* instruction ignores operand size prefix and in Intel mode ignores
 319      mnemonic size suffix check.  */
 320   IgnoreSize,
 321   /* default insn size depends on mode */
 322   DefaultSize,
 323   /* b suffix on instruction illegal */
 324   No_bSuf,
 325   /* w suffix on instruction illegal */
 326   No_wSuf,
 327   /* l suffix on instruction illegal */
 328   No_lSuf,
 329   /* s suffix on instruction illegal */
 330   No_sSuf,
 331   /* q suffix on instruction illegal */
 332   No_qSuf,
 333   /* long double suffix on instruction illegal */
 334   No_ldSuf,
 335   /* instruction needs FWAIT */
 336   FWait,
 337   /* quick test for string instructions */
 338   IsString,
 339   /* quick test if branch instruction is MPX supported */
 340   BNDPrefixOk,
 341   /* quick test for lockable instructions */
 342   IsLockable,
 343   /* fake an extra reg operand for clr, imul and special register
 344      processing for some instructions.  */
 345   RegKludge,
 346   /* The first operand must be xmm0 */
 347   FirstXmm0,
 348   /* An implicit xmm0 as the first operand */
 349   Implicit1stXmm0,
 350   /* The HLE prefix is OK:
 351      1. With a LOCK prefix.
 352      2. With or without a LOCK prefix.
 353      3. With a RELEASE (0xf3) prefix.
 354    */
 355 #define HLEPrefixNone           0
 356 #define HLEPrefixLock           1
 357 #define HLEPrefixAny            2
 358 #define HLEPrefixRelease        3
 359   HLEPrefixOk,
 360   /* An instruction on which a "rep" prefix is acceptable.  */
 361   RepPrefixOk,
 362   /* Convert to DWORD */
 363   ToDword,
 364   /* Convert to QWORD */
 365   ToQword,
 366   /* Address prefix changes operand 0 */
 367   AddrPrefixOp0,
 368   /* opcode is a prefix */
 369   IsPrefix,
 370   /* instruction has extension in 8 bit imm */
 371   ImmExt,
 372   /* instruction don't need Rex64 prefix.  */
 373   NoRex64,
 374   /* instruction require Rex64 prefix.  */
 375   Rex64,
 376   /* deprecated fp insn, gets a warning */
 377   Ugh,
 378   /* insn has VEX prefix:
 379         1: 128bit VEX prefix.
 380         2: 256bit VEX prefix.
 381         3: Scalar VEX prefix.
 382    */
 383 #define VEX128          1
 384 #define VEX256          2
 385 #define VEXScalar       3
 386   Vex,
 387   /* How to encode VEX.vvvv:
 388      0: VEX.vvvv must be 1111b.
 389      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 390         the content of source registers will be preserved.
 391         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 392         where the content of first source register will be overwritten
 393         by the result.
 394         VEX.NDD2.  The second destination register operand is encoded in
 395         VEX.vvvv for instructions with 2 destination register operands.
 396         For assembler, there are no difference between VEX.NDS, VEX.DDS
 397         and VEX.NDD2.
 398      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 399      instructions with 1 destination register operand.
 400      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 401         of the operands can access a memory location.
 402    */
 403 #define VEXXDS  1
 404 #define VEXNDD  2
 405 #define VEXLWP  3
 406   VexVVVV,
 407   /* How the VEX.W bit is used:
 408      0: Set by the REX.W bit.
 409      1: VEX.W0.  Should always be 0.
 410      2: VEX.W1.  Should always be 1.
 411    */
 412 #define VEXW0   1
 413 #define VEXW1   2
 414   VexW,
 415   /* VEX opcode prefix:
 416      0: VEX 0x0F opcode prefix.
 417      1: VEX 0x0F38 opcode prefix.
 418      2: VEX 0x0F3A opcode prefix
 419      3: XOP 0x08 opcode prefix.
 420      4: XOP 0x09 opcode prefix
 421      5: XOP 0x0A opcode prefix.
 422    */
 423 #define VEX0F           0
 424 #define VEX0F38         1
 425 #define VEX0F3A         2
 426 #define XOP08           3
 427 #define XOP09           4
 428 #define XOP0A           5
 429   VexOpcode,
 430   /* number of VEX source operands:
 431      0: <= 2 source operands.
 432      1: 2 XOP source operands.
 433      2: 3 source operands.
 434    */
 435 #define XOP2SOURCES     1
 436 #define VEX3SOURCES     2
 437   VexSources,
 438   /* instruction has VEX 8 bit imm */
 439   VexImmExt,
 440   /* Instruction with vector SIB byte:
 441         1: 128bit vector register.
 442         2: 256bit vector register.
 443         3: 512bit vector register.
 444    */
 445 #define VecSIB128       1
 446 #define VecSIB256       2
 447 #define VecSIB512       3
 448   VecSIB,
 449   /* SSE to AVX support required */
 450   SSE2AVX,
 451   /* No AVX equivalent */
 452   NoAVX,
 453
 454   /* insn has EVEX prefix:
 455         1: 512bit EVEX prefix.
 456         2: 128bit EVEX prefix.
 457         3: 256bit EVEX prefix.
 458         4: Length-ignored (LIG) EVEX prefix.
 459    */
 460 #define EVEX512                1
 461 #define EVEX128                2
 462 #define EVEX256                3
 463 #define EVEXLIG                4
 464   EVex,
 465
 466   /* AVX512 masking support:
 467         1: Zeroing-masking.
 468         2: Merging-masking.
 469         3: Both zeroing and merging masking.
 470    */
 471 #define ZEROING_MASKING 1
 472 #define MERGING_MASKING 2
 473 #define BOTH_MASKING    3
 474   Masking,
 475
 476   /* Input element size of vector insn:
 477         0: 32bit.
 478         1: 64bit.
 479    */
 480   VecESize,
 481
 482   /* Broadcast factor.
 483         0: No broadcast.
 484         1: 1to16 broadcast.
 485         2: 1to8 broadcast.
 486    */
 487 #define NO_BROADCAST    0
 488 #define BROADCAST_1TO16 1
 489 #define BROADCAST_1TO8  2
 490   Broadcast,
 491
 492   /* Static rounding control is supported.  */
 493   StaticRounding,
 494
 495   /* Supress All Exceptions is supported.  */
 496   SAE,
 497
 498   /* Copressed Disp8*N attribute.  */
 499   Disp8MemShift,
 500
 501   /* Default mask isn't allowed.  */
 502   NoDefMask,
 503
 504   /* Compatible with old (<= 2.8.1) versions of gcc  */
 505   OldGcc,
 506   /* AT&T mnemonic.  */
 507   ATTMnemonic,
 508   /* AT&T syntax.  */
 509   ATTSyntax,
 510   /* Intel syntax.  */
 511   IntelSyntax,
 512   /* The last bitfield in i386_opcode_modifier.  */
 513   Opcode_Modifier_Max
 514 };
 515
 516 typedef struct i386_opcode_modifier
 517 {
 518   unsigned int d:1;
 519   unsigned int w:1;
 520   unsigned int s:1;
 521   unsigned int modrm:1;
 522   unsigned int shortform:1;
 523   unsigned int jump:1;
 524   unsigned int jumpdword:1;
 525   unsigned int jumpbyte:1;
 526   unsigned int jumpintersegment:1;
 527   unsigned int floatmf:1;
 528   unsigned int floatr:1;
 529   unsigned int floatd:1;
 530   unsigned int size16:1;
 531   unsigned int size32:1;
 532   unsigned int size64:1;
 533   unsigned int checkregsize:1;
 534   unsigned int ignoresize:1;
 535   unsigned int defaultsize:1;
 536   unsigned int no_bsuf:1;
 537   unsigned int no_wsuf:1;
 538   unsigned int no_lsuf:1;
 539   unsigned int no_ssuf:1;
 540   unsigned int no_qsuf:1;
 541   unsigned int no_ldsuf:1;
 542   unsigned int fwait:1;
 543   unsigned int isstring:1;
 544   unsigned int bndprefixok:1;
 545   unsigned int islockable:1;
 546   unsigned int regkludge:1;
 547   unsigned int firstxmm0:1;
 548   unsigned int implicit1stxmm0:1;
 549   unsigned int hleprefixok:2;
 550   unsigned int repprefixok:1;
 551   unsigned int todword:1;
 552   unsigned int toqword:1;
 553   unsigned int addrprefixop0:1;
 554   unsigned int isprefix:1;
 555   unsigned int immext:1;
 556   unsigned int norex64:1;
 557   unsigned int rex64:1;
 558   unsigned int ugh:1;
 559   unsigned int vex:2;
 560   unsigned int vexvvvv:2;
 561   unsigned int vexw:2;
 562   unsigned int vexopcode:3;
 563   unsigned int vexsources:2;
 564   unsigned int veximmext:1;
 565   unsigned int vecsib:2;
 566   unsigned int sse2avx:1;
 567   unsigned int noavx:1;
 568   unsigned int evex:3;
 569   unsigned int masking:2;
 570   unsigned int vecesize:1;
 571   unsigned int broadcast:3;
 572   unsigned int staticrounding:1;
 573   unsigned int sae:1;
 574   unsigned int disp8memshift:3;
 575   unsigned int nodefmask:1;
 576   unsigned int oldgcc:1;
 577   unsigned int attmnemonic:1;
 578   unsigned int attsyntax:1;
 579   unsigned int intelsyntax:1;
 580 } i386_opcode_modifier;
 581
 582 /* Position of operand_type bits.  */
 583
 584 enum
 585 {
 586   /* 8bit register */
 587   Reg8 = 0,
 588   /* 16bit register */
 589   Reg16,
 590   /* 32bit register */
 591   Reg32,
 592   /* 64bit register */
 593   Reg64,
 594   /* Floating pointer stack register */
 595   FloatReg,
 596   /* MMX register */
 597   RegMMX,
 598   /* SSE register */
 599   RegXMM,
 600   /* AVX registers */
 601   RegYMM,
 602   /* AVX512 registers */
 603   RegZMM,
 604   /* Vector Mask registers */
 605   RegMask,
 606   /* Control register */
 607   Control,
 608   /* Debug register */
 609   Debug,
 610   /* Test register */
 611   Test,
 612   /* 2 bit segment register */
 613   SReg2,
 614   /* 3 bit segment register */
 615   SReg3,
 616   /* 1 bit immediate */
 617   Imm1,
 618   /* 8 bit immediate */
 619   Imm8,
 620   /* 8 bit immediate sign extended */
 621   Imm8S,
 622   /* 16 bit immediate */
 623   Imm16,
 624   /* 32 bit immediate */
 625   Imm32,
 626   /* 32 bit immediate sign extended */
 627   Imm32S,
 628   /* 64 bit immediate */
 629   Imm64,
 630   /* 8bit/16bit/32bit displacements are used in different ways,
 631      depending on the instruction.  For jumps, they specify the
 632      size of the PC relative displacement, for instructions with
 633      memory operand, they specify the size of the offset relative
 634      to the base register, and for instructions with memory offset
 635      such as `mov 1234,%al' they specify the size of the offset
 636      relative to the segment base.  */
 637   /* 8 bit displacement */
 638   Disp8,
 639   /* 16 bit displacement */
 640   Disp16,
 641   /* 32 bit displacement */
 642   Disp32,
 643   /* 32 bit signed displacement */
 644   Disp32S,
 645   /* 64 bit displacement */
 646   Disp64,
 647   /* Accumulator %al/%ax/%eax/%rax */
 648   Acc,
 649   /* Floating pointer top stack register %st(0) */
 650   FloatAcc,
 651   /* Register which can be used for base or index in memory operand.  */
 652   BaseIndex,
 653   /* Register to hold in/out port addr = dx */
 654   InOutPortReg,
 655   /* Register to hold shift count = cl */
 656   ShiftCount,
 657   /* Absolute address for jump.  */
 658   JumpAbsolute,
 659   /* String insn operand with fixed es segment */
 660   EsSeg,
 661   /* RegMem is for instructions with a modrm byte where the register
 662      destination operand should be encoded in the mod and regmem fields.
 663      Normally, it will be encoded in the reg field. We add a RegMem
 664      flag to the destination register operand to indicate that it should
 665      be encoded in the regmem field.  */
 666   RegMem,
 667   /* Memory.  */
 668   Mem,
 669   /* BYTE memory. */
 670   Byte,
 671   /* WORD memory. 2 byte */
 672   Word,
 673   /* DWORD memory. 4 byte */
 674   Dword,
 675   /* FWORD memory. 6 byte */
 676   Fword,
 677   /* QWORD memory. 8 byte */
 678   Qword,
 679   /* TBYTE memory. 10 byte */
 680   Tbyte,
 681   /* XMMWORD memory. */
 682   Xmmword,
 683   /* YMMWORD memory. */
 684   Ymmword,
 685   /* ZMMWORD memory.  */
 686   Zmmword,
 687   /* Unspecified memory size.  */
 688   Unspecified,
 689   /* Any memory size.  */
 690   Anysize,
 691
 692   /* Vector 4 bit immediate.  */
 693   Vec_Imm4,
 694
 695   /* Bound register.  */
 696   RegBND,
 697
 698   /* Vector 8bit displacement */
 699   Vec_Disp8,
 700
 701   /* The last bitfield in i386_operand_type.  */
 702   OTMax
 703 };
 704
 705 #define OTNumOfUints \
 706   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 707 #define OTNumOfBits \
 708   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 709
 710 /* If you get a compiler error for zero width of the unused field,
 711    comment it out.  */
 712 #define OTUnused                (OTMax + 1)
 713
 714 typedef union i386_operand_type
 715 {
 716   struct
 717     {
 718       unsigned int reg8:1;
 719       unsigned int reg16:1;
 720       unsigned int reg32:1;
 721       unsigned int reg64:1;
 722       unsigned int floatreg:1;
 723       unsigned int regmmx:1;
 724       unsigned int regxmm:1;
 725       unsigned int regymm:1;
 726       unsigned int regzmm:1;
 727       unsigned int regmask:1;
 728       unsigned int control:1;
 729       unsigned int debug:1;
 730       unsigned int test:1;
 731       unsigned int sreg2:1;
 732       unsigned int sreg3:1;
 733       unsigned int imm1:1;
 734       unsigned int imm8:1;
 735       unsigned int imm8s:1;
 736       unsigned int imm16:1;
 737       unsigned int imm32:1;
 738       unsigned int imm32s:1;
 739       unsigned int imm64:1;
 740       unsigned int disp8:1;
 741       unsigned int disp16:1;
 742       unsigned int disp32:1;
 743       unsigned int disp32s:1;
 744       unsigned int disp64:1;
 745       unsigned int acc:1;
 746       unsigned int floatacc:1;
 747       unsigned int baseindex:1;
 748       unsigned int inoutportreg:1;
 749       unsigned int shiftcount:1;
 750       unsigned int jumpabsolute:1;
 751       unsigned int esseg:1;
 752       unsigned int regmem:1;
 753       unsigned int mem:1;
 754       unsigned int byte:1;
 755       unsigned int word:1;
 756       unsigned int dword:1;
 757       unsigned int fword:1;
 758       unsigned int qword:1;
 759       unsigned int tbyte:1;
 760       unsigned int xmmword:1;
 761       unsigned int ymmword:1;
 762       unsigned int zmmword:1;
 763       unsigned int unspecified:1;
 764       unsigned int anysize:1;
 765       unsigned int vec_imm4:1;
 766       unsigned int regbnd:1;
 767       unsigned int vec_disp8:1;
 768 #ifdef OTUnused
 769       unsigned int unused:(OTNumOfBits - OTUnused);
 770 #endif
 771     } bitfield;
 772   unsigned int array[OTNumOfUints];
 773 } i386_operand_type;
 774
 775 typedef struct insn_template
 776 {
 777   /* instruction name sans width suffix ("mov" for movl insns) */
 778   char *name;
 779
 780   /* how many operands */
 781   unsigned int operands;
 782
 783   /* base_opcode is the fundamental opcode byte without optional
 784      prefix(es).  */
 785   unsigned int base_opcode;
 786 #define Opcode_D        0x2 /* Direction bit:
 787                                set if Reg --> Regmem;
 788                                unset if Regmem --> Reg. */
 789 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 790 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 791
 792   /* extension_opcode is the 3 bit extension for group <n> insns.
 793      This field is also used to store the 8-bit opcode suffix for the
 794      AMD 3DNow! instructions.
 795      If this template has no extension opcode (the usual case) use None
 796      Instructions */
 797   unsigned int extension_opcode;
 798 #define None 0xffff             /* If no extension_opcode is possible.  */
 799
 800   /* Opcode length.  */
 801   unsigned char opcode_length;
 802
 803   /* cpu feature flags */
 804   i386_cpu_flags cpu_flags;
 805
 806   /* the bits in opcode_modifier are used to generate the final opcode from
 807      the base_opcode.  These bits also are used to detect alternate forms of
 808      the same instruction */
 809   i386_opcode_modifier opcode_modifier;
 810
 811   /* operand_types[i] describes the type of operand i.  This is made
 812      by OR'ing together all of the possible type masks.  (e.g.
 813      'operand_types[i] = Reg|Imm' specifies that operand i can be
 814      either a register or an immediate operand.  */
 815   i386_operand_type operand_types[MAX_OPERANDS];
 816 }
 817 insn_template;
 818
 819 extern const insn_template i386_optab[];
 820
 821 /* these are for register name --> number & type hash lookup */
 822 typedef struct
 823 {
 824   char *reg_name;
 825   i386_operand_type reg_type;
 826   unsigned char reg_flags;
 827 #define RegRex      0x1  /* Extended register.  */
 828 #define RegRex64    0x2  /* Extended 8 bit register.  */
 829 #define RegVRex     0x4  /* Extended vector register.  */
 830   unsigned char reg_num;
 831 #define RegRip  ((unsigned char ) ~0)
 832 #define RegEip  (RegRip - 1)
 833 /* EIZ and RIZ are fake index registers.  */
 834 #define RegEiz  (RegEip - 1)
 835 #define RegRiz  (RegEiz - 1)
 836 /* FLAT is a fake segment register (Intel mode).  */
 837 #define RegFlat     ((unsigned char) ~0)
 838   signed char dw2_regnum[2];
 839 #define Dw2Inval (-1)
 840 }
 841 reg_entry;
 842
 843 /* Entries in i386_regtab.  */
 844 #define REGNAM_AL 1
 845 #define REGNAM_AX 25
 846 #define REGNAM_EAX 41
 847
 848 extern const reg_entry i386_regtab[];
 849 extern const unsigned int i386_regtab_size;
 850
 851 typedef struct
 852 {
 853   char *seg_name;
 854   unsigned int seg_prefix;
 855 }
 856 seg_entry;
 857
 858 extern const seg_entry cs;
 859 extern const seg_entry ds;
 860 extern const seg_entry ss;
 861 extern const seg_entry es;
 862 extern const seg_entry fs;
 863 extern const seg_entry gs;