opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instruction support required */
 218   CpuCET,
 219   /* GFNI instructions required */
 220   CpuGFNI,
 221   /* VAES instructions required */
 222   CpuVAES,
 223   /* VPCLMULQDQ instructions required */
 224   CpuVPCLMULQDQ,
 225   /* MMX register support required */
 226   CpuRegMMX,
 227   /* XMM register support required */
 228   CpuRegXMM,
 229   /* YMM register support required */
 230   CpuRegYMM,
 231   /* ZMM register support required */
 232   CpuRegZMM,
 233   /* Mask register support required */
 234   CpuRegMask,
 235   /* 64bit support required  */
 236   Cpu64,
 237   /* Not supported in the 64bit mode  */
 238   CpuNo64,
 239   /* The last bitfield in i386_cpu_flags.  */
 240   CpuMax = CpuNo64
 241 };
 242
 243 #define CpuNumOfUints \
 244   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 245 #define CpuNumOfBits \
 246   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 247
 248 /* If you get a compiler error for zero width of the unused field,
 249    comment it out.  */
 250 #define CpuUnused       (CpuMax + 1)
 251
 252 /* We can check if an instruction is available with array instead
 253    of bitfield. */
 254 typedef union i386_cpu_flags
 255 {
 256   struct
 257     {
 258       unsigned int cpui186:1;
 259       unsigned int cpui286:1;
 260       unsigned int cpui386:1;
 261       unsigned int cpui486:1;
 262       unsigned int cpui586:1;
 263       unsigned int cpui686:1;
 264       unsigned int cpuclflush:1;
 265       unsigned int cpunop:1;
 266       unsigned int cpusyscall:1;
 267       unsigned int cpu8087:1;
 268       unsigned int cpu287:1;
 269       unsigned int cpu387:1;
 270       unsigned int cpu687:1;
 271       unsigned int cpufisttp:1;
 272       unsigned int cpummx:1;
 273       unsigned int cpusse:1;
 274       unsigned int cpusse2:1;
 275       unsigned int cpua3dnow:1;
 276       unsigned int cpua3dnowa:1;
 277       unsigned int cpusse3:1;
 278       unsigned int cpupadlock:1;
 279       unsigned int cpusvme:1;
 280       unsigned int cpuvmx:1;
 281       unsigned int cpusmx:1;
 282       unsigned int cpussse3:1;
 283       unsigned int cpusse4a:1;
 284       unsigned int cpuabm:1;
 285       unsigned int cpusse4_1:1;
 286       unsigned int cpusse4_2:1;
 287       unsigned int cpuavx:1;
 288       unsigned int cpuavx2:1;
 289       unsigned int cpuavx512f:1;
 290       unsigned int cpuavx512cd:1;
 291       unsigned int cpuavx512er:1;
 292       unsigned int cpuavx512pf:1;
 293       unsigned int cpuavx512vl:1;
 294       unsigned int cpuavx512dq:1;
 295       unsigned int cpuavx512bw:1;
 296       unsigned int cpul1om:1;
 297       unsigned int cpuk1om:1;
 298       unsigned int cpuiamcu:1;
 299       unsigned int cpuxsave:1;
 300       unsigned int cpuxsaveopt:1;
 301       unsigned int cpuaes:1;
 302       unsigned int cpupclmul:1;
 303       unsigned int cpufma:1;
 304       unsigned int cpufma4:1;
 305       unsigned int cpuxop:1;
 306       unsigned int cpulwp:1;
 307       unsigned int cpubmi:1;
 308       unsigned int cputbm:1;
 309       unsigned int cpumovbe:1;
 310       unsigned int cpucx16:1;
 311       unsigned int cpuept:1;
 312       unsigned int cpurdtscp:1;
 313       unsigned int cpufsgsbase:1;
 314       unsigned int cpurdrnd:1;
 315       unsigned int cpuf16c:1;
 316       unsigned int cpubmi2:1;
 317       unsigned int cpulzcnt:1;
 318       unsigned int cpuhle:1;
 319       unsigned int cpurtm:1;
 320       unsigned int cpuinvpcid:1;
 321       unsigned int cpuvmfunc:1;
 322       unsigned int cpumpx:1;
 323       unsigned int cpulm:1;
 324       unsigned int cpurdseed:1;
 325       unsigned int cpuadx:1;
 326       unsigned int cpuprfchw:1;
 327       unsigned int cpusmap:1;
 328       unsigned int cpusha:1;
 329       unsigned int cpuvrex:1;
 330       unsigned int cpuclflushopt:1;
 331       unsigned int cpuxsaves:1;
 332       unsigned int cpuxsavec:1;
 333       unsigned int cpuprefetchwt1:1;
 334       unsigned int cpuse1:1;
 335       unsigned int cpuclwb:1;
 336       unsigned int cpuavx512ifma:1;
 337       unsigned int cpuavx512vbmi:1;
 338       unsigned int cpuavx512_4fmaps:1;
 339       unsigned int cpuavx512_4vnniw:1;
 340       unsigned int cpuavx512_vpopcntdq:1;
 341       unsigned int cpuavx512_vbmi2:1;
 342       unsigned int cpuavx512_vnni:1;
 343       unsigned int cpuavx512_bitalg:1;
 344       unsigned int cpumwaitx:1;
 345       unsigned int cpuclzero:1;
 346       unsigned int cpuospke:1;
 347       unsigned int cpurdpid:1;
 348       unsigned int cpuptwrite:1;
 349       unsigned int cpucet:1;
 350       unsigned int cpugfni:1;
 351       unsigned int cpuvaes:1;
 352       unsigned int cpuvpclmulqdq:1;
 353       unsigned int cpuregmmx:1;
 354       unsigned int cpuregxmm:1;
 355       unsigned int cpuregymm:1;
 356       unsigned int cpuregzmm:1;
 357       unsigned int cpuregmask:1;
 358       unsigned int cpu64:1;
 359       unsigned int cpuno64:1;
 360 #ifdef CpuUnused
 361       unsigned int unused:(CpuNumOfBits - CpuUnused);
 362 #endif
 363     } bitfield;
 364   unsigned int array[CpuNumOfUints];
 365 } i386_cpu_flags;
 366
 367 /* Position of opcode_modifier bits.  */
 368
 369 enum
 370 {
 371   /* has direction bit. */
 372   D = 0,
 373   /* set if operands can be words or dwords encoded the canonical way */
 374   W,
 375   /* load form instruction. Must be placed before store form.  */
 376   Load,
 377   /* insn has a modrm byte. */
 378   Modrm,
 379   /* register is in low 3 bits of opcode */
 380   ShortForm,
 381   /* special case for jump insns.  */
 382   Jump,
 383   /* call and jump */
 384   JumpDword,
 385   /* loop and jecxz */
 386   JumpByte,
 387   /* special case for intersegment leaps/calls */
 388   JumpInterSegment,
 389   /* FP insn memory format bit, sized by 0x4 */
 390   FloatMF,
 391   /* src/dest swap for floats. */
 392   FloatR,
 393   /* has float insn direction bit. */
 394   FloatD,
 395   /* needs size prefix if in 32-bit mode */
 396   Size16,
 397   /* needs size prefix if in 16-bit mode */
 398   Size32,
 399   /* needs size prefix if in 64-bit mode */
 400   Size64,
 401   /* check register size.  */
 402   CheckRegSize,
 403   /* instruction ignores operand size prefix and in Intel mode ignores
 404      mnemonic size suffix check.  */
 405   IgnoreSize,
 406   /* default insn size depends on mode */
 407   DefaultSize,
 408   /* b suffix on instruction illegal */
 409   No_bSuf,
 410   /* w suffix on instruction illegal */
 411   No_wSuf,
 412   /* l suffix on instruction illegal */
 413   No_lSuf,
 414   /* s suffix on instruction illegal */
 415   No_sSuf,
 416   /* q suffix on instruction illegal */
 417   No_qSuf,
 418   /* long double suffix on instruction illegal */
 419   No_ldSuf,
 420   /* instruction needs FWAIT */
 421   FWait,
 422   /* quick test for string instructions */
 423   IsString,
 424   /* quick test if branch instruction is MPX supported */
 425   BNDPrefixOk,
 426   /* quick test if NOTRACK prefix is supported */
 427   NoTrackPrefixOk,
 428   /* quick test for lockable instructions */
 429   IsLockable,
 430   /* fake an extra reg operand for clr, imul and special register
 431      processing for some instructions.  */
 432   RegKludge,
 433   /* An implicit xmm0 as the first operand */
 434   Implicit1stXmm0,
 435   /* The HLE prefix is OK:
 436      1. With a LOCK prefix.
 437      2. With or without a LOCK prefix.
 438      3. With a RELEASE (0xf3) prefix.
 439    */
 440 #define HLEPrefixNone           0
 441 #define HLEPrefixLock           1
 442 #define HLEPrefixAny            2
 443 #define HLEPrefixRelease        3
 444   HLEPrefixOk,
 445   /* An instruction on which a "rep" prefix is acceptable.  */
 446   RepPrefixOk,
 447   /* Convert to DWORD */
 448   ToDword,
 449   /* Convert to QWORD */
 450   ToQword,
 451   /* Address prefix changes operand 0 */
 452   AddrPrefixOp0,
 453   /* opcode is a prefix */
 454   IsPrefix,
 455   /* instruction has extension in 8 bit imm */
 456   ImmExt,
 457   /* instruction don't need Rex64 prefix.  */
 458   NoRex64,
 459   /* instruction require Rex64 prefix.  */
 460   Rex64,
 461   /* deprecated fp insn, gets a warning */
 462   Ugh,
 463   /* insn has VEX prefix:
 464         1: 128bit VEX prefix (or operand dependent).
 465         2: 256bit VEX prefix.
 466         3: Scalar VEX prefix.
 467    */
 468 #define VEX128          1
 469 #define VEX256          2
 470 #define VEXScalar       3
 471   Vex,
 472   /* How to encode VEX.vvvv:
 473      0: VEX.vvvv must be 1111b.
 474      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 475         the content of source registers will be preserved.
 476         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 477         where the content of first source register will be overwritten
 478         by the result.
 479         VEX.NDD2.  The second destination register operand is encoded in
 480         VEX.vvvv for instructions with 2 destination register operands.
 481         For assembler, there are no difference between VEX.NDS, VEX.DDS
 482         and VEX.NDD2.
 483      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 484      instructions with 1 destination register operand.
 485      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 486         of the operands can access a memory location.
 487    */
 488 #define VEXXDS  1
 489 #define VEXNDD  2
 490 #define VEXLWP  3
 491   VexVVVV,
 492   /* How the VEX.W bit is used:
 493      0: Set by the REX.W bit.
 494      1: VEX.W0.  Should always be 0.
 495      2: VEX.W1.  Should always be 1.
 496    */
 497 #define VEXW0   1
 498 #define VEXW1   2
 499   VexW,
 500   /* VEX opcode prefix:
 501      0: VEX 0x0F opcode prefix.
 502      1: VEX 0x0F38 opcode prefix.
 503      2: VEX 0x0F3A opcode prefix
 504      3: XOP 0x08 opcode prefix.
 505      4: XOP 0x09 opcode prefix
 506      5: XOP 0x0A opcode prefix.
 507    */
 508 #define VEX0F           0
 509 #define VEX0F38         1
 510 #define VEX0F3A         2
 511 #define XOP08           3
 512 #define XOP09           4
 513 #define XOP0A           5
 514   VexOpcode,
 515   /* number of VEX source operands:
 516      0: <= 2 source operands.
 517      1: 2 XOP source operands.
 518      2: 3 source operands.
 519    */
 520 #define XOP2SOURCES     1
 521 #define VEX3SOURCES     2
 522   VexSources,
 523   /* instruction has VEX 8 bit imm */
 524   VexImmExt,
 525   /* Instruction with vector SIB byte:
 526         1: 128bit vector register.
 527         2: 256bit vector register.
 528         3: 512bit vector register.
 529    */
 530 #define VecSIB128       1
 531 #define VecSIB256       2
 532 #define VecSIB512       3
 533   VecSIB,
 534   /* SSE to AVX support required */
 535   SSE2AVX,
 536   /* No AVX equivalent */
 537   NoAVX,
 538
 539   /* insn has EVEX prefix:
 540         1: 512bit EVEX prefix.
 541         2: 128bit EVEX prefix.
 542         3: 256bit EVEX prefix.
 543         4: Length-ignored (LIG) EVEX prefix.
 544    */
 545 #define EVEX512                1
 546 #define EVEX128                2
 547 #define EVEX256                3
 548 #define EVEXLIG                4
 549   EVex,
 550
 551   /* AVX512 masking support:
 552         1: Zeroing-masking.
 553         2: Merging-masking.
 554         3: Both zeroing and merging masking.
 555    */
 556 #define ZEROING_MASKING 1
 557 #define MERGING_MASKING 2
 558 #define BOTH_MASKING    3
 559   Masking,
 560
 561   /* Input element size of vector insn:
 562         0: 32bit.
 563         1: 64bit.
 564    */
 565   VecESize,
 566
 567   /* Broadcast factor.
 568         0: No broadcast.
 569         1: 1to16 broadcast.
 570         2: 1to8 broadcast.
 571    */
 572 #define NO_BROADCAST    0
 573 #define BROADCAST_1TO16 1
 574 #define BROADCAST_1TO8  2
 575 #define BROADCAST_1TO4  3
 576 #define BROADCAST_1TO2  4
 577   Broadcast,
 578
 579   /* Static rounding control is supported.  */
 580   StaticRounding,
 581
 582   /* Supress All Exceptions is supported.  */
 583   SAE,
 584
 585   /* Copressed Disp8*N attribute.  */
 586   Disp8MemShift,
 587
 588   /* Default mask isn't allowed.  */
 589   NoDefMask,
 590
 591   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 592      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 593    */
 594   ImplicitQuadGroup,
 595
 596   /* Compatible with old (<= 2.8.1) versions of gcc  */
 597   OldGcc,
 598   /* AT&T mnemonic.  */
 599   ATTMnemonic,
 600   /* AT&T syntax.  */
 601   ATTSyntax,
 602   /* Intel syntax.  */
 603   IntelSyntax,
 604   /* AMD64.  */
 605   AMD64,
 606   /* Intel64.  */
 607   Intel64,
 608   /* The last bitfield in i386_opcode_modifier.  */
 609   Opcode_Modifier_Max
 610 };
 611
 612 typedef struct i386_opcode_modifier
 613 {
 614   unsigned int d:1;
 615   unsigned int w:1;
 616   unsigned int load:1;
 617   unsigned int modrm:1;
 618   unsigned int shortform:1;
 619   unsigned int jump:1;
 620   unsigned int jumpdword:1;
 621   unsigned int jumpbyte:1;
 622   unsigned int jumpintersegment:1;
 623   unsigned int floatmf:1;
 624   unsigned int floatr:1;
 625   unsigned int floatd:1;
 626   unsigned int size16:1;
 627   unsigned int size32:1;
 628   unsigned int size64:1;
 629   unsigned int checkregsize:1;
 630   unsigned int ignoresize:1;
 631   unsigned int defaultsize:1;
 632   unsigned int no_bsuf:1;
 633   unsigned int no_wsuf:1;
 634   unsigned int no_lsuf:1;
 635   unsigned int no_ssuf:1;
 636   unsigned int no_qsuf:1;
 637   unsigned int no_ldsuf:1;
 638   unsigned int fwait:1;
 639   unsigned int isstring:1;
 640   unsigned int bndprefixok:1;
 641   unsigned int notrackprefixok:1;
 642   unsigned int islockable:1;
 643   unsigned int regkludge:1;
 644   unsigned int implicit1stxmm0:1;
 645   unsigned int hleprefixok:2;
 646   unsigned int repprefixok:1;
 647   unsigned int todword:1;
 648   unsigned int toqword:1;
 649   unsigned int addrprefixop0:1;
 650   unsigned int isprefix:1;
 651   unsigned int immext:1;
 652   unsigned int norex64:1;
 653   unsigned int rex64:1;
 654   unsigned int ugh:1;
 655   unsigned int vex:2;
 656   unsigned int vexvvvv:2;
 657   unsigned int vexw:2;
 658   unsigned int vexopcode:3;
 659   unsigned int vexsources:2;
 660   unsigned int veximmext:1;
 661   unsigned int vecsib:2;
 662   unsigned int sse2avx:1;
 663   unsigned int noavx:1;
 664   unsigned int evex:3;
 665   unsigned int masking:2;
 666   unsigned int vecesize:1;
 667   unsigned int broadcast:3;
 668   unsigned int staticrounding:1;
 669   unsigned int sae:1;
 670   unsigned int disp8memshift:3;
 671   unsigned int nodefmask:1;
 672   unsigned int implicitquadgroup:1;
 673   unsigned int oldgcc:1;
 674   unsigned int attmnemonic:1;
 675   unsigned int attsyntax:1;
 676   unsigned int intelsyntax:1;
 677   unsigned int amd64:1;
 678   unsigned int intel64:1;
 679 } i386_opcode_modifier;
 680
 681 /* Position of operand_type bits.  */
 682
 683 enum
 684 {
 685   /* Register (qualified by Byte, Word, etc) */
 686   Reg = 0,
 687   /* MMX register */
 688   RegMMX,
 689   /* Vector registers */
 690   RegSIMD,
 691   /* Vector Mask registers */
 692   RegMask,
 693   /* Control register */
 694   Control,
 695   /* Debug register */
 696   Debug,
 697   /* Test register */
 698   Test,
 699   /* 2 bit segment register */
 700   SReg2,
 701   /* 3 bit segment register */
 702   SReg3,
 703   /* 1 bit immediate */
 704   Imm1,
 705   /* 8 bit immediate */
 706   Imm8,
 707   /* 8 bit immediate sign extended */
 708   Imm8S,
 709   /* 16 bit immediate */
 710   Imm16,
 711   /* 32 bit immediate */
 712   Imm32,
 713   /* 32 bit immediate sign extended */
 714   Imm32S,
 715   /* 64 bit immediate */
 716   Imm64,
 717   /* 8bit/16bit/32bit displacements are used in different ways,
 718      depending on the instruction.  For jumps, they specify the
 719      size of the PC relative displacement, for instructions with
 720      memory operand, they specify the size of the offset relative
 721      to the base register, and for instructions with memory offset
 722      such as `mov 1234,%al' they specify the size of the offset
 723      relative to the segment base.  */
 724   /* 8 bit displacement */
 725   Disp8,
 726   /* 16 bit displacement */
 727   Disp16,
 728   /* 32 bit displacement */
 729   Disp32,
 730   /* 32 bit signed displacement */
 731   Disp32S,
 732   /* 64 bit displacement */
 733   Disp64,
 734   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 735   Acc,
 736   /* Register which can be used for base or index in memory operand.  */
 737   BaseIndex,
 738   /* Register to hold in/out port addr = dx */
 739   InOutPortReg,
 740   /* Register to hold shift count = cl */
 741   ShiftCount,
 742   /* Absolute address for jump.  */
 743   JumpAbsolute,
 744   /* String insn operand with fixed es segment */
 745   EsSeg,
 746   /* RegMem is for instructions with a modrm byte where the register
 747      destination operand should be encoded in the mod and regmem fields.
 748      Normally, it will be encoded in the reg field. We add a RegMem
 749      flag to the destination register operand to indicate that it should
 750      be encoded in the regmem field.  */
 751   RegMem,
 752   /* Memory.  */
 753   Mem,
 754   /* BYTE memory. */
 755   Byte,
 756   /* WORD memory. 2 byte */
 757   Word,
 758   /* DWORD memory. 4 byte */
 759   Dword,
 760   /* FWORD memory. 6 byte */
 761   Fword,
 762   /* QWORD memory. 8 byte */
 763   Qword,
 764   /* TBYTE memory. 10 byte */
 765   Tbyte,
 766   /* XMMWORD memory. */
 767   Xmmword,
 768   /* YMMWORD memory. */
 769   Ymmword,
 770   /* ZMMWORD memory.  */
 771   Zmmword,
 772   /* Unspecified memory size.  */
 773   Unspecified,
 774   /* Any memory size.  */
 775   Anysize,
 776
 777   /* Vector 4 bit immediate.  */
 778   Vec_Imm4,
 779
 780   /* Bound register.  */
 781   RegBND,
 782
 783   /* The last bitfield in i386_operand_type.  */
 784   OTMax
 785 };
 786
 787 #define OTNumOfUints \
 788   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 789 #define OTNumOfBits \
 790   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 791
 792 /* If you get a compiler error for zero width of the unused field,
 793    comment it out.  */
 794 #define OTUnused                (OTMax + 1)
 795
 796 typedef union i386_operand_type
 797 {
 798   struct
 799     {
 800       unsigned int reg:1;
 801       unsigned int regmmx:1;
 802       unsigned int regsimd:1;
 803       unsigned int regmask:1;
 804       unsigned int control:1;
 805       unsigned int debug:1;
 806       unsigned int test:1;
 807       unsigned int sreg2:1;
 808       unsigned int sreg3:1;
 809       unsigned int imm1:1;
 810       unsigned int imm8:1;
 811       unsigned int imm8s:1;
 812       unsigned int imm16:1;
 813       unsigned int imm32:1;
 814       unsigned int imm32s:1;
 815       unsigned int imm64:1;
 816       unsigned int disp8:1;
 817       unsigned int disp16:1;
 818       unsigned int disp32:1;
 819       unsigned int disp32s:1;
 820       unsigned int disp64:1;
 821       unsigned int acc:1;
 822       unsigned int baseindex:1;
 823       unsigned int inoutportreg:1;
 824       unsigned int shiftcount:1;
 825       unsigned int jumpabsolute:1;
 826       unsigned int esseg:1;
 827       unsigned int regmem:1;
 828       unsigned int mem:1;
 829       unsigned int byte:1;
 830       unsigned int word:1;
 831       unsigned int dword:1;
 832       unsigned int fword:1;
 833       unsigned int qword:1;
 834       unsigned int tbyte:1;
 835       unsigned int xmmword:1;
 836       unsigned int ymmword:1;
 837       unsigned int zmmword:1;
 838       unsigned int unspecified:1;
 839       unsigned int anysize:1;
 840       unsigned int vec_imm4:1;
 841       unsigned int regbnd:1;
 842 #ifdef OTUnused
 843       unsigned int unused:(OTNumOfBits - OTUnused);
 844 #endif
 845     } bitfield;
 846   unsigned int array[OTNumOfUints];
 847 } i386_operand_type;
 848
 849 typedef struct insn_template
 850 {
 851   /* instruction name sans width suffix ("mov" for movl insns) */
 852   char *name;
 853
 854   /* how many operands */
 855   unsigned int operands;
 856
 857   /* base_opcode is the fundamental opcode byte without optional
 858      prefix(es).  */
 859   unsigned int base_opcode;
 860 #define Opcode_D        0x2 /* Direction bit:
 861                                set if Reg --> Regmem;
 862                                unset if Regmem --> Reg. */
 863 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 864 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 865
 866   /* extension_opcode is the 3 bit extension for group <n> insns.
 867      This field is also used to store the 8-bit opcode suffix for the
 868      AMD 3DNow! instructions.
 869      If this template has no extension opcode (the usual case) use None
 870      Instructions */
 871   unsigned int extension_opcode;
 872 #define None 0xffff             /* If no extension_opcode is possible.  */
 873
 874   /* Opcode length.  */
 875   unsigned char opcode_length;
 876
 877   /* cpu feature flags */
 878   i386_cpu_flags cpu_flags;
 879
 880   /* the bits in opcode_modifier are used to generate the final opcode from
 881      the base_opcode.  These bits also are used to detect alternate forms of
 882      the same instruction */
 883   i386_opcode_modifier opcode_modifier;
 884
 885   /* operand_types[i] describes the type of operand i.  This is made
 886      by OR'ing together all of the possible type masks.  (e.g.
 887      'operand_types[i] = Reg|Imm' specifies that operand i can be
 888      either a register or an immediate operand.  */
 889   i386_operand_type operand_types[MAX_OPERANDS];
 890 }
 891 insn_template;
 892
 893 extern const insn_template i386_optab[];
 894
 895 /* these are for register name --> number & type hash lookup */
 896 typedef struct
 897 {
 898   char *reg_name;
 899   i386_operand_type reg_type;
 900   unsigned char reg_flags;
 901 #define RegRex      0x1  /* Extended register.  */
 902 #define RegRex64    0x2  /* Extended 8 bit register.  */
 903 #define RegVRex     0x4  /* Extended vector register.  */
 904   unsigned char reg_num;
 905 #define RegRip  ((unsigned char ) ~0)
 906 #define RegEip  (RegRip - 1)
 907 /* EIZ and RIZ are fake index registers.  */
 908 #define RegEiz  (RegEip - 1)
 909 #define RegRiz  (RegEiz - 1)
 910 /* FLAT is a fake segment register (Intel mode).  */
 911 #define RegFlat     ((unsigned char) ~0)
 912   signed char dw2_regnum[2];
 913 #define Dw2Inval (-1)
 914 }
 915 reg_entry;
 916
 917 /* Entries in i386_regtab.  */
 918 #define REGNAM_AL 1
 919 #define REGNAM_AX 25
 920 #define REGNAM_EAX 41
 921
 922 extern const reg_entry i386_regtab[];
 923 extern const unsigned int i386_regtab_size;
 924
 925 typedef struct
 926 {
 927   char *seg_name;
 928   unsigned int seg_prefix;
 929 }
 930 seg_entry;
 931
 932 extern const seg_entry cs;
 933 extern const seg_entry ds;
 934 extern const seg_entry ss;
 935 extern const seg_entry es;
 936 extern const seg_entry fs;
 937 extern const seg_entry gs;