opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2015 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* PCOMMIT instruction required */
 192   CpuPCOMMIT,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Clzero instruction required */
 198   CpuCLZERO,
 199   /* 64bit support required  */
 200   Cpu64,
 201   /* Not supported in the 64bit mode  */
 202   CpuNo64,
 203   /* AMD64 support required  */
 204   CpuAMD64,
 205   /* Intel64 support required  */
 206   CpuIntel64,
 207   /* The last bitfield in i386_cpu_flags.  */
 208   CpuMax = CpuNo64
 209 };
 210
 211 #define CpuNumOfUints \
 212   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 213 #define CpuNumOfBits \
 214   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 215
 216 /* If you get a compiler error for zero width of the unused field,
 217    comment it out.  */
 218 #define CpuUnused       (CpuMax + 1)
 219
 220 /* We can check if an instruction is available with array instead
 221    of bitfield. */
 222 typedef union i386_cpu_flags
 223 {
 224   struct
 225     {
 226       unsigned int cpui186:1;
 227       unsigned int cpui286:1;
 228       unsigned int cpui386:1;
 229       unsigned int cpui486:1;
 230       unsigned int cpui586:1;
 231       unsigned int cpui686:1;
 232       unsigned int cpuclflush:1;
 233       unsigned int cpunop:1;
 234       unsigned int cpusyscall:1;
 235       unsigned int cpu8087:1;
 236       unsigned int cpu287:1;
 237       unsigned int cpu387:1;
 238       unsigned int cpu687:1;
 239       unsigned int cpufisttp:1;
 240       unsigned int cpummx:1;
 241       unsigned int cpusse:1;
 242       unsigned int cpusse2:1;
 243       unsigned int cpua3dnow:1;
 244       unsigned int cpua3dnowa:1;
 245       unsigned int cpusse3:1;
 246       unsigned int cpupadlock:1;
 247       unsigned int cpusvme:1;
 248       unsigned int cpuvmx:1;
 249       unsigned int cpusmx:1;
 250       unsigned int cpussse3:1;
 251       unsigned int cpusse4a:1;
 252       unsigned int cpuabm:1;
 253       unsigned int cpusse4_1:1;
 254       unsigned int cpusse4_2:1;
 255       unsigned int cpuavx:1;
 256       unsigned int cpuavx2:1;
 257       unsigned int cpuavx512f:1;
 258       unsigned int cpuavx512cd:1;
 259       unsigned int cpuavx512er:1;
 260       unsigned int cpuavx512pf:1;
 261       unsigned int cpuavx512vl:1;
 262       unsigned int cpuavx512dq:1;
 263       unsigned int cpuavx512bw:1;
 264       unsigned int cpul1om:1;
 265       unsigned int cpuk1om:1;
 266       unsigned int cpuiamcu:1;
 267       unsigned int cpuxsave:1;
 268       unsigned int cpuxsaveopt:1;
 269       unsigned int cpuaes:1;
 270       unsigned int cpupclmul:1;
 271       unsigned int cpufma:1;
 272       unsigned int cpufma4:1;
 273       unsigned int cpuxop:1;
 274       unsigned int cpulwp:1;
 275       unsigned int cpubmi:1;
 276       unsigned int cputbm:1;
 277       unsigned int cpumovbe:1;
 278       unsigned int cpucx16:1;
 279       unsigned int cpuept:1;
 280       unsigned int cpurdtscp:1;
 281       unsigned int cpufsgsbase:1;
 282       unsigned int cpurdrnd:1;
 283       unsigned int cpuf16c:1;
 284       unsigned int cpubmi2:1;
 285       unsigned int cpulzcnt:1;
 286       unsigned int cpuhle:1;
 287       unsigned int cpurtm:1;
 288       unsigned int cpuinvpcid:1;
 289       unsigned int cpuvmfunc:1;
 290       unsigned int cpumpx:1;
 291       unsigned int cpulm:1;
 292       unsigned int cpurdseed:1;
 293       unsigned int cpuadx:1;
 294       unsigned int cpuprfchw:1;
 295       unsigned int cpusmap:1;
 296       unsigned int cpusha:1;
 297       unsigned int cpuvrex:1;
 298       unsigned int cpuclflushopt:1;
 299       unsigned int cpuxsaves:1;
 300       unsigned int cpuxsavec:1;
 301       unsigned int cpuprefetchwt1:1;
 302       unsigned int cpuse1:1;
 303       unsigned int cpuclwb:1;
 304       unsigned int cpupcommit:1;
 305       unsigned int cpuavx512ifma:1;
 306       unsigned int cpuavx512vbmi:1;
 307       unsigned int cpuclzero:1;
 308       unsigned int cpu64:1;
 309       unsigned int cpuno64:1;
 310       unsigned int cpuamd64:1;
 311       unsigned int cpuintel64:1;
 312 #ifdef CpuUnused
 313       unsigned int unused:(CpuNumOfBits - CpuUnused);
 314 #endif
 315     } bitfield;
 316   unsigned int array[CpuNumOfUints];
 317 } i386_cpu_flags;
 318
 319 /* Position of opcode_modifier bits.  */
 320
 321 enum
 322 {
 323   /* has direction bit. */
 324   D = 0,
 325   /* set if operands can be words or dwords encoded the canonical way */
 326   W,
 327   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 328      operand in encoding.  */
 329   S,
 330   /* insn has a modrm byte. */
 331   Modrm,
 332   /* register is in low 3 bits of opcode */
 333   ShortForm,
 334   /* special case for jump insns.  */
 335   Jump,
 336   /* call and jump */
 337   JumpDword,
 338   /* loop and jecxz */
 339   JumpByte,
 340   /* special case for intersegment leaps/calls */
 341   JumpInterSegment,
 342   /* FP insn memory format bit, sized by 0x4 */
 343   FloatMF,
 344   /* src/dest swap for floats. */
 345   FloatR,
 346   /* has float insn direction bit. */
 347   FloatD,
 348   /* needs size prefix if in 32-bit mode */
 349   Size16,
 350   /* needs size prefix if in 16-bit mode */
 351   Size32,
 352   /* needs size prefix if in 64-bit mode */
 353   Size64,
 354   /* check register size.  */
 355   CheckRegSize,
 356   /* instruction ignores operand size prefix and in Intel mode ignores
 357      mnemonic size suffix check.  */
 358   IgnoreSize,
 359   /* default insn size depends on mode */
 360   DefaultSize,
 361   /* b suffix on instruction illegal */
 362   No_bSuf,
 363   /* w suffix on instruction illegal */
 364   No_wSuf,
 365   /* l suffix on instruction illegal */
 366   No_lSuf,
 367   /* s suffix on instruction illegal */
 368   No_sSuf,
 369   /* q suffix on instruction illegal */
 370   No_qSuf,
 371   /* long double suffix on instruction illegal */
 372   No_ldSuf,
 373   /* instruction needs FWAIT */
 374   FWait,
 375   /* quick test for string instructions */
 376   IsString,
 377   /* quick test if branch instruction is MPX supported */
 378   BNDPrefixOk,
 379   /* quick test for lockable instructions */
 380   IsLockable,
 381   /* fake an extra reg operand for clr, imul and special register
 382      processing for some instructions.  */
 383   RegKludge,
 384   /* The first operand must be xmm0 */
 385   FirstXmm0,
 386   /* An implicit xmm0 as the first operand */
 387   Implicit1stXmm0,
 388   /* The HLE prefix is OK:
 389      1. With a LOCK prefix.
 390      2. With or without a LOCK prefix.
 391      3. With a RELEASE (0xf3) prefix.
 392    */
 393 #define HLEPrefixNone           0
 394 #define HLEPrefixLock           1
 395 #define HLEPrefixAny            2
 396 #define HLEPrefixRelease        3
 397   HLEPrefixOk,
 398   /* An instruction on which a "rep" prefix is acceptable.  */
 399   RepPrefixOk,
 400   /* Convert to DWORD */
 401   ToDword,
 402   /* Convert to QWORD */
 403   ToQword,
 404   /* Address prefix changes operand 0 */
 405   AddrPrefixOp0,
 406   /* opcode is a prefix */
 407   IsPrefix,
 408   /* instruction has extension in 8 bit imm */
 409   ImmExt,
 410   /* instruction don't need Rex64 prefix.  */
 411   NoRex64,
 412   /* instruction require Rex64 prefix.  */
 413   Rex64,
 414   /* deprecated fp insn, gets a warning */
 415   Ugh,
 416   /* insn has VEX prefix:
 417         1: 128bit VEX prefix.
 418         2: 256bit VEX prefix.
 419         3: Scalar VEX prefix.
 420    */
 421 #define VEX128          1
 422 #define VEX256          2
 423 #define VEXScalar       3
 424   Vex,
 425   /* How to encode VEX.vvvv:
 426      0: VEX.vvvv must be 1111b.
 427      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 428         the content of source registers will be preserved.
 429         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 430         where the content of first source register will be overwritten
 431         by the result.
 432         VEX.NDD2.  The second destination register operand is encoded in
 433         VEX.vvvv for instructions with 2 destination register operands.
 434         For assembler, there are no difference between VEX.NDS, VEX.DDS
 435         and VEX.NDD2.
 436      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 437      instructions with 1 destination register operand.
 438      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 439         of the operands can access a memory location.
 440    */
 441 #define VEXXDS  1
 442 #define VEXNDD  2
 443 #define VEXLWP  3
 444   VexVVVV,
 445   /* How the VEX.W bit is used:
 446      0: Set by the REX.W bit.
 447      1: VEX.W0.  Should always be 0.
 448      2: VEX.W1.  Should always be 1.
 449    */
 450 #define VEXW0   1
 451 #define VEXW1   2
 452   VexW,
 453   /* VEX opcode prefix:
 454      0: VEX 0x0F opcode prefix.
 455      1: VEX 0x0F38 opcode prefix.
 456      2: VEX 0x0F3A opcode prefix
 457      3: XOP 0x08 opcode prefix.
 458      4: XOP 0x09 opcode prefix
 459      5: XOP 0x0A opcode prefix.
 460    */
 461 #define VEX0F           0
 462 #define VEX0F38         1
 463 #define VEX0F3A         2
 464 #define XOP08           3
 465 #define XOP09           4
 466 #define XOP0A           5
 467   VexOpcode,
 468   /* number of VEX source operands:
 469      0: <= 2 source operands.
 470      1: 2 XOP source operands.
 471      2: 3 source operands.
 472    */
 473 #define XOP2SOURCES     1
 474 #define VEX3SOURCES     2
 475   VexSources,
 476   /* instruction has VEX 8 bit imm */
 477   VexImmExt,
 478   /* Instruction with vector SIB byte:
 479         1: 128bit vector register.
 480         2: 256bit vector register.
 481         3: 512bit vector register.
 482    */
 483 #define VecSIB128       1
 484 #define VecSIB256       2
 485 #define VecSIB512       3
 486   VecSIB,
 487   /* SSE to AVX support required */
 488   SSE2AVX,
 489   /* No AVX equivalent */
 490   NoAVX,
 491
 492   /* insn has EVEX prefix:
 493         1: 512bit EVEX prefix.
 494         2: 128bit EVEX prefix.
 495         3: 256bit EVEX prefix.
 496         4: Length-ignored (LIG) EVEX prefix.
 497    */
 498 #define EVEX512                1
 499 #define EVEX128                2
 500 #define EVEX256                3
 501 #define EVEXLIG                4
 502   EVex,
 503
 504   /* AVX512 masking support:
 505         1: Zeroing-masking.
 506         2: Merging-masking.
 507         3: Both zeroing and merging masking.
 508    */
 509 #define ZEROING_MASKING 1
 510 #define MERGING_MASKING 2
 511 #define BOTH_MASKING    3
 512   Masking,
 513
 514   /* Input element size of vector insn:
 515         0: 32bit.
 516         1: 64bit.
 517    */
 518   VecESize,
 519
 520   /* Broadcast factor.
 521         0: No broadcast.
 522         1: 1to16 broadcast.
 523         2: 1to8 broadcast.
 524    */
 525 #define NO_BROADCAST    0
 526 #define BROADCAST_1TO16 1
 527 #define BROADCAST_1TO8  2
 528 #define BROADCAST_1TO4  3
 529 #define BROADCAST_1TO2  4
 530   Broadcast,
 531
 532   /* Static rounding control is supported.  */
 533   StaticRounding,
 534
 535   /* Supress All Exceptions is supported.  */
 536   SAE,
 537
 538   /* Copressed Disp8*N attribute.  */
 539   Disp8MemShift,
 540
 541   /* Default mask isn't allowed.  */
 542   NoDefMask,
 543
 544   /* Compatible with old (<= 2.8.1) versions of gcc  */
 545   OldGcc,
 546   /* AT&T mnemonic.  */
 547   ATTMnemonic,
 548   /* AT&T syntax.  */
 549   ATTSyntax,
 550   /* Intel syntax.  */
 551   IntelSyntax,
 552   /* The last bitfield in i386_opcode_modifier.  */
 553   Opcode_Modifier_Max
 554 };
 555
 556 typedef struct i386_opcode_modifier
 557 {
 558   unsigned int d:1;
 559   unsigned int w:1;
 560   unsigned int s:1;
 561   unsigned int modrm:1;
 562   unsigned int shortform:1;
 563   unsigned int jump:1;
 564   unsigned int jumpdword:1;
 565   unsigned int jumpbyte:1;
 566   unsigned int jumpintersegment:1;
 567   unsigned int floatmf:1;
 568   unsigned int floatr:1;
 569   unsigned int floatd:1;
 570   unsigned int size16:1;
 571   unsigned int size32:1;
 572   unsigned int size64:1;
 573   unsigned int checkregsize:1;
 574   unsigned int ignoresize:1;
 575   unsigned int defaultsize:1;
 576   unsigned int no_bsuf:1;
 577   unsigned int no_wsuf:1;
 578   unsigned int no_lsuf:1;
 579   unsigned int no_ssuf:1;
 580   unsigned int no_qsuf:1;
 581   unsigned int no_ldsuf:1;
 582   unsigned int fwait:1;
 583   unsigned int isstring:1;
 584   unsigned int bndprefixok:1;
 585   unsigned int islockable:1;
 586   unsigned int regkludge:1;
 587   unsigned int firstxmm0:1;
 588   unsigned int implicit1stxmm0:1;
 589   unsigned int hleprefixok:2;
 590   unsigned int repprefixok:1;
 591   unsigned int todword:1;
 592   unsigned int toqword:1;
 593   unsigned int addrprefixop0:1;
 594   unsigned int isprefix:1;
 595   unsigned int immext:1;
 596   unsigned int norex64:1;
 597   unsigned int rex64:1;
 598   unsigned int ugh:1;
 599   unsigned int vex:2;
 600   unsigned int vexvvvv:2;
 601   unsigned int vexw:2;
 602   unsigned int vexopcode:3;
 603   unsigned int vexsources:2;
 604   unsigned int veximmext:1;
 605   unsigned int vecsib:2;
 606   unsigned int sse2avx:1;
 607   unsigned int noavx:1;
 608   unsigned int evex:3;
 609   unsigned int masking:2;
 610   unsigned int vecesize:1;
 611   unsigned int broadcast:3;
 612   unsigned int staticrounding:1;
 613   unsigned int sae:1;
 614   unsigned int disp8memshift:3;
 615   unsigned int nodefmask:1;
 616   unsigned int oldgcc:1;
 617   unsigned int attmnemonic:1;
 618   unsigned int attsyntax:1;
 619   unsigned int intelsyntax:1;
 620 } i386_opcode_modifier;
 621
 622 /* Position of operand_type bits.  */
 623
 624 enum
 625 {
 626   /* 8bit register */
 627   Reg8 = 0,
 628   /* 16bit register */
 629   Reg16,
 630   /* 32bit register */
 631   Reg32,
 632   /* 64bit register */
 633   Reg64,
 634   /* Floating pointer stack register */
 635   FloatReg,
 636   /* MMX register */
 637   RegMMX,
 638   /* SSE register */
 639   RegXMM,
 640   /* AVX registers */
 641   RegYMM,
 642   /* AVX512 registers */
 643   RegZMM,
 644   /* Vector Mask registers */
 645   RegMask,
 646   /* Control register */
 647   Control,
 648   /* Debug register */
 649   Debug,
 650   /* Test register */
 651   Test,
 652   /* 2 bit segment register */
 653   SReg2,
 654   /* 3 bit segment register */
 655   SReg3,
 656   /* 1 bit immediate */
 657   Imm1,
 658   /* 8 bit immediate */
 659   Imm8,
 660   /* 8 bit immediate sign extended */
 661   Imm8S,
 662   /* 16 bit immediate */
 663   Imm16,
 664   /* 32 bit immediate */
 665   Imm32,
 666   /* 32 bit immediate sign extended */
 667   Imm32S,
 668   /* 64 bit immediate */
 669   Imm64,
 670   /* 8bit/16bit/32bit displacements are used in different ways,
 671      depending on the instruction.  For jumps, they specify the
 672      size of the PC relative displacement, for instructions with
 673      memory operand, they specify the size of the offset relative
 674      to the base register, and for instructions with memory offset
 675      such as `mov 1234,%al' they specify the size of the offset
 676      relative to the segment base.  */
 677   /* 8 bit displacement */
 678   Disp8,
 679   /* 16 bit displacement */
 680   Disp16,
 681   /* 32 bit displacement */
 682   Disp32,
 683   /* 32 bit signed displacement */
 684   Disp32S,
 685   /* 64 bit displacement */
 686   Disp64,
 687   /* Accumulator %al/%ax/%eax/%rax */
 688   Acc,
 689   /* Floating pointer top stack register %st(0) */
 690   FloatAcc,
 691   /* Register which can be used for base or index in memory operand.  */
 692   BaseIndex,
 693   /* Register to hold in/out port addr = dx */
 694   InOutPortReg,
 695   /* Register to hold shift count = cl */
 696   ShiftCount,
 697   /* Absolute address for jump.  */
 698   JumpAbsolute,
 699   /* String insn operand with fixed es segment */
 700   EsSeg,
 701   /* RegMem is for instructions with a modrm byte where the register
 702      destination operand should be encoded in the mod and regmem fields.
 703      Normally, it will be encoded in the reg field. We add a RegMem
 704      flag to the destination register operand to indicate that it should
 705      be encoded in the regmem field.  */
 706   RegMem,
 707   /* Memory.  */
 708   Mem,
 709   /* BYTE memory. */
 710   Byte,
 711   /* WORD memory. 2 byte */
 712   Word,
 713   /* DWORD memory. 4 byte */
 714   Dword,
 715   /* FWORD memory. 6 byte */
 716   Fword,
 717   /* QWORD memory. 8 byte */
 718   Qword,
 719   /* TBYTE memory. 10 byte */
 720   Tbyte,
 721   /* XMMWORD memory. */
 722   Xmmword,
 723   /* YMMWORD memory. */
 724   Ymmword,
 725   /* ZMMWORD memory.  */
 726   Zmmword,
 727   /* Unspecified memory size.  */
 728   Unspecified,
 729   /* Any memory size.  */
 730   Anysize,
 731
 732   /* Vector 4 bit immediate.  */
 733   Vec_Imm4,
 734
 735   /* Bound register.  */
 736   RegBND,
 737
 738   /* Vector 8bit displacement */
 739   Vec_Disp8,
 740
 741   /* The last bitfield in i386_operand_type.  */
 742   OTMax
 743 };
 744
 745 #define OTNumOfUints \
 746   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 747 #define OTNumOfBits \
 748   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 749
 750 /* If you get a compiler error for zero width of the unused field,
 751    comment it out.  */
 752 #define OTUnused                (OTMax + 1)
 753
 754 typedef union i386_operand_type
 755 {
 756   struct
 757     {
 758       unsigned int reg8:1;
 759       unsigned int reg16:1;
 760       unsigned int reg32:1;
 761       unsigned int reg64:1;
 762       unsigned int floatreg:1;
 763       unsigned int regmmx:1;
 764       unsigned int regxmm:1;
 765       unsigned int regymm:1;
 766       unsigned int regzmm:1;
 767       unsigned int regmask:1;
 768       unsigned int control:1;
 769       unsigned int debug:1;
 770       unsigned int test:1;
 771       unsigned int sreg2:1;
 772       unsigned int sreg3:1;
 773       unsigned int imm1:1;
 774       unsigned int imm8:1;
 775       unsigned int imm8s:1;
 776       unsigned int imm16:1;
 777       unsigned int imm32:1;
 778       unsigned int imm32s:1;
 779       unsigned int imm64:1;
 780       unsigned int disp8:1;
 781       unsigned int disp16:1;
 782       unsigned int disp32:1;
 783       unsigned int disp32s:1;
 784       unsigned int disp64:1;
 785       unsigned int acc:1;
 786       unsigned int floatacc:1;
 787       unsigned int baseindex:1;
 788       unsigned int inoutportreg:1;
 789       unsigned int shiftcount:1;
 790       unsigned int jumpabsolute:1;
 791       unsigned int esseg:1;
 792       unsigned int regmem:1;
 793       unsigned int mem:1;
 794       unsigned int byte:1;
 795       unsigned int word:1;
 796       unsigned int dword:1;
 797       unsigned int fword:1;
 798       unsigned int qword:1;
 799       unsigned int tbyte:1;
 800       unsigned int xmmword:1;
 801       unsigned int ymmword:1;
 802       unsigned int zmmword:1;
 803       unsigned int unspecified:1;
 804       unsigned int anysize:1;
 805       unsigned int vec_imm4:1;
 806       unsigned int regbnd:1;
 807       unsigned int vec_disp8:1;
 808 #ifdef OTUnused
 809       unsigned int unused:(OTNumOfBits - OTUnused);
 810 #endif
 811     } bitfield;
 812   unsigned int array[OTNumOfUints];
 813 } i386_operand_type;
 814
 815 typedef struct insn_template
 816 {
 817   /* instruction name sans width suffix ("mov" for movl insns) */
 818   char *name;
 819
 820   /* how many operands */
 821   unsigned int operands;
 822
 823   /* base_opcode is the fundamental opcode byte without optional
 824      prefix(es).  */
 825   unsigned int base_opcode;
 826 #define Opcode_D        0x2 /* Direction bit:
 827                                set if Reg --> Regmem;
 828                                unset if Regmem --> Reg. */
 829 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 830 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 831
 832   /* extension_opcode is the 3 bit extension for group <n> insns.
 833      This field is also used to store the 8-bit opcode suffix for the
 834      AMD 3DNow! instructions.
 835      If this template has no extension opcode (the usual case) use None
 836      Instructions */
 837   unsigned int extension_opcode;
 838 #define None 0xffff             /* If no extension_opcode is possible.  */
 839
 840   /* Opcode length.  */
 841   unsigned char opcode_length;
 842
 843   /* cpu feature flags */
 844   i386_cpu_flags cpu_flags;
 845
 846   /* the bits in opcode_modifier are used to generate the final opcode from
 847      the base_opcode.  These bits also are used to detect alternate forms of
 848      the same instruction */
 849   i386_opcode_modifier opcode_modifier;
 850
 851   /* operand_types[i] describes the type of operand i.  This is made
 852      by OR'ing together all of the possible type masks.  (e.g.
 853      'operand_types[i] = Reg|Imm' specifies that operand i can be
 854      either a register or an immediate operand.  */
 855   i386_operand_type operand_types[MAX_OPERANDS];
 856 }
 857 insn_template;
 858
 859 extern const insn_template i386_optab[];
 860
 861 /* these are for register name --> number & type hash lookup */
 862 typedef struct
 863 {
 864   char *reg_name;
 865   i386_operand_type reg_type;
 866   unsigned char reg_flags;
 867 #define RegRex      0x1  /* Extended register.  */
 868 #define RegRex64    0x2  /* Extended 8 bit register.  */
 869 #define RegVRex     0x4  /* Extended vector register.  */
 870   unsigned char reg_num;
 871 #define RegRip  ((unsigned char ) ~0)
 872 #define RegEip  (RegRip - 1)
 873 /* EIZ and RIZ are fake index registers.  */
 874 #define RegEiz  (RegEip - 1)
 875 #define RegRiz  (RegEiz - 1)
 876 /* FLAT is a fake segment register (Intel mode).  */
 877 #define RegFlat     ((unsigned char) ~0)
 878   signed char dw2_regnum[2];
 879 #define Dw2Inval (-1)
 880 }
 881 reg_entry;
 882
 883 /* Entries in i386_regtab.  */
 884 #define REGNAM_AL 1
 885 #define REGNAM_AX 25
 886 #define REGNAM_EAX 41
 887
 888 extern const reg_entry i386_regtab[];
 889 extern const unsigned int i386_regtab_size;
 890
 891 typedef struct
 892 {
 893   char *seg_name;
 894   unsigned int seg_prefix;
 895 }
 896 seg_entry;
 897
 898 extern const seg_entry cs;
 899 extern const seg_entry ds;
 900 extern const seg_entry ss;
 901 extern const seg_entry es;
 902 extern const seg_entry fs;
 903 extern const seg_entry gs;