opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SMX Instructions required */
  72 #define CpuSMX          (CpuVMX + 1)
  73 /* SSSE3 support required */
  74 #define CpuSSSE3        (CpuSMX + 1)
  75 /* SSE4a support required */
  76 #define CpuSSE4a        (CpuSSSE3 + 1)
  77 /* ABM New Instructions required */
  78 #define CpuABM          (CpuSSE4a + 1)
  79 /* SSE4.1 support required */
  80 #define CpuSSE4_1       (CpuABM + 1)
  81 /* SSE4.2 support required */
  82 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  83 /* SSE5 support required */
  84 #define CpuSSE5         (CpuSSE4_2 + 1)
  85 /* SSE4.1 or SSE5 support required */
  86 #define CpuSSE4_1_Or_5  (CpuSSE5 + 1)
  87 /* SSE4.2 or ABM support required */
  88 #define CpuSSE4_2_Or_ABM (CpuSSE4_1_Or_5 + 1)
  89 /* 64bit support available, used by -march= in assembler.  */
  90 #define CpuLM           (CpuSSE4_2_Or_ABM + 1)
  91 /* 64bit support required  */
  92 #define Cpu64           (CpuLM + 1)
  93 /* Not supported in the 64bit mode  */
  94 #define CpuNo64         (Cpu64 + 1)
  95 /* The last bitfield in i386_cpu_flags.  */
  96 #define CpuMax          CpuNo64
  97
  98 #define CpuNumOfUints \
  99   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 100 #define CpuNumOfBits \
 101   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 102
 103 /* If you get a compiler error for zero width of the unused field,
 104    comment it out.  */
 105 #define CpuUnused       (CpuMax + 1)
 106
 107 /* We can check if an instruction is available with array instead
 108    of bitfield. */
 109 typedef union i386_cpu_flags
 110 {
 111   struct
 112     {
 113       unsigned int cpui186:1;
 114       unsigned int cpui286:1;
 115       unsigned int cpui386:1;
 116       unsigned int cpui486:1;
 117       unsigned int cpui586:1;
 118       unsigned int cpui686:1;
 119       unsigned int cpup4:1;
 120       unsigned int cpuk6:1;
 121       unsigned int cpuk8:1;
 122       unsigned int cpummx:1;
 123       unsigned int cpummx2:1;
 124       unsigned int cpusse:1;
 125       unsigned int cpusse2:1;
 126       unsigned int cpua3dnow:1;
 127       unsigned int cpua3dnowa:1;
 128       unsigned int cpusse3:1;
 129       unsigned int cpupadlock:1;
 130       unsigned int cpusvme:1;
 131       unsigned int cpuvmx:1;
 132       unsigned int cpusmx:1;
 133       unsigned int cpussse3:1;
 134       unsigned int cpusse4a:1;
 135       unsigned int cpuabm:1;
 136       unsigned int cpusse4_1:1;
 137       unsigned int cpusse4_2:1;
 138       unsigned int cpusse5:1;
 139       unsigned int cpusse4_1_or_5:1;
 140       unsigned int cpusse4_2_or_abm:1;
 141       unsigned int cpulm:1;
 142       unsigned int cpu64:1;
 143       unsigned int cpuno64:1;
 144 #ifdef CpuUnused
 145       unsigned int unused:(CpuNumOfBits - CpuUnused);
 146 #endif
 147     } bitfield;
 148   unsigned int array[CpuNumOfUints];
 149 } i386_cpu_flags;
 150
 151 /* Position of opcode_modifier bits.  */
 152
 153 /* has direction bit. */
 154 #define D                       0
 155 /* set if operands can be words or dwords encoded the canonical way */
 156 #define W                       (D + 1)
 157 /* insn has a modrm byte. */
 158 #define Modrm                   (W + 1)
 159 /* register is in low 3 bits of opcode */
 160 #define ShortForm               (Modrm + 1)
 161 /* special case for jump insns.  */
 162 #define Jump                    (ShortForm + 1)
 163 /* call and jump */
 164 #define JumpDword               (Jump + 1)
 165 /* loop and jecxz */
 166 #define JumpByte                (JumpDword + 1)
 167 /* special case for intersegment leaps/calls */
 168 #define JumpInterSegment        (JumpByte + 1)
 169 /* FP insn memory format bit, sized by 0x4 */
 170 #define FloatMF                 (JumpInterSegment + 1)
 171 /* src/dest swap for floats. */
 172 #define FloatR                  (FloatMF + 1)
 173 /* has float insn direction bit. */
 174 #define FloatD                  (FloatR + 1)
 175 /* needs size prefix if in 32-bit mode */
 176 #define Size16                  (FloatD + 1)
 177 /* needs size prefix if in 16-bit mode */
 178 #define Size32                  (Size16 + 1)
 179 /* needs size prefix if in 64-bit mode */
 180 #define Size64                  (Size32 + 1)
 181 /* instruction ignores operand size prefix and in Intel mode ignores
 182    mnemonic size suffix check.  */
 183 #define IgnoreSize              (Size64 + 1)
 184 /* default insn size depends on mode */
 185 #define DefaultSize             (IgnoreSize + 1)
 186 /* b suffix on instruction illegal */
 187 #define No_bSuf                 (DefaultSize + 1)
 188 /* w suffix on instruction illegal */
 189 #define No_wSuf                 (No_bSuf + 1)
 190 /* l suffix on instruction illegal */
 191 #define No_lSuf                 (No_wSuf + 1)
 192 /* s suffix on instruction illegal */
 193 #define No_sSuf                 (No_lSuf + 1)
 194 /* q suffix on instruction illegal */
 195 #define No_qSuf                 (No_sSuf + 1)
 196 /* long double suffix on instruction illegal */
 197 #define No_ldSuf                (No_qSuf + 1)
 198 /* x suffix on instruction illegal */
 199 #define No_xSuf                 (No_ldSuf + 1)
 200 /* check memory size on instruction in Intel mode if it is specified.  */
 201 #define CheckSize               (No_xSuf + 1)
 202 /* BYTE memory on instruction */
 203 #define Byte                    (CheckSize + 1)
 204 /* WORD memory on instruction */
 205 #define Word                    (Byte + 1)
 206 /* DWORD memory on instruction */
 207 #define Dword                   (Word + 1)
 208 /* QWORD memory on instruction */
 209 #define Qword                   (Dword + 1)
 210 /* XMMWORD memory on instruction */
 211 #define Xmmword                 (Qword + 1)
 212 /* instruction needs FWAIT */
 213 #define FWait                   (Xmmword + 1)
 214 /* quick test for string instructions */
 215 #define IsString                (FWait + 1)
 216 /* fake an extra reg operand for clr, imul and special register
 217    processing for some instructions.  */
 218 #define RegKludge               (IsString + 1)
 219 /* The first operand must be xmm0 */
 220 #define FirstXmm0               (RegKludge + 1)
 221 /* BYTE is OK in Intel syntax. */
 222 #define ByteOkIntel             (FirstXmm0 + 1)
 223 /* Convert to DWORD */
 224 #define ToDword                 (ByteOkIntel + 1)
 225 /* Convert to QWORD */
 226 #define ToQword                 (ToDword + 1)
 227 /* Address prefix changes operand 0 */
 228 #define AddrPrefixOp0           (ToQword + 1)
 229 /* opcode is a prefix */
 230 #define IsPrefix                (AddrPrefixOp0 + 1)
 231 /* instruction has extension in 8 bit imm */
 232 #define ImmExt                  (IsPrefix + 1)
 233 /* instruction don't need Rex64 prefix.  */
 234 #define NoRex64                 (ImmExt + 1)
 235 /* instruction require Rex64 prefix.  */
 236 #define Rex64                   (NoRex64 + 1)
 237 /* deprecated fp insn, gets a warning */
 238 #define Ugh                     (Rex64 + 1)
 239 #define Drex                    (Ugh + 1)
 240 /* instruction needs DREX with multiple encodings for memory ops */
 241 #define Drexv                   (Drex + 1)
 242 /* special DREX for comparisons */
 243 #define Drexc                   (Drexv + 1)
 244 /* Compatible with old (<= 2.8.1) versions of gcc  */
 245 #define OldGcc                  (Drexc + 1)
 246 /* AT&T mnemonic.  */
 247 #define ATTMnemonic             (OldGcc + 1)
 248 /* Intel mnemonic.  */
 249 #define IntelMnemonic           (ATTMnemonic + 1)
 250 /* The last bitfield in i386_opcode_modifier.  */
 251 #define Opcode_Modifier_Max     IntelMnemonic
 252
 253 typedef struct i386_opcode_modifier
 254 {
 255   unsigned int d:1;
 256   unsigned int w:1;
 257   unsigned int modrm:1;
 258   unsigned int shortform:1;
 259   unsigned int jump:1;
 260   unsigned int jumpdword:1;
 261   unsigned int jumpbyte:1;
 262   unsigned int jumpintersegment:1;
 263   unsigned int floatmf:1;
 264   unsigned int floatr:1;
 265   unsigned int floatd:1;
 266   unsigned int size16:1;
 267   unsigned int size32:1;
 268   unsigned int size64:1;
 269   unsigned int ignoresize:1;
 270   unsigned int defaultsize:1;
 271   unsigned int no_bsuf:1;
 272   unsigned int no_wsuf:1;
 273   unsigned int no_lsuf:1;
 274   unsigned int no_ssuf:1;
 275   unsigned int no_qsuf:1;
 276   unsigned int no_ldsuf:1;
 277   unsigned int no_xsuf:1;
 278   unsigned int checksize:1;
 279   unsigned int byte:1;
 280   unsigned int word:1;
 281   unsigned int dword:1;
 282   unsigned int qword:1;
 283   unsigned int xmmword:1;
 284   unsigned int fwait:1;
 285   unsigned int isstring:1;
 286   unsigned int regkludge:1;
 287   unsigned int firstxmm0:1;
 288   unsigned int byteokintel:1;
 289   unsigned int todword:1;
 290   unsigned int toqword:1;
 291   unsigned int addrprefixop0:1;
 292   unsigned int isprefix:1;
 293   unsigned int immext:1;
 294   unsigned int norex64:1;
 295   unsigned int rex64:1;
 296   unsigned int ugh:1;
 297   unsigned int drex:1;
 298   unsigned int drexv:1;
 299   unsigned int drexc:1;
 300   unsigned int oldgcc:1;
 301   unsigned int attmnemonic:1;
 302   unsigned int intelmnemonic:1;
 303 } i386_opcode_modifier;
 304
 305 /* Position of operand_type bits.  */
 306
 307 /* Registers  */
 308
 309 /* 8 bit reg */
 310 #define Reg8                    0
 311 /* 16 bit reg */
 312 #define Reg16                   (Reg8 + 1)
 313 /* 32 bit reg */
 314 #define Reg32                   (Reg16 + 1)
 315 /* 64 bit reg */
 316 #define Reg64                   (Reg32 + 1)
 317
 318 /* immediate */
 319
 320 /* 8 bit immediate */
 321 #define Imm8                    (Reg64 + 1)
 322 /* 8 bit immediate sign extended */
 323 #define Imm8S                   (Imm8 + 1)
 324 /* 16 bit immediate */
 325 #define Imm16                   (Imm8S + 1)
 326 /* 32 bit immediate */
 327 #define Imm32                   (Imm16 + 1)
 328 /* 32 bit immediate sign extended */
 329 #define Imm32S                  (Imm32 + 1)
 330 /* 64 bit immediate */
 331 #define Imm64                   (Imm32S + 1)
 332 /* 1 bit immediate */
 333 #define Imm1                    (Imm64 + 1)
 334
 335 /* memory */
 336
 337 #define BaseIndex               (Imm1 + 1)
 338 /* Disp8,16,32 are used in different ways, depending on the
 339    instruction.  For jumps, they specify the size of the PC relative
 340    displacement, for baseindex type instructions, they specify the
 341    size of the offset relative to the base register, and for memory
 342    offset instructions such as `mov 1234,%al' they specify the size of
 343    the offset relative to the segment base.  */
 344 /* 8 bit displacement */
 345 #define Disp8                   (BaseIndex + 1)
 346 /* 16 bit displacement */
 347 #define Disp16                  (Disp8 + 1)
 348 /* 32 bit displacement */
 349 #define Disp32                  (Disp16 + 1)
 350 /* 32 bit signed displacement */
 351 #define Disp32S                 (Disp32 + 1)
 352 /* 64 bit displacement */
 353 #define Disp64                  (Disp32S + 1)
 354
 355 /* specials */
 356
 357 /* register to hold in/out port addr = dx */
 358 #define InOutPortReg            (Disp64 + 1)
 359 /* register to hold shift count = cl */
 360 #define ShiftCount              (InOutPortReg + 1)
 361 /* Control register */
 362 #define Control                 (ShiftCount + 1)
 363 /* Debug register */
 364 #define Debug                   (Control + 1)
 365 /* Test register */
 366 #define Test                    (Debug + 1)
 367 /* Float register */
 368 #define FloatReg                (Test + 1)
 369 /* Float stack top %st(0) */
 370 #define FloatAcc                (FloatReg + 1)
 371 /* 2 bit segment register */
 372 #define SReg2                   (FloatAcc + 1)
 373 /* 3 bit segment register */
 374 #define SReg3                   (SReg2 + 1)
 375 /* Accumulator %al or %ax or %eax */
 376 #define Acc                     (SReg3 + 1)
 377 #define JumpAbsolute            (Acc + 1)
 378 /* MMX register */
 379 #define RegMMX                  (JumpAbsolute + 1)
 380 /* XMM registers in PIII */
 381 #define RegXMM                  (RegMMX + 1)
 382 /* String insn operand with fixed es segment */
 383 #define EsSeg                   (RegXMM + 1)
 384
 385 /* RegMem is for instructions with a modrm byte where the register
 386    destination operand should be encoded in the mod and regmem fields.
 387    Normally, it will be encoded in the reg field. We add a RegMem
 388    flag to the destination register operand to indicate that it should
 389    be encoded in the regmem field.  */
 390 #define RegMem                  (EsSeg + 1)
 391
 392 /* The last bitfield in i386_operand_type.  */
 393 #define OTMax                   RegMem
 394
 395 #define OTNumOfUints \
 396   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 397 #define OTNumOfBits \
 398   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 399
 400 /* If you get a compiler error for zero width of the unused field,
 401    comment it out.  */
 402 #if 0
 403 #define OTUnused                (OTMax + 1)
 404 #endif
 405
 406 typedef union i386_operand_type
 407 {
 408   struct
 409     {
 410       unsigned int reg8:1;
 411       unsigned int reg16:1;
 412       unsigned int reg32:1;
 413       unsigned int reg64:1;
 414       unsigned int imm8:1;
 415       unsigned int imm8s:1;
 416       unsigned int imm16:1;
 417       unsigned int imm32:1;
 418       unsigned int imm32s:1;
 419       unsigned int imm64:1;
 420       unsigned int imm1:1;
 421       unsigned int baseindex:1;
 422       unsigned int disp8:1;
 423       unsigned int disp16:1;
 424       unsigned int disp32:1;
 425       unsigned int disp32s:1;
 426       unsigned int disp64:1;
 427       unsigned int inoutportreg:1;
 428       unsigned int shiftcount:1;
 429       unsigned int control:1;
 430       unsigned int debug:1;
 431       unsigned int test:1;
 432       unsigned int floatreg:1;
 433       unsigned int floatacc:1;
 434       unsigned int sreg2:1;
 435       unsigned int sreg3:1;
 436       unsigned int acc:1;
 437       unsigned int jumpabsolute:1;
 438       unsigned int regmmx:1;
 439       unsigned int regxmm:1;
 440       unsigned int esseg:1;
 441       unsigned int regmem:1;
 442 #ifdef OTUnused
 443       unsigned int unused:(OTNumOfBits - OTUnused);
 444 #endif
 445     } bitfield;
 446   unsigned int array[OTNumOfUints];
 447 } i386_operand_type;
 448
 449 typedef struct template
 450 {
 451   /* instruction name sans width suffix ("mov" for movl insns) */
 452   char *name;
 453
 454   /* how many operands */
 455   unsigned int operands;
 456
 457   /* base_opcode is the fundamental opcode byte without optional
 458      prefix(es).  */
 459   unsigned int base_opcode;
 460 #define Opcode_D        0x2 /* Direction bit:
 461                                set if Reg --> Regmem;
 462                                unset if Regmem --> Reg. */
 463 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 464 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 465
 466   /* extension_opcode is the 3 bit extension for group <n> insns.
 467      This field is also used to store the 8-bit opcode suffix for the
 468      AMD 3DNow! instructions.
 469      If this template has no extension opcode (the usual case) use None
 470      Instructions with Drex use this to specify 2 bits for OC */
 471   unsigned int extension_opcode;
 472 #define None 0xffff             /* If no extension_opcode is possible.  */
 473
 474   /* Opcode length.  */
 475   unsigned char opcode_length;
 476
 477   /* cpu feature flags */
 478   i386_cpu_flags cpu_flags;
 479
 480   /* the bits in opcode_modifier are used to generate the final opcode from
 481      the base_opcode.  These bits also are used to detect alternate forms of
 482      the same instruction */
 483   i386_opcode_modifier opcode_modifier;
 484
 485   /* operand_types[i] describes the type of operand i.  This is made
 486      by OR'ing together all of the possible type masks.  (e.g.
 487      'operand_types[i] = Reg|Imm' specifies that operand i can be
 488      either a register or an immediate operand.  */
 489   i386_operand_type operand_types[MAX_OPERANDS];
 490 }
 491 template;
 492
 493 extern const template i386_optab[];
 494
 495 /* these are for register name --> number & type hash lookup */
 496 typedef struct
 497 {
 498   char *reg_name;
 499   i386_operand_type reg_type;
 500   unsigned int reg_flags;
 501 #define RegRex      0x1  /* Extended register.  */
 502 #define RegRex64    0x2  /* Extended 8 bit register.  */
 503   unsigned int reg_num;
 504 #define RegRip  ((unsigned int ) ~0)
 505 #define RegEip  (RegRip - 1)
 506 /* EIZ and RIZ are fake index registers.  */
 507 #define RegEiz  (RegEip - 1)
 508 #define RegRiz  (RegEiz - 1)
 509 }
 510 reg_entry;
 511
 512 /* Entries in i386_regtab.  */
 513 #define REGNAM_AL 1
 514 #define REGNAM_AX 25
 515 #define REGNAM_EAX 41
 516
 517 extern const reg_entry i386_regtab[];
 518 extern const unsigned int i386_regtab_size;
 519
 520 typedef struct
 521 {
 522   char *seg_name;
 523   unsigned int seg_prefix;
 524 }
 525 seg_entry;
 526
 527 extern const seg_entry cs;
 528 extern const seg_entry ds;
 529 extern const seg_entry ss;
 530 extern const seg_entry es;
 531 extern const seg_entry fs;
 532 extern const seg_entry gs;