1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* Intel AVX-512 4VNNIW Instructions support required. */
199 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
201 /* Intel AVX-512 VBMI2 Instructions support required. */
203 /* Intel AVX-512 VNNI Instructions support required. */
205 /* Intel AVX-512 BITALG Instructions support required. */
207 /* mwaitx instruction required */
209 /* Clzero instruction required */
211 /* OSPKE instruction required */
213 /* RDPID instruction required */
215 /* PTWRITE instruction required */
217 /* CET instruction support required */
219 /* GFNI instructions required */
221 /* VAES instructions required */
223 /* VPCLMULQDQ instructions required */
225 /* MMX register support required */
227 /* XMM register support required */
229 /* YMM register support required */
231 /* ZMM register support required */
233 /* Mask register support required */
235 /* 64bit support required */
237 /* Not supported in the 64bit mode */
239 /* The last bitfield in i386_cpu_flags. */
243 #define CpuNumOfUints \
244 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
245 #define CpuNumOfBits \
246 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
248 /* If you get a compiler error for zero width of the unused field,
250 #define CpuUnused (CpuMax + 1)
252 /* We can check if an instruction is available with array instead
254 typedef union i386_cpu_flags
258 unsigned int cpui186
:1;
259 unsigned int cpui286
:1;
260 unsigned int cpui386
:1;
261 unsigned int cpui486
:1;
262 unsigned int cpui586
:1;
263 unsigned int cpui686
:1;
264 unsigned int cpuclflush
:1;
265 unsigned int cpunop
:1;
266 unsigned int cpusyscall
:1;
267 unsigned int cpu8087
:1;
268 unsigned int cpu287
:1;
269 unsigned int cpu387
:1;
270 unsigned int cpu687
:1;
271 unsigned int cpufisttp
:1;
272 unsigned int cpummx
:1;
273 unsigned int cpusse
:1;
274 unsigned int cpusse2
:1;
275 unsigned int cpua3dnow
:1;
276 unsigned int cpua3dnowa
:1;
277 unsigned int cpusse3
:1;
278 unsigned int cpupadlock
:1;
279 unsigned int cpusvme
:1;
280 unsigned int cpuvmx
:1;
281 unsigned int cpusmx
:1;
282 unsigned int cpussse3
:1;
283 unsigned int cpusse4a
:1;
284 unsigned int cpuabm
:1;
285 unsigned int cpusse4_1
:1;
286 unsigned int cpusse4_2
:1;
287 unsigned int cpuavx
:1;
288 unsigned int cpuavx2
:1;
289 unsigned int cpuavx512f
:1;
290 unsigned int cpuavx512cd
:1;
291 unsigned int cpuavx512er
:1;
292 unsigned int cpuavx512pf
:1;
293 unsigned int cpuavx512vl
:1;
294 unsigned int cpuavx512dq
:1;
295 unsigned int cpuavx512bw
:1;
296 unsigned int cpul1om
:1;
297 unsigned int cpuk1om
:1;
298 unsigned int cpuiamcu
:1;
299 unsigned int cpuxsave
:1;
300 unsigned int cpuxsaveopt
:1;
301 unsigned int cpuaes
:1;
302 unsigned int cpupclmul
:1;
303 unsigned int cpufma
:1;
304 unsigned int cpufma4
:1;
305 unsigned int cpuxop
:1;
306 unsigned int cpulwp
:1;
307 unsigned int cpubmi
:1;
308 unsigned int cputbm
:1;
309 unsigned int cpumovbe
:1;
310 unsigned int cpucx16
:1;
311 unsigned int cpuept
:1;
312 unsigned int cpurdtscp
:1;
313 unsigned int cpufsgsbase
:1;
314 unsigned int cpurdrnd
:1;
315 unsigned int cpuf16c
:1;
316 unsigned int cpubmi2
:1;
317 unsigned int cpulzcnt
:1;
318 unsigned int cpuhle
:1;
319 unsigned int cpurtm
:1;
320 unsigned int cpuinvpcid
:1;
321 unsigned int cpuvmfunc
:1;
322 unsigned int cpumpx
:1;
323 unsigned int cpulm
:1;
324 unsigned int cpurdseed
:1;
325 unsigned int cpuadx
:1;
326 unsigned int cpuprfchw
:1;
327 unsigned int cpusmap
:1;
328 unsigned int cpusha
:1;
329 unsigned int cpuvrex
:1;
330 unsigned int cpuclflushopt
:1;
331 unsigned int cpuxsaves
:1;
332 unsigned int cpuxsavec
:1;
333 unsigned int cpuprefetchwt1
:1;
334 unsigned int cpuse1
:1;
335 unsigned int cpuclwb
:1;
336 unsigned int cpuavx512ifma
:1;
337 unsigned int cpuavx512vbmi
:1;
338 unsigned int cpuavx512_4fmaps
:1;
339 unsigned int cpuavx512_4vnniw
:1;
340 unsigned int cpuavx512_vpopcntdq
:1;
341 unsigned int cpuavx512_vbmi2
:1;
342 unsigned int cpuavx512_vnni
:1;
343 unsigned int cpuavx512_bitalg
:1;
344 unsigned int cpumwaitx
:1;
345 unsigned int cpuclzero
:1;
346 unsigned int cpuospke
:1;
347 unsigned int cpurdpid
:1;
348 unsigned int cpuptwrite
:1;
349 unsigned int cpucet
:1;
350 unsigned int cpugfni
:1;
351 unsigned int cpuvaes
:1;
352 unsigned int cpuvpclmulqdq
:1;
353 unsigned int cpuregmmx
:1;
354 unsigned int cpuregxmm
:1;
355 unsigned int cpuregymm
:1;
356 unsigned int cpuregzmm
:1;
357 unsigned int cpuregmask
:1;
358 unsigned int cpu64
:1;
359 unsigned int cpuno64
:1;
361 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
364 unsigned int array
[CpuNumOfUints
];
367 /* Position of opcode_modifier bits. */
371 /* has direction bit. */
373 /* set if operands can be words or dwords encoded the canonical way */
375 /* load form instruction. Must be placed before store form. */
377 /* insn has a modrm byte. */
379 /* register is in low 3 bits of opcode */
381 /* special case for jump insns. */
387 /* special case for intersegment leaps/calls */
389 /* FP insn memory format bit, sized by 0x4 */
391 /* src/dest swap for floats. */
393 /* has float insn direction bit. */
395 /* needs size prefix if in 32-bit mode */
397 /* needs size prefix if in 16-bit mode */
399 /* needs size prefix if in 64-bit mode */
401 /* check register size. */
403 /* instruction ignores operand size prefix and in Intel mode ignores
404 mnemonic size suffix check. */
406 /* default insn size depends on mode */
408 /* b suffix on instruction illegal */
410 /* w suffix on instruction illegal */
412 /* l suffix on instruction illegal */
414 /* s suffix on instruction illegal */
416 /* q suffix on instruction illegal */
418 /* long double suffix on instruction illegal */
420 /* instruction needs FWAIT */
422 /* quick test for string instructions */
424 /* quick test if branch instruction is MPX supported */
426 /* quick test if NOTRACK prefix is supported */
428 /* quick test for lockable instructions */
430 /* fake an extra reg operand for clr, imul and special register
431 processing for some instructions. */
433 /* An implicit xmm0 as the first operand */
435 /* The HLE prefix is OK:
436 1. With a LOCK prefix.
437 2. With or without a LOCK prefix.
438 3. With a RELEASE (0xf3) prefix.
440 #define HLEPrefixNone 0
441 #define HLEPrefixLock 1
442 #define HLEPrefixAny 2
443 #define HLEPrefixRelease 3
445 /* An instruction on which a "rep" prefix is acceptable. */
447 /* Convert to DWORD */
449 /* Convert to QWORD */
451 /* Address prefix changes operand 0 */
453 /* opcode is a prefix */
455 /* instruction has extension in 8 bit imm */
457 /* instruction don't need Rex64 prefix. */
459 /* instruction require Rex64 prefix. */
461 /* deprecated fp insn, gets a warning */
463 /* insn has VEX prefix:
464 1: 128bit VEX prefix (or operand dependent).
465 2: 256bit VEX prefix.
466 3: Scalar VEX prefix.
472 /* How to encode VEX.vvvv:
473 0: VEX.vvvv must be 1111b.
474 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
475 the content of source registers will be preserved.
476 VEX.DDS. The second register operand is encoded in VEX.vvvv
477 where the content of first source register will be overwritten
479 VEX.NDD2. The second destination register operand is encoded in
480 VEX.vvvv for instructions with 2 destination register operands.
481 For assembler, there are no difference between VEX.NDS, VEX.DDS
483 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
484 instructions with 1 destination register operand.
485 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
486 of the operands can access a memory location.
492 /* How the VEX.W bit is used:
493 0: Set by the REX.W bit.
494 1: VEX.W0. Should always be 0.
495 2: VEX.W1. Should always be 1.
500 /* VEX opcode prefix:
501 0: VEX 0x0F opcode prefix.
502 1: VEX 0x0F38 opcode prefix.
503 2: VEX 0x0F3A opcode prefix
504 3: XOP 0x08 opcode prefix.
505 4: XOP 0x09 opcode prefix
506 5: XOP 0x0A opcode prefix.
515 /* number of VEX source operands:
516 0: <= 2 source operands.
517 1: 2 XOP source operands.
518 2: 3 source operands.
520 #define XOP2SOURCES 1
521 #define VEX3SOURCES 2
523 /* instruction has VEX 8 bit imm */
525 /* Instruction with vector SIB byte:
526 1: 128bit vector register.
527 2: 256bit vector register.
528 3: 512bit vector register.
534 /* SSE to AVX support required */
536 /* No AVX equivalent */
539 /* insn has EVEX prefix:
540 1: 512bit EVEX prefix.
541 2: 128bit EVEX prefix.
542 3: 256bit EVEX prefix.
543 4: Length-ignored (LIG) EVEX prefix.
551 /* AVX512 masking support:
554 3: Both zeroing and merging masking.
556 #define ZEROING_MASKING 1
557 #define MERGING_MASKING 2
558 #define BOTH_MASKING 3
561 /* Input element size of vector insn:
572 #define NO_BROADCAST 0
573 #define BROADCAST_1TO16 1
574 #define BROADCAST_1TO8 2
575 #define BROADCAST_1TO4 3
576 #define BROADCAST_1TO2 4
579 /* Static rounding control is supported. */
582 /* Supress All Exceptions is supported. */
585 /* Copressed Disp8*N attribute. */
588 /* Default mask isn't allowed. */
591 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
592 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
596 /* Compatible with old (<= 2.8.1) versions of gcc */
608 /* The last bitfield in i386_opcode_modifier. */
612 typedef struct i386_opcode_modifier
617 unsigned int modrm
:1;
618 unsigned int shortform
:1;
620 unsigned int jumpdword
:1;
621 unsigned int jumpbyte
:1;
622 unsigned int jumpintersegment
:1;
623 unsigned int floatmf
:1;
624 unsigned int floatr
:1;
625 unsigned int floatd
:1;
626 unsigned int size16
:1;
627 unsigned int size32
:1;
628 unsigned int size64
:1;
629 unsigned int checkregsize
:1;
630 unsigned int ignoresize
:1;
631 unsigned int defaultsize
:1;
632 unsigned int no_bsuf
:1;
633 unsigned int no_wsuf
:1;
634 unsigned int no_lsuf
:1;
635 unsigned int no_ssuf
:1;
636 unsigned int no_qsuf
:1;
637 unsigned int no_ldsuf
:1;
638 unsigned int fwait
:1;
639 unsigned int isstring
:1;
640 unsigned int bndprefixok
:1;
641 unsigned int notrackprefixok
:1;
642 unsigned int islockable
:1;
643 unsigned int regkludge
:1;
644 unsigned int implicit1stxmm0
:1;
645 unsigned int hleprefixok
:2;
646 unsigned int repprefixok
:1;
647 unsigned int todword
:1;
648 unsigned int toqword
:1;
649 unsigned int addrprefixop0
:1;
650 unsigned int isprefix
:1;
651 unsigned int immext
:1;
652 unsigned int norex64
:1;
653 unsigned int rex64
:1;
656 unsigned int vexvvvv
:2;
658 unsigned int vexopcode
:3;
659 unsigned int vexsources
:2;
660 unsigned int veximmext
:1;
661 unsigned int vecsib
:2;
662 unsigned int sse2avx
:1;
663 unsigned int noavx
:1;
665 unsigned int masking
:2;
666 unsigned int vecesize
:1;
667 unsigned int broadcast
:3;
668 unsigned int staticrounding
:1;
670 unsigned int disp8memshift
:3;
671 unsigned int nodefmask
:1;
672 unsigned int implicitquadgroup
:1;
673 unsigned int oldgcc
:1;
674 unsigned int attmnemonic
:1;
675 unsigned int attsyntax
:1;
676 unsigned int intelsyntax
:1;
677 unsigned int amd64
:1;
678 unsigned int intel64
:1;
679 } i386_opcode_modifier
;
681 /* Position of operand_type bits. */
685 /* Register (qualified by Byte, Word, etc) */
689 /* Vector registers */
691 /* Vector Mask registers */
693 /* Control register */
699 /* 2 bit segment register */
701 /* 3 bit segment register */
703 /* 1 bit immediate */
705 /* 8 bit immediate */
707 /* 8 bit immediate sign extended */
709 /* 16 bit immediate */
711 /* 32 bit immediate */
713 /* 32 bit immediate sign extended */
715 /* 64 bit immediate */
717 /* 8bit/16bit/32bit displacements are used in different ways,
718 depending on the instruction. For jumps, they specify the
719 size of the PC relative displacement, for instructions with
720 memory operand, they specify the size of the offset relative
721 to the base register, and for instructions with memory offset
722 such as `mov 1234,%al' they specify the size of the offset
723 relative to the segment base. */
724 /* 8 bit displacement */
726 /* 16 bit displacement */
728 /* 32 bit displacement */
730 /* 32 bit signed displacement */
732 /* 64 bit displacement */
734 /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
736 /* Register which can be used for base or index in memory operand. */
738 /* Register to hold in/out port addr = dx */
740 /* Register to hold shift count = cl */
742 /* Absolute address for jump. */
744 /* String insn operand with fixed es segment */
746 /* RegMem is for instructions with a modrm byte where the register
747 destination operand should be encoded in the mod and regmem fields.
748 Normally, it will be encoded in the reg field. We add a RegMem
749 flag to the destination register operand to indicate that it should
750 be encoded in the regmem field. */
756 /* WORD memory. 2 byte */
758 /* DWORD memory. 4 byte */
760 /* FWORD memory. 6 byte */
762 /* QWORD memory. 8 byte */
764 /* TBYTE memory. 10 byte */
766 /* XMMWORD memory. */
768 /* YMMWORD memory. */
770 /* ZMMWORD memory. */
772 /* Unspecified memory size. */
774 /* Any memory size. */
777 /* Vector 4 bit immediate. */
780 /* Bound register. */
783 /* The last bitfield in i386_operand_type. */
787 #define OTNumOfUints \
788 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
789 #define OTNumOfBits \
790 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
792 /* If you get a compiler error for zero width of the unused field,
794 #define OTUnused (OTMax + 1)
796 typedef union i386_operand_type
801 unsigned int regmmx
:1;
802 unsigned int regsimd
:1;
803 unsigned int regmask
:1;
804 unsigned int control
:1;
805 unsigned int debug
:1;
807 unsigned int sreg2
:1;
808 unsigned int sreg3
:1;
811 unsigned int imm8s
:1;
812 unsigned int imm16
:1;
813 unsigned int imm32
:1;
814 unsigned int imm32s
:1;
815 unsigned int imm64
:1;
816 unsigned int disp8
:1;
817 unsigned int disp16
:1;
818 unsigned int disp32
:1;
819 unsigned int disp32s
:1;
820 unsigned int disp64
:1;
822 unsigned int baseindex
:1;
823 unsigned int inoutportreg
:1;
824 unsigned int shiftcount
:1;
825 unsigned int jumpabsolute
:1;
826 unsigned int esseg
:1;
827 unsigned int regmem
:1;
831 unsigned int dword
:1;
832 unsigned int fword
:1;
833 unsigned int qword
:1;
834 unsigned int tbyte
:1;
835 unsigned int xmmword
:1;
836 unsigned int ymmword
:1;
837 unsigned int zmmword
:1;
838 unsigned int unspecified
:1;
839 unsigned int anysize
:1;
840 unsigned int vec_imm4
:1;
841 unsigned int regbnd
:1;
843 unsigned int unused
:(OTNumOfBits
- OTUnused
);
846 unsigned int array
[OTNumOfUints
];
849 typedef struct insn_template
851 /* instruction name sans width suffix ("mov" for movl insns) */
854 /* how many operands */
855 unsigned int operands
;
857 /* base_opcode is the fundamental opcode byte without optional
859 unsigned int base_opcode
;
860 #define Opcode_D 0x2 /* Direction bit:
861 set if Reg --> Regmem;
862 unset if Regmem --> Reg. */
863 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
864 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
866 /* extension_opcode is the 3 bit extension for group <n> insns.
867 This field is also used to store the 8-bit opcode suffix for the
868 AMD 3DNow! instructions.
869 If this template has no extension opcode (the usual case) use None
871 unsigned int extension_opcode
;
872 #define None 0xffff /* If no extension_opcode is possible. */
875 unsigned char opcode_length
;
877 /* cpu feature flags */
878 i386_cpu_flags cpu_flags
;
880 /* the bits in opcode_modifier are used to generate the final opcode from
881 the base_opcode. These bits also are used to detect alternate forms of
882 the same instruction */
883 i386_opcode_modifier opcode_modifier
;
885 /* operand_types[i] describes the type of operand i. This is made
886 by OR'ing together all of the possible type masks. (e.g.
887 'operand_types[i] = Reg|Imm' specifies that operand i can be
888 either a register or an immediate operand. */
889 i386_operand_type operand_types
[MAX_OPERANDS
];
893 extern const insn_template i386_optab
[];
895 /* these are for register name --> number & type hash lookup */
899 i386_operand_type reg_type
;
900 unsigned char reg_flags
;
901 #define RegRex 0x1 /* Extended register. */
902 #define RegRex64 0x2 /* Extended 8 bit register. */
903 #define RegVRex 0x4 /* Extended vector register. */
904 unsigned char reg_num
;
905 #define RegRip ((unsigned char ) ~0)
906 #define RegEip (RegRip - 1)
907 /* EIZ and RIZ are fake index registers. */
908 #define RegEiz (RegEip - 1)
909 #define RegRiz (RegEiz - 1)
910 /* FLAT is a fake segment register (Intel mode). */
911 #define RegFlat ((unsigned char) ~0)
912 signed char dw2_regnum
[2];
913 #define Dw2Inval (-1)
917 /* Entries in i386_regtab. */
920 #define REGNAM_EAX 41
922 extern const reg_entry i386_regtab
[];
923 extern const unsigned int i386_regtab_size
;
928 unsigned int seg_prefix
;
932 extern const seg_entry cs
;
933 extern const seg_entry ds
;
934 extern const seg_entry ss
;
935 extern const seg_entry es
;
936 extern const seg_entry fs
;
937 extern const seg_entry gs
;