1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2015 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Xsave/xrstor New Instructions support required */
117 /* Xsaveopt New Instructions support required */
119 /* AES support required */
121 /* PCLMUL support required */
123 /* FMA support required */
125 /* FMA4 support required */
127 /* XOP support required */
129 /* LWP support required */
131 /* BMI support required */
133 /* TBM support required */
135 /* MOVBE Instruction support required */
137 /* CMPXCHG16B instruction support required. */
139 /* EPT Instructions required */
141 /* RDTSCP Instruction support required */
143 /* FSGSBASE Instructions required */
145 /* RDRND Instructions required */
147 /* F16C Instructions required */
149 /* Intel BMI2 support required */
151 /* LZCNT support required */
153 /* HLE support required */
155 /* RTM support required */
157 /* INVPCID Instructions required */
159 /* VMFUNC Instruction required */
161 /* Intel MPX Instructions required */
163 /* 64bit support available, used by -march= in assembler. */
165 /* RDRSEED instruction required. */
167 /* Multi-presisionn add-carry instructions are required. */
169 /* Supports prefetchw and prefetch instructions. */
171 /* SMAP instructions required. */
173 /* SHA instructions required. */
175 /* VREX support required */
177 /* CLFLUSHOPT instruction required */
179 /* XSAVES/XRSTORS instruction required */
181 /* XSAVEC instruction required */
183 /* PREFETCHWT1 instruction required */
185 /* SE1 instruction required */
187 /* CLWB instruction required */
189 /* PCOMMIT instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* 64bit support required */
197 /* Not supported in the 64bit mode */
199 /* The last bitfield in i386_cpu_flags. */
203 #define CpuNumOfUints \
204 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
205 #define CpuNumOfBits \
206 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
208 /* If you get a compiler error for zero width of the unused field,
210 #define CpuUnused (CpuMax + 1)
212 /* We can check if an instruction is available with array instead
214 typedef union i386_cpu_flags
218 unsigned int cpui186
:1;
219 unsigned int cpui286
:1;
220 unsigned int cpui386
:1;
221 unsigned int cpui486
:1;
222 unsigned int cpui586
:1;
223 unsigned int cpui686
:1;
224 unsigned int cpuclflush
:1;
225 unsigned int cpunop
:1;
226 unsigned int cpusyscall
:1;
227 unsigned int cpu8087
:1;
228 unsigned int cpu287
:1;
229 unsigned int cpu387
:1;
230 unsigned int cpu687
:1;
231 unsigned int cpufisttp
:1;
232 unsigned int cpummx
:1;
233 unsigned int cpusse
:1;
234 unsigned int cpusse2
:1;
235 unsigned int cpua3dnow
:1;
236 unsigned int cpua3dnowa
:1;
237 unsigned int cpusse3
:1;
238 unsigned int cpupadlock
:1;
239 unsigned int cpusvme
:1;
240 unsigned int cpuvmx
:1;
241 unsigned int cpusmx
:1;
242 unsigned int cpussse3
:1;
243 unsigned int cpusse4a
:1;
244 unsigned int cpuabm
:1;
245 unsigned int cpusse4_1
:1;
246 unsigned int cpusse4_2
:1;
247 unsigned int cpuavx
:1;
248 unsigned int cpuavx2
:1;
249 unsigned int cpuavx512f
:1;
250 unsigned int cpuavx512cd
:1;
251 unsigned int cpuavx512er
:1;
252 unsigned int cpuavx512pf
:1;
253 unsigned int cpuavx512vl
:1;
254 unsigned int cpuavx512dq
:1;
255 unsigned int cpuavx512bw
:1;
256 unsigned int cpul1om
:1;
257 unsigned int cpuk1om
:1;
258 unsigned int cpuxsave
:1;
259 unsigned int cpuxsaveopt
:1;
260 unsigned int cpuaes
:1;
261 unsigned int cpupclmul
:1;
262 unsigned int cpufma
:1;
263 unsigned int cpufma4
:1;
264 unsigned int cpuxop
:1;
265 unsigned int cpulwp
:1;
266 unsigned int cpubmi
:1;
267 unsigned int cputbm
:1;
268 unsigned int cpumovbe
:1;
269 unsigned int cpucx16
:1;
270 unsigned int cpuept
:1;
271 unsigned int cpurdtscp
:1;
272 unsigned int cpufsgsbase
:1;
273 unsigned int cpurdrnd
:1;
274 unsigned int cpuf16c
:1;
275 unsigned int cpubmi2
:1;
276 unsigned int cpulzcnt
:1;
277 unsigned int cpuhle
:1;
278 unsigned int cpurtm
:1;
279 unsigned int cpuinvpcid
:1;
280 unsigned int cpuvmfunc
:1;
281 unsigned int cpumpx
:1;
282 unsigned int cpulm
:1;
283 unsigned int cpurdseed
:1;
284 unsigned int cpuadx
:1;
285 unsigned int cpuprfchw
:1;
286 unsigned int cpusmap
:1;
287 unsigned int cpusha
:1;
288 unsigned int cpuvrex
:1;
289 unsigned int cpuclflushopt
:1;
290 unsigned int cpuxsaves
:1;
291 unsigned int cpuxsavec
:1;
292 unsigned int cpuprefetchwt1
:1;
293 unsigned int cpuse1
:1;
294 unsigned int cpuclwb
:1;
295 unsigned int cpupcommit
:1;
296 unsigned int cpuavx512ifma
:1;
297 unsigned int cpuavx512vbmi
:1;
298 unsigned int cpu64
:1;
299 unsigned int cpuno64
:1;
301 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
304 unsigned int array
[CpuNumOfUints
];
307 /* Position of opcode_modifier bits. */
311 /* has direction bit. */
313 /* set if operands can be words or dwords encoded the canonical way */
315 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
316 operand in encoding. */
318 /* insn has a modrm byte. */
320 /* register is in low 3 bits of opcode */
322 /* special case for jump insns. */
328 /* special case for intersegment leaps/calls */
330 /* FP insn memory format bit, sized by 0x4 */
332 /* src/dest swap for floats. */
334 /* has float insn direction bit. */
336 /* needs size prefix if in 32-bit mode */
338 /* needs size prefix if in 16-bit mode */
340 /* needs size prefix if in 64-bit mode */
342 /* check register size. */
344 /* instruction ignores operand size prefix and in Intel mode ignores
345 mnemonic size suffix check. */
347 /* default insn size depends on mode */
349 /* b suffix on instruction illegal */
351 /* w suffix on instruction illegal */
353 /* l suffix on instruction illegal */
355 /* s suffix on instruction illegal */
357 /* q suffix on instruction illegal */
359 /* long double suffix on instruction illegal */
361 /* instruction needs FWAIT */
363 /* quick test for string instructions */
365 /* quick test if branch instruction is MPX supported */
367 /* quick test for lockable instructions */
369 /* fake an extra reg operand for clr, imul and special register
370 processing for some instructions. */
372 /* The first operand must be xmm0 */
374 /* An implicit xmm0 as the first operand */
376 /* The HLE prefix is OK:
377 1. With a LOCK prefix.
378 2. With or without a LOCK prefix.
379 3. With a RELEASE (0xf3) prefix.
381 #define HLEPrefixNone 0
382 #define HLEPrefixLock 1
383 #define HLEPrefixAny 2
384 #define HLEPrefixRelease 3
386 /* An instruction on which a "rep" prefix is acceptable. */
388 /* Convert to DWORD */
390 /* Convert to QWORD */
392 /* Address prefix changes operand 0 */
394 /* opcode is a prefix */
396 /* instruction has extension in 8 bit imm */
398 /* instruction don't need Rex64 prefix. */
400 /* instruction require Rex64 prefix. */
402 /* deprecated fp insn, gets a warning */
404 /* insn has VEX prefix:
405 1: 128bit VEX prefix.
406 2: 256bit VEX prefix.
407 3: Scalar VEX prefix.
413 /* How to encode VEX.vvvv:
414 0: VEX.vvvv must be 1111b.
415 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
416 the content of source registers will be preserved.
417 VEX.DDS. The second register operand is encoded in VEX.vvvv
418 where the content of first source register will be overwritten
420 VEX.NDD2. The second destination register operand is encoded in
421 VEX.vvvv for instructions with 2 destination register operands.
422 For assembler, there are no difference between VEX.NDS, VEX.DDS
424 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
425 instructions with 1 destination register operand.
426 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
427 of the operands can access a memory location.
433 /* How the VEX.W bit is used:
434 0: Set by the REX.W bit.
435 1: VEX.W0. Should always be 0.
436 2: VEX.W1. Should always be 1.
441 /* VEX opcode prefix:
442 0: VEX 0x0F opcode prefix.
443 1: VEX 0x0F38 opcode prefix.
444 2: VEX 0x0F3A opcode prefix
445 3: XOP 0x08 opcode prefix.
446 4: XOP 0x09 opcode prefix
447 5: XOP 0x0A opcode prefix.
456 /* number of VEX source operands:
457 0: <= 2 source operands.
458 1: 2 XOP source operands.
459 2: 3 source operands.
461 #define XOP2SOURCES 1
462 #define VEX3SOURCES 2
464 /* instruction has VEX 8 bit imm */
466 /* Instruction with vector SIB byte:
467 1: 128bit vector register.
468 2: 256bit vector register.
469 3: 512bit vector register.
475 /* SSE to AVX support required */
477 /* No AVX equivalent */
480 /* insn has EVEX prefix:
481 1: 512bit EVEX prefix.
482 2: 128bit EVEX prefix.
483 3: 256bit EVEX prefix.
484 4: Length-ignored (LIG) EVEX prefix.
492 /* AVX512 masking support:
495 3: Both zeroing and merging masking.
497 #define ZEROING_MASKING 1
498 #define MERGING_MASKING 2
499 #define BOTH_MASKING 3
502 /* Input element size of vector insn:
513 #define NO_BROADCAST 0
514 #define BROADCAST_1TO16 1
515 #define BROADCAST_1TO8 2
516 #define BROADCAST_1TO4 3
517 #define BROADCAST_1TO2 4
520 /* Static rounding control is supported. */
523 /* Supress All Exceptions is supported. */
526 /* Copressed Disp8*N attribute. */
529 /* Default mask isn't allowed. */
532 /* Compatible with old (<= 2.8.1) versions of gcc */
540 /* The last bitfield in i386_opcode_modifier. */
544 typedef struct i386_opcode_modifier
549 unsigned int modrm
:1;
550 unsigned int shortform
:1;
552 unsigned int jumpdword
:1;
553 unsigned int jumpbyte
:1;
554 unsigned int jumpintersegment
:1;
555 unsigned int floatmf
:1;
556 unsigned int floatr
:1;
557 unsigned int floatd
:1;
558 unsigned int size16
:1;
559 unsigned int size32
:1;
560 unsigned int size64
:1;
561 unsigned int checkregsize
:1;
562 unsigned int ignoresize
:1;
563 unsigned int defaultsize
:1;
564 unsigned int no_bsuf
:1;
565 unsigned int no_wsuf
:1;
566 unsigned int no_lsuf
:1;
567 unsigned int no_ssuf
:1;
568 unsigned int no_qsuf
:1;
569 unsigned int no_ldsuf
:1;
570 unsigned int fwait
:1;
571 unsigned int isstring
:1;
572 unsigned int bndprefixok
:1;
573 unsigned int islockable
:1;
574 unsigned int regkludge
:1;
575 unsigned int firstxmm0
:1;
576 unsigned int implicit1stxmm0
:1;
577 unsigned int hleprefixok
:2;
578 unsigned int repprefixok
:1;
579 unsigned int todword
:1;
580 unsigned int toqword
:1;
581 unsigned int addrprefixop0
:1;
582 unsigned int isprefix
:1;
583 unsigned int immext
:1;
584 unsigned int norex64
:1;
585 unsigned int rex64
:1;
588 unsigned int vexvvvv
:2;
590 unsigned int vexopcode
:3;
591 unsigned int vexsources
:2;
592 unsigned int veximmext
:1;
593 unsigned int vecsib
:2;
594 unsigned int sse2avx
:1;
595 unsigned int noavx
:1;
597 unsigned int masking
:2;
598 unsigned int vecesize
:1;
599 unsigned int broadcast
:3;
600 unsigned int staticrounding
:1;
602 unsigned int disp8memshift
:3;
603 unsigned int nodefmask
:1;
604 unsigned int oldgcc
:1;
605 unsigned int attmnemonic
:1;
606 unsigned int attsyntax
:1;
607 unsigned int intelsyntax
:1;
608 } i386_opcode_modifier
;
610 /* Position of operand_type bits. */
622 /* Floating pointer stack register */
630 /* AVX512 registers */
632 /* Vector Mask registers */
634 /* Control register */
640 /* 2 bit segment register */
642 /* 3 bit segment register */
644 /* 1 bit immediate */
646 /* 8 bit immediate */
648 /* 8 bit immediate sign extended */
650 /* 16 bit immediate */
652 /* 32 bit immediate */
654 /* 32 bit immediate sign extended */
656 /* 64 bit immediate */
658 /* 8bit/16bit/32bit displacements are used in different ways,
659 depending on the instruction. For jumps, they specify the
660 size of the PC relative displacement, for instructions with
661 memory operand, they specify the size of the offset relative
662 to the base register, and for instructions with memory offset
663 such as `mov 1234,%al' they specify the size of the offset
664 relative to the segment base. */
665 /* 8 bit displacement */
667 /* 16 bit displacement */
669 /* 32 bit displacement */
671 /* 32 bit signed displacement */
673 /* 64 bit displacement */
675 /* Accumulator %al/%ax/%eax/%rax */
677 /* Floating pointer top stack register %st(0) */
679 /* Register which can be used for base or index in memory operand. */
681 /* Register to hold in/out port addr = dx */
683 /* Register to hold shift count = cl */
685 /* Absolute address for jump. */
687 /* String insn operand with fixed es segment */
689 /* RegMem is for instructions with a modrm byte where the register
690 destination operand should be encoded in the mod and regmem fields.
691 Normally, it will be encoded in the reg field. We add a RegMem
692 flag to the destination register operand to indicate that it should
693 be encoded in the regmem field. */
699 /* WORD memory. 2 byte */
701 /* DWORD memory. 4 byte */
703 /* FWORD memory. 6 byte */
705 /* QWORD memory. 8 byte */
707 /* TBYTE memory. 10 byte */
709 /* XMMWORD memory. */
711 /* YMMWORD memory. */
713 /* ZMMWORD memory. */
715 /* Unspecified memory size. */
717 /* Any memory size. */
720 /* Vector 4 bit immediate. */
723 /* Bound register. */
726 /* Vector 8bit displacement */
729 /* The last bitfield in i386_operand_type. */
733 #define OTNumOfUints \
734 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
735 #define OTNumOfBits \
736 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
738 /* If you get a compiler error for zero width of the unused field,
740 #define OTUnused (OTMax + 1)
742 typedef union i386_operand_type
747 unsigned int reg16
:1;
748 unsigned int reg32
:1;
749 unsigned int reg64
:1;
750 unsigned int floatreg
:1;
751 unsigned int regmmx
:1;
752 unsigned int regxmm
:1;
753 unsigned int regymm
:1;
754 unsigned int regzmm
:1;
755 unsigned int regmask
:1;
756 unsigned int control
:1;
757 unsigned int debug
:1;
759 unsigned int sreg2
:1;
760 unsigned int sreg3
:1;
763 unsigned int imm8s
:1;
764 unsigned int imm16
:1;
765 unsigned int imm32
:1;
766 unsigned int imm32s
:1;
767 unsigned int imm64
:1;
768 unsigned int disp8
:1;
769 unsigned int disp16
:1;
770 unsigned int disp32
:1;
771 unsigned int disp32s
:1;
772 unsigned int disp64
:1;
774 unsigned int floatacc
:1;
775 unsigned int baseindex
:1;
776 unsigned int inoutportreg
:1;
777 unsigned int shiftcount
:1;
778 unsigned int jumpabsolute
:1;
779 unsigned int esseg
:1;
780 unsigned int regmem
:1;
784 unsigned int dword
:1;
785 unsigned int fword
:1;
786 unsigned int qword
:1;
787 unsigned int tbyte
:1;
788 unsigned int xmmword
:1;
789 unsigned int ymmword
:1;
790 unsigned int zmmword
:1;
791 unsigned int unspecified
:1;
792 unsigned int anysize
:1;
793 unsigned int vec_imm4
:1;
794 unsigned int regbnd
:1;
795 unsigned int vec_disp8
:1;
797 unsigned int unused
:(OTNumOfBits
- OTUnused
);
800 unsigned int array
[OTNumOfUints
];
803 typedef struct insn_template
805 /* instruction name sans width suffix ("mov" for movl insns) */
808 /* how many operands */
809 unsigned int operands
;
811 /* base_opcode is the fundamental opcode byte without optional
813 unsigned int base_opcode
;
814 #define Opcode_D 0x2 /* Direction bit:
815 set if Reg --> Regmem;
816 unset if Regmem --> Reg. */
817 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
818 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
820 /* extension_opcode is the 3 bit extension for group <n> insns.
821 This field is also used to store the 8-bit opcode suffix for the
822 AMD 3DNow! instructions.
823 If this template has no extension opcode (the usual case) use None
825 unsigned int extension_opcode
;
826 #define None 0xffff /* If no extension_opcode is possible. */
829 unsigned char opcode_length
;
831 /* cpu feature flags */
832 i386_cpu_flags cpu_flags
;
834 /* the bits in opcode_modifier are used to generate the final opcode from
835 the base_opcode. These bits also are used to detect alternate forms of
836 the same instruction */
837 i386_opcode_modifier opcode_modifier
;
839 /* operand_types[i] describes the type of operand i. This is made
840 by OR'ing together all of the possible type masks. (e.g.
841 'operand_types[i] = Reg|Imm' specifies that operand i can be
842 either a register or an immediate operand. */
843 i386_operand_type operand_types
[MAX_OPERANDS
];
847 extern const insn_template i386_optab
[];
849 /* these are for register name --> number & type hash lookup */
853 i386_operand_type reg_type
;
854 unsigned char reg_flags
;
855 #define RegRex 0x1 /* Extended register. */
856 #define RegRex64 0x2 /* Extended 8 bit register. */
857 #define RegVRex 0x4 /* Extended vector register. */
858 unsigned char reg_num
;
859 #define RegRip ((unsigned char ) ~0)
860 #define RegEip (RegRip - 1)
861 /* EIZ and RIZ are fake index registers. */
862 #define RegEiz (RegEip - 1)
863 #define RegRiz (RegEiz - 1)
864 /* FLAT is a fake segment register (Intel mode). */
865 #define RegFlat ((unsigned char) ~0)
866 signed char dw2_regnum
[2];
867 #define Dw2Inval (-1)
871 /* Entries in i386_regtab. */
874 #define REGNAM_EAX 41
876 extern const reg_entry i386_regtab
[];
877 extern const unsigned int i386_regtab_size
;
882 unsigned int seg_prefix
;
886 extern const seg_entry cs
;
887 extern const seg_entry ds
;
888 extern const seg_entry ss
;
889 extern const seg_entry es
;
890 extern const seg_entry fs
;
891 extern const seg_entry gs
;