1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2016 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* PCOMMIT instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* mwaitx instruction required */
199 /* Clzero instruction required */
201 /* OSPKE instruction required */
203 /* RDPID instruction required */
205 /* 64bit support required */
207 /* Not supported in the 64bit mode */
209 /* AMD64 support required */
211 /* Intel64 support required */
213 /* The last bitfield in i386_cpu_flags. */
217 #define CpuNumOfUints \
218 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
219 #define CpuNumOfBits \
220 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
222 /* If you get a compiler error for zero width of the unused field,
224 #define CpuUnused (CpuMax + 1)
226 /* We can check if an instruction is available with array instead
228 typedef union i386_cpu_flags
232 unsigned int cpui186
:1;
233 unsigned int cpui286
:1;
234 unsigned int cpui386
:1;
235 unsigned int cpui486
:1;
236 unsigned int cpui586
:1;
237 unsigned int cpui686
:1;
238 unsigned int cpuclflush
:1;
239 unsigned int cpunop
:1;
240 unsigned int cpusyscall
:1;
241 unsigned int cpu8087
:1;
242 unsigned int cpu287
:1;
243 unsigned int cpu387
:1;
244 unsigned int cpu687
:1;
245 unsigned int cpufisttp
:1;
246 unsigned int cpummx
:1;
247 unsigned int cpusse
:1;
248 unsigned int cpusse2
:1;
249 unsigned int cpua3dnow
:1;
250 unsigned int cpua3dnowa
:1;
251 unsigned int cpusse3
:1;
252 unsigned int cpupadlock
:1;
253 unsigned int cpusvme
:1;
254 unsigned int cpuvmx
:1;
255 unsigned int cpusmx
:1;
256 unsigned int cpussse3
:1;
257 unsigned int cpusse4a
:1;
258 unsigned int cpuabm
:1;
259 unsigned int cpusse4_1
:1;
260 unsigned int cpusse4_2
:1;
261 unsigned int cpuavx
:1;
262 unsigned int cpuavx2
:1;
263 unsigned int cpuavx512f
:1;
264 unsigned int cpuavx512cd
:1;
265 unsigned int cpuavx512er
:1;
266 unsigned int cpuavx512pf
:1;
267 unsigned int cpuavx512vl
:1;
268 unsigned int cpuavx512dq
:1;
269 unsigned int cpuavx512bw
:1;
270 unsigned int cpul1om
:1;
271 unsigned int cpuk1om
:1;
272 unsigned int cpuiamcu
:1;
273 unsigned int cpuxsave
:1;
274 unsigned int cpuxsaveopt
:1;
275 unsigned int cpuaes
:1;
276 unsigned int cpupclmul
:1;
277 unsigned int cpufma
:1;
278 unsigned int cpufma4
:1;
279 unsigned int cpuxop
:1;
280 unsigned int cpulwp
:1;
281 unsigned int cpubmi
:1;
282 unsigned int cputbm
:1;
283 unsigned int cpumovbe
:1;
284 unsigned int cpucx16
:1;
285 unsigned int cpuept
:1;
286 unsigned int cpurdtscp
:1;
287 unsigned int cpufsgsbase
:1;
288 unsigned int cpurdrnd
:1;
289 unsigned int cpuf16c
:1;
290 unsigned int cpubmi2
:1;
291 unsigned int cpulzcnt
:1;
292 unsigned int cpuhle
:1;
293 unsigned int cpurtm
:1;
294 unsigned int cpuinvpcid
:1;
295 unsigned int cpuvmfunc
:1;
296 unsigned int cpumpx
:1;
297 unsigned int cpulm
:1;
298 unsigned int cpurdseed
:1;
299 unsigned int cpuadx
:1;
300 unsigned int cpuprfchw
:1;
301 unsigned int cpusmap
:1;
302 unsigned int cpusha
:1;
303 unsigned int cpuvrex
:1;
304 unsigned int cpuclflushopt
:1;
305 unsigned int cpuxsaves
:1;
306 unsigned int cpuxsavec
:1;
307 unsigned int cpuprefetchwt1
:1;
308 unsigned int cpuse1
:1;
309 unsigned int cpuclwb
:1;
310 unsigned int cpupcommit
:1;
311 unsigned int cpuavx512ifma
:1;
312 unsigned int cpuavx512vbmi
:1;
313 unsigned int cpumwaitx
:1;
314 unsigned int cpuclzero
:1;
315 unsigned int cpuospke
:1;
316 unsigned int cpurdpid
:1;
317 unsigned int cpu64
:1;
318 unsigned int cpuno64
:1;
319 unsigned int cpuamd64
:1;
320 unsigned int cpuintel64
:1;
322 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
325 unsigned int array
[CpuNumOfUints
];
328 /* Position of opcode_modifier bits. */
332 /* has direction bit. */
334 /* set if operands can be words or dwords encoded the canonical way */
336 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
337 operand in encoding. */
339 /* insn has a modrm byte. */
341 /* register is in low 3 bits of opcode */
343 /* special case for jump insns. */
349 /* special case for intersegment leaps/calls */
351 /* FP insn memory format bit, sized by 0x4 */
353 /* src/dest swap for floats. */
355 /* has float insn direction bit. */
357 /* needs size prefix if in 32-bit mode */
359 /* needs size prefix if in 16-bit mode */
361 /* needs size prefix if in 64-bit mode */
363 /* check register size. */
365 /* instruction ignores operand size prefix and in Intel mode ignores
366 mnemonic size suffix check. */
368 /* default insn size depends on mode */
370 /* b suffix on instruction illegal */
372 /* w suffix on instruction illegal */
374 /* l suffix on instruction illegal */
376 /* s suffix on instruction illegal */
378 /* q suffix on instruction illegal */
380 /* long double suffix on instruction illegal */
382 /* instruction needs FWAIT */
384 /* quick test for string instructions */
386 /* quick test if branch instruction is MPX supported */
388 /* quick test for lockable instructions */
390 /* fake an extra reg operand for clr, imul and special register
391 processing for some instructions. */
393 /* The first operand must be xmm0 */
395 /* An implicit xmm0 as the first operand */
397 /* The HLE prefix is OK:
398 1. With a LOCK prefix.
399 2. With or without a LOCK prefix.
400 3. With a RELEASE (0xf3) prefix.
402 #define HLEPrefixNone 0
403 #define HLEPrefixLock 1
404 #define HLEPrefixAny 2
405 #define HLEPrefixRelease 3
407 /* An instruction on which a "rep" prefix is acceptable. */
409 /* Convert to DWORD */
411 /* Convert to QWORD */
413 /* Address prefix changes operand 0 */
415 /* opcode is a prefix */
417 /* instruction has extension in 8 bit imm */
419 /* instruction don't need Rex64 prefix. */
421 /* instruction require Rex64 prefix. */
423 /* deprecated fp insn, gets a warning */
425 /* insn has VEX prefix:
426 1: 128bit VEX prefix.
427 2: 256bit VEX prefix.
428 3: Scalar VEX prefix.
434 /* How to encode VEX.vvvv:
435 0: VEX.vvvv must be 1111b.
436 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
437 the content of source registers will be preserved.
438 VEX.DDS. The second register operand is encoded in VEX.vvvv
439 where the content of first source register will be overwritten
441 VEX.NDD2. The second destination register operand is encoded in
442 VEX.vvvv for instructions with 2 destination register operands.
443 For assembler, there are no difference between VEX.NDS, VEX.DDS
445 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
446 instructions with 1 destination register operand.
447 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
448 of the operands can access a memory location.
454 /* How the VEX.W bit is used:
455 0: Set by the REX.W bit.
456 1: VEX.W0. Should always be 0.
457 2: VEX.W1. Should always be 1.
462 /* VEX opcode prefix:
463 0: VEX 0x0F opcode prefix.
464 1: VEX 0x0F38 opcode prefix.
465 2: VEX 0x0F3A opcode prefix
466 3: XOP 0x08 opcode prefix.
467 4: XOP 0x09 opcode prefix
468 5: XOP 0x0A opcode prefix.
477 /* number of VEX source operands:
478 0: <= 2 source operands.
479 1: 2 XOP source operands.
480 2: 3 source operands.
482 #define XOP2SOURCES 1
483 #define VEX3SOURCES 2
485 /* instruction has VEX 8 bit imm */
487 /* Instruction with vector SIB byte:
488 1: 128bit vector register.
489 2: 256bit vector register.
490 3: 512bit vector register.
496 /* SSE to AVX support required */
498 /* No AVX equivalent */
501 /* insn has EVEX prefix:
502 1: 512bit EVEX prefix.
503 2: 128bit EVEX prefix.
504 3: 256bit EVEX prefix.
505 4: Length-ignored (LIG) EVEX prefix.
513 /* AVX512 masking support:
516 3: Both zeroing and merging masking.
518 #define ZEROING_MASKING 1
519 #define MERGING_MASKING 2
520 #define BOTH_MASKING 3
523 /* Input element size of vector insn:
534 #define NO_BROADCAST 0
535 #define BROADCAST_1TO16 1
536 #define BROADCAST_1TO8 2
537 #define BROADCAST_1TO4 3
538 #define BROADCAST_1TO2 4
541 /* Static rounding control is supported. */
544 /* Supress All Exceptions is supported. */
547 /* Copressed Disp8*N attribute. */
550 /* Default mask isn't allowed. */
553 /* Compatible with old (<= 2.8.1) versions of gcc */
561 /* The last bitfield in i386_opcode_modifier. */
565 typedef struct i386_opcode_modifier
570 unsigned int modrm
:1;
571 unsigned int shortform
:1;
573 unsigned int jumpdword
:1;
574 unsigned int jumpbyte
:1;
575 unsigned int jumpintersegment
:1;
576 unsigned int floatmf
:1;
577 unsigned int floatr
:1;
578 unsigned int floatd
:1;
579 unsigned int size16
:1;
580 unsigned int size32
:1;
581 unsigned int size64
:1;
582 unsigned int checkregsize
:1;
583 unsigned int ignoresize
:1;
584 unsigned int defaultsize
:1;
585 unsigned int no_bsuf
:1;
586 unsigned int no_wsuf
:1;
587 unsigned int no_lsuf
:1;
588 unsigned int no_ssuf
:1;
589 unsigned int no_qsuf
:1;
590 unsigned int no_ldsuf
:1;
591 unsigned int fwait
:1;
592 unsigned int isstring
:1;
593 unsigned int bndprefixok
:1;
594 unsigned int islockable
:1;
595 unsigned int regkludge
:1;
596 unsigned int firstxmm0
:1;
597 unsigned int implicit1stxmm0
:1;
598 unsigned int hleprefixok
:2;
599 unsigned int repprefixok
:1;
600 unsigned int todword
:1;
601 unsigned int toqword
:1;
602 unsigned int addrprefixop0
:1;
603 unsigned int isprefix
:1;
604 unsigned int immext
:1;
605 unsigned int norex64
:1;
606 unsigned int rex64
:1;
609 unsigned int vexvvvv
:2;
611 unsigned int vexopcode
:3;
612 unsigned int vexsources
:2;
613 unsigned int veximmext
:1;
614 unsigned int vecsib
:2;
615 unsigned int sse2avx
:1;
616 unsigned int noavx
:1;
618 unsigned int masking
:2;
619 unsigned int vecesize
:1;
620 unsigned int broadcast
:3;
621 unsigned int staticrounding
:1;
623 unsigned int disp8memshift
:3;
624 unsigned int nodefmask
:1;
625 unsigned int oldgcc
:1;
626 unsigned int attmnemonic
:1;
627 unsigned int attsyntax
:1;
628 unsigned int intelsyntax
:1;
629 } i386_opcode_modifier
;
631 /* Position of operand_type bits. */
643 /* Floating pointer stack register */
651 /* AVX512 registers */
653 /* Vector Mask registers */
655 /* Control register */
661 /* 2 bit segment register */
663 /* 3 bit segment register */
665 /* 1 bit immediate */
667 /* 8 bit immediate */
669 /* 8 bit immediate sign extended */
671 /* 16 bit immediate */
673 /* 32 bit immediate */
675 /* 32 bit immediate sign extended */
677 /* 64 bit immediate */
679 /* 8bit/16bit/32bit displacements are used in different ways,
680 depending on the instruction. For jumps, they specify the
681 size of the PC relative displacement, for instructions with
682 memory operand, they specify the size of the offset relative
683 to the base register, and for instructions with memory offset
684 such as `mov 1234,%al' they specify the size of the offset
685 relative to the segment base. */
686 /* 8 bit displacement */
688 /* 16 bit displacement */
690 /* 32 bit displacement */
692 /* 32 bit signed displacement */
694 /* 64 bit displacement */
696 /* Accumulator %al/%ax/%eax/%rax */
698 /* Floating pointer top stack register %st(0) */
700 /* Register which can be used for base or index in memory operand. */
702 /* Register to hold in/out port addr = dx */
704 /* Register to hold shift count = cl */
706 /* Absolute address for jump. */
708 /* String insn operand with fixed es segment */
710 /* RegMem is for instructions with a modrm byte where the register
711 destination operand should be encoded in the mod and regmem fields.
712 Normally, it will be encoded in the reg field. We add a RegMem
713 flag to the destination register operand to indicate that it should
714 be encoded in the regmem field. */
720 /* WORD memory. 2 byte */
722 /* DWORD memory. 4 byte */
724 /* FWORD memory. 6 byte */
726 /* QWORD memory. 8 byte */
728 /* TBYTE memory. 10 byte */
730 /* XMMWORD memory. */
732 /* YMMWORD memory. */
734 /* ZMMWORD memory. */
736 /* Unspecified memory size. */
738 /* Any memory size. */
741 /* Vector 4 bit immediate. */
744 /* Bound register. */
747 /* Vector 8bit displacement */
750 /* The last bitfield in i386_operand_type. */
754 #define OTNumOfUints \
755 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
756 #define OTNumOfBits \
757 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
759 /* If you get a compiler error for zero width of the unused field,
761 #define OTUnused (OTMax + 1)
763 typedef union i386_operand_type
768 unsigned int reg16
:1;
769 unsigned int reg32
:1;
770 unsigned int reg64
:1;
771 unsigned int floatreg
:1;
772 unsigned int regmmx
:1;
773 unsigned int regxmm
:1;
774 unsigned int regymm
:1;
775 unsigned int regzmm
:1;
776 unsigned int regmask
:1;
777 unsigned int control
:1;
778 unsigned int debug
:1;
780 unsigned int sreg2
:1;
781 unsigned int sreg3
:1;
784 unsigned int imm8s
:1;
785 unsigned int imm16
:1;
786 unsigned int imm32
:1;
787 unsigned int imm32s
:1;
788 unsigned int imm64
:1;
789 unsigned int disp8
:1;
790 unsigned int disp16
:1;
791 unsigned int disp32
:1;
792 unsigned int disp32s
:1;
793 unsigned int disp64
:1;
795 unsigned int floatacc
:1;
796 unsigned int baseindex
:1;
797 unsigned int inoutportreg
:1;
798 unsigned int shiftcount
:1;
799 unsigned int jumpabsolute
:1;
800 unsigned int esseg
:1;
801 unsigned int regmem
:1;
805 unsigned int dword
:1;
806 unsigned int fword
:1;
807 unsigned int qword
:1;
808 unsigned int tbyte
:1;
809 unsigned int xmmword
:1;
810 unsigned int ymmword
:1;
811 unsigned int zmmword
:1;
812 unsigned int unspecified
:1;
813 unsigned int anysize
:1;
814 unsigned int vec_imm4
:1;
815 unsigned int regbnd
:1;
816 unsigned int vec_disp8
:1;
818 unsigned int unused
:(OTNumOfBits
- OTUnused
);
821 unsigned int array
[OTNumOfUints
];
824 typedef struct insn_template
826 /* instruction name sans width suffix ("mov" for movl insns) */
829 /* how many operands */
830 unsigned int operands
;
832 /* base_opcode is the fundamental opcode byte without optional
834 unsigned int base_opcode
;
835 #define Opcode_D 0x2 /* Direction bit:
836 set if Reg --> Regmem;
837 unset if Regmem --> Reg. */
838 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
839 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
841 /* extension_opcode is the 3 bit extension for group <n> insns.
842 This field is also used to store the 8-bit opcode suffix for the
843 AMD 3DNow! instructions.
844 If this template has no extension opcode (the usual case) use None
846 unsigned int extension_opcode
;
847 #define None 0xffff /* If no extension_opcode is possible. */
850 unsigned char opcode_length
;
852 /* cpu feature flags */
853 i386_cpu_flags cpu_flags
;
855 /* the bits in opcode_modifier are used to generate the final opcode from
856 the base_opcode. These bits also are used to detect alternate forms of
857 the same instruction */
858 i386_opcode_modifier opcode_modifier
;
860 /* operand_types[i] describes the type of operand i. This is made
861 by OR'ing together all of the possible type masks. (e.g.
862 'operand_types[i] = Reg|Imm' specifies that operand i can be
863 either a register or an immediate operand. */
864 i386_operand_type operand_types
[MAX_OPERANDS
];
868 extern const insn_template i386_optab
[];
870 /* these are for register name --> number & type hash lookup */
874 i386_operand_type reg_type
;
875 unsigned char reg_flags
;
876 #define RegRex 0x1 /* Extended register. */
877 #define RegRex64 0x2 /* Extended 8 bit register. */
878 #define RegVRex 0x4 /* Extended vector register. */
879 unsigned char reg_num
;
880 #define RegRip ((unsigned char ) ~0)
881 #define RegEip (RegRip - 1)
882 /* EIZ and RIZ are fake index registers. */
883 #define RegEiz (RegEip - 1)
884 #define RegRiz (RegEiz - 1)
885 /* FLAT is a fake segment register (Intel mode). */
886 #define RegFlat ((unsigned char) ~0)
887 signed char dw2_regnum
[2];
888 #define Dw2Inval (-1)
892 /* Entries in i386_regtab. */
895 #define REGNAM_EAX 41
897 extern const reg_entry i386_regtab
[];
898 extern const unsigned int i386_regtab_size
;
903 unsigned int seg_prefix
;
907 extern const seg_entry cs
;
908 extern const seg_entry ds
;
909 extern const seg_entry ss
;
910 extern const seg_entry es
;
911 extern const seg_entry fs
;
912 extern const seg_entry gs
;