opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* mwaitx instruction required */
 202   CpuMWAITX,
 203   /* Clzero instruction required */
 204   CpuCLZERO,
 205   /* OSPKE instruction required */
 206   CpuOSPKE,
 207   /* RDPID instruction required */
 208   CpuRDPID,
 209   /* PTWRITE instruction required */
 210   CpuPTWRITE,
 211   /* CET instruction support required */
 212   CpuCET,
 213   /* MMX register support required */
 214   CpuRegMMX,
 215   /* XMM register support required */
 216   CpuRegXMM,
 217   /* YMM register support required */
 218   CpuRegYMM,
 219   /* ZMM register support required */
 220   CpuRegZMM,
 221   /* Mask register support required */
 222   CpuRegMask,
 223   /* 64bit support required  */
 224   Cpu64,
 225   /* Not supported in the 64bit mode  */
 226   CpuNo64,
 227   /* The last bitfield in i386_cpu_flags.  */
 228   CpuMax = CpuNo64
 229 };
 230
 231 #define CpuNumOfUints \
 232   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 233 #define CpuNumOfBits \
 234   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 235
 236 /* If you get a compiler error for zero width of the unused field,
 237    comment it out.  */
 238 #if 0
 239 #define CpuUnused       (CpuMax + 1)
 240 #endif
 241
 242 /* We can check if an instruction is available with array instead
 243    of bitfield. */
 244 typedef union i386_cpu_flags
 245 {
 246   struct
 247     {
 248       unsigned int cpui186:1;
 249       unsigned int cpui286:1;
 250       unsigned int cpui386:1;
 251       unsigned int cpui486:1;
 252       unsigned int cpui586:1;
 253       unsigned int cpui686:1;
 254       unsigned int cpuclflush:1;
 255       unsigned int cpunop:1;
 256       unsigned int cpusyscall:1;
 257       unsigned int cpu8087:1;
 258       unsigned int cpu287:1;
 259       unsigned int cpu387:1;
 260       unsigned int cpu687:1;
 261       unsigned int cpufisttp:1;
 262       unsigned int cpummx:1;
 263       unsigned int cpusse:1;
 264       unsigned int cpusse2:1;
 265       unsigned int cpua3dnow:1;
 266       unsigned int cpua3dnowa:1;
 267       unsigned int cpusse3:1;
 268       unsigned int cpupadlock:1;
 269       unsigned int cpusvme:1;
 270       unsigned int cpuvmx:1;
 271       unsigned int cpusmx:1;
 272       unsigned int cpussse3:1;
 273       unsigned int cpusse4a:1;
 274       unsigned int cpuabm:1;
 275       unsigned int cpusse4_1:1;
 276       unsigned int cpusse4_2:1;
 277       unsigned int cpuavx:1;
 278       unsigned int cpuavx2:1;
 279       unsigned int cpuavx512f:1;
 280       unsigned int cpuavx512cd:1;
 281       unsigned int cpuavx512er:1;
 282       unsigned int cpuavx512pf:1;
 283       unsigned int cpuavx512vl:1;
 284       unsigned int cpuavx512dq:1;
 285       unsigned int cpuavx512bw:1;
 286       unsigned int cpul1om:1;
 287       unsigned int cpuk1om:1;
 288       unsigned int cpuiamcu:1;
 289       unsigned int cpuxsave:1;
 290       unsigned int cpuxsaveopt:1;
 291       unsigned int cpuaes:1;
 292       unsigned int cpupclmul:1;
 293       unsigned int cpufma:1;
 294       unsigned int cpufma4:1;
 295       unsigned int cpuxop:1;
 296       unsigned int cpulwp:1;
 297       unsigned int cpubmi:1;
 298       unsigned int cputbm:1;
 299       unsigned int cpumovbe:1;
 300       unsigned int cpucx16:1;
 301       unsigned int cpuept:1;
 302       unsigned int cpurdtscp:1;
 303       unsigned int cpufsgsbase:1;
 304       unsigned int cpurdrnd:1;
 305       unsigned int cpuf16c:1;
 306       unsigned int cpubmi2:1;
 307       unsigned int cpulzcnt:1;
 308       unsigned int cpuhle:1;
 309       unsigned int cpurtm:1;
 310       unsigned int cpuinvpcid:1;
 311       unsigned int cpuvmfunc:1;
 312       unsigned int cpumpx:1;
 313       unsigned int cpulm:1;
 314       unsigned int cpurdseed:1;
 315       unsigned int cpuadx:1;
 316       unsigned int cpuprfchw:1;
 317       unsigned int cpusmap:1;
 318       unsigned int cpusha:1;
 319       unsigned int cpuvrex:1;
 320       unsigned int cpuclflushopt:1;
 321       unsigned int cpuxsaves:1;
 322       unsigned int cpuxsavec:1;
 323       unsigned int cpuprefetchwt1:1;
 324       unsigned int cpuse1:1;
 325       unsigned int cpuclwb:1;
 326       unsigned int cpuavx512ifma:1;
 327       unsigned int cpuavx512vbmi:1;
 328       unsigned int cpuavx512_4fmaps:1;
 329       unsigned int cpuavx512_4vnniw:1;
 330       unsigned int cpuavx512_vpopcntdq:1;
 331       unsigned int cpumwaitx:1;
 332       unsigned int cpuclzero:1;
 333       unsigned int cpuospke:1;
 334       unsigned int cpurdpid:1;
 335       unsigned int cpuptwrite:1;
 336       unsigned int cpucet:1;
 337       unsigned int cpuregmmx:1;
 338       unsigned int cpuregxmm:1;
 339       unsigned int cpuregymm:1;
 340       unsigned int cpuregzmm:1;
 341       unsigned int cpuregmask:1;
 342       unsigned int cpu64:1;
 343       unsigned int cpuno64:1;
 344 #ifdef CpuUnused
 345       unsigned int unused:(CpuNumOfBits - CpuUnused);
 346 #endif
 347     } bitfield;
 348   unsigned int array[CpuNumOfUints];
 349 } i386_cpu_flags;
 350
 351 /* Position of opcode_modifier bits.  */
 352
 353 enum
 354 {
 355   /* has direction bit. */
 356   D = 0,
 357   /* set if operands can be words or dwords encoded the canonical way */
 358   W,
 359   /* load form instruction. Must be placed before store form.  */
 360   Load,
 361   /* insn has a modrm byte. */
 362   Modrm,
 363   /* register is in low 3 bits of opcode */
 364   ShortForm,
 365   /* special case for jump insns.  */
 366   Jump,
 367   /* call and jump */
 368   JumpDword,
 369   /* loop and jecxz */
 370   JumpByte,
 371   /* special case for intersegment leaps/calls */
 372   JumpInterSegment,
 373   /* FP insn memory format bit, sized by 0x4 */
 374   FloatMF,
 375   /* src/dest swap for floats. */
 376   FloatR,
 377   /* has float insn direction bit. */
 378   FloatD,
 379   /* needs size prefix if in 32-bit mode */
 380   Size16,
 381   /* needs size prefix if in 16-bit mode */
 382   Size32,
 383   /* needs size prefix if in 64-bit mode */
 384   Size64,
 385   /* check register size.  */
 386   CheckRegSize,
 387   /* instruction ignores operand size prefix and in Intel mode ignores
 388      mnemonic size suffix check.  */
 389   IgnoreSize,
 390   /* default insn size depends on mode */
 391   DefaultSize,
 392   /* b suffix on instruction illegal */
 393   No_bSuf,
 394   /* w suffix on instruction illegal */
 395   No_wSuf,
 396   /* l suffix on instruction illegal */
 397   No_lSuf,
 398   /* s suffix on instruction illegal */
 399   No_sSuf,
 400   /* q suffix on instruction illegal */
 401   No_qSuf,
 402   /* long double suffix on instruction illegal */
 403   No_ldSuf,
 404   /* instruction needs FWAIT */
 405   FWait,
 406   /* quick test for string instructions */
 407   IsString,
 408   /* quick test if branch instruction is MPX supported */
 409   BNDPrefixOk,
 410   /* quick test if NOTRACK prefix is supported */
 411   NoTrackPrefixOk,
 412   /* quick test for lockable instructions */
 413   IsLockable,
 414   /* fake an extra reg operand for clr, imul and special register
 415      processing for some instructions.  */
 416   RegKludge,
 417   /* The first operand must be xmm0 */
 418   FirstXmm0,
 419   /* An implicit xmm0 as the first operand */
 420   Implicit1stXmm0,
 421   /* The HLE prefix is OK:
 422      1. With a LOCK prefix.
 423      2. With or without a LOCK prefix.
 424      3. With a RELEASE (0xf3) prefix.
 425    */
 426 #define HLEPrefixNone           0
 427 #define HLEPrefixLock           1
 428 #define HLEPrefixAny            2
 429 #define HLEPrefixRelease        3
 430   HLEPrefixOk,
 431   /* An instruction on which a "rep" prefix is acceptable.  */
 432   RepPrefixOk,
 433   /* Convert to DWORD */
 434   ToDword,
 435   /* Convert to QWORD */
 436   ToQword,
 437   /* Address prefix changes operand 0 */
 438   AddrPrefixOp0,
 439   /* opcode is a prefix */
 440   IsPrefix,
 441   /* instruction has extension in 8 bit imm */
 442   ImmExt,
 443   /* instruction don't need Rex64 prefix.  */
 444   NoRex64,
 445   /* instruction require Rex64 prefix.  */
 446   Rex64,
 447   /* deprecated fp insn, gets a warning */
 448   Ugh,
 449   /* insn has VEX prefix:
 450         1: 128bit VEX prefix.
 451         2: 256bit VEX prefix.
 452         3: Scalar VEX prefix.
 453    */
 454 #define VEX128          1
 455 #define VEX256          2
 456 #define VEXScalar       3
 457   Vex,
 458   /* How to encode VEX.vvvv:
 459      0: VEX.vvvv must be 1111b.
 460      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 461         the content of source registers will be preserved.
 462         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 463         where the content of first source register will be overwritten
 464         by the result.
 465         VEX.NDD2.  The second destination register operand is encoded in
 466         VEX.vvvv for instructions with 2 destination register operands.
 467         For assembler, there are no difference between VEX.NDS, VEX.DDS
 468         and VEX.NDD2.
 469      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 470      instructions with 1 destination register operand.
 471      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 472         of the operands can access a memory location.
 473    */
 474 #define VEXXDS  1
 475 #define VEXNDD  2
 476 #define VEXLWP  3
 477   VexVVVV,
 478   /* How the VEX.W bit is used:
 479      0: Set by the REX.W bit.
 480      1: VEX.W0.  Should always be 0.
 481      2: VEX.W1.  Should always be 1.
 482    */
 483 #define VEXW0   1
 484 #define VEXW1   2
 485   VexW,
 486   /* VEX opcode prefix:
 487      0: VEX 0x0F opcode prefix.
 488      1: VEX 0x0F38 opcode prefix.
 489      2: VEX 0x0F3A opcode prefix
 490      3: XOP 0x08 opcode prefix.
 491      4: XOP 0x09 opcode prefix
 492      5: XOP 0x0A opcode prefix.
 493    */
 494 #define VEX0F           0
 495 #define VEX0F38         1
 496 #define VEX0F3A         2
 497 #define XOP08           3
 498 #define XOP09           4
 499 #define XOP0A           5
 500   VexOpcode,
 501   /* number of VEX source operands:
 502      0: <= 2 source operands.
 503      1: 2 XOP source operands.
 504      2: 3 source operands.
 505    */
 506 #define XOP2SOURCES     1
 507 #define VEX3SOURCES     2
 508   VexSources,
 509   /* instruction has VEX 8 bit imm */
 510   VexImmExt,
 511   /* Instruction with vector SIB byte:
 512         1: 128bit vector register.
 513         2: 256bit vector register.
 514         3: 512bit vector register.
 515    */
 516 #define VecSIB128       1
 517 #define VecSIB256       2
 518 #define VecSIB512       3
 519   VecSIB,
 520   /* SSE to AVX support required */
 521   SSE2AVX,
 522   /* No AVX equivalent */
 523   NoAVX,
 524
 525   /* insn has EVEX prefix:
 526         1: 512bit EVEX prefix.
 527         2: 128bit EVEX prefix.
 528         3: 256bit EVEX prefix.
 529         4: Length-ignored (LIG) EVEX prefix.
 530    */
 531 #define EVEX512                1
 532 #define EVEX128                2
 533 #define EVEX256                3
 534 #define EVEXLIG                4
 535   EVex,
 536
 537   /* AVX512 masking support:
 538         1: Zeroing-masking.
 539         2: Merging-masking.
 540         3: Both zeroing and merging masking.
 541    */
 542 #define ZEROING_MASKING 1
 543 #define MERGING_MASKING 2
 544 #define BOTH_MASKING    3
 545   Masking,
 546
 547   /* Input element size of vector insn:
 548         0: 32bit.
 549         1: 64bit.
 550    */
 551   VecESize,
 552
 553   /* Broadcast factor.
 554         0: No broadcast.
 555         1: 1to16 broadcast.
 556         2: 1to8 broadcast.
 557    */
 558 #define NO_BROADCAST    0
 559 #define BROADCAST_1TO16 1
 560 #define BROADCAST_1TO8  2
 561 #define BROADCAST_1TO4  3
 562 #define BROADCAST_1TO2  4
 563   Broadcast,
 564
 565   /* Static rounding control is supported.  */
 566   StaticRounding,
 567
 568   /* Supress All Exceptions is supported.  */
 569   SAE,
 570
 571   /* Copressed Disp8*N attribute.  */
 572   Disp8MemShift,
 573
 574   /* Default mask isn't allowed.  */
 575   NoDefMask,
 576
 577   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 578      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 579    */
 580   ImplicitQuadGroup,
 581
 582   /* Compatible with old (<= 2.8.1) versions of gcc  */
 583   OldGcc,
 584   /* AT&T mnemonic.  */
 585   ATTMnemonic,
 586   /* AT&T syntax.  */
 587   ATTSyntax,
 588   /* Intel syntax.  */
 589   IntelSyntax,
 590   /* AMD64.  */
 591   AMD64,
 592   /* Intel64.  */
 593   Intel64,
 594   /* The last bitfield in i386_opcode_modifier.  */
 595   Opcode_Modifier_Max
 596 };
 597
 598 typedef struct i386_opcode_modifier
 599 {
 600   unsigned int d:1;
 601   unsigned int w:1;
 602   unsigned int load:1;
 603   unsigned int modrm:1;
 604   unsigned int shortform:1;
 605   unsigned int jump:1;
 606   unsigned int jumpdword:1;
 607   unsigned int jumpbyte:1;
 608   unsigned int jumpintersegment:1;
 609   unsigned int floatmf:1;
 610   unsigned int floatr:1;
 611   unsigned int floatd:1;
 612   unsigned int size16:1;
 613   unsigned int size32:1;
 614   unsigned int size64:1;
 615   unsigned int checkregsize:1;
 616   unsigned int ignoresize:1;
 617   unsigned int defaultsize:1;
 618   unsigned int no_bsuf:1;
 619   unsigned int no_wsuf:1;
 620   unsigned int no_lsuf:1;
 621   unsigned int no_ssuf:1;
 622   unsigned int no_qsuf:1;
 623   unsigned int no_ldsuf:1;
 624   unsigned int fwait:1;
 625   unsigned int isstring:1;
 626   unsigned int bndprefixok:1;
 627   unsigned int notrackprefixok:1;
 628   unsigned int islockable:1;
 629   unsigned int regkludge:1;
 630   unsigned int firstxmm0:1;
 631   unsigned int implicit1stxmm0:1;
 632   unsigned int hleprefixok:2;
 633   unsigned int repprefixok:1;
 634   unsigned int todword:1;
 635   unsigned int toqword:1;
 636   unsigned int addrprefixop0:1;
 637   unsigned int isprefix:1;
 638   unsigned int immext:1;
 639   unsigned int norex64:1;
 640   unsigned int rex64:1;
 641   unsigned int ugh:1;
 642   unsigned int vex:2;
 643   unsigned int vexvvvv:2;
 644   unsigned int vexw:2;
 645   unsigned int vexopcode:3;
 646   unsigned int vexsources:2;
 647   unsigned int veximmext:1;
 648   unsigned int vecsib:2;
 649   unsigned int sse2avx:1;
 650   unsigned int noavx:1;
 651   unsigned int evex:3;
 652   unsigned int masking:2;
 653   unsigned int vecesize:1;
 654   unsigned int broadcast:3;
 655   unsigned int staticrounding:1;
 656   unsigned int sae:1;
 657   unsigned int disp8memshift:3;
 658   unsigned int nodefmask:1;
 659   unsigned int implicitquadgroup:1;
 660   unsigned int oldgcc:1;
 661   unsigned int attmnemonic:1;
 662   unsigned int attsyntax:1;
 663   unsigned int intelsyntax:1;
 664   unsigned int amd64:1;
 665   unsigned int intel64:1;
 666 } i386_opcode_modifier;
 667
 668 /* Position of operand_type bits.  */
 669
 670 enum
 671 {
 672   /* 8bit register */
 673   Reg8 = 0,
 674   /* 16bit register */
 675   Reg16,
 676   /* 32bit register */
 677   Reg32,
 678   /* 64bit register */
 679   Reg64,
 680   /* Floating pointer stack register */
 681   FloatReg,
 682   /* MMX register */
 683   RegMMX,
 684   /* SSE register */
 685   RegXMM,
 686   /* AVX registers */
 687   RegYMM,
 688   /* AVX512 registers */
 689   RegZMM,
 690   /* Vector Mask registers */
 691   RegMask,
 692   /* Control register */
 693   Control,
 694   /* Debug register */
 695   Debug,
 696   /* Test register */
 697   Test,
 698   /* 2 bit segment register */
 699   SReg2,
 700   /* 3 bit segment register */
 701   SReg3,
 702   /* 1 bit immediate */
 703   Imm1,
 704   /* 8 bit immediate */
 705   Imm8,
 706   /* 8 bit immediate sign extended */
 707   Imm8S,
 708   /* 16 bit immediate */
 709   Imm16,
 710   /* 32 bit immediate */
 711   Imm32,
 712   /* 32 bit immediate sign extended */
 713   Imm32S,
 714   /* 64 bit immediate */
 715   Imm64,
 716   /* 8bit/16bit/32bit displacements are used in different ways,
 717      depending on the instruction.  For jumps, they specify the
 718      size of the PC relative displacement, for instructions with
 719      memory operand, they specify the size of the offset relative
 720      to the base register, and for instructions with memory offset
 721      such as `mov 1234,%al' they specify the size of the offset
 722      relative to the segment base.  */
 723   /* 8 bit displacement */
 724   Disp8,
 725   /* 16 bit displacement */
 726   Disp16,
 727   /* 32 bit displacement */
 728   Disp32,
 729   /* 32 bit signed displacement */
 730   Disp32S,
 731   /* 64 bit displacement */
 732   Disp64,
 733   /* Accumulator %al/%ax/%eax/%rax */
 734   Acc,
 735   /* Floating pointer top stack register %st(0) */
 736   FloatAcc,
 737   /* Register which can be used for base or index in memory operand.  */
 738   BaseIndex,
 739   /* Register to hold in/out port addr = dx */
 740   InOutPortReg,
 741   /* Register to hold shift count = cl */
 742   ShiftCount,
 743   /* Absolute address for jump.  */
 744   JumpAbsolute,
 745   /* String insn operand with fixed es segment */
 746   EsSeg,
 747   /* RegMem is for instructions with a modrm byte where the register
 748      destination operand should be encoded in the mod and regmem fields.
 749      Normally, it will be encoded in the reg field. We add a RegMem
 750      flag to the destination register operand to indicate that it should
 751      be encoded in the regmem field.  */
 752   RegMem,
 753   /* Memory.  */
 754   Mem,
 755   /* BYTE memory. */
 756   Byte,
 757   /* WORD memory. 2 byte */
 758   Word,
 759   /* DWORD memory. 4 byte */
 760   Dword,
 761   /* FWORD memory. 6 byte */
 762   Fword,
 763   /* QWORD memory. 8 byte */
 764   Qword,
 765   /* TBYTE memory. 10 byte */
 766   Tbyte,
 767   /* XMMWORD memory. */
 768   Xmmword,
 769   /* YMMWORD memory. */
 770   Ymmword,
 771   /* ZMMWORD memory.  */
 772   Zmmword,
 773   /* Unspecified memory size.  */
 774   Unspecified,
 775   /* Any memory size.  */
 776   Anysize,
 777
 778   /* Vector 4 bit immediate.  */
 779   Vec_Imm4,
 780
 781   /* Bound register.  */
 782   RegBND,
 783
 784   /* Vector 8bit displacement */
 785   Vec_Disp8,
 786
 787   /* The last bitfield in i386_operand_type.  */
 788   OTMax
 789 };
 790
 791 #define OTNumOfUints \
 792   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 793 #define OTNumOfBits \
 794   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 795
 796 /* If you get a compiler error for zero width of the unused field,
 797    comment it out.  */
 798 #define OTUnused                (OTMax + 1)
 799
 800 typedef union i386_operand_type
 801 {
 802   struct
 803     {
 804       unsigned int reg8:1;
 805       unsigned int reg16:1;
 806       unsigned int reg32:1;
 807       unsigned int reg64:1;
 808       unsigned int floatreg:1;
 809       unsigned int regmmx:1;
 810       unsigned int regxmm:1;
 811       unsigned int regymm:1;
 812       unsigned int regzmm:1;
 813       unsigned int regmask:1;
 814       unsigned int control:1;
 815       unsigned int debug:1;
 816       unsigned int test:1;
 817       unsigned int sreg2:1;
 818       unsigned int sreg3:1;
 819       unsigned int imm1:1;
 820       unsigned int imm8:1;
 821       unsigned int imm8s:1;
 822       unsigned int imm16:1;
 823       unsigned int imm32:1;
 824       unsigned int imm32s:1;
 825       unsigned int imm64:1;
 826       unsigned int disp8:1;
 827       unsigned int disp16:1;
 828       unsigned int disp32:1;
 829       unsigned int disp32s:1;
 830       unsigned int disp64:1;
 831       unsigned int acc:1;
 832       unsigned int floatacc:1;
 833       unsigned int baseindex:1;
 834       unsigned int inoutportreg:1;
 835       unsigned int shiftcount:1;
 836       unsigned int jumpabsolute:1;
 837       unsigned int esseg:1;
 838       unsigned int regmem:1;
 839       unsigned int mem:1;
 840       unsigned int byte:1;
 841       unsigned int word:1;
 842       unsigned int dword:1;
 843       unsigned int fword:1;
 844       unsigned int qword:1;
 845       unsigned int tbyte:1;
 846       unsigned int xmmword:1;
 847       unsigned int ymmword:1;
 848       unsigned int zmmword:1;
 849       unsigned int unspecified:1;
 850       unsigned int anysize:1;
 851       unsigned int vec_imm4:1;
 852       unsigned int regbnd:1;
 853       unsigned int vec_disp8:1;
 854 #ifdef OTUnused
 855       unsigned int unused:(OTNumOfBits - OTUnused);
 856 #endif
 857     } bitfield;
 858   unsigned int array[OTNumOfUints];
 859 } i386_operand_type;
 860
 861 typedef struct insn_template
 862 {
 863   /* instruction name sans width suffix ("mov" for movl insns) */
 864   char *name;
 865
 866   /* how many operands */
 867   unsigned int operands;
 868
 869   /* base_opcode is the fundamental opcode byte without optional
 870      prefix(es).  */
 871   unsigned int base_opcode;
 872 #define Opcode_D        0x2 /* Direction bit:
 873                                set if Reg --> Regmem;
 874                                unset if Regmem --> Reg. */
 875 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 876 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 877
 878   /* extension_opcode is the 3 bit extension for group <n> insns.
 879      This field is also used to store the 8-bit opcode suffix for the
 880      AMD 3DNow! instructions.
 881      If this template has no extension opcode (the usual case) use None
 882      Instructions */
 883   unsigned int extension_opcode;
 884 #define None 0xffff             /* If no extension_opcode is possible.  */
 885
 886   /* Opcode length.  */
 887   unsigned char opcode_length;
 888
 889   /* cpu feature flags */
 890   i386_cpu_flags cpu_flags;
 891
 892   /* the bits in opcode_modifier are used to generate the final opcode from
 893      the base_opcode.  These bits also are used to detect alternate forms of
 894      the same instruction */
 895   i386_opcode_modifier opcode_modifier;
 896
 897   /* operand_types[i] describes the type of operand i.  This is made
 898      by OR'ing together all of the possible type masks.  (e.g.
 899      'operand_types[i] = Reg|Imm' specifies that operand i can be
 900      either a register or an immediate operand.  */
 901   i386_operand_type operand_types[MAX_OPERANDS];
 902 }
 903 insn_template;
 904
 905 extern const insn_template i386_optab[];
 906
 907 /* these are for register name --> number & type hash lookup */
 908 typedef struct
 909 {
 910   char *reg_name;
 911   i386_operand_type reg_type;
 912   unsigned char reg_flags;
 913 #define RegRex      0x1  /* Extended register.  */
 914 #define RegRex64    0x2  /* Extended 8 bit register.  */
 915 #define RegVRex     0x4  /* Extended vector register.  */
 916   unsigned char reg_num;
 917 #define RegRip  ((unsigned char ) ~0)
 918 #define RegEip  (RegRip - 1)
 919 /* EIZ and RIZ are fake index registers.  */
 920 #define RegEiz  (RegEip - 1)
 921 #define RegRiz  (RegEiz - 1)
 922 /* FLAT is a fake segment register (Intel mode).  */
 923 #define RegFlat     ((unsigned char) ~0)
 924   signed char dw2_regnum[2];
 925 #define Dw2Inval (-1)
 926 }
 927 reg_entry;
 928
 929 /* Entries in i386_regtab.  */
 930 #define REGNAM_AL 1
 931 #define REGNAM_AX 25
 932 #define REGNAM_EAX 41
 933
 934 extern const reg_entry i386_regtab[];
 935 extern const unsigned int i386_regtab_size;
 936
 937 typedef struct
 938 {
 939   char *seg_name;
 940   unsigned int seg_prefix;
 941 }
 942 seg_entry;
 943
 944 extern const seg_entry cs;
 945 extern const seg_entry ds;
 946 extern const seg_entry ss;
 947 extern const seg_entry es;
 948 extern const seg_entry fs;
 949 extern const seg_entry gs;