opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel L1OM support required */
 106   CpuL1OM,
 107   /* Intel K1OM support required */
 108   CpuK1OM,
 109   /* Xsave/xrstor New Instructions support required */
 110   CpuXsave,
 111   /* Xsaveopt New Instructions support required */
 112   CpuXsaveopt,
 113   /* AES support required */
 114   CpuAES,
 115   /* PCLMUL support required */
 116   CpuPCLMUL,
 117   /* FMA support required */
 118   CpuFMA,
 119   /* FMA4 support required */
 120   CpuFMA4,
 121   /* XOP support required */
 122   CpuXOP,
 123   /* LWP support required */
 124   CpuLWP,
 125   /* BMI support required */
 126   CpuBMI,
 127   /* TBM support required */
 128   CpuTBM,
 129   /* MOVBE Instruction support required */
 130   CpuMovbe,
 131   /* CMPXCHG16B instruction support required.  */
 132   CpuCX16,
 133   /* EPT Instructions required */
 134   CpuEPT,
 135   /* RDTSCP Instruction support required */
 136   CpuRdtscp,
 137   /* FSGSBASE Instructions required */
 138   CpuFSGSBase,
 139   /* RDRND Instructions required */
 140   CpuRdRnd,
 141   /* F16C Instructions required */
 142   CpuF16C,
 143   /* Intel BMI2 support required */
 144   CpuBMI2,
 145   /* LZCNT support required */
 146   CpuLZCNT,
 147   /* HLE support required */
 148   CpuHLE,
 149   /* RTM support required */
 150   CpuRTM,
 151   /* INVPCID Instructions required */
 152   CpuINVPCID,
 153   /* VMFUNC Instruction required */
 154   CpuVMFUNC,
 155   /* Intel MPX Instructions required  */
 156   CpuMPX,
 157   /* 64bit support available, used by -march= in assembler.  */
 158   CpuLM,
 159   /* RDRSEED instruction required.  */
 160   CpuRDSEED,
 161   /* Multi-presisionn add-carry instructions are required.  */
 162   CpuADX,
 163   /* Supports prefetchw and prefetch instructions.  */
 164   CpuPRFCHW,
 165   /* SMAP instructions required.  */
 166   CpuSMAP,
 167   /* SHA instructions required.  */
 168   CpuSHA,
 169   /* VREX support required  */
 170   CpuVREX,
 171   /* CLFLUSHOPT instruction required */
 172   CpuClflushOpt,
 173   /* XSAVES/XRSTORS instruction required */
 174   CpuXSAVES,
 175   /* XSAVEC instruction required */
 176   CpuXSAVEC,
 177   /* PREFETCHWT1 instruction required */
 178   CpuPREFETCHWT1,
 179   /* SE1 instruction required */
 180   CpuSE1,
 181   /* 64bit support required  */
 182   Cpu64,
 183   /* Not supported in the 64bit mode  */
 184   CpuNo64,
 185   /* The last bitfield in i386_cpu_flags.  */
 186   CpuMax = CpuNo64
 187 };
 188
 189 #define CpuNumOfUints \
 190   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 191 #define CpuNumOfBits \
 192   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 193
 194 /* If you get a compiler error for zero width of the unused field,
 195    comment it out.  */
 196 #define CpuUnused       (CpuMax + 1)
 197
 198 /* We can check if an instruction is available with array instead
 199    of bitfield. */
 200 typedef union i386_cpu_flags
 201 {
 202   struct
 203     {
 204       unsigned int cpui186:1;
 205       unsigned int cpui286:1;
 206       unsigned int cpui386:1;
 207       unsigned int cpui486:1;
 208       unsigned int cpui586:1;
 209       unsigned int cpui686:1;
 210       unsigned int cpuclflush:1;
 211       unsigned int cpunop:1;
 212       unsigned int cpusyscall:1;
 213       unsigned int cpu8087:1;
 214       unsigned int cpu287:1;
 215       unsigned int cpu387:1;
 216       unsigned int cpu687:1;
 217       unsigned int cpufisttp:1;
 218       unsigned int cpummx:1;
 219       unsigned int cpusse:1;
 220       unsigned int cpusse2:1;
 221       unsigned int cpua3dnow:1;
 222       unsigned int cpua3dnowa:1;
 223       unsigned int cpusse3:1;
 224       unsigned int cpupadlock:1;
 225       unsigned int cpusvme:1;
 226       unsigned int cpuvmx:1;
 227       unsigned int cpusmx:1;
 228       unsigned int cpussse3:1;
 229       unsigned int cpusse4a:1;
 230       unsigned int cpuabm:1;
 231       unsigned int cpusse4_1:1;
 232       unsigned int cpusse4_2:1;
 233       unsigned int cpuavx:1;
 234       unsigned int cpuavx2:1;
 235       unsigned int cpuavx512f:1;
 236       unsigned int cpuavx512cd:1;
 237       unsigned int cpuavx512er:1;
 238       unsigned int cpuavx512pf:1;
 239       unsigned int cpul1om:1;
 240       unsigned int cpuk1om:1;
 241       unsigned int cpuxsave:1;
 242       unsigned int cpuxsaveopt:1;
 243       unsigned int cpuaes:1;
 244       unsigned int cpupclmul:1;
 245       unsigned int cpufma:1;
 246       unsigned int cpufma4:1;
 247       unsigned int cpuxop:1;
 248       unsigned int cpulwp:1;
 249       unsigned int cpubmi:1;
 250       unsigned int cputbm:1;
 251       unsigned int cpumovbe:1;
 252       unsigned int cpucx16:1;
 253       unsigned int cpuept:1;
 254       unsigned int cpurdtscp:1;
 255       unsigned int cpufsgsbase:1;
 256       unsigned int cpurdrnd:1;
 257       unsigned int cpuf16c:1;
 258       unsigned int cpubmi2:1;
 259       unsigned int cpulzcnt:1;
 260       unsigned int cpuhle:1;
 261       unsigned int cpurtm:1;
 262       unsigned int cpuinvpcid:1;
 263       unsigned int cpuvmfunc:1;
 264       unsigned int cpumpx:1;
 265       unsigned int cpulm:1;
 266       unsigned int cpurdseed:1;
 267       unsigned int cpuadx:1;
 268       unsigned int cpuprfchw:1;
 269       unsigned int cpusmap:1;
 270       unsigned int cpusha:1;
 271       unsigned int cpuvrex:1;
 272       unsigned int cpuclflushopt:1;
 273       unsigned int cpuxsaves:1;
 274       unsigned int cpuxsavec:1;
 275       unsigned int cpuprefetchwt1:1;
 276       unsigned int cpuse1:1;
 277       unsigned int cpu64:1;
 278       unsigned int cpuno64:1;
 279 #ifdef CpuUnused
 280       unsigned int unused:(CpuNumOfBits - CpuUnused);
 281 #endif
 282     } bitfield;
 283   unsigned int array[CpuNumOfUints];
 284 } i386_cpu_flags;
 285
 286 /* Position of opcode_modifier bits.  */
 287
 288 enum
 289 {
 290   /* has direction bit. */
 291   D = 0,
 292   /* set if operands can be words or dwords encoded the canonical way */
 293   W,
 294   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 295      operand in encoding.  */
 296   S,
 297   /* insn has a modrm byte. */
 298   Modrm,
 299   /* register is in low 3 bits of opcode */
 300   ShortForm,
 301   /* special case for jump insns.  */
 302   Jump,
 303   /* call and jump */
 304   JumpDword,
 305   /* loop and jecxz */
 306   JumpByte,
 307   /* special case for intersegment leaps/calls */
 308   JumpInterSegment,
 309   /* FP insn memory format bit, sized by 0x4 */
 310   FloatMF,
 311   /* src/dest swap for floats. */
 312   FloatR,
 313   /* has float insn direction bit. */
 314   FloatD,
 315   /* needs size prefix if in 32-bit mode */
 316   Size16,
 317   /* needs size prefix if in 16-bit mode */
 318   Size32,
 319   /* needs size prefix if in 64-bit mode */
 320   Size64,
 321   /* check register size.  */
 322   CheckRegSize,
 323   /* instruction ignores operand size prefix and in Intel mode ignores
 324      mnemonic size suffix check.  */
 325   IgnoreSize,
 326   /* default insn size depends on mode */
 327   DefaultSize,
 328   /* b suffix on instruction illegal */
 329   No_bSuf,
 330   /* w suffix on instruction illegal */
 331   No_wSuf,
 332   /* l suffix on instruction illegal */
 333   No_lSuf,
 334   /* s suffix on instruction illegal */
 335   No_sSuf,
 336   /* q suffix on instruction illegal */
 337   No_qSuf,
 338   /* long double suffix on instruction illegal */
 339   No_ldSuf,
 340   /* instruction needs FWAIT */
 341   FWait,
 342   /* quick test for string instructions */
 343   IsString,
 344   /* quick test if branch instruction is MPX supported */
 345   BNDPrefixOk,
 346   /* quick test for lockable instructions */
 347   IsLockable,
 348   /* fake an extra reg operand for clr, imul and special register
 349      processing for some instructions.  */
 350   RegKludge,
 351   /* The first operand must be xmm0 */
 352   FirstXmm0,
 353   /* An implicit xmm0 as the first operand */
 354   Implicit1stXmm0,
 355   /* The HLE prefix is OK:
 356      1. With a LOCK prefix.
 357      2. With or without a LOCK prefix.
 358      3. With a RELEASE (0xf3) prefix.
 359    */
 360 #define HLEPrefixNone           0
 361 #define HLEPrefixLock           1
 362 #define HLEPrefixAny            2
 363 #define HLEPrefixRelease        3
 364   HLEPrefixOk,
 365   /* An instruction on which a "rep" prefix is acceptable.  */
 366   RepPrefixOk,
 367   /* Convert to DWORD */
 368   ToDword,
 369   /* Convert to QWORD */
 370   ToQword,
 371   /* Address prefix changes operand 0 */
 372   AddrPrefixOp0,
 373   /* opcode is a prefix */
 374   IsPrefix,
 375   /* instruction has extension in 8 bit imm */
 376   ImmExt,
 377   /* instruction don't need Rex64 prefix.  */
 378   NoRex64,
 379   /* instruction require Rex64 prefix.  */
 380   Rex64,
 381   /* deprecated fp insn, gets a warning */
 382   Ugh,
 383   /* insn has VEX prefix:
 384         1: 128bit VEX prefix.
 385         2: 256bit VEX prefix.
 386         3: Scalar VEX prefix.
 387    */
 388 #define VEX128          1
 389 #define VEX256          2
 390 #define VEXScalar       3
 391   Vex,
 392   /* How to encode VEX.vvvv:
 393      0: VEX.vvvv must be 1111b.
 394      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 395         the content of source registers will be preserved.
 396         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 397         where the content of first source register will be overwritten
 398         by the result.
 399         VEX.NDD2.  The second destination register operand is encoded in
 400         VEX.vvvv for instructions with 2 destination register operands.
 401         For assembler, there are no difference between VEX.NDS, VEX.DDS
 402         and VEX.NDD2.
 403      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 404      instructions with 1 destination register operand.
 405      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 406         of the operands can access a memory location.
 407    */
 408 #define VEXXDS  1
 409 #define VEXNDD  2
 410 #define VEXLWP  3
 411   VexVVVV,
 412   /* How the VEX.W bit is used:
 413      0: Set by the REX.W bit.
 414      1: VEX.W0.  Should always be 0.
 415      2: VEX.W1.  Should always be 1.
 416    */
 417 #define VEXW0   1
 418 #define VEXW1   2
 419   VexW,
 420   /* VEX opcode prefix:
 421      0: VEX 0x0F opcode prefix.
 422      1: VEX 0x0F38 opcode prefix.
 423      2: VEX 0x0F3A opcode prefix
 424      3: XOP 0x08 opcode prefix.
 425      4: XOP 0x09 opcode prefix
 426      5: XOP 0x0A opcode prefix.
 427    */
 428 #define VEX0F           0
 429 #define VEX0F38         1
 430 #define VEX0F3A         2
 431 #define XOP08           3
 432 #define XOP09           4
 433 #define XOP0A           5
 434   VexOpcode,
 435   /* number of VEX source operands:
 436      0: <= 2 source operands.
 437      1: 2 XOP source operands.
 438      2: 3 source operands.
 439    */
 440 #define XOP2SOURCES     1
 441 #define VEX3SOURCES     2
 442   VexSources,
 443   /* instruction has VEX 8 bit imm */
 444   VexImmExt,
 445   /* Instruction with vector SIB byte:
 446         1: 128bit vector register.
 447         2: 256bit vector register.
 448         3: 512bit vector register.
 449    */
 450 #define VecSIB128       1
 451 #define VecSIB256       2
 452 #define VecSIB512       3
 453   VecSIB,
 454   /* SSE to AVX support required */
 455   SSE2AVX,
 456   /* No AVX equivalent */
 457   NoAVX,
 458
 459   /* insn has EVEX prefix:
 460         1: 512bit EVEX prefix.
 461         2: 128bit EVEX prefix.
 462         3: 256bit EVEX prefix.
 463         4: Length-ignored (LIG) EVEX prefix.
 464    */
 465 #define EVEX512                1
 466 #define EVEX128                2
 467 #define EVEX256                3
 468 #define EVEXLIG                4
 469   EVex,
 470
 471   /* AVX512 masking support:
 472         1: Zeroing-masking.
 473         2: Merging-masking.
 474         3: Both zeroing and merging masking.
 475    */
 476 #define ZEROING_MASKING 1
 477 #define MERGING_MASKING 2
 478 #define BOTH_MASKING    3
 479   Masking,
 480
 481   /* Input element size of vector insn:
 482         0: 32bit.
 483         1: 64bit.
 484    */
 485   VecESize,
 486
 487   /* Broadcast factor.
 488         0: No broadcast.
 489         1: 1to16 broadcast.
 490         2: 1to8 broadcast.
 491    */
 492 #define NO_BROADCAST    0
 493 #define BROADCAST_1TO16 1
 494 #define BROADCAST_1TO8  2
 495   Broadcast,
 496
 497   /* Static rounding control is supported.  */
 498   StaticRounding,
 499
 500   /* Supress All Exceptions is supported.  */
 501   SAE,
 502
 503   /* Copressed Disp8*N attribute.  */
 504   Disp8MemShift,
 505
 506   /* Default mask isn't allowed.  */
 507   NoDefMask,
 508
 509   /* Compatible with old (<= 2.8.1) versions of gcc  */
 510   OldGcc,
 511   /* AT&T mnemonic.  */
 512   ATTMnemonic,
 513   /* AT&T syntax.  */
 514   ATTSyntax,
 515   /* Intel syntax.  */
 516   IntelSyntax,
 517   /* The last bitfield in i386_opcode_modifier.  */
 518   Opcode_Modifier_Max
 519 };
 520
 521 typedef struct i386_opcode_modifier
 522 {
 523   unsigned int d:1;
 524   unsigned int w:1;
 525   unsigned int s:1;
 526   unsigned int modrm:1;
 527   unsigned int shortform:1;
 528   unsigned int jump:1;
 529   unsigned int jumpdword:1;
 530   unsigned int jumpbyte:1;
 531   unsigned int jumpintersegment:1;
 532   unsigned int floatmf:1;
 533   unsigned int floatr:1;
 534   unsigned int floatd:1;
 535   unsigned int size16:1;
 536   unsigned int size32:1;
 537   unsigned int size64:1;
 538   unsigned int checkregsize:1;
 539   unsigned int ignoresize:1;
 540   unsigned int defaultsize:1;
 541   unsigned int no_bsuf:1;
 542   unsigned int no_wsuf:1;
 543   unsigned int no_lsuf:1;
 544   unsigned int no_ssuf:1;
 545   unsigned int no_qsuf:1;
 546   unsigned int no_ldsuf:1;
 547   unsigned int fwait:1;
 548   unsigned int isstring:1;
 549   unsigned int bndprefixok:1;
 550   unsigned int islockable:1;
 551   unsigned int regkludge:1;
 552   unsigned int firstxmm0:1;
 553   unsigned int implicit1stxmm0:1;
 554   unsigned int hleprefixok:2;
 555   unsigned int repprefixok:1;
 556   unsigned int todword:1;
 557   unsigned int toqword:1;
 558   unsigned int addrprefixop0:1;
 559   unsigned int isprefix:1;
 560   unsigned int immext:1;
 561   unsigned int norex64:1;
 562   unsigned int rex64:1;
 563   unsigned int ugh:1;
 564   unsigned int vex:2;
 565   unsigned int vexvvvv:2;
 566   unsigned int vexw:2;
 567   unsigned int vexopcode:3;
 568   unsigned int vexsources:2;
 569   unsigned int veximmext:1;
 570   unsigned int vecsib:2;
 571   unsigned int sse2avx:1;
 572   unsigned int noavx:1;
 573   unsigned int evex:3;
 574   unsigned int masking:2;
 575   unsigned int vecesize:1;
 576   unsigned int broadcast:3;
 577   unsigned int staticrounding:1;
 578   unsigned int sae:1;
 579   unsigned int disp8memshift:3;
 580   unsigned int nodefmask:1;
 581   unsigned int oldgcc:1;
 582   unsigned int attmnemonic:1;
 583   unsigned int attsyntax:1;
 584   unsigned int intelsyntax:1;
 585 } i386_opcode_modifier;
 586
 587 /* Position of operand_type bits.  */
 588
 589 enum
 590 {
 591   /* 8bit register */
 592   Reg8 = 0,
 593   /* 16bit register */
 594   Reg16,
 595   /* 32bit register */
 596   Reg32,
 597   /* 64bit register */
 598   Reg64,
 599   /* Floating pointer stack register */
 600   FloatReg,
 601   /* MMX register */
 602   RegMMX,
 603   /* SSE register */
 604   RegXMM,
 605   /* AVX registers */
 606   RegYMM,
 607   /* AVX512 registers */
 608   RegZMM,
 609   /* Vector Mask registers */
 610   RegMask,
 611   /* Control register */
 612   Control,
 613   /* Debug register */
 614   Debug,
 615   /* Test register */
 616   Test,
 617   /* 2 bit segment register */
 618   SReg2,
 619   /* 3 bit segment register */
 620   SReg3,
 621   /* 1 bit immediate */
 622   Imm1,
 623   /* 8 bit immediate */
 624   Imm8,
 625   /* 8 bit immediate sign extended */
 626   Imm8S,
 627   /* 16 bit immediate */
 628   Imm16,
 629   /* 32 bit immediate */
 630   Imm32,
 631   /* 32 bit immediate sign extended */
 632   Imm32S,
 633   /* 64 bit immediate */
 634   Imm64,
 635   /* 8bit/16bit/32bit displacements are used in different ways,
 636      depending on the instruction.  For jumps, they specify the
 637      size of the PC relative displacement, for instructions with
 638      memory operand, they specify the size of the offset relative
 639      to the base register, and for instructions with memory offset
 640      such as `mov 1234,%al' they specify the size of the offset
 641      relative to the segment base.  */
 642   /* 8 bit displacement */
 643   Disp8,
 644   /* 16 bit displacement */
 645   Disp16,
 646   /* 32 bit displacement */
 647   Disp32,
 648   /* 32 bit signed displacement */
 649   Disp32S,
 650   /* 64 bit displacement */
 651   Disp64,
 652   /* Accumulator %al/%ax/%eax/%rax */
 653   Acc,
 654   /* Floating pointer top stack register %st(0) */
 655   FloatAcc,
 656   /* Register which can be used for base or index in memory operand.  */
 657   BaseIndex,
 658   /* Register to hold in/out port addr = dx */
 659   InOutPortReg,
 660   /* Register to hold shift count = cl */
 661   ShiftCount,
 662   /* Absolute address for jump.  */
 663   JumpAbsolute,
 664   /* String insn operand with fixed es segment */
 665   EsSeg,
 666   /* RegMem is for instructions with a modrm byte where the register
 667      destination operand should be encoded in the mod and regmem fields.
 668      Normally, it will be encoded in the reg field. We add a RegMem
 669      flag to the destination register operand to indicate that it should
 670      be encoded in the regmem field.  */
 671   RegMem,
 672   /* Memory.  */
 673   Mem,
 674   /* BYTE memory. */
 675   Byte,
 676   /* WORD memory. 2 byte */
 677   Word,
 678   /* DWORD memory. 4 byte */
 679   Dword,
 680   /* FWORD memory. 6 byte */
 681   Fword,
 682   /* QWORD memory. 8 byte */
 683   Qword,
 684   /* TBYTE memory. 10 byte */
 685   Tbyte,
 686   /* XMMWORD memory. */
 687   Xmmword,
 688   /* YMMWORD memory. */
 689   Ymmword,
 690   /* ZMMWORD memory.  */
 691   Zmmword,
 692   /* Unspecified memory size.  */
 693   Unspecified,
 694   /* Any memory size.  */
 695   Anysize,
 696
 697   /* Vector 4 bit immediate.  */
 698   Vec_Imm4,
 699
 700   /* Bound register.  */
 701   RegBND,
 702
 703   /* Vector 8bit displacement */
 704   Vec_Disp8,
 705
 706   /* The last bitfield in i386_operand_type.  */
 707   OTMax
 708 };
 709
 710 #define OTNumOfUints \
 711   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 712 #define OTNumOfBits \
 713   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 714
 715 /* If you get a compiler error for zero width of the unused field,
 716    comment it out.  */
 717 #define OTUnused                (OTMax + 1)
 718
 719 typedef union i386_operand_type
 720 {
 721   struct
 722     {
 723       unsigned int reg8:1;
 724       unsigned int reg16:1;
 725       unsigned int reg32:1;
 726       unsigned int reg64:1;
 727       unsigned int floatreg:1;
 728       unsigned int regmmx:1;
 729       unsigned int regxmm:1;
 730       unsigned int regymm:1;
 731       unsigned int regzmm:1;
 732       unsigned int regmask:1;
 733       unsigned int control:1;
 734       unsigned int debug:1;
 735       unsigned int test:1;
 736       unsigned int sreg2:1;
 737       unsigned int sreg3:1;
 738       unsigned int imm1:1;
 739       unsigned int imm8:1;
 740       unsigned int imm8s:1;
 741       unsigned int imm16:1;
 742       unsigned int imm32:1;
 743       unsigned int imm32s:1;
 744       unsigned int imm64:1;
 745       unsigned int disp8:1;
 746       unsigned int disp16:1;
 747       unsigned int disp32:1;
 748       unsigned int disp32s:1;
 749       unsigned int disp64:1;
 750       unsigned int acc:1;
 751       unsigned int floatacc:1;
 752       unsigned int baseindex:1;
 753       unsigned int inoutportreg:1;
 754       unsigned int shiftcount:1;
 755       unsigned int jumpabsolute:1;
 756       unsigned int esseg:1;
 757       unsigned int regmem:1;
 758       unsigned int mem:1;
 759       unsigned int byte:1;
 760       unsigned int word:1;
 761       unsigned int dword:1;
 762       unsigned int fword:1;
 763       unsigned int qword:1;
 764       unsigned int tbyte:1;
 765       unsigned int xmmword:1;
 766       unsigned int ymmword:1;
 767       unsigned int zmmword:1;
 768       unsigned int unspecified:1;
 769       unsigned int anysize:1;
 770       unsigned int vec_imm4:1;
 771       unsigned int regbnd:1;
 772       unsigned int vec_disp8:1;
 773 #ifdef OTUnused
 774       unsigned int unused:(OTNumOfBits - OTUnused);
 775 #endif
 776     } bitfield;
 777   unsigned int array[OTNumOfUints];
 778 } i386_operand_type;
 779
 780 typedef struct insn_template
 781 {
 782   /* instruction name sans width suffix ("mov" for movl insns) */
 783   char *name;
 784
 785   /* how many operands */
 786   unsigned int operands;
 787
 788   /* base_opcode is the fundamental opcode byte without optional
 789      prefix(es).  */
 790   unsigned int base_opcode;
 791 #define Opcode_D        0x2 /* Direction bit:
 792                                set if Reg --> Regmem;
 793                                unset if Regmem --> Reg. */
 794 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 795 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 796
 797   /* extension_opcode is the 3 bit extension for group <n> insns.
 798      This field is also used to store the 8-bit opcode suffix for the
 799      AMD 3DNow! instructions.
 800      If this template has no extension opcode (the usual case) use None
 801      Instructions */
 802   unsigned int extension_opcode;
 803 #define None 0xffff             /* If no extension_opcode is possible.  */
 804
 805   /* Opcode length.  */
 806   unsigned char opcode_length;
 807
 808   /* cpu feature flags */
 809   i386_cpu_flags cpu_flags;
 810
 811   /* the bits in opcode_modifier are used to generate the final opcode from
 812      the base_opcode.  These bits also are used to detect alternate forms of
 813      the same instruction */
 814   i386_opcode_modifier opcode_modifier;
 815
 816   /* operand_types[i] describes the type of operand i.  This is made
 817      by OR'ing together all of the possible type masks.  (e.g.
 818      'operand_types[i] = Reg|Imm' specifies that operand i can be
 819      either a register or an immediate operand.  */
 820   i386_operand_type operand_types[MAX_OPERANDS];
 821 }
 822 insn_template;
 823
 824 extern const insn_template i386_optab[];
 825
 826 /* these are for register name --> number & type hash lookup */
 827 typedef struct
 828 {
 829   char *reg_name;
 830   i386_operand_type reg_type;
 831   unsigned char reg_flags;
 832 #define RegRex      0x1  /* Extended register.  */
 833 #define RegRex64    0x2  /* Extended 8 bit register.  */
 834 #define RegVRex     0x4  /* Extended vector register.  */
 835   unsigned char reg_num;
 836 #define RegRip  ((unsigned char ) ~0)
 837 #define RegEip  (RegRip - 1)
 838 /* EIZ and RIZ are fake index registers.  */
 839 #define RegEiz  (RegEip - 1)
 840 #define RegRiz  (RegEiz - 1)
 841 /* FLAT is a fake segment register (Intel mode).  */
 842 #define RegFlat     ((unsigned char) ~0)
 843   signed char dw2_regnum[2];
 844 #define Dw2Inval (-1)
 845 }
 846 reg_entry;
 847
 848 /* Entries in i386_regtab.  */
 849 #define REGNAM_AL 1
 850 #define REGNAM_AX 25
 851 #define REGNAM_EAX 41
 852
 853 extern const reg_entry i386_regtab[];
 854 extern const unsigned int i386_regtab_size;
 855
 856 typedef struct
 857 {
 858   char *seg_name;
 859   unsigned int seg_prefix;
 860 }
 861 seg_entry;
 862
 863 extern const seg_entry cs;
 864 extern const seg_entry ds;
 865 extern const seg_entry ss;
 866 extern const seg_entry es;
 867 extern const seg_entry fs;
 868 extern const seg_entry gs;