opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* mwaitx instruction required */
 202   CpuMWAITX,
 203   /* Clzero instruction required */
 204   CpuCLZERO,
 205   /* OSPKE instruction required */
 206   CpuOSPKE,
 207   /* RDPID instruction required */
 208   CpuRDPID,
 209   /* PTWRITE instruction required */
 210   CpuPTWRITE,
 211   /* CET instruction support required */
 212   CpuCET,
 213   /* MMX register support required */
 214   CpuRegMMX,
 215   /* XMM register support required */
 216   CpuRegXMM,
 217   /* YMM register support required */
 218   CpuRegYMM,
 219   /* ZMM register support required */
 220   CpuRegZMM,
 221   /* Mask register support required */
 222   CpuRegMask,
 223   /* 64bit support required  */
 224   Cpu64,
 225   /* Not supported in the 64bit mode  */
 226   CpuNo64,
 227   /* The last bitfield in i386_cpu_flags.  */
 228   CpuMax = CpuNo64
 229 };
 230
 231 #define CpuNumOfUints \
 232   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 233 #define CpuNumOfBits \
 234   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 235
 236 /* If you get a compiler error for zero width of the unused field,
 237    comment it out.  */
 238 #if 0
 239 #define CpuUnused       (CpuMax + 1)
 240 #endif
 241
 242 /* We can check if an instruction is available with array instead
 243    of bitfield. */
 244 typedef union i386_cpu_flags
 245 {
 246   struct
 247     {
 248       unsigned int cpui186:1;
 249       unsigned int cpui286:1;
 250       unsigned int cpui386:1;
 251       unsigned int cpui486:1;
 252       unsigned int cpui586:1;
 253       unsigned int cpui686:1;
 254       unsigned int cpuclflush:1;
 255       unsigned int cpunop:1;
 256       unsigned int cpusyscall:1;
 257       unsigned int cpu8087:1;
 258       unsigned int cpu287:1;
 259       unsigned int cpu387:1;
 260       unsigned int cpu687:1;
 261       unsigned int cpufisttp:1;
 262       unsigned int cpummx:1;
 263       unsigned int cpusse:1;
 264       unsigned int cpusse2:1;
 265       unsigned int cpua3dnow:1;
 266       unsigned int cpua3dnowa:1;
 267       unsigned int cpusse3:1;
 268       unsigned int cpupadlock:1;
 269       unsigned int cpusvme:1;
 270       unsigned int cpuvmx:1;
 271       unsigned int cpusmx:1;
 272       unsigned int cpussse3:1;
 273       unsigned int cpusse4a:1;
 274       unsigned int cpuabm:1;
 275       unsigned int cpusse4_1:1;
 276       unsigned int cpusse4_2:1;
 277       unsigned int cpuavx:1;
 278       unsigned int cpuavx2:1;
 279       unsigned int cpuavx512f:1;
 280       unsigned int cpuavx512cd:1;
 281       unsigned int cpuavx512er:1;
 282       unsigned int cpuavx512pf:1;
 283       unsigned int cpuavx512vl:1;
 284       unsigned int cpuavx512dq:1;
 285       unsigned int cpuavx512bw:1;
 286       unsigned int cpul1om:1;
 287       unsigned int cpuk1om:1;
 288       unsigned int cpuiamcu:1;
 289       unsigned int cpuxsave:1;
 290       unsigned int cpuxsaveopt:1;
 291       unsigned int cpuaes:1;
 292       unsigned int cpupclmul:1;
 293       unsigned int cpufma:1;
 294       unsigned int cpufma4:1;
 295       unsigned int cpuxop:1;
 296       unsigned int cpulwp:1;
 297       unsigned int cpubmi:1;
 298       unsigned int cputbm:1;
 299       unsigned int cpumovbe:1;
 300       unsigned int cpucx16:1;
 301       unsigned int cpuept:1;
 302       unsigned int cpurdtscp:1;
 303       unsigned int cpufsgsbase:1;
 304       unsigned int cpurdrnd:1;
 305       unsigned int cpuf16c:1;
 306       unsigned int cpubmi2:1;
 307       unsigned int cpulzcnt:1;
 308       unsigned int cpuhle:1;
 309       unsigned int cpurtm:1;
 310       unsigned int cpuinvpcid:1;
 311       unsigned int cpuvmfunc:1;
 312       unsigned int cpumpx:1;
 313       unsigned int cpulm:1;
 314       unsigned int cpurdseed:1;
 315       unsigned int cpuadx:1;
 316       unsigned int cpuprfchw:1;
 317       unsigned int cpusmap:1;
 318       unsigned int cpusha:1;
 319       unsigned int cpuvrex:1;
 320       unsigned int cpuclflushopt:1;
 321       unsigned int cpuxsaves:1;
 322       unsigned int cpuxsavec:1;
 323       unsigned int cpuprefetchwt1:1;
 324       unsigned int cpuse1:1;
 325       unsigned int cpuclwb:1;
 326       unsigned int cpuavx512ifma:1;
 327       unsigned int cpuavx512vbmi:1;
 328       unsigned int cpuavx512_4fmaps:1;
 329       unsigned int cpuavx512_4vnniw:1;
 330       unsigned int cpuavx512_vpopcntdq:1;
 331       unsigned int cpumwaitx:1;
 332       unsigned int cpuclzero:1;
 333       unsigned int cpuospke:1;
 334       unsigned int cpurdpid:1;
 335       unsigned int cpuptwrite:1;
 336       unsigned int cpucet:1;
 337       unsigned int cpuregmmx:1;
 338       unsigned int cpuregxmm:1;
 339       unsigned int cpuregymm:1;
 340       unsigned int cpuregzmm:1;
 341       unsigned int cpuregmask:1;
 342       unsigned int cpu64:1;
 343       unsigned int cpuno64:1;
 344 #ifdef CpuUnused
 345       unsigned int unused:(CpuNumOfBits - CpuUnused);
 346 #endif
 347     } bitfield;
 348   unsigned int array[CpuNumOfUints];
 349 } i386_cpu_flags;
 350
 351 /* Position of opcode_modifier bits.  */
 352
 353 enum
 354 {
 355   /* has direction bit. */
 356   D = 0,
 357   /* set if operands can be words or dwords encoded the canonical way */
 358   W,
 359   /* load form instruction. Must be placed before store form.  */
 360   Load,
 361   /* insn has a modrm byte. */
 362   Modrm,
 363   /* register is in low 3 bits of opcode */
 364   ShortForm,
 365   /* special case for jump insns.  */
 366   Jump,
 367   /* call and jump */
 368   JumpDword,
 369   /* loop and jecxz */
 370   JumpByte,
 371   /* special case for intersegment leaps/calls */
 372   JumpInterSegment,
 373   /* FP insn memory format bit, sized by 0x4 */
 374   FloatMF,
 375   /* src/dest swap for floats. */
 376   FloatR,
 377   /* has float insn direction bit. */
 378   FloatD,
 379   /* needs size prefix if in 32-bit mode */
 380   Size16,
 381   /* needs size prefix if in 16-bit mode */
 382   Size32,
 383   /* needs size prefix if in 64-bit mode */
 384   Size64,
 385   /* check register size.  */
 386   CheckRegSize,
 387   /* instruction ignores operand size prefix and in Intel mode ignores
 388      mnemonic size suffix check.  */
 389   IgnoreSize,
 390   /* default insn size depends on mode */
 391   DefaultSize,
 392   /* b suffix on instruction illegal */
 393   No_bSuf,
 394   /* w suffix on instruction illegal */
 395   No_wSuf,
 396   /* l suffix on instruction illegal */
 397   No_lSuf,
 398   /* s suffix on instruction illegal */
 399   No_sSuf,
 400   /* q suffix on instruction illegal */
 401   No_qSuf,
 402   /* long double suffix on instruction illegal */
 403   No_ldSuf,
 404   /* instruction needs FWAIT */
 405   FWait,
 406   /* quick test for string instructions */
 407   IsString,
 408   /* quick test if branch instruction is MPX supported */
 409   BNDPrefixOk,
 410   /* quick test for lockable instructions */
 411   IsLockable,
 412   /* fake an extra reg operand for clr, imul and special register
 413      processing for some instructions.  */
 414   RegKludge,
 415   /* The first operand must be xmm0 */
 416   FirstXmm0,
 417   /* An implicit xmm0 as the first operand */
 418   Implicit1stXmm0,
 419   /* The HLE prefix is OK:
 420      1. With a LOCK prefix.
 421      2. With or without a LOCK prefix.
 422      3. With a RELEASE (0xf3) prefix.
 423    */
 424 #define HLEPrefixNone           0
 425 #define HLEPrefixLock           1
 426 #define HLEPrefixAny            2
 427 #define HLEPrefixRelease        3
 428   HLEPrefixOk,
 429   /* An instruction on which a "rep" prefix is acceptable.  */
 430   RepPrefixOk,
 431   /* Convert to DWORD */
 432   ToDword,
 433   /* Convert to QWORD */
 434   ToQword,
 435   /* Address prefix changes operand 0 */
 436   AddrPrefixOp0,
 437   /* opcode is a prefix */
 438   IsPrefix,
 439   /* instruction has extension in 8 bit imm */
 440   ImmExt,
 441   /* instruction don't need Rex64 prefix.  */
 442   NoRex64,
 443   /* instruction require Rex64 prefix.  */
 444   Rex64,
 445   /* deprecated fp insn, gets a warning */
 446   Ugh,
 447   /* insn has VEX prefix:
 448         1: 128bit VEX prefix.
 449         2: 256bit VEX prefix.
 450         3: Scalar VEX prefix.
 451    */
 452 #define VEX128          1
 453 #define VEX256          2
 454 #define VEXScalar       3
 455   Vex,
 456   /* How to encode VEX.vvvv:
 457      0: VEX.vvvv must be 1111b.
 458      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 459         the content of source registers will be preserved.
 460         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 461         where the content of first source register will be overwritten
 462         by the result.
 463         VEX.NDD2.  The second destination register operand is encoded in
 464         VEX.vvvv for instructions with 2 destination register operands.
 465         For assembler, there are no difference between VEX.NDS, VEX.DDS
 466         and VEX.NDD2.
 467      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 468      instructions with 1 destination register operand.
 469      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 470         of the operands can access a memory location.
 471    */
 472 #define VEXXDS  1
 473 #define VEXNDD  2
 474 #define VEXLWP  3
 475   VexVVVV,
 476   /* How the VEX.W bit is used:
 477      0: Set by the REX.W bit.
 478      1: VEX.W0.  Should always be 0.
 479      2: VEX.W1.  Should always be 1.
 480    */
 481 #define VEXW0   1
 482 #define VEXW1   2
 483   VexW,
 484   /* VEX opcode prefix:
 485      0: VEX 0x0F opcode prefix.
 486      1: VEX 0x0F38 opcode prefix.
 487      2: VEX 0x0F3A opcode prefix
 488      3: XOP 0x08 opcode prefix.
 489      4: XOP 0x09 opcode prefix
 490      5: XOP 0x0A opcode prefix.
 491    */
 492 #define VEX0F           0
 493 #define VEX0F38         1
 494 #define VEX0F3A         2
 495 #define XOP08           3
 496 #define XOP09           4
 497 #define XOP0A           5
 498   VexOpcode,
 499   /* number of VEX source operands:
 500      0: <= 2 source operands.
 501      1: 2 XOP source operands.
 502      2: 3 source operands.
 503    */
 504 #define XOP2SOURCES     1
 505 #define VEX3SOURCES     2
 506   VexSources,
 507   /* instruction has VEX 8 bit imm */
 508   VexImmExt,
 509   /* Instruction with vector SIB byte:
 510         1: 128bit vector register.
 511         2: 256bit vector register.
 512         3: 512bit vector register.
 513    */
 514 #define VecSIB128       1
 515 #define VecSIB256       2
 516 #define VecSIB512       3
 517   VecSIB,
 518   /* SSE to AVX support required */
 519   SSE2AVX,
 520   /* No AVX equivalent */
 521   NoAVX,
 522
 523   /* insn has EVEX prefix:
 524         1: 512bit EVEX prefix.
 525         2: 128bit EVEX prefix.
 526         3: 256bit EVEX prefix.
 527         4: Length-ignored (LIG) EVEX prefix.
 528    */
 529 #define EVEX512                1
 530 #define EVEX128                2
 531 #define EVEX256                3
 532 #define EVEXLIG                4
 533   EVex,
 534
 535   /* AVX512 masking support:
 536         1: Zeroing-masking.
 537         2: Merging-masking.
 538         3: Both zeroing and merging masking.
 539    */
 540 #define ZEROING_MASKING 1
 541 #define MERGING_MASKING 2
 542 #define BOTH_MASKING    3
 543   Masking,
 544
 545   /* Input element size of vector insn:
 546         0: 32bit.
 547         1: 64bit.
 548    */
 549   VecESize,
 550
 551   /* Broadcast factor.
 552         0: No broadcast.
 553         1: 1to16 broadcast.
 554         2: 1to8 broadcast.
 555    */
 556 #define NO_BROADCAST    0
 557 #define BROADCAST_1TO16 1
 558 #define BROADCAST_1TO8  2
 559 #define BROADCAST_1TO4  3
 560 #define BROADCAST_1TO2  4
 561   Broadcast,
 562
 563   /* Static rounding control is supported.  */
 564   StaticRounding,
 565
 566   /* Supress All Exceptions is supported.  */
 567   SAE,
 568
 569   /* Copressed Disp8*N attribute.  */
 570   Disp8MemShift,
 571
 572   /* Default mask isn't allowed.  */
 573   NoDefMask,
 574
 575   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 576      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 577    */
 578   ImplicitQuadGroup,
 579
 580   /* Compatible with old (<= 2.8.1) versions of gcc  */
 581   OldGcc,
 582   /* AT&T mnemonic.  */
 583   ATTMnemonic,
 584   /* AT&T syntax.  */
 585   ATTSyntax,
 586   /* Intel syntax.  */
 587   IntelSyntax,
 588   /* AMD64.  */
 589   AMD64,
 590   /* Intel64.  */
 591   Intel64,
 592   /* The last bitfield in i386_opcode_modifier.  */
 593   Opcode_Modifier_Max
 594 };
 595
 596 typedef struct i386_opcode_modifier
 597 {
 598   unsigned int d:1;
 599   unsigned int w:1;
 600   unsigned int load:1;
 601   unsigned int modrm:1;
 602   unsigned int shortform:1;
 603   unsigned int jump:1;
 604   unsigned int jumpdword:1;
 605   unsigned int jumpbyte:1;
 606   unsigned int jumpintersegment:1;
 607   unsigned int floatmf:1;
 608   unsigned int floatr:1;
 609   unsigned int floatd:1;
 610   unsigned int size16:1;
 611   unsigned int size32:1;
 612   unsigned int size64:1;
 613   unsigned int checkregsize:1;
 614   unsigned int ignoresize:1;
 615   unsigned int defaultsize:1;
 616   unsigned int no_bsuf:1;
 617   unsigned int no_wsuf:1;
 618   unsigned int no_lsuf:1;
 619   unsigned int no_ssuf:1;
 620   unsigned int no_qsuf:1;
 621   unsigned int no_ldsuf:1;
 622   unsigned int fwait:1;
 623   unsigned int isstring:1;
 624   unsigned int bndprefixok:1;
 625   unsigned int islockable:1;
 626   unsigned int regkludge:1;
 627   unsigned int firstxmm0:1;
 628   unsigned int implicit1stxmm0:1;
 629   unsigned int hleprefixok:2;
 630   unsigned int repprefixok:1;
 631   unsigned int todword:1;
 632   unsigned int toqword:1;
 633   unsigned int addrprefixop0:1;
 634   unsigned int isprefix:1;
 635   unsigned int immext:1;
 636   unsigned int norex64:1;
 637   unsigned int rex64:1;
 638   unsigned int ugh:1;
 639   unsigned int vex:2;
 640   unsigned int vexvvvv:2;
 641   unsigned int vexw:2;
 642   unsigned int vexopcode:3;
 643   unsigned int vexsources:2;
 644   unsigned int veximmext:1;
 645   unsigned int vecsib:2;
 646   unsigned int sse2avx:1;
 647   unsigned int noavx:1;
 648   unsigned int evex:3;
 649   unsigned int masking:2;
 650   unsigned int vecesize:1;
 651   unsigned int broadcast:3;
 652   unsigned int staticrounding:1;
 653   unsigned int sae:1;
 654   unsigned int disp8memshift:3;
 655   unsigned int nodefmask:1;
 656   unsigned int implicitquadgroup:1;
 657   unsigned int oldgcc:1;
 658   unsigned int attmnemonic:1;
 659   unsigned int attsyntax:1;
 660   unsigned int intelsyntax:1;
 661   unsigned int amd64:1;
 662   unsigned int intel64:1;
 663 } i386_opcode_modifier;
 664
 665 /* Position of operand_type bits.  */
 666
 667 enum
 668 {
 669   /* 8bit register */
 670   Reg8 = 0,
 671   /* 16bit register */
 672   Reg16,
 673   /* 32bit register */
 674   Reg32,
 675   /* 64bit register */
 676   Reg64,
 677   /* Floating pointer stack register */
 678   FloatReg,
 679   /* MMX register */
 680   RegMMX,
 681   /* SSE register */
 682   RegXMM,
 683   /* AVX registers */
 684   RegYMM,
 685   /* AVX512 registers */
 686   RegZMM,
 687   /* Vector Mask registers */
 688   RegMask,
 689   /* Control register */
 690   Control,
 691   /* Debug register */
 692   Debug,
 693   /* Test register */
 694   Test,
 695   /* 2 bit segment register */
 696   SReg2,
 697   /* 3 bit segment register */
 698   SReg3,
 699   /* 1 bit immediate */
 700   Imm1,
 701   /* 8 bit immediate */
 702   Imm8,
 703   /* 8 bit immediate sign extended */
 704   Imm8S,
 705   /* 16 bit immediate */
 706   Imm16,
 707   /* 32 bit immediate */
 708   Imm32,
 709   /* 32 bit immediate sign extended */
 710   Imm32S,
 711   /* 64 bit immediate */
 712   Imm64,
 713   /* 8bit/16bit/32bit displacements are used in different ways,
 714      depending on the instruction.  For jumps, they specify the
 715      size of the PC relative displacement, for instructions with
 716      memory operand, they specify the size of the offset relative
 717      to the base register, and for instructions with memory offset
 718      such as `mov 1234,%al' they specify the size of the offset
 719      relative to the segment base.  */
 720   /* 8 bit displacement */
 721   Disp8,
 722   /* 16 bit displacement */
 723   Disp16,
 724   /* 32 bit displacement */
 725   Disp32,
 726   /* 32 bit signed displacement */
 727   Disp32S,
 728   /* 64 bit displacement */
 729   Disp64,
 730   /* Accumulator %al/%ax/%eax/%rax */
 731   Acc,
 732   /* Floating pointer top stack register %st(0) */
 733   FloatAcc,
 734   /* Register which can be used for base or index in memory operand.  */
 735   BaseIndex,
 736   /* Register to hold in/out port addr = dx */
 737   InOutPortReg,
 738   /* Register to hold shift count = cl */
 739   ShiftCount,
 740   /* Absolute address for jump.  */
 741   JumpAbsolute,
 742   /* String insn operand with fixed es segment */
 743   EsSeg,
 744   /* RegMem is for instructions with a modrm byte where the register
 745      destination operand should be encoded in the mod and regmem fields.
 746      Normally, it will be encoded in the reg field. We add a RegMem
 747      flag to the destination register operand to indicate that it should
 748      be encoded in the regmem field.  */
 749   RegMem,
 750   /* Memory.  */
 751   Mem,
 752   /* BYTE memory. */
 753   Byte,
 754   /* WORD memory. 2 byte */
 755   Word,
 756   /* DWORD memory. 4 byte */
 757   Dword,
 758   /* FWORD memory. 6 byte */
 759   Fword,
 760   /* QWORD memory. 8 byte */
 761   Qword,
 762   /* TBYTE memory. 10 byte */
 763   Tbyte,
 764   /* XMMWORD memory. */
 765   Xmmword,
 766   /* YMMWORD memory. */
 767   Ymmword,
 768   /* ZMMWORD memory.  */
 769   Zmmword,
 770   /* Unspecified memory size.  */
 771   Unspecified,
 772   /* Any memory size.  */
 773   Anysize,
 774
 775   /* Vector 4 bit immediate.  */
 776   Vec_Imm4,
 777
 778   /* Bound register.  */
 779   RegBND,
 780
 781   /* Vector 8bit displacement */
 782   Vec_Disp8,
 783
 784   /* The last bitfield in i386_operand_type.  */
 785   OTMax
 786 };
 787
 788 #define OTNumOfUints \
 789   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 790 #define OTNumOfBits \
 791   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 792
 793 /* If you get a compiler error for zero width of the unused field,
 794    comment it out.  */
 795 #define OTUnused                (OTMax + 1)
 796
 797 typedef union i386_operand_type
 798 {
 799   struct
 800     {
 801       unsigned int reg8:1;
 802       unsigned int reg16:1;
 803       unsigned int reg32:1;
 804       unsigned int reg64:1;
 805       unsigned int floatreg:1;
 806       unsigned int regmmx:1;
 807       unsigned int regxmm:1;
 808       unsigned int regymm:1;
 809       unsigned int regzmm:1;
 810       unsigned int regmask:1;
 811       unsigned int control:1;
 812       unsigned int debug:1;
 813       unsigned int test:1;
 814       unsigned int sreg2:1;
 815       unsigned int sreg3:1;
 816       unsigned int imm1:1;
 817       unsigned int imm8:1;
 818       unsigned int imm8s:1;
 819       unsigned int imm16:1;
 820       unsigned int imm32:1;
 821       unsigned int imm32s:1;
 822       unsigned int imm64:1;
 823       unsigned int disp8:1;
 824       unsigned int disp16:1;
 825       unsigned int disp32:1;
 826       unsigned int disp32s:1;
 827       unsigned int disp64:1;
 828       unsigned int acc:1;
 829       unsigned int floatacc:1;
 830       unsigned int baseindex:1;
 831       unsigned int inoutportreg:1;
 832       unsigned int shiftcount:1;
 833       unsigned int jumpabsolute:1;
 834       unsigned int esseg:1;
 835       unsigned int regmem:1;
 836       unsigned int mem:1;
 837       unsigned int byte:1;
 838       unsigned int word:1;
 839       unsigned int dword:1;
 840       unsigned int fword:1;
 841       unsigned int qword:1;
 842       unsigned int tbyte:1;
 843       unsigned int xmmword:1;
 844       unsigned int ymmword:1;
 845       unsigned int zmmword:1;
 846       unsigned int unspecified:1;
 847       unsigned int anysize:1;
 848       unsigned int vec_imm4:1;
 849       unsigned int regbnd:1;
 850       unsigned int vec_disp8:1;
 851 #ifdef OTUnused
 852       unsigned int unused:(OTNumOfBits - OTUnused);
 853 #endif
 854     } bitfield;
 855   unsigned int array[OTNumOfUints];
 856 } i386_operand_type;
 857
 858 typedef struct insn_template
 859 {
 860   /* instruction name sans width suffix ("mov" for movl insns) */
 861   char *name;
 862
 863   /* how many operands */
 864   unsigned int operands;
 865
 866   /* base_opcode is the fundamental opcode byte without optional
 867      prefix(es).  */
 868   unsigned int base_opcode;
 869 #define Opcode_D        0x2 /* Direction bit:
 870                                set if Reg --> Regmem;
 871                                unset if Regmem --> Reg. */
 872 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 873 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 874
 875   /* extension_opcode is the 3 bit extension for group <n> insns.
 876      This field is also used to store the 8-bit opcode suffix for the
 877      AMD 3DNow! instructions.
 878      If this template has no extension opcode (the usual case) use None
 879      Instructions */
 880   unsigned int extension_opcode;
 881 #define None 0xffff             /* If no extension_opcode is possible.  */
 882
 883   /* Opcode length.  */
 884   unsigned char opcode_length;
 885
 886   /* cpu feature flags */
 887   i386_cpu_flags cpu_flags;
 888
 889   /* the bits in opcode_modifier are used to generate the final opcode from
 890      the base_opcode.  These bits also are used to detect alternate forms of
 891      the same instruction */
 892   i386_opcode_modifier opcode_modifier;
 893
 894   /* operand_types[i] describes the type of operand i.  This is made
 895      by OR'ing together all of the possible type masks.  (e.g.
 896      'operand_types[i] = Reg|Imm' specifies that operand i can be
 897      either a register or an immediate operand.  */
 898   i386_operand_type operand_types[MAX_OPERANDS];
 899 }
 900 insn_template;
 901
 902 extern const insn_template i386_optab[];
 903
 904 /* these are for register name --> number & type hash lookup */
 905 typedef struct
 906 {
 907   char *reg_name;
 908   i386_operand_type reg_type;
 909   unsigned char reg_flags;
 910 #define RegRex      0x1  /* Extended register.  */
 911 #define RegRex64    0x2  /* Extended 8 bit register.  */
 912 #define RegVRex     0x4  /* Extended vector register.  */
 913   unsigned char reg_num;
 914 #define RegRip  ((unsigned char ) ~0)
 915 #define RegEip  (RegRip - 1)
 916 /* EIZ and RIZ are fake index registers.  */
 917 #define RegEiz  (RegEip - 1)
 918 #define RegRiz  (RegEiz - 1)
 919 /* FLAT is a fake segment register (Intel mode).  */
 920 #define RegFlat     ((unsigned char) ~0)
 921   signed char dw2_regnum[2];
 922 #define Dw2Inval (-1)
 923 }
 924 reg_entry;
 925
 926 /* Entries in i386_regtab.  */
 927 #define REGNAM_AL 1
 928 #define REGNAM_AX 25
 929 #define REGNAM_EAX 41
 930
 931 extern const reg_entry i386_regtab[];
 932 extern const unsigned int i386_regtab_size;
 933
 934 typedef struct
 935 {
 936   char *seg_name;
 937   unsigned int seg_prefix;
 938 }
 939 seg_entry;
 940
 941 extern const seg_entry cs;
 942 extern const seg_entry ds;
 943 extern const seg_entry ss;
 944 extern const seg_entry es;
 945 extern const seg_entry fs;
 946 extern const seg_entry gs;