1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CMOV Instruction support required */
48 /* FXSR Instruction support required */
50 /* CLFLUSH Instruction support required */
52 /* NOP Instruction support required */
54 /* SYSCALL Instructions support required */
56 /* Floating point support required */
58 /* i287 support required */
60 /* i387 support required */
62 /* i686 and floating point support required */
64 /* SSE3 and floating point support required */
66 /* MMX support required */
68 /* SSE support required */
70 /* SSE2 support required */
72 /* 3dnow! support required */
74 /* 3dnow! Extensions support required */
76 /* SSE3 support required */
78 /* VIA PadLock required */
80 /* AMD Secure Virtual Machine Ext-s required */
82 /* VMX Instructions required */
84 /* SMX Instructions required */
86 /* SSSE3 support required */
88 /* SSE4a support required */
90 /* ABM New Instructions required */
92 /* SSE4.1 support required */
94 /* SSE4.2 support required */
96 /* AVX support required */
98 /* AVX2 support required */
100 /* Intel AVX-512 Foundation Instructions support required */
102 /* Intel AVX-512 Conflict Detection Instructions support required */
104 /* Intel AVX-512 Exponential and Reciprocal Instructions support
107 /* Intel AVX-512 Prefetch Instructions support required */
109 /* Intel AVX-512 VL Instructions support required. */
111 /* Intel AVX-512 DQ Instructions support required. */
113 /* Intel AVX-512 BW Instructions support required. */
115 /* Intel L1OM support required */
117 /* Intel K1OM support required */
119 /* Intel IAMCU support required */
121 /* Xsave/xrstor New Instructions support required */
123 /* Xsaveopt New Instructions support required */
125 /* AES support required */
127 /* PCLMUL support required */
129 /* FMA support required */
131 /* FMA4 support required */
133 /* XOP support required */
135 /* LWP support required */
137 /* BMI support required */
139 /* TBM support required */
141 /* MOVBE Instruction support required */
143 /* CMPXCHG16B instruction support required. */
145 /* EPT Instructions required */
147 /* RDTSCP Instruction support required */
149 /* FSGSBASE Instructions required */
151 /* RDRND Instructions required */
153 /* F16C Instructions required */
155 /* Intel BMI2 support required */
157 /* LZCNT support required */
159 /* HLE support required */
161 /* RTM support required */
163 /* INVPCID Instructions required */
165 /* VMFUNC Instruction required */
167 /* Intel MPX Instructions required */
169 /* 64bit support available, used by -march= in assembler. */
171 /* RDRSEED instruction required. */
173 /* Multi-presisionn add-carry instructions are required. */
175 /* Supports prefetchw and prefetch instructions. */
177 /* SMAP instructions required. */
179 /* SHA instructions required. */
181 /* CLFLUSHOPT instruction required */
183 /* XSAVES/XRSTORS instruction required */
185 /* XSAVEC instruction required */
187 /* PREFETCHWT1 instruction required */
189 /* SE1 instruction required */
191 /* CLWB instruction required */
193 /* Intel AVX-512 IFMA Instructions support required. */
195 /* Intel AVX-512 VBMI Instructions support required. */
197 /* Intel AVX-512 4FMAPS Instructions support required. */
199 /* Intel AVX-512 4VNNIW Instructions support required. */
201 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
203 /* Intel AVX-512 VBMI2 Instructions support required. */
205 /* Intel AVX-512 VNNI Instructions support required. */
207 /* Intel AVX-512 BITALG Instructions support required. */
209 /* Intel AVX-512 BF16 Instructions support required. */
211 /* Intel AVX-512 VP2INTERSECT Instructions support required. */
212 CpuAVX512_VP2INTERSECT
,
213 /* mwaitx instruction required */
215 /* Clzero instruction required */
217 /* OSPKE instruction required */
219 /* RDPID instruction required */
221 /* PTWRITE instruction required */
223 /* CET instructions support required */
226 /* GFNI instructions required */
228 /* VAES instructions required */
230 /* VPCLMULQDQ instructions required */
232 /* WBNOINVD instructions required */
234 /* PCONFIG instructions required */
236 /* WAITPKG instructions required */
238 /* CLDEMOTE instruction required */
240 /* MOVDIRI instruction support required */
242 /* MOVDIRR64B instruction required */
244 /* ENQCMD instruction required */
246 /* RDPRU instruction required */
248 /* MCOMMIT instruction required */
250 /* 64bit support required */
252 /* Not supported in the 64bit mode */
254 /* The last bitfield in i386_cpu_flags. */
258 #define CpuNumOfUints \
259 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
260 #define CpuNumOfBits \
261 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
263 /* If you get a compiler error for zero width of the unused field,
265 #define CpuUnused (CpuMax + 1)
267 /* We can check if an instruction is available with array instead
269 typedef union i386_cpu_flags
273 unsigned int cpui186
:1;
274 unsigned int cpui286
:1;
275 unsigned int cpui386
:1;
276 unsigned int cpui486
:1;
277 unsigned int cpui586
:1;
278 unsigned int cpui686
:1;
279 unsigned int cpucmov
:1;
280 unsigned int cpufxsr
:1;
281 unsigned int cpuclflush
:1;
282 unsigned int cpunop
:1;
283 unsigned int cpusyscall
:1;
284 unsigned int cpu8087
:1;
285 unsigned int cpu287
:1;
286 unsigned int cpu387
:1;
287 unsigned int cpu687
:1;
288 unsigned int cpufisttp
:1;
289 unsigned int cpummx
:1;
290 unsigned int cpusse
:1;
291 unsigned int cpusse2
:1;
292 unsigned int cpua3dnow
:1;
293 unsigned int cpua3dnowa
:1;
294 unsigned int cpusse3
:1;
295 unsigned int cpupadlock
:1;
296 unsigned int cpusvme
:1;
297 unsigned int cpuvmx
:1;
298 unsigned int cpusmx
:1;
299 unsigned int cpussse3
:1;
300 unsigned int cpusse4a
:1;
301 unsigned int cpuabm
:1;
302 unsigned int cpusse4_1
:1;
303 unsigned int cpusse4_2
:1;
304 unsigned int cpuavx
:1;
305 unsigned int cpuavx2
:1;
306 unsigned int cpuavx512f
:1;
307 unsigned int cpuavx512cd
:1;
308 unsigned int cpuavx512er
:1;
309 unsigned int cpuavx512pf
:1;
310 unsigned int cpuavx512vl
:1;
311 unsigned int cpuavx512dq
:1;
312 unsigned int cpuavx512bw
:1;
313 unsigned int cpul1om
:1;
314 unsigned int cpuk1om
:1;
315 unsigned int cpuiamcu
:1;
316 unsigned int cpuxsave
:1;
317 unsigned int cpuxsaveopt
:1;
318 unsigned int cpuaes
:1;
319 unsigned int cpupclmul
:1;
320 unsigned int cpufma
:1;
321 unsigned int cpufma4
:1;
322 unsigned int cpuxop
:1;
323 unsigned int cpulwp
:1;
324 unsigned int cpubmi
:1;
325 unsigned int cputbm
:1;
326 unsigned int cpumovbe
:1;
327 unsigned int cpucx16
:1;
328 unsigned int cpuept
:1;
329 unsigned int cpurdtscp
:1;
330 unsigned int cpufsgsbase
:1;
331 unsigned int cpurdrnd
:1;
332 unsigned int cpuf16c
:1;
333 unsigned int cpubmi2
:1;
334 unsigned int cpulzcnt
:1;
335 unsigned int cpuhle
:1;
336 unsigned int cpurtm
:1;
337 unsigned int cpuinvpcid
:1;
338 unsigned int cpuvmfunc
:1;
339 unsigned int cpumpx
:1;
340 unsigned int cpulm
:1;
341 unsigned int cpurdseed
:1;
342 unsigned int cpuadx
:1;
343 unsigned int cpuprfchw
:1;
344 unsigned int cpusmap
:1;
345 unsigned int cpusha
:1;
346 unsigned int cpuclflushopt
:1;
347 unsigned int cpuxsaves
:1;
348 unsigned int cpuxsavec
:1;
349 unsigned int cpuprefetchwt1
:1;
350 unsigned int cpuse1
:1;
351 unsigned int cpuclwb
:1;
352 unsigned int cpuavx512ifma
:1;
353 unsigned int cpuavx512vbmi
:1;
354 unsigned int cpuavx512_4fmaps
:1;
355 unsigned int cpuavx512_4vnniw
:1;
356 unsigned int cpuavx512_vpopcntdq
:1;
357 unsigned int cpuavx512_vbmi2
:1;
358 unsigned int cpuavx512_vnni
:1;
359 unsigned int cpuavx512_bitalg
:1;
360 unsigned int cpuavx512_bf16
:1;
361 unsigned int cpuavx512_vp2intersect
:1;
362 unsigned int cpumwaitx
:1;
363 unsigned int cpuclzero
:1;
364 unsigned int cpuospke
:1;
365 unsigned int cpurdpid
:1;
366 unsigned int cpuptwrite
:1;
367 unsigned int cpuibt
:1;
368 unsigned int cpushstk
:1;
369 unsigned int cpugfni
:1;
370 unsigned int cpuvaes
:1;
371 unsigned int cpuvpclmulqdq
:1;
372 unsigned int cpuwbnoinvd
:1;
373 unsigned int cpupconfig
:1;
374 unsigned int cpuwaitpkg
:1;
375 unsigned int cpucldemote
:1;
376 unsigned int cpumovdiri
:1;
377 unsigned int cpumovdir64b
:1;
378 unsigned int cpuenqcmd
:1;
379 unsigned int cpurdpru
:1;
380 unsigned int cpumcommit
:1;
381 unsigned int cpu64
:1;
382 unsigned int cpuno64
:1;
384 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
387 unsigned int array
[CpuNumOfUints
];
390 /* Position of opcode_modifier bits. */
394 /* has direction bit. */
396 /* set if operands can be both bytes and words/dwords/qwords, encoded the
397 canonical way; the base_opcode field should hold the encoding for byte
400 /* load form instruction. Must be placed before store form. */
402 /* insn has a modrm byte. */
404 /* register is in low 3 bits of opcode */
406 /* special case for jump insns. */
412 /* special case for intersegment leaps/calls */
414 /* FP insn memory format bit, sized by 0x4 */
416 /* src/dest swap for floats. */
418 /* needs size prefix if in 32-bit mode */
420 /* needs size prefix if in 16-bit mode */
422 /* needs size prefix if in 64-bit mode */
425 /* check register size. */
427 /* instruction ignores operand size prefix and in Intel mode ignores
428 mnemonic size suffix check. */
430 /* default insn size depends on mode */
432 /* b suffix on instruction illegal */
434 /* w suffix on instruction illegal */
436 /* l suffix on instruction illegal */
438 /* s suffix on instruction illegal */
440 /* q suffix on instruction illegal */
442 /* long double suffix on instruction illegal */
444 /* instruction needs FWAIT */
446 /* IsString provides for a quick test for string instructions, and
447 its actual value also indicates which of the operands (if any)
448 requires use of the %es segment. */
449 #define IS_STRING_ES_OP0 2
450 #define IS_STRING_ES_OP1 3
452 /* RegMem is for instructions with a modrm byte where the register
453 destination operand should be encoded in the mod and regmem fields.
454 Normally, it will be encoded in the reg field. We add a RegMem
455 flag to indicate that it should be encoded in the regmem field. */
457 /* quick test if branch instruction is MPX supported */
459 /* quick test if NOTRACK prefix is supported */
461 /* quick test for lockable instructions */
463 /* fake an extra reg operand for clr, imul and special register
464 processing for some instructions. */
466 /* An implicit xmm0 as the first operand */
468 /* The HLE prefix is OK:
469 1. With a LOCK prefix.
470 2. With or without a LOCK prefix.
471 3. With a RELEASE (0xf3) prefix.
473 #define HLEPrefixNone 0
474 #define HLEPrefixLock 1
475 #define HLEPrefixAny 2
476 #define HLEPrefixRelease 3
478 /* An instruction on which a "rep" prefix is acceptable. */
480 /* Convert to DWORD */
482 /* Convert to QWORD */
484 /* Address prefix changes register operand */
486 /* opcode is a prefix */
488 /* instruction has extension in 8 bit imm */
490 /* instruction don't need Rex64 prefix. */
492 /* instruction require Rex64 prefix. */
494 /* deprecated fp insn, gets a warning */
496 /* insn has VEX prefix:
497 1: 128bit VEX prefix (or operand dependent).
498 2: 256bit VEX prefix.
499 3: Scalar VEX prefix.
505 /* How to encode VEX.vvvv:
506 0: VEX.vvvv must be 1111b.
507 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
508 the content of source registers will be preserved.
509 VEX.DDS. The second register operand is encoded in VEX.vvvv
510 where the content of first source register will be overwritten
512 VEX.NDD2. The second destination register operand is encoded in
513 VEX.vvvv for instructions with 2 destination register operands.
514 For assembler, there are no difference between VEX.NDS, VEX.DDS
516 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
517 instructions with 1 destination register operand.
518 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
519 of the operands can access a memory location.
525 /* How the VEX.W bit is used:
526 0: Set by the REX.W bit.
527 1: VEX.W0. Should always be 0.
528 2: VEX.W1. Should always be 1.
529 3: VEX.WIG. The VEX.W bit is ignored.
535 /* VEX opcode prefix:
536 0: VEX 0x0F opcode prefix.
537 1: VEX 0x0F38 opcode prefix.
538 2: VEX 0x0F3A opcode prefix
539 3: XOP 0x08 opcode prefix.
540 4: XOP 0x09 opcode prefix
541 5: XOP 0x0A opcode prefix.
550 /* number of VEX source operands:
551 0: <= 2 source operands.
552 1: 2 XOP source operands.
553 2: 3 source operands.
555 #define XOP2SOURCES 1
556 #define VEX3SOURCES 2
558 /* Instruction with vector SIB byte:
559 1: 128bit vector register.
560 2: 256bit vector register.
561 3: 512bit vector register.
567 /* SSE to AVX support required */
569 /* No AVX equivalent */
572 /* insn has EVEX prefix:
573 1: 512bit EVEX prefix.
574 2: 128bit EVEX prefix.
575 3: 256bit EVEX prefix.
576 4: Length-ignored (LIG) EVEX prefix.
577 5: Length determined from actual operands.
586 /* AVX512 masking support:
587 1: Zeroing or merging masking depending on operands.
589 3: Both zeroing and merging masking.
591 #define DYNAMIC_MASKING 1
592 #define MERGING_MASKING 2
593 #define BOTH_MASKING 3
596 /* AVX512 broadcast support. The number of bytes to broadcast is
597 1 << (Broadcast - 1):
603 #define BYTE_BROADCAST 1
604 #define WORD_BROADCAST 2
605 #define DWORD_BROADCAST 3
606 #define QWORD_BROADCAST 4
609 /* Static rounding control is supported. */
612 /* Supress All Exceptions is supported. */
615 /* Compressed Disp8*N attribute. */
616 #define DISP8_SHIFT_VL 7
619 /* Default mask isn't allowed. */
622 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
623 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
627 /* Support encoding optimization. */
640 /* The last bitfield in i386_opcode_modifier. */
644 typedef struct i386_opcode_modifier
649 unsigned int modrm
:1;
650 unsigned int shortform
:1;
652 unsigned int jumpdword
:1;
653 unsigned int jumpbyte
:1;
654 unsigned int jumpintersegment
:1;
655 unsigned int floatmf
:1;
656 unsigned int floatr
:1;
658 unsigned int checkregsize
:1;
659 unsigned int ignoresize
:1;
660 unsigned int defaultsize
:1;
661 unsigned int no_bsuf
:1;
662 unsigned int no_wsuf
:1;
663 unsigned int no_lsuf
:1;
664 unsigned int no_ssuf
:1;
665 unsigned int no_qsuf
:1;
666 unsigned int no_ldsuf
:1;
667 unsigned int fwait
:1;
668 unsigned int isstring
:2;
669 unsigned int regmem
:1;
670 unsigned int bndprefixok
:1;
671 unsigned int notrackprefixok
:1;
672 unsigned int islockable
:1;
673 unsigned int regkludge
:1;
674 unsigned int implicit1stxmm0
:1;
675 unsigned int hleprefixok
:2;
676 unsigned int repprefixok
:1;
677 unsigned int todword
:1;
678 unsigned int toqword
:1;
679 unsigned int addrprefixopreg
:1;
680 unsigned int isprefix
:1;
681 unsigned int immext
:1;
682 unsigned int norex64
:1;
683 unsigned int rex64
:1;
686 unsigned int vexvvvv
:2;
688 unsigned int vexopcode
:3;
689 unsigned int vexsources
:2;
690 unsigned int vecsib
:2;
691 unsigned int sse2avx
:1;
692 unsigned int noavx
:1;
694 unsigned int masking
:2;
695 unsigned int broadcast
:3;
696 unsigned int staticrounding
:1;
698 unsigned int disp8memshift
:3;
699 unsigned int nodefmask
:1;
700 unsigned int implicitquadgroup
:1;
701 unsigned int optimize
:1;
702 unsigned int attmnemonic
:1;
703 unsigned int attsyntax
:1;
704 unsigned int intelsyntax
:1;
705 unsigned int amd64
:1;
706 unsigned int intel64
:1;
707 } i386_opcode_modifier
;
709 /* Operand classes. */
711 #define CLASS_WIDTH 4
715 Reg
, /* GPRs and FP regs, distinguished by operand size */
716 SReg
, /* Segment register */
717 RegCR
, /* Control register */
718 RegDR
, /* Debug register */
719 RegTR
, /* Test register */
720 RegMMX
, /* MMX register */
721 RegSIMD
, /* XMM/YMM/ZMM registers, distinguished by operand size */
722 RegMask
, /* Vector Mask register */
723 RegBND
, /* Bound register */
726 /* Special operand instances. */
728 #define INSTANCE_WIDTH 3
729 enum operand_instance
732 Accum
, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
733 RegC
, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
734 RegD
, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
735 RegB
, /* %bl / %bx / %ebx / %rbx */
738 /* Position of operand_type bits. */
742 /* Class and Instance */
743 ClassInstance
= CLASS_WIDTH
+ INSTANCE_WIDTH
- 1,
744 /* 1 bit immediate */
746 /* 8 bit immediate */
748 /* 8 bit immediate sign extended */
750 /* 16 bit immediate */
752 /* 32 bit immediate */
754 /* 32 bit immediate sign extended */
756 /* 64 bit immediate */
758 /* 8bit/16bit/32bit displacements are used in different ways,
759 depending on the instruction. For jumps, they specify the
760 size of the PC relative displacement, for instructions with
761 memory operand, they specify the size of the offset relative
762 to the base register, and for instructions with memory offset
763 such as `mov 1234,%al' they specify the size of the offset
764 relative to the segment base. */
765 /* 8 bit displacement */
767 /* 16 bit displacement */
769 /* 32 bit displacement */
771 /* 32 bit signed displacement */
773 /* 64 bit displacement */
775 /* Register which can be used for base or index in memory operand. */
777 /* Absolute address for jump. */
781 /* WORD size. 2 byte */
783 /* DWORD size. 4 byte */
785 /* FWORD size. 6 byte */
787 /* QWORD size. 8 byte */
789 /* TBYTE size. 10 byte */
797 /* Unspecified memory size. */
799 /* Any memory size. */
802 /* The number of bits in i386_operand_type. */
806 #define OTNumOfUints \
807 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
808 #define OTNumOfBits \
809 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
811 /* If you get a compiler error for zero width of the unused field,
813 #define OTUnused OTNum
816 typedef union i386_operand_type
820 unsigned int class:CLASS_WIDTH
;
821 unsigned int instance
:INSTANCE_WIDTH
;
824 unsigned int imm8s
:1;
825 unsigned int imm16
:1;
826 unsigned int imm32
:1;
827 unsigned int imm32s
:1;
828 unsigned int imm64
:1;
829 unsigned int disp8
:1;
830 unsigned int disp16
:1;
831 unsigned int disp32
:1;
832 unsigned int disp32s
:1;
833 unsigned int disp64
:1;
834 unsigned int baseindex
:1;
835 unsigned int jumpabsolute
:1;
838 unsigned int dword
:1;
839 unsigned int fword
:1;
840 unsigned int qword
:1;
841 unsigned int tbyte
:1;
842 unsigned int xmmword
:1;
843 unsigned int ymmword
:1;
844 unsigned int zmmword
:1;
845 unsigned int unspecified
:1;
846 unsigned int anysize
:1;
848 unsigned int unused
:(OTNumOfBits
- OTUnused
);
851 unsigned int array
[OTNumOfUints
];
854 typedef struct insn_template
856 /* instruction name sans width suffix ("mov" for movl insns) */
859 /* base_opcode is the fundamental opcode byte without optional
861 unsigned int base_opcode
;
862 #define Opcode_D 0x2 /* Direction bit:
863 set if Reg --> Regmem;
864 unset if Regmem --> Reg. */
865 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
866 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
867 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
868 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
870 /* extension_opcode is the 3 bit extension for group <n> insns.
871 This field is also used to store the 8-bit opcode suffix for the
872 AMD 3DNow! instructions.
873 If this template has no extension opcode (the usual case) use None
875 unsigned short extension_opcode
;
876 #define None 0xffff /* If no extension_opcode is possible. */
879 unsigned char opcode_length
;
881 /* how many operands */
882 unsigned char operands
;
884 /* cpu feature flags */
885 i386_cpu_flags cpu_flags
;
887 /* the bits in opcode_modifier are used to generate the final opcode from
888 the base_opcode. These bits also are used to detect alternate forms of
889 the same instruction */
890 i386_opcode_modifier opcode_modifier
;
892 /* operand_types[i] describes the type of operand i. This is made
893 by OR'ing together all of the possible type masks. (e.g.
894 'operand_types[i] = Reg|Imm' specifies that operand i can be
895 either a register or an immediate operand. */
896 i386_operand_type operand_types
[MAX_OPERANDS
];
900 extern const insn_template i386_optab
[];
902 /* these are for register name --> number & type hash lookup */
906 i386_operand_type reg_type
;
907 unsigned char reg_flags
;
908 #define RegRex 0x1 /* Extended register. */
909 #define RegRex64 0x2 /* Extended 8 bit register. */
910 #define RegVRex 0x4 /* Extended vector register. */
911 unsigned char reg_num
;
912 #define RegIP ((unsigned char ) ~0)
913 /* EIZ and RIZ are fake index registers. */
914 #define RegIZ (RegIP - 1)
915 /* FLAT is a fake segment register (Intel mode). */
916 #define RegFlat ((unsigned char) ~0)
917 signed char dw2_regnum
[2];
918 #define Dw2Inval (-1)
922 /* Entries in i386_regtab. */
925 #define REGNAM_EAX 41
927 extern const reg_entry i386_regtab
[];
928 extern const unsigned int i386_regtab_size
;
933 unsigned int seg_prefix
;
937 extern const seg_entry cs
;
938 extern const seg_entry ds
;
939 extern const seg_entry ss
;
940 extern const seg_entry es
;
941 extern const seg_entry fs
;
942 extern const seg_entry gs
;