1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 BW Instructions support required. */
109 /* Intel L1OM support required */
111 /* Intel K1OM support required */
113 /* Xsave/xrstor New Instructions support required */
115 /* Xsaveopt New Instructions support required */
117 /* AES support required */
119 /* PCLMUL support required */
121 /* FMA support required */
123 /* FMA4 support required */
125 /* XOP support required */
127 /* LWP support required */
129 /* BMI support required */
131 /* TBM support required */
133 /* MOVBE Instruction support required */
135 /* CMPXCHG16B instruction support required. */
137 /* EPT Instructions required */
139 /* RDTSCP Instruction support required */
141 /* FSGSBASE Instructions required */
143 /* RDRND Instructions required */
145 /* F16C Instructions required */
147 /* Intel BMI2 support required */
149 /* LZCNT support required */
151 /* HLE support required */
153 /* RTM support required */
155 /* INVPCID Instructions required */
157 /* VMFUNC Instruction required */
159 /* Intel MPX Instructions required */
161 /* 64bit support available, used by -march= in assembler. */
163 /* RDRSEED instruction required. */
165 /* Multi-presisionn add-carry instructions are required. */
167 /* Supports prefetchw and prefetch instructions. */
169 /* SMAP instructions required. */
171 /* SHA instructions required. */
173 /* VREX support required */
175 /* CLFLUSHOPT instruction required */
177 /* XSAVES/XRSTORS instruction required */
179 /* XSAVEC instruction required */
181 /* PREFETCHWT1 instruction required */
183 /* SE1 instruction required */
185 /* 64bit support required */
187 /* Not supported in the 64bit mode */
189 /* The last bitfield in i386_cpu_flags. */
193 #define CpuNumOfUints \
194 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
195 #define CpuNumOfBits \
196 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
198 /* If you get a compiler error for zero width of the unused field,
200 #define CpuUnused (CpuMax + 1)
202 /* We can check if an instruction is available with array instead
204 typedef union i386_cpu_flags
208 unsigned int cpui186
:1;
209 unsigned int cpui286
:1;
210 unsigned int cpui386
:1;
211 unsigned int cpui486
:1;
212 unsigned int cpui586
:1;
213 unsigned int cpui686
:1;
214 unsigned int cpuclflush
:1;
215 unsigned int cpunop
:1;
216 unsigned int cpusyscall
:1;
217 unsigned int cpu8087
:1;
218 unsigned int cpu287
:1;
219 unsigned int cpu387
:1;
220 unsigned int cpu687
:1;
221 unsigned int cpufisttp
:1;
222 unsigned int cpummx
:1;
223 unsigned int cpusse
:1;
224 unsigned int cpusse2
:1;
225 unsigned int cpua3dnow
:1;
226 unsigned int cpua3dnowa
:1;
227 unsigned int cpusse3
:1;
228 unsigned int cpupadlock
:1;
229 unsigned int cpusvme
:1;
230 unsigned int cpuvmx
:1;
231 unsigned int cpusmx
:1;
232 unsigned int cpussse3
:1;
233 unsigned int cpusse4a
:1;
234 unsigned int cpuabm
:1;
235 unsigned int cpusse4_1
:1;
236 unsigned int cpusse4_2
:1;
237 unsigned int cpuavx
:1;
238 unsigned int cpuavx2
:1;
239 unsigned int cpuavx512f
:1;
240 unsigned int cpuavx512cd
:1;
241 unsigned int cpuavx512er
:1;
242 unsigned int cpuavx512pf
:1;
243 unsigned int cpuavx512vl
:1;
244 unsigned int cpuavx512bw
:1;
245 unsigned int cpul1om
:1;
246 unsigned int cpuk1om
:1;
247 unsigned int cpuxsave
:1;
248 unsigned int cpuxsaveopt
:1;
249 unsigned int cpuaes
:1;
250 unsigned int cpupclmul
:1;
251 unsigned int cpufma
:1;
252 unsigned int cpufma4
:1;
253 unsigned int cpuxop
:1;
254 unsigned int cpulwp
:1;
255 unsigned int cpubmi
:1;
256 unsigned int cputbm
:1;
257 unsigned int cpumovbe
:1;
258 unsigned int cpucx16
:1;
259 unsigned int cpuept
:1;
260 unsigned int cpurdtscp
:1;
261 unsigned int cpufsgsbase
:1;
262 unsigned int cpurdrnd
:1;
263 unsigned int cpuf16c
:1;
264 unsigned int cpubmi2
:1;
265 unsigned int cpulzcnt
:1;
266 unsigned int cpuhle
:1;
267 unsigned int cpurtm
:1;
268 unsigned int cpuinvpcid
:1;
269 unsigned int cpuvmfunc
:1;
270 unsigned int cpumpx
:1;
271 unsigned int cpulm
:1;
272 unsigned int cpurdseed
:1;
273 unsigned int cpuadx
:1;
274 unsigned int cpuprfchw
:1;
275 unsigned int cpusmap
:1;
276 unsigned int cpusha
:1;
277 unsigned int cpuvrex
:1;
278 unsigned int cpuclflushopt
:1;
279 unsigned int cpuxsaves
:1;
280 unsigned int cpuxsavec
:1;
281 unsigned int cpuprefetchwt1
:1;
282 unsigned int cpuse1
:1;
283 unsigned int cpu64
:1;
284 unsigned int cpuno64
:1;
286 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
289 unsigned int array
[CpuNumOfUints
];
292 /* Position of opcode_modifier bits. */
296 /* has direction bit. */
298 /* set if operands can be words or dwords encoded the canonical way */
300 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
301 operand in encoding. */
303 /* insn has a modrm byte. */
305 /* register is in low 3 bits of opcode */
307 /* special case for jump insns. */
313 /* special case for intersegment leaps/calls */
315 /* FP insn memory format bit, sized by 0x4 */
317 /* src/dest swap for floats. */
319 /* has float insn direction bit. */
321 /* needs size prefix if in 32-bit mode */
323 /* needs size prefix if in 16-bit mode */
325 /* needs size prefix if in 64-bit mode */
327 /* check register size. */
329 /* instruction ignores operand size prefix and in Intel mode ignores
330 mnemonic size suffix check. */
332 /* default insn size depends on mode */
334 /* b suffix on instruction illegal */
336 /* w suffix on instruction illegal */
338 /* l suffix on instruction illegal */
340 /* s suffix on instruction illegal */
342 /* q suffix on instruction illegal */
344 /* long double suffix on instruction illegal */
346 /* instruction needs FWAIT */
348 /* quick test for string instructions */
350 /* quick test if branch instruction is MPX supported */
352 /* quick test for lockable instructions */
354 /* fake an extra reg operand for clr, imul and special register
355 processing for some instructions. */
357 /* The first operand must be xmm0 */
359 /* An implicit xmm0 as the first operand */
361 /* The HLE prefix is OK:
362 1. With a LOCK prefix.
363 2. With or without a LOCK prefix.
364 3. With a RELEASE (0xf3) prefix.
366 #define HLEPrefixNone 0
367 #define HLEPrefixLock 1
368 #define HLEPrefixAny 2
369 #define HLEPrefixRelease 3
371 /* An instruction on which a "rep" prefix is acceptable. */
373 /* Convert to DWORD */
375 /* Convert to QWORD */
377 /* Address prefix changes operand 0 */
379 /* opcode is a prefix */
381 /* instruction has extension in 8 bit imm */
383 /* instruction don't need Rex64 prefix. */
385 /* instruction require Rex64 prefix. */
387 /* deprecated fp insn, gets a warning */
389 /* insn has VEX prefix:
390 1: 128bit VEX prefix.
391 2: 256bit VEX prefix.
392 3: Scalar VEX prefix.
398 /* How to encode VEX.vvvv:
399 0: VEX.vvvv must be 1111b.
400 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
401 the content of source registers will be preserved.
402 VEX.DDS. The second register operand is encoded in VEX.vvvv
403 where the content of first source register will be overwritten
405 VEX.NDD2. The second destination register operand is encoded in
406 VEX.vvvv for instructions with 2 destination register operands.
407 For assembler, there are no difference between VEX.NDS, VEX.DDS
409 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
410 instructions with 1 destination register operand.
411 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
412 of the operands can access a memory location.
418 /* How the VEX.W bit is used:
419 0: Set by the REX.W bit.
420 1: VEX.W0. Should always be 0.
421 2: VEX.W1. Should always be 1.
426 /* VEX opcode prefix:
427 0: VEX 0x0F opcode prefix.
428 1: VEX 0x0F38 opcode prefix.
429 2: VEX 0x0F3A opcode prefix
430 3: XOP 0x08 opcode prefix.
431 4: XOP 0x09 opcode prefix
432 5: XOP 0x0A opcode prefix.
441 /* number of VEX source operands:
442 0: <= 2 source operands.
443 1: 2 XOP source operands.
444 2: 3 source operands.
446 #define XOP2SOURCES 1
447 #define VEX3SOURCES 2
449 /* instruction has VEX 8 bit imm */
451 /* Instruction with vector SIB byte:
452 1: 128bit vector register.
453 2: 256bit vector register.
454 3: 512bit vector register.
460 /* SSE to AVX support required */
462 /* No AVX equivalent */
465 /* insn has EVEX prefix:
466 1: 512bit EVEX prefix.
467 2: 128bit EVEX prefix.
468 3: 256bit EVEX prefix.
469 4: Length-ignored (LIG) EVEX prefix.
477 /* AVX512 masking support:
480 3: Both zeroing and merging masking.
482 #define ZEROING_MASKING 1
483 #define MERGING_MASKING 2
484 #define BOTH_MASKING 3
487 /* Input element size of vector insn:
498 #define NO_BROADCAST 0
499 #define BROADCAST_1TO16 1
500 #define BROADCAST_1TO8 2
501 #define BROADCAST_1TO4 3
502 #define BROADCAST_1TO2 4
505 /* Static rounding control is supported. */
508 /* Supress All Exceptions is supported. */
511 /* Copressed Disp8*N attribute. */
514 /* Default mask isn't allowed. */
517 /* Compatible with old (<= 2.8.1) versions of gcc */
525 /* The last bitfield in i386_opcode_modifier. */
529 typedef struct i386_opcode_modifier
534 unsigned int modrm
:1;
535 unsigned int shortform
:1;
537 unsigned int jumpdword
:1;
538 unsigned int jumpbyte
:1;
539 unsigned int jumpintersegment
:1;
540 unsigned int floatmf
:1;
541 unsigned int floatr
:1;
542 unsigned int floatd
:1;
543 unsigned int size16
:1;
544 unsigned int size32
:1;
545 unsigned int size64
:1;
546 unsigned int checkregsize
:1;
547 unsigned int ignoresize
:1;
548 unsigned int defaultsize
:1;
549 unsigned int no_bsuf
:1;
550 unsigned int no_wsuf
:1;
551 unsigned int no_lsuf
:1;
552 unsigned int no_ssuf
:1;
553 unsigned int no_qsuf
:1;
554 unsigned int no_ldsuf
:1;
555 unsigned int fwait
:1;
556 unsigned int isstring
:1;
557 unsigned int bndprefixok
:1;
558 unsigned int islockable
:1;
559 unsigned int regkludge
:1;
560 unsigned int firstxmm0
:1;
561 unsigned int implicit1stxmm0
:1;
562 unsigned int hleprefixok
:2;
563 unsigned int repprefixok
:1;
564 unsigned int todword
:1;
565 unsigned int toqword
:1;
566 unsigned int addrprefixop0
:1;
567 unsigned int isprefix
:1;
568 unsigned int immext
:1;
569 unsigned int norex64
:1;
570 unsigned int rex64
:1;
573 unsigned int vexvvvv
:2;
575 unsigned int vexopcode
:3;
576 unsigned int vexsources
:2;
577 unsigned int veximmext
:1;
578 unsigned int vecsib
:2;
579 unsigned int sse2avx
:1;
580 unsigned int noavx
:1;
582 unsigned int masking
:2;
583 unsigned int vecesize
:1;
584 unsigned int broadcast
:3;
585 unsigned int staticrounding
:1;
587 unsigned int disp8memshift
:3;
588 unsigned int nodefmask
:1;
589 unsigned int oldgcc
:1;
590 unsigned int attmnemonic
:1;
591 unsigned int attsyntax
:1;
592 unsigned int intelsyntax
:1;
593 } i386_opcode_modifier
;
595 /* Position of operand_type bits. */
607 /* Floating pointer stack register */
615 /* AVX512 registers */
617 /* Vector Mask registers */
619 /* Control register */
625 /* 2 bit segment register */
627 /* 3 bit segment register */
629 /* 1 bit immediate */
631 /* 8 bit immediate */
633 /* 8 bit immediate sign extended */
635 /* 16 bit immediate */
637 /* 32 bit immediate */
639 /* 32 bit immediate sign extended */
641 /* 64 bit immediate */
643 /* 8bit/16bit/32bit displacements are used in different ways,
644 depending on the instruction. For jumps, they specify the
645 size of the PC relative displacement, for instructions with
646 memory operand, they specify the size of the offset relative
647 to the base register, and for instructions with memory offset
648 such as `mov 1234,%al' they specify the size of the offset
649 relative to the segment base. */
650 /* 8 bit displacement */
652 /* 16 bit displacement */
654 /* 32 bit displacement */
656 /* 32 bit signed displacement */
658 /* 64 bit displacement */
660 /* Accumulator %al/%ax/%eax/%rax */
662 /* Floating pointer top stack register %st(0) */
664 /* Register which can be used for base or index in memory operand. */
666 /* Register to hold in/out port addr = dx */
668 /* Register to hold shift count = cl */
670 /* Absolute address for jump. */
672 /* String insn operand with fixed es segment */
674 /* RegMem is for instructions with a modrm byte where the register
675 destination operand should be encoded in the mod and regmem fields.
676 Normally, it will be encoded in the reg field. We add a RegMem
677 flag to the destination register operand to indicate that it should
678 be encoded in the regmem field. */
684 /* WORD memory. 2 byte */
686 /* DWORD memory. 4 byte */
688 /* FWORD memory. 6 byte */
690 /* QWORD memory. 8 byte */
692 /* TBYTE memory. 10 byte */
694 /* XMMWORD memory. */
696 /* YMMWORD memory. */
698 /* ZMMWORD memory. */
700 /* Unspecified memory size. */
702 /* Any memory size. */
705 /* Vector 4 bit immediate. */
708 /* Bound register. */
711 /* Vector 8bit displacement */
714 /* The last bitfield in i386_operand_type. */
718 #define OTNumOfUints \
719 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
720 #define OTNumOfBits \
721 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
723 /* If you get a compiler error for zero width of the unused field,
725 #define OTUnused (OTMax + 1)
727 typedef union i386_operand_type
732 unsigned int reg16
:1;
733 unsigned int reg32
:1;
734 unsigned int reg64
:1;
735 unsigned int floatreg
:1;
736 unsigned int regmmx
:1;
737 unsigned int regxmm
:1;
738 unsigned int regymm
:1;
739 unsigned int regzmm
:1;
740 unsigned int regmask
:1;
741 unsigned int control
:1;
742 unsigned int debug
:1;
744 unsigned int sreg2
:1;
745 unsigned int sreg3
:1;
748 unsigned int imm8s
:1;
749 unsigned int imm16
:1;
750 unsigned int imm32
:1;
751 unsigned int imm32s
:1;
752 unsigned int imm64
:1;
753 unsigned int disp8
:1;
754 unsigned int disp16
:1;
755 unsigned int disp32
:1;
756 unsigned int disp32s
:1;
757 unsigned int disp64
:1;
759 unsigned int floatacc
:1;
760 unsigned int baseindex
:1;
761 unsigned int inoutportreg
:1;
762 unsigned int shiftcount
:1;
763 unsigned int jumpabsolute
:1;
764 unsigned int esseg
:1;
765 unsigned int regmem
:1;
769 unsigned int dword
:1;
770 unsigned int fword
:1;
771 unsigned int qword
:1;
772 unsigned int tbyte
:1;
773 unsigned int xmmword
:1;
774 unsigned int ymmword
:1;
775 unsigned int zmmword
:1;
776 unsigned int unspecified
:1;
777 unsigned int anysize
:1;
778 unsigned int vec_imm4
:1;
779 unsigned int regbnd
:1;
780 unsigned int vec_disp8
:1;
782 unsigned int unused
:(OTNumOfBits
- OTUnused
);
785 unsigned int array
[OTNumOfUints
];
788 typedef struct insn_template
790 /* instruction name sans width suffix ("mov" for movl insns) */
793 /* how many operands */
794 unsigned int operands
;
796 /* base_opcode is the fundamental opcode byte without optional
798 unsigned int base_opcode
;
799 #define Opcode_D 0x2 /* Direction bit:
800 set if Reg --> Regmem;
801 unset if Regmem --> Reg. */
802 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
803 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
805 /* extension_opcode is the 3 bit extension for group <n> insns.
806 This field is also used to store the 8-bit opcode suffix for the
807 AMD 3DNow! instructions.
808 If this template has no extension opcode (the usual case) use None
810 unsigned int extension_opcode
;
811 #define None 0xffff /* If no extension_opcode is possible. */
814 unsigned char opcode_length
;
816 /* cpu feature flags */
817 i386_cpu_flags cpu_flags
;
819 /* the bits in opcode_modifier are used to generate the final opcode from
820 the base_opcode. These bits also are used to detect alternate forms of
821 the same instruction */
822 i386_opcode_modifier opcode_modifier
;
824 /* operand_types[i] describes the type of operand i. This is made
825 by OR'ing together all of the possible type masks. (e.g.
826 'operand_types[i] = Reg|Imm' specifies that operand i can be
827 either a register or an immediate operand. */
828 i386_operand_type operand_types
[MAX_OPERANDS
];
832 extern const insn_template i386_optab
[];
834 /* these are for register name --> number & type hash lookup */
838 i386_operand_type reg_type
;
839 unsigned char reg_flags
;
840 #define RegRex 0x1 /* Extended register. */
841 #define RegRex64 0x2 /* Extended 8 bit register. */
842 #define RegVRex 0x4 /* Extended vector register. */
843 unsigned char reg_num
;
844 #define RegRip ((unsigned char ) ~0)
845 #define RegEip (RegRip - 1)
846 /* EIZ and RIZ are fake index registers. */
847 #define RegEiz (RegEip - 1)
848 #define RegRiz (RegEiz - 1)
849 /* FLAT is a fake segment register (Intel mode). */
850 #define RegFlat ((unsigned char) ~0)
851 signed char dw2_regnum
[2];
852 #define Dw2Inval (-1)
856 /* Entries in i386_regtab. */
859 #define REGNAM_EAX 41
861 extern const reg_entry i386_regtab
[];
862 extern const unsigned int i386_regtab_size
;
867 unsigned int seg_prefix
;
871 extern const seg_entry cs
;
872 extern const seg_entry ds
;
873 extern const seg_entry ss
;
874 extern const seg_entry es
;
875 extern const seg_entry fs
;
876 extern const seg_entry gs
;