opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008, 2009, 2010, 2012
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 enum
  34 {
  35   /* i186 or better required */
  36   Cpu186 = 0,
  37   /* i286 or better required */
  38   Cpu286,
  39   /* i386 or better required */
  40   Cpu386,
  41   /* i486 or better required */
  42   Cpu486,
  43   /* i585 or better required */
  44   Cpu586,
  45   /* i686 or better required */
  46   Cpu686,
  47   /* CLFLUSH Instruction support required */
  48   CpuClflush,
  49   /* NOP Instruction support required */
  50   CpuNop,
  51   /* SYSCALL Instructions support required */
  52   CpuSYSCALL,
  53   /* Floating point support required */
  54   Cpu8087,
  55   /* i287 support required */
  56   Cpu287,
  57   /* i387 support required */
  58   Cpu387,
  59   /* i686 and floating point support required */
  60   Cpu687,
  61   /* SSE3 and floating point support required */
  62   CpuFISTTP,
  63   /* MMX support required */
  64   CpuMMX,
  65   /* SSE support required */
  66   CpuSSE,
  67   /* SSE2 support required */
  68   CpuSSE2,
  69   /* 3dnow! support required */
  70   Cpu3dnow,
  71   /* 3dnow! Extensions support required */
  72   Cpu3dnowA,
  73   /* SSE3 support required */
  74   CpuSSE3,
  75   /* VIA PadLock required */
  76   CpuPadLock,
  77   /* AMD Secure Virtual Machine Ext-s required */
  78   CpuSVME,
  79   /* VMX Instructions required */
  80   CpuVMX,
  81   /* SMX Instructions required */
  82   CpuSMX,
  83   /* SSSE3 support required */
  84   CpuSSSE3,
  85   /* SSE4a support required */
  86   CpuSSE4a,
  87   /* ABM New Instructions required */
  88   CpuABM,
  89   /* SSE4.1 support required */
  90   CpuSSE4_1,
  91   /* SSE4.2 support required */
  92   CpuSSE4_2,
  93   /* AVX support required */
  94   CpuAVX,
  95   /* AVX2 support required */
  96   CpuAVX2,
  97   /* Intel L1OM support required */
  98   CpuL1OM,
  99   /* Intel K1OM support required */
 100   CpuK1OM,
 101   /* Xsave/xrstor New Instructions support required */
 102   CpuXsave,
 103   /* Xsaveopt New Instructions support required */
 104   CpuXsaveopt,
 105   /* AES support required */
 106   CpuAES,
 107   /* PCLMUL support required */
 108   CpuPCLMUL,
 109   /* FMA support required */
 110   CpuFMA,
 111   /* FMA4 support required */
 112   CpuFMA4,
 113   /* XOP support required */
 114   CpuXOP,
 115   /* LWP support required */
 116   CpuLWP,
 117   /* BMI support required */
 118   CpuBMI,
 119   /* TBM support required */
 120   CpuTBM,
 121   /* MOVBE Instruction support required */
 122   CpuMovbe,
 123   /* EPT Instructions required */
 124   CpuEPT,
 125   /* RDTSCP Instruction support required */
 126   CpuRdtscp,
 127   /* FSGSBASE Instructions required */
 128   CpuFSGSBase,
 129   /* RDRND Instructions required */
 130   CpuRdRnd,
 131   /* F16C Instructions required */
 132   CpuF16C,
 133   /* Intel BMI2 support required */
 134   CpuBMI2,
 135   /* LZCNT support required */
 136   CpuLZCNT,
 137   /* HLE support required */
 138   CpuHLE,
 139   /* RTM support required */
 140   CpuRTM,
 141   /* INVPCID Instructions required */
 142   CpuINVPCID,
 143   /* VMFUNC Instruction required */
 144   CpuVMFUNC,
 145   /* 64bit support available, used by -march= in assembler.  */
 146   CpuLM,
 147   /* 64bit support required  */
 148   Cpu64,
 149   /* Not supported in the 64bit mode  */
 150   CpuNo64,
 151   /* The last bitfield in i386_cpu_flags.  */
 152   CpuMax = CpuNo64
 153 };
 154
 155 #define CpuNumOfUints \
 156   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 157 #define CpuNumOfBits \
 158   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 159
 160 /* If you get a compiler error for zero width of the unused field,
 161    comment it out.  */
 162 #define CpuUnused       (CpuMax + 1)
 163
 164 /* We can check if an instruction is available with array instead
 165    of bitfield. */
 166 typedef union i386_cpu_flags
 167 {
 168   struct
 169     {
 170       unsigned int cpui186:1;
 171       unsigned int cpui286:1;
 172       unsigned int cpui386:1;
 173       unsigned int cpui486:1;
 174       unsigned int cpui586:1;
 175       unsigned int cpui686:1;
 176       unsigned int cpuclflush:1;
 177       unsigned int cpunop:1;
 178       unsigned int cpusyscall:1;
 179       unsigned int cpu8087:1;
 180       unsigned int cpu287:1;
 181       unsigned int cpu387:1;
 182       unsigned int cpu687:1;
 183       unsigned int cpufisttp:1;
 184       unsigned int cpummx:1;
 185       unsigned int cpusse:1;
 186       unsigned int cpusse2:1;
 187       unsigned int cpua3dnow:1;
 188       unsigned int cpua3dnowa:1;
 189       unsigned int cpusse3:1;
 190       unsigned int cpupadlock:1;
 191       unsigned int cpusvme:1;
 192       unsigned int cpuvmx:1;
 193       unsigned int cpusmx:1;
 194       unsigned int cpussse3:1;
 195       unsigned int cpusse4a:1;
 196       unsigned int cpuabm:1;
 197       unsigned int cpusse4_1:1;
 198       unsigned int cpusse4_2:1;
 199       unsigned int cpuavx:1;
 200       unsigned int cpuavx2:1;
 201       unsigned int cpul1om:1;
 202       unsigned int cpuk1om:1;
 203       unsigned int cpuxsave:1;
 204       unsigned int cpuxsaveopt:1;
 205       unsigned int cpuaes:1;
 206       unsigned int cpupclmul:1;
 207       unsigned int cpufma:1;
 208       unsigned int cpufma4:1;
 209       unsigned int cpuxop:1;
 210       unsigned int cpulwp:1;
 211       unsigned int cpubmi:1;
 212       unsigned int cputbm:1;
 213       unsigned int cpumovbe:1;
 214       unsigned int cpuept:1;
 215       unsigned int cpurdtscp:1;
 216       unsigned int cpufsgsbase:1;
 217       unsigned int cpurdrnd:1;
 218       unsigned int cpuf16c:1;
 219       unsigned int cpubmi2:1;
 220       unsigned int cpulzcnt:1;
 221       unsigned int cpuhle:1;
 222       unsigned int cpurtm:1;
 223       unsigned int cpuinvpcid:1;
 224       unsigned int cpuvmfunc:1;
 225       unsigned int cpulm:1;
 226       unsigned int cpu64:1;
 227       unsigned int cpuno64:1;
 228 #ifdef CpuUnused
 229       unsigned int unused:(CpuNumOfBits - CpuUnused);
 230 #endif
 231     } bitfield;
 232   unsigned int array[CpuNumOfUints];
 233 } i386_cpu_flags;
 234
 235 /* Position of opcode_modifier bits.  */
 236
 237 enum
 238 {
 239   /* has direction bit. */
 240   D = 0,
 241   /* set if operands can be words or dwords encoded the canonical way */
 242   W,
 243   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 244      operand in encoding.  */
 245   S,
 246   /* insn has a modrm byte. */
 247   Modrm,
 248   /* register is in low 3 bits of opcode */
 249   ShortForm,
 250   /* special case for jump insns.  */
 251   Jump,
 252   /* call and jump */
 253   JumpDword,
 254   /* loop and jecxz */
 255   JumpByte,
 256   /* special case for intersegment leaps/calls */
 257   JumpInterSegment,
 258   /* FP insn memory format bit, sized by 0x4 */
 259   FloatMF,
 260   /* src/dest swap for floats. */
 261   FloatR,
 262   /* has float insn direction bit. */
 263   FloatD,
 264   /* needs size prefix if in 32-bit mode */
 265   Size16,
 266   /* needs size prefix if in 16-bit mode */
 267   Size32,
 268   /* needs size prefix if in 64-bit mode */
 269   Size64,
 270   /* check register size.  */
 271   CheckRegSize,
 272   /* instruction ignores operand size prefix and in Intel mode ignores
 273      mnemonic size suffix check.  */
 274   IgnoreSize,
 275   /* default insn size depends on mode */
 276   DefaultSize,
 277   /* b suffix on instruction illegal */
 278   No_bSuf,
 279   /* w suffix on instruction illegal */
 280   No_wSuf,
 281   /* l suffix on instruction illegal */
 282   No_lSuf,
 283   /* s suffix on instruction illegal */
 284   No_sSuf,
 285   /* q suffix on instruction illegal */
 286   No_qSuf,
 287   /* long double suffix on instruction illegal */
 288   No_ldSuf,
 289   /* instruction needs FWAIT */
 290   FWait,
 291   /* quick test for string instructions */
 292   IsString,
 293   /* quick test for lockable instructions */
 294   IsLockable,
 295   /* fake an extra reg operand for clr, imul and special register
 296      processing for some instructions.  */
 297   RegKludge,
 298   /* The first operand must be xmm0 */
 299   FirstXmm0,
 300   /* An implicit xmm0 as the first operand */
 301   Implicit1stXmm0,
 302   /* The HLE prefix is OK:
 303      1. With a LOCK prefix.
 304      2. With or without a LOCK prefix.
 305      3. With a RELEASE (0xf3) prefix.
 306    */
 307 #define HLEPrefixNone           0
 308 #define HLEPrefixLock           1
 309 #define HLEPrefixAny            2
 310 #define HLEPrefixRelease        3
 311   HLEPrefixOk,
 312   /* An instruction on which a "rep" prefix is acceptable.  */
 313   RepPrefixOk,
 314   /* Convert to DWORD */
 315   ToDword,
 316   /* Convert to QWORD */
 317   ToQword,
 318   /* Address prefix changes operand 0 */
 319   AddrPrefixOp0,
 320   /* opcode is a prefix */
 321   IsPrefix,
 322   /* instruction has extension in 8 bit imm */
 323   ImmExt,
 324   /* instruction don't need Rex64 prefix.  */
 325   NoRex64,
 326   /* instruction require Rex64 prefix.  */
 327   Rex64,
 328   /* deprecated fp insn, gets a warning */
 329   Ugh,
 330   /* insn has VEX prefix:
 331         1: 128bit VEX prefix.
 332         2: 256bit VEX prefix.
 333         3: Scalar VEX prefix.
 334    */
 335 #define VEX128          1
 336 #define VEX256          2
 337 #define VEXScalar       3
 338   Vex,
 339   /* How to encode VEX.vvvv:
 340      0: VEX.vvvv must be 1111b.
 341      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 342         the content of source registers will be preserved.
 343         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 344         where the content of first source register will be overwritten
 345         by the result.
 346         VEX.NDD2.  The second destination register operand is encoded in
 347         VEX.vvvv for instructions with 2 destination register operands.
 348         For assembler, there are no difference between VEX.NDS, VEX.DDS
 349         and VEX.NDD2.
 350      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 351      instructions with 1 destination register operand.
 352      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 353         of the operands can access a memory location.
 354    */
 355 #define VEXXDS  1
 356 #define VEXNDD  2
 357 #define VEXLWP  3
 358   VexVVVV,
 359   /* How the VEX.W bit is used:
 360      0: Set by the REX.W bit.
 361      1: VEX.W0.  Should always be 0.
 362      2: VEX.W1.  Should always be 1.
 363    */
 364 #define VEXW0   1
 365 #define VEXW1   2
 366   VexW,
 367   /* VEX opcode prefix:
 368      0: VEX 0x0F opcode prefix.
 369      1: VEX 0x0F38 opcode prefix.
 370      2: VEX 0x0F3A opcode prefix
 371      3: XOP 0x08 opcode prefix.
 372      4: XOP 0x09 opcode prefix
 373      5: XOP 0x0A opcode prefix.
 374    */
 375 #define VEX0F           0
 376 #define VEX0F38         1
 377 #define VEX0F3A         2
 378 #define XOP08           3
 379 #define XOP09           4
 380 #define XOP0A           5
 381   VexOpcode,
 382   /* number of VEX source operands:
 383      0: <= 2 source operands.
 384      1: 2 XOP source operands.
 385      2: 3 source operands.
 386    */
 387 #define XOP2SOURCES     1
 388 #define VEX3SOURCES     2
 389   VexSources,
 390   /* instruction has VEX 8 bit imm */
 391   VexImmExt,
 392   /* Instruction with vector SIB byte:
 393         1: 128bit vector register.
 394         2: 256bit vector register.
 395    */
 396 #define VecSIB128       1
 397 #define VecSIB256       2
 398   VecSIB,
 399   /* SSE to AVX support required */
 400   SSE2AVX,
 401   /* No AVX equivalent */
 402   NoAVX,
 403   /* Compatible with old (<= 2.8.1) versions of gcc  */
 404   OldGcc,
 405   /* AT&T mnemonic.  */
 406   ATTMnemonic,
 407   /* AT&T syntax.  */
 408   ATTSyntax,
 409   /* Intel syntax.  */
 410   IntelSyntax,
 411   /* The last bitfield in i386_opcode_modifier.  */
 412   Opcode_Modifier_Max
 413 };
 414
 415 typedef struct i386_opcode_modifier
 416 {
 417   unsigned int d:1;
 418   unsigned int w:1;
 419   unsigned int s:1;
 420   unsigned int modrm:1;
 421   unsigned int shortform:1;
 422   unsigned int jump:1;
 423   unsigned int jumpdword:1;
 424   unsigned int jumpbyte:1;
 425   unsigned int jumpintersegment:1;
 426   unsigned int floatmf:1;
 427   unsigned int floatr:1;
 428   unsigned int floatd:1;
 429   unsigned int size16:1;
 430   unsigned int size32:1;
 431   unsigned int size64:1;
 432   unsigned int checkregsize:1;
 433   unsigned int ignoresize:1;
 434   unsigned int defaultsize:1;
 435   unsigned int no_bsuf:1;
 436   unsigned int no_wsuf:1;
 437   unsigned int no_lsuf:1;
 438   unsigned int no_ssuf:1;
 439   unsigned int no_qsuf:1;
 440   unsigned int no_ldsuf:1;
 441   unsigned int fwait:1;
 442   unsigned int isstring:1;
 443   unsigned int islockable:1;
 444   unsigned int regkludge:1;
 445   unsigned int firstxmm0:1;
 446   unsigned int implicit1stxmm0:1;
 447   unsigned int hleprefixok:2;
 448   unsigned int repprefixok:1;
 449   unsigned int todword:1;
 450   unsigned int toqword:1;
 451   unsigned int addrprefixop0:1;
 452   unsigned int isprefix:1;
 453   unsigned int immext:1;
 454   unsigned int norex64:1;
 455   unsigned int rex64:1;
 456   unsigned int ugh:1;
 457   unsigned int vex:2;
 458   unsigned int vexvvvv:2;
 459   unsigned int vexw:2;
 460   unsigned int vexopcode:3;
 461   unsigned int vexsources:2;
 462   unsigned int veximmext:1;
 463   unsigned int vecsib:2;
 464   unsigned int sse2avx:1;
 465   unsigned int noavx:1;
 466   unsigned int oldgcc:1;
 467   unsigned int attmnemonic:1;
 468   unsigned int attsyntax:1;
 469   unsigned int intelsyntax:1;
 470 } i386_opcode_modifier;
 471
 472 /* Position of operand_type bits.  */
 473
 474 enum
 475 {
 476   /* 8bit register */
 477   Reg8 = 0,
 478   /* 16bit register */
 479   Reg16,
 480   /* 32bit register */
 481   Reg32,
 482   /* 64bit register */
 483   Reg64,
 484   /* Floating pointer stack register */
 485   FloatReg,
 486   /* MMX register */
 487   RegMMX,
 488   /* SSE register */
 489   RegXMM,
 490   /* AVX registers */
 491   RegYMM,
 492   /* Control register */
 493   Control,
 494   /* Debug register */
 495   Debug,
 496   /* Test register */
 497   Test,
 498   /* 2 bit segment register */
 499   SReg2,
 500   /* 3 bit segment register */
 501   SReg3,
 502   /* 1 bit immediate */
 503   Imm1,
 504   /* 8 bit immediate */
 505   Imm8,
 506   /* 8 bit immediate sign extended */
 507   Imm8S,
 508   /* 16 bit immediate */
 509   Imm16,
 510   /* 32 bit immediate */
 511   Imm32,
 512   /* 32 bit immediate sign extended */
 513   Imm32S,
 514   /* 64 bit immediate */
 515   Imm64,
 516   /* 8bit/16bit/32bit displacements are used in different ways,
 517      depending on the instruction.  For jumps, they specify the
 518      size of the PC relative displacement, for instructions with
 519      memory operand, they specify the size of the offset relative
 520      to the base register, and for instructions with memory offset
 521      such as `mov 1234,%al' they specify the size of the offset
 522      relative to the segment base.  */
 523   /* 8 bit displacement */
 524   Disp8,
 525   /* 16 bit displacement */
 526   Disp16,
 527   /* 32 bit displacement */
 528   Disp32,
 529   /* 32 bit signed displacement */
 530   Disp32S,
 531   /* 64 bit displacement */
 532   Disp64,
 533   /* Accumulator %al/%ax/%eax/%rax */
 534   Acc,
 535   /* Floating pointer top stack register %st(0) */
 536   FloatAcc,
 537   /* Register which can be used for base or index in memory operand.  */
 538   BaseIndex,
 539   /* Register to hold in/out port addr = dx */
 540   InOutPortReg,
 541   /* Register to hold shift count = cl */
 542   ShiftCount,
 543   /* Absolute address for jump.  */
 544   JumpAbsolute,
 545   /* String insn operand with fixed es segment */
 546   EsSeg,
 547   /* RegMem is for instructions with a modrm byte where the register
 548      destination operand should be encoded in the mod and regmem fields.
 549      Normally, it will be encoded in the reg field. We add a RegMem
 550      flag to the destination register operand to indicate that it should
 551      be encoded in the regmem field.  */
 552   RegMem,
 553   /* Memory.  */
 554   Mem,
 555   /* BYTE memory. */
 556   Byte,
 557   /* WORD memory. 2 byte */
 558   Word,
 559   /* DWORD memory. 4 byte */
 560   Dword,
 561   /* FWORD memory. 6 byte */
 562   Fword,
 563   /* QWORD memory. 8 byte */
 564   Qword,
 565   /* TBYTE memory. 10 byte */
 566   Tbyte,
 567   /* XMMWORD memory. */
 568   Xmmword,
 569   /* YMMWORD memory. */
 570   Ymmword,
 571   /* Unspecified memory size.  */
 572   Unspecified,
 573   /* Any memory size.  */
 574   Anysize,
 575
 576   /* Vector 4 bit immediate.  */
 577   Vec_Imm4,
 578
 579   /* The last bitfield in i386_operand_type.  */
 580   OTMax
 581 };
 582
 583 #define OTNumOfUints \
 584   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 585 #define OTNumOfBits \
 586   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 587
 588 /* If you get a compiler error for zero width of the unused field,
 589    comment it out.  */
 590 #define OTUnused                (OTMax + 1)
 591
 592 typedef union i386_operand_type
 593 {
 594   struct
 595     {
 596       unsigned int reg8:1;
 597       unsigned int reg16:1;
 598       unsigned int reg32:1;
 599       unsigned int reg64:1;
 600       unsigned int floatreg:1;
 601       unsigned int regmmx:1;
 602       unsigned int regxmm:1;
 603       unsigned int regymm:1;
 604       unsigned int control:1;
 605       unsigned int debug:1;
 606       unsigned int test:1;
 607       unsigned int sreg2:1;
 608       unsigned int sreg3:1;
 609       unsigned int imm1:1;
 610       unsigned int imm8:1;
 611       unsigned int imm8s:1;
 612       unsigned int imm16:1;
 613       unsigned int imm32:1;
 614       unsigned int imm32s:1;
 615       unsigned int imm64:1;
 616       unsigned int disp8:1;
 617       unsigned int disp16:1;
 618       unsigned int disp32:1;
 619       unsigned int disp32s:1;
 620       unsigned int disp64:1;
 621       unsigned int acc:1;
 622       unsigned int floatacc:1;
 623       unsigned int baseindex:1;
 624       unsigned int inoutportreg:1;
 625       unsigned int shiftcount:1;
 626       unsigned int jumpabsolute:1;
 627       unsigned int esseg:1;
 628       unsigned int regmem:1;
 629       unsigned int mem:1;
 630       unsigned int byte:1;
 631       unsigned int word:1;
 632       unsigned int dword:1;
 633       unsigned int fword:1;
 634       unsigned int qword:1;
 635       unsigned int tbyte:1;
 636       unsigned int xmmword:1;
 637       unsigned int ymmword:1;
 638       unsigned int unspecified:1;
 639       unsigned int anysize:1;
 640       unsigned int vec_imm4:1;
 641 #ifdef OTUnused
 642       unsigned int unused:(OTNumOfBits - OTUnused);
 643 #endif
 644     } bitfield;
 645   unsigned int array[OTNumOfUints];
 646 } i386_operand_type;
 647
 648 typedef struct insn_template
 649 {
 650   /* instruction name sans width suffix ("mov" for movl insns) */
 651   char *name;
 652
 653   /* how many operands */
 654   unsigned int operands;
 655
 656   /* base_opcode is the fundamental opcode byte without optional
 657      prefix(es).  */
 658   unsigned int base_opcode;
 659 #define Opcode_D        0x2 /* Direction bit:
 660                                set if Reg --> Regmem;
 661                                unset if Regmem --> Reg. */
 662 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 663 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 664
 665   /* extension_opcode is the 3 bit extension for group <n> insns.
 666      This field is also used to store the 8-bit opcode suffix for the
 667      AMD 3DNow! instructions.
 668      If this template has no extension opcode (the usual case) use None
 669      Instructions */
 670   unsigned int extension_opcode;
 671 #define None 0xffff             /* If no extension_opcode is possible.  */
 672
 673   /* Opcode length.  */
 674   unsigned char opcode_length;
 675
 676   /* cpu feature flags */
 677   i386_cpu_flags cpu_flags;
 678
 679   /* the bits in opcode_modifier are used to generate the final opcode from
 680      the base_opcode.  These bits also are used to detect alternate forms of
 681      the same instruction */
 682   i386_opcode_modifier opcode_modifier;
 683
 684   /* operand_types[i] describes the type of operand i.  This is made
 685      by OR'ing together all of the possible type masks.  (e.g.
 686      'operand_types[i] = Reg|Imm' specifies that operand i can be
 687      either a register or an immediate operand.  */
 688   i386_operand_type operand_types[MAX_OPERANDS];
 689 }
 690 insn_template;
 691
 692 extern const insn_template i386_optab[];
 693
 694 /* these are for register name --> number & type hash lookup */
 695 typedef struct
 696 {
 697   char *reg_name;
 698   i386_operand_type reg_type;
 699   unsigned char reg_flags;
 700 #define RegRex      0x1  /* Extended register.  */
 701 #define RegRex64    0x2  /* Extended 8 bit register.  */
 702   unsigned char reg_num;
 703 #define RegRip  ((unsigned char ) ~0)
 704 #define RegEip  (RegRip - 1)
 705 /* EIZ and RIZ are fake index registers.  */
 706 #define RegEiz  (RegEip - 1)
 707 #define RegRiz  (RegEiz - 1)
 708 /* FLAT is a fake segment register (Intel mode).  */
 709 #define RegFlat     ((unsigned char) ~0)
 710   signed char dw2_regnum[2];
 711 #define Dw2Inval (-1)
 712 }
 713 reg_entry;
 714
 715 /* Entries in i386_regtab.  */
 716 #define REGNAM_AL 1
 717 #define REGNAM_AX 25
 718 #define REGNAM_EAX 41
 719
 720 extern const reg_entry i386_regtab[];
 721 extern const unsigned int i386_regtab_size;
 722
 723 typedef struct
 724 {
 725   char *seg_name;
 726   unsigned int seg_prefix;
 727 }
 728 seg_entry;
 729
 730 extern const seg_entry cs;
 731 extern const seg_entry ds;
 732 extern const seg_entry ss;
 733 extern const seg_entry es;
 734 extern const seg_entry fs;
 735 extern const seg_entry gs;