opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2014 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel L1OM support required */
 106   CpuL1OM,
 107   /* Intel K1OM support required */
 108   CpuK1OM,
 109   /* Xsave/xrstor New Instructions support required */
 110   CpuXsave,
 111   /* Xsaveopt New Instructions support required */
 112   CpuXsaveopt,
 113   /* AES support required */
 114   CpuAES,
 115   /* PCLMUL support required */
 116   CpuPCLMUL,
 117   /* FMA support required */
 118   CpuFMA,
 119   /* FMA4 support required */
 120   CpuFMA4,
 121   /* XOP support required */
 122   CpuXOP,
 123   /* LWP support required */
 124   CpuLWP,
 125   /* BMI support required */
 126   CpuBMI,
 127   /* TBM support required */
 128   CpuTBM,
 129   /* MOVBE Instruction support required */
 130   CpuMovbe,
 131   /* CMPXCHG16B instruction support required.  */
 132   CpuCX16,
 133   /* EPT Instructions required */
 134   CpuEPT,
 135   /* RDTSCP Instruction support required */
 136   CpuRdtscp,
 137   /* FSGSBASE Instructions required */
 138   CpuFSGSBase,
 139   /* RDRND Instructions required */
 140   CpuRdRnd,
 141   /* F16C Instructions required */
 142   CpuF16C,
 143   /* Intel BMI2 support required */
 144   CpuBMI2,
 145   /* LZCNT support required */
 146   CpuLZCNT,
 147   /* HLE support required */
 148   CpuHLE,
 149   /* RTM support required */
 150   CpuRTM,
 151   /* INVPCID Instructions required */
 152   CpuINVPCID,
 153   /* VMFUNC Instruction required */
 154   CpuVMFUNC,
 155   /* Intel MPX Instructions required  */
 156   CpuMPX,
 157   /* 64bit support available, used by -march= in assembler.  */
 158   CpuLM,
 159   /* RDRSEED instruction required.  */
 160   CpuRDSEED,
 161   /* Multi-presisionn add-carry instructions are required.  */
 162   CpuADX,
 163   /* Supports prefetchw and prefetch instructions.  */
 164   CpuPRFCHW,
 165   /* SMAP instructions required.  */
 166   CpuSMAP,
 167   /* SHA instructions required.  */
 168   CpuSHA,
 169   /* VREX support required  */
 170   CpuVREX,
 171   /* CLFLUSHOPT instruction required */
 172   CpuClflushOpt,
 173   /* XSAVES/XRSTORS instruction required */
 174   CpuXSAVES,
 175   /* XSAVEC instruction required */
 176   CpuXSAVEC,
 177   /* PREFETCHWT1 instruction required */
 178   CpuPREFETCHWT1,
 179   /* 64bit support required  */
 180   Cpu64,
 181   /* Not supported in the 64bit mode  */
 182   CpuNo64,
 183   /* The last bitfield in i386_cpu_flags.  */
 184   CpuMax = CpuNo64
 185 };
 186
 187 #define CpuNumOfUints \
 188   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 189 #define CpuNumOfBits \
 190   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 191
 192 /* If you get a compiler error for zero width of the unused field,
 193    comment it out.  */
 194 #define CpuUnused       (CpuMax + 1)
 195
 196 /* We can check if an instruction is available with array instead
 197    of bitfield. */
 198 typedef union i386_cpu_flags
 199 {
 200   struct
 201     {
 202       unsigned int cpui186:1;
 203       unsigned int cpui286:1;
 204       unsigned int cpui386:1;
 205       unsigned int cpui486:1;
 206       unsigned int cpui586:1;
 207       unsigned int cpui686:1;
 208       unsigned int cpuclflush:1;
 209       unsigned int cpunop:1;
 210       unsigned int cpusyscall:1;
 211       unsigned int cpu8087:1;
 212       unsigned int cpu287:1;
 213       unsigned int cpu387:1;
 214       unsigned int cpu687:1;
 215       unsigned int cpufisttp:1;
 216       unsigned int cpummx:1;
 217       unsigned int cpusse:1;
 218       unsigned int cpusse2:1;
 219       unsigned int cpua3dnow:1;
 220       unsigned int cpua3dnowa:1;
 221       unsigned int cpusse3:1;
 222       unsigned int cpupadlock:1;
 223       unsigned int cpusvme:1;
 224       unsigned int cpuvmx:1;
 225       unsigned int cpusmx:1;
 226       unsigned int cpussse3:1;
 227       unsigned int cpusse4a:1;
 228       unsigned int cpuabm:1;
 229       unsigned int cpusse4_1:1;
 230       unsigned int cpusse4_2:1;
 231       unsigned int cpuavx:1;
 232       unsigned int cpuavx2:1;
 233       unsigned int cpuavx512f:1;
 234       unsigned int cpuavx512cd:1;
 235       unsigned int cpuavx512er:1;
 236       unsigned int cpuavx512pf:1;
 237       unsigned int cpul1om:1;
 238       unsigned int cpuk1om:1;
 239       unsigned int cpuxsave:1;
 240       unsigned int cpuxsaveopt:1;
 241       unsigned int cpuaes:1;
 242       unsigned int cpupclmul:1;
 243       unsigned int cpufma:1;
 244       unsigned int cpufma4:1;
 245       unsigned int cpuxop:1;
 246       unsigned int cpulwp:1;
 247       unsigned int cpubmi:1;
 248       unsigned int cputbm:1;
 249       unsigned int cpumovbe:1;
 250       unsigned int cpucx16:1;
 251       unsigned int cpuept:1;
 252       unsigned int cpurdtscp:1;
 253       unsigned int cpufsgsbase:1;
 254       unsigned int cpurdrnd:1;
 255       unsigned int cpuf16c:1;
 256       unsigned int cpubmi2:1;
 257       unsigned int cpulzcnt:1;
 258       unsigned int cpuhle:1;
 259       unsigned int cpurtm:1;
 260       unsigned int cpuinvpcid:1;
 261       unsigned int cpuvmfunc:1;
 262       unsigned int cpumpx:1;
 263       unsigned int cpulm:1;
 264       unsigned int cpurdseed:1;
 265       unsigned int cpuadx:1;
 266       unsigned int cpuprfchw:1;
 267       unsigned int cpusmap:1;
 268       unsigned int cpusha:1;
 269       unsigned int cpuvrex:1;
 270       unsigned int cpuclflushopt:1;
 271       unsigned int cpuxsaves:1;
 272       unsigned int cpuxsavec:1;
 273       unsigned int cpuprefetchwt1:1;
 274       unsigned int cpu64:1;
 275       unsigned int cpuno64:1;
 276 #ifdef CpuUnused
 277       unsigned int unused:(CpuNumOfBits - CpuUnused);
 278 #endif
 279     } bitfield;
 280   unsigned int array[CpuNumOfUints];
 281 } i386_cpu_flags;
 282
 283 /* Position of opcode_modifier bits.  */
 284
 285 enum
 286 {
 287   /* has direction bit. */
 288   D = 0,
 289   /* set if operands can be words or dwords encoded the canonical way */
 290   W,
 291   /* Skip the current insn and use the next insn in i386-opc.tbl to swap
 292      operand in encoding.  */
 293   S,
 294   /* insn has a modrm byte. */
 295   Modrm,
 296   /* register is in low 3 bits of opcode */
 297   ShortForm,
 298   /* special case for jump insns.  */
 299   Jump,
 300   /* call and jump */
 301   JumpDword,
 302   /* loop and jecxz */
 303   JumpByte,
 304   /* special case for intersegment leaps/calls */
 305   JumpInterSegment,
 306   /* FP insn memory format bit, sized by 0x4 */
 307   FloatMF,
 308   /* src/dest swap for floats. */
 309   FloatR,
 310   /* has float insn direction bit. */
 311   FloatD,
 312   /* needs size prefix if in 32-bit mode */
 313   Size16,
 314   /* needs size prefix if in 16-bit mode */
 315   Size32,
 316   /* needs size prefix if in 64-bit mode */
 317   Size64,
 318   /* check register size.  */
 319   CheckRegSize,
 320   /* instruction ignores operand size prefix and in Intel mode ignores
 321      mnemonic size suffix check.  */
 322   IgnoreSize,
 323   /* default insn size depends on mode */
 324   DefaultSize,
 325   /* b suffix on instruction illegal */
 326   No_bSuf,
 327   /* w suffix on instruction illegal */
 328   No_wSuf,
 329   /* l suffix on instruction illegal */
 330   No_lSuf,
 331   /* s suffix on instruction illegal */
 332   No_sSuf,
 333   /* q suffix on instruction illegal */
 334   No_qSuf,
 335   /* long double suffix on instruction illegal */
 336   No_ldSuf,
 337   /* instruction needs FWAIT */
 338   FWait,
 339   /* quick test for string instructions */
 340   IsString,
 341   /* quick test if branch instruction is MPX supported */
 342   BNDPrefixOk,
 343   /* quick test for lockable instructions */
 344   IsLockable,
 345   /* fake an extra reg operand for clr, imul and special register
 346      processing for some instructions.  */
 347   RegKludge,
 348   /* The first operand must be xmm0 */
 349   FirstXmm0,
 350   /* An implicit xmm0 as the first operand */
 351   Implicit1stXmm0,
 352   /* The HLE prefix is OK:
 353      1. With a LOCK prefix.
 354      2. With or without a LOCK prefix.
 355      3. With a RELEASE (0xf3) prefix.
 356    */
 357 #define HLEPrefixNone           0
 358 #define HLEPrefixLock           1
 359 #define HLEPrefixAny            2
 360 #define HLEPrefixRelease        3
 361   HLEPrefixOk,
 362   /* An instruction on which a "rep" prefix is acceptable.  */
 363   RepPrefixOk,
 364   /* Convert to DWORD */
 365   ToDword,
 366   /* Convert to QWORD */
 367   ToQword,
 368   /* Address prefix changes operand 0 */
 369   AddrPrefixOp0,
 370   /* opcode is a prefix */
 371   IsPrefix,
 372   /* instruction has extension in 8 bit imm */
 373   ImmExt,
 374   /* instruction don't need Rex64 prefix.  */
 375   NoRex64,
 376   /* instruction require Rex64 prefix.  */
 377   Rex64,
 378   /* deprecated fp insn, gets a warning */
 379   Ugh,
 380   /* insn has VEX prefix:
 381         1: 128bit VEX prefix.
 382         2: 256bit VEX prefix.
 383         3: Scalar VEX prefix.
 384    */
 385 #define VEX128          1
 386 #define VEX256          2
 387 #define VEXScalar       3
 388   Vex,
 389   /* How to encode VEX.vvvv:
 390      0: VEX.vvvv must be 1111b.
 391      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 392         the content of source registers will be preserved.
 393         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 394         where the content of first source register will be overwritten
 395         by the result.
 396         VEX.NDD2.  The second destination register operand is encoded in
 397         VEX.vvvv for instructions with 2 destination register operands.
 398         For assembler, there are no difference between VEX.NDS, VEX.DDS
 399         and VEX.NDD2.
 400      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 401      instructions with 1 destination register operand.
 402      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 403         of the operands can access a memory location.
 404    */
 405 #define VEXXDS  1
 406 #define VEXNDD  2
 407 #define VEXLWP  3
 408   VexVVVV,
 409   /* How the VEX.W bit is used:
 410      0: Set by the REX.W bit.
 411      1: VEX.W0.  Should always be 0.
 412      2: VEX.W1.  Should always be 1.
 413    */
 414 #define VEXW0   1
 415 #define VEXW1   2
 416   VexW,
 417   /* VEX opcode prefix:
 418      0: VEX 0x0F opcode prefix.
 419      1: VEX 0x0F38 opcode prefix.
 420      2: VEX 0x0F3A opcode prefix
 421      3: XOP 0x08 opcode prefix.
 422      4: XOP 0x09 opcode prefix
 423      5: XOP 0x0A opcode prefix.
 424    */
 425 #define VEX0F           0
 426 #define VEX0F38         1
 427 #define VEX0F3A         2
 428 #define XOP08           3
 429 #define XOP09           4
 430 #define XOP0A           5
 431   VexOpcode,
 432   /* number of VEX source operands:
 433      0: <= 2 source operands.
 434      1: 2 XOP source operands.
 435      2: 3 source operands.
 436    */
 437 #define XOP2SOURCES     1
 438 #define VEX3SOURCES     2
 439   VexSources,
 440   /* instruction has VEX 8 bit imm */
 441   VexImmExt,
 442   /* Instruction with vector SIB byte:
 443         1: 128bit vector register.
 444         2: 256bit vector register.
 445         3: 512bit vector register.
 446    */
 447 #define VecSIB128       1
 448 #define VecSIB256       2
 449 #define VecSIB512       3
 450   VecSIB,
 451   /* SSE to AVX support required */
 452   SSE2AVX,
 453   /* No AVX equivalent */
 454   NoAVX,
 455
 456   /* insn has EVEX prefix:
 457         1: 512bit EVEX prefix.
 458         2: 128bit EVEX prefix.
 459         3: 256bit EVEX prefix.
 460         4: Length-ignored (LIG) EVEX prefix.
 461    */
 462 #define EVEX512                1
 463 #define EVEX128                2
 464 #define EVEX256                3
 465 #define EVEXLIG                4
 466   EVex,
 467
 468   /* AVX512 masking support:
 469         1: Zeroing-masking.
 470         2: Merging-masking.
 471         3: Both zeroing and merging masking.
 472    */
 473 #define ZEROING_MASKING 1
 474 #define MERGING_MASKING 2
 475 #define BOTH_MASKING    3
 476   Masking,
 477
 478   /* Input element size of vector insn:
 479         0: 32bit.
 480         1: 64bit.
 481    */
 482   VecESize,
 483
 484   /* Broadcast factor.
 485         0: No broadcast.
 486         1: 1to16 broadcast.
 487         2: 1to8 broadcast.
 488    */
 489 #define NO_BROADCAST    0
 490 #define BROADCAST_1TO16 1
 491 #define BROADCAST_1TO8  2
 492   Broadcast,
 493
 494   /* Static rounding control is supported.  */
 495   StaticRounding,
 496
 497   /* Supress All Exceptions is supported.  */
 498   SAE,
 499
 500   /* Copressed Disp8*N attribute.  */
 501   Disp8MemShift,
 502
 503   /* Default mask isn't allowed.  */
 504   NoDefMask,
 505
 506   /* Compatible with old (<= 2.8.1) versions of gcc  */
 507   OldGcc,
 508   /* AT&T mnemonic.  */
 509   ATTMnemonic,
 510   /* AT&T syntax.  */
 511   ATTSyntax,
 512   /* Intel syntax.  */
 513   IntelSyntax,
 514   /* The last bitfield in i386_opcode_modifier.  */
 515   Opcode_Modifier_Max
 516 };
 517
 518 typedef struct i386_opcode_modifier
 519 {
 520   unsigned int d:1;
 521   unsigned int w:1;
 522   unsigned int s:1;
 523   unsigned int modrm:1;
 524   unsigned int shortform:1;
 525   unsigned int jump:1;
 526   unsigned int jumpdword:1;
 527   unsigned int jumpbyte:1;
 528   unsigned int jumpintersegment:1;
 529   unsigned int floatmf:1;
 530   unsigned int floatr:1;
 531   unsigned int floatd:1;
 532   unsigned int size16:1;
 533   unsigned int size32:1;
 534   unsigned int size64:1;
 535   unsigned int checkregsize:1;
 536   unsigned int ignoresize:1;
 537   unsigned int defaultsize:1;
 538   unsigned int no_bsuf:1;
 539   unsigned int no_wsuf:1;
 540   unsigned int no_lsuf:1;
 541   unsigned int no_ssuf:1;
 542   unsigned int no_qsuf:1;
 543   unsigned int no_ldsuf:1;
 544   unsigned int fwait:1;
 545   unsigned int isstring:1;
 546   unsigned int bndprefixok:1;
 547   unsigned int islockable:1;
 548   unsigned int regkludge:1;
 549   unsigned int firstxmm0:1;
 550   unsigned int implicit1stxmm0:1;
 551   unsigned int hleprefixok:2;
 552   unsigned int repprefixok:1;
 553   unsigned int todword:1;
 554   unsigned int toqword:1;
 555   unsigned int addrprefixop0:1;
 556   unsigned int isprefix:1;
 557   unsigned int immext:1;
 558   unsigned int norex64:1;
 559   unsigned int rex64:1;
 560   unsigned int ugh:1;
 561   unsigned int vex:2;
 562   unsigned int vexvvvv:2;
 563   unsigned int vexw:2;
 564   unsigned int vexopcode:3;
 565   unsigned int vexsources:2;
 566   unsigned int veximmext:1;
 567   unsigned int vecsib:2;
 568   unsigned int sse2avx:1;
 569   unsigned int noavx:1;
 570   unsigned int evex:3;
 571   unsigned int masking:2;
 572   unsigned int vecesize:1;
 573   unsigned int broadcast:3;
 574   unsigned int staticrounding:1;
 575   unsigned int sae:1;
 576   unsigned int disp8memshift:3;
 577   unsigned int nodefmask:1;
 578   unsigned int oldgcc:1;
 579   unsigned int attmnemonic:1;
 580   unsigned int attsyntax:1;
 581   unsigned int intelsyntax:1;
 582 } i386_opcode_modifier;
 583
 584 /* Position of operand_type bits.  */
 585
 586 enum
 587 {
 588   /* 8bit register */
 589   Reg8 = 0,
 590   /* 16bit register */
 591   Reg16,
 592   /* 32bit register */
 593   Reg32,
 594   /* 64bit register */
 595   Reg64,
 596   /* Floating pointer stack register */
 597   FloatReg,
 598   /* MMX register */
 599   RegMMX,
 600   /* SSE register */
 601   RegXMM,
 602   /* AVX registers */
 603   RegYMM,
 604   /* AVX512 registers */
 605   RegZMM,
 606   /* Vector Mask registers */
 607   RegMask,
 608   /* Control register */
 609   Control,
 610   /* Debug register */
 611   Debug,
 612   /* Test register */
 613   Test,
 614   /* 2 bit segment register */
 615   SReg2,
 616   /* 3 bit segment register */
 617   SReg3,
 618   /* 1 bit immediate */
 619   Imm1,
 620   /* 8 bit immediate */
 621   Imm8,
 622   /* 8 bit immediate sign extended */
 623   Imm8S,
 624   /* 16 bit immediate */
 625   Imm16,
 626   /* 32 bit immediate */
 627   Imm32,
 628   /* 32 bit immediate sign extended */
 629   Imm32S,
 630   /* 64 bit immediate */
 631   Imm64,
 632   /* 8bit/16bit/32bit displacements are used in different ways,
 633      depending on the instruction.  For jumps, they specify the
 634      size of the PC relative displacement, for instructions with
 635      memory operand, they specify the size of the offset relative
 636      to the base register, and for instructions with memory offset
 637      such as `mov 1234,%al' they specify the size of the offset
 638      relative to the segment base.  */
 639   /* 8 bit displacement */
 640   Disp8,
 641   /* 16 bit displacement */
 642   Disp16,
 643   /* 32 bit displacement */
 644   Disp32,
 645   /* 32 bit signed displacement */
 646   Disp32S,
 647   /* 64 bit displacement */
 648   Disp64,
 649   /* Accumulator %al/%ax/%eax/%rax */
 650   Acc,
 651   /* Floating pointer top stack register %st(0) */
 652   FloatAcc,
 653   /* Register which can be used for base or index in memory operand.  */
 654   BaseIndex,
 655   /* Register to hold in/out port addr = dx */
 656   InOutPortReg,
 657   /* Register to hold shift count = cl */
 658   ShiftCount,
 659   /* Absolute address for jump.  */
 660   JumpAbsolute,
 661   /* String insn operand with fixed es segment */
 662   EsSeg,
 663   /* RegMem is for instructions with a modrm byte where the register
 664      destination operand should be encoded in the mod and regmem fields.
 665      Normally, it will be encoded in the reg field. We add a RegMem
 666      flag to the destination register operand to indicate that it should
 667      be encoded in the regmem field.  */
 668   RegMem,
 669   /* Memory.  */
 670   Mem,
 671   /* BYTE memory. */
 672   Byte,
 673   /* WORD memory. 2 byte */
 674   Word,
 675   /* DWORD memory. 4 byte */
 676   Dword,
 677   /* FWORD memory. 6 byte */
 678   Fword,
 679   /* QWORD memory. 8 byte */
 680   Qword,
 681   /* TBYTE memory. 10 byte */
 682   Tbyte,
 683   /* XMMWORD memory. */
 684   Xmmword,
 685   /* YMMWORD memory. */
 686   Ymmword,
 687   /* ZMMWORD memory.  */
 688   Zmmword,
 689   /* Unspecified memory size.  */
 690   Unspecified,
 691   /* Any memory size.  */
 692   Anysize,
 693
 694   /* Vector 4 bit immediate.  */
 695   Vec_Imm4,
 696
 697   /* Bound register.  */
 698   RegBND,
 699
 700   /* Vector 8bit displacement */
 701   Vec_Disp8,
 702
 703   /* The last bitfield in i386_operand_type.  */
 704   OTMax
 705 };
 706
 707 #define OTNumOfUints \
 708   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 709 #define OTNumOfBits \
 710   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 711
 712 /* If you get a compiler error for zero width of the unused field,
 713    comment it out.  */
 714 #define OTUnused                (OTMax + 1)
 715
 716 typedef union i386_operand_type
 717 {
 718   struct
 719     {
 720       unsigned int reg8:1;
 721       unsigned int reg16:1;
 722       unsigned int reg32:1;
 723       unsigned int reg64:1;
 724       unsigned int floatreg:1;
 725       unsigned int regmmx:1;
 726       unsigned int regxmm:1;
 727       unsigned int regymm:1;
 728       unsigned int regzmm:1;
 729       unsigned int regmask:1;
 730       unsigned int control:1;
 731       unsigned int debug:1;
 732       unsigned int test:1;
 733       unsigned int sreg2:1;
 734       unsigned int sreg3:1;
 735       unsigned int imm1:1;
 736       unsigned int imm8:1;
 737       unsigned int imm8s:1;
 738       unsigned int imm16:1;
 739       unsigned int imm32:1;
 740       unsigned int imm32s:1;
 741       unsigned int imm64:1;
 742       unsigned int disp8:1;
 743       unsigned int disp16:1;
 744       unsigned int disp32:1;
 745       unsigned int disp32s:1;
 746       unsigned int disp64:1;
 747       unsigned int acc:1;
 748       unsigned int floatacc:1;
 749       unsigned int baseindex:1;
 750       unsigned int inoutportreg:1;
 751       unsigned int shiftcount:1;
 752       unsigned int jumpabsolute:1;
 753       unsigned int esseg:1;
 754       unsigned int regmem:1;
 755       unsigned int mem:1;
 756       unsigned int byte:1;
 757       unsigned int word:1;
 758       unsigned int dword:1;
 759       unsigned int fword:1;
 760       unsigned int qword:1;
 761       unsigned int tbyte:1;
 762       unsigned int xmmword:1;
 763       unsigned int ymmword:1;
 764       unsigned int zmmword:1;
 765       unsigned int unspecified:1;
 766       unsigned int anysize:1;
 767       unsigned int vec_imm4:1;
 768       unsigned int regbnd:1;
 769       unsigned int vec_disp8:1;
 770 #ifdef OTUnused
 771       unsigned int unused:(OTNumOfBits - OTUnused);
 772 #endif
 773     } bitfield;
 774   unsigned int array[OTNumOfUints];
 775 } i386_operand_type;
 776
 777 typedef struct insn_template
 778 {
 779   /* instruction name sans width suffix ("mov" for movl insns) */
 780   char *name;
 781
 782   /* how many operands */
 783   unsigned int operands;
 784
 785   /* base_opcode is the fundamental opcode byte without optional
 786      prefix(es).  */
 787   unsigned int base_opcode;
 788 #define Opcode_D        0x2 /* Direction bit:
 789                                set if Reg --> Regmem;
 790                                unset if Regmem --> Reg. */
 791 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 792 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 793
 794   /* extension_opcode is the 3 bit extension for group <n> insns.
 795      This field is also used to store the 8-bit opcode suffix for the
 796      AMD 3DNow! instructions.
 797      If this template has no extension opcode (the usual case) use None
 798      Instructions */
 799   unsigned int extension_opcode;
 800 #define None 0xffff             /* If no extension_opcode is possible.  */
 801
 802   /* Opcode length.  */
 803   unsigned char opcode_length;
 804
 805   /* cpu feature flags */
 806   i386_cpu_flags cpu_flags;
 807
 808   /* the bits in opcode_modifier are used to generate the final opcode from
 809      the base_opcode.  These bits also are used to detect alternate forms of
 810      the same instruction */
 811   i386_opcode_modifier opcode_modifier;
 812
 813   /* operand_types[i] describes the type of operand i.  This is made
 814      by OR'ing together all of the possible type masks.  (e.g.
 815      'operand_types[i] = Reg|Imm' specifies that operand i can be
 816      either a register or an immediate operand.  */
 817   i386_operand_type operand_types[MAX_OPERANDS];
 818 }
 819 insn_template;
 820
 821 extern const insn_template i386_optab[];
 822
 823 /* these are for register name --> number & type hash lookup */
 824 typedef struct
 825 {
 826   char *reg_name;
 827   i386_operand_type reg_type;
 828   unsigned char reg_flags;
 829 #define RegRex      0x1  /* Extended register.  */
 830 #define RegRex64    0x2  /* Extended 8 bit register.  */
 831 #define RegVRex     0x4  /* Extended vector register.  */
 832   unsigned char reg_num;
 833 #define RegRip  ((unsigned char ) ~0)
 834 #define RegEip  (RegRip - 1)
 835 /* EIZ and RIZ are fake index registers.  */
 836 #define RegEiz  (RegEip - 1)
 837 #define RegRiz  (RegEiz - 1)
 838 /* FLAT is a fake segment register (Intel mode).  */
 839 #define RegFlat     ((unsigned char) ~0)
 840   signed char dw2_regnum[2];
 841 #define Dw2Inval (-1)
 842 }
 843 reg_entry;
 844
 845 /* Entries in i386_regtab.  */
 846 #define REGNAM_AL 1
 847 #define REGNAM_AX 25
 848 #define REGNAM_EAX 41
 849
 850 extern const reg_entry i386_regtab[];
 851 extern const unsigned int i386_regtab_size;
 852
 853 typedef struct
 854 {
 855   char *seg_name;
 856   unsigned int seg_prefix;
 857 }
 858 seg_entry;
 859
 860 extern const seg_entry cs;
 861 extern const seg_entry ds;
 862 extern const seg_entry ss;
 863 extern const seg_entry es;
 864 extern const seg_entry fs;
 865 extern const seg_entry gs;