opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2020 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CMOV Instruction support required */
  47   CpuCMOV,
  48   /* FXSR Instruction support required */
  49   CpuFXSR,
  50   /* CLFLUSH Instruction support required */
  51   CpuClflush,
  52   /* NOP Instruction support required */
  53   CpuNop,
  54   /* SYSCALL Instructions support required */
  55   CpuSYSCALL,
  56   /* Floating point support required */
  57   Cpu8087,
  58   /* i287 support required */
  59   Cpu287,
  60   /* i387 support required */
  61   Cpu387,
  62   /* i686 and floating point support required */
  63   Cpu687,
  64   /* SSE3 and floating point support required */
  65   CpuFISTTP,
  66   /* MMX support required */
  67   CpuMMX,
  68   /* SSE support required */
  69   CpuSSE,
  70   /* SSE2 support required */
  71   CpuSSE2,
  72   /* 3dnow! support required */
  73   Cpu3dnow,
  74   /* 3dnow! Extensions support required */
  75   Cpu3dnowA,
  76   /* SSE3 support required */
  77   CpuSSE3,
  78   /* VIA PadLock required */
  79   CpuPadLock,
  80   /* AMD Secure Virtual Machine Ext-s required */
  81   CpuSVME,
  82   /* VMX Instructions required */
  83   CpuVMX,
  84   /* SMX Instructions required */
  85   CpuSMX,
  86   /* SSSE3 support required */
  87   CpuSSSE3,
  88   /* SSE4a support required */
  89   CpuSSE4a,
  90   /* LZCNT support required */
  91   CpuLZCNT,
  92   /* POPCNT support required */
  93   CpuPOPCNT,
  94   /* SSE4.1 support required */
  95   CpuSSE4_1,
  96   /* SSE4.2 support required */
  97   CpuSSE4_2,
  98   /* AVX support required */
  99   CpuAVX,
 100   /* AVX2 support required */
 101   CpuAVX2,
 102   /* Intel AVX-512 Foundation Instructions support required */
 103   CpuAVX512F,
 104   /* Intel AVX-512 Conflict Detection Instructions support required */
 105   CpuAVX512CD,
 106   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 107      required */
 108   CpuAVX512ER,
 109   /* Intel AVX-512 Prefetch Instructions support required */
 110   CpuAVX512PF,
 111   /* Intel AVX-512 VL Instructions support required.  */
 112   CpuAVX512VL,
 113   /* Intel AVX-512 DQ Instructions support required.  */
 114   CpuAVX512DQ,
 115   /* Intel AVX-512 BW Instructions support required.  */
 116   CpuAVX512BW,
 117   /* Intel L1OM support required */
 118   CpuL1OM,
 119   /* Intel K1OM support required */
 120   CpuK1OM,
 121   /* Intel IAMCU support required */
 122   CpuIAMCU,
 123   /* Xsave/xrstor New Instructions support required */
 124   CpuXsave,
 125   /* Xsaveopt New Instructions support required */
 126   CpuXsaveopt,
 127   /* AES support required */
 128   CpuAES,
 129   /* PCLMUL support required */
 130   CpuPCLMUL,
 131   /* FMA support required */
 132   CpuFMA,
 133   /* FMA4 support required */
 134   CpuFMA4,
 135   /* XOP support required */
 136   CpuXOP,
 137   /* LWP support required */
 138   CpuLWP,
 139   /* BMI support required */
 140   CpuBMI,
 141   /* TBM support required */
 142   CpuTBM,
 143   /* MOVBE Instruction support required */
 144   CpuMovbe,
 145   /* CMPXCHG16B instruction support required.  */
 146   CpuCX16,
 147   /* EPT Instructions required */
 148   CpuEPT,
 149   /* RDTSCP Instruction support required */
 150   CpuRdtscp,
 151   /* FSGSBASE Instructions required */
 152   CpuFSGSBase,
 153   /* RDRND Instructions required */
 154   CpuRdRnd,
 155   /* F16C Instructions required */
 156   CpuF16C,
 157   /* Intel BMI2 support required */
 158   CpuBMI2,
 159   /* HLE support required */
 160   CpuHLE,
 161   /* RTM support required */
 162   CpuRTM,
 163   /* INVPCID Instructions required */
 164   CpuINVPCID,
 165   /* VMFUNC Instruction required */
 166   CpuVMFUNC,
 167   /* Intel MPX Instructions required  */
 168   CpuMPX,
 169   /* 64bit support available, used by -march= in assembler.  */
 170   CpuLM,
 171   /* RDRSEED instruction required.  */
 172   CpuRDSEED,
 173   /* Multi-presisionn add-carry instructions are required.  */
 174   CpuADX,
 175   /* Supports prefetchw and prefetch instructions.  */
 176   CpuPRFCHW,
 177   /* SMAP instructions required.  */
 178   CpuSMAP,
 179   /* SHA instructions required.  */
 180   CpuSHA,
 181   /* CLFLUSHOPT instruction required */
 182   CpuClflushOpt,
 183   /* XSAVES/XRSTORS instruction required */
 184   CpuXSAVES,
 185   /* XSAVEC instruction required */
 186   CpuXSAVEC,
 187   /* PREFETCHWT1 instruction required */
 188   CpuPREFETCHWT1,
 189   /* SE1 instruction required */
 190   CpuSE1,
 191   /* CLWB instruction required */
 192   CpuCLWB,
 193   /* Intel AVX-512 IFMA Instructions support required.  */
 194   CpuAVX512IFMA,
 195   /* Intel AVX-512 VBMI Instructions support required.  */
 196   CpuAVX512VBMI,
 197   /* Intel AVX-512 4FMAPS Instructions support required.  */
 198   CpuAVX512_4FMAPS,
 199   /* Intel AVX-512 4VNNIW Instructions support required.  */
 200   CpuAVX512_4VNNIW,
 201   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 202   CpuAVX512_VPOPCNTDQ,
 203   /* Intel AVX-512 VBMI2 Instructions support required.  */
 204   CpuAVX512_VBMI2,
 205   /* Intel AVX-512 VNNI Instructions support required.  */
 206   CpuAVX512_VNNI,
 207   /* Intel AVX-512 BITALG Instructions support required.  */
 208   CpuAVX512_BITALG,
 209   /* Intel AVX-512 BF16 Instructions support required.  */
 210   CpuAVX512_BF16,
 211   /* Intel AVX-512 VP2INTERSECT Instructions support required.  */
 212   CpuAVX512_VP2INTERSECT,
 213   /* TDX Instructions support required.  */
 214   CpuTDX,
 215   /* Intel AVX VNNI Instructions support required.  */
 216   CpuAVX_VNNI,
 217   /* mwaitx instruction required */
 218   CpuMWAITX,
 219   /* Clzero instruction required */
 220   CpuCLZERO,
 221   /* OSPKE instruction required */
 222   CpuOSPKE,
 223   /* RDPID instruction required */
 224   CpuRDPID,
 225   /* PTWRITE instruction required */
 226   CpuPTWRITE,
 227   /* CET instructions support required */
 228   CpuIBT,
 229   CpuSHSTK,
 230   /* AMX-INT8 instructions required */
 231   CpuAMX_INT8,
 232   /* AMX-BF16 instructions required */
 233   CpuAMX_BF16,
 234   /* AMX-TILE instructions required */
 235   CpuAMX_TILE,
 236   /* GFNI instructions required */
 237   CpuGFNI,
 238   /* VAES instructions required */
 239   CpuVAES,
 240   /* VPCLMULQDQ instructions required */
 241   CpuVPCLMULQDQ,
 242   /* WBNOINVD instructions required */
 243   CpuWBNOINVD,
 244   /* PCONFIG instructions required */
 245   CpuPCONFIG,
 246   /* WAITPKG instructions required */
 247   CpuWAITPKG,
 248   /* UINTR instructions required */
 249   CpuUINTR,
 250   /* CLDEMOTE instruction required */
 251   CpuCLDEMOTE,
 252   /* MOVDIRI instruction support required */
 253   CpuMOVDIRI,
 254   /* MOVDIRR64B instruction required */
 255   CpuMOVDIR64B,
 256   /* ENQCMD instruction required */
 257   CpuENQCMD,
 258   /* SERIALIZE instruction required */
 259   CpuSERIALIZE,
 260   /* RDPRU instruction required */
 261   CpuRDPRU,
 262   /* MCOMMIT instruction required */
 263   CpuMCOMMIT,
 264   /* SEV-ES instruction(s) required */
 265   CpuSEV_ES,
 266   /* TSXLDTRK instruction required */
 267   CpuTSXLDTRK,
 268   /* KL instruction support required */
 269   CpuKL,
 270   /* WideKL instruction support required */
 271   CpuWideKL,
 272   /* HRESET instruction required */
 273   CpuHRESET,
 274   /* 64bit support required  */
 275   Cpu64,
 276   /* Not supported in the 64bit mode  */
 277   CpuNo64,
 278   /* The last bitfield in i386_cpu_flags.  */
 279   CpuMax = CpuNo64
 280 };
 281
 282 #define CpuNumOfUints \
 283   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 284 #define CpuNumOfBits \
 285   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 286
 287 /* If you get a compiler error for zero width of the unused field,
 288    comment it out.  */
 289 #define CpuUnused       (CpuMax + 1)
 290
 291 /* We can check if an instruction is available with array instead
 292    of bitfield. */
 293 typedef union i386_cpu_flags
 294 {
 295   struct
 296     {
 297       unsigned int cpui186:1;
 298       unsigned int cpui286:1;
 299       unsigned int cpui386:1;
 300       unsigned int cpui486:1;
 301       unsigned int cpui586:1;
 302       unsigned int cpui686:1;
 303       unsigned int cpucmov:1;
 304       unsigned int cpufxsr:1;
 305       unsigned int cpuclflush:1;
 306       unsigned int cpunop:1;
 307       unsigned int cpusyscall:1;
 308       unsigned int cpu8087:1;
 309       unsigned int cpu287:1;
 310       unsigned int cpu387:1;
 311       unsigned int cpu687:1;
 312       unsigned int cpufisttp:1;
 313       unsigned int cpummx:1;
 314       unsigned int cpusse:1;
 315       unsigned int cpusse2:1;
 316       unsigned int cpua3dnow:1;
 317       unsigned int cpua3dnowa:1;
 318       unsigned int cpusse3:1;
 319       unsigned int cpupadlock:1;
 320       unsigned int cpusvme:1;
 321       unsigned int cpuvmx:1;
 322       unsigned int cpusmx:1;
 323       unsigned int cpussse3:1;
 324       unsigned int cpusse4a:1;
 325       unsigned int cpulzcnt:1;
 326       unsigned int cpupopcnt:1;
 327       unsigned int cpusse4_1:1;
 328       unsigned int cpusse4_2:1;
 329       unsigned int cpuavx:1;
 330       unsigned int cpuavx2:1;
 331       unsigned int cpuavx512f:1;
 332       unsigned int cpuavx512cd:1;
 333       unsigned int cpuavx512er:1;
 334       unsigned int cpuavx512pf:1;
 335       unsigned int cpuavx512vl:1;
 336       unsigned int cpuavx512dq:1;
 337       unsigned int cpuavx512bw:1;
 338       unsigned int cpul1om:1;
 339       unsigned int cpuk1om:1;
 340       unsigned int cpuiamcu:1;
 341       unsigned int cpuxsave:1;
 342       unsigned int cpuxsaveopt:1;
 343       unsigned int cpuaes:1;
 344       unsigned int cpupclmul:1;
 345       unsigned int cpufma:1;
 346       unsigned int cpufma4:1;
 347       unsigned int cpuxop:1;
 348       unsigned int cpulwp:1;
 349       unsigned int cpubmi:1;
 350       unsigned int cputbm:1;
 351       unsigned int cpumovbe:1;
 352       unsigned int cpucx16:1;
 353       unsigned int cpuept:1;
 354       unsigned int cpurdtscp:1;
 355       unsigned int cpufsgsbase:1;
 356       unsigned int cpurdrnd:1;
 357       unsigned int cpuf16c:1;
 358       unsigned int cpubmi2:1;
 359       unsigned int cpuhle:1;
 360       unsigned int cpurtm:1;
 361       unsigned int cpuinvpcid:1;
 362       unsigned int cpuvmfunc:1;
 363       unsigned int cpumpx:1;
 364       unsigned int cpulm:1;
 365       unsigned int cpurdseed:1;
 366       unsigned int cpuadx:1;
 367       unsigned int cpuprfchw:1;
 368       unsigned int cpusmap:1;
 369       unsigned int cpusha:1;
 370       unsigned int cpuclflushopt:1;
 371       unsigned int cpuxsaves:1;
 372       unsigned int cpuxsavec:1;
 373       unsigned int cpuprefetchwt1:1;
 374       unsigned int cpuse1:1;
 375       unsigned int cpuclwb:1;
 376       unsigned int cpuavx512ifma:1;
 377       unsigned int cpuavx512vbmi:1;
 378       unsigned int cpuavx512_4fmaps:1;
 379       unsigned int cpuavx512_4vnniw:1;
 380       unsigned int cpuavx512_vpopcntdq:1;
 381       unsigned int cpuavx512_vbmi2:1;
 382       unsigned int cpuavx512_vnni:1;
 383       unsigned int cpuavx512_bitalg:1;
 384       unsigned int cpuavx512_bf16:1;
 385       unsigned int cpuavx512_vp2intersect:1;
 386       unsigned int cputdx:1;
 387       unsigned int cpuavx_vnni:1;
 388       unsigned int cpumwaitx:1;
 389       unsigned int cpuclzero:1;
 390       unsigned int cpuospke:1;
 391       unsigned int cpurdpid:1;
 392       unsigned int cpuptwrite:1;
 393       unsigned int cpuibt:1;
 394       unsigned int cpushstk:1;
 395       unsigned int cpuamx_int8:1;
 396       unsigned int cpuamx_bf16:1;
 397       unsigned int cpuamx_tile:1;
 398       unsigned int cpugfni:1;
 399       unsigned int cpuvaes:1;
 400       unsigned int cpuvpclmulqdq:1;
 401       unsigned int cpuwbnoinvd:1;
 402       unsigned int cpupconfig:1;
 403       unsigned int cpuwaitpkg:1;
 404       unsigned int cpuuintr:1;
 405       unsigned int cpucldemote:1;
 406       unsigned int cpumovdiri:1;
 407       unsigned int cpumovdir64b:1;
 408       unsigned int cpuenqcmd:1;
 409       unsigned int cpuserialize:1;
 410       unsigned int cpurdpru:1;
 411       unsigned int cpumcommit:1;
 412       unsigned int cpusev_es:1;
 413       unsigned int cputsxldtrk:1;
 414       unsigned int cpukl:1;
 415       unsigned int cpuwidekl:1;
 416       unsigned int cpuhreset:1;
 417       unsigned int cpu64:1;
 418       unsigned int cpuno64:1;
 419 #ifdef CpuUnused
 420       unsigned int unused:(CpuNumOfBits - CpuUnused);
 421 #endif
 422     } bitfield;
 423   unsigned int array[CpuNumOfUints];
 424 } i386_cpu_flags;
 425
 426 /* Position of opcode_modifier bits.  */
 427
 428 enum
 429 {
 430   /* has direction bit. */
 431   D = 0,
 432   /* set if operands can be both bytes and words/dwords/qwords, encoded the
 433      canonical way; the base_opcode field should hold the encoding for byte
 434      operands  */
 435   W,
 436   /* load form instruction. Must be placed before store form.  */
 437   Load,
 438   /* insn has a modrm byte. */
 439   Modrm,
 440   /* special case for jump insns; value has to be 1 */
 441 #define JUMP 1
 442   /* call and jump */
 443 #define JUMP_DWORD 2
 444   /* loop and jecxz */
 445 #define JUMP_BYTE 3
 446   /* special case for intersegment leaps/calls */
 447 #define JUMP_INTERSEGMENT 4
 448   /* absolute address for jump */
 449 #define JUMP_ABSOLUTE 5
 450   Jump,
 451   /* FP insn memory format bit, sized by 0x4 */
 452   FloatMF,
 453   /* src/dest swap for floats. */
 454   FloatR,
 455   /* needs size prefix if in 32-bit mode */
 456 #define SIZE16 1
 457   /* needs size prefix if in 16-bit mode */
 458 #define SIZE32 2
 459   /* needs size prefix if in 64-bit mode */
 460 #define SIZE64 3
 461   Size,
 462   /* check register size.  */
 463   CheckRegSize,
 464   /* instruction ignores operand size prefix and in Intel mode ignores
 465      mnemonic size suffix check.  */
 466 #define IGNORESIZE      1
 467   /* default insn size depends on mode */
 468 #define DEFAULTSIZE     2
 469   MnemonicSize,
 470   /* any memory size */
 471   Anysize,
 472   /* b suffix on instruction illegal */
 473   No_bSuf,
 474   /* w suffix on instruction illegal */
 475   No_wSuf,
 476   /* l suffix on instruction illegal */
 477   No_lSuf,
 478   /* s suffix on instruction illegal */
 479   No_sSuf,
 480   /* q suffix on instruction illegal */
 481   No_qSuf,
 482   /* long double suffix on instruction illegal */
 483   No_ldSuf,
 484   /* instruction needs FWAIT */
 485   FWait,
 486   /* IsString provides for a quick test for string instructions, and
 487      its actual value also indicates which of the operands (if any)
 488      requires use of the %es segment.  */
 489 #define IS_STRING_ES_OP0 2
 490 #define IS_STRING_ES_OP1 3
 491   IsString,
 492   /* RegMem is for instructions with a modrm byte where the register
 493      destination operand should be encoded in the mod and regmem fields.
 494      Normally, it will be encoded in the reg field. We add a RegMem
 495      flag to indicate that it should be encoded in the regmem field.  */
 496   RegMem,
 497   /* quick test if branch instruction is MPX supported */
 498   BNDPrefixOk,
 499   /* quick test if NOTRACK prefix is supported */
 500   NoTrackPrefixOk,
 501   /* quick test for lockable instructions */
 502   IsLockable,
 503   /* fake an extra reg operand for clr, imul and special register
 504      processing for some instructions.  */
 505   RegKludge,
 506   /* An implicit xmm0 as the first operand */
 507   Implicit1stXmm0,
 508   /* The HLE prefix is OK:
 509      1. With a LOCK prefix.
 510      2. With or without a LOCK prefix.
 511      3. With a RELEASE (0xf3) prefix.
 512    */
 513 #define HLEPrefixNone           0
 514 #define HLEPrefixLock           1
 515 #define HLEPrefixAny            2
 516 #define HLEPrefixRelease        3
 517   HLEPrefixOk,
 518   /* An instruction on which a "rep" prefix is acceptable.  */
 519   RepPrefixOk,
 520   /* Convert to DWORD */
 521   ToDword,
 522   /* Convert to QWORD */
 523   ToQword,
 524   /* Address prefix changes register operand */
 525   AddrPrefixOpReg,
 526   /* opcode is a prefix */
 527   IsPrefix,
 528   /* instruction has extension in 8 bit imm */
 529   ImmExt,
 530   /* instruction don't need Rex64 prefix.  */
 531   NoRex64,
 532   /* deprecated fp insn, gets a warning */
 533   Ugh,
 534   /* Intel AVX Instructions support via {vex} prefix */
 535   PseudoVexPrefix,
 536   /* insn has VEX prefix:
 537         1: 128bit VEX prefix (or operand dependent).
 538         2: 256bit VEX prefix.
 539         3: Scalar VEX prefix.
 540    */
 541 #define VEX128          1
 542 #define VEX256          2
 543 #define VEXScalar       3
 544   Vex,
 545   /* How to encode VEX.vvvv:
 546      0: VEX.vvvv must be 1111b.
 547      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 548         the content of source registers will be preserved.
 549         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 550         where the content of first source register will be overwritten
 551         by the result.
 552         VEX.NDD2.  The second destination register operand is encoded in
 553         VEX.vvvv for instructions with 2 destination register operands.
 554         For assembler, there are no difference between VEX.NDS, VEX.DDS
 555         and VEX.NDD2.
 556      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 557      instructions with 1 destination register operand.
 558      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 559         of the operands can access a memory location.
 560    */
 561 #define VEXXDS  1
 562 #define VEXNDD  2
 563 #define VEXLWP  3
 564   VexVVVV,
 565   /* How the VEX.W bit is used:
 566      0: Set by the REX.W bit.
 567      1: VEX.W0.  Should always be 0.
 568      2: VEX.W1.  Should always be 1.
 569      3: VEX.WIG. The VEX.W bit is ignored.
 570    */
 571 #define VEXW0   1
 572 #define VEXW1   2
 573 #define VEXWIG  3
 574   VexW,
 575   /* Regular opcode prefix:
 576      0: None
 577      1: Add 0x66 opcode prefix.
 578      2: Add 0xf2 opcode prefix.
 579      3: Add 0xf3 opcode prefix.
 580    */
 581 #define PREFIX_NONE     0
 582 #define PREFIX_0X66     1
 583 #define PREFIX_0XF2     2
 584 #define PREFIX_0XF3     3
 585   /* VEX opcode prefix:
 586      0: VEX 0x0F opcode prefix.
 587      1: VEX 0x0F38 opcode prefix.
 588      2: VEX 0x0F3A opcode prefix
 589      3: XOP 0x08 opcode prefix.
 590      4: XOP 0x09 opcode prefix
 591      5: XOP 0x0A opcode prefix.
 592    */
 593 #define VEX0F           0
 594 #define VEX0F38         1
 595 #define VEX0F3A         2
 596 #define XOP08           3
 597 #define XOP09           4
 598 #define XOP0A           5
 599   OpcodePrefix,
 600   /* number of VEX source operands:
 601      0: <= 2 source operands.
 602      1: 2 XOP source operands.
 603      2: 3 source operands.
 604    */
 605 #define XOP2SOURCES     1
 606 #define VEX3SOURCES     2
 607   VexSources,
 608   /* Instruction with a mandatory SIB byte:
 609         1: 128bit vector register.
 610         2: 256bit vector register.
 611         3: 512bit vector register.
 612    */
 613 #define VECSIB128       1
 614 #define VECSIB256       2
 615 #define VECSIB512       3
 616 #define SIBMEM          4
 617   SIB,
 618
 619   /* SSE to AVX support required */
 620   SSE2AVX,
 621   /* No AVX equivalent */
 622   NoAVX,
 623
 624   /* insn has EVEX prefix:
 625         1: 512bit EVEX prefix.
 626         2: 128bit EVEX prefix.
 627         3: 256bit EVEX prefix.
 628         4: Length-ignored (LIG) EVEX prefix.
 629         5: Length determined from actual operands.
 630    */
 631 #define EVEX512                1
 632 #define EVEX128                2
 633 #define EVEX256                3
 634 #define EVEXLIG                4
 635 #define EVEXDYN                5
 636   EVex,
 637
 638   /* AVX512 masking support:
 639         1: Zeroing or merging masking depending on operands.
 640         2: Merging-masking.
 641         3: Both zeroing and merging masking.
 642    */
 643 #define DYNAMIC_MASKING 1
 644 #define MERGING_MASKING 2
 645 #define BOTH_MASKING    3
 646   Masking,
 647
 648   /* AVX512 broadcast support.  The number of bytes to broadcast is
 649      1 << (Broadcast - 1):
 650         1: Byte broadcast.
 651         2: Word broadcast.
 652         3: Dword broadcast.
 653         4: Qword broadcast.
 654    */
 655 #define BYTE_BROADCAST  1
 656 #define WORD_BROADCAST  2
 657 #define DWORD_BROADCAST 3
 658 #define QWORD_BROADCAST 4
 659   Broadcast,
 660
 661   /* Static rounding control is supported.  */
 662   StaticRounding,
 663
 664   /* Supress All Exceptions is supported.  */
 665   SAE,
 666
 667   /* Compressed Disp8*N attribute.  */
 668 #define DISP8_SHIFT_VL 7
 669   Disp8MemShift,
 670
 671   /* Default mask isn't allowed.  */
 672   NoDefMask,
 673
 674   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 675      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 676    */
 677   ImplicitQuadGroup,
 678
 679   /* Two source operands are swapped.  */
 680   SwapSources,
 681
 682   /* Support encoding optimization.  */
 683   Optimize,
 684
 685   /* AT&T mnemonic.  */
 686   ATTMnemonic,
 687   /* AT&T syntax.  */
 688   ATTSyntax,
 689   /* Intel syntax.  */
 690   IntelSyntax,
 691   /* ISA64: Don't change the order without other code adjustments.
 692         0: Common to AMD64 and Intel64.
 693         1: AMD64.
 694         2: Intel64.
 695         3: Only in Intel64.
 696    */
 697 #define AMD64           1
 698 #define INTEL64         2
 699 #define INTEL64ONLY     3
 700   ISA64,
 701   /* The last bitfield in i386_opcode_modifier.  */
 702   Opcode_Modifier_Num
 703 };
 704
 705 typedef struct i386_opcode_modifier
 706 {
 707   unsigned int d:1;
 708   unsigned int w:1;
 709   unsigned int load:1;
 710   unsigned int modrm:1;
 711   unsigned int jump:3;
 712   unsigned int floatmf:1;
 713   unsigned int floatr:1;
 714   unsigned int size:2;
 715   unsigned int checkregsize:1;
 716   unsigned int mnemonicsize:2;
 717   unsigned int anysize:1;
 718   unsigned int no_bsuf:1;
 719   unsigned int no_wsuf:1;
 720   unsigned int no_lsuf:1;
 721   unsigned int no_ssuf:1;
 722   unsigned int no_qsuf:1;
 723   unsigned int no_ldsuf:1;
 724   unsigned int fwait:1;
 725   unsigned int isstring:2;
 726   unsigned int regmem:1;
 727   unsigned int bndprefixok:1;
 728   unsigned int notrackprefixok:1;
 729   unsigned int islockable:1;
 730   unsigned int regkludge:1;
 731   unsigned int implicit1stxmm0:1;
 732   unsigned int hleprefixok:2;
 733   unsigned int repprefixok:1;
 734   unsigned int todword:1;
 735   unsigned int toqword:1;
 736   unsigned int addrprefixopreg:1;
 737   unsigned int isprefix:1;
 738   unsigned int immext:1;
 739   unsigned int norex64:1;
 740   unsigned int ugh:1;
 741   unsigned int pseudovexprefix:1;
 742   unsigned int vex:2;
 743   unsigned int vexvvvv:2;
 744   unsigned int vexw:2;
 745   unsigned int opcodeprefix:3;
 746   unsigned int vexsources:2;
 747   unsigned int sib:3;
 748   unsigned int sse2avx:1;
 749   unsigned int noavx:1;
 750   unsigned int evex:3;
 751   unsigned int masking:2;
 752   unsigned int broadcast:3;
 753   unsigned int staticrounding:1;
 754   unsigned int sae:1;
 755   unsigned int disp8memshift:3;
 756   unsigned int nodefmask:1;
 757   unsigned int implicitquadgroup:1;
 758   unsigned int swapsources:1;
 759   unsigned int optimize:1;
 760   unsigned int attmnemonic:1;
 761   unsigned int attsyntax:1;
 762   unsigned int intelsyntax:1;
 763   unsigned int isa64:2;
 764 } i386_opcode_modifier;
 765
 766 /* Operand classes.  */
 767
 768 #define CLASS_WIDTH 4
 769 enum operand_class
 770 {
 771   ClassNone,
 772   Reg, /* GPRs and FP regs, distinguished by operand size */
 773   SReg, /* Segment register */
 774   RegCR, /* Control register */
 775   RegDR, /* Debug register */
 776   RegTR, /* Test register */
 777   RegMMX, /* MMX register */
 778   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
 779   RegMask, /* Vector Mask register */
 780   RegBND, /* Bound register */
 781 };
 782
 783 /* Special operand instances.  */
 784
 785 #define INSTANCE_WIDTH 3
 786 enum operand_instance
 787 {
 788   InstanceNone,
 789   Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 790   RegC,  /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
 791   RegD,  /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
 792   RegB,  /* %bl / %bx / %ebx / %rbx */
 793 };
 794
 795 /* Position of operand_type bits.  */
 796
 797 enum
 798 {
 799   /* Class and Instance */
 800   ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
 801   /* 1 bit immediate */
 802   Imm1,
 803   /* 8 bit immediate */
 804   Imm8,
 805   /* 8 bit immediate sign extended */
 806   Imm8S,
 807   /* 16 bit immediate */
 808   Imm16,
 809   /* 32 bit immediate */
 810   Imm32,
 811   /* 32 bit immediate sign extended */
 812   Imm32S,
 813   /* 64 bit immediate */
 814   Imm64,
 815   /* 8bit/16bit/32bit displacements are used in different ways,
 816      depending on the instruction.  For jumps, they specify the
 817      size of the PC relative displacement, for instructions with
 818      memory operand, they specify the size of the offset relative
 819      to the base register, and for instructions with memory offset
 820      such as `mov 1234,%al' they specify the size of the offset
 821      relative to the segment base.  */
 822   /* 8 bit displacement */
 823   Disp8,
 824   /* 16 bit displacement */
 825   Disp16,
 826   /* 32 bit displacement */
 827   Disp32,
 828   /* 32 bit signed displacement */
 829   Disp32S,
 830   /* 64 bit displacement */
 831   Disp64,
 832   /* Register which can be used for base or index in memory operand.  */
 833   BaseIndex,
 834   /* BYTE size. */
 835   Byte,
 836   /* WORD size. 2 byte */
 837   Word,
 838   /* DWORD size. 4 byte */
 839   Dword,
 840   /* FWORD size. 6 byte */
 841   Fword,
 842   /* QWORD size. 8 byte */
 843   Qword,
 844   /* TBYTE size. 10 byte */
 845   Tbyte,
 846   /* XMMWORD size. */
 847   Xmmword,
 848   /* YMMWORD size. */
 849   Ymmword,
 850   /* ZMMWORD size.  */
 851   Zmmword,
 852   /* TMMWORD size.  */
 853   Tmmword,
 854   /* Unspecified memory size.  */
 855   Unspecified,
 856
 857   /* The number of bits in i386_operand_type.  */
 858   OTNum
 859 };
 860
 861 #define OTNumOfUints \
 862   ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
 863 #define OTNumOfBits \
 864   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 865
 866 /* If you get a compiler error for zero width of the unused field,
 867    comment it out.  */
 868 #define OTUnused                OTNum
 869
 870 typedef union i386_operand_type
 871 {
 872   struct
 873     {
 874       unsigned int class:CLASS_WIDTH;
 875       unsigned int instance:INSTANCE_WIDTH;
 876       unsigned int imm1:1;
 877       unsigned int imm8:1;
 878       unsigned int imm8s:1;
 879       unsigned int imm16:1;
 880       unsigned int imm32:1;
 881       unsigned int imm32s:1;
 882       unsigned int imm64:1;
 883       unsigned int disp8:1;
 884       unsigned int disp16:1;
 885       unsigned int disp32:1;
 886       unsigned int disp32s:1;
 887       unsigned int disp64:1;
 888       unsigned int baseindex:1;
 889       unsigned int byte:1;
 890       unsigned int word:1;
 891       unsigned int dword:1;
 892       unsigned int fword:1;
 893       unsigned int qword:1;
 894       unsigned int tbyte:1;
 895       unsigned int xmmword:1;
 896       unsigned int ymmword:1;
 897       unsigned int zmmword:1;
 898       unsigned int tmmword:1;
 899       unsigned int unspecified:1;
 900 #ifdef OTUnused
 901       unsigned int unused:(OTNumOfBits - OTUnused);
 902 #endif
 903     } bitfield;
 904   unsigned int array[OTNumOfUints];
 905 } i386_operand_type;
 906
 907 typedef struct insn_template
 908 {
 909   /* instruction name sans width suffix ("mov" for movl insns) */
 910   char *name;
 911
 912   /* base_opcode is the fundamental opcode byte without optional
 913      prefix(es).  */
 914   unsigned int base_opcode;
 915 #define Opcode_D        0x2 /* Direction bit:
 916                                set if Reg --> Regmem;
 917                                unset if Regmem --> Reg. */
 918 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 919 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 920 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 921 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 922
 923 /* Pseudo prefixes.  */
 924 #define Prefix_Disp8            0       /* {disp8} */
 925 #define Prefix_Disp16           1       /* {disp16} */
 926 #define Prefix_Disp32           2       /* {disp32} */
 927 #define Prefix_Load             3       /* {load} */
 928 #define Prefix_Store            4       /* {store} */
 929 #define Prefix_VEX              5       /* {vex} */
 930 #define Prefix_VEX3             6       /* {vex3} */
 931 #define Prefix_EVEX             7       /* {evex} */
 932 #define Prefix_REX              8       /* {rex} */
 933 #define Prefix_NoOptimize       9       /* {nooptimize} */
 934
 935   /* extension_opcode is the 3 bit extension for group <n> insns.
 936      This field is also used to store the 8-bit opcode suffix for the
 937      AMD 3DNow! instructions.
 938      If this template has no extension opcode (the usual case) use None
 939      Instructions */
 940   unsigned short extension_opcode;
 941 #define None 0xffff             /* If no extension_opcode is possible.  */
 942
 943   /* Opcode length.  */
 944   unsigned char opcode_length;
 945
 946   /* how many operands */
 947   unsigned char operands;
 948
 949   /* cpu feature flags */
 950   i386_cpu_flags cpu_flags;
 951
 952   /* the bits in opcode_modifier are used to generate the final opcode from
 953      the base_opcode.  These bits also are used to detect alternate forms of
 954      the same instruction */
 955   i386_opcode_modifier opcode_modifier;
 956
 957   /* operand_types[i] describes the type of operand i.  This is made
 958      by OR'ing together all of the possible type masks.  (e.g.
 959      'operand_types[i] = Reg|Imm' specifies that operand i can be
 960      either a register or an immediate operand.  */
 961   i386_operand_type operand_types[MAX_OPERANDS];
 962 }
 963 insn_template;
 964
 965 extern const insn_template i386_optab[];
 966
 967 /* these are for register name --> number & type hash lookup */
 968 typedef struct
 969 {
 970   const char *reg_name;
 971   i386_operand_type reg_type;
 972   unsigned char reg_flags;
 973 #define RegRex      0x1  /* Extended register.  */
 974 #define RegRex64    0x2  /* Extended 8 bit register.  */
 975 #define RegVRex     0x4  /* Extended vector register.  */
 976   unsigned char reg_num;
 977 #define RegIP   ((unsigned char ) ~0)
 978 /* EIZ and RIZ are fake index registers.  */
 979 #define RegIZ   (RegIP - 1)
 980 /* FLAT is a fake segment register (Intel mode).  */
 981 #define RegFlat     ((unsigned char) ~0)
 982   signed char dw2_regnum[2];
 983 #define Dw2Inval (-1)
 984 }
 985 reg_entry;
 986
 987 /* Entries in i386_regtab.  */
 988 #define REGNAM_AL 1
 989 #define REGNAM_AX 25
 990 #define REGNAM_EAX 41
 991
 992 extern const reg_entry i386_regtab[];
 993 extern const unsigned int i386_regtab_size;
 994
 995 typedef struct
 996 {
 997   char *seg_name;
 998   unsigned int seg_prefix;
 999 }
1000 seg_entry;
1001
1002 extern const seg_entry cs;
1003 extern const seg_entry ds;
1004 extern const seg_entry ss;
1005 extern const seg_entry es;
1006 extern const seg_entry fs;
1007 extern const seg_entry gs;