opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright 2007, 2008
   3    Free Software Foundation, Inc.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GAS; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 #include "opcode/i386.h"
  23 #ifdef HAVE_LIMITS_H
  24 #include <limits.h>
  25 #endif
  26
  27 #ifndef CHAR_BIT
  28 #define CHAR_BIT 8
  29 #endif
  30
  31 /* Position of cpu flags bitfiled.  */
  32
  33 /* i186 or better required */
  34 #define Cpu186          0
  35 /* i286 or better required */
  36 #define Cpu286          (Cpu186 + 1)
  37 /* i386 or better required */
  38 #define Cpu386          (Cpu286 + 1)
  39 /* i486 or better required */
  40 #define Cpu486          (Cpu386 + 1)
  41 /* i585 or better required */
  42 #define Cpu586          (Cpu486 + 1)
  43 /* i686 or better required */
  44 #define Cpu686          (Cpu586 + 1)
  45 /* Pentium4 or better required */
  46 #define CpuP4           (Cpu686 + 1)
  47 /* AMD K6 or better required*/
  48 #define CpuK6           (CpuP4 + 1)
  49 /* AMD K8 or better required */
  50 #define CpuK8           (CpuK6 + 1)
  51 /* MMX support required */
  52 #define CpuMMX          (CpuK8 + 1)
  53 /* extended MMX support (with SSE or 3DNow!Ext) required */
  54 #define CpuMMX2         (CpuMMX + 1)
  55 /* SSE support required */
  56 #define CpuSSE          (CpuMMX2 + 1)
  57 /* SSE2 support required */
  58 #define CpuSSE2         (CpuSSE + 1)
  59 /* 3dnow! support required */
  60 #define Cpu3dnow        (CpuSSE2 + 1)
  61 /* 3dnow! Extensions support required */
  62 #define Cpu3dnowA       (Cpu3dnow + 1)
  63 /* SSE3 support required */
  64 #define CpuSSE3         (Cpu3dnowA + 1)
  65 /* VIA PadLock required */
  66 #define CpuPadLock      (CpuSSE3 + 1)
  67 /* AMD Secure Virtual Machine Ext-s required */
  68 #define CpuSVME         (CpuPadLock + 1)
  69 /* VMX Instructions required */
  70 #define CpuVMX          (CpuSVME + 1)
  71 /* SMX Instructions required */
  72 #define CpuSMX          (CpuVMX + 1)
  73 /* SSSE3 support required */
  74 #define CpuSSSE3        (CpuSMX + 1)
  75 /* SSE4a support required */
  76 #define CpuSSE4a        (CpuSSSE3 + 1)
  77 /* ABM New Instructions required */
  78 #define CpuABM          (CpuSSE4a + 1)
  79 /* SSE4.1 support required */
  80 #define CpuSSE4_1       (CpuABM + 1)
  81 /* SSE4.2 support required */
  82 #define CpuSSE4_2       (CpuSSE4_1 + 1)
  83 /* SSE5 support required */
  84 #define CpuSSE5         (CpuSSE4_2 + 1)
  85 /* 64bit support available, used by -march= in assembler.  */
  86 #define CpuLM           (CpuSSE5 + 1)
  87 /* 64bit support required  */
  88 #define Cpu64           (CpuLM + 1)
  89 /* Not supported in the 64bit mode  */
  90 #define CpuNo64         (Cpu64 + 1)
  91 /* The last bitfield in i386_cpu_flags.  */
  92 #define CpuMax          CpuNo64
  93
  94 #define CpuNumOfUints \
  95   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
  96 #define CpuNumOfBits \
  97   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
  98
  99 /* If you get a compiler error for zero width of the unused field,
 100    comment it out.  */
 101 #define CpuUnused       (CpuMax + 1)
 102
 103 /* We can check if an instruction is available with array instead
 104    of bitfield. */
 105 typedef union i386_cpu_flags
 106 {
 107   struct
 108     {
 109       unsigned int cpui186:1;
 110       unsigned int cpui286:1;
 111       unsigned int cpui386:1;
 112       unsigned int cpui486:1;
 113       unsigned int cpui586:1;
 114       unsigned int cpui686:1;
 115       unsigned int cpup4:1;
 116       unsigned int cpuk6:1;
 117       unsigned int cpuk8:1;
 118       unsigned int cpummx:1;
 119       unsigned int cpummx2:1;
 120       unsigned int cpusse:1;
 121       unsigned int cpusse2:1;
 122       unsigned int cpua3dnow:1;
 123       unsigned int cpua3dnowa:1;
 124       unsigned int cpusse3:1;
 125       unsigned int cpupadlock:1;
 126       unsigned int cpusvme:1;
 127       unsigned int cpuvmx:1;
 128       unsigned int cpusmx:1;
 129       unsigned int cpussse3:1;
 130       unsigned int cpusse4a:1;
 131       unsigned int cpuabm:1;
 132       unsigned int cpusse4_1:1;
 133       unsigned int cpusse4_2:1;
 134       unsigned int cpusse5:1;
 135       unsigned int cpulm:1;
 136       unsigned int cpu64:1;
 137       unsigned int cpuno64:1;
 138 #ifdef CpuUnused
 139       unsigned int unused:(CpuNumOfBits - CpuUnused);
 140 #endif
 141     } bitfield;
 142   unsigned int array[CpuNumOfUints];
 143 } i386_cpu_flags;
 144
 145 /* Position of opcode_modifier bits.  */
 146
 147 /* has direction bit. */
 148 #define D                       0
 149 /* set if operands can be words or dwords encoded the canonical way */
 150 #define W                       (D + 1)
 151 /* insn has a modrm byte. */
 152 #define Modrm                   (W + 1)
 153 /* register is in low 3 bits of opcode */
 154 #define ShortForm               (Modrm + 1)
 155 /* special case for jump insns.  */
 156 #define Jump                    (ShortForm + 1)
 157 /* call and jump */
 158 #define JumpDword               (Jump + 1)
 159 /* loop and jecxz */
 160 #define JumpByte                (JumpDword + 1)
 161 /* special case for intersegment leaps/calls */
 162 #define JumpInterSegment        (JumpByte + 1)
 163 /* FP insn memory format bit, sized by 0x4 */
 164 #define FloatMF                 (JumpInterSegment + 1)
 165 /* src/dest swap for floats. */
 166 #define FloatR                  (FloatMF + 1)
 167 /* has float insn direction bit. */
 168 #define FloatD                  (FloatR + 1)
 169 /* needs size prefix if in 32-bit mode */
 170 #define Size16                  (FloatD + 1)
 171 /* needs size prefix if in 16-bit mode */
 172 #define Size32                  (Size16 + 1)
 173 /* needs size prefix if in 64-bit mode */
 174 #define Size64                  (Size32 + 1)
 175 /* instruction ignores operand size prefix and in Intel mode ignores
 176    mnemonic size suffix check.  */
 177 #define IgnoreSize              (Size64 + 1)
 178 /* default insn size depends on mode */
 179 #define DefaultSize             (IgnoreSize + 1)
 180 /* b suffix on instruction illegal */
 181 #define No_bSuf                 (DefaultSize + 1)
 182 /* w suffix on instruction illegal */
 183 #define No_wSuf                 (No_bSuf + 1)
 184 /* l suffix on instruction illegal */
 185 #define No_lSuf                 (No_wSuf + 1)
 186 /* s suffix on instruction illegal */
 187 #define No_sSuf                 (No_lSuf + 1)
 188 /* q suffix on instruction illegal */
 189 #define No_qSuf                 (No_sSuf + 1)
 190 /* long double suffix on instruction illegal */
 191 #define No_ldSuf                (No_qSuf + 1)
 192 /* instruction needs FWAIT */
 193 #define FWait                   (No_ldSuf + 1)
 194 /* quick test for string instructions */
 195 #define IsString                (FWait + 1)
 196 /* fake an extra reg operand for clr, imul and special register
 197    processing for some instructions.  */
 198 #define RegKludge               (IsString + 1)
 199 /* The first operand must be xmm0 */
 200 #define FirstXmm0               (RegKludge + 1)
 201 /* BYTE is OK in Intel syntax. */
 202 #define ByteOkIntel             (FirstXmm0 + 1)
 203 /* Convert to DWORD */
 204 #define ToDword                 (ByteOkIntel + 1)
 205 /* Convert to QWORD */
 206 #define ToQword                 (ToDword + 1)
 207 /* Address prefix changes operand 0 */
 208 #define AddrPrefixOp0           (ToQword + 1)
 209 /* opcode is a prefix */
 210 #define IsPrefix                (AddrPrefixOp0 + 1)
 211 /* instruction has extension in 8 bit imm */
 212 #define ImmExt                  (IsPrefix + 1)
 213 /* instruction don't need Rex64 prefix.  */
 214 #define NoRex64                 (ImmExt + 1)
 215 /* instruction require Rex64 prefix.  */
 216 #define Rex64                   (NoRex64 + 1)
 217 /* deprecated fp insn, gets a warning */
 218 #define Ugh                     (Rex64 + 1)
 219 #define Drex                    (Ugh + 1)
 220 /* instruction needs DREX with multiple encodings for memory ops */
 221 #define Drexv                   (Drex + 1)
 222 /* special DREX for comparisons */
 223 #define Drexc                   (Drexv + 1)
 224 /* Compatible with old (<= 2.8.1) versions of gcc  */
 225 #define OldGcc                  (Drexc + 1)
 226 /* AT&T mnemonic.  */
 227 #define ATTMnemonic             (OldGcc + 1)
 228 /* AT&T syntax.  */
 229 #define ATTSyntax               (ATTMnemonic + 1)
 230 /* The last bitfield in i386_opcode_modifier.  */
 231 #define Opcode_Modifier_Max     ATTSyntax
 232
 233 typedef struct i386_opcode_modifier
 234 {
 235   unsigned int d:1;
 236   unsigned int w:1;
 237   unsigned int modrm:1;
 238   unsigned int shortform:1;
 239   unsigned int jump:1;
 240   unsigned int jumpdword:1;
 241   unsigned int jumpbyte:1;
 242   unsigned int jumpintersegment:1;
 243   unsigned int floatmf:1;
 244   unsigned int floatr:1;
 245   unsigned int floatd:1;
 246   unsigned int size16:1;
 247   unsigned int size32:1;
 248   unsigned int size64:1;
 249   unsigned int ignoresize:1;
 250   unsigned int defaultsize:1;
 251   unsigned int no_bsuf:1;
 252   unsigned int no_wsuf:1;
 253   unsigned int no_lsuf:1;
 254   unsigned int no_ssuf:1;
 255   unsigned int no_qsuf:1;
 256   unsigned int no_ldsuf:1;
 257   unsigned int fwait:1;
 258   unsigned int isstring:1;
 259   unsigned int regkludge:1;
 260   unsigned int firstxmm0:1;
 261   unsigned int byteokintel:1;
 262   unsigned int todword:1;
 263   unsigned int toqword:1;
 264   unsigned int addrprefixop0:1;
 265   unsigned int isprefix:1;
 266   unsigned int immext:1;
 267   unsigned int norex64:1;
 268   unsigned int rex64:1;
 269   unsigned int ugh:1;
 270   unsigned int drex:1;
 271   unsigned int drexv:1;
 272   unsigned int drexc:1;
 273   unsigned int oldgcc:1;
 274   unsigned int attmnemonic:1;
 275   unsigned int attsyntax:1;
 276 } i386_opcode_modifier;
 277
 278 /* Position of operand_type bits.  */
 279
 280 /* 8bit register */
 281 #define Reg8                    0
 282 /* 16bit register */
 283 #define Reg16                   (Reg8 + 1)
 284 /* 32bit register */
 285 #define Reg32                   (Reg16 + 1)
 286 /* 64bit register */
 287 #define Reg64                   (Reg32 + 1)
 288 /* Floating pointer stack register */
 289 #define FloatReg                (Reg64 + 1)
 290 /* MMX register */
 291 #define RegMMX                  (FloatReg + 1)
 292 /* SSE register */
 293 #define RegXMM                  (RegMMX + 1)
 294 /* Control register */
 295 #define Control                 (RegXMM + 1)
 296 /* Debug register */
 297 #define Debug                   (Control + 1)
 298 /* Test register */
 299 #define Test                    (Debug + 1)
 300 /* 2 bit segment register */
 301 #define SReg2                   (Test + 1)
 302 /* 3 bit segment register */
 303 #define SReg3                   (SReg2 + 1)
 304 /* 1 bit immediate */
 305 #define Imm1                    (SReg3 + 1)
 306 /* 8 bit immediate */
 307 #define Imm8                    (Imm1 + 1)
 308 /* 8 bit immediate sign extended */
 309 #define Imm8S                   (Imm8 + 1)
 310 /* 16 bit immediate */
 311 #define Imm16                   (Imm8S + 1)
 312 /* 32 bit immediate */
 313 #define Imm32                   (Imm16 + 1)
 314 /* 32 bit immediate sign extended */
 315 #define Imm32S                  (Imm32 + 1)
 316 /* 64 bit immediate */
 317 #define Imm64                   (Imm32S + 1)
 318 /* 8bit/16bit/32bit displacements are used in different ways,
 319    depending on the instruction.  For jumps, they specify the
 320    size of the PC relative displacement, for instructions with
 321    memory operand, they specify the size of the offset relative
 322    to the base register, and for instructions with memory offset
 323    such as `mov 1234,%al' they specify the size of the offset
 324    relative to the segment base.  */
 325 /* 8 bit displacement */
 326 #define Disp8                   (Imm64 + 1)
 327 /* 16 bit displacement */
 328 #define Disp16                  (Disp8 + 1)
 329 /* 32 bit displacement */
 330 #define Disp32                  (Disp16 + 1)
 331 /* 32 bit signed displacement */
 332 #define Disp32S                 (Disp32 + 1)
 333 /* 64 bit displacement */
 334 #define Disp64                  (Disp32S + 1)
 335 /* Accumulator %al/%ax/%eax/%rax */
 336 #define Acc                     (Disp64 + 1)
 337 /* Floating pointer top stack register %st(0) */
 338 #define FloatAcc                (Acc + 1)
 339 /* Register which can be used for base or index in memory operand.  */
 340 #define BaseIndex               (FloatAcc + 1)
 341 /* Register to hold in/out port addr = dx */
 342 #define InOutPortReg            (BaseIndex + 1)
 343 /* Register to hold shift count = cl */
 344 #define ShiftCount              (InOutPortReg + 1)
 345 /* Absolute address for jump.  */
 346 #define JumpAbsolute            (ShiftCount + 1)
 347 /* String insn operand with fixed es segment */
 348 #define EsSeg                   (JumpAbsolute + 1)
 349 /* RegMem is for instructions with a modrm byte where the register
 350    destination operand should be encoded in the mod and regmem fields.
 351    Normally, it will be encoded in the reg field. We add a RegMem
 352    flag to the destination register operand to indicate that it should
 353    be encoded in the regmem field.  */
 354 #define RegMem                  (EsSeg + 1)
 355 /* BYTE memory. */
 356 #define Byte                    (RegMem)
 357 /* WORD memory. 2 byte */
 358 #define Word                    (Byte + 1)
 359 /* DWORD memory. 4 byte */
 360 #define Dword                   (Word + 1)
 361 /* FWORD memory. 6 byte */
 362 #define Fword                   (Dword + 1)
 363 /* QWORD memory. 8 byte */
 364 #define Qword                   (Fword + 1)
 365 /* TBYTE memory. 10 byte */
 366 #define Tbyte                   (Qword + 1)
 367 /* XMMWORD memory. */
 368 #define Xmmword                 (Tbyte + 1)
 369 /* Unspecified memory size.  */
 370 #define Unspecified             (Xmmword + 1)
 371 /* Any memory size.  */
 372 #define Anysize                 (Unspecified  + 1)
 373
 374 /* The last bitfield in i386_operand_type.  */
 375 #define OTMax                   Anysize
 376
 377 #define OTNumOfUints \
 378   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 379 #define OTNumOfBits \
 380   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 381
 382 /* If you get a compiler error for zero width of the unused field,
 383    comment it out.  */
 384 #define OTUnused                (OTMax + 1)
 385
 386 typedef union i386_operand_type
 387 {
 388   struct
 389     {
 390       unsigned int reg8:1;
 391       unsigned int reg16:1;
 392       unsigned int reg32:1;
 393       unsigned int reg64:1;
 394       unsigned int floatreg:1;
 395       unsigned int regmmx:1;
 396       unsigned int regxmm:1;
 397       unsigned int control:1;
 398       unsigned int debug:1;
 399       unsigned int test:1;
 400       unsigned int sreg2:1;
 401       unsigned int sreg3:1;
 402       unsigned int imm1:1;
 403       unsigned int imm8:1;
 404       unsigned int imm8s:1;
 405       unsigned int imm16:1;
 406       unsigned int imm32:1;
 407       unsigned int imm32s:1;
 408       unsigned int imm64:1;
 409       unsigned int disp8:1;
 410       unsigned int disp16:1;
 411       unsigned int disp32:1;
 412       unsigned int disp32s:1;
 413       unsigned int disp64:1;
 414       unsigned int acc:1;
 415       unsigned int floatacc:1;
 416       unsigned int baseindex:1;
 417       unsigned int inoutportreg:1;
 418       unsigned int shiftcount:1;
 419       unsigned int jumpabsolute:1;
 420       unsigned int esseg:1;
 421       unsigned int regmem:1;
 422       unsigned int byte:1;
 423       unsigned int word:1;
 424       unsigned int dword:1;
 425       unsigned int fword:1;
 426       unsigned int qword:1;
 427       unsigned int tbyte:1;
 428       unsigned int xmmword:1;
 429       unsigned int unspecified:1;
 430       unsigned int anysize:1;
 431 #ifdef OTUnused
 432       unsigned int unused:(OTNumOfBits - OTUnused);
 433 #endif
 434     } bitfield;
 435   unsigned int array[OTNumOfUints];
 436 } i386_operand_type;
 437
 438 typedef struct template
 439 {
 440   /* instruction name sans width suffix ("mov" for movl insns) */
 441   char *name;
 442
 443   /* how many operands */
 444   unsigned int operands;
 445
 446   /* base_opcode is the fundamental opcode byte without optional
 447      prefix(es).  */
 448   unsigned int base_opcode;
 449 #define Opcode_D        0x2 /* Direction bit:
 450                                set if Reg --> Regmem;
 451                                unset if Regmem --> Reg. */
 452 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 453 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 454
 455   /* extension_opcode is the 3 bit extension for group <n> insns.
 456      This field is also used to store the 8-bit opcode suffix for the
 457      AMD 3DNow! instructions.
 458      If this template has no extension opcode (the usual case) use None
 459      Instructions with Drex use this to specify 2 bits for OC */
 460   unsigned int extension_opcode;
 461 #define None 0xffff             /* If no extension_opcode is possible.  */
 462
 463   /* Opcode length.  */
 464   unsigned char opcode_length;
 465
 466   /* cpu feature flags */
 467   i386_cpu_flags cpu_flags;
 468
 469   /* the bits in opcode_modifier are used to generate the final opcode from
 470      the base_opcode.  These bits also are used to detect alternate forms of
 471      the same instruction */
 472   i386_opcode_modifier opcode_modifier;
 473
 474   /* operand_types[i] describes the type of operand i.  This is made
 475      by OR'ing together all of the possible type masks.  (e.g.
 476      'operand_types[i] = Reg|Imm' specifies that operand i can be
 477      either a register or an immediate operand.  */
 478   i386_operand_type operand_types[MAX_OPERANDS];
 479 }
 480 template;
 481
 482 extern const template i386_optab[];
 483
 484 /* these are for register name --> number & type hash lookup */
 485 typedef struct
 486 {
 487   char *reg_name;
 488   i386_operand_type reg_type;
 489   unsigned int reg_flags;
 490 #define RegRex      0x1  /* Extended register.  */
 491 #define RegRex64    0x2  /* Extended 8 bit register.  */
 492   unsigned int reg_num;
 493 #define RegRip  ((unsigned int ) ~0)
 494 #define RegEip  (RegRip - 1)
 495 /* EIZ and RIZ are fake index registers.  */
 496 #define RegEiz  (RegEip - 1)
 497 #define RegRiz  (RegEiz - 1)
 498 }
 499 reg_entry;
 500
 501 /* Entries in i386_regtab.  */
 502 #define REGNAM_AL 1
 503 #define REGNAM_AX 25
 504 #define REGNAM_EAX 41
 505
 506 extern const reg_entry i386_regtab[];
 507 extern const unsigned int i386_regtab_size;
 508
 509 typedef struct
 510 {
 511   char *seg_name;
 512   unsigned int seg_prefix;
 513 }
 514 seg_entry;
 515
 516 extern const seg_entry cs;
 517 extern const seg_entry ds;
 518 extern const seg_entry ss;
 519 extern const seg_entry es;
 520 extern const seg_entry fs;
 521 extern const seg_entry gs;