opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2017 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* mwaitx instruction required */
 204   CpuMWAITX,
 205   /* Clzero instruction required */
 206   CpuCLZERO,
 207   /* OSPKE instruction required */
 208   CpuOSPKE,
 209   /* RDPID instruction required */
 210   CpuRDPID,
 211   /* PTWRITE instruction required */
 212   CpuPTWRITE,
 213   /* CET instruction support required */
 214   CpuCET,
 215   /* GFNI instructions required */
 216   CpuGFNI,
 217   /* VAES instructions required */
 218   CpuVAES,
 219   /* MMX register support required */
 220   CpuRegMMX,
 221   /* XMM register support required */
 222   CpuRegXMM,
 223   /* YMM register support required */
 224   CpuRegYMM,
 225   /* ZMM register support required */
 226   CpuRegZMM,
 227   /* Mask register support required */
 228   CpuRegMask,
 229   /* 64bit support required  */
 230   Cpu64,
 231   /* Not supported in the 64bit mode  */
 232   CpuNo64,
 233   /* The last bitfield in i386_cpu_flags.  */
 234   CpuMax = CpuNo64
 235 };
 236
 237 #define CpuNumOfUints \
 238   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 239 #define CpuNumOfBits \
 240   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 241
 242 /* If you get a compiler error for zero width of the unused field,
 243    comment it out.  */
 244 #define CpuUnused       (CpuMax + 1)
 245
 246 /* We can check if an instruction is available with array instead
 247    of bitfield. */
 248 typedef union i386_cpu_flags
 249 {
 250   struct
 251     {
 252       unsigned int cpui186:1;
 253       unsigned int cpui286:1;
 254       unsigned int cpui386:1;
 255       unsigned int cpui486:1;
 256       unsigned int cpui586:1;
 257       unsigned int cpui686:1;
 258       unsigned int cpuclflush:1;
 259       unsigned int cpunop:1;
 260       unsigned int cpusyscall:1;
 261       unsigned int cpu8087:1;
 262       unsigned int cpu287:1;
 263       unsigned int cpu387:1;
 264       unsigned int cpu687:1;
 265       unsigned int cpufisttp:1;
 266       unsigned int cpummx:1;
 267       unsigned int cpusse:1;
 268       unsigned int cpusse2:1;
 269       unsigned int cpua3dnow:1;
 270       unsigned int cpua3dnowa:1;
 271       unsigned int cpusse3:1;
 272       unsigned int cpupadlock:1;
 273       unsigned int cpusvme:1;
 274       unsigned int cpuvmx:1;
 275       unsigned int cpusmx:1;
 276       unsigned int cpussse3:1;
 277       unsigned int cpusse4a:1;
 278       unsigned int cpuabm:1;
 279       unsigned int cpusse4_1:1;
 280       unsigned int cpusse4_2:1;
 281       unsigned int cpuavx:1;
 282       unsigned int cpuavx2:1;
 283       unsigned int cpuavx512f:1;
 284       unsigned int cpuavx512cd:1;
 285       unsigned int cpuavx512er:1;
 286       unsigned int cpuavx512pf:1;
 287       unsigned int cpuavx512vl:1;
 288       unsigned int cpuavx512dq:1;
 289       unsigned int cpuavx512bw:1;
 290       unsigned int cpul1om:1;
 291       unsigned int cpuk1om:1;
 292       unsigned int cpuiamcu:1;
 293       unsigned int cpuxsave:1;
 294       unsigned int cpuxsaveopt:1;
 295       unsigned int cpuaes:1;
 296       unsigned int cpupclmul:1;
 297       unsigned int cpufma:1;
 298       unsigned int cpufma4:1;
 299       unsigned int cpuxop:1;
 300       unsigned int cpulwp:1;
 301       unsigned int cpubmi:1;
 302       unsigned int cputbm:1;
 303       unsigned int cpumovbe:1;
 304       unsigned int cpucx16:1;
 305       unsigned int cpuept:1;
 306       unsigned int cpurdtscp:1;
 307       unsigned int cpufsgsbase:1;
 308       unsigned int cpurdrnd:1;
 309       unsigned int cpuf16c:1;
 310       unsigned int cpubmi2:1;
 311       unsigned int cpulzcnt:1;
 312       unsigned int cpuhle:1;
 313       unsigned int cpurtm:1;
 314       unsigned int cpuinvpcid:1;
 315       unsigned int cpuvmfunc:1;
 316       unsigned int cpumpx:1;
 317       unsigned int cpulm:1;
 318       unsigned int cpurdseed:1;
 319       unsigned int cpuadx:1;
 320       unsigned int cpuprfchw:1;
 321       unsigned int cpusmap:1;
 322       unsigned int cpusha:1;
 323       unsigned int cpuvrex:1;
 324       unsigned int cpuclflushopt:1;
 325       unsigned int cpuxsaves:1;
 326       unsigned int cpuxsavec:1;
 327       unsigned int cpuprefetchwt1:1;
 328       unsigned int cpuse1:1;
 329       unsigned int cpuclwb:1;
 330       unsigned int cpuavx512ifma:1;
 331       unsigned int cpuavx512vbmi:1;
 332       unsigned int cpuavx512_4fmaps:1;
 333       unsigned int cpuavx512_4vnniw:1;
 334       unsigned int cpuavx512_vpopcntdq:1;
 335       unsigned int cpuavx512_vbmi2:1;
 336       unsigned int cpumwaitx:1;
 337       unsigned int cpuclzero:1;
 338       unsigned int cpuospke:1;
 339       unsigned int cpurdpid:1;
 340       unsigned int cpuptwrite:1;
 341       unsigned int cpucet:1;
 342       unsigned int cpugfni:1;
 343       unsigned int cpuvaes:1;
 344       unsigned int cpuregmmx:1;
 345       unsigned int cpuregxmm:1;
 346       unsigned int cpuregymm:1;
 347       unsigned int cpuregzmm:1;
 348       unsigned int cpuregmask:1;
 349       unsigned int cpu64:1;
 350       unsigned int cpuno64:1;
 351 #ifdef CpuUnused
 352       unsigned int unused:(CpuNumOfBits - CpuUnused);
 353 #endif
 354     } bitfield;
 355   unsigned int array[CpuNumOfUints];
 356 } i386_cpu_flags;
 357
 358 /* Position of opcode_modifier bits.  */
 359
 360 enum
 361 {
 362   /* has direction bit. */
 363   D = 0,
 364   /* set if operands can be words or dwords encoded the canonical way */
 365   W,
 366   /* load form instruction. Must be placed before store form.  */
 367   Load,
 368   /* insn has a modrm byte. */
 369   Modrm,
 370   /* register is in low 3 bits of opcode */
 371   ShortForm,
 372   /* special case for jump insns.  */
 373   Jump,
 374   /* call and jump */
 375   JumpDword,
 376   /* loop and jecxz */
 377   JumpByte,
 378   /* special case for intersegment leaps/calls */
 379   JumpInterSegment,
 380   /* FP insn memory format bit, sized by 0x4 */
 381   FloatMF,
 382   /* src/dest swap for floats. */
 383   FloatR,
 384   /* has float insn direction bit. */
 385   FloatD,
 386   /* needs size prefix if in 32-bit mode */
 387   Size16,
 388   /* needs size prefix if in 16-bit mode */
 389   Size32,
 390   /* needs size prefix if in 64-bit mode */
 391   Size64,
 392   /* check register size.  */
 393   CheckRegSize,
 394   /* instruction ignores operand size prefix and in Intel mode ignores
 395      mnemonic size suffix check.  */
 396   IgnoreSize,
 397   /* default insn size depends on mode */
 398   DefaultSize,
 399   /* b suffix on instruction illegal */
 400   No_bSuf,
 401   /* w suffix on instruction illegal */
 402   No_wSuf,
 403   /* l suffix on instruction illegal */
 404   No_lSuf,
 405   /* s suffix on instruction illegal */
 406   No_sSuf,
 407   /* q suffix on instruction illegal */
 408   No_qSuf,
 409   /* long double suffix on instruction illegal */
 410   No_ldSuf,
 411   /* instruction needs FWAIT */
 412   FWait,
 413   /* quick test for string instructions */
 414   IsString,
 415   /* quick test if branch instruction is MPX supported */
 416   BNDPrefixOk,
 417   /* quick test if NOTRACK prefix is supported */
 418   NoTrackPrefixOk,
 419   /* quick test for lockable instructions */
 420   IsLockable,
 421   /* fake an extra reg operand for clr, imul and special register
 422      processing for some instructions.  */
 423   RegKludge,
 424   /* The first operand must be xmm0 */
 425   FirstXmm0,
 426   /* An implicit xmm0 as the first operand */
 427   Implicit1stXmm0,
 428   /* The HLE prefix is OK:
 429      1. With a LOCK prefix.
 430      2. With or without a LOCK prefix.
 431      3. With a RELEASE (0xf3) prefix.
 432    */
 433 #define HLEPrefixNone           0
 434 #define HLEPrefixLock           1
 435 #define HLEPrefixAny            2
 436 #define HLEPrefixRelease        3
 437   HLEPrefixOk,
 438   /* An instruction on which a "rep" prefix is acceptable.  */
 439   RepPrefixOk,
 440   /* Convert to DWORD */
 441   ToDword,
 442   /* Convert to QWORD */
 443   ToQword,
 444   /* Address prefix changes operand 0 */
 445   AddrPrefixOp0,
 446   /* opcode is a prefix */
 447   IsPrefix,
 448   /* instruction has extension in 8 bit imm */
 449   ImmExt,
 450   /* instruction don't need Rex64 prefix.  */
 451   NoRex64,
 452   /* instruction require Rex64 prefix.  */
 453   Rex64,
 454   /* deprecated fp insn, gets a warning */
 455   Ugh,
 456   /* insn has VEX prefix:
 457         1: 128bit VEX prefix.
 458         2: 256bit VEX prefix.
 459         3: Scalar VEX prefix.
 460    */
 461 #define VEX128          1
 462 #define VEX256          2
 463 #define VEXScalar       3
 464   Vex,
 465   /* How to encode VEX.vvvv:
 466      0: VEX.vvvv must be 1111b.
 467      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 468         the content of source registers will be preserved.
 469         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 470         where the content of first source register will be overwritten
 471         by the result.
 472         VEX.NDD2.  The second destination register operand is encoded in
 473         VEX.vvvv for instructions with 2 destination register operands.
 474         For assembler, there are no difference between VEX.NDS, VEX.DDS
 475         and VEX.NDD2.
 476      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 477      instructions with 1 destination register operand.
 478      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 479         of the operands can access a memory location.
 480    */
 481 #define VEXXDS  1
 482 #define VEXNDD  2
 483 #define VEXLWP  3
 484   VexVVVV,
 485   /* How the VEX.W bit is used:
 486      0: Set by the REX.W bit.
 487      1: VEX.W0.  Should always be 0.
 488      2: VEX.W1.  Should always be 1.
 489    */
 490 #define VEXW0   1
 491 #define VEXW1   2
 492   VexW,
 493   /* VEX opcode prefix:
 494      0: VEX 0x0F opcode prefix.
 495      1: VEX 0x0F38 opcode prefix.
 496      2: VEX 0x0F3A opcode prefix
 497      3: XOP 0x08 opcode prefix.
 498      4: XOP 0x09 opcode prefix
 499      5: XOP 0x0A opcode prefix.
 500    */
 501 #define VEX0F           0
 502 #define VEX0F38         1
 503 #define VEX0F3A         2
 504 #define XOP08           3
 505 #define XOP09           4
 506 #define XOP0A           5
 507   VexOpcode,
 508   /* number of VEX source operands:
 509      0: <= 2 source operands.
 510      1: 2 XOP source operands.
 511      2: 3 source operands.
 512    */
 513 #define XOP2SOURCES     1
 514 #define VEX3SOURCES     2
 515   VexSources,
 516   /* instruction has VEX 8 bit imm */
 517   VexImmExt,
 518   /* Instruction with vector SIB byte:
 519         1: 128bit vector register.
 520         2: 256bit vector register.
 521         3: 512bit vector register.
 522    */
 523 #define VecSIB128       1
 524 #define VecSIB256       2
 525 #define VecSIB512       3
 526   VecSIB,
 527   /* SSE to AVX support required */
 528   SSE2AVX,
 529   /* No AVX equivalent */
 530   NoAVX,
 531
 532   /* insn has EVEX prefix:
 533         1: 512bit EVEX prefix.
 534         2: 128bit EVEX prefix.
 535         3: 256bit EVEX prefix.
 536         4: Length-ignored (LIG) EVEX prefix.
 537    */
 538 #define EVEX512                1
 539 #define EVEX128                2
 540 #define EVEX256                3
 541 #define EVEXLIG                4
 542   EVex,
 543
 544   /* AVX512 masking support:
 545         1: Zeroing-masking.
 546         2: Merging-masking.
 547         3: Both zeroing and merging masking.
 548    */
 549 #define ZEROING_MASKING 1
 550 #define MERGING_MASKING 2
 551 #define BOTH_MASKING    3
 552   Masking,
 553
 554   /* Input element size of vector insn:
 555         0: 32bit.
 556         1: 64bit.
 557    */
 558   VecESize,
 559
 560   /* Broadcast factor.
 561         0: No broadcast.
 562         1: 1to16 broadcast.
 563         2: 1to8 broadcast.
 564    */
 565 #define NO_BROADCAST    0
 566 #define BROADCAST_1TO16 1
 567 #define BROADCAST_1TO8  2
 568 #define BROADCAST_1TO4  3
 569 #define BROADCAST_1TO2  4
 570   Broadcast,
 571
 572   /* Static rounding control is supported.  */
 573   StaticRounding,
 574
 575   /* Supress All Exceptions is supported.  */
 576   SAE,
 577
 578   /* Copressed Disp8*N attribute.  */
 579   Disp8MemShift,
 580
 581   /* Default mask isn't allowed.  */
 582   NoDefMask,
 583
 584   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 585      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 586    */
 587   ImplicitQuadGroup,
 588
 589   /* Compatible with old (<= 2.8.1) versions of gcc  */
 590   OldGcc,
 591   /* AT&T mnemonic.  */
 592   ATTMnemonic,
 593   /* AT&T syntax.  */
 594   ATTSyntax,
 595   /* Intel syntax.  */
 596   IntelSyntax,
 597   /* AMD64.  */
 598   AMD64,
 599   /* Intel64.  */
 600   Intel64,
 601   /* The last bitfield in i386_opcode_modifier.  */
 602   Opcode_Modifier_Max
 603 };
 604
 605 typedef struct i386_opcode_modifier
 606 {
 607   unsigned int d:1;
 608   unsigned int w:1;
 609   unsigned int load:1;
 610   unsigned int modrm:1;
 611   unsigned int shortform:1;
 612   unsigned int jump:1;
 613   unsigned int jumpdword:1;
 614   unsigned int jumpbyte:1;
 615   unsigned int jumpintersegment:1;
 616   unsigned int floatmf:1;
 617   unsigned int floatr:1;
 618   unsigned int floatd:1;
 619   unsigned int size16:1;
 620   unsigned int size32:1;
 621   unsigned int size64:1;
 622   unsigned int checkregsize:1;
 623   unsigned int ignoresize:1;
 624   unsigned int defaultsize:1;
 625   unsigned int no_bsuf:1;
 626   unsigned int no_wsuf:1;
 627   unsigned int no_lsuf:1;
 628   unsigned int no_ssuf:1;
 629   unsigned int no_qsuf:1;
 630   unsigned int no_ldsuf:1;
 631   unsigned int fwait:1;
 632   unsigned int isstring:1;
 633   unsigned int bndprefixok:1;
 634   unsigned int notrackprefixok:1;
 635   unsigned int islockable:1;
 636   unsigned int regkludge:1;
 637   unsigned int firstxmm0:1;
 638   unsigned int implicit1stxmm0:1;
 639   unsigned int hleprefixok:2;
 640   unsigned int repprefixok:1;
 641   unsigned int todword:1;
 642   unsigned int toqword:1;
 643   unsigned int addrprefixop0:1;
 644   unsigned int isprefix:1;
 645   unsigned int immext:1;
 646   unsigned int norex64:1;
 647   unsigned int rex64:1;
 648   unsigned int ugh:1;
 649   unsigned int vex:2;
 650   unsigned int vexvvvv:2;
 651   unsigned int vexw:2;
 652   unsigned int vexopcode:3;
 653   unsigned int vexsources:2;
 654   unsigned int veximmext:1;
 655   unsigned int vecsib:2;
 656   unsigned int sse2avx:1;
 657   unsigned int noavx:1;
 658   unsigned int evex:3;
 659   unsigned int masking:2;
 660   unsigned int vecesize:1;
 661   unsigned int broadcast:3;
 662   unsigned int staticrounding:1;
 663   unsigned int sae:1;
 664   unsigned int disp8memshift:3;
 665   unsigned int nodefmask:1;
 666   unsigned int implicitquadgroup:1;
 667   unsigned int oldgcc:1;
 668   unsigned int attmnemonic:1;
 669   unsigned int attsyntax:1;
 670   unsigned int intelsyntax:1;
 671   unsigned int amd64:1;
 672   unsigned int intel64:1;
 673 } i386_opcode_modifier;
 674
 675 /* Position of operand_type bits.  */
 676
 677 enum
 678 {
 679   /* 8bit register */
 680   Reg8 = 0,
 681   /* 16bit register */
 682   Reg16,
 683   /* 32bit register */
 684   Reg32,
 685   /* 64bit register */
 686   Reg64,
 687   /* Floating pointer stack register */
 688   FloatReg,
 689   /* MMX register */
 690   RegMMX,
 691   /* SSE register */
 692   RegXMM,
 693   /* AVX registers */
 694   RegYMM,
 695   /* AVX512 registers */
 696   RegZMM,
 697   /* Vector Mask registers */
 698   RegMask,
 699   /* Control register */
 700   Control,
 701   /* Debug register */
 702   Debug,
 703   /* Test register */
 704   Test,
 705   /* 2 bit segment register */
 706   SReg2,
 707   /* 3 bit segment register */
 708   SReg3,
 709   /* 1 bit immediate */
 710   Imm1,
 711   /* 8 bit immediate */
 712   Imm8,
 713   /* 8 bit immediate sign extended */
 714   Imm8S,
 715   /* 16 bit immediate */
 716   Imm16,
 717   /* 32 bit immediate */
 718   Imm32,
 719   /* 32 bit immediate sign extended */
 720   Imm32S,
 721   /* 64 bit immediate */
 722   Imm64,
 723   /* 8bit/16bit/32bit displacements are used in different ways,
 724      depending on the instruction.  For jumps, they specify the
 725      size of the PC relative displacement, for instructions with
 726      memory operand, they specify the size of the offset relative
 727      to the base register, and for instructions with memory offset
 728      such as `mov 1234,%al' they specify the size of the offset
 729      relative to the segment base.  */
 730   /* 8 bit displacement */
 731   Disp8,
 732   /* 16 bit displacement */
 733   Disp16,
 734   /* 32 bit displacement */
 735   Disp32,
 736   /* 32 bit signed displacement */
 737   Disp32S,
 738   /* 64 bit displacement */
 739   Disp64,
 740   /* Accumulator %al/%ax/%eax/%rax */
 741   Acc,
 742   /* Floating pointer top stack register %st(0) */
 743   FloatAcc,
 744   /* Register which can be used for base or index in memory operand.  */
 745   BaseIndex,
 746   /* Register to hold in/out port addr = dx */
 747   InOutPortReg,
 748   /* Register to hold shift count = cl */
 749   ShiftCount,
 750   /* Absolute address for jump.  */
 751   JumpAbsolute,
 752   /* String insn operand with fixed es segment */
 753   EsSeg,
 754   /* RegMem is for instructions with a modrm byte where the register
 755      destination operand should be encoded in the mod and regmem fields.
 756      Normally, it will be encoded in the reg field. We add a RegMem
 757      flag to the destination register operand to indicate that it should
 758      be encoded in the regmem field.  */
 759   RegMem,
 760   /* Memory.  */
 761   Mem,
 762   /* BYTE memory. */
 763   Byte,
 764   /* WORD memory. 2 byte */
 765   Word,
 766   /* DWORD memory. 4 byte */
 767   Dword,
 768   /* FWORD memory. 6 byte */
 769   Fword,
 770   /* QWORD memory. 8 byte */
 771   Qword,
 772   /* TBYTE memory. 10 byte */
 773   Tbyte,
 774   /* XMMWORD memory. */
 775   Xmmword,
 776   /* YMMWORD memory. */
 777   Ymmword,
 778   /* ZMMWORD memory.  */
 779   Zmmword,
 780   /* Unspecified memory size.  */
 781   Unspecified,
 782   /* Any memory size.  */
 783   Anysize,
 784
 785   /* Vector 4 bit immediate.  */
 786   Vec_Imm4,
 787
 788   /* Bound register.  */
 789   RegBND,
 790
 791   /* Vector 8bit displacement */
 792   Vec_Disp8,
 793
 794   /* The last bitfield in i386_operand_type.  */
 795   OTMax
 796 };
 797
 798 #define OTNumOfUints \
 799   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 800 #define OTNumOfBits \
 801   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 802
 803 /* If you get a compiler error for zero width of the unused field,
 804    comment it out.  */
 805 #define OTUnused                (OTMax + 1)
 806
 807 typedef union i386_operand_type
 808 {
 809   struct
 810     {
 811       unsigned int reg8:1;
 812       unsigned int reg16:1;
 813       unsigned int reg32:1;
 814       unsigned int reg64:1;
 815       unsigned int floatreg:1;
 816       unsigned int regmmx:1;
 817       unsigned int regxmm:1;
 818       unsigned int regymm:1;
 819       unsigned int regzmm:1;
 820       unsigned int regmask:1;
 821       unsigned int control:1;
 822       unsigned int debug:1;
 823       unsigned int test:1;
 824       unsigned int sreg2:1;
 825       unsigned int sreg3:1;
 826       unsigned int imm1:1;
 827       unsigned int imm8:1;
 828       unsigned int imm8s:1;
 829       unsigned int imm16:1;
 830       unsigned int imm32:1;
 831       unsigned int imm32s:1;
 832       unsigned int imm64:1;
 833       unsigned int disp8:1;
 834       unsigned int disp16:1;
 835       unsigned int disp32:1;
 836       unsigned int disp32s:1;
 837       unsigned int disp64:1;
 838       unsigned int acc:1;
 839       unsigned int floatacc:1;
 840       unsigned int baseindex:1;
 841       unsigned int inoutportreg:1;
 842       unsigned int shiftcount:1;
 843       unsigned int jumpabsolute:1;
 844       unsigned int esseg:1;
 845       unsigned int regmem:1;
 846       unsigned int mem:1;
 847       unsigned int byte:1;
 848       unsigned int word:1;
 849       unsigned int dword:1;
 850       unsigned int fword:1;
 851       unsigned int qword:1;
 852       unsigned int tbyte:1;
 853       unsigned int xmmword:1;
 854       unsigned int ymmword:1;
 855       unsigned int zmmword:1;
 856       unsigned int unspecified:1;
 857       unsigned int anysize:1;
 858       unsigned int vec_imm4:1;
 859       unsigned int regbnd:1;
 860       unsigned int vec_disp8:1;
 861 #ifdef OTUnused
 862       unsigned int unused:(OTNumOfBits - OTUnused);
 863 #endif
 864     } bitfield;
 865   unsigned int array[OTNumOfUints];
 866 } i386_operand_type;
 867
 868 typedef struct insn_template
 869 {
 870   /* instruction name sans width suffix ("mov" for movl insns) */
 871   char *name;
 872
 873   /* how many operands */
 874   unsigned int operands;
 875
 876   /* base_opcode is the fundamental opcode byte without optional
 877      prefix(es).  */
 878   unsigned int base_opcode;
 879 #define Opcode_D        0x2 /* Direction bit:
 880                                set if Reg --> Regmem;
 881                                unset if Regmem --> Reg. */
 882 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 883 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 884
 885   /* extension_opcode is the 3 bit extension for group <n> insns.
 886      This field is also used to store the 8-bit opcode suffix for the
 887      AMD 3DNow! instructions.
 888      If this template has no extension opcode (the usual case) use None
 889      Instructions */
 890   unsigned int extension_opcode;
 891 #define None 0xffff             /* If no extension_opcode is possible.  */
 892
 893   /* Opcode length.  */
 894   unsigned char opcode_length;
 895
 896   /* cpu feature flags */
 897   i386_cpu_flags cpu_flags;
 898
 899   /* the bits in opcode_modifier are used to generate the final opcode from
 900      the base_opcode.  These bits also are used to detect alternate forms of
 901      the same instruction */
 902   i386_opcode_modifier opcode_modifier;
 903
 904   /* operand_types[i] describes the type of operand i.  This is made
 905      by OR'ing together all of the possible type masks.  (e.g.
 906      'operand_types[i] = Reg|Imm' specifies that operand i can be
 907      either a register or an immediate operand.  */
 908   i386_operand_type operand_types[MAX_OPERANDS];
 909 }
 910 insn_template;
 911
 912 extern const insn_template i386_optab[];
 913
 914 /* these are for register name --> number & type hash lookup */
 915 typedef struct
 916 {
 917   char *reg_name;
 918   i386_operand_type reg_type;
 919   unsigned char reg_flags;
 920 #define RegRex      0x1  /* Extended register.  */
 921 #define RegRex64    0x2  /* Extended 8 bit register.  */
 922 #define RegVRex     0x4  /* Extended vector register.  */
 923   unsigned char reg_num;
 924 #define RegRip  ((unsigned char ) ~0)
 925 #define RegEip  (RegRip - 1)
 926 /* EIZ and RIZ are fake index registers.  */
 927 #define RegEiz  (RegEip - 1)
 928 #define RegRiz  (RegEiz - 1)
 929 /* FLAT is a fake segment register (Intel mode).  */
 930 #define RegFlat     ((unsigned char) ~0)
 931   signed char dw2_regnum[2];
 932 #define Dw2Inval (-1)
 933 }
 934 reg_entry;
 935
 936 /* Entries in i386_regtab.  */
 937 #define REGNAM_AL 1
 938 #define REGNAM_AX 25
 939 #define REGNAM_EAX 41
 940
 941 extern const reg_entry i386_regtab[];
 942 extern const unsigned int i386_regtab_size;
 943
 944 typedef struct
 945 {
 946   char *seg_name;
 947   unsigned int seg_prefix;
 948 }
 949 seg_entry;
 950
 951 extern const seg_entry cs;
 952 extern const seg_entry ds;
 953 extern const seg_entry ss;
 954 extern const seg_entry es;
 955 extern const seg_entry fs;
 956 extern const seg_entry gs;