1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Xsave/xrstor New Instructions support required */
117 /* Xsaveopt New Instructions support required */
119 /* AES support required */
121 /* PCLMUL support required */
123 /* FMA support required */
125 /* FMA4 support required */
127 /* XOP support required */
129 /* LWP support required */
131 /* BMI support required */
133 /* TBM support required */
135 /* MOVBE Instruction support required */
137 /* CMPXCHG16B instruction support required. */
139 /* EPT Instructions required */
141 /* RDTSCP Instruction support required */
143 /* FSGSBASE Instructions required */
145 /* RDRND Instructions required */
147 /* F16C Instructions required */
149 /* Intel BMI2 support required */
151 /* LZCNT support required */
153 /* HLE support required */
155 /* RTM support required */
157 /* INVPCID Instructions required */
159 /* VMFUNC Instruction required */
161 /* Intel MPX Instructions required */
163 /* 64bit support available, used by -march= in assembler. */
165 /* RDRSEED instruction required. */
167 /* Multi-presisionn add-carry instructions are required. */
169 /* Supports prefetchw and prefetch instructions. */
171 /* SMAP instructions required. */
173 /* SHA instructions required. */
175 /* VREX support required */
177 /* CLFLUSHOPT instruction required */
179 /* XSAVES/XRSTORS instruction required */
181 /* XSAVEC instruction required */
183 /* PREFETCHWT1 instruction required */
185 /* SE1 instruction required */
187 /* CLWB instruction required */
189 /* PCOMMIT instruction required */
191 /* 64bit support required */
193 /* Not supported in the 64bit mode */
195 /* The last bitfield in i386_cpu_flags. */
199 #define CpuNumOfUints \
200 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
201 #define CpuNumOfBits \
202 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
204 /* If you get a compiler error for zero width of the unused field,
206 #define CpuUnused (CpuMax + 1)
208 /* We can check if an instruction is available with array instead
210 typedef union i386_cpu_flags
214 unsigned int cpui186
:1;
215 unsigned int cpui286
:1;
216 unsigned int cpui386
:1;
217 unsigned int cpui486
:1;
218 unsigned int cpui586
:1;
219 unsigned int cpui686
:1;
220 unsigned int cpuclflush
:1;
221 unsigned int cpunop
:1;
222 unsigned int cpusyscall
:1;
223 unsigned int cpu8087
:1;
224 unsigned int cpu287
:1;
225 unsigned int cpu387
:1;
226 unsigned int cpu687
:1;
227 unsigned int cpufisttp
:1;
228 unsigned int cpummx
:1;
229 unsigned int cpusse
:1;
230 unsigned int cpusse2
:1;
231 unsigned int cpua3dnow
:1;
232 unsigned int cpua3dnowa
:1;
233 unsigned int cpusse3
:1;
234 unsigned int cpupadlock
:1;
235 unsigned int cpusvme
:1;
236 unsigned int cpuvmx
:1;
237 unsigned int cpusmx
:1;
238 unsigned int cpussse3
:1;
239 unsigned int cpusse4a
:1;
240 unsigned int cpuabm
:1;
241 unsigned int cpusse4_1
:1;
242 unsigned int cpusse4_2
:1;
243 unsigned int cpuavx
:1;
244 unsigned int cpuavx2
:1;
245 unsigned int cpuavx512f
:1;
246 unsigned int cpuavx512cd
:1;
247 unsigned int cpuavx512er
:1;
248 unsigned int cpuavx512pf
:1;
249 unsigned int cpuavx512vl
:1;
250 unsigned int cpuavx512dq
:1;
251 unsigned int cpuavx512bw
:1;
252 unsigned int cpul1om
:1;
253 unsigned int cpuk1om
:1;
254 unsigned int cpuxsave
:1;
255 unsigned int cpuxsaveopt
:1;
256 unsigned int cpuaes
:1;
257 unsigned int cpupclmul
:1;
258 unsigned int cpufma
:1;
259 unsigned int cpufma4
:1;
260 unsigned int cpuxop
:1;
261 unsigned int cpulwp
:1;
262 unsigned int cpubmi
:1;
263 unsigned int cputbm
:1;
264 unsigned int cpumovbe
:1;
265 unsigned int cpucx16
:1;
266 unsigned int cpuept
:1;
267 unsigned int cpurdtscp
:1;
268 unsigned int cpufsgsbase
:1;
269 unsigned int cpurdrnd
:1;
270 unsigned int cpuf16c
:1;
271 unsigned int cpubmi2
:1;
272 unsigned int cpulzcnt
:1;
273 unsigned int cpuhle
:1;
274 unsigned int cpurtm
:1;
275 unsigned int cpuinvpcid
:1;
276 unsigned int cpuvmfunc
:1;
277 unsigned int cpumpx
:1;
278 unsigned int cpulm
:1;
279 unsigned int cpurdseed
:1;
280 unsigned int cpuadx
:1;
281 unsigned int cpuprfchw
:1;
282 unsigned int cpusmap
:1;
283 unsigned int cpusha
:1;
284 unsigned int cpuvrex
:1;
285 unsigned int cpuclflushopt
:1;
286 unsigned int cpuxsaves
:1;
287 unsigned int cpuxsavec
:1;
288 unsigned int cpuprefetchwt1
:1;
289 unsigned int cpuse1
:1;
290 unsigned int cpuclwb
:1;
291 unsigned int cpupcommit
:1;
292 unsigned int cpu64
:1;
293 unsigned int cpuno64
:1;
295 unsigned int unused
:(CpuNumOfBits
- CpuUnused
);
298 unsigned int array
[CpuNumOfUints
];
301 /* Position of opcode_modifier bits. */
305 /* has direction bit. */
307 /* set if operands can be words or dwords encoded the canonical way */
309 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
310 operand in encoding. */
312 /* insn has a modrm byte. */
314 /* register is in low 3 bits of opcode */
316 /* special case for jump insns. */
322 /* special case for intersegment leaps/calls */
324 /* FP insn memory format bit, sized by 0x4 */
326 /* src/dest swap for floats. */
328 /* has float insn direction bit. */
330 /* needs size prefix if in 32-bit mode */
332 /* needs size prefix if in 16-bit mode */
334 /* needs size prefix if in 64-bit mode */
336 /* check register size. */
338 /* instruction ignores operand size prefix and in Intel mode ignores
339 mnemonic size suffix check. */
341 /* default insn size depends on mode */
343 /* b suffix on instruction illegal */
345 /* w suffix on instruction illegal */
347 /* l suffix on instruction illegal */
349 /* s suffix on instruction illegal */
351 /* q suffix on instruction illegal */
353 /* long double suffix on instruction illegal */
355 /* instruction needs FWAIT */
357 /* quick test for string instructions */
359 /* quick test if branch instruction is MPX supported */
361 /* quick test for lockable instructions */
363 /* fake an extra reg operand for clr, imul and special register
364 processing for some instructions. */
366 /* The first operand must be xmm0 */
368 /* An implicit xmm0 as the first operand */
370 /* The HLE prefix is OK:
371 1. With a LOCK prefix.
372 2. With or without a LOCK prefix.
373 3. With a RELEASE (0xf3) prefix.
375 #define HLEPrefixNone 0
376 #define HLEPrefixLock 1
377 #define HLEPrefixAny 2
378 #define HLEPrefixRelease 3
380 /* An instruction on which a "rep" prefix is acceptable. */
382 /* Convert to DWORD */
384 /* Convert to QWORD */
386 /* Address prefix changes operand 0 */
388 /* opcode is a prefix */
390 /* instruction has extension in 8 bit imm */
392 /* instruction don't need Rex64 prefix. */
394 /* instruction require Rex64 prefix. */
396 /* deprecated fp insn, gets a warning */
398 /* insn has VEX prefix:
399 1: 128bit VEX prefix.
400 2: 256bit VEX prefix.
401 3: Scalar VEX prefix.
407 /* How to encode VEX.vvvv:
408 0: VEX.vvvv must be 1111b.
409 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
410 the content of source registers will be preserved.
411 VEX.DDS. The second register operand is encoded in VEX.vvvv
412 where the content of first source register will be overwritten
414 VEX.NDD2. The second destination register operand is encoded in
415 VEX.vvvv for instructions with 2 destination register operands.
416 For assembler, there are no difference between VEX.NDS, VEX.DDS
418 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
419 instructions with 1 destination register operand.
420 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
421 of the operands can access a memory location.
427 /* How the VEX.W bit is used:
428 0: Set by the REX.W bit.
429 1: VEX.W0. Should always be 0.
430 2: VEX.W1. Should always be 1.
435 /* VEX opcode prefix:
436 0: VEX 0x0F opcode prefix.
437 1: VEX 0x0F38 opcode prefix.
438 2: VEX 0x0F3A opcode prefix
439 3: XOP 0x08 opcode prefix.
440 4: XOP 0x09 opcode prefix
441 5: XOP 0x0A opcode prefix.
450 /* number of VEX source operands:
451 0: <= 2 source operands.
452 1: 2 XOP source operands.
453 2: 3 source operands.
455 #define XOP2SOURCES 1
456 #define VEX3SOURCES 2
458 /* instruction has VEX 8 bit imm */
460 /* Instruction with vector SIB byte:
461 1: 128bit vector register.
462 2: 256bit vector register.
463 3: 512bit vector register.
469 /* SSE to AVX support required */
471 /* No AVX equivalent */
474 /* insn has EVEX prefix:
475 1: 512bit EVEX prefix.
476 2: 128bit EVEX prefix.
477 3: 256bit EVEX prefix.
478 4: Length-ignored (LIG) EVEX prefix.
486 /* AVX512 masking support:
489 3: Both zeroing and merging masking.
491 #define ZEROING_MASKING 1
492 #define MERGING_MASKING 2
493 #define BOTH_MASKING 3
496 /* Input element size of vector insn:
507 #define NO_BROADCAST 0
508 #define BROADCAST_1TO16 1
509 #define BROADCAST_1TO8 2
510 #define BROADCAST_1TO4 3
511 #define BROADCAST_1TO2 4
514 /* Static rounding control is supported. */
517 /* Supress All Exceptions is supported. */
520 /* Copressed Disp8*N attribute. */
523 /* Default mask isn't allowed. */
526 /* Compatible with old (<= 2.8.1) versions of gcc */
534 /* The last bitfield in i386_opcode_modifier. */
538 typedef struct i386_opcode_modifier
543 unsigned int modrm
:1;
544 unsigned int shortform
:1;
546 unsigned int jumpdword
:1;
547 unsigned int jumpbyte
:1;
548 unsigned int jumpintersegment
:1;
549 unsigned int floatmf
:1;
550 unsigned int floatr
:1;
551 unsigned int floatd
:1;
552 unsigned int size16
:1;
553 unsigned int size32
:1;
554 unsigned int size64
:1;
555 unsigned int checkregsize
:1;
556 unsigned int ignoresize
:1;
557 unsigned int defaultsize
:1;
558 unsigned int no_bsuf
:1;
559 unsigned int no_wsuf
:1;
560 unsigned int no_lsuf
:1;
561 unsigned int no_ssuf
:1;
562 unsigned int no_qsuf
:1;
563 unsigned int no_ldsuf
:1;
564 unsigned int fwait
:1;
565 unsigned int isstring
:1;
566 unsigned int bndprefixok
:1;
567 unsigned int islockable
:1;
568 unsigned int regkludge
:1;
569 unsigned int firstxmm0
:1;
570 unsigned int implicit1stxmm0
:1;
571 unsigned int hleprefixok
:2;
572 unsigned int repprefixok
:1;
573 unsigned int todword
:1;
574 unsigned int toqword
:1;
575 unsigned int addrprefixop0
:1;
576 unsigned int isprefix
:1;
577 unsigned int immext
:1;
578 unsigned int norex64
:1;
579 unsigned int rex64
:1;
582 unsigned int vexvvvv
:2;
584 unsigned int vexopcode
:3;
585 unsigned int vexsources
:2;
586 unsigned int veximmext
:1;
587 unsigned int vecsib
:2;
588 unsigned int sse2avx
:1;
589 unsigned int noavx
:1;
591 unsigned int masking
:2;
592 unsigned int vecesize
:1;
593 unsigned int broadcast
:3;
594 unsigned int staticrounding
:1;
596 unsigned int disp8memshift
:3;
597 unsigned int nodefmask
:1;
598 unsigned int oldgcc
:1;
599 unsigned int attmnemonic
:1;
600 unsigned int attsyntax
:1;
601 unsigned int intelsyntax
:1;
602 } i386_opcode_modifier
;
604 /* Position of operand_type bits. */
616 /* Floating pointer stack register */
624 /* AVX512 registers */
626 /* Vector Mask registers */
628 /* Control register */
634 /* 2 bit segment register */
636 /* 3 bit segment register */
638 /* 1 bit immediate */
640 /* 8 bit immediate */
642 /* 8 bit immediate sign extended */
644 /* 16 bit immediate */
646 /* 32 bit immediate */
648 /* 32 bit immediate sign extended */
650 /* 64 bit immediate */
652 /* 8bit/16bit/32bit displacements are used in different ways,
653 depending on the instruction. For jumps, they specify the
654 size of the PC relative displacement, for instructions with
655 memory operand, they specify the size of the offset relative
656 to the base register, and for instructions with memory offset
657 such as `mov 1234,%al' they specify the size of the offset
658 relative to the segment base. */
659 /* 8 bit displacement */
661 /* 16 bit displacement */
663 /* 32 bit displacement */
665 /* 32 bit signed displacement */
667 /* 64 bit displacement */
669 /* Accumulator %al/%ax/%eax/%rax */
671 /* Floating pointer top stack register %st(0) */
673 /* Register which can be used for base or index in memory operand. */
675 /* Register to hold in/out port addr = dx */
677 /* Register to hold shift count = cl */
679 /* Absolute address for jump. */
681 /* String insn operand with fixed es segment */
683 /* RegMem is for instructions with a modrm byte where the register
684 destination operand should be encoded in the mod and regmem fields.
685 Normally, it will be encoded in the reg field. We add a RegMem
686 flag to the destination register operand to indicate that it should
687 be encoded in the regmem field. */
693 /* WORD memory. 2 byte */
695 /* DWORD memory. 4 byte */
697 /* FWORD memory. 6 byte */
699 /* QWORD memory. 8 byte */
701 /* TBYTE memory. 10 byte */
703 /* XMMWORD memory. */
705 /* YMMWORD memory. */
707 /* ZMMWORD memory. */
709 /* Unspecified memory size. */
711 /* Any memory size. */
714 /* Vector 4 bit immediate. */
717 /* Bound register. */
720 /* Vector 8bit displacement */
723 /* The last bitfield in i386_operand_type. */
727 #define OTNumOfUints \
728 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
729 #define OTNumOfBits \
730 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
732 /* If you get a compiler error for zero width of the unused field,
734 #define OTUnused (OTMax + 1)
736 typedef union i386_operand_type
741 unsigned int reg16
:1;
742 unsigned int reg32
:1;
743 unsigned int reg64
:1;
744 unsigned int floatreg
:1;
745 unsigned int regmmx
:1;
746 unsigned int regxmm
:1;
747 unsigned int regymm
:1;
748 unsigned int regzmm
:1;
749 unsigned int regmask
:1;
750 unsigned int control
:1;
751 unsigned int debug
:1;
753 unsigned int sreg2
:1;
754 unsigned int sreg3
:1;
757 unsigned int imm8s
:1;
758 unsigned int imm16
:1;
759 unsigned int imm32
:1;
760 unsigned int imm32s
:1;
761 unsigned int imm64
:1;
762 unsigned int disp8
:1;
763 unsigned int disp16
:1;
764 unsigned int disp32
:1;
765 unsigned int disp32s
:1;
766 unsigned int disp64
:1;
768 unsigned int floatacc
:1;
769 unsigned int baseindex
:1;
770 unsigned int inoutportreg
:1;
771 unsigned int shiftcount
:1;
772 unsigned int jumpabsolute
:1;
773 unsigned int esseg
:1;
774 unsigned int regmem
:1;
778 unsigned int dword
:1;
779 unsigned int fword
:1;
780 unsigned int qword
:1;
781 unsigned int tbyte
:1;
782 unsigned int xmmword
:1;
783 unsigned int ymmword
:1;
784 unsigned int zmmword
:1;
785 unsigned int unspecified
:1;
786 unsigned int anysize
:1;
787 unsigned int vec_imm4
:1;
788 unsigned int regbnd
:1;
789 unsigned int vec_disp8
:1;
791 unsigned int unused
:(OTNumOfBits
- OTUnused
);
794 unsigned int array
[OTNumOfUints
];
797 typedef struct insn_template
799 /* instruction name sans width suffix ("mov" for movl insns) */
802 /* how many operands */
803 unsigned int operands
;
805 /* base_opcode is the fundamental opcode byte without optional
807 unsigned int base_opcode
;
808 #define Opcode_D 0x2 /* Direction bit:
809 set if Reg --> Regmem;
810 unset if Regmem --> Reg. */
811 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
812 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
814 /* extension_opcode is the 3 bit extension for group <n> insns.
815 This field is also used to store the 8-bit opcode suffix for the
816 AMD 3DNow! instructions.
817 If this template has no extension opcode (the usual case) use None
819 unsigned int extension_opcode
;
820 #define None 0xffff /* If no extension_opcode is possible. */
823 unsigned char opcode_length
;
825 /* cpu feature flags */
826 i386_cpu_flags cpu_flags
;
828 /* the bits in opcode_modifier are used to generate the final opcode from
829 the base_opcode. These bits also are used to detect alternate forms of
830 the same instruction */
831 i386_opcode_modifier opcode_modifier
;
833 /* operand_types[i] describes the type of operand i. This is made
834 by OR'ing together all of the possible type masks. (e.g.
835 'operand_types[i] = Reg|Imm' specifies that operand i can be
836 either a register or an immediate operand. */
837 i386_operand_type operand_types
[MAX_OPERANDS
];
841 extern const insn_template i386_optab
[];
843 /* these are for register name --> number & type hash lookup */
847 i386_operand_type reg_type
;
848 unsigned char reg_flags
;
849 #define RegRex 0x1 /* Extended register. */
850 #define RegRex64 0x2 /* Extended 8 bit register. */
851 #define RegVRex 0x4 /* Extended vector register. */
852 unsigned char reg_num
;
853 #define RegRip ((unsigned char ) ~0)
854 #define RegEip (RegRip - 1)
855 /* EIZ and RIZ are fake index registers. */
856 #define RegEiz (RegEip - 1)
857 #define RegRiz (RegEiz - 1)
858 /* FLAT is a fake segment register (Intel mode). */
859 #define RegFlat ((unsigned char) ~0)
860 signed char dw2_regnum
[2];
861 #define Dw2Inval (-1)
865 /* Entries in i386_regtab. */
868 #define REGNAM_EAX 41
870 extern const reg_entry i386_regtab
[];
871 extern const unsigned int i386_regtab_size
;
876 unsigned int seg_prefix
;
880 extern const seg_entry cs
;
881 extern const seg_entry ds
;
882 extern const seg_entry ss
;
883 extern const seg_entry es
;
884 extern const seg_entry fs
;
885 extern const seg_entry gs
;