opcodes/i386-opc.h

   1 /* Declarations for Intel 80386 opcode table
   2    Copyright (C) 2007-2018 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with GAS; see the file COPYING.  If not, write to the Free
  18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  19    02110-1301, USA.  */
  20
  21 #include "opcode/i386.h"
  22 #ifdef HAVE_LIMITS_H
  23 #include <limits.h>
  24 #endif
  25
  26 #ifndef CHAR_BIT
  27 #define CHAR_BIT 8
  28 #endif
  29
  30 /* Position of cpu flags bitfiled.  */
  31
  32 enum
  33 {
  34   /* i186 or better required */
  35   Cpu186 = 0,
  36   /* i286 or better required */
  37   Cpu286,
  38   /* i386 or better required */
  39   Cpu386,
  40   /* i486 or better required */
  41   Cpu486,
  42   /* i585 or better required */
  43   Cpu586,
  44   /* i686 or better required */
  45   Cpu686,
  46   /* CLFLUSH Instruction support required */
  47   CpuClflush,
  48   /* NOP Instruction support required */
  49   CpuNop,
  50   /* SYSCALL Instructions support required */
  51   CpuSYSCALL,
  52   /* Floating point support required */
  53   Cpu8087,
  54   /* i287 support required */
  55   Cpu287,
  56   /* i387 support required */
  57   Cpu387,
  58   /* i686 and floating point support required */
  59   Cpu687,
  60   /* SSE3 and floating point support required */
  61   CpuFISTTP,
  62   /* MMX support required */
  63   CpuMMX,
  64   /* SSE support required */
  65   CpuSSE,
  66   /* SSE2 support required */
  67   CpuSSE2,
  68   /* 3dnow! support required */
  69   Cpu3dnow,
  70   /* 3dnow! Extensions support required */
  71   Cpu3dnowA,
  72   /* SSE3 support required */
  73   CpuSSE3,
  74   /* VIA PadLock required */
  75   CpuPadLock,
  76   /* AMD Secure Virtual Machine Ext-s required */
  77   CpuSVME,
  78   /* VMX Instructions required */
  79   CpuVMX,
  80   /* SMX Instructions required */
  81   CpuSMX,
  82   /* SSSE3 support required */
  83   CpuSSSE3,
  84   /* SSE4a support required */
  85   CpuSSE4a,
  86   /* ABM New Instructions required */
  87   CpuABM,
  88   /* SSE4.1 support required */
  89   CpuSSE4_1,
  90   /* SSE4.2 support required */
  91   CpuSSE4_2,
  92   /* AVX support required */
  93   CpuAVX,
  94   /* AVX2 support required */
  95   CpuAVX2,
  96   /* Intel AVX-512 Foundation Instructions support required */
  97   CpuAVX512F,
  98   /* Intel AVX-512 Conflict Detection Instructions support required */
  99   CpuAVX512CD,
 100   /* Intel AVX-512 Exponential and Reciprocal Instructions support
 101      required */
 102   CpuAVX512ER,
 103   /* Intel AVX-512 Prefetch Instructions support required */
 104   CpuAVX512PF,
 105   /* Intel AVX-512 VL Instructions support required.  */
 106   CpuAVX512VL,
 107   /* Intel AVX-512 DQ Instructions support required.  */
 108   CpuAVX512DQ,
 109   /* Intel AVX-512 BW Instructions support required.  */
 110   CpuAVX512BW,
 111   /* Intel L1OM support required */
 112   CpuL1OM,
 113   /* Intel K1OM support required */
 114   CpuK1OM,
 115   /* Intel IAMCU support required */
 116   CpuIAMCU,
 117   /* Xsave/xrstor New Instructions support required */
 118   CpuXsave,
 119   /* Xsaveopt New Instructions support required */
 120   CpuXsaveopt,
 121   /* AES support required */
 122   CpuAES,
 123   /* PCLMUL support required */
 124   CpuPCLMUL,
 125   /* FMA support required */
 126   CpuFMA,
 127   /* FMA4 support required */
 128   CpuFMA4,
 129   /* XOP support required */
 130   CpuXOP,
 131   /* LWP support required */
 132   CpuLWP,
 133   /* BMI support required */
 134   CpuBMI,
 135   /* TBM support required */
 136   CpuTBM,
 137   /* MOVBE Instruction support required */
 138   CpuMovbe,
 139   /* CMPXCHG16B instruction support required.  */
 140   CpuCX16,
 141   /* EPT Instructions required */
 142   CpuEPT,
 143   /* RDTSCP Instruction support required */
 144   CpuRdtscp,
 145   /* FSGSBASE Instructions required */
 146   CpuFSGSBase,
 147   /* RDRND Instructions required */
 148   CpuRdRnd,
 149   /* F16C Instructions required */
 150   CpuF16C,
 151   /* Intel BMI2 support required */
 152   CpuBMI2,
 153   /* LZCNT support required */
 154   CpuLZCNT,
 155   /* HLE support required */
 156   CpuHLE,
 157   /* RTM support required */
 158   CpuRTM,
 159   /* INVPCID Instructions required */
 160   CpuINVPCID,
 161   /* VMFUNC Instruction required */
 162   CpuVMFUNC,
 163   /* Intel MPX Instructions required  */
 164   CpuMPX,
 165   /* 64bit support available, used by -march= in assembler.  */
 166   CpuLM,
 167   /* RDRSEED instruction required.  */
 168   CpuRDSEED,
 169   /* Multi-presisionn add-carry instructions are required.  */
 170   CpuADX,
 171   /* Supports prefetchw and prefetch instructions.  */
 172   CpuPRFCHW,
 173   /* SMAP instructions required.  */
 174   CpuSMAP,
 175   /* SHA instructions required.  */
 176   CpuSHA,
 177   /* VREX support required  */
 178   CpuVREX,
 179   /* CLFLUSHOPT instruction required */
 180   CpuClflushOpt,
 181   /* XSAVES/XRSTORS instruction required */
 182   CpuXSAVES,
 183   /* XSAVEC instruction required */
 184   CpuXSAVEC,
 185   /* PREFETCHWT1 instruction required */
 186   CpuPREFETCHWT1,
 187   /* SE1 instruction required */
 188   CpuSE1,
 189   /* CLWB instruction required */
 190   CpuCLWB,
 191   /* Intel AVX-512 IFMA Instructions support required.  */
 192   CpuAVX512IFMA,
 193   /* Intel AVX-512 VBMI Instructions support required.  */
 194   CpuAVX512VBMI,
 195   /* Intel AVX-512 4FMAPS Instructions support required.  */
 196   CpuAVX512_4FMAPS,
 197   /* Intel AVX-512 4VNNIW Instructions support required.  */
 198   CpuAVX512_4VNNIW,
 199   /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
 200   CpuAVX512_VPOPCNTDQ,
 201   /* Intel AVX-512 VBMI2 Instructions support required.  */
 202   CpuAVX512_VBMI2,
 203   /* Intel AVX-512 VNNI Instructions support required.  */
 204   CpuAVX512_VNNI,
 205   /* Intel AVX-512 BITALG Instructions support required.  */
 206   CpuAVX512_BITALG,
 207   /* mwaitx instruction required */
 208   CpuMWAITX,
 209   /* Clzero instruction required */
 210   CpuCLZERO,
 211   /* OSPKE instruction required */
 212   CpuOSPKE,
 213   /* RDPID instruction required */
 214   CpuRDPID,
 215   /* PTWRITE instruction required */
 216   CpuPTWRITE,
 217   /* CET instructions support required */
 218   CpuIBT,
 219   CpuSHSTK,
 220   /* GFNI instructions required */
 221   CpuGFNI,
 222   /* VAES instructions required */
 223   CpuVAES,
 224   /* VPCLMULQDQ instructions required */
 225   CpuVPCLMULQDQ,
 226   /* MMX register support required */
 227   CpuRegMMX,
 228   /* XMM register support required */
 229   CpuRegXMM,
 230   /* YMM register support required */
 231   CpuRegYMM,
 232   /* ZMM register support required */
 233   CpuRegZMM,
 234   /* Mask register support required */
 235   CpuRegMask,
 236   /* 64bit support required  */
 237   Cpu64,
 238   /* Not supported in the 64bit mode  */
 239   CpuNo64,
 240   /* The last bitfield in i386_cpu_flags.  */
 241   CpuMax = CpuNo64
 242 };
 243
 244 #define CpuNumOfUints \
 245   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
 246 #define CpuNumOfBits \
 247   (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 248
 249 /* If you get a compiler error for zero width of the unused field,
 250    comment it out.  */
 251 #define CpuUnused       (CpuMax + 1)
 252
 253 /* We can check if an instruction is available with array instead
 254    of bitfield. */
 255 typedef union i386_cpu_flags
 256 {
 257   struct
 258     {
 259       unsigned int cpui186:1;
 260       unsigned int cpui286:1;
 261       unsigned int cpui386:1;
 262       unsigned int cpui486:1;
 263       unsigned int cpui586:1;
 264       unsigned int cpui686:1;
 265       unsigned int cpuclflush:1;
 266       unsigned int cpunop:1;
 267       unsigned int cpusyscall:1;
 268       unsigned int cpu8087:1;
 269       unsigned int cpu287:1;
 270       unsigned int cpu387:1;
 271       unsigned int cpu687:1;
 272       unsigned int cpufisttp:1;
 273       unsigned int cpummx:1;
 274       unsigned int cpusse:1;
 275       unsigned int cpusse2:1;
 276       unsigned int cpua3dnow:1;
 277       unsigned int cpua3dnowa:1;
 278       unsigned int cpusse3:1;
 279       unsigned int cpupadlock:1;
 280       unsigned int cpusvme:1;
 281       unsigned int cpuvmx:1;
 282       unsigned int cpusmx:1;
 283       unsigned int cpussse3:1;
 284       unsigned int cpusse4a:1;
 285       unsigned int cpuabm:1;
 286       unsigned int cpusse4_1:1;
 287       unsigned int cpusse4_2:1;
 288       unsigned int cpuavx:1;
 289       unsigned int cpuavx2:1;
 290       unsigned int cpuavx512f:1;
 291       unsigned int cpuavx512cd:1;
 292       unsigned int cpuavx512er:1;
 293       unsigned int cpuavx512pf:1;
 294       unsigned int cpuavx512vl:1;
 295       unsigned int cpuavx512dq:1;
 296       unsigned int cpuavx512bw:1;
 297       unsigned int cpul1om:1;
 298       unsigned int cpuk1om:1;
 299       unsigned int cpuiamcu:1;
 300       unsigned int cpuxsave:1;
 301       unsigned int cpuxsaveopt:1;
 302       unsigned int cpuaes:1;
 303       unsigned int cpupclmul:1;
 304       unsigned int cpufma:1;
 305       unsigned int cpufma4:1;
 306       unsigned int cpuxop:1;
 307       unsigned int cpulwp:1;
 308       unsigned int cpubmi:1;
 309       unsigned int cputbm:1;
 310       unsigned int cpumovbe:1;
 311       unsigned int cpucx16:1;
 312       unsigned int cpuept:1;
 313       unsigned int cpurdtscp:1;
 314       unsigned int cpufsgsbase:1;
 315       unsigned int cpurdrnd:1;
 316       unsigned int cpuf16c:1;
 317       unsigned int cpubmi2:1;
 318       unsigned int cpulzcnt:1;
 319       unsigned int cpuhle:1;
 320       unsigned int cpurtm:1;
 321       unsigned int cpuinvpcid:1;
 322       unsigned int cpuvmfunc:1;
 323       unsigned int cpumpx:1;
 324       unsigned int cpulm:1;
 325       unsigned int cpurdseed:1;
 326       unsigned int cpuadx:1;
 327       unsigned int cpuprfchw:1;
 328       unsigned int cpusmap:1;
 329       unsigned int cpusha:1;
 330       unsigned int cpuvrex:1;
 331       unsigned int cpuclflushopt:1;
 332       unsigned int cpuxsaves:1;
 333       unsigned int cpuxsavec:1;
 334       unsigned int cpuprefetchwt1:1;
 335       unsigned int cpuse1:1;
 336       unsigned int cpuclwb:1;
 337       unsigned int cpuavx512ifma:1;
 338       unsigned int cpuavx512vbmi:1;
 339       unsigned int cpuavx512_4fmaps:1;
 340       unsigned int cpuavx512_4vnniw:1;
 341       unsigned int cpuavx512_vpopcntdq:1;
 342       unsigned int cpuavx512_vbmi2:1;
 343       unsigned int cpuavx512_vnni:1;
 344       unsigned int cpuavx512_bitalg:1;
 345       unsigned int cpumwaitx:1;
 346       unsigned int cpuclzero:1;
 347       unsigned int cpuospke:1;
 348       unsigned int cpurdpid:1;
 349       unsigned int cpuptwrite:1;
 350       unsigned int cpuibt:1;
 351       unsigned int cpushstk:1;
 352       unsigned int cpugfni:1;
 353       unsigned int cpuvaes:1;
 354       unsigned int cpuvpclmulqdq:1;
 355       unsigned int cpuregmmx:1;
 356       unsigned int cpuregxmm:1;
 357       unsigned int cpuregymm:1;
 358       unsigned int cpuregzmm:1;
 359       unsigned int cpuregmask:1;
 360       unsigned int cpu64:1;
 361       unsigned int cpuno64:1;
 362 #ifdef CpuUnused
 363       unsigned int unused:(CpuNumOfBits - CpuUnused);
 364 #endif
 365     } bitfield;
 366   unsigned int array[CpuNumOfUints];
 367 } i386_cpu_flags;
 368
 369 /* Position of opcode_modifier bits.  */
 370
 371 enum
 372 {
 373   /* has direction bit. */
 374   D = 0,
 375   /* set if operands can be words or dwords encoded the canonical way */
 376   W,
 377   /* load form instruction. Must be placed before store form.  */
 378   Load,
 379   /* insn has a modrm byte. */
 380   Modrm,
 381   /* register is in low 3 bits of opcode */
 382   ShortForm,
 383   /* special case for jump insns.  */
 384   Jump,
 385   /* call and jump */
 386   JumpDword,
 387   /* loop and jecxz */
 388   JumpByte,
 389   /* special case for intersegment leaps/calls */
 390   JumpInterSegment,
 391   /* FP insn memory format bit, sized by 0x4 */
 392   FloatMF,
 393   /* src/dest swap for floats. */
 394   FloatR,
 395   /* has float insn direction bit. */
 396   FloatD,
 397   /* needs size prefix if in 32-bit mode */
 398   Size16,
 399   /* needs size prefix if in 16-bit mode */
 400   Size32,
 401   /* needs size prefix if in 64-bit mode */
 402   Size64,
 403   /* check register size.  */
 404   CheckRegSize,
 405   /* instruction ignores operand size prefix and in Intel mode ignores
 406      mnemonic size suffix check.  */
 407   IgnoreSize,
 408   /* default insn size depends on mode */
 409   DefaultSize,
 410   /* b suffix on instruction illegal */
 411   No_bSuf,
 412   /* w suffix on instruction illegal */
 413   No_wSuf,
 414   /* l suffix on instruction illegal */
 415   No_lSuf,
 416   /* s suffix on instruction illegal */
 417   No_sSuf,
 418   /* q suffix on instruction illegal */
 419   No_qSuf,
 420   /* long double suffix on instruction illegal */
 421   No_ldSuf,
 422   /* instruction needs FWAIT */
 423   FWait,
 424   /* quick test for string instructions */
 425   IsString,
 426   /* quick test if branch instruction is MPX supported */
 427   BNDPrefixOk,
 428   /* quick test if NOTRACK prefix is supported */
 429   NoTrackPrefixOk,
 430   /* quick test for lockable instructions */
 431   IsLockable,
 432   /* fake an extra reg operand for clr, imul and special register
 433      processing for some instructions.  */
 434   RegKludge,
 435   /* An implicit xmm0 as the first operand */
 436   Implicit1stXmm0,
 437   /* The HLE prefix is OK:
 438      1. With a LOCK prefix.
 439      2. With or without a LOCK prefix.
 440      3. With a RELEASE (0xf3) prefix.
 441    */
 442 #define HLEPrefixNone           0
 443 #define HLEPrefixLock           1
 444 #define HLEPrefixAny            2
 445 #define HLEPrefixRelease        3
 446   HLEPrefixOk,
 447   /* An instruction on which a "rep" prefix is acceptable.  */
 448   RepPrefixOk,
 449   /* Convert to DWORD */
 450   ToDword,
 451   /* Convert to QWORD */
 452   ToQword,
 453   /* Address prefix changes operand 0 */
 454   AddrPrefixOp0,
 455   /* opcode is a prefix */
 456   IsPrefix,
 457   /* instruction has extension in 8 bit imm */
 458   ImmExt,
 459   /* instruction don't need Rex64 prefix.  */
 460   NoRex64,
 461   /* instruction require Rex64 prefix.  */
 462   Rex64,
 463   /* deprecated fp insn, gets a warning */
 464   Ugh,
 465   /* insn has VEX prefix:
 466         1: 128bit VEX prefix (or operand dependent).
 467         2: 256bit VEX prefix.
 468         3: Scalar VEX prefix.
 469    */
 470 #define VEX128          1
 471 #define VEX256          2
 472 #define VEXScalar       3
 473   Vex,
 474   /* How to encode VEX.vvvv:
 475      0: VEX.vvvv must be 1111b.
 476      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
 477         the content of source registers will be preserved.
 478         VEX.DDS.  The second register operand is encoded in VEX.vvvv
 479         where the content of first source register will be overwritten
 480         by the result.
 481         VEX.NDD2.  The second destination register operand is encoded in
 482         VEX.vvvv for instructions with 2 destination register operands.
 483         For assembler, there are no difference between VEX.NDS, VEX.DDS
 484         and VEX.NDD2.
 485      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
 486      instructions with 1 destination register operand.
 487      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 488         of the operands can access a memory location.
 489    */
 490 #define VEXXDS  1
 491 #define VEXNDD  2
 492 #define VEXLWP  3
 493   VexVVVV,
 494   /* How the VEX.W bit is used:
 495      0: Set by the REX.W bit.
 496      1: VEX.W0.  Should always be 0.
 497      2: VEX.W1.  Should always be 1.
 498    */
 499 #define VEXW0   1
 500 #define VEXW1   2
 501   VexW,
 502   /* VEX opcode prefix:
 503      0: VEX 0x0F opcode prefix.
 504      1: VEX 0x0F38 opcode prefix.
 505      2: VEX 0x0F3A opcode prefix
 506      3: XOP 0x08 opcode prefix.
 507      4: XOP 0x09 opcode prefix
 508      5: XOP 0x0A opcode prefix.
 509    */
 510 #define VEX0F           0
 511 #define VEX0F38         1
 512 #define VEX0F3A         2
 513 #define XOP08           3
 514 #define XOP09           4
 515 #define XOP0A           5
 516   VexOpcode,
 517   /* number of VEX source operands:
 518      0: <= 2 source operands.
 519      1: 2 XOP source operands.
 520      2: 3 source operands.
 521    */
 522 #define XOP2SOURCES     1
 523 #define VEX3SOURCES     2
 524   VexSources,
 525   /* instruction has VEX 8 bit imm */
 526   VexImmExt,
 527   /* Instruction with vector SIB byte:
 528         1: 128bit vector register.
 529         2: 256bit vector register.
 530         3: 512bit vector register.
 531    */
 532 #define VecSIB128       1
 533 #define VecSIB256       2
 534 #define VecSIB512       3
 535   VecSIB,
 536   /* SSE to AVX support required */
 537   SSE2AVX,
 538   /* No AVX equivalent */
 539   NoAVX,
 540
 541   /* insn has EVEX prefix:
 542         1: 512bit EVEX prefix.
 543         2: 128bit EVEX prefix.
 544         3: 256bit EVEX prefix.
 545         4: Length-ignored (LIG) EVEX prefix.
 546    */
 547 #define EVEX512                1
 548 #define EVEX128                2
 549 #define EVEX256                3
 550 #define EVEXLIG                4
 551   EVex,
 552
 553   /* AVX512 masking support:
 554         1: Zeroing-masking.
 555         2: Merging-masking.
 556         3: Both zeroing and merging masking.
 557    */
 558 #define ZEROING_MASKING 1
 559 #define MERGING_MASKING 2
 560 #define BOTH_MASKING    3
 561   Masking,
 562
 563   /* Input element size of vector insn:
 564         0: 32bit.
 565         1: 64bit.
 566    */
 567   VecESize,
 568
 569   /* Broadcast factor.
 570         0: No broadcast.
 571         1: 1to16 broadcast.
 572         2: 1to8 broadcast.
 573    */
 574 #define NO_BROADCAST    0
 575 #define BROADCAST_1TO16 1
 576 #define BROADCAST_1TO8  2
 577 #define BROADCAST_1TO4  3
 578 #define BROADCAST_1TO2  4
 579   Broadcast,
 580
 581   /* Static rounding control is supported.  */
 582   StaticRounding,
 583
 584   /* Supress All Exceptions is supported.  */
 585   SAE,
 586
 587   /* Copressed Disp8*N attribute.  */
 588   Disp8MemShift,
 589
 590   /* Default mask isn't allowed.  */
 591   NoDefMask,
 592
 593   /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
 594      It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
 595    */
 596   ImplicitQuadGroup,
 597
 598   /* Compatible with old (<= 2.8.1) versions of gcc  */
 599   OldGcc,
 600   /* AT&T mnemonic.  */
 601   ATTMnemonic,
 602   /* AT&T syntax.  */
 603   ATTSyntax,
 604   /* Intel syntax.  */
 605   IntelSyntax,
 606   /* AMD64.  */
 607   AMD64,
 608   /* Intel64.  */
 609   Intel64,
 610   /* The last bitfield in i386_opcode_modifier.  */
 611   Opcode_Modifier_Max
 612 };
 613
 614 typedef struct i386_opcode_modifier
 615 {
 616   unsigned int d:1;
 617   unsigned int w:1;
 618   unsigned int load:1;
 619   unsigned int modrm:1;
 620   unsigned int shortform:1;
 621   unsigned int jump:1;
 622   unsigned int jumpdword:1;
 623   unsigned int jumpbyte:1;
 624   unsigned int jumpintersegment:1;
 625   unsigned int floatmf:1;
 626   unsigned int floatr:1;
 627   unsigned int floatd:1;
 628   unsigned int size16:1;
 629   unsigned int size32:1;
 630   unsigned int size64:1;
 631   unsigned int checkregsize:1;
 632   unsigned int ignoresize:1;
 633   unsigned int defaultsize:1;
 634   unsigned int no_bsuf:1;
 635   unsigned int no_wsuf:1;
 636   unsigned int no_lsuf:1;
 637   unsigned int no_ssuf:1;
 638   unsigned int no_qsuf:1;
 639   unsigned int no_ldsuf:1;
 640   unsigned int fwait:1;
 641   unsigned int isstring:1;
 642   unsigned int bndprefixok:1;
 643   unsigned int notrackprefixok:1;
 644   unsigned int islockable:1;
 645   unsigned int regkludge:1;
 646   unsigned int implicit1stxmm0:1;
 647   unsigned int hleprefixok:2;
 648   unsigned int repprefixok:1;
 649   unsigned int todword:1;
 650   unsigned int toqword:1;
 651   unsigned int addrprefixop0:1;
 652   unsigned int isprefix:1;
 653   unsigned int immext:1;
 654   unsigned int norex64:1;
 655   unsigned int rex64:1;
 656   unsigned int ugh:1;
 657   unsigned int vex:2;
 658   unsigned int vexvvvv:2;
 659   unsigned int vexw:2;
 660   unsigned int vexopcode:3;
 661   unsigned int vexsources:2;
 662   unsigned int veximmext:1;
 663   unsigned int vecsib:2;
 664   unsigned int sse2avx:1;
 665   unsigned int noavx:1;
 666   unsigned int evex:3;
 667   unsigned int masking:2;
 668   unsigned int vecesize:1;
 669   unsigned int broadcast:3;
 670   unsigned int staticrounding:1;
 671   unsigned int sae:1;
 672   unsigned int disp8memshift:3;
 673   unsigned int nodefmask:1;
 674   unsigned int implicitquadgroup:1;
 675   unsigned int oldgcc:1;
 676   unsigned int attmnemonic:1;
 677   unsigned int attsyntax:1;
 678   unsigned int intelsyntax:1;
 679   unsigned int amd64:1;
 680   unsigned int intel64:1;
 681 } i386_opcode_modifier;
 682
 683 /* Position of operand_type bits.  */
 684
 685 enum
 686 {
 687   /* Register (qualified by Byte, Word, etc) */
 688   Reg = 0,
 689   /* MMX register */
 690   RegMMX,
 691   /* Vector registers */
 692   RegSIMD,
 693   /* Vector Mask registers */
 694   RegMask,
 695   /* Control register */
 696   Control,
 697   /* Debug register */
 698   Debug,
 699   /* Test register */
 700   Test,
 701   /* 2 bit segment register */
 702   SReg2,
 703   /* 3 bit segment register */
 704   SReg3,
 705   /* 1 bit immediate */
 706   Imm1,
 707   /* 8 bit immediate */
 708   Imm8,
 709   /* 8 bit immediate sign extended */
 710   Imm8S,
 711   /* 16 bit immediate */
 712   Imm16,
 713   /* 32 bit immediate */
 714   Imm32,
 715   /* 32 bit immediate sign extended */
 716   Imm32S,
 717   /* 64 bit immediate */
 718   Imm64,
 719   /* 8bit/16bit/32bit displacements are used in different ways,
 720      depending on the instruction.  For jumps, they specify the
 721      size of the PC relative displacement, for instructions with
 722      memory operand, they specify the size of the offset relative
 723      to the base register, and for instructions with memory offset
 724      such as `mov 1234,%al' they specify the size of the offset
 725      relative to the segment base.  */
 726   /* 8 bit displacement */
 727   Disp8,
 728   /* 16 bit displacement */
 729   Disp16,
 730   /* 32 bit displacement */
 731   Disp32,
 732   /* 32 bit signed displacement */
 733   Disp32S,
 734   /* 64 bit displacement */
 735   Disp64,
 736   /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
 737   Acc,
 738   /* Register which can be used for base or index in memory operand.  */
 739   BaseIndex,
 740   /* Register to hold in/out port addr = dx */
 741   InOutPortReg,
 742   /* Register to hold shift count = cl */
 743   ShiftCount,
 744   /* Absolute address for jump.  */
 745   JumpAbsolute,
 746   /* String insn operand with fixed es segment */
 747   EsSeg,
 748   /* RegMem is for instructions with a modrm byte where the register
 749      destination operand should be encoded in the mod and regmem fields.
 750      Normally, it will be encoded in the reg field. We add a RegMem
 751      flag to the destination register operand to indicate that it should
 752      be encoded in the regmem field.  */
 753   RegMem,
 754   /* Memory.  */
 755   Mem,
 756   /* BYTE memory. */
 757   Byte,
 758   /* WORD memory. 2 byte */
 759   Word,
 760   /* DWORD memory. 4 byte */
 761   Dword,
 762   /* FWORD memory. 6 byte */
 763   Fword,
 764   /* QWORD memory. 8 byte */
 765   Qword,
 766   /* TBYTE memory. 10 byte */
 767   Tbyte,
 768   /* XMMWORD memory. */
 769   Xmmword,
 770   /* YMMWORD memory. */
 771   Ymmword,
 772   /* ZMMWORD memory.  */
 773   Zmmword,
 774   /* Unspecified memory size.  */
 775   Unspecified,
 776   /* Any memory size.  */
 777   Anysize,
 778
 779   /* Vector 4 bit immediate.  */
 780   Vec_Imm4,
 781
 782   /* Bound register.  */
 783   RegBND,
 784
 785   /* The last bitfield in i386_operand_type.  */
 786   OTMax
 787 };
 788
 789 #define OTNumOfUints \
 790   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
 791 #define OTNumOfBits \
 792   (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
 793
 794 /* If you get a compiler error for zero width of the unused field,
 795    comment it out.  */
 796 #define OTUnused                (OTMax + 1)
 797
 798 typedef union i386_operand_type
 799 {
 800   struct
 801     {
 802       unsigned int reg:1;
 803       unsigned int regmmx:1;
 804       unsigned int regsimd:1;
 805       unsigned int regmask:1;
 806       unsigned int control:1;
 807       unsigned int debug:1;
 808       unsigned int test:1;
 809       unsigned int sreg2:1;
 810       unsigned int sreg3:1;
 811       unsigned int imm1:1;
 812       unsigned int imm8:1;
 813       unsigned int imm8s:1;
 814       unsigned int imm16:1;
 815       unsigned int imm32:1;
 816       unsigned int imm32s:1;
 817       unsigned int imm64:1;
 818       unsigned int disp8:1;
 819       unsigned int disp16:1;
 820       unsigned int disp32:1;
 821       unsigned int disp32s:1;
 822       unsigned int disp64:1;
 823       unsigned int acc:1;
 824       unsigned int baseindex:1;
 825       unsigned int inoutportreg:1;
 826       unsigned int shiftcount:1;
 827       unsigned int jumpabsolute:1;
 828       unsigned int esseg:1;
 829       unsigned int regmem:1;
 830       unsigned int mem:1;
 831       unsigned int byte:1;
 832       unsigned int word:1;
 833       unsigned int dword:1;
 834       unsigned int fword:1;
 835       unsigned int qword:1;
 836       unsigned int tbyte:1;
 837       unsigned int xmmword:1;
 838       unsigned int ymmword:1;
 839       unsigned int zmmword:1;
 840       unsigned int unspecified:1;
 841       unsigned int anysize:1;
 842       unsigned int vec_imm4:1;
 843       unsigned int regbnd:1;
 844 #ifdef OTUnused
 845       unsigned int unused:(OTNumOfBits - OTUnused);
 846 #endif
 847     } bitfield;
 848   unsigned int array[OTNumOfUints];
 849 } i386_operand_type;
 850
 851 typedef struct insn_template
 852 {
 853   /* instruction name sans width suffix ("mov" for movl insns) */
 854   char *name;
 855
 856   /* how many operands */
 857   unsigned int operands;
 858
 859   /* base_opcode is the fundamental opcode byte without optional
 860      prefix(es).  */
 861   unsigned int base_opcode;
 862 #define Opcode_D        0x2 /* Direction bit:
 863                                set if Reg --> Regmem;
 864                                unset if Regmem --> Reg. */
 865 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 866 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 867
 868   /* extension_opcode is the 3 bit extension for group <n> insns.
 869      This field is also used to store the 8-bit opcode suffix for the
 870      AMD 3DNow! instructions.
 871      If this template has no extension opcode (the usual case) use None
 872      Instructions */
 873   unsigned int extension_opcode;
 874 #define None 0xffff             /* If no extension_opcode is possible.  */
 875
 876   /* Opcode length.  */
 877   unsigned char opcode_length;
 878
 879   /* cpu feature flags */
 880   i386_cpu_flags cpu_flags;
 881
 882   /* the bits in opcode_modifier are used to generate the final opcode from
 883      the base_opcode.  These bits also are used to detect alternate forms of
 884      the same instruction */
 885   i386_opcode_modifier opcode_modifier;
 886
 887   /* operand_types[i] describes the type of operand i.  This is made
 888      by OR'ing together all of the possible type masks.  (e.g.
 889      'operand_types[i] = Reg|Imm' specifies that operand i can be
 890      either a register or an immediate operand.  */
 891   i386_operand_type operand_types[MAX_OPERANDS];
 892 }
 893 insn_template;
 894
 895 extern const insn_template i386_optab[];
 896
 897 /* these are for register name --> number & type hash lookup */
 898 typedef struct
 899 {
 900   char *reg_name;
 901   i386_operand_type reg_type;
 902   unsigned char reg_flags;
 903 #define RegRex      0x1  /* Extended register.  */
 904 #define RegRex64    0x2  /* Extended 8 bit register.  */
 905 #define RegVRex     0x4  /* Extended vector register.  */
 906   unsigned char reg_num;
 907 #define RegRip  ((unsigned char ) ~0)
 908 #define RegEip  (RegRip - 1)
 909 /* EIZ and RIZ are fake index registers.  */
 910 #define RegEiz  (RegEip - 1)
 911 #define RegRiz  (RegEiz - 1)
 912 /* FLAT is a fake segment register (Intel mode).  */
 913 #define RegFlat     ((unsigned char) ~0)
 914   signed char dw2_regnum[2];
 915 #define Dw2Inval (-1)
 916 }
 917 reg_entry;
 918
 919 /* Entries in i386_regtab.  */
 920 #define REGNAM_AL 1
 921 #define REGNAM_AX 25
 922 #define REGNAM_EAX 41
 923
 924 extern const reg_entry i386_regtab[];
 925 extern const unsigned int i386_regtab_size;
 926
 927 typedef struct
 928 {
 929   char *seg_name;
 930   unsigned int seg_prefix;
 931 }
 932 seg_entry;
 933
 934 extern const seg_entry cs;
 935 extern const seg_entry ds;
 936 extern const seg_entry ss;
 937 extern const seg_entry es;
 938 extern const seg_entry fs;
 939 extern const seg_entry gs;