opcodes/i960c-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 THIS FILE IS USED TO GENERATE i960c-opc.c.
   5
   6 Copyright (C) 1998, 1999 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software Foundation, Inc.,
  22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "i960c-opc.h"
  31 #include "opintl.h"
  32
  33 /* Used by the ifield rtx function.  */
  34 #define FLD(f) (fields->f)
  35
  36 /* The hash functions are recorded here to help keep assembler code out of
  37    the disassembler and vice versa.  */
  38
  39 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
  40 static unsigned int asm_hash_insn PARAMS ((const char *));
  41 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
  42 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
  43
  44 /* Look up instruction INSN_VALUE and extract its fields.
  45    INSN, if non-null, is the insn table entry.
  46    Otherwise INSN_VALUE is examined to compute it.
  47    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  48    0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
  49    If INSN != NULL, LENGTH must be valid.
  50    ALIAS_P is non-zero if alias insns are to be included in the search.
  51
  52    The result is a pointer to the insn table entry, or NULL if the instruction
  53    wasn't recognized.  */
  54
  55 const CGEN_INSN *
  56 i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
  57      CGEN_OPCODE_DESC od;
  58      const CGEN_INSN *insn;
  59      CGEN_INSN_BYTES insn_value;
  60      int length;
  61      CGEN_FIELDS *fields;
  62      int alias_p;
  63 {
  64   unsigned char buf[CGEN_MAX_INSN_SIZE];
  65   unsigned char *bufp;
  66   CGEN_INSN_INT base_insn;
  67 #if CGEN_INT_INSN_P
  68   CGEN_EXTRACT_INFO *info = NULL;
  69 #else
  70   CGEN_EXTRACT_INFO ex_info;
  71   CGEN_EXTRACT_INFO *info = &ex_info;
  72 #endif
  73
  74 #if CGEN_INT_INSN_P
  75   cgen_put_insn_value (od, buf, length, insn_value);
  76   bufp = buf;
  77   base_insn = insn_value; /*???*/
  78 #else
  79   ex_info.dis_info = NULL;
  80   ex_info.insn_bytes = insn_value;
  81   ex_info.valid = -1;
  82   base_insn = cgen_get_insn_value (od, buf, length);
  83   bufp = insn_value;
  84 #endif
  85
  86   if (!insn)
  87     {
  88       const CGEN_INSN_LIST *insn_list;
  89
  90       /* The instructions are stored in hash lists.
  91          Pick the first one and keep trying until we find the right one.  */
  92
  93       insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
  94       while (insn_list != NULL)
  95         {
  96           insn = insn_list->insn;
  97
  98           if (alias_p
  99               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 100             {
 101               /* Basic bit mask must be correct.  */
 102               /* ??? May wish to allow target to defer this check until the
 103                  extract handler.  */
 104               if ((base_insn & CGEN_INSN_BASE_MASK (insn))
 105                   == CGEN_INSN_BASE_VALUE (insn))
 106                 {
 107                   /* ??? 0 is passed for `pc' */
 108                   int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
 109                                                            base_insn, fields,
 110                                                            (bfd_vma) 0);
 111                   if (elength > 0)
 112                     {
 113                       /* sanity check */
 114                       if (length != 0 && length != elength)
 115                         abort ();
 116                       return insn;
 117                     }
 118                 }
 119             }
 120
 121           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 122         }
 123     }
 124   else
 125     {
 126       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 127       if (! alias_p
 128           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 129         abort ();
 130       /* Sanity check: length must be correct.  */
 131       if (length != CGEN_INSN_BITSIZE (insn))
 132         abort ();
 133
 134       /* ??? 0 is passed for `pc' */
 135       length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
 136                                           (bfd_vma) 0);
 137       /* Sanity check: must succeed.
 138          Could relax this later if it ever proves useful.  */
 139       if (length == 0)
 140         abort ();
 141       return insn;
 142     }
 143
 144   return NULL;
 145 }
 146
 147 /* Fill in the operand instances used by INSN whose operands are FIELDS.
 148    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 149    in.  */
 150
 151 void
 152 i960_cgen_get_insn_operands (od, insn, fields, indices)
 153      CGEN_OPCODE_DESC od;
 154      const CGEN_INSN * insn;
 155      const CGEN_FIELDS * fields;
 156      int *indices;
 157 {
 158   const CGEN_OPERAND_INSTANCE *opinst;
 159   int i;
 160
 161   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 162        opinst != NULL
 163          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 164        ++i, ++opinst)
 165     {
 166       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 167       if (op == NULL)
 168         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 169       else
 170         indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
 171                                                   fields);
 172     }
 173 }
 174
 175 /* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
 176    isn't known.
 177    The INSN, INSN_VALUE, and LENGTH arguments are passed to
 178    i960_cgen_lookup_insn unchanged.
 179
 180    The result is the insn table entry or NULL if the instruction wasn't
 181    recognized.  */
 182
 183 const CGEN_INSN *
 184 i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
 185      CGEN_OPCODE_DESC od;
 186      const CGEN_INSN *insn;
 187      CGEN_INSN_BYTES insn_value;
 188      int length;
 189      int *indices;
 190 {
 191   CGEN_FIELDS fields;
 192
 193   /* Pass non-zero for ALIAS_P only if INSN != NULL.
 194      If INSN == NULL, we want a real insn.  */
 195   insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields,
 196                                   insn != NULL);
 197   if (! insn)
 198     return NULL;
 199
 200   i960_cgen_get_insn_operands (od, insn, &fields, indices);
 201   return insn;
 202 }
 203 /* Attributes.  */
 204
 205 static const CGEN_ATTR_ENTRY bool_attr[] =
 206 {
 207   { "#f", 0 },
 208   { "#t", 1 },
 209   { 0, 0 }
 210 };
 211
 212 static const CGEN_ATTR_ENTRY MACH_attr[] =
 213 {
 214   { "base", MACH_BASE },
 215   { "i960_ka_sa", MACH_I960_KA_SA },
 216   { "i960_ca", MACH_I960_CA },
 217   { "max", MACH_MAX },
 218   { 0, 0 }
 219 };
 220
 221 const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
 222 {
 223   { "MACH", & MACH_attr[0] },
 224   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 225   { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
 226   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 227   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 228   { "RESERVED", &bool_attr[0], &bool_attr[0] },
 229   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 230   { 0, 0, 0 }
 231 };
 232
 233 const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
 234 {
 235   { "MACH", & MACH_attr[0] },
 236   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 237   { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
 238   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 239   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
 240   { "FUN-ACCESS", &bool_attr[0], &bool_attr[0] },
 241   { "PC", &bool_attr[0], &bool_attr[0] },
 242   { "PROFILE", &bool_attr[0], &bool_attr[0] },
 243   { 0, 0, 0 }
 244 };
 245
 246 const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
 247 {
 248   { "MACH", & MACH_attr[0] },
 249   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 250   { "UNSIGNED", &bool_attr[0], &bool_attr[0] },
 251   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 252   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 253   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 254   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 255   { "RELAX", &bool_attr[0], &bool_attr[0] },
 256   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 257   { 0, 0, 0 }
 258 };
 259
 260 const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
 261 {
 262   { "MACH", & MACH_attr[0] },
 263   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 264   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 265   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 266   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 267   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 268   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 269   { "RELAX", &bool_attr[0], &bool_attr[0] },
 270   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 271   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 272   { "PBB", &bool_attr[0], &bool_attr[0] },
 273   { 0, 0, 0 }
 274 };
 275
 276 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
 277 {
 278   { "fp", 31 },
 279   { "sp", 1 },
 280   { "r0", 0 },
 281   { "r1", 1 },
 282   { "r2", 2 },
 283   { "r3", 3 },
 284   { "r4", 4 },
 285   { "r5", 5 },
 286   { "r6", 6 },
 287   { "r7", 7 },
 288   { "r8", 8 },
 289   { "r9", 9 },
 290   { "r10", 10 },
 291   { "r11", 11 },
 292   { "r12", 12 },
 293   { "r13", 13 },
 294   { "r14", 14 },
 295   { "r15", 15 },
 296   { "g0", 16 },
 297   { "g1", 17 },
 298   { "g2", 18 },
 299   { "g3", 19 },
 300   { "g4", 20 },
 301   { "g5", 21 },
 302   { "g6", 22 },
 303   { "g7", 23 },
 304   { "g8", 24 },
 305   { "g9", 25 },
 306   { "g10", 26 },
 307   { "g11", 27 },
 308   { "g12", 28 },
 309   { "g13", 29 },
 310   { "g14", 30 },
 311   { "g15", 31 }
 312 };
 313
 314 CGEN_KEYWORD i960_cgen_opval_h_gr =
 315 {
 316   & i960_cgen_opval_h_gr_entries[0],
 317   34
 318 };
 319
 320 CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
 321 {
 322   { "cc", 0 }
 323 };
 324
 325 CGEN_KEYWORD i960_cgen_opval_h_cc =
 326 {
 327   & i960_cgen_opval_h_cc_entries[0],
 328   1
 329 };
 330
 331
 332 /* The hardware table.  */
 333
 334 #define HW_ENT(n) i960_cgen_hw_entries[n]
 335 static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
 336 {
 337   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { (1<<MACH_BASE) } } },
 338   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 339   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 340   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 341   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 342   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { CGEN_HW_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } } },
 343   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
 344   { HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { CGEN_HW_NBOOL_ATTRS, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { (1<<MACH_BASE) } } },
 345   { 0 }
 346 };
 347
 348 /* The instruction field table.  */
 349
 350 static const CGEN_IFLD i960_cgen_ifld_table[] =
 351 {
 352   { I960_F_NIL, "f-nil", 0, 0, 0, 0, { CGEN_IFLD_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }  },
 353   { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 354   { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 355   { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 356   { I960_F_M3, "f-m3", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 357   { I960_F_M2, "f-m2", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 358   { I960_F_M1, "f-m1", 0, 32, 20, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 359   { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 360   { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 361   { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 362   { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 363   { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 364   { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 365   { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 366   { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 367   { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 368   { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 369   { I960_F_INDEX, "f-index", 0, 32, 27, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 370   { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 371   { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 372   { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 373   { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 374   { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } }  },
 375   { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 376   { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_PCREL_ADDR), { (1<<MACH_BASE) } }  },
 377   { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { CGEN_IFLD_NBOOL_ATTRS, 0|(1<<CGEN_IFLD_UNSIGNED), { (1<<MACH_BASE) } }  },
 378   { 0 }
 379 };
 380
 381 /* The operand table.  */
 382
 383 #define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
 384 #define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
 385
 386 const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
 387 {
 388 /* pc: program counter */
 389   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 390     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_SEM_ONLY), { (1<<MACH_BASE) } }  },
 391 /* src1: source register 1 */
 392   { "src1", & HW_ENT (HW_H_GR), 27, 5,
 393     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 394 /* src2: source register 2 */
 395   { "src2", & HW_ENT (HW_H_GR), 13, 5,
 396     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 397 /* dst: source/dest register */
 398   { "dst", & HW_ENT (HW_H_GR), 8, 5,
 399     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 400 /* lit1: literal 1 */
 401   { "lit1", & HW_ENT (HW_H_UINT), 27, 5,
 402     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 403 /* lit2: literal 2 */
 404   { "lit2", & HW_ENT (HW_H_UINT), 13, 5,
 405     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 406 /* st_src: store src */
 407   { "st_src", & HW_ENT (HW_H_GR), 8, 5,
 408     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 409 /* abase: abase */
 410   { "abase", & HW_ENT (HW_H_GR), 13, 5,
 411     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 412 /* offset: offset */
 413   { "offset", & HW_ENT (HW_H_UINT), 20, 12,
 414     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 415 /* scale: scale */
 416   { "scale", & HW_ENT (HW_H_UINT), 22, 3,
 417     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 418 /* index: index */
 419   { "index", & HW_ENT (HW_H_GR), 27, 5,
 420     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 421 /* optdisp: optional displacement */
 422   { "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
 423     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 424 /* br_src1: branch src1 */
 425   { "br_src1", & HW_ENT (HW_H_GR), 8, 5,
 426     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 427 /* br_src2: branch src2 */
 428   { "br_src2", & HW_ENT (HW_H_GR), 13, 5,
 429     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 430 /* br_disp: branch displacement */
 431   { "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
 432     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } }  },
 433 /* br_lit1: branch literal 1 */
 434   { "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
 435     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_UNSIGNED), { (1<<MACH_BASE) } }  },
 436 /* ctrl_disp: ctrl branch disp */
 437   { "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
 438     { CGEN_OPERAND_NBOOL_ATTRS, 0|(1<<CGEN_OPERAND_PCREL_ADDR), { (1<<MACH_BASE) } }  },
 439 };
 440
 441 /* Instruction formats.  */
 442
 443 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
 444
 445 static const CGEN_IFMT ifmt_empty = {
 446   0, 0, 0x0, { 0 }
 447 };
 448
 449 static const CGEN_IFMT ifmt_mulo = {
 450   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 451 };
 452
 453 static const CGEN_IFMT ifmt_mulo1 = {
 454   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 455 };
 456
 457 static const CGEN_IFMT ifmt_mulo2 = {
 458   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 459 };
 460
 461 static const CGEN_IFMT ifmt_mulo3 = {
 462   32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
 463 };
 464
 465 static const CGEN_IFMT ifmt_lda_offset = {
 466   32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
 467 };
 468
 469 static const CGEN_IFMT ifmt_lda_indirect = {
 470   32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 471 };
 472
 473 static const CGEN_IFMT ifmt_lda_disp = {
 474   32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 475 };
 476
 477 static const CGEN_IFMT ifmt_st_offset = {
 478   32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
 479 };
 480
 481 static const CGEN_IFMT ifmt_st_indirect = {
 482   32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 483 };
 484
 485 static const CGEN_IFMT ifmt_st_disp = {
 486   32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
 487 };
 488
 489 static const CGEN_IFMT ifmt_cmpobe_reg = {
 490   32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
 491 };
 492
 493 static const CGEN_IFMT ifmt_cmpobe_lit = {
 494   32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
 495 };
 496
 497 static const CGEN_IFMT ifmt_bno = {
 498   32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
 499 };
 500
 501 #undef F
 502
 503 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 504 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 505 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 506
 507 /* The instruction table.
 508    This is currently non-static because the simulator accesses it
 509    directly.  */
 510
 511 const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
 512 {
 513   /* Special null first entry.
 514      A `num' value of zero is thus invalid.
 515      Also, the special `invalid' insn resides here.  */
 516   { { 0 }, 0 },
 517 /* mulo $src1, $src2, $dst */
 518   {
 519     { 1, 1, 1, 1 },
 520     I960_INSN_MULO, "mulo", "mulo",
 521     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 522     & ifmt_mulo, { 0x70000080 },
 523     (PTR) 0,
 524     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 525   },
 526 /* mulo $lit1, $src2, $dst */
 527   {
 528     { 1, 1, 1, 1 },
 529     I960_INSN_MULO1, "mulo1", "mulo",
 530     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 531     & ifmt_mulo1, { 0x70000880 },
 532     (PTR) 0,
 533     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 534   },
 535 /* mulo $src1, $lit2, $dst */
 536   {
 537     { 1, 1, 1, 1 },
 538     I960_INSN_MULO2, "mulo2", "mulo",
 539     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 540     & ifmt_mulo2, { 0x70001080 },
 541     (PTR) 0,
 542     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 543   },
 544 /* mulo $lit1, $lit2, $dst */
 545   {
 546     { 1, 1, 1, 1 },
 547     I960_INSN_MULO3, "mulo3", "mulo",
 548     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 549     & ifmt_mulo3, { 0x70001880 },
 550     (PTR) 0,
 551     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 552   },
 553 /* remo $src1, $src2, $dst */
 554   {
 555     { 1, 1, 1, 1 },
 556     I960_INSN_REMO, "remo", "remo",
 557     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 558     & ifmt_mulo, { 0x70000400 },
 559     (PTR) 0,
 560     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 561   },
 562 /* remo $lit1, $src2, $dst */
 563   {
 564     { 1, 1, 1, 1 },
 565     I960_INSN_REMO1, "remo1", "remo",
 566     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 567     & ifmt_mulo1, { 0x70000c00 },
 568     (PTR) 0,
 569     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 570   },
 571 /* remo $src1, $lit2, $dst */
 572   {
 573     { 1, 1, 1, 1 },
 574     I960_INSN_REMO2, "remo2", "remo",
 575     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 576     & ifmt_mulo2, { 0x70001400 },
 577     (PTR) 0,
 578     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 579   },
 580 /* remo $lit1, $lit2, $dst */
 581   {
 582     { 1, 1, 1, 1 },
 583     I960_INSN_REMO3, "remo3", "remo",
 584     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 585     & ifmt_mulo3, { 0x70001c00 },
 586     (PTR) 0,
 587     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 588   },
 589 /* divo $src1, $src2, $dst */
 590   {
 591     { 1, 1, 1, 1 },
 592     I960_INSN_DIVO, "divo", "divo",
 593     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 594     & ifmt_mulo, { 0x70000580 },
 595     (PTR) 0,
 596     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 597   },
 598 /* divo $lit1, $src2, $dst */
 599   {
 600     { 1, 1, 1, 1 },
 601     I960_INSN_DIVO1, "divo1", "divo",
 602     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 603     & ifmt_mulo1, { 0x70000d80 },
 604     (PTR) 0,
 605     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 606   },
 607 /* divo $src1, $lit2, $dst */
 608   {
 609     { 1, 1, 1, 1 },
 610     I960_INSN_DIVO2, "divo2", "divo",
 611     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 612     & ifmt_mulo2, { 0x70001580 },
 613     (PTR) 0,
 614     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 615   },
 616 /* divo $lit1, $lit2, $dst */
 617   {
 618     { 1, 1, 1, 1 },
 619     I960_INSN_DIVO3, "divo3", "divo",
 620     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 621     & ifmt_mulo3, { 0x70001d80 },
 622     (PTR) 0,
 623     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 624   },
 625 /* remi $src1, $src2, $dst */
 626   {
 627     { 1, 1, 1, 1 },
 628     I960_INSN_REMI, "remi", "remi",
 629     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 630     & ifmt_mulo, { 0x74000400 },
 631     (PTR) 0,
 632     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 633   },
 634 /* remi $lit1, $src2, $dst */
 635   {
 636     { 1, 1, 1, 1 },
 637     I960_INSN_REMI1, "remi1", "remi",
 638     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 639     & ifmt_mulo1, { 0x74000c00 },
 640     (PTR) 0,
 641     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 642   },
 643 /* remi $src1, $lit2, $dst */
 644   {
 645     { 1, 1, 1, 1 },
 646     I960_INSN_REMI2, "remi2", "remi",
 647     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 648     & ifmt_mulo2, { 0x74001400 },
 649     (PTR) 0,
 650     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 651   },
 652 /* remi $lit1, $lit2, $dst */
 653   {
 654     { 1, 1, 1, 1 },
 655     I960_INSN_REMI3, "remi3", "remi",
 656     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 657     & ifmt_mulo3, { 0x74001c00 },
 658     (PTR) 0,
 659     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 660   },
 661 /* divi $src1, $src2, $dst */
 662   {
 663     { 1, 1, 1, 1 },
 664     I960_INSN_DIVI, "divi", "divi",
 665     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 666     & ifmt_mulo, { 0x74000580 },
 667     (PTR) 0,
 668     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 669   },
 670 /* divi $lit1, $src2, $dst */
 671   {
 672     { 1, 1, 1, 1 },
 673     I960_INSN_DIVI1, "divi1", "divi",
 674     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 675     & ifmt_mulo1, { 0x74000d80 },
 676     (PTR) 0,
 677     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 678   },
 679 /* divi $src1, $lit2, $dst */
 680   {
 681     { 1, 1, 1, 1 },
 682     I960_INSN_DIVI2, "divi2", "divi",
 683     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 684     & ifmt_mulo2, { 0x74001580 },
 685     (PTR) 0,
 686     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 687   },
 688 /* divi $lit1, $lit2, $dst */
 689   {
 690     { 1, 1, 1, 1 },
 691     I960_INSN_DIVI3, "divi3", "divi",
 692     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 693     & ifmt_mulo3, { 0x74001d80 },
 694     (PTR) 0,
 695     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 696   },
 697 /* addo $src1, $src2, $dst */
 698   {
 699     { 1, 1, 1, 1 },
 700     I960_INSN_ADDO, "addo", "addo",
 701     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 702     & ifmt_mulo, { 0x59000000 },
 703     (PTR) 0,
 704     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 705   },
 706 /* addo $lit1, $src2, $dst */
 707   {
 708     { 1, 1, 1, 1 },
 709     I960_INSN_ADDO1, "addo1", "addo",
 710     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 711     & ifmt_mulo1, { 0x59000800 },
 712     (PTR) 0,
 713     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 714   },
 715 /* addo $src1, $lit2, $dst */
 716   {
 717     { 1, 1, 1, 1 },
 718     I960_INSN_ADDO2, "addo2", "addo",
 719     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 720     & ifmt_mulo2, { 0x59001000 },
 721     (PTR) 0,
 722     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 723   },
 724 /* addo $lit1, $lit2, $dst */
 725   {
 726     { 1, 1, 1, 1 },
 727     I960_INSN_ADDO3, "addo3", "addo",
 728     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 729     & ifmt_mulo3, { 0x59001800 },
 730     (PTR) 0,
 731     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 732   },
 733 /* subo $src1, $src2, $dst */
 734   {
 735     { 1, 1, 1, 1 },
 736     I960_INSN_SUBO, "subo", "subo",
 737     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 738     & ifmt_mulo, { 0x59000100 },
 739     (PTR) 0,
 740     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 741   },
 742 /* subo $lit1, $src2, $dst */
 743   {
 744     { 1, 1, 1, 1 },
 745     I960_INSN_SUBO1, "subo1", "subo",
 746     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 747     & ifmt_mulo1, { 0x59000900 },
 748     (PTR) 0,
 749     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 750   },
 751 /* subo $src1, $lit2, $dst */
 752   {
 753     { 1, 1, 1, 1 },
 754     I960_INSN_SUBO2, "subo2", "subo",
 755     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 756     & ifmt_mulo2, { 0x59001100 },
 757     (PTR) 0,
 758     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 759   },
 760 /* subo $lit1, $lit2, $dst */
 761   {
 762     { 1, 1, 1, 1 },
 763     I960_INSN_SUBO3, "subo3", "subo",
 764     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 765     & ifmt_mulo3, { 0x59001900 },
 766     (PTR) 0,
 767     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 768   },
 769 /* notbit $src1, $src2, $dst */
 770   {
 771     { 1, 1, 1, 1 },
 772     I960_INSN_NOTBIT, "notbit", "notbit",
 773     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 774     & ifmt_mulo, { 0x58000000 },
 775     (PTR) 0,
 776     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 777   },
 778 /* notbit $lit1, $src2, $dst */
 779   {
 780     { 1, 1, 1, 1 },
 781     I960_INSN_NOTBIT1, "notbit1", "notbit",
 782     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 783     & ifmt_mulo1, { 0x58000800 },
 784     (PTR) 0,
 785     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 786   },
 787 /* notbit $src1, $lit2, $dst */
 788   {
 789     { 1, 1, 1, 1 },
 790     I960_INSN_NOTBIT2, "notbit2", "notbit",
 791     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 792     & ifmt_mulo2, { 0x58001000 },
 793     (PTR) 0,
 794     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 795   },
 796 /* notbit $lit1, $lit2, $dst */
 797   {
 798     { 1, 1, 1, 1 },
 799     I960_INSN_NOTBIT3, "notbit3", "notbit",
 800     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 801     & ifmt_mulo3, { 0x58001800 },
 802     (PTR) 0,
 803     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 804   },
 805 /* and $src1, $src2, $dst */
 806   {
 807     { 1, 1, 1, 1 },
 808     I960_INSN_AND, "and", "and",
 809     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 810     & ifmt_mulo, { 0x58000080 },
 811     (PTR) 0,
 812     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 813   },
 814 /* and $lit1, $src2, $dst */
 815   {
 816     { 1, 1, 1, 1 },
 817     I960_INSN_AND1, "and1", "and",
 818     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 819     & ifmt_mulo1, { 0x58000880 },
 820     (PTR) 0,
 821     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 822   },
 823 /* and $src1, $lit2, $dst */
 824   {
 825     { 1, 1, 1, 1 },
 826     I960_INSN_AND2, "and2", "and",
 827     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 828     & ifmt_mulo2, { 0x58001080 },
 829     (PTR) 0,
 830     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 831   },
 832 /* and $lit1, $lit2, $dst */
 833   {
 834     { 1, 1, 1, 1 },
 835     I960_INSN_AND3, "and3", "and",
 836     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 837     & ifmt_mulo3, { 0x58001880 },
 838     (PTR) 0,
 839     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 840   },
 841 /* andnot $src1, $src2, $dst */
 842   {
 843     { 1, 1, 1, 1 },
 844     I960_INSN_ANDNOT, "andnot", "andnot",
 845     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 846     & ifmt_mulo, { 0x58000100 },
 847     (PTR) 0,
 848     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 849   },
 850 /* andnot $lit1, $src2, $dst */
 851   {
 852     { 1, 1, 1, 1 },
 853     I960_INSN_ANDNOT1, "andnot1", "andnot",
 854     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 855     & ifmt_mulo1, { 0x58000900 },
 856     (PTR) 0,
 857     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 858   },
 859 /* andnot $src1, $lit2, $dst */
 860   {
 861     { 1, 1, 1, 1 },
 862     I960_INSN_ANDNOT2, "andnot2", "andnot",
 863     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 864     & ifmt_mulo2, { 0x58001100 },
 865     (PTR) 0,
 866     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 867   },
 868 /* andnot $lit1, $lit2, $dst */
 869   {
 870     { 1, 1, 1, 1 },
 871     I960_INSN_ANDNOT3, "andnot3", "andnot",
 872     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 873     & ifmt_mulo3, { 0x58001900 },
 874     (PTR) 0,
 875     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 876   },
 877 /* setbit $src1, $src2, $dst */
 878   {
 879     { 1, 1, 1, 1 },
 880     I960_INSN_SETBIT, "setbit", "setbit",
 881     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 882     & ifmt_mulo, { 0x58000180 },
 883     (PTR) 0,
 884     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 885   },
 886 /* setbit $lit1, $src2, $dst */
 887   {
 888     { 1, 1, 1, 1 },
 889     I960_INSN_SETBIT1, "setbit1", "setbit",
 890     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 891     & ifmt_mulo1, { 0x58000980 },
 892     (PTR) 0,
 893     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 894   },
 895 /* setbit $src1, $lit2, $dst */
 896   {
 897     { 1, 1, 1, 1 },
 898     I960_INSN_SETBIT2, "setbit2", "setbit",
 899     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 900     & ifmt_mulo2, { 0x58001180 },
 901     (PTR) 0,
 902     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 903   },
 904 /* setbit $lit1, $lit2, $dst */
 905   {
 906     { 1, 1, 1, 1 },
 907     I960_INSN_SETBIT3, "setbit3", "setbit",
 908     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 909     & ifmt_mulo3, { 0x58001980 },
 910     (PTR) 0,
 911     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 912   },
 913 /* notand $src1, $src2, $dst */
 914   {
 915     { 1, 1, 1, 1 },
 916     I960_INSN_NOTAND, "notand", "notand",
 917     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 918     & ifmt_mulo, { 0x58000200 },
 919     (PTR) 0,
 920     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 921   },
 922 /* notand $lit1, $src2, $dst */
 923   {
 924     { 1, 1, 1, 1 },
 925     I960_INSN_NOTAND1, "notand1", "notand",
 926     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 927     & ifmt_mulo1, { 0x58000a00 },
 928     (PTR) 0,
 929     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 930   },
 931 /* notand $src1, $lit2, $dst */
 932   {
 933     { 1, 1, 1, 1 },
 934     I960_INSN_NOTAND2, "notand2", "notand",
 935     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 936     & ifmt_mulo2, { 0x58001200 },
 937     (PTR) 0,
 938     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 939   },
 940 /* notand $lit1, $lit2, $dst */
 941   {
 942     { 1, 1, 1, 1 },
 943     I960_INSN_NOTAND3, "notand3", "notand",
 944     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 945     & ifmt_mulo3, { 0x58001a00 },
 946     (PTR) 0,
 947     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 948   },
 949 /* xor $src1, $src2, $dst */
 950   {
 951     { 1, 1, 1, 1 },
 952     I960_INSN_XOR, "xor", "xor",
 953     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 954     & ifmt_mulo, { 0x58000300 },
 955     (PTR) 0,
 956     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 957   },
 958 /* xor $lit1, $src2, $dst */
 959   {
 960     { 1, 1, 1, 1 },
 961     I960_INSN_XOR1, "xor1", "xor",
 962     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 963     & ifmt_mulo1, { 0x58000b00 },
 964     (PTR) 0,
 965     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 966   },
 967 /* xor $src1, $lit2, $dst */
 968   {
 969     { 1, 1, 1, 1 },
 970     I960_INSN_XOR2, "xor2", "xor",
 971     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 972     & ifmt_mulo2, { 0x58001300 },
 973     (PTR) 0,
 974     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 975   },
 976 /* xor $lit1, $lit2, $dst */
 977   {
 978     { 1, 1, 1, 1 },
 979     I960_INSN_XOR3, "xor3", "xor",
 980     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
 981     & ifmt_mulo3, { 0x58001b00 },
 982     (PTR) 0,
 983     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 984   },
 985 /* or $src1, $src2, $dst */
 986   {
 987     { 1, 1, 1, 1 },
 988     I960_INSN_OR, "or", "or",
 989     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 990     & ifmt_mulo, { 0x58000380 },
 991     (PTR) 0,
 992     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
 993   },
 994 /* or $lit1, $src2, $dst */
 995   {
 996     { 1, 1, 1, 1 },
 997     I960_INSN_OR1, "or1", "or",
 998     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
 999     & ifmt_mulo1, { 0x58000b80 },
1000     (PTR) 0,
1001     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1002   },
1003 /* or $src1, $lit2, $dst */
1004   {
1005     { 1, 1, 1, 1 },
1006     I960_INSN_OR2, "or2", "or",
1007     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1008     & ifmt_mulo2, { 0x58001380 },
1009     (PTR) 0,
1010     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1011   },
1012 /* or $lit1, $lit2, $dst */
1013   {
1014     { 1, 1, 1, 1 },
1015     I960_INSN_OR3, "or3", "or",
1016     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1017     & ifmt_mulo3, { 0x58001b80 },
1018     (PTR) 0,
1019     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1020   },
1021 /* nor $src1, $src2, $dst */
1022   {
1023     { 1, 1, 1, 1 },
1024     I960_INSN_NOR, "nor", "nor",
1025     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1026     & ifmt_mulo, { 0x58000400 },
1027     (PTR) 0,
1028     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1029   },
1030 /* nor $lit1, $src2, $dst */
1031   {
1032     { 1, 1, 1, 1 },
1033     I960_INSN_NOR1, "nor1", "nor",
1034     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1035     & ifmt_mulo1, { 0x58000c00 },
1036     (PTR) 0,
1037     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1038   },
1039 /* nor $src1, $lit2, $dst */
1040   {
1041     { 1, 1, 1, 1 },
1042     I960_INSN_NOR2, "nor2", "nor",
1043     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1044     & ifmt_mulo2, { 0x58001400 },
1045     (PTR) 0,
1046     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1047   },
1048 /* nor $lit1, $lit2, $dst */
1049   {
1050     { 1, 1, 1, 1 },
1051     I960_INSN_NOR3, "nor3", "nor",
1052     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1053     & ifmt_mulo3, { 0x58001c00 },
1054     (PTR) 0,
1055     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1056   },
1057 /* not $src1, $src2, $dst */
1058   {
1059     { 1, 1, 1, 1 },
1060     I960_INSN_NOT, "not", "not",
1061     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1062     & ifmt_mulo, { 0x58000500 },
1063     (PTR) 0,
1064     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1065   },
1066 /* not $lit1, $src2, $dst */
1067   {
1068     { 1, 1, 1, 1 },
1069     I960_INSN_NOT1, "not1", "not",
1070     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1071     & ifmt_mulo1, { 0x58000d00 },
1072     (PTR) 0,
1073     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1074   },
1075 /* not $src1, $lit2, $dst */
1076   {
1077     { 1, 1, 1, 1 },
1078     I960_INSN_NOT2, "not2", "not",
1079     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1080     & ifmt_mulo2, { 0x58001500 },
1081     (PTR) 0,
1082     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1083   },
1084 /* not $lit1, $lit2, $dst */
1085   {
1086     { 1, 1, 1, 1 },
1087     I960_INSN_NOT3, "not3", "not",
1088     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1089     & ifmt_mulo3, { 0x58001d00 },
1090     (PTR) 0,
1091     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1092   },
1093 /* clrbit $src1, $src2, $dst */
1094   {
1095     { 1, 1, 1, 1 },
1096     I960_INSN_CLRBIT, "clrbit", "clrbit",
1097     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1098     & ifmt_mulo, { 0x58000600 },
1099     (PTR) 0,
1100     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1101   },
1102 /* clrbit $lit1, $src2, $dst */
1103   {
1104     { 1, 1, 1, 1 },
1105     I960_INSN_CLRBIT1, "clrbit1", "clrbit",
1106     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1107     & ifmt_mulo1, { 0x58000e00 },
1108     (PTR) 0,
1109     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1110   },
1111 /* clrbit $src1, $lit2, $dst */
1112   {
1113     { 1, 1, 1, 1 },
1114     I960_INSN_CLRBIT2, "clrbit2", "clrbit",
1115     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1116     & ifmt_mulo2, { 0x58001600 },
1117     (PTR) 0,
1118     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1119   },
1120 /* clrbit $lit1, $lit2, $dst */
1121   {
1122     { 1, 1, 1, 1 },
1123     I960_INSN_CLRBIT3, "clrbit3", "clrbit",
1124     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1125     & ifmt_mulo3, { 0x58001e00 },
1126     (PTR) 0,
1127     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1128   },
1129 /* shlo $src1, $src2, $dst */
1130   {
1131     { 1, 1, 1, 1 },
1132     I960_INSN_SHLO, "shlo", "shlo",
1133     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1134     & ifmt_mulo, { 0x59000600 },
1135     (PTR) 0,
1136     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1137   },
1138 /* shlo $lit1, $src2, $dst */
1139   {
1140     { 1, 1, 1, 1 },
1141     I960_INSN_SHLO1, "shlo1", "shlo",
1142     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1143     & ifmt_mulo1, { 0x59000e00 },
1144     (PTR) 0,
1145     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1146   },
1147 /* shlo $src1, $lit2, $dst */
1148   {
1149     { 1, 1, 1, 1 },
1150     I960_INSN_SHLO2, "shlo2", "shlo",
1151     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1152     & ifmt_mulo2, { 0x59001600 },
1153     (PTR) 0,
1154     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1155   },
1156 /* shlo $lit1, $lit2, $dst */
1157   {
1158     { 1, 1, 1, 1 },
1159     I960_INSN_SHLO3, "shlo3", "shlo",
1160     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1161     & ifmt_mulo3, { 0x59001e00 },
1162     (PTR) 0,
1163     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1164   },
1165 /* shro $src1, $src2, $dst */
1166   {
1167     { 1, 1, 1, 1 },
1168     I960_INSN_SHRO, "shro", "shro",
1169     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1170     & ifmt_mulo, { 0x59000400 },
1171     (PTR) 0,
1172     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1173   },
1174 /* shro $lit1, $src2, $dst */
1175   {
1176     { 1, 1, 1, 1 },
1177     I960_INSN_SHRO1, "shro1", "shro",
1178     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1179     & ifmt_mulo1, { 0x59000c00 },
1180     (PTR) 0,
1181     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1182   },
1183 /* shro $src1, $lit2, $dst */
1184   {
1185     { 1, 1, 1, 1 },
1186     I960_INSN_SHRO2, "shro2", "shro",
1187     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1188     & ifmt_mulo2, { 0x59001400 },
1189     (PTR) 0,
1190     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1191   },
1192 /* shro $lit1, $lit2, $dst */
1193   {
1194     { 1, 1, 1, 1 },
1195     I960_INSN_SHRO3, "shro3", "shro",
1196     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1197     & ifmt_mulo3, { 0x59001c00 },
1198     (PTR) 0,
1199     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1200   },
1201 /* shli $src1, $src2, $dst */
1202   {
1203     { 1, 1, 1, 1 },
1204     I960_INSN_SHLI, "shli", "shli",
1205     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1206     & ifmt_mulo, { 0x59000700 },
1207     (PTR) 0,
1208     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1209   },
1210 /* shli $lit1, $src2, $dst */
1211   {
1212     { 1, 1, 1, 1 },
1213     I960_INSN_SHLI1, "shli1", "shli",
1214     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1215     & ifmt_mulo1, { 0x59000f00 },
1216     (PTR) 0,
1217     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1218   },
1219 /* shli $src1, $lit2, $dst */
1220   {
1221     { 1, 1, 1, 1 },
1222     I960_INSN_SHLI2, "shli2", "shli",
1223     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1224     & ifmt_mulo2, { 0x59001700 },
1225     (PTR) 0,
1226     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1227   },
1228 /* shli $lit1, $lit2, $dst */
1229   {
1230     { 1, 1, 1, 1 },
1231     I960_INSN_SHLI3, "shli3", "shli",
1232     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1233     & ifmt_mulo3, { 0x59001f00 },
1234     (PTR) 0,
1235     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1236   },
1237 /* shri $src1, $src2, $dst */
1238   {
1239     { 1, 1, 1, 1 },
1240     I960_INSN_SHRI, "shri", "shri",
1241     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1242     & ifmt_mulo, { 0x59000580 },
1243     (PTR) 0,
1244     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1245   },
1246 /* shri $lit1, $src2, $dst */
1247   {
1248     { 1, 1, 1, 1 },
1249     I960_INSN_SHRI1, "shri1", "shri",
1250     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1251     & ifmt_mulo1, { 0x59000d80 },
1252     (PTR) 0,
1253     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1254   },
1255 /* shri $src1, $lit2, $dst */
1256   {
1257     { 1, 1, 1, 1 },
1258     I960_INSN_SHRI2, "shri2", "shri",
1259     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1260     & ifmt_mulo2, { 0x59001580 },
1261     (PTR) 0,
1262     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1263   },
1264 /* shri $lit1, $lit2, $dst */
1265   {
1266     { 1, 1, 1, 1 },
1267     I960_INSN_SHRI3, "shri3", "shri",
1268     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1269     & ifmt_mulo3, { 0x59001d80 },
1270     (PTR) 0,
1271     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1272   },
1273 /* emul $src1, $src2, $dst */
1274   {
1275     { 1, 1, 1, 1 },
1276     I960_INSN_EMUL, "emul", "emul",
1277     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1278     & ifmt_mulo, { 0x67000000 },
1279     (PTR) 0,
1280     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1281   },
1282 /* emul $lit1, $src2, $dst */
1283   {
1284     { 1, 1, 1, 1 },
1285     I960_INSN_EMUL1, "emul1", "emul",
1286     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1287     & ifmt_mulo1, { 0x67000800 },
1288     (PTR) 0,
1289     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1290   },
1291 /* emul $src1, $lit2, $dst */
1292   {
1293     { 1, 1, 1, 1 },
1294     I960_INSN_EMUL2, "emul2", "emul",
1295     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1296     & ifmt_mulo2, { 0x67001000 },
1297     (PTR) 0,
1298     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1299   },
1300 /* emul $lit1, $lit2, $dst */
1301   {
1302     { 1, 1, 1, 1 },
1303     I960_INSN_EMUL3, "emul3", "emul",
1304     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
1305     & ifmt_mulo3, { 0x67001800 },
1306     (PTR) 0,
1307     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1308   },
1309 /* mov $src1, $dst */
1310   {
1311     { 1, 1, 1, 1 },
1312     I960_INSN_MOV, "mov", "mov",
1313     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1314     & ifmt_mulo2, { 0x5c001600 },
1315     (PTR) 0,
1316     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1317   },
1318 /* mov $lit1, $dst */
1319   {
1320     { 1, 1, 1, 1 },
1321     I960_INSN_MOV1, "mov1", "mov",
1322     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1323     & ifmt_mulo3, { 0x5c001e00 },
1324     (PTR) 0,
1325     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1326   },
1327 /* movl $src1, $dst */
1328   {
1329     { 1, 1, 1, 1 },
1330     I960_INSN_MOVL, "movl", "movl",
1331     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1332     & ifmt_mulo2, { 0x5d001600 },
1333     (PTR) 0,
1334     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1335   },
1336 /* movl $lit1, $dst */
1337   {
1338     { 1, 1, 1, 1 },
1339     I960_INSN_MOVL1, "movl1", "movl",
1340     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1341     & ifmt_mulo3, { 0x5d001e00 },
1342     (PTR) 0,
1343     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1344   },
1345 /* movt $src1, $dst */
1346   {
1347     { 1, 1, 1, 1 },
1348     I960_INSN_MOVT, "movt", "movt",
1349     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1350     & ifmt_mulo2, { 0x5e001600 },
1351     (PTR) 0,
1352     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1353   },
1354 /* movt $lit1, $dst */
1355   {
1356     { 1, 1, 1, 1 },
1357     I960_INSN_MOVT1, "movt1", "movt",
1358     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1359     & ifmt_mulo3, { 0x5e001e00 },
1360     (PTR) 0,
1361     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1362   },
1363 /* movq $src1, $dst */
1364   {
1365     { 1, 1, 1, 1 },
1366     I960_INSN_MOVQ, "movq", "movq",
1367     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
1368     & ifmt_mulo2, { 0x5f001600 },
1369     (PTR) 0,
1370     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1371   },
1372 /* movq $lit1, $dst */
1373   {
1374     { 1, 1, 1, 1 },
1375     I960_INSN_MOVQ1, "movq1", "movq",
1376     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
1377     & ifmt_mulo3, { 0x5f001e00 },
1378     (PTR) 0,
1379     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1380   },
1381 /* modpc $src1, $src2, $dst */
1382   {
1383     { 1, 1, 1, 1 },
1384     I960_INSN_MODPC, "modpc", "modpc",
1385     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1386     & ifmt_mulo, { 0x65000280 },
1387     (PTR) 0,
1388     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1389   },
1390 /* modac $src1, $src2, $dst */
1391   {
1392     { 1, 1, 1, 1 },
1393     I960_INSN_MODAC, "modac", "modac",
1394     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
1395     & ifmt_mulo, { 0x64000280 },
1396     (PTR) 0,
1397     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1398   },
1399 /* lda $offset, $dst */
1400   {
1401     { 1, 1, 1, 1 },
1402     I960_INSN_LDA_OFFSET, "lda-offset", "lda",
1403     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1404     & ifmt_lda_offset, { 0x8c000000 },
1405     (PTR) 0,
1406     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1407   },
1408 /* lda $offset($abase), $dst */
1409   {
1410     { 1, 1, 1, 1 },
1411     I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
1412     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1413     & ifmt_lda_offset, { 0x8c002000 },
1414     (PTR) 0,
1415     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1416   },
1417 /* lda ($abase), $dst */
1418   {
1419     { 1, 1, 1, 1 },
1420     I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
1421     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1422     & ifmt_lda_indirect, { 0x8c001000 },
1423     (PTR) 0,
1424     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1425   },
1426 /* lda ($abase)[$index*S$scale], $dst */
1427   {
1428     { 1, 1, 1, 1 },
1429     I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
1430     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1431     & ifmt_lda_indirect, { 0x8c001c00 },
1432     (PTR) 0,
1433     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1434   },
1435 /* lda $optdisp, $dst */
1436   {
1437     { 1, 1, 1, 1 },
1438     I960_INSN_LDA_DISP, "lda-disp", "lda",
1439     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1440     & ifmt_lda_disp, { 0x8c003000 },
1441     (PTR) 0,
1442     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1443   },
1444 /* lda $optdisp($abase), $dst */
1445   {
1446     { 1, 1, 1, 1 },
1447     I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
1448     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1449     & ifmt_lda_disp, { 0x8c003400 },
1450     (PTR) 0,
1451     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1452   },
1453 /* lda $optdisp[$index*S$scale], $dst */
1454   {
1455     { 1, 1, 1, 1 },
1456     I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
1457     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1458     & ifmt_lda_disp, { 0x8c003800 },
1459     (PTR) 0,
1460     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1461   },
1462 /* lda $optdisp($abase)[$index*S$scale], $dst */
1463   {
1464     { 1, 1, 1, 1 },
1465     I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
1466     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1467     & ifmt_lda_disp, { 0x8c003c00 },
1468     (PTR) 0,
1469     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1470   },
1471 /* ld $offset, $dst */
1472   {
1473     { 1, 1, 1, 1 },
1474     I960_INSN_LD_OFFSET, "ld-offset", "ld",
1475     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1476     & ifmt_lda_offset, { 0x90000000 },
1477     (PTR) 0,
1478     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1479   },
1480 /* ld $offset($abase), $dst */
1481   {
1482     { 1, 1, 1, 1 },
1483     I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
1484     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1485     & ifmt_lda_offset, { 0x90002000 },
1486     (PTR) 0,
1487     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1488   },
1489 /* ld ($abase), $dst */
1490   {
1491     { 1, 1, 1, 1 },
1492     I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
1493     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1494     & ifmt_lda_indirect, { 0x90001000 },
1495     (PTR) 0,
1496     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1497   },
1498 /* ld ($abase)[$index*S$scale], $dst */
1499   {
1500     { 1, 1, 1, 1 },
1501     I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
1502     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1503     & ifmt_lda_indirect, { 0x90001c00 },
1504     (PTR) 0,
1505     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1506   },
1507 /* ld $optdisp, $dst */
1508   {
1509     { 1, 1, 1, 1 },
1510     I960_INSN_LD_DISP, "ld-disp", "ld",
1511     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1512     & ifmt_lda_disp, { 0x90003000 },
1513     (PTR) 0,
1514     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1515   },
1516 /* ld $optdisp($abase), $dst */
1517   {
1518     { 1, 1, 1, 1 },
1519     I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
1520     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1521     & ifmt_lda_disp, { 0x90003400 },
1522     (PTR) 0,
1523     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1524   },
1525 /* ld $optdisp[$index*S$scale], $dst */
1526   {
1527     { 1, 1, 1, 1 },
1528     I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
1529     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1530     & ifmt_lda_disp, { 0x90003800 },
1531     (PTR) 0,
1532     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1533   },
1534 /* ld $optdisp($abase)[$index*S$scale], $dst */
1535   {
1536     { 1, 1, 1, 1 },
1537     I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
1538     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1539     & ifmt_lda_disp, { 0x90003c00 },
1540     (PTR) 0,
1541     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1542   },
1543 /* ldob $offset, $dst */
1544   {
1545     { 1, 1, 1, 1 },
1546     I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
1547     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1548     & ifmt_lda_offset, { 0x80000000 },
1549     (PTR) 0,
1550     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1551   },
1552 /* ldob $offset($abase), $dst */
1553   {
1554     { 1, 1, 1, 1 },
1555     I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
1556     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1557     & ifmt_lda_offset, { 0x80002000 },
1558     (PTR) 0,
1559     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1560   },
1561 /* ldob ($abase), $dst */
1562   {
1563     { 1, 1, 1, 1 },
1564     I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
1565     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1566     & ifmt_lda_indirect, { 0x80001000 },
1567     (PTR) 0,
1568     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1569   },
1570 /* ldob ($abase)[$index*S$scale], $dst */
1571   {
1572     { 1, 1, 1, 1 },
1573     I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
1574     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1575     & ifmt_lda_indirect, { 0x80001c00 },
1576     (PTR) 0,
1577     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1578   },
1579 /* ldob $optdisp, $dst */
1580   {
1581     { 1, 1, 1, 1 },
1582     I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
1583     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1584     & ifmt_lda_disp, { 0x80003000 },
1585     (PTR) 0,
1586     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1587   },
1588 /* ldob $optdisp($abase), $dst */
1589   {
1590     { 1, 1, 1, 1 },
1591     I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
1592     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1593     & ifmt_lda_disp, { 0x80003400 },
1594     (PTR) 0,
1595     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1596   },
1597 /* ldob $optdisp[$index*S$scale], $dst */
1598   {
1599     { 1, 1, 1, 1 },
1600     I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
1601     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1602     & ifmt_lda_disp, { 0x80003800 },
1603     (PTR) 0,
1604     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1605   },
1606 /* ldob $optdisp($abase)[$index*S$scale], $dst */
1607   {
1608     { 1, 1, 1, 1 },
1609     I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
1610     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1611     & ifmt_lda_disp, { 0x80003c00 },
1612     (PTR) 0,
1613     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1614   },
1615 /* ldos $offset, $dst */
1616   {
1617     { 1, 1, 1, 1 },
1618     I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
1619     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1620     & ifmt_lda_offset, { 0x88000000 },
1621     (PTR) 0,
1622     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1623   },
1624 /* ldos $offset($abase), $dst */
1625   {
1626     { 1, 1, 1, 1 },
1627     I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
1628     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1629     & ifmt_lda_offset, { 0x88002000 },
1630     (PTR) 0,
1631     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1632   },
1633 /* ldos ($abase), $dst */
1634   {
1635     { 1, 1, 1, 1 },
1636     I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
1637     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1638     & ifmt_lda_indirect, { 0x88001000 },
1639     (PTR) 0,
1640     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1641   },
1642 /* ldos ($abase)[$index*S$scale], $dst */
1643   {
1644     { 1, 1, 1, 1 },
1645     I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
1646     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1647     & ifmt_lda_indirect, { 0x88001c00 },
1648     (PTR) 0,
1649     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1650   },
1651 /* ldos $optdisp, $dst */
1652   {
1653     { 1, 1, 1, 1 },
1654     I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
1655     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1656     & ifmt_lda_disp, { 0x88003000 },
1657     (PTR) 0,
1658     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1659   },
1660 /* ldos $optdisp($abase), $dst */
1661   {
1662     { 1, 1, 1, 1 },
1663     I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
1664     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1665     & ifmt_lda_disp, { 0x88003400 },
1666     (PTR) 0,
1667     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1668   },
1669 /* ldos $optdisp[$index*S$scale], $dst */
1670   {
1671     { 1, 1, 1, 1 },
1672     I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
1673     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1674     & ifmt_lda_disp, { 0x88003800 },
1675     (PTR) 0,
1676     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1677   },
1678 /* ldos $optdisp($abase)[$index*S$scale], $dst */
1679   {
1680     { 1, 1, 1, 1 },
1681     I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
1682     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1683     & ifmt_lda_disp, { 0x88003c00 },
1684     (PTR) 0,
1685     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1686   },
1687 /* ldib $offset, $dst */
1688   {
1689     { 1, 1, 1, 1 },
1690     I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
1691     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1692     & ifmt_lda_offset, { 0xc0000000 },
1693     (PTR) 0,
1694     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1695   },
1696 /* ldib $offset($abase), $dst */
1697   {
1698     { 1, 1, 1, 1 },
1699     I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
1700     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1701     & ifmt_lda_offset, { 0xc0002000 },
1702     (PTR) 0,
1703     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1704   },
1705 /* ldib ($abase), $dst */
1706   {
1707     { 1, 1, 1, 1 },
1708     I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
1709     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1710     & ifmt_lda_indirect, { 0xc0001000 },
1711     (PTR) 0,
1712     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1713   },
1714 /* ldib ($abase)[$index*S$scale], $dst */
1715   {
1716     { 1, 1, 1, 1 },
1717     I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
1718     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1719     & ifmt_lda_indirect, { 0xc0001c00 },
1720     (PTR) 0,
1721     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1722   },
1723 /* ldib $optdisp, $dst */
1724   {
1725     { 1, 1, 1, 1 },
1726     I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
1727     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1728     & ifmt_lda_disp, { 0xc0003000 },
1729     (PTR) 0,
1730     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1731   },
1732 /* ldib $optdisp($abase), $dst */
1733   {
1734     { 1, 1, 1, 1 },
1735     I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
1736     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1737     & ifmt_lda_disp, { 0xc0003400 },
1738     (PTR) 0,
1739     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1740   },
1741 /* ldib $optdisp[$index*S$scale], $dst */
1742   {
1743     { 1, 1, 1, 1 },
1744     I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
1745     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1746     & ifmt_lda_disp, { 0xc0003800 },
1747     (PTR) 0,
1748     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1749   },
1750 /* ldib $optdisp($abase)[$index*S$scale], $dst */
1751   {
1752     { 1, 1, 1, 1 },
1753     I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
1754     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1755     & ifmt_lda_disp, { 0xc0003c00 },
1756     (PTR) 0,
1757     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1758   },
1759 /* ldis $offset, $dst */
1760   {
1761     { 1, 1, 1, 1 },
1762     I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
1763     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1764     & ifmt_lda_offset, { 0xc8000000 },
1765     (PTR) 0,
1766     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1767   },
1768 /* ldis $offset($abase), $dst */
1769   {
1770     { 1, 1, 1, 1 },
1771     I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
1772     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1773     & ifmt_lda_offset, { 0xc8002000 },
1774     (PTR) 0,
1775     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1776   },
1777 /* ldis ($abase), $dst */
1778   {
1779     { 1, 1, 1, 1 },
1780     I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
1781     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1782     & ifmt_lda_indirect, { 0xc8001000 },
1783     (PTR) 0,
1784     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1785   },
1786 /* ldis ($abase)[$index*S$scale], $dst */
1787   {
1788     { 1, 1, 1, 1 },
1789     I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
1790     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1791     & ifmt_lda_indirect, { 0xc8001c00 },
1792     (PTR) 0,
1793     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1794   },
1795 /* ldis $optdisp, $dst */
1796   {
1797     { 1, 1, 1, 1 },
1798     I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
1799     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1800     & ifmt_lda_disp, { 0xc8003000 },
1801     (PTR) 0,
1802     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1803   },
1804 /* ldis $optdisp($abase), $dst */
1805   {
1806     { 1, 1, 1, 1 },
1807     I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
1808     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1809     & ifmt_lda_disp, { 0xc8003400 },
1810     (PTR) 0,
1811     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1812   },
1813 /* ldis $optdisp[$index*S$scale], $dst */
1814   {
1815     { 1, 1, 1, 1 },
1816     I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
1817     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1818     & ifmt_lda_disp, { 0xc8003800 },
1819     (PTR) 0,
1820     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1821   },
1822 /* ldis $optdisp($abase)[$index*S$scale], $dst */
1823   {
1824     { 1, 1, 1, 1 },
1825     I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
1826     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1827     & ifmt_lda_disp, { 0xc8003c00 },
1828     (PTR) 0,
1829     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1830   },
1831 /* ldl $offset, $dst */
1832   {
1833     { 1, 1, 1, 1 },
1834     I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
1835     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1836     & ifmt_lda_offset, { 0x98000000 },
1837     (PTR) 0,
1838     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1839   },
1840 /* ldl $offset($abase), $dst */
1841   {
1842     { 1, 1, 1, 1 },
1843     I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
1844     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1845     & ifmt_lda_offset, { 0x98002000 },
1846     (PTR) 0,
1847     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1848   },
1849 /* ldl ($abase), $dst */
1850   {
1851     { 1, 1, 1, 1 },
1852     I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
1853     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1854     & ifmt_lda_indirect, { 0x98001000 },
1855     (PTR) 0,
1856     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1857   },
1858 /* ldl ($abase)[$index*S$scale], $dst */
1859   {
1860     { 1, 1, 1, 1 },
1861     I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
1862     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1863     & ifmt_lda_indirect, { 0x98001c00 },
1864     (PTR) 0,
1865     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1866   },
1867 /* ldl $optdisp, $dst */
1868   {
1869     { 1, 1, 1, 1 },
1870     I960_INSN_LDL_DISP, "ldl-disp", "ldl",
1871     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1872     & ifmt_lda_disp, { 0x98003000 },
1873     (PTR) 0,
1874     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1875   },
1876 /* ldl $optdisp($abase), $dst */
1877   {
1878     { 1, 1, 1, 1 },
1879     I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
1880     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1881     & ifmt_lda_disp, { 0x98003400 },
1882     (PTR) 0,
1883     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1884   },
1885 /* ldl $optdisp[$index*S$scale], $dst */
1886   {
1887     { 1, 1, 1, 1 },
1888     I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
1889     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1890     & ifmt_lda_disp, { 0x98003800 },
1891     (PTR) 0,
1892     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1893   },
1894 /* ldl $optdisp($abase)[$index*S$scale], $dst */
1895   {
1896     { 1, 1, 1, 1 },
1897     I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
1898     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1899     & ifmt_lda_disp, { 0x98003c00 },
1900     (PTR) 0,
1901     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1902   },
1903 /* ldt $offset, $dst */
1904   {
1905     { 1, 1, 1, 1 },
1906     I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
1907     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1908     & ifmt_lda_offset, { 0xa0000000 },
1909     (PTR) 0,
1910     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1911   },
1912 /* ldt $offset($abase), $dst */
1913   {
1914     { 1, 1, 1, 1 },
1915     I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
1916     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1917     & ifmt_lda_offset, { 0xa0002000 },
1918     (PTR) 0,
1919     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1920   },
1921 /* ldt ($abase), $dst */
1922   {
1923     { 1, 1, 1, 1 },
1924     I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
1925     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1926     & ifmt_lda_indirect, { 0xa0001000 },
1927     (PTR) 0,
1928     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1929   },
1930 /* ldt ($abase)[$index*S$scale], $dst */
1931   {
1932     { 1, 1, 1, 1 },
1933     I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
1934     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1935     & ifmt_lda_indirect, { 0xa0001c00 },
1936     (PTR) 0,
1937     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1938   },
1939 /* ldt $optdisp, $dst */
1940   {
1941     { 1, 1, 1, 1 },
1942     I960_INSN_LDT_DISP, "ldt-disp", "ldt",
1943     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
1944     & ifmt_lda_disp, { 0xa0003000 },
1945     (PTR) 0,
1946     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1947   },
1948 /* ldt $optdisp($abase), $dst */
1949   {
1950     { 1, 1, 1, 1 },
1951     I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
1952     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1953     & ifmt_lda_disp, { 0xa0003400 },
1954     (PTR) 0,
1955     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1956   },
1957 /* ldt $optdisp[$index*S$scale], $dst */
1958   {
1959     { 1, 1, 1, 1 },
1960     I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
1961     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1962     & ifmt_lda_disp, { 0xa0003800 },
1963     (PTR) 0,
1964     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1965   },
1966 /* ldt $optdisp($abase)[$index*S$scale], $dst */
1967   {
1968     { 1, 1, 1, 1 },
1969     I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
1970     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
1971     & ifmt_lda_disp, { 0xa0003c00 },
1972     (PTR) 0,
1973     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1974   },
1975 /* ldq $offset, $dst */
1976   {
1977     { 1, 1, 1, 1 },
1978     I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
1979     { { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
1980     & ifmt_lda_offset, { 0xb0000000 },
1981     (PTR) 0,
1982     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1983   },
1984 /* ldq $offset($abase), $dst */
1985   {
1986     { 1, 1, 1, 1 },
1987     I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
1988     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1989     & ifmt_lda_offset, { 0xb0002000 },
1990     (PTR) 0,
1991     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
1992   },
1993 /* ldq ($abase), $dst */
1994   {
1995     { 1, 1, 1, 1 },
1996     I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
1997     { { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
1998     & ifmt_lda_indirect, { 0xb0001000 },
1999     (PTR) 0,
2000     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2001   },
2002 /* ldq ($abase)[$index*S$scale], $dst */
2003   {
2004     { 1, 1, 1, 1 },
2005     I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
2006     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2007     & ifmt_lda_indirect, { 0xb0001c00 },
2008     (PTR) 0,
2009     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2010   },
2011 /* ldq $optdisp, $dst */
2012   {
2013     { 1, 1, 1, 1 },
2014     I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
2015     { { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
2016     & ifmt_lda_disp, { 0xb0003000 },
2017     (PTR) 0,
2018     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2019   },
2020 /* ldq $optdisp($abase), $dst */
2021   {
2022     { 1, 1, 1, 1 },
2023     I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
2024     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
2025     & ifmt_lda_disp, { 0xb0003400 },
2026     (PTR) 0,
2027     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2028   },
2029 /* ldq $optdisp[$index*S$scale], $dst */
2030   {
2031     { 1, 1, 1, 1 },
2032     I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
2033     { { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2034     & ifmt_lda_disp, { 0xb0003800 },
2035     (PTR) 0,
2036     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2037   },
2038 /* ldq $optdisp($abase)[$index*S$scale], $dst */
2039   {
2040     { 1, 1, 1, 1 },
2041     I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
2042     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
2043     & ifmt_lda_disp, { 0xb0003c00 },
2044     (PTR) 0,
2045     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2046   },
2047 /* st $st_src, $offset */
2048   {
2049     { 1, 1, 1, 1 },
2050     I960_INSN_ST_OFFSET, "st-offset", "st",
2051     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2052     & ifmt_st_offset, { 0x92000000 },
2053     (PTR) 0,
2054     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2055   },
2056 /* st $st_src, $offset($abase) */
2057   {
2058     { 1, 1, 1, 1 },
2059     I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
2060     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2061     & ifmt_st_offset, { 0x92002000 },
2062     (PTR) 0,
2063     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2064   },
2065 /* st $st_src, ($abase) */
2066   {
2067     { 1, 1, 1, 1 },
2068     I960_INSN_ST_INDIRECT, "st-indirect", "st",
2069     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2070     & ifmt_st_indirect, { 0x92001000 },
2071     (PTR) 0,
2072     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2073   },
2074 /* st $st_src, ($abase)[$index*S$scale] */
2075   {
2076     { 1, 1, 1, 1 },
2077     I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
2078     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2079     & ifmt_st_indirect, { 0x92001c00 },
2080     (PTR) 0,
2081     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2082   },
2083 /* st $st_src, $optdisp */
2084   {
2085     { 1, 1, 1, 1 },
2086     I960_INSN_ST_DISP, "st-disp", "st",
2087     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2088     & ifmt_st_disp, { 0x92003000 },
2089     (PTR) 0,
2090     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2091   },
2092 /* st $st_src, $optdisp($abase) */
2093   {
2094     { 1, 1, 1, 1 },
2095     I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
2096     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2097     & ifmt_st_disp, { 0x92003400 },
2098     (PTR) 0,
2099     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2100   },
2101 /* st $st_src, $optdisp[$index*S$scale */
2102   {
2103     { 1, 1, 1, 1 },
2104     I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
2105     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2106     & ifmt_st_disp, { 0x92003800 },
2107     (PTR) 0,
2108     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2109   },
2110 /* st $st_src, $optdisp($abase)[$index*S$scale] */
2111   {
2112     { 1, 1, 1, 1 },
2113     I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
2114     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2115     & ifmt_st_disp, { 0x92003c00 },
2116     (PTR) 0,
2117     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2118   },
2119 /* stob $st_src, $offset */
2120   {
2121     { 1, 1, 1, 1 },
2122     I960_INSN_STOB_OFFSET, "stob-offset", "stob",
2123     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2124     & ifmt_st_offset, { 0x82000000 },
2125     (PTR) 0,
2126     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2127   },
2128 /* stob $st_src, $offset($abase) */
2129   {
2130     { 1, 1, 1, 1 },
2131     I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
2132     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2133     & ifmt_st_offset, { 0x82002000 },
2134     (PTR) 0,
2135     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2136   },
2137 /* stob $st_src, ($abase) */
2138   {
2139     { 1, 1, 1, 1 },
2140     I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
2141     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2142     & ifmt_st_indirect, { 0x82001000 },
2143     (PTR) 0,
2144     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2145   },
2146 /* stob $st_src, ($abase)[$index*S$scale] */
2147   {
2148     { 1, 1, 1, 1 },
2149     I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
2150     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2151     & ifmt_st_indirect, { 0x82001c00 },
2152     (PTR) 0,
2153     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2154   },
2155 /* stob $st_src, $optdisp */
2156   {
2157     { 1, 1, 1, 1 },
2158     I960_INSN_STOB_DISP, "stob-disp", "stob",
2159     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2160     & ifmt_st_disp, { 0x82003000 },
2161     (PTR) 0,
2162     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2163   },
2164 /* stob $st_src, $optdisp($abase) */
2165   {
2166     { 1, 1, 1, 1 },
2167     I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
2168     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2169     & ifmt_st_disp, { 0x82003400 },
2170     (PTR) 0,
2171     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2172   },
2173 /* stob $st_src, $optdisp[$index*S$scale */
2174   {
2175     { 1, 1, 1, 1 },
2176     I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
2177     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2178     & ifmt_st_disp, { 0x82003800 },
2179     (PTR) 0,
2180     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2181   },
2182 /* stob $st_src, $optdisp($abase)[$index*S$scale] */
2183   {
2184     { 1, 1, 1, 1 },
2185     I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
2186     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2187     & ifmt_st_disp, { 0x82003c00 },
2188     (PTR) 0,
2189     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2190   },
2191 /* stos $st_src, $offset */
2192   {
2193     { 1, 1, 1, 1 },
2194     I960_INSN_STOS_OFFSET, "stos-offset", "stos",
2195     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2196     & ifmt_st_offset, { 0x8a000000 },
2197     (PTR) 0,
2198     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2199   },
2200 /* stos $st_src, $offset($abase) */
2201   {
2202     { 1, 1, 1, 1 },
2203     I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
2204     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2205     & ifmt_st_offset, { 0x8a002000 },
2206     (PTR) 0,
2207     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2208   },
2209 /* stos $st_src, ($abase) */
2210   {
2211     { 1, 1, 1, 1 },
2212     I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
2213     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2214     & ifmt_st_indirect, { 0x8a001000 },
2215     (PTR) 0,
2216     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2217   },
2218 /* stos $st_src, ($abase)[$index*S$scale] */
2219   {
2220     { 1, 1, 1, 1 },
2221     I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
2222     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2223     & ifmt_st_indirect, { 0x8a001c00 },
2224     (PTR) 0,
2225     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2226   },
2227 /* stos $st_src, $optdisp */
2228   {
2229     { 1, 1, 1, 1 },
2230     I960_INSN_STOS_DISP, "stos-disp", "stos",
2231     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2232     & ifmt_st_disp, { 0x8a003000 },
2233     (PTR) 0,
2234     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2235   },
2236 /* stos $st_src, $optdisp($abase) */
2237   {
2238     { 1, 1, 1, 1 },
2239     I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
2240     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2241     & ifmt_st_disp, { 0x8a003400 },
2242     (PTR) 0,
2243     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2244   },
2245 /* stos $st_src, $optdisp[$index*S$scale */
2246   {
2247     { 1, 1, 1, 1 },
2248     I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
2249     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2250     & ifmt_st_disp, { 0x8a003800 },
2251     (PTR) 0,
2252     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2253   },
2254 /* stos $st_src, $optdisp($abase)[$index*S$scale] */
2255   {
2256     { 1, 1, 1, 1 },
2257     I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
2258     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2259     & ifmt_st_disp, { 0x8a003c00 },
2260     (PTR) 0,
2261     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2262   },
2263 /* stl $st_src, $offset */
2264   {
2265     { 1, 1, 1, 1 },
2266     I960_INSN_STL_OFFSET, "stl-offset", "stl",
2267     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2268     & ifmt_st_offset, { 0x9a000000 },
2269     (PTR) 0,
2270     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2271   },
2272 /* stl $st_src, $offset($abase) */
2273   {
2274     { 1, 1, 1, 1 },
2275     I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
2276     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2277     & ifmt_st_offset, { 0x9a002000 },
2278     (PTR) 0,
2279     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2280   },
2281 /* stl $st_src, ($abase) */
2282   {
2283     { 1, 1, 1, 1 },
2284     I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
2285     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2286     & ifmt_st_indirect, { 0x9a001000 },
2287     (PTR) 0,
2288     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2289   },
2290 /* stl $st_src, ($abase)[$index*S$scale] */
2291   {
2292     { 1, 1, 1, 1 },
2293     I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
2294     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2295     & ifmt_st_indirect, { 0x9a001c00 },
2296     (PTR) 0,
2297     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2298   },
2299 /* stl $st_src, $optdisp */
2300   {
2301     { 1, 1, 1, 1 },
2302     I960_INSN_STL_DISP, "stl-disp", "stl",
2303     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2304     & ifmt_st_disp, { 0x9a003000 },
2305     (PTR) 0,
2306     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2307   },
2308 /* stl $st_src, $optdisp($abase) */
2309   {
2310     { 1, 1, 1, 1 },
2311     I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
2312     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2313     & ifmt_st_disp, { 0x9a003400 },
2314     (PTR) 0,
2315     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2316   },
2317 /* stl $st_src, $optdisp[$index*S$scale */
2318   {
2319     { 1, 1, 1, 1 },
2320     I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
2321     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2322     & ifmt_st_disp, { 0x9a003800 },
2323     (PTR) 0,
2324     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2325   },
2326 /* stl $st_src, $optdisp($abase)[$index*S$scale] */
2327   {
2328     { 1, 1, 1, 1 },
2329     I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
2330     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2331     & ifmt_st_disp, { 0x9a003c00 },
2332     (PTR) 0,
2333     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2334   },
2335 /* stt $st_src, $offset */
2336   {
2337     { 1, 1, 1, 1 },
2338     I960_INSN_STT_OFFSET, "stt-offset", "stt",
2339     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2340     & ifmt_st_offset, { 0xa2000000 },
2341     (PTR) 0,
2342     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2343   },
2344 /* stt $st_src, $offset($abase) */
2345   {
2346     { 1, 1, 1, 1 },
2347     I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
2348     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2349     & ifmt_st_offset, { 0xa2002000 },
2350     (PTR) 0,
2351     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2352   },
2353 /* stt $st_src, ($abase) */
2354   {
2355     { 1, 1, 1, 1 },
2356     I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
2357     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2358     & ifmt_st_indirect, { 0xa2001000 },
2359     (PTR) 0,
2360     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2361   },
2362 /* stt $st_src, ($abase)[$index*S$scale] */
2363   {
2364     { 1, 1, 1, 1 },
2365     I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
2366     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2367     & ifmt_st_indirect, { 0xa2001c00 },
2368     (PTR) 0,
2369     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2370   },
2371 /* stt $st_src, $optdisp */
2372   {
2373     { 1, 1, 1, 1 },
2374     I960_INSN_STT_DISP, "stt-disp", "stt",
2375     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2376     & ifmt_st_disp, { 0xa2003000 },
2377     (PTR) 0,
2378     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2379   },
2380 /* stt $st_src, $optdisp($abase) */
2381   {
2382     { 1, 1, 1, 1 },
2383     I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
2384     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2385     & ifmt_st_disp, { 0xa2003400 },
2386     (PTR) 0,
2387     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2388   },
2389 /* stt $st_src, $optdisp[$index*S$scale */
2390   {
2391     { 1, 1, 1, 1 },
2392     I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
2393     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2394     & ifmt_st_disp, { 0xa2003800 },
2395     (PTR) 0,
2396     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2397   },
2398 /* stt $st_src, $optdisp($abase)[$index*S$scale] */
2399   {
2400     { 1, 1, 1, 1 },
2401     I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
2402     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2403     & ifmt_st_disp, { 0xa2003c00 },
2404     (PTR) 0,
2405     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2406   },
2407 /* stq $st_src, $offset */
2408   {
2409     { 1, 1, 1, 1 },
2410     I960_INSN_STQ_OFFSET, "stq-offset", "stq",
2411     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
2412     & ifmt_st_offset, { 0xb2000000 },
2413     (PTR) 0,
2414     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2415   },
2416 /* stq $st_src, $offset($abase) */
2417   {
2418     { 1, 1, 1, 1 },
2419     I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
2420     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2421     & ifmt_st_offset, { 0xb2002000 },
2422     (PTR) 0,
2423     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2424   },
2425 /* stq $st_src, ($abase) */
2426   {
2427     { 1, 1, 1, 1 },
2428     I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
2429     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
2430     & ifmt_st_indirect, { 0xb2001000 },
2431     (PTR) 0,
2432     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2433   },
2434 /* stq $st_src, ($abase)[$index*S$scale] */
2435   {
2436     { 1, 1, 1, 1 },
2437     I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
2438     { { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2439     & ifmt_st_indirect, { 0xb2001c00 },
2440     (PTR) 0,
2441     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2442   },
2443 /* stq $st_src, $optdisp */
2444   {
2445     { 1, 1, 1, 1 },
2446     I960_INSN_STQ_DISP, "stq-disp", "stq",
2447     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
2448     & ifmt_st_disp, { 0xb2003000 },
2449     (PTR) 0,
2450     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2451   },
2452 /* stq $st_src, $optdisp($abase) */
2453   {
2454     { 1, 1, 1, 1 },
2455     I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
2456     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2457     & ifmt_st_disp, { 0xb2003400 },
2458     (PTR) 0,
2459     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2460   },
2461 /* stq $st_src, $optdisp[$index*S$scale */
2462   {
2463     { 1, 1, 1, 1 },
2464     I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
2465     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
2466     & ifmt_st_disp, { 0xb2003800 },
2467     (PTR) 0,
2468     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2469   },
2470 /* stq $st_src, $optdisp($abase)[$index*S$scale] */
2471   {
2472     { 1, 1, 1, 1 },
2473     I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
2474     { { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2475     & ifmt_st_disp, { 0xb2003c00 },
2476     (PTR) 0,
2477     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2478   },
2479 /* cmpobe $br_src1, $br_src2, $br_disp */
2480   {
2481     { 1, 1, 1, 1 },
2482     I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
2483     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2484     & ifmt_cmpobe_reg, { 0x32000000 },
2485     (PTR) 0,
2486     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2487   },
2488 /* cmpobe $br_lit1, $br_src2, $br_disp */
2489   {
2490     { 1, 1, 1, 1 },
2491     I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
2492     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2493     & ifmt_cmpobe_lit, { 0x32002000 },
2494     (PTR) 0,
2495     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2496   },
2497 /* cmpobne $br_src1, $br_src2, $br_disp */
2498   {
2499     { 1, 1, 1, 1 },
2500     I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
2501     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2502     & ifmt_cmpobe_reg, { 0x35000000 },
2503     (PTR) 0,
2504     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2505   },
2506 /* cmpobne $br_lit1, $br_src2, $br_disp */
2507   {
2508     { 1, 1, 1, 1 },
2509     I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
2510     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2511     & ifmt_cmpobe_lit, { 0x35002000 },
2512     (PTR) 0,
2513     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2514   },
2515 /* cmpobl $br_src1, $br_src2, $br_disp */
2516   {
2517     { 1, 1, 1, 1 },
2518     I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
2519     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2520     & ifmt_cmpobe_reg, { 0x34000000 },
2521     (PTR) 0,
2522     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2523   },
2524 /* cmpobl $br_lit1, $br_src2, $br_disp */
2525   {
2526     { 1, 1, 1, 1 },
2527     I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
2528     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2529     & ifmt_cmpobe_lit, { 0x34002000 },
2530     (PTR) 0,
2531     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2532   },
2533 /* cmpoble $br_src1, $br_src2, $br_disp */
2534   {
2535     { 1, 1, 1, 1 },
2536     I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
2537     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2538     & ifmt_cmpobe_reg, { 0x36000000 },
2539     (PTR) 0,
2540     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2541   },
2542 /* cmpoble $br_lit1, $br_src2, $br_disp */
2543   {
2544     { 1, 1, 1, 1 },
2545     I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
2546     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2547     & ifmt_cmpobe_lit, { 0x36002000 },
2548     (PTR) 0,
2549     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2550   },
2551 /* cmpobg $br_src1, $br_src2, $br_disp */
2552   {
2553     { 1, 1, 1, 1 },
2554     I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
2555     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2556     & ifmt_cmpobe_reg, { 0x31000000 },
2557     (PTR) 0,
2558     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2559   },
2560 /* cmpobg $br_lit1, $br_src2, $br_disp */
2561   {
2562     { 1, 1, 1, 1 },
2563     I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
2564     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2565     & ifmt_cmpobe_lit, { 0x31002000 },
2566     (PTR) 0,
2567     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2568   },
2569 /* cmpobge $br_src1, $br_src2, $br_disp */
2570   {
2571     { 1, 1, 1, 1 },
2572     I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
2573     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2574     & ifmt_cmpobe_reg, { 0x33000000 },
2575     (PTR) 0,
2576     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2577   },
2578 /* cmpobge $br_lit1, $br_src2, $br_disp */
2579   {
2580     { 1, 1, 1, 1 },
2581     I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
2582     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2583     & ifmt_cmpobe_lit, { 0x33002000 },
2584     (PTR) 0,
2585     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2586   },
2587 /* cmpibe $br_src1, $br_src2, $br_disp */
2588   {
2589     { 1, 1, 1, 1 },
2590     I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
2591     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2592     & ifmt_cmpobe_reg, { 0x3a000000 },
2593     (PTR) 0,
2594     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2595   },
2596 /* cmpibe $br_lit1, $br_src2, $br_disp */
2597   {
2598     { 1, 1, 1, 1 },
2599     I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
2600     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2601     & ifmt_cmpobe_lit, { 0x3a002000 },
2602     (PTR) 0,
2603     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2604   },
2605 /* cmpibne $br_src1, $br_src2, $br_disp */
2606   {
2607     { 1, 1, 1, 1 },
2608     I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
2609     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2610     & ifmt_cmpobe_reg, { 0x3d000000 },
2611     (PTR) 0,
2612     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2613   },
2614 /* cmpibne $br_lit1, $br_src2, $br_disp */
2615   {
2616     { 1, 1, 1, 1 },
2617     I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
2618     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2619     & ifmt_cmpobe_lit, { 0x3d002000 },
2620     (PTR) 0,
2621     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2622   },
2623 /* cmpibl $br_src1, $br_src2, $br_disp */
2624   {
2625     { 1, 1, 1, 1 },
2626     I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
2627     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2628     & ifmt_cmpobe_reg, { 0x3c000000 },
2629     (PTR) 0,
2630     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2631   },
2632 /* cmpibl $br_lit1, $br_src2, $br_disp */
2633   {
2634     { 1, 1, 1, 1 },
2635     I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
2636     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2637     & ifmt_cmpobe_lit, { 0x3c002000 },
2638     (PTR) 0,
2639     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2640   },
2641 /* cmpible $br_src1, $br_src2, $br_disp */
2642   {
2643     { 1, 1, 1, 1 },
2644     I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
2645     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2646     & ifmt_cmpobe_reg, { 0x3e000000 },
2647     (PTR) 0,
2648     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2649   },
2650 /* cmpible $br_lit1, $br_src2, $br_disp */
2651   {
2652     { 1, 1, 1, 1 },
2653     I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
2654     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2655     & ifmt_cmpobe_lit, { 0x3e002000 },
2656     (PTR) 0,
2657     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2658   },
2659 /* cmpibg $br_src1, $br_src2, $br_disp */
2660   {
2661     { 1, 1, 1, 1 },
2662     I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
2663     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2664     & ifmt_cmpobe_reg, { 0x39000000 },
2665     (PTR) 0,
2666     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2667   },
2668 /* cmpibg $br_lit1, $br_src2, $br_disp */
2669   {
2670     { 1, 1, 1, 1 },
2671     I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
2672     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2673     & ifmt_cmpobe_lit, { 0x39002000 },
2674     (PTR) 0,
2675     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2676   },
2677 /* cmpibge $br_src1, $br_src2, $br_disp */
2678   {
2679     { 1, 1, 1, 1 },
2680     I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
2681     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2682     & ifmt_cmpobe_reg, { 0x3b000000 },
2683     (PTR) 0,
2684     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2685   },
2686 /* cmpibge $br_lit1, $br_src2, $br_disp */
2687   {
2688     { 1, 1, 1, 1 },
2689     I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
2690     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2691     & ifmt_cmpobe_lit, { 0x3b002000 },
2692     (PTR) 0,
2693     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2694   },
2695 /* bbc $br_src1, $br_src2, $br_disp */
2696   {
2697     { 1, 1, 1, 1 },
2698     I960_INSN_BBC_REG, "bbc-reg", "bbc",
2699     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2700     & ifmt_cmpobe_reg, { 0x30000000 },
2701     (PTR) 0,
2702     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2703   },
2704 /* bbc $br_lit1, $br_src2, $br_disp */
2705   {
2706     { 1, 1, 1, 1 },
2707     I960_INSN_BBC_LIT, "bbc-lit", "bbc",
2708     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2709     & ifmt_cmpobe_lit, { 0x30002000 },
2710     (PTR) 0,
2711     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2712   },
2713 /* bbs $br_src1, $br_src2, $br_disp */
2714   {
2715     { 1, 1, 1, 1 },
2716     I960_INSN_BBS_REG, "bbs-reg", "bbs",
2717     { { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2718     & ifmt_cmpobe_reg, { 0x37000000 },
2719     (PTR) 0,
2720     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2721   },
2722 /* bbs $br_lit1, $br_src2, $br_disp */
2723   {
2724     { 1, 1, 1, 1 },
2725     I960_INSN_BBS_LIT, "bbs-lit", "bbs",
2726     { { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
2727     & ifmt_cmpobe_lit, { 0x37002000 },
2728     (PTR) 0,
2729     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2730   },
2731 /* cmpi $src1, $src2 */
2732   {
2733     { 1, 1, 1, 1 },
2734     I960_INSN_CMPI, "cmpi", "cmpi",
2735     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
2736     & ifmt_mulo, { 0x5a002080 },
2737     (PTR) 0,
2738     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2739   },
2740 /* cmpi $lit1, $src2 */
2741   {
2742     { 1, 1, 1, 1 },
2743     I960_INSN_CMPI1, "cmpi1", "cmpi",
2744     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
2745     & ifmt_mulo1, { 0x5a002880 },
2746     (PTR) 0,
2747     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2748   },
2749 /* cmpi $src1, $lit2 */
2750   {
2751     { 1, 1, 1, 1 },
2752     I960_INSN_CMPI2, "cmpi2", "cmpi",
2753     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
2754     & ifmt_mulo2, { 0x5a003080 },
2755     (PTR) 0,
2756     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2757   },
2758 /* cmpi $lit1, $lit2 */
2759   {
2760     { 1, 1, 1, 1 },
2761     I960_INSN_CMPI3, "cmpi3", "cmpi",
2762     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
2763     & ifmt_mulo3, { 0x5a003880 },
2764     (PTR) 0,
2765     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2766   },
2767 /* cmpo $src1, $src2 */
2768   {
2769     { 1, 1, 1, 1 },
2770     I960_INSN_CMPO, "cmpo", "cmpo",
2771     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
2772     & ifmt_mulo, { 0x5a002000 },
2773     (PTR) 0,
2774     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2775   },
2776 /* cmpo $lit1, $src2 */
2777   {
2778     { 1, 1, 1, 1 },
2779     I960_INSN_CMPO1, "cmpo1", "cmpo",
2780     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
2781     & ifmt_mulo1, { 0x5a002800 },
2782     (PTR) 0,
2783     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2784   },
2785 /* cmpo $src1, $lit2 */
2786   {
2787     { 1, 1, 1, 1 },
2788     I960_INSN_CMPO2, "cmpo2", "cmpo",
2789     { { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
2790     & ifmt_mulo2, { 0x5a003000 },
2791     (PTR) 0,
2792     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2793   },
2794 /* cmpo $lit1, $lit2 */
2795   {
2796     { 1, 1, 1, 1 },
2797     I960_INSN_CMPO3, "cmpo3", "cmpo",
2798     { { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
2799     & ifmt_mulo3, { 0x5a003800 },
2800     (PTR) 0,
2801     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2802   },
2803 /* testno $br_src1 */
2804   {
2805     { 1, 1, 1, 1 },
2806     I960_INSN_TESTNO_REG, "testno-reg", "testno",
2807     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2808     & ifmt_cmpobe_reg, { 0x20000000 },
2809     (PTR) 0,
2810     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2811   },
2812 /* testg $br_src1 */
2813   {
2814     { 1, 1, 1, 1 },
2815     I960_INSN_TESTG_REG, "testg-reg", "testg",
2816     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2817     & ifmt_cmpobe_reg, { 0x21000000 },
2818     (PTR) 0,
2819     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2820   },
2821 /* teste $br_src1 */
2822   {
2823     { 1, 1, 1, 1 },
2824     I960_INSN_TESTE_REG, "teste-reg", "teste",
2825     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2826     & ifmt_cmpobe_reg, { 0x22000000 },
2827     (PTR) 0,
2828     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2829   },
2830 /* testge $br_src1 */
2831   {
2832     { 1, 1, 1, 1 },
2833     I960_INSN_TESTGE_REG, "testge-reg", "testge",
2834     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2835     & ifmt_cmpobe_reg, { 0x23000000 },
2836     (PTR) 0,
2837     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2838   },
2839 /* testl $br_src1 */
2840   {
2841     { 1, 1, 1, 1 },
2842     I960_INSN_TESTL_REG, "testl-reg", "testl",
2843     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2844     & ifmt_cmpobe_reg, { 0x24000000 },
2845     (PTR) 0,
2846     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2847   },
2848 /* testne $br_src1 */
2849   {
2850     { 1, 1, 1, 1 },
2851     I960_INSN_TESTNE_REG, "testne-reg", "testne",
2852     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2853     & ifmt_cmpobe_reg, { 0x25000000 },
2854     (PTR) 0,
2855     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2856   },
2857 /* testle $br_src1 */
2858   {
2859     { 1, 1, 1, 1 },
2860     I960_INSN_TESTLE_REG, "testle-reg", "testle",
2861     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2862     & ifmt_cmpobe_reg, { 0x26000000 },
2863     (PTR) 0,
2864     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2865   },
2866 /* testo $br_src1 */
2867   {
2868     { 1, 1, 1, 1 },
2869     I960_INSN_TESTO_REG, "testo-reg", "testo",
2870     { { MNEM, ' ', OP (BR_SRC1), 0 } },
2871     & ifmt_cmpobe_reg, { 0x27000000 },
2872     (PTR) 0,
2873     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
2874   },
2875 /* bno $ctrl_disp */
2876   {
2877     { 1, 1, 1, 1 },
2878     I960_INSN_BNO, "bno", "bno",
2879     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2880     & ifmt_bno, { 0x10000000 },
2881     (PTR) 0,
2882     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2883   },
2884 /* bg $ctrl_disp */
2885   {
2886     { 1, 1, 1, 1 },
2887     I960_INSN_BG, "bg", "bg",
2888     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2889     & ifmt_bno, { 0x11000000 },
2890     (PTR) 0,
2891     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2892   },
2893 /* be $ctrl_disp */
2894   {
2895     { 1, 1, 1, 1 },
2896     I960_INSN_BE, "be", "be",
2897     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2898     & ifmt_bno, { 0x12000000 },
2899     (PTR) 0,
2900     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2901   },
2902 /* bge $ctrl_disp */
2903   {
2904     { 1, 1, 1, 1 },
2905     I960_INSN_BGE, "bge", "bge",
2906     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2907     & ifmt_bno, { 0x13000000 },
2908     (PTR) 0,
2909     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2910   },
2911 /* bl $ctrl_disp */
2912   {
2913     { 1, 1, 1, 1 },
2914     I960_INSN_BL, "bl", "bl",
2915     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2916     & ifmt_bno, { 0x14000000 },
2917     (PTR) 0,
2918     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2919   },
2920 /* bne $ctrl_disp */
2921   {
2922     { 1, 1, 1, 1 },
2923     I960_INSN_BNE, "bne", "bne",
2924     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2925     & ifmt_bno, { 0x15000000 },
2926     (PTR) 0,
2927     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2928   },
2929 /* ble $ctrl_disp */
2930   {
2931     { 1, 1, 1, 1 },
2932     I960_INSN_BLE, "ble", "ble",
2933     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2934     & ifmt_bno, { 0x16000000 },
2935     (PTR) 0,
2936     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2937   },
2938 /* bo $ctrl_disp */
2939   {
2940     { 1, 1, 1, 1 },
2941     I960_INSN_BO, "bo", "bo",
2942     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2943     & ifmt_bno, { 0x17000000 },
2944     (PTR) 0,
2945     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_BASE) } }
2946   },
2947 /* b $ctrl_disp */
2948   {
2949     { 1, 1, 1, 1 },
2950     I960_INSN_B, "b", "b",
2951     { { MNEM, ' ', OP (CTRL_DISP), 0 } },
2952     & ifmt_bno, { 0x8000000 },
2953     (PTR) 0,
2954     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2955   },
2956 /* bx $offset($abase) */
2957   {
2958     { 1, 1, 1, 1 },
2959     I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
2960     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
2961     & ifmt_lda_offset, { 0x84002000 },
2962     (PTR) 0,
2963     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2964   },
2965 /* bx ($abase) */
2966   {
2967     { 1, 1, 1, 1 },
2968     I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
2969     { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
2970     & ifmt_lda_indirect, { 0x84001000 },
2971     (PTR) 0,
2972     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2973   },
2974 /* bx ($abase)[$index*S$scale] */
2975   {
2976     { 1, 1, 1, 1 },
2977     I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
2978     { { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
2979     & ifmt_lda_indirect, { 0x84001c00 },
2980     (PTR) 0,
2981     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2982   },
2983 /* bx $optdisp */
2984   {
2985     { 1, 1, 1, 1 },
2986     I960_INSN_BX_DISP, "bx-disp", "bx",
2987     { { MNEM, ' ', OP (OPTDISP), 0 } },
2988     & ifmt_lda_disp, { 0x84003000 },
2989     (PTR) 0,
2990     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
2991   },
2992 /* bx $optdisp($abase) */
2993   {
2994     { 1, 1, 1, 1 },
2995     I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
2996     { { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
2997     & ifmt_lda_disp, { 0x84003400 },
2998     (PTR) 0,
2999     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3000   },
3001 /* callx $optdisp */
3002   {
3003     { 1, 1, 1, 1 },
3004     I960_INSN_CALLX_DISP, "callx-disp", "callx",
3005     { { MNEM, ' ', OP (OPTDISP), 0 } },
3006     & ifmt_lda_disp, { 0x86003000 },
3007     (PTR) 0,
3008     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3009   },
3010 /* callx ($abase) */
3011   {
3012     { 1, 1, 1, 1 },
3013     I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
3014     { { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
3015     & ifmt_lda_indirect, { 0x86001000 },
3016     (PTR) 0,
3017     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3018   },
3019 /* callx $offset($abase) */
3020   {
3021     { 1, 1, 1, 1 },
3022     I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
3023     { { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
3024     & ifmt_lda_offset, { 0x86002000 },
3025     (PTR) 0,
3026     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3027   },
3028 /* ret */
3029   {
3030     { 1, 1, 1, 1 },
3031     I960_INSN_RET, "ret", "ret",
3032     { { MNEM, 0 } },
3033     & ifmt_bno, { 0xa000000 },
3034     (PTR) 0,
3035     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3036   },
3037 /* calls $src1 */
3038   {
3039     { 1, 1, 1, 1 },
3040     I960_INSN_CALLS, "calls", "calls",
3041     { { MNEM, ' ', OP (SRC1), 0 } },
3042     & ifmt_mulo, { 0x66003000 },
3043     (PTR) 0,
3044     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3045   },
3046 /* fmark */
3047   {
3048     { 1, 1, 1, 1 },
3049     I960_INSN_FMARK, "fmark", "fmark",
3050     { { MNEM, 0 } },
3051     & ifmt_mulo, { 0x66003e00 },
3052     (PTR) 0,
3053     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
3054   },
3055 /* flushreg */
3056   {
3057     { 1, 1, 1, 1 },
3058     I960_INSN_FLUSHREG, "flushreg", "flushreg",
3059     { { MNEM, 0 } },
3060     & ifmt_mulo, { 0x66003e80 },
3061     (PTR) 0,
3062     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_BASE) } }
3063   },
3064 };
3065
3066 #undef A
3067 #undef MNEM
3068 #undef OP
3069
3070 static const CGEN_INSN_TABLE insn_table =
3071 {
3072   & i960_cgen_insn_table_entries[0],
3073   sizeof (CGEN_INSN),
3074   MAX_INSNS,
3075   NULL
3076 };
3077
3078 /* Formats for ALIAS macro-insns.  */
3079
3080 #define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
3081
3082 #undef F
3083
3084 /* Each non-simple macro entry points to an array of expansion possibilities.  */
3085
3086 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
3087 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
3088 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
3089
3090 /* The macro instruction table.  */
3091
3092 static const CGEN_INSN macro_insn_table_entries[] =
3093 {
3094 };
3095
3096 #undef A
3097 #undef MNEM
3098 #undef OP
3099
3100 static const CGEN_INSN_TABLE macro_insn_table =
3101 {
3102   & macro_insn_table_entries[0],
3103   sizeof (CGEN_INSN),
3104   (sizeof (macro_insn_table_entries) /
3105    sizeof (macro_insn_table_entries[0])),
3106   NULL
3107 };
3108
3109 static void
3110 init_tables ()
3111 {
3112 }
3113
3114 /* Return non-zero if INSN is to be added to the hash table.
3115    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
3116
3117 static int
3118 asm_hash_insn_p (insn)
3119      const CGEN_INSN * insn;
3120 {
3121   return CGEN_ASM_HASH_P (insn);
3122 }
3123
3124 static int
3125 dis_hash_insn_p (insn)
3126      const CGEN_INSN * insn;
3127 {
3128   /* If building the hash table and the NO-DIS attribute is present,
3129      ignore.  */
3130   if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
3131     return 0;
3132   return CGEN_DIS_HASH_P (insn);
3133 }
3134
3135 /* The result is the hash value of the insn.
3136    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
3137
3138 static unsigned int
3139 asm_hash_insn (mnem)
3140      const char * mnem;
3141 {
3142   return CGEN_ASM_HASH (mnem);
3143 }
3144
3145 /* BUF is a pointer to the insn's bytes in target order.
3146    VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
3147    host order.  */
3148
3149 static unsigned int
3150 dis_hash_insn (buf, value)
3151      const char * buf;
3152      CGEN_INSN_INT value;
3153 {
3154   return CGEN_DIS_HASH (buf, value);
3155 }
3156
3157 /* Initialize an opcode table and return a descriptor.
3158    It's much like opening a file, and must be the first function called.  */
3159
3160 CGEN_OPCODE_DESC
3161 i960_cgen_opcode_open (mach, endian)
3162      int mach;
3163      enum cgen_endian endian;
3164 {
3165   CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
3166   static int init_p;
3167
3168   if (! init_p)
3169     {
3170       init_tables ();
3171       init_p = 1;
3172     }
3173
3174   memset (table, 0, sizeof (*table));
3175
3176   CGEN_OPCODE_MACH (table) = mach;
3177   CGEN_OPCODE_ENDIAN (table) = endian;
3178   /* FIXME: for the sparc case we can determine insn-endianness statically.
3179      The worry here is where both data and insn endian can be independently
3180      chosen, in which case this function will need another argument.
3181      Actually, will want to allow for more arguments in the future anyway.  */
3182   CGEN_OPCODE_INSN_ENDIAN (table) = endian;
3183
3184   CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0];
3185
3186   CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0];
3187
3188   CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0];
3189
3190   * CGEN_OPCODE_INSN_TABLE (table) = insn_table;
3191
3192   * CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
3193
3194   CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
3195   CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
3196   CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
3197
3198   CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
3199   CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
3200   CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
3201
3202   return (CGEN_OPCODE_DESC) table;
3203 }
3204
3205 /* Close an opcode table.  */
3206
3207 void
3208 i960_cgen_opcode_close (desc)
3209      CGEN_OPCODE_DESC desc;
3210 {
3211   free (desc);
3212 }
3213
3214 /* Getting values from cgen_fields is handled by a collection of functions.
3215    They are distinguished by the type of the VALUE argument they return.
3216    TODO: floating point, inlining support, remove cases where result type
3217    not appropriate.  */
3218
3219 int
3220 i960_cgen_get_int_operand (opindex, fields)
3221      int opindex;
3222      const CGEN_FIELDS * fields;
3223 {
3224   int value;
3225
3226   switch (opindex)
3227     {
3228     case I960_OPERAND_SRC1 :
3229       value = fields->f_src1;
3230       break;
3231     case I960_OPERAND_SRC2 :
3232       value = fields->f_src2;
3233       break;
3234     case I960_OPERAND_DST :
3235       value = fields->f_srcdst;
3236       break;
3237     case I960_OPERAND_LIT1 :
3238       value = fields->f_src1;
3239       break;
3240     case I960_OPERAND_LIT2 :
3241       value = fields->f_src2;
3242       break;
3243     case I960_OPERAND_ST_SRC :
3244       value = fields->f_srcdst;
3245       break;
3246     case I960_OPERAND_ABASE :
3247       value = fields->f_abase;
3248       break;
3249     case I960_OPERAND_OFFSET :
3250       value = fields->f_offset;
3251       break;
3252     case I960_OPERAND_SCALE :
3253       value = fields->f_scale;
3254       break;
3255     case I960_OPERAND_INDEX :
3256       value = fields->f_index;
3257       break;
3258     case I960_OPERAND_OPTDISP :
3259       value = fields->f_optdisp;
3260       break;
3261     case I960_OPERAND_BR_SRC1 :
3262       value = fields->f_br_src1;
3263       break;
3264     case I960_OPERAND_BR_SRC2 :
3265       value = fields->f_br_src2;
3266       break;
3267     case I960_OPERAND_BR_DISP :
3268       value = fields->f_br_disp;
3269       break;
3270     case I960_OPERAND_BR_LIT1 :
3271       value = fields->f_br_src1;
3272       break;
3273     case I960_OPERAND_CTRL_DISP :
3274       value = fields->f_ctrl_disp;
3275       break;
3276
3277     default :
3278       /* xgettext:c-format */
3279       fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
3280                        opindex);
3281       abort ();
3282   }
3283
3284   return value;
3285 }
3286
3287 bfd_vma
3288 i960_cgen_get_vma_operand (opindex, fields)
3289      int opindex;
3290      const CGEN_FIELDS * fields;
3291 {
3292   bfd_vma value;
3293
3294   switch (opindex)
3295     {
3296     case I960_OPERAND_SRC1 :
3297       value = fields->f_src1;
3298       break;
3299     case I960_OPERAND_SRC2 :
3300       value = fields->f_src2;
3301       break;
3302     case I960_OPERAND_DST :
3303       value = fields->f_srcdst;
3304       break;
3305     case I960_OPERAND_LIT1 :
3306       value = fields->f_src1;
3307       break;
3308     case I960_OPERAND_LIT2 :
3309       value = fields->f_src2;
3310       break;
3311     case I960_OPERAND_ST_SRC :
3312       value = fields->f_srcdst;
3313       break;
3314     case I960_OPERAND_ABASE :
3315       value = fields->f_abase;
3316       break;
3317     case I960_OPERAND_OFFSET :
3318       value = fields->f_offset;
3319       break;
3320     case I960_OPERAND_SCALE :
3321       value = fields->f_scale;
3322       break;
3323     case I960_OPERAND_INDEX :
3324       value = fields->f_index;
3325       break;
3326     case I960_OPERAND_OPTDISP :
3327       value = fields->f_optdisp;
3328       break;
3329     case I960_OPERAND_BR_SRC1 :
3330       value = fields->f_br_src1;
3331       break;
3332     case I960_OPERAND_BR_SRC2 :
3333       value = fields->f_br_src2;
3334       break;
3335     case I960_OPERAND_BR_DISP :
3336       value = fields->f_br_disp;
3337       break;
3338     case I960_OPERAND_BR_LIT1 :
3339       value = fields->f_br_src1;
3340       break;
3341     case I960_OPERAND_CTRL_DISP :
3342       value = fields->f_ctrl_disp;
3343       break;
3344
3345     default :
3346       /* xgettext:c-format */
3347       fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
3348                        opindex);
3349       abort ();
3350   }
3351
3352   return value;
3353 }
3354
3355 /* Stuffing values in cgen_fields is handled by a collection of functions.
3356    They are distinguished by the type of the VALUE argument they accept.
3357    TODO: floating point, inlining support, remove cases where argument type
3358    not appropriate.  */
3359
3360 void
3361 i960_cgen_set_int_operand (opindex, fields, value)
3362      int opindex;
3363      CGEN_FIELDS * fields;
3364      int value;
3365 {
3366   switch (opindex)
3367     {
3368     case I960_OPERAND_SRC1 :
3369       fields->f_src1 = value;
3370       break;
3371     case I960_OPERAND_SRC2 :
3372       fields->f_src2 = value;
3373       break;
3374     case I960_OPERAND_DST :
3375       fields->f_srcdst = value;
3376       break;
3377     case I960_OPERAND_LIT1 :
3378       fields->f_src1 = value;
3379       break;
3380     case I960_OPERAND_LIT2 :
3381       fields->f_src2 = value;
3382       break;
3383     case I960_OPERAND_ST_SRC :
3384       fields->f_srcdst = value;
3385       break;
3386     case I960_OPERAND_ABASE :
3387       fields->f_abase = value;
3388       break;
3389     case I960_OPERAND_OFFSET :
3390       fields->f_offset = value;
3391       break;
3392     case I960_OPERAND_SCALE :
3393       fields->f_scale = value;
3394       break;
3395     case I960_OPERAND_INDEX :
3396       fields->f_index = value;
3397       break;
3398     case I960_OPERAND_OPTDISP :
3399       fields->f_optdisp = value;
3400       break;
3401     case I960_OPERAND_BR_SRC1 :
3402       fields->f_br_src1 = value;
3403       break;
3404     case I960_OPERAND_BR_SRC2 :
3405       fields->f_br_src2 = value;
3406       break;
3407     case I960_OPERAND_BR_DISP :
3408       fields->f_br_disp = value;
3409       break;
3410     case I960_OPERAND_BR_LIT1 :
3411       fields->f_br_src1 = value;
3412       break;
3413     case I960_OPERAND_CTRL_DISP :
3414       fields->f_ctrl_disp = value;
3415       break;
3416
3417     default :
3418       /* xgettext:c-format */
3419       fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
3420                        opindex);
3421       abort ();
3422   }
3423 }
3424
3425 void
3426 i960_cgen_set_vma_operand (opindex, fields, value)
3427      int opindex;
3428      CGEN_FIELDS * fields;
3429      bfd_vma value;
3430 {
3431   switch (opindex)
3432     {
3433     case I960_OPERAND_SRC1 :
3434       fields->f_src1 = value;
3435       break;
3436     case I960_OPERAND_SRC2 :
3437       fields->f_src2 = value;
3438       break;
3439     case I960_OPERAND_DST :
3440       fields->f_srcdst = value;
3441       break;
3442     case I960_OPERAND_LIT1 :
3443       fields->f_src1 = value;
3444       break;
3445     case I960_OPERAND_LIT2 :
3446       fields->f_src2 = value;
3447       break;
3448     case I960_OPERAND_ST_SRC :
3449       fields->f_srcdst = value;
3450       break;
3451     case I960_OPERAND_ABASE :
3452       fields->f_abase = value;
3453       break;
3454     case I960_OPERAND_OFFSET :
3455       fields->f_offset = value;
3456       break;
3457     case I960_OPERAND_SCALE :
3458       fields->f_scale = value;
3459       break;
3460     case I960_OPERAND_INDEX :
3461       fields->f_index = value;
3462       break;
3463     case I960_OPERAND_OPTDISP :
3464       fields->f_optdisp = value;
3465       break;
3466     case I960_OPERAND_BR_SRC1 :
3467       fields->f_br_src1 = value;
3468       break;
3469     case I960_OPERAND_BR_SRC2 :
3470       fields->f_br_src2 = value;
3471       break;
3472     case I960_OPERAND_BR_DISP :
3473       fields->f_br_disp = value;
3474       break;
3475     case I960_OPERAND_BR_LIT1 :
3476       fields->f_br_src1 = value;
3477       break;
3478     case I960_OPERAND_CTRL_DISP :
3479       fields->f_ctrl_disp = value;
3480       break;
3481
3482     default :
3483       /* xgettext:c-format */
3484       fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
3485                        opindex);
3486       abort ();
3487   }
3488 }
3489