opcodes/ia64-opc-i.c

   1 /* ia64-opc-i.c -- IA-64 `I' opcode table.
   2    Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
   3    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    2, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
  20    02111-1307, USA.  */
  21
  22 #include "ia64-opc.h"
  23
  24 #define I0      IA64_TYPE_I, 0
  25 #define I       IA64_TYPE_I, 1
  26 #define I2      IA64_TYPE_I, 2
  27
  28 /* instruction bit fields: */
  29 #define bC(x)           (((ia64_insn) ((x) & 0x1)) << 12)
  30 #define bIh(x)          (((ia64_insn) ((x) & 0x1)) << 23)
  31 #define bTa(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  32 #define bTag13(x)       (((ia64_insn) ((x) & 0x1)) << 33)
  33 #define bTb(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  34 #define bVc(x)          (((ia64_insn) ((x) & 0x1)) << 20)
  35 #define bVe(x)          (((ia64_insn) ((x) & 0x1)) << 32)
  36 #define bWh(x)          (((ia64_insn) ((x) & 0x3)) << 20)
  37 #define bX(x)           (((ia64_insn) ((x) & 0x1)) << 33)
  38 #define bXb(x)          (((ia64_insn) ((x) & 0x1)) << 22)
  39 #define bX2(x)          (((ia64_insn) ((x) & 0x3)) << 34)
  40 #define bX2a(x)         (((ia64_insn) ((x) & 0x3)) << 34)
  41 #define bX2b(x)         (((ia64_insn) ((x) & 0x3)) << 28)
  42 #define bX2c(x)         (((ia64_insn) ((x) & 0x3)) << 30)
  43 #define bX3(x)          (((ia64_insn) ((x) & 0x7)) << 33)
  44 #define bX6(x)          (((ia64_insn) ((x) & 0x3f)) << 27)
  45 #define bYa(x)          (((ia64_insn) ((x) & 0x1)) << 13)
  46 #define bYb(x)          (((ia64_insn) ((x) & 0x1)) << 26)
  47 #define bZa(x)          (((ia64_insn) ((x) & 0x1)) << 36)
  48 #define bZb(x)          (((ia64_insn) ((x) & 0x1)) << 33)
  49
  50 /* instruction bit masks: */
  51 #define mC      bC (-1)
  52 #define mIh     bIh (-1)
  53 #define mTa     bTa (-1)
  54 #define mTag13  bTag13 (-1)
  55 #define mTb     bTb (-1)
  56 #define mVc     bVc (-1)
  57 #define mVe     bVe (-1)
  58 #define mWh     bWh (-1)
  59 #define mX      bX (-1)
  60 #define mXb     bXb (-1)
  61 #define mX2     bX2 (-1)
  62 #define mX2a    bX2a (-1)
  63 #define mX2b    bX2b (-1)
  64 #define mX2c    bX2c (-1)
  65 #define mX3     bX3 (-1)
  66 #define mX6     bX6 (-1)
  67 #define mYa     bYa (-1)
  68 #define mYb     bYb (-1)
  69 #define mZa     bZa (-1)
  70 #define mZb     bZb (-1)
  71
  72 #define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
  73         (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
  74         (mOp | mZa | mZb | mVe | mX2a | mX2b)
  75 #define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
  76   (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
  77         (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
  78 #define OpX2X(a,b,c)            (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
  79 #define OpX2XYa(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
  80                                 (mOp | mX2 | mX | mYa)
  81 #define OpX2XYb(a,b,c,d)        (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
  82                                 (mOp | mX2 | mX | mYb)
  83 #define OpX2TaTbYaC(a,b,c,d,e,f) \
  84         (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
  85         (mOp | mX2 | mTa | mTb | mYa | mC)
  86 #define OpX3(a,b)               (bOp (a) | bX3 (b)), (mOp | mX3)
  87 #define OpX3X6(a,b,c)           (bOp (a) | bX3 (b) | bX6(c)), \
  88                                 (mOp | mX3 | mX6)
  89 #define OpX3XbIhWh(a,b,c,d,e) \
  90   (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
  91   (mOp | mX3 | mXb | mIh | mWh)
  92 #define OpX3XbIhWhTag13(a,b,c,d,e,f) \
  93      (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
  94      (mOp | mX3 | mXb | mIh | mWh | mTag13)
  95
  96 /* Used to initialise unused fields in ia64_opcode struct,
  97    in order to stop gcc from complaining.  */
  98 #define EMPTY 0,0,NULL
  99
 100 struct ia64_opcode ia64_opcodes_i[] =
 101   {
 102     /* I-type instruction encodings (sorted according to major opcode).  */
 103
 104     {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
 105     {"nop.i",   I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX, 0, NULL},
 106     {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
 107
 108     {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
 109 #define MOV(a,b,c,d) \
 110     I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
 111     {"mov.sptk",                MOV (7, 0, 0, 0)},
 112     {"mov.sptk.imp",            MOV (7, 0, 1, 0)},
 113     {"mov",                     MOV (7, 0, 0, 1)},
 114     {"mov.imp",                 MOV (7, 0, 1, 1)},
 115     {"mov.dptk",                MOV (7, 0, 0, 2)},
 116     {"mov.dptk.imp",            MOV (7, 0, 1, 2)},
 117     {"mov.ret.sptk",            MOV (7, 1, 0, 0)},
 118     {"mov.ret.sptk.imp",        MOV (7, 1, 1, 0)},
 119     {"mov.ret",                 MOV (7, 1, 0, 1)},
 120     {"mov.ret.imp",             MOV (7, 1, 1, 1)},
 121     {"mov.ret.dptk",            MOV (7, 1, 0, 2)},
 122     {"mov.ret.dptk.imp",        MOV (7, 1, 1, 2)},
 123 #undef MOV
 124     {"mov",     I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
 125     {"mov",     I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
 126     {"mov",     I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
 127     {"mov",     I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
 128     {"mov",     I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
 129     {"mov.i",   I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
 130     {"mov.i",   I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
 131     {"mov.i",   I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
 132     {"zxt1",    I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
 133     {"zxt2",    I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
 134     {"zxt4",    I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
 135     {"sxt1",    I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
 136     {"sxt2",    I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
 137     {"sxt4",    I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
 138     {"czx1.l",  I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
 139     {"czx2.l",  I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
 140     {"czx1.r",  I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
 141     {"czx2.r",  I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
 142
 143     {"dep",     I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
 144
 145     {"shrp",    I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
 146
 147     {"shr.u",   I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
 148      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
 149     {"extr.u",  I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
 150
 151     {"shr",     I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
 152      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
 153     {"extr",    I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
 154
 155     {"shl",     I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
 156      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
 157     {"dep.z",   I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
 158     {"dep.z",   I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
 159     {"dep",     I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
 160 #define TBIT(a,b,c,d) \
 161         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
 162 #define TBITCM(a,b,c,d) \
 163         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
 164     {"tbit.z",           TBIT   (0, 0, 0, 0)},
 165     {"tbit.nz",          TBITCM (0, 0, 0, 0)},
 166     {"tbit.z.unc",       TBIT   (0, 0, 0, 1)},
 167     {"tbit.nz.unc",      TBITCM (0, 0, 0, 1)},
 168     {"tbit.z.and",       TBIT   (0, 1, 0, 0)},
 169     {"tbit.nz.andcm",    TBITCM (0, 1, 0, 0)},
 170     {"tbit.nz.and",      TBIT   (0, 1, 0, 1)},
 171     {"tbit.z.andcm",     TBITCM (0, 1, 0, 1)},
 172     {"tbit.z.or",        TBIT   (1, 0, 0, 0)},
 173     {"tbit.nz.orcm",     TBITCM (1, 0, 0, 0)},
 174     {"tbit.nz.or",       TBIT   (1, 0, 0, 1)},
 175     {"tbit.z.orcm",      TBITCM (1, 0, 0, 1)},
 176     {"tbit.z.or.andcm",  TBIT   (1, 1, 0, 0)},
 177     {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
 178     {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
 179     {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
 180 #undef TBIT
 181 #define TNAT(a,b,c,d) \
 182         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
 183 #define TNATCM(a,b,c,d) \
 184         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
 185     {"tnat.z",           TNAT   (0, 0, 1, 0)},
 186     {"tnat.nz",          TNATCM (0, 0, 1, 0)},
 187     {"tnat.z.unc",       TNAT   (0, 0, 1, 1)},
 188     {"tnat.nz.unc",      TNATCM (0, 0, 1, 1)},
 189     {"tnat.z.and",       TNAT   (0, 1, 1, 0)},
 190     {"tnat.nz.andcm",    TNATCM (0, 1, 1, 0)},
 191     {"tnat.nz.and",      TNAT   (0, 1, 1, 1)},
 192     {"tnat.z.andcm",     TNATCM (0, 1, 1, 1)},
 193     {"tnat.z.or",        TNAT   (1, 0, 1, 0)},
 194     {"tnat.nz.orcm",     TNATCM (1, 0, 1, 0)},
 195     {"tnat.nz.or",       TNAT   (1, 0, 1, 1)},
 196     {"tnat.z.orcm",      TNATCM (1, 0, 1, 1)},
 197     {"tnat.z.or.andcm",  TNAT   (1, 1, 1, 0)},
 198     {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
 199     {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
 200     {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
 201 #undef TNAT
 202
 203     {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
 204     {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
 205     {"pmpy2.r",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
 206     {"pmpy2.l",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
 207     {"mix1.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
 208     {"mix2.r",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
 209     {"mix4.r",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
 210     {"mix1.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
 211     {"mix2.l",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
 212     {"mix4.l",     I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
 213     {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
 214     {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
 215     {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
 216     {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
 217     {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
 218     {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
 219     {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
 220     {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
 221     {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
 222     {"pmin1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
 223     {"pmax1.u",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
 224     {"pmin2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
 225     {"pmax2",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
 226     {"psad1",      I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
 227     {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
 228     {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
 229     {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
 230     {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
 231     {"shr",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
 232     {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
 233     {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
 234     {"shr.u",   I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
 235     {"pshr2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
 236     {"pshr4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
 237     {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
 238     {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
 239     {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
 240     {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
 241     {"shl",     I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
 242     {"pshl2",   I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
 243     {"pshl4",   I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
 244     {"popcnt",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
 245
 246     {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
 247   };
 248
 249 #undef I0
 250 #undef I
 251 #undef I2
 252 #undef L
 253 #undef bC
 254 #undef bIh
 255 #undef bTa
 256 #undef bTag13
 257 #undef bTb
 258 #undef bVc
 259 #undef bVe
 260 #undef bWh
 261 #undef bX
 262 #undef bXb
 263 #undef bX2
 264 #undef bX2a
 265 #undef bX2b
 266 #undef bX2c
 267 #undef bX3
 268 #undef bX6
 269 #undef bY
 270 #undef bZa
 271 #undef bZb
 272 #undef mC
 273 #undef mIh
 274 #undef mTa
 275 #undef mTag13
 276 #undef mTb
 277 #undef mVc
 278 #undef mVe
 279 #undef mWh
 280 #undef mX
 281 #undef mXb
 282 #undef mX2
 283 #undef mX2a
 284 #undef mX2b
 285 #undef mX2c
 286 #undef mX3
 287 #undef mX6
 288 #undef mY
 289 #undef mZa
 290 #undef mZb
 291 #undef OpZaZbVeX2aX2b
 292 #undef OpZaZbVeX2aX2bX2c
 293 #undef OpX2X
 294 #undef OpX2XYa
 295 #undef OpX2XYb
 296 #undef OpX2TaTbYaC
 297 #undef OpX3
 298 #undef OpX3X6
 299 #undef OpX3XbIhWh
 300 #undef OpX3XbIhWhTag13
 301 #undef EMPTY