opcodes/m32r-desc.c

   1 /* CPU data for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996-2016 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "m32r-desc.h"
  32 #include "m32r-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  47 {
  48   { "base", MACH_BASE },
  49   { "m32r", MACH_M32R },
  50   { "m32rx", MACH_M32RX },
  51   { "m32r2", MACH_M32R2 },
  52   { "max", MACH_MAX },
  53   { 0, 0 }
  54 };
  55
  56 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  57 {
  58   { "m32r", ISA_M32R },
  59   { "max", ISA_MAX },
  60   { 0, 0 }
  61 };
  62
  63 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
  64 {
  65   { "NONE", PIPE_NONE },
  66   { "O", PIPE_O },
  67   { "S", PIPE_S },
  68   { "OS", PIPE_OS },
  69   { "O_OS", PIPE_O_OS },
  70   { 0, 0 }
  71 };
  72
  73 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  74 {
  75   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  76   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  77   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  78   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  79   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  80   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  81   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  82   { "RELOC", &bool_attr[0], &bool_attr[0] },
  83   { 0, 0, 0 }
  84 };
  85
  86 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  87 {
  88   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  89   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  90   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  91   { "PC", &bool_attr[0], &bool_attr[0] },
  92   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  93   { 0, 0, 0 }
  94 };
  95
  96 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  97 {
  98   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  99   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 100   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
 101   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 102   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 103   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 104   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 105   { "RELAX", &bool_attr[0], &bool_attr[0] },
 106   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 107   { "RELOC", &bool_attr[0], &bool_attr[0] },
 108   { 0, 0, 0 }
 109 };
 110
 111 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 112 {
 113   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 114   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 115   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 116   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 117   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 118   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 119   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 120   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 121   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 122   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 123   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 124   { "PBB", &bool_attr[0], &bool_attr[0] },
 125   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 126   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 127   { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
 128   { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
 129   { 0, 0, 0 }
 130 };
 131
 132 /* Instruction set variants.  */
 133
 134 static const CGEN_ISA m32r_cgen_isa_table[] = {
 135   { "m32r", 32, 32, 16, 32 },
 136   { 0, 0, 0, 0, 0 }
 137 };
 138
 139 /* Machine variants.  */
 140
 141 static const CGEN_MACH m32r_cgen_mach_table[] = {
 142   { "m32r", "m32r", MACH_M32R, 0 },
 143   { "m32rx", "m32rx", MACH_M32RX, 0 },
 144   { "m32r2", "m32r2", MACH_M32R2, 0 },
 145   { 0, 0, 0, 0 }
 146 };
 147
 148 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 149 {
 150   { "fp", 13, {0, {{{0, 0}}}}, 0, 0 },
 151   { "lr", 14, {0, {{{0, 0}}}}, 0, 0 },
 152   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 },
 153   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 154   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 155   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 156   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 157   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 158   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 159   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 160   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 161   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 162   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 163   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
 164   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
 165   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
 166   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
 167   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
 168   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
 169 };
 170
 171 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 172 {
 173   & m32r_cgen_opval_gr_names_entries[0],
 174   19,
 175   0, 0, 0, 0, ""
 176 };
 177
 178 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 179 {
 180   { "psw", 0, {0, {{{0, 0}}}}, 0, 0 },
 181   { "cbr", 1, {0, {{{0, 0}}}}, 0, 0 },
 182   { "spi", 2, {0, {{{0, 0}}}}, 0, 0 },
 183   { "spu", 3, {0, {{{0, 0}}}}, 0, 0 },
 184   { "bpc", 6, {0, {{{0, 0}}}}, 0, 0 },
 185   { "bbpsw", 8, {0, {{{0, 0}}}}, 0, 0 },
 186   { "bbpc", 14, {0, {{{0, 0}}}}, 0, 0 },
 187   { "evb", 5, {0, {{{0, 0}}}}, 0, 0 },
 188   { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
 189   { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
 190   { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
 191   { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
 192   { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
 193   { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
 194   { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
 195   { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
 196   { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
 197   { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
 198   { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
 199   { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
 200   { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
 201   { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
 202   { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
 203   { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
 204 };
 205
 206 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 207 {
 208   & m32r_cgen_opval_cr_names_entries[0],
 209   24,
 210   0, 0, 0, 0, ""
 211 };
 212
 213 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 214 {
 215   { "a0", 0, {0, {{{0, 0}}}}, 0, 0 },
 216   { "a1", 1, {0, {{{0, 0}}}}, 0, 0 }
 217 };
 218
 219 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 220 {
 221   & m32r_cgen_opval_h_accums_entries[0],
 222   2,
 223   0, 0, 0, 0, ""
 224 };
 225
 226
 227 /* The hardware table.  */
 228
 229 #define A(a) (1 << CGEN_HW_##a)
 230
 231 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 232 {
 233   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 234   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 235   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 236   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 237   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 238   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 239   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 240   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 241   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 242   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 243   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 244   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 245   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } } },
 246   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 247   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 248   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 249   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 250   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 251   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 252 };
 253
 254 #undef A
 255
 256
 257 /* The instruction field table.  */
 258
 259 #define A(a) (1 << CGEN_IFLD_##a)
 260
 261 const CGEN_IFLD m32r_cgen_ifld_table[] =
 262 {
 263   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 264   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 265   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 266   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 267   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 268   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 269   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 270   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 271   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 272   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 273   { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 274   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 275   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 276   { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 277   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 278   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 279   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 280   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 281   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 282   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 283   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 284   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 285   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 286   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 287   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 288   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 289   { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 290   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 291   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 292   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 293 };
 294
 295 #undef A
 296
 297
 298
 299 /* multi ifield declarations */
 300
 301
 302
 303 /* multi ifield definitions */
 304
 305
 306 /* The operand table.  */
 307
 308 #define A(a) (1 << CGEN_OPERAND_##a)
 309 #define OPERAND(op) M32R_OPERAND_##op
 310
 311 const CGEN_OPERAND m32r_cgen_operand_table[] =
 312 {
 313 /* pc: program counter */
 314   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 315     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
 316     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 317 /* sr: source register */
 318   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 319     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 320     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 321 /* dr: destination register */
 322   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 323     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 324     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 325 /* src1: source register 1 */
 326   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 327     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 328     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 329 /* src2: source register 2 */
 330   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 331     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 332     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 333 /* scr: source control register */
 334   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 335     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 336     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 337 /* dcr: destination control register */
 338   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 339     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 340     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 341 /* simm8: 8 bit signed immediate */
 342   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 343     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
 344     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 345 /* simm16: 16 bit signed immediate */
 346   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 347     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 348     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 349 /* uimm3: 3 bit unsigned number */
 350   { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
 351     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } },
 352     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 353 /* uimm4: 4 bit trap number */
 354   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 355     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
 356     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 357 /* uimm5: 5 bit shift count */
 358   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 359     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
 360     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 361 /* uimm8: 8 bit unsigned immediate */
 362   { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
 363     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } },
 364     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 365 /* uimm16: 16 bit unsigned immediate */
 366   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 367     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 368     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 369 /* imm1: 1 bit immediate */
 370   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 371     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
 372     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 373 /* accd: accumulator destination register */
 374   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 375     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
 376     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 377 /* accs: accumulator source register */
 378   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 379     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
 380     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 381 /* acc: accumulator reg (d) */
 382   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 383     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
 384     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } } } }  },
 385 /* hash: # prefix */
 386   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 387     { 0, { (const PTR) 0 } },
 388     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 389 /* hi16: high 16 bit immediate, sign optional */
 390   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 391     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
 392     { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
 393 /* slo16: 16 bit signed immediate, for low() */
 394   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 395     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 396     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 397 /* ulo16: 16 bit unsigned immediate, for low() */
 398   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 399     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 400     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 401 /* uimm24: 24 bit address */
 402   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 403     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
 404     { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 405 /* disp8: 8 bit displacement */
 406   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 407     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
 408     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 409 /* disp16: 16 bit displacement */
 410   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 411     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
 412     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 413 /* disp24: 24 bit displacement */
 414   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 415     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
 416     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 417 /* condbit: condition bit */
 418   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 419     { 0, { (const PTR) 0 } },
 420     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 421 /* accum: accumulator */
 422   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 423     { 0, { (const PTR) 0 } },
 424     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 425 /* sentinel */
 426   { 0, 0, 0, 0, 0,
 427     { 0, { (const PTR) 0 } },
 428     { 0, { { { (1<<MACH_BASE), 0 } } } } }
 429 };
 430
 431 #undef A
 432
 433
 434 /* The instruction table.  */
 435
 436 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 437 #define A(a) (1 << CGEN_INSN_##a)
 438
 439 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 440 {
 441   /* Special null first entry.
 442      A `num' value of zero is thus invalid.
 443      Also, the special `invalid' insn resides here.  */
 444   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
 445 /* add $dr,$sr */
 446   {
 447     M32R_INSN_ADD, "add", "add", 16,
 448     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 449   },
 450 /* add3 $dr,$sr,$hash$slo16 */
 451   {
 452     M32R_INSN_ADD3, "add3", "add3", 32,
 453     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 454   },
 455 /* and $dr,$sr */
 456   {
 457     M32R_INSN_AND, "and", "and", 16,
 458     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 459   },
 460 /* and3 $dr,$sr,$uimm16 */
 461   {
 462     M32R_INSN_AND3, "and3", "and3", 32,
 463     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 464   },
 465 /* or $dr,$sr */
 466   {
 467     M32R_INSN_OR, "or", "or", 16,
 468     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 469   },
 470 /* or3 $dr,$sr,$hash$ulo16 */
 471   {
 472     M32R_INSN_OR3, "or3", "or3", 32,
 473     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 474   },
 475 /* xor $dr,$sr */
 476   {
 477     M32R_INSN_XOR, "xor", "xor", 16,
 478     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 479   },
 480 /* xor3 $dr,$sr,$uimm16 */
 481   {
 482     M32R_INSN_XOR3, "xor3", "xor3", 32,
 483     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 484   },
 485 /* addi $dr,$simm8 */
 486   {
 487     M32R_INSN_ADDI, "addi", "addi", 16,
 488     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 489   },
 490 /* addv $dr,$sr */
 491   {
 492     M32R_INSN_ADDV, "addv", "addv", 16,
 493     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 494   },
 495 /* addv3 $dr,$sr,$simm16 */
 496   {
 497     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 498     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 499   },
 500 /* addx $dr,$sr */
 501   {
 502     M32R_INSN_ADDX, "addx", "addx", 16,
 503     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 504   },
 505 /* bc.s $disp8 */
 506   {
 507     M32R_INSN_BC8, "bc8", "bc.s", 16,
 508     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 509   },
 510 /* bc.l $disp24 */
 511   {
 512     M32R_INSN_BC24, "bc24", "bc.l", 32,
 513     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 514   },
 515 /* beq $src1,$src2,$disp16 */
 516   {
 517     M32R_INSN_BEQ, "beq", "beq", 32,
 518     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 519   },
 520 /* beqz $src2,$disp16 */
 521   {
 522     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 523     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 524   },
 525 /* bgez $src2,$disp16 */
 526   {
 527     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 528     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 529   },
 530 /* bgtz $src2,$disp16 */
 531   {
 532     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 533     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 534   },
 535 /* blez $src2,$disp16 */
 536   {
 537     M32R_INSN_BLEZ, "blez", "blez", 32,
 538     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 539   },
 540 /* bltz $src2,$disp16 */
 541   {
 542     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 543     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 544   },
 545 /* bnez $src2,$disp16 */
 546   {
 547     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 548     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 549   },
 550 /* bl.s $disp8 */
 551   {
 552     M32R_INSN_BL8, "bl8", "bl.s", 16,
 553     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 554   },
 555 /* bl.l $disp24 */
 556   {
 557     M32R_INSN_BL24, "bl24", "bl.l", 32,
 558     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 559   },
 560 /* bcl.s $disp8 */
 561   {
 562     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 563     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 564   },
 565 /* bcl.l $disp24 */
 566   {
 567     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 568     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 569   },
 570 /* bnc.s $disp8 */
 571   {
 572     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 573     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 574   },
 575 /* bnc.l $disp24 */
 576   {
 577     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 578     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 579   },
 580 /* bne $src1,$src2,$disp16 */
 581   {
 582     M32R_INSN_BNE, "bne", "bne", 32,
 583     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 584   },
 585 /* bra.s $disp8 */
 586   {
 587     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 588     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 589   },
 590 /* bra.l $disp24 */
 591   {
 592     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 593     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 594   },
 595 /* bncl.s $disp8 */
 596   {
 597     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 598     { 0|A(FILL_SLOT)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 599   },
 600 /* bncl.l $disp24 */
 601   {
 602     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 603     { 0|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 604   },
 605 /* cmp $src1,$src2 */
 606   {
 607     M32R_INSN_CMP, "cmp", "cmp", 16,
 608     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 609   },
 610 /* cmpi $src2,$simm16 */
 611   {
 612     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 613     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 614   },
 615 /* cmpu $src1,$src2 */
 616   {
 617     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 618     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 619   },
 620 /* cmpui $src2,$simm16 */
 621   {
 622     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 623     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 624   },
 625 /* cmpeq $src1,$src2 */
 626   {
 627     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 628     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
 629   },
 630 /* cmpz $src2 */
 631   {
 632     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 633     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
 634   },
 635 /* div $dr,$sr */
 636   {
 637     M32R_INSN_DIV, "div", "div", 32,
 638     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 639   },
 640 /* divu $dr,$sr */
 641   {
 642     M32R_INSN_DIVU, "divu", "divu", 32,
 643     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 644   },
 645 /* rem $dr,$sr */
 646   {
 647     M32R_INSN_REM, "rem", "rem", 32,
 648     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 649   },
 650 /* remu $dr,$sr */
 651   {
 652     M32R_INSN_REMU, "remu", "remu", 32,
 653     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 654   },
 655 /* remh $dr,$sr */
 656   {
 657     M32R_INSN_REMH, "remh", "remh", 32,
 658     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 659   },
 660 /* remuh $dr,$sr */
 661   {
 662     M32R_INSN_REMUH, "remuh", "remuh", 32,
 663     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 664   },
 665 /* remb $dr,$sr */
 666   {
 667     M32R_INSN_REMB, "remb", "remb", 32,
 668     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 669   },
 670 /* remub $dr,$sr */
 671   {
 672     M32R_INSN_REMUB, "remub", "remub", 32,
 673     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 674   },
 675 /* divuh $dr,$sr */
 676   {
 677     M32R_INSN_DIVUH, "divuh", "divuh", 32,
 678     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 679   },
 680 /* divb $dr,$sr */
 681   {
 682     M32R_INSN_DIVB, "divb", "divb", 32,
 683     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 684   },
 685 /* divub $dr,$sr */
 686   {
 687     M32R_INSN_DIVUB, "divub", "divub", 32,
 688     { 0, { { { (1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 689   },
 690 /* divh $dr,$sr */
 691   {
 692     M32R_INSN_DIVH, "divh", "divh", 32,
 693     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
 694   },
 695 /* jc $sr */
 696   {
 697     M32R_INSN_JC, "jc", "jc", 16,
 698     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 699   },
 700 /* jnc $sr */
 701   {
 702     M32R_INSN_JNC, "jnc", "jnc", 16,
 703     { 0|A(SPECIAL)|A(COND_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
 704   },
 705 /* jl $sr */
 706   {
 707     M32R_INSN_JL, "jl", "jl", 16,
 708     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 709   },
 710 /* jmp $sr */
 711   {
 712     M32R_INSN_JMP, "jmp", "jmp", 16,
 713     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 714   },
 715 /* ld $dr,@$sr */
 716   {
 717     M32R_INSN_LD, "ld", "ld", 16,
 718     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 719   },
 720 /* ld $dr,@($slo16,$sr) */
 721   {
 722     M32R_INSN_LD_D, "ld-d", "ld", 32,
 723     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 724   },
 725 /* ldb $dr,@$sr */
 726   {
 727     M32R_INSN_LDB, "ldb", "ldb", 16,
 728     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 729   },
 730 /* ldb $dr,@($slo16,$sr) */
 731   {
 732     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 733     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 734   },
 735 /* ldh $dr,@$sr */
 736   {
 737     M32R_INSN_LDH, "ldh", "ldh", 16,
 738     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 739   },
 740 /* ldh $dr,@($slo16,$sr) */
 741   {
 742     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 743     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 744   },
 745 /* ldub $dr,@$sr */
 746   {
 747     M32R_INSN_LDUB, "ldub", "ldub", 16,
 748     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 749   },
 750 /* ldub $dr,@($slo16,$sr) */
 751   {
 752     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 753     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 754   },
 755 /* lduh $dr,@$sr */
 756   {
 757     M32R_INSN_LDUH, "lduh", "lduh", 16,
 758     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 759   },
 760 /* lduh $dr,@($slo16,$sr) */
 761   {
 762     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 763     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 764   },
 765 /* ld $dr,@$sr+ */
 766   {
 767     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 768     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 769   },
 770 /* ld24 $dr,$uimm24 */
 771   {
 772     M32R_INSN_LD24, "ld24", "ld24", 32,
 773     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 774   },
 775 /* ldi8 $dr,$simm8 */
 776   {
 777     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 778     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 779   },
 780 /* ldi16 $dr,$hash$slo16 */
 781   {
 782     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 783     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 784   },
 785 /* lock $dr,@$sr */
 786   {
 787     M32R_INSN_LOCK, "lock", "lock", 16,
 788     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 789   },
 790 /* machi $src1,$src2 */
 791   {
 792     M32R_INSN_MACHI, "machi", "machi", 16,
 793     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 794   },
 795 /* machi $src1,$src2,$acc */
 796   {
 797     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 798     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 799   },
 800 /* maclo $src1,$src2 */
 801   {
 802     M32R_INSN_MACLO, "maclo", "maclo", 16,
 803     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 804   },
 805 /* maclo $src1,$src2,$acc */
 806   {
 807     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 808     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 809   },
 810 /* macwhi $src1,$src2 */
 811   {
 812     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 813     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 814   },
 815 /* macwhi $src1,$src2,$acc */
 816   {
 817     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 818     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 819   },
 820 /* macwlo $src1,$src2 */
 821   {
 822     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 823     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 824   },
 825 /* macwlo $src1,$src2,$acc */
 826   {
 827     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 828     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 829   },
 830 /* mul $dr,$sr */
 831   {
 832     M32R_INSN_MUL, "mul", "mul", 16,
 833     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_S, 0 } } } }
 834   },
 835 /* mulhi $src1,$src2 */
 836   {
 837     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 838     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 839   },
 840 /* mulhi $src1,$src2,$acc */
 841   {
 842     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 843     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 844   },
 845 /* mullo $src1,$src2 */
 846   {
 847     M32R_INSN_MULLO, "mullo", "mullo", 16,
 848     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 849   },
 850 /* mullo $src1,$src2,$acc */
 851   {
 852     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 853     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 854   },
 855 /* mulwhi $src1,$src2 */
 856   {
 857     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 858     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 859   },
 860 /* mulwhi $src1,$src2,$acc */
 861   {
 862     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 863     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 864   },
 865 /* mulwlo $src1,$src2 */
 866   {
 867     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 868     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 869   },
 870 /* mulwlo $src1,$src2,$acc */
 871   {
 872     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 873     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 874   },
 875 /* mv $dr,$sr */
 876   {
 877     M32R_INSN_MV, "mv", "mv", 16,
 878     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 879   },
 880 /* mvfachi $dr */
 881   {
 882     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 883     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 884   },
 885 /* mvfachi $dr,$accs */
 886   {
 887     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 888     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 889   },
 890 /* mvfaclo $dr */
 891   {
 892     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 893     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 894   },
 895 /* mvfaclo $dr,$accs */
 896   {
 897     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 898     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 899   },
 900 /* mvfacmi $dr */
 901   {
 902     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 903     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 904   },
 905 /* mvfacmi $dr,$accs */
 906   {
 907     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 908     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 909   },
 910 /* mvfc $dr,$scr */
 911   {
 912     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 913     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 914   },
 915 /* mvtachi $src1 */
 916   {
 917     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 918     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 919   },
 920 /* mvtachi $src1,$accs */
 921   {
 922     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 923     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 924   },
 925 /* mvtaclo $src1 */
 926   {
 927     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 928     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 929   },
 930 /* mvtaclo $src1,$accs */
 931   {
 932     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 933     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 934   },
 935 /* mvtc $sr,$dcr */
 936   {
 937     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 938     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 939   },
 940 /* neg $dr,$sr */
 941   {
 942     M32R_INSN_NEG, "neg", "neg", 16,
 943     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 944   },
 945 /* nop */
 946   {
 947     M32R_INSN_NOP, "nop", "nop", 16,
 948     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 949   },
 950 /* not $dr,$sr */
 951   {
 952     M32R_INSN_NOT, "not", "not", 16,
 953     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
 954   },
 955 /* rac */
 956   {
 957     M32R_INSN_RAC, "rac", "rac", 16,
 958     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 959   },
 960 /* rac $accd,$accs,$imm1 */
 961   {
 962     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 963     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 964   },
 965 /* rach */
 966   {
 967     M32R_INSN_RACH, "rach", "rach", 16,
 968     { 0, { { { (1<<MACH_M32R), 0 } }, { { PIPE_S, 0 } } } }
 969   },
 970 /* rach $accd,$accs,$imm1 */
 971   {
 972     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 973     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
 974   },
 975 /* rte */
 976   {
 977     M32R_INSN_RTE, "rte", "rte", 16,
 978     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
 979   },
 980 /* seth $dr,$hash$hi16 */
 981   {
 982     M32R_INSN_SETH, "seth", "seth", 32,
 983     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 984   },
 985 /* sll $dr,$sr */
 986   {
 987     M32R_INSN_SLL, "sll", "sll", 16,
 988     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
 989   },
 990 /* sll3 $dr,$sr,$simm16 */
 991   {
 992     M32R_INSN_SLL3, "sll3", "sll3", 32,
 993     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
 994   },
 995 /* slli $dr,$uimm5 */
 996   {
 997     M32R_INSN_SLLI, "slli", "slli", 16,
 998     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
 999   },
1000 /* sra $dr,$sr */
1001   {
1002     M32R_INSN_SRA, "sra", "sra", 16,
1003     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1004   },
1005 /* sra3 $dr,$sr,$simm16 */
1006   {
1007     M32R_INSN_SRA3, "sra3", "sra3", 32,
1008     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1009   },
1010 /* srai $dr,$uimm5 */
1011   {
1012     M32R_INSN_SRAI, "srai", "srai", 16,
1013     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1014   },
1015 /* srl $dr,$sr */
1016   {
1017     M32R_INSN_SRL, "srl", "srl", 16,
1018     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1019   },
1020 /* srl3 $dr,$sr,$simm16 */
1021   {
1022     M32R_INSN_SRL3, "srl3", "srl3", 32,
1023     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1024   },
1025 /* srli $dr,$uimm5 */
1026   {
1027     M32R_INSN_SRLI, "srli", "srli", 16,
1028     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O_OS, 0 } } } }
1029   },
1030 /* st $src1,@$src2 */
1031   {
1032     M32R_INSN_ST, "st", "st", 16,
1033     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1034   },
1035 /* st $src1,@($slo16,$src2) */
1036   {
1037     M32R_INSN_ST_D, "st-d", "st", 32,
1038     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1039   },
1040 /* stb $src1,@$src2 */
1041   {
1042     M32R_INSN_STB, "stb", "stb", 16,
1043     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1044   },
1045 /* stb $src1,@($slo16,$src2) */
1046   {
1047     M32R_INSN_STB_D, "stb-d", "stb", 32,
1048     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1049   },
1050 /* sth $src1,@$src2 */
1051   {
1052     M32R_INSN_STH, "sth", "sth", 16,
1053     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1054   },
1055 /* sth $src1,@($slo16,$src2) */
1056   {
1057     M32R_INSN_STH_D, "sth-d", "sth", 32,
1058     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1059   },
1060 /* st $src1,@+$src2 */
1061   {
1062     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1063     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1064   },
1065 /* sth $src1,@$src2+ */
1066   {
1067     M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
1068     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1069   },
1070 /* stb $src1,@$src2+ */
1071   {
1072     M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
1073     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1074   },
1075 /* st $src1,@-$src2 */
1076   {
1077     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1078     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1079   },
1080 /* sub $dr,$sr */
1081   {
1082     M32R_INSN_SUB, "sub", "sub", 16,
1083     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1084   },
1085 /* subv $dr,$sr */
1086   {
1087     M32R_INSN_SUBV, "subv", "subv", 16,
1088     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1089   },
1090 /* subx $dr,$sr */
1091   {
1092     M32R_INSN_SUBX, "subx", "subx", 16,
1093     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1094   },
1095 /* trap $uimm4 */
1096   {
1097     M32R_INSN_TRAP, "trap", "trap", 16,
1098     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1099   },
1100 /* unlock $src1,@$src2 */
1101   {
1102     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1103     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1104   },
1105 /* satb $dr,$sr */
1106   {
1107     M32R_INSN_SATB, "satb", "satb", 32,
1108     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1109   },
1110 /* sath $dr,$sr */
1111   {
1112     M32R_INSN_SATH, "sath", "sath", 32,
1113     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1114   },
1115 /* sat $dr,$sr */
1116   {
1117     M32R_INSN_SAT, "sat", "sat", 32,
1118     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_NONE, 0 } } } }
1119   },
1120 /* pcmpbz $src2 */
1121   {
1122     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1123     { 0|A(SPECIAL), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_OS, 0 } } } }
1124   },
1125 /* sadd */
1126   {
1127     M32R_INSN_SADD, "sadd", "sadd", 16,
1128     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1129   },
1130 /* macwu1 $src1,$src2 */
1131   {
1132     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1133     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1134   },
1135 /* msblo $src1,$src2 */
1136   {
1137     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1138     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1139   },
1140 /* mulwu1 $src1,$src2 */
1141   {
1142     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1143     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1144   },
1145 /* maclh1 $src1,$src2 */
1146   {
1147     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1148     { 0, { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_S, 0 } } } }
1149   },
1150 /* sc */
1151   {
1152     M32R_INSN_SC, "sc", "sc", 16,
1153     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1154   },
1155 /* snc */
1156   {
1157     M32R_INSN_SNC, "snc", "snc", 16,
1158     { 0|A(SPECIAL)|A(SKIP_CTI), { { { (1<<MACH_M32RX)|(1<<MACH_M32R2), 0 } }, { { PIPE_O, 0 } } } }
1159   },
1160 /* clrpsw $uimm8 */
1161   {
1162     M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
1163     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1164   },
1165 /* setpsw $uimm8 */
1166   {
1167     M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
1168     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1169   },
1170 /* bset $uimm3,@($slo16,$sr) */
1171   {
1172     M32R_INSN_BSET, "bset", "bset", 32,
1173     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1174   },
1175 /* bclr $uimm3,@($slo16,$sr) */
1176   {
1177     M32R_INSN_BCLR, "bclr", "bclr", 32,
1178     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } }
1179   },
1180 /* btst $uimm3,$sr */
1181   {
1182     M32R_INSN_BTST, "btst", "btst", 16,
1183     { 0|A(SPECIAL_M32R), { { { (1<<MACH_BASE), 0 } }, { { PIPE_O, 0 } } } }
1184   },
1185 };
1186
1187 #undef OP
1188 #undef A
1189
1190 /* Initialize anything needed to be done once, before any cpu_open call.  */
1191
1192 static void
1193 init_tables (void)
1194 {
1195 }
1196
1197 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1198 static void build_hw_table      (CGEN_CPU_TABLE *);
1199 static void build_ifield_table  (CGEN_CPU_TABLE *);
1200 static void build_operand_table (CGEN_CPU_TABLE *);
1201 static void build_insn_table    (CGEN_CPU_TABLE *);
1202 static void m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1203
1204 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1205
1206 static const CGEN_MACH *
1207 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1208 {
1209   while (table->name)
1210     {
1211       if (strcmp (name, table->bfd_name) == 0)
1212         return table;
1213       ++table;
1214     }
1215   abort ();
1216 }
1217
1218 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1219
1220 static void
1221 build_hw_table (CGEN_CPU_TABLE *cd)
1222 {
1223   int i;
1224   int machs = cd->machs;
1225   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1226   /* MAX_HW is only an upper bound on the number of selected entries.
1227      However each entry is indexed by it's enum so there can be holes in
1228      the table.  */
1229   const CGEN_HW_ENTRY **selected =
1230     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1231
1232   cd->hw_table.init_entries = init;
1233   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1234   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1235   /* ??? For now we just use machs to determine which ones we want.  */
1236   for (i = 0; init[i].name != NULL; ++i)
1237     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1238         & machs)
1239       selected[init[i].type] = &init[i];
1240   cd->hw_table.entries = selected;
1241   cd->hw_table.num_entries = MAX_HW;
1242 }
1243
1244 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1245
1246 static void
1247 build_ifield_table (CGEN_CPU_TABLE *cd)
1248 {
1249   cd->ifld_table = & m32r_cgen_ifld_table[0];
1250 }
1251
1252 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1253
1254 static void
1255 build_operand_table (CGEN_CPU_TABLE *cd)
1256 {
1257   int i;
1258   int machs = cd->machs;
1259   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1260   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1261      However each entry is indexed by it's enum so there can be holes in
1262      the table.  */
1263   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1264
1265   cd->operand_table.init_entries = init;
1266   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1267   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1268   /* ??? For now we just use mach to determine which ones we want.  */
1269   for (i = 0; init[i].name != NULL; ++i)
1270     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1271         & machs)
1272       selected[init[i].type] = &init[i];
1273   cd->operand_table.entries = selected;
1274   cd->operand_table.num_entries = MAX_OPERANDS;
1275 }
1276
1277 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1278    ??? This could leave out insns not supported by the specified mach/isa,
1279    but that would cause errors like "foo only supported by bar" to become
1280    "unknown insn", so for now we include all insns and require the app to
1281    do the checking later.
1282    ??? On the other hand, parsing of such insns may require their hardware or
1283    operand elements to be in the table [which they mightn't be].  */
1284
1285 static void
1286 build_insn_table (CGEN_CPU_TABLE *cd)
1287 {
1288   int i;
1289   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1290   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1291
1292   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1293   for (i = 0; i < MAX_INSNS; ++i)
1294     insns[i].base = &ib[i];
1295   cd->insn_table.init_entries = insns;
1296   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1297   cd->insn_table.num_init_entries = MAX_INSNS;
1298 }
1299
1300 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1301
1302 static void
1303 m32r_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1304 {
1305   int i;
1306   CGEN_BITSET *isas = cd->isas;
1307   unsigned int machs = cd->machs;
1308
1309   cd->int_insn_p = CGEN_INT_INSN_P;
1310
1311   /* Data derived from the isa spec.  */
1312 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1313   cd->default_insn_bitsize = UNSET;
1314   cd->base_insn_bitsize = UNSET;
1315   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1316   cd->max_insn_bitsize = 0;
1317   for (i = 0; i < MAX_ISAS; ++i)
1318     if (cgen_bitset_contains (isas, i))
1319       {
1320         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1321
1322         /* Default insn sizes of all selected isas must be
1323            equal or we set the result to 0, meaning "unknown".  */
1324         if (cd->default_insn_bitsize == UNSET)
1325           cd->default_insn_bitsize = isa->default_insn_bitsize;
1326         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1327           ; /* This is ok.  */
1328         else
1329           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1330
1331         /* Base insn sizes of all selected isas must be equal
1332            or we set the result to 0, meaning "unknown".  */
1333         if (cd->base_insn_bitsize == UNSET)
1334           cd->base_insn_bitsize = isa->base_insn_bitsize;
1335         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1336           ; /* This is ok.  */
1337         else
1338           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1339
1340         /* Set min,max insn sizes.  */
1341         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1342           cd->min_insn_bitsize = isa->min_insn_bitsize;
1343         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1344           cd->max_insn_bitsize = isa->max_insn_bitsize;
1345       }
1346
1347   /* Data derived from the mach spec.  */
1348   for (i = 0; i < MAX_MACHS; ++i)
1349     if (((1 << i) & machs) != 0)
1350       {
1351         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1352
1353         if (mach->insn_chunk_bitsize != 0)
1354         {
1355           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1356             {
1357               fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1358                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1359               abort ();
1360             }
1361
1362           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1363         }
1364       }
1365
1366   /* Determine which hw elements are used by MACH.  */
1367   build_hw_table (cd);
1368
1369   /* Build the ifield table.  */
1370   build_ifield_table (cd);
1371
1372   /* Determine which operands are used by MACH/ISA.  */
1373   build_operand_table (cd);
1374
1375   /* Build the instruction table.  */
1376   build_insn_table (cd);
1377 }
1378
1379 /* Initialize a cpu table and return a descriptor.
1380    It's much like opening a file, and must be the first function called.
1381    The arguments are a set of (type/value) pairs, terminated with
1382    CGEN_CPU_OPEN_END.
1383
1384    Currently supported values:
1385    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1386    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1387    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1388    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1389    CGEN_CPU_OPEN_END:     terminates arguments
1390
1391    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1392    precluded.  */
1393
1394 CGEN_CPU_DESC
1395 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1396 {
1397   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1398   static int init_p;
1399   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1400   unsigned int machs = 0; /* 0 = "unspecified" */
1401   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1402   va_list ap;
1403
1404   if (! init_p)
1405     {
1406       init_tables ();
1407       init_p = 1;
1408     }
1409
1410   memset (cd, 0, sizeof (*cd));
1411
1412   va_start (ap, arg_type);
1413   while (arg_type != CGEN_CPU_OPEN_END)
1414     {
1415       switch (arg_type)
1416         {
1417         case CGEN_CPU_OPEN_ISAS :
1418           isas = va_arg (ap, CGEN_BITSET *);
1419           break;
1420         case CGEN_CPU_OPEN_MACHS :
1421           machs = va_arg (ap, unsigned int);
1422           break;
1423         case CGEN_CPU_OPEN_BFDMACH :
1424           {
1425             const char *name = va_arg (ap, const char *);
1426             const CGEN_MACH *mach =
1427               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1428
1429             machs |= 1 << mach->num;
1430             break;
1431           }
1432         case CGEN_CPU_OPEN_ENDIAN :
1433           endian = va_arg (ap, enum cgen_endian);
1434           break;
1435         default :
1436           fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1437                    arg_type);
1438           abort (); /* ??? return NULL? */
1439         }
1440       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1441     }
1442   va_end (ap);
1443
1444   /* Mach unspecified means "all".  */
1445   if (machs == 0)
1446     machs = (1 << MAX_MACHS) - 1;
1447   /* Base mach is always selected.  */
1448   machs |= 1;
1449   if (endian == CGEN_ENDIAN_UNKNOWN)
1450     {
1451       /* ??? If target has only one, could have a default.  */
1452       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1453       abort ();
1454     }
1455
1456   cd->isas = cgen_bitset_copy (isas);
1457   cd->machs = machs;
1458   cd->endian = endian;
1459   /* FIXME: for the sparc case we can determine insn-endianness statically.
1460      The worry here is where both data and insn endian can be independently
1461      chosen, in which case this function will need another argument.
1462      Actually, will want to allow for more arguments in the future anyway.  */
1463   cd->insn_endian = endian;
1464
1465   /* Table (re)builder.  */
1466   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1467   m32r_cgen_rebuild_tables (cd);
1468
1469   /* Default to not allowing signed overflow.  */
1470   cd->signed_overflow_ok_p = 0;
1471
1472   return (CGEN_CPU_DESC) cd;
1473 }
1474
1475 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1476    MACH_NAME is the bfd name of the mach.  */
1477
1478 CGEN_CPU_DESC
1479 m32r_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1480 {
1481   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1482                                CGEN_CPU_OPEN_ENDIAN, endian,
1483                                CGEN_CPU_OPEN_END);
1484 }
1485
1486 /* Close a cpu table.
1487    ??? This can live in a machine independent file, but there's currently
1488    no place to put this file (there's no libcgen).  libopcodes is the wrong
1489    place as some simulator ports use this but they don't use libopcodes.  */
1490
1491 void
1492 m32r_cgen_cpu_close (CGEN_CPU_DESC cd)
1493 {
1494   unsigned int i;
1495   const CGEN_INSN *insns;
1496
1497   if (cd->macro_insn_table.init_entries)
1498     {
1499       insns = cd->macro_insn_table.init_entries;
1500       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1501         if (CGEN_INSN_RX ((insns)))
1502           regfree (CGEN_INSN_RX (insns));
1503     }
1504
1505   if (cd->insn_table.init_entries)
1506     {
1507       insns = cd->insn_table.init_entries;
1508       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1509         if (CGEN_INSN_RX (insns))
1510           regfree (CGEN_INSN_RX (insns));
1511     }
1512
1513   if (cd->macro_insn_table.init_entries)
1514     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1515
1516   if (cd->insn_table.init_entries)
1517     free ((CGEN_INSN *) cd->insn_table.init_entries);
1518
1519   if (cd->hw_table.entries)
1520     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1521
1522   if (cd->operand_table.entries)
1523     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1524
1525   free (cd);
1526 }
1527