opcodes/m32r-desc.c

   1 /* CPU data for m32r.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "m32r-desc.h"
  32 #include "m32r-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] =
  47 {
  48   { "base", MACH_BASE },
  49   { "m32r", MACH_M32R },
  50   { "m32rx", MACH_M32RX },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] =
  56 {
  57   { "m32r", ISA_M32R },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 static const CGEN_ATTR_ENTRY PIPE_attr[] =
  63 {
  64   { "NONE", PIPE_NONE },
  65   { "O", PIPE_O },
  66   { "S", PIPE_S },
  67   { "OS", PIPE_OS },
  68   { 0, 0 }
  69 };
  70
  71 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
  72 {
  73   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  74   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  75   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  76   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  77   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  78   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  79   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  80   { "RELOC", &bool_attr[0], &bool_attr[0] },
  81   { 0, 0, 0 }
  82 };
  83
  84 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
  85 {
  86   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  87   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  88   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  89   { "PC", &bool_attr[0], &bool_attr[0] },
  90   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  91   { 0, 0, 0 }
  92 };
  93
  94 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
  95 {
  96   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  97   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  98   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  99   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
 100   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
 101   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 102   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 103   { "RELAX", &bool_attr[0], &bool_attr[0] },
 104   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 105   { "RELOC", &bool_attr[0], &bool_attr[0] },
 106   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 107   { 0, 0, 0 }
 108 };
 109
 110 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 111 {
 112   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 113   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 114   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 115   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 116   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 117   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 118   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 119   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 120   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 121   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 122   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 123   { "PBB", &bool_attr[0], &bool_attr[0] },
 124   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
 125   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
 126   { 0, 0, 0 }
 127 };
 128
 129 /* Instruction set variants.  */
 130
 131 static const CGEN_ISA m32r_cgen_isa_table[] = {
 132   { "m32r", 32, 32, 16, 32 },
 133   { 0, 0, 0, 0, 0 }
 134 };
 135
 136 /* Machine variants.  */
 137
 138 static const CGEN_MACH m32r_cgen_mach_table[] = {
 139   { "m32r", "m32r", MACH_M32R, 0 },
 140   { "m32rx", "m32rx", MACH_M32RX, 0 },
 141   { 0, 0, 0, 0 }
 142 };
 143
 144 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 145 {
 146   { "fp", 13, {0, {0}}, 0, 0 },
 147   { "lr", 14, {0, {0}}, 0, 0 },
 148   { "sp", 15, {0, {0}}, 0, 0 },
 149   { "r0", 0, {0, {0}}, 0, 0 },
 150   { "r1", 1, {0, {0}}, 0, 0 },
 151   { "r2", 2, {0, {0}}, 0, 0 },
 152   { "r3", 3, {0, {0}}, 0, 0 },
 153   { "r4", 4, {0, {0}}, 0, 0 },
 154   { "r5", 5, {0, {0}}, 0, 0 },
 155   { "r6", 6, {0, {0}}, 0, 0 },
 156   { "r7", 7, {0, {0}}, 0, 0 },
 157   { "r8", 8, {0, {0}}, 0, 0 },
 158   { "r9", 9, {0, {0}}, 0, 0 },
 159   { "r10", 10, {0, {0}}, 0, 0 },
 160   { "r11", 11, {0, {0}}, 0, 0 },
 161   { "r12", 12, {0, {0}}, 0, 0 },
 162   { "r13", 13, {0, {0}}, 0, 0 },
 163   { "r14", 14, {0, {0}}, 0, 0 },
 164   { "r15", 15, {0, {0}}, 0, 0 }
 165 };
 166
 167 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 168 {
 169   & m32r_cgen_opval_gr_names_entries[0],
 170   19,
 171   0, 0, 0, 0, ""
 172 };
 173
 174 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 175 {
 176   { "psw", 0, {0, {0}}, 0, 0 },
 177   { "cbr", 1, {0, {0}}, 0, 0 },
 178   { "spi", 2, {0, {0}}, 0, 0 },
 179   { "spu", 3, {0, {0}}, 0, 0 },
 180   { "bpc", 6, {0, {0}}, 0, 0 },
 181   { "bbpsw", 8, {0, {0}}, 0, 0 },
 182   { "bbpc", 14, {0, {0}}, 0, 0 },
 183   { "cr0", 0, {0, {0}}, 0, 0 },
 184   { "cr1", 1, {0, {0}}, 0, 0 },
 185   { "cr2", 2, {0, {0}}, 0, 0 },
 186   { "cr3", 3, {0, {0}}, 0, 0 },
 187   { "cr4", 4, {0, {0}}, 0, 0 },
 188   { "cr5", 5, {0, {0}}, 0, 0 },
 189   { "cr6", 6, {0, {0}}, 0, 0 },
 190   { "cr7", 7, {0, {0}}, 0, 0 },
 191   { "cr8", 8, {0, {0}}, 0, 0 },
 192   { "cr9", 9, {0, {0}}, 0, 0 },
 193   { "cr10", 10, {0, {0}}, 0, 0 },
 194   { "cr11", 11, {0, {0}}, 0, 0 },
 195   { "cr12", 12, {0, {0}}, 0, 0 },
 196   { "cr13", 13, {0, {0}}, 0, 0 },
 197   { "cr14", 14, {0, {0}}, 0, 0 },
 198   { "cr15", 15, {0, {0}}, 0, 0 }
 199 };
 200
 201 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 202 {
 203   & m32r_cgen_opval_cr_names_entries[0],
 204   23,
 205   0, 0, 0, 0, ""
 206 };
 207
 208 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 209 {
 210   { "a0", 0, {0, {0}}, 0, 0 },
 211   { "a1", 1, {0, {0}}, 0, 0 }
 212 };
 213
 214 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 215 {
 216   & m32r_cgen_opval_h_accums_entries[0],
 217   2,
 218   0, 0, 0, 0, ""
 219 };
 220
 221
 222 /* The hardware table.  */
 223
 224 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 225 #define A(a) (1 << CGEN_HW_##a)
 226 #else
 227 #define A(a) (1 << CGEN_HW_/**/a)
 228 #endif
 229
 230 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 231 {
 232   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 233   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 234   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 235   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 236   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 237   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
 238   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 239   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 240   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 241   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
 242   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
 243   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 244   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
 245   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 246   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 247   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 248   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 249   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
 250   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 251 };
 252
 253 #undef A
 254
 255
 256 /* The instruction field table.  */
 257
 258 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 259 #define A(a) (1 << CGEN_IFLD_##a)
 260 #else
 261 #define A(a) (1 << CGEN_IFLD_/**/a)
 262 #endif
 263
 264 const CGEN_IFLD m32r_cgen_ifld_table[] =
 265 {
 266   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 267   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
 268   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
 269   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
 270   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 271   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
 272   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 273   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
 274   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 275   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
 276   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
 277   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
 278   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
 279   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 280   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 281   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 282   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 283   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 284   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
 285   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
 286   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
 287   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
 288   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
 289   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
 290   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
 291   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
 292   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 293 };
 294
 295 #undef A
 296
 297
 298
 299 /* multi ifield declarations */
 300
 301
 302
 303 /* multi ifield definitions */
 304
 305
 306 /* The operand table.  */
 307
 308 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 309 #define A(a) (1 << CGEN_OPERAND_##a)
 310 #else
 311 #define A(a) (1 << CGEN_OPERAND_/**/a)
 312 #endif
 313 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 314 #define OPERAND(op) M32R_OPERAND_##op
 315 #else
 316 #define OPERAND(op) M32R_OPERAND_/**/op
 317 #endif
 318
 319 const CGEN_OPERAND m32r_cgen_operand_table[] =
 320 {
 321 /* pc: program counter */
 322   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
 323     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
 324     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 325 /* sr: source register */
 326   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
 327     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 328     { 0, { (1<<MACH_BASE) } }  },
 329 /* dr: destination register */
 330   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
 331     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 332     { 0, { (1<<MACH_BASE) } }  },
 333 /* src1: source register 1 */
 334   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
 335     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 336     { 0, { (1<<MACH_BASE) } }  },
 337 /* src2: source register 2 */
 338   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
 339     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 340     { 0, { (1<<MACH_BASE) } }  },
 341 /* scr: source control register */
 342   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
 343     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
 344     { 0, { (1<<MACH_BASE) } }  },
 345 /* dcr: destination control register */
 346   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
 347     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
 348     { 0, { (1<<MACH_BASE) } }  },
 349 /* simm8: 8 bit signed immediate */
 350   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
 351     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
 352     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 353 /* simm16: 16 bit signed immediate */
 354   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
 355     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 356     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 357 /* uimm4: 4 bit trap number */
 358   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
 359     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
 360     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 361 /* uimm5: 5 bit shift count */
 362   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
 363     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
 364     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 365 /* uimm16: 16 bit unsigned immediate */
 366   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
 367     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 368     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 369 /* imm1: 1 bit immediate */
 370   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
 371     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
 372     { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
 373 /* accd: accumulator destination register */
 374   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
 375     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
 376     { 0, { (1<<MACH_M32RX) } }  },
 377 /* accs: accumulator source register */
 378   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
 379     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
 380     { 0, { (1<<MACH_M32RX) } }  },
 381 /* acc: accumulator reg (d) */
 382   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
 383     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
 384     { 0, { (1<<MACH_M32RX) } }  },
 385 /* hash: # prefix */
 386   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
 387     { 0, { (const PTR) 0 } },
 388     { 0, { (1<<MACH_BASE) } }  },
 389 /* hi16: high 16 bit immediate, sign optional */
 390   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
 391     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
 392     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 393 /* slo16: 16 bit signed immediate, for low() */
 394   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
 395     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
 396     { 0, { (1<<MACH_BASE) } }  },
 397 /* ulo16: 16 bit unsigned immediate, for low() */
 398   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
 399     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
 400     { 0, { (1<<MACH_BASE) } }  },
 401 /* uimm24: 24 bit address */
 402   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
 403     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
 404     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 405 /* disp8: 8 bit displacement */
 406   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
 407     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
 408     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 409 /* disp16: 16 bit displacement */
 410   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
 411     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
 412     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 413 /* disp24: 24 bit displacement */
 414   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
 415     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
 416     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 417 /* condbit: condition bit */
 418   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 419     { 0, { (const PTR) 0 } },
 420     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 421 /* accum: accumulator */
 422   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
 423     { 0, { (const PTR) 0 } },
 424     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 425 /* sentinel */
 426   { 0, 0, 0, 0, 0,
 427     { 0, { (const PTR) 0 } },
 428     { 0, { 0 } } }
 429 };
 430
 431 #undef A
 432
 433
 434 /* The instruction table.  */
 435
 436 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 437 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 438 #define A(a) (1 << CGEN_INSN_##a)
 439 #else
 440 #define A(a) (1 << CGEN_INSN_/**/a)
 441 #endif
 442
 443 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 444 {
 445   /* Special null first entry.
 446      A `num' value of zero is thus invalid.
 447      Also, the special `invalid' insn resides here.  */
 448   { 0, 0, 0, 0, {0, {0}} },
 449 /* add $dr,$sr */
 450   {
 451     M32R_INSN_ADD, "add", "add", 16,
 452     { 0, { (1<<MACH_BASE), PIPE_OS } }
 453   },
 454 /* add3 $dr,$sr,$hash$slo16 */
 455   {
 456     M32R_INSN_ADD3, "add3", "add3", 32,
 457     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 458   },
 459 /* and $dr,$sr */
 460   {
 461     M32R_INSN_AND, "and", "and", 16,
 462     { 0, { (1<<MACH_BASE), PIPE_OS } }
 463   },
 464 /* and3 $dr,$sr,$uimm16 */
 465   {
 466     M32R_INSN_AND3, "and3", "and3", 32,
 467     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 468   },
 469 /* or $dr,$sr */
 470   {
 471     M32R_INSN_OR, "or", "or", 16,
 472     { 0, { (1<<MACH_BASE), PIPE_OS } }
 473   },
 474 /* or3 $dr,$sr,$hash$ulo16 */
 475   {
 476     M32R_INSN_OR3, "or3", "or3", 32,
 477     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 478   },
 479 /* xor $dr,$sr */
 480   {
 481     M32R_INSN_XOR, "xor", "xor", 16,
 482     { 0, { (1<<MACH_BASE), PIPE_OS } }
 483   },
 484 /* xor3 $dr,$sr,$uimm16 */
 485   {
 486     M32R_INSN_XOR3, "xor3", "xor3", 32,
 487     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 488   },
 489 /* addi $dr,$simm8 */
 490   {
 491     M32R_INSN_ADDI, "addi", "addi", 16,
 492     { 0, { (1<<MACH_BASE), PIPE_OS } }
 493   },
 494 /* addv $dr,$sr */
 495   {
 496     M32R_INSN_ADDV, "addv", "addv", 16,
 497     { 0, { (1<<MACH_BASE), PIPE_OS } }
 498   },
 499 /* addv3 $dr,$sr,$simm16 */
 500   {
 501     M32R_INSN_ADDV3, "addv3", "addv3", 32,
 502     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 503   },
 504 /* addx $dr,$sr */
 505   {
 506     M32R_INSN_ADDX, "addx", "addx", 16,
 507     { 0, { (1<<MACH_BASE), PIPE_OS } }
 508   },
 509 /* bc.s $disp8 */
 510   {
 511     M32R_INSN_BC8, "bc8", "bc.s", 16,
 512     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 513   },
 514 /* bc.l $disp24 */
 515   {
 516     M32R_INSN_BC24, "bc24", "bc.l", 32,
 517     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 518   },
 519 /* beq $src1,$src2,$disp16 */
 520   {
 521     M32R_INSN_BEQ, "beq", "beq", 32,
 522     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 523   },
 524 /* beqz $src2,$disp16 */
 525   {
 526     M32R_INSN_BEQZ, "beqz", "beqz", 32,
 527     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 528   },
 529 /* bgez $src2,$disp16 */
 530   {
 531     M32R_INSN_BGEZ, "bgez", "bgez", 32,
 532     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 533   },
 534 /* bgtz $src2,$disp16 */
 535   {
 536     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
 537     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 538   },
 539 /* blez $src2,$disp16 */
 540   {
 541     M32R_INSN_BLEZ, "blez", "blez", 32,
 542     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 543   },
 544 /* bltz $src2,$disp16 */
 545   {
 546     M32R_INSN_BLTZ, "bltz", "bltz", 32,
 547     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 548   },
 549 /* bnez $src2,$disp16 */
 550   {
 551     M32R_INSN_BNEZ, "bnez", "bnez", 32,
 552     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 553   },
 554 /* bl.s $disp8 */
 555   {
 556     M32R_INSN_BL8, "bl8", "bl.s", 16,
 557     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 558   },
 559 /* bl.l $disp24 */
 560   {
 561     M32R_INSN_BL24, "bl24", "bl.l", 32,
 562     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 563   },
 564 /* bcl.s $disp8 */
 565   {
 566     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
 567     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 568   },
 569 /* bcl.l $disp24 */
 570   {
 571     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
 572     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 573   },
 574 /* bnc.s $disp8 */
 575   {
 576     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
 577     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
 578   },
 579 /* bnc.l $disp24 */
 580   {
 581     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
 582     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 583   },
 584 /* bne $src1,$src2,$disp16 */
 585   {
 586     M32R_INSN_BNE, "bne", "bne", 32,
 587     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 588   },
 589 /* bra.s $disp8 */
 590   {
 591     M32R_INSN_BRA8, "bra8", "bra.s", 16,
 592     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 593   },
 594 /* bra.l $disp24 */
 595   {
 596     M32R_INSN_BRA24, "bra24", "bra.l", 32,
 597     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
 598   },
 599 /* bncl.s $disp8 */
 600   {
 601     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
 602     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 603   },
 604 /* bncl.l $disp24 */
 605   {
 606     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
 607     { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
 608   },
 609 /* cmp $src1,$src2 */
 610   {
 611     M32R_INSN_CMP, "cmp", "cmp", 16,
 612     { 0, { (1<<MACH_BASE), PIPE_OS } }
 613   },
 614 /* cmpi $src2,$simm16 */
 615   {
 616     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
 617     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 618   },
 619 /* cmpu $src1,$src2 */
 620   {
 621     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
 622     { 0, { (1<<MACH_BASE), PIPE_OS } }
 623   },
 624 /* cmpui $src2,$simm16 */
 625   {
 626     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
 627     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 628   },
 629 /* cmpeq $src1,$src2 */
 630   {
 631     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
 632     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 633   },
 634 /* cmpz $src2 */
 635   {
 636     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
 637     { 0, { (1<<MACH_M32RX), PIPE_OS } }
 638   },
 639 /* div $dr,$sr */
 640   {
 641     M32R_INSN_DIV, "div", "div", 32,
 642     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 643   },
 644 /* divu $dr,$sr */
 645   {
 646     M32R_INSN_DIVU, "divu", "divu", 32,
 647     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 648   },
 649 /* rem $dr,$sr */
 650   {
 651     M32R_INSN_REM, "rem", "rem", 32,
 652     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 653   },
 654 /* remu $dr,$sr */
 655   {
 656     M32R_INSN_REMU, "remu", "remu", 32,
 657     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 658   },
 659 /* divh $dr,$sr */
 660   {
 661     M32R_INSN_DIVH, "divh", "divh", 32,
 662     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
 663   },
 664 /* jc $sr */
 665   {
 666     M32R_INSN_JC, "jc", "jc", 16,
 667     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 668   },
 669 /* jnc $sr */
 670   {
 671     M32R_INSN_JNC, "jnc", "jnc", 16,
 672     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
 673   },
 674 /* jl $sr */
 675   {
 676     M32R_INSN_JL, "jl", "jl", 16,
 677     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 678   },
 679 /* jmp $sr */
 680   {
 681     M32R_INSN_JMP, "jmp", "jmp", 16,
 682     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 683   },
 684 /* ld $dr,@$sr */
 685   {
 686     M32R_INSN_LD, "ld", "ld", 16,
 687     { 0, { (1<<MACH_BASE), PIPE_O } }
 688   },
 689 /* ld $dr,@($slo16,$sr) */
 690   {
 691     M32R_INSN_LD_D, "ld-d", "ld", 32,
 692     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 693   },
 694 /* ldb $dr,@$sr */
 695   {
 696     M32R_INSN_LDB, "ldb", "ldb", 16,
 697     { 0, { (1<<MACH_BASE), PIPE_O } }
 698   },
 699 /* ldb $dr,@($slo16,$sr) */
 700   {
 701     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
 702     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 703   },
 704 /* ldh $dr,@$sr */
 705   {
 706     M32R_INSN_LDH, "ldh", "ldh", 16,
 707     { 0, { (1<<MACH_BASE), PIPE_O } }
 708   },
 709 /* ldh $dr,@($slo16,$sr) */
 710   {
 711     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
 712     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 713   },
 714 /* ldub $dr,@$sr */
 715   {
 716     M32R_INSN_LDUB, "ldub", "ldub", 16,
 717     { 0, { (1<<MACH_BASE), PIPE_O } }
 718   },
 719 /* ldub $dr,@($slo16,$sr) */
 720   {
 721     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
 722     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 723   },
 724 /* lduh $dr,@$sr */
 725   {
 726     M32R_INSN_LDUH, "lduh", "lduh", 16,
 727     { 0, { (1<<MACH_BASE), PIPE_O } }
 728   },
 729 /* lduh $dr,@($slo16,$sr) */
 730   {
 731     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
 732     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 733   },
 734 /* ld $dr,@$sr+ */
 735   {
 736     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
 737     { 0, { (1<<MACH_BASE), PIPE_O } }
 738   },
 739 /* ld24 $dr,$uimm24 */
 740   {
 741     M32R_INSN_LD24, "ld24", "ld24", 32,
 742     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 743   },
 744 /* ldi8 $dr,$simm8 */
 745   {
 746     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
 747     { 0, { (1<<MACH_BASE), PIPE_OS } }
 748   },
 749 /* ldi16 $dr,$hash$slo16 */
 750   {
 751     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
 752     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 753   },
 754 /* lock $dr,@$sr */
 755   {
 756     M32R_INSN_LOCK, "lock", "lock", 16,
 757     { 0, { (1<<MACH_BASE), PIPE_O } }
 758   },
 759 /* machi $src1,$src2 */
 760   {
 761     M32R_INSN_MACHI, "machi", "machi", 16,
 762     { 0, { (1<<MACH_M32R), PIPE_S } }
 763   },
 764 /* machi $src1,$src2,$acc */
 765   {
 766     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
 767     { 0, { (1<<MACH_M32RX), PIPE_S } }
 768   },
 769 /* maclo $src1,$src2 */
 770   {
 771     M32R_INSN_MACLO, "maclo", "maclo", 16,
 772     { 0, { (1<<MACH_M32R), PIPE_S } }
 773   },
 774 /* maclo $src1,$src2,$acc */
 775   {
 776     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
 777     { 0, { (1<<MACH_M32RX), PIPE_S } }
 778   },
 779 /* macwhi $src1,$src2 */
 780   {
 781     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
 782     { 0, { (1<<MACH_M32R), PIPE_S } }
 783   },
 784 /* macwhi $src1,$src2,$acc */
 785   {
 786     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
 787     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 788   },
 789 /* macwlo $src1,$src2 */
 790   {
 791     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
 792     { 0, { (1<<MACH_M32R), PIPE_S } }
 793   },
 794 /* macwlo $src1,$src2,$acc */
 795   {
 796     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
 797     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 798   },
 799 /* mul $dr,$sr */
 800   {
 801     M32R_INSN_MUL, "mul", "mul", 16,
 802     { 0, { (1<<MACH_BASE), PIPE_S } }
 803   },
 804 /* mulhi $src1,$src2 */
 805   {
 806     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
 807     { 0, { (1<<MACH_M32R), PIPE_S } }
 808   },
 809 /* mulhi $src1,$src2,$acc */
 810   {
 811     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
 812     { 0, { (1<<MACH_M32RX), PIPE_S } }
 813   },
 814 /* mullo $src1,$src2 */
 815   {
 816     M32R_INSN_MULLO, "mullo", "mullo", 16,
 817     { 0, { (1<<MACH_M32R), PIPE_S } }
 818   },
 819 /* mullo $src1,$src2,$acc */
 820   {
 821     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
 822     { 0, { (1<<MACH_M32RX), PIPE_S } }
 823   },
 824 /* mulwhi $src1,$src2 */
 825   {
 826     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
 827     { 0, { (1<<MACH_M32R), PIPE_S } }
 828   },
 829 /* mulwhi $src1,$src2,$acc */
 830   {
 831     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
 832     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 833   },
 834 /* mulwlo $src1,$src2 */
 835   {
 836     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
 837     { 0, { (1<<MACH_M32R), PIPE_S } }
 838   },
 839 /* mulwlo $src1,$src2,$acc */
 840   {
 841     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
 842     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
 843   },
 844 /* mv $dr,$sr */
 845   {
 846     M32R_INSN_MV, "mv", "mv", 16,
 847     { 0, { (1<<MACH_BASE), PIPE_OS } }
 848   },
 849 /* mvfachi $dr */
 850   {
 851     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
 852     { 0, { (1<<MACH_M32R), PIPE_S } }
 853   },
 854 /* mvfachi $dr,$accs */
 855   {
 856     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
 857     { 0, { (1<<MACH_M32RX), PIPE_S } }
 858   },
 859 /* mvfaclo $dr */
 860   {
 861     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
 862     { 0, { (1<<MACH_M32R), PIPE_S } }
 863   },
 864 /* mvfaclo $dr,$accs */
 865   {
 866     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
 867     { 0, { (1<<MACH_M32RX), PIPE_S } }
 868   },
 869 /* mvfacmi $dr */
 870   {
 871     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
 872     { 0, { (1<<MACH_M32R), PIPE_S } }
 873   },
 874 /* mvfacmi $dr,$accs */
 875   {
 876     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
 877     { 0, { (1<<MACH_M32RX), PIPE_S } }
 878   },
 879 /* mvfc $dr,$scr */
 880   {
 881     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
 882     { 0, { (1<<MACH_BASE), PIPE_O } }
 883   },
 884 /* mvtachi $src1 */
 885   {
 886     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
 887     { 0, { (1<<MACH_M32R), PIPE_S } }
 888   },
 889 /* mvtachi $src1,$accs */
 890   {
 891     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
 892     { 0, { (1<<MACH_M32RX), PIPE_S } }
 893   },
 894 /* mvtaclo $src1 */
 895   {
 896     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
 897     { 0, { (1<<MACH_M32R), PIPE_S } }
 898   },
 899 /* mvtaclo $src1,$accs */
 900   {
 901     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
 902     { 0, { (1<<MACH_M32RX), PIPE_S } }
 903   },
 904 /* mvtc $sr,$dcr */
 905   {
 906     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
 907     { 0, { (1<<MACH_BASE), PIPE_O } }
 908   },
 909 /* neg $dr,$sr */
 910   {
 911     M32R_INSN_NEG, "neg", "neg", 16,
 912     { 0, { (1<<MACH_BASE), PIPE_OS } }
 913   },
 914 /* nop */
 915   {
 916     M32R_INSN_NOP, "nop", "nop", 16,
 917     { 0, { (1<<MACH_BASE), PIPE_OS } }
 918   },
 919 /* not $dr,$sr */
 920   {
 921     M32R_INSN_NOT, "not", "not", 16,
 922     { 0, { (1<<MACH_BASE), PIPE_OS } }
 923   },
 924 /* rac */
 925   {
 926     M32R_INSN_RAC, "rac", "rac", 16,
 927     { 0, { (1<<MACH_M32R), PIPE_S } }
 928   },
 929 /* rac $accd,$accs,$imm1 */
 930   {
 931     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
 932     { 0, { (1<<MACH_M32RX), PIPE_S } }
 933   },
 934 /* rach */
 935   {
 936     M32R_INSN_RACH, "rach", "rach", 16,
 937     { 0, { (1<<MACH_M32R), PIPE_S } }
 938   },
 939 /* rach $accd,$accs,$imm1 */
 940   {
 941     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
 942     { 0, { (1<<MACH_M32RX), PIPE_S } }
 943   },
 944 /* rte */
 945   {
 946     M32R_INSN_RTE, "rte", "rte", 16,
 947     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
 948   },
 949 /* seth $dr,$hash$hi16 */
 950   {
 951     M32R_INSN_SETH, "seth", "seth", 32,
 952     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 953   },
 954 /* sll $dr,$sr */
 955   {
 956     M32R_INSN_SLL, "sll", "sll", 16,
 957     { 0, { (1<<MACH_BASE), PIPE_O } }
 958   },
 959 /* sll3 $dr,$sr,$simm16 */
 960   {
 961     M32R_INSN_SLL3, "sll3", "sll3", 32,
 962     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 963   },
 964 /* slli $dr,$uimm5 */
 965   {
 966     M32R_INSN_SLLI, "slli", "slli", 16,
 967     { 0, { (1<<MACH_BASE), PIPE_O } }
 968   },
 969 /* sra $dr,$sr */
 970   {
 971     M32R_INSN_SRA, "sra", "sra", 16,
 972     { 0, { (1<<MACH_BASE), PIPE_O } }
 973   },
 974 /* sra3 $dr,$sr,$simm16 */
 975   {
 976     M32R_INSN_SRA3, "sra3", "sra3", 32,
 977     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 978   },
 979 /* srai $dr,$uimm5 */
 980   {
 981     M32R_INSN_SRAI, "srai", "srai", 16,
 982     { 0, { (1<<MACH_BASE), PIPE_O } }
 983   },
 984 /* srl $dr,$sr */
 985   {
 986     M32R_INSN_SRL, "srl", "srl", 16,
 987     { 0, { (1<<MACH_BASE), PIPE_O } }
 988   },
 989 /* srl3 $dr,$sr,$simm16 */
 990   {
 991     M32R_INSN_SRL3, "srl3", "srl3", 32,
 992     { 0, { (1<<MACH_BASE), PIPE_NONE } }
 993   },
 994 /* srli $dr,$uimm5 */
 995   {
 996     M32R_INSN_SRLI, "srli", "srli", 16,
 997     { 0, { (1<<MACH_BASE), PIPE_O } }
 998   },
 999 /* st $src1,@$src2 */
1000   {
1001     M32R_INSN_ST, "st", "st", 16,
1002     { 0, { (1<<MACH_BASE), PIPE_O } }
1003   },
1004 /* st $src1,@($slo16,$src2) */
1005   {
1006     M32R_INSN_ST_D, "st-d", "st", 32,
1007     { 0, { (1<<MACH_BASE), PIPE_NONE } }
1008   },
1009 /* stb $src1,@$src2 */
1010   {
1011     M32R_INSN_STB, "stb", "stb", 16,
1012     { 0, { (1<<MACH_BASE), PIPE_O } }
1013   },
1014 /* stb $src1,@($slo16,$src2) */
1015   {
1016     M32R_INSN_STB_D, "stb-d", "stb", 32,
1017     { 0, { (1<<MACH_BASE), PIPE_NONE } }
1018   },
1019 /* sth $src1,@$src2 */
1020   {
1021     M32R_INSN_STH, "sth", "sth", 16,
1022     { 0, { (1<<MACH_BASE), PIPE_O } }
1023   },
1024 /* sth $src1,@($slo16,$src2) */
1025   {
1026     M32R_INSN_STH_D, "sth-d", "sth", 32,
1027     { 0, { (1<<MACH_BASE), PIPE_NONE } }
1028   },
1029 /* st $src1,@+$src2 */
1030   {
1031     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
1032     { 0, { (1<<MACH_BASE), PIPE_O } }
1033   },
1034 /* st $src1,@-$src2 */
1035   {
1036     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
1037     { 0, { (1<<MACH_BASE), PIPE_O } }
1038   },
1039 /* sub $dr,$sr */
1040   {
1041     M32R_INSN_SUB, "sub", "sub", 16,
1042     { 0, { (1<<MACH_BASE), PIPE_OS } }
1043   },
1044 /* subv $dr,$sr */
1045   {
1046     M32R_INSN_SUBV, "subv", "subv", 16,
1047     { 0, { (1<<MACH_BASE), PIPE_OS } }
1048   },
1049 /* subx $dr,$sr */
1050   {
1051     M32R_INSN_SUBX, "subx", "subx", 16,
1052     { 0, { (1<<MACH_BASE), PIPE_OS } }
1053   },
1054 /* trap $uimm4 */
1055   {
1056     M32R_INSN_TRAP, "trap", "trap", 16,
1057     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
1058   },
1059 /* unlock $src1,@$src2 */
1060   {
1061     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
1062     { 0, { (1<<MACH_BASE), PIPE_O } }
1063   },
1064 /* satb $dr,$sr */
1065   {
1066     M32R_INSN_SATB, "satb", "satb", 32,
1067     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1068   },
1069 /* sath $dr,$sr */
1070   {
1071     M32R_INSN_SATH, "sath", "sath", 32,
1072     { 0, { (1<<MACH_M32RX), PIPE_NONE } }
1073   },
1074 /* sat $dr,$sr */
1075   {
1076     M32R_INSN_SAT, "sat", "sat", 32,
1077     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
1078   },
1079 /* pcmpbz $src2 */
1080   {
1081     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
1082     { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
1083   },
1084 /* sadd */
1085   {
1086     M32R_INSN_SADD, "sadd", "sadd", 16,
1087     { 0, { (1<<MACH_M32RX), PIPE_S } }
1088   },
1089 /* macwu1 $src1,$src2 */
1090   {
1091     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
1092     { 0, { (1<<MACH_M32RX), PIPE_S } }
1093   },
1094 /* msblo $src1,$src2 */
1095   {
1096     M32R_INSN_MSBLO, "msblo", "msblo", 16,
1097     { 0, { (1<<MACH_M32RX), PIPE_S } }
1098   },
1099 /* mulwu1 $src1,$src2 */
1100   {
1101     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
1102     { 0, { (1<<MACH_M32RX), PIPE_S } }
1103   },
1104 /* maclh1 $src1,$src2 */
1105   {
1106     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
1107     { 0, { (1<<MACH_M32RX), PIPE_S } }
1108   },
1109 /* sc */
1110   {
1111     M32R_INSN_SC, "sc", "sc", 16,
1112     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1113   },
1114 /* snc */
1115   {
1116     M32R_INSN_SNC, "snc", "snc", 16,
1117     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
1118   },
1119 };
1120
1121 #undef OP
1122 #undef A
1123
1124 /* Initialize anything needed to be done once, before any cpu_open call.  */
1125 static void init_tables PARAMS ((void));
1126
1127 static void
1128 init_tables ()
1129 {
1130 }
1131
1132 static const CGEN_MACH * lookup_mach_via_bfd_name
1133   PARAMS ((const CGEN_MACH *, const char *));
1134 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
1135 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
1136 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1137 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
1138 static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1139
1140 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
1141
1142 static const CGEN_MACH *
1143 lookup_mach_via_bfd_name (table, name)
1144      const CGEN_MACH *table;
1145      const char *name;
1146 {
1147   while (table->name)
1148     {
1149       if (strcmp (name, table->bfd_name) == 0)
1150         return table;
1151       ++table;
1152     }
1153   abort ();
1154 }
1155
1156 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1157
1158 static void
1159 build_hw_table (cd)
1160      CGEN_CPU_TABLE *cd;
1161 {
1162   int i;
1163   int machs = cd->machs;
1164   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
1165   /* MAX_HW is only an upper bound on the number of selected entries.
1166      However each entry is indexed by it's enum so there can be holes in
1167      the table.  */
1168   const CGEN_HW_ENTRY **selected =
1169     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1170
1171   cd->hw_table.init_entries = init;
1172   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1173   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1174   /* ??? For now we just use machs to determine which ones we want.  */
1175   for (i = 0; init[i].name != NULL; ++i)
1176     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1177         & machs)
1178       selected[init[i].type] = &init[i];
1179   cd->hw_table.entries = selected;
1180   cd->hw_table.num_entries = MAX_HW;
1181 }
1182
1183 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1184
1185 static void
1186 build_ifield_table (cd)
1187      CGEN_CPU_TABLE *cd;
1188 {
1189   cd->ifld_table = & m32r_cgen_ifld_table[0];
1190 }
1191
1192 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
1193
1194 static void
1195 build_operand_table (cd)
1196      CGEN_CPU_TABLE *cd;
1197 {
1198   int i;
1199   int machs = cd->machs;
1200   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
1201   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1202      However each entry is indexed by it's enum so there can be holes in
1203      the table.  */
1204   const CGEN_OPERAND **selected =
1205     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1206
1207   cd->operand_table.init_entries = init;
1208   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1209   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1210   /* ??? For now we just use mach to determine which ones we want.  */
1211   for (i = 0; init[i].name != NULL; ++i)
1212     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1213         & machs)
1214       selected[init[i].type] = &init[i];
1215   cd->operand_table.entries = selected;
1216   cd->operand_table.num_entries = MAX_OPERANDS;
1217 }
1218
1219 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
1220    ??? This could leave out insns not supported by the specified mach/isa,
1221    but that would cause errors like "foo only supported by bar" to become
1222    "unknown insn", so for now we include all insns and require the app to
1223    do the checking later.
1224    ??? On the other hand, parsing of such insns may require their hardware or
1225    operand elements to be in the table [which they mightn't be].  */
1226
1227 static void
1228 build_insn_table (cd)
1229      CGEN_CPU_TABLE *cd;
1230 {
1231   int i;
1232   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
1233   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1234
1235   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1236   for (i = 0; i < MAX_INSNS; ++i)
1237     insns[i].base = &ib[i];
1238   cd->insn_table.init_entries = insns;
1239   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1240   cd->insn_table.num_init_entries = MAX_INSNS;
1241 }
1242
1243 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
1244
1245 static void
1246 m32r_cgen_rebuild_tables (cd)
1247      CGEN_CPU_TABLE *cd;
1248 {
1249   int i;
1250   unsigned int isas = cd->isas;
1251   unsigned int machs = cd->machs;
1252
1253   cd->int_insn_p = CGEN_INT_INSN_P;
1254
1255   /* Data derived from the isa spec.  */
1256 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1257   cd->default_insn_bitsize = UNSET;
1258   cd->base_insn_bitsize = UNSET;
1259   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1260   cd->max_insn_bitsize = 0;
1261   for (i = 0; i < MAX_ISAS; ++i)
1262     if (((1 << i) & isas) != 0)
1263       {
1264         const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
1265
1266         /* Default insn sizes of all selected isas must be
1267            equal or we set the result to 0, meaning "unknown".  */
1268         if (cd->default_insn_bitsize == UNSET)
1269           cd->default_insn_bitsize = isa->default_insn_bitsize;
1270         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1271           ; /* this is ok */
1272         else
1273           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1274
1275         /* Base insn sizes of all selected isas must be equal
1276            or we set the result to 0, meaning "unknown".  */
1277         if (cd->base_insn_bitsize == UNSET)
1278           cd->base_insn_bitsize = isa->base_insn_bitsize;
1279         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1280           ; /* this is ok */
1281         else
1282           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1283
1284         /* Set min,max insn sizes.  */
1285         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1286           cd->min_insn_bitsize = isa->min_insn_bitsize;
1287         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1288           cd->max_insn_bitsize = isa->max_insn_bitsize;
1289       }
1290
1291   /* Data derived from the mach spec.  */
1292   for (i = 0; i < MAX_MACHS; ++i)
1293     if (((1 << i) & machs) != 0)
1294       {
1295         const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
1296
1297         if (mach->insn_chunk_bitsize != 0)
1298         {
1299           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1300             {
1301               fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
1302                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1303               abort ();
1304             }
1305
1306           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1307         }
1308       }
1309
1310   /* Determine which hw elements are used by MACH.  */
1311   build_hw_table (cd);
1312
1313   /* Build the ifield table.  */
1314   build_ifield_table (cd);
1315
1316   /* Determine which operands are used by MACH/ISA.  */
1317   build_operand_table (cd);
1318
1319   /* Build the instruction table.  */
1320   build_insn_table (cd);
1321 }
1322
1323 /* Initialize a cpu table and return a descriptor.
1324    It's much like opening a file, and must be the first function called.
1325    The arguments are a set of (type/value) pairs, terminated with
1326    CGEN_CPU_OPEN_END.
1327
1328    Currently supported values:
1329    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1330    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1331    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1332    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1333    CGEN_CPU_OPEN_END:     terminates arguments
1334
1335    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1336    precluded.
1337
1338    ??? We only support ISO C stdargs here, not K&R.
1339    Laziness, plus experiment to see if anything requires K&R - eventually
1340    K&R will no longer be supported - e.g. GDB is currently trying this.  */
1341
1342 CGEN_CPU_DESC
1343 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1344 {
1345   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1346   static int init_p;
1347   unsigned int isas = 0;  /* 0 = "unspecified" */
1348   unsigned int machs = 0; /* 0 = "unspecified" */
1349   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1350   va_list ap;
1351
1352   if (! init_p)
1353     {
1354       init_tables ();
1355       init_p = 1;
1356     }
1357
1358   memset (cd, 0, sizeof (*cd));
1359
1360   va_start (ap, arg_type);
1361   while (arg_type != CGEN_CPU_OPEN_END)
1362     {
1363       switch (arg_type)
1364         {
1365         case CGEN_CPU_OPEN_ISAS :
1366           isas = va_arg (ap, unsigned int);
1367           break;
1368         case CGEN_CPU_OPEN_MACHS :
1369           machs = va_arg (ap, unsigned int);
1370           break;
1371         case CGEN_CPU_OPEN_BFDMACH :
1372           {
1373             const char *name = va_arg (ap, const char *);
1374             const CGEN_MACH *mach =
1375               lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
1376
1377             machs |= 1 << mach->num;
1378             break;
1379           }
1380         case CGEN_CPU_OPEN_ENDIAN :
1381           endian = va_arg (ap, enum cgen_endian);
1382           break;
1383         default :
1384           fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
1385                    arg_type);
1386           abort (); /* ??? return NULL? */
1387         }
1388       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1389     }
1390   va_end (ap);
1391
1392   /* mach unspecified means "all" */
1393   if (machs == 0)
1394     machs = (1 << MAX_MACHS) - 1;
1395   /* base mach is always selected */
1396   machs |= 1;
1397   /* isa unspecified means "all" */
1398   if (isas == 0)
1399     isas = (1 << MAX_ISAS) - 1;
1400   if (endian == CGEN_ENDIAN_UNKNOWN)
1401     {
1402       /* ??? If target has only one, could have a default.  */
1403       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
1404       abort ();
1405     }
1406
1407   cd->isas = isas;
1408   cd->machs = machs;
1409   cd->endian = endian;
1410   /* FIXME: for the sparc case we can determine insn-endianness statically.
1411      The worry here is where both data and insn endian can be independently
1412      chosen, in which case this function will need another argument.
1413      Actually, will want to allow for more arguments in the future anyway.  */
1414   cd->insn_endian = endian;
1415
1416   /* Table (re)builder.  */
1417   cd->rebuild_tables = m32r_cgen_rebuild_tables;
1418   m32r_cgen_rebuild_tables (cd);
1419
1420   /* Default to not allowing signed overflow.  */
1421   cd->signed_overflow_ok_p = 0;
1422
1423   return (CGEN_CPU_DESC) cd;
1424 }
1425
1426 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1427    MACH_NAME is the bfd name of the mach.  */
1428
1429 CGEN_CPU_DESC
1430 m32r_cgen_cpu_open_1 (mach_name, endian)
1431      const char *mach_name;
1432      enum cgen_endian endian;
1433 {
1434   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1435                                CGEN_CPU_OPEN_ENDIAN, endian,
1436                                CGEN_CPU_OPEN_END);
1437 }
1438
1439 /* Close a cpu table.
1440    ??? This can live in a machine independent file, but there's currently
1441    no place to put this file (there's no libcgen).  libopcodes is the wrong
1442    place as some simulator ports use this but they don't use libopcodes.  */
1443
1444 void
1445 m32r_cgen_cpu_close (cd)
1446      CGEN_CPU_DESC cd;
1447 {
1448   unsigned int i;
1449   const CGEN_INSN *insns;
1450
1451   if (cd->macro_insn_table.init_entries)
1452     {
1453       insns = cd->macro_insn_table.init_entries;
1454       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1455         {
1456           if (CGEN_INSN_RX ((insns)))
1457             regfree (CGEN_INSN_RX (insns));
1458         }
1459     }
1460
1461   if (cd->insn_table.init_entries)
1462     {
1463       insns = cd->insn_table.init_entries;
1464       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1465         {
1466           if (CGEN_INSN_RX (insns))
1467             regfree (CGEN_INSN_RX (insns));
1468         }
1469     }
1470
1471
1472
1473   if (cd->macro_insn_table.init_entries)
1474     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1475
1476   if (cd->insn_table.init_entries)
1477     free ((CGEN_INSN *) cd->insn_table.init_entries);
1478
1479   if (cd->hw_table.entries)
1480     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1481
1482   if (cd->operand_table.entries)
1483     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1484
1485   free (cd);
1486 }
1487