4 #define CGEN_PRINT_INSN my_print_insn
7 my_print_insn (pc, info, buf, buflen)
9 disassemble_info *info;
14 if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
15 return print_insn (pc, info, buf, buflen);
17 /* Print the first insn. */
20 if (print_insn (pc, info, buf, 16) == 0)
21 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
28 (*info->fprintf_func) (info->stream, " || ");
32 (*info->fprintf_func) (info->stream, " -> ");
34 /* The "& 3" is to ensure the branch address is computed correctly
35 [if it is a branch]. */
36 if (print_insn (pc & ~ (bfd_vma) 3, info, buf, 16) == 0)
37 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
39 return (pc & 3) ? 2 : 4;
44 /* Main entry point for operand extraction.
46 This function is basically just a big switch statement. Earlier versions
47 used tables to look up the function to use, but
48 - if the table contains both assembler and disassembler functions then
49 the disassembler contains much of the assembler and vice-versa,
50 - there's a lot of inlining possibilities as things grow,
51 - using a switch statement avoids the function call overhead.
53 This function could be moved into `print_insn_normal', but keeping it
54 separate makes clear the interface between `print_insn_normal' and each of
59 m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields)
62 cgen_insn_t insn_value;
69 case M32R_OPERAND_SR :
70 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
72 case M32R_OPERAND_DR :
73 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
75 case M32R_OPERAND_SRC1 :
76 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
78 case M32R_OPERAND_SRC2 :
79 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
81 case M32R_OPERAND_SCR :
82 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r2);
84 case M32R_OPERAND_DCR :
85 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 4, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_r1);
87 case M32R_OPERAND_SIMM8 :
88 length = extract_normal (NULL /*FIXME*/, insn_value, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm8);
90 case M32R_OPERAND_SIMM16 :
91 length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
93 case M32R_OPERAND_UIMM4 :
94 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 4, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm4);
96 case M32R_OPERAND_UIMM5 :
97 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 11, 5, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm5);
99 case M32R_OPERAND_UIMM16 :
100 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
102 case M32R_OPERAND_ACC_S :
103 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 12, 2, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc_s);
105 case M32R_OPERAND_ACC :
106 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 8, 1, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_acc);
108 case M32R_OPERAND_HI16 :
109 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_hi16);
111 case M32R_OPERAND_SLO16 :
112 length = extract_normal (NULL /*FIXME*/, insn_value, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_simm16);
114 case M32R_OPERAND_ULO16 :
115 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm16);
117 case M32R_OPERAND_UIMM24 :
118 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 8, 24, 0, CGEN_FIELDS_BITSIZE (fields), &fields->f_uimm24);
120 case M32R_OPERAND_DISP8 :
121 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 8, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp8);
123 case M32R_OPERAND_DISP16 :
124 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 16, 16, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp16);
126 case M32R_OPERAND_DISP24 :
127 length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 8, 24, 2, CGEN_FIELDS_BITSIZE (fields), &fields->f_disp24);
131 fprintf (stderr, "Unrecognized field %d while decoding insn.\n",
139 /* Main entry point for printing operands.
141 This function is basically just a big switch statement. Earlier versions
142 used tables to look up the function to use, but
143 - if the table contains both assembler and disassembler functions then
144 the disassembler contains much of the assembler and vice-versa,
145 - there's a lot of inlining possibilities as things grow,
146 - using a switch statement avoids the function call overhead.
148 This function could be moved into `print_insn_normal', but keeping it
149 separate makes clear the interface between `print_insn_normal' and each of
154 m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length)
156 disassemble_info *info;
164 case M32R_OPERAND_SR :
165 print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
167 case M32R_OPERAND_DR :
168 print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
170 case M32R_OPERAND_SRC1 :
171 print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
173 case M32R_OPERAND_SRC2 :
174 print_keyword (info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
176 case M32R_OPERAND_SCR :
177 print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
179 case M32R_OPERAND_DCR :
180 print_keyword (info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
182 case M32R_OPERAND_SIMM8 :
183 print_normal (info, fields->f_simm8, 0, pc, length);
185 case M32R_OPERAND_SIMM16 :
186 print_normal (info, fields->f_simm16, 0, pc, length);
188 case M32R_OPERAND_UIMM4 :
189 print_normal (info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
191 case M32R_OPERAND_UIMM5 :
192 print_normal (info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
194 case M32R_OPERAND_UIMM16 :
195 print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
197 case M32R_OPERAND_ACC_S :
198 print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc_s, 0|(1<<CGEN_OPERAND_UNSIGNED));
200 case M32R_OPERAND_ACC :
201 print_keyword (info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
203 case M32R_OPERAND_HI16 :
204 print_normal (info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
206 case M32R_OPERAND_SLO16 :
207 print_normal (info, fields->f_simm16, 0, pc, length);
209 case M32R_OPERAND_ULO16 :
210 print_normal (info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
212 case M32R_OPERAND_UIMM24 :
213 print_normal (info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
215 case M32R_OPERAND_DISP8 :
216 print_normal (info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
218 case M32R_OPERAND_DISP16 :
219 print_normal (info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
221 case M32R_OPERAND_DISP24 :
222 print_normal (info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
226 fprintf (stderr, "Unrecognized field %d while printing insn.\n",
232 cgen_extract_fn *m32r_cgen_extract_handlers[] = {
237 cgen_print_fn *m32r_cgen_print_handlers[] = {
244 m32r_cgen_init_dis (mach, endian)
246 enum cgen_endian endian;
248 m32r_cgen_init_tables (mach);
249 cgen_set_cpu (& m32r_cgen_opcode_data, mach, endian);