1 /* Instruction building/extraction support for m32r. -*- C -*-
3 THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
4 - the resultant file is machine generated, cgen-ibld.in isn't
6 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
33 #include "m32r-desc.h"
38 #define min(a,b) ((a) < (b) ? (a) : (b))
40 #define max(a,b) ((a) > (b) ? (a) : (b))
42 /* Used by the ifield rtx function. */
43 #define FLD(f) (fields->f)
45 static const char * insert_normal
46 PARAMS ((CGEN_CPU_DESC
, long, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR
));
48 static const char * insert_insn_normal
49 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*,
50 CGEN_FIELDS
*, CGEN_INSN_BYTES_PTR
, bfd_vma
));
52 static int extract_normal
53 PARAMS ((CGEN_CPU_DESC
, CGEN_EXTRACT_INFO
*, CGEN_INSN_INT
,
54 unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int, bfd_vma
, long *));
56 static int extract_insn_normal
57 PARAMS ((CGEN_CPU_DESC
, const CGEN_INSN
*, CGEN_EXTRACT_INFO
*,
58 CGEN_INSN_INT
, CGEN_FIELDS
*, bfd_vma
));
59 static void put_insn_int_value
60 PARAMS ((CGEN_CPU_DESC
, CGEN_INSN_BYTES_PTR
, int, int, CGEN_INSN_INT
));
61 const char * m32r_cgen_insert_operand
62 PARAMS ((CGEN_CPU_DESC
, int, CGEN_FIELDS
*, CGEN_INSN_BYTES_PTR
, bfd_vma
));
63 int m32r_cgen_extract_operand
64 PARAMS ((CGEN_CPU_DESC
, int, CGEN_EXTRACT_INFO
*, CGEN_INSN_INT
, CGEN_FIELDS
*, bfd_vma
));
65 int m32r_cgen_get_int_operand
66 PARAMS ((CGEN_CPU_DESC
, int, const CGEN_FIELDS
*));
67 bfd_vma m32r_cgen_get_vma_operand
68 PARAMS ((CGEN_CPU_DESC
, int, const CGEN_FIELDS
*));
69 void m32r_cgen_set_int_operand
70 PARAMS ((CGEN_CPU_DESC
, int, CGEN_FIELDS
*, int));
71 void m32r_cgen_set_vma_operand
72 PARAMS ((CGEN_CPU_DESC
, int, CGEN_FIELDS
*, bfd_vma
));
74 /* Operand insertion. */
78 /* Subroutine of insert_normal. */
80 static CGEN_INLINE
void
81 insert_1 (cd
, value
, start
, length
, word_length
, bufp
)
84 int start
,length
,word_length
;
89 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
91 x
= bfd_get_bits (bufp
, word_length
, big_p
);
93 /* Written this way to avoid undefined behaviour. */
94 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
96 shift
= (start
+ 1) - length
;
98 shift
= (word_length
- (start
+ length
));
99 x
= (x
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
101 bfd_put_bits ((bfd_vma
) x
, bufp
, word_length
, big_p
);
104 #endif /* ! CGEN_INT_INSN_P */
106 /* Default insertion routine.
108 ATTRS is a mask of the boolean attributes.
109 WORD_OFFSET is the offset in bits from the start of the insn of the value.
110 WORD_LENGTH is the length of the word in bits in which the value resides.
111 START is the starting bit number in the word, architecture origin.
112 LENGTH is the length of VALUE in bits.
113 TOTAL_LENGTH is the total length of the insn in bits.
115 The result is an error message or NULL if success. */
117 /* ??? This duplicates functionality with bfd's howto table and
118 bfd_install_relocation. */
119 /* ??? This doesn't handle bfd_vma's. Create another function when
123 insert_normal (cd
, value
, attrs
, word_offset
, start
, length
, word_length
,
124 total_length
, buffer
)
128 unsigned int word_offset
, start
, length
, word_length
, total_length
;
129 CGEN_INSN_BYTES_PTR buffer
;
131 static char errbuf
[100];
132 /* Written this way to avoid undefined behaviour. */
133 unsigned long mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
135 /* If LENGTH is zero, this operand doesn't contribute to the value. */
145 if (word_length
> 32)
148 /* For architectures with insns smaller than the base-insn-bitsize,
149 word_length may be too big. */
150 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
153 && word_length
> total_length
)
154 word_length
= total_length
;
157 /* Ensure VALUE will fit. */
158 if (CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGN_OPT
))
160 long minval
= - (1L << (length
- 1));
161 unsigned long maxval
= mask
;
163 if ((value
> 0 && (unsigned long) value
> maxval
)
166 /* xgettext:c-format */
168 _("operand out of range (%ld not between %ld and %lu)"),
169 value
, minval
, maxval
);
173 else if (! CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
))
175 unsigned long maxval
= mask
;
177 if ((unsigned long) value
> maxval
)
179 /* xgettext:c-format */
181 _("operand out of range (%lu not between 0 and %lu)"),
188 if (! cgen_signed_overflow_ok_p (cd
))
190 long minval
= - (1L << (length
- 1));
191 long maxval
= (1L << (length
- 1)) - 1;
193 if (value
< minval
|| value
> maxval
)
196 /* xgettext:c-format */
197 (errbuf
, _("operand out of range (%ld not between %ld and %ld)"),
198 value
, minval
, maxval
);
209 if (CGEN_INSN_LSB0_P
)
210 shift
= (word_offset
+ start
+ 1) - length
;
212 shift
= total_length
- (word_offset
+ start
+ length
);
213 *buffer
= (*buffer
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
216 #else /* ! CGEN_INT_INSN_P */
219 unsigned char *bufp
= (unsigned char *) buffer
+ word_offset
/ 8;
221 insert_1 (cd
, value
, start
, length
, word_length
, bufp
);
224 #endif /* ! CGEN_INT_INSN_P */
229 /* Default insn builder (insert handler).
230 The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
231 that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
232 recorded in host byte order, otherwise BUFFER is an array of bytes
233 and the value is recorded in target byte order).
234 The result is an error message or NULL if success. */
237 insert_insn_normal (cd
, insn
, fields
, buffer
, pc
)
239 const CGEN_INSN
* insn
;
240 CGEN_FIELDS
* fields
;
241 CGEN_INSN_BYTES_PTR buffer
;
244 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
246 const CGEN_SYNTAX_CHAR_TYPE
* syn
;
248 CGEN_INIT_INSERT (cd
);
249 value
= CGEN_INSN_BASE_VALUE (insn
);
251 /* If we're recording insns as numbers (rather than a string of bytes),
252 target byte order handling is deferred until later. */
256 put_insn_int_value (cd
, buffer
, cd
->base_insn_bitsize
,
257 CGEN_FIELDS_BITSIZE (fields
), value
);
261 cgen_put_insn_value (cd
, buffer
, min (cd
->base_insn_bitsize
,
262 CGEN_FIELDS_BITSIZE (fields
)),
265 #endif /* ! CGEN_INT_INSN_P */
267 /* ??? It would be better to scan the format's fields.
268 Still need to be able to insert a value based on the operand though;
269 e.g. storing a branch displacement that got resolved later.
270 Needs more thought first. */
272 for (syn
= CGEN_SYNTAX_STRING (syntax
); * syn
; ++ syn
)
276 if (CGEN_SYNTAX_CHAR_P (* syn
))
279 errmsg
= (* cd
->insert_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
288 /* Cover function to store an insn value into an integral insn. Must go here
289 because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */
292 put_insn_int_value (cd
, buf
, length
, insn_length
, value
)
293 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
294 CGEN_INSN_BYTES_PTR buf
;
299 /* For architectures with insns smaller than the base-insn-bitsize,
300 length may be too big. */
301 if (length
> insn_length
)
305 int shift
= insn_length
- length
;
306 /* Written this way to avoid undefined behaviour. */
307 CGEN_INSN_INT mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
308 *buf
= (*buf
& ~(mask
<< shift
)) | ((value
& mask
) << shift
);
312 /* Operand extraction. */
314 #if ! CGEN_INT_INSN_P
316 /* Subroutine of extract_normal.
317 Ensure sufficient bytes are cached in EX_INFO.
318 OFFSET is the offset in bytes from the start of the insn of the value.
319 BYTES is the length of the needed value.
320 Returns 1 for success, 0 for failure. */
322 static CGEN_INLINE
int
323 fill_cache (cd
, ex_info
, offset
, bytes
, pc
)
325 CGEN_EXTRACT_INFO
*ex_info
;
329 /* It's doubtful that the middle part has already been fetched so
330 we don't optimize that case. kiss. */
332 disassemble_info
*info
= (disassemble_info
*) ex_info
->dis_info
;
334 /* First do a quick check. */
335 mask
= (1 << bytes
) - 1;
336 if (((ex_info
->valid
>> offset
) & mask
) == mask
)
339 /* Search for the first byte we need to read. */
340 for (mask
= 1 << offset
; bytes
> 0; --bytes
, ++offset
, mask
<<= 1)
341 if (! (mask
& ex_info
->valid
))
349 status
= (*info
->read_memory_func
)
350 (pc
, ex_info
->insn_bytes
+ offset
, bytes
, info
);
354 (*info
->memory_error_func
) (status
, pc
, info
);
358 ex_info
->valid
|= ((1 << bytes
) - 1) << offset
;
364 /* Subroutine of extract_normal. */
366 static CGEN_INLINE
long
367 extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
)
369 CGEN_EXTRACT_INFO
*ex_info
;
370 int start
,length
,word_length
;
376 int big_p
= CGEN_CPU_INSN_ENDIAN (cd
) == CGEN_ENDIAN_BIG
;
378 x
= bfd_get_bits (bufp
, word_length
, big_p
);
380 if (CGEN_INSN_LSB0_P
)
381 shift
= (start
+ 1) - length
;
383 shift
= (word_length
- (start
+ length
));
387 #endif /* ! CGEN_INT_INSN_P */
389 /* Default extraction routine.
391 INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
392 or sometimes less for cases like the m32r where the base insn size is 32
393 but some insns are 16 bits.
394 ATTRS is a mask of the boolean attributes. We only need `SIGNED',
395 but for generality we take a bitmask of all of them.
396 WORD_OFFSET is the offset in bits from the start of the insn of the value.
397 WORD_LENGTH is the length of the word in bits in which the value resides.
398 START is the starting bit number in the word, architecture origin.
399 LENGTH is the length of VALUE in bits.
400 TOTAL_LENGTH is the total length of the insn in bits.
402 Returns 1 for success, 0 for failure. */
404 /* ??? The return code isn't properly used. wip. */
406 /* ??? This doesn't handle bfd_vma's. Create another function when
410 extract_normal (cd
, ex_info
, insn_value
, attrs
, word_offset
, start
, length
,
411 word_length
, total_length
, pc
, valuep
)
413 #if ! CGEN_INT_INSN_P
414 CGEN_EXTRACT_INFO
*ex_info
;
416 CGEN_EXTRACT_INFO
*ex_info ATTRIBUTE_UNUSED
;
418 CGEN_INSN_INT insn_value
;
420 unsigned int word_offset
, start
, length
, word_length
, total_length
;
421 #if ! CGEN_INT_INSN_P
424 bfd_vma pc ATTRIBUTE_UNUSED
;
430 /* If LENGTH is zero, this operand doesn't contribute to the value
431 so give it a standard value of zero. */
444 if (word_length
> 32)
447 /* For architectures with insns smaller than the insn-base-bitsize,
448 word_length may be too big. */
449 if (cd
->min_insn_bitsize
< cd
->base_insn_bitsize
)
452 && word_length
> total_length
)
453 word_length
= total_length
;
456 /* Does the value reside in INSN_VALUE, and at the right alignment? */
458 if (CGEN_INT_INSN_P
|| (word_offset
== 0 && word_length
== total_length
))
460 if (CGEN_INSN_LSB0_P
)
461 value
= insn_value
>> ((word_offset
+ start
+ 1) - length
);
463 value
= insn_value
>> (total_length
- ( word_offset
+ start
+ length
));
466 #if ! CGEN_INT_INSN_P
470 unsigned char *bufp
= ex_info
->insn_bytes
+ word_offset
/ 8;
472 if (word_length
> 32)
475 if (fill_cache (cd
, ex_info
, word_offset
/ 8, word_length
/ 8, pc
) == 0)
478 value
= extract_1 (cd
, ex_info
, start
, length
, word_length
, bufp
, pc
);
481 #endif /* ! CGEN_INT_INSN_P */
483 /* Written this way to avoid undefined behaviour. */
484 mask
= (((1L << (length
- 1)) - 1) << 1) | 1;
488 if (CGEN_BOOL_ATTR (attrs
, CGEN_IFLD_SIGNED
)
489 && (value
& (1L << (length
- 1))))
497 /* Default insn extractor.
499 INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
500 The extracted fields are stored in FIELDS.
501 EX_INFO is used to handle reading variable length insns.
502 Return the length of the insn in bits, or 0 if no match,
503 or -1 if an error occurs fetching data (memory_error_func will have
507 extract_insn_normal (cd
, insn
, ex_info
, insn_value
, fields
, pc
)
509 const CGEN_INSN
*insn
;
510 CGEN_EXTRACT_INFO
*ex_info
;
511 CGEN_INSN_INT insn_value
;
515 const CGEN_SYNTAX
*syntax
= CGEN_INSN_SYNTAX (insn
);
516 const CGEN_SYNTAX_CHAR_TYPE
*syn
;
518 CGEN_FIELDS_BITSIZE (fields
) = CGEN_INSN_BITSIZE (insn
);
520 CGEN_INIT_EXTRACT (cd
);
522 for (syn
= CGEN_SYNTAX_STRING (syntax
); *syn
; ++syn
)
526 if (CGEN_SYNTAX_CHAR_P (*syn
))
529 length
= (* cd
->extract_operand
) (cd
, CGEN_SYNTAX_FIELD (*syn
),
530 ex_info
, insn_value
, fields
, pc
);
535 /* We recognized and successfully extracted this insn. */
536 return CGEN_INSN_BITSIZE (insn
);
539 /* machine generated code added here */
541 /* Main entry point for operand insertion.
543 This function is basically just a big switch statement. Earlier versions
544 used tables to look up the function to use, but
545 - if the table contains both assembler and disassembler functions then
546 the disassembler contains much of the assembler and vice-versa,
547 - there's a lot of inlining possibilities as things grow,
548 - using a switch statement avoids the function call overhead.
550 This function could be moved into `parse_insn_normal', but keeping it
551 separate makes clear the interface between `parse_insn_normal' and each of
552 the handlers. It's also needed by GAS to insert operands that couldn't be
553 resolved during parsing.
557 m32r_cgen_insert_operand (cd
, opindex
, fields
, buffer
, pc
)
560 CGEN_FIELDS
* fields
;
561 CGEN_INSN_BYTES_PTR buffer
;
564 const char * errmsg
= NULL
;
565 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
569 case M32R_OPERAND_ACC
:
570 errmsg
= insert_normal (cd
, fields
->f_acc
, 0, 0, 8, 1, 32, total_length
, buffer
);
572 case M32R_OPERAND_ACCD
:
573 errmsg
= insert_normal (cd
, fields
->f_accd
, 0, 0, 4, 2, 32, total_length
, buffer
);
575 case M32R_OPERAND_ACCS
:
576 errmsg
= insert_normal (cd
, fields
->f_accs
, 0, 0, 12, 2, 32, total_length
, buffer
);
578 case M32R_OPERAND_DCR
:
579 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
581 case M32R_OPERAND_DISP16
:
583 long value
= fields
->f_disp16
;
584 value
= ((int) (((value
) - (pc
))) >> (2));
585 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, buffer
);
588 case M32R_OPERAND_DISP24
:
590 long value
= fields
->f_disp24
;
591 value
= ((int) (((value
) - (pc
))) >> (2));
592 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
595 case M32R_OPERAND_DISP8
:
597 long value
= fields
->f_disp8
;
598 value
= ((int) (((value
) - (((pc
) & (-4))))) >> (2));
599 errmsg
= insert_normal (cd
, value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, buffer
);
602 case M32R_OPERAND_DR
:
603 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
605 case M32R_OPERAND_HASH
:
607 case M32R_OPERAND_HI16
:
608 errmsg
= insert_normal (cd
, fields
->f_hi16
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, buffer
);
610 case M32R_OPERAND_IMM1
:
612 long value
= fields
->f_imm1
;
613 value
= ((value
) - (1));
614 errmsg
= insert_normal (cd
, value
, 0, 0, 15, 1, 32, total_length
, buffer
);
617 case M32R_OPERAND_SCR
:
618 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
620 case M32R_OPERAND_SIMM16
:
621 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
623 case M32R_OPERAND_SIMM8
:
624 errmsg
= insert_normal (cd
, fields
->f_simm8
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, buffer
);
626 case M32R_OPERAND_SLO16
:
627 errmsg
= insert_normal (cd
, fields
->f_simm16
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, buffer
);
629 case M32R_OPERAND_SR
:
630 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
632 case M32R_OPERAND_SRC1
:
633 errmsg
= insert_normal (cd
, fields
->f_r1
, 0, 0, 4, 4, 32, total_length
, buffer
);
635 case M32R_OPERAND_SRC2
:
636 errmsg
= insert_normal (cd
, fields
->f_r2
, 0, 0, 12, 4, 32, total_length
, buffer
);
638 case M32R_OPERAND_UIMM16
:
639 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
641 case M32R_OPERAND_UIMM24
:
642 errmsg
= insert_normal (cd
, fields
->f_uimm24
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, buffer
);
644 case M32R_OPERAND_UIMM4
:
645 errmsg
= insert_normal (cd
, fields
->f_uimm4
, 0, 0, 12, 4, 32, total_length
, buffer
);
647 case M32R_OPERAND_UIMM5
:
648 errmsg
= insert_normal (cd
, fields
->f_uimm5
, 0, 0, 11, 5, 32, total_length
, buffer
);
650 case M32R_OPERAND_ULO16
:
651 errmsg
= insert_normal (cd
, fields
->f_uimm16
, 0, 0, 16, 16, 32, total_length
, buffer
);
655 /* xgettext:c-format */
656 fprintf (stderr
, _("Unrecognized field %d while building insn.\n"),
664 /* Main entry point for operand extraction.
665 The result is <= 0 for error, >0 for success.
666 ??? Actual values aren't well defined right now.
668 This function is basically just a big switch statement. Earlier versions
669 used tables to look up the function to use, but
670 - if the table contains both assembler and disassembler functions then
671 the disassembler contains much of the assembler and vice-versa,
672 - there's a lot of inlining possibilities as things grow,
673 - using a switch statement avoids the function call overhead.
675 This function could be moved into `print_insn_normal', but keeping it
676 separate makes clear the interface between `print_insn_normal' and each of
681 m32r_cgen_extract_operand (cd
, opindex
, ex_info
, insn_value
, fields
, pc
)
684 CGEN_EXTRACT_INFO
*ex_info
;
685 CGEN_INSN_INT insn_value
;
686 CGEN_FIELDS
* fields
;
689 /* Assume success (for those operands that are nops). */
691 unsigned int total_length
= CGEN_FIELDS_BITSIZE (fields
);
695 case M32R_OPERAND_ACC
:
696 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 8, 1, 32, total_length
, pc
, & fields
->f_acc
);
698 case M32R_OPERAND_ACCD
:
699 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 2, 32, total_length
, pc
, & fields
->f_accd
);
701 case M32R_OPERAND_ACCS
:
702 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 2, 32, total_length
, pc
, & fields
->f_accs
);
704 case M32R_OPERAND_DCR
:
705 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
707 case M32R_OPERAND_DISP16
:
710 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 16, 16, 32, total_length
, pc
, & value
);
711 value
= ((((value
) << (2))) + (pc
));
712 fields
->f_disp16
= value
;
715 case M32R_OPERAND_DISP24
:
718 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 24, 32, total_length
, pc
, & value
);
719 value
= ((((value
) << (2))) + (pc
));
720 fields
->f_disp24
= value
;
723 case M32R_OPERAND_DISP8
:
726 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
)|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_PCREL_ADDR
), 0, 8, 8, 32, total_length
, pc
, & value
);
727 value
= ((((value
) << (2))) + (((pc
) & (-4))));
728 fields
->f_disp8
= value
;
731 case M32R_OPERAND_DR
:
732 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
734 case M32R_OPERAND_HASH
:
736 case M32R_OPERAND_HI16
:
737 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGN_OPT
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_hi16
);
739 case M32R_OPERAND_IMM1
:
742 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 15, 1, 32, total_length
, pc
, & value
);
743 value
= ((value
) + (1));
744 fields
->f_imm1
= value
;
747 case M32R_OPERAND_SCR
:
748 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
750 case M32R_OPERAND_SIMM16
:
751 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
753 case M32R_OPERAND_SIMM8
:
754 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 8, 8, 32, total_length
, pc
, & fields
->f_simm8
);
756 case M32R_OPERAND_SLO16
:
757 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_SIGNED
), 0, 16, 16, 32, total_length
, pc
, & fields
->f_simm16
);
759 case M32R_OPERAND_SR
:
760 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
762 case M32R_OPERAND_SRC1
:
763 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 4, 4, 32, total_length
, pc
, & fields
->f_r1
);
765 case M32R_OPERAND_SRC2
:
766 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_r2
);
768 case M32R_OPERAND_UIMM16
:
769 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
771 case M32R_OPERAND_UIMM24
:
772 length
= extract_normal (cd
, ex_info
, insn_value
, 0|(1<<CGEN_IFLD_RELOC
)|(1<<CGEN_IFLD_ABS_ADDR
), 0, 8, 24, 32, total_length
, pc
, & fields
->f_uimm24
);
774 case M32R_OPERAND_UIMM4
:
775 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 12, 4, 32, total_length
, pc
, & fields
->f_uimm4
);
777 case M32R_OPERAND_UIMM5
:
778 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 11, 5, 32, total_length
, pc
, & fields
->f_uimm5
);
780 case M32R_OPERAND_ULO16
:
781 length
= extract_normal (cd
, ex_info
, insn_value
, 0, 0, 16, 16, 32, total_length
, pc
, & fields
->f_uimm16
);
785 /* xgettext:c-format */
786 fprintf (stderr
, _("Unrecognized field %d while decoding insn.\n"),
794 cgen_insert_fn
* const m32r_cgen_insert_handlers
[] =
799 cgen_extract_fn
* const m32r_cgen_extract_handlers
[] =
804 /* Getting values from cgen_fields is handled by a collection of functions.
805 They are distinguished by the type of the VALUE argument they return.
806 TODO: floating point, inlining support, remove cases where result type
810 m32r_cgen_get_int_operand (cd
, opindex
, fields
)
811 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
813 const CGEN_FIELDS
* fields
;
819 case M32R_OPERAND_ACC
:
820 value
= fields
->f_acc
;
822 case M32R_OPERAND_ACCD
:
823 value
= fields
->f_accd
;
825 case M32R_OPERAND_ACCS
:
826 value
= fields
->f_accs
;
828 case M32R_OPERAND_DCR
:
829 value
= fields
->f_r1
;
831 case M32R_OPERAND_DISP16
:
832 value
= fields
->f_disp16
;
834 case M32R_OPERAND_DISP24
:
835 value
= fields
->f_disp24
;
837 case M32R_OPERAND_DISP8
:
838 value
= fields
->f_disp8
;
840 case M32R_OPERAND_DR
:
841 value
= fields
->f_r1
;
843 case M32R_OPERAND_HASH
:
846 case M32R_OPERAND_HI16
:
847 value
= fields
->f_hi16
;
849 case M32R_OPERAND_IMM1
:
850 value
= fields
->f_imm1
;
852 case M32R_OPERAND_SCR
:
853 value
= fields
->f_r2
;
855 case M32R_OPERAND_SIMM16
:
856 value
= fields
->f_simm16
;
858 case M32R_OPERAND_SIMM8
:
859 value
= fields
->f_simm8
;
861 case M32R_OPERAND_SLO16
:
862 value
= fields
->f_simm16
;
864 case M32R_OPERAND_SR
:
865 value
= fields
->f_r2
;
867 case M32R_OPERAND_SRC1
:
868 value
= fields
->f_r1
;
870 case M32R_OPERAND_SRC2
:
871 value
= fields
->f_r2
;
873 case M32R_OPERAND_UIMM16
:
874 value
= fields
->f_uimm16
;
876 case M32R_OPERAND_UIMM24
:
877 value
= fields
->f_uimm24
;
879 case M32R_OPERAND_UIMM4
:
880 value
= fields
->f_uimm4
;
882 case M32R_OPERAND_UIMM5
:
883 value
= fields
->f_uimm5
;
885 case M32R_OPERAND_ULO16
:
886 value
= fields
->f_uimm16
;
890 /* xgettext:c-format */
891 fprintf (stderr
, _("Unrecognized field %d while getting int operand.\n"),
900 m32r_cgen_get_vma_operand (cd
, opindex
, fields
)
901 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
903 const CGEN_FIELDS
* fields
;
909 case M32R_OPERAND_ACC
:
910 value
= fields
->f_acc
;
912 case M32R_OPERAND_ACCD
:
913 value
= fields
->f_accd
;
915 case M32R_OPERAND_ACCS
:
916 value
= fields
->f_accs
;
918 case M32R_OPERAND_DCR
:
919 value
= fields
->f_r1
;
921 case M32R_OPERAND_DISP16
:
922 value
= fields
->f_disp16
;
924 case M32R_OPERAND_DISP24
:
925 value
= fields
->f_disp24
;
927 case M32R_OPERAND_DISP8
:
928 value
= fields
->f_disp8
;
930 case M32R_OPERAND_DR
:
931 value
= fields
->f_r1
;
933 case M32R_OPERAND_HASH
:
936 case M32R_OPERAND_HI16
:
937 value
= fields
->f_hi16
;
939 case M32R_OPERAND_IMM1
:
940 value
= fields
->f_imm1
;
942 case M32R_OPERAND_SCR
:
943 value
= fields
->f_r2
;
945 case M32R_OPERAND_SIMM16
:
946 value
= fields
->f_simm16
;
948 case M32R_OPERAND_SIMM8
:
949 value
= fields
->f_simm8
;
951 case M32R_OPERAND_SLO16
:
952 value
= fields
->f_simm16
;
954 case M32R_OPERAND_SR
:
955 value
= fields
->f_r2
;
957 case M32R_OPERAND_SRC1
:
958 value
= fields
->f_r1
;
960 case M32R_OPERAND_SRC2
:
961 value
= fields
->f_r2
;
963 case M32R_OPERAND_UIMM16
:
964 value
= fields
->f_uimm16
;
966 case M32R_OPERAND_UIMM24
:
967 value
= fields
->f_uimm24
;
969 case M32R_OPERAND_UIMM4
:
970 value
= fields
->f_uimm4
;
972 case M32R_OPERAND_UIMM5
:
973 value
= fields
->f_uimm5
;
975 case M32R_OPERAND_ULO16
:
976 value
= fields
->f_uimm16
;
980 /* xgettext:c-format */
981 fprintf (stderr
, _("Unrecognized field %d while getting vma operand.\n"),
989 /* Stuffing values in cgen_fields is handled by a collection of functions.
990 They are distinguished by the type of the VALUE argument they accept.
991 TODO: floating point, inlining support, remove cases where argument type
995 m32r_cgen_set_int_operand (cd
, opindex
, fields
, value
)
996 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
998 CGEN_FIELDS
* fields
;
1003 case M32R_OPERAND_ACC
:
1004 fields
->f_acc
= value
;
1006 case M32R_OPERAND_ACCD
:
1007 fields
->f_accd
= value
;
1009 case M32R_OPERAND_ACCS
:
1010 fields
->f_accs
= value
;
1012 case M32R_OPERAND_DCR
:
1013 fields
->f_r1
= value
;
1015 case M32R_OPERAND_DISP16
:
1016 fields
->f_disp16
= value
;
1018 case M32R_OPERAND_DISP24
:
1019 fields
->f_disp24
= value
;
1021 case M32R_OPERAND_DISP8
:
1022 fields
->f_disp8
= value
;
1024 case M32R_OPERAND_DR
:
1025 fields
->f_r1
= value
;
1027 case M32R_OPERAND_HASH
:
1029 case M32R_OPERAND_HI16
:
1030 fields
->f_hi16
= value
;
1032 case M32R_OPERAND_IMM1
:
1033 fields
->f_imm1
= value
;
1035 case M32R_OPERAND_SCR
:
1036 fields
->f_r2
= value
;
1038 case M32R_OPERAND_SIMM16
:
1039 fields
->f_simm16
= value
;
1041 case M32R_OPERAND_SIMM8
:
1042 fields
->f_simm8
= value
;
1044 case M32R_OPERAND_SLO16
:
1045 fields
->f_simm16
= value
;
1047 case M32R_OPERAND_SR
:
1048 fields
->f_r2
= value
;
1050 case M32R_OPERAND_SRC1
:
1051 fields
->f_r1
= value
;
1053 case M32R_OPERAND_SRC2
:
1054 fields
->f_r2
= value
;
1056 case M32R_OPERAND_UIMM16
:
1057 fields
->f_uimm16
= value
;
1059 case M32R_OPERAND_UIMM24
:
1060 fields
->f_uimm24
= value
;
1062 case M32R_OPERAND_UIMM4
:
1063 fields
->f_uimm4
= value
;
1065 case M32R_OPERAND_UIMM5
:
1066 fields
->f_uimm5
= value
;
1068 case M32R_OPERAND_ULO16
:
1069 fields
->f_uimm16
= value
;
1073 /* xgettext:c-format */
1074 fprintf (stderr
, _("Unrecognized field %d while setting int operand.\n"),
1081 m32r_cgen_set_vma_operand (cd
, opindex
, fields
, value
)
1082 CGEN_CPU_DESC cd ATTRIBUTE_UNUSED
;
1084 CGEN_FIELDS
* fields
;
1089 case M32R_OPERAND_ACC
:
1090 fields
->f_acc
= value
;
1092 case M32R_OPERAND_ACCD
:
1093 fields
->f_accd
= value
;
1095 case M32R_OPERAND_ACCS
:
1096 fields
->f_accs
= value
;
1098 case M32R_OPERAND_DCR
:
1099 fields
->f_r1
= value
;
1101 case M32R_OPERAND_DISP16
:
1102 fields
->f_disp16
= value
;
1104 case M32R_OPERAND_DISP24
:
1105 fields
->f_disp24
= value
;
1107 case M32R_OPERAND_DISP8
:
1108 fields
->f_disp8
= value
;
1110 case M32R_OPERAND_DR
:
1111 fields
->f_r1
= value
;
1113 case M32R_OPERAND_HASH
:
1115 case M32R_OPERAND_HI16
:
1116 fields
->f_hi16
= value
;
1118 case M32R_OPERAND_IMM1
:
1119 fields
->f_imm1
= value
;
1121 case M32R_OPERAND_SCR
:
1122 fields
->f_r2
= value
;
1124 case M32R_OPERAND_SIMM16
:
1125 fields
->f_simm16
= value
;
1127 case M32R_OPERAND_SIMM8
:
1128 fields
->f_simm8
= value
;
1130 case M32R_OPERAND_SLO16
:
1131 fields
->f_simm16
= value
;
1133 case M32R_OPERAND_SR
:
1134 fields
->f_r2
= value
;
1136 case M32R_OPERAND_SRC1
:
1137 fields
->f_r1
= value
;
1139 case M32R_OPERAND_SRC2
:
1140 fields
->f_r2
= value
;
1142 case M32R_OPERAND_UIMM16
:
1143 fields
->f_uimm16
= value
;
1145 case M32R_OPERAND_UIMM24
:
1146 fields
->f_uimm24
= value
;
1148 case M32R_OPERAND_UIMM4
:
1149 fields
->f_uimm4
= value
;
1151 case M32R_OPERAND_UIMM5
:
1152 fields
->f_uimm5
= value
;
1154 case M32R_OPERAND_ULO16
:
1155 fields
->f_uimm16
= value
;
1159 /* xgettext:c-format */
1160 fprintf (stderr
, _("Unrecognized field %d while setting vma operand.\n"),
1166 /* Function to call before using the instruction builder tables. */
1169 m32r_cgen_init_ibld_table (cd
)
1172 cd
->insert_handlers
= & m32r_cgen_insert_handlers
[0];
1173 cd
->extract_handlers
= & m32r_cgen_extract_handlers
[0];
1175 cd
->insert_operand
= m32r_cgen_insert_operand
;
1176 cd
->extract_operand
= m32r_cgen_extract_operand
;
1178 cd
->get_int_operand
= m32r_cgen_get_int_operand
;
1179 cd
->set_int_operand
= m32r_cgen_set_int_operand
;
1180 cd
->get_vma_operand
= m32r_cgen_get_vma_operand
;
1181 cd
->set_vma_operand
= m32r_cgen_set_vma_operand
;