1 /* Generic opcode table support for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 This file is used to generate m32r-opc.c.
6 Copyright (C) 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
27 #include "libiberty.h"
32 /* Look up instruction INSN_VALUE and extract its fields.
33 If non-null INSN is the insn table entry.
34 Otherwise INSN_VALUE is examined to compute it.
35 LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
36 ALIAS_P is non-zero if alias insns are to be included in the search.
37 The result a pointer to the insn table entry, or NULL if the instruction
41 m32r_cgen_lookup_insn (insn
, insn_value
, length
, fields
, alias_p
)
42 const CGEN_INSN
*insn
;
43 cgen_insn_t insn_value
;
51 const CGEN_INSN_LIST
*insn_list
;
60 if (cgen_current_endian
== CGEN_ENDIAN_BIG
)
61 bfd_putb16 (insn_value
, buf
);
63 bfd_putl16 (insn_value
, buf
);
66 if (cgen_current_endian
== CGEN_ENDIAN_BIG
)
67 bfd_putb32 (insn_value
, buf
);
69 bfd_putl32 (insn_value
, buf
);
75 abort (); /* FIXME: unfinished */
78 /* The instructions are stored in hash lists.
79 Pick the first one and keep trying until we find the right one. */
81 insn_list
= CGEN_DIS_LOOKUP_INSN (buf
, insn_value
);
82 while (insn_list
!= NULL
)
84 insn
= insn_list
->insn
;
87 || ! CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
89 /* Basic bit mask must be correct. */
90 /* ??? May wish to allow target to defer this check until the
92 if ((insn_value
& CGEN_INSN_MASK (insn
)) == CGEN_INSN_VALUE (insn
))
94 length
= (*CGEN_EXTRACT_FN (insn
)) (insn
, NULL
, insn_value
, fields
);
100 insn_list
= CGEN_DIS_NEXT_INSN (insn_list
);
105 /* Sanity check: can't pass an alias insn if ! alias_p. */
107 && CGEN_INSN_ATTR (insn
, CGEN_INSN_ALIAS
))
110 length
= (*CGEN_EXTRACT_FN (insn
)) (insn
, NULL
, insn_value
, fields
);
118 /* Fill in the operand instances used by insn INSN_VALUE.
119 If non-null INS is the insn table entry.
120 Otherwise INSN_VALUE is examined to compute it.
121 LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
122 INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
124 The result a pointer to the insn table entry, or NULL if the instruction
125 wasn't recognized. */
128 m32r_cgen_get_insn_operands (insn
, insn_value
, length
, indices
)
129 const CGEN_INSN
*insn
;
130 cgen_insn_t insn_value
;
135 const CGEN_OPERAND_INSTANCE
*opinst
;
138 /* FIXME: ALIAS insns are in transition from being record in the insn table
139 to being recorded separately as macros. They don't have semantic code
140 so they can't be used here. Thus we currently always ignore the INSN
142 insn
= m32r_cgen_lookup_insn (NULL
, insn_value
, length
, &fields
, 0);
146 for (i
= 0, opinst
= CGEN_INSN_OPERANDS (insn
);
148 && CGEN_OPERAND_INSTANCE_TYPE (opinst
) != CGEN_OPERAND_INSTANCE_END
;
151 const CGEN_OPERAND
*op
= CGEN_OPERAND_INSTANCE_OPERAND (opinst
);
153 indices
[i
] = CGEN_OPERAND_INSTANCE_INDEX (opinst
);
155 indices
[i
] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op
), &fields
);
162 static const CGEN_ATTR_ENTRY MACH_attr
[] =
164 { "m32r", MACH_M32R
},
165 /* start-sanitize-m32rx */
166 { "m32rx", MACH_M32RX
},
167 /* end-sanitize-m32rx */
172 /* start-sanitize-m32rx */
173 static const CGEN_ATTR_ENTRY PIPE_attr
[] =
175 { "NONE", PIPE_NONE
},
182 /* end-sanitize-m32rx */
183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table
[] =
185 { "ABS-ADDR", NULL
},
187 { "NEGATIVE", NULL
},
189 { "PCREL-ADDR", NULL
},
192 { "SIGN-OPT", NULL
},
193 { "UNSIGNED", NULL
},
197 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table
[] =
199 { "MACH", & MACH_attr
[0] },
200 /* start-sanitize-m32rx */
201 { "PIPE", & PIPE_attr
[0] },
202 /* end-sanitize-m32rx */
204 { "COND-CTI", NULL
},
205 { "FILL-SLOT", NULL
},
206 { "PARALLEL", NULL
},
208 { "RELAXABLE", NULL
},
209 { "UNCOND-CTI", NULL
},
213 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries
[] =
236 CGEN_KEYWORD m32r_cgen_opval_h_gr
=
238 & m32r_cgen_opval_h_gr_entries
[0],
242 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries
[] =
258 CGEN_KEYWORD m32r_cgen_opval_h_cr
=
260 & m32r_cgen_opval_h_cr_entries
[0],
264 /* start-sanitize-m32rx */
265 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries
[] =
271 CGEN_KEYWORD m32r_cgen_opval_h_accums
=
273 & m32r_cgen_opval_h_accums_entries
[0],
277 /* end-sanitize-m32rx */
279 /* The hardware table. */
281 #define HW_ENT(n) m32r_cgen_hw_entries[n]
282 static const CGEN_HW_ENTRY m32r_cgen_hw_entries
[] =
284 { HW_H_PC
, & HW_ENT (HW_H_PC
+ 1), "h-pc", CGEN_ASM_KEYWORD
, (PTR
) 0 },
285 { HW_H_MEMORY
, & HW_ENT (HW_H_MEMORY
+ 1), "h-memory", CGEN_ASM_KEYWORD
, (PTR
) 0 },
286 { HW_H_SINT
, & HW_ENT (HW_H_SINT
+ 1), "h-sint", CGEN_ASM_KEYWORD
, (PTR
) 0 },
287 { HW_H_UINT
, & HW_ENT (HW_H_UINT
+ 1), "h-uint", CGEN_ASM_KEYWORD
, (PTR
) 0 },
288 { HW_H_ADDR
, & HW_ENT (HW_H_ADDR
+ 1), "h-addr", CGEN_ASM_KEYWORD
, (PTR
) 0 },
289 { HW_H_IADDR
, & HW_ENT (HW_H_IADDR
+ 1), "h-iaddr", CGEN_ASM_KEYWORD
, (PTR
) 0 },
290 { HW_H_HI16
, & HW_ENT (HW_H_HI16
+ 1), "h-hi16", CGEN_ASM_KEYWORD
, (PTR
) 0 },
291 { HW_H_SLO16
, & HW_ENT (HW_H_SLO16
+ 1), "h-slo16", CGEN_ASM_KEYWORD
, (PTR
) 0 },
292 { HW_H_ULO16
, & HW_ENT (HW_H_ULO16
+ 1), "h-ulo16", CGEN_ASM_KEYWORD
, (PTR
) 0 },
293 { HW_H_GR
, & HW_ENT (HW_H_GR
+ 1), "h-gr", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_gr
},
294 { HW_H_CR
, & HW_ENT (HW_H_CR
+ 1), "h-cr", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_cr
},
295 { HW_H_ACCUM
, & HW_ENT (HW_H_ACCUM
+ 1), "h-accum", CGEN_ASM_KEYWORD
, (PTR
) 0 },
296 /* start-sanitize-m32rx */
297 { HW_H_ACCUMS
, & HW_ENT (HW_H_ACCUMS
+ 1), "h-accums", CGEN_ASM_KEYWORD
, (PTR
) & m32r_cgen_opval_h_accums
},
298 /* end-sanitize-m32rx */
299 /* start-sanitize-m32rx */
300 { HW_H_ABORT
, & HW_ENT (HW_H_ABORT
+ 1), "h-abort", CGEN_ASM_KEYWORD
, (PTR
) 0 },
301 /* end-sanitize-m32rx */
302 { HW_H_COND
, & HW_ENT (HW_H_COND
+ 1), "h-cond", CGEN_ASM_KEYWORD
, (PTR
) 0 },
303 { HW_H_SM
, & HW_ENT (HW_H_SM
+ 1), "h-sm", CGEN_ASM_KEYWORD
, (PTR
) 0 },
304 { HW_H_BSM
, & HW_ENT (HW_H_BSM
+ 1), "h-bsm", CGEN_ASM_KEYWORD
, (PTR
) 0 },
305 { HW_H_IE
, & HW_ENT (HW_H_IE
+ 1), "h-ie", CGEN_ASM_KEYWORD
, (PTR
) 0 },
306 { HW_H_BIE
, & HW_ENT (HW_H_BIE
+ 1), "h-bie", CGEN_ASM_KEYWORD
, (PTR
) 0 },
307 { HW_H_BCOND
, & HW_ENT (HW_H_BCOND
+ 1), "h-bcond", CGEN_ASM_KEYWORD
, (PTR
) 0 },
308 { HW_H_BPC
, & HW_ENT (HW_H_BPC
+ 1), "h-bpc", CGEN_ASM_KEYWORD
, (PTR
) 0 },
309 { HW_H_LOCK
, & HW_ENT (HW_H_LOCK
+ 1), "h-lock", CGEN_ASM_KEYWORD
, (PTR
) 0 },
313 /* The operand table. */
315 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
316 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
317 const CGEN_OPERAND m32r_cgen_operand_table
[MAX_OPERANDS
] =
319 /* pc: program counter */
320 { "pc", & HW_ENT (HW_H_PC
), 0, 0,
321 { 0, 0|(1<<CGEN_OPERAND_FAKE
)|(1<<CGEN_OPERAND_PC
), { 0 } } },
322 /* sr: source register */
323 { "sr", & HW_ENT (HW_H_GR
), 12, 4,
324 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
325 /* dr: destination register */
326 { "dr", & HW_ENT (HW_H_GR
), 4, 4,
327 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
328 /* src1: source register 1 */
329 { "src1", & HW_ENT (HW_H_GR
), 4, 4,
330 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
331 /* src2: source register 2 */
332 { "src2", & HW_ENT (HW_H_GR
), 12, 4,
333 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
334 /* scr: source control register */
335 { "scr", & HW_ENT (HW_H_CR
), 12, 4,
336 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
337 /* dcr: destination control register */
338 { "dcr", & HW_ENT (HW_H_CR
), 4, 4,
339 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
340 /* simm8: 8 bit signed immediate */
341 { "simm8", & HW_ENT (HW_H_SINT
), 8, 8,
343 /* simm16: 16 bit signed immediate */
344 { "simm16", & HW_ENT (HW_H_SINT
), 16, 16,
346 /* uimm4: 4 bit trap number */
347 { "uimm4", & HW_ENT (HW_H_UINT
), 12, 4,
348 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
349 /* uimm5: 5 bit shift count */
350 { "uimm5", & HW_ENT (HW_H_UINT
), 11, 5,
351 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
352 /* uimm16: 16 bit unsigned immediate */
353 { "uimm16", & HW_ENT (HW_H_UINT
), 16, 16,
354 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
355 /* start-sanitize-m32rx */
356 /* imm1: 1 bit immediate */
357 { "imm1", & HW_ENT (HW_H_UINT
), 15, 1,
358 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
359 /* end-sanitize-m32rx */
360 /* start-sanitize-m32rx */
361 /* accd: accumulator destination register */
362 { "accd", & HW_ENT (HW_H_ACCUMS
), 4, 2,
363 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
364 /* end-sanitize-m32rx */
365 /* start-sanitize-m32rx */
366 /* accs: accumulator source register */
367 { "accs", & HW_ENT (HW_H_ACCUMS
), 12, 2,
368 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
369 /* end-sanitize-m32rx */
370 /* start-sanitize-m32rx */
371 /* acc: accumulator reg (d) */
372 { "acc", & HW_ENT (HW_H_ACCUMS
), 8, 1,
373 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
374 /* end-sanitize-m32rx */
375 /* hi16: high 16 bit immediate, sign optional */
376 { "hi16", & HW_ENT (HW_H_HI16
), 16, 16,
377 { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
378 /* slo16: 16 bit signed immediate, for low() */
379 { "slo16", & HW_ENT (HW_H_SLO16
), 16, 16,
381 /* ulo16: 16 bit unsigned immediate, for low() */
382 { "ulo16", & HW_ENT (HW_H_ULO16
), 16, 16,
383 { 0, 0|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
384 /* uimm24: 24 bit address */
385 { "uimm24", & HW_ENT (HW_H_ADDR
), 8, 24,
386 { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_ABS_ADDR
)|(1<<CGEN_OPERAND_UNSIGNED
), { 0 } } },
387 /* disp8: 8 bit displacement */
388 { "disp8", & HW_ENT (HW_H_IADDR
), 8, 8,
389 { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
390 /* disp16: 16 bit displacement */
391 { "disp16", & HW_ENT (HW_H_IADDR
), 16, 16,
392 { 0, 0|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
393 /* disp24: 24 bit displacement */
394 { "disp24", & HW_ENT (HW_H_IADDR
), 8, 24,
395 { 0, 0|(1<<CGEN_OPERAND_RELAX
)|(1<<CGEN_OPERAND_RELOC
)|(1<<CGEN_OPERAND_PCREL_ADDR
), { 0 } } },
396 /* condbit: condition bit */
397 { "condbit", & HW_ENT (HW_H_COND
), 0, 0,
398 { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
399 /* accum: accumulator */
400 { "accum", & HW_ENT (HW_H_ACCUM
), 0, 0,
401 { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
402 /* start-sanitize-m32rx */
403 /* abort-parallel-execution: abort parallel execution */
404 { "abort-parallel-execution", & HW_ENT (HW_H_ABORT
), 0, 0,
405 { 0, 0|(1<<CGEN_OPERAND_FAKE
), { 0 } } },
406 /* end-sanitize-m32rx */
409 /* Operand references. */
411 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
412 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
414 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops
[] = {
415 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
416 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
417 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
421 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops
[] = {
422 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
423 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
424 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
428 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops
[] = {
429 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
430 { INPUT
, & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM16
), 0 },
431 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
435 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops
[] = {
436 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
437 { INPUT
, & HW_ENT (HW_H_ULO16
), CGEN_MODE_UHI
, & OP_ENT (ULO16
), 0 },
438 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
442 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops
[] = {
443 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
444 { INPUT
, & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM8
), 0 },
445 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
449 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops
[] = {
450 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
451 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
452 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
453 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
457 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops
[] = {
458 { INPUT
, & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
459 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
460 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
461 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
465 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops
[] = {
466 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
467 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
468 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
469 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
470 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
474 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops
[] = {
475 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
476 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP8
), 0 },
477 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
481 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops
[] = {
482 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
483 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP24
), 0 },
484 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
488 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops
[] = {
489 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP16
), 0 },
490 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
491 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
492 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
496 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops
[] = {
497 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP16
), 0 },
498 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
499 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
503 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops
[] = {
504 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP8
), 0 },
505 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
506 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
507 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
511 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops
[] = {
512 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP24
), 0 },
513 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
514 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
515 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
519 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops
[] = {
520 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
521 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP8
), 0 },
522 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
523 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
524 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
528 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops
[] = {
529 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
530 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP24
), 0 },
531 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
532 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
533 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
537 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops
[] = {
538 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP8
), 0 },
539 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
543 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops
[] = {
544 { INPUT
, & HW_ENT (HW_H_IADDR
), CGEN_MODE_VM
, & OP_ENT (DISP24
), 0 },
545 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
549 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops
[] = {
550 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
551 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
552 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
556 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops
[] = {
557 { INPUT
, & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
558 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
559 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
563 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops
[] = {
564 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
565 { INPUT
, & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM16
), 0 },
566 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
570 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops
[] = {
571 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
572 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
576 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops
[] = {
577 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
578 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
579 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
583 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops
[] = {
584 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
585 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
586 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
590 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops
[] = {
591 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
592 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
593 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
594 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, 0, 14 },
598 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops
[] = {
599 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
600 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
604 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops
[] = {
605 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
606 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
607 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
611 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops
[] = {
612 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
613 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
614 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
615 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
619 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops
[] = {
620 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
621 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
622 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
626 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops
[] = {
627 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
628 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
629 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
630 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
634 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops
[] = {
635 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
636 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
637 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
641 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops
[] = {
642 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
643 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
644 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
645 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
649 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops
[] = {
650 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
651 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
652 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
653 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
657 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops
[] = {
658 { INPUT
, & HW_ENT (HW_H_ADDR
), CGEN_MODE_VM
, & OP_ENT (UIMM24
), 0 },
659 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
663 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops
[] = {
664 { INPUT
, & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM8
), 0 },
665 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
669 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops
[] = {
670 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
671 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
675 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops
[] = {
676 { INPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
677 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
678 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
679 { OUTPUT
, & HW_ENT (HW_H_LOCK
), CGEN_MODE_UBI
, 0, 0 },
683 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops
[] = {
684 { INPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
685 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
686 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
687 { OUTPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
691 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops
[] = {
692 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
693 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
694 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
695 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
699 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops
[] = {
700 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
701 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
702 { OUTPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
706 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops
[] = {
707 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
708 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
709 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACC
), 0 },
713 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops
[] = {
714 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
715 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
719 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops
[] = {
720 { INPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
721 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
725 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops
[] = {
726 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
727 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
731 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops
[] = {
732 { INPUT
, & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, & OP_ENT (SCR
), 0 },
733 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
737 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops
[] = {
738 { INPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
739 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
740 { OUTPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
744 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops
[] = {
745 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
746 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
747 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
751 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops
[] = {
752 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
753 { OUTPUT
, & HW_ENT (HW_H_CR
), CGEN_MODE_USI
, & OP_ENT (DCR
), 0 },
757 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops
[] = {
758 { INPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
759 { OUTPUT
, & HW_ENT (HW_H_ACCUM
), CGEN_MODE_DI
, 0, 0 },
763 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops
[] = {
764 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCS
), 0 },
765 { INPUT
, & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (IMM1
), 0 },
766 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, & OP_ENT (ACCD
), 0 },
770 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops
[] = {
771 { INPUT
, & HW_ENT (HW_H_BCOND
), CGEN_MODE_VM
, 0, 0 },
772 { INPUT
, & HW_ENT (HW_H_BIE
), CGEN_MODE_VM
, 0, 0 },
773 { INPUT
, & HW_ENT (HW_H_BPC
), CGEN_MODE_VM
, 0, 0 },
774 { INPUT
, & HW_ENT (HW_H_BSM
), CGEN_MODE_VM
, 0, 0 },
775 { OUTPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
776 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
777 { OUTPUT
, & HW_ENT (HW_H_IE
), CGEN_MODE_VM
, 0, 0 },
778 { OUTPUT
, & HW_ENT (HW_H_SM
), CGEN_MODE_VM
, 0, 0 },
782 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops
[] = {
783 { INPUT
, & HW_ENT (HW_H_HI16
), CGEN_MODE_UHI
, & OP_ENT (HI16
), 0 },
784 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
788 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops
[] = {
789 { INPUT
, & HW_ENT (HW_H_SINT
), CGEN_MODE_SI
, & OP_ENT (SIMM16
), 0 },
790 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
791 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
795 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops
[] = {
796 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
797 { INPUT
, & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM5
), 0 },
798 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
802 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops
[] = {
803 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
804 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
805 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
809 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops
[] = {
810 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
811 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
812 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
813 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
817 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops
[] = {
818 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
819 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
820 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
824 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops
[] = {
825 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
826 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
827 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
828 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_QI
, 0, 0 },
832 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops
[] = {
833 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
834 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
835 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
839 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops
[] = {
840 { INPUT
, & HW_ENT (HW_H_SLO16
), CGEN_MODE_HI
, & OP_ENT (SLO16
), 0 },
841 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
842 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
843 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_HI
, 0, 0 },
847 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops
[] = {
848 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
849 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
850 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
851 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
855 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops
[] = {
856 { INPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
857 { INPUT
, & HW_ENT (HW_H_CR
), CGEN_MODE_SI
, 0, 0 },
858 { INPUT
, & HW_ENT (HW_H_UINT
), CGEN_MODE_USI
, & OP_ENT (UIMM4
), 0 },
859 { OUTPUT
, & HW_ENT (HW_H_PC
), CGEN_MODE_USI
, 0, 0 },
860 { OUTPUT
, & HW_ENT (HW_H_CR
), CGEN_MODE_SI
, 0, 0 },
861 { OUTPUT
, & HW_ENT (HW_H_CR
), CGEN_MODE_SI
, 0, 6 },
865 static const CGEN_OPERAND_INSTANCE fmt_72_unlock_ops
[] = {
866 { INPUT
, & HW_ENT (HW_H_LOCK
), CGEN_MODE_UBI
, 0, 0 },
867 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
868 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
869 { OUTPUT
, & HW_ENT (HW_H_MEMORY
), CGEN_MODE_SI
, 0, 0 },
870 { OUTPUT
, & HW_ENT (HW_H_LOCK
), CGEN_MODE_UBI
, 0, 0 },
874 static const CGEN_OPERAND_INSTANCE fmt_75_satb_ops
[] = {
875 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
876 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
880 static const CGEN_OPERAND_INSTANCE fmt_76_sat_ops
[] = {
881 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
882 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SR
), 0 },
883 { OUTPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (DR
), 0 },
887 static const CGEN_OPERAND_INSTANCE fmt_77_sadd_ops
[] = {
888 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 0 },
889 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
890 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 0 },
894 static const CGEN_OPERAND_INSTANCE fmt_78_macwu1_ops
[] = {
895 { INPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
896 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
897 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
898 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
902 static const CGEN_OPERAND_INSTANCE fmt_79_mulwu1_ops
[] = {
903 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC1
), 0 },
904 { INPUT
, & HW_ENT (HW_H_GR
), CGEN_MODE_SI
, & OP_ENT (SRC2
), 0 },
905 { OUTPUT
, & HW_ENT (HW_H_ACCUMS
), CGEN_MODE_DI
, 0, 1 },
909 static const CGEN_OPERAND_INSTANCE fmt_80_sc_ops
[] = {
910 { INPUT
, & HW_ENT (HW_H_COND
), CGEN_MODE_UBI
, 0, 0 },
911 { OUTPUT
, & HW_ENT (HW_H_ABORT
), CGEN_MODE_UBI
, 0, 0 },
918 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
919 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
921 static const CGEN_SYNTAX syntax_table
[] =
924 /* 0 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), 0 },
925 /* <mnem> $dr,$sr,#$slo16 */
926 /* 1 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', '#', OP (SLO16
), 0 },
927 /* <mnem> $dr,$sr,$slo16 */
928 /* 2 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SLO16
), 0 },
929 /* <mnem> $dr,$sr,#$uimm16 */
930 /* 3 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', '#', OP (UIMM16
), 0 },
931 /* <mnem> $dr,$sr,$uimm16 */
932 /* 4 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (UIMM16
), 0 },
933 /* <mnem> $dr,$sr,#$ulo16 */
934 /* 5 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', '#', OP (ULO16
), 0 },
935 /* <mnem> $dr,$sr,$ulo16 */
936 /* 6 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (ULO16
), 0 },
937 /* <mnem> $dr,#$simm8 */
938 /* 7 */ { MNEM
, ' ', OP (DR
), ',', '#', OP (SIMM8
), 0 },
939 /* <mnem> $dr,$simm8 */
940 /* 8 */ { MNEM
, ' ', OP (DR
), ',', OP (SIMM8
), 0 },
941 /* <mnem> $dr,$sr,#$simm16 */
942 /* 9 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', '#', OP (SIMM16
), 0 },
943 /* <mnem> $dr,$sr,$simm16 */
944 /* 10 */ { MNEM
, ' ', OP (DR
), ',', OP (SR
), ',', OP (SIMM16
), 0 },
946 /* 11 */ { MNEM
, ' ', OP (DISP8
), 0 },
948 /* 12 */ { MNEM
, ' ', OP (DISP24
), 0 },
949 /* <mnem> $src1,$src2,$disp16 */
950 /* 13 */ { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (DISP16
), 0 },
951 /* <mnem> $src2,$disp16 */
952 /* 14 */ { MNEM
, ' ', OP (SRC2
), ',', OP (DISP16
), 0 },
953 /* <mnem> $src1,$src2 */
954 /* 15 */ { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), 0 },
955 /* <mnem> $src2,#$simm16 */
956 /* 16 */ { MNEM
, ' ', OP (SRC2
), ',', '#', OP (SIMM16
), 0 },
957 /* <mnem> $src2,$simm16 */
958 /* 17 */ { MNEM
, ' ', OP (SRC2
), ',', OP (SIMM16
), 0 },
959 /* <mnem> $src2,#$uimm16 */
960 /* 18 */ { MNEM
, ' ', OP (SRC2
), ',', '#', OP (UIMM16
), 0 },
961 /* <mnem> $src2,$uimm16 */
962 /* 19 */ { MNEM
, ' ', OP (SRC2
), ',', OP (UIMM16
), 0 },
964 /* 20 */ { MNEM
, ' ', OP (SRC2
), 0 },
966 /* 21 */ { MNEM
, ' ', OP (SR
), 0 },
967 /* <mnem> $dr,@$sr */
968 /* 22 */ { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), 0 },
969 /* <mnem> $dr,@($sr) */
970 /* 23 */ { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ')', 0 },
971 /* <mnem> $dr,@($slo16,$sr) */
972 /* 24 */ { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SLO16
), ',', OP (SR
), ')', 0 },
973 /* <mnem> $dr,@($sr,$slo16) */
974 /* 25 */ { MNEM
, ' ', OP (DR
), ',', '@', '(', OP (SR
), ',', OP (SLO16
), ')', 0 },
975 /* <mnem> $dr,@$sr+ */
976 /* 26 */ { MNEM
, ' ', OP (DR
), ',', '@', OP (SR
), '+', 0 },
977 /* <mnem> $dr,#$uimm24 */
978 /* 27 */ { MNEM
, ' ', OP (DR
), ',', '#', OP (UIMM24
), 0 },
979 /* <mnem> $dr,$uimm24 */
980 /* 28 */ { MNEM
, ' ', OP (DR
), ',', OP (UIMM24
), 0 },
981 /* <mnem> $dr,$slo16 */
982 /* 29 */ { MNEM
, ' ', OP (DR
), ',', OP (SLO16
), 0 },
983 /* <mnem> $src1,$src2,$acc */
984 /* 30 */ { MNEM
, ' ', OP (SRC1
), ',', OP (SRC2
), ',', OP (ACC
), 0 },
986 /* 31 */ { MNEM
, ' ', OP (DR
), 0 },
987 /* <mnem> $dr,$accs */
988 /* 32 */ { MNEM
, ' ', OP (DR
), ',', OP (ACCS
), 0 },
989 /* <mnem> $dr,$scr */
990 /* 33 */ { MNEM
, ' ', OP (DR
), ',', OP (SCR
), 0 },
992 /* 34 */ { MNEM
, ' ', OP (SRC1
), 0 },
993 /* <mnem> $src1,$accs */
994 /* 35 */ { MNEM
, ' ', OP (SRC1
), ',', OP (ACCS
), 0 },
995 /* <mnem> $sr,$dcr */
996 /* 36 */ { MNEM
, ' ', OP (SR
), ',', OP (DCR
), 0 },
998 /* 37 */ { MNEM
, 0 },
1000 /* 38 */ { MNEM
, ' ', OP (ACCD
), 0 },
1001 /* <mnem> $accd,$accs */
1002 /* 39 */ { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), 0 },
1003 /* <mnem> $accd,$accs,#$imm1 */
1004 /* 40 */ { MNEM
, ' ', OP (ACCD
), ',', OP (ACCS
), ',', '#', OP (IMM1
), 0 },
1005 /* <mnem> $dr,#$hi16 */
1006 /* 41 */ { MNEM
, ' ', OP (DR
), ',', '#', OP (HI16
), 0 },
1007 /* <mnem> $dr,$hi16 */
1008 /* 42 */ { MNEM
, ' ', OP (DR
), ',', OP (HI16
), 0 },
1009 /* <mnem> $dr,#$uimm5 */
1010 /* 43 */ { MNEM
, ' ', OP (DR
), ',', '#', OP (UIMM5
), 0 },
1011 /* <mnem> $dr,$uimm5 */
1012 /* 44 */ { MNEM
, ' ', OP (DR
), ',', OP (UIMM5
), 0 },
1013 /* <mnem> $src1,@$src2 */
1014 /* 45 */ { MNEM
, ' ', OP (SRC1
), ',', '@', OP (SRC2
), 0 },
1015 /* <mnem> $src1,@($src2) */
1016 /* 46 */ { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ')', 0 },
1017 /* <mnem> $src1,@($slo16,$src2) */
1018 /* 47 */ { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SLO16
), ',', OP (SRC2
), ')', 0 },
1019 /* <mnem> $src1,@($src2,$slo16) */
1020 /* 48 */ { MNEM
, ' ', OP (SRC1
), ',', '@', '(', OP (SRC2
), ',', OP (SLO16
), ')', 0 },
1021 /* <mnem> $src1,@+$src2 */
1022 /* 49 */ { MNEM
, ' ', OP (SRC1
), ',', '@', '+', OP (SRC2
), 0 },
1023 /* <mnem> $src1,@-$src2 */
1024 /* 50 */ { MNEM
, ' ', OP (SRC1
), ',', '@', '-', OP (SRC2
), 0 },
1025 /* <mnem> #$uimm4 */
1026 /* 51 */ { MNEM
, ' ', '#', OP (UIMM4
), 0 },
1028 /* 52 */ { MNEM
, ' ', OP (UIMM4
), 0 },
1034 static const CGEN_FORMAT format_table
[] =
1036 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */
1037 /* 0 */ { 16, 16, 0xf0f0 },
1038 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */
1039 /* 1 */ { 32, 32, 0xf0f00000 },
1040 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */
1041 /* 2 */ { 32, 32, 0xf0f00000 },
1042 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */
1043 /* 3 */ { 32, 32, 0xf0f00000 },
1044 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */
1045 /* 4 */ { 16, 16, 0xf000 },
1046 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1047 /* 5 */ { 16, 16, 0xf0f0 },
1048 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */
1049 /* 6 */ { 32, 32, 0xf0f00000 },
1050 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */
1051 /* 7 */ { 16, 16, 0xf0f0 },
1052 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI) */
1053 /* 8 */ { 16, 16, 0xff00 },
1054 /* (f-op1 #)(f-r1 #)(f-disp8 disp8) */
1055 /* 9 */ { 16, 16, 0xff00 },
1056 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI) */
1057 /* 10 */ { 32, 32, 0xff000000 },
1058 /* (f-op1 #)(f-r1 #)(f-disp24 disp24) */
1059 /* 11 */ { 32, 32, 0xff000000 },
1060 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI)(pc USI) */
1061 /* 12 */ { 32, 32, 0xf0f00000 },
1062 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI)(pc USI) */
1063 /* 13 */ { 32, 32, 0xfff00000 },
1064 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1065 /* 14 */ { 16, 16, 0xff00 },
1066 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1067 /* 15 */ { 32, 32, 0xff000000 },
1068 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1069 /* 16 */ { 16, 16, 0xff00 },
1070 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */
1071 /* 17 */ { 32, 32, 0xff000000 },
1072 /* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI) */
1073 /* 18 */ { 16, 16, 0xff00 },
1074 /* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI) */
1075 /* 19 */ { 32, 32, 0xff000000 },
1076 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */
1077 /* 20 */ { 16, 16, 0xf0f0 },
1078 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */
1079 /* 21 */ { 32, 32, 0xfff00000 },
1080 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */
1081 /* 22 */ { 32, 32, 0xfff00000 },
1082 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */
1083 /* 23 */ { 16, 16, 0xfff0 },
1084 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */
1085 /* 24 */ { 32, 32, 0xf0f0ffff },
1086 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI)(pc USI) */
1087 /* 25 */ { 16, 16, 0xfff0 },
1088 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(pc USI)(h-gr-14 SI) */
1089 /* 26 */ { 16, 16, 0xfff0 },
1090 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI)(pc USI) */
1091 /* 27 */ { 16, 16, 0xfff0 },
1092 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */
1093 /* 28 */ { 16, 16, 0xf0f0 },
1094 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */
1095 /* 29 */ { 16, 16, 0xf0f0 },
1096 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */
1097 /* 30 */ { 32, 32, 0xf0f00000 },
1098 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */
1099 /* 31 */ { 32, 32, 0xf0f00000 },
1100 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */
1101 /* 32 */ { 16, 16, 0xf0f0 },
1102 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */
1103 /* 33 */ { 32, 32, 0xf0f00000 },
1104 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */
1105 /* 34 */ { 16, 16, 0xf0f0 },
1106 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */
1107 /* 35 */ { 32, 32, 0xf0f00000 },
1108 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */
1109 /* 36 */ { 16, 16, 0xf0f0 },
1110 /* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */
1111 /* 37 */ { 32, 32, 0xf0000000 },
1112 /* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */
1113 /* 38 */ { 16, 16, 0xf000 },
1114 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */
1115 /* 39 */ { 32, 32, 0xf0ff0000 },
1116 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(h-lock-0 UBI) */
1117 /* 40 */ { 16, 16, 0xf0f0 },
1118 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */
1119 /* 41 */ { 16, 16, 0xf0f0 },
1120 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */
1121 /* 42 */ { 16, 16, 0xf070 },
1122 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */
1123 /* 43 */ { 16, 16, 0xf0f0 },
1124 /* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */
1125 /* 44 */ { 16, 16, 0xf070 },
1126 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */
1127 /* 45 */ { 16, 16, 0xf0f0 },
1128 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */
1129 /* 46 */ { 16, 16, 0xf0ff },
1130 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */
1131 /* 47 */ { 16, 16, 0xf0f3 },
1132 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr USI)(dr SI) */
1133 /* 48 */ { 16, 16, 0xf0f0 },
1134 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */
1135 /* 49 */ { 16, 16, 0xf0ff },
1136 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */
1137 /* 50 */ { 16, 16, 0xf0f3 },
1138 /* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr USI) */
1139 /* 51 */ { 16, 16, 0xf0f0 },
1140 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */
1141 /* 52 */ { 16, 16, 0xffff },
1142 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */
1143 /* 53 */ { 16, 16, 0xffff },
1144 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #) */
1145 /* 54 */ { 16, 16, 0xf3ff },
1146 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #) */
1147 /* 55 */ { 16, 16, 0xf3f3 },
1148 /* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */
1149 /* 56 */ { 16, 16, 0xf3f2 },
1150 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */
1151 /* 57 */ { 16, 16, 0xffff },
1152 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */
1153 /* 58 */ { 32, 32, 0xf0ff0000 },
1154 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */
1155 /* 59 */ { 32, 32, 0xf0f00000 },
1156 /* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */
1157 /* 60 */ { 16, 16, 0xf0e0 },
1158 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */
1159 /* 61 */ { 16, 16, 0xf0f0 },
1160 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */
1161 /* 62 */ { 16, 16, 0xf0f0 },
1162 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */
1163 /* 63 */ { 32, 32, 0xf0f00000 },
1164 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */
1165 /* 64 */ { 32, 32, 0xf0f00000 },
1166 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */
1167 /* 65 */ { 16, 16, 0xf0f0 },
1168 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */
1169 /* 66 */ { 32, 32, 0xf0f00000 },
1170 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */
1171 /* 67 */ { 16, 16, 0xf0f0 },
1172 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */
1173 /* 68 */ { 32, 32, 0xf0f00000 },
1174 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */
1175 /* 69 */ { 16, 16, 0xf0f0 },
1176 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(pc USI)(h-cr-0 SI)(uimm4 USI)(pc USI)(h-cr-0 SI)(h-cr-6 SI) */
1177 /* 70 */ { 16, 16, 0xfff0 },
1178 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4) */
1179 /* 71 */ { 16, 16, 0xfff0 },
1180 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-lock-0 UBI)(src1 SI)(src2 SI)(h-memory-src2 SI)(h-lock-0 UBI) */
1181 /* 72 */ { 16, 16, 0xf0f0 },
1182 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */
1183 /* 73 */ { 16, 16, 0xf0ff },
1184 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */
1185 /* 74 */ { 16, 16, 0xf0ff },
1186 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */
1187 /* 75 */ { 32, 32, 0xf0f0ffff },
1188 /* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */
1189 /* 76 */ { 32, 32, 0xf0f0ffff },
1190 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */
1191 /* 77 */ { 16, 16, 0xffff },
1192 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */
1193 /* 78 */ { 16, 16, 0xf0f0 },
1194 /* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */
1195 /* 79 */ { 16, 16, 0xf0f0 },
1196 /* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */
1197 /* 80 */ { 16, 16, 0xffff },
1200 #define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a))
1201 #define SYN(n) (& syntax_table[n])
1202 #define FMT(n) (& format_table[n])
1204 /* The instruction table. */
1206 const CGEN_INSN m32r_cgen_insn_table_entries
[MAX_INSNS
] =
1208 /* null first entry, end of all hash chains */
1213 "add", "add", SYN (0), FMT (0), 0xa0,
1215 { CGEN_INSN_NBOOL_ATTRS
, 0|A(PARALLEL
), { (1<<MACH_M32R
), PIPE_OS
} }
1217 /* add3 $dr,$sr,#$slo16 */
1220 "add3", "add3", SYN (1), FMT (1), 0x80a00000,
1221 & fmt_1_add3_ops
[0],
1222 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1224 /* add3 $dr,$sr,$slo16 */
1227 "add3.a", "add3", SYN (2), FMT (1), 0x80a00000,
1228 & fmt_1_add3_ops
[0],
1229 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1234 "and", "and", SYN (0), FMT (0), 0xc0,
1236 { CGEN_INSN_NBOOL_ATTRS
, 0|A(PARALLEL
), { (1<<MACH_M32R
), PIPE_OS
} }
1238 /* and3 $dr,$sr,#$uimm16 */
1241 "and3", "and3", SYN (3), FMT (2), 0x80c00000,
1242 & fmt_2_and3_ops
[0],
1243 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1245 /* and3 $dr,$sr,$uimm16 */
1248 "and3.a", "and3", SYN (4), FMT (2), 0x80c00000,
1249 & fmt_2_and3_ops
[0],
1250 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1255 "or", "or", SYN (0), FMT (0), 0xe0,
1257 { CGEN_INSN_NBOOL_ATTRS
, 0|A(PARALLEL
), { (1<<MACH_M32R
), PIPE_OS
} }
1259 /* or3 $dr,$sr,#$ulo16 */
1262 "or3", "or3", SYN (5), FMT (3), 0x80e00000,
1264 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1266 /* or3 $dr,$sr,$ulo16 */
1269 "or3.a", "or3", SYN (6), FMT (3), 0x80e00000,
1271 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1276 "xor", "xor", SYN (0), FMT (0), 0xd0,
1278 { CGEN_INSN_NBOOL_ATTRS
, 0|A(PARALLEL
), { (1<<MACH_M32R
), PIPE_OS
} }
1280 /* xor3 $dr,$sr,#$uimm16 */
1283 "xor3", "xor3", SYN (3), FMT (2), 0x80d00000,
1284 & fmt_2_and3_ops
[0],
1285 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1287 /* xor3 $dr,$sr,$uimm16 */
1290 "xor3.a", "xor3", SYN (4), FMT (2), 0x80d00000,
1291 & fmt_2_and3_ops
[0],
1292 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1294 /* addi $dr,#$simm8 */
1297 "addi", "addi", SYN (7), FMT (4), 0x4000,
1298 & fmt_4_addi_ops
[0],
1299 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1301 /* addi $dr,$simm8 */
1304 "addi.a", "addi", SYN (8), FMT (4), 0x4000,
1305 & fmt_4_addi_ops
[0],
1306 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_OS
} }
1311 "addv", "addv", SYN (0), FMT (5), 0x80,
1312 & fmt_5_addv_ops
[0],
1313 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1315 /* addv3 $dr,$sr,#$simm16 */
1318 "addv3", "addv3", SYN (9), FMT (6), 0x80800000,
1319 & fmt_6_addv3_ops
[0],
1320 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1322 /* addv3 $dr,$sr,$simm16 */
1325 "addv3.a", "addv3", SYN (10), FMT (6), 0x80800000,
1326 & fmt_6_addv3_ops
[0],
1327 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1332 "addx", "addx", SYN (0), FMT (7), 0x90,
1333 & fmt_7_addx_ops
[0],
1334 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1339 "bc8", "bc", SYN (11), FMT (8), 0x7c00,
1341 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1346 "bc8.s", "bc.s", SYN (11), FMT (9), 0x7c00,
1348 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1353 "bc24", "bc", SYN (12), FMT (10), 0xfc000000,
1354 & fmt_10_bc24_ops
[0],
1355 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1360 "bc24.l", "bc.l", SYN (12), FMT (11), 0xfc000000,
1362 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1364 /* beq $src1,$src2,$disp16 */
1367 "beq", "beq", SYN (13), FMT (12), 0xb0000000,
1368 & fmt_12_beq_ops
[0],
1369 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1371 /* beqz $src2,$disp16 */
1374 "beqz", "beqz", SYN (14), FMT (13), 0xb0800000,
1375 & fmt_13_beqz_ops
[0],
1376 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1378 /* bgez $src2,$disp16 */
1381 "bgez", "bgez", SYN (14), FMT (13), 0xb0b00000,
1382 & fmt_13_beqz_ops
[0],
1383 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1385 /* bgtz $src2,$disp16 */
1388 "bgtz", "bgtz", SYN (14), FMT (13), 0xb0d00000,
1389 & fmt_13_beqz_ops
[0],
1390 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1392 /* blez $src2,$disp16 */
1395 "blez", "blez", SYN (14), FMT (13), 0xb0c00000,
1396 & fmt_13_beqz_ops
[0],
1397 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1399 /* bltz $src2,$disp16 */
1402 "bltz", "bltz", SYN (14), FMT (13), 0xb0a00000,
1403 & fmt_13_beqz_ops
[0],
1404 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1406 /* bnez $src2,$disp16 */
1409 "bnez", "bnez", SYN (14), FMT (13), 0xb0900000,
1410 & fmt_13_beqz_ops
[0],
1411 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1416 "bl8", "bl", SYN (11), FMT (14), 0x7e00,
1417 & fmt_14_bl8_ops
[0],
1418 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(RELAXABLE
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1423 "bl8.s", "bl.s", SYN (11), FMT (9), 0x7e00,
1425 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(ALIAS
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1430 "bl24", "bl", SYN (12), FMT (15), 0xfe000000,
1431 & fmt_15_bl24_ops
[0],
1432 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1437 "bl24.l", "bl.l", SYN (12), FMT (11), 0xfe000000,
1439 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1441 /* start-sanitize-m32rx */
1445 "bcl8", "bcl", SYN (11), FMT (16), 0x7800,
1446 & fmt_16_bcl8_ops
[0],
1447 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1449 /* end-sanitize-m32rx */
1450 /* start-sanitize-m32rx */
1454 "bcl8.s", "bcl.s", SYN (11), FMT (9), 0x7800,
1456 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1458 /* end-sanitize-m32rx */
1459 /* start-sanitize-m32rx */
1463 "bcl24", "bcl", SYN (12), FMT (17), 0xf8000000,
1464 & fmt_17_bcl24_ops
[0],
1465 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1467 /* end-sanitize-m32rx */
1468 /* start-sanitize-m32rx */
1472 "bcl24.l", "bcl.l", SYN (12), FMT (11), 0xf8000000,
1474 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1476 /* end-sanitize-m32rx */
1480 "bnc8", "bnc", SYN (11), FMT (8), 0x7d00,
1482 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1487 "bnc8.s", "bnc.s", SYN (11), FMT (9), 0x7d00,
1489 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1494 "bnc24", "bnc", SYN (12), FMT (10), 0xfd000000,
1495 & fmt_10_bc24_ops
[0],
1496 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1501 "bnc24.l", "bnc.l", SYN (12), FMT (11), 0xfd000000,
1503 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1505 /* bne $src1,$src2,$disp16 */
1508 "bne", "bne", SYN (13), FMT (12), 0xb0100000,
1509 & fmt_12_beq_ops
[0],
1510 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1515 "bra8", "bra", SYN (11), FMT (18), 0x7f00,
1516 & fmt_18_bra8_ops
[0],
1517 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(RELAXABLE
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1522 "bra8.s", "bra.s", SYN (11), FMT (9), 0x7f00,
1524 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1529 "bra24", "bra", SYN (12), FMT (19), 0xff000000,
1530 & fmt_19_bra24_ops
[0],
1531 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1536 "bra24.l", "bra.l", SYN (12), FMT (11), 0xff000000,
1538 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_NONE
} }
1540 /* start-sanitize-m32rx */
1544 "bncl8", "bncl", SYN (11), FMT (16), 0x7900,
1545 & fmt_16_bcl8_ops
[0],
1546 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAXABLE
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1548 /* end-sanitize-m32rx */
1549 /* start-sanitize-m32rx */
1553 "bncl8.s", "bncl.s", SYN (11), FMT (9), 0x7900,
1555 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1557 /* end-sanitize-m32rx */
1558 /* start-sanitize-m32rx */
1562 "bncl24", "bncl", SYN (12), FMT (17), 0xf9000000,
1563 & fmt_17_bcl24_ops
[0],
1564 { CGEN_INSN_NBOOL_ATTRS
, 0|A(RELAX
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1566 /* end-sanitize-m32rx */
1567 /* start-sanitize-m32rx */
1568 /* bncl.l $disp24 */
1571 "bncl24.l", "bncl.l", SYN (12), FMT (11), 0xf9000000,
1573 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_NONE
} }
1575 /* end-sanitize-m32rx */
1576 /* cmp $src1,$src2 */
1579 "cmp", "cmp", SYN (15), FMT (20), 0x40,
1580 & fmt_20_cmp_ops
[0],
1581 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1583 /* cmpi $src2,#$simm16 */
1586 "cmpi", "cmpi", SYN (16), FMT (21), 0x80400000,
1587 & fmt_21_cmpi_ops
[0],
1588 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1590 /* cmpi $src2,$simm16 */
1593 "cmpi.a", "cmpi", SYN (17), FMT (21), 0x80400000,
1594 & fmt_21_cmpi_ops
[0],
1595 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1597 /* cmpu $src1,$src2 */
1600 "cmpu", "cmpu", SYN (15), FMT (20), 0x50,
1601 & fmt_20_cmp_ops
[0],
1602 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1604 /* cmpui $src2,#$uimm16 */
1607 "cmpui", "cmpui", SYN (18), FMT (22), 0x80500000,
1608 & fmt_22_cmpui_ops
[0],
1609 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1611 /* cmpui $src2,$uimm16 */
1614 "cmpui.a", "cmpui", SYN (19), FMT (22), 0x80500000,
1615 & fmt_22_cmpui_ops
[0],
1616 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1618 /* start-sanitize-m32rx */
1619 /* cmpeq $src1,$src2 */
1622 "cmpeq", "cmpeq", SYN (15), FMT (20), 0x60,
1623 & fmt_20_cmp_ops
[0],
1624 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
1626 /* end-sanitize-m32rx */
1627 /* start-sanitize-m32rx */
1631 "cmpz", "cmpz", SYN (20), FMT (23), 0x70,
1632 & fmt_23_cmpz_ops
[0],
1633 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
1635 /* end-sanitize-m32rx */
1639 "div", "div", SYN (0), FMT (24), 0x90000000,
1640 & fmt_24_div_ops
[0],
1641 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1646 "divu", "divu", SYN (0), FMT (24), 0x90100000,
1647 & fmt_24_div_ops
[0],
1648 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1653 "rem", "rem", SYN (0), FMT (24), 0x90200000,
1654 & fmt_24_div_ops
[0],
1655 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1660 "remu", "remu", SYN (0), FMT (24), 0x90300000,
1661 & fmt_24_div_ops
[0],
1662 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1664 /* start-sanitize-m32rx */
1668 "divh", "divh", SYN (0), FMT (24), 0x90000010,
1669 & fmt_24_div_ops
[0],
1670 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
1672 /* end-sanitize-m32rx */
1673 /* start-sanitize-m32rx */
1677 "jc", "jc", SYN (21), FMT (25), 0x1cc0,
1679 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1681 /* end-sanitize-m32rx */
1682 /* start-sanitize-m32rx */
1686 "jnc", "jnc", SYN (21), FMT (25), 0x1dc0,
1688 { CGEN_INSN_NBOOL_ATTRS
, 0|A(COND_CTI
), { (1<<MACH_M32RX
), PIPE_O
} }
1690 /* end-sanitize-m32rx */
1694 "jl", "jl", SYN (21), FMT (26), 0x1ec0,
1696 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1701 "jmp", "jmp", SYN (21), FMT (27), 0x1fc0,
1702 & fmt_27_jmp_ops
[0],
1703 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
1708 "ld", "ld", SYN (22), FMT (28), 0x20c0,
1710 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1715 "ld-2", "ld", SYN (23), FMT (29), 0x20c0,
1717 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
1719 /* ld $dr,@($slo16,$sr) */
1722 "ld-d", "ld", SYN (24), FMT (30), 0xa0c00000,
1723 & fmt_30_ld_d_ops
[0],
1724 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1726 /* ld $dr,@($sr,$slo16) */
1729 "ld-d2", "ld", SYN (25), FMT (31), 0xa0c00000,
1731 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1736 "ldb", "ldb", SYN (22), FMT (32), 0x2080,
1737 & fmt_32_ldb_ops
[0],
1738 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1740 /* ldb $dr,@($sr) */
1743 "ldb-2", "ldb", SYN (23), FMT (29), 0x2080,
1745 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
1747 /* ldb $dr,@($slo16,$sr) */
1750 "ldb-d", "ldb", SYN (24), FMT (33), 0xa0800000,
1751 & fmt_33_ldb_d_ops
[0],
1752 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1754 /* ldb $dr,@($sr,$slo16) */
1757 "ldb-d2", "ldb", SYN (25), FMT (31), 0xa0800000,
1759 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1764 "ldh", "ldh", SYN (22), FMT (34), 0x20a0,
1765 & fmt_34_ldh_ops
[0],
1766 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1768 /* ldh $dr,@($sr) */
1771 "ldh-2", "ldh", SYN (23), FMT (29), 0x20a0,
1773 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
1775 /* ldh $dr,@($slo16,$sr) */
1778 "ldh-d", "ldh", SYN (24), FMT (35), 0xa0a00000,
1779 & fmt_35_ldh_d_ops
[0],
1780 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1782 /* ldh $dr,@($sr,$slo16) */
1785 "ldh-d2", "ldh", SYN (25), FMT (31), 0xa0a00000,
1787 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1792 "ldub", "ldub", SYN (22), FMT (32), 0x2090,
1793 & fmt_32_ldb_ops
[0],
1794 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1796 /* ldub $dr,@($sr) */
1799 "ldub-2", "ldub", SYN (23), FMT (29), 0x2090,
1801 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
1803 /* ldub $dr,@($slo16,$sr) */
1806 "ldub-d", "ldub", SYN (24), FMT (33), 0xa0900000,
1807 & fmt_33_ldb_d_ops
[0],
1808 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1810 /* ldub $dr,@($sr,$slo16) */
1813 "ldub-d2", "ldub", SYN (25), FMT (31), 0xa0900000,
1815 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1820 "lduh", "lduh", SYN (22), FMT (34), 0x20b0,
1821 & fmt_34_ldh_ops
[0],
1822 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1824 /* lduh $dr,@($sr) */
1827 "lduh-2", "lduh", SYN (23), FMT (29), 0x20b0,
1829 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
1831 /* lduh $dr,@($slo16,$sr) */
1834 "lduh-d", "lduh", SYN (24), FMT (35), 0xa0b00000,
1835 & fmt_35_ldh_d_ops
[0],
1836 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1838 /* lduh $dr,@($sr,$slo16) */
1841 "lduh-d2", "lduh", SYN (25), FMT (31), 0xa0b00000,
1843 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1848 "ld-plus", "ld", SYN (26), FMT (36), 0x20e0,
1849 & fmt_36_ld_plus_ops
[0],
1850 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1852 /* ld24 $dr,#$uimm24 */
1855 "ld24", "ld24", SYN (27), FMT (37), 0xe0000000,
1856 & fmt_37_ld24_ops
[0],
1857 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1859 /* ld24 $dr,$uimm24 */
1862 "ld24.a", "ld24", SYN (28), FMT (37), 0xe0000000,
1863 & fmt_37_ld24_ops
[0],
1864 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1866 /* ldi $dr,#$simm8 */
1869 "ldi8", "ldi", SYN (7), FMT (38), 0x6000,
1870 & fmt_38_ldi8_ops
[0],
1871 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
1873 /* ldi $dr,$simm8 */
1876 "ldi8.a", "ldi", SYN (8), FMT (38), 0x6000,
1877 & fmt_38_ldi8_ops
[0],
1878 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_OS
} }
1880 /* ldi8 $dr,#$simm8 */
1883 "ldi8a", "ldi8", SYN (7), FMT (38), 0x6000,
1884 & fmt_38_ldi8_ops
[0],
1885 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_OS
} }
1887 /* ldi8 $dr,$simm8 */
1890 "ldi8a.a", "ldi8", SYN (8), FMT (38), 0x6000,
1891 & fmt_38_ldi8_ops
[0],
1892 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_OS
} }
1894 /* ldi $dr,$slo16 */
1897 "ldi16", "ldi", SYN (29), FMT (39), 0x90f00000,
1898 & fmt_39_ldi16_ops
[0],
1899 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
1901 /* ldi16 $dr,$slo16 */
1904 "ldi16a", "ldi16", SYN (29), FMT (39), 0x90f00000,
1905 & fmt_39_ldi16_ops
[0],
1906 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
1911 "lock", "lock", SYN (22), FMT (40), 0x20d0,
1912 & fmt_40_lock_ops
[0],
1913 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
1915 /* machi $src1,$src2 */
1918 "machi", "machi", SYN (15), FMT (41), 0x3040,
1919 & fmt_41_machi_ops
[0],
1920 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1922 /* start-sanitize-m32rx */
1923 /* machi $src1,$src2,$acc */
1926 "machi-a", "machi", SYN (30), FMT (42), 0x3040,
1927 & fmt_42_machi_a_ops
[0],
1928 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1930 /* end-sanitize-m32rx */
1931 /* maclo $src1,$src2 */
1934 "maclo", "maclo", SYN (15), FMT (41), 0x3050,
1935 & fmt_41_machi_ops
[0],
1936 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1938 /* start-sanitize-m32rx */
1939 /* maclo $src1,$src2,$acc */
1942 "maclo-a", "maclo", SYN (30), FMT (42), 0x3050,
1943 & fmt_42_machi_a_ops
[0],
1944 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1946 /* end-sanitize-m32rx */
1947 /* macwhi $src1,$src2 */
1950 "macwhi", "macwhi", SYN (15), FMT (41), 0x3060,
1951 & fmt_41_machi_ops
[0],
1952 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1954 /* macwlo $src1,$src2 */
1957 "macwlo", "macwlo", SYN (15), FMT (41), 0x3070,
1958 & fmt_41_machi_ops
[0],
1959 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1964 "mul", "mul", SYN (0), FMT (0), 0x1060,
1966 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1968 /* mulhi $src1,$src2 */
1971 "mulhi", "mulhi", SYN (15), FMT (43), 0x3000,
1972 & fmt_43_mulhi_ops
[0],
1973 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1975 /* start-sanitize-m32rx */
1976 /* mulhi $src1,$src2,$acc */
1979 "mulhi-a", "mulhi", SYN (30), FMT (44), 0x3000,
1980 & fmt_44_mulhi_a_ops
[0],
1981 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1983 /* end-sanitize-m32rx */
1984 /* mullo $src1,$src2 */
1987 "mullo", "mullo", SYN (15), FMT (43), 0x3010,
1988 & fmt_43_mulhi_ops
[0],
1989 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
1991 /* start-sanitize-m32rx */
1992 /* mullo $src1,$src2,$acc */
1995 "mullo-a", "mullo", SYN (30), FMT (44), 0x3010,
1996 & fmt_44_mulhi_a_ops
[0],
1997 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
1999 /* end-sanitize-m32rx */
2000 /* mulwhi $src1,$src2 */
2003 "mulwhi", "mulwhi", SYN (15), FMT (43), 0x3020,
2004 & fmt_43_mulhi_ops
[0],
2005 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2007 /* mulwlo $src1,$src2 */
2010 "mulwlo", "mulwlo", SYN (15), FMT (43), 0x3030,
2011 & fmt_43_mulhi_ops
[0],
2012 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2017 "mv", "mv", SYN (0), FMT (45), 0x1080,
2019 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2024 "mvfachi", "mvfachi", SYN (31), FMT (46), 0x50f0,
2025 & fmt_46_mvfachi_ops
[0],
2026 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2028 /* start-sanitize-m32rx */
2029 /* mvfachi $dr,$accs */
2032 "mvfachi-a", "mvfachi", SYN (32), FMT (47), 0x50f0,
2033 & fmt_47_mvfachi_a_ops
[0],
2034 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2036 /* end-sanitize-m32rx */
2040 "mvfaclo", "mvfaclo", SYN (31), FMT (46), 0x50f1,
2041 & fmt_46_mvfachi_ops
[0],
2042 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2044 /* start-sanitize-m32rx */
2045 /* mvfaclo $dr,$accs */
2048 "mvfaclo-a", "mvfaclo", SYN (32), FMT (47), 0x50f1,
2049 & fmt_47_mvfachi_a_ops
[0],
2050 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2052 /* end-sanitize-m32rx */
2056 "mvfacmi", "mvfacmi", SYN (31), FMT (46), 0x50f2,
2057 & fmt_46_mvfachi_ops
[0],
2058 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2060 /* start-sanitize-m32rx */
2061 /* mvfacmi $dr,$accs */
2064 "mvfacmi-a", "mvfacmi", SYN (32), FMT (47), 0x50f2,
2065 & fmt_47_mvfachi_a_ops
[0],
2066 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2068 /* end-sanitize-m32rx */
2072 "mvfc", "mvfc", SYN (33), FMT (48), 0x1090,
2073 & fmt_48_mvfc_ops
[0],
2074 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2079 "mvtachi", "mvtachi", SYN (34), FMT (49), 0x5070,
2080 & fmt_49_mvtachi_ops
[0],
2081 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2083 /* start-sanitize-m32rx */
2084 /* mvtachi $src1,$accs */
2087 "mvtachi-a", "mvtachi", SYN (35), FMT (50), 0x5070,
2088 & fmt_50_mvtachi_a_ops
[0],
2089 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2091 /* end-sanitize-m32rx */
2095 "mvtaclo", "mvtaclo", SYN (34), FMT (49), 0x5071,
2096 & fmt_49_mvtachi_ops
[0],
2097 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2099 /* start-sanitize-m32rx */
2100 /* mvtaclo $src1,$accs */
2103 "mvtaclo-a", "mvtaclo", SYN (35), FMT (50), 0x5071,
2104 & fmt_50_mvtachi_a_ops
[0],
2105 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2107 /* end-sanitize-m32rx */
2111 "mvtc", "mvtc", SYN (36), FMT (51), 0x10a0,
2112 & fmt_51_mvtc_ops
[0],
2113 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2118 "neg", "neg", SYN (0), FMT (45), 0x30,
2120 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2125 "nop", "nop", SYN (37), FMT (52), 0x7000,
2127 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2132 "not", "not", SYN (0), FMT (45), 0xb0,
2134 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2139 "rac", "rac", SYN (37), FMT (53), 0x5090,
2140 & fmt_53_rac_ops
[0],
2141 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2143 /* start-sanitize-m32rx */
2147 "rac-d", "rac", SYN (38), FMT (54), 0x5090,
2149 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2151 /* end-sanitize-m32rx */
2152 /* start-sanitize-m32rx */
2153 /* rac $accd,$accs */
2156 "rac-ds", "rac", SYN (39), FMT (55), 0x5090,
2158 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2160 /* end-sanitize-m32rx */
2161 /* start-sanitize-m32rx */
2162 /* rac $accd,$accs,#$imm1 */
2165 "rac-dsi", "rac", SYN (40), FMT (56), 0x5090,
2166 & fmt_56_rac_dsi_ops
[0],
2167 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2169 /* end-sanitize-m32rx */
2173 "rach", "rach", SYN (37), FMT (53), 0x5080,
2174 & fmt_53_rac_ops
[0],
2175 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_S
} }
2177 /* start-sanitize-m32rx */
2181 "rach-d", "rach", SYN (38), FMT (54), 0x5080,
2183 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2185 /* end-sanitize-m32rx */
2186 /* start-sanitize-m32rx */
2187 /* rach $accd,$accs */
2190 "rach-ds", "rach", SYN (39), FMT (55), 0x5080,
2192 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2194 /* end-sanitize-m32rx */
2195 /* start-sanitize-m32rx */
2196 /* rach $accd,$accs,#$imm1 */
2199 "rach-dsi", "rach", SYN (40), FMT (56), 0x5080,
2200 & fmt_56_rac_dsi_ops
[0],
2201 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2203 /* end-sanitize-m32rx */
2207 "rte", "rte", SYN (37), FMT (57), 0x10d6,
2208 & fmt_57_rte_ops
[0],
2209 { CGEN_INSN_NBOOL_ATTRS
, 0|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
2211 /* seth $dr,#$hi16 */
2214 "seth", "seth", SYN (41), FMT (58), 0xd0c00000,
2215 & fmt_58_seth_ops
[0],
2216 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2218 /* seth $dr,$hi16 */
2221 "seth.a", "seth", SYN (42), FMT (58), 0xd0c00000,
2222 & fmt_58_seth_ops
[0],
2223 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2228 "sll", "sll", SYN (0), FMT (0), 0x1040,
2230 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2232 /* sll3 $dr,$sr,#$simm16 */
2235 "sll3", "sll3", SYN (9), FMT (59), 0x90c00000,
2236 & fmt_59_sll3_ops
[0],
2237 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2239 /* sll3 $dr,$sr,$simm16 */
2242 "sll3.a", "sll3", SYN (10), FMT (59), 0x90c00000,
2243 & fmt_59_sll3_ops
[0],
2244 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2246 /* slli $dr,#$uimm5 */
2249 "slli", "slli", SYN (43), FMT (60), 0x5040,
2250 & fmt_60_slli_ops
[0],
2251 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2253 /* slli $dr,$uimm5 */
2256 "slli.a", "slli", SYN (44), FMT (60), 0x5040,
2257 & fmt_60_slli_ops
[0],
2258 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2263 "sra", "sra", SYN (0), FMT (0), 0x1020,
2265 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2267 /* sra3 $dr,$sr,#$simm16 */
2270 "sra3", "sra3", SYN (9), FMT (59), 0x90a00000,
2271 & fmt_59_sll3_ops
[0],
2272 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2274 /* sra3 $dr,$sr,$simm16 */
2277 "sra3.a", "sra3", SYN (10), FMT (59), 0x90a00000,
2278 & fmt_59_sll3_ops
[0],
2279 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2281 /* srai $dr,#$uimm5 */
2284 "srai", "srai", SYN (43), FMT (60), 0x5020,
2285 & fmt_60_slli_ops
[0],
2286 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2288 /* srai $dr,$uimm5 */
2291 "srai.a", "srai", SYN (44), FMT (60), 0x5020,
2292 & fmt_60_slli_ops
[0],
2293 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2298 "srl", "srl", SYN (0), FMT (0), 0x1000,
2300 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2302 /* srl3 $dr,$sr,#$simm16 */
2305 "srl3", "srl3", SYN (9), FMT (59), 0x90800000,
2306 & fmt_59_sll3_ops
[0],
2307 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2309 /* srl3 $dr,$sr,$simm16 */
2312 "srl3.a", "srl3", SYN (10), FMT (59), 0x90800000,
2313 & fmt_59_sll3_ops
[0],
2314 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2316 /* srli $dr,#$uimm5 */
2319 "srli", "srli", SYN (43), FMT (60), 0x5000,
2320 & fmt_60_slli_ops
[0],
2321 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2323 /* srli $dr,$uimm5 */
2326 "srli.a", "srli", SYN (44), FMT (60), 0x5000,
2327 & fmt_60_slli_ops
[0],
2328 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2330 /* st $src1,@$src2 */
2333 "st", "st", SYN (45), FMT (61), 0x2040,
2335 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2337 /* st $src1,@($src2) */
2340 "st-2", "st", SYN (46), FMT (62), 0x2040,
2342 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2344 /* st $src1,@($slo16,$src2) */
2347 "st-d", "st", SYN (47), FMT (63), 0xa0400000,
2348 & fmt_63_st_d_ops
[0],
2349 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2351 /* st $src1,@($src2,$slo16) */
2354 "st-d2", "st", SYN (48), FMT (64), 0xa0400000,
2356 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2358 /* stb $src1,@$src2 */
2361 "stb", "stb", SYN (45), FMT (65), 0x2000,
2362 & fmt_65_stb_ops
[0],
2363 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2365 /* stb $src1,@($src2) */
2368 "stb-2", "stb", SYN (46), FMT (62), 0x2000,
2370 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2372 /* stb $src1,@($slo16,$src2) */
2375 "stb-d", "stb", SYN (47), FMT (66), 0xa0000000,
2376 & fmt_66_stb_d_ops
[0],
2377 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2379 /* stb $src1,@($src2,$slo16) */
2382 "stb-d2", "stb", SYN (48), FMT (64), 0xa0000000,
2384 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2386 /* sth $src1,@$src2 */
2389 "sth", "sth", SYN (45), FMT (67), 0x2020,
2390 & fmt_67_sth_ops
[0],
2391 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2393 /* sth $src1,@($src2) */
2396 "sth-2", "sth", SYN (46), FMT (62), 0x2020,
2398 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_O
} }
2400 /* sth $src1,@($slo16,$src2) */
2403 "sth-d", "sth", SYN (47), FMT (68), 0xa0200000,
2404 & fmt_68_sth_d_ops
[0],
2405 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_NONE
} }
2407 /* sth $src1,@($src2,$slo16) */
2410 "sth-d2", "sth", SYN (48), FMT (64), 0xa0200000,
2412 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2414 /* st $src1,@+$src2 */
2417 "st-plus", "st", SYN (49), FMT (69), 0x2060,
2418 & fmt_69_st_plus_ops
[0],
2419 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2421 /* st $src1,@-$src2 */
2424 "st-minus", "st", SYN (50), FMT (69), 0x2070,
2425 & fmt_69_st_plus_ops
[0],
2426 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2431 "sub", "sub", SYN (0), FMT (0), 0x20,
2433 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2438 "subv", "subv", SYN (0), FMT (5), 0x0,
2439 & fmt_5_addv_ops
[0],
2440 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2445 "subx", "subx", SYN (0), FMT (7), 0x10,
2446 & fmt_7_addx_ops
[0],
2447 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_OS
} }
2452 "trap", "trap", SYN (51), FMT (70), 0x10f0,
2453 & fmt_70_trap_ops
[0],
2454 { CGEN_INSN_NBOOL_ATTRS
, 0|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
2459 "trap.a", "trap", SYN (52), FMT (71), 0x10f0,
2461 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
)|A(FILL_SLOT
)|A(UNCOND_CTI
), { (1<<MACH_M32R
), PIPE_O
} }
2463 /* unlock $src1,@$src2 */
2466 "unlock", "unlock", SYN (45), FMT (72), 0x2050,
2467 & fmt_72_unlock_ops
[0],
2468 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32R
), PIPE_O
} }
2473 "push", "push", SYN (34), FMT (73), 0x207f,
2475 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2480 "pop", "pop", SYN (31), FMT (74), 0x20ef,
2482 { CGEN_INSN_NBOOL_ATTRS
, 0|A(ALIAS
), { (1<<MACH_M32R
), PIPE_NONE
} }
2484 /* start-sanitize-m32rx */
2488 "satb", "satb", SYN (0), FMT (75), 0x80000100,
2489 & fmt_75_satb_ops
[0],
2490 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
2492 /* end-sanitize-m32rx */
2493 /* start-sanitize-m32rx */
2497 "sath", "sath", SYN (0), FMT (75), 0x80000200,
2498 & fmt_75_satb_ops
[0],
2499 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
2501 /* end-sanitize-m32rx */
2502 /* start-sanitize-m32rx */
2506 "sat", "sat", SYN (0), FMT (76), 0x80000000,
2507 & fmt_76_sat_ops
[0],
2508 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_NONE
} }
2510 /* end-sanitize-m32rx */
2511 /* start-sanitize-m32rx */
2515 "pcmpbz", "pcmpbz", SYN (20), FMT (23), 0x370,
2516 & fmt_23_cmpz_ops
[0],
2517 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_OS
} }
2519 /* end-sanitize-m32rx */
2520 /* start-sanitize-m32rx */
2524 "sadd", "sadd", SYN (37), FMT (77), 0x50e4,
2525 & fmt_77_sadd_ops
[0],
2526 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2528 /* end-sanitize-m32rx */
2529 /* start-sanitize-m32rx */
2530 /* macwu1 $src1,$src2 */
2533 "macwu1", "macwu1", SYN (15), FMT (78), 0x50b0,
2534 & fmt_78_macwu1_ops
[0],
2535 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2537 /* end-sanitize-m32rx */
2538 /* start-sanitize-m32rx */
2539 /* msblo $src1,$src2 */
2542 "msblo", "msblo", SYN (15), FMT (41), 0x50d0,
2543 & fmt_41_machi_ops
[0],
2544 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2546 /* end-sanitize-m32rx */
2547 /* start-sanitize-m32rx */
2548 /* mulwu1 $src1,$src2 */
2551 "mulwu1", "mulwu1", SYN (15), FMT (79), 0x50a0,
2552 & fmt_79_mulwu1_ops
[0],
2553 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2555 /* end-sanitize-m32rx */
2556 /* start-sanitize-m32rx */
2557 /* maclh1 $src1,$src2 */
2560 "maclh1", "maclh1", SYN (15), FMT (78), 0x50c0,
2561 & fmt_78_macwu1_ops
[0],
2562 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_S
} }
2564 /* end-sanitize-m32rx */
2565 /* start-sanitize-m32rx */
2569 "sc", "sc", SYN (37), FMT (80), 0x7401,
2571 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_O
} }
2573 /* end-sanitize-m32rx */
2574 /* start-sanitize-m32rx */
2578 "snc", "snc", SYN (37), FMT (80), 0x7501,
2580 { CGEN_INSN_NBOOL_ATTRS
, 0, { (1<<MACH_M32RX
), PIPE_O
} }
2582 /* end-sanitize-m32rx */
2589 CGEN_INSN_TABLE m32r_cgen_insn_table
=
2591 & m32r_cgen_insn_table_entries
[0],
2595 m32r_cgen_asm_hash_insn
, CGEN_ASM_HASH_SIZE
,
2596 m32r_cgen_dis_hash_insn
, CGEN_DIS_HASH_SIZE
2599 /* The hash functions are recorded here to help keep assembler code out of
2600 the disassembler and vice versa. */
2603 m32r_cgen_asm_hash_insn (insn
)
2606 return CGEN_ASM_HASH (insn
);
2610 m32r_cgen_dis_hash_insn (buf
, value
)
2612 unsigned long value
;
2614 return CGEN_DIS_HASH (buf
, value
);
2617 CGEN_OPCODE_DATA m32r_cgen_opcode_data
=
2619 & m32r_cgen_hw_entries
[0],
2620 & m32r_cgen_insn_table
,
2624 m32r_cgen_init_tables (mach
)
2629 /* Main entry point for stuffing values in cgen_fields. */
2632 m32r_cgen_set_operand (opindex
, valuep
, fields
)
2634 const long * valuep
;
2635 CGEN_FIELDS
* fields
;
2639 case M32R_OPERAND_SR
:
2640 fields
->f_r2
= * valuep
;
2642 case M32R_OPERAND_DR
:
2643 fields
->f_r1
= * valuep
;
2645 case M32R_OPERAND_SRC1
:
2646 fields
->f_r1
= * valuep
;
2648 case M32R_OPERAND_SRC2
:
2649 fields
->f_r2
= * valuep
;
2651 case M32R_OPERAND_SCR
:
2652 fields
->f_r2
= * valuep
;
2654 case M32R_OPERAND_DCR
:
2655 fields
->f_r1
= * valuep
;
2657 case M32R_OPERAND_SIMM8
:
2658 fields
->f_simm8
= * valuep
;
2660 case M32R_OPERAND_SIMM16
:
2661 fields
->f_simm16
= * valuep
;
2663 case M32R_OPERAND_UIMM4
:
2664 fields
->f_uimm4
= * valuep
;
2666 case M32R_OPERAND_UIMM5
:
2667 fields
->f_uimm5
= * valuep
;
2669 case M32R_OPERAND_UIMM16
:
2670 fields
->f_uimm16
= * valuep
;
2672 /* start-sanitize-m32rx */
2673 case M32R_OPERAND_IMM1
:
2674 fields
->f_imm1
= * valuep
;
2676 /* end-sanitize-m32rx */
2677 /* start-sanitize-m32rx */
2678 case M32R_OPERAND_ACCD
:
2679 fields
->f_accd
= * valuep
;
2681 /* end-sanitize-m32rx */
2682 /* start-sanitize-m32rx */
2683 case M32R_OPERAND_ACCS
:
2684 fields
->f_accs
= * valuep
;
2686 /* end-sanitize-m32rx */
2687 /* start-sanitize-m32rx */
2688 case M32R_OPERAND_ACC
:
2689 fields
->f_acc
= * valuep
;
2691 /* end-sanitize-m32rx */
2692 case M32R_OPERAND_HI16
:
2693 fields
->f_hi16
= * valuep
;
2695 case M32R_OPERAND_SLO16
:
2696 fields
->f_simm16
= * valuep
;
2698 case M32R_OPERAND_ULO16
:
2699 fields
->f_uimm16
= * valuep
;
2701 case M32R_OPERAND_UIMM24
:
2702 fields
->f_uimm24
= * valuep
;
2704 case M32R_OPERAND_DISP8
:
2705 fields
->f_disp8
= * valuep
;
2707 case M32R_OPERAND_DISP16
:
2708 fields
->f_disp16
= * valuep
;
2710 case M32R_OPERAND_DISP24
:
2711 fields
->f_disp24
= * valuep
;
2715 fprintf (stderr
, "Unrecognized field %d while setting operand.\n",
2721 /* Main entry point for getting values from cgen_fields. */
2724 m32r_cgen_get_operand (opindex
, fields
)
2726 const CGEN_FIELDS
* fields
;
2732 case M32R_OPERAND_SR
:
2733 value
= fields
->f_r2
;
2735 case M32R_OPERAND_DR
:
2736 value
= fields
->f_r1
;
2738 case M32R_OPERAND_SRC1
:
2739 value
= fields
->f_r1
;
2741 case M32R_OPERAND_SRC2
:
2742 value
= fields
->f_r2
;
2744 case M32R_OPERAND_SCR
:
2745 value
= fields
->f_r2
;
2747 case M32R_OPERAND_DCR
:
2748 value
= fields
->f_r1
;
2750 case M32R_OPERAND_SIMM8
:
2751 value
= fields
->f_simm8
;
2753 case M32R_OPERAND_SIMM16
:
2754 value
= fields
->f_simm16
;
2756 case M32R_OPERAND_UIMM4
:
2757 value
= fields
->f_uimm4
;
2759 case M32R_OPERAND_UIMM5
:
2760 value
= fields
->f_uimm5
;
2762 case M32R_OPERAND_UIMM16
:
2763 value
= fields
->f_uimm16
;
2765 /* start-sanitize-m32rx */
2766 case M32R_OPERAND_IMM1
:
2767 value
= fields
->f_imm1
;
2769 /* end-sanitize-m32rx */
2770 /* start-sanitize-m32rx */
2771 case M32R_OPERAND_ACCD
:
2772 value
= fields
->f_accd
;
2774 /* end-sanitize-m32rx */
2775 /* start-sanitize-m32rx */
2776 case M32R_OPERAND_ACCS
:
2777 value
= fields
->f_accs
;
2779 /* end-sanitize-m32rx */
2780 /* start-sanitize-m32rx */
2781 case M32R_OPERAND_ACC
:
2782 value
= fields
->f_acc
;
2784 /* end-sanitize-m32rx */
2785 case M32R_OPERAND_HI16
:
2786 value
= fields
->f_hi16
;
2788 case M32R_OPERAND_SLO16
:
2789 value
= fields
->f_simm16
;
2791 case M32R_OPERAND_ULO16
:
2792 value
= fields
->f_uimm16
;
2794 case M32R_OPERAND_UIMM24
:
2795 value
= fields
->f_uimm24
;
2797 case M32R_OPERAND_DISP8
:
2798 value
= fields
->f_disp8
;
2800 case M32R_OPERAND_DISP16
:
2801 value
= fields
->f_disp16
;
2803 case M32R_OPERAND_DISP24
:
2804 value
= fields
->f_disp24
;
2808 fprintf (stderr
, "Unrecognized field %d while getting operand.\n",