opcodes/m32r-opc.c

   1 /* Generic opcode table support for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4 This file is used to generate m32r-opc.c.
   5
   6 Copyright (C) 1998 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and GDB, the GNU debugger.
   9
  10 This program is free software; you can redistribute it and/or modify
  11 it under the terms of the GNU General Public License as published by
  12 the Free Software Foundation; either version 2, or (at your option)
  13 any later version.
  14
  15 This program is distributed in the hope that it will be useful,
  16 but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 GNU General Public License for more details.
  19
  20 You should have received a copy of the GNU General Public License
  21 along with this program; if not, write to the Free Software
  22 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  23
  24 #include "sysdep.h"
  25 #include <stdio.h>
  26 #include "ansidecl.h"
  27 #include "libiberty.h"
  28 #include "bfd.h"
  29 #include "symcat.h"
  30 #include "m32r-opc.h"
  31
  32 /* Look up instruction INSN_VALUE and extract its fields.
  33    If non-null INSN is the insn table entry.
  34    Otherwise INSN_VALUE is examined to compute it.
  35    LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
  36    ALIAS_P is non-zero if alias insns are to be included in the search.
  37    The result a pointer to the insn table entry, or NULL if the instruction
  38    wasn't recognized.  */
  39
  40 const CGEN_INSN *
  41 m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p)
  42      const CGEN_INSN *insn;
  43      cgen_insn_t insn_value;
  44      int length;
  45      CGEN_FIELDS *fields;
  46 {
  47   char buf[16];
  48
  49   if (!insn)
  50     {
  51       const CGEN_INSN_LIST *insn_list;
  52
  53 #ifdef CGEN_INT_INSN
  54       switch (length)
  55         {
  56         case 8:
  57           buf[0] = insn_value;
  58           break;
  59         case 16:
  60           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  61             bfd_putb16 (insn_value, buf);
  62           else
  63             bfd_putl16 (insn_value, buf);
  64           break;
  65         case 32:
  66           if (cgen_current_endian == CGEN_ENDIAN_BIG)
  67             bfd_putb32 (insn_value, buf);
  68           else
  69             bfd_putl32 (insn_value, buf);
  70           break;
  71         default:
  72           abort ();
  73         }
  74 #else
  75       abort (); /* FIXME: unfinished */
  76 #endif
  77
  78       /* The instructions are stored in hash lists.
  79          Pick the first one and keep trying until we find the right one.  */
  80
  81       insn_list = CGEN_DIS_LOOKUP_INSN (buf, insn_value);
  82       while (insn_list != NULL)
  83         {
  84           insn = insn_list->insn;
  85
  86           if (alias_p
  87               || ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
  88             {
  89               /* Basic bit mask must be correct.  */
  90               /* ??? May wish to allow target to defer this check until the
  91                  extract handler.  */
  92               if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn))
  93                 {
  94                   length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
  95                   if (length > 0)
  96                     return insn;
  97                 }
  98             }
  99
 100           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 101         }
 102     }
 103   else
 104     {
 105       /* Sanity check: can't pass an alias insn if ! alias_p.  */
 106       if (! alias_p
 107           && CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
 108         abort ();
 109
 110       length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields);
 111       if (length > 0)
 112         return insn;
 113     }
 114
 115   return NULL;
 116 }
 117
 118 /* Fill in the operand instances used by insn INSN_VALUE.
 119    If non-null INS is the insn table entry.
 120    Otherwise INSN_VALUE is examined to compute it.
 121    LENGTH is the number of bits in INSN_VALUE if known, otherwise 0.
 122    INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
 123    in.
 124    The result a pointer to the insn table entry, or NULL if the instruction
 125    wasn't recognized.  */
 126
 127 const CGEN_INSN *
 128 m32r_cgen_get_insn_operands (insn, insn_value, length, indices)
 129      const CGEN_INSN *insn;
 130      cgen_insn_t insn_value;
 131      int length;
 132      int *indices;
 133 {
 134   CGEN_FIELDS fields;
 135   const CGEN_OPERAND_INSTANCE *opinst;
 136   int i;
 137
 138   /* FIXME: ALIAS insns are in transition from being record in the insn table
 139      to being recorded separately as macros.  They don't have semantic code
 140      so they can't be used here.  Thus we currently always ignore the INSN
 141      argument.  */
 142   insn = m32r_cgen_lookup_insn (NULL, insn_value, length, &fields, 0);
 143   if (! insn)
 144     return NULL;
 145
 146   for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
 147        opinst != NULL
 148          && CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
 149        ++i, ++opinst)
 150     {
 151       const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
 152       if (op == NULL)
 153         indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
 154       else
 155         indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), &fields);
 156     }
 157
 158   return insn;
 159 }
 160 /* Attributes.  */
 161
 162 static const CGEN_ATTR_ENTRY MACH_attr[] =
 163 {
 164   { "m32r", MACH_M32R },
 165 /* start-sanitize-m32rx */
 166   { "m32rx", MACH_M32RX },
 167 /* end-sanitize-m32rx */
 168   { "max", MACH_MAX },
 169   { 0, 0 }
 170 };
 171
 172 /* start-sanitize-m32rx */
 173 static const CGEN_ATTR_ENTRY PIPE_attr[] =
 174 {
 175   { "NONE", PIPE_NONE },
 176   { "O", PIPE_O },
 177   { "S", PIPE_S },
 178   { "OS", PIPE_OS },
 179   { 0, 0 }
 180 };
 181
 182 /* end-sanitize-m32rx */
 183 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 184 {
 185   { "ABS-ADDR", NULL },
 186   { "FAKE", NULL },
 187   { "HASH-PREFIX", NULL },
 188   { "NEGATIVE", NULL },
 189   { "PC", NULL },
 190   { "PCREL-ADDR", NULL },
 191   { "RELAX", NULL },
 192   { "RELOC", NULL },
 193   { "SIGN-OPT", NULL },
 194   { "UNSIGNED", NULL },
 195   { 0, 0 }
 196 };
 197
 198 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 199 {
 200   { "MACH", & MACH_attr[0] },
 201 /* start-sanitize-m32rx */
 202   { "PIPE", & PIPE_attr[0] },
 203 /* end-sanitize-m32rx */
 204   { "ALIAS", NULL },
 205   { "COND-CTI", NULL },
 206   { "FILL-SLOT", NULL },
 207   { "PARALLEL", NULL },
 208   { "RELAX", NULL },
 209   { "RELAXABLE", NULL },
 210   { "UNCOND-CTI", NULL },
 211   { 0, 0 }
 212 };
 213
 214 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_gr_entries[] =
 215 {
 216   { "fp", 13 },
 217   { "lr", 14 },
 218   { "sp", 15 },
 219   { "r0", 0 },
 220   { "r1", 1 },
 221   { "r2", 2 },
 222   { "r3", 3 },
 223   { "r4", 4 },
 224   { "r5", 5 },
 225   { "r6", 6 },
 226   { "r7", 7 },
 227   { "r8", 8 },
 228   { "r9", 9 },
 229   { "r10", 10 },
 230   { "r11", 11 },
 231   { "r12", 12 },
 232   { "r13", 13 },
 233   { "r14", 14 },
 234   { "r15", 15 }
 235 };
 236
 237 CGEN_KEYWORD m32r_cgen_opval_h_gr =
 238 {
 239   & m32r_cgen_opval_h_gr_entries[0],
 240   19
 241 };
 242
 243 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_cr_entries[] =
 244 {
 245   { "psw", 0 },
 246   { "cbr", 1 },
 247   { "spi", 2 },
 248   { "spu", 3 },
 249   { "bpc", 6 },
 250   { "cr0", 0 },
 251   { "cr1", 1 },
 252   { "cr2", 2 },
 253   { "cr3", 3 },
 254   { "cr4", 4 },
 255   { "cr5", 5 },
 256   { "cr6", 6 },
 257   { "cr7", 7 },
 258   { "cr8", 8 },
 259   { "cr9", 9 },
 260   { "cr10", 10 },
 261   { "cr11", 11 },
 262   { "cr12", 12 },
 263   { "cr13", 13 },
 264   { "cr14", 14 },
 265   { "cr15", 15 }
 266 };
 267
 268 CGEN_KEYWORD m32r_cgen_opval_h_cr =
 269 {
 270   & m32r_cgen_opval_h_cr_entries[0],
 271   21
 272 };
 273
 274 /* start-sanitize-m32rx */
 275 CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
 276 {
 277   { "a0", 0 },
 278   { "a1", 1 }
 279 };
 280
 281 CGEN_KEYWORD m32r_cgen_opval_h_accums =
 282 {
 283   & m32r_cgen_opval_h_accums_entries[0],
 284   2
 285 };
 286
 287 /* end-sanitize-m32rx */
 288
 289 /* The hardware table.  */
 290
 291 #define HW_ENT(n) m32r_cgen_hw_entries[n]
 292 static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] =
 293 {
 294   { HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0 },
 295   { HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0 },
 296   { HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0 },
 297   { HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0 },
 298   { HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0 },
 299   { HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0 },
 300   { HW_H_HI16, & HW_ENT (HW_H_HI16 + 1), "h-hi16", CGEN_ASM_KEYWORD, (PTR) 0 },
 301   { HW_H_SLO16, & HW_ENT (HW_H_SLO16 + 1), "h-slo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 302   { HW_H_ULO16, & HW_ENT (HW_H_ULO16 + 1), "h-ulo16", CGEN_ASM_KEYWORD, (PTR) 0 },
 303   { HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_gr },
 304   { HW_H_CR, & HW_ENT (HW_H_CR + 1), "h-cr", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_cr },
 305   { HW_H_ACCUM, & HW_ENT (HW_H_ACCUM + 1), "h-accum", CGEN_ASM_KEYWORD, (PTR) 0 },
 306 /* start-sanitize-m32rx */
 307   { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums },
 308 /* end-sanitize-m32rx */
 309 /* start-sanitize-m32rx */
 310   { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 },
 311 /* end-sanitize-m32rx */
 312   { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 },
 313   { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 },
 314   { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 },
 315   { HW_H_IE, & HW_ENT (HW_H_IE + 1), "h-ie", CGEN_ASM_KEYWORD, (PTR) 0 },
 316   { HW_H_BIE, & HW_ENT (HW_H_BIE + 1), "h-bie", CGEN_ASM_KEYWORD, (PTR) 0 },
 317   { HW_H_BCOND, & HW_ENT (HW_H_BCOND + 1), "h-bcond", CGEN_ASM_KEYWORD, (PTR) 0 },
 318   { HW_H_BPC, & HW_ENT (HW_H_BPC + 1), "h-bpc", CGEN_ASM_KEYWORD, (PTR) 0 },
 319   { HW_H_LOCK, & HW_ENT (HW_H_LOCK + 1), "h-lock", CGEN_ASM_KEYWORD, (PTR) 0 },
 320   { 0 }
 321 };
 322
 323 /* The operand table.  */
 324
 325 #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
 326 #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)]
 327
 328 const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] =
 329 {
 330 /* pc: program counter */
 331   { "pc", & HW_ENT (HW_H_PC), 0, 0,
 332     { 0, 0|(1<<CGEN_OPERAND_FAKE)|(1<<CGEN_OPERAND_PC), { 0 } }  },
 333 /* sr: source register */
 334   { "sr", & HW_ENT (HW_H_GR), 12, 4,
 335     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 336 /* dr: destination register */
 337   { "dr", & HW_ENT (HW_H_GR), 4, 4,
 338     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 339 /* src1: source register 1 */
 340   { "src1", & HW_ENT (HW_H_GR), 4, 4,
 341     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 342 /* src2: source register 2 */
 343   { "src2", & HW_ENT (HW_H_GR), 12, 4,
 344     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 345 /* scr: source control register */
 346   { "scr", & HW_ENT (HW_H_CR), 12, 4,
 347     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 348 /* dcr: destination control register */
 349   { "dcr", & HW_ENT (HW_H_CR), 4, 4,
 350     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 351 /* simm8: 8 bit signed immediate */
 352   { "simm8", & HW_ENT (HW_H_SINT), 8, 8,
 353     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 354 /* simm16: 16 bit signed immediate */
 355   { "simm16", & HW_ENT (HW_H_SINT), 16, 16,
 356     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX), { 0 } }  },
 357 /* uimm4: 4 bit trap number */
 358   { "uimm4", & HW_ENT (HW_H_UINT), 12, 4,
 359     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 360 /* uimm5: 5 bit shift count */
 361   { "uimm5", & HW_ENT (HW_H_UINT), 11, 5,
 362     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 363 /* uimm16: 16 bit unsigned immediate */
 364   { "uimm16", & HW_ENT (HW_H_UINT), 16, 16,
 365     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 366 /* start-sanitize-m32rx */
 367 /* imm1: 1 bit immediate */
 368   { "imm1", & HW_ENT (HW_H_UINT), 15, 1,
 369     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 370 /* end-sanitize-m32rx */
 371 /* start-sanitize-m32rx */
 372 /* accd: accumulator destination register */
 373   { "accd", & HW_ENT (HW_H_ACCUMS), 4, 2,
 374     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 375 /* end-sanitize-m32rx */
 376 /* start-sanitize-m32rx */
 377 /* accs: accumulator source register */
 378   { "accs", & HW_ENT (HW_H_ACCUMS), 12, 2,
 379     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 380 /* end-sanitize-m32rx */
 381 /* start-sanitize-m32rx */
 382 /* acc: accumulator reg (d) */
 383   { "acc", & HW_ENT (HW_H_ACCUMS), 8, 1,
 384     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 385 /* end-sanitize-m32rx */
 386 /* hash: # prefix */
 387   { "hash", & HW_ENT (HW_H_SINT), 0, 0,
 388     { 0, 0, { 0 } }  },
 389 /* hi16: high 16 bit immediate, sign optional */
 390   { "hi16", & HW_ENT (HW_H_HI16), 16, 16,
 391     { 0, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 392 /* slo16: 16 bit signed immediate, for low() */
 393   { "slo16", & HW_ENT (HW_H_SLO16), 16, 16,
 394     { 0, 0, { 0 } }  },
 395 /* ulo16: 16 bit unsigned immediate, for low() */
 396   { "ulo16", & HW_ENT (HW_H_ULO16), 16, 16,
 397     { 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 398 /* uimm24: 24 bit address */
 399   { "uimm24", & HW_ENT (HW_H_ADDR), 8, 24,
 400     { 0, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), { 0 } }  },
 401 /* disp8: 8 bit displacement */
 402   { "disp8", & HW_ENT (HW_H_IADDR), 8, 8,
 403     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 404 /* disp16: 16 bit displacement */
 405   { "disp16", & HW_ENT (HW_H_IADDR), 16, 16,
 406     { 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 407 /* disp24: 24 bit displacement */
 408   { "disp24", & HW_ENT (HW_H_IADDR), 8, 24,
 409     { 0, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } }  },
 410 /* condbit: condition bit */
 411   { "condbit", & HW_ENT (HW_H_COND), 0, 0,
 412     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 413 /* accum: accumulator */
 414   { "accum", & HW_ENT (HW_H_ACCUM), 0, 0,
 415     { 0, 0|(1<<CGEN_OPERAND_FAKE), { 0 } }  },
 416 };
 417
 418 /* Operand references.  */
 419
 420 #define INPUT CGEN_OPERAND_INSTANCE_INPUT
 421 #define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
 422
 423 static const CGEN_OPERAND_INSTANCE fmt_0_add_ops[] = {
 424   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 425   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 426   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 427   { 0 }
 428 };
 429
 430 static const CGEN_OPERAND_INSTANCE fmt_1_add3_ops[] = {
 431   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 432   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 433   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 434   { 0 }
 435 };
 436
 437 static const CGEN_OPERAND_INSTANCE fmt_2_and3_ops[] = {
 438   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 439   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 440   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 441   { 0 }
 442 };
 443
 444 static const CGEN_OPERAND_INSTANCE fmt_3_or3_ops[] = {
 445   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 446   { INPUT, & HW_ENT (HW_H_ULO16), CGEN_MODE_UHI, & OP_ENT (ULO16), 0 },
 447   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 448   { 0 }
 449 };
 450
 451 static const CGEN_OPERAND_INSTANCE fmt_4_addi_ops[] = {
 452   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 453   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 454   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 455   { 0 }
 456 };
 457
 458 static const CGEN_OPERAND_INSTANCE fmt_5_addv_ops[] = {
 459   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 460   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 461   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 462   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 463   { 0 }
 464 };
 465
 466 static const CGEN_OPERAND_INSTANCE fmt_6_addv3_ops[] = {
 467   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 468   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 469   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 470   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 471   { 0 }
 472 };
 473
 474 static const CGEN_OPERAND_INSTANCE fmt_7_addx_ops[] = {
 475   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 476   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 477   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 478   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 479   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 480   { 0 }
 481 };
 482
 483 static const CGEN_OPERAND_INSTANCE fmt_8_bc8_ops[] = {
 484   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 485   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 486   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 487   { 0 }
 488 };
 489
 490 static const CGEN_OPERAND_INSTANCE fmt_10_bc24_ops[] = {
 491   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 492   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 493   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 494   { 0 }
 495 };
 496
 497 static const CGEN_OPERAND_INSTANCE fmt_12_beq_ops[] = {
 498   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 499   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 500   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 501   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 502   { 0 }
 503 };
 504
 505 static const CGEN_OPERAND_INSTANCE fmt_13_beqz_ops[] = {
 506   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP16), 0 },
 507   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 508   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 509   { 0 }
 510 };
 511
 512 static const CGEN_OPERAND_INSTANCE fmt_14_bl8_ops[] = {
 513   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 514   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 515   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 516   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 517   { 0 }
 518 };
 519
 520 static const CGEN_OPERAND_INSTANCE fmt_15_bl24_ops[] = {
 521   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 522   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 523   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 524   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 525   { 0 }
 526 };
 527
 528 /* start-sanitize-m32rx */
 529 static const CGEN_OPERAND_INSTANCE fmt_16_bcl8_ops[] = {
 530   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 531   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 532   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 533   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 534   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 535   { 0 }
 536 };
 537
 538 /* end-sanitize-m32rx */
 539 /* start-sanitize-m32rx */
 540 static const CGEN_OPERAND_INSTANCE fmt_17_bcl24_ops[] = {
 541   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 542   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 543   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 544   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 545   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 546   { 0 }
 547 };
 548
 549 /* end-sanitize-m32rx */
 550 static const CGEN_OPERAND_INSTANCE fmt_18_bra8_ops[] = {
 551   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP8), 0 },
 552   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 553   { 0 }
 554 };
 555
 556 static const CGEN_OPERAND_INSTANCE fmt_19_bra24_ops[] = {
 557   { INPUT, & HW_ENT (HW_H_IADDR), CGEN_MODE_VM, & OP_ENT (DISP24), 0 },
 558   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 559   { 0 }
 560 };
 561
 562 static const CGEN_OPERAND_INSTANCE fmt_20_cmp_ops[] = {
 563   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 564   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 565   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 566   { 0 }
 567 };
 568
 569 static const CGEN_OPERAND_INSTANCE fmt_21_cmpi_ops[] = {
 570   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 571   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 572   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 573   { 0 }
 574 };
 575
 576 static const CGEN_OPERAND_INSTANCE fmt_22_cmpui_ops[] = {
 577   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 578   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM16), 0 },
 579   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 580   { 0 }
 581 };
 582
 583 /* start-sanitize-m32rx */
 584 static const CGEN_OPERAND_INSTANCE fmt_23_cmpz_ops[] = {
 585   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 586   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 587   { 0 }
 588 };
 589
 590 /* end-sanitize-m32rx */
 591 static const CGEN_OPERAND_INSTANCE fmt_24_div_ops[] = {
 592   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 593   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 594   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 595   { 0 }
 596 };
 597
 598 /* start-sanitize-m32rx */
 599 static const CGEN_OPERAND_INSTANCE fmt_25_jc_ops[] = {
 600   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 601   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 602   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 603   { 0 }
 604 };
 605
 606 /* end-sanitize-m32rx */
 607 static const CGEN_OPERAND_INSTANCE fmt_26_jl_ops[] = {
 608   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 609   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 610   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 611   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14 },
 612   { 0 }
 613 };
 614
 615 static const CGEN_OPERAND_INSTANCE fmt_27_jmp_ops[] = {
 616   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 617   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 618   { 0 }
 619 };
 620
 621 static const CGEN_OPERAND_INSTANCE fmt_28_ld_ops[] = {
 622   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 623   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 624   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 625   { 0 }
 626 };
 627
 628 static const CGEN_OPERAND_INSTANCE fmt_30_ld_d_ops[] = {
 629   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 630   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 631   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 632   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 633   { 0 }
 634 };
 635
 636 static const CGEN_OPERAND_INSTANCE fmt_32_ldb_ops[] = {
 637   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 638   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 639   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 640   { 0 }
 641 };
 642
 643 static const CGEN_OPERAND_INSTANCE fmt_33_ldb_d_ops[] = {
 644   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 645   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 646   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 647   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 648   { 0 }
 649 };
 650
 651 static const CGEN_OPERAND_INSTANCE fmt_34_ldh_ops[] = {
 652   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 653   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 654   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 655   { 0 }
 656 };
 657
 658 static const CGEN_OPERAND_INSTANCE fmt_35_ldh_d_ops[] = {
 659   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 660   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 661   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 662   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 663   { 0 }
 664 };
 665
 666 static const CGEN_OPERAND_INSTANCE fmt_36_ld_plus_ops[] = {
 667   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 668   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 669   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 670   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 671   { 0 }
 672 };
 673
 674 static const CGEN_OPERAND_INSTANCE fmt_37_ld24_ops[] = {
 675   { INPUT, & HW_ENT (HW_H_ADDR), CGEN_MODE_VM, & OP_ENT (UIMM24), 0 },
 676   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 677   { 0 }
 678 };
 679
 680 static const CGEN_OPERAND_INSTANCE fmt_38_ldi8_ops[] = {
 681   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM8), 0 },
 682   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 683   { 0 }
 684 };
 685
 686 static const CGEN_OPERAND_INSTANCE fmt_39_ldi16_ops[] = {
 687   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 688   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 689   { 0 }
 690 };
 691
 692 static const CGEN_OPERAND_INSTANCE fmt_40_lock_ops[] = {
 693   { INPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 694   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 695   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 696   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 697   { 0 }
 698 };
 699
 700 static const CGEN_OPERAND_INSTANCE fmt_41_machi_ops[] = {
 701   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 702   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 703   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 704   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 705   { 0 }
 706 };
 707
 708 /* start-sanitize-m32rx */
 709 static const CGEN_OPERAND_INSTANCE fmt_42_machi_a_ops[] = {
 710   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 711   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 712   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 713   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 714   { 0 }
 715 };
 716
 717 /* end-sanitize-m32rx */
 718 static const CGEN_OPERAND_INSTANCE fmt_43_mulhi_ops[] = {
 719   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 720   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 721   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 722   { 0 }
 723 };
 724
 725 /* start-sanitize-m32rx */
 726 static const CGEN_OPERAND_INSTANCE fmt_44_mulhi_a_ops[] = {
 727   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 728   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 729   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACC), 0 },
 730   { 0 }
 731 };
 732
 733 /* end-sanitize-m32rx */
 734 static const CGEN_OPERAND_INSTANCE fmt_45_mv_ops[] = {
 735   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 736   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 737   { 0 }
 738 };
 739
 740 static const CGEN_OPERAND_INSTANCE fmt_46_mvfachi_ops[] = {
 741   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 742   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 743   { 0 }
 744 };
 745
 746 /* start-sanitize-m32rx */
 747 static const CGEN_OPERAND_INSTANCE fmt_47_mvfachi_a_ops[] = {
 748   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 749   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 750   { 0 }
 751 };
 752
 753 /* end-sanitize-m32rx */
 754 static const CGEN_OPERAND_INSTANCE fmt_48_mvfc_ops[] = {
 755   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (SCR), 0 },
 756   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 757   { 0 }
 758 };
 759
 760 static const CGEN_OPERAND_INSTANCE fmt_49_mvtachi_ops[] = {
 761   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 762   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 763   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 764   { 0 }
 765 };
 766
 767 /* start-sanitize-m32rx */
 768 static const CGEN_OPERAND_INSTANCE fmt_50_mvtachi_a_ops[] = {
 769   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 770   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 771   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 772   { 0 }
 773 };
 774
 775 /* end-sanitize-m32rx */
 776 static const CGEN_OPERAND_INSTANCE fmt_51_mvtc_ops[] = {
 777   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 778   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_USI, & OP_ENT (DCR), 0 },
 779   { 0 }
 780 };
 781
 782 static const CGEN_OPERAND_INSTANCE fmt_53_rac_ops[] = {
 783   { INPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 784   { OUTPUT, & HW_ENT (HW_H_ACCUM), CGEN_MODE_DI, 0, 0 },
 785   { 0 }
 786 };
 787
 788 /* start-sanitize-m32rx */
 789 static const CGEN_OPERAND_INSTANCE fmt_56_rac_dsi_ops[] = {
 790   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCS), 0 },
 791   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (IMM1), 0 },
 792   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, & OP_ENT (ACCD), 0 },
 793   { 0 }
 794 };
 795
 796 /* end-sanitize-m32rx */
 797 static const CGEN_OPERAND_INSTANCE fmt_57_rte_ops[] = {
 798   { INPUT, & HW_ENT (HW_H_BCOND), CGEN_MODE_VM, 0, 0 },
 799   { INPUT, & HW_ENT (HW_H_BIE), CGEN_MODE_VM, 0, 0 },
 800   { INPUT, & HW_ENT (HW_H_BPC), CGEN_MODE_VM, 0, 0 },
 801   { INPUT, & HW_ENT (HW_H_BSM), CGEN_MODE_VM, 0, 0 },
 802   { OUTPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 803   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 804   { OUTPUT, & HW_ENT (HW_H_IE), CGEN_MODE_VM, 0, 0 },
 805   { OUTPUT, & HW_ENT (HW_H_SM), CGEN_MODE_VM, 0, 0 },
 806   { 0 }
 807 };
 808
 809 static const CGEN_OPERAND_INSTANCE fmt_58_seth_ops[] = {
 810   { INPUT, & HW_ENT (HW_H_HI16), CGEN_MODE_UHI, & OP_ENT (HI16), 0 },
 811   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 812   { 0 }
 813 };
 814
 815 static const CGEN_OPERAND_INSTANCE fmt_59_sll3_ops[] = {
 816   { INPUT, & HW_ENT (HW_H_SINT), CGEN_MODE_SI, & OP_ENT (SIMM16), 0 },
 817   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 818   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 819   { 0 }
 820 };
 821
 822 static const CGEN_OPERAND_INSTANCE fmt_60_slli_ops[] = {
 823   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 824   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM5), 0 },
 825   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 826   { 0 }
 827 };
 828
 829 static const CGEN_OPERAND_INSTANCE fmt_61_st_ops[] = {
 830   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 831   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 832   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 833   { 0 }
 834 };
 835
 836 static const CGEN_OPERAND_INSTANCE fmt_63_st_d_ops[] = {
 837   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 838   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 839   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 840   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 841   { 0 }
 842 };
 843
 844 static const CGEN_OPERAND_INSTANCE fmt_65_stb_ops[] = {
 845   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 846   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 847   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 848   { 0 }
 849 };
 850
 851 static const CGEN_OPERAND_INSTANCE fmt_66_stb_d_ops[] = {
 852   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 853   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 854   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 855   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0 },
 856   { 0 }
 857 };
 858
 859 static const CGEN_OPERAND_INSTANCE fmt_67_sth_ops[] = {
 860   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 861   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 862   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 863   { 0 }
 864 };
 865
 866 static const CGEN_OPERAND_INSTANCE fmt_68_sth_d_ops[] = {
 867   { INPUT, & HW_ENT (HW_H_SLO16), CGEN_MODE_HI, & OP_ENT (SLO16), 0 },
 868   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 869   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 870   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0 },
 871   { 0 }
 872 };
 873
 874 static const CGEN_OPERAND_INSTANCE fmt_69_st_plus_ops[] = {
 875   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 876   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 877   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 878   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 879   { 0 }
 880 };
 881
 882 static const CGEN_OPERAND_INSTANCE fmt_70_trap_ops[] = {
 883   { INPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 884   { INPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 885   { INPUT, & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (UIMM4), 0 },
 886   { OUTPUT, & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0 },
 887   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 0 },
 888   { OUTPUT, & HW_ENT (HW_H_CR), CGEN_MODE_SI, 0, 6 },
 889   { 0 }
 890 };
 891
 892 static const CGEN_OPERAND_INSTANCE fmt_71_unlock_ops[] = {
 893   { INPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 894   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 895   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 896   { OUTPUT, & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0 },
 897   { OUTPUT, & HW_ENT (HW_H_LOCK), CGEN_MODE_UBI, 0, 0 },
 898   { 0 }
 899 };
 900
 901 /* start-sanitize-m32rx */
 902 static const CGEN_OPERAND_INSTANCE fmt_74_satb_ops[] = {
 903   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 904   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 905   { 0 }
 906 };
 907
 908 /* end-sanitize-m32rx */
 909 /* start-sanitize-m32rx */
 910 static const CGEN_OPERAND_INSTANCE fmt_75_sat_ops[] = {
 911   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 912   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SR), 0 },
 913   { OUTPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DR), 0 },
 914   { 0 }
 915 };
 916
 917 /* end-sanitize-m32rx */
 918 /* start-sanitize-m32rx */
 919 static const CGEN_OPERAND_INSTANCE fmt_76_sadd_ops[] = {
 920   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 921   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 922   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 0 },
 923   { 0 }
 924 };
 925
 926 /* end-sanitize-m32rx */
 927 /* start-sanitize-m32rx */
 928 static const CGEN_OPERAND_INSTANCE fmt_77_macwu1_ops[] = {
 929   { INPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 930   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 931   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 932   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 933   { 0 }
 934 };
 935
 936 /* end-sanitize-m32rx */
 937 /* start-sanitize-m32rx */
 938 static const CGEN_OPERAND_INSTANCE fmt_78_mulwu1_ops[] = {
 939   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0 },
 940   { INPUT, & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0 },
 941   { OUTPUT, & HW_ENT (HW_H_ACCUMS), CGEN_MODE_DI, 0, 1 },
 942   { 0 }
 943 };
 944
 945 /* end-sanitize-m32rx */
 946 /* start-sanitize-m32rx */
 947 static const CGEN_OPERAND_INSTANCE fmt_79_sc_ops[] = {
 948   { INPUT, & HW_ENT (HW_H_COND), CGEN_MODE_UBI, 0, 0 },
 949   { 0 }
 950 };
 951
 952 /* end-sanitize-m32rx */
 953 #undef INPUT
 954 #undef OUTPUT
 955
 956 #define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
 957 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
 958 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 959
 960 /* The instruction table.  */
 961
 962 const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] =
 963 {
 964   /* null first entry, end of all hash chains */
 965   { { 0 }, 0 },
 966 /* add $dr,$sr */
 967   {
 968     { 1, 1, 1, 1 },
 969     "add", "add",
 970     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 971     { 16, 16, 0xf0f0 }, 0xa0,
 972     & fmt_0_add_ops[0],
 973     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 974   },
 975 /* add3 $dr,$sr,$hash$slo16 */
 976   {
 977     { 1, 1, 1, 1 },
 978     "add3", "add3",
 979     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 },
 980     { 32, 32, 0xf0f00000 }, 0x80a00000,
 981     & fmt_1_add3_ops[0],
 982     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
 983   },
 984 /* and $dr,$sr */
 985   {
 986     { 1, 1, 1, 1 },
 987     "and", "and",
 988     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
 989     { 16, 16, 0xf0f0 }, 0xc0,
 990     & fmt_0_add_ops[0],
 991     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
 992   },
 993 /* and3 $dr,$sr,$uimm16 */
 994   {
 995     { 1, 1, 1, 1 },
 996     "and3", "and3",
 997     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
 998     { 32, 32, 0xf0f00000 }, 0x80c00000,
 999     & fmt_2_and3_ops[0],
1000     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1001   },
1002 /* or $dr,$sr */
1003   {
1004     { 1, 1, 1, 1 },
1005     "or", "or",
1006     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1007     { 16, 16, 0xf0f0 }, 0xe0,
1008     & fmt_0_add_ops[0],
1009     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1010   },
1011 /* or3 $dr,$sr,$hash$ulo16 */
1012   {
1013     { 1, 1, 1, 1 },
1014     "or3", "or3",
1015     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 },
1016     { 32, 32, 0xf0f00000 }, 0x80e00000,
1017     & fmt_3_or3_ops[0],
1018     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1019   },
1020 /* xor $dr,$sr */
1021   {
1022     { 1, 1, 1, 1 },
1023     "xor", "xor",
1024     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1025     { 16, 16, 0xf0f0 }, 0xd0,
1026     & fmt_0_add_ops[0],
1027     { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<<MACH_M32R), PIPE_OS } }
1028   },
1029 /* xor3 $dr,$sr,$uimm16 */
1030   {
1031     { 1, 1, 1, 1 },
1032     "xor3", "xor3",
1033     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 },
1034     { 32, 32, 0xf0f00000 }, 0x80d00000,
1035     & fmt_2_and3_ops[0],
1036     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1037   },
1038 /* addi $dr,$simm8 */
1039   {
1040     { 1, 1, 1, 1 },
1041     "addi", "addi",
1042     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1043     { 16, 16, 0xf000 }, 0x4000,
1044     & fmt_4_addi_ops[0],
1045     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1046   },
1047 /* addv $dr,$sr */
1048   {
1049     { 1, 1, 1, 1 },
1050     "addv", "addv",
1051     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1052     { 16, 16, 0xf0f0 }, 0x80,
1053     & fmt_5_addv_ops[0],
1054     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1055   },
1056 /* addv3 $dr,$sr,$simm16 */
1057   {
1058     { 1, 1, 1, 1 },
1059     "addv3", "addv3",
1060     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
1061     { 32, 32, 0xf0f00000 }, 0x80800000,
1062     & fmt_6_addv3_ops[0],
1063     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1064   },
1065 /* addx $dr,$sr */
1066   {
1067     { 1, 1, 1, 1 },
1068     "addx", "addx",
1069     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1070     { 16, 16, 0xf0f0 }, 0x90,
1071     & fmt_7_addx_ops[0],
1072     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1073   },
1074 /* bc $disp8 */
1075   {
1076     { 1, 1, 1, 1 },
1077     "bc8", "bc",
1078     { MNEM, ' ', OP (DISP8), 0 },
1079     { 16, 16, 0xff00 }, 0x7c00,
1080     & fmt_8_bc8_ops[0],
1081     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1082   },
1083 /* bc.s $disp8 */
1084   {
1085     { 1, 1, 1, 1 },
1086     "bc8.s", "bc.s",
1087     { MNEM, ' ', OP (DISP8), 0 },
1088     { 16, 16, 0xff00 }, 0x7c00,
1089     0,
1090     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1091   },
1092 /* bc $disp24 */
1093   {
1094     { 1, 1, 1, 1 },
1095     "bc24", "bc",
1096     { MNEM, ' ', OP (DISP24), 0 },
1097     { 32, 32, 0xff000000 }, 0xfc000000,
1098     & fmt_10_bc24_ops[0],
1099     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1100   },
1101 /* bc.l $disp24 */
1102   {
1103     { 1, 1, 1, 1 },
1104     "bc24.l", "bc.l",
1105     { MNEM, ' ', OP (DISP24), 0 },
1106     { 32, 32, 0xff000000 }, 0xfc000000,
1107     0,
1108     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1109   },
1110 /* beq $src1,$src2,$disp16 */
1111   {
1112     { 1, 1, 1, 1 },
1113     "beq", "beq",
1114     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1115     { 32, 32, 0xf0f00000 }, 0xb0000000,
1116     & fmt_12_beq_ops[0],
1117     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1118   },
1119 /* beqz $src2,$disp16 */
1120   {
1121     { 1, 1, 1, 1 },
1122     "beqz", "beqz",
1123     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1124     { 32, 32, 0xfff00000 }, 0xb0800000,
1125     & fmt_13_beqz_ops[0],
1126     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1127   },
1128 /* bgez $src2,$disp16 */
1129   {
1130     { 1, 1, 1, 1 },
1131     "bgez", "bgez",
1132     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1133     { 32, 32, 0xfff00000 }, 0xb0b00000,
1134     & fmt_13_beqz_ops[0],
1135     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1136   },
1137 /* bgtz $src2,$disp16 */
1138   {
1139     { 1, 1, 1, 1 },
1140     "bgtz", "bgtz",
1141     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1142     { 32, 32, 0xfff00000 }, 0xb0d00000,
1143     & fmt_13_beqz_ops[0],
1144     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1145   },
1146 /* blez $src2,$disp16 */
1147   {
1148     { 1, 1, 1, 1 },
1149     "blez", "blez",
1150     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1151     { 32, 32, 0xfff00000 }, 0xb0c00000,
1152     & fmt_13_beqz_ops[0],
1153     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1154   },
1155 /* bltz $src2,$disp16 */
1156   {
1157     { 1, 1, 1, 1 },
1158     "bltz", "bltz",
1159     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1160     { 32, 32, 0xfff00000 }, 0xb0a00000,
1161     & fmt_13_beqz_ops[0],
1162     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1163   },
1164 /* bnez $src2,$disp16 */
1165   {
1166     { 1, 1, 1, 1 },
1167     "bnez", "bnez",
1168     { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 },
1169     { 32, 32, 0xfff00000 }, 0xb0900000,
1170     & fmt_13_beqz_ops[0],
1171     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1172   },
1173 /* bl $disp8 */
1174   {
1175     { 1, 1, 1, 1 },
1176     "bl8", "bl",
1177     { MNEM, ' ', OP (DISP8), 0 },
1178     { 16, 16, 0xff00 }, 0x7e00,
1179     & fmt_14_bl8_ops[0],
1180     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1181   },
1182 /* bl.s $disp8 */
1183   {
1184     { 1, 1, 1, 1 },
1185     "bl8.s", "bl.s",
1186     { MNEM, ' ', OP (DISP8), 0 },
1187     { 16, 16, 0xff00 }, 0x7e00,
1188     0,
1189     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1190   },
1191 /* bl $disp24 */
1192   {
1193     { 1, 1, 1, 1 },
1194     "bl24", "bl",
1195     { MNEM, ' ', OP (DISP24), 0 },
1196     { 32, 32, 0xff000000 }, 0xfe000000,
1197     & fmt_15_bl24_ops[0],
1198     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1199   },
1200 /* bl.l $disp24 */
1201   {
1202     { 1, 1, 1, 1 },
1203     "bl24.l", "bl.l",
1204     { MNEM, ' ', OP (DISP24), 0 },
1205     { 32, 32, 0xff000000 }, 0xfe000000,
1206     0,
1207     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1208   },
1209 /* start-sanitize-m32rx */
1210 /* bcl $disp8 */
1211   {
1212     { 1, 1, 1, 1 },
1213     "bcl8", "bcl",
1214     { MNEM, ' ', OP (DISP8), 0 },
1215     { 16, 16, 0xff00 }, 0x7800,
1216     & fmt_16_bcl8_ops[0],
1217     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1218   },
1219 /* end-sanitize-m32rx */
1220 /* start-sanitize-m32rx */
1221 /* bcl.s $disp8 */
1222   {
1223     { 1, 1, 1, 1 },
1224     "bcl8.s", "bcl.s",
1225     { MNEM, ' ', OP (DISP8), 0 },
1226     { 16, 16, 0xff00 }, 0x7800,
1227     0,
1228     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1229   },
1230 /* end-sanitize-m32rx */
1231 /* start-sanitize-m32rx */
1232 /* bcl $disp24 */
1233   {
1234     { 1, 1, 1, 1 },
1235     "bcl24", "bcl",
1236     { MNEM, ' ', OP (DISP24), 0 },
1237     { 32, 32, 0xff000000 }, 0xf8000000,
1238     & fmt_17_bcl24_ops[0],
1239     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1240   },
1241 /* end-sanitize-m32rx */
1242 /* start-sanitize-m32rx */
1243 /* bcl.l $disp24 */
1244   {
1245     { 1, 1, 1, 1 },
1246     "bcl24.l", "bcl.l",
1247     { MNEM, ' ', OP (DISP24), 0 },
1248     { 32, 32, 0xff000000 }, 0xf8000000,
1249     0,
1250     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1251   },
1252 /* end-sanitize-m32rx */
1253 /* bnc $disp8 */
1254   {
1255     { 1, 1, 1, 1 },
1256     "bnc8", "bnc",
1257     { MNEM, ' ', OP (DISP8), 0 },
1258     { 16, 16, 0xff00 }, 0x7d00,
1259     & fmt_8_bc8_ops[0],
1260     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1261   },
1262 /* bnc.s $disp8 */
1263   {
1264     { 1, 1, 1, 1 },
1265     "bnc8.s", "bnc.s",
1266     { MNEM, ' ', OP (DISP8), 0 },
1267     { 16, 16, 0xff00 }, 0x7d00,
1268     0,
1269     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_O } }
1270   },
1271 /* bnc $disp24 */
1272   {
1273     { 1, 1, 1, 1 },
1274     "bnc24", "bnc",
1275     { MNEM, ' ', OP (DISP24), 0 },
1276     { 32, 32, 0xff000000 }, 0xfd000000,
1277     & fmt_10_bc24_ops[0],
1278     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1279   },
1280 /* bnc.l $disp24 */
1281   {
1282     { 1, 1, 1, 1 },
1283     "bnc24.l", "bnc.l",
1284     { MNEM, ' ', OP (DISP24), 0 },
1285     { 32, 32, 0xff000000 }, 0xfd000000,
1286     0,
1287     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1288   },
1289 /* bne $src1,$src2,$disp16 */
1290   {
1291     { 1, 1, 1, 1 },
1292     "bne", "bne",
1293     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 },
1294     { 32, 32, 0xf0f00000 }, 0xb0100000,
1295     & fmt_12_beq_ops[0],
1296     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1297   },
1298 /* bra $disp8 */
1299   {
1300     { 1, 1, 1, 1 },
1301     "bra8", "bra",
1302     { MNEM, ' ', OP (DISP8), 0 },
1303     { 16, 16, 0xff00 }, 0x7f00,
1304     & fmt_18_bra8_ops[0],
1305     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1306   },
1307 /* bra.s $disp8 */
1308   {
1309     { 1, 1, 1, 1 },
1310     "bra8.s", "bra.s",
1311     { MNEM, ' ', OP (DISP8), 0 },
1312     { 16, 16, 0xff00 }, 0x7f00,
1313     0,
1314     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1315   },
1316 /* bra $disp24 */
1317   {
1318     { 1, 1, 1, 1 },
1319     "bra24", "bra",
1320     { MNEM, ' ', OP (DISP24), 0 },
1321     { 32, 32, 0xff000000 }, 0xff000000,
1322     & fmt_19_bra24_ops[0],
1323     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1324   },
1325 /* bra.l $disp24 */
1326   {
1327     { 1, 1, 1, 1 },
1328     "bra24.l", "bra.l",
1329     { MNEM, ' ', OP (DISP24), 0 },
1330     { 32, 32, 0xff000000 }, 0xff000000,
1331     0,
1332     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_NONE } }
1333   },
1334 /* start-sanitize-m32rx */
1335 /* bncl $disp8 */
1336   {
1337     { 1, 1, 1, 1 },
1338     "bncl8", "bncl",
1339     { MNEM, ' ', OP (DISP8), 0 },
1340     { 16, 16, 0xff00 }, 0x7900,
1341     & fmt_16_bcl8_ops[0],
1342     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1343   },
1344 /* end-sanitize-m32rx */
1345 /* start-sanitize-m32rx */
1346 /* bncl.s $disp8 */
1347   {
1348     { 1, 1, 1, 1 },
1349     "bncl8.s", "bncl.s",
1350     { MNEM, ' ', OP (DISP8), 0 },
1351     { 16, 16, 0xff00 }, 0x7900,
1352     0,
1353     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1354   },
1355 /* end-sanitize-m32rx */
1356 /* start-sanitize-m32rx */
1357 /* bncl $disp24 */
1358   {
1359     { 1, 1, 1, 1 },
1360     "bncl24", "bncl",
1361     { MNEM, ' ', OP (DISP24), 0 },
1362     { 32, 32, 0xff000000 }, 0xf9000000,
1363     & fmt_17_bcl24_ops[0],
1364     { CGEN_INSN_NBOOL_ATTRS, 0|A(RELAX)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1365   },
1366 /* end-sanitize-m32rx */
1367 /* start-sanitize-m32rx */
1368 /* bncl.l $disp24 */
1369   {
1370     { 1, 1, 1, 1 },
1371     "bncl24.l", "bncl.l",
1372     { MNEM, ' ', OP (DISP24), 0 },
1373     { 32, 32, 0xff000000 }, 0xf9000000,
1374     0,
1375     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
1376   },
1377 /* end-sanitize-m32rx */
1378 /* cmp $src1,$src2 */
1379   {
1380     { 1, 1, 1, 1 },
1381     "cmp", "cmp",
1382     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1383     { 16, 16, 0xf0f0 }, 0x40,
1384     & fmt_20_cmp_ops[0],
1385     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1386   },
1387 /* cmpi $src2,$simm16 */
1388   {
1389     { 1, 1, 1, 1 },
1390     "cmpi", "cmpi",
1391     { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 },
1392     { 32, 32, 0xfff00000 }, 0x80400000,
1393     & fmt_21_cmpi_ops[0],
1394     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1395   },
1396 /* cmpu $src1,$src2 */
1397   {
1398     { 1, 1, 1, 1 },
1399     "cmpu", "cmpu",
1400     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1401     { 16, 16, 0xf0f0 }, 0x50,
1402     & fmt_20_cmp_ops[0],
1403     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1404   },
1405 /* cmpui $src2,$uimm16 */
1406   {
1407     { 1, 1, 1, 1 },
1408     "cmpui", "cmpui",
1409     { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 },
1410     { 32, 32, 0xfff00000 }, 0x80500000,
1411     & fmt_22_cmpui_ops[0],
1412     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1413   },
1414 /* start-sanitize-m32rx */
1415 /* cmpeq $src1,$src2 */
1416   {
1417     { 1, 1, 1, 1 },
1418     "cmpeq", "cmpeq",
1419     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1420     { 16, 16, 0xf0f0 }, 0x60,
1421     & fmt_20_cmp_ops[0],
1422     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1423   },
1424 /* end-sanitize-m32rx */
1425 /* start-sanitize-m32rx */
1426 /* cmpz $src2 */
1427   {
1428     { 1, 1, 1, 1 },
1429     "cmpz", "cmpz",
1430     { MNEM, ' ', OP (SRC2), 0 },
1431     { 16, 16, 0xfff0 }, 0x70,
1432     & fmt_23_cmpz_ops[0],
1433     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
1434   },
1435 /* end-sanitize-m32rx */
1436 /* div $dr,$sr */
1437   {
1438     { 1, 1, 1, 1 },
1439     "div", "div",
1440     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1441     { 32, 32, 0xf0f0ffff }, 0x90000000,
1442     & fmt_24_div_ops[0],
1443     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1444   },
1445 /* divu $dr,$sr */
1446   {
1447     { 1, 1, 1, 1 },
1448     "divu", "divu",
1449     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1450     { 32, 32, 0xf0f0ffff }, 0x90100000,
1451     & fmt_24_div_ops[0],
1452     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1453   },
1454 /* rem $dr,$sr */
1455   {
1456     { 1, 1, 1, 1 },
1457     "rem", "rem",
1458     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1459     { 32, 32, 0xf0f0ffff }, 0x90200000,
1460     & fmt_24_div_ops[0],
1461     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1462   },
1463 /* remu $dr,$sr */
1464   {
1465     { 1, 1, 1, 1 },
1466     "remu", "remu",
1467     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1468     { 32, 32, 0xf0f0ffff }, 0x90300000,
1469     & fmt_24_div_ops[0],
1470     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1471   },
1472 /* start-sanitize-m32rx */
1473 /* divh $dr,$sr */
1474   {
1475     { 1, 1, 1, 1 },
1476     "divh", "divh",
1477     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1478     { 32, 32, 0xf0f0ffff }, 0x90000010,
1479     & fmt_24_div_ops[0],
1480     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
1481   },
1482 /* end-sanitize-m32rx */
1483 /* start-sanitize-m32rx */
1484 /* jc $sr */
1485   {
1486     { 1, 1, 1, 1 },
1487     "jc", "jc",
1488     { MNEM, ' ', OP (SR), 0 },
1489     { 16, 16, 0xfff0 }, 0x1cc0,
1490     & fmt_25_jc_ops[0],
1491     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1492   },
1493 /* end-sanitize-m32rx */
1494 /* start-sanitize-m32rx */
1495 /* jnc $sr */
1496   {
1497     { 1, 1, 1, 1 },
1498     "jnc", "jnc",
1499     { MNEM, ' ', OP (SR), 0 },
1500     { 16, 16, 0xfff0 }, 0x1dc0,
1501     & fmt_25_jc_ops[0],
1502     { CGEN_INSN_NBOOL_ATTRS, 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
1503   },
1504 /* end-sanitize-m32rx */
1505 /* jl $sr */
1506   {
1507     { 1, 1, 1, 1 },
1508     "jl", "jl",
1509     { MNEM, ' ', OP (SR), 0 },
1510     { 16, 16, 0xfff0 }, 0x1ec0,
1511     & fmt_26_jl_ops[0],
1512     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1513   },
1514 /* jmp $sr */
1515   {
1516     { 1, 1, 1, 1 },
1517     "jmp", "jmp",
1518     { MNEM, ' ', OP (SR), 0 },
1519     { 16, 16, 0xfff0 }, 0x1fc0,
1520     & fmt_27_jmp_ops[0],
1521     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
1522   },
1523 /* ld $dr,@$sr */
1524   {
1525     { 1, 1, 1, 1 },
1526     "ld", "ld",
1527     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1528     { 16, 16, 0xf0f0 }, 0x20c0,
1529     & fmt_28_ld_ops[0],
1530     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1531   },
1532 /* ld $dr,@($sr) */
1533   {
1534     { 1, 1, 1, 1 },
1535     "ld-2", "ld",
1536     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1537     { 16, 16, 0xf0f0 }, 0x20c0,
1538     0,
1539     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1540   },
1541 /* ld $dr,@($slo16,$sr) */
1542   {
1543     { 1, 1, 1, 1 },
1544     "ld-d", "ld",
1545     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1546     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1547     & fmt_30_ld_d_ops[0],
1548     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1549   },
1550 /* ld $dr,@($sr,$slo16) */
1551   {
1552     { 1, 1, 1, 1 },
1553     "ld-d2", "ld",
1554     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1555     { 32, 32, 0xf0f00000 }, 0xa0c00000,
1556     0,
1557     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1558   },
1559 /* ldb $dr,@$sr */
1560   {
1561     { 1, 1, 1, 1 },
1562     "ldb", "ldb",
1563     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1564     { 16, 16, 0xf0f0 }, 0x2080,
1565     & fmt_32_ldb_ops[0],
1566     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1567   },
1568 /* ldb $dr,@($sr) */
1569   {
1570     { 1, 1, 1, 1 },
1571     "ldb-2", "ldb",
1572     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1573     { 16, 16, 0xf0f0 }, 0x2080,
1574     0,
1575     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1576   },
1577 /* ldb $dr,@($slo16,$sr) */
1578   {
1579     { 1, 1, 1, 1 },
1580     "ldb-d", "ldb",
1581     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1582     { 32, 32, 0xf0f00000 }, 0xa0800000,
1583     & fmt_33_ldb_d_ops[0],
1584     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1585   },
1586 /* ldb $dr,@($sr,$slo16) */
1587   {
1588     { 1, 1, 1, 1 },
1589     "ldb-d2", "ldb",
1590     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1591     { 32, 32, 0xf0f00000 }, 0xa0800000,
1592     0,
1593     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1594   },
1595 /* ldh $dr,@$sr */
1596   {
1597     { 1, 1, 1, 1 },
1598     "ldh", "ldh",
1599     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1600     { 16, 16, 0xf0f0 }, 0x20a0,
1601     & fmt_34_ldh_ops[0],
1602     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1603   },
1604 /* ldh $dr,@($sr) */
1605   {
1606     { 1, 1, 1, 1 },
1607     "ldh-2", "ldh",
1608     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1609     { 16, 16, 0xf0f0 }, 0x20a0,
1610     0,
1611     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1612   },
1613 /* ldh $dr,@($slo16,$sr) */
1614   {
1615     { 1, 1, 1, 1 },
1616     "ldh-d", "ldh",
1617     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1618     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1619     & fmt_35_ldh_d_ops[0],
1620     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1621   },
1622 /* ldh $dr,@($sr,$slo16) */
1623   {
1624     { 1, 1, 1, 1 },
1625     "ldh-d2", "ldh",
1626     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1627     { 32, 32, 0xf0f00000 }, 0xa0a00000,
1628     0,
1629     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1630   },
1631 /* ldub $dr,@$sr */
1632   {
1633     { 1, 1, 1, 1 },
1634     "ldub", "ldub",
1635     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1636     { 16, 16, 0xf0f0 }, 0x2090,
1637     & fmt_32_ldb_ops[0],
1638     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1639   },
1640 /* ldub $dr,@($sr) */
1641   {
1642     { 1, 1, 1, 1 },
1643     "ldub-2", "ldub",
1644     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1645     { 16, 16, 0xf0f0 }, 0x2090,
1646     0,
1647     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1648   },
1649 /* ldub $dr,@($slo16,$sr) */
1650   {
1651     { 1, 1, 1, 1 },
1652     "ldub-d", "ldub",
1653     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1654     { 32, 32, 0xf0f00000 }, 0xa0900000,
1655     & fmt_33_ldb_d_ops[0],
1656     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1657   },
1658 /* ldub $dr,@($sr,$slo16) */
1659   {
1660     { 1, 1, 1, 1 },
1661     "ldub-d2", "ldub",
1662     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1663     { 32, 32, 0xf0f00000 }, 0xa0900000,
1664     0,
1665     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1666   },
1667 /* lduh $dr,@$sr */
1668   {
1669     { 1, 1, 1, 1 },
1670     "lduh", "lduh",
1671     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1672     { 16, 16, 0xf0f0 }, 0x20b0,
1673     & fmt_34_ldh_ops[0],
1674     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1675   },
1676 /* lduh $dr,@($sr) */
1677   {
1678     { 1, 1, 1, 1 },
1679     "lduh-2", "lduh",
1680     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 },
1681     { 16, 16, 0xf0f0 }, 0x20b0,
1682     0,
1683     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
1684   },
1685 /* lduh $dr,@($slo16,$sr) */
1686   {
1687     { 1, 1, 1, 1 },
1688     "lduh-d", "lduh",
1689     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 },
1690     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1691     & fmt_35_ldh_d_ops[0],
1692     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1693   },
1694 /* lduh $dr,@($sr,$slo16) */
1695   {
1696     { 1, 1, 1, 1 },
1697     "lduh-d2", "lduh",
1698     { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 },
1699     { 32, 32, 0xf0f00000 }, 0xa0b00000,
1700     0,
1701     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1702   },
1703 /* ld $dr,@$sr+ */
1704   {
1705     { 1, 1, 1, 1 },
1706     "ld-plus", "ld",
1707     { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 },
1708     { 16, 16, 0xf0f0 }, 0x20e0,
1709     & fmt_36_ld_plus_ops[0],
1710     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1711   },
1712 /* ld24 $dr,$uimm24 */
1713   {
1714     { 1, 1, 1, 1 },
1715     "ld24", "ld24",
1716     { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 },
1717     { 32, 32, 0xf0000000 }, 0xe0000000,
1718     & fmt_37_ld24_ops[0],
1719     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1720   },
1721 /* ldi $dr,$simm8 */
1722   {
1723     { 1, 1, 1, 1 },
1724     "ldi8", "ldi",
1725     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1726     { 16, 16, 0xf000 }, 0x6000,
1727     & fmt_38_ldi8_ops[0],
1728     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1729   },
1730 /* ldi8 $dr,$simm8 */
1731   {
1732     { 1, 1, 1, 1 },
1733     "ldi8a", "ldi8",
1734     { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 },
1735     { 16, 16, 0xf000 }, 0x6000,
1736     & fmt_38_ldi8_ops[0],
1737     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_OS } }
1738   },
1739 /* ldi $dr,$hash$slo16 */
1740   {
1741     { 1, 1, 1, 1 },
1742     "ldi16", "ldi",
1743     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1744     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1745     & fmt_39_ldi16_ops[0],
1746     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
1747   },
1748 /* ldi16 $dr,$hash$slo16 */
1749   {
1750     { 1, 1, 1, 1 },
1751     "ldi16a", "ldi16",
1752     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 },
1753     { 32, 32, 0xf0ff0000 }, 0x90f00000,
1754     & fmt_39_ldi16_ops[0],
1755     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
1756   },
1757 /* lock $dr,@$sr */
1758   {
1759     { 1, 1, 1, 1 },
1760     "lock", "lock",
1761     { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 },
1762     { 16, 16, 0xf0f0 }, 0x20d0,
1763     & fmt_40_lock_ops[0],
1764     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1765   },
1766 /* machi $src1,$src2 */
1767   {
1768     { 1, 1, 1, 1 },
1769     "machi", "machi",
1770     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1771     { 16, 16, 0xf0f0 }, 0x3040,
1772     & fmt_41_machi_ops[0],
1773     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1774   },
1775 /* start-sanitize-m32rx */
1776 /* machi $src1,$src2,$acc */
1777   {
1778     { 1, 1, 1, 1 },
1779     "machi-a", "machi",
1780     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1781     { 16, 16, 0xf070 }, 0x3040,
1782     & fmt_42_machi_a_ops[0],
1783     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1784   },
1785 /* end-sanitize-m32rx */
1786 /* maclo $src1,$src2 */
1787   {
1788     { 1, 1, 1, 1 },
1789     "maclo", "maclo",
1790     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1791     { 16, 16, 0xf0f0 }, 0x3050,
1792     & fmt_41_machi_ops[0],
1793     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1794   },
1795 /* start-sanitize-m32rx */
1796 /* maclo $src1,$src2,$acc */
1797   {
1798     { 1, 1, 1, 1 },
1799     "maclo-a", "maclo",
1800     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1801     { 16, 16, 0xf070 }, 0x3050,
1802     & fmt_42_machi_a_ops[0],
1803     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1804   },
1805 /* end-sanitize-m32rx */
1806 /* macwhi $src1,$src2 */
1807   {
1808     { 1, 1, 1, 1 },
1809     "macwhi", "macwhi",
1810     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1811     { 16, 16, 0xf0f0 }, 0x3060,
1812     & fmt_41_machi_ops[0],
1813     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1814   },
1815 /* macwlo $src1,$src2 */
1816   {
1817     { 1, 1, 1, 1 },
1818     "macwlo", "macwlo",
1819     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1820     { 16, 16, 0xf0f0 }, 0x3070,
1821     & fmt_41_machi_ops[0],
1822     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1823   },
1824 /* mul $dr,$sr */
1825   {
1826     { 1, 1, 1, 1 },
1827     "mul", "mul",
1828     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1829     { 16, 16, 0xf0f0 }, 0x1060,
1830     & fmt_0_add_ops[0],
1831     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1832   },
1833 /* mulhi $src1,$src2 */
1834   {
1835     { 1, 1, 1, 1 },
1836     "mulhi", "mulhi",
1837     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1838     { 16, 16, 0xf0f0 }, 0x3000,
1839     & fmt_43_mulhi_ops[0],
1840     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1841   },
1842 /* start-sanitize-m32rx */
1843 /* mulhi $src1,$src2,$acc */
1844   {
1845     { 1, 1, 1, 1 },
1846     "mulhi-a", "mulhi",
1847     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1848     { 16, 16, 0xf070 }, 0x3000,
1849     & fmt_44_mulhi_a_ops[0],
1850     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1851   },
1852 /* end-sanitize-m32rx */
1853 /* mullo $src1,$src2 */
1854   {
1855     { 1, 1, 1, 1 },
1856     "mullo", "mullo",
1857     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1858     { 16, 16, 0xf0f0 }, 0x3010,
1859     & fmt_43_mulhi_ops[0],
1860     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1861   },
1862 /* start-sanitize-m32rx */
1863 /* mullo $src1,$src2,$acc */
1864   {
1865     { 1, 1, 1, 1 },
1866     "mullo-a", "mullo",
1867     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 },
1868     { 16, 16, 0xf070 }, 0x3010,
1869     & fmt_44_mulhi_a_ops[0],
1870     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1871   },
1872 /* end-sanitize-m32rx */
1873 /* mulwhi $src1,$src2 */
1874   {
1875     { 1, 1, 1, 1 },
1876     "mulwhi", "mulwhi",
1877     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1878     { 16, 16, 0xf0f0 }, 0x3020,
1879     & fmt_43_mulhi_ops[0],
1880     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1881   },
1882 /* mulwlo $src1,$src2 */
1883   {
1884     { 1, 1, 1, 1 },
1885     "mulwlo", "mulwlo",
1886     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
1887     { 16, 16, 0xf0f0 }, 0x3030,
1888     & fmt_43_mulhi_ops[0],
1889     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1890   },
1891 /* mv $dr,$sr */
1892   {
1893     { 1, 1, 1, 1 },
1894     "mv", "mv",
1895     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
1896     { 16, 16, 0xf0f0 }, 0x1080,
1897     & fmt_45_mv_ops[0],
1898     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
1899   },
1900 /* mvfachi $dr */
1901   {
1902     { 1, 1, 1, 1 },
1903     "mvfachi", "mvfachi",
1904     { MNEM, ' ', OP (DR), 0 },
1905     { 16, 16, 0xf0ff }, 0x50f0,
1906     & fmt_46_mvfachi_ops[0],
1907     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1908   },
1909 /* start-sanitize-m32rx */
1910 /* mvfachi $dr,$accs */
1911   {
1912     { 1, 1, 1, 1 },
1913     "mvfachi-a", "mvfachi",
1914     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1915     { 16, 16, 0xf0f3 }, 0x50f0,
1916     & fmt_47_mvfachi_a_ops[0],
1917     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1918   },
1919 /* end-sanitize-m32rx */
1920 /* mvfaclo $dr */
1921   {
1922     { 1, 1, 1, 1 },
1923     "mvfaclo", "mvfaclo",
1924     { MNEM, ' ', OP (DR), 0 },
1925     { 16, 16, 0xf0ff }, 0x50f1,
1926     & fmt_46_mvfachi_ops[0],
1927     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1928   },
1929 /* start-sanitize-m32rx */
1930 /* mvfaclo $dr,$accs */
1931   {
1932     { 1, 1, 1, 1 },
1933     "mvfaclo-a", "mvfaclo",
1934     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1935     { 16, 16, 0xf0f3 }, 0x50f1,
1936     & fmt_47_mvfachi_a_ops[0],
1937     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1938   },
1939 /* end-sanitize-m32rx */
1940 /* mvfacmi $dr */
1941   {
1942     { 1, 1, 1, 1 },
1943     "mvfacmi", "mvfacmi",
1944     { MNEM, ' ', OP (DR), 0 },
1945     { 16, 16, 0xf0ff }, 0x50f2,
1946     & fmt_46_mvfachi_ops[0],
1947     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1948   },
1949 /* start-sanitize-m32rx */
1950 /* mvfacmi $dr,$accs */
1951   {
1952     { 1, 1, 1, 1 },
1953     "mvfacmi-a", "mvfacmi",
1954     { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 },
1955     { 16, 16, 0xf0f3 }, 0x50f2,
1956     & fmt_47_mvfachi_a_ops[0],
1957     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1958   },
1959 /* end-sanitize-m32rx */
1960 /* mvfc $dr,$scr */
1961   {
1962     { 1, 1, 1, 1 },
1963     "mvfc", "mvfc",
1964     { MNEM, ' ', OP (DR), ',', OP (SCR), 0 },
1965     { 16, 16, 0xf0f0 }, 0x1090,
1966     & fmt_48_mvfc_ops[0],
1967     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
1968   },
1969 /* mvtachi $src1 */
1970   {
1971     { 1, 1, 1, 1 },
1972     "mvtachi", "mvtachi",
1973     { MNEM, ' ', OP (SRC1), 0 },
1974     { 16, 16, 0xf0ff }, 0x5070,
1975     & fmt_49_mvtachi_ops[0],
1976     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1977   },
1978 /* start-sanitize-m32rx */
1979 /* mvtachi $src1,$accs */
1980   {
1981     { 1, 1, 1, 1 },
1982     "mvtachi-a", "mvtachi",
1983     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
1984     { 16, 16, 0xf0f3 }, 0x5070,
1985     & fmt_50_mvtachi_a_ops[0],
1986     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
1987   },
1988 /* end-sanitize-m32rx */
1989 /* mvtaclo $src1 */
1990   {
1991     { 1, 1, 1, 1 },
1992     "mvtaclo", "mvtaclo",
1993     { MNEM, ' ', OP (SRC1), 0 },
1994     { 16, 16, 0xf0ff }, 0x5071,
1995     & fmt_49_mvtachi_ops[0],
1996     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
1997   },
1998 /* start-sanitize-m32rx */
1999 /* mvtaclo $src1,$accs */
2000   {
2001     { 1, 1, 1, 1 },
2002     "mvtaclo-a", "mvtaclo",
2003     { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 },
2004     { 16, 16, 0xf0f3 }, 0x5071,
2005     & fmt_50_mvtachi_a_ops[0],
2006     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2007   },
2008 /* end-sanitize-m32rx */
2009 /* mvtc $sr,$dcr */
2010   {
2011     { 1, 1, 1, 1 },
2012     "mvtc", "mvtc",
2013     { MNEM, ' ', OP (SR), ',', OP (DCR), 0 },
2014     { 16, 16, 0xf0f0 }, 0x10a0,
2015     & fmt_51_mvtc_ops[0],
2016     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2017   },
2018 /* neg $dr,$sr */
2019   {
2020     { 1, 1, 1, 1 },
2021     "neg", "neg",
2022     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2023     { 16, 16, 0xf0f0 }, 0x30,
2024     & fmt_45_mv_ops[0],
2025     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2026   },
2027 /* nop */
2028   {
2029     { 1, 1, 1, 1 },
2030     "nop", "nop",
2031     { MNEM, 0 },
2032     { 16, 16, 0xffff }, 0x7000,
2033     0,
2034     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2035   },
2036 /* not $dr,$sr */
2037   {
2038     { 1, 1, 1, 1 },
2039     "not", "not",
2040     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2041     { 16, 16, 0xf0f0 }, 0xb0,
2042     & fmt_45_mv_ops[0],
2043     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2044   },
2045 /* rac */
2046   {
2047     { 1, 1, 1, 1 },
2048     "rac", "rac",
2049     { MNEM, 0 },
2050     { 16, 16, 0xffff }, 0x5090,
2051     & fmt_53_rac_ops[0],
2052     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2053   },
2054 /* start-sanitize-m32rx */
2055 /* rac $accd */
2056   {
2057     { 1, 1, 1, 1 },
2058     "rac-d", "rac",
2059     { MNEM, ' ', OP (ACCD), 0 },
2060     { 16, 16, 0xf3ff }, 0x5090,
2061     0,
2062     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2063   },
2064 /* end-sanitize-m32rx */
2065 /* start-sanitize-m32rx */
2066 /* rac $accd,$accs */
2067   {
2068     { 1, 1, 1, 1 },
2069     "rac-ds", "rac",
2070     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2071     { 16, 16, 0xf3f3 }, 0x5090,
2072     0,
2073     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2074   },
2075 /* end-sanitize-m32rx */
2076 /* start-sanitize-m32rx */
2077 /* rac $accd,$accs,$imm1 */
2078   {
2079     { 1, 1, 1, 1 },
2080     "rac-dsi", "rac",
2081     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2082     { 16, 16, 0xf3f2 }, 0x5090,
2083     & fmt_56_rac_dsi_ops[0],
2084     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2085   },
2086 /* end-sanitize-m32rx */
2087 /* rach */
2088   {
2089     { 1, 1, 1, 1 },
2090     "rach", "rach",
2091     { MNEM, 0 },
2092     { 16, 16, 0xffff }, 0x5080,
2093     & fmt_53_rac_ops[0],
2094     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_S } }
2095   },
2096 /* start-sanitize-m32rx */
2097 /* rach $accd */
2098   {
2099     { 1, 1, 1, 1 },
2100     "rach-d", "rach",
2101     { MNEM, ' ', OP (ACCD), 0 },
2102     { 16, 16, 0xf3ff }, 0x5080,
2103     0,
2104     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2105   },
2106 /* end-sanitize-m32rx */
2107 /* start-sanitize-m32rx */
2108 /* rach $accd,$accs */
2109   {
2110     { 1, 1, 1, 1 },
2111     "rach-ds", "rach",
2112     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 },
2113     { 16, 16, 0xf3f3 }, 0x5080,
2114     0,
2115     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2116   },
2117 /* end-sanitize-m32rx */
2118 /* start-sanitize-m32rx */
2119 /* rach $accd,$accs,$imm1 */
2120   {
2121     { 1, 1, 1, 1 },
2122     "rach-dsi", "rach",
2123     { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 },
2124     { 16, 16, 0xf3f2 }, 0x5080,
2125     & fmt_56_rac_dsi_ops[0],
2126     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2127   },
2128 /* end-sanitize-m32rx */
2129 /* rte */
2130   {
2131     { 1, 1, 1, 1 },
2132     "rte", "rte",
2133     { MNEM, 0 },
2134     { 16, 16, 0xffff }, 0x10d6,
2135     & fmt_57_rte_ops[0],
2136     { CGEN_INSN_NBOOL_ATTRS, 0|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2137   },
2138 /* seth $dr,$hash$hi16 */
2139   {
2140     { 1, 1, 1, 1 },
2141     "seth", "seth",
2142     { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 },
2143     { 32, 32, 0xf0ff0000 }, 0xd0c00000,
2144     & fmt_58_seth_ops[0],
2145     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2146   },
2147 /* sll $dr,$sr */
2148   {
2149     { 1, 1, 1, 1 },
2150     "sll", "sll",
2151     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2152     { 16, 16, 0xf0f0 }, 0x1040,
2153     & fmt_0_add_ops[0],
2154     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2155   },
2156 /* sll3 $dr,$sr,$simm16 */
2157   {
2158     { 1, 1, 1, 1 },
2159     "sll3", "sll3",
2160     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2161     { 32, 32, 0xf0f00000 }, 0x90c00000,
2162     & fmt_59_sll3_ops[0],
2163     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2164   },
2165 /* slli $dr,$uimm5 */
2166   {
2167     { 1, 1, 1, 1 },
2168     "slli", "slli",
2169     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2170     { 16, 16, 0xf0e0 }, 0x5040,
2171     & fmt_60_slli_ops[0],
2172     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2173   },
2174 /* sra $dr,$sr */
2175   {
2176     { 1, 1, 1, 1 },
2177     "sra", "sra",
2178     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2179     { 16, 16, 0xf0f0 }, 0x1020,
2180     & fmt_0_add_ops[0],
2181     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2182   },
2183 /* sra3 $dr,$sr,$simm16 */
2184   {
2185     { 1, 1, 1, 1 },
2186     "sra3", "sra3",
2187     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2188     { 32, 32, 0xf0f00000 }, 0x90a00000,
2189     & fmt_59_sll3_ops[0],
2190     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2191   },
2192 /* srai $dr,$uimm5 */
2193   {
2194     { 1, 1, 1, 1 },
2195     "srai", "srai",
2196     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2197     { 16, 16, 0xf0e0 }, 0x5020,
2198     & fmt_60_slli_ops[0],
2199     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2200   },
2201 /* srl $dr,$sr */
2202   {
2203     { 1, 1, 1, 1 },
2204     "srl", "srl",
2205     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2206     { 16, 16, 0xf0f0 }, 0x1000,
2207     & fmt_0_add_ops[0],
2208     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2209   },
2210 /* srl3 $dr,$sr,$simm16 */
2211   {
2212     { 1, 1, 1, 1 },
2213     "srl3", "srl3",
2214     { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 },
2215     { 32, 32, 0xf0f00000 }, 0x90800000,
2216     & fmt_59_sll3_ops[0],
2217     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2218   },
2219 /* srli $dr,$uimm5 */
2220   {
2221     { 1, 1, 1, 1 },
2222     "srli", "srli",
2223     { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 },
2224     { 16, 16, 0xf0e0 }, 0x5000,
2225     & fmt_60_slli_ops[0],
2226     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2227   },
2228 /* st $src1,@$src2 */
2229   {
2230     { 1, 1, 1, 1 },
2231     "st", "st",
2232     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2233     { 16, 16, 0xf0f0 }, 0x2040,
2234     & fmt_61_st_ops[0],
2235     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2236   },
2237 /* st $src1,@($src2) */
2238   {
2239     { 1, 1, 1, 1 },
2240     "st-2", "st",
2241     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2242     { 16, 16, 0xf0f0 }, 0x2040,
2243     0,
2244     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2245   },
2246 /* st $src1,@($slo16,$src2) */
2247   {
2248     { 1, 1, 1, 1 },
2249     "st-d", "st",
2250     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2251     { 32, 32, 0xf0f00000 }, 0xa0400000,
2252     & fmt_63_st_d_ops[0],
2253     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2254   },
2255 /* st $src1,@($src2,$slo16) */
2256   {
2257     { 1, 1, 1, 1 },
2258     "st-d2", "st",
2259     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2260     { 32, 32, 0xf0f00000 }, 0xa0400000,
2261     0,
2262     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2263   },
2264 /* stb $src1,@$src2 */
2265   {
2266     { 1, 1, 1, 1 },
2267     "stb", "stb",
2268     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2269     { 16, 16, 0xf0f0 }, 0x2000,
2270     & fmt_65_stb_ops[0],
2271     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2272   },
2273 /* stb $src1,@($src2) */
2274   {
2275     { 1, 1, 1, 1 },
2276     "stb-2", "stb",
2277     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2278     { 16, 16, 0xf0f0 }, 0x2000,
2279     0,
2280     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2281   },
2282 /* stb $src1,@($slo16,$src2) */
2283   {
2284     { 1, 1, 1, 1 },
2285     "stb-d", "stb",
2286     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2287     { 32, 32, 0xf0f00000 }, 0xa0000000,
2288     & fmt_66_stb_d_ops[0],
2289     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2290   },
2291 /* stb $src1,@($src2,$slo16) */
2292   {
2293     { 1, 1, 1, 1 },
2294     "stb-d2", "stb",
2295     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2296     { 32, 32, 0xf0f00000 }, 0xa0000000,
2297     0,
2298     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2299   },
2300 /* sth $src1,@$src2 */
2301   {
2302     { 1, 1, 1, 1 },
2303     "sth", "sth",
2304     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2305     { 16, 16, 0xf0f0 }, 0x2020,
2306     & fmt_67_sth_ops[0],
2307     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2308   },
2309 /* sth $src1,@($src2) */
2310   {
2311     { 1, 1, 1, 1 },
2312     "sth-2", "sth",
2313     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 },
2314     { 16, 16, 0xf0f0 }, 0x2020,
2315     0,
2316     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_O } }
2317   },
2318 /* sth $src1,@($slo16,$src2) */
2319   {
2320     { 1, 1, 1, 1 },
2321     "sth-d", "sth",
2322     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 },
2323     { 32, 32, 0xf0f00000 }, 0xa0200000,
2324     & fmt_68_sth_d_ops[0],
2325     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_NONE } }
2326   },
2327 /* sth $src1,@($src2,$slo16) */
2328   {
2329     { 1, 1, 1, 1 },
2330     "sth-d2", "sth",
2331     { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 },
2332     { 32, 32, 0xf0f00000 }, 0xa0200000,
2333     0,
2334     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2335   },
2336 /* st $src1,@+$src2 */
2337   {
2338     { 1, 1, 1, 1 },
2339     "st-plus", "st",
2340     { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 },
2341     { 16, 16, 0xf0f0 }, 0x2060,
2342     & fmt_69_st_plus_ops[0],
2343     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2344   },
2345 /* st $src1,@-$src2 */
2346   {
2347     { 1, 1, 1, 1 },
2348     "st-minus", "st",
2349     { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 },
2350     { 16, 16, 0xf0f0 }, 0x2070,
2351     & fmt_69_st_plus_ops[0],
2352     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2353   },
2354 /* sub $dr,$sr */
2355   {
2356     { 1, 1, 1, 1 },
2357     "sub", "sub",
2358     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2359     { 16, 16, 0xf0f0 }, 0x20,
2360     & fmt_0_add_ops[0],
2361     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2362   },
2363 /* subv $dr,$sr */
2364   {
2365     { 1, 1, 1, 1 },
2366     "subv", "subv",
2367     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2368     { 16, 16, 0xf0f0 }, 0x0,
2369     & fmt_5_addv_ops[0],
2370     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2371   },
2372 /* subx $dr,$sr */
2373   {
2374     { 1, 1, 1, 1 },
2375     "subx", "subx",
2376     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2377     { 16, 16, 0xf0f0 }, 0x10,
2378     & fmt_7_addx_ops[0],
2379     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_OS } }
2380   },
2381 /* trap $uimm4 */
2382   {
2383     { 1, 1, 1, 1 },
2384     "trap", "trap",
2385     { MNEM, ' ', OP (UIMM4), 0 },
2386     { 16, 16, 0xfff0 }, 0x10f0,
2387     & fmt_70_trap_ops[0],
2388     { CGEN_INSN_NBOOL_ATTRS, 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_M32R), PIPE_O } }
2389   },
2390 /* unlock $src1,@$src2 */
2391   {
2392     { 1, 1, 1, 1 },
2393     "unlock", "unlock",
2394     { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 },
2395     { 16, 16, 0xf0f0 }, 0x2050,
2396     & fmt_71_unlock_ops[0],
2397     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32R), PIPE_O } }
2398   },
2399 /* push $src1 */
2400   {
2401     { 1, 1, 1, 1 },
2402     "push", "push",
2403     { MNEM, ' ', OP (SRC1), 0 },
2404     { 16, 16, 0xf0ff }, 0x207f,
2405     0,
2406     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2407   },
2408 /* pop $dr */
2409   {
2410     { 1, 1, 1, 1 },
2411     "pop", "pop",
2412     { MNEM, ' ', OP (DR), 0 },
2413     { 16, 16, 0xf0ff }, 0x20ef,
2414     0,
2415     { CGEN_INSN_NBOOL_ATTRS, 0|A(ALIAS), { (1<<MACH_M32R), PIPE_NONE } }
2416   },
2417 /* start-sanitize-m32rx */
2418 /* satb $dr,$sr */
2419   {
2420     { 1, 1, 1, 1 },
2421     "satb", "satb",
2422     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2423     { 32, 32, 0xf0f0ffff }, 0x80600100,
2424     & fmt_74_satb_ops[0],
2425     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2426   },
2427 /* end-sanitize-m32rx */
2428 /* start-sanitize-m32rx */
2429 /* sath $dr,$sr */
2430   {
2431     { 1, 1, 1, 1 },
2432     "sath", "sath",
2433     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2434     { 32, 32, 0xf0f0ffff }, 0x80600200,
2435     & fmt_74_satb_ops[0],
2436     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2437   },
2438 /* end-sanitize-m32rx */
2439 /* start-sanitize-m32rx */
2440 /* sat $dr,$sr */
2441   {
2442     { 1, 1, 1, 1 },
2443     "sat", "sat",
2444     { MNEM, ' ', OP (DR), ',', OP (SR), 0 },
2445     { 32, 32, 0xf0f0ffff }, 0x80000000,
2446     & fmt_75_sat_ops[0],
2447     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_NONE } }
2448   },
2449 /* end-sanitize-m32rx */
2450 /* start-sanitize-m32rx */
2451 /* pcmpbz $src2 */
2452   {
2453     { 1, 1, 1, 1 },
2454     "pcmpbz", "pcmpbz",
2455     { MNEM, ' ', OP (SRC2), 0 },
2456     { 16, 16, 0xfff0 }, 0x370,
2457     & fmt_23_cmpz_ops[0],
2458     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_OS } }
2459   },
2460 /* end-sanitize-m32rx */
2461 /* start-sanitize-m32rx */
2462 /* sadd */
2463   {
2464     { 1, 1, 1, 1 },
2465     "sadd", "sadd",
2466     { MNEM, 0 },
2467     { 16, 16, 0xffff }, 0x50e4,
2468     & fmt_76_sadd_ops[0],
2469     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2470   },
2471 /* end-sanitize-m32rx */
2472 /* start-sanitize-m32rx */
2473 /* macwu1 $src1,$src2 */
2474   {
2475     { 1, 1, 1, 1 },
2476     "macwu1", "macwu1",
2477     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2478     { 16, 16, 0xf0f0 }, 0x50b0,
2479     & fmt_77_macwu1_ops[0],
2480     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2481   },
2482 /* end-sanitize-m32rx */
2483 /* start-sanitize-m32rx */
2484 /* msblo $src1,$src2 */
2485   {
2486     { 1, 1, 1, 1 },
2487     "msblo", "msblo",
2488     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2489     { 16, 16, 0xf0f0 }, 0x50d0,
2490     & fmt_41_machi_ops[0],
2491     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2492   },
2493 /* end-sanitize-m32rx */
2494 /* start-sanitize-m32rx */
2495 /* mulwu1 $src1,$src2 */
2496   {
2497     { 1, 1, 1, 1 },
2498     "mulwu1", "mulwu1",
2499     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2500     { 16, 16, 0xf0f0 }, 0x50a0,
2501     & fmt_78_mulwu1_ops[0],
2502     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2503   },
2504 /* end-sanitize-m32rx */
2505 /* start-sanitize-m32rx */
2506 /* maclh1 $src1,$src2 */
2507   {
2508     { 1, 1, 1, 1 },
2509     "maclh1", "maclh1",
2510     { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 },
2511     { 16, 16, 0xf0f0 }, 0x50c0,
2512     & fmt_77_macwu1_ops[0],
2513     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_S } }
2514   },
2515 /* end-sanitize-m32rx */
2516 /* start-sanitize-m32rx */
2517 /* sc */
2518   {
2519     { 1, 1, 1, 1 },
2520     "sc", "sc",
2521     { MNEM, 0 },
2522     { 16, 16, 0xffff }, 0x7401,
2523     & fmt_79_sc_ops[0],
2524     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2525   },
2526 /* end-sanitize-m32rx */
2527 /* start-sanitize-m32rx */
2528 /* snc */
2529   {
2530     { 1, 1, 1, 1 },
2531     "snc", "snc",
2532     { MNEM, 0 },
2533     { 16, 16, 0xffff }, 0x7501,
2534     & fmt_79_sc_ops[0],
2535     { CGEN_INSN_NBOOL_ATTRS, 0, { (1<<MACH_M32RX), PIPE_O } }
2536   },
2537 /* end-sanitize-m32rx */
2538 };
2539
2540 #undef A
2541 #undef MNEM
2542 #undef OP
2543
2544 CGEN_INSN_TABLE m32r_cgen_insn_table =
2545 {
2546   & m32r_cgen_insn_table_entries[0],
2547   sizeof (CGEN_INSN),
2548   MAX_INSNS,
2549   NULL,
2550   m32r_cgen_asm_hash_insn, CGEN_ASM_HASH_SIZE,
2551   m32r_cgen_dis_hash_insn, CGEN_DIS_HASH_SIZE
2552 };
2553
2554 /* The hash functions are recorded here to help keep assembler code out of
2555    the disassembler and vice versa.  */
2556
2557 unsigned int
2558 m32r_cgen_asm_hash_insn (insn)
2559      const char * insn;
2560 {
2561   return CGEN_ASM_HASH (insn);
2562 }
2563
2564 unsigned int
2565 m32r_cgen_dis_hash_insn (buf, value)
2566      const char * buf;
2567      unsigned long value;
2568 {
2569   return CGEN_DIS_HASH (buf, value);
2570 }
2571
2572 CGEN_OPCODE_DATA m32r_cgen_opcode_data =
2573 {
2574   & m32r_cgen_hw_entries[0],
2575   & m32r_cgen_insn_table,
2576 };
2577
2578 void
2579 m32r_cgen_init_tables (mach)
2580     int mach;
2581 {
2582 }
2583
2584 /* Main entry point for stuffing values in cgen_fields.  */
2585
2586 void
2587 m32r_cgen_set_operand (opindex, valuep, fields)
2588      int opindex;
2589      const long * valuep;
2590      CGEN_FIELDS * fields;
2591 {
2592   switch (opindex)
2593     {
2594     case M32R_OPERAND_SR :
2595       fields->f_r2 = * valuep;
2596       break;
2597     case M32R_OPERAND_DR :
2598       fields->f_r1 = * valuep;
2599       break;
2600     case M32R_OPERAND_SRC1 :
2601       fields->f_r1 = * valuep;
2602       break;
2603     case M32R_OPERAND_SRC2 :
2604       fields->f_r2 = * valuep;
2605       break;
2606     case M32R_OPERAND_SCR :
2607       fields->f_r2 = * valuep;
2608       break;
2609     case M32R_OPERAND_DCR :
2610       fields->f_r1 = * valuep;
2611       break;
2612     case M32R_OPERAND_SIMM8 :
2613       fields->f_simm8 = * valuep;
2614       break;
2615     case M32R_OPERAND_SIMM16 :
2616       fields->f_simm16 = * valuep;
2617       break;
2618     case M32R_OPERAND_UIMM4 :
2619       fields->f_uimm4 = * valuep;
2620       break;
2621     case M32R_OPERAND_UIMM5 :
2622       fields->f_uimm5 = * valuep;
2623       break;
2624     case M32R_OPERAND_UIMM16 :
2625       fields->f_uimm16 = * valuep;
2626       break;
2627 /* start-sanitize-m32rx */
2628     case M32R_OPERAND_IMM1 :
2629       fields->f_imm1 = * valuep;
2630       break;
2631 /* end-sanitize-m32rx */
2632 /* start-sanitize-m32rx */
2633     case M32R_OPERAND_ACCD :
2634       fields->f_accd = * valuep;
2635       break;
2636 /* end-sanitize-m32rx */
2637 /* start-sanitize-m32rx */
2638     case M32R_OPERAND_ACCS :
2639       fields->f_accs = * valuep;
2640       break;
2641 /* end-sanitize-m32rx */
2642 /* start-sanitize-m32rx */
2643     case M32R_OPERAND_ACC :
2644       fields->f_acc = * valuep;
2645       break;
2646 /* end-sanitize-m32rx */
2647     case M32R_OPERAND_HASH :
2648       fields->f_nil = * valuep;
2649       break;
2650     case M32R_OPERAND_HI16 :
2651       fields->f_hi16 = * valuep;
2652       break;
2653     case M32R_OPERAND_SLO16 :
2654       fields->f_simm16 = * valuep;
2655       break;
2656     case M32R_OPERAND_ULO16 :
2657       fields->f_uimm16 = * valuep;
2658       break;
2659     case M32R_OPERAND_UIMM24 :
2660       fields->f_uimm24 = * valuep;
2661       break;
2662     case M32R_OPERAND_DISP8 :
2663       fields->f_disp8 = * valuep;
2664       break;
2665     case M32R_OPERAND_DISP16 :
2666       fields->f_disp16 = * valuep;
2667       break;
2668     case M32R_OPERAND_DISP24 :
2669       fields->f_disp24 = * valuep;
2670       break;
2671
2672     default :
2673       fprintf (stderr, "Unrecognized field %d while setting operand.\n",
2674                        opindex);
2675       abort ();
2676   }
2677 }
2678
2679 /* Main entry point for getting values from cgen_fields.  */
2680
2681 long
2682 m32r_cgen_get_operand (opindex, fields)
2683      int opindex;
2684      const CGEN_FIELDS * fields;
2685 {
2686   long value;
2687
2688   switch (opindex)
2689     {
2690     case M32R_OPERAND_SR :
2691       value = fields->f_r2;
2692       break;
2693     case M32R_OPERAND_DR :
2694       value = fields->f_r1;
2695       break;
2696     case M32R_OPERAND_SRC1 :
2697       value = fields->f_r1;
2698       break;
2699     case M32R_OPERAND_SRC2 :
2700       value = fields->f_r2;
2701       break;
2702     case M32R_OPERAND_SCR :
2703       value = fields->f_r2;
2704       break;
2705     case M32R_OPERAND_DCR :
2706       value = fields->f_r1;
2707       break;
2708     case M32R_OPERAND_SIMM8 :
2709       value = fields->f_simm8;
2710       break;
2711     case M32R_OPERAND_SIMM16 :
2712       value = fields->f_simm16;
2713       break;
2714     case M32R_OPERAND_UIMM4 :
2715       value = fields->f_uimm4;
2716       break;
2717     case M32R_OPERAND_UIMM5 :
2718       value = fields->f_uimm5;
2719       break;
2720     case M32R_OPERAND_UIMM16 :
2721       value = fields->f_uimm16;
2722       break;
2723 /* start-sanitize-m32rx */
2724     case M32R_OPERAND_IMM1 :
2725       value = fields->f_imm1;
2726       break;
2727 /* end-sanitize-m32rx */
2728 /* start-sanitize-m32rx */
2729     case M32R_OPERAND_ACCD :
2730       value = fields->f_accd;
2731       break;
2732 /* end-sanitize-m32rx */
2733 /* start-sanitize-m32rx */
2734     case M32R_OPERAND_ACCS :
2735       value = fields->f_accs;
2736       break;
2737 /* end-sanitize-m32rx */
2738 /* start-sanitize-m32rx */
2739     case M32R_OPERAND_ACC :
2740       value = fields->f_acc;
2741       break;
2742 /* end-sanitize-m32rx */
2743     case M32R_OPERAND_HASH :
2744       value = fields->f_nil;
2745       break;
2746     case M32R_OPERAND_HI16 :
2747       value = fields->f_hi16;
2748       break;
2749     case M32R_OPERAND_SLO16 :
2750       value = fields->f_simm16;
2751       break;
2752     case M32R_OPERAND_ULO16 :
2753       value = fields->f_uimm16;
2754       break;
2755     case M32R_OPERAND_UIMM24 :
2756       value = fields->f_uimm24;
2757       break;
2758     case M32R_OPERAND_DISP8 :
2759       value = fields->f_disp8;
2760       break;
2761     case M32R_OPERAND_DISP16 :
2762       value = fields->f_disp16;
2763       break;
2764     case M32R_OPERAND_DISP24 :
2765       value = fields->f_disp24;
2766       break;
2767
2768     default :
2769       fprintf (stderr, "Unrecognized field %d while getting operand.\n",
2770                        opindex);
2771       abort ();
2772   }
2773
2774   return value;
2775 }
2776